747 lines
32 KiB
Verilog
747 lines
32 KiB
Verilog
// mlkem_axi_slave.v — AXI4 (burst) slave wrapper for the ML-KEM core.
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// Makes the ML-KEM accelerator (KeyGen / Encaps / Decaps) CPU-controllable.
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//
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// This slave and mlkem_top run in the same clock domain as the shared
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// FFT/ML-KEM AXI window.
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//
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// Register map (byte offsets from base, e.g. virtual 0xbf400000):
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// 0x000 CTRL W bit0 = start (launches op selected in CONFIG)
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// bit1 = soft_reset (resets ML-KEM core state)
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// 0x004 STATUS R bit0 busy, bit1 done, bit2 preload_busy
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// W1C write bit1=1 to clear the latched done flag
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// 0x008 CONFIG RW [2:0] k (2/3/4), [5:4] op (0=KeyGen 1=Encaps 2=Decaps)
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// 0x010..0x02C D RW KeyGen seed d (8 words; d byte0 in word0[7:0])
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// 0x030..0x04C Z RW implicit-reject seed z (8 words)
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// 0x050..0x06C MSG RW Encaps message m (8 words)
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// 0x070..0x08C SS R shared secret out (8 words)
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// 0x100 PRELOAD_SEL RW 0=ek_in 1=dk_in 2=c_in
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// 0x104 PRELOAD_ADDR RW byte address (auto-increments after each data write)
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// 0x108 PRELOAD_DATA W write low byte -> streams to selected port (wait-stated)
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// 0x10C RDBK_SEL RW 0=ek 1=dk_pke 2=full-dk 3=ciphertext
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// 0x110 RDBK_ADDR RW output byte index
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// 0x114 RDBK_DATA R selected readback-tap byte (low 8 bits)
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// 0x1000..0x1FFF EK W: preload ek_in, R: read generated ek
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// 0x2000..0x2FFF DK W: preload dk_in, R: read generated full dk
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// 0x3000..0x3FFF CT W: preload c_in, R: read generated ciphertext
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module mlkem_axi_slave (
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input clk,
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input resetn, // active low
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// AXI Write Address Channel
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input [4:0] s_axi_awid,
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input [31:0] s_axi_awaddr,
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input [7:0] s_axi_awlen,
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input [2:0] s_axi_awsize,
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input [1:0] s_axi_awburst,
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input s_axi_awlock,
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input [3:0] s_axi_awcache,
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input [2:0] s_axi_awprot,
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input s_axi_awvalid,
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output reg s_axi_awready,
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// AXI Write Data Channel
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input [4:0] s_axi_wid,
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input [31:0] s_axi_wdata,
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input [3:0] s_axi_wstrb,
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input s_axi_wlast,
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input s_axi_wvalid,
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output reg s_axi_wready,
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// AXI Write Response Channel
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output [4:0] s_axi_bid,
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output [1:0] s_axi_bresp,
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output reg s_axi_bvalid,
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input s_axi_bready,
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// AXI Read Address Channel
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input [4:0] s_axi_arid,
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input [31:0] s_axi_araddr,
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input [7:0] s_axi_arlen,
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input [2:0] s_axi_arsize,
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input [1:0] s_axi_arburst,
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input s_axi_arlock,
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input [3:0] s_axi_arcache,
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input [2:0] s_axi_arprot,
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input s_axi_arvalid,
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output reg s_axi_arready,
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// AXI Read Data Channel
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output reg [4:0] s_axi_rid,
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output reg [31:0] s_axi_rdata,
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output [1:0] s_axi_rresp,
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output reg s_axi_rlast,
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output reg s_axi_rvalid,
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input s_axi_rready,
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// Interrupt output (active high level, asserted while done latched)
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output intr
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);
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// ==========================================
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// Address map (byte offsets within the 1 MB slave window)
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// ==========================================
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localparam ADDR_CTRL = 12'h000;
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localparam ADDR_STATUS = 12'h004;
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localparam ADDR_CONFIG = 12'h008;
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localparam ADDR_D = 12'h010; // 0x010..0x02C (8 words)
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localparam ADDR_Z = 12'h030; // 0x030..0x04C
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localparam ADDR_MSG = 12'h050; // 0x050..0x06C
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localparam ADDR_SS = 12'h070; // 0x070..0x08C (read-only)
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localparam ADDR_PRE_SEL = 12'h100;
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localparam ADDR_PRE_ADR = 12'h104;
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localparam ADDR_PRE_DAT = 12'h108;
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localparam ADDR_RDB_SEL = 12'h10C;
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localparam ADDR_RDB_ADR = 12'h110;
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localparam ADDR_RDB_DAT = 12'h114;
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localparam WIN_EK = 4'h1;
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localparam WIN_DK = 4'h2;
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localparam WIN_CT = 4'h3;
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assign s_axi_bresp = 2'b00;
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assign s_axi_rresp = 2'b00;
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function [31:0] apply_wstrb;
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input [31:0] old_value;
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input [31:0] new_value;
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input [3:0] strobe;
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begin
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apply_wstrb = old_value;
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if (strobe[0]) apply_wstrb[7:0] = new_value[7:0];
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if (strobe[1]) apply_wstrb[15:8] = new_value[15:8];
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if (strobe[2]) apply_wstrb[23:16] = new_value[23:16];
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if (strobe[3]) apply_wstrb[31:24] = new_value[31:24];
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end
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endfunction
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function [7:0] select_byte;
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input [31:0] word;
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input [1:0] lane;
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begin
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case (lane)
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2'd0: select_byte = word[7:0];
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2'd1: select_byte = word[15:8];
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2'd2: select_byte = word[23:16];
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default: select_byte = word[31:24];
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endcase
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end
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endfunction
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function [1:0] window_preload_sel;
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input [3:0] window;
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begin
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case (window)
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WIN_DK: window_preload_sel = 2'd1;
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WIN_CT: window_preload_sel = 2'd2;
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default: window_preload_sel = 2'd0;
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endcase
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end
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endfunction
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function [1:0] window_readback_sel;
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input [3:0] window;
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begin
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case (window)
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WIN_DK: window_readback_sel = 2'd2; // full dk
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WIN_CT: window_readback_sel = 2'd3; // ciphertext
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default: window_readback_sel = 2'd0; // ek
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endcase
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end
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endfunction
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// ==========================================
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// AXI/core clock-domain config / data registers.
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// ==========================================
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reg [2:0] cfg_k; // 2/3/4
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reg [1:0] cfg_op; // 0=KeyGen 1=Encaps 2=Decaps
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reg [31:0] d_word [0:7];
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reg [31:0] z_word [0:7];
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reg [31:0] msg_word [0:7];
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wire [255:0] d_bus = {d_word[7], d_word[6], d_word[5], d_word[4],
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d_word[3], d_word[2], d_word[1], d_word[0]};
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wire [255:0] z_bus = {z_word[7], z_word[6], z_word[5], z_word[4],
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z_word[3], z_word[2], z_word[1], z_word[0]};
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wire [255:0] msg_bus = {msg_word[7],msg_word[6],msg_word[5],msg_word[4],
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msg_word[3],msg_word[2],msg_word[1],msg_word[0]};
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// Preload / readback index registers (sys domain).
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reg [1:0] pre_sel; // 0=ek 1=dk 2=c
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reg [11:0] pre_addr; // byte address into the selected port
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reg [1:0] rdb_sel; // 0=ek 1=dk_pke 2=full-dk 3=ciphertext
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reg [11:0] rdb_addr; // output byte index
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// ==========================================
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// Start pulse: CTRL.start flips a toggle, edge-detected into start_i.
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// ==========================================
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reg start_tg; // sys-domain toggle, flips on CTRL.start write
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reg [2:0] start_sync; // mlkem-domain 2FF sync (+1 for edge)
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wire mlkem_start = start_sync[2] ^ start_sync[1]; // 1 clk pulse
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// ==========================================
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// Software reset pulse: CTRL.soft_reset flips a toggle and stretches reset.
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// ==========================================
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reg srst_tg; // flips on CTRL.soft_reset
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reg [2:0] srst_sync; // edge detector shift register
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reg [3:0] srst_cnt; // reset stretcher in clk domain
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wire mlkem_srst_edge = srst_sync[2] ^ srst_sync[1];
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wire mlkem_srst_active = (srst_cnt != 4'd0);
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wire core_resetn = resetn && !mlkem_srst_active;
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// ==========================================
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// Busy / done status.
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// ==========================================
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wire core_busy;
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wire core_done;
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reg done_latch;
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reg [1:0] busy_sync;
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reg [1:0] done_sync;
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// done-clear: STATUS W1C flips a toggle, edge-detected to clear done_latch.
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reg dclr_tg;
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reg [2:0] dclr_sync;
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wire mlkem_dclr = dclr_sync[2] ^ dclr_sync[1];
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// ==========================================
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// Preload byte write handshake.
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// Latch {sel,addr,byte}, flip pre_req_tg, pulse the selected *_in_we for
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// one cycle, then flip pre_ack_tg to release the AXI write beat.
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// ==========================================
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reg pre_req_tg; // a byte is pending
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reg [2:0] pre_req_sync; // edge detector shift register
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wire mlkem_pre_we = pre_req_sync[2] ^ pre_req_sync[1];
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reg pre_ack_tg; // byte consumed
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reg [2:0] pre_ack_sync; // edge detector shift register
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wire pre_ack_edge = pre_ack_sync[2] ^ pre_ack_sync[1];
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reg pre_busy; // a preload handshake is in flight
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// latched byte/port for the in-flight preload, stable while pre_busy
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reg [1:0] pre_sel_l;
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reg [11:0] pre_addr_l;
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reg [7:0] pre_byte_l;
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reg pre_auto_inc_l;
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// ==========================================
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// Bulk readback byte handshake.
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// Hold {sel,addr}, flip rdb_req_tg, let the BRAM read settle, latch one
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// byte, then flip rdb_ack_tg.
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// ==========================================
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reg rdb_req_tg; // one readback byte request
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reg [2:0] rdb_req_sync; // edge detector shift register
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wire mlkem_rdb_req = rdb_req_sync[2] ^ rdb_req_sync[1];
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reg rdb_ack_tg; // readback byte ready
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reg [2:0] rdb_ack_sync; // edge detector shift register
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wire rdb_ack_edge = rdb_ack_sync[2] ^ rdb_ack_sync[1];
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reg [1:0] rdb_req_sel_l; // stable while request in flight
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reg [11:0] rdb_req_addr_l; // stable while request in flight
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reg [1:0] rdb_sel_m; // captured request
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reg [11:0] rdb_addr_m; // captured request
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reg [1:0] rdb_wait_m; // waits for BRAM registered read
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reg rdb_busy_m;
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reg [7:0] rdb_data_m; // held stable until next ack
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// ==========================================
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// mlkem_top instance
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// ==========================================
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wire [7:0] dbg_byte_o, dbg_dk_o, dbg_ct_o;
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wire [255:0] ss_o;
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wire [1:0] eff_rdb_sel = rdb_busy_m ? rdb_sel_m : rdb_sel;
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wire [11:0] eff_rdb_addr = rdb_busy_m ? rdb_addr_m : rdb_addr;
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wire dbg_byte_sel = (eff_rdb_sel == 2'd1); // 0=ek, 1=dk_pke
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// The core's ek/dkp read-address muxes give dbg_dk_idx_i priority over
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// dbg_byte_idx_i whenever it lands in the ek (768..1567) or dk_pke (<768)
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// region (mlkem_top: ek_rd_addr / dkp_rd_addr). So only drive dbg_dk_idx_i
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// with the real index during a full-dk readback (rdb_sel==2); otherwise hold
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// it out of range (0xFFF) so an ek/dk_pke readback isn't corrupted.
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wire [11:0] dbg_dk_idx = (eff_rdb_sel == 2'd2) ? eff_rdb_addr : 12'hFFF;
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// one-cycle write-enable pulses into the core.
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wire ek_in_we = core_resetn && mlkem_pre_we && (pre_sel_l == 2'd0);
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wire dk_in_we = core_resetn && mlkem_pre_we && (pre_sel_l == 2'd1);
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wire c_in_we = core_resetn && mlkem_pre_we && (pre_sel_l == 2'd2);
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mlkem_top #(.KMAX(4)) u_mlkem (
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.clk (clk),
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.rst_n (core_resetn),
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.k_i (cfg_k),
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.op_i (cfg_op),
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.d_i (d_bus),
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.z_i (z_bus),
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.msg_i (msg_bus),
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.start_i (core_resetn ? mlkem_start : 1'b0),
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.busy_o (core_busy),
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.done_o (core_done),
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// ek preload
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.ek_in_we (ek_in_we),
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.ek_in_addr (pre_addr_l[10:0]),
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.ek_in_byte (pre_byte_l),
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// dk preload
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.dk_in_we (dk_in_we),
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.dk_in_addr (pre_addr_l),
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.dk_in_byte (pre_byte_l),
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// ciphertext preload
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.c_in_we (c_in_we),
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.c_in_addr (pre_addr_l[10:0]),
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.c_in_byte (pre_byte_l),
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// shared secret out
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.ss_o (ss_o),
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// ciphertext readback tap
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.dbg_ct_idx_i (eff_rdb_addr[10:0]),
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.dbg_ct_o (dbg_ct_o),
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// coefficient debug tap (unused by CPU path; tie inputs off)
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.dbg_slot_i (6'd0),
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.dbg_idx_i (8'd0),
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.dbg_coeff_o (/* unused */),
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// ek / dk_pke byte readback
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.dbg_byte_sel_i (dbg_byte_sel),
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.dbg_byte_idx_i (eff_rdb_addr[10:0]),
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.dbg_byte_o (dbg_byte_o),
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// full-dk byte readback
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.dbg_dk_idx_i (dbg_dk_idx),
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.dbg_dk_o (dbg_dk_o),
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// remaining debug taps unused
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.dbg_rho_o (/* unused */),
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.dbg_sigma_o (/* unused */),
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.dbg_r_o (/* unused */),
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.dbg_hek_o (/* unused */),
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.dbg_mprime_o (/* unused */),
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.dbg_kbar_o (/* unused */),
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.dbg_decz_o (/* unused */),
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.dbg_dech_o (/* unused */)
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);
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// ==========================================
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// Core/AXI clock domain: edge detectors, done latch, preload/readback acks.
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// ==========================================
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always @(posedge clk or negedge resetn) begin
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if (!resetn) begin
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start_sync <= 3'd0;
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srst_sync <= 3'd0;
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srst_cnt <= 4'd0;
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dclr_sync <= 3'd0;
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pre_req_sync <= 3'd0;
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pre_ack_tg <= 1'b0;
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rdb_req_sync <= 3'd0;
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rdb_ack_tg <= 1'b0;
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rdb_sel_m <= 2'd0;
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rdb_addr_m <= 12'd0;
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rdb_wait_m <= 2'd0;
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rdb_busy_m <= 1'b0;
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rdb_data_m <= 8'd0;
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done_latch <= 1'b0;
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end else begin
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// Edge-detect request toggles.
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start_sync <= {start_sync[1:0], start_tg};
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srst_sync <= {srst_sync[1:0], srst_tg};
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dclr_sync <= {dclr_sync[1:0], dclr_tg};
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pre_req_sync <= {pre_req_sync[1:0], pre_req_tg};
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rdb_req_sync <= {rdb_req_sync[1:0], rdb_req_tg};
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if (mlkem_srst_edge)
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srst_cnt <= 4'd8;
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else if (srst_cnt != 4'd0)
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srst_cnt <= srst_cnt - 4'd1;
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// acknowledge a consumed preload byte (write-enable pulsed this cycle)
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if (core_resetn && mlkem_pre_we) pre_ack_tg <= ~pre_ack_tg;
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if (!core_resetn) begin
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rdb_wait_m <= 2'd0;
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rdb_busy_m <= 1'b0;
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end else if (mlkem_rdb_req) begin
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rdb_sel_m <= rdb_req_sel_l;
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rdb_addr_m <= rdb_req_addr_l;
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rdb_wait_m <= 2'd2;
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rdb_busy_m <= 1'b1;
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end else if (rdb_wait_m != 2'd0) begin
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if (rdb_wait_m == 2'd1) begin
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rdb_data_m <= rdb_byte;
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rdb_ack_tg <= ~rdb_ack_tg;
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rdb_wait_m <= 2'd0;
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rdb_busy_m <= 1'b0;
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end else begin
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rdb_wait_m <= rdb_wait_m - 2'd1;
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end
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end
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// sticky done: set on the core's done_o pulse, cleared by synced W1C.
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// (mlkem_start also clears it so a new run starts with done low.)
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if (mlkem_srst_active) done_latch <= 1'b0;
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else if (core_done) done_latch <= 1'b1;
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else if (mlkem_dclr) done_latch <= 1'b0;
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else if (mlkem_start) done_latch <= 1'b0;
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end
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end
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// ==========================================
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// AXI clock domain: register status and acknowledge toggles.
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// ==========================================
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always @(posedge clk or negedge resetn) begin
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if (!resetn) begin
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busy_sync <= 2'd0;
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done_sync <= 2'd0;
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pre_ack_sync <= 3'd0;
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rdb_ack_sync <= 3'd0;
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end else begin
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busy_sync <= {busy_sync[0], core_busy | mlkem_srst_active};
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done_sync <= {done_sync[0], done_latch};
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pre_ack_sync <= {pre_ack_sync[1:0], pre_ack_tg};
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rdb_ack_sync <= {rdb_ack_sync[1:0], rdb_ack_tg};
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end
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end
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wire status_busy = busy_sync[1];
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wire status_done = done_sync[1];
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assign intr = status_done;
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// ==========================================
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// AXI Write channel (INCR burst). Preload-data beats are wait-stated until
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// the cross-domain byte handshake completes (W_PRELOAD).
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// ==========================================
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localparam W_IDLE = 3'd0;
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localparam W_DATA = 3'd1;
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localparam W_PRELOAD = 3'd2;
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localparam W_STREAM = 3'd3;
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localparam W_RESP = 3'd4;
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reg [2:0] w_state;
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reg [31:0] w_addr;
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reg [4:0] w_id;
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reg [1:0] w_burst;
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reg w_last_l; // saved wlast across a preload wait
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wire [11:0] w_offset = w_addr[11:0];
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wire w_stream_window = (w_addr[15:12] == WIN_EK) ||
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(w_addr[15:12] == WIN_DK) ||
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(w_addr[15:12] == WIN_CT);
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reg [31:0] stream_wdata;
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reg [3:0] stream_wstrb;
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reg [11:0] stream_byte_addr;
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reg [2:0] stream_lane;
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reg [1:0] stream_sel;
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assign s_axi_bid = w_id;
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integer wi;
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always @(posedge clk or negedge resetn) begin
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if (!resetn) begin
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w_state <= W_IDLE;
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s_axi_awready <= 1'b1;
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s_axi_wready <= 1'b0;
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s_axi_bvalid <= 1'b0;
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cfg_k <= 3'd4; // default ML-KEM-1024
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cfg_op <= 2'd0;
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pre_sel <= 2'd0;
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pre_addr <= 12'd0;
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rdb_sel <= 2'd0;
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rdb_addr <= 12'd0;
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start_tg <= 1'b0;
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srst_tg <= 1'b0;
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dclr_tg <= 1'b0;
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pre_req_tg <= 1'b0;
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pre_busy <= 1'b0;
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pre_sel_l <= 2'd0;
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pre_addr_l <= 12'd0;
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pre_byte_l <= 8'd0;
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pre_auto_inc_l <= 1'b0;
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w_last_l <= 1'b0;
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stream_wdata <= 32'd0;
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stream_wstrb <= 4'd0;
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stream_byte_addr <= 12'd0;
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stream_lane <= 3'd0;
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stream_sel <= 2'd0;
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for (wi = 0; wi < 8; wi = wi + 1) begin
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d_word[wi] = 32'd0;
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z_word[wi] = 32'd0;
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msg_word[wi] = 32'd0;
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end
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end else begin
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// clear the preload-busy flag when the mlkem domain acks the byte
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if (pre_ack_edge) begin
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pre_busy <= 1'b0;
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if (pre_auto_inc_l)
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pre_addr <= pre_addr + 12'd1; // legacy PRE_DAT auto-increment
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end
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case (w_state)
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W_IDLE: begin
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s_axi_awready <= 1'b1;
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if (s_axi_awvalid && s_axi_awready) begin
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s_axi_awready <= 1'b0;
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s_axi_wready <= 1'b1;
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w_addr <= s_axi_awaddr;
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w_id <= s_axi_awid;
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w_burst <= s_axi_awburst;
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w_state <= W_DATA;
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end
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end
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W_DATA: begin
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if (s_axi_wvalid && s_axi_wready) begin
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if (w_stream_window) begin
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stream_wdata <= s_axi_wdata;
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stream_wstrb <= s_axi_wstrb;
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stream_byte_addr <= w_offset;
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stream_lane <= 3'd0;
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stream_sel <= window_preload_sel(w_addr[15:12]);
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w_last_l <= s_axi_wlast;
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s_axi_wready <= 1'b0;
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w_state <= W_STREAM;
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end else if (w_offset == ADDR_PRE_DAT) begin
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// launch cross-domain byte write; stall the beat.
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pre_sel_l <= pre_sel;
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pre_addr_l <= pre_addr;
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pre_byte_l <= s_axi_wdata[7:0];
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pre_auto_inc_l <= 1'b1;
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pre_req_tg <= ~pre_req_tg;
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pre_busy <= 1'b1;
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w_last_l <= s_axi_wlast;
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s_axi_wready <= 1'b0;
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w_state <= W_PRELOAD;
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end else begin
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// normal single-cycle register write
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case (1'b1)
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(w_offset == ADDR_CTRL): begin
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if (s_axi_wdata[0]) start_tg <= ~start_tg;
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if (s_axi_wdata[1]) srst_tg <= ~srst_tg;
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end
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(w_offset == ADDR_STATUS):
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if (s_axi_wdata[1]) dclr_tg <= ~dclr_tg; // clear done
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(w_offset == ADDR_CONFIG): begin
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cfg_k <= s_axi_wdata[2:0];
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cfg_op <= s_axi_wdata[5:4];
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end
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(w_offset == ADDR_PRE_SEL): pre_sel <= s_axi_wdata[1:0];
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(w_offset == ADDR_PRE_ADR): pre_addr <= s_axi_wdata[11:0];
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(w_offset == ADDR_RDB_SEL): rdb_sel <= s_axi_wdata[1:0];
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(w_offset == ADDR_RDB_ADR): rdb_addr <= s_axi_wdata[11:0];
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(w_offset >= ADDR_D && w_offset < ADDR_D + 12'h20):
|
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d_word[(w_offset-ADDR_D)>>2] <= apply_wstrb(d_word[(w_offset-ADDR_D)>>2], s_axi_wdata, s_axi_wstrb);
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(w_offset >= ADDR_Z && w_offset < ADDR_Z + 12'h20):
|
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z_word[(w_offset-ADDR_Z)>>2] <= apply_wstrb(z_word[(w_offset-ADDR_Z)>>2], s_axi_wdata, s_axi_wstrb);
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(w_offset >= ADDR_MSG && w_offset < ADDR_MSG + 12'h20):
|
|
msg_word[(w_offset-ADDR_MSG)>>2] <= apply_wstrb(msg_word[(w_offset-ADDR_MSG)>>2], s_axi_wdata, s_axi_wstrb);
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|
default: ; // SS / RDB_DAT / unmapped: ignore
|
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endcase
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|
|
if (w_burst == 2'b01) w_addr <= w_addr + 32'd4;
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|
if (s_axi_wlast) begin
|
|
s_axi_wready <= 1'b0;
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|
s_axi_bvalid <= 1'b1;
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|
w_state <= W_RESP;
|
|
end
|
|
end
|
|
end
|
|
end
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W_PRELOAD: begin
|
|
// wait for the synced ack (pre_ack_edge clears pre_busy above)
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|
if (!pre_busy) begin
|
|
if (w_burst == 2'b01) w_addr <= w_addr + 32'd4;
|
|
if (w_last_l) begin
|
|
s_axi_bvalid <= 1'b1;
|
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w_state <= W_RESP;
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|
end else begin
|
|
s_axi_wready <= 1'b1;
|
|
w_state <= W_DATA;
|
|
end
|
|
end
|
|
end
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|
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W_STREAM: begin
|
|
if (!pre_busy) begin
|
|
if (stream_lane < 3'd4 && !stream_wstrb[stream_lane[1:0]]) begin
|
|
stream_lane <= stream_lane + 3'd1;
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|
end else if (stream_lane < 3'd4) begin
|
|
pre_sel_l <= stream_sel;
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|
pre_addr_l <= stream_byte_addr + {10'd0, stream_lane[1:0]};
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|
pre_byte_l <= select_byte(stream_wdata, stream_lane[1:0]);
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|
pre_auto_inc_l <= 1'b0;
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|
pre_req_tg <= ~pre_req_tg;
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|
pre_busy <= 1'b1;
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stream_lane <= stream_lane + 3'd1;
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end else begin
|
|
if (w_burst == 2'b01) w_addr <= w_addr + 32'd4;
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if (w_last_l) begin
|
|
s_axi_bvalid <= 1'b1;
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w_state <= W_RESP;
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|
end else begin
|
|
s_axi_wready <= 1'b1;
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|
w_state <= W_DATA;
|
|
end
|
|
end
|
|
end
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|
end
|
|
|
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W_RESP: begin
|
|
if (s_axi_bvalid && s_axi_bready) begin
|
|
s_axi_bvalid <= 1'b0;
|
|
s_axi_awready <= 1'b1;
|
|
w_state <= W_IDLE;
|
|
end
|
|
end
|
|
default: w_state <= W_IDLE;
|
|
endcase
|
|
end
|
|
end
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|
|
|
// ==========================================
|
|
// AXI Read channel (INCR burst).
|
|
// ==========================================
|
|
localparam R_IDLE = 3'd0;
|
|
localparam R_DATA = 3'd1;
|
|
localparam R_BULK_WAIT = 3'd2;
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|
|
|
reg [2:0] r_state;
|
|
reg [31:0] r_addr;
|
|
reg [7:0] r_cnt;
|
|
reg [7:0] r_len;
|
|
reg [1:0] r_burst;
|
|
wire [11:0] r_offset = r_addr[11:0];
|
|
wire ar_stream_window = (s_axi_araddr[15:12] == WIN_EK) ||
|
|
(s_axi_araddr[15:12] == WIN_DK) ||
|
|
(s_axi_araddr[15:12] == WIN_CT);
|
|
|
|
reg r_bulk;
|
|
reg [1:0] bulk_sel_r;
|
|
reg [11:0] bulk_addr_r;
|
|
reg [1:0] bulk_lane;
|
|
reg [31:0] bulk_word;
|
|
|
|
always @(posedge clk or negedge resetn) begin
|
|
if (!resetn) begin
|
|
r_state <= R_IDLE;
|
|
s_axi_arready <= 1'b1;
|
|
s_axi_rvalid <= 1'b0;
|
|
s_axi_rlast <= 1'b0;
|
|
s_axi_rid <= 5'd0;
|
|
r_addr <= 32'd0;
|
|
r_cnt <= 8'd0;
|
|
r_len <= 8'd0;
|
|
r_burst <= 2'd0;
|
|
r_bulk <= 1'b0;
|
|
bulk_sel_r <= 2'd0;
|
|
bulk_addr_r <= 12'd0;
|
|
bulk_lane <= 2'd0;
|
|
bulk_word <= 32'd0;
|
|
rdb_req_tg <= 1'b0;
|
|
rdb_req_sel_l <= 2'd0;
|
|
rdb_req_addr_l <= 12'd0;
|
|
end else begin
|
|
case (r_state)
|
|
R_IDLE: begin
|
|
s_axi_arready <= 1'b1;
|
|
if (s_axi_arvalid && s_axi_arready) begin
|
|
s_axi_arready <= 1'b0;
|
|
r_addr <= s_axi_araddr;
|
|
r_len <= s_axi_arlen;
|
|
r_burst <= s_axi_arburst;
|
|
r_cnt <= 8'd0;
|
|
s_axi_rid <= s_axi_arid;
|
|
r_bulk <= ar_stream_window;
|
|
if (ar_stream_window) begin
|
|
bulk_sel_r <= window_readback_sel(s_axi_araddr[15:12]);
|
|
bulk_addr_r <= s_axi_araddr[11:0];
|
|
bulk_lane <= 2'd0;
|
|
bulk_word <= 32'd0;
|
|
rdb_req_sel_l <= window_readback_sel(s_axi_araddr[15:12]);
|
|
rdb_req_addr_l <= s_axi_araddr[11:0];
|
|
rdb_req_tg <= ~rdb_req_tg;
|
|
s_axi_rvalid <= 1'b0;
|
|
s_axi_rlast <= 1'b0;
|
|
r_state <= R_BULK_WAIT;
|
|
end else begin
|
|
s_axi_rvalid <= 1'b1;
|
|
s_axi_rlast <= (s_axi_arlen == 8'd0);
|
|
r_state <= R_DATA;
|
|
end
|
|
end
|
|
end
|
|
R_BULK_WAIT: begin
|
|
if (rdb_ack_edge) begin
|
|
case (bulk_lane)
|
|
2'd0: bulk_word[7:0] <= rdb_data_m;
|
|
2'd1: bulk_word[15:8] <= rdb_data_m;
|
|
2'd2: bulk_word[23:16] <= rdb_data_m;
|
|
default: bulk_word[31:24] <= rdb_data_m;
|
|
endcase
|
|
|
|
if (bulk_lane == 2'd3) begin
|
|
s_axi_rvalid <= 1'b1;
|
|
s_axi_rlast <= (r_cnt == r_len);
|
|
r_state <= R_DATA;
|
|
end else begin
|
|
bulk_lane <= bulk_lane + 2'd1;
|
|
bulk_addr_r <= bulk_addr_r + 12'd1;
|
|
rdb_req_addr_l <= bulk_addr_r + 12'd1;
|
|
rdb_req_tg <= ~rdb_req_tg;
|
|
end
|
|
end
|
|
end
|
|
R_DATA: begin
|
|
if (s_axi_rvalid && s_axi_rready) begin
|
|
if (r_cnt == r_len) begin
|
|
s_axi_rvalid <= 1'b0;
|
|
s_axi_rlast <= 1'b0;
|
|
s_axi_arready <= 1'b1;
|
|
r_bulk <= 1'b0;
|
|
r_state <= R_IDLE;
|
|
end else begin
|
|
r_cnt <= r_cnt + 8'd1;
|
|
if (r_burst == 2'b01) r_addr <= r_addr + 32'd4;
|
|
if (r_bulk) begin
|
|
bulk_addr_r <= (r_burst == 2'b01) ? (r_offset + 12'd4) : r_offset;
|
|
bulk_lane <= 2'd0;
|
|
bulk_word <= 32'd0;
|
|
rdb_req_sel_l <= bulk_sel_r;
|
|
rdb_req_addr_l <= (r_burst == 2'b01) ? (r_offset + 12'd4) : r_offset;
|
|
rdb_req_tg <= ~rdb_req_tg;
|
|
s_axi_rvalid <= 1'b0;
|
|
s_axi_rlast <= 1'b0;
|
|
r_state <= R_BULK_WAIT;
|
|
end else begin
|
|
s_axi_rlast <= (r_cnt + 8'd1 == r_len);
|
|
end
|
|
end
|
|
end
|
|
end
|
|
default: r_state <= R_IDLE;
|
|
endcase
|
|
end
|
|
end
|
|
|
|
// Read-data mux. Use the live address while in R_IDLE accepting AR so the
|
|
// first beat is valid the cycle rvalid asserts (matches matmul style).
|
|
wire [11:0] cur_off = (r_state == R_DATA) ? r_offset : s_axi_araddr[11:0];
|
|
// Selected readback byte (taps are combinational over the core's BRAMs).
|
|
wire [7:0] rdb_byte = (eff_rdb_sel == 2'd3) ? dbg_ct_o :
|
|
(eff_rdb_sel == 2'd2) ? dbg_dk_o : dbg_byte_o;
|
|
|
|
always @(*) begin
|
|
s_axi_rdata = 32'd0;
|
|
if (r_bulk && r_state == R_DATA) begin
|
|
s_axi_rdata = bulk_word;
|
|
end else if (r_state == R_DATA || (r_state == R_IDLE && s_axi_arvalid)) begin
|
|
case (1'b1)
|
|
(cur_off == ADDR_CTRL): s_axi_rdata = 32'd0;
|
|
(cur_off == ADDR_STATUS): s_axi_rdata = {29'd0, pre_busy, status_done, status_busy};
|
|
(cur_off == ADDR_CONFIG): s_axi_rdata = {26'd0, cfg_op, 1'b0, cfg_k};
|
|
(cur_off == ADDR_PRE_SEL): s_axi_rdata = {30'd0, pre_sel};
|
|
(cur_off == ADDR_PRE_ADR): s_axi_rdata = {20'd0, pre_addr};
|
|
(cur_off == ADDR_RDB_SEL): s_axi_rdata = {30'd0, rdb_sel};
|
|
(cur_off == ADDR_RDB_ADR): s_axi_rdata = {20'd0, rdb_addr};
|
|
(cur_off == ADDR_RDB_DAT): s_axi_rdata = {24'd0, rdb_byte};
|
|
(cur_off >= ADDR_D && cur_off < ADDR_D + 12'h20):
|
|
s_axi_rdata = d_word[(cur_off-ADDR_D)>>2];
|
|
(cur_off >= ADDR_Z && cur_off < ADDR_Z + 12'h20):
|
|
s_axi_rdata = z_word[(cur_off-ADDR_Z)>>2];
|
|
(cur_off >= ADDR_MSG && cur_off < ADDR_MSG + 12'h20):
|
|
s_axi_rdata = msg_word[(cur_off-ADDR_MSG)>>2];
|
|
(cur_off >= ADDR_SS && cur_off < ADDR_SS + 12'h20):
|
|
s_axi_rdata = ss_o[((cur_off-ADDR_SS)>>2)*32 +: 32];
|
|
default: s_axi_rdata = 32'd0;
|
|
endcase
|
|
end
|
|
end
|
|
|
|
endmodule
|