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ciciec2026/sdk/software/examples/dma/result.txt
FallenSigh e35fa5884d Use uncached ExtRAM access (0xBC400000) to bypass CPU data cache
The open-la500 core has USE_CACHE enabled. Writes to 0x1c400000
go to the write-back data cache and never reach the SRAM model
before the testbench checks ExtRAM. Use the 0xA0000000 uncached
segment (same pattern as fft_dma/main.c).
2026-06-24 02:04:40 +08:00

76 lines
747 B
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dma_status init = 0
src_array: 1c080d80
dst_array: 1c080c80
phys_src_array: 1c080d80
phys_dst_array: 1c080c80
uncached_src: bc080d80
uncached_dst: bc080c80
polling...
dma passed!
0: 0
1: 1
2: 4
3: 9
4: 16
5: 25
6: 36
7: 49
8: 64
9: 81
10: 100
11: 121
12: 144
13: 169
14: 196
15: 225
16: 256
17: 289
18: 324
19: 361
20: 400
21: 441
22: 484
23: 529
24: 576
25: 625
26: 676
27: 729
28: 784
29: 841
30: 900
31: 961
32: 1024
33: 1089
34: 1156
35: 1225
36: 1296
37: 1369
38: 1444
39: 1521
40: 1600
41: 1681
42: 1764
43: 1849
44: 1936
45: 2025
46: 2116
47: 2209
48: 2304
49: 2401
50: 2500
51: 2601
52: 2704
53: 2809
54: 2916
55: 3025
56: 3136
57: 3249
58: 3364
59: 3481
60: 3600
61: 3721
62: 3844
63: 3969
Success! Array to Array DMA transfer verified.