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FallenSigh db9997b473 Pipelined multiplier: 3-stage LUT-based replaces shift_add, FSM simplified to 2-state

2026-06-25 22:09:20 +08:00

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00-bootstrap-guidelines

Clean production code: -O2, read CRC32 from ExtRAM, remove all debug

2026-06-24 23:42:35 +08:00

06-25-hardware-crc32-engine-in-matmul-ip

Hardware CRC32 engine in matmul IP: 4-byte/cycle combinational, register at 0x010

2026-06-25 20:40:08 +08:00

06-25-pipelined-multiplier-for-matmul-ip

Pipelined multiplier: 3-stage LUT-based replaces shift_add, FSM simplified to 2-state

2026-06-25 22:09:20 +08:00