56 lines
1.6 KiB
Verilog
56 lines
1.6 KiB
Verilog
`timescale 1ns/100ps
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module sram_sp #(
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parameter AW = 16,
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parameter Init_File = "none"
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)
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(
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inout [31:0] ram_data, //BaseRAM数据，低8位与CPLD串口控制器共享
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input [19:0] ram_addr, //BaseRAM地址
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input [ 3:0] ram_be_n, //BaseRAM字节使能，低有效。如果不使用字节使能，请保持为0
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input ram_ce_n, //BaseRAM片选，低有效
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input ram_oe_n, //BaseRAM读使能，低有效
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input ram_we_n //BaseRAM写使能，低有效
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);
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localparam AWT = ((1<<(AW-0))-1);
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reg [31:0] BRAM [AWT:0];
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initial begin
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if(Init_File != "none") begin
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$readmemb(Init_File,BRAM);
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end
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end
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reg [AW-1:0] addr_q1;
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wire [3:0] write_enable;
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assign write_enable[3:0] = (~ram_be_n) & {4{(~ram_ce_n) & (~ram_we_n)}};
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always@(posedge write_enable[0]) begin
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#10;
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if(~ram_be_n[0]) begin
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BRAM[ram_addr][7:0] <= ram_data[7:0];
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if (ram_addr >= 10'd320 && ram_addr < 10'd400)
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$display("SRAM WR addr=%d data=%08x be0=%b", ram_addr, ram_data, ram_be_n[0]);
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end
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always@(posedge write_enable[1]) begin
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#10;
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if(~ram_be_n[1]) BRAM[ram_addr][15:8] <= ram_data[15:8];
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end
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always@(posedge write_enable[2]) begin
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#10;
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if(~ram_be_n[2]) BRAM[ram_addr][23:16] <= ram_data[23:16];
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end
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always@(posedge write_enable[3]) begin
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#10;
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if(~ram_be_n[3]) BRAM[ram_addr][31:24] <= ram_data[31:24];
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end
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wire [31:0] RDATA = BRAM[ram_addr];
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assign ram_data = ((~ram_ce_n) & (~ram_oe_n)) ? RDATA : 32'hzzzzzzzz;
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endmodule
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