FallenSigh
975903000e
Double-buffer poly_mul_sync so the next MAC term's 256-cycle load overlaps the current term's accumulate. Decouple the top-level MAC load index (u_ldj) from the accumulate index (u_j) in the shared ENC_U/ENC_V/DEC_W engine; load reads bank_a/bank_se while accumulate reads bank_t (disjoint ports, no conflict). Accumulate stays strictly serial (psum order-dependent); only the load is hidden. Verified byte-exact vs NIST KAT in ~/Dev/mlkem: Encaps 9/9, Decaps 9/9 (incl. implicit-reject + DECOMP), KeyGen all, hello_world end-to-end. ENC_U 5585->5073, ENC_V 2793->2537 (K=2). Larger relative win at K=4 (K^2 terms). poly_mul contract unchanged (standalone TB 11/11).
208 lines
8.5 KiB
Verilog
208 lines
8.5 KiB
Verilog
// poly_mul_sync.v - Synchronous NTT-domain polynomial multiplier (B2 ping-pong)
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//
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// Computes pointwise (Karatsuba-like base-case) multiplication of two
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// 256-coefficient NTT-domain polynomials.
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//
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// Double-buffered (ping-pong) load so the caller can stream the NEXT operation's
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// 256 A+B pairs into the idle buffer WHILE the current operation's results are
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// still draining out. This hides the 256-cycle load behind the ~256-cycle
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// compute/output of the previous multiply: back-to-back multiplies cost ~256
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// cycles each instead of 512 (load THEN run).
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//
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// Contract (backward compatible with the single-shot testbench):
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// - ready_o is high whenever a buffer is free to accept a load. A fresh op is
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// accepted (load_active started) as soon as the first pair arrives.
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// - Each op streams 256 pairs on coeff_a_in/coeff_b_in (one per accepted cyc).
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// - When a buffer is full it is handed to the compute engine, which issues one
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// base-case every two cycles and emits 256 result coeffs on coeff_out via
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// valid_o/ready_i (c0 then c1 per pair).
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// - A caller that only ever loads-then-drains (never loads during RUN) sees
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// the exact same behaviour as before, just with an extra buffer.
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//
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// Interface (unchanged ports):
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// clk, rst_n - Clock, active-low reset
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// coeff_a_in[11:0]- Polynomial A coefficient (index = pairs accepted this load)
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// coeff_b_in[11:0]- Polynomial B coefficient
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// valid_i - Input valid
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// ready_o - Ready to accept a load pair (a buffer is free)
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// coeff_out[11:0] - Result coefficient output
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// valid_o - Output valid
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// ready_i - Output consumer ready
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module poly_mul_sync (
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input clk, rst_n,
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input [11:0] coeff_a_in,
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input [11:0] coeff_b_in,
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input valid_i,
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output ready_o,
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output [11:0] coeff_out,
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output valid_o,
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input ready_i
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);
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// Two coefficient buffers (ping-pong).
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reg [11:0] mem_A0 [0:255];
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reg [11:0] mem_B0 [0:255];
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reg [11:0] mem_A1 [0:255];
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reg [11:0] mem_B1 [0:255];
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// ---- Load side ----
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reg ld_active; // currently accepting a load into ld_ptr
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reg ld_ptr; // FIFO write buffer (toggles each completed load)
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reg [8:0] load_cnt; // 0..256 pairs written this load
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reg buf_full [0:1]; // buffer holds a complete (unconsumed) operand set
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// ---- Compute side ----
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reg run_active; // compute engine busy on rn_ptr
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reg rn_ptr; // FIFO read buffer (toggles each completed run)
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reg [7:0] issue_cnt; // 0..128 base-cases issued
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reg [7:0] out_cnt; // 0..255 output coeffs consumed
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reg issue_gap; // 2-cycle issue spacing
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reg out_phase; // 0=c0, 1=c1
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reg out_valid_r;
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// Registered basecase inputs/results
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reg [11:0] bc_a0_reg, bc_a1_reg;
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reg [11:0] bc_b0_reg, bc_b1_reg;
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reg [11:0] bc_zeta_reg;
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reg bc_valid_reg;
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reg [11:0] c0_reg, c1_reg;
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// Compute-side memory read (from the buffer being consumed).
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wire [6:0] issue_k = issue_cnt[6:0];
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wire [7:0] addr_even = {issue_k, 1'b0};
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wire [7:0] addr_odd = {issue_k, 1'b1};
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wire [11:0] mem_a0 = rn_ptr ? mem_A1[addr_even] : mem_A0[addr_even];
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wire [11:0] mem_a1 = rn_ptr ? mem_A1[addr_odd] : mem_A0[addr_odd];
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wire [11:0] mem_b0 = rn_ptr ? mem_B1[addr_even] : mem_B0[addr_even];
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wire [11:0] mem_b1 = rn_ptr ? mem_B1[addr_odd] : mem_B0[addr_odd];
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wire [11:0] zeta;
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poly_mul_zeta_rom u_zeta (.addr(issue_k), .zeta(zeta));
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wire [11:0] bc_c0, bc_c1;
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wire bc_vo;
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basecase_mul_pipe u_bc (
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.clk(clk), .rst_n(rst_n),
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.valid_i(bc_valid_reg),
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.a0(bc_a0_reg), .a1(bc_a1_reg),
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.b0(bc_b0_reg), .b1(bc_b1_reg),
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.zeta(bc_zeta_reg),
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.c0(bc_c0), .c1(bc_c1),
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.valid_o(bc_vo)
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);
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// Accept a load pair whenever the FIFO write buffer (ld_ptr) is free. Once a
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// load is in progress it always finishes (ready stays high for its 256).
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assign ready_o = ld_active ? 1'b1 : !buf_full[ld_ptr];
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assign valid_o = out_valid_r;
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assign coeff_out = out_phase ? c1_reg : c0_reg;
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wire ld_fire = valid_i && ready_o;
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integer i;
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always @(posedge clk or negedge rst_n) begin
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if (!rst_n) begin
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ld_active <= 1'b0; ld_ptr <= 1'b0; load_cnt <= 9'd0;
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buf_full[0] <= 1'b0; buf_full[1] <= 1'b0;
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run_active <= 1'b0; rn_ptr <= 1'b0;
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issue_cnt <= 8'd0; out_cnt <= 8'd0; issue_gap <= 1'b0;
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out_phase <= 1'b0; out_valid_r <= 1'b0;
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bc_a0_reg <= 12'd0; bc_a1_reg <= 12'd0;
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bc_b0_reg <= 12'd0; bc_b1_reg <= 12'd0;
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bc_zeta_reg <= 12'd0; bc_valid_reg <= 1'b0;
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c0_reg <= 12'd0; c1_reg <= 12'd0;
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for (i = 0; i < 256; i = i + 1) begin
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mem_A0[i] = 12'd0; mem_B0[i] = 12'd0;
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mem_A1[i] = 12'd0; mem_B1[i] = 12'd0;
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end
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end else begin
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bc_valid_reg <= 1'b0;
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// ================= LOAD SIDE (FIFO write into ld_ptr) =================
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if (!ld_active) begin
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if (ld_fire) begin
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if (!ld_ptr) begin
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mem_A0[0] <= coeff_a_in; mem_B0[0] <= coeff_b_in;
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end else begin
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mem_A1[0] <= coeff_a_in; mem_B1[0] <= coeff_b_in;
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end
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load_cnt <= 9'd1;
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ld_active <= 1'b1;
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end
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end else begin
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if (ld_fire) begin
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if (!ld_ptr) begin
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mem_A0[load_cnt[7:0]] <= coeff_a_in;
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mem_B0[load_cnt[7:0]] <= coeff_b_in;
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end else begin
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mem_A1[load_cnt[7:0]] <= coeff_a_in;
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mem_B1[load_cnt[7:0]] <= coeff_b_in;
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end
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if (load_cnt == 9'd255) begin
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buf_full[ld_ptr] <= 1'b1; // buffer complete
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ld_ptr <= ~ld_ptr; // FIFO advance
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ld_active <= 1'b0;
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load_cnt <= 9'd0;
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end else begin
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load_cnt <= load_cnt + 9'd1;
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end
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end
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end
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// ================= COMPUTE SIDE (FIFO read from rn_ptr) =============
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if (!run_active) begin
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// Start compute on the FIFO head buffer once it is full (and not
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// still mid-load, which cannot happen for rn_ptr==ld_ptr while
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// ld_active, since buf_full is set only at load completion).
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if (buf_full[rn_ptr]) begin
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run_active <= 1'b1;
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issue_cnt <= 8'd0; out_cnt <= 8'd0;
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issue_gap <= 1'b0; out_phase <= 1'b0; out_valid_r <= 1'b0;
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end
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end else begin
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// Issue one base-case every two cycles.
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if (issue_cnt < 8'd128) begin
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if (!issue_gap) begin
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bc_a0_reg <= mem_a0; bc_a1_reg <= mem_a1;
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bc_b0_reg <= mem_b0; bc_b1_reg <= mem_b1;
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bc_zeta_reg <= zeta;
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bc_valid_reg <= 1'b1;
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issue_cnt <= issue_cnt + 8'd1;
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issue_gap <= 1'b1;
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end else begin
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issue_gap <= 1'b0;
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end
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end
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if (out_valid_r && ready_i) begin
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out_cnt <= out_cnt + 8'd1;
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if (out_cnt == 8'd255) begin
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out_valid_r <= 1'b0; out_phase <= 1'b0;
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end else if (!out_phase) begin
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out_phase <= 1'b1;
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end else begin
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out_valid_r <= 1'b0; out_phase <= 1'b0;
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end
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end
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if (bc_vo) begin
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c0_reg <= bc_c0; c1_reg <= bc_c1;
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out_valid_r <= 1'b1; out_phase <= 1'b0;
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end
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// Final output consumed: free this buffer, advance FIFO read ptr.
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if (out_valid_r && ready_i && out_cnt == 8'd255) begin
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buf_full[rn_ptr] <= 1'b0;
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rn_ptr <= ~rn_ptr;
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run_active <= 1'b0;
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issue_cnt <= 8'd0; out_cnt <= 8'd0;
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issue_gap <= 1'b0; out_phase <= 1'b0; out_valid_r <= 1'b0;
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end
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end
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end
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end
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endmodule
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