32215 lines
2.6 MiB
32215 lines
2.6 MiB
Copyright 1986-2019 Xilinx, Inc. All Rights Reserved.
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| Tool Version : Vivado v.2019.2 (lin64) Build 2708876 Wed Nov 6 21:39:14 MST 2019
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| Date : Wed Jul 8 03:34:11 2026
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| Host : fedora running 64-bit unknown
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| Command : report_timing_summary -delay_type min -report_unconstrained -check_timing_verbose -max_paths 50 -file /home/fallensigh/vivado_reports_nodsp/timing_summary_hold_full.rpt
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| Design : soc_top
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| Device : 7a200t-fbg676
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| Speed File : -1 PRODUCTION 1.23 2018-06-13
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------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
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Timing Summary Report
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------------------------------------------------------------------------------------------------
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| Timer Settings
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| --------------
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------------------------------------------------------------------------------------------------
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Enable Multi Corner Analysis : Yes
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Enable Pessimism Removal : Yes
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Pessimism Removal Resolution : Nearest Common Node
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Enable Input Delay Default Clock : No
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Enable Preset / Clear Arcs : No
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Disable Flight Delays : No
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Ignore I/O Paths : No
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Timing Early Launch at Borrowing Latches : No
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Borrow Time for Max Delay Exceptions : Yes
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Merge Timing Exceptions : Yes
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Corner Analyze Analyze
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Name Max Paths Min Paths
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------ --------- ---------
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Slow Yes Yes
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Fast Yes Yes
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check_timing report
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Table of Contents
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-----------------
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1. checking no_clock
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2. checking constant_clock
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3. checking pulse_width_clock
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4. checking unconstrained_internal_endpoints
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5. checking no_input_delay
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6. checking no_output_delay
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7. checking multiple_clock
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8. checking generated_clocks
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9. checking loops
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10. checking partial_input_delay
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11. checking partial_output_delay
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12. checking latch_loops
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1. checking no_clock
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--------------------
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There are 0 register/latch pins with no clock.
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2. checking constant_clock
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--------------------------
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There are 0 register/latch pins with constant_clock.
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3. checking pulse_width_clock
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-----------------------------
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There are 0 register/latch pins which need pulse_width check
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4. checking unconstrained_internal_endpoints
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--------------------------------------------
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There are 0 pins that are not constrained for maximum delay.
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There are 0 pins that are not constrained for maximum delay due to constant clock.
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5. checking no_input_delay
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--------------------------
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There are 38 input ports with no input delay specified. (HIGH)
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UART_RX
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UART_TX
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dip_sw[0]
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dip_sw[10]
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dip_sw[11]
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dip_sw[12]
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dip_sw[13]
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dip_sw[14]
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dip_sw[15]
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dip_sw[16]
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dip_sw[17]
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dip_sw[18]
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dip_sw[19]
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dip_sw[1]
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dip_sw[20]
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dip_sw[21]
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dip_sw[22]
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dip_sw[23]
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dip_sw[24]
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dip_sw[25]
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dip_sw[26]
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dip_sw[27]
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dip_sw[28]
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dip_sw[29]
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dip_sw[2]
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dip_sw[30]
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dip_sw[31]
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dip_sw[3]
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dip_sw[4]
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dip_sw[5]
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dip_sw[6]
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dip_sw[7]
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dip_sw[8]
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dip_sw[9]
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touch_btn[0]
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touch_btn[1]
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touch_btn[2]
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touch_btn[3]
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There are 0 input ports with no input delay but user has a false path constraint.
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6. checking no_output_delay
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---------------------------
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There are 40 ports with no output delay specified. (HIGH)
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UART_RX
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UART_TX
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dpy0[0]
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dpy0[1]
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dpy0[2]
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dpy0[3]
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dpy0[4]
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dpy0[5]
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dpy0[6]
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dpy0[7]
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dpy1[0]
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dpy1[1]
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dpy1[2]
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dpy1[3]
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dpy1[4]
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dpy1[5]
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dpy1[6]
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dpy1[7]
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leds[0]
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leds[10]
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leds[11]
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leds[12]
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leds[13]
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leds[14]
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leds[15]
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leds[1]
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leds[2]
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leds[3]
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leds[4]
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leds[5]
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leds[6]
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leds[7]
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leds[8]
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leds[9]
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video_de
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video_hsync
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video_red[0]
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video_red[1]
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video_red[2]
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video_vsync
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There are 0 ports with no output delay but user has a false path constraint
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There are 0 ports with no output delay but with a timing clock defined on it or propagating through it
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7. checking multiple_clock
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--------------------------
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There are 0 register/latch pins with multiple clocks.
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8. checking generated_clocks
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----------------------------
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There are 0 generated clocks that are not connected to a clock source.
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9. checking loops
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-----------------
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There are 0 combinational loops in the design.
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10. checking partial_input_delay
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--------------------------------
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There are 0 input ports with partial input delay specified.
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11. checking partial_output_delay
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---------------------------------
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There are 0 ports with partial output delay specified.
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12. checking latch_loops
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------------------------
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There are 0 combinational latch loops in the design through latch input
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------------------------------------------------------------------------------------------------
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| Design Timing Summary
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| ---------------------
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------------------------------------------------------------------------------------------------
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WHS(ns) THS(ns) THS Failing Endpoints THS Total Endpoints WPWS(ns) TPWS(ns) TPWS Failing Endpoints TPWS Total Endpoints
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------- ------- --------------------- ------------------- -------- -------- ---------------------- --------------------
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0.032 0.000 0 115177 7.000 0.000 0 42610
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All user specified timing constraints are met.
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------------------------------------------------------------------------------------------------
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| Clock Summary
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| -------------
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------------------------------------------------------------------------------------------------
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Clock Waveform(ns) Period(ns) Frequency(MHz)
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----- ------------ ---------- --------------
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clk {0.000 10.000} 20.000 50.000
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clkfbout_clk_pll {0.000 10.000} 20.000 50.000
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cpu_clk {0.000 15.161} 30.323 32.979
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mlkem_clk_clk_pll {0.000 20.000} 40.000 25.000
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sys_clk {0.000 10.000} 20.000 50.000
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------------------------------------------------------------------------------------------------
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| Intra Clock Table
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| -----------------
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------------------------------------------------------------------------------------------------
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Clock WHS(ns) THS(ns) THS Failing Endpoints THS Total Endpoints WPWS(ns) TPWS(ns) TPWS Failing Endpoints TPWS Total Endpoints
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----- ------- ------- --------------------- ------------------- -------- -------- ---------------------- --------------------
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clk 7.000 0.000 0 1
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clkfbout_clk_pll 17.845 0.000 0 3
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cpu_clk 0.049 0.000 0 17197 13.911 0.000 0 6486
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mlkem_clk_clk_pll 0.058 0.000 0 48474 18.750 0.000 0 26131
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sys_clk 0.079 0.000 0 22818 8.750 0.000 0 9989
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------------------------------------------------------------------------------------------------
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| Inter Clock Table
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| -----------------
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------------------------------------------------------------------------------------------------
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From Clock To Clock WHS(ns) THS(ns) THS Failing Endpoints THS Total Endpoints
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---------- -------- ------- ------- --------------------- -------------------
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sys_clk mlkem_clk_clk_pll 0.054 0.000 0 108
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mlkem_clk_clk_pll sys_clk 0.032 0.000 0 59
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------------------------------------------------------------------------------------------------
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| Other Path Groups Table
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| -----------------------
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------------------------------------------------------------------------------------------------
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Path Group From Clock To Clock WHS(ns) THS(ns) THS Failing Endpoints THS Total Endpoints
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---------- ---------- -------- ------- ------- --------------------- -------------------
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**async_default** cpu_clk cpu_clk 0.651 0.000 0 67
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**async_default** mlkem_clk_clk_pll mlkem_clk_clk_pll 0.613 0.000 0 25694
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**async_default** sys_clk mlkem_clk_clk_pll 2.861 0.000 0 4
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**async_default** mlkem_clk_clk_pll sys_clk 2.991 0.000 0 2
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**async_default** sys_clk sys_clk 0.479 0.000 0 886
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------------------------------------------------------------------------------------------------
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| User Ignored Path Table
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| -----------------------
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------------------------------------------------------------------------------------------------
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Path Group From Clock To Clock
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---------- ---------- --------
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(none) sys_clk cpu_clk
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(none) cpu_clk sys_clk
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------------------------------------------------------------------------------------------------
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| Unconstrained Path Table
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| ------------------------
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------------------------------------------------------------------------------------------------
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Path Group From Clock To Clock
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---------- ---------- --------
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(none) clkfbout_clk_pll
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(none) sys_clk
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(none) sys_clk
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------------------------------------------------------------------------------------------------
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| Timing Details
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| --------------
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------------------------------------------------------------------------------------------------
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---------------------------------------------------------------------------------------------------
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From Clock: clk
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To Clock: clk
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Setup : NA Failing Endpoints, Worst Slack NA , Total Violation NA
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Hold : NA Failing Endpoints, Worst Slack NA , Total Violation NA
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PW : 0 Failing Endpoints, Worst Slack 7.000ns, Total Violation 0.000ns
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---------------------------------------------------------------------------------------------------
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Pulse Width Checks
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--------------------------------------------------------------------------------------
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Clock Name: clk
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Waveform(ns): { 0.000 10.000 }
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Period(ns): 20.000
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Sources: { clk }
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Check Type Corner Lib Pin Reference Pin Required(ns) Actual(ns) Slack(ns) Location Pin
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Min Period n/a PLLE2_ADV/CLKIN1 n/a 1.249 20.000 18.751 PLLE2_ADV_X0Y3 pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1
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Max Period n/a PLLE2_ADV/CLKIN1 n/a 52.633 20.000 32.633 PLLE2_ADV_X0Y3 pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1
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Low Pulse Width Slow PLLE2_ADV/CLKIN1 n/a 3.000 10.000 7.000 PLLE2_ADV_X0Y3 pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1
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Low Pulse Width Fast PLLE2_ADV/CLKIN1 n/a 3.000 10.000 7.000 PLLE2_ADV_X0Y3 pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1
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High Pulse Width Fast PLLE2_ADV/CLKIN1 n/a 3.000 10.000 7.000 PLLE2_ADV_X0Y3 pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1
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High Pulse Width Slow PLLE2_ADV/CLKIN1 n/a 3.000 10.000 7.000 PLLE2_ADV_X0Y3 pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1
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---------------------------------------------------------------------------------------------------
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From Clock: clkfbout_clk_pll
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To Clock: clkfbout_clk_pll
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Setup : NA Failing Endpoints, Worst Slack NA , Total Violation NA
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Hold : NA Failing Endpoints, Worst Slack NA , Total Violation NA
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PW : 0 Failing Endpoints, Worst Slack 17.845ns, Total Violation 0.000ns
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---------------------------------------------------------------------------------------------------
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Pulse Width Checks
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--------------------------------------------------------------------------------------
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Clock Name: clkfbout_clk_pll
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Waveform(ns): { 0.000 10.000 }
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Period(ns): 20.000
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Sources: { pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKFBOUT }
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Check Type Corner Lib Pin Reference Pin Required(ns) Actual(ns) Slack(ns) Location Pin
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Min Period n/a BUFG/I n/a 2.155 20.000 17.845 BUFGCTRL_X0Y19 pll_clk.u_clk_pll/inst/clkf_buf/I
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Min Period n/a PLLE2_ADV/CLKFBOUT n/a 1.249 20.000 18.751 PLLE2_ADV_X0Y3 pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKFBOUT
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Min Period n/a PLLE2_ADV/CLKFBIN n/a 1.249 20.000 18.751 PLLE2_ADV_X0Y3 pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKFBIN
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Max Period n/a PLLE2_ADV/CLKFBIN n/a 52.633 20.000 32.633 PLLE2_ADV_X0Y3 pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKFBIN
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Max Period n/a PLLE2_ADV/CLKFBOUT n/a 160.000 20.000 140.000 PLLE2_ADV_X0Y3 pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKFBOUT
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---------------------------------------------------------------------------------------------------
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From Clock: cpu_clk
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To Clock: cpu_clk
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Setup : NA Failing Endpoints, Worst Slack NA , Total Violation NA
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Hold : 0 Failing Endpoints, Worst Slack 0.049ns, Total Violation 0.000ns
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PW : 0 Failing Endpoints, Worst Slack 13.911ns, Total Violation 0.000ns
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---------------------------------------------------------------------------------------------------
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Min Delay Paths
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--------------------------------------------------------------------------------------
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Slack (MET) : 0.049ns (arrival time - required time)
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Source: u_cpu/u_csr/csr_tlbelo0_reg[14]/C
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(rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns})
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Destination: u_cpu/addr_trans/tlb_entry/tlb_ppn0_reg_r3_0_31_6_11/RAMA/I
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(rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns})
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Path Group: cpu_clk
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Path Type: Hold (Min at Fast Process Corner)
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Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns)
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Data Path Delay: 0.209ns (logic 0.141ns (67.454%) route 0.068ns (32.546%))
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Logic Levels: 0
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Clock Path Skew: 0.013ns (DCD - SCD - CPR)
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Destination Clock Delay (DCD): -0.310ns
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Source Clock Delay (SCD): -0.541ns
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Clock Pessimism Removal (CPR): 0.218ns
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Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
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------------------------------------------------------------------- -------------------
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(clock cpu_clk rise edge) 0.000 0.000 r
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K21 0.000 0.000 r clk (IN)
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net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1
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K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O
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net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll
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PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0)
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-2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0
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net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll
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BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout1_buf/O
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net (fo=6484, routed) 0.722 -0.541 u_cpu/u_csr/cpu_clk
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SLICE_X47Y34 FDRE r u_cpu/u_csr/csr_tlbelo0_reg[14]/C
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------------------------------------------------------------------- -------------------
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SLICE_X47Y34 FDRE (Prop_fdre_C_Q) 0.141 -0.400 r u_cpu/u_csr/csr_tlbelo0_reg[14]/Q
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net (fo=4, routed) 0.068 -0.332 u_cpu/addr_trans/tlb_entry/tlb_ppn0_reg_r3_0_31_6_11/DIA0
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SLICE_X46Y34 RAMD32 r u_cpu/addr_trans/tlb_entry/tlb_ppn0_reg_r3_0_31_6_11/RAMA/I
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------------------------------------------------------------------- -------------------
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(clock cpu_clk rise edge) 0.000 0.000 r
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K21 0.000 0.000 r clk (IN)
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net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1
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K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O
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net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll
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PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0)
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-2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0
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net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll
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BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout1_buf/O
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net (fo=6484, routed) 0.998 -0.310 u_cpu/addr_trans/tlb_entry/tlb_ppn0_reg_r3_0_31_6_11/WCLK
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SLICE_X46Y34 RAMD32 r u_cpu/addr_trans/tlb_entry/tlb_ppn0_reg_r3_0_31_6_11/RAMA/CLK
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clock pessimism -0.218 -0.528
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SLICE_X46Y34 RAMD32 (Hold_ramd32_CLK_I)
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0.147 -0.381 u_cpu/addr_trans/tlb_entry/tlb_ppn0_reg_r3_0_31_6_11/RAMA
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-------------------------------------------------------------------
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required time 0.381
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arrival time -0.332
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-------------------------------------------------------------------
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slack 0.049
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Slack (MET) : 0.052ns (arrival time - required time)
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Source: u_cpu/u_csr/csr_tlbelo0_reg[3]/C
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(rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns})
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Destination: u_cpu/addr_trans/tlb_entry/tlb_plv0_reg_r3_0_31_1_1/SP/I
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(rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns})
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Path Group: cpu_clk
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Path Type: Hold (Min at Fast Process Corner)
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Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns)
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Data Path Delay: 0.209ns (logic 0.141ns (67.433%) route 0.068ns (32.567%))
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Logic Levels: 0
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Clock Path Skew: 0.013ns (DCD - SCD - CPR)
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Destination Clock Delay (DCD): -0.308ns
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Source Clock Delay (SCD): -0.540ns
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Clock Pessimism Removal (CPR): 0.219ns
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Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
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------------------------------------------------------------------- -------------------
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(clock cpu_clk rise edge) 0.000 0.000 r
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K21 0.000 0.000 r clk (IN)
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net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1
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K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O
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net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll
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PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0)
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-2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0
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net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll
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BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout1_buf/O
|
|
net (fo=6484, routed) 0.723 -0.540 u_cpu/u_csr/cpu_clk
|
|
SLICE_X43Y35 FDRE r u_cpu/u_csr/csr_tlbelo0_reg[3]/C
|
|
------------------------------------------------------------------- -------------------
|
|
SLICE_X43Y35 FDRE (Prop_fdre_C_Q) 0.141 -0.399 r u_cpu/u_csr/csr_tlbelo0_reg[3]/Q
|
|
net (fo=7, routed) 0.068 -0.331 u_cpu/addr_trans/tlb_entry/tlb_plv0_reg_r3_0_31_1_1/D
|
|
SLICE_X42Y35 RAMD32 r u_cpu/addr_trans/tlb_entry/tlb_plv0_reg_r3_0_31_1_1/SP/I
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock cpu_clk rise edge) 0.000 0.000 r
|
|
K21 0.000 0.000 r clk (IN)
|
|
net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1
|
|
K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O
|
|
net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll
|
|
PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0)
|
|
-2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0
|
|
net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll
|
|
BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout1_buf/O
|
|
net (fo=6484, routed) 1.000 -0.308 u_cpu/addr_trans/tlb_entry/tlb_plv0_reg_r3_0_31_1_1/WCLK
|
|
SLICE_X42Y35 RAMD32 r u_cpu/addr_trans/tlb_entry/tlb_plv0_reg_r3_0_31_1_1/SP/CLK
|
|
clock pessimism -0.219 -0.527
|
|
SLICE_X42Y35 RAMD32 (Hold_ramd32_CLK_I)
|
|
0.144 -0.383 u_cpu/addr_trans/tlb_entry/tlb_plv0_reg_r3_0_31_1_1/SP
|
|
-------------------------------------------------------------------
|
|
required time 0.383
|
|
arrival time -0.331
|
|
-------------------------------------------------------------------
|
|
slack 0.052
|
|
|
|
Slack (MET) : 0.057ns (arrival time - required time)
|
|
Source: u_cpu/axi_bridge/awaddr_reg[10]/C
|
|
(rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns})
|
|
Destination: u_Axi_CDC/awFifo/ram_reg_0_3_6_11/RAMC/I
|
|
(rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns})
|
|
Path Group: cpu_clk
|
|
Path Type: Hold (Min at Fast Process Corner)
|
|
Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns)
|
|
Data Path Delay: 0.395ns (logic 0.141ns (35.653%) route 0.254ns (64.347%))
|
|
Logic Levels: 0
|
|
Clock Path Skew: 0.194ns (DCD - SCD - CPR)
|
|
Destination Clock Delay (DCD): -0.338ns
|
|
Source Clock Delay (SCD): -0.496ns
|
|
Clock Pessimism Removal (CPR): -0.037ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock cpu_clk rise edge) 0.000 0.000 r
|
|
K21 0.000 0.000 r clk (IN)
|
|
net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1
|
|
K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O
|
|
net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll
|
|
PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0)
|
|
-2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0
|
|
net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll
|
|
BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout1_buf/O
|
|
net (fo=6484, routed) 0.767 -0.496 u_cpu/axi_bridge/cpu_clk
|
|
SLICE_X17Y49 FDRE r u_cpu/axi_bridge/awaddr_reg[10]/C
|
|
------------------------------------------------------------------- -------------------
|
|
SLICE_X17Y49 FDRE (Prop_fdre_C_Q) 0.141 -0.355 r u_cpu/axi_bridge/awaddr_reg[10]/Q
|
|
net (fo=1, routed) 0.254 -0.100 u_Axi_CDC/awFifo/ram_reg_0_3_6_11/DIC0
|
|
SLICE_X16Y57 RAMD32 r u_Axi_CDC/awFifo/ram_reg_0_3_6_11/RAMC/I
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock cpu_clk rise edge) 0.000 0.000 r
|
|
K21 0.000 0.000 r clk (IN)
|
|
net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1
|
|
K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O
|
|
net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll
|
|
PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0)
|
|
-2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0
|
|
net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll
|
|
BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout1_buf/O
|
|
net (fo=6484, routed) 0.970 -0.338 u_Axi_CDC/awFifo/ram_reg_0_3_6_11/WCLK
|
|
SLICE_X16Y57 RAMD32 r u_Axi_CDC/awFifo/ram_reg_0_3_6_11/RAMC/CLK
|
|
clock pessimism 0.037 -0.301
|
|
SLICE_X16Y57 RAMD32 (Hold_ramd32_CLK_I)
|
|
0.144 -0.157 u_Axi_CDC/awFifo/ram_reg_0_3_6_11/RAMC
|
|
-------------------------------------------------------------------
|
|
required time 0.157
|
|
arrival time -0.100
|
|
-------------------------------------------------------------------
|
|
slack 0.057
|
|
|
|
Slack (MET) : 0.058ns (arrival time - required time)
|
|
Source: u_cpu/axi_bridge/awaddr_reg[0]/C
|
|
(rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns})
|
|
Destination: u_Axi_CDC/awFifo/ram_reg_0_3_0_5/RAMA/I
|
|
(rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns})
|
|
Path Group: cpu_clk
|
|
Path Type: Hold (Min at Fast Process Corner)
|
|
Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns)
|
|
Data Path Delay: 0.400ns (logic 0.141ns (35.262%) route 0.259ns (64.738%))
|
|
Logic Levels: 0
|
|
Clock Path Skew: 0.194ns (DCD - SCD - CPR)
|
|
Destination Clock Delay (DCD): -0.339ns
|
|
Source Clock Delay (SCD): -0.497ns
|
|
Clock Pessimism Removal (CPR): -0.037ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock cpu_clk rise edge) 0.000 0.000 r
|
|
K21 0.000 0.000 r clk (IN)
|
|
net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1
|
|
K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O
|
|
net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll
|
|
PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0)
|
|
-2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0
|
|
net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll
|
|
BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout1_buf/O
|
|
net (fo=6484, routed) 0.766 -0.497 u_cpu/axi_bridge/cpu_clk
|
|
SLICE_X23Y49 FDRE r u_cpu/axi_bridge/awaddr_reg[0]/C
|
|
------------------------------------------------------------------- -------------------
|
|
SLICE_X23Y49 FDRE (Prop_fdre_C_Q) 0.141 -0.356 r u_cpu/axi_bridge/awaddr_reg[0]/Q
|
|
net (fo=1, routed) 0.259 -0.097 u_Axi_CDC/awFifo/ram_reg_0_3_0_5/DIA0
|
|
SLICE_X20Y58 RAMD32 r u_Axi_CDC/awFifo/ram_reg_0_3_0_5/RAMA/I
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock cpu_clk rise edge) 0.000 0.000 r
|
|
K21 0.000 0.000 r clk (IN)
|
|
net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1
|
|
K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O
|
|
net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll
|
|
PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0)
|
|
-2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0
|
|
net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll
|
|
BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout1_buf/O
|
|
net (fo=6484, routed) 0.969 -0.339 u_Axi_CDC/awFifo/ram_reg_0_3_0_5/WCLK
|
|
SLICE_X20Y58 RAMD32 r u_Axi_CDC/awFifo/ram_reg_0_3_0_5/RAMA/CLK
|
|
clock pessimism 0.037 -0.302
|
|
SLICE_X20Y58 RAMD32 (Hold_ramd32_CLK_I)
|
|
0.147 -0.155 u_Axi_CDC/awFifo/ram_reg_0_3_0_5/RAMA
|
|
-------------------------------------------------------------------
|
|
required time 0.155
|
|
arrival time -0.097
|
|
-------------------------------------------------------------------
|
|
slack 0.058
|
|
|
|
Slack (MET) : 0.061ns (arrival time - required time)
|
|
Source: u_cpu/u_csr/csr_tlbelo1_reg[20]/C
|
|
(rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns})
|
|
Destination: u_cpu/addr_trans/tlb_entry/tlb_ppn1_reg_r3_0_31_12_17/RAMA/I
|
|
(rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns})
|
|
Path Group: cpu_clk
|
|
Path Type: Hold (Min at Fast Process Corner)
|
|
Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns)
|
|
Data Path Delay: 0.221ns (logic 0.141ns (63.716%) route 0.080ns (36.284%))
|
|
Logic Levels: 0
|
|
Clock Path Skew: 0.013ns (DCD - SCD - CPR)
|
|
Destination Clock Delay (DCD): -0.273ns
|
|
Source Clock Delay (SCD): -0.507ns
|
|
Clock Pessimism Removal (CPR): 0.221ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock cpu_clk rise edge) 0.000 0.000 r
|
|
K21 0.000 0.000 r clk (IN)
|
|
net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1
|
|
K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O
|
|
net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll
|
|
PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0)
|
|
-2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0
|
|
net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll
|
|
BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout1_buf/O
|
|
net (fo=6484, routed) 0.756 -0.507 u_cpu/u_csr/cpu_clk
|
|
SLICE_X37Y38 FDRE r u_cpu/u_csr/csr_tlbelo1_reg[20]/C
|
|
------------------------------------------------------------------- -------------------
|
|
SLICE_X37Y38 FDRE (Prop_fdre_C_Q) 0.141 -0.366 r u_cpu/u_csr/csr_tlbelo1_reg[20]/Q
|
|
net (fo=4, routed) 0.080 -0.285 u_cpu/addr_trans/tlb_entry/tlb_ppn1_reg_r3_0_31_12_17/DIA0
|
|
SLICE_X36Y38 RAMD32 r u_cpu/addr_trans/tlb_entry/tlb_ppn1_reg_r3_0_31_12_17/RAMA/I
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock cpu_clk rise edge) 0.000 0.000 r
|
|
K21 0.000 0.000 r clk (IN)
|
|
net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1
|
|
K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O
|
|
net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll
|
|
PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0)
|
|
-2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0
|
|
net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll
|
|
BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout1_buf/O
|
|
net (fo=6484, routed) 1.035 -0.273 u_cpu/addr_trans/tlb_entry/tlb_ppn1_reg_r3_0_31_12_17/WCLK
|
|
SLICE_X36Y38 RAMD32 r u_cpu/addr_trans/tlb_entry/tlb_ppn1_reg_r3_0_31_12_17/RAMA/CLK
|
|
clock pessimism -0.221 -0.494
|
|
SLICE_X36Y38 RAMD32 (Hold_ramd32_CLK_I)
|
|
0.147 -0.347 u_cpu/addr_trans/tlb_entry/tlb_ppn1_reg_r3_0_31_12_17/RAMA
|
|
-------------------------------------------------------------------
|
|
required time 0.347
|
|
arrival time -0.285
|
|
-------------------------------------------------------------------
|
|
slack 0.061
|
|
|
|
Slack (MET) : 0.079ns (arrival time - required time)
|
|
Source: u_cpu/u_csr/csr_tlbelo0_reg[3]/C
|
|
(rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns})
|
|
Destination: u_cpu/addr_trans/tlb_entry/tlb_plv0_reg_r3_0_31_1_1/DP/I
|
|
(rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns})
|
|
Path Group: cpu_clk
|
|
Path Type: Hold (Min at Fast Process Corner)
|
|
Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns)
|
|
Data Path Delay: 0.209ns (logic 0.141ns (67.433%) route 0.068ns (32.567%))
|
|
Logic Levels: 0
|
|
Clock Path Skew: 0.013ns (DCD - SCD - CPR)
|
|
Destination Clock Delay (DCD): -0.308ns
|
|
Source Clock Delay (SCD): -0.540ns
|
|
Clock Pessimism Removal (CPR): 0.219ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock cpu_clk rise edge) 0.000 0.000 r
|
|
K21 0.000 0.000 r clk (IN)
|
|
net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1
|
|
K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O
|
|
net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll
|
|
PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0)
|
|
-2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0
|
|
net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll
|
|
BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout1_buf/O
|
|
net (fo=6484, routed) 0.723 -0.540 u_cpu/u_csr/cpu_clk
|
|
SLICE_X43Y35 FDRE r u_cpu/u_csr/csr_tlbelo0_reg[3]/C
|
|
------------------------------------------------------------------- -------------------
|
|
SLICE_X43Y35 FDRE (Prop_fdre_C_Q) 0.141 -0.399 r u_cpu/u_csr/csr_tlbelo0_reg[3]/Q
|
|
net (fo=7, routed) 0.068 -0.331 u_cpu/addr_trans/tlb_entry/tlb_plv0_reg_r3_0_31_1_1/D
|
|
SLICE_X42Y35 RAMD32 r u_cpu/addr_trans/tlb_entry/tlb_plv0_reg_r3_0_31_1_1/DP/I
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock cpu_clk rise edge) 0.000 0.000 r
|
|
K21 0.000 0.000 r clk (IN)
|
|
net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1
|
|
K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O
|
|
net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll
|
|
PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0)
|
|
-2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0
|
|
net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll
|
|
BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout1_buf/O
|
|
net (fo=6484, routed) 1.000 -0.308 u_cpu/addr_trans/tlb_entry/tlb_plv0_reg_r3_0_31_1_1/WCLK
|
|
SLICE_X42Y35 RAMD32 r u_cpu/addr_trans/tlb_entry/tlb_plv0_reg_r3_0_31_1_1/DP/CLK
|
|
clock pessimism -0.219 -0.527
|
|
SLICE_X42Y35 RAMD32 (Hold_ramd32_CLK_I)
|
|
0.117 -0.410 u_cpu/addr_trans/tlb_entry/tlb_plv0_reg_r3_0_31_1_1/DP
|
|
-------------------------------------------------------------------
|
|
required time 0.410
|
|
arrival time -0.331
|
|
-------------------------------------------------------------------
|
|
slack 0.079
|
|
|
|
Slack (MET) : 0.085ns (arrival time - required time)
|
|
Source: u_cpu/axi_bridge/awaddr_reg[1]/C
|
|
(rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns})
|
|
Destination: u_Axi_CDC/awFifo/ram_reg_0_3_0_5/RAMA_D1/I
|
|
(rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns})
|
|
Path Group: cpu_clk
|
|
Path Type: Hold (Min at Fast Process Corner)
|
|
Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns)
|
|
Data Path Delay: 0.400ns (logic 0.141ns (35.262%) route 0.259ns (64.738%))
|
|
Logic Levels: 0
|
|
Clock Path Skew: 0.194ns (DCD - SCD - CPR)
|
|
Destination Clock Delay (DCD): -0.339ns
|
|
Source Clock Delay (SCD): -0.497ns
|
|
Clock Pessimism Removal (CPR): -0.037ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock cpu_clk rise edge) 0.000 0.000 r
|
|
K21 0.000 0.000 r clk (IN)
|
|
net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1
|
|
K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O
|
|
net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll
|
|
PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0)
|
|
-2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0
|
|
net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll
|
|
BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout1_buf/O
|
|
net (fo=6484, routed) 0.766 -0.497 u_cpu/axi_bridge/cpu_clk
|
|
SLICE_X23Y49 FDRE r u_cpu/axi_bridge/awaddr_reg[1]/C
|
|
------------------------------------------------------------------- -------------------
|
|
SLICE_X23Y49 FDRE (Prop_fdre_C_Q) 0.141 -0.356 r u_cpu/axi_bridge/awaddr_reg[1]/Q
|
|
net (fo=1, routed) 0.259 -0.097 u_Axi_CDC/awFifo/ram_reg_0_3_0_5/DIA1
|
|
SLICE_X20Y58 RAMD32 r u_Axi_CDC/awFifo/ram_reg_0_3_0_5/RAMA_D1/I
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock cpu_clk rise edge) 0.000 0.000 r
|
|
K21 0.000 0.000 r clk (IN)
|
|
net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1
|
|
K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O
|
|
net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll
|
|
PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0)
|
|
-2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0
|
|
net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll
|
|
BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout1_buf/O
|
|
net (fo=6484, routed) 0.969 -0.339 u_Axi_CDC/awFifo/ram_reg_0_3_0_5/WCLK
|
|
SLICE_X20Y58 RAMD32 r u_Axi_CDC/awFifo/ram_reg_0_3_0_5/RAMA_D1/CLK
|
|
clock pessimism 0.037 -0.302
|
|
SLICE_X20Y58 RAMD32 (Hold_ramd32_CLK_I)
|
|
0.120 -0.182 u_Axi_CDC/awFifo/ram_reg_0_3_0_5/RAMA_D1
|
|
-------------------------------------------------------------------
|
|
required time 0.182
|
|
arrival time -0.097
|
|
-------------------------------------------------------------------
|
|
slack 0.085
|
|
|
|
Slack (MET) : 0.096ns (arrival time - required time)
|
|
Source: u_cpu/axi_bridge/wdata_reg[14]/C
|
|
(rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns})
|
|
Destination: u_Axi_CDC/wFifo/ram_reg_0_7_12_17/RAMB/I
|
|
(rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns})
|
|
Path Group: cpu_clk
|
|
Path Type: Hold (Min at Fast Process Corner)
|
|
Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns)
|
|
Data Path Delay: 0.257ns (logic 0.141ns (54.812%) route 0.116ns (45.188%))
|
|
Logic Levels: 0
|
|
Clock Path Skew: 0.015ns (DCD - SCD - CPR)
|
|
Destination Clock Delay (DCD): -0.232ns
|
|
Source Clock Delay (SCD): -0.467ns
|
|
Clock Pessimism Removal (CPR): 0.220ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock cpu_clk rise edge) 0.000 0.000 r
|
|
K21 0.000 0.000 r clk (IN)
|
|
net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1
|
|
K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O
|
|
net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll
|
|
PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0)
|
|
-2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0
|
|
net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll
|
|
BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout1_buf/O
|
|
net (fo=6484, routed) 0.796 -0.467 u_cpu/axi_bridge/cpu_clk
|
|
SLICE_X7Y48 FDRE r u_cpu/axi_bridge/wdata_reg[14]/C
|
|
------------------------------------------------------------------- -------------------
|
|
SLICE_X7Y48 FDRE (Prop_fdre_C_Q) 0.141 -0.326 r u_cpu/axi_bridge/wdata_reg[14]/Q
|
|
net (fo=1, routed) 0.116 -0.210 u_Axi_CDC/wFifo/ram_reg_0_7_12_17/DIB0
|
|
SLICE_X6Y46 RAMD32 r u_Axi_CDC/wFifo/ram_reg_0_7_12_17/RAMB/I
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock cpu_clk rise edge) 0.000 0.000 r
|
|
K21 0.000 0.000 r clk (IN)
|
|
net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1
|
|
K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O
|
|
net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll
|
|
PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0)
|
|
-2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0
|
|
net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll
|
|
BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout1_buf/O
|
|
net (fo=6484, routed) 1.076 -0.232 u_Axi_CDC/wFifo/ram_reg_0_7_12_17/WCLK
|
|
SLICE_X6Y46 RAMD32 r u_Axi_CDC/wFifo/ram_reg_0_7_12_17/RAMB/CLK
|
|
clock pessimism -0.220 -0.452
|
|
SLICE_X6Y46 RAMD32 (Hold_ramd32_CLK_I)
|
|
0.146 -0.306 u_Axi_CDC/wFifo/ram_reg_0_7_12_17/RAMB
|
|
-------------------------------------------------------------------
|
|
required time 0.306
|
|
arrival time -0.210
|
|
-------------------------------------------------------------------
|
|
slack 0.096
|
|
|
|
Slack (MET) : 0.099ns (arrival time - required time)
|
|
Source: u_cpu/u_csr/csr_tlbelo1_reg[26]/C
|
|
(rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns})
|
|
Destination: u_cpu/addr_trans/tlb_entry/tlb_ppn1_reg_r1_0_31_18_19/RAMA/I
|
|
(rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns})
|
|
Path Group: cpu_clk
|
|
Path Type: Hold (Min at Fast Process Corner)
|
|
Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns)
|
|
Data Path Delay: 0.261ns (logic 0.141ns (54.037%) route 0.120ns (45.963%))
|
|
Logic Levels: 0
|
|
Clock Path Skew: 0.015ns (DCD - SCD - CPR)
|
|
Destination Clock Delay (DCD): -0.309ns
|
|
Source Clock Delay (SCD): -0.541ns
|
|
Clock Pessimism Removal (CPR): 0.217ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock cpu_clk rise edge) 0.000 0.000 r
|
|
K21 0.000 0.000 r clk (IN)
|
|
net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1
|
|
K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O
|
|
net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll
|
|
PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0)
|
|
-2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0
|
|
net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll
|
|
BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout1_buf/O
|
|
net (fo=6484, routed) 0.722 -0.541 u_cpu/u_csr/cpu_clk
|
|
SLICE_X47Y35 FDRE r u_cpu/u_csr/csr_tlbelo1_reg[26]/C
|
|
------------------------------------------------------------------- -------------------
|
|
SLICE_X47Y35 FDRE (Prop_fdre_C_Q) 0.141 -0.400 r u_cpu/u_csr/csr_tlbelo1_reg[26]/Q
|
|
net (fo=4, routed) 0.120 -0.280 u_cpu/addr_trans/tlb_entry/tlb_ppn1_reg_r1_0_31_18_19/DIA0
|
|
SLICE_X46Y36 RAMD32 r u_cpu/addr_trans/tlb_entry/tlb_ppn1_reg_r1_0_31_18_19/RAMA/I
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock cpu_clk rise edge) 0.000 0.000 r
|
|
K21 0.000 0.000 r clk (IN)
|
|
net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1
|
|
K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O
|
|
net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll
|
|
PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0)
|
|
-2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0
|
|
net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll
|
|
BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout1_buf/O
|
|
net (fo=6484, routed) 0.999 -0.309 u_cpu/addr_trans/tlb_entry/tlb_ppn1_reg_r1_0_31_18_19/WCLK
|
|
SLICE_X46Y36 RAMD32 r u_cpu/addr_trans/tlb_entry/tlb_ppn1_reg_r1_0_31_18_19/RAMA/CLK
|
|
clock pessimism -0.217 -0.526
|
|
SLICE_X46Y36 RAMD32 (Hold_ramd32_CLK_I)
|
|
0.147 -0.379 u_cpu/addr_trans/tlb_entry/tlb_ppn1_reg_r1_0_31_18_19/RAMA
|
|
-------------------------------------------------------------------
|
|
required time 0.379
|
|
arrival time -0.280
|
|
-------------------------------------------------------------------
|
|
slack 0.099
|
|
|
|
Slack (MET) : 0.103ns (arrival time - required time)
|
|
Source: u_cpu/axi_bridge/awaddr_reg[3]/C
|
|
(rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns})
|
|
Destination: u_Axi_CDC/awFifo/ram_reg_0_3_0_5/RAMB_D1/I
|
|
(rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns})
|
|
Path Group: cpu_clk
|
|
Path Type: Hold (Min at Fast Process Corner)
|
|
Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns)
|
|
Data Path Delay: 0.422ns (logic 0.141ns (33.450%) route 0.281ns (66.550%))
|
|
Logic Levels: 0
|
|
Clock Path Skew: 0.194ns (DCD - SCD - CPR)
|
|
Destination Clock Delay (DCD): -0.339ns
|
|
Source Clock Delay (SCD): -0.497ns
|
|
Clock Pessimism Removal (CPR): -0.037ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock cpu_clk rise edge) 0.000 0.000 r
|
|
K21 0.000 0.000 r clk (IN)
|
|
net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1
|
|
K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O
|
|
net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll
|
|
PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0)
|
|
-2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0
|
|
net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll
|
|
BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout1_buf/O
|
|
net (fo=6484, routed) 0.766 -0.497 u_cpu/axi_bridge/cpu_clk
|
|
SLICE_X21Y48 FDRE r u_cpu/axi_bridge/awaddr_reg[3]/C
|
|
------------------------------------------------------------------- -------------------
|
|
SLICE_X21Y48 FDRE (Prop_fdre_C_Q) 0.141 -0.356 r u_cpu/axi_bridge/awaddr_reg[3]/Q
|
|
net (fo=1, routed) 0.281 -0.075 u_Axi_CDC/awFifo/ram_reg_0_3_0_5/DIB1
|
|
SLICE_X20Y58 RAMD32 r u_Axi_CDC/awFifo/ram_reg_0_3_0_5/RAMB_D1/I
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock cpu_clk rise edge) 0.000 0.000 r
|
|
K21 0.000 0.000 r clk (IN)
|
|
net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1
|
|
K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O
|
|
net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll
|
|
PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0)
|
|
-2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0
|
|
net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll
|
|
BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout1_buf/O
|
|
net (fo=6484, routed) 0.969 -0.339 u_Axi_CDC/awFifo/ram_reg_0_3_0_5/WCLK
|
|
SLICE_X20Y58 RAMD32 r u_Axi_CDC/awFifo/ram_reg_0_3_0_5/RAMB_D1/CLK
|
|
clock pessimism 0.037 -0.302
|
|
SLICE_X20Y58 RAMD32 (Hold_ramd32_CLK_I)
|
|
0.124 -0.178 u_Axi_CDC/awFifo/ram_reg_0_3_0_5/RAMB_D1
|
|
-------------------------------------------------------------------
|
|
required time 0.178
|
|
arrival time -0.075
|
|
-------------------------------------------------------------------
|
|
slack 0.103
|
|
|
|
Slack (MET) : 0.106ns (arrival time - required time)
|
|
Source: u_cpu/axi_bridge/wdata_reg[1]/C
|
|
(rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns})
|
|
Destination: u_Axi_CDC/wFifo/ram_reg_0_7_0_5/RAMA_D1/I
|
|
(rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns})
|
|
Path Group: cpu_clk
|
|
Path Type: Hold (Min at Fast Process Corner)
|
|
Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns)
|
|
Data Path Delay: 0.242ns (logic 0.141ns (58.263%) route 0.101ns (41.737%))
|
|
Logic Levels: 0
|
|
Clock Path Skew: 0.016ns (DCD - SCD - CPR)
|
|
Destination Clock Delay (DCD): -0.232ns
|
|
Source Clock Delay (SCD): -0.468ns
|
|
Clock Pessimism Removal (CPR): 0.220ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock cpu_clk rise edge) 0.000 0.000 r
|
|
K21 0.000 0.000 r clk (IN)
|
|
net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1
|
|
K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O
|
|
net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll
|
|
PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0)
|
|
-2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0
|
|
net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll
|
|
BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout1_buf/O
|
|
net (fo=6484, routed) 0.795 -0.468 u_cpu/axi_bridge/cpu_clk
|
|
SLICE_X5Y45 FDRE r u_cpu/axi_bridge/wdata_reg[1]/C
|
|
------------------------------------------------------------------- -------------------
|
|
SLICE_X5Y45 FDRE (Prop_fdre_C_Q) 0.141 -0.327 r u_cpu/axi_bridge/wdata_reg[1]/Q
|
|
net (fo=1, routed) 0.101 -0.226 u_Axi_CDC/wFifo/ram_reg_0_7_0_5/DIA1
|
|
SLICE_X6Y45 RAMD32 r u_Axi_CDC/wFifo/ram_reg_0_7_0_5/RAMA_D1/I
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock cpu_clk rise edge) 0.000 0.000 r
|
|
K21 0.000 0.000 r clk (IN)
|
|
net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1
|
|
K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O
|
|
net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll
|
|
PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0)
|
|
-2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0
|
|
net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll
|
|
BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout1_buf/O
|
|
net (fo=6484, routed) 1.076 -0.232 u_Axi_CDC/wFifo/ram_reg_0_7_0_5/WCLK
|
|
SLICE_X6Y45 RAMD32 r u_Axi_CDC/wFifo/ram_reg_0_7_0_5/RAMA_D1/CLK
|
|
clock pessimism -0.220 -0.452
|
|
SLICE_X6Y45 RAMD32 (Hold_ramd32_CLK_I)
|
|
0.120 -0.332 u_Axi_CDC/wFifo/ram_reg_0_7_0_5/RAMA_D1
|
|
-------------------------------------------------------------------
|
|
required time 0.332
|
|
arrival time -0.226
|
|
-------------------------------------------------------------------
|
|
slack 0.106
|
|
|
|
Slack (MET) : 0.118ns (arrival time - required time)
|
|
Source: u_cpu/axi_bridge/wdata_reg[15]/C
|
|
(rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns})
|
|
Destination: u_Axi_CDC/wFifo/ram_reg_0_7_12_17/RAMB_D1/I
|
|
(rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns})
|
|
Path Group: cpu_clk
|
|
Path Type: Hold (Min at Fast Process Corner)
|
|
Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns)
|
|
Data Path Delay: 0.257ns (logic 0.141ns (54.812%) route 0.116ns (45.188%))
|
|
Logic Levels: 0
|
|
Clock Path Skew: 0.015ns (DCD - SCD - CPR)
|
|
Destination Clock Delay (DCD): -0.232ns
|
|
Source Clock Delay (SCD): -0.467ns
|
|
Clock Pessimism Removal (CPR): 0.220ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock cpu_clk rise edge) 0.000 0.000 r
|
|
K21 0.000 0.000 r clk (IN)
|
|
net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1
|
|
K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O
|
|
net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll
|
|
PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0)
|
|
-2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0
|
|
net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll
|
|
BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout1_buf/O
|
|
net (fo=6484, routed) 0.796 -0.467 u_cpu/axi_bridge/cpu_clk
|
|
SLICE_X7Y48 FDRE r u_cpu/axi_bridge/wdata_reg[15]/C
|
|
------------------------------------------------------------------- -------------------
|
|
SLICE_X7Y48 FDRE (Prop_fdre_C_Q) 0.141 -0.326 r u_cpu/axi_bridge/wdata_reg[15]/Q
|
|
net (fo=1, routed) 0.116 -0.210 u_Axi_CDC/wFifo/ram_reg_0_7_12_17/DIB1
|
|
SLICE_X6Y46 RAMD32 r u_Axi_CDC/wFifo/ram_reg_0_7_12_17/RAMB_D1/I
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock cpu_clk rise edge) 0.000 0.000 r
|
|
K21 0.000 0.000 r clk (IN)
|
|
net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1
|
|
K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O
|
|
net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll
|
|
PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0)
|
|
-2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0
|
|
net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll
|
|
BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout1_buf/O
|
|
net (fo=6484, routed) 1.076 -0.232 u_Axi_CDC/wFifo/ram_reg_0_7_12_17/WCLK
|
|
SLICE_X6Y46 RAMD32 r u_Axi_CDC/wFifo/ram_reg_0_7_12_17/RAMB_D1/CLK
|
|
clock pessimism -0.220 -0.452
|
|
SLICE_X6Y46 RAMD32 (Hold_ramd32_CLK_I)
|
|
0.124 -0.328 u_Axi_CDC/wFifo/ram_reg_0_7_12_17/RAMB_D1
|
|
-------------------------------------------------------------------
|
|
required time 0.328
|
|
arrival time -0.210
|
|
-------------------------------------------------------------------
|
|
slack 0.118
|
|
|
|
Slack (MET) : 0.121ns (arrival time - required time)
|
|
Source: u_cpu/u_csr/csr_tlbelo1_reg[3]/C
|
|
(rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns})
|
|
Destination: u_cpu/addr_trans/tlb_entry/tlb_plv1_reg_r3_0_31_1_1/SP/I
|
|
(rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns})
|
|
Path Group: cpu_clk
|
|
Path Type: Hold (Min at Fast Process Corner)
|
|
Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns)
|
|
Data Path Delay: 0.261ns (logic 0.141ns (54.075%) route 0.120ns (45.925%))
|
|
Logic Levels: 0
|
|
Clock Path Skew: 0.016ns (DCD - SCD - CPR)
|
|
Destination Clock Delay (DCD): -0.275ns
|
|
Source Clock Delay (SCD): -0.509ns
|
|
Clock Pessimism Removal (CPR): 0.218ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock cpu_clk rise edge) 0.000 0.000 r
|
|
K21 0.000 0.000 r clk (IN)
|
|
net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1
|
|
K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O
|
|
net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll
|
|
PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0)
|
|
-2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0
|
|
net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll
|
|
BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout1_buf/O
|
|
net (fo=6484, routed) 0.754 -0.509 u_cpu/u_csr/cpu_clk
|
|
SLICE_X39Y39 FDRE r u_cpu/u_csr/csr_tlbelo1_reg[3]/C
|
|
------------------------------------------------------------------- -------------------
|
|
SLICE_X39Y39 FDRE (Prop_fdre_C_Q) 0.141 -0.368 r u_cpu/u_csr/csr_tlbelo1_reg[3]/Q
|
|
net (fo=7, routed) 0.120 -0.248 u_cpu/addr_trans/tlb_entry/tlb_plv1_reg_r3_0_31_1_1/D
|
|
SLICE_X40Y39 RAMD32 r u_cpu/addr_trans/tlb_entry/tlb_plv1_reg_r3_0_31_1_1/SP/I
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock cpu_clk rise edge) 0.000 0.000 r
|
|
K21 0.000 0.000 r clk (IN)
|
|
net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1
|
|
K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O
|
|
net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll
|
|
PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0)
|
|
-2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0
|
|
net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll
|
|
BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout1_buf/O
|
|
net (fo=6484, routed) 1.033 -0.275 u_cpu/addr_trans/tlb_entry/tlb_plv1_reg_r3_0_31_1_1/WCLK
|
|
SLICE_X40Y39 RAMD32 r u_cpu/addr_trans/tlb_entry/tlb_plv1_reg_r3_0_31_1_1/SP/CLK
|
|
clock pessimism -0.218 -0.493
|
|
SLICE_X40Y39 RAMD32 (Hold_ramd32_CLK_I)
|
|
0.124 -0.369 u_cpu/addr_trans/tlb_entry/tlb_plv1_reg_r3_0_31_1_1/SP
|
|
-------------------------------------------------------------------
|
|
required time 0.369
|
|
arrival time -0.248
|
|
-------------------------------------------------------------------
|
|
slack 0.121
|
|
|
|
Slack (MET) : 0.121ns (arrival time - required time)
|
|
Source: u_Axi_CDC/awFifo/popToPushGray_buffercc/buffers_0_reg[2]/C
|
|
(rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns})
|
|
Destination: u_Axi_CDC/awFifo/popToPushGray_buffercc/buffers_1_reg[2]/D
|
|
(rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns})
|
|
Path Group: cpu_clk
|
|
Path Type: Hold (Min at Fast Process Corner)
|
|
Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns)
|
|
Data Path Delay: 0.197ns (logic 0.141ns (71.611%) route 0.056ns (28.389%))
|
|
Logic Levels: 0
|
|
Clock Path Skew: 0.000ns (DCD - SCD - CPR)
|
|
Destination Clock Delay (DCD): -0.347ns
|
|
Source Clock Delay (SCD): -0.575ns
|
|
Clock Pessimism Removal (CPR): 0.228ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock cpu_clk rise edge) 0.000 0.000 r
|
|
K21 0.000 0.000 r clk (IN)
|
|
net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1
|
|
K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O
|
|
net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll
|
|
PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0)
|
|
-2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0
|
|
net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll
|
|
BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout1_buf/O
|
|
net (fo=6484, routed) 0.687 -0.575 u_Axi_CDC/awFifo/popToPushGray_buffercc/cpu_clk
|
|
SLICE_X15Y69 FDCE r u_Axi_CDC/awFifo/popToPushGray_buffercc/buffers_0_reg[2]/C
|
|
------------------------------------------------------------------- -------------------
|
|
SLICE_X15Y69 FDCE (Prop_fdce_C_Q) 0.141 -0.434 r u_Axi_CDC/awFifo/popToPushGray_buffercc/buffers_0_reg[2]/Q
|
|
net (fo=1, routed) 0.056 -0.378 u_Axi_CDC/awFifo/popToPushGray_buffercc/buffers_0[2]
|
|
SLICE_X15Y69 FDCE r u_Axi_CDC/awFifo/popToPushGray_buffercc/buffers_1_reg[2]/D
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock cpu_clk rise edge) 0.000 0.000 r
|
|
K21 0.000 0.000 r clk (IN)
|
|
net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1
|
|
K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O
|
|
net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll
|
|
PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0)
|
|
-2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0
|
|
net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll
|
|
BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout1_buf/O
|
|
net (fo=6484, routed) 0.961 -0.347 u_Axi_CDC/awFifo/popToPushGray_buffercc/cpu_clk
|
|
SLICE_X15Y69 FDCE r u_Axi_CDC/awFifo/popToPushGray_buffercc/buffers_1_reg[2]/C
|
|
clock pessimism -0.228 -0.575
|
|
SLICE_X15Y69 FDCE (Hold_fdce_C_D) 0.076 -0.499 u_Axi_CDC/awFifo/popToPushGray_buffercc/buffers_1_reg[2]
|
|
-------------------------------------------------------------------
|
|
required time 0.499
|
|
arrival time -0.378
|
|
-------------------------------------------------------------------
|
|
slack 0.121
|
|
|
|
Slack (MET) : 0.121ns (arrival time - required time)
|
|
Source: u_Axi_CDC/bFifo/pushToPopGray_buffercc/buffers_0_reg[2]/C
|
|
(rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns})
|
|
Destination: u_Axi_CDC/bFifo/pushToPopGray_buffercc/buffers_1_reg[2]/D
|
|
(rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns})
|
|
Path Group: cpu_clk
|
|
Path Type: Hold (Min at Fast Process Corner)
|
|
Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns)
|
|
Data Path Delay: 0.197ns (logic 0.141ns (71.611%) route 0.056ns (28.389%))
|
|
Logic Levels: 0
|
|
Clock Path Skew: 0.000ns (DCD - SCD - CPR)
|
|
Destination Clock Delay (DCD): -0.338ns
|
|
Source Clock Delay (SCD): -0.568ns
|
|
Clock Pessimism Removal (CPR): 0.230ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock cpu_clk rise edge) 0.000 0.000 r
|
|
K21 0.000 0.000 r clk (IN)
|
|
net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1
|
|
K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O
|
|
net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll
|
|
PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0)
|
|
-2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0
|
|
net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll
|
|
BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout1_buf/O
|
|
net (fo=6484, routed) 0.694 -0.568 u_Axi_CDC/bFifo/pushToPopGray_buffercc/cpu_clk
|
|
SLICE_X19Y59 FDCE r u_Axi_CDC/bFifo/pushToPopGray_buffercc/buffers_0_reg[2]/C
|
|
------------------------------------------------------------------- -------------------
|
|
SLICE_X19Y59 FDCE (Prop_fdce_C_Q) 0.141 -0.427 r u_Axi_CDC/bFifo/pushToPopGray_buffercc/buffers_0_reg[2]/Q
|
|
net (fo=1, routed) 0.056 -0.371 u_Axi_CDC/bFifo/pushToPopGray_buffercc/buffers_0[2]
|
|
SLICE_X19Y59 FDCE r u_Axi_CDC/bFifo/pushToPopGray_buffercc/buffers_1_reg[2]/D
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock cpu_clk rise edge) 0.000 0.000 r
|
|
K21 0.000 0.000 r clk (IN)
|
|
net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1
|
|
K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O
|
|
net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll
|
|
PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0)
|
|
-2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0
|
|
net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll
|
|
BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout1_buf/O
|
|
net (fo=6484, routed) 0.970 -0.338 u_Axi_CDC/bFifo/pushToPopGray_buffercc/cpu_clk
|
|
SLICE_X19Y59 FDCE r u_Axi_CDC/bFifo/pushToPopGray_buffercc/buffers_1_reg[2]/C
|
|
clock pessimism -0.230 -0.568
|
|
SLICE_X19Y59 FDCE (Hold_fdce_C_D) 0.076 -0.492 u_Axi_CDC/bFifo/pushToPopGray_buffercc/buffers_1_reg[2]
|
|
-------------------------------------------------------------------
|
|
required time 0.492
|
|
arrival time -0.371
|
|
-------------------------------------------------------------------
|
|
slack 0.121
|
|
|
|
Slack (MET) : 0.121ns (arrival time - required time)
|
|
Source: u_Axi_CDC/rFifo/pushToPopGray_buffercc/buffers_0_reg[2]/C
|
|
(rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns})
|
|
Destination: u_Axi_CDC/rFifo/pushToPopGray_buffercc/buffers_1_reg[2]/D
|
|
(rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns})
|
|
Path Group: cpu_clk
|
|
Path Type: Hold (Min at Fast Process Corner)
|
|
Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns)
|
|
Data Path Delay: 0.197ns (logic 0.141ns (71.611%) route 0.056ns (28.389%))
|
|
Logic Levels: 0
|
|
Clock Path Skew: 0.000ns (DCD - SCD - CPR)
|
|
Destination Clock Delay (DCD): -0.323ns
|
|
Source Clock Delay (SCD): -0.552ns
|
|
Clock Pessimism Removal (CPR): 0.229ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock cpu_clk rise edge) 0.000 0.000 r
|
|
K21 0.000 0.000 r clk (IN)
|
|
net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1
|
|
K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O
|
|
net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll
|
|
PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0)
|
|
-2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0
|
|
net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll
|
|
BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout1_buf/O
|
|
net (fo=6484, routed) 0.710 -0.552 u_Axi_CDC/rFifo/pushToPopGray_buffercc/cpu_clk
|
|
SLICE_X5Y76 FDCE r u_Axi_CDC/rFifo/pushToPopGray_buffercc/buffers_0_reg[2]/C
|
|
------------------------------------------------------------------- -------------------
|
|
SLICE_X5Y76 FDCE (Prop_fdce_C_Q) 0.141 -0.411 r u_Axi_CDC/rFifo/pushToPopGray_buffercc/buffers_0_reg[2]/Q
|
|
net (fo=1, routed) 0.056 -0.355 u_Axi_CDC/rFifo/pushToPopGray_buffercc/buffers_0[2]
|
|
SLICE_X5Y76 FDCE r u_Axi_CDC/rFifo/pushToPopGray_buffercc/buffers_1_reg[2]/D
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock cpu_clk rise edge) 0.000 0.000 r
|
|
K21 0.000 0.000 r clk (IN)
|
|
net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1
|
|
K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O
|
|
net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll
|
|
PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0)
|
|
-2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0
|
|
net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll
|
|
BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout1_buf/O
|
|
net (fo=6484, routed) 0.985 -0.323 u_Axi_CDC/rFifo/pushToPopGray_buffercc/cpu_clk
|
|
SLICE_X5Y76 FDCE r u_Axi_CDC/rFifo/pushToPopGray_buffercc/buffers_1_reg[2]/C
|
|
clock pessimism -0.229 -0.552
|
|
SLICE_X5Y76 FDCE (Hold_fdce_C_D) 0.076 -0.476 u_Axi_CDC/rFifo/pushToPopGray_buffercc/buffers_1_reg[2]
|
|
-------------------------------------------------------------------
|
|
required time 0.476
|
|
arrival time -0.355
|
|
-------------------------------------------------------------------
|
|
slack 0.121
|
|
|
|
Slack (MET) : 0.121ns (arrival time - required time)
|
|
Source: u_cpu/u_csr/csr_tlbelo0_reg[10]/C
|
|
(rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns})
|
|
Destination: u_cpu/addr_trans/tlb_entry/tlb_ppn0_reg_r3_0_31_0_5/RAMB/I
|
|
(rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns})
|
|
Path Group: cpu_clk
|
|
Path Type: Hold (Min at Fast Process Corner)
|
|
Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns)
|
|
Data Path Delay: 0.281ns (logic 0.141ns (50.124%) route 0.140ns (49.876%))
|
|
Logic Levels: 0
|
|
Clock Path Skew: 0.014ns (DCD - SCD - CPR)
|
|
Destination Clock Delay (DCD): -0.309ns
|
|
Source Clock Delay (SCD): -0.540ns
|
|
Clock Pessimism Removal (CPR): 0.217ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock cpu_clk rise edge) 0.000 0.000 r
|
|
K21 0.000 0.000 r clk (IN)
|
|
net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1
|
|
K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O
|
|
net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll
|
|
PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0)
|
|
-2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0
|
|
net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll
|
|
BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout1_buf/O
|
|
net (fo=6484, routed) 0.723 -0.540 u_cpu/u_csr/cpu_clk
|
|
SLICE_X45Y36 FDRE r u_cpu/u_csr/csr_tlbelo0_reg[10]/C
|
|
------------------------------------------------------------------- -------------------
|
|
SLICE_X45Y36 FDRE (Prop_fdre_C_Q) 0.141 -0.399 r u_cpu/u_csr/csr_tlbelo0_reg[10]/Q
|
|
net (fo=4, routed) 0.140 -0.258 u_cpu/addr_trans/tlb_entry/tlb_ppn0_reg_r3_0_31_0_5/DIB0
|
|
SLICE_X44Y34 RAMD32 r u_cpu/addr_trans/tlb_entry/tlb_ppn0_reg_r3_0_31_0_5/RAMB/I
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock cpu_clk rise edge) 0.000 0.000 r
|
|
K21 0.000 0.000 r clk (IN)
|
|
net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1
|
|
K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O
|
|
net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll
|
|
PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0)
|
|
-2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0
|
|
net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll
|
|
BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout1_buf/O
|
|
net (fo=6484, routed) 0.999 -0.309 u_cpu/addr_trans/tlb_entry/tlb_ppn0_reg_r3_0_31_0_5/WCLK
|
|
SLICE_X44Y34 RAMD32 r u_cpu/addr_trans/tlb_entry/tlb_ppn0_reg_r3_0_31_0_5/RAMB/CLK
|
|
clock pessimism -0.217 -0.526
|
|
SLICE_X44Y34 RAMD32 (Hold_ramd32_CLK_I)
|
|
0.146 -0.380 u_cpu/addr_trans/tlb_entry/tlb_ppn0_reg_r3_0_31_0_5/RAMB
|
|
-------------------------------------------------------------------
|
|
required time 0.380
|
|
arrival time -0.258
|
|
-------------------------------------------------------------------
|
|
slack 0.121
|
|
|
|
Slack (MET) : 0.122ns (arrival time - required time)
|
|
Source: u_Axi_CDC/awFifo/popToPushGray_buffercc/buffers_0_reg[0]/C
|
|
(rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns})
|
|
Destination: u_Axi_CDC/awFifo/popToPushGray_buffercc/buffers_1_reg[0]/D
|
|
(rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns})
|
|
Path Group: cpu_clk
|
|
Path Type: Hold (Min at Fast Process Corner)
|
|
Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns)
|
|
Data Path Delay: 0.197ns (logic 0.141ns (71.611%) route 0.056ns (28.389%))
|
|
Logic Levels: 0
|
|
Clock Path Skew: 0.000ns (DCD - SCD - CPR)
|
|
Destination Clock Delay (DCD): -0.347ns
|
|
Source Clock Delay (SCD): -0.575ns
|
|
Clock Pessimism Removal (CPR): 0.228ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock cpu_clk rise edge) 0.000 0.000 r
|
|
K21 0.000 0.000 r clk (IN)
|
|
net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1
|
|
K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O
|
|
net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll
|
|
PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0)
|
|
-2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0
|
|
net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll
|
|
BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout1_buf/O
|
|
net (fo=6484, routed) 0.687 -0.575 u_Axi_CDC/awFifo/popToPushGray_buffercc/cpu_clk
|
|
SLICE_X15Y69 FDCE r u_Axi_CDC/awFifo/popToPushGray_buffercc/buffers_0_reg[0]/C
|
|
------------------------------------------------------------------- -------------------
|
|
SLICE_X15Y69 FDCE (Prop_fdce_C_Q) 0.141 -0.434 r u_Axi_CDC/awFifo/popToPushGray_buffercc/buffers_0_reg[0]/Q
|
|
net (fo=1, routed) 0.056 -0.378 u_Axi_CDC/awFifo/popToPushGray_buffercc/buffers_0[0]
|
|
SLICE_X15Y69 FDCE r u_Axi_CDC/awFifo/popToPushGray_buffercc/buffers_1_reg[0]/D
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock cpu_clk rise edge) 0.000 0.000 r
|
|
K21 0.000 0.000 r clk (IN)
|
|
net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1
|
|
K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O
|
|
net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll
|
|
PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0)
|
|
-2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0
|
|
net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll
|
|
BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout1_buf/O
|
|
net (fo=6484, routed) 0.961 -0.347 u_Axi_CDC/awFifo/popToPushGray_buffercc/cpu_clk
|
|
SLICE_X15Y69 FDCE r u_Axi_CDC/awFifo/popToPushGray_buffercc/buffers_1_reg[0]/C
|
|
clock pessimism -0.228 -0.575
|
|
SLICE_X15Y69 FDCE (Hold_fdce_C_D) 0.075 -0.500 u_Axi_CDC/awFifo/popToPushGray_buffercc/buffers_1_reg[0]
|
|
-------------------------------------------------------------------
|
|
required time 0.500
|
|
arrival time -0.378
|
|
-------------------------------------------------------------------
|
|
slack 0.122
|
|
|
|
Slack (MET) : 0.122ns (arrival time - required time)
|
|
Source: u_Axi_CDC/bFifo/pushToPopGray_buffercc/buffers_0_reg[0]/C
|
|
(rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns})
|
|
Destination: u_Axi_CDC/bFifo/pushToPopGray_buffercc/buffers_1_reg[0]/D
|
|
(rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns})
|
|
Path Group: cpu_clk
|
|
Path Type: Hold (Min at Fast Process Corner)
|
|
Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns)
|
|
Data Path Delay: 0.197ns (logic 0.141ns (71.611%) route 0.056ns (28.389%))
|
|
Logic Levels: 0
|
|
Clock Path Skew: 0.000ns (DCD - SCD - CPR)
|
|
Destination Clock Delay (DCD): -0.338ns
|
|
Source Clock Delay (SCD): -0.568ns
|
|
Clock Pessimism Removal (CPR): 0.230ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock cpu_clk rise edge) 0.000 0.000 r
|
|
K21 0.000 0.000 r clk (IN)
|
|
net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1
|
|
K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O
|
|
net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll
|
|
PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0)
|
|
-2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0
|
|
net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll
|
|
BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout1_buf/O
|
|
net (fo=6484, routed) 0.694 -0.568 u_Axi_CDC/bFifo/pushToPopGray_buffercc/cpu_clk
|
|
SLICE_X19Y59 FDCE r u_Axi_CDC/bFifo/pushToPopGray_buffercc/buffers_0_reg[0]/C
|
|
------------------------------------------------------------------- -------------------
|
|
SLICE_X19Y59 FDCE (Prop_fdce_C_Q) 0.141 -0.427 r u_Axi_CDC/bFifo/pushToPopGray_buffercc/buffers_0_reg[0]/Q
|
|
net (fo=1, routed) 0.056 -0.371 u_Axi_CDC/bFifo/pushToPopGray_buffercc/buffers_0[0]
|
|
SLICE_X19Y59 FDCE r u_Axi_CDC/bFifo/pushToPopGray_buffercc/buffers_1_reg[0]/D
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock cpu_clk rise edge) 0.000 0.000 r
|
|
K21 0.000 0.000 r clk (IN)
|
|
net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1
|
|
K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O
|
|
net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll
|
|
PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0)
|
|
-2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0
|
|
net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll
|
|
BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout1_buf/O
|
|
net (fo=6484, routed) 0.970 -0.338 u_Axi_CDC/bFifo/pushToPopGray_buffercc/cpu_clk
|
|
SLICE_X19Y59 FDCE r u_Axi_CDC/bFifo/pushToPopGray_buffercc/buffers_1_reg[0]/C
|
|
clock pessimism -0.230 -0.568
|
|
SLICE_X19Y59 FDCE (Hold_fdce_C_D) 0.075 -0.493 u_Axi_CDC/bFifo/pushToPopGray_buffercc/buffers_1_reg[0]
|
|
-------------------------------------------------------------------
|
|
required time 0.493
|
|
arrival time -0.371
|
|
-------------------------------------------------------------------
|
|
slack 0.122
|
|
|
|
Slack (MET) : 0.122ns (arrival time - required time)
|
|
Source: u_Axi_CDC/rFifo/pushToPopGray_buffercc/buffers_0_reg[0]/C
|
|
(rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns})
|
|
Destination: u_Axi_CDC/rFifo/pushToPopGray_buffercc/buffers_1_reg[0]/D
|
|
(rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns})
|
|
Path Group: cpu_clk
|
|
Path Type: Hold (Min at Fast Process Corner)
|
|
Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns)
|
|
Data Path Delay: 0.197ns (logic 0.141ns (71.611%) route 0.056ns (28.389%))
|
|
Logic Levels: 0
|
|
Clock Path Skew: 0.000ns (DCD - SCD - CPR)
|
|
Destination Clock Delay (DCD): -0.323ns
|
|
Source Clock Delay (SCD): -0.552ns
|
|
Clock Pessimism Removal (CPR): 0.229ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock cpu_clk rise edge) 0.000 0.000 r
|
|
K21 0.000 0.000 r clk (IN)
|
|
net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1
|
|
K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O
|
|
net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll
|
|
PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0)
|
|
-2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0
|
|
net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll
|
|
BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout1_buf/O
|
|
net (fo=6484, routed) 0.710 -0.552 u_Axi_CDC/rFifo/pushToPopGray_buffercc/cpu_clk
|
|
SLICE_X5Y76 FDCE r u_Axi_CDC/rFifo/pushToPopGray_buffercc/buffers_0_reg[0]/C
|
|
------------------------------------------------------------------- -------------------
|
|
SLICE_X5Y76 FDCE (Prop_fdce_C_Q) 0.141 -0.411 r u_Axi_CDC/rFifo/pushToPopGray_buffercc/buffers_0_reg[0]/Q
|
|
net (fo=1, routed) 0.056 -0.355 u_Axi_CDC/rFifo/pushToPopGray_buffercc/buffers_0[0]
|
|
SLICE_X5Y76 FDCE r u_Axi_CDC/rFifo/pushToPopGray_buffercc/buffers_1_reg[0]/D
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock cpu_clk rise edge) 0.000 0.000 r
|
|
K21 0.000 0.000 r clk (IN)
|
|
net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1
|
|
K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O
|
|
net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll
|
|
PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0)
|
|
-2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0
|
|
net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll
|
|
BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout1_buf/O
|
|
net (fo=6484, routed) 0.985 -0.323 u_Axi_CDC/rFifo/pushToPopGray_buffercc/cpu_clk
|
|
SLICE_X5Y76 FDCE r u_Axi_CDC/rFifo/pushToPopGray_buffercc/buffers_1_reg[0]/C
|
|
clock pessimism -0.229 -0.552
|
|
SLICE_X5Y76 FDCE (Hold_fdce_C_D) 0.075 -0.477 u_Axi_CDC/rFifo/pushToPopGray_buffercc/buffers_1_reg[0]
|
|
-------------------------------------------------------------------
|
|
required time 0.477
|
|
arrival time -0.355
|
|
-------------------------------------------------------------------
|
|
slack 0.122
|
|
|
|
Slack (MET) : 0.122ns (arrival time - required time)
|
|
Source: u_Axi_CDC/rFifo/pushToPopGray_buffercc/buffers_0_reg[3]/C
|
|
(rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns})
|
|
Destination: u_Axi_CDC/rFifo/pushToPopGray_buffercc/buffers_1_reg[3]/D
|
|
(rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns})
|
|
Path Group: cpu_clk
|
|
Path Type: Hold (Min at Fast Process Corner)
|
|
Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns)
|
|
Data Path Delay: 0.197ns (logic 0.141ns (71.611%) route 0.056ns (28.389%))
|
|
Logic Levels: 0
|
|
Clock Path Skew: 0.000ns (DCD - SCD - CPR)
|
|
Destination Clock Delay (DCD): -0.324ns
|
|
Source Clock Delay (SCD): -0.553ns
|
|
Clock Pessimism Removal (CPR): 0.229ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock cpu_clk rise edge) 0.000 0.000 r
|
|
K21 0.000 0.000 r clk (IN)
|
|
net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1
|
|
K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O
|
|
net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll
|
|
PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0)
|
|
-2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0
|
|
net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll
|
|
BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout1_buf/O
|
|
net (fo=6484, routed) 0.709 -0.553 u_Axi_CDC/rFifo/pushToPopGray_buffercc/cpu_clk
|
|
SLICE_X5Y75 FDCE r u_Axi_CDC/rFifo/pushToPopGray_buffercc/buffers_0_reg[3]/C
|
|
------------------------------------------------------------------- -------------------
|
|
SLICE_X5Y75 FDCE (Prop_fdce_C_Q) 0.141 -0.412 r u_Axi_CDC/rFifo/pushToPopGray_buffercc/buffers_0_reg[3]/Q
|
|
net (fo=1, routed) 0.056 -0.356 u_Axi_CDC/rFifo/pushToPopGray_buffercc/buffers_0[3]
|
|
SLICE_X5Y75 FDCE r u_Axi_CDC/rFifo/pushToPopGray_buffercc/buffers_1_reg[3]/D
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock cpu_clk rise edge) 0.000 0.000 r
|
|
K21 0.000 0.000 r clk (IN)
|
|
net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1
|
|
K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O
|
|
net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll
|
|
PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0)
|
|
-2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0
|
|
net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll
|
|
BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout1_buf/O
|
|
net (fo=6484, routed) 0.984 -0.324 u_Axi_CDC/rFifo/pushToPopGray_buffercc/cpu_clk
|
|
SLICE_X5Y75 FDCE r u_Axi_CDC/rFifo/pushToPopGray_buffercc/buffers_1_reg[3]/C
|
|
clock pessimism -0.229 -0.553
|
|
SLICE_X5Y75 FDCE (Hold_fdce_C_D) 0.075 -0.478 u_Axi_CDC/rFifo/pushToPopGray_buffercc/buffers_1_reg[3]
|
|
-------------------------------------------------------------------
|
|
required time 0.478
|
|
arrival time -0.356
|
|
-------------------------------------------------------------------
|
|
slack 0.122
|
|
|
|
Slack (MET) : 0.123ns (arrival time - required time)
|
|
Source: u_cpu/u_csr/csr_tlbelo0_reg[12]/C
|
|
(rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns})
|
|
Destination: u_cpu/addr_trans/tlb_entry/tlb_ppn0_reg_r3_0_31_0_5/RAMC/I
|
|
(rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns})
|
|
Path Group: cpu_clk
|
|
Path Type: Hold (Min at Fast Process Corner)
|
|
Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns)
|
|
Data Path Delay: 0.280ns (logic 0.141ns (50.404%) route 0.139ns (49.596%))
|
|
Logic Levels: 0
|
|
Clock Path Skew: 0.013ns (DCD - SCD - CPR)
|
|
Destination Clock Delay (DCD): -0.309ns
|
|
Source Clock Delay (SCD): -0.540ns
|
|
Clock Pessimism Removal (CPR): 0.218ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock cpu_clk rise edge) 0.000 0.000 r
|
|
K21 0.000 0.000 r clk (IN)
|
|
net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1
|
|
K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O
|
|
net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll
|
|
PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0)
|
|
-2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0
|
|
net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll
|
|
BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout1_buf/O
|
|
net (fo=6484, routed) 0.723 -0.540 u_cpu/u_csr/cpu_clk
|
|
SLICE_X45Y34 FDRE r u_cpu/u_csr/csr_tlbelo0_reg[12]/C
|
|
------------------------------------------------------------------- -------------------
|
|
SLICE_X45Y34 FDRE (Prop_fdre_C_Q) 0.141 -0.399 r u_cpu/u_csr/csr_tlbelo0_reg[12]/Q
|
|
net (fo=4, routed) 0.139 -0.260 u_cpu/addr_trans/tlb_entry/tlb_ppn0_reg_r3_0_31_0_5/DIC0
|
|
SLICE_X44Y34 RAMD32 r u_cpu/addr_trans/tlb_entry/tlb_ppn0_reg_r3_0_31_0_5/RAMC/I
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock cpu_clk rise edge) 0.000 0.000 r
|
|
K21 0.000 0.000 r clk (IN)
|
|
net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1
|
|
K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O
|
|
net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll
|
|
PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0)
|
|
-2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0
|
|
net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll
|
|
BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout1_buf/O
|
|
net (fo=6484, routed) 0.999 -0.309 u_cpu/addr_trans/tlb_entry/tlb_ppn0_reg_r3_0_31_0_5/WCLK
|
|
SLICE_X44Y34 RAMD32 r u_cpu/addr_trans/tlb_entry/tlb_ppn0_reg_r3_0_31_0_5/RAMC/CLK
|
|
clock pessimism -0.218 -0.527
|
|
SLICE_X44Y34 RAMD32 (Hold_ramd32_CLK_I)
|
|
0.144 -0.383 u_cpu/addr_trans/tlb_entry/tlb_ppn0_reg_r3_0_31_0_5/RAMC
|
|
-------------------------------------------------------------------
|
|
required time 0.383
|
|
arrival time -0.260
|
|
-------------------------------------------------------------------
|
|
slack 0.123
|
|
|
|
Slack (MET) : 0.124ns (arrival time - required time)
|
|
Source: u_cpu/u_csr/csr_tlbelo0_reg[16]/C
|
|
(rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns})
|
|
Destination: u_cpu/addr_trans/tlb_entry/tlb_ppn0_reg_r3_0_31_6_11/RAMB/I
|
|
(rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns})
|
|
Path Group: cpu_clk
|
|
Path Type: Hold (Min at Fast Process Corner)
|
|
Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns)
|
|
Data Path Delay: 0.284ns (logic 0.141ns (49.682%) route 0.143ns (50.318%))
|
|
Logic Levels: 0
|
|
Clock Path Skew: 0.014ns (DCD - SCD - CPR)
|
|
Destination Clock Delay (DCD): -0.310ns
|
|
Source Clock Delay (SCD): -0.541ns
|
|
Clock Pessimism Removal (CPR): 0.217ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock cpu_clk rise edge) 0.000 0.000 r
|
|
K21 0.000 0.000 r clk (IN)
|
|
net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1
|
|
K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O
|
|
net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll
|
|
PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0)
|
|
-2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0
|
|
net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll
|
|
BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout1_buf/O
|
|
net (fo=6484, routed) 0.722 -0.541 u_cpu/u_csr/cpu_clk
|
|
SLICE_X47Y36 FDRE r u_cpu/u_csr/csr_tlbelo0_reg[16]/C
|
|
------------------------------------------------------------------- -------------------
|
|
SLICE_X47Y36 FDRE (Prop_fdre_C_Q) 0.141 -0.400 r u_cpu/u_csr/csr_tlbelo0_reg[16]/Q
|
|
net (fo=4, routed) 0.143 -0.257 u_cpu/addr_trans/tlb_entry/tlb_ppn0_reg_r3_0_31_6_11/DIB0
|
|
SLICE_X46Y34 RAMD32 r u_cpu/addr_trans/tlb_entry/tlb_ppn0_reg_r3_0_31_6_11/RAMB/I
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock cpu_clk rise edge) 0.000 0.000 r
|
|
K21 0.000 0.000 r clk (IN)
|
|
net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1
|
|
K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O
|
|
net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll
|
|
PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0)
|
|
-2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0
|
|
net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll
|
|
BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout1_buf/O
|
|
net (fo=6484, routed) 0.998 -0.310 u_cpu/addr_trans/tlb_entry/tlb_ppn0_reg_r3_0_31_6_11/WCLK
|
|
SLICE_X46Y34 RAMD32 r u_cpu/addr_trans/tlb_entry/tlb_ppn0_reg_r3_0_31_6_11/RAMB/CLK
|
|
clock pessimism -0.217 -0.527
|
|
SLICE_X46Y34 RAMD32 (Hold_ramd32_CLK_I)
|
|
0.146 -0.381 u_cpu/addr_trans/tlb_entry/tlb_ppn0_reg_r3_0_31_6_11/RAMB
|
|
-------------------------------------------------------------------
|
|
required time 0.381
|
|
arrival time -0.257
|
|
-------------------------------------------------------------------
|
|
slack 0.124
|
|
|
|
Slack (MET) : 0.124ns (arrival time - required time)
|
|
Source: u_cpu/axi_bridge/wdata_reg[22]/C
|
|
(rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns})
|
|
Destination: u_Axi_CDC/wFifo/ram_reg_0_7_18_23/RAMC/I
|
|
(rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns})
|
|
Path Group: cpu_clk
|
|
Path Type: Hold (Min at Fast Process Corner)
|
|
Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns)
|
|
Data Path Delay: 0.310ns (logic 0.141ns (45.479%) route 0.169ns (54.521%))
|
|
Logic Levels: 0
|
|
Clock Path Skew: 0.042ns (DCD - SCD - CPR)
|
|
Destination Clock Delay (DCD): -0.229ns
|
|
Source Clock Delay (SCD): -0.467ns
|
|
Clock Pessimism Removal (CPR): 0.196ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock cpu_clk rise edge) 0.000 0.000 r
|
|
K21 0.000 0.000 r clk (IN)
|
|
net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1
|
|
K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O
|
|
net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll
|
|
PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0)
|
|
-2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0
|
|
net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll
|
|
BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout1_buf/O
|
|
net (fo=6484, routed) 0.796 -0.467 u_cpu/axi_bridge/cpu_clk
|
|
SLICE_X5Y47 FDRE r u_cpu/axi_bridge/wdata_reg[22]/C
|
|
------------------------------------------------------------------- -------------------
|
|
SLICE_X5Y47 FDRE (Prop_fdre_C_Q) 0.141 -0.326 r u_cpu/axi_bridge/wdata_reg[22]/Q
|
|
net (fo=1, routed) 0.169 -0.157 u_Axi_CDC/wFifo/ram_reg_0_7_18_23/DIC0
|
|
SLICE_X2Y48 RAMD32 r u_Axi_CDC/wFifo/ram_reg_0_7_18_23/RAMC/I
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock cpu_clk rise edge) 0.000 0.000 r
|
|
K21 0.000 0.000 r clk (IN)
|
|
net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1
|
|
K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O
|
|
net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll
|
|
PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0)
|
|
-2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0
|
|
net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll
|
|
BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout1_buf/O
|
|
net (fo=6484, routed) 1.079 -0.229 u_Axi_CDC/wFifo/ram_reg_0_7_18_23/WCLK
|
|
SLICE_X2Y48 RAMD32 r u_Axi_CDC/wFifo/ram_reg_0_7_18_23/RAMC/CLK
|
|
clock pessimism -0.196 -0.425
|
|
SLICE_X2Y48 RAMD32 (Hold_ramd32_CLK_I)
|
|
0.144 -0.281 u_Axi_CDC/wFifo/ram_reg_0_7_18_23/RAMC
|
|
-------------------------------------------------------------------
|
|
required time 0.281
|
|
arrival time -0.157
|
|
-------------------------------------------------------------------
|
|
slack 0.124
|
|
|
|
Slack (MET) : 0.125ns (arrival time - required time)
|
|
Source: u_cpu/u_csr/csr_tlbelo1_reg[3]/C
|
|
(rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns})
|
|
Destination: u_cpu/addr_trans/tlb_entry/tlb_plv1_reg_r3_0_31_1_1/DP/I
|
|
(rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns})
|
|
Path Group: cpu_clk
|
|
Path Type: Hold (Min at Fast Process Corner)
|
|
Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns)
|
|
Data Path Delay: 0.261ns (logic 0.141ns (54.075%) route 0.120ns (45.925%))
|
|
Logic Levels: 0
|
|
Clock Path Skew: 0.016ns (DCD - SCD - CPR)
|
|
Destination Clock Delay (DCD): -0.275ns
|
|
Source Clock Delay (SCD): -0.509ns
|
|
Clock Pessimism Removal (CPR): 0.218ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock cpu_clk rise edge) 0.000 0.000 r
|
|
K21 0.000 0.000 r clk (IN)
|
|
net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1
|
|
K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O
|
|
net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll
|
|
PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0)
|
|
-2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0
|
|
net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll
|
|
BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout1_buf/O
|
|
net (fo=6484, routed) 0.754 -0.509 u_cpu/u_csr/cpu_clk
|
|
SLICE_X39Y39 FDRE r u_cpu/u_csr/csr_tlbelo1_reg[3]/C
|
|
------------------------------------------------------------------- -------------------
|
|
SLICE_X39Y39 FDRE (Prop_fdre_C_Q) 0.141 -0.368 r u_cpu/u_csr/csr_tlbelo1_reg[3]/Q
|
|
net (fo=7, routed) 0.120 -0.248 u_cpu/addr_trans/tlb_entry/tlb_plv1_reg_r3_0_31_1_1/D
|
|
SLICE_X40Y39 RAMD32 r u_cpu/addr_trans/tlb_entry/tlb_plv1_reg_r3_0_31_1_1/DP/I
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock cpu_clk rise edge) 0.000 0.000 r
|
|
K21 0.000 0.000 r clk (IN)
|
|
net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1
|
|
K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O
|
|
net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll
|
|
PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0)
|
|
-2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0
|
|
net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll
|
|
BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout1_buf/O
|
|
net (fo=6484, routed) 1.033 -0.275 u_cpu/addr_trans/tlb_entry/tlb_plv1_reg_r3_0_31_1_1/WCLK
|
|
SLICE_X40Y39 RAMD32 r u_cpu/addr_trans/tlb_entry/tlb_plv1_reg_r3_0_31_1_1/DP/CLK
|
|
clock pessimism -0.218 -0.493
|
|
SLICE_X40Y39 RAMD32 (Hold_ramd32_CLK_I)
|
|
0.120 -0.373 u_cpu/addr_trans/tlb_entry/tlb_plv1_reg_r3_0_31_1_1/DP
|
|
-------------------------------------------------------------------
|
|
required time 0.373
|
|
arrival time -0.248
|
|
-------------------------------------------------------------------
|
|
slack 0.125
|
|
|
|
Slack (MET) : 0.126ns (arrival time - required time)
|
|
Source: u_Axi_CDC/awFifo/popToPushGray_buffercc/buffers_0_reg[1]/C
|
|
(rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns})
|
|
Destination: u_Axi_CDC/awFifo/popToPushGray_buffercc/buffers_1_reg[1]/D
|
|
(rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns})
|
|
Path Group: cpu_clk
|
|
Path Type: Hold (Min at Fast Process Corner)
|
|
Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns)
|
|
Data Path Delay: 0.197ns (logic 0.141ns (71.611%) route 0.056ns (28.389%))
|
|
Logic Levels: 0
|
|
Clock Path Skew: 0.000ns (DCD - SCD - CPR)
|
|
Destination Clock Delay (DCD): -0.347ns
|
|
Source Clock Delay (SCD): -0.575ns
|
|
Clock Pessimism Removal (CPR): 0.228ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock cpu_clk rise edge) 0.000 0.000 r
|
|
K21 0.000 0.000 r clk (IN)
|
|
net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1
|
|
K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O
|
|
net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll
|
|
PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0)
|
|
-2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0
|
|
net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll
|
|
BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout1_buf/O
|
|
net (fo=6484, routed) 0.687 -0.575 u_Axi_CDC/awFifo/popToPushGray_buffercc/cpu_clk
|
|
SLICE_X15Y69 FDCE r u_Axi_CDC/awFifo/popToPushGray_buffercc/buffers_0_reg[1]/C
|
|
------------------------------------------------------------------- -------------------
|
|
SLICE_X15Y69 FDCE (Prop_fdce_C_Q) 0.141 -0.434 r u_Axi_CDC/awFifo/popToPushGray_buffercc/buffers_0_reg[1]/Q
|
|
net (fo=1, routed) 0.056 -0.378 u_Axi_CDC/awFifo/popToPushGray_buffercc/buffers_0[1]
|
|
SLICE_X15Y69 FDCE r u_Axi_CDC/awFifo/popToPushGray_buffercc/buffers_1_reg[1]/D
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock cpu_clk rise edge) 0.000 0.000 r
|
|
K21 0.000 0.000 r clk (IN)
|
|
net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1
|
|
K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O
|
|
net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll
|
|
PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0)
|
|
-2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0
|
|
net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll
|
|
BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout1_buf/O
|
|
net (fo=6484, routed) 0.961 -0.347 u_Axi_CDC/awFifo/popToPushGray_buffercc/cpu_clk
|
|
SLICE_X15Y69 FDCE r u_Axi_CDC/awFifo/popToPushGray_buffercc/buffers_1_reg[1]/C
|
|
clock pessimism -0.228 -0.575
|
|
SLICE_X15Y69 FDCE (Hold_fdce_C_D) 0.071 -0.504 u_Axi_CDC/awFifo/popToPushGray_buffercc/buffers_1_reg[1]
|
|
-------------------------------------------------------------------
|
|
required time 0.504
|
|
arrival time -0.378
|
|
-------------------------------------------------------------------
|
|
slack 0.126
|
|
|
|
Slack (MET) : 0.126ns (arrival time - required time)
|
|
Source: u_Axi_CDC/bFifo/pushToPopGray_buffercc/buffers_0_reg[1]/C
|
|
(rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns})
|
|
Destination: u_Axi_CDC/bFifo/pushToPopGray_buffercc/buffers_1_reg[1]/D
|
|
(rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns})
|
|
Path Group: cpu_clk
|
|
Path Type: Hold (Min at Fast Process Corner)
|
|
Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns)
|
|
Data Path Delay: 0.197ns (logic 0.141ns (71.611%) route 0.056ns (28.389%))
|
|
Logic Levels: 0
|
|
Clock Path Skew: 0.000ns (DCD - SCD - CPR)
|
|
Destination Clock Delay (DCD): -0.338ns
|
|
Source Clock Delay (SCD): -0.568ns
|
|
Clock Pessimism Removal (CPR): 0.230ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock cpu_clk rise edge) 0.000 0.000 r
|
|
K21 0.000 0.000 r clk (IN)
|
|
net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1
|
|
K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O
|
|
net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll
|
|
PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0)
|
|
-2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0
|
|
net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll
|
|
BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout1_buf/O
|
|
net (fo=6484, routed) 0.694 -0.568 u_Axi_CDC/bFifo/pushToPopGray_buffercc/cpu_clk
|
|
SLICE_X19Y59 FDCE r u_Axi_CDC/bFifo/pushToPopGray_buffercc/buffers_0_reg[1]/C
|
|
------------------------------------------------------------------- -------------------
|
|
SLICE_X19Y59 FDCE (Prop_fdce_C_Q) 0.141 -0.427 r u_Axi_CDC/bFifo/pushToPopGray_buffercc/buffers_0_reg[1]/Q
|
|
net (fo=1, routed) 0.056 -0.371 u_Axi_CDC/bFifo/pushToPopGray_buffercc/buffers_0[1]
|
|
SLICE_X19Y59 FDCE r u_Axi_CDC/bFifo/pushToPopGray_buffercc/buffers_1_reg[1]/D
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock cpu_clk rise edge) 0.000 0.000 r
|
|
K21 0.000 0.000 r clk (IN)
|
|
net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1
|
|
K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O
|
|
net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll
|
|
PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0)
|
|
-2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0
|
|
net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll
|
|
BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout1_buf/O
|
|
net (fo=6484, routed) 0.970 -0.338 u_Axi_CDC/bFifo/pushToPopGray_buffercc/cpu_clk
|
|
SLICE_X19Y59 FDCE r u_Axi_CDC/bFifo/pushToPopGray_buffercc/buffers_1_reg[1]/C
|
|
clock pessimism -0.230 -0.568
|
|
SLICE_X19Y59 FDCE (Hold_fdce_C_D) 0.071 -0.497 u_Axi_CDC/bFifo/pushToPopGray_buffercc/buffers_1_reg[1]
|
|
-------------------------------------------------------------------
|
|
required time 0.497
|
|
arrival time -0.371
|
|
-------------------------------------------------------------------
|
|
slack 0.126
|
|
|
|
Slack (MET) : 0.126ns (arrival time - required time)
|
|
Source: u_Axi_CDC/rFifo/pushToPopGray_buffercc/buffers_0_reg[1]/C
|
|
(rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns})
|
|
Destination: u_Axi_CDC/rFifo/pushToPopGray_buffercc/buffers_1_reg[1]/D
|
|
(rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns})
|
|
Path Group: cpu_clk
|
|
Path Type: Hold (Min at Fast Process Corner)
|
|
Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns)
|
|
Data Path Delay: 0.197ns (logic 0.141ns (71.611%) route 0.056ns (28.389%))
|
|
Logic Levels: 0
|
|
Clock Path Skew: 0.000ns (DCD - SCD - CPR)
|
|
Destination Clock Delay (DCD): -0.323ns
|
|
Source Clock Delay (SCD): -0.552ns
|
|
Clock Pessimism Removal (CPR): 0.229ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock cpu_clk rise edge) 0.000 0.000 r
|
|
K21 0.000 0.000 r clk (IN)
|
|
net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1
|
|
K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O
|
|
net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll
|
|
PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0)
|
|
-2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0
|
|
net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll
|
|
BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout1_buf/O
|
|
net (fo=6484, routed) 0.710 -0.552 u_Axi_CDC/rFifo/pushToPopGray_buffercc/cpu_clk
|
|
SLICE_X5Y76 FDCE r u_Axi_CDC/rFifo/pushToPopGray_buffercc/buffers_0_reg[1]/C
|
|
------------------------------------------------------------------- -------------------
|
|
SLICE_X5Y76 FDCE (Prop_fdce_C_Q) 0.141 -0.411 r u_Axi_CDC/rFifo/pushToPopGray_buffercc/buffers_0_reg[1]/Q
|
|
net (fo=1, routed) 0.056 -0.355 u_Axi_CDC/rFifo/pushToPopGray_buffercc/buffers_0[1]
|
|
SLICE_X5Y76 FDCE r u_Axi_CDC/rFifo/pushToPopGray_buffercc/buffers_1_reg[1]/D
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock cpu_clk rise edge) 0.000 0.000 r
|
|
K21 0.000 0.000 r clk (IN)
|
|
net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1
|
|
K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O
|
|
net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll
|
|
PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0)
|
|
-2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0
|
|
net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll
|
|
BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout1_buf/O
|
|
net (fo=6484, routed) 0.985 -0.323 u_Axi_CDC/rFifo/pushToPopGray_buffercc/cpu_clk
|
|
SLICE_X5Y76 FDCE r u_Axi_CDC/rFifo/pushToPopGray_buffercc/buffers_1_reg[1]/C
|
|
clock pessimism -0.229 -0.552
|
|
SLICE_X5Y76 FDCE (Hold_fdce_C_D) 0.071 -0.481 u_Axi_CDC/rFifo/pushToPopGray_buffercc/buffers_1_reg[1]
|
|
-------------------------------------------------------------------
|
|
required time 0.481
|
|
arrival time -0.355
|
|
-------------------------------------------------------------------
|
|
slack 0.126
|
|
|
|
Slack (MET) : 0.128ns (arrival time - required time)
|
|
Source: u_Axi_CDC/wFifo/popToPushGray_buffercc/buffers_0_reg[1]/C
|
|
(rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns})
|
|
Destination: u_Axi_CDC/wFifo/popToPushGray_buffercc/buffers_1_reg[1]/D
|
|
(rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns})
|
|
Path Group: cpu_clk
|
|
Path Type: Hold (Min at Fast Process Corner)
|
|
Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns)
|
|
Data Path Delay: 0.199ns (logic 0.141ns (70.953%) route 0.058ns (29.047%))
|
|
Logic Levels: 0
|
|
Clock Path Skew: 0.000ns (DCD - SCD - CPR)
|
|
Destination Clock Delay (DCD): -0.229ns
|
|
Source Clock Delay (SCD): -0.465ns
|
|
Clock Pessimism Removal (CPR): 0.236ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock cpu_clk rise edge) 0.000 0.000 r
|
|
K21 0.000 0.000 r clk (IN)
|
|
net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1
|
|
K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O
|
|
net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll
|
|
PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0)
|
|
-2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0
|
|
net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll
|
|
BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout1_buf/O
|
|
net (fo=6484, routed) 0.798 -0.465 u_Axi_CDC/wFifo/popToPushGray_buffercc/cpu_clk
|
|
SLICE_X0Y49 FDCE r u_Axi_CDC/wFifo/popToPushGray_buffercc/buffers_0_reg[1]/C
|
|
------------------------------------------------------------------- -------------------
|
|
SLICE_X0Y49 FDCE (Prop_fdce_C_Q) 0.141 -0.324 r u_Axi_CDC/wFifo/popToPushGray_buffercc/buffers_0_reg[1]/Q
|
|
net (fo=1, routed) 0.058 -0.266 u_Axi_CDC/wFifo/popToPushGray_buffercc/buffers_0[1]
|
|
SLICE_X0Y49 FDCE r u_Axi_CDC/wFifo/popToPushGray_buffercc/buffers_1_reg[1]/D
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock cpu_clk rise edge) 0.000 0.000 r
|
|
K21 0.000 0.000 r clk (IN)
|
|
net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1
|
|
K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O
|
|
net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll
|
|
PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0)
|
|
-2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0
|
|
net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll
|
|
BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout1_buf/O
|
|
net (fo=6484, routed) 1.079 -0.229 u_Axi_CDC/wFifo/popToPushGray_buffercc/cpu_clk
|
|
SLICE_X0Y49 FDCE r u_Axi_CDC/wFifo/popToPushGray_buffercc/buffers_1_reg[1]/C
|
|
clock pessimism -0.236 -0.465
|
|
SLICE_X0Y49 FDCE (Hold_fdce_C_D) 0.071 -0.394 u_Axi_CDC/wFifo/popToPushGray_buffercc/buffers_1_reg[1]
|
|
-------------------------------------------------------------------
|
|
required time 0.394
|
|
arrival time -0.266
|
|
-------------------------------------------------------------------
|
|
slack 0.128
|
|
|
|
Slack (MET) : 0.128ns (arrival time - required time)
|
|
Source: u_cpu/u_csr/csr_tlbelo1_reg[15]/C
|
|
(rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns})
|
|
Destination: u_cpu/addr_trans/tlb_entry/tlb_ppn1_reg_r1_0_31_6_11/RAMA_D1/I
|
|
(rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns})
|
|
Path Group: cpu_clk
|
|
Path Type: Hold (Min at Fast Process Corner)
|
|
Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns)
|
|
Data Path Delay: 0.265ns (logic 0.141ns (53.167%) route 0.124ns (46.833%))
|
|
Logic Levels: 0
|
|
Clock Path Skew: 0.017ns (DCD - SCD - CPR)
|
|
Destination Clock Delay (DCD): -0.275ns
|
|
Source Clock Delay (SCD): -0.510ns
|
|
Clock Pessimism Removal (CPR): 0.218ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock cpu_clk rise edge) 0.000 0.000 r
|
|
K21 0.000 0.000 r clk (IN)
|
|
net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1
|
|
K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O
|
|
net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll
|
|
PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0)
|
|
-2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0
|
|
net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll
|
|
BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout1_buf/O
|
|
net (fo=6484, routed) 0.753 -0.510 u_cpu/u_csr/cpu_clk
|
|
SLICE_X41Y37 FDRE r u_cpu/u_csr/csr_tlbelo1_reg[15]/C
|
|
------------------------------------------------------------------- -------------------
|
|
SLICE_X41Y37 FDRE (Prop_fdre_C_Q) 0.141 -0.369 r u_cpu/u_csr/csr_tlbelo1_reg[15]/Q
|
|
net (fo=4, routed) 0.124 -0.245 u_cpu/addr_trans/tlb_entry/tlb_ppn1_reg_r1_0_31_6_11/DIA1
|
|
SLICE_X40Y38 RAMD32 r u_cpu/addr_trans/tlb_entry/tlb_ppn1_reg_r1_0_31_6_11/RAMA_D1/I
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock cpu_clk rise edge) 0.000 0.000 r
|
|
K21 0.000 0.000 r clk (IN)
|
|
net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1
|
|
K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O
|
|
net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll
|
|
PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0)
|
|
-2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0
|
|
net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll
|
|
BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout1_buf/O
|
|
net (fo=6484, routed) 1.033 -0.275 u_cpu/addr_trans/tlb_entry/tlb_ppn1_reg_r1_0_31_6_11/WCLK
|
|
SLICE_X40Y38 RAMD32 r u_cpu/addr_trans/tlb_entry/tlb_ppn1_reg_r1_0_31_6_11/RAMA_D1/CLK
|
|
clock pessimism -0.218 -0.493
|
|
SLICE_X40Y38 RAMD32 (Hold_ramd32_CLK_I)
|
|
0.120 -0.373 u_cpu/addr_trans/tlb_entry/tlb_ppn1_reg_r1_0_31_6_11/RAMA_D1
|
|
-------------------------------------------------------------------
|
|
required time 0.373
|
|
arrival time -0.245
|
|
-------------------------------------------------------------------
|
|
slack 0.128
|
|
|
|
Slack (MET) : 0.128ns (arrival time - required time)
|
|
Source: u_cpu/u_csr/csr_tlbelo1_reg[27]/C
|
|
(rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns})
|
|
Destination: u_cpu/addr_trans/tlb_entry/tlb_ppn1_reg_r1_0_31_18_19/RAMA_D1/I
|
|
(rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns})
|
|
Path Group: cpu_clk
|
|
Path Type: Hold (Min at Fast Process Corner)
|
|
Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns)
|
|
Data Path Delay: 0.263ns (logic 0.141ns (53.571%) route 0.122ns (46.429%))
|
|
Logic Levels: 0
|
|
Clock Path Skew: 0.015ns (DCD - SCD - CPR)
|
|
Destination Clock Delay (DCD): -0.309ns
|
|
Source Clock Delay (SCD): -0.541ns
|
|
Clock Pessimism Removal (CPR): 0.217ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock cpu_clk rise edge) 0.000 0.000 r
|
|
K21 0.000 0.000 r clk (IN)
|
|
net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1
|
|
K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O
|
|
net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll
|
|
PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0)
|
|
-2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0
|
|
net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll
|
|
BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout1_buf/O
|
|
net (fo=6484, routed) 0.722 -0.541 u_cpu/u_csr/cpu_clk
|
|
SLICE_X47Y35 FDRE r u_cpu/u_csr/csr_tlbelo1_reg[27]/C
|
|
------------------------------------------------------------------- -------------------
|
|
SLICE_X47Y35 FDRE (Prop_fdre_C_Q) 0.141 -0.400 r u_cpu/u_csr/csr_tlbelo1_reg[27]/Q
|
|
net (fo=4, routed) 0.122 -0.278 u_cpu/addr_trans/tlb_entry/tlb_ppn1_reg_r1_0_31_18_19/DIA1
|
|
SLICE_X46Y36 RAMD32 r u_cpu/addr_trans/tlb_entry/tlb_ppn1_reg_r1_0_31_18_19/RAMA_D1/I
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock cpu_clk rise edge) 0.000 0.000 r
|
|
K21 0.000 0.000 r clk (IN)
|
|
net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1
|
|
K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O
|
|
net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll
|
|
PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0)
|
|
-2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0
|
|
net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll
|
|
BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout1_buf/O
|
|
net (fo=6484, routed) 0.999 -0.309 u_cpu/addr_trans/tlb_entry/tlb_ppn1_reg_r1_0_31_18_19/WCLK
|
|
SLICE_X46Y36 RAMD32 r u_cpu/addr_trans/tlb_entry/tlb_ppn1_reg_r1_0_31_18_19/RAMA_D1/CLK
|
|
clock pessimism -0.217 -0.526
|
|
SLICE_X46Y36 RAMD32 (Hold_ramd32_CLK_I)
|
|
0.120 -0.406 u_cpu/addr_trans/tlb_entry/tlb_ppn1_reg_r1_0_31_18_19/RAMA_D1
|
|
-------------------------------------------------------------------
|
|
required time 0.406
|
|
arrival time -0.278
|
|
-------------------------------------------------------------------
|
|
slack 0.128
|
|
|
|
Slack (MET) : 0.131ns (arrival time - required time)
|
|
Source: u_Axi_CDC/bFifo/bufferCC_12/buffers_0_reg/C
|
|
(rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns})
|
|
Destination: u_Axi_CDC/bFifo/bufferCC_12/buffers_1_reg/D
|
|
(rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns})
|
|
Path Group: cpu_clk
|
|
Path Type: Hold (Min at Fast Process Corner)
|
|
Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns)
|
|
Data Path Delay: 0.206ns (logic 0.141ns (68.336%) route 0.065ns (31.664%))
|
|
Logic Levels: 0
|
|
Clock Path Skew: 0.000ns (DCD - SCD - CPR)
|
|
Destination Clock Delay (DCD): -0.345ns
|
|
Source Clock Delay (SCD): -0.575ns
|
|
Clock Pessimism Removal (CPR): 0.230ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock cpu_clk rise edge) 0.000 0.000 r
|
|
K21 0.000 0.000 r clk (IN)
|
|
net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1
|
|
K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O
|
|
net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll
|
|
PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0)
|
|
-2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0
|
|
net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll
|
|
BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout1_buf/O
|
|
net (fo=6484, routed) 0.687 -0.575 u_Axi_CDC/bFifo/bufferCC_12/cpu_clk
|
|
SLICE_X30Y58 FDCE r u_Axi_CDC/bFifo/bufferCC_12/buffers_0_reg/C
|
|
------------------------------------------------------------------- -------------------
|
|
SLICE_X30Y58 FDCE (Prop_fdce_C_Q) 0.141 -0.434 r u_Axi_CDC/bFifo/bufferCC_12/buffers_0_reg/Q
|
|
net (fo=1, routed) 0.065 -0.369 u_Axi_CDC/bFifo/bufferCC_12/buffers_0
|
|
SLICE_X30Y58 FDCE r u_Axi_CDC/bFifo/bufferCC_12/buffers_1_reg/D
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock cpu_clk rise edge) 0.000 0.000 r
|
|
K21 0.000 0.000 r clk (IN)
|
|
net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1
|
|
K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O
|
|
net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll
|
|
PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0)
|
|
-2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0
|
|
net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll
|
|
BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout1_buf/O
|
|
net (fo=6484, routed) 0.963 -0.345 u_Axi_CDC/bFifo/bufferCC_12/cpu_clk
|
|
SLICE_X30Y58 FDCE r u_Axi_CDC/bFifo/bufferCC_12/buffers_1_reg/C
|
|
clock pessimism -0.230 -0.575
|
|
SLICE_X30Y58 FDCE (Hold_fdce_C_D) 0.075 -0.500 u_Axi_CDC/bFifo/bufferCC_12/buffers_1_reg
|
|
-------------------------------------------------------------------
|
|
required time 0.500
|
|
arrival time -0.369
|
|
-------------------------------------------------------------------
|
|
slack 0.131
|
|
|
|
Slack (MET) : 0.131ns (arrival time - required time)
|
|
Source: u_Axi_CDC/wFifo/popToPushGray_buffercc/buffers_0_reg[0]/C
|
|
(rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns})
|
|
Destination: u_Axi_CDC/wFifo/popToPushGray_buffercc/buffers_1_reg[0]/D
|
|
(rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns})
|
|
Path Group: cpu_clk
|
|
Path Type: Hold (Min at Fast Process Corner)
|
|
Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns)
|
|
Data Path Delay: 0.206ns (logic 0.141ns (68.336%) route 0.065ns (31.664%))
|
|
Logic Levels: 0
|
|
Clock Path Skew: 0.000ns (DCD - SCD - CPR)
|
|
Destination Clock Delay (DCD): -0.229ns
|
|
Source Clock Delay (SCD): -0.465ns
|
|
Clock Pessimism Removal (CPR): 0.236ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock cpu_clk rise edge) 0.000 0.000 r
|
|
K21 0.000 0.000 r clk (IN)
|
|
net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1
|
|
K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O
|
|
net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll
|
|
PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0)
|
|
-2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0
|
|
net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll
|
|
BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout1_buf/O
|
|
net (fo=6484, routed) 0.798 -0.465 u_Axi_CDC/wFifo/popToPushGray_buffercc/cpu_clk
|
|
SLICE_X0Y49 FDCE r u_Axi_CDC/wFifo/popToPushGray_buffercc/buffers_0_reg[0]/C
|
|
------------------------------------------------------------------- -------------------
|
|
SLICE_X0Y49 FDCE (Prop_fdce_C_Q) 0.141 -0.324 r u_Axi_CDC/wFifo/popToPushGray_buffercc/buffers_0_reg[0]/Q
|
|
net (fo=1, routed) 0.065 -0.258 u_Axi_CDC/wFifo/popToPushGray_buffercc/buffers_0[0]
|
|
SLICE_X0Y49 FDCE r u_Axi_CDC/wFifo/popToPushGray_buffercc/buffers_1_reg[0]/D
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock cpu_clk rise edge) 0.000 0.000 r
|
|
K21 0.000 0.000 r clk (IN)
|
|
net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1
|
|
K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O
|
|
net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll
|
|
PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0)
|
|
-2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0
|
|
net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll
|
|
BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout1_buf/O
|
|
net (fo=6484, routed) 1.079 -0.229 u_Axi_CDC/wFifo/popToPushGray_buffercc/cpu_clk
|
|
SLICE_X0Y49 FDCE r u_Axi_CDC/wFifo/popToPushGray_buffercc/buffers_1_reg[0]/C
|
|
clock pessimism -0.236 -0.465
|
|
SLICE_X0Y49 FDCE (Hold_fdce_C_D) 0.075 -0.390 u_Axi_CDC/wFifo/popToPushGray_buffercc/buffers_1_reg[0]
|
|
-------------------------------------------------------------------
|
|
required time 0.390
|
|
arrival time -0.258
|
|
-------------------------------------------------------------------
|
|
slack 0.131
|
|
|
|
Slack (MET) : 0.132ns (arrival time - required time)
|
|
Source: u_cpu/u_csr/csr_tlbelo0_reg[20]/C
|
|
(rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns})
|
|
Destination: u_cpu/addr_trans/tlb_entry/tlb_ppn0_reg_r3_0_31_12_17/RAMA/I
|
|
(rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns})
|
|
Path Group: cpu_clk
|
|
Path Type: Hold (Min at Fast Process Corner)
|
|
Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns)
|
|
Data Path Delay: 0.294ns (logic 0.141ns (47.970%) route 0.153ns (52.030%))
|
|
Logic Levels: 0
|
|
Clock Path Skew: 0.015ns (DCD - SCD - CPR)
|
|
Destination Clock Delay (DCD): -0.310ns
|
|
Source Clock Delay (SCD): -0.542ns
|
|
Clock Pessimism Removal (CPR): 0.217ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock cpu_clk rise edge) 0.000 0.000 r
|
|
K21 0.000 0.000 r clk (IN)
|
|
net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1
|
|
K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O
|
|
net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll
|
|
PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0)
|
|
-2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0
|
|
net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll
|
|
BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout1_buf/O
|
|
net (fo=6484, routed) 0.721 -0.542 u_cpu/u_csr/cpu_clk
|
|
SLICE_X43Y32 FDRE r u_cpu/u_csr/csr_tlbelo0_reg[20]/C
|
|
------------------------------------------------------------------- -------------------
|
|
SLICE_X43Y32 FDRE (Prop_fdre_C_Q) 0.141 -0.401 r u_cpu/u_csr/csr_tlbelo0_reg[20]/Q
|
|
net (fo=4, routed) 0.153 -0.248 u_cpu/addr_trans/tlb_entry/tlb_ppn0_reg_r3_0_31_12_17/DIA0
|
|
SLICE_X42Y33 RAMD32 r u_cpu/addr_trans/tlb_entry/tlb_ppn0_reg_r3_0_31_12_17/RAMA/I
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock cpu_clk rise edge) 0.000 0.000 r
|
|
K21 0.000 0.000 r clk (IN)
|
|
net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1
|
|
K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O
|
|
net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll
|
|
PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0)
|
|
-2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0
|
|
net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll
|
|
BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout1_buf/O
|
|
net (fo=6484, routed) 0.998 -0.310 u_cpu/addr_trans/tlb_entry/tlb_ppn0_reg_r3_0_31_12_17/WCLK
|
|
SLICE_X42Y33 RAMD32 r u_cpu/addr_trans/tlb_entry/tlb_ppn0_reg_r3_0_31_12_17/RAMA/CLK
|
|
clock pessimism -0.217 -0.527
|
|
SLICE_X42Y33 RAMD32 (Hold_ramd32_CLK_I)
|
|
0.147 -0.380 u_cpu/addr_trans/tlb_entry/tlb_ppn0_reg_r3_0_31_12_17/RAMA
|
|
-------------------------------------------------------------------
|
|
required time 0.380
|
|
arrival time -0.248
|
|
-------------------------------------------------------------------
|
|
slack 0.132
|
|
|
|
Slack (MET) : 0.133ns (arrival time - required time)
|
|
Source: u_cpu/axi_bridge/wdata_reg[0]/C
|
|
(rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns})
|
|
Destination: u_Axi_CDC/wFifo/ram_reg_0_7_0_5/RAMA/I
|
|
(rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns})
|
|
Path Group: cpu_clk
|
|
Path Type: Hold (Min at Fast Process Corner)
|
|
Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns)
|
|
Data Path Delay: 0.296ns (logic 0.141ns (47.613%) route 0.155ns (52.387%))
|
|
Logic Levels: 0
|
|
Clock Path Skew: 0.016ns (DCD - SCD - CPR)
|
|
Destination Clock Delay (DCD): -0.232ns
|
|
Source Clock Delay (SCD): -0.468ns
|
|
Clock Pessimism Removal (CPR): 0.220ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock cpu_clk rise edge) 0.000 0.000 r
|
|
K21 0.000 0.000 r clk (IN)
|
|
net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1
|
|
K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O
|
|
net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll
|
|
PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0)
|
|
-2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0
|
|
net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll
|
|
BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout1_buf/O
|
|
net (fo=6484, routed) 0.795 -0.468 u_cpu/axi_bridge/cpu_clk
|
|
SLICE_X5Y45 FDRE r u_cpu/axi_bridge/wdata_reg[0]/C
|
|
------------------------------------------------------------------- -------------------
|
|
SLICE_X5Y45 FDRE (Prop_fdre_C_Q) 0.141 -0.327 r u_cpu/axi_bridge/wdata_reg[0]/Q
|
|
net (fo=1, routed) 0.155 -0.172 u_Axi_CDC/wFifo/ram_reg_0_7_0_5/DIA0
|
|
SLICE_X6Y45 RAMD32 r u_Axi_CDC/wFifo/ram_reg_0_7_0_5/RAMA/I
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock cpu_clk rise edge) 0.000 0.000 r
|
|
K21 0.000 0.000 r clk (IN)
|
|
net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1
|
|
K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O
|
|
net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll
|
|
PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0)
|
|
-2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0
|
|
net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll
|
|
BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout1_buf/O
|
|
net (fo=6484, routed) 1.076 -0.232 u_Axi_CDC/wFifo/ram_reg_0_7_0_5/WCLK
|
|
SLICE_X6Y45 RAMD32 r u_Axi_CDC/wFifo/ram_reg_0_7_0_5/RAMA/CLK
|
|
clock pessimism -0.220 -0.452
|
|
SLICE_X6Y45 RAMD32 (Hold_ramd32_CLK_I)
|
|
0.147 -0.305 u_Axi_CDC/wFifo/ram_reg_0_7_0_5/RAMA
|
|
-------------------------------------------------------------------
|
|
required time 0.305
|
|
arrival time -0.172
|
|
-------------------------------------------------------------------
|
|
slack 0.133
|
|
|
|
Slack (MET) : 0.134ns (arrival time - required time)
|
|
Source: u_cpu/u_csr/csr_tlbelo1_reg[2]/C
|
|
(rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns})
|
|
Destination: u_cpu/addr_trans/tlb_entry/tlb_plv1_reg_r2_0_31_0_0/DP/I
|
|
(rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns})
|
|
Path Group: cpu_clk
|
|
Path Type: Hold (Min at Fast Process Corner)
|
|
Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns)
|
|
Data Path Delay: 0.264ns (logic 0.141ns (53.394%) route 0.123ns (46.606%))
|
|
Logic Levels: 0
|
|
Clock Path Skew: 0.016ns (DCD - SCD - CPR)
|
|
Destination Clock Delay (DCD): -0.275ns
|
|
Source Clock Delay (SCD): -0.509ns
|
|
Clock Pessimism Removal (CPR): 0.218ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock cpu_clk rise edge) 0.000 0.000 r
|
|
K21 0.000 0.000 r clk (IN)
|
|
net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1
|
|
K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O
|
|
net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll
|
|
PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0)
|
|
-2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0
|
|
net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll
|
|
BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout1_buf/O
|
|
net (fo=6484, routed) 0.754 -0.509 u_cpu/u_csr/cpu_clk
|
|
SLICE_X39Y39 FDRE r u_cpu/u_csr/csr_tlbelo1_reg[2]/C
|
|
------------------------------------------------------------------- -------------------
|
|
SLICE_X39Y39 FDRE (Prop_fdre_C_Q) 0.141 -0.368 r u_cpu/u_csr/csr_tlbelo1_reg[2]/Q
|
|
net (fo=7, routed) 0.123 -0.245 u_cpu/addr_trans/tlb_entry/tlb_plv1_reg_r2_0_31_0_0/D
|
|
SLICE_X40Y39 RAMD32 r u_cpu/addr_trans/tlb_entry/tlb_plv1_reg_r2_0_31_0_0/DP/I
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock cpu_clk rise edge) 0.000 0.000 r
|
|
K21 0.000 0.000 r clk (IN)
|
|
net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1
|
|
K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O
|
|
net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll
|
|
PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0)
|
|
-2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0
|
|
net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll
|
|
BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout1_buf/O
|
|
net (fo=6484, routed) 1.033 -0.275 u_cpu/addr_trans/tlb_entry/tlb_plv1_reg_r2_0_31_0_0/WCLK
|
|
SLICE_X40Y39 RAMD32 r u_cpu/addr_trans/tlb_entry/tlb_plv1_reg_r2_0_31_0_0/DP/CLK
|
|
clock pessimism -0.218 -0.493
|
|
SLICE_X40Y39 RAMD32 (Hold_ramd32_CLK_I)
|
|
0.114 -0.379 u_cpu/addr_trans/tlb_entry/tlb_plv1_reg_r2_0_31_0_0/DP
|
|
-------------------------------------------------------------------
|
|
required time 0.379
|
|
arrival time -0.245
|
|
-------------------------------------------------------------------
|
|
slack 0.134
|
|
|
|
Slack (MET) : 0.135ns (arrival time - required time)
|
|
Source: u_cpu/axi_bridge/araddr_reg[2]/C
|
|
(rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns})
|
|
Destination: u_Axi_CDC/arFifo/ram_reg_0_3_0_5/RAMB/I
|
|
(rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns})
|
|
Path Group: cpu_clk
|
|
Path Type: Hold (Min at Fast Process Corner)
|
|
Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns)
|
|
Data Path Delay: 0.469ns (logic 0.141ns (30.053%) route 0.328ns (69.947%))
|
|
Logic Levels: 0
|
|
Clock Path Skew: 0.188ns (DCD - SCD - CPR)
|
|
Destination Clock Delay (DCD): -0.348ns
|
|
Source Clock Delay (SCD): -0.500ns
|
|
Clock Pessimism Removal (CPR): -0.037ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock cpu_clk rise edge) 0.000 0.000 r
|
|
K21 0.000 0.000 r clk (IN)
|
|
net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1
|
|
K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O
|
|
net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll
|
|
PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0)
|
|
-2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0
|
|
net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll
|
|
BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout1_buf/O
|
|
net (fo=6484, routed) 0.763 -0.500 u_cpu/axi_bridge/cpu_clk
|
|
SLICE_X28Y48 FDRE r u_cpu/axi_bridge/araddr_reg[2]/C
|
|
------------------------------------------------------------------- -------------------
|
|
SLICE_X28Y48 FDRE (Prop_fdre_C_Q) 0.141 -0.359 r u_cpu/axi_bridge/araddr_reg[2]/Q
|
|
net (fo=1, routed) 0.328 -0.031 u_Axi_CDC/arFifo/ram_reg_0_3_0_5/DIB0
|
|
SLICE_X36Y59 RAMD32 r u_Axi_CDC/arFifo/ram_reg_0_3_0_5/RAMB/I
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock cpu_clk rise edge) 0.000 0.000 r
|
|
K21 0.000 0.000 r clk (IN)
|
|
net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1
|
|
K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O
|
|
net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll
|
|
PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0)
|
|
-2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0
|
|
net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll
|
|
BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout1_buf/O
|
|
net (fo=6484, routed) 0.960 -0.348 u_Axi_CDC/arFifo/ram_reg_0_3_0_5/WCLK
|
|
SLICE_X36Y59 RAMD32 r u_Axi_CDC/arFifo/ram_reg_0_3_0_5/RAMB/CLK
|
|
clock pessimism 0.037 -0.311
|
|
SLICE_X36Y59 RAMD32 (Hold_ramd32_CLK_I)
|
|
0.146 -0.165 u_Axi_CDC/arFifo/ram_reg_0_3_0_5/RAMB
|
|
-------------------------------------------------------------------
|
|
required time 0.165
|
|
arrival time -0.031
|
|
-------------------------------------------------------------------
|
|
slack 0.135
|
|
|
|
Slack (MET) : 0.135ns (arrival time - required time)
|
|
Source: u_cpu/axi_bridge/wdata_reg[12]/C
|
|
(rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns})
|
|
Destination: u_Axi_CDC/wFifo/ram_reg_0_7_12_17/RAMA/I
|
|
(rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns})
|
|
Path Group: cpu_clk
|
|
Path Type: Hold (Min at Fast Process Corner)
|
|
Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns)
|
|
Data Path Delay: 0.298ns (logic 0.141ns (47.334%) route 0.157ns (52.666%))
|
|
Logic Levels: 0
|
|
Clock Path Skew: 0.016ns (DCD - SCD - CPR)
|
|
Destination Clock Delay (DCD): -0.232ns
|
|
Source Clock Delay (SCD): -0.468ns
|
|
Clock Pessimism Removal (CPR): 0.220ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock cpu_clk rise edge) 0.000 0.000 r
|
|
K21 0.000 0.000 r clk (IN)
|
|
net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1
|
|
K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O
|
|
net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll
|
|
PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0)
|
|
-2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0
|
|
net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll
|
|
BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout1_buf/O
|
|
net (fo=6484, routed) 0.795 -0.468 u_cpu/axi_bridge/cpu_clk
|
|
SLICE_X5Y45 FDRE r u_cpu/axi_bridge/wdata_reg[12]/C
|
|
------------------------------------------------------------------- -------------------
|
|
SLICE_X5Y45 FDRE (Prop_fdre_C_Q) 0.141 -0.327 r u_cpu/axi_bridge/wdata_reg[12]/Q
|
|
net (fo=1, routed) 0.157 -0.170 u_Axi_CDC/wFifo/ram_reg_0_7_12_17/DIA0
|
|
SLICE_X6Y46 RAMD32 r u_Axi_CDC/wFifo/ram_reg_0_7_12_17/RAMA/I
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock cpu_clk rise edge) 0.000 0.000 r
|
|
K21 0.000 0.000 r clk (IN)
|
|
net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1
|
|
K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O
|
|
net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll
|
|
PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0)
|
|
-2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0
|
|
net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll
|
|
BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout1_buf/O
|
|
net (fo=6484, routed) 1.076 -0.232 u_Axi_CDC/wFifo/ram_reg_0_7_12_17/WCLK
|
|
SLICE_X6Y46 RAMD32 r u_Axi_CDC/wFifo/ram_reg_0_7_12_17/RAMA/CLK
|
|
clock pessimism -0.220 -0.452
|
|
SLICE_X6Y46 RAMD32 (Hold_ramd32_CLK_I)
|
|
0.147 -0.305 u_Axi_CDC/wFifo/ram_reg_0_7_12_17/RAMA
|
|
-------------------------------------------------------------------
|
|
required time 0.305
|
|
arrival time -0.170
|
|
-------------------------------------------------------------------
|
|
slack 0.135
|
|
|
|
Slack (MET) : 0.136ns (arrival time - required time)
|
|
Source: u_cpu/u_csr/csr_tlbelo1_reg[12]/C
|
|
(rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns})
|
|
Destination: u_cpu/addr_trans/tlb_entry/tlb_ppn1_reg_r3_0_31_0_5/RAMC/I
|
|
(rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns})
|
|
Path Group: cpu_clk
|
|
Path Type: Hold (Min at Fast Process Corner)
|
|
Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns)
|
|
Data Path Delay: 0.294ns (logic 0.164ns (55.832%) route 0.130ns (44.168%))
|
|
Logic Levels: 0
|
|
Clock Path Skew: 0.014ns (DCD - SCD - CPR)
|
|
Destination Clock Delay (DCD): -0.312ns
|
|
Source Clock Delay (SCD): -0.543ns
|
|
Clock Pessimism Removal (CPR): 0.217ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock cpu_clk rise edge) 0.000 0.000 r
|
|
K21 0.000 0.000 r clk (IN)
|
|
net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1
|
|
K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O
|
|
net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll
|
|
PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0)
|
|
-2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0
|
|
net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll
|
|
BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout1_buf/O
|
|
net (fo=6484, routed) 0.720 -0.543 u_cpu/u_csr/cpu_clk
|
|
SLICE_X48Y32 FDRE r u_cpu/u_csr/csr_tlbelo1_reg[12]/C
|
|
------------------------------------------------------------------- -------------------
|
|
SLICE_X48Y32 FDRE (Prop_fdre_C_Q) 0.164 -0.379 r u_cpu/u_csr/csr_tlbelo1_reg[12]/Q
|
|
net (fo=4, routed) 0.130 -0.249 u_cpu/addr_trans/tlb_entry/tlb_ppn1_reg_r3_0_31_0_5/DIC0
|
|
SLICE_X46Y32 RAMD32 r u_cpu/addr_trans/tlb_entry/tlb_ppn1_reg_r3_0_31_0_5/RAMC/I
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock cpu_clk rise edge) 0.000 0.000 r
|
|
K21 0.000 0.000 r clk (IN)
|
|
net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1
|
|
K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O
|
|
net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll
|
|
PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0)
|
|
-2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0
|
|
net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll
|
|
BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout1_buf/O
|
|
net (fo=6484, routed) 0.996 -0.312 u_cpu/addr_trans/tlb_entry/tlb_ppn1_reg_r3_0_31_0_5/WCLK
|
|
SLICE_X46Y32 RAMD32 r u_cpu/addr_trans/tlb_entry/tlb_ppn1_reg_r3_0_31_0_5/RAMC/CLK
|
|
clock pessimism -0.217 -0.529
|
|
SLICE_X46Y32 RAMD32 (Hold_ramd32_CLK_I)
|
|
0.144 -0.385 u_cpu/addr_trans/tlb_entry/tlb_ppn1_reg_r3_0_31_0_5/RAMC
|
|
-------------------------------------------------------------------
|
|
required time 0.385
|
|
arrival time -0.249
|
|
-------------------------------------------------------------------
|
|
slack 0.136
|
|
|
|
Slack (MET) : 0.136ns (arrival time - required time)
|
|
Source: u_cpu/axi_bridge/araddr_reg[0]/C
|
|
(rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns})
|
|
Destination: u_Axi_CDC/arFifo/ram_reg_0_3_0_5/RAMA/I
|
|
(rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns})
|
|
Path Group: cpu_clk
|
|
Path Type: Hold (Min at Fast Process Corner)
|
|
Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns)
|
|
Data Path Delay: 0.472ns (logic 0.141ns (29.890%) route 0.331ns (70.110%))
|
|
Logic Levels: 0
|
|
Clock Path Skew: 0.188ns (DCD - SCD - CPR)
|
|
Destination Clock Delay (DCD): -0.348ns
|
|
Source Clock Delay (SCD): -0.500ns
|
|
Clock Pessimism Removal (CPR): -0.037ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock cpu_clk rise edge) 0.000 0.000 r
|
|
K21 0.000 0.000 r clk (IN)
|
|
net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1
|
|
K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O
|
|
net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll
|
|
PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0)
|
|
-2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0
|
|
net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll
|
|
BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout1_buf/O
|
|
net (fo=6484, routed) 0.763 -0.500 u_cpu/axi_bridge/cpu_clk
|
|
SLICE_X29Y48 FDRE r u_cpu/axi_bridge/araddr_reg[0]/C
|
|
------------------------------------------------------------------- -------------------
|
|
SLICE_X29Y48 FDRE (Prop_fdre_C_Q) 0.141 -0.359 r u_cpu/axi_bridge/araddr_reg[0]/Q
|
|
net (fo=1, routed) 0.331 -0.028 u_Axi_CDC/arFifo/ram_reg_0_3_0_5/DIA0
|
|
SLICE_X36Y59 RAMD32 r u_Axi_CDC/arFifo/ram_reg_0_3_0_5/RAMA/I
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock cpu_clk rise edge) 0.000 0.000 r
|
|
K21 0.000 0.000 r clk (IN)
|
|
net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1
|
|
K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O
|
|
net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll
|
|
PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0)
|
|
-2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0
|
|
net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll
|
|
BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout1_buf/O
|
|
net (fo=6484, routed) 0.960 -0.348 u_Axi_CDC/arFifo/ram_reg_0_3_0_5/WCLK
|
|
SLICE_X36Y59 RAMD32 r u_Axi_CDC/arFifo/ram_reg_0_3_0_5/RAMA/CLK
|
|
clock pessimism 0.037 -0.311
|
|
SLICE_X36Y59 RAMD32 (Hold_ramd32_CLK_I)
|
|
0.147 -0.164 u_Axi_CDC/arFifo/ram_reg_0_3_0_5/RAMA
|
|
-------------------------------------------------------------------
|
|
required time 0.164
|
|
arrival time -0.028
|
|
-------------------------------------------------------------------
|
|
slack 0.136
|
|
|
|
Slack (MET) : 0.137ns (arrival time - required time)
|
|
Source: u_cpu/u_csr/csr_tlbelo1_reg[11]/C
|
|
(rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns})
|
|
Destination: u_cpu/addr_trans/tlb_entry/tlb_ppn1_reg_r3_0_31_0_5/RAMB_D1/I
|
|
(rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns})
|
|
Path Group: cpu_clk
|
|
Path Type: Hold (Min at Fast Process Corner)
|
|
Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns)
|
|
Data Path Delay: 0.275ns (logic 0.164ns (59.651%) route 0.111ns (40.349%))
|
|
Logic Levels: 0
|
|
Clock Path Skew: 0.014ns (DCD - SCD - CPR)
|
|
Destination Clock Delay (DCD): -0.312ns
|
|
Source Clock Delay (SCD): -0.543ns
|
|
Clock Pessimism Removal (CPR): 0.217ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock cpu_clk rise edge) 0.000 0.000 r
|
|
K21 0.000 0.000 r clk (IN)
|
|
net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1
|
|
K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O
|
|
net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll
|
|
PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0)
|
|
-2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0
|
|
net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll
|
|
BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout1_buf/O
|
|
net (fo=6484, routed) 0.720 -0.543 u_cpu/u_csr/cpu_clk
|
|
SLICE_X48Y32 FDRE r u_cpu/u_csr/csr_tlbelo1_reg[11]/C
|
|
------------------------------------------------------------------- -------------------
|
|
SLICE_X48Y32 FDRE (Prop_fdre_C_Q) 0.164 -0.379 r u_cpu/u_csr/csr_tlbelo1_reg[11]/Q
|
|
net (fo=4, routed) 0.111 -0.268 u_cpu/addr_trans/tlb_entry/tlb_ppn1_reg_r3_0_31_0_5/DIB1
|
|
SLICE_X46Y32 RAMD32 r u_cpu/addr_trans/tlb_entry/tlb_ppn1_reg_r3_0_31_0_5/RAMB_D1/I
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock cpu_clk rise edge) 0.000 0.000 r
|
|
K21 0.000 0.000 r clk (IN)
|
|
net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1
|
|
K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O
|
|
net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll
|
|
PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0)
|
|
-2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0
|
|
net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll
|
|
BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout1_buf/O
|
|
net (fo=6484, routed) 0.996 -0.312 u_cpu/addr_trans/tlb_entry/tlb_ppn1_reg_r3_0_31_0_5/WCLK
|
|
SLICE_X46Y32 RAMD32 r u_cpu/addr_trans/tlb_entry/tlb_ppn1_reg_r3_0_31_0_5/RAMB_D1/CLK
|
|
clock pessimism -0.217 -0.529
|
|
SLICE_X46Y32 RAMD32 (Hold_ramd32_CLK_I)
|
|
0.124 -0.405 u_cpu/addr_trans/tlb_entry/tlb_ppn1_reg_r3_0_31_0_5/RAMB_D1
|
|
-------------------------------------------------------------------
|
|
required time 0.405
|
|
arrival time -0.268
|
|
-------------------------------------------------------------------
|
|
slack 0.137
|
|
|
|
Slack (MET) : 0.138ns (arrival time - required time)
|
|
Source: u_cpu/axi_bridge/wdata_reg[28]/C
|
|
(rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns})
|
|
Destination: u_Axi_CDC/wFifo/ram_reg_0_7_24_29/RAMC/I
|
|
(rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns})
|
|
Path Group: cpu_clk
|
|
Path Type: Hold (Min at Fast Process Corner)
|
|
Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns)
|
|
Data Path Delay: 0.244ns (logic 0.128ns (52.542%) route 0.116ns (47.458%))
|
|
Logic Levels: 0
|
|
Clock Path Skew: 0.016ns (DCD - SCD - CPR)
|
|
Destination Clock Delay (DCD): -0.229ns
|
|
Source Clock Delay (SCD): -0.465ns
|
|
Clock Pessimism Removal (CPR): 0.220ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock cpu_clk rise edge) 0.000 0.000 r
|
|
K21 0.000 0.000 r clk (IN)
|
|
net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1
|
|
K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O
|
|
net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll
|
|
PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0)
|
|
-2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0
|
|
net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll
|
|
BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout1_buf/O
|
|
net (fo=6484, routed) 0.798 -0.465 u_cpu/axi_bridge/cpu_clk
|
|
SLICE_X3Y48 FDRE r u_cpu/axi_bridge/wdata_reg[28]/C
|
|
------------------------------------------------------------------- -------------------
|
|
SLICE_X3Y48 FDRE (Prop_fdre_C_Q) 0.128 -0.337 r u_cpu/axi_bridge/wdata_reg[28]/Q
|
|
net (fo=1, routed) 0.116 -0.221 u_Axi_CDC/wFifo/ram_reg_0_7_24_29/DIC0
|
|
SLICE_X2Y49 RAMD32 r u_Axi_CDC/wFifo/ram_reg_0_7_24_29/RAMC/I
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock cpu_clk rise edge) 0.000 0.000 r
|
|
K21 0.000 0.000 r clk (IN)
|
|
net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1
|
|
K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O
|
|
net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll
|
|
PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0)
|
|
-2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0
|
|
net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll
|
|
BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout1_buf/O
|
|
net (fo=6484, routed) 1.079 -0.229 u_Axi_CDC/wFifo/ram_reg_0_7_24_29/WCLK
|
|
SLICE_X2Y49 RAMD32 r u_Axi_CDC/wFifo/ram_reg_0_7_24_29/RAMC/CLK
|
|
clock pessimism -0.220 -0.449
|
|
SLICE_X2Y49 RAMD32 (Hold_ramd32_CLK_I)
|
|
0.090 -0.359 u_Axi_CDC/wFifo/ram_reg_0_7_24_29/RAMC
|
|
-------------------------------------------------------------------
|
|
required time 0.359
|
|
arrival time -0.221
|
|
-------------------------------------------------------------------
|
|
slack 0.138
|
|
|
|
Slack (MET) : 0.139ns (arrival time - required time)
|
|
Source: u_cpu/icache/lfsr/r_lfsr_reg[6]/C
|
|
(rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns})
|
|
Destination: u_cpu/icache/lfsr/r_lfsr_reg[7]/D
|
|
(rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns})
|
|
Path Group: cpu_clk
|
|
Path Type: Hold (Min at Fast Process Corner)
|
|
Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns)
|
|
Data Path Delay: 0.210ns (logic 0.141ns (67.004%) route 0.069ns (32.996%))
|
|
Logic Levels: 0
|
|
Clock Path Skew: 0.000ns (DCD - SCD - CPR)
|
|
Destination Clock Delay (DCD): -0.232ns
|
|
Source Clock Delay (SCD): -0.468ns
|
|
Clock Pessimism Removal (CPR): 0.236ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock cpu_clk rise edge) 0.000 0.000 r
|
|
K21 0.000 0.000 r clk (IN)
|
|
net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1
|
|
K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O
|
|
net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll
|
|
PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0)
|
|
-2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0
|
|
net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll
|
|
BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout1_buf/O
|
|
net (fo=6484, routed) 0.795 -0.468 u_cpu/icache/lfsr/cpu_clk
|
|
SLICE_X5Y43 FDRE r u_cpu/icache/lfsr/r_lfsr_reg[6]/C
|
|
------------------------------------------------------------------- -------------------
|
|
SLICE_X5Y43 FDRE (Prop_fdre_C_Q) 0.141 -0.327 r u_cpu/icache/lfsr/r_lfsr_reg[6]/Q
|
|
net (fo=2, routed) 0.069 -0.257 u_cpu/icache/lfsr/Q[0]
|
|
SLICE_X5Y43 FDRE r u_cpu/icache/lfsr/r_lfsr_reg[7]/D
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock cpu_clk rise edge) 0.000 0.000 r
|
|
K21 0.000 0.000 r clk (IN)
|
|
net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1
|
|
K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O
|
|
net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll
|
|
PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0)
|
|
-2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0
|
|
net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll
|
|
BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout1_buf/O
|
|
net (fo=6484, routed) 1.076 -0.232 u_cpu/icache/lfsr/cpu_clk
|
|
SLICE_X5Y43 FDRE r u_cpu/icache/lfsr/r_lfsr_reg[7]/C
|
|
clock pessimism -0.236 -0.468
|
|
SLICE_X5Y43 FDRE (Hold_fdre_C_D) 0.071 -0.397 u_cpu/icache/lfsr/r_lfsr_reg[7]
|
|
-------------------------------------------------------------------
|
|
required time 0.397
|
|
arrival time -0.257
|
|
-------------------------------------------------------------------
|
|
slack 0.139
|
|
|
|
Slack (MET) : 0.140ns (arrival time - required time)
|
|
Source: u_cpu/u_csr/csr_tlbelo0_reg[11]/C
|
|
(rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns})
|
|
Destination: u_cpu/addr_trans/tlb_entry/tlb_ppn0_reg_r1_0_31_0_5/RAMB_D1/I
|
|
(rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns})
|
|
Path Group: cpu_clk
|
|
Path Type: Hold (Min at Fast Process Corner)
|
|
Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns)
|
|
Data Path Delay: 0.280ns (logic 0.141ns (50.435%) route 0.139ns (49.565%))
|
|
Logic Levels: 0
|
|
Clock Path Skew: 0.016ns (DCD - SCD - CPR)
|
|
Destination Clock Delay (DCD): -0.307ns
|
|
Source Clock Delay (SCD): -0.540ns
|
|
Clock Pessimism Removal (CPR): 0.217ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock cpu_clk rise edge) 0.000 0.000 r
|
|
K21 0.000 0.000 r clk (IN)
|
|
net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1
|
|
K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O
|
|
net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll
|
|
PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0)
|
|
-2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0
|
|
net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll
|
|
BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout1_buf/O
|
|
net (fo=6484, routed) 0.723 -0.540 u_cpu/u_csr/cpu_clk
|
|
SLICE_X45Y36 FDRE r u_cpu/u_csr/csr_tlbelo0_reg[11]/C
|
|
------------------------------------------------------------------- -------------------
|
|
SLICE_X45Y36 FDRE (Prop_fdre_C_Q) 0.141 -0.399 r u_cpu/u_csr/csr_tlbelo0_reg[11]/Q
|
|
net (fo=4, routed) 0.139 -0.260 u_cpu/addr_trans/tlb_entry/tlb_ppn0_reg_r1_0_31_0_5/DIB1
|
|
SLICE_X44Y37 RAMD32 r u_cpu/addr_trans/tlb_entry/tlb_ppn0_reg_r1_0_31_0_5/RAMB_D1/I
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock cpu_clk rise edge) 0.000 0.000 r
|
|
K21 0.000 0.000 r clk (IN)
|
|
net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1
|
|
K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O
|
|
net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll
|
|
PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0)
|
|
-2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0
|
|
net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll
|
|
BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout1_buf/O
|
|
net (fo=6484, routed) 1.001 -0.307 u_cpu/addr_trans/tlb_entry/tlb_ppn0_reg_r1_0_31_0_5/WCLK
|
|
SLICE_X44Y37 RAMD32 r u_cpu/addr_trans/tlb_entry/tlb_ppn0_reg_r1_0_31_0_5/RAMB_D1/CLK
|
|
clock pessimism -0.217 -0.524
|
|
SLICE_X44Y37 RAMD32 (Hold_ramd32_CLK_I)
|
|
0.124 -0.400 u_cpu/addr_trans/tlb_entry/tlb_ppn0_reg_r1_0_31_0_5/RAMB_D1
|
|
-------------------------------------------------------------------
|
|
required time 0.400
|
|
arrival time -0.260
|
|
-------------------------------------------------------------------
|
|
slack 0.140
|
|
|
|
Slack (MET) : 0.140ns (arrival time - required time)
|
|
Source: u_cpu/wb_stage/ms_to_ws_bus_r_reg[238]/C
|
|
(rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns})
|
|
Destination: u_cpu/u_csr/lladdr_reg[16]/D
|
|
(rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns})
|
|
Path Group: cpu_clk
|
|
Path Type: Hold (Min at Fast Process Corner)
|
|
Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns)
|
|
Data Path Delay: 0.200ns (logic 0.141ns (70.330%) route 0.059ns (29.670%))
|
|
Logic Levels: 0
|
|
Clock Path Skew: 0.013ns (DCD - SCD - CPR)
|
|
Destination Clock Delay (DCD): -0.268ns
|
|
Source Clock Delay (SCD): -0.502ns
|
|
Clock Pessimism Removal (CPR): 0.221ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock cpu_clk rise edge) 0.000 0.000 r
|
|
K21 0.000 0.000 r clk (IN)
|
|
net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1
|
|
K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O
|
|
net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll
|
|
PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0)
|
|
-2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0
|
|
net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll
|
|
BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout1_buf/O
|
|
net (fo=6484, routed) 0.761 -0.502 u_cpu/wb_stage/cpu_clk
|
|
SLICE_X31Y41 FDRE r u_cpu/wb_stage/ms_to_ws_bus_r_reg[238]/C
|
|
------------------------------------------------------------------- -------------------
|
|
SLICE_X31Y41 FDRE (Prop_fdre_C_Q) 0.141 -0.361 r u_cpu/wb_stage/ms_to_ws_bus_r_reg[238]/Q
|
|
net (fo=1, routed) 0.059 -0.301 u_cpu/u_csr/ws_lladdr[16]
|
|
SLICE_X30Y41 FDRE r u_cpu/u_csr/lladdr_reg[16]/D
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock cpu_clk rise edge) 0.000 0.000 r
|
|
K21 0.000 0.000 r clk (IN)
|
|
net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1
|
|
K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O
|
|
net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll
|
|
PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0)
|
|
-2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0
|
|
net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll
|
|
BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout1_buf/O
|
|
net (fo=6484, routed) 1.040 -0.268 u_cpu/u_csr/cpu_clk
|
|
SLICE_X30Y41 FDRE r u_cpu/u_csr/lladdr_reg[16]/C
|
|
clock pessimism -0.221 -0.489
|
|
SLICE_X30Y41 FDRE (Hold_fdre_C_D) 0.047 -0.442 u_cpu/u_csr/lladdr_reg[16]
|
|
-------------------------------------------------------------------
|
|
required time 0.442
|
|
arrival time -0.301
|
|
-------------------------------------------------------------------
|
|
slack 0.140
|
|
|
|
Slack (MET) : 0.143ns (arrival time - required time)
|
|
Source: u_cpu/wb_stage/ms_to_ws_bus_r_reg[231]/C
|
|
(rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns})
|
|
Destination: u_cpu/u_csr/lladdr_reg[9]/D
|
|
(rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns})
|
|
Path Group: cpu_clk
|
|
Path Type: Hold (Min at Fast Process Corner)
|
|
Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns)
|
|
Data Path Delay: 0.260ns (logic 0.141ns (54.241%) route 0.119ns (45.759%))
|
|
Logic Levels: 0
|
|
Clock Path Skew: 0.039ns (DCD - SCD - CPR)
|
|
Destination Clock Delay (DCD): -0.269ns
|
|
Source Clock Delay (SCD): -0.504ns
|
|
Clock Pessimism Removal (CPR): 0.196ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock cpu_clk rise edge) 0.000 0.000 r
|
|
K21 0.000 0.000 r clk (IN)
|
|
net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1
|
|
K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O
|
|
net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll
|
|
PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0)
|
|
-2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0
|
|
net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll
|
|
BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout1_buf/O
|
|
net (fo=6484, routed) 0.759 -0.504 u_cpu/wb_stage/cpu_clk
|
|
SLICE_X32Y40 FDRE r u_cpu/wb_stage/ms_to_ws_bus_r_reg[231]/C
|
|
------------------------------------------------------------------- -------------------
|
|
SLICE_X32Y40 FDRE (Prop_fdre_C_Q) 0.141 -0.363 r u_cpu/wb_stage/ms_to_ws_bus_r_reg[231]/Q
|
|
net (fo=1, routed) 0.119 -0.244 u_cpu/u_csr/ws_lladdr[9]
|
|
SLICE_X31Y39 FDRE r u_cpu/u_csr/lladdr_reg[9]/D
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock cpu_clk rise edge) 0.000 0.000 r
|
|
K21 0.000 0.000 r clk (IN)
|
|
net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1
|
|
K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O
|
|
net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll
|
|
PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0)
|
|
-2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0
|
|
net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll
|
|
BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout1_buf/O
|
|
net (fo=6484, routed) 1.039 -0.269 u_cpu/u_csr/cpu_clk
|
|
SLICE_X31Y39 FDRE r u_cpu/u_csr/lladdr_reg[9]/C
|
|
clock pessimism -0.196 -0.465
|
|
SLICE_X31Y39 FDRE (Hold_fdre_C_D) 0.078 -0.387 u_cpu/u_csr/lladdr_reg[9]
|
|
-------------------------------------------------------------------
|
|
required time 0.387
|
|
arrival time -0.244
|
|
-------------------------------------------------------------------
|
|
slack 0.143
|
|
|
|
Slack (MET) : 0.148ns (arrival time - required time)
|
|
Source: u_cpu/mem_stage/es_to_ms_bus_r_reg[89]/C
|
|
(rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns})
|
|
Destination: u_cpu/wb_stage/ms_to_ws_bus_r_reg[82]/D
|
|
(rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns})
|
|
Path Group: cpu_clk
|
|
Path Type: Hold (Min at Fast Process Corner)
|
|
Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns)
|
|
Data Path Delay: 0.254ns (logic 0.141ns (55.548%) route 0.113ns (44.452%))
|
|
Logic Levels: 0
|
|
Clock Path Skew: 0.035ns (DCD - SCD - CPR)
|
|
Destination Clock Delay (DCD): -0.282ns
|
|
Source Clock Delay (SCD): -0.513ns
|
|
Clock Pessimism Removal (CPR): 0.196ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock cpu_clk rise edge) 0.000 0.000 r
|
|
K21 0.000 0.000 r clk (IN)
|
|
net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1
|
|
K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O
|
|
net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll
|
|
PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0)
|
|
-2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0
|
|
net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll
|
|
BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout1_buf/O
|
|
net (fo=6484, routed) 0.750 -0.513 u_cpu/mem_stage/cpu_clk
|
|
SLICE_X27Y26 FDRE r u_cpu/mem_stage/es_to_ms_bus_r_reg[89]/C
|
|
------------------------------------------------------------------- -------------------
|
|
SLICE_X27Y26 FDRE (Prop_fdre_C_Q) 0.141 -0.372 r u_cpu/mem_stage/es_to_ms_bus_r_reg[89]/Q
|
|
net (fo=1, routed) 0.113 -0.259 u_cpu/wb_stage/ms_to_ws_bus[46]
|
|
SLICE_X28Y26 FDRE r u_cpu/wb_stage/ms_to_ws_bus_r_reg[82]/D
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock cpu_clk rise edge) 0.000 0.000 r
|
|
K21 0.000 0.000 r clk (IN)
|
|
net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1
|
|
K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O
|
|
net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll
|
|
PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0)
|
|
-2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0
|
|
net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll
|
|
BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout1_buf/O
|
|
net (fo=6484, routed) 1.026 -0.282 u_cpu/wb_stage/cpu_clk
|
|
SLICE_X28Y26 FDRE r u_cpu/wb_stage/ms_to_ws_bus_r_reg[82]/C
|
|
clock pessimism -0.196 -0.478
|
|
SLICE_X28Y26 FDRE (Hold_fdre_C_D) 0.071 -0.407 u_cpu/wb_stage/ms_to_ws_bus_r_reg[82]
|
|
-------------------------------------------------------------------
|
|
required time 0.407
|
|
arrival time -0.259
|
|
-------------------------------------------------------------------
|
|
slack 0.148
|
|
|
|
Slack (MET) : 0.148ns (arrival time - required time)
|
|
Source: u_Axi_CDC/wFifo/pushCC_pushPtr_reg[0]/C
|
|
(rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns})
|
|
Destination: u_Axi_CDC/wFifo/ram_reg_0_7_24_29/RAMA/WADR0
|
|
(rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns})
|
|
Path Group: cpu_clk
|
|
Path Type: Hold (Min at Fast Process Corner)
|
|
Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns)
|
|
Data Path Delay: 0.471ns (logic 0.141ns (29.919%) route 0.330ns (70.081%))
|
|
Logic Levels: 0
|
|
Clock Path Skew: 0.013ns (DCD - SCD - CPR)
|
|
Destination Clock Delay (DCD): -0.229ns
|
|
Source Clock Delay (SCD): -0.465ns
|
|
Clock Pessimism Removal (CPR): 0.223ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock cpu_clk rise edge) 0.000 0.000 r
|
|
K21 0.000 0.000 r clk (IN)
|
|
net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1
|
|
K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O
|
|
net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll
|
|
PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0)
|
|
-2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0
|
|
net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll
|
|
BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout1_buf/O
|
|
net (fo=6484, routed) 0.798 -0.465 u_Axi_CDC/wFifo/cpu_clk
|
|
SLICE_X3Y49 FDCE r u_Axi_CDC/wFifo/pushCC_pushPtr_reg[0]/C
|
|
------------------------------------------------------------------- -------------------
|
|
SLICE_X3Y49 FDCE (Prop_fdce_C_Q) 0.141 -0.324 r u_Axi_CDC/wFifo/pushCC_pushPtr_reg[0]/Q
|
|
net (fo=62, routed) 0.330 0.007 u_Axi_CDC/wFifo/ram_reg_0_7_24_29/ADDRD0
|
|
SLICE_X2Y49 RAMD32 r u_Axi_CDC/wFifo/ram_reg_0_7_24_29/RAMA/WADR0
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock cpu_clk rise edge) 0.000 0.000 r
|
|
K21 0.000 0.000 r clk (IN)
|
|
net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1
|
|
K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O
|
|
net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll
|
|
PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0)
|
|
-2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0
|
|
net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll
|
|
BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout1_buf/O
|
|
net (fo=6484, routed) 1.079 -0.229 u_Axi_CDC/wFifo/ram_reg_0_7_24_29/WCLK
|
|
SLICE_X2Y49 RAMD32 r u_Axi_CDC/wFifo/ram_reg_0_7_24_29/RAMA/CLK
|
|
clock pessimism -0.223 -0.452
|
|
SLICE_X2Y49 RAMD32 (Hold_ramd32_CLK_WADR0)
|
|
0.310 -0.142 u_Axi_CDC/wFifo/ram_reg_0_7_24_29/RAMA
|
|
-------------------------------------------------------------------
|
|
required time 0.142
|
|
arrival time 0.007
|
|
-------------------------------------------------------------------
|
|
slack 0.148
|
|
|
|
Slack (MET) : 0.148ns (arrival time - required time)
|
|
Source: u_Axi_CDC/wFifo/pushCC_pushPtr_reg[0]/C
|
|
(rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns})
|
|
Destination: u_Axi_CDC/wFifo/ram_reg_0_7_24_29/RAMA_D1/WADR0
|
|
(rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns})
|
|
Path Group: cpu_clk
|
|
Path Type: Hold (Min at Fast Process Corner)
|
|
Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns)
|
|
Data Path Delay: 0.471ns (logic 0.141ns (29.919%) route 0.330ns (70.081%))
|
|
Logic Levels: 0
|
|
Clock Path Skew: 0.013ns (DCD - SCD - CPR)
|
|
Destination Clock Delay (DCD): -0.229ns
|
|
Source Clock Delay (SCD): -0.465ns
|
|
Clock Pessimism Removal (CPR): 0.223ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock cpu_clk rise edge) 0.000 0.000 r
|
|
K21 0.000 0.000 r clk (IN)
|
|
net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1
|
|
K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O
|
|
net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll
|
|
PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0)
|
|
-2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0
|
|
net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll
|
|
BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout1_buf/O
|
|
net (fo=6484, routed) 0.798 -0.465 u_Axi_CDC/wFifo/cpu_clk
|
|
SLICE_X3Y49 FDCE r u_Axi_CDC/wFifo/pushCC_pushPtr_reg[0]/C
|
|
------------------------------------------------------------------- -------------------
|
|
SLICE_X3Y49 FDCE (Prop_fdce_C_Q) 0.141 -0.324 r u_Axi_CDC/wFifo/pushCC_pushPtr_reg[0]/Q
|
|
net (fo=62, routed) 0.330 0.007 u_Axi_CDC/wFifo/ram_reg_0_7_24_29/ADDRD0
|
|
SLICE_X2Y49 RAMD32 r u_Axi_CDC/wFifo/ram_reg_0_7_24_29/RAMA_D1/WADR0
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock cpu_clk rise edge) 0.000 0.000 r
|
|
K21 0.000 0.000 r clk (IN)
|
|
net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1
|
|
K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O
|
|
net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll
|
|
PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0)
|
|
-2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0
|
|
net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll
|
|
BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout1_buf/O
|
|
net (fo=6484, routed) 1.079 -0.229 u_Axi_CDC/wFifo/ram_reg_0_7_24_29/WCLK
|
|
SLICE_X2Y49 RAMD32 r u_Axi_CDC/wFifo/ram_reg_0_7_24_29/RAMA_D1/CLK
|
|
clock pessimism -0.223 -0.452
|
|
SLICE_X2Y49 RAMD32 (Hold_ramd32_CLK_WADR0)
|
|
0.310 -0.142 u_Axi_CDC/wFifo/ram_reg_0_7_24_29/RAMA_D1
|
|
-------------------------------------------------------------------
|
|
required time 0.142
|
|
arrival time 0.007
|
|
-------------------------------------------------------------------
|
|
slack 0.148
|
|
|
|
Slack (MET) : 0.148ns (arrival time - required time)
|
|
Source: u_Axi_CDC/wFifo/pushCC_pushPtr_reg[0]/C
|
|
(rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns})
|
|
Destination: u_Axi_CDC/wFifo/ram_reg_0_7_24_29/RAMB/WADR0
|
|
(rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns})
|
|
Path Group: cpu_clk
|
|
Path Type: Hold (Min at Fast Process Corner)
|
|
Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns)
|
|
Data Path Delay: 0.471ns (logic 0.141ns (29.919%) route 0.330ns (70.081%))
|
|
Logic Levels: 0
|
|
Clock Path Skew: 0.013ns (DCD - SCD - CPR)
|
|
Destination Clock Delay (DCD): -0.229ns
|
|
Source Clock Delay (SCD): -0.465ns
|
|
Clock Pessimism Removal (CPR): 0.223ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock cpu_clk rise edge) 0.000 0.000 r
|
|
K21 0.000 0.000 r clk (IN)
|
|
net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1
|
|
K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O
|
|
net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll
|
|
PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0)
|
|
-2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0
|
|
net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll
|
|
BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout1_buf/O
|
|
net (fo=6484, routed) 0.798 -0.465 u_Axi_CDC/wFifo/cpu_clk
|
|
SLICE_X3Y49 FDCE r u_Axi_CDC/wFifo/pushCC_pushPtr_reg[0]/C
|
|
------------------------------------------------------------------- -------------------
|
|
SLICE_X3Y49 FDCE (Prop_fdce_C_Q) 0.141 -0.324 r u_Axi_CDC/wFifo/pushCC_pushPtr_reg[0]/Q
|
|
net (fo=62, routed) 0.330 0.007 u_Axi_CDC/wFifo/ram_reg_0_7_24_29/ADDRD0
|
|
SLICE_X2Y49 RAMD32 r u_Axi_CDC/wFifo/ram_reg_0_7_24_29/RAMB/WADR0
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock cpu_clk rise edge) 0.000 0.000 r
|
|
K21 0.000 0.000 r clk (IN)
|
|
net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1
|
|
K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O
|
|
net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll
|
|
PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0)
|
|
-2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0
|
|
net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll
|
|
BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout1_buf/O
|
|
net (fo=6484, routed) 1.079 -0.229 u_Axi_CDC/wFifo/ram_reg_0_7_24_29/WCLK
|
|
SLICE_X2Y49 RAMD32 r u_Axi_CDC/wFifo/ram_reg_0_7_24_29/RAMB/CLK
|
|
clock pessimism -0.223 -0.452
|
|
SLICE_X2Y49 RAMD32 (Hold_ramd32_CLK_WADR0)
|
|
0.310 -0.142 u_Axi_CDC/wFifo/ram_reg_0_7_24_29/RAMB
|
|
-------------------------------------------------------------------
|
|
required time 0.142
|
|
arrival time 0.007
|
|
-------------------------------------------------------------------
|
|
slack 0.148
|
|
|
|
|
|
|
|
|
|
|
|
Pulse Width Checks
|
|
--------------------------------------------------------------------------------------
|
|
Clock Name: cpu_clk
|
|
Waveform(ns): { 0.000 15.161 }
|
|
Period(ns): 30.323
|
|
Sources: { pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 }
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Check Type Corner Lib Pin Reference Pin Required(ns) Actual(ns) Slack(ns) Location Pin
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Min Period n/a RAMB18E1/CLKARDCLK n/a 2.944 30.323 27.379 RAMB18_X0Y14 u_cpu/dcache/data_ram_way[0].data_ram_bank[0].u/mem_reg_reg/CLKARDCLK
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Min Period n/a RAMB18E1/CLKBWRCLK n/a 2.944 30.323 27.379 RAMB18_X0Y14 u_cpu/dcache/data_ram_way[0].data_ram_bank[0].u/mem_reg_reg/CLKBWRCLK
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Min Period n/a RAMB18E1/CLKARDCLK n/a 2.944 30.323 27.379 RAMB18_X0Y16 u_cpu/dcache/data_ram_way[0].data_ram_bank[1].u/mem_reg_reg/CLKARDCLK
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Min Period n/a RAMB18E1/CLKBWRCLK n/a 2.944 30.323 27.379 RAMB18_X0Y16 u_cpu/dcache/data_ram_way[0].data_ram_bank[1].u/mem_reg_reg/CLKBWRCLK
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Min Period n/a RAMB18E1/CLKARDCLK n/a 2.944 30.323 27.379 RAMB18_X0Y15 u_cpu/dcache/data_ram_way[0].data_ram_bank[2].u/mem_reg_reg/CLKARDCLK
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Min Period n/a RAMB18E1/CLKBWRCLK n/a 2.944 30.323 27.379 RAMB18_X0Y15 u_cpu/dcache/data_ram_way[0].data_ram_bank[2].u/mem_reg_reg/CLKBWRCLK
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Min Period n/a RAMB18E1/CLKARDCLK n/a 2.944 30.323 27.379 RAMB18_X0Y10 u_cpu/dcache/data_ram_way[0].data_ram_bank[3].u/mem_reg_reg/CLKARDCLK
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Min Period n/a RAMB18E1/CLKBWRCLK n/a 2.944 30.323 27.379 RAMB18_X0Y10 u_cpu/dcache/data_ram_way[0].data_ram_bank[3].u/mem_reg_reg/CLKBWRCLK
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Min Period n/a RAMB18E1/CLKARDCLK n/a 2.944 30.323 27.379 RAMB18_X0Y17 u_cpu/dcache/data_ram_way[1].data_ram_bank[0].u/mem_reg_reg/CLKARDCLK
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Min Period n/a RAMB18E1/CLKBWRCLK n/a 2.944 30.323 27.379 RAMB18_X0Y17 u_cpu/dcache/data_ram_way[1].data_ram_bank[0].u/mem_reg_reg/CLKBWRCLK
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Min Period n/a RAMB18E1/CLKARDCLK n/a 2.944 30.323 27.379 RAMB18_X0Y13 u_cpu/dcache/data_ram_way[1].data_ram_bank[1].u/mem_reg_reg/CLKARDCLK
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Min Period n/a RAMB18E1/CLKBWRCLK n/a 2.944 30.323 27.379 RAMB18_X0Y13 u_cpu/dcache/data_ram_way[1].data_ram_bank[1].u/mem_reg_reg/CLKBWRCLK
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Min Period n/a RAMB18E1/CLKARDCLK n/a 2.944 30.323 27.379 RAMB18_X0Y11 u_cpu/dcache/data_ram_way[1].data_ram_bank[2].u/mem_reg_reg/CLKARDCLK
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Min Period n/a RAMB18E1/CLKBWRCLK n/a 2.944 30.323 27.379 RAMB18_X0Y11 u_cpu/dcache/data_ram_way[1].data_ram_bank[2].u/mem_reg_reg/CLKBWRCLK
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Min Period n/a RAMB18E1/CLKARDCLK n/a 2.944 30.323 27.379 RAMB18_X0Y12 u_cpu/dcache/data_ram_way[1].data_ram_bank[3].u/mem_reg_reg/CLKARDCLK
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Min Period n/a RAMB18E1/CLKBWRCLK n/a 2.944 30.323 27.379 RAMB18_X0Y12 u_cpu/dcache/data_ram_way[1].data_ram_bank[3].u/mem_reg_reg/CLKBWRCLK
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Min Period n/a RAMB18E1/CLKARDCLK n/a 2.944 30.323 27.379 RAMB18_X1Y2 u_cpu/icache/data_ram_way[0].data_ram_bank[0].u/mem_reg_reg/CLKARDCLK
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Min Period n/a RAMB18E1/CLKBWRCLK n/a 2.944 30.323 27.379 RAMB18_X1Y2 u_cpu/icache/data_ram_way[0].data_ram_bank[0].u/mem_reg_reg/CLKBWRCLK
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Min Period n/a RAMB18E1/CLKARDCLK n/a 2.944 30.323 27.379 RAMB18_X1Y3 u_cpu/icache/data_ram_way[0].data_ram_bank[1].u/mem_reg_reg/CLKARDCLK
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Min Period n/a RAMB18E1/CLKBWRCLK n/a 2.944 30.323 27.379 RAMB18_X1Y3 u_cpu/icache/data_ram_way[0].data_ram_bank[1].u/mem_reg_reg/CLKBWRCLK
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Min Period n/a RAMB18E1/CLKARDCLK n/a 2.944 30.323 27.379 RAMB18_X1Y0 u_cpu/icache/data_ram_way[0].data_ram_bank[2].u/mem_reg_reg/CLKARDCLK
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Min Period n/a RAMB18E1/CLKBWRCLK n/a 2.944 30.323 27.379 RAMB18_X1Y0 u_cpu/icache/data_ram_way[0].data_ram_bank[2].u/mem_reg_reg/CLKBWRCLK
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Min Period n/a RAMB18E1/CLKARDCLK n/a 2.944 30.323 27.379 RAMB18_X1Y1 u_cpu/icache/data_ram_way[0].data_ram_bank[3].u/mem_reg_reg/CLKARDCLK
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Min Period n/a RAMB18E1/CLKBWRCLK n/a 2.944 30.323 27.379 RAMB18_X1Y1 u_cpu/icache/data_ram_way[0].data_ram_bank[3].u/mem_reg_reg/CLKBWRCLK
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Min Period n/a RAMB18E1/CLKARDCLK n/a 2.944 30.323 27.379 RAMB18_X2Y2 u_cpu/icache/data_ram_way[1].data_ram_bank[0].u/mem_reg_reg/CLKARDCLK
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Min Period n/a RAMB18E1/CLKBWRCLK n/a 2.944 30.323 27.379 RAMB18_X2Y2 u_cpu/icache/data_ram_way[1].data_ram_bank[0].u/mem_reg_reg/CLKBWRCLK
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Min Period n/a RAMB18E1/CLKARDCLK n/a 2.944 30.323 27.379 RAMB18_X2Y1 u_cpu/icache/data_ram_way[1].data_ram_bank[1].u/mem_reg_reg/CLKARDCLK
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Min Period n/a RAMB18E1/CLKBWRCLK n/a 2.944 30.323 27.379 RAMB18_X2Y1 u_cpu/icache/data_ram_way[1].data_ram_bank[1].u/mem_reg_reg/CLKBWRCLK
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Min Period n/a RAMB18E1/CLKARDCLK n/a 2.944 30.323 27.379 RAMB18_X2Y3 u_cpu/icache/data_ram_way[1].data_ram_bank[2].u/mem_reg_reg/CLKARDCLK
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Min Period n/a RAMB18E1/CLKBWRCLK n/a 2.944 30.323 27.379 RAMB18_X2Y3 u_cpu/icache/data_ram_way[1].data_ram_bank[2].u/mem_reg_reg/CLKBWRCLK
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Min Period n/a RAMB18E1/CLKARDCLK n/a 2.944 30.323 27.379 RAMB18_X2Y0 u_cpu/icache/data_ram_way[1].data_ram_bank[3].u/mem_reg_reg/CLKARDCLK
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Min Period n/a RAMB18E1/CLKBWRCLK n/a 2.944 30.323 27.379 RAMB18_X2Y0 u_cpu/icache/data_ram_way[1].data_ram_bank[3].u/mem_reg_reg/CLKBWRCLK
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Min Period n/a RAMB18E1/CLKARDCLK n/a 2.576 30.323 27.747 RAMB18_X1Y18 u_cpu/dcache/tagv_ram_way[0].u/mem_reg_reg/CLKARDCLK
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Min Period n/a RAMB18E1/CLKBWRCLK n/a 2.576 30.323 27.747 RAMB18_X1Y18 u_cpu/dcache/tagv_ram_way[0].u/mem_reg_reg/CLKBWRCLK
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Min Period n/a RAMB18E1/CLKARDCLK n/a 2.576 30.323 27.747 RAMB18_X1Y16 u_cpu/dcache/tagv_ram_way[1].u/mem_reg_reg/CLKARDCLK
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Min Period n/a RAMB18E1/CLKBWRCLK n/a 2.576 30.323 27.747 RAMB18_X1Y16 u_cpu/dcache/tagv_ram_way[1].u/mem_reg_reg/CLKBWRCLK
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Min Period n/a RAMB18E1/CLKARDCLK n/a 2.576 30.323 27.747 RAMB18_X2Y12 u_cpu/icache/tagv_ram_way[0].u/mem_reg_reg/CLKARDCLK
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Min Period n/a RAMB18E1/CLKBWRCLK n/a 2.576 30.323 27.747 RAMB18_X2Y12 u_cpu/icache/tagv_ram_way[0].u/mem_reg_reg/CLKBWRCLK
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Min Period n/a RAMB18E1/CLKARDCLK n/a 2.576 30.323 27.747 RAMB18_X2Y13 u_cpu/icache/tagv_ram_way[1].u/mem_reg_reg/CLKARDCLK
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Min Period n/a RAMB18E1/CLKBWRCLK n/a 2.576 30.323 27.747 RAMB18_X2Y13 u_cpu/icache/tagv_ram_way[1].u/mem_reg_reg/CLKBWRCLK
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Min Period n/a BUFG/I n/a 2.155 30.323 28.167 BUFGCTRL_X0Y18 pll_clk.u_clk_pll/inst/clkout1_buf/I
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Min Period n/a PLLE2_ADV/CLKOUT0 n/a 1.249 30.323 29.074 PLLE2_ADV_X0Y3 pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0
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Min Period n/a FDCE/C n/a 1.000 30.323 29.323 SLICE_X0Y48 pll_clk.u_rst_cpu/delay_reg[0]/C
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Min Period n/a FDCE/C n/a 1.000 30.323 29.323 SLICE_X0Y48 pll_clk.u_rst_cpu/delay_reg[1]/C
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Min Period n/a FDRE/C n/a 1.000 30.323 29.323 SLICE_X46Y5 u_cpu/btb/btb_untaken_entry_r_reg[0]/C
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Min Period n/a FDRE/C n/a 1.000 30.323 29.323 SLICE_X46Y6 u_cpu/btb/btb_untaken_entry_r_reg[10]/C
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Min Period n/a FDRE/C n/a 1.000 30.323 29.323 SLICE_X48Y8 u_cpu/btb/btb_untaken_entry_r_reg[11]/C
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Min Period n/a FDRE/C n/a 1.000 30.323 29.323 SLICE_X48Y4 u_cpu/btb/btb_untaken_entry_r_reg[12]/C
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Min Period n/a FDRE/C n/a 1.000 30.323 29.323 SLICE_X50Y5 u_cpu/btb/btb_untaken_entry_r_reg[13]/C
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Min Period n/a FDRE/C n/a 1.000 30.323 29.323 SLICE_X49Y9 u_cpu/btb/btb_untaken_entry_r_reg[14]/C
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Max Period n/a PLLE2_ADV/CLKOUT0 n/a 160.000 30.323 129.677 PLLE2_ADV_X0Y3 pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0
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Low Pulse Width Fast RAMD32/CLK n/a 1.250 15.161 13.911 SLICE_X40Y12 u_cpu/btb/btb_target_reg_0_31_12_13/RAMA/CLK
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Low Pulse Width Fast RAMD32/CLK n/a 1.250 15.161 13.911 SLICE_X40Y12 u_cpu/btb/btb_target_reg_0_31_12_13/RAMA_D1/CLK
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Low Pulse Width Fast RAMD32/CLK n/a 1.250 15.161 13.911 SLICE_X40Y12 u_cpu/btb/btb_target_reg_0_31_12_13/RAMB/CLK
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Low Pulse Width Fast RAMD32/CLK n/a 1.250 15.161 13.911 SLICE_X40Y12 u_cpu/btb/btb_target_reg_0_31_12_13/RAMB_D1/CLK
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Low Pulse Width Fast RAMD32/CLK n/a 1.250 15.161 13.911 SLICE_X40Y12 u_cpu/btb/btb_target_reg_0_31_12_13/RAMC/CLK
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Low Pulse Width Fast RAMD32/CLK n/a 1.250 15.161 13.911 SLICE_X40Y12 u_cpu/btb/btb_target_reg_0_31_12_13/RAMC_D1/CLK
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Low Pulse Width Fast RAMS32/CLK n/a 1.250 15.161 13.911 SLICE_X40Y12 u_cpu/btb/btb_target_reg_0_31_12_13/RAMD/CLK
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Low Pulse Width Fast RAMS32/CLK n/a 1.250 15.161 13.911 SLICE_X40Y12 u_cpu/btb/btb_target_reg_0_31_12_13/RAMD_D1/CLK
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Low Pulse Width Slow RAMD32/CLK n/a 1.250 15.161 13.911 SLICE_X36Y13 u_cpu/btb/btb_target_reg_0_31_14_15/RAMA/CLK
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Low Pulse Width Slow RAMD32/CLK n/a 1.250 15.161 13.911 SLICE_X36Y13 u_cpu/btb/btb_target_reg_0_31_14_15/RAMA_D1/CLK
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Low Pulse Width Slow RAMD32/CLK n/a 1.250 15.161 13.911 SLICE_X36Y13 u_cpu/btb/btb_target_reg_0_31_14_15/RAMB/CLK
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Low Pulse Width Slow RAMD32/CLK n/a 1.250 15.161 13.911 SLICE_X36Y13 u_cpu/btb/btb_target_reg_0_31_14_15/RAMB_D1/CLK
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Low Pulse Width Slow RAMD32/CLK n/a 1.250 15.161 13.911 SLICE_X36Y13 u_cpu/btb/btb_target_reg_0_31_14_15/RAMC/CLK
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Low Pulse Width Slow RAMD32/CLK n/a 1.250 15.161 13.911 SLICE_X36Y13 u_cpu/btb/btb_target_reg_0_31_14_15/RAMC_D1/CLK
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Low Pulse Width Slow RAMS32/CLK n/a 1.250 15.161 13.911 SLICE_X36Y13 u_cpu/btb/btb_target_reg_0_31_14_15/RAMD/CLK
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Low Pulse Width Slow RAMS32/CLK n/a 1.250 15.161 13.911 SLICE_X36Y13 u_cpu/btb/btb_target_reg_0_31_14_15/RAMD_D1/CLK
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Low Pulse Width Slow RAMD32/CLK n/a 1.250 15.161 13.911 SLICE_X36Y12 u_cpu/btb/btb_target_reg_0_31_20_21/RAMA/CLK
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Low Pulse Width Fast RAMD32/CLK n/a 1.250 15.161 13.911 SLICE_X36Y12 u_cpu/btb/btb_target_reg_0_31_20_21/RAMA/CLK
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Low Pulse Width Slow RAMD32/CLK n/a 1.250 15.161 13.911 SLICE_X36Y12 u_cpu/btb/btb_target_reg_0_31_20_21/RAMA_D1/CLK
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Low Pulse Width Fast RAMD32/CLK n/a 1.250 15.161 13.911 SLICE_X36Y12 u_cpu/btb/btb_target_reg_0_31_20_21/RAMA_D1/CLK
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Low Pulse Width Slow RAMD32/CLK n/a 1.250 15.161 13.911 SLICE_X36Y12 u_cpu/btb/btb_target_reg_0_31_20_21/RAMB/CLK
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Low Pulse Width Fast RAMD32/CLK n/a 1.250 15.161 13.911 SLICE_X36Y12 u_cpu/btb/btb_target_reg_0_31_20_21/RAMB/CLK
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Low Pulse Width Slow RAMD32/CLK n/a 1.250 15.161 13.911 SLICE_X36Y12 u_cpu/btb/btb_target_reg_0_31_20_21/RAMB_D1/CLK
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Low Pulse Width Fast RAMD32/CLK n/a 1.250 15.161 13.911 SLICE_X36Y12 u_cpu/btb/btb_target_reg_0_31_20_21/RAMB_D1/CLK
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Low Pulse Width Slow RAMD32/CLK n/a 1.250 15.161 13.911 SLICE_X36Y12 u_cpu/btb/btb_target_reg_0_31_20_21/RAMC/CLK
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Low Pulse Width Fast RAMD32/CLK n/a 1.250 15.161 13.911 SLICE_X36Y12 u_cpu/btb/btb_target_reg_0_31_20_21/RAMC/CLK
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Low Pulse Width Slow RAMD32/CLK n/a 1.250 15.161 13.911 SLICE_X36Y12 u_cpu/btb/btb_target_reg_0_31_20_21/RAMC_D1/CLK
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Low Pulse Width Fast RAMD32/CLK n/a 1.250 15.161 13.911 SLICE_X36Y12 u_cpu/btb/btb_target_reg_0_31_20_21/RAMC_D1/CLK
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Low Pulse Width Slow RAMS32/CLK n/a 1.250 15.161 13.911 SLICE_X36Y12 u_cpu/btb/btb_target_reg_0_31_20_21/RAMD/CLK
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Low Pulse Width Fast RAMS32/CLK n/a 1.250 15.161 13.911 SLICE_X36Y12 u_cpu/btb/btb_target_reg_0_31_20_21/RAMD/CLK
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Low Pulse Width Slow RAMS32/CLK n/a 1.250 15.161 13.911 SLICE_X36Y12 u_cpu/btb/btb_target_reg_0_31_20_21/RAMD_D1/CLK
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Low Pulse Width Fast RAMS32/CLK n/a 1.250 15.161 13.911 SLICE_X36Y12 u_cpu/btb/btb_target_reg_0_31_20_21/RAMD_D1/CLK
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Low Pulse Width Slow RAMD32/CLK n/a 1.250 15.161 13.911 SLICE_X40Y15 u_cpu/btb/ras_reg_0_7_24_29/RAMA/CLK
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Low Pulse Width Slow RAMD32/CLK n/a 1.250 15.161 13.911 SLICE_X40Y15 u_cpu/btb/ras_reg_0_7_24_29/RAMA_D1/CLK
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Low Pulse Width Slow RAMD32/CLK n/a 1.250 15.161 13.911 SLICE_X40Y15 u_cpu/btb/ras_reg_0_7_24_29/RAMB/CLK
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Low Pulse Width Slow RAMD32/CLK n/a 1.250 15.161 13.911 SLICE_X40Y15 u_cpu/btb/ras_reg_0_7_24_29/RAMB_D1/CLK
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Low Pulse Width Slow RAMD32/CLK n/a 1.250 15.161 13.911 SLICE_X40Y15 u_cpu/btb/ras_reg_0_7_24_29/RAMC/CLK
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Low Pulse Width Slow RAMD32/CLK n/a 1.250 15.161 13.911 SLICE_X40Y15 u_cpu/btb/ras_reg_0_7_24_29/RAMC_D1/CLK
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Low Pulse Width Slow RAMS32/CLK n/a 1.250 15.161 13.911 SLICE_X40Y15 u_cpu/btb/ras_reg_0_7_24_29/RAMD/CLK
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Low Pulse Width Slow RAMS32/CLK n/a 1.250 15.161 13.911 SLICE_X40Y15 u_cpu/btb/ras_reg_0_7_24_29/RAMD_D1/CLK
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Low Pulse Width Slow RAMD32/CLK n/a 1.250 15.161 13.911 SLICE_X20Y60 u_Axi_CDC/arFifo/ram_reg_0_3_24_29/RAMA/CLK
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Low Pulse Width Slow RAMD32/CLK n/a 1.250 15.161 13.911 SLICE_X20Y60 u_Axi_CDC/arFifo/ram_reg_0_3_24_29/RAMA_D1/CLK
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Low Pulse Width Slow RAMD32/CLK n/a 1.250 15.161 13.911 SLICE_X20Y60 u_Axi_CDC/arFifo/ram_reg_0_3_24_29/RAMB/CLK
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Low Pulse Width Slow RAMD32/CLK n/a 1.250 15.161 13.911 SLICE_X20Y60 u_Axi_CDC/arFifo/ram_reg_0_3_24_29/RAMB_D1/CLK
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Low Pulse Width Slow RAMD32/CLK n/a 1.250 15.161 13.911 SLICE_X20Y60 u_Axi_CDC/arFifo/ram_reg_0_3_24_29/RAMC/CLK
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Low Pulse Width Slow RAMD32/CLK n/a 1.250 15.161 13.911 SLICE_X20Y60 u_Axi_CDC/arFifo/ram_reg_0_3_24_29/RAMC_D1/CLK
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Low Pulse Width Slow RAMS32/CLK n/a 1.250 15.161 13.911 SLICE_X20Y60 u_Axi_CDC/arFifo/ram_reg_0_3_24_29/RAMD/CLK
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Low Pulse Width Slow RAMS32/CLK n/a 1.250 15.161 13.911 SLICE_X20Y60 u_Axi_CDC/arFifo/ram_reg_0_3_24_29/RAMD_D1/CLK
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Low Pulse Width Slow RAMD32/CLK n/a 1.250 15.161 13.911 SLICE_X20Y58 u_Axi_CDC/awFifo/ram_reg_0_3_0_5/RAMA/CLK
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Low Pulse Width Slow RAMD32/CLK n/a 1.250 15.161 13.911 SLICE_X20Y58 u_Axi_CDC/awFifo/ram_reg_0_3_0_5/RAMA_D1/CLK
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High Pulse Width Fast RAMD32/CLK n/a 1.250 15.161 13.911 SLICE_X42Y10 u_cpu/btb/btb_target_reg_0_31_10_11/RAMA/CLK
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High Pulse Width Fast RAMD32/CLK n/a 1.250 15.161 13.911 SLICE_X42Y10 u_cpu/btb/btb_target_reg_0_31_10_11/RAMA_D1/CLK
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High Pulse Width Fast RAMD32/CLK n/a 1.250 15.161 13.911 SLICE_X42Y10 u_cpu/btb/btb_target_reg_0_31_10_11/RAMB/CLK
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High Pulse Width Fast RAMD32/CLK n/a 1.250 15.161 13.911 SLICE_X42Y10 u_cpu/btb/btb_target_reg_0_31_10_11/RAMB_D1/CLK
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High Pulse Width Fast RAMD32/CLK n/a 1.250 15.161 13.911 SLICE_X42Y10 u_cpu/btb/btb_target_reg_0_31_10_11/RAMC/CLK
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High Pulse Width Fast RAMD32/CLK n/a 1.250 15.161 13.911 SLICE_X42Y10 u_cpu/btb/btb_target_reg_0_31_10_11/RAMC_D1/CLK
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High Pulse Width Fast RAMS32/CLK n/a 1.250 15.161 13.911 SLICE_X42Y10 u_cpu/btb/btb_target_reg_0_31_10_11/RAMD/CLK
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High Pulse Width Fast RAMS32/CLK n/a 1.250 15.161 13.911 SLICE_X42Y10 u_cpu/btb/btb_target_reg_0_31_10_11/RAMD_D1/CLK
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High Pulse Width Fast RAMD32/CLK n/a 1.250 15.161 13.911 SLICE_X36Y13 u_cpu/btb/btb_target_reg_0_31_14_15/RAMA/CLK
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High Pulse Width Fast RAMD32/CLK n/a 1.250 15.161 13.911 SLICE_X36Y13 u_cpu/btb/btb_target_reg_0_31_14_15/RAMA_D1/CLK
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High Pulse Width Fast RAMD32/CLK n/a 1.250 15.161 13.911 SLICE_X36Y13 u_cpu/btb/btb_target_reg_0_31_14_15/RAMB/CLK
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High Pulse Width Fast RAMD32/CLK n/a 1.250 15.161 13.911 SLICE_X36Y13 u_cpu/btb/btb_target_reg_0_31_14_15/RAMB_D1/CLK
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High Pulse Width Fast RAMD32/CLK n/a 1.250 15.161 13.911 SLICE_X36Y13 u_cpu/btb/btb_target_reg_0_31_14_15/RAMC/CLK
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High Pulse Width Fast RAMD32/CLK n/a 1.250 15.161 13.911 SLICE_X36Y13 u_cpu/btb/btb_target_reg_0_31_14_15/RAMC_D1/CLK
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High Pulse Width Fast RAMS32/CLK n/a 1.250 15.161 13.911 SLICE_X36Y13 u_cpu/btb/btb_target_reg_0_31_14_15/RAMD/CLK
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High Pulse Width Fast RAMS32/CLK n/a 1.250 15.161 13.911 SLICE_X36Y13 u_cpu/btb/btb_target_reg_0_31_14_15/RAMD_D1/CLK
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High Pulse Width Fast RAMD32/CLK n/a 1.250 15.161 13.911 SLICE_X40Y9 u_cpu/btb/btb_target_reg_0_31_16_17/RAMA/CLK
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High Pulse Width Fast RAMD32/CLK n/a 1.250 15.161 13.911 SLICE_X40Y9 u_cpu/btb/btb_target_reg_0_31_16_17/RAMA_D1/CLK
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High Pulse Width Fast RAMD32/CLK n/a 1.250 15.161 13.911 SLICE_X40Y9 u_cpu/btb/btb_target_reg_0_31_16_17/RAMB/CLK
|
|
High Pulse Width Fast RAMD32/CLK n/a 1.250 15.161 13.911 SLICE_X40Y9 u_cpu/btb/btb_target_reg_0_31_16_17/RAMB_D1/CLK
|
|
High Pulse Width Fast RAMD32/CLK n/a 1.250 15.161 13.911 SLICE_X40Y9 u_cpu/btb/btb_target_reg_0_31_16_17/RAMC/CLK
|
|
High Pulse Width Fast RAMD32/CLK n/a 1.250 15.161 13.911 SLICE_X40Y9 u_cpu/btb/btb_target_reg_0_31_16_17/RAMC_D1/CLK
|
|
High Pulse Width Fast RAMS32/CLK n/a 1.250 15.161 13.911 SLICE_X40Y9 u_cpu/btb/btb_target_reg_0_31_16_17/RAMD/CLK
|
|
High Pulse Width Fast RAMS32/CLK n/a 1.250 15.161 13.911 SLICE_X40Y9 u_cpu/btb/btb_target_reg_0_31_16_17/RAMD_D1/CLK
|
|
High Pulse Width Fast RAMD32/CLK n/a 1.250 15.161 13.911 SLICE_X40Y8 u_cpu/btb/btb_target_reg_0_31_18_19/RAMA/CLK
|
|
High Pulse Width Fast RAMD32/CLK n/a 1.250 15.161 13.911 SLICE_X40Y8 u_cpu/btb/btb_target_reg_0_31_18_19/RAMA_D1/CLK
|
|
High Pulse Width Fast RAMD32/CLK n/a 1.250 15.161 13.911 SLICE_X40Y8 u_cpu/btb/btb_target_reg_0_31_18_19/RAMB/CLK
|
|
High Pulse Width Fast RAMD32/CLK n/a 1.250 15.161 13.911 SLICE_X40Y8 u_cpu/btb/btb_target_reg_0_31_18_19/RAMB_D1/CLK
|
|
High Pulse Width Fast RAMD32/CLK n/a 1.250 15.161 13.911 SLICE_X40Y8 u_cpu/btb/btb_target_reg_0_31_18_19/RAMC/CLK
|
|
High Pulse Width Fast RAMD32/CLK n/a 1.250 15.161 13.911 SLICE_X40Y8 u_cpu/btb/btb_target_reg_0_31_18_19/RAMC_D1/CLK
|
|
High Pulse Width Fast RAMS32/CLK n/a 1.250 15.161 13.911 SLICE_X40Y8 u_cpu/btb/btb_target_reg_0_31_18_19/RAMD/CLK
|
|
High Pulse Width Fast RAMS32/CLK n/a 1.250 15.161 13.911 SLICE_X40Y8 u_cpu/btb/btb_target_reg_0_31_18_19/RAMD_D1/CLK
|
|
High Pulse Width Fast RAMD32/CLK n/a 1.250 15.161 13.911 SLICE_X36Y12 u_cpu/btb/btb_target_reg_0_31_20_21/RAMA/CLK
|
|
High Pulse Width Fast RAMD32/CLK n/a 1.250 15.161 13.911 SLICE_X36Y12 u_cpu/btb/btb_target_reg_0_31_20_21/RAMA_D1/CLK
|
|
High Pulse Width Fast RAMD32/CLK n/a 1.250 15.161 13.911 SLICE_X36Y12 u_cpu/btb/btb_target_reg_0_31_20_21/RAMB/CLK
|
|
High Pulse Width Fast RAMD32/CLK n/a 1.250 15.161 13.911 SLICE_X36Y12 u_cpu/btb/btb_target_reg_0_31_20_21/RAMB_D1/CLK
|
|
High Pulse Width Fast RAMD32/CLK n/a 1.250 15.161 13.911 SLICE_X36Y12 u_cpu/btb/btb_target_reg_0_31_20_21/RAMC/CLK
|
|
High Pulse Width Fast RAMD32/CLK n/a 1.250 15.161 13.911 SLICE_X36Y12 u_cpu/btb/btb_target_reg_0_31_20_21/RAMC_D1/CLK
|
|
High Pulse Width Fast RAMS32/CLK n/a 1.250 15.161 13.911 SLICE_X36Y12 u_cpu/btb/btb_target_reg_0_31_20_21/RAMD/CLK
|
|
High Pulse Width Fast RAMS32/CLK n/a 1.250 15.161 13.911 SLICE_X36Y12 u_cpu/btb/btb_target_reg_0_31_20_21/RAMD_D1/CLK
|
|
High Pulse Width Fast RAMD32/CLK n/a 1.250 15.161 13.911 SLICE_X36Y10 u_cpu/btb/btb_target_reg_0_31_24_25/RAMA/CLK
|
|
High Pulse Width Fast RAMD32/CLK n/a 1.250 15.161 13.911 SLICE_X36Y10 u_cpu/btb/btb_target_reg_0_31_24_25/RAMA_D1/CLK
|
|
High Pulse Width Fast RAMD32/CLK n/a 1.250 15.161 13.911 SLICE_X36Y10 u_cpu/btb/btb_target_reg_0_31_24_25/RAMB/CLK
|
|
High Pulse Width Fast RAMD32/CLK n/a 1.250 15.161 13.911 SLICE_X36Y10 u_cpu/btb/btb_target_reg_0_31_24_25/RAMB_D1/CLK
|
|
High Pulse Width Fast RAMD32/CLK n/a 1.250 15.161 13.911 SLICE_X36Y10 u_cpu/btb/btb_target_reg_0_31_24_25/RAMC/CLK
|
|
High Pulse Width Fast RAMD32/CLK n/a 1.250 15.161 13.911 SLICE_X36Y10 u_cpu/btb/btb_target_reg_0_31_24_25/RAMC_D1/CLK
|
|
High Pulse Width Fast RAMS32/CLK n/a 1.250 15.161 13.911 SLICE_X36Y10 u_cpu/btb/btb_target_reg_0_31_24_25/RAMD/CLK
|
|
High Pulse Width Fast RAMS32/CLK n/a 1.250 15.161 13.911 SLICE_X36Y10 u_cpu/btb/btb_target_reg_0_31_24_25/RAMD_D1/CLK
|
|
High Pulse Width Fast RAMD32/CLK n/a 1.250 15.161 13.911 SLICE_X42Y11 u_cpu/btb/btb_target_reg_0_31_26_27/RAMA/CLK
|
|
High Pulse Width Fast RAMD32/CLK n/a 1.250 15.161 13.911 SLICE_X42Y11 u_cpu/btb/btb_target_reg_0_31_26_27/RAMA_D1/CLK
|
|
|
|
|
|
|
|
---------------------------------------------------------------------------------------------------
|
|
From Clock: mlkem_clk_clk_pll
|
|
To Clock: mlkem_clk_clk_pll
|
|
|
|
Setup : NA Failing Endpoints, Worst Slack NA , Total Violation NA
|
|
Hold : 0 Failing Endpoints, Worst Slack 0.058ns, Total Violation 0.000ns
|
|
PW : 0 Failing Endpoints, Worst Slack 18.750ns, Total Violation 0.000ns
|
|
---------------------------------------------------------------------------------------------------
|
|
|
|
|
|
Min Delay Paths
|
|
--------------------------------------------------------------------------------------
|
|
Slack (MET) : 0.058ns (arrival time - required time)
|
|
Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/valid_sr_reg[5]_u_fft_mlkem_axi_slave_u_mlkem_axi_slave_u_mlkem_u_ntt_u_scl_valid_sr_reg_c_3/C
|
|
(rising edge-triggered cell FDRE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns})
|
|
Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/valid_sr_reg[6]/D
|
|
(rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns})
|
|
Path Group: mlkem_clk_clk_pll
|
|
Path Type: Hold (Min at Fast Process Corner)
|
|
Requirement: 0.000ns (mlkem_clk_clk_pll rise@0.000ns - mlkem_clk_clk_pll rise@0.000ns)
|
|
Data Path Delay: 0.444ns (logic 0.247ns (55.601%) route 0.197ns (44.399%))
|
|
Logic Levels: 1 (LUT2=1)
|
|
Clock Path Skew: 0.265ns (DCD - SCD - CPR)
|
|
Destination Clock Delay (DCD): -0.475ns
|
|
Source Clock Delay (SCD): -0.695ns
|
|
Clock Pessimism Removal (CPR): -0.045ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock mlkem_clk_clk_pll rise edge)
|
|
0.000 0.000 r
|
|
K21 0.000 0.000 r clk (IN)
|
|
net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1
|
|
K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O
|
|
net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll
|
|
PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2)
|
|
-2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2
|
|
net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll
|
|
BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout3_buf/O
|
|
net (fo=26129, routed) 0.568 -0.695 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/mlkem_clk
|
|
SLICE_X84Y144 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/valid_sr_reg[5]_u_fft_mlkem_axi_slave_u_mlkem_axi_slave_u_mlkem_u_ntt_u_scl_valid_sr_reg_c_3/C
|
|
------------------------------------------------------------------- -------------------
|
|
SLICE_X84Y144 FDRE (Prop_fdre_C_Q) 0.148 -0.547 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/valid_sr_reg[5]_u_fft_mlkem_axi_slave_u_mlkem_axi_slave_u_mlkem_u_ntt_u_scl_valid_sr_reg_c_3/Q
|
|
net (fo=1, routed) 0.197 -0.350 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/valid_sr_reg[5]_u_fft_mlkem_axi_slave_u_mlkem_axi_slave_u_mlkem_u_ntt_u_scl_valid_sr_reg_c_3_n_0
|
|
SLICE_X84Y151 LUT2 (Prop_lut2_I0_O) 0.099 -0.251 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/valid_sr_reg_gate/O
|
|
net (fo=1, routed) 0.000 -0.251 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/valid_sr_reg_gate_n_0
|
|
SLICE_X84Y151 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/valid_sr_reg[6]/D
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock mlkem_clk_clk_pll rise edge)
|
|
0.000 0.000 r
|
|
K21 0.000 0.000 r clk (IN)
|
|
net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1
|
|
K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O
|
|
net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll
|
|
PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2)
|
|
-2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2
|
|
net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll
|
|
BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout3_buf/O
|
|
net (fo=26129, routed) 0.833 -0.475 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/mlkem_clk
|
|
SLICE_X84Y151 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/valid_sr_reg[6]/C
|
|
clock pessimism 0.045 -0.430
|
|
SLICE_X84Y151 FDCE (Hold_fdce_C_D) 0.121 -0.309 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/valid_sr_reg[6]
|
|
-------------------------------------------------------------------
|
|
required time 0.309
|
|
arrival time -0.251
|
|
-------------------------------------------------------------------
|
|
slack 0.058
|
|
|
|
Slack (MET) : 0.077ns (arrival time - required time)
|
|
Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/wb_b_data_r_reg[2]/C
|
|
(rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns})
|
|
Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/cr_reg[241][2]/D
|
|
(rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns})
|
|
Path Group: mlkem_clk_clk_pll
|
|
Path Type: Hold (Min at Fast Process Corner)
|
|
Requirement: 0.000ns (mlkem_clk_clk_pll rise@0.000ns - mlkem_clk_clk_pll rise@0.000ns)
|
|
Data Path Delay: 0.446ns (logic 0.186ns (41.734%) route 0.260ns (58.266%))
|
|
Logic Levels: 1 (LUT6=1)
|
|
Clock Path Skew: 0.277ns (DCD - SCD - CPR)
|
|
Destination Clock Delay (DCD): -0.469ns
|
|
Source Clock Delay (SCD): -0.701ns
|
|
Clock Pessimism Removal (CPR): -0.045ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock mlkem_clk_clk_pll rise edge)
|
|
0.000 0.000 r
|
|
K21 0.000 0.000 r clk (IN)
|
|
net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1
|
|
K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O
|
|
net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll
|
|
PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2)
|
|
-2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2
|
|
net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll
|
|
BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout3_buf/O
|
|
net (fo=26129, routed) 0.562 -0.701 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/mlkem_clk
|
|
SLICE_X86Y154 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/wb_b_data_r_reg[2]/C
|
|
------------------------------------------------------------------- -------------------
|
|
SLICE_X86Y154 FDCE (Prop_fdce_C_Q) 0.141 -0.560 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/wb_b_data_r_reg[2]/Q
|
|
net (fo=234, routed) 0.260 -0.300 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/wb_b_data_r[2]
|
|
SLICE_X86Y148 LUT6 (Prop_lut6_I0_O) 0.045 -0.255 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/cr[241][2]_i_1/O
|
|
net (fo=1, routed) 0.000 -0.255 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/cr[241][2]_i_1_n_0
|
|
SLICE_X86Y148 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/cr_reg[241][2]/D
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock mlkem_clk_clk_pll rise edge)
|
|
0.000 0.000 r
|
|
K21 0.000 0.000 r clk (IN)
|
|
net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1
|
|
K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O
|
|
net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll
|
|
PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2)
|
|
-2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2
|
|
net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll
|
|
BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout3_buf/O
|
|
net (fo=26129, routed) 0.839 -0.469 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/mlkem_clk
|
|
SLICE_X86Y148 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/cr_reg[241][2]/C
|
|
clock pessimism 0.045 -0.424
|
|
SLICE_X86Y148 FDCE (Hold_fdce_C_D) 0.092 -0.332 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/cr_reg[241][2]
|
|
-------------------------------------------------------------------
|
|
required time 0.332
|
|
arrival time -0.255
|
|
-------------------------------------------------------------------
|
|
slack 0.077
|
|
|
|
Slack (MET) : 0.083ns (arrival time - required time)
|
|
Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/wb_valid_r_reg_rep__5/C
|
|
(rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns})
|
|
Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/cr_reg[130][5]/D
|
|
(rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns})
|
|
Path Group: mlkem_clk_clk_pll
|
|
Path Type: Hold (Min at Fast Process Corner)
|
|
Requirement: 0.000ns (mlkem_clk_clk_pll rise@0.000ns - mlkem_clk_clk_pll rise@0.000ns)
|
|
Data Path Delay: 0.453ns (logic 0.186ns (41.036%) route 0.267ns (58.964%))
|
|
Logic Levels: 1 (LUT6=1)
|
|
Clock Path Skew: 0.278ns (DCD - SCD - CPR)
|
|
Destination Clock Delay (DCD): -0.439ns
|
|
Source Clock Delay (SCD): -0.672ns
|
|
Clock Pessimism Removal (CPR): -0.045ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock mlkem_clk_clk_pll rise edge)
|
|
0.000 0.000 r
|
|
K21 0.000 0.000 r clk (IN)
|
|
net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1
|
|
K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O
|
|
net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll
|
|
PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2)
|
|
-2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2
|
|
net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll
|
|
BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout3_buf/O
|
|
net (fo=26129, routed) 0.591 -0.672 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/mlkem_clk
|
|
SLICE_X138Y154 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/wb_valid_r_reg_rep__5/C
|
|
------------------------------------------------------------------- -------------------
|
|
SLICE_X138Y154 FDCE (Prop_fdce_C_Q) 0.141 -0.531 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/wb_valid_r_reg_rep__5/Q
|
|
net (fo=127, routed) 0.267 -0.264 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/wb_valid_r_reg_rep__5_n_0
|
|
SLICE_X137Y147 LUT6 (Prop_lut6_I3_O) 0.045 -0.219 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/cr[130][5]_i_1/O
|
|
net (fo=1, routed) 0.000 -0.219 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/cr[130][5]_i_1_n_0
|
|
SLICE_X137Y147 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/cr_reg[130][5]/D
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock mlkem_clk_clk_pll rise edge)
|
|
0.000 0.000 r
|
|
K21 0.000 0.000 r clk (IN)
|
|
net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1
|
|
K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O
|
|
net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll
|
|
PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2)
|
|
-2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2
|
|
net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll
|
|
BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout3_buf/O
|
|
net (fo=26129, routed) 0.869 -0.439 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/mlkem_clk
|
|
SLICE_X137Y147 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/cr_reg[130][5]/C
|
|
clock pessimism 0.045 -0.394
|
|
SLICE_X137Y147 FDCE (Hold_fdce_C_D) 0.092 -0.302 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/cr_reg[130][5]
|
|
-------------------------------------------------------------------
|
|
required time 0.302
|
|
arrival time -0.219
|
|
-------------------------------------------------------------------
|
|
slack 0.083
|
|
|
|
Slack (MET) : 0.094ns (arrival time - required time)
|
|
Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/qprod_s4_reg[0]/C
|
|
(rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns})
|
|
Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[0]/D
|
|
(rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns})
|
|
Path Group: mlkem_clk_clk_pll
|
|
Path Type: Hold (Min at Fast Process Corner)
|
|
Requirement: 0.000ns (mlkem_clk_clk_pll rise@0.000ns - mlkem_clk_clk_pll rise@0.000ns)
|
|
Data Path Delay: 0.463ns (logic 0.256ns (55.346%) route 0.207ns (44.654%))
|
|
Logic Levels: 2 (CARRY4=1 LUT2=1)
|
|
Clock Path Skew: 0.264ns (DCD - SCD - CPR)
|
|
Destination Clock Delay (DCD): -0.477ns
|
|
Source Clock Delay (SCD): -0.701ns
|
|
Clock Pessimism Removal (CPR): -0.040ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock mlkem_clk_clk_pll rise edge)
|
|
0.000 0.000 r
|
|
K21 0.000 0.000 r clk (IN)
|
|
net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1
|
|
K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O
|
|
net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll
|
|
PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2)
|
|
-2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2
|
|
net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll
|
|
BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout3_buf/O
|
|
net (fo=26129, routed) 0.562 -0.701 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/mlkem_clk
|
|
SLICE_X85Y156 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/qprod_s4_reg[0]/C
|
|
------------------------------------------------------------------- -------------------
|
|
SLICE_X85Y156 FDCE (Prop_fdce_C_Q) 0.141 -0.560 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/qprod_s4_reg[0]/Q
|
|
net (fo=1, routed) 0.207 -0.353 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/qprod_s4[0]
|
|
SLICE_X83Y154 LUT2 (Prop_lut2_I1_O) 0.045 -0.308 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5[3]_i_5/O
|
|
net (fo=1, routed) 0.000 -0.308 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5[3]_i_5_n_0
|
|
SLICE_X83Y154 CARRY4 (Prop_carry4_S[0]_O[0])
|
|
0.070 -0.238 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[3]_i_1/O[0]
|
|
net (fo=1, routed) 0.000 -0.238 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s50[0]
|
|
SLICE_X83Y154 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[0]/D
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock mlkem_clk_clk_pll rise edge)
|
|
0.000 0.000 r
|
|
K21 0.000 0.000 r clk (IN)
|
|
net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1
|
|
K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O
|
|
net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll
|
|
PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2)
|
|
-2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2
|
|
net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll
|
|
BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout3_buf/O
|
|
net (fo=26129, routed) 0.831 -0.477 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/mlkem_clk
|
|
SLICE_X83Y154 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[0]/C
|
|
clock pessimism 0.040 -0.437
|
|
SLICE_X83Y154 FDCE (Hold_fdce_C_D) 0.105 -0.332 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[0]
|
|
-------------------------------------------------------------------
|
|
required time 0.332
|
|
arrival time -0.238
|
|
-------------------------------------------------------------------
|
|
slack 0.094
|
|
|
|
Slack (MET) : 0.095ns (arrival time - required time)
|
|
Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/p_s1_reg[16]/C
|
|
(rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns})
|
|
Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/p_s2_reg[16]/D
|
|
(rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns})
|
|
Path Group: mlkem_clk_clk_pll
|
|
Path Type: Hold (Min at Fast Process Corner)
|
|
Requirement: 0.000ns (mlkem_clk_clk_pll rise@0.000ns - mlkem_clk_clk_pll rise@0.000ns)
|
|
Data Path Delay: 0.416ns (logic 0.141ns (33.875%) route 0.275ns (66.125%))
|
|
Logic Levels: 0
|
|
Clock Path Skew: 0.264ns (DCD - SCD - CPR)
|
|
Destination Clock Delay (DCD): -0.464ns
|
|
Source Clock Delay (SCD): -0.683ns
|
|
Clock Pessimism Removal (CPR): -0.045ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock mlkem_clk_clk_pll rise edge)
|
|
0.000 0.000 r
|
|
K21 0.000 0.000 r clk (IN)
|
|
net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1
|
|
K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O
|
|
net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll
|
|
PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2)
|
|
-2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2
|
|
net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll
|
|
BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout3_buf/O
|
|
net (fo=26129, routed) 0.580 -0.683 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/mlkem_clk
|
|
SLICE_X73Y148 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/p_s1_reg[16]/C
|
|
------------------------------------------------------------------- -------------------
|
|
SLICE_X73Y148 FDCE (Prop_fdce_C_Q) 0.141 -0.542 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/p_s1_reg[16]/Q
|
|
net (fo=14, routed) 0.275 -0.267 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/Q[16]
|
|
SLICE_X73Y154 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/p_s2_reg[16]/D
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock mlkem_clk_clk_pll rise edge)
|
|
0.000 0.000 r
|
|
K21 0.000 0.000 r clk (IN)
|
|
net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1
|
|
K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O
|
|
net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll
|
|
PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2)
|
|
-2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2
|
|
net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll
|
|
BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout3_buf/O
|
|
net (fo=26129, routed) 0.844 -0.464 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/mlkem_clk
|
|
SLICE_X73Y154 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/p_s2_reg[16]/C
|
|
clock pessimism 0.045 -0.419
|
|
SLICE_X73Y154 FDCE (Hold_fdce_C_D) 0.057 -0.362 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/p_s2_reg[16]
|
|
-------------------------------------------------------------------
|
|
required time 0.362
|
|
arrival time -0.267
|
|
-------------------------------------------------------------------
|
|
slack 0.095
|
|
|
|
Slack (MET) : 0.099ns (arrival time - required time)
|
|
Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_scl/p_s4_reg[2]/C
|
|
(rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns})
|
|
Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_scl/r0_s5_reg[2]/D
|
|
(rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns})
|
|
Path Group: mlkem_clk_clk_pll
|
|
Path Type: Hold (Min at Fast Process Corner)
|
|
Requirement: 0.000ns (mlkem_clk_clk_pll rise@0.000ns - mlkem_clk_clk_pll rise@0.000ns)
|
|
Data Path Delay: 0.470ns (logic 0.252ns (53.610%) route 0.218ns (46.390%))
|
|
Logic Levels: 2 (CARRY4=1 LUT2=1)
|
|
Clock Path Skew: 0.266ns (DCD - SCD - CPR)
|
|
Destination Clock Delay (DCD): -0.477ns
|
|
Source Clock Delay (SCD): -0.703ns
|
|
Clock Pessimism Removal (CPR): -0.040ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock mlkem_clk_clk_pll rise edge)
|
|
0.000 0.000 r
|
|
K21 0.000 0.000 r clk (IN)
|
|
net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1
|
|
K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O
|
|
net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll
|
|
PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2)
|
|
-2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2
|
|
net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll
|
|
BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout3_buf/O
|
|
net (fo=26129, routed) 0.560 -0.703 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_scl/mlkem_clk
|
|
SLICE_X85Y160 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_scl/p_s4_reg[2]/C
|
|
------------------------------------------------------------------- -------------------
|
|
SLICE_X85Y160 FDCE (Prop_fdce_C_Q) 0.141 -0.562 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_scl/p_s4_reg[2]/Q
|
|
net (fo=2, routed) 0.218 -0.344 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_scl/p_s4[2]
|
|
SLICE_X79Y160 LUT2 (Prop_lut2_I0_O) 0.045 -0.299 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_scl/r0_s5[3]_i_3__0/O
|
|
net (fo=1, routed) 0.000 -0.299 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_scl/r0_s5[3]_i_3__0_n_0
|
|
SLICE_X79Y160 CARRY4 (Prop_carry4_S[2]_O[2])
|
|
0.066 -0.233 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_scl/r0_s5_reg[3]_i_1__0/O[2]
|
|
net (fo=1, routed) 0.000 -0.233 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_scl/r0_s50[2]
|
|
SLICE_X79Y160 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_scl/r0_s5_reg[2]/D
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock mlkem_clk_clk_pll rise edge)
|
|
0.000 0.000 r
|
|
K21 0.000 0.000 r clk (IN)
|
|
net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1
|
|
K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O
|
|
net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll
|
|
PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2)
|
|
-2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2
|
|
net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll
|
|
BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout3_buf/O
|
|
net (fo=26129, routed) 0.831 -0.477 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_scl/mlkem_clk
|
|
SLICE_X79Y160 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_scl/r0_s5_reg[2]/C
|
|
clock pessimism 0.040 -0.437
|
|
SLICE_X79Y160 FDCE (Hold_fdce_C_D) 0.105 -0.332 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_scl/r0_s5_reg[2]
|
|
-------------------------------------------------------------------
|
|
required time 0.332
|
|
arrival time -0.233
|
|
-------------------------------------------------------------------
|
|
slack 0.099
|
|
|
|
Slack (MET) : 0.105ns (arrival time - required time)
|
|
Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[5]/C
|
|
(rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns})
|
|
Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r1_s6_reg[5]/D
|
|
(rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns})
|
|
Path Group: mlkem_clk_clk_pll
|
|
Path Type: Hold (Min at Fast Process Corner)
|
|
Requirement: 0.000ns (mlkem_clk_clk_pll rise@0.000ns - mlkem_clk_clk_pll rise@0.000ns)
|
|
Data Path Delay: 0.502ns (logic 0.185ns (36.874%) route 0.317ns (63.126%))
|
|
Logic Levels: 1 (LUT3=1)
|
|
Clock Path Skew: 0.266ns (DCD - SCD - CPR)
|
|
Destination Clock Delay (DCD): -0.476ns
|
|
Source Clock Delay (SCD): -0.702ns
|
|
Clock Pessimism Removal (CPR): -0.040ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock mlkem_clk_clk_pll rise edge)
|
|
0.000 0.000 r
|
|
K21 0.000 0.000 r clk (IN)
|
|
net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1
|
|
K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O
|
|
net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll
|
|
PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2)
|
|
-2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2
|
|
net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll
|
|
BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout3_buf/O
|
|
net (fo=26129, routed) 0.561 -0.702 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/mlkem_clk
|
|
SLICE_X83Y155 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[5]/C
|
|
------------------------------------------------------------------- -------------------
|
|
SLICE_X83Y155 FDCE (Prop_fdce_C_Q) 0.141 -0.561 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[5]/Q
|
|
net (fo=4, routed) 0.317 -0.244 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5[5]
|
|
SLICE_X84Y155 LUT3 (Prop_lut3_I0_O) 0.044 -0.200 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r1_s6[5]_i_1/O
|
|
net (fo=1, routed) 0.000 -0.200 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r1_s6[5]_i_1_n_0
|
|
SLICE_X84Y155 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r1_s6_reg[5]/D
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock mlkem_clk_clk_pll rise edge)
|
|
0.000 0.000 r
|
|
K21 0.000 0.000 r clk (IN)
|
|
net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1
|
|
K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O
|
|
net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll
|
|
PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2)
|
|
-2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2
|
|
net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll
|
|
BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout3_buf/O
|
|
net (fo=26129, routed) 0.831 -0.476 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/mlkem_clk
|
|
SLICE_X84Y155 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r1_s6_reg[5]/C
|
|
clock pessimism 0.040 -0.436
|
|
SLICE_X84Y155 FDCE (Hold_fdce_C_D) 0.131 -0.305 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r1_s6_reg[5]
|
|
-------------------------------------------------------------------
|
|
required time 0.305
|
|
arrival time -0.200
|
|
-------------------------------------------------------------------
|
|
slack 0.105
|
|
|
|
Slack (MET) : 0.107ns (arrival time - required time)
|
|
Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/qprod_s4_reg[10]/C
|
|
(rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns})
|
|
Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[10]/D
|
|
(rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns})
|
|
Path Group: mlkem_clk_clk_pll
|
|
Path Type: Hold (Min at Fast Process Corner)
|
|
Requirement: 0.000ns (mlkem_clk_clk_pll rise@0.000ns - mlkem_clk_clk_pll rise@0.000ns)
|
|
Data Path Delay: 0.475ns (logic 0.275ns (57.843%) route 0.200ns (42.157%))
|
|
Logic Levels: 2 (CARRY4=1 LUT2=1)
|
|
Clock Path Skew: 0.264ns (DCD - SCD - CPR)
|
|
Destination Clock Delay (DCD): -0.477ns
|
|
Source Clock Delay (SCD): -0.701ns
|
|
Clock Pessimism Removal (CPR): -0.040ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock mlkem_clk_clk_pll rise edge)
|
|
0.000 0.000 r
|
|
K21 0.000 0.000 r clk (IN)
|
|
net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1
|
|
K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O
|
|
net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll
|
|
PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2)
|
|
-2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2
|
|
net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll
|
|
BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout3_buf/O
|
|
net (fo=26129, routed) 0.562 -0.701 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/mlkem_clk
|
|
SLICE_X84Y156 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/qprod_s4_reg[10]/C
|
|
------------------------------------------------------------------- -------------------
|
|
SLICE_X84Y156 FDCE (Prop_fdce_C_Q) 0.164 -0.537 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/qprod_s4_reg[10]/Q
|
|
net (fo=1, routed) 0.200 -0.336 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/qprod_s4[10]
|
|
SLICE_X83Y156 LUT2 (Prop_lut2_I1_O) 0.045 -0.291 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5[11]_i_3/O
|
|
net (fo=1, routed) 0.000 -0.291 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5[11]_i_3_n_0
|
|
SLICE_X83Y156 CARRY4 (Prop_carry4_S[2]_O[2])
|
|
0.066 -0.225 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[11]_i_1/O[2]
|
|
net (fo=1, routed) 0.000 -0.225 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s50[10]
|
|
SLICE_X83Y156 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[10]/D
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock mlkem_clk_clk_pll rise edge)
|
|
0.000 0.000 r
|
|
K21 0.000 0.000 r clk (IN)
|
|
net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1
|
|
K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O
|
|
net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll
|
|
PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2)
|
|
-2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2
|
|
net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll
|
|
BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout3_buf/O
|
|
net (fo=26129, routed) 0.831 -0.477 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/mlkem_clk
|
|
SLICE_X83Y156 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[10]/C
|
|
clock pessimism 0.040 -0.437
|
|
SLICE_X83Y156 FDCE (Hold_fdce_C_D) 0.105 -0.332 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[10]
|
|
-------------------------------------------------------------------
|
|
required time 0.332
|
|
arrival time -0.225
|
|
-------------------------------------------------------------------
|
|
slack 0.107
|
|
|
|
Slack (MET) : 0.107ns (arrival time - required time)
|
|
Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/qprod_s4_reg[14]/C
|
|
(rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns})
|
|
Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[14]/D
|
|
(rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns})
|
|
Path Group: mlkem_clk_clk_pll
|
|
Path Type: Hold (Min at Fast Process Corner)
|
|
Requirement: 0.000ns (mlkem_clk_clk_pll rise@0.000ns - mlkem_clk_clk_pll rise@0.000ns)
|
|
Data Path Delay: 0.475ns (logic 0.275ns (57.843%) route 0.200ns (42.157%))
|
|
Logic Levels: 2 (CARRY4=1 LUT2=1)
|
|
Clock Path Skew: 0.264ns (DCD - SCD - CPR)
|
|
Destination Clock Delay (DCD): -0.478ns
|
|
Source Clock Delay (SCD): -0.702ns
|
|
Clock Pessimism Removal (CPR): -0.040ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock mlkem_clk_clk_pll rise edge)
|
|
0.000 0.000 r
|
|
K21 0.000 0.000 r clk (IN)
|
|
net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1
|
|
K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O
|
|
net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll
|
|
PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2)
|
|
-2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2
|
|
net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll
|
|
BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout3_buf/O
|
|
net (fo=26129, routed) 0.561 -0.702 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/mlkem_clk
|
|
SLICE_X84Y157 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/qprod_s4_reg[14]/C
|
|
------------------------------------------------------------------- -------------------
|
|
SLICE_X84Y157 FDCE (Prop_fdce_C_Q) 0.164 -0.538 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/qprod_s4_reg[14]/Q
|
|
net (fo=1, routed) 0.200 -0.337 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/qprod_s4[14]
|
|
SLICE_X83Y157 LUT2 (Prop_lut2_I1_O) 0.045 -0.292 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5[15]_i_3/O
|
|
net (fo=1, routed) 0.000 -0.292 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5[15]_i_3_n_0
|
|
SLICE_X83Y157 CARRY4 (Prop_carry4_S[2]_O[2])
|
|
0.066 -0.226 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[15]_i_1/O[2]
|
|
net (fo=1, routed) 0.000 -0.226 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s50[14]
|
|
SLICE_X83Y157 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[14]/D
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock mlkem_clk_clk_pll rise edge)
|
|
0.000 0.000 r
|
|
K21 0.000 0.000 r clk (IN)
|
|
net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1
|
|
K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O
|
|
net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll
|
|
PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2)
|
|
-2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2
|
|
net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll
|
|
BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout3_buf/O
|
|
net (fo=26129, routed) 0.830 -0.478 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/mlkem_clk
|
|
SLICE_X83Y157 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[14]/C
|
|
clock pessimism 0.040 -0.438
|
|
SLICE_X83Y157 FDCE (Hold_fdce_C_D) 0.105 -0.333 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[14]
|
|
-------------------------------------------------------------------
|
|
required time 0.333
|
|
arrival time -0.226
|
|
-------------------------------------------------------------------
|
|
slack 0.107
|
|
|
|
Slack (MET) : 0.107ns (arrival time - required time)
|
|
Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/qprod_s4_reg[18]/C
|
|
(rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns})
|
|
Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[18]/D
|
|
(rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns})
|
|
Path Group: mlkem_clk_clk_pll
|
|
Path Type: Hold (Min at Fast Process Corner)
|
|
Requirement: 0.000ns (mlkem_clk_clk_pll rise@0.000ns - mlkem_clk_clk_pll rise@0.000ns)
|
|
Data Path Delay: 0.475ns (logic 0.275ns (57.843%) route 0.200ns (42.157%))
|
|
Logic Levels: 2 (CARRY4=1 LUT2=1)
|
|
Clock Path Skew: 0.264ns (DCD - SCD - CPR)
|
|
Destination Clock Delay (DCD): -0.478ns
|
|
Source Clock Delay (SCD): -0.702ns
|
|
Clock Pessimism Removal (CPR): -0.040ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock mlkem_clk_clk_pll rise edge)
|
|
0.000 0.000 r
|
|
K21 0.000 0.000 r clk (IN)
|
|
net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1
|
|
K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O
|
|
net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll
|
|
PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2)
|
|
-2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2
|
|
net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll
|
|
BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout3_buf/O
|
|
net (fo=26129, routed) 0.561 -0.702 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/mlkem_clk
|
|
SLICE_X84Y158 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/qprod_s4_reg[18]/C
|
|
------------------------------------------------------------------- -------------------
|
|
SLICE_X84Y158 FDCE (Prop_fdce_C_Q) 0.164 -0.538 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/qprod_s4_reg[18]/Q
|
|
net (fo=1, routed) 0.200 -0.337 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/qprod_s4[18]
|
|
SLICE_X83Y158 LUT2 (Prop_lut2_I1_O) 0.045 -0.292 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5[19]_i_3/O
|
|
net (fo=1, routed) 0.000 -0.292 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5[19]_i_3_n_0
|
|
SLICE_X83Y158 CARRY4 (Prop_carry4_S[2]_O[2])
|
|
0.066 -0.226 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[19]_i_1/O[2]
|
|
net (fo=1, routed) 0.000 -0.226 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s50[18]
|
|
SLICE_X83Y158 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[18]/D
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock mlkem_clk_clk_pll rise edge)
|
|
0.000 0.000 r
|
|
K21 0.000 0.000 r clk (IN)
|
|
net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1
|
|
K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O
|
|
net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll
|
|
PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2)
|
|
-2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2
|
|
net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll
|
|
BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout3_buf/O
|
|
net (fo=26129, routed) 0.830 -0.478 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/mlkem_clk
|
|
SLICE_X83Y158 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[18]/C
|
|
clock pessimism 0.040 -0.438
|
|
SLICE_X83Y158 FDCE (Hold_fdce_C_D) 0.105 -0.333 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[18]
|
|
-------------------------------------------------------------------
|
|
required time 0.333
|
|
arrival time -0.226
|
|
-------------------------------------------------------------------
|
|
slack 0.107
|
|
|
|
Slack (MET) : 0.107ns (arrival time - required time)
|
|
Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/qprod_s4_reg[22]/C
|
|
(rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns})
|
|
Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[22]/D
|
|
(rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns})
|
|
Path Group: mlkem_clk_clk_pll
|
|
Path Type: Hold (Min at Fast Process Corner)
|
|
Requirement: 0.000ns (mlkem_clk_clk_pll rise@0.000ns - mlkem_clk_clk_pll rise@0.000ns)
|
|
Data Path Delay: 0.475ns (logic 0.275ns (57.843%) route 0.200ns (42.157%))
|
|
Logic Levels: 2 (CARRY4=1 LUT2=1)
|
|
Clock Path Skew: 0.264ns (DCD - SCD - CPR)
|
|
Destination Clock Delay (DCD): -0.478ns
|
|
Source Clock Delay (SCD): -0.702ns
|
|
Clock Pessimism Removal (CPR): -0.040ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock mlkem_clk_clk_pll rise edge)
|
|
0.000 0.000 r
|
|
K21 0.000 0.000 r clk (IN)
|
|
net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1
|
|
K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O
|
|
net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll
|
|
PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2)
|
|
-2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2
|
|
net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll
|
|
BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout3_buf/O
|
|
net (fo=26129, routed) 0.561 -0.702 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/mlkem_clk
|
|
SLICE_X84Y159 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/qprod_s4_reg[22]/C
|
|
------------------------------------------------------------------- -------------------
|
|
SLICE_X84Y159 FDCE (Prop_fdce_C_Q) 0.164 -0.538 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/qprod_s4_reg[22]/Q
|
|
net (fo=1, routed) 0.200 -0.337 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/qprod_s4[22]
|
|
SLICE_X83Y159 LUT2 (Prop_lut2_I1_O) 0.045 -0.292 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5[23]_i_3/O
|
|
net (fo=1, routed) 0.000 -0.292 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5[23]_i_3_n_0
|
|
SLICE_X83Y159 CARRY4 (Prop_carry4_S[2]_O[2])
|
|
0.066 -0.226 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[23]_i_1/O[2]
|
|
net (fo=1, routed) 0.000 -0.226 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s50[22]
|
|
SLICE_X83Y159 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[22]/D
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock mlkem_clk_clk_pll rise edge)
|
|
0.000 0.000 r
|
|
K21 0.000 0.000 r clk (IN)
|
|
net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1
|
|
K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O
|
|
net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll
|
|
PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2)
|
|
-2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2
|
|
net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll
|
|
BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout3_buf/O
|
|
net (fo=26129, routed) 0.830 -0.478 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/mlkem_clk
|
|
SLICE_X83Y159 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[22]/C
|
|
clock pessimism 0.040 -0.438
|
|
SLICE_X83Y159 FDCE (Hold_fdce_C_D) 0.105 -0.333 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[22]
|
|
-------------------------------------------------------------------
|
|
required time 0.333
|
|
arrival time -0.226
|
|
-------------------------------------------------------------------
|
|
slack 0.107
|
|
|
|
Slack (MET) : 0.107ns (arrival time - required time)
|
|
Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/wb_a_data_r_reg[8]/C
|
|
(rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns})
|
|
Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/cr_reg[240][8]/D
|
|
(rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns})
|
|
Path Group: mlkem_clk_clk_pll
|
|
Path Type: Hold (Min at Fast Process Corner)
|
|
Requirement: 0.000ns (mlkem_clk_clk_pll rise@0.000ns - mlkem_clk_clk_pll rise@0.000ns)
|
|
Data Path Delay: 0.508ns (logic 0.186ns (36.603%) route 0.322ns (63.397%))
|
|
Logic Levels: 1 (LUT6=1)
|
|
Clock Path Skew: 0.280ns (DCD - SCD - CPR)
|
|
Destination Clock Delay (DCD): -0.458ns
|
|
Source Clock Delay (SCD): -0.693ns
|
|
Clock Pessimism Removal (CPR): -0.045ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock mlkem_clk_clk_pll rise edge)
|
|
0.000 0.000 r
|
|
K21 0.000 0.000 r clk (IN)
|
|
net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1
|
|
K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O
|
|
net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll
|
|
PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2)
|
|
-2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2
|
|
net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll
|
|
BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout3_buf/O
|
|
net (fo=26129, routed) 0.570 -0.693 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/mlkem_clk
|
|
SLICE_X89Y154 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/wb_a_data_r_reg[8]/C
|
|
------------------------------------------------------------------- -------------------
|
|
SLICE_X89Y154 FDCE (Prop_fdce_C_Q) 0.141 -0.552 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/wb_a_data_r_reg[8]/Q
|
|
net (fo=234, routed) 0.322 -0.230 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/wb_a_data_r[8]
|
|
SLICE_X90Y147 LUT6 (Prop_lut6_I3_O) 0.045 -0.185 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/cr[240][8]_i_1/O
|
|
net (fo=1, routed) 0.000 -0.185 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/cr[240][8]_i_1_n_0
|
|
SLICE_X90Y147 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/cr_reg[240][8]/D
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock mlkem_clk_clk_pll rise edge)
|
|
0.000 0.000 r
|
|
K21 0.000 0.000 r clk (IN)
|
|
net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1
|
|
K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O
|
|
net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll
|
|
PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2)
|
|
-2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2
|
|
net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll
|
|
BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout3_buf/O
|
|
net (fo=26129, routed) 0.850 -0.458 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/mlkem_clk
|
|
SLICE_X90Y147 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/cr_reg[240][8]/C
|
|
clock pessimism 0.045 -0.413
|
|
SLICE_X90Y147 FDCE (Hold_fdce_C_D) 0.121 -0.292 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/cr_reg[240][8]
|
|
-------------------------------------------------------------------
|
|
required time 0.292
|
|
arrival time -0.185
|
|
-------------------------------------------------------------------
|
|
slack 0.107
|
|
|
|
Slack (MET) : 0.110ns (arrival time - required time)
|
|
Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/qprod_s4_reg[24]/C
|
|
(rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns})
|
|
Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[24]/D
|
|
(rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns})
|
|
Path Group: mlkem_clk_clk_pll
|
|
Path Type: Hold (Min at Fast Process Corner)
|
|
Requirement: 0.000ns (mlkem_clk_clk_pll rise@0.000ns - mlkem_clk_clk_pll rise@0.000ns)
|
|
Data Path Delay: 0.478ns (logic 0.279ns (58.317%) route 0.199ns (41.683%))
|
|
Logic Levels: 2 (CARRY4=1 LUT1=1)
|
|
Clock Path Skew: 0.264ns (DCD - SCD - CPR)
|
|
Destination Clock Delay (DCD): -0.479ns
|
|
Source Clock Delay (SCD): -0.703ns
|
|
Clock Pessimism Removal (CPR): -0.040ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock mlkem_clk_clk_pll rise edge)
|
|
0.000 0.000 r
|
|
K21 0.000 0.000 r clk (IN)
|
|
net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1
|
|
K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O
|
|
net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll
|
|
PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2)
|
|
-2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2
|
|
net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll
|
|
BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout3_buf/O
|
|
net (fo=26129, routed) 0.560 -0.703 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/mlkem_clk
|
|
SLICE_X84Y160 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/qprod_s4_reg[24]/C
|
|
------------------------------------------------------------------- -------------------
|
|
SLICE_X84Y160 FDCE (Prop_fdce_C_Q) 0.164 -0.539 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/qprod_s4_reg[24]/Q
|
|
net (fo=1, routed) 0.199 -0.339 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/qprod_s4[24]
|
|
SLICE_X83Y160 LUT1 (Prop_lut1_I0_O) 0.045 -0.294 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5[24]_i_2/O
|
|
net (fo=1, routed) 0.000 -0.294 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5[24]_i_2_n_0
|
|
SLICE_X83Y160 CARRY4 (Prop_carry4_S[0]_O[0])
|
|
0.070 -0.224 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[24]_i_1/O[0]
|
|
net (fo=1, routed) 0.000 -0.224 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s50[24]
|
|
SLICE_X83Y160 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[24]/D
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock mlkem_clk_clk_pll rise edge)
|
|
0.000 0.000 r
|
|
K21 0.000 0.000 r clk (IN)
|
|
net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1
|
|
K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O
|
|
net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll
|
|
PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2)
|
|
-2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2
|
|
net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll
|
|
BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout3_buf/O
|
|
net (fo=26129, routed) 0.829 -0.479 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/mlkem_clk
|
|
SLICE_X83Y160 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[24]/C
|
|
clock pessimism 0.040 -0.439
|
|
SLICE_X83Y160 FDCE (Hold_fdce_C_D) 0.105 -0.334 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[24]
|
|
-------------------------------------------------------------------
|
|
required time 0.334
|
|
arrival time -0.224
|
|
-------------------------------------------------------------------
|
|
slack 0.110
|
|
|
|
Slack (MET) : 0.110ns (arrival time - required time)
|
|
Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/qprod_s4_reg[12]/C
|
|
(rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns})
|
|
Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[12]/D
|
|
(rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns})
|
|
Path Group: mlkem_clk_clk_pll
|
|
Path Type: Hold (Min at Fast Process Corner)
|
|
Requirement: 0.000ns (mlkem_clk_clk_pll rise@0.000ns - mlkem_clk_clk_pll rise@0.000ns)
|
|
Data Path Delay: 0.478ns (logic 0.279ns (58.317%) route 0.199ns (41.683%))
|
|
Logic Levels: 2 (CARRY4=1 LUT2=1)
|
|
Clock Path Skew: 0.264ns (DCD - SCD - CPR)
|
|
Destination Clock Delay (DCD): -0.478ns
|
|
Source Clock Delay (SCD): -0.702ns
|
|
Clock Pessimism Removal (CPR): -0.040ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock mlkem_clk_clk_pll rise edge)
|
|
0.000 0.000 r
|
|
K21 0.000 0.000 r clk (IN)
|
|
net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1
|
|
K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O
|
|
net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll
|
|
PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2)
|
|
-2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2
|
|
net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll
|
|
BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout3_buf/O
|
|
net (fo=26129, routed) 0.561 -0.702 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/mlkem_clk
|
|
SLICE_X84Y157 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/qprod_s4_reg[12]/C
|
|
------------------------------------------------------------------- -------------------
|
|
SLICE_X84Y157 FDCE (Prop_fdce_C_Q) 0.164 -0.538 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/qprod_s4_reg[12]/Q
|
|
net (fo=1, routed) 0.199 -0.338 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/qprod_s4[12]
|
|
SLICE_X83Y157 LUT2 (Prop_lut2_I1_O) 0.045 -0.293 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5[15]_i_5/O
|
|
net (fo=1, routed) 0.000 -0.293 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5[15]_i_5_n_0
|
|
SLICE_X83Y157 CARRY4 (Prop_carry4_S[0]_O[0])
|
|
0.070 -0.223 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[15]_i_1/O[0]
|
|
net (fo=1, routed) 0.000 -0.223 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s50[12]
|
|
SLICE_X83Y157 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[12]/D
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock mlkem_clk_clk_pll rise edge)
|
|
0.000 0.000 r
|
|
K21 0.000 0.000 r clk (IN)
|
|
net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1
|
|
K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O
|
|
net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll
|
|
PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2)
|
|
-2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2
|
|
net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll
|
|
BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout3_buf/O
|
|
net (fo=26129, routed) 0.830 -0.478 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/mlkem_clk
|
|
SLICE_X83Y157 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[12]/C
|
|
clock pessimism 0.040 -0.438
|
|
SLICE_X83Y157 FDCE (Hold_fdce_C_D) 0.105 -0.333 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[12]
|
|
-------------------------------------------------------------------
|
|
required time 0.333
|
|
arrival time -0.223
|
|
-------------------------------------------------------------------
|
|
slack 0.110
|
|
|
|
Slack (MET) : 0.110ns (arrival time - required time)
|
|
Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/qprod_s4_reg[16]/C
|
|
(rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns})
|
|
Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[16]/D
|
|
(rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns})
|
|
Path Group: mlkem_clk_clk_pll
|
|
Path Type: Hold (Min at Fast Process Corner)
|
|
Requirement: 0.000ns (mlkem_clk_clk_pll rise@0.000ns - mlkem_clk_clk_pll rise@0.000ns)
|
|
Data Path Delay: 0.478ns (logic 0.279ns (58.317%) route 0.199ns (41.683%))
|
|
Logic Levels: 2 (CARRY4=1 LUT2=1)
|
|
Clock Path Skew: 0.264ns (DCD - SCD - CPR)
|
|
Destination Clock Delay (DCD): -0.478ns
|
|
Source Clock Delay (SCD): -0.702ns
|
|
Clock Pessimism Removal (CPR): -0.040ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock mlkem_clk_clk_pll rise edge)
|
|
0.000 0.000 r
|
|
K21 0.000 0.000 r clk (IN)
|
|
net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1
|
|
K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O
|
|
net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll
|
|
PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2)
|
|
-2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2
|
|
net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll
|
|
BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout3_buf/O
|
|
net (fo=26129, routed) 0.561 -0.702 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/mlkem_clk
|
|
SLICE_X84Y158 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/qprod_s4_reg[16]/C
|
|
------------------------------------------------------------------- -------------------
|
|
SLICE_X84Y158 FDCE (Prop_fdce_C_Q) 0.164 -0.538 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/qprod_s4_reg[16]/Q
|
|
net (fo=1, routed) 0.199 -0.338 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/qprod_s4[16]
|
|
SLICE_X83Y158 LUT2 (Prop_lut2_I1_O) 0.045 -0.293 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5[19]_i_5/O
|
|
net (fo=1, routed) 0.000 -0.293 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5[19]_i_5_n_0
|
|
SLICE_X83Y158 CARRY4 (Prop_carry4_S[0]_O[0])
|
|
0.070 -0.223 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[19]_i_1/O[0]
|
|
net (fo=1, routed) 0.000 -0.223 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s50[16]
|
|
SLICE_X83Y158 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[16]/D
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock mlkem_clk_clk_pll rise edge)
|
|
0.000 0.000 r
|
|
K21 0.000 0.000 r clk (IN)
|
|
net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1
|
|
K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O
|
|
net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll
|
|
PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2)
|
|
-2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2
|
|
net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll
|
|
BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout3_buf/O
|
|
net (fo=26129, routed) 0.830 -0.478 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/mlkem_clk
|
|
SLICE_X83Y158 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[16]/C
|
|
clock pessimism 0.040 -0.438
|
|
SLICE_X83Y158 FDCE (Hold_fdce_C_D) 0.105 -0.333 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[16]
|
|
-------------------------------------------------------------------
|
|
required time 0.333
|
|
arrival time -0.223
|
|
-------------------------------------------------------------------
|
|
slack 0.110
|
|
|
|
Slack (MET) : 0.110ns (arrival time - required time)
|
|
Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/qprod_s4_reg[20]/C
|
|
(rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns})
|
|
Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[20]/D
|
|
(rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns})
|
|
Path Group: mlkem_clk_clk_pll
|
|
Path Type: Hold (Min at Fast Process Corner)
|
|
Requirement: 0.000ns (mlkem_clk_clk_pll rise@0.000ns - mlkem_clk_clk_pll rise@0.000ns)
|
|
Data Path Delay: 0.478ns (logic 0.279ns (58.317%) route 0.199ns (41.683%))
|
|
Logic Levels: 2 (CARRY4=1 LUT2=1)
|
|
Clock Path Skew: 0.264ns (DCD - SCD - CPR)
|
|
Destination Clock Delay (DCD): -0.478ns
|
|
Source Clock Delay (SCD): -0.702ns
|
|
Clock Pessimism Removal (CPR): -0.040ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock mlkem_clk_clk_pll rise edge)
|
|
0.000 0.000 r
|
|
K21 0.000 0.000 r clk (IN)
|
|
net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1
|
|
K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O
|
|
net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll
|
|
PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2)
|
|
-2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2
|
|
net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll
|
|
BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout3_buf/O
|
|
net (fo=26129, routed) 0.561 -0.702 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/mlkem_clk
|
|
SLICE_X84Y159 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/qprod_s4_reg[20]/C
|
|
------------------------------------------------------------------- -------------------
|
|
SLICE_X84Y159 FDCE (Prop_fdce_C_Q) 0.164 -0.538 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/qprod_s4_reg[20]/Q
|
|
net (fo=1, routed) 0.199 -0.338 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/qprod_s4[20]
|
|
SLICE_X83Y159 LUT2 (Prop_lut2_I1_O) 0.045 -0.293 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5[23]_i_5/O
|
|
net (fo=1, routed) 0.000 -0.293 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5[23]_i_5_n_0
|
|
SLICE_X83Y159 CARRY4 (Prop_carry4_S[0]_O[0])
|
|
0.070 -0.223 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[23]_i_1/O[0]
|
|
net (fo=1, routed) 0.000 -0.223 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s50[20]
|
|
SLICE_X83Y159 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[20]/D
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock mlkem_clk_clk_pll rise edge)
|
|
0.000 0.000 r
|
|
K21 0.000 0.000 r clk (IN)
|
|
net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1
|
|
K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O
|
|
net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll
|
|
PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2)
|
|
-2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2
|
|
net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll
|
|
BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout3_buf/O
|
|
net (fo=26129, routed) 0.830 -0.478 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/mlkem_clk
|
|
SLICE_X83Y159 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[20]/C
|
|
clock pessimism 0.040 -0.438
|
|
SLICE_X83Y159 FDCE (Hold_fdce_C_D) 0.105 -0.333 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[20]
|
|
-------------------------------------------------------------------
|
|
required time 0.333
|
|
arrival time -0.223
|
|
-------------------------------------------------------------------
|
|
slack 0.110
|
|
|
|
Slack (MET) : 0.110ns (arrival time - required time)
|
|
Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/qprod_s4_reg[8]/C
|
|
(rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns})
|
|
Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[8]/D
|
|
(rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns})
|
|
Path Group: mlkem_clk_clk_pll
|
|
Path Type: Hold (Min at Fast Process Corner)
|
|
Requirement: 0.000ns (mlkem_clk_clk_pll rise@0.000ns - mlkem_clk_clk_pll rise@0.000ns)
|
|
Data Path Delay: 0.478ns (logic 0.279ns (58.317%) route 0.199ns (41.683%))
|
|
Logic Levels: 2 (CARRY4=1 LUT2=1)
|
|
Clock Path Skew: 0.264ns (DCD - SCD - CPR)
|
|
Destination Clock Delay (DCD): -0.477ns
|
|
Source Clock Delay (SCD): -0.701ns
|
|
Clock Pessimism Removal (CPR): -0.040ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock mlkem_clk_clk_pll rise edge)
|
|
0.000 0.000 r
|
|
K21 0.000 0.000 r clk (IN)
|
|
net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1
|
|
K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O
|
|
net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll
|
|
PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2)
|
|
-2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2
|
|
net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll
|
|
BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout3_buf/O
|
|
net (fo=26129, routed) 0.562 -0.701 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/mlkem_clk
|
|
SLICE_X84Y156 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/qprod_s4_reg[8]/C
|
|
------------------------------------------------------------------- -------------------
|
|
SLICE_X84Y156 FDCE (Prop_fdce_C_Q) 0.164 -0.537 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/qprod_s4_reg[8]/Q
|
|
net (fo=1, routed) 0.199 -0.337 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/qprod_s4[8]
|
|
SLICE_X83Y156 LUT2 (Prop_lut2_I1_O) 0.045 -0.292 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5[11]_i_5/O
|
|
net (fo=1, routed) 0.000 -0.292 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5[11]_i_5_n_0
|
|
SLICE_X83Y156 CARRY4 (Prop_carry4_S[0]_O[0])
|
|
0.070 -0.222 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[11]_i_1/O[0]
|
|
net (fo=1, routed) 0.000 -0.222 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s50[8]
|
|
SLICE_X83Y156 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[8]/D
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock mlkem_clk_clk_pll rise edge)
|
|
0.000 0.000 r
|
|
K21 0.000 0.000 r clk (IN)
|
|
net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1
|
|
K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O
|
|
net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll
|
|
PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2)
|
|
-2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2
|
|
net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll
|
|
BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout3_buf/O
|
|
net (fo=26129, routed) 0.831 -0.477 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/mlkem_clk
|
|
SLICE_X83Y156 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[8]/C
|
|
clock pessimism 0.040 -0.437
|
|
SLICE_X83Y156 FDCE (Hold_fdce_C_D) 0.105 -0.332 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[8]
|
|
-------------------------------------------------------------------
|
|
required time 0.332
|
|
arrival time -0.222
|
|
-------------------------------------------------------------------
|
|
slack 0.110
|
|
|
|
Slack (MET) : 0.111ns (arrival time - required time)
|
|
Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/q_s3_reg[12]/C
|
|
(rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns})
|
|
Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/qprod_s4_reg[12]/D
|
|
(rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns})
|
|
Path Group: mlkem_clk_clk_pll
|
|
Path Type: Hold (Min at Fast Process Corner)
|
|
Requirement: 0.000ns (mlkem_clk_clk_pll rise@0.000ns - mlkem_clk_clk_pll rise@0.000ns)
|
|
Data Path Delay: 0.510ns (logic 0.256ns (50.190%) route 0.254ns (49.810%))
|
|
Logic Levels: 2 (CARRY4=1 LUT4=1)
|
|
Clock Path Skew: 0.265ns (DCD - SCD - CPR)
|
|
Destination Clock Delay (DCD): -0.477ns
|
|
Source Clock Delay (SCD): -0.702ns
|
|
Clock Pessimism Removal (CPR): -0.040ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock mlkem_clk_clk_pll rise edge)
|
|
0.000 0.000 r
|
|
K21 0.000 0.000 r clk (IN)
|
|
net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1
|
|
K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O
|
|
net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll
|
|
PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2)
|
|
-2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2
|
|
net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll
|
|
BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout3_buf/O
|
|
net (fo=26129, routed) 0.561 -0.702 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/mlkem_clk
|
|
SLICE_X82Y156 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/q_s3_reg[12]/C
|
|
------------------------------------------------------------------- -------------------
|
|
SLICE_X82Y156 FDCE (Prop_fdce_C_Q) 0.141 -0.561 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/q_s3_reg[12]/Q
|
|
net (fo=7, routed) 0.254 -0.307 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/q_s3_reg[12]_0[10]
|
|
SLICE_X84Y157 LUT4 (Prop_lut4_I3_O) 0.045 -0.262 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/qprod_s4[15]_i_9/O
|
|
net (fo=1, routed) 0.000 -0.262 u_fft_mlkem_axi_slave_n_123
|
|
SLICE_X84Y157 CARRY4 (Prop_carry4_S[0]_O[0])
|
|
0.070 -0.192 r u_bf/u_barrett/qprod_s4_reg[15]_i_1/O[0]
|
|
net (fo=1, routed) 0.000 -0.192 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/qprod_s4_reg[23]_1[4]
|
|
SLICE_X84Y157 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/qprod_s4_reg[12]/D
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock mlkem_clk_clk_pll rise edge)
|
|
0.000 0.000 r
|
|
K21 0.000 0.000 r clk (IN)
|
|
net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1
|
|
K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O
|
|
net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll
|
|
PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2)
|
|
-2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2
|
|
net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll
|
|
BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout3_buf/O
|
|
net (fo=26129, routed) 0.831 -0.477 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/mlkem_clk
|
|
SLICE_X84Y157 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/qprod_s4_reg[12]/C
|
|
clock pessimism 0.040 -0.437
|
|
SLICE_X84Y157 FDCE (Hold_fdce_C_D) 0.134 -0.303 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/qprod_s4_reg[12]
|
|
-------------------------------------------------------------------
|
|
required time 0.303
|
|
arrival time -0.192
|
|
-------------------------------------------------------------------
|
|
slack 0.111
|
|
|
|
Slack (MET) : 0.114ns (arrival time - required time)
|
|
Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_snt/squeeze_state_r_reg[445]/C
|
|
(rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns})
|
|
Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r_reg[445]/D
|
|
(rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns})
|
|
Path Group: mlkem_clk_clk_pll
|
|
Path Type: Hold (Min at Fast Process Corner)
|
|
Requirement: 0.000ns (mlkem_clk_clk_pll rise@0.000ns - mlkem_clk_clk_pll rise@0.000ns)
|
|
Data Path Delay: 0.557ns (logic 0.234ns (42.015%) route 0.323ns (57.985%))
|
|
Logic Levels: 2 (LUT3=1 LUT6=1)
|
|
Clock Path Skew: 0.336ns (DCD - SCD - CPR)
|
|
Destination Clock Delay (DCD): -0.398ns
|
|
Source Clock Delay (SCD): -0.694ns
|
|
Clock Pessimism Removal (CPR): -0.040ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock mlkem_clk_clk_pll rise edge)
|
|
0.000 0.000 r
|
|
K21 0.000 0.000 r clk (IN)
|
|
net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1
|
|
K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O
|
|
net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll
|
|
PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2)
|
|
-2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2
|
|
net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll
|
|
BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout3_buf/O
|
|
net (fo=26129, routed) 0.569 -0.694 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_snt/mlkem_clk
|
|
SLICE_X79Y101 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_snt/squeeze_state_r_reg[445]/C
|
|
------------------------------------------------------------------- -------------------
|
|
SLICE_X79Y101 FDCE (Prop_fdce_C_Q) 0.141 -0.553 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_snt/squeeze_state_r_reg[445]/Q
|
|
net (fo=2, routed) 0.169 -0.384 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_snt/data18[13]
|
|
SLICE_X81Y99 LUT6 (Prop_lut6_I0_O) 0.045 -0.339 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_snt/state_r[445]_i_2/O
|
|
net (fo=1, routed) 0.154 -0.185 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/kc_state_i_mux[185]
|
|
SLICE_X81Y99 LUT3 (Prop_lut3_I1_O) 0.048 -0.137 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r[445]_i_1/O
|
|
net (fo=1, routed) 0.000 -0.137 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/p_1_in[445]
|
|
SLICE_X81Y99 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r_reg[445]/D
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock mlkem_clk_clk_pll rise edge)
|
|
0.000 0.000 r
|
|
K21 0.000 0.000 r clk (IN)
|
|
net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1
|
|
K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O
|
|
net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll
|
|
PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2)
|
|
-2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2
|
|
net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll
|
|
BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout3_buf/O
|
|
net (fo=26129, routed) 0.910 -0.398 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/mlkem_clk
|
|
SLICE_X81Y99 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r_reg[445]/C
|
|
clock pessimism 0.040 -0.358
|
|
SLICE_X81Y99 FDCE (Hold_fdce_C_D) 0.107 -0.251 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r_reg[445]
|
|
-------------------------------------------------------------------
|
|
required time 0.251
|
|
arrival time -0.137
|
|
-------------------------------------------------------------------
|
|
slack 0.114
|
|
|
|
Slack (MET) : 0.115ns (arrival time - required time)
|
|
Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/wb_a_data_r_reg[4]/C
|
|
(rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns})
|
|
Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/cr_reg[240][4]/D
|
|
(rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns})
|
|
Path Group: mlkem_clk_clk_pll
|
|
Path Type: Hold (Min at Fast Process Corner)
|
|
Requirement: 0.000ns (mlkem_clk_clk_pll rise@0.000ns - mlkem_clk_clk_pll rise@0.000ns)
|
|
Data Path Delay: 0.518ns (logic 0.186ns (35.884%) route 0.332ns (64.116%))
|
|
Logic Levels: 1 (LUT6=1)
|
|
Clock Path Skew: 0.282ns (DCD - SCD - CPR)
|
|
Destination Clock Delay (DCD): -0.456ns
|
|
Source Clock Delay (SCD): -0.693ns
|
|
Clock Pessimism Removal (CPR): -0.045ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock mlkem_clk_clk_pll rise edge)
|
|
0.000 0.000 r
|
|
K21 0.000 0.000 r clk (IN)
|
|
net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1
|
|
K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O
|
|
net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll
|
|
PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2)
|
|
-2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2
|
|
net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll
|
|
BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout3_buf/O
|
|
net (fo=26129, routed) 0.570 -0.693 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/mlkem_clk
|
|
SLICE_X89Y155 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/wb_a_data_r_reg[4]/C
|
|
------------------------------------------------------------------- -------------------
|
|
SLICE_X89Y155 FDCE (Prop_fdce_C_Q) 0.141 -0.552 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/wb_a_data_r_reg[4]/Q
|
|
net (fo=234, routed) 0.332 -0.220 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/wb_a_data_r[4]
|
|
SLICE_X92Y145 LUT6 (Prop_lut6_I3_O) 0.045 -0.175 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/cr[240][4]_i_1/O
|
|
net (fo=1, routed) 0.000 -0.175 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/cr[240][4]_i_1_n_0
|
|
SLICE_X92Y145 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/cr_reg[240][4]/D
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock mlkem_clk_clk_pll rise edge)
|
|
0.000 0.000 r
|
|
K21 0.000 0.000 r clk (IN)
|
|
net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1
|
|
K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O
|
|
net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll
|
|
PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2)
|
|
-2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2
|
|
net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll
|
|
BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout3_buf/O
|
|
net (fo=26129, routed) 0.852 -0.456 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/mlkem_clk
|
|
SLICE_X92Y145 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/cr_reg[240][4]/C
|
|
clock pessimism 0.045 -0.411
|
|
SLICE_X92Y145 FDCE (Hold_fdce_C_D) 0.121 -0.290 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/cr_reg[240][4]
|
|
-------------------------------------------------------------------
|
|
required time 0.290
|
|
arrival time -0.175
|
|
-------------------------------------------------------------------
|
|
slack 0.115
|
|
|
|
Slack (MET) : 0.116ns (arrival time - required time)
|
|
Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_scl/r1_s6_reg[6]/C
|
|
(rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns})
|
|
Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_scl/product_r_reg[6]/D
|
|
(rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns})
|
|
Path Group: mlkem_clk_clk_pll
|
|
Path Type: Hold (Min at Fast Process Corner)
|
|
Requirement: 0.000ns (mlkem_clk_clk_pll rise@0.000ns - mlkem_clk_clk_pll rise@0.000ns)
|
|
Data Path Delay: 0.474ns (logic 0.226ns (47.682%) route 0.248ns (52.318%))
|
|
Logic Levels: 1 (LUT3=1)
|
|
Clock Path Skew: 0.266ns (DCD - SCD - CPR)
|
|
Destination Clock Delay (DCD): -0.478ns
|
|
Source Clock Delay (SCD): -0.704ns
|
|
Clock Pessimism Removal (CPR): -0.040ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock mlkem_clk_clk_pll rise edge)
|
|
0.000 0.000 r
|
|
K21 0.000 0.000 r clk (IN)
|
|
net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1
|
|
K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O
|
|
net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll
|
|
PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2)
|
|
-2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2
|
|
net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll
|
|
BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout3_buf/O
|
|
net (fo=26129, routed) 0.559 -0.704 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_scl/mlkem_clk
|
|
SLICE_X81Y162 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_scl/r1_s6_reg[6]/C
|
|
------------------------------------------------------------------- -------------------
|
|
SLICE_X81Y162 FDCE (Prop_fdce_C_Q) 0.128 -0.576 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_scl/r1_s6_reg[6]/Q
|
|
net (fo=4, routed) 0.248 -0.328 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_scl/r1_s6_reg_n_0_[6]
|
|
SLICE_X87Y160 LUT3 (Prop_lut3_I0_O) 0.098 -0.230 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_scl/product_r[6]_i_1__0/O
|
|
net (fo=1, routed) 0.000 -0.230 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_scl/product_r[6]_i_1__0_n_0
|
|
SLICE_X87Y160 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_scl/product_r_reg[6]/D
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock mlkem_clk_clk_pll rise edge)
|
|
0.000 0.000 r
|
|
K21 0.000 0.000 r clk (IN)
|
|
net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1
|
|
K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O
|
|
net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll
|
|
PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2)
|
|
-2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2
|
|
net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll
|
|
BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout3_buf/O
|
|
net (fo=26129, routed) 0.830 -0.478 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_scl/mlkem_clk
|
|
SLICE_X87Y160 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_scl/product_r_reg[6]/C
|
|
clock pessimism 0.040 -0.438
|
|
SLICE_X87Y160 FDCE (Hold_fdce_C_D) 0.092 -0.346 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_scl/product_r_reg[6]
|
|
-------------------------------------------------------------------
|
|
required time 0.346
|
|
arrival time -0.230
|
|
-------------------------------------------------------------------
|
|
slack 0.116
|
|
|
|
Slack (MET) : 0.120ns (arrival time - required time)
|
|
Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/q_s3_reg[12]/C
|
|
(rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns})
|
|
Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/qprod_s4_reg[13]/D
|
|
(rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns})
|
|
Path Group: mlkem_clk_clk_pll
|
|
Path Type: Hold (Min at Fast Process Corner)
|
|
Requirement: 0.000ns (mlkem_clk_clk_pll rise@0.000ns - mlkem_clk_clk_pll rise@0.000ns)
|
|
Data Path Delay: 0.519ns (logic 0.252ns (48.552%) route 0.267ns (51.448%))
|
|
Logic Levels: 2 (CARRY4=1 LUT5=1)
|
|
Clock Path Skew: 0.265ns (DCD - SCD - CPR)
|
|
Destination Clock Delay (DCD): -0.477ns
|
|
Source Clock Delay (SCD): -0.702ns
|
|
Clock Pessimism Removal (CPR): -0.040ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock mlkem_clk_clk_pll rise edge)
|
|
0.000 0.000 r
|
|
K21 0.000 0.000 r clk (IN)
|
|
net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1
|
|
K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O
|
|
net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll
|
|
PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2)
|
|
-2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2
|
|
net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll
|
|
BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout3_buf/O
|
|
net (fo=26129, routed) 0.561 -0.702 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/mlkem_clk
|
|
SLICE_X82Y156 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/q_s3_reg[12]/C
|
|
------------------------------------------------------------------- -------------------
|
|
SLICE_X82Y156 FDCE (Prop_fdce_C_Q) 0.141 -0.561 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/q_s3_reg[12]/Q
|
|
net (fo=7, routed) 0.267 -0.294 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/q_s3_reg[12]_0[10]
|
|
SLICE_X84Y157 LUT5 (Prop_lut5_I0_O) 0.045 -0.249 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/qprod_s4[15]_i_8/O
|
|
net (fo=1, routed) 0.000 -0.249 u_fft_mlkem_axi_slave_n_122
|
|
SLICE_X84Y157 CARRY4 (Prop_carry4_S[1]_O[1])
|
|
0.066 -0.183 r u_bf/u_barrett/qprod_s4_reg[15]_i_1/O[1]
|
|
net (fo=1, routed) 0.000 -0.183 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/qprod_s4_reg[23]_1[5]
|
|
SLICE_X84Y157 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/qprod_s4_reg[13]/D
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock mlkem_clk_clk_pll rise edge)
|
|
0.000 0.000 r
|
|
K21 0.000 0.000 r clk (IN)
|
|
net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1
|
|
K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O
|
|
net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll
|
|
PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2)
|
|
-2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2
|
|
net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll
|
|
BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout3_buf/O
|
|
net (fo=26129, routed) 0.831 -0.477 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/mlkem_clk
|
|
SLICE_X84Y157 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/qprod_s4_reg[13]/C
|
|
clock pessimism 0.040 -0.437
|
|
SLICE_X84Y157 FDCE (Hold_fdce_C_D) 0.134 -0.303 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/qprod_s4_reg[13]
|
|
-------------------------------------------------------------------
|
|
required time 0.303
|
|
arrival time -0.183
|
|
-------------------------------------------------------------------
|
|
slack 0.120
|
|
|
|
Slack (MET) : 0.121ns (arrival time - required time)
|
|
Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/pushToPopGray_buffercc/buffers_0_reg[2]/C
|
|
(rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns})
|
|
Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/pushToPopGray_buffercc/buffers_1_reg[2]/D
|
|
(rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns})
|
|
Path Group: mlkem_clk_clk_pll
|
|
Path Type: Hold (Min at Fast Process Corner)
|
|
Requirement: 0.000ns (mlkem_clk_clk_pll rise@0.000ns - mlkem_clk_clk_pll rise@0.000ns)
|
|
Data Path Delay: 0.197ns (logic 0.141ns (71.611%) route 0.056ns (28.389%))
|
|
Logic Levels: 0
|
|
Clock Path Skew: 0.000ns (DCD - SCD - CPR)
|
|
Destination Clock Delay (DCD): -0.353ns
|
|
Source Clock Delay (SCD): -0.581ns
|
|
Clock Pessimism Removal (CPR): 0.228ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock mlkem_clk_clk_pll rise edge)
|
|
0.000 0.000 r
|
|
K21 0.000 0.000 r clk (IN)
|
|
net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1
|
|
K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O
|
|
net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll
|
|
PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2)
|
|
-2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2
|
|
net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll
|
|
BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout3_buf/O
|
|
net (fo=26129, routed) 0.681 -0.581 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/pushToPopGray_buffercc/mlkem_clk
|
|
SLICE_X27Y79 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/pushToPopGray_buffercc/buffers_0_reg[2]/C
|
|
------------------------------------------------------------------- -------------------
|
|
SLICE_X27Y79 FDCE (Prop_fdce_C_Q) 0.141 -0.440 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/pushToPopGray_buffercc/buffers_0_reg[2]/Q
|
|
net (fo=1, routed) 0.056 -0.384 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/pushToPopGray_buffercc/buffers_0[2]
|
|
SLICE_X27Y79 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/pushToPopGray_buffercc/buffers_1_reg[2]/D
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock mlkem_clk_clk_pll rise edge)
|
|
0.000 0.000 r
|
|
K21 0.000 0.000 r clk (IN)
|
|
net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1
|
|
K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O
|
|
net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll
|
|
PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2)
|
|
-2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2
|
|
net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll
|
|
BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout3_buf/O
|
|
net (fo=26129, routed) 0.955 -0.353 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/pushToPopGray_buffercc/mlkem_clk
|
|
SLICE_X27Y79 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/pushToPopGray_buffercc/buffers_1_reg[2]/C
|
|
clock pessimism -0.228 -0.581
|
|
SLICE_X27Y79 FDCE (Hold_fdce_C_D) 0.076 -0.505 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/pushToPopGray_buffercc/buffers_1_reg[2]
|
|
-------------------------------------------------------------------
|
|
required time 0.505
|
|
arrival time -0.384
|
|
-------------------------------------------------------------------
|
|
slack 0.121
|
|
|
|
Slack (MET) : 0.121ns (arrival time - required time)
|
|
Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/popToPushGray_buffercc/buffers_0_reg[2]/C
|
|
(rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns})
|
|
Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/popToPushGray_buffercc/buffers_1_reg[2]/D
|
|
(rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns})
|
|
Path Group: mlkem_clk_clk_pll
|
|
Path Type: Hold (Min at Fast Process Corner)
|
|
Requirement: 0.000ns (mlkem_clk_clk_pll rise@0.000ns - mlkem_clk_clk_pll rise@0.000ns)
|
|
Data Path Delay: 0.197ns (logic 0.141ns (71.611%) route 0.056ns (28.389%))
|
|
Logic Levels: 0
|
|
Clock Path Skew: 0.000ns (DCD - SCD - CPR)
|
|
Destination Clock Delay (DCD): -0.355ns
|
|
Source Clock Delay (SCD): -0.582ns
|
|
Clock Pessimism Removal (CPR): 0.227ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock mlkem_clk_clk_pll rise edge)
|
|
0.000 0.000 r
|
|
K21 0.000 0.000 r clk (IN)
|
|
net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1
|
|
K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O
|
|
net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll
|
|
PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2)
|
|
-2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2
|
|
net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll
|
|
BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout3_buf/O
|
|
net (fo=26129, routed) 0.680 -0.582 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/popToPushGray_buffercc/mlkem_clk
|
|
SLICE_X27Y72 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/popToPushGray_buffercc/buffers_0_reg[2]/C
|
|
------------------------------------------------------------------- -------------------
|
|
SLICE_X27Y72 FDCE (Prop_fdce_C_Q) 0.141 -0.441 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/popToPushGray_buffercc/buffers_0_reg[2]/Q
|
|
net (fo=1, routed) 0.056 -0.385 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/popToPushGray_buffercc/buffers_0[2]
|
|
SLICE_X27Y72 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/popToPushGray_buffercc/buffers_1_reg[2]/D
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock mlkem_clk_clk_pll rise edge)
|
|
0.000 0.000 r
|
|
K21 0.000 0.000 r clk (IN)
|
|
net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1
|
|
K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O
|
|
net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll
|
|
PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2)
|
|
-2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2
|
|
net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll
|
|
BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout3_buf/O
|
|
net (fo=26129, routed) 0.953 -0.355 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/popToPushGray_buffercc/mlkem_clk
|
|
SLICE_X27Y72 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/popToPushGray_buffercc/buffers_1_reg[2]/C
|
|
clock pessimism -0.227 -0.582
|
|
SLICE_X27Y72 FDCE (Hold_fdce_C_D) 0.076 -0.506 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/popToPushGray_buffercc/buffers_1_reg[2]
|
|
-------------------------------------------------------------------
|
|
required time 0.506
|
|
arrival time -0.385
|
|
-------------------------------------------------------------------
|
|
slack 0.121
|
|
|
|
Slack (MET) : 0.122ns (arrival time - required time)
|
|
Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/pushToPopGray_buffercc/buffers_0_reg[0]/C
|
|
(rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns})
|
|
Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/pushToPopGray_buffercc/buffers_1_reg[0]/D
|
|
(rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns})
|
|
Path Group: mlkem_clk_clk_pll
|
|
Path Type: Hold (Min at Fast Process Corner)
|
|
Requirement: 0.000ns (mlkem_clk_clk_pll rise@0.000ns - mlkem_clk_clk_pll rise@0.000ns)
|
|
Data Path Delay: 0.197ns (logic 0.141ns (71.611%) route 0.056ns (28.389%))
|
|
Logic Levels: 0
|
|
Clock Path Skew: 0.000ns (DCD - SCD - CPR)
|
|
Destination Clock Delay (DCD): -0.353ns
|
|
Source Clock Delay (SCD): -0.581ns
|
|
Clock Pessimism Removal (CPR): 0.228ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock mlkem_clk_clk_pll rise edge)
|
|
0.000 0.000 r
|
|
K21 0.000 0.000 r clk (IN)
|
|
net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1
|
|
K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O
|
|
net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll
|
|
PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2)
|
|
-2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2
|
|
net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll
|
|
BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout3_buf/O
|
|
net (fo=26129, routed) 0.681 -0.581 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/pushToPopGray_buffercc/mlkem_clk
|
|
SLICE_X27Y79 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/pushToPopGray_buffercc/buffers_0_reg[0]/C
|
|
------------------------------------------------------------------- -------------------
|
|
SLICE_X27Y79 FDCE (Prop_fdce_C_Q) 0.141 -0.440 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/pushToPopGray_buffercc/buffers_0_reg[0]/Q
|
|
net (fo=1, routed) 0.056 -0.384 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/pushToPopGray_buffercc/buffers_0[0]
|
|
SLICE_X27Y79 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/pushToPopGray_buffercc/buffers_1_reg[0]/D
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock mlkem_clk_clk_pll rise edge)
|
|
0.000 0.000 r
|
|
K21 0.000 0.000 r clk (IN)
|
|
net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1
|
|
K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O
|
|
net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll
|
|
PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2)
|
|
-2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2
|
|
net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll
|
|
BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout3_buf/O
|
|
net (fo=26129, routed) 0.955 -0.353 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/pushToPopGray_buffercc/mlkem_clk
|
|
SLICE_X27Y79 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/pushToPopGray_buffercc/buffers_1_reg[0]/C
|
|
clock pessimism -0.228 -0.581
|
|
SLICE_X27Y79 FDCE (Hold_fdce_C_D) 0.075 -0.506 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/pushToPopGray_buffercc/buffers_1_reg[0]
|
|
-------------------------------------------------------------------
|
|
required time 0.506
|
|
arrival time -0.384
|
|
-------------------------------------------------------------------
|
|
slack 0.122
|
|
|
|
Slack (MET) : 0.122ns (arrival time - required time)
|
|
Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/buffers_0_reg/C
|
|
(rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns})
|
|
Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/buffers_1_reg/D
|
|
(rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns})
|
|
Path Group: mlkem_clk_clk_pll
|
|
Path Type: Hold (Min at Fast Process Corner)
|
|
Requirement: 0.000ns (mlkem_clk_clk_pll rise@0.000ns - mlkem_clk_clk_pll rise@0.000ns)
|
|
Data Path Delay: 0.197ns (logic 0.141ns (71.611%) route 0.056ns (28.389%))
|
|
Logic Levels: 0
|
|
Clock Path Skew: 0.000ns (DCD - SCD - CPR)
|
|
Destination Clock Delay (DCD): -0.353ns
|
|
Source Clock Delay (SCD): -0.581ns
|
|
Clock Pessimism Removal (CPR): 0.228ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock mlkem_clk_clk_pll rise edge)
|
|
0.000 0.000 r
|
|
K21 0.000 0.000 r clk (IN)
|
|
net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1
|
|
K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O
|
|
net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll
|
|
PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2)
|
|
-2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2
|
|
net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll
|
|
BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout3_buf/O
|
|
net (fo=26129, routed) 0.681 -0.581 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/mlkem_clk
|
|
SLICE_X25Y79 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/buffers_0_reg/C
|
|
------------------------------------------------------------------- -------------------
|
|
SLICE_X25Y79 FDCE (Prop_fdce_C_Q) 0.141 -0.440 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/buffers_0_reg/Q
|
|
net (fo=1, routed) 0.056 -0.384 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/buffers_0
|
|
SLICE_X25Y79 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/buffers_1_reg/D
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock mlkem_clk_clk_pll rise edge)
|
|
0.000 0.000 r
|
|
K21 0.000 0.000 r clk (IN)
|
|
net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1
|
|
K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O
|
|
net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll
|
|
PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2)
|
|
-2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2
|
|
net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll
|
|
BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout3_buf/O
|
|
net (fo=26129, routed) 0.955 -0.353 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/mlkem_clk
|
|
SLICE_X25Y79 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/buffers_1_reg/C
|
|
clock pessimism -0.228 -0.581
|
|
SLICE_X25Y79 FDCE (Hold_fdce_C_D) 0.075 -0.506 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/buffers_1_reg
|
|
-------------------------------------------------------------------
|
|
required time 0.506
|
|
arrival time -0.384
|
|
-------------------------------------------------------------------
|
|
slack 0.122
|
|
|
|
Slack (MET) : 0.122ns (arrival time - required time)
|
|
Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/popToPushGray_buffercc/buffers_0_reg[0]/C
|
|
(rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns})
|
|
Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/popToPushGray_buffercc/buffers_1_reg[0]/D
|
|
(rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns})
|
|
Path Group: mlkem_clk_clk_pll
|
|
Path Type: Hold (Min at Fast Process Corner)
|
|
Requirement: 0.000ns (mlkem_clk_clk_pll rise@0.000ns - mlkem_clk_clk_pll rise@0.000ns)
|
|
Data Path Delay: 0.197ns (logic 0.141ns (71.611%) route 0.056ns (28.389%))
|
|
Logic Levels: 0
|
|
Clock Path Skew: 0.000ns (DCD - SCD - CPR)
|
|
Destination Clock Delay (DCD): -0.355ns
|
|
Source Clock Delay (SCD): -0.582ns
|
|
Clock Pessimism Removal (CPR): 0.227ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock mlkem_clk_clk_pll rise edge)
|
|
0.000 0.000 r
|
|
K21 0.000 0.000 r clk (IN)
|
|
net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1
|
|
K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O
|
|
net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll
|
|
PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2)
|
|
-2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2
|
|
net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll
|
|
BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout3_buf/O
|
|
net (fo=26129, routed) 0.680 -0.582 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/popToPushGray_buffercc/mlkem_clk
|
|
SLICE_X27Y72 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/popToPushGray_buffercc/buffers_0_reg[0]/C
|
|
------------------------------------------------------------------- -------------------
|
|
SLICE_X27Y72 FDCE (Prop_fdce_C_Q) 0.141 -0.441 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/popToPushGray_buffercc/buffers_0_reg[0]/Q
|
|
net (fo=1, routed) 0.056 -0.385 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/popToPushGray_buffercc/buffers_0[0]
|
|
SLICE_X27Y72 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/popToPushGray_buffercc/buffers_1_reg[0]/D
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock mlkem_clk_clk_pll rise edge)
|
|
0.000 0.000 r
|
|
K21 0.000 0.000 r clk (IN)
|
|
net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1
|
|
K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O
|
|
net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll
|
|
PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2)
|
|
-2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2
|
|
net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll
|
|
BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout3_buf/O
|
|
net (fo=26129, routed) 0.953 -0.355 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/popToPushGray_buffercc/mlkem_clk
|
|
SLICE_X27Y72 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/popToPushGray_buffercc/buffers_1_reg[0]/C
|
|
clock pessimism -0.227 -0.582
|
|
SLICE_X27Y72 FDCE (Hold_fdce_C_D) 0.075 -0.507 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/popToPushGray_buffercc/buffers_1_reg[0]
|
|
-------------------------------------------------------------------
|
|
required time 0.507
|
|
arrival time -0.385
|
|
-------------------------------------------------------------------
|
|
slack 0.122
|
|
|
|
Slack (MET) : 0.122ns (arrival time - required time)
|
|
Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/pushToPopGray_buffercc/buffers_0_reg[0]/C
|
|
(rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns})
|
|
Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/pushToPopGray_buffercc/buffers_1_reg[0]/D
|
|
(rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns})
|
|
Path Group: mlkem_clk_clk_pll
|
|
Path Type: Hold (Min at Fast Process Corner)
|
|
Requirement: 0.000ns (mlkem_clk_clk_pll rise@0.000ns - mlkem_clk_clk_pll rise@0.000ns)
|
|
Data Path Delay: 0.197ns (logic 0.141ns (71.611%) route 0.056ns (28.389%))
|
|
Logic Levels: 0
|
|
Clock Path Skew: 0.000ns (DCD - SCD - CPR)
|
|
Destination Clock Delay (DCD): -0.389ns
|
|
Source Clock Delay (SCD): -0.615ns
|
|
Clock Pessimism Removal (CPR): 0.226ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock mlkem_clk_clk_pll rise edge)
|
|
0.000 0.000 r
|
|
K21 0.000 0.000 r clk (IN)
|
|
net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1
|
|
K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O
|
|
net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll
|
|
PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2)
|
|
-2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2
|
|
net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll
|
|
BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout3_buf/O
|
|
net (fo=26129, routed) 0.647 -0.615 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/pushToPopGray_buffercc/mlkem_clk
|
|
SLICE_X115Y75 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/pushToPopGray_buffercc/buffers_0_reg[0]/C
|
|
------------------------------------------------------------------- -------------------
|
|
SLICE_X115Y75 FDCE (Prop_fdce_C_Q) 0.141 -0.474 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/pushToPopGray_buffercc/buffers_0_reg[0]/Q
|
|
net (fo=1, routed) 0.056 -0.418 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/pushToPopGray_buffercc/buffers_0[0]
|
|
SLICE_X115Y75 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/pushToPopGray_buffercc/buffers_1_reg[0]/D
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock mlkem_clk_clk_pll rise edge)
|
|
0.000 0.000 r
|
|
K21 0.000 0.000 r clk (IN)
|
|
net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1
|
|
K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O
|
|
net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll
|
|
PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2)
|
|
-2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2
|
|
net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll
|
|
BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout3_buf/O
|
|
net (fo=26129, routed) 0.919 -0.389 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/pushToPopGray_buffercc/mlkem_clk
|
|
SLICE_X115Y75 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/pushToPopGray_buffercc/buffers_1_reg[0]/C
|
|
clock pessimism -0.226 -0.615
|
|
SLICE_X115Y75 FDCE (Hold_fdce_C_D) 0.075 -0.540 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/pushToPopGray_buffercc/buffers_1_reg[0]
|
|
-------------------------------------------------------------------
|
|
required time 0.540
|
|
arrival time -0.418
|
|
-------------------------------------------------------------------
|
|
slack 0.122
|
|
|
|
Slack (MET) : 0.122ns (arrival time - required time)
|
|
Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/pushToPopGray_buffercc/buffers_0_reg[1]/C
|
|
(rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns})
|
|
Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/pushToPopGray_buffercc/buffers_1_reg[1]/D
|
|
(rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns})
|
|
Path Group: mlkem_clk_clk_pll
|
|
Path Type: Hold (Min at Fast Process Corner)
|
|
Requirement: 0.000ns (mlkem_clk_clk_pll rise@0.000ns - mlkem_clk_clk_pll rise@0.000ns)
|
|
Data Path Delay: 0.197ns (logic 0.141ns (71.611%) route 0.056ns (28.389%))
|
|
Logic Levels: 0
|
|
Clock Path Skew: 0.000ns (DCD - SCD - CPR)
|
|
Destination Clock Delay (DCD): -0.388ns
|
|
Source Clock Delay (SCD): -0.614ns
|
|
Clock Pessimism Removal (CPR): 0.226ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock mlkem_clk_clk_pll rise edge)
|
|
0.000 0.000 r
|
|
K21 0.000 0.000 r clk (IN)
|
|
net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1
|
|
K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O
|
|
net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll
|
|
PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2)
|
|
-2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2
|
|
net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll
|
|
BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout3_buf/O
|
|
net (fo=26129, routed) 0.648 -0.614 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/pushToPopGray_buffercc/mlkem_clk
|
|
SLICE_X117Y75 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/pushToPopGray_buffercc/buffers_0_reg[1]/C
|
|
------------------------------------------------------------------- -------------------
|
|
SLICE_X117Y75 FDCE (Prop_fdce_C_Q) 0.141 -0.473 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/pushToPopGray_buffercc/buffers_0_reg[1]/Q
|
|
net (fo=1, routed) 0.056 -0.417 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/pushToPopGray_buffercc/buffers_0[1]
|
|
SLICE_X117Y75 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/pushToPopGray_buffercc/buffers_1_reg[1]/D
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock mlkem_clk_clk_pll rise edge)
|
|
0.000 0.000 r
|
|
K21 0.000 0.000 r clk (IN)
|
|
net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1
|
|
K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O
|
|
net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll
|
|
PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2)
|
|
-2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2
|
|
net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll
|
|
BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout3_buf/O
|
|
net (fo=26129, routed) 0.920 -0.388 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/pushToPopGray_buffercc/mlkem_clk
|
|
SLICE_X117Y75 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/pushToPopGray_buffercc/buffers_1_reg[1]/C
|
|
clock pessimism -0.226 -0.614
|
|
SLICE_X117Y75 FDCE (Hold_fdce_C_D) 0.075 -0.539 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/pushToPopGray_buffercc/buffers_1_reg[1]
|
|
-------------------------------------------------------------------
|
|
required time 0.539
|
|
arrival time -0.417
|
|
-------------------------------------------------------------------
|
|
slack 0.122
|
|
|
|
Slack (MET) : 0.122ns (arrival time - required time)
|
|
Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/q_s3_reg[3]/C
|
|
(rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns})
|
|
Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/qprod_s4_reg[11]/D
|
|
(rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns})
|
|
Path Group: mlkem_clk_clk_pll
|
|
Path Type: Hold (Min at Fast Process Corner)
|
|
Requirement: 0.000ns (mlkem_clk_clk_pll rise@0.000ns - mlkem_clk_clk_pll rise@0.000ns)
|
|
Data Path Delay: 0.521ns (logic 0.273ns (52.394%) route 0.248ns (47.606%))
|
|
Logic Levels: 2 (CARRY4=1 LUT4=1)
|
|
Clock Path Skew: 0.265ns (DCD - SCD - CPR)
|
|
Destination Clock Delay (DCD): -0.476ns
|
|
Source Clock Delay (SCD): -0.701ns
|
|
Clock Pessimism Removal (CPR): -0.040ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock mlkem_clk_clk_pll rise edge)
|
|
0.000 0.000 r
|
|
K21 0.000 0.000 r clk (IN)
|
|
net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1
|
|
K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O
|
|
net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll
|
|
PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2)
|
|
-2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2
|
|
net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll
|
|
BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout3_buf/O
|
|
net (fo=26129, routed) 0.562 -0.701 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/mlkem_clk
|
|
SLICE_X80Y155 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/q_s3_reg[3]/C
|
|
------------------------------------------------------------------- -------------------
|
|
SLICE_X80Y155 FDCE (Prop_fdce_C_Q) 0.164 -0.537 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/q_s3_reg[3]/Q
|
|
net (fo=6, routed) 0.248 -0.289 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/q_s3_reg[12]_0[3]
|
|
SLICE_X84Y156 LUT4 (Prop_lut4_I1_O) 0.045 -0.244 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/qprod_s4[11]_i_5/O
|
|
net (fo=1, routed) 0.000 -0.244 u_fft_mlkem_axi_slave_n_417
|
|
SLICE_X84Y156 CARRY4 (Prop_carry4_S[3]_O[3])
|
|
0.064 -0.180 r u_bf/u_barrett/qprod_s4_reg[11]_i_1/O[3]
|
|
net (fo=1, routed) 0.000 -0.180 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/qprod_s4_reg[23]_1[3]
|
|
SLICE_X84Y156 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/qprod_s4_reg[11]/D
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock mlkem_clk_clk_pll rise edge)
|
|
0.000 0.000 r
|
|
K21 0.000 0.000 r clk (IN)
|
|
net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1
|
|
K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O
|
|
net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll
|
|
PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2)
|
|
-2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2
|
|
net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll
|
|
BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout3_buf/O
|
|
net (fo=26129, routed) 0.831 -0.476 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/mlkem_clk
|
|
SLICE_X84Y156 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/qprod_s4_reg[11]/C
|
|
clock pessimism 0.040 -0.436
|
|
SLICE_X84Y156 FDCE (Hold_fdce_C_D) 0.134 -0.302 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/qprod_s4_reg[11]
|
|
-------------------------------------------------------------------
|
|
required time 0.302
|
|
arrival time -0.180
|
|
-------------------------------------------------------------------
|
|
slack 0.122
|
|
|
|
Slack (MET) : 0.126ns (arrival time - required time)
|
|
Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/qprod_s4_reg[11]/C
|
|
(rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns})
|
|
Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[11]/D
|
|
(rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns})
|
|
Path Group: mlkem_clk_clk_pll
|
|
Path Type: Hold (Min at Fast Process Corner)
|
|
Requirement: 0.000ns (mlkem_clk_clk_pll rise@0.000ns - mlkem_clk_clk_pll rise@0.000ns)
|
|
Data Path Delay: 0.494ns (logic 0.272ns (55.014%) route 0.222ns (44.986%))
|
|
Logic Levels: 2 (CARRY4=1 LUT2=1)
|
|
Clock Path Skew: 0.264ns (DCD - SCD - CPR)
|
|
Destination Clock Delay (DCD): -0.477ns
|
|
Source Clock Delay (SCD): -0.701ns
|
|
Clock Pessimism Removal (CPR): -0.040ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock mlkem_clk_clk_pll rise edge)
|
|
0.000 0.000 r
|
|
K21 0.000 0.000 r clk (IN)
|
|
net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1
|
|
K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O
|
|
net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll
|
|
PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2)
|
|
-2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2
|
|
net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll
|
|
BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout3_buf/O
|
|
net (fo=26129, routed) 0.562 -0.701 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/mlkem_clk
|
|
SLICE_X84Y156 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/qprod_s4_reg[11]/C
|
|
------------------------------------------------------------------- -------------------
|
|
SLICE_X84Y156 FDCE (Prop_fdce_C_Q) 0.164 -0.537 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/qprod_s4_reg[11]/Q
|
|
net (fo=1, routed) 0.222 -0.314 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/qprod_s4[11]
|
|
SLICE_X83Y156 LUT2 (Prop_lut2_I1_O) 0.045 -0.269 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5[11]_i_2/O
|
|
net (fo=1, routed) 0.000 -0.269 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5[11]_i_2_n_0
|
|
SLICE_X83Y156 CARRY4 (Prop_carry4_S[3]_O[3])
|
|
0.063 -0.206 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[11]_i_1/O[3]
|
|
net (fo=1, routed) 0.000 -0.206 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s50[11]
|
|
SLICE_X83Y156 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[11]/D
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock mlkem_clk_clk_pll rise edge)
|
|
0.000 0.000 r
|
|
K21 0.000 0.000 r clk (IN)
|
|
net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1
|
|
K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O
|
|
net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll
|
|
PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2)
|
|
-2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2
|
|
net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll
|
|
BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout3_buf/O
|
|
net (fo=26129, routed) 0.831 -0.477 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/mlkem_clk
|
|
SLICE_X83Y156 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[11]/C
|
|
clock pessimism 0.040 -0.437
|
|
SLICE_X83Y156 FDCE (Hold_fdce_C_D) 0.105 -0.332 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[11]
|
|
-------------------------------------------------------------------
|
|
required time 0.332
|
|
arrival time -0.206
|
|
-------------------------------------------------------------------
|
|
slack 0.126
|
|
|
|
Slack (MET) : 0.126ns (arrival time - required time)
|
|
Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/qprod_s4_reg[15]/C
|
|
(rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns})
|
|
Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[15]/D
|
|
(rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns})
|
|
Path Group: mlkem_clk_clk_pll
|
|
Path Type: Hold (Min at Fast Process Corner)
|
|
Requirement: 0.000ns (mlkem_clk_clk_pll rise@0.000ns - mlkem_clk_clk_pll rise@0.000ns)
|
|
Data Path Delay: 0.494ns (logic 0.272ns (55.014%) route 0.222ns (44.986%))
|
|
Logic Levels: 2 (CARRY4=1 LUT2=1)
|
|
Clock Path Skew: 0.264ns (DCD - SCD - CPR)
|
|
Destination Clock Delay (DCD): -0.478ns
|
|
Source Clock Delay (SCD): -0.702ns
|
|
Clock Pessimism Removal (CPR): -0.040ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock mlkem_clk_clk_pll rise edge)
|
|
0.000 0.000 r
|
|
K21 0.000 0.000 r clk (IN)
|
|
net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1
|
|
K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O
|
|
net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll
|
|
PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2)
|
|
-2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2
|
|
net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll
|
|
BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout3_buf/O
|
|
net (fo=26129, routed) 0.561 -0.702 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/mlkem_clk
|
|
SLICE_X84Y157 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/qprod_s4_reg[15]/C
|
|
------------------------------------------------------------------- -------------------
|
|
SLICE_X84Y157 FDCE (Prop_fdce_C_Q) 0.164 -0.538 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/qprod_s4_reg[15]/Q
|
|
net (fo=1, routed) 0.222 -0.315 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/qprod_s4[15]
|
|
SLICE_X83Y157 LUT2 (Prop_lut2_I1_O) 0.045 -0.270 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5[15]_i_2/O
|
|
net (fo=1, routed) 0.000 -0.270 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5[15]_i_2_n_0
|
|
SLICE_X83Y157 CARRY4 (Prop_carry4_S[3]_O[3])
|
|
0.063 -0.207 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[15]_i_1/O[3]
|
|
net (fo=1, routed) 0.000 -0.207 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s50[15]
|
|
SLICE_X83Y157 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[15]/D
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock mlkem_clk_clk_pll rise edge)
|
|
0.000 0.000 r
|
|
K21 0.000 0.000 r clk (IN)
|
|
net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1
|
|
K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O
|
|
net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll
|
|
PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2)
|
|
-2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2
|
|
net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll
|
|
BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout3_buf/O
|
|
net (fo=26129, routed) 0.830 -0.478 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/mlkem_clk
|
|
SLICE_X83Y157 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[15]/C
|
|
clock pessimism 0.040 -0.438
|
|
SLICE_X83Y157 FDCE (Hold_fdce_C_D) 0.105 -0.333 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[15]
|
|
-------------------------------------------------------------------
|
|
required time 0.333
|
|
arrival time -0.207
|
|
-------------------------------------------------------------------
|
|
slack 0.126
|
|
|
|
Slack (MET) : 0.126ns (arrival time - required time)
|
|
Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/qprod_s4_reg[19]/C
|
|
(rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns})
|
|
Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[19]/D
|
|
(rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns})
|
|
Path Group: mlkem_clk_clk_pll
|
|
Path Type: Hold (Min at Fast Process Corner)
|
|
Requirement: 0.000ns (mlkem_clk_clk_pll rise@0.000ns - mlkem_clk_clk_pll rise@0.000ns)
|
|
Data Path Delay: 0.494ns (logic 0.272ns (55.014%) route 0.222ns (44.986%))
|
|
Logic Levels: 2 (CARRY4=1 LUT2=1)
|
|
Clock Path Skew: 0.264ns (DCD - SCD - CPR)
|
|
Destination Clock Delay (DCD): -0.478ns
|
|
Source Clock Delay (SCD): -0.702ns
|
|
Clock Pessimism Removal (CPR): -0.040ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock mlkem_clk_clk_pll rise edge)
|
|
0.000 0.000 r
|
|
K21 0.000 0.000 r clk (IN)
|
|
net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1
|
|
K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O
|
|
net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll
|
|
PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2)
|
|
-2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2
|
|
net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll
|
|
BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout3_buf/O
|
|
net (fo=26129, routed) 0.561 -0.702 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/mlkem_clk
|
|
SLICE_X84Y158 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/qprod_s4_reg[19]/C
|
|
------------------------------------------------------------------- -------------------
|
|
SLICE_X84Y158 FDCE (Prop_fdce_C_Q) 0.164 -0.538 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/qprod_s4_reg[19]/Q
|
|
net (fo=1, routed) 0.222 -0.315 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/qprod_s4[19]
|
|
SLICE_X83Y158 LUT2 (Prop_lut2_I1_O) 0.045 -0.270 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5[19]_i_2/O
|
|
net (fo=1, routed) 0.000 -0.270 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5[19]_i_2_n_0
|
|
SLICE_X83Y158 CARRY4 (Prop_carry4_S[3]_O[3])
|
|
0.063 -0.207 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[19]_i_1/O[3]
|
|
net (fo=1, routed) 0.000 -0.207 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s50[19]
|
|
SLICE_X83Y158 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[19]/D
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock mlkem_clk_clk_pll rise edge)
|
|
0.000 0.000 r
|
|
K21 0.000 0.000 r clk (IN)
|
|
net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1
|
|
K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O
|
|
net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll
|
|
PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2)
|
|
-2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2
|
|
net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll
|
|
BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout3_buf/O
|
|
net (fo=26129, routed) 0.830 -0.478 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/mlkem_clk
|
|
SLICE_X83Y158 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[19]/C
|
|
clock pessimism 0.040 -0.438
|
|
SLICE_X83Y158 FDCE (Hold_fdce_C_D) 0.105 -0.333 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[19]
|
|
-------------------------------------------------------------------
|
|
required time 0.333
|
|
arrival time -0.207
|
|
-------------------------------------------------------------------
|
|
slack 0.126
|
|
|
|
Slack (MET) : 0.126ns (arrival time - required time)
|
|
Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/qprod_s4_reg[23]/C
|
|
(rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns})
|
|
Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[23]/D
|
|
(rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns})
|
|
Path Group: mlkem_clk_clk_pll
|
|
Path Type: Hold (Min at Fast Process Corner)
|
|
Requirement: 0.000ns (mlkem_clk_clk_pll rise@0.000ns - mlkem_clk_clk_pll rise@0.000ns)
|
|
Data Path Delay: 0.494ns (logic 0.272ns (55.014%) route 0.222ns (44.986%))
|
|
Logic Levels: 2 (CARRY4=1 LUT2=1)
|
|
Clock Path Skew: 0.264ns (DCD - SCD - CPR)
|
|
Destination Clock Delay (DCD): -0.478ns
|
|
Source Clock Delay (SCD): -0.702ns
|
|
Clock Pessimism Removal (CPR): -0.040ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock mlkem_clk_clk_pll rise edge)
|
|
0.000 0.000 r
|
|
K21 0.000 0.000 r clk (IN)
|
|
net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1
|
|
K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O
|
|
net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll
|
|
PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2)
|
|
-2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2
|
|
net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll
|
|
BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout3_buf/O
|
|
net (fo=26129, routed) 0.561 -0.702 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/mlkem_clk
|
|
SLICE_X84Y159 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/qprod_s4_reg[23]/C
|
|
------------------------------------------------------------------- -------------------
|
|
SLICE_X84Y159 FDCE (Prop_fdce_C_Q) 0.164 -0.538 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/qprod_s4_reg[23]/Q
|
|
net (fo=1, routed) 0.222 -0.315 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/qprod_s4[23]
|
|
SLICE_X83Y159 LUT2 (Prop_lut2_I1_O) 0.045 -0.270 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5[23]_i_2/O
|
|
net (fo=1, routed) 0.000 -0.270 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5[23]_i_2_n_0
|
|
SLICE_X83Y159 CARRY4 (Prop_carry4_S[3]_O[3])
|
|
0.063 -0.207 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[23]_i_1/O[3]
|
|
net (fo=1, routed) 0.000 -0.207 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s50[23]
|
|
SLICE_X83Y159 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[23]/D
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock mlkem_clk_clk_pll rise edge)
|
|
0.000 0.000 r
|
|
K21 0.000 0.000 r clk (IN)
|
|
net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1
|
|
K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O
|
|
net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll
|
|
PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2)
|
|
-2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2
|
|
net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll
|
|
BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout3_buf/O
|
|
net (fo=26129, routed) 0.830 -0.478 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/mlkem_clk
|
|
SLICE_X83Y159 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[23]/C
|
|
clock pessimism 0.040 -0.438
|
|
SLICE_X83Y159 FDCE (Hold_fdce_C_D) 0.105 -0.333 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[23]
|
|
-------------------------------------------------------------------
|
|
required time 0.333
|
|
arrival time -0.207
|
|
-------------------------------------------------------------------
|
|
slack 0.126
|
|
|
|
Slack (MET) : 0.126ns (arrival time - required time)
|
|
Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/pushToPopGray_buffercc/buffers_0_reg[1]/C
|
|
(rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns})
|
|
Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/pushToPopGray_buffercc/buffers_1_reg[1]/D
|
|
(rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns})
|
|
Path Group: mlkem_clk_clk_pll
|
|
Path Type: Hold (Min at Fast Process Corner)
|
|
Requirement: 0.000ns (mlkem_clk_clk_pll rise@0.000ns - mlkem_clk_clk_pll rise@0.000ns)
|
|
Data Path Delay: 0.197ns (logic 0.141ns (71.611%) route 0.056ns (28.389%))
|
|
Logic Levels: 0
|
|
Clock Path Skew: 0.000ns (DCD - SCD - CPR)
|
|
Destination Clock Delay (DCD): -0.353ns
|
|
Source Clock Delay (SCD): -0.581ns
|
|
Clock Pessimism Removal (CPR): 0.228ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock mlkem_clk_clk_pll rise edge)
|
|
0.000 0.000 r
|
|
K21 0.000 0.000 r clk (IN)
|
|
net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1
|
|
K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O
|
|
net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll
|
|
PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2)
|
|
-2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2
|
|
net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll
|
|
BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout3_buf/O
|
|
net (fo=26129, routed) 0.681 -0.581 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/pushToPopGray_buffercc/mlkem_clk
|
|
SLICE_X27Y79 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/pushToPopGray_buffercc/buffers_0_reg[1]/C
|
|
------------------------------------------------------------------- -------------------
|
|
SLICE_X27Y79 FDCE (Prop_fdce_C_Q) 0.141 -0.440 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/pushToPopGray_buffercc/buffers_0_reg[1]/Q
|
|
net (fo=1, routed) 0.056 -0.384 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/pushToPopGray_buffercc/buffers_0[1]
|
|
SLICE_X27Y79 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/pushToPopGray_buffercc/buffers_1_reg[1]/D
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock mlkem_clk_clk_pll rise edge)
|
|
0.000 0.000 r
|
|
K21 0.000 0.000 r clk (IN)
|
|
net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1
|
|
K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O
|
|
net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll
|
|
PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2)
|
|
-2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2
|
|
net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll
|
|
BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout3_buf/O
|
|
net (fo=26129, routed) 0.955 -0.353 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/pushToPopGray_buffercc/mlkem_clk
|
|
SLICE_X27Y79 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/pushToPopGray_buffercc/buffers_1_reg[1]/C
|
|
clock pessimism -0.228 -0.581
|
|
SLICE_X27Y79 FDCE (Hold_fdce_C_D) 0.071 -0.510 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/pushToPopGray_buffercc/buffers_1_reg[1]
|
|
-------------------------------------------------------------------
|
|
required time 0.510
|
|
arrival time -0.384
|
|
-------------------------------------------------------------------
|
|
slack 0.126
|
|
|
|
Slack (MET) : 0.126ns (arrival time - required time)
|
|
Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/popToPushGray_buffercc/buffers_0_reg[1]/C
|
|
(rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns})
|
|
Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/popToPushGray_buffercc/buffers_1_reg[1]/D
|
|
(rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns})
|
|
Path Group: mlkem_clk_clk_pll
|
|
Path Type: Hold (Min at Fast Process Corner)
|
|
Requirement: 0.000ns (mlkem_clk_clk_pll rise@0.000ns - mlkem_clk_clk_pll rise@0.000ns)
|
|
Data Path Delay: 0.197ns (logic 0.141ns (71.611%) route 0.056ns (28.389%))
|
|
Logic Levels: 0
|
|
Clock Path Skew: 0.000ns (DCD - SCD - CPR)
|
|
Destination Clock Delay (DCD): -0.355ns
|
|
Source Clock Delay (SCD): -0.582ns
|
|
Clock Pessimism Removal (CPR): 0.227ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock mlkem_clk_clk_pll rise edge)
|
|
0.000 0.000 r
|
|
K21 0.000 0.000 r clk (IN)
|
|
net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1
|
|
K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O
|
|
net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll
|
|
PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2)
|
|
-2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2
|
|
net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll
|
|
BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout3_buf/O
|
|
net (fo=26129, routed) 0.680 -0.582 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/popToPushGray_buffercc/mlkem_clk
|
|
SLICE_X27Y72 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/popToPushGray_buffercc/buffers_0_reg[1]/C
|
|
------------------------------------------------------------------- -------------------
|
|
SLICE_X27Y72 FDCE (Prop_fdce_C_Q) 0.141 -0.441 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/popToPushGray_buffercc/buffers_0_reg[1]/Q
|
|
net (fo=1, routed) 0.056 -0.385 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/popToPushGray_buffercc/buffers_0[1]
|
|
SLICE_X27Y72 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/popToPushGray_buffercc/buffers_1_reg[1]/D
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock mlkem_clk_clk_pll rise edge)
|
|
0.000 0.000 r
|
|
K21 0.000 0.000 r clk (IN)
|
|
net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1
|
|
K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O
|
|
net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll
|
|
PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2)
|
|
-2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2
|
|
net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll
|
|
BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout3_buf/O
|
|
net (fo=26129, routed) 0.953 -0.355 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/popToPushGray_buffercc/mlkem_clk
|
|
SLICE_X27Y72 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/popToPushGray_buffercc/buffers_1_reg[1]/C
|
|
clock pessimism -0.227 -0.582
|
|
SLICE_X27Y72 FDCE (Hold_fdce_C_D) 0.071 -0.511 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/popToPushGray_buffercc/buffers_1_reg[1]
|
|
-------------------------------------------------------------------
|
|
required time 0.511
|
|
arrival time -0.385
|
|
-------------------------------------------------------------------
|
|
slack 0.126
|
|
|
|
Slack (MET) : 0.126ns (arrival time - required time)
|
|
Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/pushToPopGray_buffercc/buffers_0_reg[2]/C
|
|
(rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns})
|
|
Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/pushToPopGray_buffercc/buffers_1_reg[2]/D
|
|
(rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns})
|
|
Path Group: mlkem_clk_clk_pll
|
|
Path Type: Hold (Min at Fast Process Corner)
|
|
Requirement: 0.000ns (mlkem_clk_clk_pll rise@0.000ns - mlkem_clk_clk_pll rise@0.000ns)
|
|
Data Path Delay: 0.197ns (logic 0.141ns (71.611%) route 0.056ns (28.389%))
|
|
Logic Levels: 0
|
|
Clock Path Skew: 0.000ns (DCD - SCD - CPR)
|
|
Destination Clock Delay (DCD): -0.389ns
|
|
Source Clock Delay (SCD): -0.615ns
|
|
Clock Pessimism Removal (CPR): 0.226ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock mlkem_clk_clk_pll rise edge)
|
|
0.000 0.000 r
|
|
K21 0.000 0.000 r clk (IN)
|
|
net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1
|
|
K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O
|
|
net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll
|
|
PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2)
|
|
-2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2
|
|
net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll
|
|
BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout3_buf/O
|
|
net (fo=26129, routed) 0.647 -0.615 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/pushToPopGray_buffercc/mlkem_clk
|
|
SLICE_X115Y75 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/pushToPopGray_buffercc/buffers_0_reg[2]/C
|
|
------------------------------------------------------------------- -------------------
|
|
SLICE_X115Y75 FDCE (Prop_fdce_C_Q) 0.141 -0.474 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/pushToPopGray_buffercc/buffers_0_reg[2]/Q
|
|
net (fo=1, routed) 0.056 -0.418 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/pushToPopGray_buffercc/buffers_0[2]
|
|
SLICE_X115Y75 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/pushToPopGray_buffercc/buffers_1_reg[2]/D
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock mlkem_clk_clk_pll rise edge)
|
|
0.000 0.000 r
|
|
K21 0.000 0.000 r clk (IN)
|
|
net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1
|
|
K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O
|
|
net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll
|
|
PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2)
|
|
-2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2
|
|
net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll
|
|
BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout3_buf/O
|
|
net (fo=26129, routed) 0.919 -0.389 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/pushToPopGray_buffercc/mlkem_clk
|
|
SLICE_X115Y75 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/pushToPopGray_buffercc/buffers_1_reg[2]/C
|
|
clock pessimism -0.226 -0.615
|
|
SLICE_X115Y75 FDCE (Hold_fdce_C_D) 0.071 -0.544 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/pushToPopGray_buffercc/buffers_1_reg[2]
|
|
-------------------------------------------------------------------
|
|
required time 0.544
|
|
arrival time -0.418
|
|
-------------------------------------------------------------------
|
|
slack 0.126
|
|
|
|
Slack (MET) : 0.126ns (arrival time - required time)
|
|
Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/pushToPopGray_buffercc/buffers_0_reg[3]/C
|
|
(rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns})
|
|
Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/pushToPopGray_buffercc/buffers_1_reg[3]/D
|
|
(rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns})
|
|
Path Group: mlkem_clk_clk_pll
|
|
Path Type: Hold (Min at Fast Process Corner)
|
|
Requirement: 0.000ns (mlkem_clk_clk_pll rise@0.000ns - mlkem_clk_clk_pll rise@0.000ns)
|
|
Data Path Delay: 0.197ns (logic 0.141ns (71.611%) route 0.056ns (28.389%))
|
|
Logic Levels: 0
|
|
Clock Path Skew: 0.000ns (DCD - SCD - CPR)
|
|
Destination Clock Delay (DCD): -0.388ns
|
|
Source Clock Delay (SCD): -0.614ns
|
|
Clock Pessimism Removal (CPR): 0.226ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock mlkem_clk_clk_pll rise edge)
|
|
0.000 0.000 r
|
|
K21 0.000 0.000 r clk (IN)
|
|
net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1
|
|
K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O
|
|
net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll
|
|
PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2)
|
|
-2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2
|
|
net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll
|
|
BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout3_buf/O
|
|
net (fo=26129, routed) 0.648 -0.614 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/pushToPopGray_buffercc/mlkem_clk
|
|
SLICE_X117Y75 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/pushToPopGray_buffercc/buffers_0_reg[3]/C
|
|
------------------------------------------------------------------- -------------------
|
|
SLICE_X117Y75 FDCE (Prop_fdce_C_Q) 0.141 -0.473 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/pushToPopGray_buffercc/buffers_0_reg[3]/Q
|
|
net (fo=1, routed) 0.056 -0.417 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/pushToPopGray_buffercc/buffers_0[3]
|
|
SLICE_X117Y75 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/pushToPopGray_buffercc/buffers_1_reg[3]/D
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock mlkem_clk_clk_pll rise edge)
|
|
0.000 0.000 r
|
|
K21 0.000 0.000 r clk (IN)
|
|
net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1
|
|
K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O
|
|
net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll
|
|
PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2)
|
|
-2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2
|
|
net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll
|
|
BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout3_buf/O
|
|
net (fo=26129, routed) 0.920 -0.388 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/pushToPopGray_buffercc/mlkem_clk
|
|
SLICE_X117Y75 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/pushToPopGray_buffercc/buffers_1_reg[3]/C
|
|
clock pessimism -0.226 -0.614
|
|
SLICE_X117Y75 FDCE (Hold_fdce_C_D) 0.071 -0.543 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/pushToPopGray_buffercc/buffers_1_reg[3]
|
|
-------------------------------------------------------------------
|
|
required time 0.543
|
|
arrival time -0.417
|
|
-------------------------------------------------------------------
|
|
slack 0.126
|
|
|
|
Slack (MET) : 0.128ns (arrival time - required time)
|
|
Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/q_s3_reg[5]/C
|
|
(rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns})
|
|
Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/qprod_s4_reg[14]/D
|
|
(rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns})
|
|
Path Group: mlkem_clk_clk_pll
|
|
Path Type: Hold (Min at Fast Process Corner)
|
|
Requirement: 0.000ns (mlkem_clk_clk_pll rise@0.000ns - mlkem_clk_clk_pll rise@0.000ns)
|
|
Data Path Delay: 0.527ns (logic 0.251ns (47.592%) route 0.276ns (52.408%))
|
|
Logic Levels: 2 (CARRY4=1 LUT4=1)
|
|
Clock Path Skew: 0.266ns (DCD - SCD - CPR)
|
|
Destination Clock Delay (DCD): -0.477ns
|
|
Source Clock Delay (SCD): -0.703ns
|
|
Clock Pessimism Removal (CPR): -0.040ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock mlkem_clk_clk_pll rise edge)
|
|
0.000 0.000 r
|
|
K21 0.000 0.000 r clk (IN)
|
|
net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1
|
|
K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O
|
|
net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll
|
|
PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2)
|
|
-2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2
|
|
net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll
|
|
BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout3_buf/O
|
|
net (fo=26129, routed) 0.560 -0.703 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/mlkem_clk
|
|
SLICE_X82Y157 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/q_s3_reg[5]/C
|
|
------------------------------------------------------------------- -------------------
|
|
SLICE_X82Y157 FDCE (Prop_fdce_C_Q) 0.141 -0.562 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/q_s3_reg[5]/Q
|
|
net (fo=7, routed) 0.276 -0.285 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/q_s3_reg[12]_0[5]
|
|
SLICE_X84Y157 LUT4 (Prop_lut4_I0_O) 0.045 -0.240 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/qprod_s4[15]_i_7/O
|
|
net (fo=1, routed) 0.000 -0.240 u_fft_mlkem_axi_slave_n_121
|
|
SLICE_X84Y157 CARRY4 (Prop_carry4_S[2]_O[2])
|
|
0.065 -0.175 r u_bf/u_barrett/qprod_s4_reg[15]_i_1/O[2]
|
|
net (fo=1, routed) 0.000 -0.175 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/qprod_s4_reg[23]_1[6]
|
|
SLICE_X84Y157 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/qprod_s4_reg[14]/D
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock mlkem_clk_clk_pll rise edge)
|
|
0.000 0.000 r
|
|
K21 0.000 0.000 r clk (IN)
|
|
net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1
|
|
K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O
|
|
net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll
|
|
PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2)
|
|
-2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2
|
|
net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll
|
|
BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout3_buf/O
|
|
net (fo=26129, routed) 0.831 -0.477 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/mlkem_clk
|
|
SLICE_X84Y157 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/qprod_s4_reg[14]/C
|
|
clock pessimism 0.040 -0.437
|
|
SLICE_X84Y157 FDCE (Hold_fdce_C_D) 0.134 -0.303 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/qprod_s4_reg[14]
|
|
-------------------------------------------------------------------
|
|
required time 0.303
|
|
arrival time -0.175
|
|
-------------------------------------------------------------------
|
|
slack 0.128
|
|
|
|
Slack (MET) : 0.129ns (arrival time - required time)
|
|
Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[1]/C
|
|
(rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns})
|
|
Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r1_s6_reg[1]/D
|
|
(rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns})
|
|
Path Group: mlkem_clk_clk_pll
|
|
Path Type: Hold (Min at Fast Process Corner)
|
|
Requirement: 0.000ns (mlkem_clk_clk_pll rise@0.000ns - mlkem_clk_clk_pll rise@0.000ns)
|
|
Data Path Delay: 0.526ns (logic 0.185ns (35.176%) route 0.341ns (64.824%))
|
|
Logic Levels: 1 (LUT3=1)
|
|
Clock Path Skew: 0.266ns (DCD - SCD - CPR)
|
|
Destination Clock Delay (DCD): -0.476ns
|
|
Source Clock Delay (SCD): -0.702ns
|
|
Clock Pessimism Removal (CPR): -0.040ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock mlkem_clk_clk_pll rise edge)
|
|
0.000 0.000 r
|
|
K21 0.000 0.000 r clk (IN)
|
|
net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1
|
|
K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O
|
|
net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll
|
|
PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2)
|
|
-2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2
|
|
net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll
|
|
BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout3_buf/O
|
|
net (fo=26129, routed) 0.561 -0.702 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/mlkem_clk
|
|
SLICE_X83Y154 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[1]/C
|
|
------------------------------------------------------------------- -------------------
|
|
SLICE_X83Y154 FDCE (Prop_fdce_C_Q) 0.141 -0.561 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[1]/Q
|
|
net (fo=4, routed) 0.341 -0.220 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5[1]
|
|
SLICE_X84Y154 LUT3 (Prop_lut3_I0_O) 0.044 -0.176 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r1_s6[1]_i_1/O
|
|
net (fo=1, routed) 0.000 -0.176 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r1_s6[1]_i_1_n_0
|
|
SLICE_X84Y154 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r1_s6_reg[1]/D
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock mlkem_clk_clk_pll rise edge)
|
|
0.000 0.000 r
|
|
K21 0.000 0.000 r clk (IN)
|
|
net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1
|
|
K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O
|
|
net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll
|
|
PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2)
|
|
-2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2
|
|
net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll
|
|
BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout3_buf/O
|
|
net (fo=26129, routed) 0.831 -0.476 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/mlkem_clk
|
|
SLICE_X84Y154 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r1_s6_reg[1]/C
|
|
clock pessimism 0.040 -0.436
|
|
SLICE_X84Y154 FDCE (Hold_fdce_C_D) 0.131 -0.305 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r1_s6_reg[1]
|
|
-------------------------------------------------------------------
|
|
required time 0.305
|
|
arrival time -0.176
|
|
-------------------------------------------------------------------
|
|
slack 0.129
|
|
|
|
Slack (MET) : 0.130ns (arrival time - required time)
|
|
Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/qprod_s4_reg[0]/C
|
|
(rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns})
|
|
Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[1]/D
|
|
(rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns})
|
|
Path Group: mlkem_clk_clk_pll
|
|
Path Type: Hold (Min at Fast Process Corner)
|
|
Requirement: 0.000ns (mlkem_clk_clk_pll rise@0.000ns - mlkem_clk_clk_pll rise@0.000ns)
|
|
Data Path Delay: 0.499ns (logic 0.292ns (58.570%) route 0.207ns (41.430%))
|
|
Logic Levels: 2 (CARRY4=1 LUT2=1)
|
|
Clock Path Skew: 0.264ns (DCD - SCD - CPR)
|
|
Destination Clock Delay (DCD): -0.477ns
|
|
Source Clock Delay (SCD): -0.701ns
|
|
Clock Pessimism Removal (CPR): -0.040ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock mlkem_clk_clk_pll rise edge)
|
|
0.000 0.000 r
|
|
K21 0.000 0.000 r clk (IN)
|
|
net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1
|
|
K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O
|
|
net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll
|
|
PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2)
|
|
-2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2
|
|
net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll
|
|
BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout3_buf/O
|
|
net (fo=26129, routed) 0.562 -0.701 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/mlkem_clk
|
|
SLICE_X85Y156 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/qprod_s4_reg[0]/C
|
|
------------------------------------------------------------------- -------------------
|
|
SLICE_X85Y156 FDCE (Prop_fdce_C_Q) 0.141 -0.560 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/qprod_s4_reg[0]/Q
|
|
net (fo=1, routed) 0.207 -0.353 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/qprod_s4[0]
|
|
SLICE_X83Y154 LUT2 (Prop_lut2_I1_O) 0.045 -0.308 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5[3]_i_5/O
|
|
net (fo=1, routed) 0.000 -0.308 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5[3]_i_5_n_0
|
|
SLICE_X83Y154 CARRY4 (Prop_carry4_S[0]_O[1])
|
|
0.106 -0.202 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[3]_i_1/O[1]
|
|
net (fo=1, routed) 0.000 -0.202 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s50[1]
|
|
SLICE_X83Y154 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[1]/D
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock mlkem_clk_clk_pll rise edge)
|
|
0.000 0.000 r
|
|
K21 0.000 0.000 r clk (IN)
|
|
net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1
|
|
K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O
|
|
net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll
|
|
PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2)
|
|
-2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2
|
|
net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll
|
|
BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout3_buf/O
|
|
net (fo=26129, routed) 0.831 -0.477 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/mlkem_clk
|
|
SLICE_X83Y154 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[1]/C
|
|
clock pessimism 0.040 -0.437
|
|
SLICE_X83Y154 FDCE (Hold_fdce_C_D) 0.105 -0.332 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[1]
|
|
-------------------------------------------------------------------
|
|
required time 0.332
|
|
arrival time -0.202
|
|
-------------------------------------------------------------------
|
|
slack 0.130
|
|
|
|
Slack (MET) : 0.131ns (arrival time - required time)
|
|
Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_sha3/squeezed_state_r_reg[352]/C
|
|
(rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns})
|
|
Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/r_r_reg[96]/D
|
|
(rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns})
|
|
Path Group: mlkem_clk_clk_pll
|
|
Path Type: Hold (Min at Fast Process Corner)
|
|
Requirement: 0.000ns (mlkem_clk_clk_pll rise@0.000ns - mlkem_clk_clk_pll rise@0.000ns)
|
|
Data Path Delay: 0.531ns (logic 0.186ns (35.046%) route 0.345ns (64.954%))
|
|
Logic Levels: 1 (LUT2=1)
|
|
Clock Path Skew: 0.337ns (DCD - SCD - CPR)
|
|
Destination Clock Delay (DCD): -0.315ns
|
|
Source Clock Delay (SCD): -0.612ns
|
|
Clock Pessimism Removal (CPR): -0.040ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock mlkem_clk_clk_pll rise edge)
|
|
0.000 0.000 r
|
|
K21 0.000 0.000 r clk (IN)
|
|
net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1
|
|
K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O
|
|
net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll
|
|
PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2)
|
|
-2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2
|
|
net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll
|
|
BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout3_buf/O
|
|
net (fo=26129, routed) 0.651 -0.612 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_sha3/mlkem_clk
|
|
SLICE_X161Y100 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_sha3/squeezed_state_r_reg[352]/C
|
|
------------------------------------------------------------------- -------------------
|
|
SLICE_X161Y100 FDCE (Prop_fdce_C_Q) 0.141 -0.471 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_sha3/squeezed_state_r_reg[352]/Q
|
|
net (fo=1, routed) 0.156 -0.315 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_sha3/squeezed_state_r[352]
|
|
SLICE_X161Y100 LUT2 (Prop_lut2_I0_O) 0.045 -0.270 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_sha3/r_r[96]_i_1/O
|
|
net (fo=2, routed) 0.189 -0.081 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/sha3_hash[352]
|
|
SLICE_X158Y99 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/r_r_reg[96]/D
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock mlkem_clk_clk_pll rise edge)
|
|
0.000 0.000 r
|
|
K21 0.000 0.000 r clk (IN)
|
|
net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1
|
|
K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O
|
|
net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll
|
|
PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2)
|
|
-2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2
|
|
net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll
|
|
BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout3_buf/O
|
|
net (fo=26129, routed) 0.993 -0.315 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mlkem_clk
|
|
SLICE_X158Y99 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/r_r_reg[96]/C
|
|
clock pessimism 0.040 -0.275
|
|
SLICE_X158Y99 FDCE (Hold_fdce_C_D) 0.063 -0.212 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/r_r_reg[96]
|
|
-------------------------------------------------------------------
|
|
required time 0.212
|
|
arrival time -0.081
|
|
-------------------------------------------------------------------
|
|
slack 0.131
|
|
|
|
Slack (MET) : 0.131ns (arrival time - required time)
|
|
Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/p_s3_reg[5]/C
|
|
(rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns})
|
|
Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/p_s4_reg[5]/D
|
|
(rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns})
|
|
Path Group: mlkem_clk_clk_pll
|
|
Path Type: Hold (Min at Fast Process Corner)
|
|
Requirement: 0.000ns (mlkem_clk_clk_pll rise@0.000ns - mlkem_clk_clk_pll rise@0.000ns)
|
|
Data Path Delay: 0.478ns (logic 0.164ns (34.335%) route 0.314ns (65.665%))
|
|
Logic Levels: 0
|
|
Clock Path Skew: 0.264ns (DCD - SCD - CPR)
|
|
Destination Clock Delay (DCD): -0.475ns
|
|
Source Clock Delay (SCD): -0.694ns
|
|
Clock Pessimism Removal (CPR): -0.045ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock mlkem_clk_clk_pll rise edge)
|
|
0.000 0.000 r
|
|
K21 0.000 0.000 r clk (IN)
|
|
net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1
|
|
K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O
|
|
net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll
|
|
PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2)
|
|
-2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2
|
|
net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll
|
|
BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout3_buf/O
|
|
net (fo=26129, routed) 0.569 -0.694 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/mlkem_clk
|
|
SLICE_X80Y149 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/p_s3_reg[5]/C
|
|
------------------------------------------------------------------- -------------------
|
|
SLICE_X80Y149 FDCE (Prop_fdce_C_Q) 0.164 -0.530 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/p_s3_reg[5]/Q
|
|
net (fo=1, routed) 0.314 -0.216 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/p_s3[5]
|
|
SLICE_X80Y154 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/p_s4_reg[5]/D
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock mlkem_clk_clk_pll rise edge)
|
|
0.000 0.000 r
|
|
K21 0.000 0.000 r clk (IN)
|
|
net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1
|
|
K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O
|
|
net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll
|
|
PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2)
|
|
-2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2
|
|
net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll
|
|
BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout3_buf/O
|
|
net (fo=26129, routed) 0.832 -0.475 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/mlkem_clk
|
|
SLICE_X80Y154 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/p_s4_reg[5]/C
|
|
clock pessimism 0.045 -0.430
|
|
SLICE_X80Y154 FDCE (Hold_fdce_C_D) 0.083 -0.347 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/p_s4_reg[5]
|
|
-------------------------------------------------------------------
|
|
required time 0.347
|
|
arrival time -0.216
|
|
-------------------------------------------------------------------
|
|
slack 0.131
|
|
|
|
Slack (MET) : 0.131ns (arrival time - required time)
|
|
Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_scl/p_s3_reg[0]/C
|
|
(rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns})
|
|
Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_scl/p_s4_reg[0]/D
|
|
(rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns})
|
|
Path Group: mlkem_clk_clk_pll
|
|
Path Type: Hold (Min at Fast Process Corner)
|
|
Requirement: 0.000ns (mlkem_clk_clk_pll rise@0.000ns - mlkem_clk_clk_pll rise@0.000ns)
|
|
Data Path Delay: 0.454ns (logic 0.141ns (31.069%) route 0.313ns (68.931%))
|
|
Logic Levels: 0
|
|
Clock Path Skew: 0.264ns (DCD - SCD - CPR)
|
|
Destination Clock Delay (DCD): -0.478ns
|
|
Source Clock Delay (SCD): -0.702ns
|
|
Clock Pessimism Removal (CPR): -0.040ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock mlkem_clk_clk_pll rise edge)
|
|
0.000 0.000 r
|
|
K21 0.000 0.000 r clk (IN)
|
|
net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1
|
|
K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O
|
|
net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll
|
|
PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2)
|
|
-2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2
|
|
net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll
|
|
BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout3_buf/O
|
|
net (fo=26129, routed) 0.561 -0.702 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_scl/mlkem_clk
|
|
SLICE_X85Y159 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_scl/p_s3_reg[0]/C
|
|
------------------------------------------------------------------- -------------------
|
|
SLICE_X85Y159 FDCE (Prop_fdce_C_Q) 0.141 -0.561 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_scl/p_s3_reg[0]/Q
|
|
net (fo=1, routed) 0.313 -0.248 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_scl/p_s3[0]
|
|
SLICE_X82Y159 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_scl/p_s4_reg[0]/D
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock mlkem_clk_clk_pll rise edge)
|
|
0.000 0.000 r
|
|
K21 0.000 0.000 r clk (IN)
|
|
net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1
|
|
K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O
|
|
net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll
|
|
PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2)
|
|
-2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2
|
|
net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll
|
|
BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout3_buf/O
|
|
net (fo=26129, routed) 0.830 -0.478 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_scl/mlkem_clk
|
|
SLICE_X82Y159 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_scl/p_s4_reg[0]/C
|
|
clock pessimism 0.040 -0.438
|
|
SLICE_X82Y159 FDCE (Hold_fdce_C_D) 0.059 -0.379 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_scl/p_s4_reg[0]
|
|
-------------------------------------------------------------------
|
|
required time 0.379
|
|
arrival time -0.248
|
|
-------------------------------------------------------------------
|
|
slack 0.131
|
|
|
|
Slack (MET) : 0.132ns (arrival time - required time)
|
|
Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r1_s6_reg[5]/C
|
|
(rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns})
|
|
Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/product_r_reg[5]/D
|
|
(rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns})
|
|
Path Group: mlkem_clk_clk_pll
|
|
Path Type: Hold (Min at Fast Process Corner)
|
|
Requirement: 0.000ns (mlkem_clk_clk_pll rise@0.000ns - mlkem_clk_clk_pll rise@0.000ns)
|
|
Data Path Delay: 0.504ns (logic 0.249ns (49.413%) route 0.255ns (50.587%))
|
|
Logic Levels: 1 (LUT3=1)
|
|
Clock Path Skew: 0.265ns (DCD - SCD - CPR)
|
|
Destination Clock Delay (DCD): -0.476ns
|
|
Source Clock Delay (SCD): -0.701ns
|
|
Clock Pessimism Removal (CPR): -0.040ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock mlkem_clk_clk_pll rise edge)
|
|
0.000 0.000 r
|
|
K21 0.000 0.000 r clk (IN)
|
|
net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1
|
|
K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O
|
|
net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll
|
|
PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2)
|
|
-2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2
|
|
net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll
|
|
BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout3_buf/O
|
|
net (fo=26129, routed) 0.562 -0.701 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/mlkem_clk
|
|
SLICE_X84Y155 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r1_s6_reg[5]/C
|
|
------------------------------------------------------------------- -------------------
|
|
SLICE_X84Y155 FDCE (Prop_fdce_C_Q) 0.148 -0.553 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r1_s6_reg[5]/Q
|
|
net (fo=4, routed) 0.255 -0.298 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r1_s6_reg_n_0_[5]
|
|
SLICE_X82Y151 LUT3 (Prop_lut3_I0_O) 0.101 -0.197 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/product_r[5]_i_1/O
|
|
net (fo=1, routed) 0.000 -0.197 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/product_r[5]_i_1_n_0
|
|
SLICE_X82Y151 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/product_r_reg[5]/D
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock mlkem_clk_clk_pll rise edge)
|
|
0.000 0.000 r
|
|
K21 0.000 0.000 r clk (IN)
|
|
net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1
|
|
K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O
|
|
net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll
|
|
PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2)
|
|
-2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2
|
|
net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll
|
|
BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout3_buf/O
|
|
net (fo=26129, routed) 0.832 -0.476 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/mlkem_clk
|
|
SLICE_X82Y151 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/product_r_reg[5]/C
|
|
clock pessimism 0.040 -0.436
|
|
SLICE_X82Y151 FDCE (Hold_fdce_C_D) 0.107 -0.329 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/product_r_reg[5]
|
|
-------------------------------------------------------------------
|
|
required time 0.329
|
|
arrival time -0.197
|
|
-------------------------------------------------------------------
|
|
slack 0.132
|
|
|
|
Slack (MET) : 0.132ns (arrival time - required time)
|
|
Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_scl/p_s4_reg[2]/C
|
|
(rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns})
|
|
Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_scl/r0_s5_reg[3]/D
|
|
(rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns})
|
|
Path Group: mlkem_clk_clk_pll
|
|
Path Type: Hold (Min at Fast Process Corner)
|
|
Requirement: 0.000ns (mlkem_clk_clk_pll rise@0.000ns - mlkem_clk_clk_pll rise@0.000ns)
|
|
Data Path Delay: 0.503ns (logic 0.285ns (56.653%) route 0.218ns (43.347%))
|
|
Logic Levels: 2 (CARRY4=1 LUT2=1)
|
|
Clock Path Skew: 0.266ns (DCD - SCD - CPR)
|
|
Destination Clock Delay (DCD): -0.477ns
|
|
Source Clock Delay (SCD): -0.703ns
|
|
Clock Pessimism Removal (CPR): -0.040ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock mlkem_clk_clk_pll rise edge)
|
|
0.000 0.000 r
|
|
K21 0.000 0.000 r clk (IN)
|
|
net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1
|
|
K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O
|
|
net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll
|
|
PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2)
|
|
-2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2
|
|
net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll
|
|
BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout3_buf/O
|
|
net (fo=26129, routed) 0.560 -0.703 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_scl/mlkem_clk
|
|
SLICE_X85Y160 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_scl/p_s4_reg[2]/C
|
|
------------------------------------------------------------------- -------------------
|
|
SLICE_X85Y160 FDCE (Prop_fdce_C_Q) 0.141 -0.562 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_scl/p_s4_reg[2]/Q
|
|
net (fo=2, routed) 0.218 -0.344 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_scl/p_s4[2]
|
|
SLICE_X79Y160 LUT2 (Prop_lut2_I0_O) 0.045 -0.299 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_scl/r0_s5[3]_i_3__0/O
|
|
net (fo=1, routed) 0.000 -0.299 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_scl/r0_s5[3]_i_3__0_n_0
|
|
SLICE_X79Y160 CARRY4 (Prop_carry4_S[2]_O[3])
|
|
0.099 -0.200 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_scl/r0_s5_reg[3]_i_1__0/O[3]
|
|
net (fo=1, routed) 0.000 -0.200 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_scl/r0_s50[3]
|
|
SLICE_X79Y160 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_scl/r0_s5_reg[3]/D
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock mlkem_clk_clk_pll rise edge)
|
|
0.000 0.000 r
|
|
K21 0.000 0.000 r clk (IN)
|
|
net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1
|
|
K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O
|
|
net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll
|
|
PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2)
|
|
-2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2
|
|
net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll
|
|
BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout3_buf/O
|
|
net (fo=26129, routed) 0.831 -0.477 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_scl/mlkem_clk
|
|
SLICE_X79Y160 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_scl/r0_s5_reg[3]/C
|
|
clock pessimism 0.040 -0.437
|
|
SLICE_X79Y160 FDCE (Hold_fdce_C_D) 0.105 -0.332 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_scl/r0_s5_reg[3]
|
|
-------------------------------------------------------------------
|
|
required time 0.332
|
|
arrival time -0.200
|
|
-------------------------------------------------------------------
|
|
slack 0.132
|
|
|
|
Slack (MET) : 0.133ns (arrival time - required time)
|
|
Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_scl/p_s3_reg[20]/C
|
|
(rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns})
|
|
Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_scl/p_s4_reg[20]/D
|
|
(rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns})
|
|
Path Group: mlkem_clk_clk_pll
|
|
Path Type: Hold (Min at Fast Process Corner)
|
|
Requirement: 0.000ns (mlkem_clk_clk_pll rise@0.000ns - mlkem_clk_clk_pll rise@0.000ns)
|
|
Data Path Delay: 0.480ns (logic 0.141ns (29.345%) route 0.339ns (70.655%))
|
|
Logic Levels: 0
|
|
Clock Path Skew: 0.264ns (DCD - SCD - CPR)
|
|
Destination Clock Delay (DCD): -0.481ns
|
|
Source Clock Delay (SCD): -0.705ns
|
|
Clock Pessimism Removal (CPR): -0.040ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock mlkem_clk_clk_pll rise edge)
|
|
0.000 0.000 r
|
|
K21 0.000 0.000 r clk (IN)
|
|
net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1
|
|
K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O
|
|
net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll
|
|
PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2)
|
|
-2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2
|
|
net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll
|
|
BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout3_buf/O
|
|
net (fo=26129, routed) 0.558 -0.705 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_scl/mlkem_clk
|
|
SLICE_X87Y164 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_scl/p_s3_reg[20]/C
|
|
------------------------------------------------------------------- -------------------
|
|
SLICE_X87Y164 FDCE (Prop_fdce_C_Q) 0.141 -0.564 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_scl/p_s3_reg[20]/Q
|
|
net (fo=1, routed) 0.339 -0.224 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_scl/p_s3[20]
|
|
SLICE_X80Y165 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_scl/p_s4_reg[20]/D
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock mlkem_clk_clk_pll rise edge)
|
|
0.000 0.000 r
|
|
K21 0.000 0.000 r clk (IN)
|
|
net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1
|
|
K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O
|
|
net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll
|
|
PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2)
|
|
-2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2
|
|
net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll
|
|
BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout3_buf/O
|
|
net (fo=26129, routed) 0.826 -0.481 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_scl/mlkem_clk
|
|
SLICE_X80Y165 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_scl/p_s4_reg[20]/C
|
|
clock pessimism 0.040 -0.441
|
|
SLICE_X80Y165 FDCE (Hold_fdce_C_D) 0.084 -0.357 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_scl/p_s4_reg[20]
|
|
-------------------------------------------------------------------
|
|
required time 0.357
|
|
arrival time -0.224
|
|
-------------------------------------------------------------------
|
|
slack 0.133
|
|
|
|
Slack (MET) : 0.136ns (arrival time - required time)
|
|
Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/decomp_result_s5_reg[11]/C
|
|
(rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns})
|
|
Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/data_r_reg[11]/D
|
|
(rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns})
|
|
Path Group: mlkem_clk_clk_pll
|
|
Path Type: Hold (Min at Fast Process Corner)
|
|
Requirement: 0.000ns (mlkem_clk_clk_pll rise@0.000ns - mlkem_clk_clk_pll rise@0.000ns)
|
|
Data Path Delay: 0.240ns (logic 0.186ns (77.515%) route 0.054ns (22.485%))
|
|
Logic Levels: 1 (LUT5=1)
|
|
Clock Path Skew: 0.013ns (DCD - SCD - CPR)
|
|
Destination Clock Delay (DCD): -0.456ns
|
|
Source Clock Delay (SCD): -0.681ns
|
|
Clock Pessimism Removal (CPR): 0.212ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock mlkem_clk_clk_pll rise edge)
|
|
0.000 0.000 r
|
|
K21 0.000 0.000 r clk (IN)
|
|
net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1
|
|
K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O
|
|
net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll
|
|
PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2)
|
|
-2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2
|
|
net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll
|
|
BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout3_buf/O
|
|
net (fo=26129, routed) 0.582 -0.681 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/mlkem_clk
|
|
SLICE_X58Y137 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/decomp_result_s5_reg[11]/C
|
|
------------------------------------------------------------------- -------------------
|
|
SLICE_X58Y137 FDCE (Prop_fdce_C_Q) 0.141 -0.540 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/decomp_result_s5_reg[11]/Q
|
|
net (fo=1, routed) 0.054 -0.486 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/decomp_result_s5[11]
|
|
SLICE_X59Y137 LUT5 (Prop_lut5_I0_O) 0.045 -0.441 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/data_r[11]_i_1/O
|
|
net (fo=1, routed) 0.000 -0.441 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/data_r[11]_i_1_n_0
|
|
SLICE_X59Y137 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/data_r_reg[11]/D
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock mlkem_clk_clk_pll rise edge)
|
|
0.000 0.000 r
|
|
K21 0.000 0.000 r clk (IN)
|
|
net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1
|
|
K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O
|
|
net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll
|
|
PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2)
|
|
-2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2
|
|
net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll
|
|
BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout3_buf/O
|
|
net (fo=26129, routed) 0.852 -0.456 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/mlkem_clk
|
|
SLICE_X59Y137 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/data_r_reg[11]/C
|
|
clock pessimism -0.212 -0.668
|
|
SLICE_X59Y137 FDCE (Hold_fdce_C_D) 0.091 -0.577 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/data_r_reg[11]
|
|
-------------------------------------------------------------------
|
|
required time 0.577
|
|
arrival time -0.441
|
|
-------------------------------------------------------------------
|
|
slack 0.136
|
|
|
|
Slack (MET) : 0.137ns (arrival time - required time)
|
|
Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/q_s3_reg[11]/C
|
|
(rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns})
|
|
Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/qprod_s4_reg[19]/D
|
|
(rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns})
|
|
Path Group: mlkem_clk_clk_pll
|
|
Path Type: Hold (Min at Fast Process Corner)
|
|
Requirement: 0.000ns (mlkem_clk_clk_pll rise@0.000ns - mlkem_clk_clk_pll rise@0.000ns)
|
|
Data Path Delay: 0.536ns (logic 0.250ns (46.632%) route 0.286ns (53.368%))
|
|
Logic Levels: 2 (CARRY4=1 LUT4=1)
|
|
Clock Path Skew: 0.265ns (DCD - SCD - CPR)
|
|
Destination Clock Delay (DCD): -0.477ns
|
|
Source Clock Delay (SCD): -0.702ns
|
|
Clock Pessimism Removal (CPR): -0.040ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock mlkem_clk_clk_pll rise edge)
|
|
0.000 0.000 r
|
|
K21 0.000 0.000 r clk (IN)
|
|
net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1
|
|
K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O
|
|
net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll
|
|
PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2)
|
|
-2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2
|
|
net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll
|
|
BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout3_buf/O
|
|
net (fo=26129, routed) 0.561 -0.702 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/mlkem_clk
|
|
SLICE_X82Y156 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/q_s3_reg[11]/C
|
|
------------------------------------------------------------------- -------------------
|
|
SLICE_X82Y156 FDCE (Prop_fdce_C_Q) 0.141 -0.561 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/q_s3_reg[11]/Q
|
|
net (fo=8, routed) 0.286 -0.275 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/q_s3[11]
|
|
SLICE_X84Y158 LUT4 (Prop_lut4_I3_O) 0.045 -0.230 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/qprod_s4[19]_i_6/O
|
|
net (fo=1, routed) 0.000 -0.230 u_fft_mlkem_axi_slave_n_135
|
|
SLICE_X84Y158 CARRY4 (Prop_carry4_S[3]_O[3])
|
|
0.064 -0.166 r u_bf/u_barrett/qprod_s4_reg[19]_i_1/O[3]
|
|
net (fo=1, routed) 0.000 -0.166 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/qprod_s4_reg[23]_1[11]
|
|
SLICE_X84Y158 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/qprod_s4_reg[19]/D
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock mlkem_clk_clk_pll rise edge)
|
|
0.000 0.000 r
|
|
K21 0.000 0.000 r clk (IN)
|
|
net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1
|
|
K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O
|
|
net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll
|
|
PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2)
|
|
-2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2
|
|
net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll
|
|
BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout3_buf/O
|
|
net (fo=26129, routed) 0.831 -0.477 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/mlkem_clk
|
|
SLICE_X84Y158 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/qprod_s4_reg[19]/C
|
|
clock pessimism 0.040 -0.437
|
|
SLICE_X84Y158 FDCE (Hold_fdce_C_D) 0.134 -0.303 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/qprod_s4_reg[19]
|
|
-------------------------------------------------------------------
|
|
required time 0.303
|
|
arrival time -0.166
|
|
-------------------------------------------------------------------
|
|
slack 0.137
|
|
|
|
Slack (MET) : 0.138ns (arrival time - required time)
|
|
Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/wb_a_data_r_reg[6]/C
|
|
(rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns})
|
|
Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/cr_reg[245][6]/D
|
|
(rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns})
|
|
Path Group: mlkem_clk_clk_pll
|
|
Path Type: Hold (Min at Fast Process Corner)
|
|
Requirement: 0.000ns (mlkem_clk_clk_pll rise@0.000ns - mlkem_clk_clk_pll rise@0.000ns)
|
|
Data Path Delay: 0.498ns (logic 0.186ns (37.319%) route 0.312ns (62.681%))
|
|
Logic Levels: 1 (LUT6=1)
|
|
Clock Path Skew: 0.269ns (DCD - SCD - CPR)
|
|
Destination Clock Delay (DCD): -0.469ns
|
|
Source Clock Delay (SCD): -0.693ns
|
|
Clock Pessimism Removal (CPR): -0.045ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock mlkem_clk_clk_pll rise edge)
|
|
0.000 0.000 r
|
|
K21 0.000 0.000 r clk (IN)
|
|
net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1
|
|
K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O
|
|
net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll
|
|
PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2)
|
|
-2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2
|
|
net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll
|
|
BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout3_buf/O
|
|
net (fo=26129, routed) 0.570 -0.693 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/mlkem_clk
|
|
SLICE_X89Y155 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/wb_a_data_r_reg[6]/C
|
|
------------------------------------------------------------------- -------------------
|
|
SLICE_X89Y155 FDCE (Prop_fdce_C_Q) 0.141 -0.552 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/wb_a_data_r_reg[6]/Q
|
|
net (fo=234, routed) 0.312 -0.239 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/wb_a_data_r[6]
|
|
SLICE_X86Y149 LUT6 (Prop_lut6_I2_O) 0.045 -0.194 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/cr[245][6]_i_1/O
|
|
net (fo=1, routed) 0.000 -0.194 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/cr[245][6]_i_1_n_0
|
|
SLICE_X86Y149 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/cr_reg[245][6]/D
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock mlkem_clk_clk_pll rise edge)
|
|
0.000 0.000 r
|
|
K21 0.000 0.000 r clk (IN)
|
|
net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1
|
|
K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O
|
|
net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll
|
|
PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2)
|
|
-2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2
|
|
net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll
|
|
BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout3_buf/O
|
|
net (fo=26129, routed) 0.839 -0.469 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/mlkem_clk
|
|
SLICE_X86Y149 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/cr_reg[245][6]/C
|
|
clock pessimism 0.045 -0.424
|
|
SLICE_X86Y149 FDCE (Hold_fdce_C_D) 0.092 -0.332 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/cr_reg[245][6]
|
|
-------------------------------------------------------------------
|
|
required time 0.332
|
|
arrival time -0.194
|
|
-------------------------------------------------------------------
|
|
slack 0.138
|
|
|
|
|
|
|
|
|
|
|
|
Pulse Width Checks
|
|
--------------------------------------------------------------------------------------
|
|
Clock Name: mlkem_clk_clk_pll
|
|
Waveform(ns): { 0.000 20.000 }
|
|
Period(ns): 40.000
|
|
Sources: { pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 }
|
|
|
|
Check Type Corner Lib Pin Reference Pin Required(ns) Actual(ns) Slack(ns) Location Pin
|
|
Min Period n/a RAMB36E1/CLKARDCLK n/a 2.944 40.000 37.056 RAMB36_X4Y27 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_a/mem_reg_0/CLKARDCLK
|
|
Min Period n/a RAMB18E1/CLKARDCLK n/a 2.944 40.000 37.056 RAMB18_X4Y56 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_a/mem_reg_1/CLKARDCLK
|
|
Min Period n/a RAMB36E1/CLKARDCLK n/a 2.944 40.000 37.056 RAMB36_X4Y25 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_se/mem_reg/CLKARDCLK
|
|
Min Period n/a RAMB18E1/CLKARDCLK n/a 2.944 40.000 37.056 RAMB18_X4Y52 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg/CLKARDCLK
|
|
Min Period n/a RAMB18E1/CLKARDCLK n/a 2.944 40.000 37.056 RAMB18_X7Y26 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_c_in_bram/mem_reg/CLKARDCLK
|
|
Min Period n/a RAMB18E1/CLKARDCLK n/a 2.944 40.000 37.056 RAMB18_X7Y27 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ct_bram/mem_reg/CLKARDCLK
|
|
Min Period n/a RAMB18E1/CLKARDCLK n/a 2.944 40.000 37.056 RAMB18_X7Y28 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_dkp_bram/mem_reg/CLKARDCLK
|
|
Min Period n/a RAMB18E1/CLKARDCLK n/a 2.944 40.000 37.056 RAMB18_X7Y25 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/mem_reg/CLKARDCLK
|
|
Min Period n/a RAMB36E1/CLKBWRCLK n/a 2.576 40.000 37.424 RAMB36_X4Y27 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_a/mem_reg_0/CLKBWRCLK
|
|
Min Period n/a RAMB18E1/CLKBWRCLK n/a 2.576 40.000 37.424 RAMB18_X4Y56 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_a/mem_reg_1/CLKBWRCLK
|
|
Min Period n/a RAMB36E1/CLKBWRCLK n/a 2.576 40.000 37.424 RAMB36_X4Y25 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_se/mem_reg/CLKBWRCLK
|
|
Min Period n/a RAMB18E1/CLKBWRCLK n/a 2.576 40.000 37.424 RAMB18_X4Y52 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg/CLKBWRCLK
|
|
Min Period n/a RAMB18E1/CLKBWRCLK n/a 2.576 40.000 37.424 RAMB18_X7Y26 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_c_in_bram/mem_reg/CLKBWRCLK
|
|
Min Period n/a RAMB18E1/CLKBWRCLK n/a 2.576 40.000 37.424 RAMB18_X7Y27 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ct_bram/mem_reg/CLKBWRCLK
|
|
Min Period n/a RAMB18E1/CLKBWRCLK n/a 2.576 40.000 37.424 RAMB18_X7Y28 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_dkp_bram/mem_reg/CLKBWRCLK
|
|
Min Period n/a RAMB18E1/CLKBWRCLK n/a 2.576 40.000 37.424 RAMB18_X7Y25 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/mem_reg/CLKBWRCLK
|
|
Min Period n/a BUFG/I n/a 2.155 40.000 37.845 BUFGCTRL_X0Y17 pll_clk.u_clk_pll/inst/clkout3_buf/I
|
|
Min Period n/a PLLE2_ADV/CLKOUT2 n/a 1.249 40.000 38.751 PLLE2_ADV_X0Y3 pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2
|
|
Min Period n/a FDCE/C n/a 1.000 40.000 39.000 SLICE_X103Y116 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_block_r_reg[897]/C
|
|
Min Period n/a FDCE/C n/a 1.000 40.000 39.000 SLICE_X101Y117 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_block_r_reg[898]/C
|
|
Min Period n/a FDCE/C n/a 1.000 40.000 39.000 SLICE_X102Y118 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_block_r_reg[899]/C
|
|
Min Period n/a FDCE/C n/a 1.000 40.000 39.000 SLICE_X147Y105 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_block_r_reg[89]/C
|
|
Min Period n/a FDCE/C n/a 1.000 40.000 39.000 SLICE_X135Y110 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_block_r_reg[8]/C
|
|
Min Period n/a FDCE/C n/a 1.000 40.000 39.000 SLICE_X102Y114 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_block_r_reg[900]/C
|
|
Min Period n/a FDCE/C n/a 1.000 40.000 39.000 SLICE_X102Y114 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_block_r_reg[901]/C
|
|
Min Period n/a FDCE/C n/a 1.000 40.000 39.000 SLICE_X100Y117 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_block_r_reg[902]/C
|
|
Min Period n/a FDCE/C n/a 1.000 40.000 39.000 SLICE_X100Y117 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_block_r_reg[903]/C
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Min Period n/a FDCE/C n/a 1.000 40.000 39.000 SLICE_X56Y129 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_block_r_reg[904]/C
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Min Period n/a FDCE/C n/a 1.000 40.000 39.000 SLICE_X55Y130 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_block_r_reg[905]/C
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Min Period n/a FDCE/C n/a 1.000 40.000 39.000 SLICE_X55Y130 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_block_r_reg[906]/C
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Min Period n/a FDCE/C n/a 1.000 40.000 39.000 SLICE_X55Y129 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_block_r_reg[907]/C
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Min Period n/a FDCE/C n/a 1.000 40.000 39.000 SLICE_X55Y129 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_block_r_reg[908]/C
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Min Period n/a FDCE/C n/a 1.000 40.000 39.000 SLICE_X64Y123 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_block_r_reg[909]/C
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Min Period n/a FDCE/C n/a 1.000 40.000 39.000 SLICE_X147Y105 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_block_r_reg[90]/C
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Min Period n/a FDCE/C n/a 1.000 40.000 39.000 SLICE_X64Y123 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_block_r_reg[910]/C
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Min Period n/a FDCE/C n/a 1.000 40.000 39.000 SLICE_X64Y123 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_block_r_reg[911]/C
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Min Period n/a FDCE/C n/a 1.000 40.000 39.000 SLICE_X93Y117 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_block_r_reg[912]/C
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Min Period n/a FDCE/C n/a 1.000 40.000 39.000 SLICE_X93Y116 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_block_r_reg[913]/C
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Min Period n/a FDCE/C n/a 1.000 40.000 39.000 SLICE_X92Y115 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_block_r_reg[914]/C
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Min Period n/a FDCE/C n/a 1.000 40.000 39.000 SLICE_X148Y176 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_A_reg[191][3]/C
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Min Period n/a FDCE/C n/a 1.000 40.000 39.000 SLICE_X149Y181 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_A_reg[191][4]/C
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Min Period n/a FDCE/C n/a 1.000 40.000 39.000 SLICE_X149Y181 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_A_reg[191][5]/C
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Min Period n/a FDCE/C n/a 1.000 40.000 39.000 SLICE_X125Y187 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_A_reg[191][6]/C
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Min Period n/a FDCE/C n/a 1.000 40.000 39.000 SLICE_X132Y173 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_A_reg[191][7]/C
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Min Period n/a FDCE/C n/a 1.000 40.000 39.000 SLICE_X135Y186 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_A_reg[191][8]/C
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Min Period n/a FDCE/C n/a 1.000 40.000 39.000 SLICE_X150Y179 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_A_reg[191][9]/C
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Min Period n/a FDCE/C n/a 1.000 40.000 39.000 SLICE_X130Y211 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_A_reg[192][0]/C
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Min Period n/a FDCE/C n/a 1.000 40.000 39.000 SLICE_X129Y208 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_A_reg[192][10]/C
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Min Period n/a FDCE/C n/a 1.000 40.000 39.000 SLICE_X129Y208 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_A_reg[192][11]/C
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Min Period n/a FDCE/C n/a 1.000 40.000 39.000 SLICE_X121Y226 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_A_reg[192][1]/C
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Max Period n/a PLLE2_ADV/CLKOUT2 n/a 160.000 40.000 120.000 PLLE2_ADV_X0Y3 pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2
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Low Pulse Width Slow RAMD32/CLK n/a 1.250 20.000 18.750 SLICE_X64Y77 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_24_29/RAMA/CLK
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Low Pulse Width Slow RAMD32/CLK n/a 1.250 20.000 18.750 SLICE_X64Y77 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_24_29/RAMA_D1/CLK
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Low Pulse Width Slow RAMD32/CLK n/a 1.250 20.000 18.750 SLICE_X64Y77 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_24_29/RAMB/CLK
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Low Pulse Width Slow RAMD32/CLK n/a 1.250 20.000 18.750 SLICE_X64Y77 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_24_29/RAMB_D1/CLK
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Low Pulse Width Slow RAMD32/CLK n/a 1.250 20.000 18.750 SLICE_X64Y77 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_24_29/RAMC/CLK
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Low Pulse Width Slow RAMD32/CLK n/a 1.250 20.000 18.750 SLICE_X64Y77 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_24_29/RAMC_D1/CLK
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Low Pulse Width Slow RAMS32/CLK n/a 1.250 20.000 18.750 SLICE_X64Y77 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_24_29/RAMD/CLK
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Low Pulse Width Slow RAMS32/CLK n/a 1.250 20.000 18.750 SLICE_X64Y77 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_24_29/RAMD_D1/CLK
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Low Pulse Width Slow RAMD32/CLK n/a 1.250 20.000 18.750 SLICE_X20Y76 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_30_35/RAMA/CLK
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Low Pulse Width Slow RAMD32/CLK n/a 1.250 20.000 18.750 SLICE_X20Y76 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_30_35/RAMA_D1/CLK
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Low Pulse Width Slow RAMD32/CLK n/a 1.250 20.000 18.750 SLICE_X20Y76 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_30_35/RAMB/CLK
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Low Pulse Width Slow RAMD32/CLK n/a 1.250 20.000 18.750 SLICE_X20Y76 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_30_35/RAMB_D1/CLK
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Low Pulse Width Slow RAMD32/CLK n/a 1.250 20.000 18.750 SLICE_X20Y76 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_30_35/RAMC/CLK
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Low Pulse Width Slow RAMD32/CLK n/a 1.250 20.000 18.750 SLICE_X20Y76 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_30_35/RAMC_D1/CLK
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Low Pulse Width Slow RAMS32/CLK n/a 1.250 20.000 18.750 SLICE_X20Y76 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_30_35/RAMD/CLK
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Low Pulse Width Slow RAMS32/CLK n/a 1.250 20.000 18.750 SLICE_X20Y76 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_30_35/RAMD_D1/CLK
|
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Low Pulse Width Slow RAMD32/CLK n/a 1.250 20.000 18.750 SLICE_X46Y75 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_6_11/RAMA/CLK
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Low Pulse Width Slow RAMD32/CLK n/a 1.250 20.000 18.750 SLICE_X46Y75 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_6_11/RAMA_D1/CLK
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Low Pulse Width Slow RAMD32/CLK n/a 1.250 20.000 18.750 SLICE_X46Y75 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_6_11/RAMB/CLK
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Low Pulse Width Slow RAMD32/CLK n/a 1.250 20.000 18.750 SLICE_X46Y75 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_6_11/RAMB_D1/CLK
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Low Pulse Width Slow RAMD32/CLK n/a 1.250 20.000 18.750 SLICE_X46Y75 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_6_11/RAMC/CLK
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Low Pulse Width Slow RAMD32/CLK n/a 1.250 20.000 18.750 SLICE_X46Y75 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_6_11/RAMC_D1/CLK
|
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Low Pulse Width Slow RAMS32/CLK n/a 1.250 20.000 18.750 SLICE_X46Y75 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_6_11/RAMD/CLK
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Low Pulse Width Slow RAMS32/CLK n/a 1.250 20.000 18.750 SLICE_X46Y75 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_6_11/RAMD_D1/CLK
|
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Low Pulse Width Fast RAMD32/CLK n/a 1.250 20.000 18.750 SLICE_X22Y72 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/ram_reg_0_3_0_5/RAMA/CLK
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Low Pulse Width Fast RAMD32/CLK n/a 1.250 20.000 18.750 SLICE_X22Y72 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/ram_reg_0_3_0_5/RAMA_D1/CLK
|
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Low Pulse Width Fast RAMD32/CLK n/a 1.250 20.000 18.750 SLICE_X22Y72 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/ram_reg_0_3_0_5/RAMB/CLK
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Low Pulse Width Fast RAMD32/CLK n/a 1.250 20.000 18.750 SLICE_X22Y72 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/ram_reg_0_3_0_5/RAMB_D1/CLK
|
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Low Pulse Width Fast RAMD32/CLK n/a 1.250 20.000 18.750 SLICE_X22Y72 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/ram_reg_0_3_0_5/RAMC/CLK
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Low Pulse Width Fast RAMD32/CLK n/a 1.250 20.000 18.750 SLICE_X22Y72 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/ram_reg_0_3_0_5/RAMC_D1/CLK
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Low Pulse Width Fast RAMS32/CLK n/a 1.250 20.000 18.750 SLICE_X22Y72 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/ram_reg_0_3_0_5/RAMD/CLK
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Low Pulse Width Fast RAMS32/CLK n/a 1.250 20.000 18.750 SLICE_X22Y72 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/ram_reg_0_3_0_5/RAMD_D1/CLK
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Low Pulse Width Slow RAMD32/CLK n/a 1.250 20.000 18.750 SLICE_X52Y75 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_0_5/RAMA/CLK
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Low Pulse Width Slow RAMD32/CLK n/a 1.250 20.000 18.750 SLICE_X52Y75 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_0_5/RAMA_D1/CLK
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Low Pulse Width Slow RAMD32/CLK n/a 1.250 20.000 18.750 SLICE_X52Y75 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_0_5/RAMB/CLK
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Low Pulse Width Slow RAMD32/CLK n/a 1.250 20.000 18.750 SLICE_X52Y75 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_0_5/RAMB_D1/CLK
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Low Pulse Width Slow RAMD32/CLK n/a 1.250 20.000 18.750 SLICE_X52Y75 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_0_5/RAMC/CLK
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Low Pulse Width Slow RAMD32/CLK n/a 1.250 20.000 18.750 SLICE_X52Y75 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_0_5/RAMC_D1/CLK
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Low Pulse Width Slow RAMS32/CLK n/a 1.250 20.000 18.750 SLICE_X52Y75 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_0_5/RAMD/CLK
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Low Pulse Width Slow RAMS32/CLK n/a 1.250 20.000 18.750 SLICE_X52Y75 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_0_5/RAMD_D1/CLK
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Low Pulse Width Fast RAMD32/CLK n/a 1.250 20.000 18.750 SLICE_X64Y76 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_12_17/RAMA/CLK
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Low Pulse Width Fast RAMD32/CLK n/a 1.250 20.000 18.750 SLICE_X64Y76 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_12_17/RAMA_D1/CLK
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Low Pulse Width Fast RAMD32/CLK n/a 1.250 20.000 18.750 SLICE_X64Y76 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_12_17/RAMB/CLK
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Low Pulse Width Fast RAMD32/CLK n/a 1.250 20.000 18.750 SLICE_X64Y76 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_12_17/RAMB_D1/CLK
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Low Pulse Width Fast RAMD32/CLK n/a 1.250 20.000 18.750 SLICE_X64Y76 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_12_17/RAMC/CLK
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Low Pulse Width Fast RAMD32/CLK n/a 1.250 20.000 18.750 SLICE_X64Y76 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_12_17/RAMC_D1/CLK
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Low Pulse Width Fast RAMS32/CLK n/a 1.250 20.000 18.750 SLICE_X64Y76 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_12_17/RAMD/CLK
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Low Pulse Width Fast RAMS32/CLK n/a 1.250 20.000 18.750 SLICE_X64Y76 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_12_17/RAMD_D1/CLK
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Low Pulse Width Fast RAMD32/CLK n/a 1.250 20.000 18.750 SLICE_X64Y77 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_24_29/RAMA/CLK
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Low Pulse Width Fast RAMD32/CLK n/a 1.250 20.000 18.750 SLICE_X64Y77 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_24_29/RAMA_D1/CLK
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High Pulse Width Slow RAMD32/CLK n/a 1.250 20.000 18.750 SLICE_X22Y72 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/ram_reg_0_3_0_5/RAMA/CLK
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High Pulse Width Fast RAMD32/CLK n/a 1.250 20.000 18.750 SLICE_X22Y72 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/ram_reg_0_3_0_5/RAMA/CLK
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High Pulse Width Slow RAMD32/CLK n/a 1.250 20.000 18.750 SLICE_X22Y72 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/ram_reg_0_3_0_5/RAMA_D1/CLK
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High Pulse Width Fast RAMD32/CLK n/a 1.250 20.000 18.750 SLICE_X22Y72 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/ram_reg_0_3_0_5/RAMA_D1/CLK
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High Pulse Width Slow RAMD32/CLK n/a 1.250 20.000 18.750 SLICE_X22Y72 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/ram_reg_0_3_0_5/RAMB/CLK
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High Pulse Width Fast RAMD32/CLK n/a 1.250 20.000 18.750 SLICE_X22Y72 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/ram_reg_0_3_0_5/RAMB/CLK
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High Pulse Width Slow RAMD32/CLK n/a 1.250 20.000 18.750 SLICE_X22Y72 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/ram_reg_0_3_0_5/RAMB_D1/CLK
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High Pulse Width Fast RAMD32/CLK n/a 1.250 20.000 18.750 SLICE_X22Y72 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/ram_reg_0_3_0_5/RAMB_D1/CLK
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High Pulse Width Slow RAMD32/CLK n/a 1.250 20.000 18.750 SLICE_X22Y72 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/ram_reg_0_3_0_5/RAMC/CLK
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High Pulse Width Fast RAMD32/CLK n/a 1.250 20.000 18.750 SLICE_X22Y72 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/ram_reg_0_3_0_5/RAMC/CLK
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High Pulse Width Slow RAMD32/CLK n/a 1.250 20.000 18.750 SLICE_X22Y72 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/ram_reg_0_3_0_5/RAMC_D1/CLK
|
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High Pulse Width Fast RAMD32/CLK n/a 1.250 20.000 18.750 SLICE_X22Y72 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/ram_reg_0_3_0_5/RAMC_D1/CLK
|
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High Pulse Width Slow RAMS32/CLK n/a 1.250 20.000 18.750 SLICE_X22Y72 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/ram_reg_0_3_0_5/RAMD/CLK
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High Pulse Width Fast RAMS32/CLK n/a 1.250 20.000 18.750 SLICE_X22Y72 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/ram_reg_0_3_0_5/RAMD/CLK
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High Pulse Width Slow RAMS32/CLK n/a 1.250 20.000 18.750 SLICE_X22Y72 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/ram_reg_0_3_0_5/RAMD_D1/CLK
|
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High Pulse Width Fast RAMS32/CLK n/a 1.250 20.000 18.750 SLICE_X22Y72 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/ram_reg_0_3_0_5/RAMD_D1/CLK
|
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High Pulse Width Slow RAMD32/CLK n/a 1.250 20.000 18.750 SLICE_X52Y75 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_0_5/RAMA/CLK
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High Pulse Width Fast RAMD32/CLK n/a 1.250 20.000 18.750 SLICE_X52Y75 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_0_5/RAMA/CLK
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High Pulse Width Slow RAMD32/CLK n/a 1.250 20.000 18.750 SLICE_X52Y75 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_0_5/RAMA_D1/CLK
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High Pulse Width Fast RAMD32/CLK n/a 1.250 20.000 18.750 SLICE_X52Y75 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_0_5/RAMA_D1/CLK
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High Pulse Width Slow RAMD32/CLK n/a 1.250 20.000 18.750 SLICE_X52Y75 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_0_5/RAMB/CLK
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High Pulse Width Fast RAMD32/CLK n/a 1.250 20.000 18.750 SLICE_X52Y75 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_0_5/RAMB/CLK
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High Pulse Width Slow RAMD32/CLK n/a 1.250 20.000 18.750 SLICE_X52Y75 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_0_5/RAMB_D1/CLK
|
|
High Pulse Width Fast RAMD32/CLK n/a 1.250 20.000 18.750 SLICE_X52Y75 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_0_5/RAMB_D1/CLK
|
|
High Pulse Width Slow RAMD32/CLK n/a 1.250 20.000 18.750 SLICE_X52Y75 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_0_5/RAMC/CLK
|
|
High Pulse Width Fast RAMD32/CLK n/a 1.250 20.000 18.750 SLICE_X52Y75 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_0_5/RAMC/CLK
|
|
High Pulse Width Slow RAMD32/CLK n/a 1.250 20.000 18.750 SLICE_X52Y75 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_0_5/RAMC_D1/CLK
|
|
High Pulse Width Fast RAMD32/CLK n/a 1.250 20.000 18.750 SLICE_X52Y75 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_0_5/RAMC_D1/CLK
|
|
High Pulse Width Slow RAMS32/CLK n/a 1.250 20.000 18.750 SLICE_X52Y75 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_0_5/RAMD/CLK
|
|
High Pulse Width Fast RAMS32/CLK n/a 1.250 20.000 18.750 SLICE_X52Y75 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_0_5/RAMD/CLK
|
|
High Pulse Width Slow RAMS32/CLK n/a 1.250 20.000 18.750 SLICE_X52Y75 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_0_5/RAMD_D1/CLK
|
|
High Pulse Width Fast RAMS32/CLK n/a 1.250 20.000 18.750 SLICE_X52Y75 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_0_5/RAMD_D1/CLK
|
|
High Pulse Width Slow RAMD32/CLK n/a 1.250 20.000 18.750 SLICE_X64Y76 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_12_17/RAMA/CLK
|
|
High Pulse Width Fast RAMD32/CLK n/a 1.250 20.000 18.750 SLICE_X64Y76 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_12_17/RAMA/CLK
|
|
High Pulse Width Slow RAMD32/CLK n/a 1.250 20.000 18.750 SLICE_X64Y76 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_12_17/RAMA_D1/CLK
|
|
High Pulse Width Fast RAMD32/CLK n/a 1.250 20.000 18.750 SLICE_X64Y76 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_12_17/RAMA_D1/CLK
|
|
High Pulse Width Slow RAMD32/CLK n/a 1.250 20.000 18.750 SLICE_X64Y76 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_12_17/RAMB/CLK
|
|
High Pulse Width Fast RAMD32/CLK n/a 1.250 20.000 18.750 SLICE_X64Y76 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_12_17/RAMB/CLK
|
|
High Pulse Width Slow RAMD32/CLK n/a 1.250 20.000 18.750 SLICE_X64Y76 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_12_17/RAMB_D1/CLK
|
|
High Pulse Width Fast RAMD32/CLK n/a 1.250 20.000 18.750 SLICE_X64Y76 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_12_17/RAMB_D1/CLK
|
|
High Pulse Width Slow RAMD32/CLK n/a 1.250 20.000 18.750 SLICE_X64Y76 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_12_17/RAMC/CLK
|
|
High Pulse Width Fast RAMD32/CLK n/a 1.250 20.000 18.750 SLICE_X64Y76 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_12_17/RAMC/CLK
|
|
High Pulse Width Slow RAMD32/CLK n/a 1.250 20.000 18.750 SLICE_X64Y76 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_12_17/RAMC_D1/CLK
|
|
High Pulse Width Fast RAMD32/CLK n/a 1.250 20.000 18.750 SLICE_X64Y76 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_12_17/RAMC_D1/CLK
|
|
High Pulse Width Slow RAMS32/CLK n/a 1.250 20.000 18.750 SLICE_X64Y76 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_12_17/RAMD/CLK
|
|
High Pulse Width Fast RAMS32/CLK n/a 1.250 20.000 18.750 SLICE_X64Y76 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_12_17/RAMD/CLK
|
|
High Pulse Width Slow RAMS32/CLK n/a 1.250 20.000 18.750 SLICE_X64Y76 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_12_17/RAMD_D1/CLK
|
|
High Pulse Width Fast RAMS32/CLK n/a 1.250 20.000 18.750 SLICE_X64Y76 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_12_17/RAMD_D1/CLK
|
|
High Pulse Width Slow RAMD32/CLK n/a 1.250 20.000 18.750 SLICE_X64Y75 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_18_23/RAMA/CLK
|
|
High Pulse Width Fast RAMD32/CLK n/a 1.250 20.000 18.750 SLICE_X64Y75 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_18_23/RAMA/CLK
|
|
|
|
|
|
|
|
---------------------------------------------------------------------------------------------------
|
|
From Clock: sys_clk
|
|
To Clock: sys_clk
|
|
|
|
Setup : NA Failing Endpoints, Worst Slack NA , Total Violation NA
|
|
Hold : 0 Failing Endpoints, Worst Slack 0.079ns, Total Violation 0.000ns
|
|
PW : 0 Failing Endpoints, Worst Slack 8.750ns, Total Violation 0.000ns
|
|
---------------------------------------------------------------------------------------------------
|
|
|
|
|
|
Min Delay Paths
|
|
--------------------------------------------------------------------------------------
|
|
Slack (MET) : 0.079ns (arrival time - required time)
|
|
Source: u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/DB1/buf_re_reg[127][2]_srl32/CLK
|
|
(rising edge-triggered cell SRLC32E clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Destination: u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/DB1/buf_re_reg[159][2]_srl32/D
|
|
(rising edge-triggered cell SRLC32E clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Path Group: sys_clk
|
|
Path Type: Hold (Min at Fast Process Corner)
|
|
Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns)
|
|
Data Path Delay: 0.544ns (logic 0.378ns (69.538%) route 0.166ns (30.462%))
|
|
Logic Levels: 0
|
|
Clock Path Skew: 0.343ns (DCD - SCD - CPR)
|
|
Destination Clock Delay (DCD): -0.260ns
|
|
Source Clock Delay (SCD): -0.566ns
|
|
Clock Pessimism Removal (CPR): -0.037ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock sys_clk rise edge) 0.000 0.000 r
|
|
K21 0.000 0.000 r clk (IN)
|
|
net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1
|
|
K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O
|
|
net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll
|
|
PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1)
|
|
-2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1
|
|
net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll
|
|
BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O
|
|
net (fo=10004, routed) 0.696 -0.566 u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/DB1/sys_clk
|
|
SLICE_X18Y50 SRLC32E r u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/DB1/buf_re_reg[127][2]_srl32/CLK
|
|
------------------------------------------------------------------- -------------------
|
|
SLICE_X18Y50 SRLC32E (Prop_srlc32e_CLK_Q31)
|
|
0.378 -0.188 r u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/DB1/buf_re_reg[127][2]_srl32/Q31
|
|
net (fo=1, routed) 0.166 -0.023 u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/DB1/xlnx_opt__56
|
|
SLICE_X14Y49 SRLC32E r u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/DB1/buf_re_reg[159][2]_srl32/D
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock sys_clk rise edge) 0.000 0.000 r
|
|
K21 0.000 0.000 r clk (IN)
|
|
net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1
|
|
K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O
|
|
net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll
|
|
PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1)
|
|
-2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1
|
|
net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll
|
|
BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O
|
|
net (fo=10004, routed) 1.048 -0.260 u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/DB1/sys_clk
|
|
SLICE_X14Y49 SRLC32E r u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/DB1/buf_re_reg[159][2]_srl32/CLK
|
|
clock pessimism 0.037 -0.223
|
|
SLICE_X14Y49 SRLC32E (Hold_srlc32e_CLK_D)
|
|
0.122 -0.101 u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/DB1/buf_re_reg[159][2]_srl32
|
|
-------------------------------------------------------------------
|
|
required time 0.101
|
|
arrival time -0.023
|
|
-------------------------------------------------------------------
|
|
slack 0.079
|
|
|
|
Slack (MET) : 0.079ns (arrival time - required time)
|
|
Source: u_axi_uart_controller/uart0/regs/receiver/rf_data_in_reg[5]/C
|
|
(rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Destination: u_axi_uart_controller/uart0/regs/receiver/fifo_rx/rfifo/ram_reg_0_15_0_5/RAMB/I
|
|
(rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Path Group: sys_clk
|
|
Path Type: Hold (Min at Fast Process Corner)
|
|
Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns)
|
|
Data Path Delay: 0.242ns (logic 0.141ns (58.248%) route 0.101ns (41.752%))
|
|
Logic Levels: 0
|
|
Clock Path Skew: 0.017ns (DCD - SCD - CPR)
|
|
Destination Clock Delay (DCD): -0.308ns
|
|
Source Clock Delay (SCD): -0.541ns
|
|
Clock Pessimism Removal (CPR): 0.216ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock sys_clk rise edge) 0.000 0.000 r
|
|
K21 0.000 0.000 r clk (IN)
|
|
net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1
|
|
K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O
|
|
net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll
|
|
PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1)
|
|
-2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1
|
|
net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll
|
|
BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O
|
|
net (fo=10004, routed) 0.721 -0.541 u_axi_uart_controller/uart0/regs/receiver/sys_clk
|
|
SLICE_X4Y57 FDRE r u_axi_uart_controller/uart0/regs/receiver/rf_data_in_reg[5]/C
|
|
------------------------------------------------------------------- -------------------
|
|
SLICE_X4Y57 FDRE (Prop_fdre_C_Q) 0.141 -0.400 r u_axi_uart_controller/uart0/regs/receiver/rf_data_in_reg[5]/Q
|
|
net (fo=1, routed) 0.101 -0.299 u_axi_uart_controller/uart0/regs/receiver/fifo_rx/rfifo/ram_reg_0_15_0_5/DIB0
|
|
SLICE_X6Y56 RAMD32 r u_axi_uart_controller/uart0/regs/receiver/fifo_rx/rfifo/ram_reg_0_15_0_5/RAMB/I
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock sys_clk rise edge) 0.000 0.000 r
|
|
K21 0.000 0.000 r clk (IN)
|
|
net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1
|
|
K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O
|
|
net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll
|
|
PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1)
|
|
-2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1
|
|
net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll
|
|
BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O
|
|
net (fo=10004, routed) 1.000 -0.308 u_axi_uart_controller/uart0/regs/receiver/fifo_rx/rfifo/ram_reg_0_15_0_5/WCLK
|
|
SLICE_X6Y56 RAMD32 r u_axi_uart_controller/uart0/regs/receiver/fifo_rx/rfifo/ram_reg_0_15_0_5/RAMB/CLK
|
|
clock pessimism -0.216 -0.524
|
|
SLICE_X6Y56 RAMD32 (Hold_ramd32_CLK_I)
|
|
0.146 -0.378 u_axi_uart_controller/uart0/regs/receiver/fifo_rx/rfifo/ram_reg_0_15_0_5/RAMB
|
|
-------------------------------------------------------------------
|
|
required time 0.378
|
|
arrival time -0.299
|
|
-------------------------------------------------------------------
|
|
slack 0.079
|
|
|
|
Slack (MET) : 0.080ns (arrival time - required time)
|
|
Source: u_axi_uart_controller/uart0/regs/receiver/rf_data_in_reg[3]/C
|
|
(rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Destination: u_axi_uart_controller/uart0/regs/receiver/fifo_rx/rfifo/ram_reg_0_15_0_5/RAMA/I
|
|
(rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Path Group: sys_clk
|
|
Path Type: Hold (Min at Fast Process Corner)
|
|
Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns)
|
|
Data Path Delay: 0.244ns (logic 0.141ns (57.830%) route 0.103ns (42.170%))
|
|
Logic Levels: 0
|
|
Clock Path Skew: 0.017ns (DCD - SCD - CPR)
|
|
Destination Clock Delay (DCD): -0.308ns
|
|
Source Clock Delay (SCD): -0.541ns
|
|
Clock Pessimism Removal (CPR): 0.216ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock sys_clk rise edge) 0.000 0.000 r
|
|
K21 0.000 0.000 r clk (IN)
|
|
net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1
|
|
K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O
|
|
net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll
|
|
PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1)
|
|
-2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1
|
|
net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll
|
|
BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O
|
|
net (fo=10004, routed) 0.721 -0.541 u_axi_uart_controller/uart0/regs/receiver/sys_clk
|
|
SLICE_X4Y57 FDRE r u_axi_uart_controller/uart0/regs/receiver/rf_data_in_reg[3]/C
|
|
------------------------------------------------------------------- -------------------
|
|
SLICE_X4Y57 FDRE (Prop_fdre_C_Q) 0.141 -0.400 r u_axi_uart_controller/uart0/regs/receiver/rf_data_in_reg[3]/Q
|
|
net (fo=1, routed) 0.103 -0.298 u_axi_uart_controller/uart0/regs/receiver/fifo_rx/rfifo/ram_reg_0_15_0_5/DIA0
|
|
SLICE_X6Y56 RAMD32 r u_axi_uart_controller/uart0/regs/receiver/fifo_rx/rfifo/ram_reg_0_15_0_5/RAMA/I
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock sys_clk rise edge) 0.000 0.000 r
|
|
K21 0.000 0.000 r clk (IN)
|
|
net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1
|
|
K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O
|
|
net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll
|
|
PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1)
|
|
-2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1
|
|
net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll
|
|
BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O
|
|
net (fo=10004, routed) 1.000 -0.308 u_axi_uart_controller/uart0/regs/receiver/fifo_rx/rfifo/ram_reg_0_15_0_5/WCLK
|
|
SLICE_X6Y56 RAMD32 r u_axi_uart_controller/uart0/regs/receiver/fifo_rx/rfifo/ram_reg_0_15_0_5/RAMA/CLK
|
|
clock pessimism -0.216 -0.524
|
|
SLICE_X6Y56 RAMD32 (Hold_ramd32_CLK_I)
|
|
0.147 -0.377 u_axi_uart_controller/uart0/regs/receiver/fifo_rx/rfifo/ram_reg_0_15_0_5/RAMA
|
|
-------------------------------------------------------------------
|
|
required time 0.377
|
|
arrival time -0.298
|
|
-------------------------------------------------------------------
|
|
slack 0.080
|
|
|
|
Slack (MET) : 0.083ns (arrival time - required time)
|
|
Source: u_matmul_axi_slave/mult_inst[1].u_mult/prod_reg[49]/C
|
|
(rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Destination: u_matmul_axi_slave/mult_inst[1].u_mult/p_reg[49]/D
|
|
(rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Path Group: sys_clk
|
|
Path Type: Hold (Min at Fast Process Corner)
|
|
Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns)
|
|
Data Path Delay: 0.488ns (logic 0.164ns (33.640%) route 0.324ns (66.360%))
|
|
Logic Levels: 0
|
|
Clock Path Skew: 0.335ns (DCD - SCD - CPR)
|
|
Destination Clock Delay (DCD): -0.338ns
|
|
Source Clock Delay (SCD): -0.633ns
|
|
Clock Pessimism Removal (CPR): -0.040ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock sys_clk rise edge) 0.000 0.000 r
|
|
K21 0.000 0.000 r clk (IN)
|
|
net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1
|
|
K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O
|
|
net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll
|
|
PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1)
|
|
-2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1
|
|
net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll
|
|
BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O
|
|
net (fo=10004, routed) 0.630 -0.633 u_matmul_axi_slave/mult_inst[1].u_mult/sys_clk
|
|
SLICE_X14Y102 FDRE r u_matmul_axi_slave/mult_inst[1].u_mult/prod_reg[49]/C
|
|
------------------------------------------------------------------- -------------------
|
|
SLICE_X14Y102 FDRE (Prop_fdre_C_Q) 0.164 -0.469 r u_matmul_axi_slave/mult_inst[1].u_mult/prod_reg[49]/Q
|
|
net (fo=1, routed) 0.324 -0.145 u_matmul_axi_slave/mult_inst[1].u_mult/prod[49]
|
|
SLICE_X17Y92 FDRE r u_matmul_axi_slave/mult_inst[1].u_mult/p_reg[49]/D
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock sys_clk rise edge) 0.000 0.000 r
|
|
K21 0.000 0.000 r clk (IN)
|
|
net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1
|
|
K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O
|
|
net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll
|
|
PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1)
|
|
-2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1
|
|
net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll
|
|
BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O
|
|
net (fo=10004, routed) 0.970 -0.338 u_matmul_axi_slave/mult_inst[1].u_mult/sys_clk
|
|
SLICE_X17Y92 FDRE r u_matmul_axi_slave/mult_inst[1].u_mult/p_reg[49]/C
|
|
clock pessimism 0.040 -0.298
|
|
SLICE_X17Y92 FDRE (Hold_fdre_C_D) 0.070 -0.228 u_matmul_axi_slave/mult_inst[1].u_mult/p_reg[49]
|
|
-------------------------------------------------------------------
|
|
required time 0.228
|
|
arrival time -0.145
|
|
-------------------------------------------------------------------
|
|
slack 0.083
|
|
|
|
Slack (MET) : 0.085ns (arrival time - required time)
|
|
Source: u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/wptr_reg[5]/C
|
|
(rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Destination: u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/mem_reg/ADDRBWRADDR[10]
|
|
(rising edge-triggered cell RAMB18E1 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Path Group: sys_clk
|
|
Path Type: Hold (Min at Fast Process Corner)
|
|
Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns)
|
|
Data Path Delay: 0.324ns (logic 0.164ns (50.614%) route 0.160ns (49.386%))
|
|
Logic Levels: 0
|
|
Clock Path Skew: 0.056ns (DCD - SCD - CPR)
|
|
Destination Clock Delay (DCD): -0.357ns
|
|
Source Clock Delay (SCD): -0.626ns
|
|
Clock Pessimism Removal (CPR): 0.213ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock sys_clk rise edge) 0.000 0.000 r
|
|
K21 0.000 0.000 r clk (IN)
|
|
net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1
|
|
K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O
|
|
net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll
|
|
PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1)
|
|
-2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1
|
|
net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll
|
|
BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O
|
|
net (fo=10004, routed) 0.636 -0.626 u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/sys_clk
|
|
SLICE_X62Y75 FDCE r u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/wptr_reg[5]/C
|
|
------------------------------------------------------------------- -------------------
|
|
SLICE_X62Y75 FDCE (Prop_fdce_C_Q) 0.164 -0.462 r u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/wptr_reg[5]/Q
|
|
net (fo=2, routed) 0.160 -0.302 u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/wptr_reg[5]
|
|
RAMB18_X3Y30 RAMB18E1 r u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/mem_reg/ADDRBWRADDR[10]
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock sys_clk rise edge) 0.000 0.000 r
|
|
K21 0.000 0.000 r clk (IN)
|
|
net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1
|
|
K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O
|
|
net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll
|
|
PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1)
|
|
-2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1
|
|
net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll
|
|
BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O
|
|
net (fo=10004, routed) 0.951 -0.357 u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/sys_clk
|
|
RAMB18_X3Y30 RAMB18E1 r u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/mem_reg/CLKBWRCLK
|
|
clock pessimism -0.213 -0.570
|
|
RAMB18_X3Y30 RAMB18E1 (Hold_ramb18e1_CLKBWRCLK_ADDRBWRADDR[10])
|
|
0.183 -0.387 u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/mem_reg
|
|
-------------------------------------------------------------------
|
|
required time 0.387
|
|
arrival time -0.302
|
|
-------------------------------------------------------------------
|
|
slack 0.085
|
|
|
|
Slack (MET) : 0.096ns (arrival time - required time)
|
|
Source: u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/DB1/buf_re_reg[127][1]_srl32/CLK
|
|
(rising edge-triggered cell SRLC32E clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Destination: u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/DB1/buf_re_reg[159][1]_srl32/D
|
|
(rising edge-triggered cell SRLC32E clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Path Group: sys_clk
|
|
Path Type: Hold (Min at Fast Process Corner)
|
|
Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns)
|
|
Data Path Delay: 0.561ns (logic 0.378ns (67.415%) route 0.183ns (32.585%))
|
|
Logic Levels: 0
|
|
Clock Path Skew: 0.343ns (DCD - SCD - CPR)
|
|
Destination Clock Delay (DCD): -0.262ns
|
|
Source Clock Delay (SCD): -0.568ns
|
|
Clock Pessimism Removal (CPR): -0.037ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock sys_clk rise edge) 0.000 0.000 r
|
|
K21 0.000 0.000 r clk (IN)
|
|
net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1
|
|
K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O
|
|
net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll
|
|
PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1)
|
|
-2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1
|
|
net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll
|
|
BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O
|
|
net (fo=10004, routed) 0.694 -0.568 u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/DB1/sys_clk
|
|
SLICE_X20Y50 SRLC32E r u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/DB1/buf_re_reg[127][1]_srl32/CLK
|
|
------------------------------------------------------------------- -------------------
|
|
SLICE_X20Y50 SRLC32E (Prop_srlc32e_CLK_Q31)
|
|
0.378 -0.190 r u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/DB1/buf_re_reg[127][1]_srl32/Q31
|
|
net (fo=1, routed) 0.183 -0.008 u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/DB1/xlnx_opt__55
|
|
SLICE_X20Y49 SRLC32E r u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/DB1/buf_re_reg[159][1]_srl32/D
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock sys_clk rise edge) 0.000 0.000 r
|
|
K21 0.000 0.000 r clk (IN)
|
|
net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1
|
|
K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O
|
|
net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll
|
|
PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1)
|
|
-2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1
|
|
net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll
|
|
BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O
|
|
net (fo=10004, routed) 1.046 -0.262 u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/DB1/sys_clk
|
|
SLICE_X20Y49 SRLC32E r u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/DB1/buf_re_reg[159][1]_srl32/CLK
|
|
clock pessimism 0.037 -0.225
|
|
SLICE_X20Y49 SRLC32E (Hold_srlc32e_CLK_D)
|
|
0.122 -0.103 u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/DB1/buf_re_reg[159][1]_srl32
|
|
-------------------------------------------------------------------
|
|
required time 0.103
|
|
arrival time -0.008
|
|
-------------------------------------------------------------------
|
|
slack 0.096
|
|
|
|
Slack (MET) : 0.101ns (arrival time - required time)
|
|
Source: u_matmul_axi_slave/mult_inst[1].u_mult/prod_reg[51]/C
|
|
(rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Destination: u_matmul_axi_slave/mult_inst[1].u_mult/p_reg[51]/D
|
|
(rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Path Group: sys_clk
|
|
Path Type: Hold (Min at Fast Process Corner)
|
|
Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns)
|
|
Data Path Delay: 0.505ns (logic 0.164ns (32.465%) route 0.341ns (67.535%))
|
|
Logic Levels: 0
|
|
Clock Path Skew: 0.334ns (DCD - SCD - CPR)
|
|
Destination Clock Delay (DCD): -0.339ns
|
|
Source Clock Delay (SCD): -0.633ns
|
|
Clock Pessimism Removal (CPR): -0.040ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock sys_clk rise edge) 0.000 0.000 r
|
|
K21 0.000 0.000 r clk (IN)
|
|
net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1
|
|
K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O
|
|
net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll
|
|
PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1)
|
|
-2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1
|
|
net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll
|
|
BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O
|
|
net (fo=10004, routed) 0.630 -0.633 u_matmul_axi_slave/mult_inst[1].u_mult/sys_clk
|
|
SLICE_X14Y102 FDRE r u_matmul_axi_slave/mult_inst[1].u_mult/prod_reg[51]/C
|
|
------------------------------------------------------------------- -------------------
|
|
SLICE_X14Y102 FDRE (Prop_fdre_C_Q) 0.164 -0.469 r u_matmul_axi_slave/mult_inst[1].u_mult/prod_reg[51]/Q
|
|
net (fo=1, routed) 0.341 -0.128 u_matmul_axi_slave/mult_inst[1].u_mult/prod[51]
|
|
SLICE_X15Y89 FDRE r u_matmul_axi_slave/mult_inst[1].u_mult/p_reg[51]/D
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock sys_clk rise edge) 0.000 0.000 r
|
|
K21 0.000 0.000 r clk (IN)
|
|
net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1
|
|
K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O
|
|
net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll
|
|
PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1)
|
|
-2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1
|
|
net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll
|
|
BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O
|
|
net (fo=10004, routed) 0.969 -0.339 u_matmul_axi_slave/mult_inst[1].u_mult/sys_clk
|
|
SLICE_X15Y89 FDRE r u_matmul_axi_slave/mult_inst[1].u_mult/p_reg[51]/C
|
|
clock pessimism 0.040 -0.299
|
|
SLICE_X15Y89 FDRE (Hold_fdre_C_D) 0.070 -0.229 u_matmul_axi_slave/mult_inst[1].u_mult/p_reg[51]
|
|
-------------------------------------------------------------------
|
|
required time 0.229
|
|
arrival time -0.128
|
|
-------------------------------------------------------------------
|
|
slack 0.101
|
|
|
|
Slack (MET) : 0.101ns (arrival time - required time)
|
|
Source: u_matmul_axi_slave/mult_inst[1].u_mult/prod_reg[59]/C
|
|
(rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Destination: u_matmul_axi_slave/mult_inst[1].u_mult/p_reg[59]/D
|
|
(rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Path Group: sys_clk
|
|
Path Type: Hold (Min at Fast Process Corner)
|
|
Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns)
|
|
Data Path Delay: 0.509ns (logic 0.164ns (32.198%) route 0.345ns (67.802%))
|
|
Logic Levels: 0
|
|
Clock Path Skew: 0.336ns (DCD - SCD - CPR)
|
|
Destination Clock Delay (DCD): -0.338ns
|
|
Source Clock Delay (SCD): -0.634ns
|
|
Clock Pessimism Removal (CPR): -0.040ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock sys_clk rise edge) 0.000 0.000 r
|
|
K21 0.000 0.000 r clk (IN)
|
|
net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1
|
|
K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O
|
|
net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll
|
|
PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1)
|
|
-2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1
|
|
net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll
|
|
BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O
|
|
net (fo=10004, routed) 0.629 -0.634 u_matmul_axi_slave/mult_inst[1].u_mult/sys_clk
|
|
SLICE_X14Y104 FDRE r u_matmul_axi_slave/mult_inst[1].u_mult/prod_reg[59]/C
|
|
------------------------------------------------------------------- -------------------
|
|
SLICE_X14Y104 FDRE (Prop_fdre_C_Q) 0.164 -0.470 r u_matmul_axi_slave/mult_inst[1].u_mult/prod_reg[59]/Q
|
|
net (fo=1, routed) 0.345 -0.125 u_matmul_axi_slave/mult_inst[1].u_mult/prod[59]
|
|
SLICE_X17Y92 FDRE r u_matmul_axi_slave/mult_inst[1].u_mult/p_reg[59]/D
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock sys_clk rise edge) 0.000 0.000 r
|
|
K21 0.000 0.000 r clk (IN)
|
|
net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1
|
|
K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O
|
|
net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll
|
|
PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1)
|
|
-2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1
|
|
net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll
|
|
BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O
|
|
net (fo=10004, routed) 0.970 -0.338 u_matmul_axi_slave/mult_inst[1].u_mult/sys_clk
|
|
SLICE_X17Y92 FDRE r u_matmul_axi_slave/mult_inst[1].u_mult/p_reg[59]/C
|
|
clock pessimism 0.040 -0.298
|
|
SLICE_X17Y92 FDRE (Hold_fdre_C_D) 0.072 -0.226 u_matmul_axi_slave/mult_inst[1].u_mult/p_reg[59]
|
|
-------------------------------------------------------------------
|
|
required time 0.226
|
|
arrival time -0.125
|
|
-------------------------------------------------------------------
|
|
slack 0.101
|
|
|
|
Slack (MET) : 0.106ns (arrival time - required time)
|
|
Source: u_matmul_axi_slave/mult_inst[1].u_mult/prod_reg[57]/C
|
|
(rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Destination: u_matmul_axi_slave/mult_inst[1].u_mult/p_reg[57]/D
|
|
(rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Path Group: sys_clk
|
|
Path Type: Hold (Min at Fast Process Corner)
|
|
Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns)
|
|
Data Path Delay: 0.507ns (logic 0.164ns (32.320%) route 0.343ns (67.680%))
|
|
Logic Levels: 0
|
|
Clock Path Skew: 0.335ns (DCD - SCD - CPR)
|
|
Destination Clock Delay (DCD): -0.339ns
|
|
Source Clock Delay (SCD): -0.634ns
|
|
Clock Pessimism Removal (CPR): -0.040ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock sys_clk rise edge) 0.000 0.000 r
|
|
K21 0.000 0.000 r clk (IN)
|
|
net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1
|
|
K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O
|
|
net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll
|
|
PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1)
|
|
-2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1
|
|
net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll
|
|
BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O
|
|
net (fo=10004, routed) 0.629 -0.634 u_matmul_axi_slave/mult_inst[1].u_mult/sys_clk
|
|
SLICE_X14Y104 FDRE r u_matmul_axi_slave/mult_inst[1].u_mult/prod_reg[57]/C
|
|
------------------------------------------------------------------- -------------------
|
|
SLICE_X14Y104 FDRE (Prop_fdre_C_Q) 0.164 -0.470 r u_matmul_axi_slave/mult_inst[1].u_mult/prod_reg[57]/Q
|
|
net (fo=1, routed) 0.343 -0.127 u_matmul_axi_slave/mult_inst[1].u_mult/prod[57]
|
|
SLICE_X15Y89 FDRE r u_matmul_axi_slave/mult_inst[1].u_mult/p_reg[57]/D
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock sys_clk rise edge) 0.000 0.000 r
|
|
K21 0.000 0.000 r clk (IN)
|
|
net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1
|
|
K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O
|
|
net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll
|
|
PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1)
|
|
-2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1
|
|
net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll
|
|
BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O
|
|
net (fo=10004, routed) 0.969 -0.339 u_matmul_axi_slave/mult_inst[1].u_mult/sys_clk
|
|
SLICE_X15Y89 FDRE r u_matmul_axi_slave/mult_inst[1].u_mult/p_reg[57]/C
|
|
clock pessimism 0.040 -0.299
|
|
SLICE_X15Y89 FDRE (Hold_fdre_C_D) 0.066 -0.233 u_matmul_axi_slave/mult_inst[1].u_mult/p_reg[57]
|
|
-------------------------------------------------------------------
|
|
required time 0.233
|
|
arrival time -0.127
|
|
-------------------------------------------------------------------
|
|
slack 0.106
|
|
|
|
Slack (MET) : 0.108ns (arrival time - required time)
|
|
Source: u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/top_reg[2]/C
|
|
(rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Destination: u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/tfifo/ram_reg_0_15_0_5/RAMA/WADR2
|
|
(rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Path Group: sys_clk
|
|
Path Type: Hold (Min at Fast Process Corner)
|
|
Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns)
|
|
Data Path Delay: 0.379ns (logic 0.164ns (43.254%) route 0.215ns (56.746%))
|
|
Logic Levels: 0
|
|
Clock Path Skew: 0.017ns (DCD - SCD - CPR)
|
|
Destination Clock Delay (DCD): -0.310ns
|
|
Source Clock Delay (SCD): -0.543ns
|
|
Clock Pessimism Removal (CPR): 0.216ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock sys_clk rise edge) 0.000 0.000 r
|
|
K21 0.000 0.000 r clk (IN)
|
|
net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1
|
|
K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O
|
|
net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll
|
|
PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1)
|
|
-2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1
|
|
net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll
|
|
BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O
|
|
net (fo=10004, routed) 0.719 -0.543 u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/sys_clk
|
|
SLICE_X6Y62 FDRE r u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/top_reg[2]/C
|
|
------------------------------------------------------------------- -------------------
|
|
SLICE_X6Y62 FDRE (Prop_fdre_C_Q) 0.164 -0.379 r u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/top_reg[2]/Q
|
|
net (fo=18, routed) 0.215 -0.164 u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/tfifo/ram_reg_0_15_0_5/ADDRD2
|
|
SLICE_X6Y61 RAMD32 r u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/tfifo/ram_reg_0_15_0_5/RAMA/WADR2
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock sys_clk rise edge) 0.000 0.000 r
|
|
K21 0.000 0.000 r clk (IN)
|
|
net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1
|
|
K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O
|
|
net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll
|
|
PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1)
|
|
-2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1
|
|
net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll
|
|
BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O
|
|
net (fo=10004, routed) 0.998 -0.310 u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/tfifo/ram_reg_0_15_0_5/WCLK
|
|
SLICE_X6Y61 RAMD32 r u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/tfifo/ram_reg_0_15_0_5/RAMA/CLK
|
|
clock pessimism -0.216 -0.526
|
|
SLICE_X6Y61 RAMD32 (Hold_ramd32_CLK_WADR2)
|
|
0.254 -0.272 u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/tfifo/ram_reg_0_15_0_5/RAMA
|
|
-------------------------------------------------------------------
|
|
required time 0.272
|
|
arrival time -0.164
|
|
-------------------------------------------------------------------
|
|
slack 0.108
|
|
|
|
Slack (MET) : 0.108ns (arrival time - required time)
|
|
Source: u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/top_reg[2]/C
|
|
(rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Destination: u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/tfifo/ram_reg_0_15_0_5/RAMA_D1/WADR2
|
|
(rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Path Group: sys_clk
|
|
Path Type: Hold (Min at Fast Process Corner)
|
|
Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns)
|
|
Data Path Delay: 0.379ns (logic 0.164ns (43.254%) route 0.215ns (56.746%))
|
|
Logic Levels: 0
|
|
Clock Path Skew: 0.017ns (DCD - SCD - CPR)
|
|
Destination Clock Delay (DCD): -0.310ns
|
|
Source Clock Delay (SCD): -0.543ns
|
|
Clock Pessimism Removal (CPR): 0.216ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock sys_clk rise edge) 0.000 0.000 r
|
|
K21 0.000 0.000 r clk (IN)
|
|
net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1
|
|
K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O
|
|
net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll
|
|
PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1)
|
|
-2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1
|
|
net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll
|
|
BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O
|
|
net (fo=10004, routed) 0.719 -0.543 u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/sys_clk
|
|
SLICE_X6Y62 FDRE r u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/top_reg[2]/C
|
|
------------------------------------------------------------------- -------------------
|
|
SLICE_X6Y62 FDRE (Prop_fdre_C_Q) 0.164 -0.379 r u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/top_reg[2]/Q
|
|
net (fo=18, routed) 0.215 -0.164 u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/tfifo/ram_reg_0_15_0_5/ADDRD2
|
|
SLICE_X6Y61 RAMD32 r u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/tfifo/ram_reg_0_15_0_5/RAMA_D1/WADR2
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock sys_clk rise edge) 0.000 0.000 r
|
|
K21 0.000 0.000 r clk (IN)
|
|
net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1
|
|
K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O
|
|
net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll
|
|
PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1)
|
|
-2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1
|
|
net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll
|
|
BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O
|
|
net (fo=10004, routed) 0.998 -0.310 u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/tfifo/ram_reg_0_15_0_5/WCLK
|
|
SLICE_X6Y61 RAMD32 r u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/tfifo/ram_reg_0_15_0_5/RAMA_D1/CLK
|
|
clock pessimism -0.216 -0.526
|
|
SLICE_X6Y61 RAMD32 (Hold_ramd32_CLK_WADR2)
|
|
0.254 -0.272 u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/tfifo/ram_reg_0_15_0_5/RAMA_D1
|
|
-------------------------------------------------------------------
|
|
required time 0.272
|
|
arrival time -0.164
|
|
-------------------------------------------------------------------
|
|
slack 0.108
|
|
|
|
Slack (MET) : 0.108ns (arrival time - required time)
|
|
Source: u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/top_reg[2]/C
|
|
(rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Destination: u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/tfifo/ram_reg_0_15_0_5/RAMB/WADR2
|
|
(rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Path Group: sys_clk
|
|
Path Type: Hold (Min at Fast Process Corner)
|
|
Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns)
|
|
Data Path Delay: 0.379ns (logic 0.164ns (43.254%) route 0.215ns (56.746%))
|
|
Logic Levels: 0
|
|
Clock Path Skew: 0.017ns (DCD - SCD - CPR)
|
|
Destination Clock Delay (DCD): -0.310ns
|
|
Source Clock Delay (SCD): -0.543ns
|
|
Clock Pessimism Removal (CPR): 0.216ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock sys_clk rise edge) 0.000 0.000 r
|
|
K21 0.000 0.000 r clk (IN)
|
|
net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1
|
|
K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O
|
|
net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll
|
|
PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1)
|
|
-2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1
|
|
net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll
|
|
BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O
|
|
net (fo=10004, routed) 0.719 -0.543 u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/sys_clk
|
|
SLICE_X6Y62 FDRE r u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/top_reg[2]/C
|
|
------------------------------------------------------------------- -------------------
|
|
SLICE_X6Y62 FDRE (Prop_fdre_C_Q) 0.164 -0.379 r u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/top_reg[2]/Q
|
|
net (fo=18, routed) 0.215 -0.164 u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/tfifo/ram_reg_0_15_0_5/ADDRD2
|
|
SLICE_X6Y61 RAMD32 r u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/tfifo/ram_reg_0_15_0_5/RAMB/WADR2
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock sys_clk rise edge) 0.000 0.000 r
|
|
K21 0.000 0.000 r clk (IN)
|
|
net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1
|
|
K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O
|
|
net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll
|
|
PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1)
|
|
-2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1
|
|
net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll
|
|
BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O
|
|
net (fo=10004, routed) 0.998 -0.310 u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/tfifo/ram_reg_0_15_0_5/WCLK
|
|
SLICE_X6Y61 RAMD32 r u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/tfifo/ram_reg_0_15_0_5/RAMB/CLK
|
|
clock pessimism -0.216 -0.526
|
|
SLICE_X6Y61 RAMD32 (Hold_ramd32_CLK_WADR2)
|
|
0.254 -0.272 u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/tfifo/ram_reg_0_15_0_5/RAMB
|
|
-------------------------------------------------------------------
|
|
required time 0.272
|
|
arrival time -0.164
|
|
-------------------------------------------------------------------
|
|
slack 0.108
|
|
|
|
Slack (MET) : 0.108ns (arrival time - required time)
|
|
Source: u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/top_reg[2]/C
|
|
(rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Destination: u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/tfifo/ram_reg_0_15_0_5/RAMB_D1/WADR2
|
|
(rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Path Group: sys_clk
|
|
Path Type: Hold (Min at Fast Process Corner)
|
|
Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns)
|
|
Data Path Delay: 0.379ns (logic 0.164ns (43.254%) route 0.215ns (56.746%))
|
|
Logic Levels: 0
|
|
Clock Path Skew: 0.017ns (DCD - SCD - CPR)
|
|
Destination Clock Delay (DCD): -0.310ns
|
|
Source Clock Delay (SCD): -0.543ns
|
|
Clock Pessimism Removal (CPR): 0.216ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock sys_clk rise edge) 0.000 0.000 r
|
|
K21 0.000 0.000 r clk (IN)
|
|
net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1
|
|
K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O
|
|
net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll
|
|
PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1)
|
|
-2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1
|
|
net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll
|
|
BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O
|
|
net (fo=10004, routed) 0.719 -0.543 u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/sys_clk
|
|
SLICE_X6Y62 FDRE r u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/top_reg[2]/C
|
|
------------------------------------------------------------------- -------------------
|
|
SLICE_X6Y62 FDRE (Prop_fdre_C_Q) 0.164 -0.379 r u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/top_reg[2]/Q
|
|
net (fo=18, routed) 0.215 -0.164 u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/tfifo/ram_reg_0_15_0_5/ADDRD2
|
|
SLICE_X6Y61 RAMD32 r u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/tfifo/ram_reg_0_15_0_5/RAMB_D1/WADR2
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock sys_clk rise edge) 0.000 0.000 r
|
|
K21 0.000 0.000 r clk (IN)
|
|
net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1
|
|
K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O
|
|
net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll
|
|
PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1)
|
|
-2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1
|
|
net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll
|
|
BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O
|
|
net (fo=10004, routed) 0.998 -0.310 u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/tfifo/ram_reg_0_15_0_5/WCLK
|
|
SLICE_X6Y61 RAMD32 r u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/tfifo/ram_reg_0_15_0_5/RAMB_D1/CLK
|
|
clock pessimism -0.216 -0.526
|
|
SLICE_X6Y61 RAMD32 (Hold_ramd32_CLK_WADR2)
|
|
0.254 -0.272 u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/tfifo/ram_reg_0_15_0_5/RAMB_D1
|
|
-------------------------------------------------------------------
|
|
required time 0.272
|
|
arrival time -0.164
|
|
-------------------------------------------------------------------
|
|
slack 0.108
|
|
|
|
Slack (MET) : 0.108ns (arrival time - required time)
|
|
Source: u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/top_reg[2]/C
|
|
(rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Destination: u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/tfifo/ram_reg_0_15_0_5/RAMC/WADR2
|
|
(rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Path Group: sys_clk
|
|
Path Type: Hold (Min at Fast Process Corner)
|
|
Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns)
|
|
Data Path Delay: 0.379ns (logic 0.164ns (43.254%) route 0.215ns (56.746%))
|
|
Logic Levels: 0
|
|
Clock Path Skew: 0.017ns (DCD - SCD - CPR)
|
|
Destination Clock Delay (DCD): -0.310ns
|
|
Source Clock Delay (SCD): -0.543ns
|
|
Clock Pessimism Removal (CPR): 0.216ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock sys_clk rise edge) 0.000 0.000 r
|
|
K21 0.000 0.000 r clk (IN)
|
|
net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1
|
|
K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O
|
|
net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll
|
|
PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1)
|
|
-2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1
|
|
net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll
|
|
BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O
|
|
net (fo=10004, routed) 0.719 -0.543 u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/sys_clk
|
|
SLICE_X6Y62 FDRE r u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/top_reg[2]/C
|
|
------------------------------------------------------------------- -------------------
|
|
SLICE_X6Y62 FDRE (Prop_fdre_C_Q) 0.164 -0.379 r u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/top_reg[2]/Q
|
|
net (fo=18, routed) 0.215 -0.164 u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/tfifo/ram_reg_0_15_0_5/ADDRD2
|
|
SLICE_X6Y61 RAMD32 r u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/tfifo/ram_reg_0_15_0_5/RAMC/WADR2
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock sys_clk rise edge) 0.000 0.000 r
|
|
K21 0.000 0.000 r clk (IN)
|
|
net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1
|
|
K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O
|
|
net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll
|
|
PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1)
|
|
-2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1
|
|
net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll
|
|
BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O
|
|
net (fo=10004, routed) 0.998 -0.310 u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/tfifo/ram_reg_0_15_0_5/WCLK
|
|
SLICE_X6Y61 RAMD32 r u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/tfifo/ram_reg_0_15_0_5/RAMC/CLK
|
|
clock pessimism -0.216 -0.526
|
|
SLICE_X6Y61 RAMD32 (Hold_ramd32_CLK_WADR2)
|
|
0.254 -0.272 u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/tfifo/ram_reg_0_15_0_5/RAMC
|
|
-------------------------------------------------------------------
|
|
required time 0.272
|
|
arrival time -0.164
|
|
-------------------------------------------------------------------
|
|
slack 0.108
|
|
|
|
Slack (MET) : 0.108ns (arrival time - required time)
|
|
Source: u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/top_reg[2]/C
|
|
(rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Destination: u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/tfifo/ram_reg_0_15_0_5/RAMC_D1/WADR2
|
|
(rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Path Group: sys_clk
|
|
Path Type: Hold (Min at Fast Process Corner)
|
|
Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns)
|
|
Data Path Delay: 0.379ns (logic 0.164ns (43.254%) route 0.215ns (56.746%))
|
|
Logic Levels: 0
|
|
Clock Path Skew: 0.017ns (DCD - SCD - CPR)
|
|
Destination Clock Delay (DCD): -0.310ns
|
|
Source Clock Delay (SCD): -0.543ns
|
|
Clock Pessimism Removal (CPR): 0.216ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock sys_clk rise edge) 0.000 0.000 r
|
|
K21 0.000 0.000 r clk (IN)
|
|
net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1
|
|
K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O
|
|
net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll
|
|
PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1)
|
|
-2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1
|
|
net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll
|
|
BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O
|
|
net (fo=10004, routed) 0.719 -0.543 u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/sys_clk
|
|
SLICE_X6Y62 FDRE r u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/top_reg[2]/C
|
|
------------------------------------------------------------------- -------------------
|
|
SLICE_X6Y62 FDRE (Prop_fdre_C_Q) 0.164 -0.379 r u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/top_reg[2]/Q
|
|
net (fo=18, routed) 0.215 -0.164 u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/tfifo/ram_reg_0_15_0_5/ADDRD2
|
|
SLICE_X6Y61 RAMD32 r u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/tfifo/ram_reg_0_15_0_5/RAMC_D1/WADR2
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock sys_clk rise edge) 0.000 0.000 r
|
|
K21 0.000 0.000 r clk (IN)
|
|
net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1
|
|
K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O
|
|
net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll
|
|
PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1)
|
|
-2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1
|
|
net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll
|
|
BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O
|
|
net (fo=10004, routed) 0.998 -0.310 u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/tfifo/ram_reg_0_15_0_5/WCLK
|
|
SLICE_X6Y61 RAMD32 r u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/tfifo/ram_reg_0_15_0_5/RAMC_D1/CLK
|
|
clock pessimism -0.216 -0.526
|
|
SLICE_X6Y61 RAMD32 (Hold_ramd32_CLK_WADR2)
|
|
0.254 -0.272 u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/tfifo/ram_reg_0_15_0_5/RAMC_D1
|
|
-------------------------------------------------------------------
|
|
required time 0.272
|
|
arrival time -0.164
|
|
-------------------------------------------------------------------
|
|
slack 0.108
|
|
|
|
Slack (MET) : 0.108ns (arrival time - required time)
|
|
Source: u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/top_reg[2]/C
|
|
(rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Destination: u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/tfifo/ram_reg_0_15_0_5/RAMD/ADR2
|
|
(rising edge-triggered cell RAMS32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Path Group: sys_clk
|
|
Path Type: Hold (Min at Fast Process Corner)
|
|
Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns)
|
|
Data Path Delay: 0.379ns (logic 0.164ns (43.254%) route 0.215ns (56.746%))
|
|
Logic Levels: 0
|
|
Clock Path Skew: 0.017ns (DCD - SCD - CPR)
|
|
Destination Clock Delay (DCD): -0.310ns
|
|
Source Clock Delay (SCD): -0.543ns
|
|
Clock Pessimism Removal (CPR): 0.216ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock sys_clk rise edge) 0.000 0.000 r
|
|
K21 0.000 0.000 r clk (IN)
|
|
net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1
|
|
K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O
|
|
net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll
|
|
PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1)
|
|
-2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1
|
|
net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll
|
|
BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O
|
|
net (fo=10004, routed) 0.719 -0.543 u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/sys_clk
|
|
SLICE_X6Y62 FDRE r u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/top_reg[2]/C
|
|
------------------------------------------------------------------- -------------------
|
|
SLICE_X6Y62 FDRE (Prop_fdre_C_Q) 0.164 -0.379 r u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/top_reg[2]/Q
|
|
net (fo=18, routed) 0.215 -0.164 u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/tfifo/ram_reg_0_15_0_5/ADDRD2
|
|
SLICE_X6Y61 RAMS32 r u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/tfifo/ram_reg_0_15_0_5/RAMD/ADR2
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock sys_clk rise edge) 0.000 0.000 r
|
|
K21 0.000 0.000 r clk (IN)
|
|
net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1
|
|
K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O
|
|
net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll
|
|
PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1)
|
|
-2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1
|
|
net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll
|
|
BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O
|
|
net (fo=10004, routed) 0.998 -0.310 u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/tfifo/ram_reg_0_15_0_5/WCLK
|
|
SLICE_X6Y61 RAMS32 r u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/tfifo/ram_reg_0_15_0_5/RAMD/CLK
|
|
clock pessimism -0.216 -0.526
|
|
SLICE_X6Y61 RAMS32 (Hold_rams32_CLK_ADR2)
|
|
0.254 -0.272 u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/tfifo/ram_reg_0_15_0_5/RAMD
|
|
-------------------------------------------------------------------
|
|
required time 0.272
|
|
arrival time -0.164
|
|
-------------------------------------------------------------------
|
|
slack 0.108
|
|
|
|
Slack (MET) : 0.108ns (arrival time - required time)
|
|
Source: u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/top_reg[2]/C
|
|
(rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Destination: u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/tfifo/ram_reg_0_15_0_5/RAMD_D1/ADR2
|
|
(rising edge-triggered cell RAMS32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Path Group: sys_clk
|
|
Path Type: Hold (Min at Fast Process Corner)
|
|
Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns)
|
|
Data Path Delay: 0.379ns (logic 0.164ns (43.254%) route 0.215ns (56.746%))
|
|
Logic Levels: 0
|
|
Clock Path Skew: 0.017ns (DCD - SCD - CPR)
|
|
Destination Clock Delay (DCD): -0.310ns
|
|
Source Clock Delay (SCD): -0.543ns
|
|
Clock Pessimism Removal (CPR): 0.216ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock sys_clk rise edge) 0.000 0.000 r
|
|
K21 0.000 0.000 r clk (IN)
|
|
net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1
|
|
K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O
|
|
net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll
|
|
PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1)
|
|
-2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1
|
|
net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll
|
|
BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O
|
|
net (fo=10004, routed) 0.719 -0.543 u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/sys_clk
|
|
SLICE_X6Y62 FDRE r u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/top_reg[2]/C
|
|
------------------------------------------------------------------- -------------------
|
|
SLICE_X6Y62 FDRE (Prop_fdre_C_Q) 0.164 -0.379 r u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/top_reg[2]/Q
|
|
net (fo=18, routed) 0.215 -0.164 u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/tfifo/ram_reg_0_15_0_5/ADDRD2
|
|
SLICE_X6Y61 RAMS32 r u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/tfifo/ram_reg_0_15_0_5/RAMD_D1/ADR2
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock sys_clk rise edge) 0.000 0.000 r
|
|
K21 0.000 0.000 r clk (IN)
|
|
net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1
|
|
K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O
|
|
net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll
|
|
PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1)
|
|
-2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1
|
|
net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll
|
|
BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O
|
|
net (fo=10004, routed) 0.998 -0.310 u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/tfifo/ram_reg_0_15_0_5/WCLK
|
|
SLICE_X6Y61 RAMS32 r u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/tfifo/ram_reg_0_15_0_5/RAMD_D1/CLK
|
|
clock pessimism -0.216 -0.526
|
|
SLICE_X6Y61 RAMS32 (Hold_rams32_CLK_ADR2)
|
|
0.254 -0.272 u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/tfifo/ram_reg_0_15_0_5/RAMD_D1
|
|
-------------------------------------------------------------------
|
|
required time 0.272
|
|
arrival time -0.164
|
|
-------------------------------------------------------------------
|
|
slack 0.108
|
|
|
|
Slack (MET) : 0.108ns (arrival time - required time)
|
|
Source: u_matmul_axi_slave/mult_inst[1].u_mult/prod_reg[48]/C
|
|
(rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Destination: u_matmul_axi_slave/mult_inst[1].u_mult/p_reg[48]/D
|
|
(rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Path Group: sys_clk
|
|
Path Type: Hold (Min at Fast Process Corner)
|
|
Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns)
|
|
Data Path Delay: 0.509ns (logic 0.164ns (32.204%) route 0.345ns (67.796%))
|
|
Logic Levels: 0
|
|
Clock Path Skew: 0.335ns (DCD - SCD - CPR)
|
|
Destination Clock Delay (DCD): -0.338ns
|
|
Source Clock Delay (SCD): -0.633ns
|
|
Clock Pessimism Removal (CPR): -0.040ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock sys_clk rise edge) 0.000 0.000 r
|
|
K21 0.000 0.000 r clk (IN)
|
|
net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1
|
|
K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O
|
|
net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll
|
|
PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1)
|
|
-2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1
|
|
net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll
|
|
BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O
|
|
net (fo=10004, routed) 0.630 -0.633 u_matmul_axi_slave/mult_inst[1].u_mult/sys_clk
|
|
SLICE_X14Y102 FDRE r u_matmul_axi_slave/mult_inst[1].u_mult/prod_reg[48]/C
|
|
------------------------------------------------------------------- -------------------
|
|
SLICE_X14Y102 FDRE (Prop_fdre_C_Q) 0.164 -0.469 r u_matmul_axi_slave/mult_inst[1].u_mult/prod_reg[48]/Q
|
|
net (fo=1, routed) 0.345 -0.124 u_matmul_axi_slave/mult_inst[1].u_mult/prod[48]
|
|
SLICE_X17Y92 FDRE r u_matmul_axi_slave/mult_inst[1].u_mult/p_reg[48]/D
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock sys_clk rise edge) 0.000 0.000 r
|
|
K21 0.000 0.000 r clk (IN)
|
|
net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1
|
|
K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O
|
|
net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll
|
|
PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1)
|
|
-2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1
|
|
net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll
|
|
BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O
|
|
net (fo=10004, routed) 0.970 -0.338 u_matmul_axi_slave/mult_inst[1].u_mult/sys_clk
|
|
SLICE_X17Y92 FDRE r u_matmul_axi_slave/mult_inst[1].u_mult/p_reg[48]/C
|
|
clock pessimism 0.040 -0.298
|
|
SLICE_X17Y92 FDRE (Hold_fdre_C_D) 0.066 -0.232 u_matmul_axi_slave/mult_inst[1].u_mult/p_reg[48]
|
|
-------------------------------------------------------------------
|
|
required time 0.232
|
|
arrival time -0.124
|
|
-------------------------------------------------------------------
|
|
slack 0.108
|
|
|
|
Slack (MET) : 0.117ns (arrival time - required time)
|
|
Source: u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdRouteFork_translated_fifo/fifo/logic_ptr_push_reg[0]/C
|
|
(rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Destination: axi4WriteOnlyArbiter_4/cmdRouteFork_translated_fifo/fifo/logic_ram_reg_0_3_0_0/DP/WADR0
|
|
(rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Path Group: sys_clk
|
|
Path Type: Hold (Min at Fast Process Corner)
|
|
Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns)
|
|
Data Path Delay: 0.463ns (logic 0.164ns (35.436%) route 0.299ns (64.564%))
|
|
Logic Levels: 0
|
|
Clock Path Skew: 0.036ns (DCD - SCD - CPR)
|
|
Destination Clock Delay (DCD): -0.322ns
|
|
Source Clock Delay (SCD): -0.550ns
|
|
Clock Pessimism Removal (CPR): 0.192ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock sys_clk rise edge) 0.000 0.000 r
|
|
K21 0.000 0.000 r clk (IN)
|
|
net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1
|
|
K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O
|
|
net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll
|
|
PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1)
|
|
-2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1
|
|
net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll
|
|
BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O
|
|
net (fo=10004, routed) 0.712 -0.550 u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdRouteFork_translated_fifo/fifo/sys_clk
|
|
SLICE_X2Y75 FDCE r u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdRouteFork_translated_fifo/fifo/logic_ptr_push_reg[0]/C
|
|
------------------------------------------------------------------- -------------------
|
|
SLICE_X2Y75 FDCE (Prop_fdce_C_Q) 0.164 -0.386 r u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdRouteFork_translated_fifo/fifo/logic_ptr_push_reg[0]/Q
|
|
net (fo=8, routed) 0.299 -0.088 axi4WriteOnlyArbiter_4/cmdRouteFork_translated_fifo/fifo/logic_ram_reg_0_3_0_0/A0
|
|
SLICE_X2Y74 RAMD32 r axi4WriteOnlyArbiter_4/cmdRouteFork_translated_fifo/fifo/logic_ram_reg_0_3_0_0/DP/WADR0
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock sys_clk rise edge) 0.000 0.000 r
|
|
K21 0.000 0.000 r clk (IN)
|
|
net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1
|
|
K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O
|
|
net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll
|
|
PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1)
|
|
-2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1
|
|
net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll
|
|
BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O
|
|
net (fo=10004, routed) 0.986 -0.322 axi4WriteOnlyArbiter_4/cmdRouteFork_translated_fifo/fifo/logic_ram_reg_0_3_0_0/WCLK
|
|
SLICE_X2Y74 RAMD32 r axi4WriteOnlyArbiter_4/cmdRouteFork_translated_fifo/fifo/logic_ram_reg_0_3_0_0/DP/CLK
|
|
clock pessimism -0.192 -0.514
|
|
SLICE_X2Y74 RAMD32 (Hold_ramd32_CLK_WADR0)
|
|
0.310 -0.204 axi4WriteOnlyArbiter_4/cmdRouteFork_translated_fifo/fifo/logic_ram_reg_0_3_0_0/DP
|
|
-------------------------------------------------------------------
|
|
required time 0.204
|
|
arrival time -0.088
|
|
-------------------------------------------------------------------
|
|
slack 0.117
|
|
|
|
Slack (MET) : 0.117ns (arrival time - required time)
|
|
Source: u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdRouteFork_translated_fifo/fifo/logic_ptr_push_reg[0]/C
|
|
(rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Destination: axi4WriteOnlyArbiter_4/cmdRouteFork_translated_fifo/fifo/logic_ram_reg_0_3_0_0/SP/WADR0
|
|
(rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Path Group: sys_clk
|
|
Path Type: Hold (Min at Fast Process Corner)
|
|
Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns)
|
|
Data Path Delay: 0.463ns (logic 0.164ns (35.436%) route 0.299ns (64.564%))
|
|
Logic Levels: 0
|
|
Clock Path Skew: 0.036ns (DCD - SCD - CPR)
|
|
Destination Clock Delay (DCD): -0.322ns
|
|
Source Clock Delay (SCD): -0.550ns
|
|
Clock Pessimism Removal (CPR): 0.192ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock sys_clk rise edge) 0.000 0.000 r
|
|
K21 0.000 0.000 r clk (IN)
|
|
net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1
|
|
K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O
|
|
net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll
|
|
PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1)
|
|
-2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1
|
|
net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll
|
|
BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O
|
|
net (fo=10004, routed) 0.712 -0.550 u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdRouteFork_translated_fifo/fifo/sys_clk
|
|
SLICE_X2Y75 FDCE r u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdRouteFork_translated_fifo/fifo/logic_ptr_push_reg[0]/C
|
|
------------------------------------------------------------------- -------------------
|
|
SLICE_X2Y75 FDCE (Prop_fdce_C_Q) 0.164 -0.386 r u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdRouteFork_translated_fifo/fifo/logic_ptr_push_reg[0]/Q
|
|
net (fo=8, routed) 0.299 -0.088 axi4WriteOnlyArbiter_4/cmdRouteFork_translated_fifo/fifo/logic_ram_reg_0_3_0_0/A0
|
|
SLICE_X2Y74 RAMD32 r axi4WriteOnlyArbiter_4/cmdRouteFork_translated_fifo/fifo/logic_ram_reg_0_3_0_0/SP/WADR0
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock sys_clk rise edge) 0.000 0.000 r
|
|
K21 0.000 0.000 r clk (IN)
|
|
net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1
|
|
K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O
|
|
net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll
|
|
PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1)
|
|
-2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1
|
|
net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll
|
|
BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O
|
|
net (fo=10004, routed) 0.986 -0.322 axi4WriteOnlyArbiter_4/cmdRouteFork_translated_fifo/fifo/logic_ram_reg_0_3_0_0/WCLK
|
|
SLICE_X2Y74 RAMD32 r axi4WriteOnlyArbiter_4/cmdRouteFork_translated_fifo/fifo/logic_ram_reg_0_3_0_0/SP/CLK
|
|
clock pessimism -0.192 -0.514
|
|
SLICE_X2Y74 RAMD32 (Hold_ramd32_CLK_WADR0)
|
|
0.310 -0.204 axi4WriteOnlyArbiter_4/cmdRouteFork_translated_fifo/fifo/logic_ram_reg_0_3_0_0/SP
|
|
-------------------------------------------------------------------
|
|
required time 0.204
|
|
arrival time -0.088
|
|
-------------------------------------------------------------------
|
|
slack 0.117
|
|
|
|
Slack (MET) : 0.117ns (arrival time - required time)
|
|
Source: u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdRouteFork_translated_fifo/fifo/logic_ptr_push_reg[1]/C
|
|
(rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Destination: axi4WriteOnlyArbiter_4/cmdRouteFork_translated_fifo/fifo/logic_ram_reg_0_3_0_0/DP/WADR1
|
|
(rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Path Group: sys_clk
|
|
Path Type: Hold (Min at Fast Process Corner)
|
|
Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns)
|
|
Data Path Delay: 0.462ns (logic 0.164ns (35.508%) route 0.298ns (64.492%))
|
|
Logic Levels: 0
|
|
Clock Path Skew: 0.036ns (DCD - SCD - CPR)
|
|
Destination Clock Delay (DCD): -0.322ns
|
|
Source Clock Delay (SCD): -0.550ns
|
|
Clock Pessimism Removal (CPR): 0.192ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock sys_clk rise edge) 0.000 0.000 r
|
|
K21 0.000 0.000 r clk (IN)
|
|
net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1
|
|
K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O
|
|
net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll
|
|
PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1)
|
|
-2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1
|
|
net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll
|
|
BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O
|
|
net (fo=10004, routed) 0.712 -0.550 u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdRouteFork_translated_fifo/fifo/sys_clk
|
|
SLICE_X2Y75 FDCE r u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdRouteFork_translated_fifo/fifo/logic_ptr_push_reg[1]/C
|
|
------------------------------------------------------------------- -------------------
|
|
SLICE_X2Y75 FDCE (Prop_fdce_C_Q) 0.164 -0.386 r u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdRouteFork_translated_fifo/fifo/logic_ptr_push_reg[1]/Q
|
|
net (fo=7, routed) 0.298 -0.089 axi4WriteOnlyArbiter_4/cmdRouteFork_translated_fifo/fifo/logic_ram_reg_0_3_0_0/A1
|
|
SLICE_X2Y74 RAMD32 r axi4WriteOnlyArbiter_4/cmdRouteFork_translated_fifo/fifo/logic_ram_reg_0_3_0_0/DP/WADR1
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock sys_clk rise edge) 0.000 0.000 r
|
|
K21 0.000 0.000 r clk (IN)
|
|
net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1
|
|
K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O
|
|
net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll
|
|
PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1)
|
|
-2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1
|
|
net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll
|
|
BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O
|
|
net (fo=10004, routed) 0.986 -0.322 axi4WriteOnlyArbiter_4/cmdRouteFork_translated_fifo/fifo/logic_ram_reg_0_3_0_0/WCLK
|
|
SLICE_X2Y74 RAMD32 r axi4WriteOnlyArbiter_4/cmdRouteFork_translated_fifo/fifo/logic_ram_reg_0_3_0_0/DP/CLK
|
|
clock pessimism -0.192 -0.514
|
|
SLICE_X2Y74 RAMD32 (Hold_ramd32_CLK_WADR1)
|
|
0.309 -0.205 axi4WriteOnlyArbiter_4/cmdRouteFork_translated_fifo/fifo/logic_ram_reg_0_3_0_0/DP
|
|
-------------------------------------------------------------------
|
|
required time 0.205
|
|
arrival time -0.089
|
|
-------------------------------------------------------------------
|
|
slack 0.117
|
|
|
|
Slack (MET) : 0.117ns (arrival time - required time)
|
|
Source: u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdRouteFork_translated_fifo/fifo/logic_ptr_push_reg[1]/C
|
|
(rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Destination: axi4WriteOnlyArbiter_4/cmdRouteFork_translated_fifo/fifo/logic_ram_reg_0_3_0_0/SP/WADR1
|
|
(rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Path Group: sys_clk
|
|
Path Type: Hold (Min at Fast Process Corner)
|
|
Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns)
|
|
Data Path Delay: 0.462ns (logic 0.164ns (35.508%) route 0.298ns (64.492%))
|
|
Logic Levels: 0
|
|
Clock Path Skew: 0.036ns (DCD - SCD - CPR)
|
|
Destination Clock Delay (DCD): -0.322ns
|
|
Source Clock Delay (SCD): -0.550ns
|
|
Clock Pessimism Removal (CPR): 0.192ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock sys_clk rise edge) 0.000 0.000 r
|
|
K21 0.000 0.000 r clk (IN)
|
|
net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1
|
|
K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O
|
|
net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll
|
|
PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1)
|
|
-2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1
|
|
net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll
|
|
BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O
|
|
net (fo=10004, routed) 0.712 -0.550 u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdRouteFork_translated_fifo/fifo/sys_clk
|
|
SLICE_X2Y75 FDCE r u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdRouteFork_translated_fifo/fifo/logic_ptr_push_reg[1]/C
|
|
------------------------------------------------------------------- -------------------
|
|
SLICE_X2Y75 FDCE (Prop_fdce_C_Q) 0.164 -0.386 r u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdRouteFork_translated_fifo/fifo/logic_ptr_push_reg[1]/Q
|
|
net (fo=7, routed) 0.298 -0.089 axi4WriteOnlyArbiter_4/cmdRouteFork_translated_fifo/fifo/logic_ram_reg_0_3_0_0/A1
|
|
SLICE_X2Y74 RAMD32 r axi4WriteOnlyArbiter_4/cmdRouteFork_translated_fifo/fifo/logic_ram_reg_0_3_0_0/SP/WADR1
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock sys_clk rise edge) 0.000 0.000 r
|
|
K21 0.000 0.000 r clk (IN)
|
|
net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1
|
|
K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O
|
|
net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll
|
|
PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1)
|
|
-2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1
|
|
net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll
|
|
BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O
|
|
net (fo=10004, routed) 0.986 -0.322 axi4WriteOnlyArbiter_4/cmdRouteFork_translated_fifo/fifo/logic_ram_reg_0_3_0_0/WCLK
|
|
SLICE_X2Y74 RAMD32 r axi4WriteOnlyArbiter_4/cmdRouteFork_translated_fifo/fifo/logic_ram_reg_0_3_0_0/SP/CLK
|
|
clock pessimism -0.192 -0.514
|
|
SLICE_X2Y74 RAMD32 (Hold_ramd32_CLK_WADR1)
|
|
0.309 -0.205 axi4WriteOnlyArbiter_4/cmdRouteFork_translated_fifo/fifo/logic_ram_reg_0_3_0_0/SP
|
|
-------------------------------------------------------------------
|
|
required time 0.205
|
|
arrival time -0.089
|
|
-------------------------------------------------------------------
|
|
slack 0.117
|
|
|
|
Slack (MET) : 0.117ns (arrival time - required time)
|
|
Source: u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/top_reg[0]/C
|
|
(rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Destination: u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/tfifo/ram_reg_0_15_0_5/RAMA/WADR0
|
|
(rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Path Group: sys_clk
|
|
Path Type: Hold (Min at Fast Process Corner)
|
|
Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns)
|
|
Data Path Delay: 0.444ns (logic 0.164ns (36.916%) route 0.280ns (63.084%))
|
|
Logic Levels: 0
|
|
Clock Path Skew: 0.017ns (DCD - SCD - CPR)
|
|
Destination Clock Delay (DCD): -0.310ns
|
|
Source Clock Delay (SCD): -0.543ns
|
|
Clock Pessimism Removal (CPR): 0.216ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock sys_clk rise edge) 0.000 0.000 r
|
|
K21 0.000 0.000 r clk (IN)
|
|
net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1
|
|
K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O
|
|
net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll
|
|
PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1)
|
|
-2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1
|
|
net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll
|
|
BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O
|
|
net (fo=10004, routed) 0.719 -0.543 u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/sys_clk
|
|
SLICE_X6Y62 FDRE r u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/top_reg[0]/C
|
|
------------------------------------------------------------------- -------------------
|
|
SLICE_X6Y62 FDRE (Prop_fdre_C_Q) 0.164 -0.379 r u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/top_reg[0]/Q
|
|
net (fo=20, routed) 0.280 -0.099 u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/tfifo/ram_reg_0_15_0_5/ADDRD0
|
|
SLICE_X6Y61 RAMD32 r u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/tfifo/ram_reg_0_15_0_5/RAMA/WADR0
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock sys_clk rise edge) 0.000 0.000 r
|
|
K21 0.000 0.000 r clk (IN)
|
|
net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1
|
|
K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O
|
|
net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll
|
|
PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1)
|
|
-2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1
|
|
net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll
|
|
BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O
|
|
net (fo=10004, routed) 0.998 -0.310 u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/tfifo/ram_reg_0_15_0_5/WCLK
|
|
SLICE_X6Y61 RAMD32 r u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/tfifo/ram_reg_0_15_0_5/RAMA/CLK
|
|
clock pessimism -0.216 -0.526
|
|
SLICE_X6Y61 RAMD32 (Hold_ramd32_CLK_WADR0)
|
|
0.310 -0.216 u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/tfifo/ram_reg_0_15_0_5/RAMA
|
|
-------------------------------------------------------------------
|
|
required time 0.216
|
|
arrival time -0.099
|
|
-------------------------------------------------------------------
|
|
slack 0.117
|
|
|
|
Slack (MET) : 0.117ns (arrival time - required time)
|
|
Source: u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/top_reg[0]/C
|
|
(rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Destination: u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/tfifo/ram_reg_0_15_0_5/RAMA_D1/WADR0
|
|
(rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Path Group: sys_clk
|
|
Path Type: Hold (Min at Fast Process Corner)
|
|
Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns)
|
|
Data Path Delay: 0.444ns (logic 0.164ns (36.916%) route 0.280ns (63.084%))
|
|
Logic Levels: 0
|
|
Clock Path Skew: 0.017ns (DCD - SCD - CPR)
|
|
Destination Clock Delay (DCD): -0.310ns
|
|
Source Clock Delay (SCD): -0.543ns
|
|
Clock Pessimism Removal (CPR): 0.216ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock sys_clk rise edge) 0.000 0.000 r
|
|
K21 0.000 0.000 r clk (IN)
|
|
net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1
|
|
K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O
|
|
net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll
|
|
PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1)
|
|
-2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1
|
|
net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll
|
|
BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O
|
|
net (fo=10004, routed) 0.719 -0.543 u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/sys_clk
|
|
SLICE_X6Y62 FDRE r u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/top_reg[0]/C
|
|
------------------------------------------------------------------- -------------------
|
|
SLICE_X6Y62 FDRE (Prop_fdre_C_Q) 0.164 -0.379 r u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/top_reg[0]/Q
|
|
net (fo=20, routed) 0.280 -0.099 u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/tfifo/ram_reg_0_15_0_5/ADDRD0
|
|
SLICE_X6Y61 RAMD32 r u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/tfifo/ram_reg_0_15_0_5/RAMA_D1/WADR0
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock sys_clk rise edge) 0.000 0.000 r
|
|
K21 0.000 0.000 r clk (IN)
|
|
net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1
|
|
K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O
|
|
net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll
|
|
PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1)
|
|
-2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1
|
|
net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll
|
|
BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O
|
|
net (fo=10004, routed) 0.998 -0.310 u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/tfifo/ram_reg_0_15_0_5/WCLK
|
|
SLICE_X6Y61 RAMD32 r u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/tfifo/ram_reg_0_15_0_5/RAMA_D1/CLK
|
|
clock pessimism -0.216 -0.526
|
|
SLICE_X6Y61 RAMD32 (Hold_ramd32_CLK_WADR0)
|
|
0.310 -0.216 u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/tfifo/ram_reg_0_15_0_5/RAMA_D1
|
|
-------------------------------------------------------------------
|
|
required time 0.216
|
|
arrival time -0.099
|
|
-------------------------------------------------------------------
|
|
slack 0.117
|
|
|
|
Slack (MET) : 0.117ns (arrival time - required time)
|
|
Source: u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/top_reg[0]/C
|
|
(rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Destination: u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/tfifo/ram_reg_0_15_0_5/RAMB/WADR0
|
|
(rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Path Group: sys_clk
|
|
Path Type: Hold (Min at Fast Process Corner)
|
|
Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns)
|
|
Data Path Delay: 0.444ns (logic 0.164ns (36.916%) route 0.280ns (63.084%))
|
|
Logic Levels: 0
|
|
Clock Path Skew: 0.017ns (DCD - SCD - CPR)
|
|
Destination Clock Delay (DCD): -0.310ns
|
|
Source Clock Delay (SCD): -0.543ns
|
|
Clock Pessimism Removal (CPR): 0.216ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock sys_clk rise edge) 0.000 0.000 r
|
|
K21 0.000 0.000 r clk (IN)
|
|
net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1
|
|
K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O
|
|
net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll
|
|
PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1)
|
|
-2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1
|
|
net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll
|
|
BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O
|
|
net (fo=10004, routed) 0.719 -0.543 u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/sys_clk
|
|
SLICE_X6Y62 FDRE r u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/top_reg[0]/C
|
|
------------------------------------------------------------------- -------------------
|
|
SLICE_X6Y62 FDRE (Prop_fdre_C_Q) 0.164 -0.379 r u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/top_reg[0]/Q
|
|
net (fo=20, routed) 0.280 -0.099 u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/tfifo/ram_reg_0_15_0_5/ADDRD0
|
|
SLICE_X6Y61 RAMD32 r u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/tfifo/ram_reg_0_15_0_5/RAMB/WADR0
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock sys_clk rise edge) 0.000 0.000 r
|
|
K21 0.000 0.000 r clk (IN)
|
|
net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1
|
|
K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O
|
|
net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll
|
|
PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1)
|
|
-2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1
|
|
net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll
|
|
BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O
|
|
net (fo=10004, routed) 0.998 -0.310 u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/tfifo/ram_reg_0_15_0_5/WCLK
|
|
SLICE_X6Y61 RAMD32 r u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/tfifo/ram_reg_0_15_0_5/RAMB/CLK
|
|
clock pessimism -0.216 -0.526
|
|
SLICE_X6Y61 RAMD32 (Hold_ramd32_CLK_WADR0)
|
|
0.310 -0.216 u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/tfifo/ram_reg_0_15_0_5/RAMB
|
|
-------------------------------------------------------------------
|
|
required time 0.216
|
|
arrival time -0.099
|
|
-------------------------------------------------------------------
|
|
slack 0.117
|
|
|
|
Slack (MET) : 0.117ns (arrival time - required time)
|
|
Source: u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/top_reg[0]/C
|
|
(rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Destination: u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/tfifo/ram_reg_0_15_0_5/RAMB_D1/WADR0
|
|
(rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Path Group: sys_clk
|
|
Path Type: Hold (Min at Fast Process Corner)
|
|
Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns)
|
|
Data Path Delay: 0.444ns (logic 0.164ns (36.916%) route 0.280ns (63.084%))
|
|
Logic Levels: 0
|
|
Clock Path Skew: 0.017ns (DCD - SCD - CPR)
|
|
Destination Clock Delay (DCD): -0.310ns
|
|
Source Clock Delay (SCD): -0.543ns
|
|
Clock Pessimism Removal (CPR): 0.216ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock sys_clk rise edge) 0.000 0.000 r
|
|
K21 0.000 0.000 r clk (IN)
|
|
net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1
|
|
K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O
|
|
net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll
|
|
PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1)
|
|
-2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1
|
|
net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll
|
|
BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O
|
|
net (fo=10004, routed) 0.719 -0.543 u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/sys_clk
|
|
SLICE_X6Y62 FDRE r u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/top_reg[0]/C
|
|
------------------------------------------------------------------- -------------------
|
|
SLICE_X6Y62 FDRE (Prop_fdre_C_Q) 0.164 -0.379 r u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/top_reg[0]/Q
|
|
net (fo=20, routed) 0.280 -0.099 u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/tfifo/ram_reg_0_15_0_5/ADDRD0
|
|
SLICE_X6Y61 RAMD32 r u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/tfifo/ram_reg_0_15_0_5/RAMB_D1/WADR0
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock sys_clk rise edge) 0.000 0.000 r
|
|
K21 0.000 0.000 r clk (IN)
|
|
net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1
|
|
K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O
|
|
net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll
|
|
PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1)
|
|
-2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1
|
|
net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll
|
|
BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O
|
|
net (fo=10004, routed) 0.998 -0.310 u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/tfifo/ram_reg_0_15_0_5/WCLK
|
|
SLICE_X6Y61 RAMD32 r u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/tfifo/ram_reg_0_15_0_5/RAMB_D1/CLK
|
|
clock pessimism -0.216 -0.526
|
|
SLICE_X6Y61 RAMD32 (Hold_ramd32_CLK_WADR0)
|
|
0.310 -0.216 u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/tfifo/ram_reg_0_15_0_5/RAMB_D1
|
|
-------------------------------------------------------------------
|
|
required time 0.216
|
|
arrival time -0.099
|
|
-------------------------------------------------------------------
|
|
slack 0.117
|
|
|
|
Slack (MET) : 0.117ns (arrival time - required time)
|
|
Source: u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/top_reg[0]/C
|
|
(rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Destination: u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/tfifo/ram_reg_0_15_0_5/RAMC/WADR0
|
|
(rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Path Group: sys_clk
|
|
Path Type: Hold (Min at Fast Process Corner)
|
|
Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns)
|
|
Data Path Delay: 0.444ns (logic 0.164ns (36.916%) route 0.280ns (63.084%))
|
|
Logic Levels: 0
|
|
Clock Path Skew: 0.017ns (DCD - SCD - CPR)
|
|
Destination Clock Delay (DCD): -0.310ns
|
|
Source Clock Delay (SCD): -0.543ns
|
|
Clock Pessimism Removal (CPR): 0.216ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock sys_clk rise edge) 0.000 0.000 r
|
|
K21 0.000 0.000 r clk (IN)
|
|
net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1
|
|
K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O
|
|
net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll
|
|
PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1)
|
|
-2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1
|
|
net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll
|
|
BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O
|
|
net (fo=10004, routed) 0.719 -0.543 u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/sys_clk
|
|
SLICE_X6Y62 FDRE r u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/top_reg[0]/C
|
|
------------------------------------------------------------------- -------------------
|
|
SLICE_X6Y62 FDRE (Prop_fdre_C_Q) 0.164 -0.379 r u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/top_reg[0]/Q
|
|
net (fo=20, routed) 0.280 -0.099 u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/tfifo/ram_reg_0_15_0_5/ADDRD0
|
|
SLICE_X6Y61 RAMD32 r u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/tfifo/ram_reg_0_15_0_5/RAMC/WADR0
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock sys_clk rise edge) 0.000 0.000 r
|
|
K21 0.000 0.000 r clk (IN)
|
|
net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1
|
|
K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O
|
|
net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll
|
|
PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1)
|
|
-2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1
|
|
net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll
|
|
BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O
|
|
net (fo=10004, routed) 0.998 -0.310 u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/tfifo/ram_reg_0_15_0_5/WCLK
|
|
SLICE_X6Y61 RAMD32 r u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/tfifo/ram_reg_0_15_0_5/RAMC/CLK
|
|
clock pessimism -0.216 -0.526
|
|
SLICE_X6Y61 RAMD32 (Hold_ramd32_CLK_WADR0)
|
|
0.310 -0.216 u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/tfifo/ram_reg_0_15_0_5/RAMC
|
|
-------------------------------------------------------------------
|
|
required time 0.216
|
|
arrival time -0.099
|
|
-------------------------------------------------------------------
|
|
slack 0.117
|
|
|
|
Slack (MET) : 0.117ns (arrival time - required time)
|
|
Source: u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/top_reg[0]/C
|
|
(rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Destination: u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/tfifo/ram_reg_0_15_0_5/RAMC_D1/WADR0
|
|
(rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Path Group: sys_clk
|
|
Path Type: Hold (Min at Fast Process Corner)
|
|
Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns)
|
|
Data Path Delay: 0.444ns (logic 0.164ns (36.916%) route 0.280ns (63.084%))
|
|
Logic Levels: 0
|
|
Clock Path Skew: 0.017ns (DCD - SCD - CPR)
|
|
Destination Clock Delay (DCD): -0.310ns
|
|
Source Clock Delay (SCD): -0.543ns
|
|
Clock Pessimism Removal (CPR): 0.216ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock sys_clk rise edge) 0.000 0.000 r
|
|
K21 0.000 0.000 r clk (IN)
|
|
net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1
|
|
K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O
|
|
net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll
|
|
PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1)
|
|
-2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1
|
|
net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll
|
|
BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O
|
|
net (fo=10004, routed) 0.719 -0.543 u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/sys_clk
|
|
SLICE_X6Y62 FDRE r u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/top_reg[0]/C
|
|
------------------------------------------------------------------- -------------------
|
|
SLICE_X6Y62 FDRE (Prop_fdre_C_Q) 0.164 -0.379 r u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/top_reg[0]/Q
|
|
net (fo=20, routed) 0.280 -0.099 u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/tfifo/ram_reg_0_15_0_5/ADDRD0
|
|
SLICE_X6Y61 RAMD32 r u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/tfifo/ram_reg_0_15_0_5/RAMC_D1/WADR0
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock sys_clk rise edge) 0.000 0.000 r
|
|
K21 0.000 0.000 r clk (IN)
|
|
net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1
|
|
K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O
|
|
net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll
|
|
PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1)
|
|
-2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1
|
|
net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll
|
|
BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O
|
|
net (fo=10004, routed) 0.998 -0.310 u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/tfifo/ram_reg_0_15_0_5/WCLK
|
|
SLICE_X6Y61 RAMD32 r u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/tfifo/ram_reg_0_15_0_5/RAMC_D1/CLK
|
|
clock pessimism -0.216 -0.526
|
|
SLICE_X6Y61 RAMD32 (Hold_ramd32_CLK_WADR0)
|
|
0.310 -0.216 u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/tfifo/ram_reg_0_15_0_5/RAMC_D1
|
|
-------------------------------------------------------------------
|
|
required time 0.216
|
|
arrival time -0.099
|
|
-------------------------------------------------------------------
|
|
slack 0.117
|
|
|
|
Slack (MET) : 0.117ns (arrival time - required time)
|
|
Source: u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/top_reg[0]/C
|
|
(rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Destination: u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/tfifo/ram_reg_0_15_0_5/RAMD/ADR0
|
|
(rising edge-triggered cell RAMS32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Path Group: sys_clk
|
|
Path Type: Hold (Min at Fast Process Corner)
|
|
Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns)
|
|
Data Path Delay: 0.444ns (logic 0.164ns (36.916%) route 0.280ns (63.084%))
|
|
Logic Levels: 0
|
|
Clock Path Skew: 0.017ns (DCD - SCD - CPR)
|
|
Destination Clock Delay (DCD): -0.310ns
|
|
Source Clock Delay (SCD): -0.543ns
|
|
Clock Pessimism Removal (CPR): 0.216ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock sys_clk rise edge) 0.000 0.000 r
|
|
K21 0.000 0.000 r clk (IN)
|
|
net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1
|
|
K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O
|
|
net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll
|
|
PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1)
|
|
-2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1
|
|
net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll
|
|
BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O
|
|
net (fo=10004, routed) 0.719 -0.543 u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/sys_clk
|
|
SLICE_X6Y62 FDRE r u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/top_reg[0]/C
|
|
------------------------------------------------------------------- -------------------
|
|
SLICE_X6Y62 FDRE (Prop_fdre_C_Q) 0.164 -0.379 r u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/top_reg[0]/Q
|
|
net (fo=20, routed) 0.280 -0.099 u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/tfifo/ram_reg_0_15_0_5/ADDRD0
|
|
SLICE_X6Y61 RAMS32 r u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/tfifo/ram_reg_0_15_0_5/RAMD/ADR0
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock sys_clk rise edge) 0.000 0.000 r
|
|
K21 0.000 0.000 r clk (IN)
|
|
net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1
|
|
K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O
|
|
net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll
|
|
PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1)
|
|
-2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1
|
|
net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll
|
|
BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O
|
|
net (fo=10004, routed) 0.998 -0.310 u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/tfifo/ram_reg_0_15_0_5/WCLK
|
|
SLICE_X6Y61 RAMS32 r u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/tfifo/ram_reg_0_15_0_5/RAMD/CLK
|
|
clock pessimism -0.216 -0.526
|
|
SLICE_X6Y61 RAMS32 (Hold_rams32_CLK_ADR0)
|
|
0.310 -0.216 u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/tfifo/ram_reg_0_15_0_5/RAMD
|
|
-------------------------------------------------------------------
|
|
required time 0.216
|
|
arrival time -0.099
|
|
-------------------------------------------------------------------
|
|
slack 0.117
|
|
|
|
Slack (MET) : 0.117ns (arrival time - required time)
|
|
Source: u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/top_reg[0]/C
|
|
(rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Destination: u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/tfifo/ram_reg_0_15_0_5/RAMD_D1/ADR0
|
|
(rising edge-triggered cell RAMS32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Path Group: sys_clk
|
|
Path Type: Hold (Min at Fast Process Corner)
|
|
Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns)
|
|
Data Path Delay: 0.444ns (logic 0.164ns (36.916%) route 0.280ns (63.084%))
|
|
Logic Levels: 0
|
|
Clock Path Skew: 0.017ns (DCD - SCD - CPR)
|
|
Destination Clock Delay (DCD): -0.310ns
|
|
Source Clock Delay (SCD): -0.543ns
|
|
Clock Pessimism Removal (CPR): 0.216ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock sys_clk rise edge) 0.000 0.000 r
|
|
K21 0.000 0.000 r clk (IN)
|
|
net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1
|
|
K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O
|
|
net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll
|
|
PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1)
|
|
-2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1
|
|
net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll
|
|
BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O
|
|
net (fo=10004, routed) 0.719 -0.543 u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/sys_clk
|
|
SLICE_X6Y62 FDRE r u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/top_reg[0]/C
|
|
------------------------------------------------------------------- -------------------
|
|
SLICE_X6Y62 FDRE (Prop_fdre_C_Q) 0.164 -0.379 r u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/top_reg[0]/Q
|
|
net (fo=20, routed) 0.280 -0.099 u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/tfifo/ram_reg_0_15_0_5/ADDRD0
|
|
SLICE_X6Y61 RAMS32 r u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/tfifo/ram_reg_0_15_0_5/RAMD_D1/ADR0
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock sys_clk rise edge) 0.000 0.000 r
|
|
K21 0.000 0.000 r clk (IN)
|
|
net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1
|
|
K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O
|
|
net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll
|
|
PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1)
|
|
-2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1
|
|
net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll
|
|
BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O
|
|
net (fo=10004, routed) 0.998 -0.310 u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/tfifo/ram_reg_0_15_0_5/WCLK
|
|
SLICE_X6Y61 RAMS32 r u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/tfifo/ram_reg_0_15_0_5/RAMD_D1/CLK
|
|
clock pessimism -0.216 -0.526
|
|
SLICE_X6Y61 RAMS32 (Hold_rams32_CLK_ADR0)
|
|
0.310 -0.216 u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/tfifo/ram_reg_0_15_0_5/RAMD_D1
|
|
-------------------------------------------------------------------
|
|
required time 0.216
|
|
arrival time -0.099
|
|
-------------------------------------------------------------------
|
|
slack 0.117
|
|
|
|
Slack (MET) : 0.121ns (arrival time - required time)
|
|
Source: u_Axi_CDC/arFifo/pushToPopGray_buffercc/buffers_0_reg[2]/C
|
|
(rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Destination: u_Axi_CDC/arFifo/pushToPopGray_buffercc/buffers_1_reg[2]/D
|
|
(rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Path Group: sys_clk
|
|
Path Type: Hold (Min at Fast Process Corner)
|
|
Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns)
|
|
Data Path Delay: 0.197ns (logic 0.141ns (71.611%) route 0.056ns (28.389%))
|
|
Logic Levels: 0
|
|
Clock Path Skew: 0.000ns (DCD - SCD - CPR)
|
|
Destination Clock Delay (DCD): -0.344ns
|
|
Source Clock Delay (SCD): -0.572ns
|
|
Clock Pessimism Removal (CPR): 0.228ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock sys_clk rise edge) 0.000 0.000 r
|
|
K21 0.000 0.000 r clk (IN)
|
|
net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1
|
|
K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O
|
|
net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll
|
|
PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1)
|
|
-2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1
|
|
net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll
|
|
BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O
|
|
net (fo=10004, routed) 0.690 -0.572 u_Axi_CDC/arFifo/pushToPopGray_buffercc/sys_clk
|
|
SLICE_X15Y66 FDCE r u_Axi_CDC/arFifo/pushToPopGray_buffercc/buffers_0_reg[2]/C
|
|
------------------------------------------------------------------- -------------------
|
|
SLICE_X15Y66 FDCE (Prop_fdce_C_Q) 0.141 -0.431 r u_Axi_CDC/arFifo/pushToPopGray_buffercc/buffers_0_reg[2]/Q
|
|
net (fo=1, routed) 0.056 -0.375 u_Axi_CDC/arFifo/pushToPopGray_buffercc/buffers_0[2]
|
|
SLICE_X15Y66 FDCE r u_Axi_CDC/arFifo/pushToPopGray_buffercc/buffers_1_reg[2]/D
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock sys_clk rise edge) 0.000 0.000 r
|
|
K21 0.000 0.000 r clk (IN)
|
|
net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1
|
|
K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O
|
|
net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll
|
|
PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1)
|
|
-2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1
|
|
net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll
|
|
BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O
|
|
net (fo=10004, routed) 0.964 -0.344 u_Axi_CDC/arFifo/pushToPopGray_buffercc/sys_clk
|
|
SLICE_X15Y66 FDCE r u_Axi_CDC/arFifo/pushToPopGray_buffercc/buffers_1_reg[2]/C
|
|
clock pessimism -0.228 -0.572
|
|
SLICE_X15Y66 FDCE (Hold_fdce_C_D) 0.076 -0.496 u_Axi_CDC/arFifo/pushToPopGray_buffercc/buffers_1_reg[2]
|
|
-------------------------------------------------------------------
|
|
required time 0.496
|
|
arrival time -0.375
|
|
-------------------------------------------------------------------
|
|
slack 0.121
|
|
|
|
Slack (MET) : 0.121ns (arrival time - required time)
|
|
Source: u_Axi_CDC/awFifo/pushToPopGray_buffercc/buffers_0_reg[2]/C
|
|
(rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Destination: u_Axi_CDC/awFifo/pushToPopGray_buffercc/buffers_1_reg[2]/D
|
|
(rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Path Group: sys_clk
|
|
Path Type: Hold (Min at Fast Process Corner)
|
|
Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns)
|
|
Data Path Delay: 0.197ns (logic 0.141ns (71.611%) route 0.056ns (28.389%))
|
|
Logic Levels: 0
|
|
Clock Path Skew: 0.000ns (DCD - SCD - CPR)
|
|
Destination Clock Delay (DCD): -0.348ns
|
|
Source Clock Delay (SCD): -0.576ns
|
|
Clock Pessimism Removal (CPR): 0.228ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock sys_clk rise edge) 0.000 0.000 r
|
|
K21 0.000 0.000 r clk (IN)
|
|
net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1
|
|
K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O
|
|
net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll
|
|
PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1)
|
|
-2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1
|
|
net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll
|
|
BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O
|
|
net (fo=10004, routed) 0.686 -0.576 u_Axi_CDC/awFifo/pushToPopGray_buffercc/sys_clk
|
|
SLICE_X15Y70 FDCE r u_Axi_CDC/awFifo/pushToPopGray_buffercc/buffers_0_reg[2]/C
|
|
------------------------------------------------------------------- -------------------
|
|
SLICE_X15Y70 FDCE (Prop_fdce_C_Q) 0.141 -0.435 r u_Axi_CDC/awFifo/pushToPopGray_buffercc/buffers_0_reg[2]/Q
|
|
net (fo=1, routed) 0.056 -0.379 u_Axi_CDC/awFifo/pushToPopGray_buffercc/buffers_0[2]
|
|
SLICE_X15Y70 FDCE r u_Axi_CDC/awFifo/pushToPopGray_buffercc/buffers_1_reg[2]/D
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock sys_clk rise edge) 0.000 0.000 r
|
|
K21 0.000 0.000 r clk (IN)
|
|
net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1
|
|
K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O
|
|
net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll
|
|
PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1)
|
|
-2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1
|
|
net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll
|
|
BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O
|
|
net (fo=10004, routed) 0.960 -0.348 u_Axi_CDC/awFifo/pushToPopGray_buffercc/sys_clk
|
|
SLICE_X15Y70 FDCE r u_Axi_CDC/awFifo/pushToPopGray_buffercc/buffers_1_reg[2]/C
|
|
clock pessimism -0.228 -0.576
|
|
SLICE_X15Y70 FDCE (Hold_fdce_C_D) 0.076 -0.500 u_Axi_CDC/awFifo/pushToPopGray_buffercc/buffers_1_reg[2]
|
|
-------------------------------------------------------------------
|
|
required time 0.500
|
|
arrival time -0.379
|
|
-------------------------------------------------------------------
|
|
slack 0.121
|
|
|
|
Slack (MET) : 0.121ns (arrival time - required time)
|
|
Source: u_Axi_CDC/bFifo/popToPushGray_buffercc/buffers_0_reg[2]/C
|
|
(rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Destination: u_Axi_CDC/bFifo/popToPushGray_buffercc/buffers_1_reg[2]/D
|
|
(rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Path Group: sys_clk
|
|
Path Type: Hold (Min at Fast Process Corner)
|
|
Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns)
|
|
Data Path Delay: 0.197ns (logic 0.141ns (71.611%) route 0.056ns (28.389%))
|
|
Logic Levels: 0
|
|
Clock Path Skew: 0.000ns (DCD - SCD - CPR)
|
|
Destination Clock Delay (DCD): -0.338ns
|
|
Source Clock Delay (SCD): -0.568ns
|
|
Clock Pessimism Removal (CPR): 0.230ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock sys_clk rise edge) 0.000 0.000 r
|
|
K21 0.000 0.000 r clk (IN)
|
|
net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1
|
|
K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O
|
|
net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll
|
|
PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1)
|
|
-2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1
|
|
net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll
|
|
BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O
|
|
net (fo=10004, routed) 0.694 -0.568 u_Axi_CDC/bFifo/popToPushGray_buffercc/sys_clk
|
|
SLICE_X17Y59 FDCE r u_Axi_CDC/bFifo/popToPushGray_buffercc/buffers_0_reg[2]/C
|
|
------------------------------------------------------------------- -------------------
|
|
SLICE_X17Y59 FDCE (Prop_fdce_C_Q) 0.141 -0.427 r u_Axi_CDC/bFifo/popToPushGray_buffercc/buffers_0_reg[2]/Q
|
|
net (fo=1, routed) 0.056 -0.371 u_Axi_CDC/bFifo/popToPushGray_buffercc/buffers_0[2]
|
|
SLICE_X17Y59 FDCE r u_Axi_CDC/bFifo/popToPushGray_buffercc/buffers_1_reg[2]/D
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock sys_clk rise edge) 0.000 0.000 r
|
|
K21 0.000 0.000 r clk (IN)
|
|
net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1
|
|
K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O
|
|
net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll
|
|
PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1)
|
|
-2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1
|
|
net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll
|
|
BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O
|
|
net (fo=10004, routed) 0.970 -0.338 u_Axi_CDC/bFifo/popToPushGray_buffercc/sys_clk
|
|
SLICE_X17Y59 FDCE r u_Axi_CDC/bFifo/popToPushGray_buffercc/buffers_1_reg[2]/C
|
|
clock pessimism -0.230 -0.568
|
|
SLICE_X17Y59 FDCE (Hold_fdce_C_D) 0.076 -0.492 u_Axi_CDC/bFifo/popToPushGray_buffercc/buffers_1_reg[2]
|
|
-------------------------------------------------------------------
|
|
required time 0.492
|
|
arrival time -0.371
|
|
-------------------------------------------------------------------
|
|
slack 0.121
|
|
|
|
Slack (MET) : 0.121ns (arrival time - required time)
|
|
Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/popToPushGray_buffercc/buffers_0_reg[2]/C
|
|
(rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/popToPushGray_buffercc/buffers_1_reg[2]/D
|
|
(rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Path Group: sys_clk
|
|
Path Type: Hold (Min at Fast Process Corner)
|
|
Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns)
|
|
Data Path Delay: 0.197ns (logic 0.141ns (71.611%) route 0.056ns (28.389%))
|
|
Logic Levels: 0
|
|
Clock Path Skew: 0.000ns (DCD - SCD - CPR)
|
|
Destination Clock Delay (DCD): -0.354ns
|
|
Source Clock Delay (SCD): -0.582ns
|
|
Clock Pessimism Removal (CPR): 0.228ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock sys_clk rise edge) 0.000 0.000 r
|
|
K21 0.000 0.000 r clk (IN)
|
|
net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1
|
|
K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O
|
|
net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll
|
|
PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1)
|
|
-2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1
|
|
net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll
|
|
BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O
|
|
net (fo=10004, routed) 0.680 -0.582 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/popToPushGray_buffercc/sys_clk
|
|
SLICE_X27Y78 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/popToPushGray_buffercc/buffers_0_reg[2]/C
|
|
------------------------------------------------------------------- -------------------
|
|
SLICE_X27Y78 FDCE (Prop_fdce_C_Q) 0.141 -0.441 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/popToPushGray_buffercc/buffers_0_reg[2]/Q
|
|
net (fo=1, routed) 0.056 -0.385 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/popToPushGray_buffercc/buffers_0[2]
|
|
SLICE_X27Y78 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/popToPushGray_buffercc/buffers_1_reg[2]/D
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock sys_clk rise edge) 0.000 0.000 r
|
|
K21 0.000 0.000 r clk (IN)
|
|
net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1
|
|
K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O
|
|
net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll
|
|
PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1)
|
|
-2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1
|
|
net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll
|
|
BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O
|
|
net (fo=10004, routed) 0.954 -0.354 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/popToPushGray_buffercc/sys_clk
|
|
SLICE_X27Y78 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/popToPushGray_buffercc/buffers_1_reg[2]/C
|
|
clock pessimism -0.228 -0.582
|
|
SLICE_X27Y78 FDCE (Hold_fdce_C_D) 0.076 -0.506 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/popToPushGray_buffercc/buffers_1_reg[2]
|
|
-------------------------------------------------------------------
|
|
required time 0.506
|
|
arrival time -0.385
|
|
-------------------------------------------------------------------
|
|
slack 0.121
|
|
|
|
Slack (MET) : 0.122ns (arrival time - required time)
|
|
Source: u_Axi_CDC/arFifo/pushToPopGray_buffercc/buffers_0_reg[0]/C
|
|
(rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Destination: u_Axi_CDC/arFifo/pushToPopGray_buffercc/buffers_1_reg[0]/D
|
|
(rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Path Group: sys_clk
|
|
Path Type: Hold (Min at Fast Process Corner)
|
|
Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns)
|
|
Data Path Delay: 0.197ns (logic 0.141ns (71.611%) route 0.056ns (28.389%))
|
|
Logic Levels: 0
|
|
Clock Path Skew: 0.000ns (DCD - SCD - CPR)
|
|
Destination Clock Delay (DCD): -0.344ns
|
|
Source Clock Delay (SCD): -0.572ns
|
|
Clock Pessimism Removal (CPR): 0.228ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock sys_clk rise edge) 0.000 0.000 r
|
|
K21 0.000 0.000 r clk (IN)
|
|
net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1
|
|
K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O
|
|
net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll
|
|
PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1)
|
|
-2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1
|
|
net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll
|
|
BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O
|
|
net (fo=10004, routed) 0.690 -0.572 u_Axi_CDC/arFifo/pushToPopGray_buffercc/sys_clk
|
|
SLICE_X15Y66 FDCE r u_Axi_CDC/arFifo/pushToPopGray_buffercc/buffers_0_reg[0]/C
|
|
------------------------------------------------------------------- -------------------
|
|
SLICE_X15Y66 FDCE (Prop_fdce_C_Q) 0.141 -0.431 r u_Axi_CDC/arFifo/pushToPopGray_buffercc/buffers_0_reg[0]/Q
|
|
net (fo=1, routed) 0.056 -0.375 u_Axi_CDC/arFifo/pushToPopGray_buffercc/buffers_0[0]
|
|
SLICE_X15Y66 FDCE r u_Axi_CDC/arFifo/pushToPopGray_buffercc/buffers_1_reg[0]/D
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock sys_clk rise edge) 0.000 0.000 r
|
|
K21 0.000 0.000 r clk (IN)
|
|
net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1
|
|
K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O
|
|
net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll
|
|
PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1)
|
|
-2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1
|
|
net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll
|
|
BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O
|
|
net (fo=10004, routed) 0.964 -0.344 u_Axi_CDC/arFifo/pushToPopGray_buffercc/sys_clk
|
|
SLICE_X15Y66 FDCE r u_Axi_CDC/arFifo/pushToPopGray_buffercc/buffers_1_reg[0]/C
|
|
clock pessimism -0.228 -0.572
|
|
SLICE_X15Y66 FDCE (Hold_fdce_C_D) 0.075 -0.497 u_Axi_CDC/arFifo/pushToPopGray_buffercc/buffers_1_reg[0]
|
|
-------------------------------------------------------------------
|
|
required time 0.497
|
|
arrival time -0.375
|
|
-------------------------------------------------------------------
|
|
slack 0.122
|
|
|
|
Slack (MET) : 0.122ns (arrival time - required time)
|
|
Source: u_Axi_CDC/awFifo/bufferCC_12/buffers_0_reg/C
|
|
(rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Destination: u_Axi_CDC/awFifo/bufferCC_12/buffers_1_reg/D
|
|
(rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Path Group: sys_clk
|
|
Path Type: Hold (Min at Fast Process Corner)
|
|
Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns)
|
|
Data Path Delay: 0.197ns (logic 0.141ns (71.611%) route 0.056ns (28.389%))
|
|
Logic Levels: 0
|
|
Clock Path Skew: 0.000ns (DCD - SCD - CPR)
|
|
Destination Clock Delay (DCD): -0.309ns
|
|
Source Clock Delay (SCD): -0.541ns
|
|
Clock Pessimism Removal (CPR): 0.232ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock sys_clk rise edge) 0.000 0.000 r
|
|
K21 0.000 0.000 r clk (IN)
|
|
net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1
|
|
K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O
|
|
net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll
|
|
PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1)
|
|
-2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1
|
|
net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll
|
|
BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O
|
|
net (fo=10004, routed) 0.721 -0.541 u_Axi_CDC/awFifo/bufferCC_12/sys_clk
|
|
SLICE_X7Y59 FDCE r u_Axi_CDC/awFifo/bufferCC_12/buffers_0_reg/C
|
|
------------------------------------------------------------------- -------------------
|
|
SLICE_X7Y59 FDCE (Prop_fdce_C_Q) 0.141 -0.400 r u_Axi_CDC/awFifo/bufferCC_12/buffers_0_reg/Q
|
|
net (fo=1, routed) 0.056 -0.344 u_Axi_CDC/awFifo/bufferCC_12/buffers_0
|
|
SLICE_X7Y59 FDCE r u_Axi_CDC/awFifo/bufferCC_12/buffers_1_reg/D
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock sys_clk rise edge) 0.000 0.000 r
|
|
K21 0.000 0.000 r clk (IN)
|
|
net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1
|
|
K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O
|
|
net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll
|
|
PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1)
|
|
-2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1
|
|
net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll
|
|
BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O
|
|
net (fo=10004, routed) 0.999 -0.309 u_Axi_CDC/awFifo/bufferCC_12/sys_clk
|
|
SLICE_X7Y59 FDCE r u_Axi_CDC/awFifo/bufferCC_12/buffers_1_reg/C
|
|
clock pessimism -0.232 -0.541
|
|
SLICE_X7Y59 FDCE (Hold_fdce_C_D) 0.075 -0.466 u_Axi_CDC/awFifo/bufferCC_12/buffers_1_reg
|
|
-------------------------------------------------------------------
|
|
required time 0.466
|
|
arrival time -0.344
|
|
-------------------------------------------------------------------
|
|
slack 0.122
|
|
|
|
Slack (MET) : 0.122ns (arrival time - required time)
|
|
Source: u_Axi_CDC/bFifo/popToPushGray_buffercc/buffers_0_reg[0]/C
|
|
(rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Destination: u_Axi_CDC/bFifo/popToPushGray_buffercc/buffers_1_reg[0]/D
|
|
(rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Path Group: sys_clk
|
|
Path Type: Hold (Min at Fast Process Corner)
|
|
Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns)
|
|
Data Path Delay: 0.197ns (logic 0.141ns (71.611%) route 0.056ns (28.389%))
|
|
Logic Levels: 0
|
|
Clock Path Skew: 0.000ns (DCD - SCD - CPR)
|
|
Destination Clock Delay (DCD): -0.338ns
|
|
Source Clock Delay (SCD): -0.568ns
|
|
Clock Pessimism Removal (CPR): 0.230ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock sys_clk rise edge) 0.000 0.000 r
|
|
K21 0.000 0.000 r clk (IN)
|
|
net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1
|
|
K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O
|
|
net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll
|
|
PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1)
|
|
-2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1
|
|
net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll
|
|
BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O
|
|
net (fo=10004, routed) 0.694 -0.568 u_Axi_CDC/bFifo/popToPushGray_buffercc/sys_clk
|
|
SLICE_X17Y59 FDCE r u_Axi_CDC/bFifo/popToPushGray_buffercc/buffers_0_reg[0]/C
|
|
------------------------------------------------------------------- -------------------
|
|
SLICE_X17Y59 FDCE (Prop_fdce_C_Q) 0.141 -0.427 r u_Axi_CDC/bFifo/popToPushGray_buffercc/buffers_0_reg[0]/Q
|
|
net (fo=1, routed) 0.056 -0.371 u_Axi_CDC/bFifo/popToPushGray_buffercc/buffers_0[0]
|
|
SLICE_X17Y59 FDCE r u_Axi_CDC/bFifo/popToPushGray_buffercc/buffers_1_reg[0]/D
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock sys_clk rise edge) 0.000 0.000 r
|
|
K21 0.000 0.000 r clk (IN)
|
|
net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1
|
|
K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O
|
|
net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll
|
|
PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1)
|
|
-2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1
|
|
net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll
|
|
BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O
|
|
net (fo=10004, routed) 0.970 -0.338 u_Axi_CDC/bFifo/popToPushGray_buffercc/sys_clk
|
|
SLICE_X17Y59 FDCE r u_Axi_CDC/bFifo/popToPushGray_buffercc/buffers_1_reg[0]/C
|
|
clock pessimism -0.230 -0.568
|
|
SLICE_X17Y59 FDCE (Hold_fdce_C_D) 0.075 -0.493 u_Axi_CDC/bFifo/popToPushGray_buffercc/buffers_1_reg[0]
|
|
-------------------------------------------------------------------
|
|
required time 0.493
|
|
arrival time -0.371
|
|
-------------------------------------------------------------------
|
|
slack 0.122
|
|
|
|
Slack (MET) : 0.122ns (arrival time - required time)
|
|
Source: u_axi_uart_controller/uart0/regs/i_uart_sync_flops/flop_0_reg[0]/C
|
|
(rising edge-triggered cell FDSE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Destination: u_axi_uart_controller/uart0/regs/i_uart_sync_flops/sync_dat_o_reg[0]/D
|
|
(rising edge-triggered cell FDSE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Path Group: sys_clk
|
|
Path Type: Hold (Min at Fast Process Corner)
|
|
Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns)
|
|
Data Path Delay: 0.197ns (logic 0.141ns (71.611%) route 0.056ns (28.389%))
|
|
Logic Levels: 0
|
|
Clock Path Skew: 0.000ns (DCD - SCD - CPR)
|
|
Destination Clock Delay (DCD): -0.308ns
|
|
Source Clock Delay (SCD): -0.539ns
|
|
Clock Pessimism Removal (CPR): 0.231ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock sys_clk rise edge) 0.000 0.000 r
|
|
K21 0.000 0.000 r clk (IN)
|
|
net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1
|
|
K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O
|
|
net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll
|
|
PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1)
|
|
-2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1
|
|
net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll
|
|
BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O
|
|
net (fo=10004, routed) 0.723 -0.539 u_axi_uart_controller/uart0/regs/i_uart_sync_flops/sys_clk
|
|
SLICE_X1Y61 FDSE r u_axi_uart_controller/uart0/regs/i_uart_sync_flops/flop_0_reg[0]/C
|
|
------------------------------------------------------------------- -------------------
|
|
SLICE_X1Y61 FDSE (Prop_fdse_C_Q) 0.141 -0.398 r u_axi_uart_controller/uart0/regs/i_uart_sync_flops/flop_0_reg[0]/Q
|
|
net (fo=1, routed) 0.056 -0.342 u_axi_uart_controller/uart0/regs/i_uart_sync_flops/flop_0
|
|
SLICE_X1Y61 FDSE r u_axi_uart_controller/uart0/regs/i_uart_sync_flops/sync_dat_o_reg[0]/D
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock sys_clk rise edge) 0.000 0.000 r
|
|
K21 0.000 0.000 r clk (IN)
|
|
net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1
|
|
K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O
|
|
net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll
|
|
PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1)
|
|
-2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1
|
|
net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll
|
|
BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O
|
|
net (fo=10004, routed) 1.000 -0.308 u_axi_uart_controller/uart0/regs/i_uart_sync_flops/sys_clk
|
|
SLICE_X1Y61 FDSE r u_axi_uart_controller/uart0/regs/i_uart_sync_flops/sync_dat_o_reg[0]/C
|
|
clock pessimism -0.231 -0.539
|
|
SLICE_X1Y61 FDSE (Hold_fdse_C_D) 0.075 -0.464 u_axi_uart_controller/uart0/regs/i_uart_sync_flops/sync_dat_o_reg[0]
|
|
-------------------------------------------------------------------
|
|
required time 0.464
|
|
arrival time -0.342
|
|
-------------------------------------------------------------------
|
|
slack 0.122
|
|
|
|
Slack (MET) : 0.122ns (arrival time - required time)
|
|
Source: u_fft_mlkem_axi_slave/mlkem_intr_sync_reg[0]/C
|
|
(rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Destination: u_fft_mlkem_axi_slave/mlkem_intr_sync_reg[1]/D
|
|
(rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Path Group: sys_clk
|
|
Path Type: Hold (Min at Fast Process Corner)
|
|
Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns)
|
|
Data Path Delay: 0.197ns (logic 0.141ns (71.611%) route 0.056ns (28.389%))
|
|
Logic Levels: 0
|
|
Clock Path Skew: 0.000ns (DCD - SCD - CPR)
|
|
Destination Clock Delay (DCD): -0.374ns
|
|
Source Clock Delay (SCD): -0.603ns
|
|
Clock Pessimism Removal (CPR): 0.229ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock sys_clk rise edge) 0.000 0.000 r
|
|
K21 0.000 0.000 r clk (IN)
|
|
net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1
|
|
K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O
|
|
net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll
|
|
PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1)
|
|
-2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1
|
|
net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll
|
|
BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O
|
|
net (fo=10004, routed) 0.659 -0.603 u_fft_mlkem_axi_slave/sys_clk
|
|
SLICE_X117Y61 FDCE r u_fft_mlkem_axi_slave/mlkem_intr_sync_reg[0]/C
|
|
------------------------------------------------------------------- -------------------
|
|
SLICE_X117Y61 FDCE (Prop_fdce_C_Q) 0.141 -0.462 r u_fft_mlkem_axi_slave/mlkem_intr_sync_reg[0]/Q
|
|
net (fo=1, routed) 0.056 -0.406 u_fft_mlkem_axi_slave/mlkem_intr_sync[0]
|
|
SLICE_X117Y61 FDCE r u_fft_mlkem_axi_slave/mlkem_intr_sync_reg[1]/D
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock sys_clk rise edge) 0.000 0.000 r
|
|
K21 0.000 0.000 r clk (IN)
|
|
net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1
|
|
K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O
|
|
net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll
|
|
PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1)
|
|
-2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1
|
|
net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll
|
|
BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O
|
|
net (fo=10004, routed) 0.934 -0.374 u_fft_mlkem_axi_slave/sys_clk
|
|
SLICE_X117Y61 FDCE r u_fft_mlkem_axi_slave/mlkem_intr_sync_reg[1]/C
|
|
clock pessimism -0.229 -0.603
|
|
SLICE_X117Y61 FDCE (Hold_fdce_C_D) 0.075 -0.528 u_fft_mlkem_axi_slave/mlkem_intr_sync_reg[1]
|
|
-------------------------------------------------------------------
|
|
required time 0.528
|
|
arrival time -0.406
|
|
-------------------------------------------------------------------
|
|
slack 0.122
|
|
|
|
Slack (MET) : 0.122ns (arrival time - required time)
|
|
Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/popToPushGray_buffercc/buffers_0_reg[0]/C
|
|
(rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/popToPushGray_buffercc/buffers_1_reg[0]/D
|
|
(rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Path Group: sys_clk
|
|
Path Type: Hold (Min at Fast Process Corner)
|
|
Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns)
|
|
Data Path Delay: 0.197ns (logic 0.141ns (71.611%) route 0.056ns (28.389%))
|
|
Logic Levels: 0
|
|
Clock Path Skew: 0.000ns (DCD - SCD - CPR)
|
|
Destination Clock Delay (DCD): -0.354ns
|
|
Source Clock Delay (SCD): -0.582ns
|
|
Clock Pessimism Removal (CPR): 0.228ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock sys_clk rise edge) 0.000 0.000 r
|
|
K21 0.000 0.000 r clk (IN)
|
|
net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1
|
|
K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O
|
|
net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll
|
|
PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1)
|
|
-2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1
|
|
net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll
|
|
BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O
|
|
net (fo=10004, routed) 0.680 -0.582 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/popToPushGray_buffercc/sys_clk
|
|
SLICE_X27Y78 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/popToPushGray_buffercc/buffers_0_reg[0]/C
|
|
------------------------------------------------------------------- -------------------
|
|
SLICE_X27Y78 FDCE (Prop_fdce_C_Q) 0.141 -0.441 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/popToPushGray_buffercc/buffers_0_reg[0]/Q
|
|
net (fo=1, routed) 0.056 -0.385 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/popToPushGray_buffercc/buffers_0[0]
|
|
SLICE_X27Y78 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/popToPushGray_buffercc/buffers_1_reg[0]/D
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock sys_clk rise edge) 0.000 0.000 r
|
|
K21 0.000 0.000 r clk (IN)
|
|
net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1
|
|
K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O
|
|
net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll
|
|
PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1)
|
|
-2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1
|
|
net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll
|
|
BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O
|
|
net (fo=10004, routed) 0.954 -0.354 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/popToPushGray_buffercc/sys_clk
|
|
SLICE_X27Y78 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/popToPushGray_buffercc/buffers_1_reg[0]/C
|
|
clock pessimism -0.228 -0.582
|
|
SLICE_X27Y78 FDCE (Hold_fdce_C_D) 0.075 -0.507 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/popToPushGray_buffercc/buffers_1_reg[0]
|
|
-------------------------------------------------------------------
|
|
required time 0.507
|
|
arrival time -0.385
|
|
-------------------------------------------------------------------
|
|
slack 0.122
|
|
|
|
Slack (MET) : 0.122ns (arrival time - required time)
|
|
Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/popToPushGray_buffercc/buffers_0_reg[1]/C
|
|
(rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/popToPushGray_buffercc/buffers_1_reg[1]/D
|
|
(rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Path Group: sys_clk
|
|
Path Type: Hold (Min at Fast Process Corner)
|
|
Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns)
|
|
Data Path Delay: 0.197ns (logic 0.141ns (71.611%) route 0.056ns (28.389%))
|
|
Logic Levels: 0
|
|
Clock Path Skew: 0.000ns (DCD - SCD - CPR)
|
|
Destination Clock Delay (DCD): -0.360ns
|
|
Source Clock Delay (SCD): -0.587ns
|
|
Clock Pessimism Removal (CPR): 0.227ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock sys_clk rise edge) 0.000 0.000 r
|
|
K21 0.000 0.000 r clk (IN)
|
|
net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1
|
|
K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O
|
|
net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll
|
|
PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1)
|
|
-2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1
|
|
net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll
|
|
BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O
|
|
net (fo=10004, routed) 0.675 -0.587 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/popToPushGray_buffercc/sys_clk
|
|
SLICE_X29Y74 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/popToPushGray_buffercc/buffers_0_reg[1]/C
|
|
------------------------------------------------------------------- -------------------
|
|
SLICE_X29Y74 FDCE (Prop_fdce_C_Q) 0.141 -0.446 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/popToPushGray_buffercc/buffers_0_reg[1]/Q
|
|
net (fo=1, routed) 0.056 -0.390 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/popToPushGray_buffercc/buffers_0[1]
|
|
SLICE_X29Y74 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/popToPushGray_buffercc/buffers_1_reg[1]/D
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock sys_clk rise edge) 0.000 0.000 r
|
|
K21 0.000 0.000 r clk (IN)
|
|
net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1
|
|
K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O
|
|
net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll
|
|
PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1)
|
|
-2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1
|
|
net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll
|
|
BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O
|
|
net (fo=10004, routed) 0.948 -0.360 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/popToPushGray_buffercc/sys_clk
|
|
SLICE_X29Y74 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/popToPushGray_buffercc/buffers_1_reg[1]/C
|
|
clock pessimism -0.227 -0.587
|
|
SLICE_X29Y74 FDCE (Hold_fdce_C_D) 0.075 -0.512 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/popToPushGray_buffercc/buffers_1_reg[1]
|
|
-------------------------------------------------------------------
|
|
required time 0.512
|
|
arrival time -0.390
|
|
-------------------------------------------------------------------
|
|
slack 0.122
|
|
|
|
Slack (MET) : 0.122ns (arrival time - required time)
|
|
Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/buffers_0_reg/C
|
|
(rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/buffers_1_reg/D
|
|
(rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Path Group: sys_clk
|
|
Path Type: Hold (Min at Fast Process Corner)
|
|
Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns)
|
|
Data Path Delay: 0.197ns (logic 0.141ns (71.611%) route 0.056ns (28.389%))
|
|
Logic Levels: 0
|
|
Clock Path Skew: 0.000ns (DCD - SCD - CPR)
|
|
Destination Clock Delay (DCD): -0.341ns
|
|
Source Clock Delay (SCD): -0.570ns
|
|
Clock Pessimism Removal (CPR): 0.229ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock sys_clk rise edge) 0.000 0.000 r
|
|
K21 0.000 0.000 r clk (IN)
|
|
net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1
|
|
K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O
|
|
net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll
|
|
PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1)
|
|
-2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1
|
|
net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll
|
|
BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O
|
|
net (fo=10004, routed) 0.692 -0.570 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/sys_clk
|
|
SLICE_X13Y87 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/buffers_0_reg/C
|
|
------------------------------------------------------------------- -------------------
|
|
SLICE_X13Y87 FDCE (Prop_fdce_C_Q) 0.141 -0.429 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/buffers_0_reg/Q
|
|
net (fo=1, routed) 0.056 -0.373 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/buffers_0
|
|
SLICE_X13Y87 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/buffers_1_reg/D
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock sys_clk rise edge) 0.000 0.000 r
|
|
K21 0.000 0.000 r clk (IN)
|
|
net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1
|
|
K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O
|
|
net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll
|
|
PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1)
|
|
-2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1
|
|
net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll
|
|
BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O
|
|
net (fo=10004, routed) 0.967 -0.341 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/sys_clk
|
|
SLICE_X13Y87 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/buffers_1_reg/C
|
|
clock pessimism -0.229 -0.570
|
|
SLICE_X13Y87 FDCE (Hold_fdce_C_D) 0.075 -0.495 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/buffers_1_reg
|
|
-------------------------------------------------------------------
|
|
required time 0.495
|
|
arrival time -0.373
|
|
-------------------------------------------------------------------
|
|
slack 0.122
|
|
|
|
Slack (MET) : 0.122ns (arrival time - required time)
|
|
Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/pushToPopGray_buffercc/buffers_0_reg[1]/C
|
|
(rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/pushToPopGray_buffercc/buffers_1_reg[1]/D
|
|
(rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Path Group: sys_clk
|
|
Path Type: Hold (Min at Fast Process Corner)
|
|
Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns)
|
|
Data Path Delay: 0.197ns (logic 0.141ns (71.611%) route 0.056ns (28.389%))
|
|
Logic Levels: 0
|
|
Clock Path Skew: 0.000ns (DCD - SCD - CPR)
|
|
Destination Clock Delay (DCD): -0.354ns
|
|
Source Clock Delay (SCD): -0.582ns
|
|
Clock Pessimism Removal (CPR): 0.228ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock sys_clk rise edge) 0.000 0.000 r
|
|
K21 0.000 0.000 r clk (IN)
|
|
net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1
|
|
K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O
|
|
net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll
|
|
PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1)
|
|
-2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1
|
|
net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll
|
|
BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O
|
|
net (fo=10004, routed) 0.680 -0.582 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/pushToPopGray_buffercc/sys_clk
|
|
SLICE_X27Y71 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/pushToPopGray_buffercc/buffers_0_reg[1]/C
|
|
------------------------------------------------------------------- -------------------
|
|
SLICE_X27Y71 FDCE (Prop_fdce_C_Q) 0.141 -0.441 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/pushToPopGray_buffercc/buffers_0_reg[1]/Q
|
|
net (fo=1, routed) 0.056 -0.385 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/pushToPopGray_buffercc/buffers_0[1]
|
|
SLICE_X27Y71 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/pushToPopGray_buffercc/buffers_1_reg[1]/D
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock sys_clk rise edge) 0.000 0.000 r
|
|
K21 0.000 0.000 r clk (IN)
|
|
net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1
|
|
K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O
|
|
net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll
|
|
PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1)
|
|
-2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1
|
|
net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll
|
|
BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O
|
|
net (fo=10004, routed) 0.954 -0.354 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/pushToPopGray_buffercc/sys_clk
|
|
SLICE_X27Y71 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/pushToPopGray_buffercc/buffers_1_reg[1]/C
|
|
clock pessimism -0.228 -0.582
|
|
SLICE_X27Y71 FDCE (Hold_fdce_C_D) 0.075 -0.507 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/pushToPopGray_buffercc/buffers_1_reg[1]
|
|
-------------------------------------------------------------------
|
|
required time 0.507
|
|
arrival time -0.385
|
|
-------------------------------------------------------------------
|
|
slack 0.122
|
|
|
|
Slack (MET) : 0.122ns (arrival time - required time)
|
|
Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/pushToPopGray_buffercc/buffers_0_reg[0]/C
|
|
(rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/pushToPopGray_buffercc/buffers_1_reg[0]/D
|
|
(rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Path Group: sys_clk
|
|
Path Type: Hold (Min at Fast Process Corner)
|
|
Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns)
|
|
Data Path Delay: 0.197ns (logic 0.141ns (71.611%) route 0.056ns (28.389%))
|
|
Logic Levels: 0
|
|
Clock Path Skew: 0.000ns (DCD - SCD - CPR)
|
|
Destination Clock Delay (DCD): -0.339ns
|
|
Source Clock Delay (SCD): -0.569ns
|
|
Clock Pessimism Removal (CPR): 0.230ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock sys_clk rise edge) 0.000 0.000 r
|
|
K21 0.000 0.000 r clk (IN)
|
|
net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1
|
|
K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O
|
|
net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll
|
|
PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1)
|
|
-2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1
|
|
net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll
|
|
BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O
|
|
net (fo=10004, routed) 0.693 -0.569 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/pushToPopGray_buffercc/sys_clk
|
|
SLICE_X15Y88 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/pushToPopGray_buffercc/buffers_0_reg[0]/C
|
|
------------------------------------------------------------------- -------------------
|
|
SLICE_X15Y88 FDCE (Prop_fdce_C_Q) 0.141 -0.428 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/pushToPopGray_buffercc/buffers_0_reg[0]/Q
|
|
net (fo=1, routed) 0.056 -0.372 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/pushToPopGray_buffercc/buffers_0[0]
|
|
SLICE_X15Y88 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/pushToPopGray_buffercc/buffers_1_reg[0]/D
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock sys_clk rise edge) 0.000 0.000 r
|
|
K21 0.000 0.000 r clk (IN)
|
|
net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1
|
|
K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O
|
|
net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll
|
|
PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1)
|
|
-2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1
|
|
net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll
|
|
BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O
|
|
net (fo=10004, routed) 0.969 -0.339 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/pushToPopGray_buffercc/sys_clk
|
|
SLICE_X15Y88 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/pushToPopGray_buffercc/buffers_1_reg[0]/C
|
|
clock pessimism -0.230 -0.569
|
|
SLICE_X15Y88 FDCE (Hold_fdce_C_D) 0.075 -0.494 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/pushToPopGray_buffercc/buffers_1_reg[0]
|
|
-------------------------------------------------------------------
|
|
required time 0.494
|
|
arrival time -0.372
|
|
-------------------------------------------------------------------
|
|
slack 0.122
|
|
|
|
Slack (MET) : 0.122ns (arrival time - required time)
|
|
Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/pushToPopGray_buffercc/buffers_0_reg[2]/C
|
|
(rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/pushToPopGray_buffercc/buffers_1_reg[2]/D
|
|
(rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Path Group: sys_clk
|
|
Path Type: Hold (Min at Fast Process Corner)
|
|
Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns)
|
|
Data Path Delay: 0.197ns (logic 0.141ns (71.611%) route 0.056ns (28.389%))
|
|
Logic Levels: 0
|
|
Clock Path Skew: 0.000ns (DCD - SCD - CPR)
|
|
Destination Clock Delay (DCD): -0.341ns
|
|
Source Clock Delay (SCD): -0.570ns
|
|
Clock Pessimism Removal (CPR): 0.229ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock sys_clk rise edge) 0.000 0.000 r
|
|
K21 0.000 0.000 r clk (IN)
|
|
net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1
|
|
K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O
|
|
net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll
|
|
PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1)
|
|
-2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1
|
|
net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll
|
|
BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O
|
|
net (fo=10004, routed) 0.692 -0.570 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/pushToPopGray_buffercc/sys_clk
|
|
SLICE_X15Y87 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/pushToPopGray_buffercc/buffers_0_reg[2]/C
|
|
------------------------------------------------------------------- -------------------
|
|
SLICE_X15Y87 FDCE (Prop_fdce_C_Q) 0.141 -0.429 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/pushToPopGray_buffercc/buffers_0_reg[2]/Q
|
|
net (fo=1, routed) 0.056 -0.373 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/pushToPopGray_buffercc/buffers_0[2]
|
|
SLICE_X15Y87 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/pushToPopGray_buffercc/buffers_1_reg[2]/D
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock sys_clk rise edge) 0.000 0.000 r
|
|
K21 0.000 0.000 r clk (IN)
|
|
net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1
|
|
K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O
|
|
net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll
|
|
PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1)
|
|
-2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1
|
|
net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll
|
|
BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O
|
|
net (fo=10004, routed) 0.967 -0.341 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/pushToPopGray_buffercc/sys_clk
|
|
SLICE_X15Y87 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/pushToPopGray_buffercc/buffers_1_reg[2]/C
|
|
clock pessimism -0.229 -0.570
|
|
SLICE_X15Y87 FDCE (Hold_fdce_C_D) 0.075 -0.495 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/pushToPopGray_buffercc/buffers_1_reg[2]
|
|
-------------------------------------------------------------------
|
|
required time 0.495
|
|
arrival time -0.373
|
|
-------------------------------------------------------------------
|
|
slack 0.122
|
|
|
|
Slack (MET) : 0.122ns (arrival time - required time)
|
|
Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/popToPushGray_buffercc/buffers_0_reg[0]/C
|
|
(rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/popToPushGray_buffercc/buffers_1_reg[0]/D
|
|
(rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Path Group: sys_clk
|
|
Path Type: Hold (Min at Fast Process Corner)
|
|
Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns)
|
|
Data Path Delay: 0.197ns (logic 0.141ns (71.611%) route 0.056ns (28.389%))
|
|
Logic Levels: 0
|
|
Clock Path Skew: 0.000ns (DCD - SCD - CPR)
|
|
Destination Clock Delay (DCD): -0.389ns
|
|
Source Clock Delay (SCD): -0.615ns
|
|
Clock Pessimism Removal (CPR): 0.226ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock sys_clk rise edge) 0.000 0.000 r
|
|
K21 0.000 0.000 r clk (IN)
|
|
net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1
|
|
K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O
|
|
net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll
|
|
PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1)
|
|
-2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1
|
|
net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll
|
|
BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O
|
|
net (fo=10004, routed) 0.647 -0.615 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/popToPushGray_buffercc/sys_clk
|
|
SLICE_X113Y75 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/popToPushGray_buffercc/buffers_0_reg[0]/C
|
|
------------------------------------------------------------------- -------------------
|
|
SLICE_X113Y75 FDCE (Prop_fdce_C_Q) 0.141 -0.474 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/popToPushGray_buffercc/buffers_0_reg[0]/Q
|
|
net (fo=1, routed) 0.056 -0.418 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/popToPushGray_buffercc/buffers_0[0]
|
|
SLICE_X113Y75 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/popToPushGray_buffercc/buffers_1_reg[0]/D
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock sys_clk rise edge) 0.000 0.000 r
|
|
K21 0.000 0.000 r clk (IN)
|
|
net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1
|
|
K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O
|
|
net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll
|
|
PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1)
|
|
-2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1
|
|
net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll
|
|
BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O
|
|
net (fo=10004, routed) 0.919 -0.389 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/popToPushGray_buffercc/sys_clk
|
|
SLICE_X113Y75 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/popToPushGray_buffercc/buffers_1_reg[0]/C
|
|
clock pessimism -0.226 -0.615
|
|
SLICE_X113Y75 FDCE (Hold_fdce_C_D) 0.075 -0.540 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/popToPushGray_buffercc/buffers_1_reg[0]
|
|
-------------------------------------------------------------------
|
|
required time 0.540
|
|
arrival time -0.418
|
|
-------------------------------------------------------------------
|
|
slack 0.122
|
|
|
|
Slack (MET) : 0.124ns (arrival time - required time)
|
|
Source: u_Axi_CDC/wFifo/pushToPopGray_buffercc/buffers_0_reg[2]/C
|
|
(rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Destination: u_Axi_CDC/wFifo/pushToPopGray_buffercc/buffers_1_reg[2]/D
|
|
(rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Path Group: sys_clk
|
|
Path Type: Hold (Min at Fast Process Corner)
|
|
Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns)
|
|
Data Path Delay: 0.200ns (logic 0.141ns (70.589%) route 0.059ns (29.411%))
|
|
Logic Levels: 0
|
|
Clock Path Skew: 0.000ns (DCD - SCD - CPR)
|
|
Destination Clock Delay (DCD): -0.231ns
|
|
Source Clock Delay (SCD): -0.467ns
|
|
Clock Pessimism Removal (CPR): 0.236ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock sys_clk rise edge) 0.000 0.000 r
|
|
K21 0.000 0.000 r clk (IN)
|
|
net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1
|
|
K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O
|
|
net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll
|
|
PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1)
|
|
-2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1
|
|
net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll
|
|
BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O
|
|
net (fo=10004, routed) 0.796 -0.467 u_Axi_CDC/wFifo/pushToPopGray_buffercc/sys_clk
|
|
SLICE_X4Y49 FDCE r u_Axi_CDC/wFifo/pushToPopGray_buffercc/buffers_0_reg[2]/C
|
|
------------------------------------------------------------------- -------------------
|
|
SLICE_X4Y49 FDCE (Prop_fdce_C_Q) 0.141 -0.326 r u_Axi_CDC/wFifo/pushToPopGray_buffercc/buffers_0_reg[2]/Q
|
|
net (fo=1, routed) 0.059 -0.267 u_Axi_CDC/wFifo/pushToPopGray_buffercc/buffers_0[2]
|
|
SLICE_X4Y49 FDCE r u_Axi_CDC/wFifo/pushToPopGray_buffercc/buffers_1_reg[2]/D
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock sys_clk rise edge) 0.000 0.000 r
|
|
K21 0.000 0.000 r clk (IN)
|
|
net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1
|
|
K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O
|
|
net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll
|
|
PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1)
|
|
-2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1
|
|
net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll
|
|
BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O
|
|
net (fo=10004, routed) 1.077 -0.231 u_Axi_CDC/wFifo/pushToPopGray_buffercc/sys_clk
|
|
SLICE_X4Y49 FDCE r u_Axi_CDC/wFifo/pushToPopGray_buffercc/buffers_1_reg[2]/C
|
|
clock pessimism -0.236 -0.467
|
|
SLICE_X4Y49 FDCE (Hold_fdce_C_D) 0.076 -0.391 u_Axi_CDC/wFifo/pushToPopGray_buffercc/buffers_1_reg[2]
|
|
-------------------------------------------------------------------
|
|
required time 0.391
|
|
arrival time -0.267
|
|
-------------------------------------------------------------------
|
|
slack 0.124
|
|
|
|
Slack (MET) : 0.125ns (arrival time - required time)
|
|
Source: u_Axi_CDC/wFifo/pushToPopGray_buffercc/buffers_0_reg[3]/C
|
|
(rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Destination: u_Axi_CDC/wFifo/pushToPopGray_buffercc/buffers_1_reg[3]/D
|
|
(rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Path Group: sys_clk
|
|
Path Type: Hold (Min at Fast Process Corner)
|
|
Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns)
|
|
Data Path Delay: 0.203ns (logic 0.141ns (69.572%) route 0.062ns (30.428%))
|
|
Logic Levels: 0
|
|
Clock Path Skew: 0.000ns (DCD - SCD - CPR)
|
|
Destination Clock Delay (DCD): -0.231ns
|
|
Source Clock Delay (SCD): -0.467ns
|
|
Clock Pessimism Removal (CPR): 0.236ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock sys_clk rise edge) 0.000 0.000 r
|
|
K21 0.000 0.000 r clk (IN)
|
|
net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1
|
|
K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O
|
|
net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll
|
|
PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1)
|
|
-2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1
|
|
net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll
|
|
BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O
|
|
net (fo=10004, routed) 0.796 -0.467 u_Axi_CDC/wFifo/pushToPopGray_buffercc/sys_clk
|
|
SLICE_X4Y49 FDCE r u_Axi_CDC/wFifo/pushToPopGray_buffercc/buffers_0_reg[3]/C
|
|
------------------------------------------------------------------- -------------------
|
|
SLICE_X4Y49 FDCE (Prop_fdce_C_Q) 0.141 -0.326 r u_Axi_CDC/wFifo/pushToPopGray_buffercc/buffers_0_reg[3]/Q
|
|
net (fo=1, routed) 0.062 -0.264 u_Axi_CDC/wFifo/pushToPopGray_buffercc/buffers_0[3]
|
|
SLICE_X4Y49 FDCE r u_Axi_CDC/wFifo/pushToPopGray_buffercc/buffers_1_reg[3]/D
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock sys_clk rise edge) 0.000 0.000 r
|
|
K21 0.000 0.000 r clk (IN)
|
|
net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1
|
|
K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O
|
|
net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll
|
|
PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1)
|
|
-2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1
|
|
net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll
|
|
BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O
|
|
net (fo=10004, routed) 1.077 -0.231 u_Axi_CDC/wFifo/pushToPopGray_buffercc/sys_clk
|
|
SLICE_X4Y49 FDCE r u_Axi_CDC/wFifo/pushToPopGray_buffercc/buffers_1_reg[3]/C
|
|
clock pessimism -0.236 -0.467
|
|
SLICE_X4Y49 FDCE (Hold_fdce_C_D) 0.078 -0.389 u_Axi_CDC/wFifo/pushToPopGray_buffercc/buffers_1_reg[3]
|
|
-------------------------------------------------------------------
|
|
required time 0.389
|
|
arrival time -0.264
|
|
-------------------------------------------------------------------
|
|
slack 0.125
|
|
|
|
Slack (MET) : 0.126ns (arrival time - required time)
|
|
Source: u_Axi_CDC/arFifo/pushToPopGray_buffercc/buffers_0_reg[1]/C
|
|
(rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Destination: u_Axi_CDC/arFifo/pushToPopGray_buffercc/buffers_1_reg[1]/D
|
|
(rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Path Group: sys_clk
|
|
Path Type: Hold (Min at Fast Process Corner)
|
|
Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns)
|
|
Data Path Delay: 0.197ns (logic 0.141ns (71.611%) route 0.056ns (28.389%))
|
|
Logic Levels: 0
|
|
Clock Path Skew: 0.000ns (DCD - SCD - CPR)
|
|
Destination Clock Delay (DCD): -0.344ns
|
|
Source Clock Delay (SCD): -0.572ns
|
|
Clock Pessimism Removal (CPR): 0.228ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock sys_clk rise edge) 0.000 0.000 r
|
|
K21 0.000 0.000 r clk (IN)
|
|
net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1
|
|
K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O
|
|
net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll
|
|
PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1)
|
|
-2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1
|
|
net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll
|
|
BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O
|
|
net (fo=10004, routed) 0.690 -0.572 u_Axi_CDC/arFifo/pushToPopGray_buffercc/sys_clk
|
|
SLICE_X15Y66 FDCE r u_Axi_CDC/arFifo/pushToPopGray_buffercc/buffers_0_reg[1]/C
|
|
------------------------------------------------------------------- -------------------
|
|
SLICE_X15Y66 FDCE (Prop_fdce_C_Q) 0.141 -0.431 r u_Axi_CDC/arFifo/pushToPopGray_buffercc/buffers_0_reg[1]/Q
|
|
net (fo=1, routed) 0.056 -0.375 u_Axi_CDC/arFifo/pushToPopGray_buffercc/buffers_0[1]
|
|
SLICE_X15Y66 FDCE r u_Axi_CDC/arFifo/pushToPopGray_buffercc/buffers_1_reg[1]/D
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock sys_clk rise edge) 0.000 0.000 r
|
|
K21 0.000 0.000 r clk (IN)
|
|
net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1
|
|
K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O
|
|
net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll
|
|
PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1)
|
|
-2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1
|
|
net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll
|
|
BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O
|
|
net (fo=10004, routed) 0.964 -0.344 u_Axi_CDC/arFifo/pushToPopGray_buffercc/sys_clk
|
|
SLICE_X15Y66 FDCE r u_Axi_CDC/arFifo/pushToPopGray_buffercc/buffers_1_reg[1]/C
|
|
clock pessimism -0.228 -0.572
|
|
SLICE_X15Y66 FDCE (Hold_fdce_C_D) 0.071 -0.501 u_Axi_CDC/arFifo/pushToPopGray_buffercc/buffers_1_reg[1]
|
|
-------------------------------------------------------------------
|
|
required time 0.501
|
|
arrival time -0.375
|
|
-------------------------------------------------------------------
|
|
slack 0.126
|
|
|
|
Slack (MET) : 0.126ns (arrival time - required time)
|
|
Source: u_Axi_CDC/awFifo/pushToPopGray_buffercc/buffers_0_reg[1]/C
|
|
(rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Destination: u_Axi_CDC/awFifo/pushToPopGray_buffercc/buffers_1_reg[1]/D
|
|
(rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Path Group: sys_clk
|
|
Path Type: Hold (Min at Fast Process Corner)
|
|
Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns)
|
|
Data Path Delay: 0.197ns (logic 0.141ns (71.611%) route 0.056ns (28.389%))
|
|
Logic Levels: 0
|
|
Clock Path Skew: 0.000ns (DCD - SCD - CPR)
|
|
Destination Clock Delay (DCD): -0.348ns
|
|
Source Clock Delay (SCD): -0.576ns
|
|
Clock Pessimism Removal (CPR): 0.228ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock sys_clk rise edge) 0.000 0.000 r
|
|
K21 0.000 0.000 r clk (IN)
|
|
net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1
|
|
K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O
|
|
net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll
|
|
PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1)
|
|
-2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1
|
|
net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll
|
|
BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O
|
|
net (fo=10004, routed) 0.686 -0.576 u_Axi_CDC/awFifo/pushToPopGray_buffercc/sys_clk
|
|
SLICE_X15Y70 FDCE r u_Axi_CDC/awFifo/pushToPopGray_buffercc/buffers_0_reg[1]/C
|
|
------------------------------------------------------------------- -------------------
|
|
SLICE_X15Y70 FDCE (Prop_fdce_C_Q) 0.141 -0.435 r u_Axi_CDC/awFifo/pushToPopGray_buffercc/buffers_0_reg[1]/Q
|
|
net (fo=1, routed) 0.056 -0.379 u_Axi_CDC/awFifo/pushToPopGray_buffercc/buffers_0[1]
|
|
SLICE_X15Y70 FDCE r u_Axi_CDC/awFifo/pushToPopGray_buffercc/buffers_1_reg[1]/D
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock sys_clk rise edge) 0.000 0.000 r
|
|
K21 0.000 0.000 r clk (IN)
|
|
net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1
|
|
K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O
|
|
net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll
|
|
PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1)
|
|
-2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1
|
|
net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll
|
|
BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O
|
|
net (fo=10004, routed) 0.960 -0.348 u_Axi_CDC/awFifo/pushToPopGray_buffercc/sys_clk
|
|
SLICE_X15Y70 FDCE r u_Axi_CDC/awFifo/pushToPopGray_buffercc/buffers_1_reg[1]/C
|
|
clock pessimism -0.228 -0.576
|
|
SLICE_X15Y70 FDCE (Hold_fdce_C_D) 0.071 -0.505 u_Axi_CDC/awFifo/pushToPopGray_buffercc/buffers_1_reg[1]
|
|
-------------------------------------------------------------------
|
|
required time 0.505
|
|
arrival time -0.379
|
|
-------------------------------------------------------------------
|
|
slack 0.126
|
|
|
|
|
|
|
|
|
|
|
|
Pulse Width Checks
|
|
--------------------------------------------------------------------------------------
|
|
Clock Name: sys_clk
|
|
Waveform(ns): { 0.000 10.000 }
|
|
Period(ns): 20.000
|
|
Sources: { pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 }
|
|
|
|
Check Type Corner Lib Pin Reference Pin Required(ns) Actual(ns) Slack(ns) Location Pin
|
|
Min Period n/a RAMB18E1/CLKARDCLK n/a 2.944 20.000 17.056 RAMB18_X1Y24 u_fft_mlkem_axi_slave/u_fft_controller/u_in0/ram_reg/CLKARDCLK
|
|
Min Period n/a RAMB18E1/CLKARDCLK n/a 2.944 20.000 17.056 RAMB18_X1Y25 u_fft_mlkem_axi_slave/u_fft_controller/u_in1/ram_reg/CLKARDCLK
|
|
Min Period n/a RAMB18E1/CLKARDCLK n/a 2.944 20.000 17.056 RAMB18_X1Y22 u_fft_mlkem_axi_slave/u_fft_controller/u_out0/ram_reg/CLKARDCLK
|
|
Min Period n/a RAMB18E1/CLKARDCLK n/a 2.944 20.000 17.056 RAMB18_X1Y23 u_fft_mlkem_axi_slave/u_fft_controller/u_out1/ram_reg/CLKARDCLK
|
|
Min Period n/a RAMB18E1/CLKARDCLK n/a 2.944 20.000 17.056 RAMB18_X3Y30 u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/mem_reg/CLKARDCLK
|
|
Min Period n/a RAMB18E1/CLKBWRCLK n/a 2.944 20.000 17.056 RAMB18_X3Y30 u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/mem_reg/CLKBWRCLK
|
|
Min Period n/a RAMB36E1/CLKARDCLK n/a 2.576 20.000 17.424 RAMB36_X1Y4 u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/TW/ff_im_reg/CLKARDCLK
|
|
Min Period n/a RAMB36E1/CLKARDCLK n/a 2.576 20.000 17.424 RAMB36_X1Y3 u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/TW/ff_re_reg/CLKARDCLK
|
|
Min Period n/a RAMB36E1/CLKARDCLK n/a 2.576 20.000 17.424 RAMB36_X0Y2 u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU2/TW/ff_im_reg/CLKARDCLK
|
|
Min Period n/a RAMB36E1/CLKBWRCLK n/a 2.576 20.000 17.424 RAMB36_X0Y2 u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU2/TW/ff_im_reg/CLKBWRCLK
|
|
Min Period n/a RAMB36E1/CLKARDCLK n/a 2.576 20.000 17.424 RAMB36_X0Y1 u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU4/TW/ff_im_reg/CLKARDCLK
|
|
Min Period n/a RAMB36E1/CLKARDCLK n/a 2.576 20.000 17.424 RAMB36_X0Y0 u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU2/TW/ff_re_reg/CLKARDCLK
|
|
Min Period n/a RAMB36E1/CLKBWRCLK n/a 2.576 20.000 17.424 RAMB36_X0Y0 u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU2/TW/ff_re_reg/CLKBWRCLK
|
|
Min Period n/a RAMB36E1/CLKARDCLK n/a 2.576 20.000 17.424 RAMB36_X1Y2 u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU4/TW/ff_re_reg/CLKARDCLK
|
|
Min Period n/a RAMB18E1/CLKBWRCLK n/a 2.576 20.000 17.424 RAMB18_X1Y24 u_fft_mlkem_axi_slave/u_fft_controller/u_in0/ram_reg/CLKBWRCLK
|
|
Min Period n/a RAMB18E1/CLKBWRCLK n/a 2.576 20.000 17.424 RAMB18_X1Y25 u_fft_mlkem_axi_slave/u_fft_controller/u_in1/ram_reg/CLKBWRCLK
|
|
Min Period n/a RAMB18E1/CLKBWRCLK n/a 2.576 20.000 17.424 RAMB18_X1Y22 u_fft_mlkem_axi_slave/u_fft_controller/u_out0/ram_reg/CLKBWRCLK
|
|
Min Period n/a RAMB18E1/CLKBWRCLK n/a 2.576 20.000 17.424 RAMB18_X1Y23 u_fft_mlkem_axi_slave/u_fft_controller/u_out1/ram_reg/CLKBWRCLK
|
|
Min Period n/a BUFG/I n/a 2.155 20.000 17.845 BUFGCTRL_X0Y16 pll_clk.u_clk_pll/inst/clkout2_buf/I
|
|
Min Period n/a PLLE2_ADV/CLKOUT1 n/a 1.249 20.000 18.751 PLLE2_ADV_X0Y3 pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1
|
|
Min Period n/a FDRE/C n/a 1.000 20.000 19.000 SLICE_X15Y68 cdma_axil_b_bridge_reg/C
|
|
Min Period n/a FDRE/C n/a 1.000 20.000 19.000 SLICE_X24Y67 cdma_axil_r_bridge_reg/C
|
|
Min Period n/a FDRE/C n/a 1.000 20.000 19.000 SLICE_X14Y67 cdma_axil_wr_active_reg/C
|
|
Min Period n/a FDRE/C n/a 1.000 20.000 19.000 SLICE_X15Y67 cdma_axil_wr_bridge_hold_reg/C
|
|
Min Period n/a FDCE/C n/a 1.000 20.000 19.000 SLICE_X30Y0 u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU3/bf1_count_reg[0]/C
|
|
Min Period n/a FDCE/C n/a 1.000 20.000 19.000 SLICE_X30Y0 u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU3/bf1_count_reg[1]/C
|
|
Min Period n/a FDCE/C n/a 1.000 20.000 19.000 SLICE_X29Y0 u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU3/bf1_count_reg[2]/C
|
|
Min Period n/a FDCE/C n/a 1.000 20.000 19.000 SLICE_X29Y0 u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU3/bf1_count_reg[3]/C
|
|
Min Period n/a FDCE/C n/a 1.000 20.000 19.000 SLICE_X29Y0 u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU3/bf1_count_reg[4]/C
|
|
Min Period n/a FDCE/C n/a 1.000 20.000 19.000 SLICE_X30Y0 u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU3/bf1_count_reg[5]/C
|
|
Min Period n/a FDCE/C n/a 1.000 20.000 19.000 SLICE_X31Y0 u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU3/bf1_count_reg[6]/C
|
|
Min Period n/a FDCE/C n/a 1.000 20.000 19.000 SLICE_X31Y0 u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU3/bf1_count_reg[7]/C
|
|
Min Period n/a FDCE/C n/a 1.000 20.000 19.000 SLICE_X31Y0 u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU3/bf1_count_reg[8]/C
|
|
Min Period n/a FDCE/C n/a 1.000 20.000 19.000 SLICE_X30Y0 u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU3/bf1_count_reg[9]/C
|
|
Min Period n/a FDRE/C n/a 1.000 20.000 19.000 SLICE_X17Y5 u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU3/bf1_do_im_reg[0]/C
|
|
Min Period n/a FDRE/C n/a 1.000 20.000 19.000 SLICE_X21Y9 u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU3/bf1_do_im_reg[10]/C
|
|
Min Period n/a FDRE/C n/a 1.000 20.000 19.000 SLICE_X21Y10 u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU3/bf1_do_im_reg[11]/C
|
|
Min Period n/a FDRE/C n/a 1.000 20.000 19.000 SLICE_X21Y10 u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU3/bf1_do_im_reg[12]/C
|
|
Min Period n/a FDRE/C n/a 1.000 20.000 19.000 SLICE_X20Y10 u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU3/bf1_do_im_reg[13]/C
|
|
Min Period n/a FDRE/C n/a 1.000 20.000 19.000 SLICE_X17Y8 u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU3/bf1_do_im_reg[14]/C
|
|
Min Period n/a FDCE/C n/a 1.000 20.000 19.000 SLICE_X5Y51 u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/bf1_count_reg[0]/C
|
|
Min Period n/a FDCE/C n/a 1.000 20.000 19.000 SLICE_X5Y51 u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/bf1_count_reg[1]/C
|
|
Min Period n/a FDCE/C n/a 1.000 20.000 19.000 SLICE_X4Y51 u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/bf1_count_reg[2]/C
|
|
Min Period n/a FDCE/C n/a 1.000 20.000 19.000 SLICE_X4Y51 u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/bf1_count_reg[3]/C
|
|
Min Period n/a FDCE/C n/a 1.000 20.000 19.000 SLICE_X4Y50 u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/bf1_count_reg[4]/C
|
|
Min Period n/a FDCE/C n/a 1.000 20.000 19.000 SLICE_X4Y50 u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/bf1_count_reg[5]/C
|
|
Min Period n/a FDCE/C n/a 1.000 20.000 19.000 SLICE_X4Y50 u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/bf1_count_reg[6]/C
|
|
Min Period n/a FDCE/C n/a 1.000 20.000 19.000 SLICE_X5Y51 u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/bf1_count_reg[7]/C
|
|
Min Period n/a FDCE/C n/a 1.000 20.000 19.000 SLICE_X5Y51 u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/bf1_count_reg[8]/C
|
|
Min Period n/a FDCE/C n/a 1.000 20.000 19.000 SLICE_X5Y51 u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/bf1_count_reg[9]/C
|
|
Max Period n/a PLLE2_ADV/CLKOUT1 n/a 160.000 20.000 140.000 PLLE2_ADV_X0Y3 pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1
|
|
Low Pulse Width Slow RAMD32/CLK n/a 1.250 10.000 8.750 SLICE_X60Y75 u_matmul_axi_slave/b0_c_reg_r1_0_15_18_23/RAMA/CLK
|
|
Low Pulse Width Slow RAMD32/CLK n/a 1.250 10.000 8.750 SLICE_X60Y75 u_matmul_axi_slave/b0_c_reg_r1_0_15_18_23/RAMA_D1/CLK
|
|
Low Pulse Width Slow RAMD32/CLK n/a 1.250 10.000 8.750 SLICE_X60Y75 u_matmul_axi_slave/b0_c_reg_r1_0_15_18_23/RAMB/CLK
|
|
Low Pulse Width Slow RAMD32/CLK n/a 1.250 10.000 8.750 SLICE_X60Y75 u_matmul_axi_slave/b0_c_reg_r1_0_15_18_23/RAMB_D1/CLK
|
|
Low Pulse Width Slow RAMD32/CLK n/a 1.250 10.000 8.750 SLICE_X60Y75 u_matmul_axi_slave/b0_c_reg_r1_0_15_18_23/RAMC/CLK
|
|
Low Pulse Width Slow RAMD32/CLK n/a 1.250 10.000 8.750 SLICE_X60Y75 u_matmul_axi_slave/b0_c_reg_r1_0_15_18_23/RAMC_D1/CLK
|
|
Low Pulse Width Slow RAMS32/CLK n/a 1.250 10.000 8.750 SLICE_X60Y75 u_matmul_axi_slave/b0_c_reg_r1_0_15_18_23/RAMD/CLK
|
|
Low Pulse Width Slow RAMS32/CLK n/a 1.250 10.000 8.750 SLICE_X60Y75 u_matmul_axi_slave/b0_c_reg_r1_0_15_18_23/RAMD_D1/CLK
|
|
Low Pulse Width Slow RAMD32/CLK n/a 1.250 10.000 8.750 SLICE_X68Y68 u_matmul_axi_slave/b0_c_reg_r1_0_15_36_41/RAMA/CLK
|
|
Low Pulse Width Slow RAMD32/CLK n/a 1.250 10.000 8.750 SLICE_X68Y68 u_matmul_axi_slave/b0_c_reg_r1_0_15_36_41/RAMA_D1/CLK
|
|
Low Pulse Width Slow RAMD32/CLK n/a 1.250 10.000 8.750 SLICE_X68Y68 u_matmul_axi_slave/b0_c_reg_r1_0_15_36_41/RAMB/CLK
|
|
Low Pulse Width Slow RAMD32/CLK n/a 1.250 10.000 8.750 SLICE_X68Y68 u_matmul_axi_slave/b0_c_reg_r1_0_15_36_41/RAMB_D1/CLK
|
|
Low Pulse Width Slow RAMD32/CLK n/a 1.250 10.000 8.750 SLICE_X68Y68 u_matmul_axi_slave/b0_c_reg_r1_0_15_36_41/RAMC/CLK
|
|
Low Pulse Width Slow RAMD32/CLK n/a 1.250 10.000 8.750 SLICE_X68Y68 u_matmul_axi_slave/b0_c_reg_r1_0_15_36_41/RAMC_D1/CLK
|
|
Low Pulse Width Slow RAMS32/CLK n/a 1.250 10.000 8.750 SLICE_X68Y68 u_matmul_axi_slave/b0_c_reg_r1_0_15_36_41/RAMD/CLK
|
|
Low Pulse Width Slow RAMS32/CLK n/a 1.250 10.000 8.750 SLICE_X68Y68 u_matmul_axi_slave/b0_c_reg_r1_0_15_36_41/RAMD_D1/CLK
|
|
Low Pulse Width Slow RAMD32/CLK n/a 1.250 10.000 8.750 SLICE_X60Y74 u_matmul_axi_slave/b0_c_reg_r1_0_15_48_53/RAMA/CLK
|
|
Low Pulse Width Slow RAMD32/CLK n/a 1.250 10.000 8.750 SLICE_X60Y74 u_matmul_axi_slave/b0_c_reg_r1_0_15_48_53/RAMA_D1/CLK
|
|
Low Pulse Width Slow RAMD32/CLK n/a 1.250 10.000 8.750 SLICE_X60Y74 u_matmul_axi_slave/b0_c_reg_r1_0_15_48_53/RAMB/CLK
|
|
Low Pulse Width Slow RAMD32/CLK n/a 1.250 10.000 8.750 SLICE_X60Y74 u_matmul_axi_slave/b0_c_reg_r1_0_15_48_53/RAMB_D1/CLK
|
|
Low Pulse Width Slow RAMD32/CLK n/a 1.250 10.000 8.750 SLICE_X60Y74 u_matmul_axi_slave/b0_c_reg_r1_0_15_48_53/RAMC/CLK
|
|
Low Pulse Width Slow RAMD32/CLK n/a 1.250 10.000 8.750 SLICE_X60Y74 u_matmul_axi_slave/b0_c_reg_r1_0_15_48_53/RAMC_D1/CLK
|
|
Low Pulse Width Slow RAMS32/CLK n/a 1.250 10.000 8.750 SLICE_X60Y74 u_matmul_axi_slave/b0_c_reg_r1_0_15_48_53/RAMD/CLK
|
|
Low Pulse Width Slow RAMS32/CLK n/a 1.250 10.000 8.750 SLICE_X60Y74 u_matmul_axi_slave/b0_c_reg_r1_0_15_48_53/RAMD_D1/CLK
|
|
Low Pulse Width Slow RAMD32/CLK n/a 1.250 10.000 8.750 SLICE_X62Y71 u_matmul_axi_slave/b0_c_reg_r1_0_15_60_65/RAMA/CLK
|
|
Low Pulse Width Slow RAMD32/CLK n/a 1.250 10.000 8.750 SLICE_X62Y71 u_matmul_axi_slave/b0_c_reg_r1_0_15_60_65/RAMA_D1/CLK
|
|
Low Pulse Width Slow RAMD32/CLK n/a 1.250 10.000 8.750 SLICE_X62Y71 u_matmul_axi_slave/b0_c_reg_r1_0_15_60_65/RAMB/CLK
|
|
Low Pulse Width Slow RAMD32/CLK n/a 1.250 10.000 8.750 SLICE_X62Y71 u_matmul_axi_slave/b0_c_reg_r1_0_15_60_65/RAMB_D1/CLK
|
|
Low Pulse Width Slow RAMD32/CLK n/a 1.250 10.000 8.750 SLICE_X62Y71 u_matmul_axi_slave/b0_c_reg_r1_0_15_60_65/RAMC/CLK
|
|
Low Pulse Width Slow RAMD32/CLK n/a 1.250 10.000 8.750 SLICE_X62Y71 u_matmul_axi_slave/b0_c_reg_r1_0_15_60_65/RAMC_D1/CLK
|
|
Low Pulse Width Slow RAMS32/CLK n/a 1.250 10.000 8.750 SLICE_X62Y71 u_matmul_axi_slave/b0_c_reg_r1_0_15_60_65/RAMD/CLK
|
|
Low Pulse Width Slow RAMS32/CLK n/a 1.250 10.000 8.750 SLICE_X62Y71 u_matmul_axi_slave/b0_c_reg_r1_0_15_60_65/RAMD_D1/CLK
|
|
Low Pulse Width Fast RAMD32/CLK n/a 1.250 10.000 8.750 SLICE_X44Y69 u_matmul_axi_slave/b0_c_reg_r2_0_15_36_41/RAMA/CLK
|
|
Low Pulse Width Fast RAMD32/CLK n/a 1.250 10.000 8.750 SLICE_X44Y69 u_matmul_axi_slave/b0_c_reg_r2_0_15_36_41/RAMA_D1/CLK
|
|
Low Pulse Width Fast RAMD32/CLK n/a 1.250 10.000 8.750 SLICE_X44Y69 u_matmul_axi_slave/b0_c_reg_r2_0_15_36_41/RAMB/CLK
|
|
Low Pulse Width Fast RAMD32/CLK n/a 1.250 10.000 8.750 SLICE_X44Y69 u_matmul_axi_slave/b0_c_reg_r2_0_15_36_41/RAMB_D1/CLK
|
|
Low Pulse Width Fast RAMD32/CLK n/a 1.250 10.000 8.750 SLICE_X44Y69 u_matmul_axi_slave/b0_c_reg_r2_0_15_36_41/RAMC/CLK
|
|
Low Pulse Width Fast RAMD32/CLK n/a 1.250 10.000 8.750 SLICE_X44Y69 u_matmul_axi_slave/b0_c_reg_r2_0_15_36_41/RAMC_D1/CLK
|
|
Low Pulse Width Fast RAMS32/CLK n/a 1.250 10.000 8.750 SLICE_X44Y69 u_matmul_axi_slave/b0_c_reg_r2_0_15_36_41/RAMD/CLK
|
|
Low Pulse Width Fast RAMS32/CLK n/a 1.250 10.000 8.750 SLICE_X44Y69 u_matmul_axi_slave/b0_c_reg_r2_0_15_36_41/RAMD_D1/CLK
|
|
Low Pulse Width Fast RAMD32/CLK n/a 1.250 10.000 8.750 SLICE_X42Y71 u_matmul_axi_slave/b0_c_reg_r2_0_15_6_11/RAMA/CLK
|
|
Low Pulse Width Fast RAMD32/CLK n/a 1.250 10.000 8.750 SLICE_X42Y71 u_matmul_axi_slave/b0_c_reg_r2_0_15_6_11/RAMA_D1/CLK
|
|
Low Pulse Width Fast RAMD32/CLK n/a 1.250 10.000 8.750 SLICE_X42Y71 u_matmul_axi_slave/b0_c_reg_r2_0_15_6_11/RAMB/CLK
|
|
Low Pulse Width Fast RAMD32/CLK n/a 1.250 10.000 8.750 SLICE_X42Y71 u_matmul_axi_slave/b0_c_reg_r2_0_15_6_11/RAMB_D1/CLK
|
|
Low Pulse Width Fast RAMD32/CLK n/a 1.250 10.000 8.750 SLICE_X42Y71 u_matmul_axi_slave/b0_c_reg_r2_0_15_6_11/RAMC/CLK
|
|
Low Pulse Width Fast RAMD32/CLK n/a 1.250 10.000 8.750 SLICE_X42Y71 u_matmul_axi_slave/b0_c_reg_r2_0_15_6_11/RAMC_D1/CLK
|
|
Low Pulse Width Fast RAMS32/CLK n/a 1.250 10.000 8.750 SLICE_X42Y71 u_matmul_axi_slave/b0_c_reg_r2_0_15_6_11/RAMD/CLK
|
|
Low Pulse Width Fast RAMS32/CLK n/a 1.250 10.000 8.750 SLICE_X42Y71 u_matmul_axi_slave/b0_c_reg_r2_0_15_6_11/RAMD_D1/CLK
|
|
Low Pulse Width Fast RAMD32/CLK n/a 1.250 10.000 8.750 SLICE_X20Y72 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_12_17/RAMA/CLK
|
|
Low Pulse Width Fast RAMD32/CLK n/a 1.250 10.000 8.750 SLICE_X20Y72 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_12_17/RAMA_D1/CLK
|
|
High Pulse Width Slow RAMD32/CLK n/a 1.250 10.000 8.750 SLICE_X64Y68 u_matmul_axi_slave/b0_c_reg_r1_0_15_0_5/RAMA/CLK
|
|
High Pulse Width Slow RAMD32/CLK n/a 1.250 10.000 8.750 SLICE_X64Y68 u_matmul_axi_slave/b0_c_reg_r1_0_15_0_5/RAMA_D1/CLK
|
|
High Pulse Width Slow RAMD32/CLK n/a 1.250 10.000 8.750 SLICE_X64Y68 u_matmul_axi_slave/b0_c_reg_r1_0_15_0_5/RAMB/CLK
|
|
High Pulse Width Slow RAMD32/CLK n/a 1.250 10.000 8.750 SLICE_X64Y68 u_matmul_axi_slave/b0_c_reg_r1_0_15_0_5/RAMB_D1/CLK
|
|
High Pulse Width Slow RAMD32/CLK n/a 1.250 10.000 8.750 SLICE_X64Y68 u_matmul_axi_slave/b0_c_reg_r1_0_15_0_5/RAMC/CLK
|
|
High Pulse Width Slow RAMD32/CLK n/a 1.250 10.000 8.750 SLICE_X64Y68 u_matmul_axi_slave/b0_c_reg_r1_0_15_0_5/RAMC_D1/CLK
|
|
High Pulse Width Slow RAMS32/CLK n/a 1.250 10.000 8.750 SLICE_X64Y68 u_matmul_axi_slave/b0_c_reg_r1_0_15_0_5/RAMD/CLK
|
|
High Pulse Width Slow RAMS32/CLK n/a 1.250 10.000 8.750 SLICE_X64Y68 u_matmul_axi_slave/b0_c_reg_r1_0_15_0_5/RAMD_D1/CLK
|
|
High Pulse Width Slow RAMD32/CLK n/a 1.250 10.000 8.750 SLICE_X64Y69 u_matmul_axi_slave/b0_c_reg_r1_0_15_30_35/RAMA/CLK
|
|
High Pulse Width Slow RAMD32/CLK n/a 1.250 10.000 8.750 SLICE_X64Y69 u_matmul_axi_slave/b0_c_reg_r1_0_15_30_35/RAMA_D1/CLK
|
|
High Pulse Width Slow RAMD32/CLK n/a 1.250 10.000 8.750 SLICE_X64Y69 u_matmul_axi_slave/b0_c_reg_r1_0_15_30_35/RAMB/CLK
|
|
High Pulse Width Slow RAMD32/CLK n/a 1.250 10.000 8.750 SLICE_X64Y69 u_matmul_axi_slave/b0_c_reg_r1_0_15_30_35/RAMB_D1/CLK
|
|
High Pulse Width Slow RAMD32/CLK n/a 1.250 10.000 8.750 SLICE_X64Y69 u_matmul_axi_slave/b0_c_reg_r1_0_15_30_35/RAMC/CLK
|
|
High Pulse Width Slow RAMD32/CLK n/a 1.250 10.000 8.750 SLICE_X64Y69 u_matmul_axi_slave/b0_c_reg_r1_0_15_30_35/RAMC_D1/CLK
|
|
High Pulse Width Slow RAMS32/CLK n/a 1.250 10.000 8.750 SLICE_X64Y69 u_matmul_axi_slave/b0_c_reg_r1_0_15_30_35/RAMD/CLK
|
|
High Pulse Width Slow RAMS32/CLK n/a 1.250 10.000 8.750 SLICE_X64Y69 u_matmul_axi_slave/b0_c_reg_r1_0_15_30_35/RAMD_D1/CLK
|
|
High Pulse Width Slow RAMD32/CLK n/a 1.250 10.000 8.750 SLICE_X60Y72 u_matmul_axi_slave/b0_c_reg_r1_0_15_54_59/RAMA/CLK
|
|
High Pulse Width Slow RAMD32/CLK n/a 1.250 10.000 8.750 SLICE_X60Y72 u_matmul_axi_slave/b0_c_reg_r1_0_15_54_59/RAMA_D1/CLK
|
|
High Pulse Width Slow RAMD32/CLK n/a 1.250 10.000 8.750 SLICE_X60Y72 u_matmul_axi_slave/b0_c_reg_r1_0_15_54_59/RAMB/CLK
|
|
High Pulse Width Slow RAMD32/CLK n/a 1.250 10.000 8.750 SLICE_X60Y72 u_matmul_axi_slave/b0_c_reg_r1_0_15_54_59/RAMB_D1/CLK
|
|
High Pulse Width Slow RAMD32/CLK n/a 1.250 10.000 8.750 SLICE_X60Y72 u_matmul_axi_slave/b0_c_reg_r1_0_15_54_59/RAMC/CLK
|
|
High Pulse Width Slow RAMD32/CLK n/a 1.250 10.000 8.750 SLICE_X60Y72 u_matmul_axi_slave/b0_c_reg_r1_0_15_54_59/RAMC_D1/CLK
|
|
High Pulse Width Slow RAMS32/CLK n/a 1.250 10.000 8.750 SLICE_X60Y72 u_matmul_axi_slave/b0_c_reg_r1_0_15_54_59/RAMD/CLK
|
|
High Pulse Width Slow RAMS32/CLK n/a 1.250 10.000 8.750 SLICE_X60Y72 u_matmul_axi_slave/b0_c_reg_r1_0_15_54_59/RAMD_D1/CLK
|
|
High Pulse Width Fast RAMD32/CLK n/a 1.250 10.000 8.750 SLICE_X62Y71 u_matmul_axi_slave/b0_c_reg_r1_0_15_60_65/RAMA/CLK
|
|
High Pulse Width Fast RAMD32/CLK n/a 1.250 10.000 8.750 SLICE_X62Y71 u_matmul_axi_slave/b0_c_reg_r1_0_15_60_65/RAMA_D1/CLK
|
|
High Pulse Width Fast RAMD32/CLK n/a 1.250 10.000 8.750 SLICE_X62Y71 u_matmul_axi_slave/b0_c_reg_r1_0_15_60_65/RAMB/CLK
|
|
High Pulse Width Fast RAMD32/CLK n/a 1.250 10.000 8.750 SLICE_X62Y71 u_matmul_axi_slave/b0_c_reg_r1_0_15_60_65/RAMB_D1/CLK
|
|
High Pulse Width Fast RAMD32/CLK n/a 1.250 10.000 8.750 SLICE_X62Y71 u_matmul_axi_slave/b0_c_reg_r1_0_15_60_65/RAMC/CLK
|
|
High Pulse Width Fast RAMD32/CLK n/a 1.250 10.000 8.750 SLICE_X62Y71 u_matmul_axi_slave/b0_c_reg_r1_0_15_60_65/RAMC_D1/CLK
|
|
High Pulse Width Fast RAMS32/CLK n/a 1.250 10.000 8.750 SLICE_X62Y71 u_matmul_axi_slave/b0_c_reg_r1_0_15_60_65/RAMD/CLK
|
|
High Pulse Width Fast RAMS32/CLK n/a 1.250 10.000 8.750 SLICE_X62Y71 u_matmul_axi_slave/b0_c_reg_r1_0_15_60_65/RAMD_D1/CLK
|
|
High Pulse Width Fast RAMD32/CLK n/a 1.250 10.000 8.750 SLICE_X22Y75 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_36_41/RAMA/CLK
|
|
High Pulse Width Fast RAMD32/CLK n/a 1.250 10.000 8.750 SLICE_X22Y75 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_36_41/RAMA_D1/CLK
|
|
High Pulse Width Fast RAMD32/CLK n/a 1.250 10.000 8.750 SLICE_X22Y75 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_36_41/RAMB/CLK
|
|
High Pulse Width Fast RAMD32/CLK n/a 1.250 10.000 8.750 SLICE_X22Y75 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_36_41/RAMB_D1/CLK
|
|
High Pulse Width Fast RAMD32/CLK n/a 1.250 10.000 8.750 SLICE_X22Y75 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_36_41/RAMC/CLK
|
|
High Pulse Width Fast RAMD32/CLK n/a 1.250 10.000 8.750 SLICE_X22Y75 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_36_41/RAMC_D1/CLK
|
|
High Pulse Width Fast RAMS32/CLK n/a 1.250 10.000 8.750 SLICE_X22Y75 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_36_41/RAMD/CLK
|
|
High Pulse Width Fast RAMS32/CLK n/a 1.250 10.000 8.750 SLICE_X22Y75 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_36_41/RAMD_D1/CLK
|
|
High Pulse Width Fast RAMD32/CLK n/a 1.250 10.000 8.750 SLICE_X36Y68 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/ram_reg_0_3_0_5/RAMA/CLK
|
|
High Pulse Width Fast RAMD32/CLK n/a 1.250 10.000 8.750 SLICE_X36Y68 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/ram_reg_0_3_0_5/RAMA_D1/CLK
|
|
High Pulse Width Fast RAMD32/CLK n/a 1.250 10.000 8.750 SLICE_X36Y68 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/ram_reg_0_3_0_5/RAMB/CLK
|
|
High Pulse Width Fast RAMD32/CLK n/a 1.250 10.000 8.750 SLICE_X36Y68 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/ram_reg_0_3_0_5/RAMB_D1/CLK
|
|
High Pulse Width Fast RAMD32/CLK n/a 1.250 10.000 8.750 SLICE_X36Y68 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/ram_reg_0_3_0_5/RAMC/CLK
|
|
High Pulse Width Fast RAMD32/CLK n/a 1.250 10.000 8.750 SLICE_X36Y68 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/ram_reg_0_3_0_5/RAMC_D1/CLK
|
|
High Pulse Width Fast RAMS32/CLK n/a 1.250 10.000 8.750 SLICE_X36Y68 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/ram_reg_0_3_0_5/RAMD/CLK
|
|
High Pulse Width Fast RAMS32/CLK n/a 1.250 10.000 8.750 SLICE_X36Y68 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/ram_reg_0_3_0_5/RAMD_D1/CLK
|
|
High Pulse Width Fast RAMD32/CLK n/a 1.250 10.000 8.750 SLICE_X56Y75 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/ram_reg_0_7_12_17/RAMA/CLK
|
|
High Pulse Width Fast RAMD32/CLK n/a 1.250 10.000 8.750 SLICE_X56Y75 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/ram_reg_0_7_12_17/RAMA_D1/CLK
|
|
|
|
|
|
|
|
---------------------------------------------------------------------------------------------------
|
|
From Clock: sys_clk
|
|
To Clock: mlkem_clk_clk_pll
|
|
|
|
Setup : NA Failing Endpoints, Worst Slack NA , Total Violation NA
|
|
Hold : 0 Failing Endpoints, Worst Slack 0.054ns, Total Violation 0.000ns
|
|
---------------------------------------------------------------------------------------------------
|
|
|
|
|
|
Min Delay Paths
|
|
--------------------------------------------------------------------------------------
|
|
Slack (MET) : 0.054ns (arrival time - required time)
|
|
Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_12_17/RAMB/CLK
|
|
(rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/_zz_ram_port1_reg[14]/D
|
|
(rising edge-triggered cell FDRE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns})
|
|
Path Group: mlkem_clk_clk_pll
|
|
Path Type: Hold (Min at Fast Process Corner)
|
|
Requirement: 0.000ns (mlkem_clk_clk_pll rise@0.000ns - sys_clk rise@0.000ns)
|
|
Data Path Delay: 0.567ns (logic 0.394ns (69.509%) route 0.173ns (30.491%))
|
|
Logic Levels: 0
|
|
Clock Path Skew: 0.323ns (DCD - SCD - CPR)
|
|
Destination Clock Delay (DCD): -0.355ns
|
|
Source Clock Delay (SCD): -0.579ns
|
|
Clock Pessimism Removal (CPR): -0.099ns
|
|
Clock Uncertainty: 0.197ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Discrete Jitter (DJ): 0.136ns
|
|
Phase Error (PE): 0.120ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock sys_clk rise edge) 0.000 0.000 r
|
|
K21 0.000 0.000 r clk (IN)
|
|
net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1
|
|
K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O
|
|
net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll
|
|
PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1)
|
|
-2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1
|
|
net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll
|
|
BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O
|
|
net (fo=10004, routed) 0.683 -0.579 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_12_17/WCLK
|
|
SLICE_X20Y72 RAMD32 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_12_17/RAMB/CLK
|
|
------------------------------------------------------------------- -------------------
|
|
SLICE_X20Y72 RAMD32 (Prop_ramd32_CLK_O)
|
|
0.394 -0.185 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_12_17/RAMB/O
|
|
net (fo=1, routed) 0.173 -0.013 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/_zz_ram_port10__2[14]
|
|
SLICE_X23Y73 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/_zz_ram_port1_reg[14]/D
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock mlkem_clk_clk_pll rise edge)
|
|
0.000 0.000 r
|
|
K21 0.000 0.000 r clk (IN)
|
|
net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1
|
|
K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O
|
|
net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll
|
|
PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2)
|
|
-2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2
|
|
net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll
|
|
BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout3_buf/O
|
|
net (fo=26129, routed) 0.953 -0.355 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/mlkem_clk
|
|
SLICE_X23Y73 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/_zz_ram_port1_reg[14]/C
|
|
clock pessimism 0.099 -0.256
|
|
clock uncertainty 0.197 -0.060
|
|
SLICE_X23Y73 FDRE (Hold_fdre_C_D) -0.007 -0.067 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/_zz_ram_port1_reg[14]
|
|
-------------------------------------------------------------------
|
|
required time 0.067
|
|
arrival time -0.013
|
|
-------------------------------------------------------------------
|
|
slack 0.054
|
|
|
|
Slack (MET) : 0.108ns (arrival time - required time)
|
|
Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/ram_reg_0_3_30_35/RAMC/CLK
|
|
(rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/_zz_ram_port1_reg[34]/D
|
|
(rising edge-triggered cell FDRE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns})
|
|
Path Group: mlkem_clk_clk_pll
|
|
Path Type: Hold (Min at Fast Process Corner)
|
|
Requirement: 0.000ns (mlkem_clk_clk_pll rise@0.000ns - sys_clk rise@0.000ns)
|
|
Data Path Delay: 0.633ns (logic 0.390ns (61.631%) route 0.243ns (38.369%))
|
|
Logic Levels: 0
|
|
Clock Path Skew: 0.326ns (DCD - SCD - CPR)
|
|
Destination Clock Delay (DCD): -0.353ns
|
|
Source Clock Delay (SCD): -0.580ns
|
|
Clock Pessimism Removal (CPR): -0.099ns
|
|
Clock Uncertainty: 0.197ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Discrete Jitter (DJ): 0.136ns
|
|
Phase Error (PE): 0.120ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock sys_clk rise edge) 0.000 0.000 r
|
|
K21 0.000 0.000 r clk (IN)
|
|
net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1
|
|
K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O
|
|
net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll
|
|
PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1)
|
|
-2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1
|
|
net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll
|
|
BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O
|
|
net (fo=10004, routed) 0.682 -0.580 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/ram_reg_0_3_30_35/WCLK
|
|
SLICE_X22Y71 RAMD32 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/ram_reg_0_3_30_35/RAMC/CLK
|
|
------------------------------------------------------------------- -------------------
|
|
SLICE_X22Y71 RAMD32 (Prop_ramd32_CLK_O)
|
|
0.390 -0.190 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/ram_reg_0_3_30_35/RAMC/O
|
|
net (fo=1, routed) 0.243 0.052 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/_zz_ram_port10[34]
|
|
SLICE_X25Y70 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/_zz_ram_port1_reg[34]/D
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock mlkem_clk_clk_pll rise edge)
|
|
0.000 0.000 r
|
|
K21 0.000 0.000 r clk (IN)
|
|
net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1
|
|
K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O
|
|
net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll
|
|
PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2)
|
|
-2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2
|
|
net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll
|
|
BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout3_buf/O
|
|
net (fo=26129, routed) 0.955 -0.353 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/mlkem_clk
|
|
SLICE_X25Y70 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/_zz_ram_port1_reg[34]/C
|
|
clock pessimism 0.099 -0.254
|
|
clock uncertainty 0.197 -0.058
|
|
SLICE_X25Y70 FDRE (Hold_fdre_C_D) 0.002 -0.056 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/_zz_ram_port1_reg[34]
|
|
-------------------------------------------------------------------
|
|
required time 0.056
|
|
arrival time 0.052
|
|
-------------------------------------------------------------------
|
|
slack 0.108
|
|
|
|
Slack (MET) : 0.113ns (arrival time - required time)
|
|
Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_12_17/RAMA_D1/CLK
|
|
(rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/_zz_ram_port1_reg[13]/D
|
|
(rising edge-triggered cell FDRE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns})
|
|
Path Group: mlkem_clk_clk_pll
|
|
Path Type: Hold (Min at Fast Process Corner)
|
|
Requirement: 0.000ns (mlkem_clk_clk_pll rise@0.000ns - sys_clk rise@0.000ns)
|
|
Data Path Delay: 0.678ns (logic 0.478ns (70.458%) route 0.200ns (29.542%))
|
|
Logic Levels: 0
|
|
Clock Path Skew: 0.323ns (DCD - SCD - CPR)
|
|
Destination Clock Delay (DCD): -0.355ns
|
|
Source Clock Delay (SCD): -0.579ns
|
|
Clock Pessimism Removal (CPR): -0.099ns
|
|
Clock Uncertainty: 0.197ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Discrete Jitter (DJ): 0.136ns
|
|
Phase Error (PE): 0.120ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock sys_clk rise edge) 0.000 0.000 r
|
|
K21 0.000 0.000 r clk (IN)
|
|
net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1
|
|
K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O
|
|
net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll
|
|
PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1)
|
|
-2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1
|
|
net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll
|
|
BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O
|
|
net (fo=10004, routed) 0.683 -0.579 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_12_17/WCLK
|
|
SLICE_X20Y72 RAMD32 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_12_17/RAMA_D1/CLK
|
|
------------------------------------------------------------------- -------------------
|
|
SLICE_X20Y72 RAMD32 (Prop_ramd32_CLK_O)
|
|
0.478 -0.101 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_12_17/RAMA_D1/O
|
|
net (fo=1, routed) 0.200 0.099 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/_zz_ram_port10__2[13]
|
|
SLICE_X23Y73 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/_zz_ram_port1_reg[13]/D
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock mlkem_clk_clk_pll rise edge)
|
|
0.000 0.000 r
|
|
K21 0.000 0.000 r clk (IN)
|
|
net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1
|
|
K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O
|
|
net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll
|
|
PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2)
|
|
-2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2
|
|
net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll
|
|
BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout3_buf/O
|
|
net (fo=26129, routed) 0.953 -0.355 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/mlkem_clk
|
|
SLICE_X23Y73 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/_zz_ram_port1_reg[13]/C
|
|
clock pessimism 0.099 -0.256
|
|
clock uncertainty 0.197 -0.060
|
|
SLICE_X23Y73 FDRE (Hold_fdre_C_D) 0.046 -0.014 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/_zz_ram_port1_reg[13]
|
|
-------------------------------------------------------------------
|
|
required time 0.014
|
|
arrival time 0.099
|
|
-------------------------------------------------------------------
|
|
slack 0.113
|
|
|
|
Slack (MET) : 0.126ns (arrival time - required time)
|
|
Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_36_41/RAMB/CLK
|
|
(rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/_zz_ram_port1_reg[38]/D
|
|
(rising edge-triggered cell FDRE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns})
|
|
Path Group: mlkem_clk_clk_pll
|
|
Path Type: Hold (Min at Fast Process Corner)
|
|
Requirement: 0.000ns (mlkem_clk_clk_pll rise@0.000ns - sys_clk rise@0.000ns)
|
|
Data Path Delay: 0.641ns (logic 0.394ns (61.457%) route 0.247ns (38.543%))
|
|
Logic Levels: 0
|
|
Clock Path Skew: 0.325ns (DCD - SCD - CPR)
|
|
Destination Clock Delay (DCD): -0.357ns
|
|
Source Clock Delay (SCD): -0.583ns
|
|
Clock Pessimism Removal (CPR): -0.099ns
|
|
Clock Uncertainty: 0.197ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Discrete Jitter (DJ): 0.136ns
|
|
Phase Error (PE): 0.120ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock sys_clk rise edge) 0.000 0.000 r
|
|
K21 0.000 0.000 r clk (IN)
|
|
net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1
|
|
K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O
|
|
net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll
|
|
PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1)
|
|
-2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1
|
|
net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll
|
|
BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O
|
|
net (fo=10004, routed) 0.679 -0.583 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_36_41/WCLK
|
|
SLICE_X22Y75 RAMD32 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_36_41/RAMB/CLK
|
|
------------------------------------------------------------------- -------------------
|
|
SLICE_X22Y75 RAMD32 (Prop_ramd32_CLK_O)
|
|
0.394 -0.189 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_36_41/RAMB/O
|
|
net (fo=1, routed) 0.247 0.058 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/_zz_ram_port10__2[38]
|
|
SLICE_X24Y76 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/_zz_ram_port1_reg[38]/D
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock mlkem_clk_clk_pll rise edge)
|
|
0.000 0.000 r
|
|
K21 0.000 0.000 r clk (IN)
|
|
net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1
|
|
K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O
|
|
net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll
|
|
PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2)
|
|
-2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2
|
|
net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll
|
|
BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout3_buf/O
|
|
net (fo=26129, routed) 0.951 -0.357 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/mlkem_clk
|
|
SLICE_X24Y76 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/_zz_ram_port1_reg[38]/C
|
|
clock pessimism 0.099 -0.258
|
|
clock uncertainty 0.197 -0.062
|
|
SLICE_X24Y76 FDRE (Hold_fdre_C_D) -0.007 -0.069 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/_zz_ram_port1_reg[38]
|
|
-------------------------------------------------------------------
|
|
required time 0.069
|
|
arrival time 0.058
|
|
-------------------------------------------------------------------
|
|
slack 0.126
|
|
|
|
Slack (MET) : 0.129ns (arrival time - required time)
|
|
Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_36_41/RAMA_D1/CLK
|
|
(rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/_zz_ram_port1_reg[37]/D
|
|
(rising edge-triggered cell FDRE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns})
|
|
Path Group: mlkem_clk_clk_pll
|
|
Path Type: Hold (Min at Fast Process Corner)
|
|
Requirement: 0.000ns (mlkem_clk_clk_pll rise@0.000ns - sys_clk rise@0.000ns)
|
|
Data Path Delay: 0.720ns (logic 0.478ns (66.344%) route 0.242ns (33.656%))
|
|
Logic Levels: 0
|
|
Clock Path Skew: 0.325ns (DCD - SCD - CPR)
|
|
Destination Clock Delay (DCD): -0.357ns
|
|
Source Clock Delay (SCD): -0.583ns
|
|
Clock Pessimism Removal (CPR): -0.099ns
|
|
Clock Uncertainty: 0.197ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Discrete Jitter (DJ): 0.136ns
|
|
Phase Error (PE): 0.120ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock sys_clk rise edge) 0.000 0.000 r
|
|
K21 0.000 0.000 r clk (IN)
|
|
net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1
|
|
K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O
|
|
net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll
|
|
PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1)
|
|
-2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1
|
|
net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll
|
|
BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O
|
|
net (fo=10004, routed) 0.679 -0.583 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_36_41/WCLK
|
|
SLICE_X22Y75 RAMD32 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_36_41/RAMA_D1/CLK
|
|
------------------------------------------------------------------- -------------------
|
|
SLICE_X22Y75 RAMD32 (Prop_ramd32_CLK_O)
|
|
0.478 -0.105 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_36_41/RAMA_D1/O
|
|
net (fo=1, routed) 0.242 0.137 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/_zz_ram_port10__2[37]
|
|
SLICE_X27Y76 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/_zz_ram_port1_reg[37]/D
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock mlkem_clk_clk_pll rise edge)
|
|
0.000 0.000 r
|
|
K21 0.000 0.000 r clk (IN)
|
|
net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1
|
|
K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O
|
|
net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll
|
|
PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2)
|
|
-2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2
|
|
net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll
|
|
BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout3_buf/O
|
|
net (fo=26129, routed) 0.951 -0.357 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/mlkem_clk
|
|
SLICE_X27Y76 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/_zz_ram_port1_reg[37]/C
|
|
clock pessimism 0.099 -0.258
|
|
clock uncertainty 0.197 -0.062
|
|
SLICE_X27Y76 FDRE (Hold_fdre_C_D) 0.070 0.008 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/_zz_ram_port1_reg[37]
|
|
-------------------------------------------------------------------
|
|
required time -0.008
|
|
arrival time 0.137
|
|
-------------------------------------------------------------------
|
|
slack 0.129
|
|
|
|
Slack (MET) : 0.134ns (arrival time - required time)
|
|
Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/ram_reg_0_3_30_35/RAMB/CLK
|
|
(rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/_zz_ram_port1_reg[32]/D
|
|
(rising edge-triggered cell FDRE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns})
|
|
Path Group: mlkem_clk_clk_pll
|
|
Path Type: Hold (Min at Fast Process Corner)
|
|
Requirement: 0.000ns (mlkem_clk_clk_pll rise@0.000ns - sys_clk rise@0.000ns)
|
|
Data Path Delay: 0.629ns (logic 0.394ns (62.601%) route 0.235ns (37.399%))
|
|
Logic Levels: 0
|
|
Clock Path Skew: 0.326ns (DCD - SCD - CPR)
|
|
Destination Clock Delay (DCD): -0.353ns
|
|
Source Clock Delay (SCD): -0.580ns
|
|
Clock Pessimism Removal (CPR): -0.099ns
|
|
Clock Uncertainty: 0.197ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Discrete Jitter (DJ): 0.136ns
|
|
Phase Error (PE): 0.120ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock sys_clk rise edge) 0.000 0.000 r
|
|
K21 0.000 0.000 r clk (IN)
|
|
net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1
|
|
K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O
|
|
net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll
|
|
PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1)
|
|
-2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1
|
|
net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll
|
|
BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O
|
|
net (fo=10004, routed) 0.682 -0.580 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/ram_reg_0_3_30_35/WCLK
|
|
SLICE_X22Y71 RAMD32 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/ram_reg_0_3_30_35/RAMB/CLK
|
|
------------------------------------------------------------------- -------------------
|
|
SLICE_X22Y71 RAMD32 (Prop_ramd32_CLK_O)
|
|
0.394 -0.186 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/ram_reg_0_3_30_35/RAMB/O
|
|
net (fo=1, routed) 0.235 0.049 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/_zz_ram_port10[32]
|
|
SLICE_X25Y70 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/_zz_ram_port1_reg[32]/D
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock mlkem_clk_clk_pll rise edge)
|
|
0.000 0.000 r
|
|
K21 0.000 0.000 r clk (IN)
|
|
net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1
|
|
K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O
|
|
net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll
|
|
PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2)
|
|
-2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2
|
|
net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll
|
|
BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout3_buf/O
|
|
net (fo=26129, routed) 0.955 -0.353 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/mlkem_clk
|
|
SLICE_X25Y70 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/_zz_ram_port1_reg[32]/C
|
|
clock pessimism 0.099 -0.254
|
|
clock uncertainty 0.197 -0.058
|
|
SLICE_X25Y70 FDRE (Hold_fdre_C_D) -0.027 -0.085 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/_zz_ram_port1_reg[32]
|
|
-------------------------------------------------------------------
|
|
required time 0.085
|
|
arrival time 0.049
|
|
-------------------------------------------------------------------
|
|
slack 0.134
|
|
|
|
Slack (MET) : 0.137ns (arrival time - required time)
|
|
Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_36_41/RAMB_D1/CLK
|
|
(rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/_zz_ram_port1_reg[39]/D
|
|
(rising edge-triggered cell FDRE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns})
|
|
Path Group: mlkem_clk_clk_pll
|
|
Path Type: Hold (Min at Fast Process Corner)
|
|
Requirement: 0.000ns (mlkem_clk_clk_pll rise@0.000ns - sys_clk rise@0.000ns)
|
|
Data Path Delay: 0.725ns (logic 0.388ns (53.539%) route 0.337ns (46.461%))
|
|
Logic Levels: 0
|
|
Clock Path Skew: 0.325ns (DCD - SCD - CPR)
|
|
Destination Clock Delay (DCD): -0.357ns
|
|
Source Clock Delay (SCD): -0.583ns
|
|
Clock Pessimism Removal (CPR): -0.099ns
|
|
Clock Uncertainty: 0.197ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Discrete Jitter (DJ): 0.136ns
|
|
Phase Error (PE): 0.120ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock sys_clk rise edge) 0.000 0.000 r
|
|
K21 0.000 0.000 r clk (IN)
|
|
net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1
|
|
K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O
|
|
net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll
|
|
PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1)
|
|
-2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1
|
|
net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll
|
|
BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O
|
|
net (fo=10004, routed) 0.679 -0.583 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_36_41/WCLK
|
|
SLICE_X22Y75 RAMD32 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_36_41/RAMB_D1/CLK
|
|
------------------------------------------------------------------- -------------------
|
|
SLICE_X22Y75 RAMD32 (Prop_ramd32_CLK_O)
|
|
0.388 -0.195 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_36_41/RAMB_D1/O
|
|
net (fo=1, routed) 0.337 0.141 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/_zz_ram_port10__2[39]
|
|
SLICE_X27Y76 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/_zz_ram_port1_reg[39]/D
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock mlkem_clk_clk_pll rise edge)
|
|
0.000 0.000 r
|
|
K21 0.000 0.000 r clk (IN)
|
|
net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1
|
|
K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O
|
|
net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll
|
|
PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2)
|
|
-2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2
|
|
net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll
|
|
BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout3_buf/O
|
|
net (fo=26129, routed) 0.951 -0.357 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/mlkem_clk
|
|
SLICE_X27Y76 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/_zz_ram_port1_reg[39]/C
|
|
clock pessimism 0.099 -0.258
|
|
clock uncertainty 0.197 -0.062
|
|
SLICE_X27Y76 FDRE (Hold_fdre_C_D) 0.066 0.004 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/_zz_ram_port1_reg[39]
|
|
-------------------------------------------------------------------
|
|
required time -0.004
|
|
arrival time 0.141
|
|
-------------------------------------------------------------------
|
|
slack 0.137
|
|
|
|
Slack (MET) : 0.137ns (arrival time - required time)
|
|
Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_42_47/RAMA/CLK
|
|
(rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/_zz_ram_port1_reg[42]/D
|
|
(rising edge-triggered cell FDRE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns})
|
|
Path Group: mlkem_clk_clk_pll
|
|
Path Type: Hold (Min at Fast Process Corner)
|
|
Requirement: 0.000ns (mlkem_clk_clk_pll rise@0.000ns - sys_clk rise@0.000ns)
|
|
Data Path Delay: 0.666ns (logic 0.492ns (73.905%) route 0.174ns (26.095%))
|
|
Logic Levels: 0
|
|
Clock Path Skew: 0.326ns (DCD - SCD - CPR)
|
|
Destination Clock Delay (DCD): -0.355ns
|
|
Source Clock Delay (SCD): -0.582ns
|
|
Clock Pessimism Removal (CPR): -0.099ns
|
|
Clock Uncertainty: 0.197ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Discrete Jitter (DJ): 0.136ns
|
|
Phase Error (PE): 0.120ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock sys_clk rise edge) 0.000 0.000 r
|
|
K21 0.000 0.000 r clk (IN)
|
|
net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1
|
|
K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O
|
|
net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll
|
|
PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1)
|
|
-2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1
|
|
net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll
|
|
BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O
|
|
net (fo=10004, routed) 0.680 -0.582 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_42_47/WCLK
|
|
SLICE_X22Y73 RAMD32 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_42_47/RAMA/CLK
|
|
------------------------------------------------------------------- -------------------
|
|
SLICE_X22Y73 RAMD32 (Prop_ramd32_CLK_O)
|
|
0.492 -0.090 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_42_47/RAMA/O
|
|
net (fo=1, routed) 0.174 0.083 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/_zz_ram_port10__2[42]
|
|
SLICE_X23Y73 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/_zz_ram_port1_reg[42]/D
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock mlkem_clk_clk_pll rise edge)
|
|
0.000 0.000 r
|
|
K21 0.000 0.000 r clk (IN)
|
|
net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1
|
|
K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O
|
|
net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll
|
|
PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2)
|
|
-2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2
|
|
net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll
|
|
BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout3_buf/O
|
|
net (fo=26129, routed) 0.953 -0.355 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/mlkem_clk
|
|
SLICE_X23Y73 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/_zz_ram_port1_reg[42]/C
|
|
clock pessimism 0.099 -0.256
|
|
clock uncertainty 0.197 -0.060
|
|
SLICE_X23Y73 FDRE (Hold_fdre_C_D) 0.006 -0.054 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/_zz_ram_port1_reg[42]
|
|
-------------------------------------------------------------------
|
|
required time 0.054
|
|
arrival time 0.083
|
|
-------------------------------------------------------------------
|
|
slack 0.137
|
|
|
|
Slack (MET) : 0.139ns (arrival time - required time)
|
|
Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_36_41/RAMA/CLK
|
|
(rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/_zz_ram_port1_reg[36]/D
|
|
(rising edge-triggered cell FDRE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns})
|
|
Path Group: mlkem_clk_clk_pll
|
|
Path Type: Hold (Min at Fast Process Corner)
|
|
Requirement: 0.000ns (mlkem_clk_clk_pll rise@0.000ns - sys_clk rise@0.000ns)
|
|
Data Path Delay: 0.668ns (logic 0.492ns (73.684%) route 0.176ns (26.316%))
|
|
Logic Levels: 0
|
|
Clock Path Skew: 0.327ns (DCD - SCD - CPR)
|
|
Destination Clock Delay (DCD): -0.355ns
|
|
Source Clock Delay (SCD): -0.583ns
|
|
Clock Pessimism Removal (CPR): -0.099ns
|
|
Clock Uncertainty: 0.197ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Discrete Jitter (DJ): 0.136ns
|
|
Phase Error (PE): 0.120ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock sys_clk rise edge) 0.000 0.000 r
|
|
K21 0.000 0.000 r clk (IN)
|
|
net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1
|
|
K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O
|
|
net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll
|
|
PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1)
|
|
-2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1
|
|
net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll
|
|
BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O
|
|
net (fo=10004, routed) 0.679 -0.583 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_36_41/WCLK
|
|
SLICE_X22Y75 RAMD32 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_36_41/RAMA/CLK
|
|
------------------------------------------------------------------- -------------------
|
|
SLICE_X22Y75 RAMD32 (Prop_ramd32_CLK_O)
|
|
0.492 -0.091 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_36_41/RAMA/O
|
|
net (fo=1, routed) 0.176 0.084 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/_zz_ram_port10__2[36]
|
|
SLICE_X23Y76 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/_zz_ram_port1_reg[36]/D
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock mlkem_clk_clk_pll rise edge)
|
|
0.000 0.000 r
|
|
K21 0.000 0.000 r clk (IN)
|
|
net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1
|
|
K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O
|
|
net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll
|
|
PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2)
|
|
-2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2
|
|
net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll
|
|
BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout3_buf/O
|
|
net (fo=26129, routed) 0.953 -0.355 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/mlkem_clk
|
|
SLICE_X23Y76 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/_zz_ram_port1_reg[36]/C
|
|
clock pessimism 0.099 -0.256
|
|
clock uncertainty 0.197 -0.060
|
|
SLICE_X23Y76 FDRE (Hold_fdre_C_D) 0.005 -0.055 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/_zz_ram_port1_reg[36]
|
|
-------------------------------------------------------------------
|
|
required time 0.055
|
|
arrival time 0.084
|
|
-------------------------------------------------------------------
|
|
slack 0.139
|
|
|
|
Slack (MET) : 0.143ns (arrival time - required time)
|
|
Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_36_41/RAMC_D1/CLK
|
|
(rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/_zz_ram_port1_reg[41]/D
|
|
(rising edge-triggered cell FDRE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns})
|
|
Path Group: mlkem_clk_clk_pll
|
|
Path Type: Hold (Min at Fast Process Corner)
|
|
Requirement: 0.000ns (mlkem_clk_clk_pll rise@0.000ns - sys_clk rise@0.000ns)
|
|
Data Path Delay: 0.734ns (logic 0.386ns (52.563%) route 0.348ns (47.437%))
|
|
Logic Levels: 0
|
|
Clock Path Skew: 0.325ns (DCD - SCD - CPR)
|
|
Destination Clock Delay (DCD): -0.357ns
|
|
Source Clock Delay (SCD): -0.583ns
|
|
Clock Pessimism Removal (CPR): -0.099ns
|
|
Clock Uncertainty: 0.197ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Discrete Jitter (DJ): 0.136ns
|
|
Phase Error (PE): 0.120ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock sys_clk rise edge) 0.000 0.000 r
|
|
K21 0.000 0.000 r clk (IN)
|
|
net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1
|
|
K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O
|
|
net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll
|
|
PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1)
|
|
-2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1
|
|
net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll
|
|
BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O
|
|
net (fo=10004, routed) 0.679 -0.583 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_36_41/WCLK
|
|
SLICE_X22Y75 RAMD32 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_36_41/RAMC_D1/CLK
|
|
------------------------------------------------------------------- -------------------
|
|
SLICE_X22Y75 RAMD32 (Prop_ramd32_CLK_O)
|
|
0.386 -0.197 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_36_41/RAMC_D1/O
|
|
net (fo=1, routed) 0.348 0.151 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/_zz_ram_port10__2[41]
|
|
SLICE_X24Y76 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/_zz_ram_port1_reg[41]/D
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock mlkem_clk_clk_pll rise edge)
|
|
0.000 0.000 r
|
|
K21 0.000 0.000 r clk (IN)
|
|
net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1
|
|
K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O
|
|
net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll
|
|
PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2)
|
|
-2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2
|
|
net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll
|
|
BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout3_buf/O
|
|
net (fo=26129, routed) 0.951 -0.357 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/mlkem_clk
|
|
SLICE_X24Y76 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/_zz_ram_port1_reg[41]/C
|
|
clock pessimism 0.099 -0.258
|
|
clock uncertainty 0.197 -0.062
|
|
SLICE_X24Y76 FDRE (Hold_fdre_C_D) 0.070 0.008 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/_zz_ram_port1_reg[41]
|
|
-------------------------------------------------------------------
|
|
required time -0.008
|
|
arrival time 0.151
|
|
-------------------------------------------------------------------
|
|
slack 0.143
|
|
|
|
Slack (MET) : 0.148ns (arrival time - required time)
|
|
Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_30_35/RAMC_D1/CLK
|
|
(rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/_zz_ram_port1_reg[35]/D
|
|
(rising edge-triggered cell FDRE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns})
|
|
Path Group: mlkem_clk_clk_pll
|
|
Path Type: Hold (Min at Fast Process Corner)
|
|
Requirement: 0.000ns (mlkem_clk_clk_pll rise@0.000ns - sys_clk rise@0.000ns)
|
|
Data Path Delay: 0.741ns (logic 0.386ns (52.125%) route 0.355ns (47.875%))
|
|
Logic Levels: 0
|
|
Clock Path Skew: 0.324ns (DCD - SCD - CPR)
|
|
Destination Clock Delay (DCD): -0.355ns
|
|
Source Clock Delay (SCD): -0.580ns
|
|
Clock Pessimism Removal (CPR): -0.099ns
|
|
Clock Uncertainty: 0.197ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Discrete Jitter (DJ): 0.136ns
|
|
Phase Error (PE): 0.120ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock sys_clk rise edge) 0.000 0.000 r
|
|
K21 0.000 0.000 r clk (IN)
|
|
net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1
|
|
K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O
|
|
net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll
|
|
PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1)
|
|
-2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1
|
|
net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll
|
|
BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O
|
|
net (fo=10004, routed) 0.682 -0.580 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_30_35/WCLK
|
|
SLICE_X18Y74 RAMD32 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_30_35/RAMC_D1/CLK
|
|
------------------------------------------------------------------- -------------------
|
|
SLICE_X18Y74 RAMD32 (Prop_ramd32_CLK_O)
|
|
0.386 -0.194 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_30_35/RAMC_D1/O
|
|
net (fo=1, routed) 0.355 0.160 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/_zz_ram_port10__2[35]
|
|
SLICE_X23Y76 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/_zz_ram_port1_reg[35]/D
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock mlkem_clk_clk_pll rise edge)
|
|
0.000 0.000 r
|
|
K21 0.000 0.000 r clk (IN)
|
|
net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1
|
|
K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O
|
|
net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll
|
|
PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2)
|
|
-2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2
|
|
net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll
|
|
BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout3_buf/O
|
|
net (fo=26129, routed) 0.953 -0.355 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/mlkem_clk
|
|
SLICE_X23Y76 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/_zz_ram_port1_reg[35]/C
|
|
clock pessimism 0.099 -0.256
|
|
clock uncertainty 0.197 -0.060
|
|
SLICE_X23Y76 FDRE (Hold_fdre_C_D) 0.072 0.012 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/_zz_ram_port1_reg[35]
|
|
-------------------------------------------------------------------
|
|
required time -0.012
|
|
arrival time 0.160
|
|
-------------------------------------------------------------------
|
|
slack 0.148
|
|
|
|
Slack (MET) : 0.153ns (arrival time - required time)
|
|
Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_30_35/RAMB/CLK
|
|
(rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/_zz_ram_port1_reg[32]/D
|
|
(rising edge-triggered cell FDRE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns})
|
|
Path Group: mlkem_clk_clk_pll
|
|
Path Type: Hold (Min at Fast Process Corner)
|
|
Requirement: 0.000ns (mlkem_clk_clk_pll rise@0.000ns - sys_clk rise@0.000ns)
|
|
Data Path Delay: 0.670ns (logic 0.394ns (58.792%) route 0.276ns (41.208%))
|
|
Logic Levels: 0
|
|
Clock Path Skew: 0.324ns (DCD - SCD - CPR)
|
|
Destination Clock Delay (DCD): -0.355ns
|
|
Source Clock Delay (SCD): -0.580ns
|
|
Clock Pessimism Removal (CPR): -0.099ns
|
|
Clock Uncertainty: 0.197ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Discrete Jitter (DJ): 0.136ns
|
|
Phase Error (PE): 0.120ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock sys_clk rise edge) 0.000 0.000 r
|
|
K21 0.000 0.000 r clk (IN)
|
|
net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1
|
|
K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O
|
|
net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll
|
|
PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1)
|
|
-2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1
|
|
net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll
|
|
BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O
|
|
net (fo=10004, routed) 0.682 -0.580 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_30_35/WCLK
|
|
SLICE_X18Y74 RAMD32 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_30_35/RAMB/CLK
|
|
------------------------------------------------------------------- -------------------
|
|
SLICE_X18Y74 RAMD32 (Prop_ramd32_CLK_O)
|
|
0.394 -0.186 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_30_35/RAMB/O
|
|
net (fo=1, routed) 0.276 0.090 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/_zz_ram_port10__2[32]
|
|
SLICE_X23Y76 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/_zz_ram_port1_reg[32]/D
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock mlkem_clk_clk_pll rise edge)
|
|
0.000 0.000 r
|
|
K21 0.000 0.000 r clk (IN)
|
|
net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1
|
|
K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O
|
|
net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll
|
|
PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2)
|
|
-2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2
|
|
net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll
|
|
BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout3_buf/O
|
|
net (fo=26129, routed) 0.953 -0.355 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/mlkem_clk
|
|
SLICE_X23Y76 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/_zz_ram_port1_reg[32]/C
|
|
clock pessimism 0.099 -0.256
|
|
clock uncertainty 0.197 -0.060
|
|
SLICE_X23Y76 FDRE (Hold_fdre_C_D) -0.003 -0.063 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/_zz_ram_port1_reg[32]
|
|
-------------------------------------------------------------------
|
|
required time 0.063
|
|
arrival time 0.090
|
|
-------------------------------------------------------------------
|
|
slack 0.153
|
|
|
|
Slack (MET) : 0.157ns (arrival time - required time)
|
|
Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_36_41/RAMC/CLK
|
|
(rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/_zz_ram_port1_reg[40]/D
|
|
(rising edge-triggered cell FDRE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns})
|
|
Path Group: mlkem_clk_clk_pll
|
|
Path Type: Hold (Min at Fast Process Corner)
|
|
Requirement: 0.000ns (mlkem_clk_clk_pll rise@0.000ns - sys_clk rise@0.000ns)
|
|
Data Path Delay: 0.681ns (logic 0.390ns (57.280%) route 0.291ns (42.720%))
|
|
Logic Levels: 0
|
|
Clock Path Skew: 0.325ns (DCD - SCD - CPR)
|
|
Destination Clock Delay (DCD): -0.357ns
|
|
Source Clock Delay (SCD): -0.583ns
|
|
Clock Pessimism Removal (CPR): -0.099ns
|
|
Clock Uncertainty: 0.197ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Discrete Jitter (DJ): 0.136ns
|
|
Phase Error (PE): 0.120ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock sys_clk rise edge) 0.000 0.000 r
|
|
K21 0.000 0.000 r clk (IN)
|
|
net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1
|
|
K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O
|
|
net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll
|
|
PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1)
|
|
-2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1
|
|
net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll
|
|
BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O
|
|
net (fo=10004, routed) 0.679 -0.583 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_36_41/WCLK
|
|
SLICE_X22Y75 RAMD32 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_36_41/RAMC/CLK
|
|
------------------------------------------------------------------- -------------------
|
|
SLICE_X22Y75 RAMD32 (Prop_ramd32_CLK_O)
|
|
0.390 -0.193 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_36_41/RAMC/O
|
|
net (fo=1, routed) 0.291 0.097 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/_zz_ram_port10__2[40]
|
|
SLICE_X27Y76 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/_zz_ram_port1_reg[40]/D
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock mlkem_clk_clk_pll rise edge)
|
|
0.000 0.000 r
|
|
K21 0.000 0.000 r clk (IN)
|
|
net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1
|
|
K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O
|
|
net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll
|
|
PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2)
|
|
-2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2
|
|
net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll
|
|
BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout3_buf/O
|
|
net (fo=26129, routed) 0.951 -0.357 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/mlkem_clk
|
|
SLICE_X27Y76 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/_zz_ram_port1_reg[40]/C
|
|
clock pessimism 0.099 -0.258
|
|
clock uncertainty 0.197 -0.062
|
|
SLICE_X27Y76 FDRE (Hold_fdre_C_D) 0.002 -0.060 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/_zz_ram_port1_reg[40]
|
|
-------------------------------------------------------------------
|
|
required time 0.060
|
|
arrival time 0.097
|
|
-------------------------------------------------------------------
|
|
slack 0.157
|
|
|
|
Slack (MET) : 0.167ns (arrival time - required time)
|
|
Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/popCC_ptrToPush_reg[1]/C
|
|
(rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/popToPushGray_buffercc/buffers_0_reg[1]/D
|
|
(rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns})
|
|
Path Group: mlkem_clk_clk_pll
|
|
Path Type: Hold (Min at Fast Process Corner)
|
|
Requirement: 0.000ns (mlkem_clk_clk_pll rise@0.000ns - sys_clk rise@0.000ns)
|
|
Data Path Delay: 0.767ns (logic 0.164ns (21.391%) route 0.603ns (78.609%))
|
|
Logic Levels: 0
|
|
Clock Path Skew: 0.327ns (DCD - SCD - CPR)
|
|
Destination Clock Delay (DCD): -0.342ns
|
|
Source Clock Delay (SCD): -0.570ns
|
|
Clock Pessimism Removal (CPR): -0.099ns
|
|
Clock Uncertainty: 0.197ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Discrete Jitter (DJ): 0.136ns
|
|
Phase Error (PE): 0.120ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock sys_clk rise edge) 0.000 0.000 r
|
|
K21 0.000 0.000 r clk (IN)
|
|
net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1
|
|
K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O
|
|
net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll
|
|
PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1)
|
|
-2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1
|
|
net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll
|
|
BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O
|
|
net (fo=10004, routed) 0.692 -0.570 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/sys_clk
|
|
SLICE_X14Y87 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/popCC_ptrToPush_reg[1]/C
|
|
------------------------------------------------------------------- -------------------
|
|
SLICE_X14Y87 FDCE (Prop_fdce_C_Q) 0.164 -0.406 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/popCC_ptrToPush_reg[1]/Q
|
|
net (fo=1, routed) 0.603 0.196 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/popToPushGray_buffercc/Q[1]
|
|
SLICE_X14Y86 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/popToPushGray_buffercc/buffers_0_reg[1]/D
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock mlkem_clk_clk_pll rise edge)
|
|
0.000 0.000 r
|
|
K21 0.000 0.000 r clk (IN)
|
|
net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1
|
|
K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O
|
|
net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll
|
|
PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2)
|
|
-2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2
|
|
net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll
|
|
BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout3_buf/O
|
|
net (fo=26129, routed) 0.966 -0.342 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/popToPushGray_buffercc/mlkem_clk
|
|
SLICE_X14Y86 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/popToPushGray_buffercc/buffers_0_reg[1]/C
|
|
clock pessimism 0.099 -0.243
|
|
clock uncertainty 0.197 -0.047
|
|
SLICE_X14Y86 FDCE (Hold_fdce_C_D) 0.076 0.029 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/popToPushGray_buffercc/buffers_0_reg[1]
|
|
-------------------------------------------------------------------
|
|
required time -0.029
|
|
arrival time 0.196
|
|
-------------------------------------------------------------------
|
|
slack 0.167
|
|
|
|
Slack (MET) : 0.170ns (arrival time - required time)
|
|
Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/popCC_ptrToPush_reg[3]/C
|
|
(rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/popToPushGray_buffercc/buffers_0_reg[3]/D
|
|
(rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns})
|
|
Path Group: mlkem_clk_clk_pll
|
|
Path Type: Hold (Min at Fast Process Corner)
|
|
Requirement: 0.000ns (mlkem_clk_clk_pll rise@0.000ns - sys_clk rise@0.000ns)
|
|
Data Path Delay: 0.754ns (logic 0.141ns (18.697%) route 0.613ns (81.303%))
|
|
Logic Levels: 0
|
|
Clock Path Skew: 0.328ns (DCD - SCD - CPR)
|
|
Destination Clock Delay (DCD): -0.342ns
|
|
Source Clock Delay (SCD): -0.571ns
|
|
Clock Pessimism Removal (CPR): -0.099ns
|
|
Clock Uncertainty: 0.197ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Discrete Jitter (DJ): 0.136ns
|
|
Phase Error (PE): 0.120ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock sys_clk rise edge) 0.000 0.000 r
|
|
K21 0.000 0.000 r clk (IN)
|
|
net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1
|
|
K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O
|
|
net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll
|
|
PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1)
|
|
-2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1
|
|
net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll
|
|
BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O
|
|
net (fo=10004, routed) 0.691 -0.571 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/sys_clk
|
|
SLICE_X17Y86 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/popCC_ptrToPush_reg[3]/C
|
|
------------------------------------------------------------------- -------------------
|
|
SLICE_X17Y86 FDCE (Prop_fdce_C_Q) 0.141 -0.430 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/popCC_ptrToPush_reg[3]/Q
|
|
net (fo=1, routed) 0.613 0.183 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/popToPushGray_buffercc/Q[3]
|
|
SLICE_X16Y86 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/popToPushGray_buffercc/buffers_0_reg[3]/D
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock mlkem_clk_clk_pll rise edge)
|
|
0.000 0.000 r
|
|
K21 0.000 0.000 r clk (IN)
|
|
net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1
|
|
K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O
|
|
net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll
|
|
PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2)
|
|
-2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2
|
|
net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll
|
|
BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout3_buf/O
|
|
net (fo=26129, routed) 0.966 -0.342 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/popToPushGray_buffercc/mlkem_clk
|
|
SLICE_X16Y86 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/popToPushGray_buffercc/buffers_0_reg[3]/C
|
|
clock pessimism 0.099 -0.243
|
|
clock uncertainty 0.197 -0.047
|
|
SLICE_X16Y86 FDCE (Hold_fdce_C_D) 0.059 0.012 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/popToPushGray_buffercc/buffers_0_reg[3]
|
|
-------------------------------------------------------------------
|
|
required time -0.012
|
|
arrival time 0.183
|
|
-------------------------------------------------------------------
|
|
slack 0.170
|
|
|
|
Slack (MET) : 0.182ns (arrival time - required time)
|
|
Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/ram_reg_0_3_48_53/RAMA_D1/CLK
|
|
(rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/_zz_ram_port1_reg[49]/D
|
|
(rising edge-triggered cell FDRE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns})
|
|
Path Group: mlkem_clk_clk_pll
|
|
Path Type: Hold (Min at Fast Process Corner)
|
|
Requirement: 0.000ns (mlkem_clk_clk_pll rise@0.000ns - sys_clk rise@0.000ns)
|
|
Data Path Delay: 0.775ns (logic 0.478ns (61.697%) route 0.297ns (38.303%))
|
|
Logic Levels: 0
|
|
Clock Path Skew: 0.325ns (DCD - SCD - CPR)
|
|
Destination Clock Delay (DCD): -0.353ns
|
|
Source Clock Delay (SCD): -0.579ns
|
|
Clock Pessimism Removal (CPR): -0.099ns
|
|
Clock Uncertainty: 0.197ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Discrete Jitter (DJ): 0.136ns
|
|
Phase Error (PE): 0.120ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock sys_clk rise edge) 0.000 0.000 r
|
|
K21 0.000 0.000 r clk (IN)
|
|
net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1
|
|
K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O
|
|
net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll
|
|
PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1)
|
|
-2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1
|
|
net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll
|
|
BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O
|
|
net (fo=10004, routed) 0.683 -0.579 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/ram_reg_0_3_48_53/WCLK
|
|
SLICE_X22Y70 RAMD32 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/ram_reg_0_3_48_53/RAMA_D1/CLK
|
|
------------------------------------------------------------------- -------------------
|
|
SLICE_X22Y70 RAMD32 (Prop_ramd32_CLK_O)
|
|
0.478 -0.101 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/ram_reg_0_3_48_53/RAMA_D1/O
|
|
net (fo=1, routed) 0.297 0.195 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/_zz_ram_port10[49]
|
|
SLICE_X25Y70 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/_zz_ram_port1_reg[49]/D
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock mlkem_clk_clk_pll rise edge)
|
|
0.000 0.000 r
|
|
K21 0.000 0.000 r clk (IN)
|
|
net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1
|
|
K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O
|
|
net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll
|
|
PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2)
|
|
-2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2
|
|
net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll
|
|
BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout3_buf/O
|
|
net (fo=26129, routed) 0.955 -0.353 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/mlkem_clk
|
|
SLICE_X25Y70 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/_zz_ram_port1_reg[49]/C
|
|
clock pessimism 0.099 -0.254
|
|
clock uncertainty 0.197 -0.058
|
|
SLICE_X25Y70 FDRE (Hold_fdre_C_D) 0.071 0.013 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/_zz_ram_port1_reg[49]
|
|
-------------------------------------------------------------------
|
|
required time -0.013
|
|
arrival time 0.195
|
|
-------------------------------------------------------------------
|
|
slack 0.182
|
|
|
|
Slack (MET) : 0.194ns (arrival time - required time)
|
|
Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_42_47/RAMB/CLK
|
|
(rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/_zz_ram_port1_reg[44]/D
|
|
(rising edge-triggered cell FDRE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns})
|
|
Path Group: mlkem_clk_clk_pll
|
|
Path Type: Hold (Min at Fast Process Corner)
|
|
Requirement: 0.000ns (mlkem_clk_clk_pll rise@0.000ns - sys_clk rise@0.000ns)
|
|
Data Path Delay: 0.714ns (logic 0.394ns (55.191%) route 0.320ns (44.809%))
|
|
Logic Levels: 0
|
|
Clock Path Skew: 0.324ns (DCD - SCD - CPR)
|
|
Destination Clock Delay (DCD): -0.357ns
|
|
Source Clock Delay (SCD): -0.582ns
|
|
Clock Pessimism Removal (CPR): -0.099ns
|
|
Clock Uncertainty: 0.197ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Discrete Jitter (DJ): 0.136ns
|
|
Phase Error (PE): 0.120ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock sys_clk rise edge) 0.000 0.000 r
|
|
K21 0.000 0.000 r clk (IN)
|
|
net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1
|
|
K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O
|
|
net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll
|
|
PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1)
|
|
-2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1
|
|
net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll
|
|
BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O
|
|
net (fo=10004, routed) 0.680 -0.582 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_42_47/WCLK
|
|
SLICE_X22Y73 RAMD32 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_42_47/RAMB/CLK
|
|
------------------------------------------------------------------- -------------------
|
|
SLICE_X22Y73 RAMD32 (Prop_ramd32_CLK_O)
|
|
0.394 -0.188 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_42_47/RAMB/O
|
|
net (fo=1, routed) 0.320 0.132 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/_zz_ram_port10__2[44]
|
|
SLICE_X27Y76 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/_zz_ram_port1_reg[44]/D
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock mlkem_clk_clk_pll rise edge)
|
|
0.000 0.000 r
|
|
K21 0.000 0.000 r clk (IN)
|
|
net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1
|
|
K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O
|
|
net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll
|
|
PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2)
|
|
-2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2
|
|
net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll
|
|
BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout3_buf/O
|
|
net (fo=26129, routed) 0.951 -0.357 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/mlkem_clk
|
|
SLICE_X27Y76 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/_zz_ram_port1_reg[44]/C
|
|
clock pessimism 0.099 -0.258
|
|
clock uncertainty 0.197 -0.062
|
|
SLICE_X27Y76 FDRE (Hold_fdre_C_D) -0.001 -0.063 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/_zz_ram_port1_reg[44]
|
|
-------------------------------------------------------------------
|
|
required time 0.063
|
|
arrival time 0.132
|
|
-------------------------------------------------------------------
|
|
slack 0.194
|
|
|
|
Slack (MET) : 0.195ns (arrival time - required time)
|
|
Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/ram_reg_0_3_30_35/RAMB_D1/CLK
|
|
(rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/_zz_ram_port1_reg[33]/D
|
|
(rising edge-triggered cell FDRE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns})
|
|
Path Group: mlkem_clk_clk_pll
|
|
Path Type: Hold (Min at Fast Process Corner)
|
|
Requirement: 0.000ns (mlkem_clk_clk_pll rise@0.000ns - sys_clk rise@0.000ns)
|
|
Data Path Delay: 0.765ns (logic 0.388ns (50.735%) route 0.377ns (49.265%))
|
|
Logic Levels: 0
|
|
Clock Path Skew: 0.326ns (DCD - SCD - CPR)
|
|
Destination Clock Delay (DCD): -0.353ns
|
|
Source Clock Delay (SCD): -0.580ns
|
|
Clock Pessimism Removal (CPR): -0.099ns
|
|
Clock Uncertainty: 0.197ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Discrete Jitter (DJ): 0.136ns
|
|
Phase Error (PE): 0.120ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock sys_clk rise edge) 0.000 0.000 r
|
|
K21 0.000 0.000 r clk (IN)
|
|
net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1
|
|
K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O
|
|
net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll
|
|
PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1)
|
|
-2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1
|
|
net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll
|
|
BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O
|
|
net (fo=10004, routed) 0.682 -0.580 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/ram_reg_0_3_30_35/WCLK
|
|
SLICE_X22Y71 RAMD32 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/ram_reg_0_3_30_35/RAMB_D1/CLK
|
|
------------------------------------------------------------------- -------------------
|
|
SLICE_X22Y71 RAMD32 (Prop_ramd32_CLK_O)
|
|
0.388 -0.192 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/ram_reg_0_3_30_35/RAMB_D1/O
|
|
net (fo=1, routed) 0.377 0.184 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/_zz_ram_port10[33]
|
|
SLICE_X25Y70 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/_zz_ram_port1_reg[33]/D
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock mlkem_clk_clk_pll rise edge)
|
|
0.000 0.000 r
|
|
K21 0.000 0.000 r clk (IN)
|
|
net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1
|
|
K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O
|
|
net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll
|
|
PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2)
|
|
-2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2
|
|
net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll
|
|
BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout3_buf/O
|
|
net (fo=26129, routed) 0.955 -0.353 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/mlkem_clk
|
|
SLICE_X25Y70 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/_zz_ram_port1_reg[33]/C
|
|
clock pessimism 0.099 -0.254
|
|
clock uncertainty 0.197 -0.058
|
|
SLICE_X25Y70 FDRE (Hold_fdre_C_D) 0.047 -0.011 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/_zz_ram_port1_reg[33]
|
|
-------------------------------------------------------------------
|
|
required time 0.011
|
|
arrival time 0.184
|
|
-------------------------------------------------------------------
|
|
slack 0.195
|
|
|
|
Slack (MET) : 0.198ns (arrival time - required time)
|
|
Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/pushCC_pushPtrGray_reg[1]/C
|
|
(rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/pushToPopGray_buffercc/buffers_0_reg[1]/D
|
|
(rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns})
|
|
Path Group: mlkem_clk_clk_pll
|
|
Path Type: Hold (Min at Fast Process Corner)
|
|
Requirement: 0.000ns (mlkem_clk_clk_pll rise@0.000ns - sys_clk rise@0.000ns)
|
|
Data Path Delay: 0.768ns (logic 0.141ns (18.369%) route 0.627ns (81.631%))
|
|
Logic Levels: 0
|
|
Clock Path Skew: 0.327ns (DCD - SCD - CPR)
|
|
Destination Clock Delay (DCD): -0.388ns
|
|
Source Clock Delay (SCD): -0.616ns
|
|
Clock Pessimism Removal (CPR): -0.099ns
|
|
Clock Uncertainty: 0.197ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Discrete Jitter (DJ): 0.136ns
|
|
Phase Error (PE): 0.120ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock sys_clk rise edge) 0.000 0.000 r
|
|
K21 0.000 0.000 r clk (IN)
|
|
net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1
|
|
K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O
|
|
net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll
|
|
PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1)
|
|
-2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1
|
|
net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll
|
|
BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O
|
|
net (fo=10004, routed) 0.646 -0.616 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/sys_clk
|
|
SLICE_X111Y75 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/pushCC_pushPtrGray_reg[1]/C
|
|
------------------------------------------------------------------- -------------------
|
|
SLICE_X111Y75 FDCE (Prop_fdce_C_Q) 0.141 -0.475 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/pushCC_pushPtrGray_reg[1]/Q
|
|
net (fo=2, routed) 0.627 0.151 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/pushToPopGray_buffercc/D[1]
|
|
SLICE_X117Y75 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/pushToPopGray_buffercc/buffers_0_reg[1]/D
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock mlkem_clk_clk_pll rise edge)
|
|
0.000 0.000 r
|
|
K21 0.000 0.000 r clk (IN)
|
|
net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1
|
|
K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O
|
|
net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll
|
|
PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2)
|
|
-2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2
|
|
net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll
|
|
BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout3_buf/O
|
|
net (fo=26129, routed) 0.920 -0.388 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/pushToPopGray_buffercc/mlkem_clk
|
|
SLICE_X117Y75 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/pushToPopGray_buffercc/buffers_0_reg[1]/C
|
|
clock pessimism 0.099 -0.289
|
|
clock uncertainty 0.197 -0.093
|
|
SLICE_X117Y75 FDCE (Hold_fdce_C_D) 0.046 -0.047 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/pushToPopGray_buffercc/buffers_0_reg[1]
|
|
-------------------------------------------------------------------
|
|
required time 0.047
|
|
arrival time 0.151
|
|
-------------------------------------------------------------------
|
|
slack 0.198
|
|
|
|
Slack (MET) : 0.205ns (arrival time - required time)
|
|
Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/pushCC_pushPtrGray_reg[0]/C
|
|
(rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/pushToPopGray_buffercc/buffers_0_reg[0]/D
|
|
(rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns})
|
|
Path Group: mlkem_clk_clk_pll
|
|
Path Type: Hold (Min at Fast Process Corner)
|
|
Requirement: 0.000ns (mlkem_clk_clk_pll rise@0.000ns - sys_clk rise@0.000ns)
|
|
Data Path Delay: 0.775ns (logic 0.141ns (18.187%) route 0.634ns (81.813%))
|
|
Logic Levels: 0
|
|
Clock Path Skew: 0.328ns (DCD - SCD - CPR)
|
|
Destination Clock Delay (DCD): -0.353ns
|
|
Source Clock Delay (SCD): -0.582ns
|
|
Clock Pessimism Removal (CPR): -0.099ns
|
|
Clock Uncertainty: 0.197ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Discrete Jitter (DJ): 0.136ns
|
|
Phase Error (PE): 0.120ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock sys_clk rise edge) 0.000 0.000 r
|
|
K21 0.000 0.000 r clk (IN)
|
|
net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1
|
|
K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O
|
|
net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll
|
|
PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1)
|
|
-2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1
|
|
net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll
|
|
BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O
|
|
net (fo=10004, routed) 0.680 -0.582 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/sys_clk
|
|
SLICE_X27Y77 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/pushCC_pushPtrGray_reg[0]/C
|
|
------------------------------------------------------------------- -------------------
|
|
SLICE_X27Y77 FDCE (Prop_fdce_C_Q) 0.141 -0.441 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/pushCC_pushPtrGray_reg[0]/Q
|
|
net (fo=2, routed) 0.634 0.193 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/pushToPopGray_buffercc/Q[0]
|
|
SLICE_X27Y79 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/pushToPopGray_buffercc/buffers_0_reg[0]/D
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock mlkem_clk_clk_pll rise edge)
|
|
0.000 0.000 r
|
|
K21 0.000 0.000 r clk (IN)
|
|
net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1
|
|
K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O
|
|
net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll
|
|
PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2)
|
|
-2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2
|
|
net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll
|
|
BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout3_buf/O
|
|
net (fo=26129, routed) 0.955 -0.353 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/pushToPopGray_buffercc/mlkem_clk
|
|
SLICE_X27Y79 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/pushToPopGray_buffercc/buffers_0_reg[0]/C
|
|
clock pessimism 0.099 -0.254
|
|
clock uncertainty 0.197 -0.058
|
|
SLICE_X27Y79 FDCE (Hold_fdce_C_D) 0.046 -0.012 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/pushToPopGray_buffercc/buffers_0_reg[0]
|
|
-------------------------------------------------------------------
|
|
required time 0.012
|
|
arrival time 0.193
|
|
-------------------------------------------------------------------
|
|
slack 0.205
|
|
|
|
Slack (MET) : 0.220ns (arrival time - required time)
|
|
Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/pushCC_pushPtrGray_reg[3]/C
|
|
(rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/pushToPopGray_buffercc/buffers_0_reg[3]/D
|
|
(rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns})
|
|
Path Group: mlkem_clk_clk_pll
|
|
Path Type: Hold (Min at Fast Process Corner)
|
|
Requirement: 0.000ns (mlkem_clk_clk_pll rise@0.000ns - sys_clk rise@0.000ns)
|
|
Data Path Delay: 0.738ns (logic 0.128ns (17.350%) route 0.610ns (82.650%))
|
|
Logic Levels: 0
|
|
Clock Path Skew: 0.327ns (DCD - SCD - CPR)
|
|
Destination Clock Delay (DCD): -0.388ns
|
|
Source Clock Delay (SCD): -0.616ns
|
|
Clock Pessimism Removal (CPR): -0.099ns
|
|
Clock Uncertainty: 0.197ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Discrete Jitter (DJ): 0.136ns
|
|
Phase Error (PE): 0.120ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock sys_clk rise edge) 0.000 0.000 r
|
|
K21 0.000 0.000 r clk (IN)
|
|
net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1
|
|
K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O
|
|
net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll
|
|
PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1)
|
|
-2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1
|
|
net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll
|
|
BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O
|
|
net (fo=10004, routed) 0.646 -0.616 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/sys_clk
|
|
SLICE_X111Y75 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/pushCC_pushPtrGray_reg[3]/C
|
|
------------------------------------------------------------------- -------------------
|
|
SLICE_X111Y75 FDCE (Prop_fdce_C_Q) 0.128 -0.488 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/pushCC_pushPtrGray_reg[3]/Q
|
|
net (fo=4, routed) 0.610 0.121 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/pushToPopGray_buffercc/D[3]
|
|
SLICE_X117Y75 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/pushToPopGray_buffercc/buffers_0_reg[3]/D
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock mlkem_clk_clk_pll rise edge)
|
|
0.000 0.000 r
|
|
K21 0.000 0.000 r clk (IN)
|
|
net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1
|
|
K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O
|
|
net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll
|
|
PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2)
|
|
-2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2
|
|
net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll
|
|
BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout3_buf/O
|
|
net (fo=26129, routed) 0.920 -0.388 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/pushToPopGray_buffercc/mlkem_clk
|
|
SLICE_X117Y75 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/pushToPopGray_buffercc/buffers_0_reg[3]/C
|
|
clock pessimism 0.099 -0.289
|
|
clock uncertainty 0.197 -0.093
|
|
SLICE_X117Y75 FDCE (Hold_fdce_C_D) -0.006 -0.099 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/pushToPopGray_buffercc/buffers_0_reg[3]
|
|
-------------------------------------------------------------------
|
|
required time 0.099
|
|
arrival time 0.121
|
|
-------------------------------------------------------------------
|
|
slack 0.220
|
|
|
|
Slack (MET) : 0.225ns (arrival time - required time)
|
|
Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_30_35/RAMC/CLK
|
|
(rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/_zz_ram_port1_reg[34]/D
|
|
(rising edge-triggered cell FDRE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns})
|
|
Path Group: mlkem_clk_clk_pll
|
|
Path Type: Hold (Min at Fast Process Corner)
|
|
Requirement: 0.000ns (mlkem_clk_clk_pll rise@0.000ns - sys_clk rise@0.000ns)
|
|
Data Path Delay: 0.748ns (logic 0.390ns (52.130%) route 0.358ns (47.870%))
|
|
Logic Levels: 0
|
|
Clock Path Skew: 0.324ns (DCD - SCD - CPR)
|
|
Destination Clock Delay (DCD): -0.355ns
|
|
Source Clock Delay (SCD): -0.580ns
|
|
Clock Pessimism Removal (CPR): -0.099ns
|
|
Clock Uncertainty: 0.197ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Discrete Jitter (DJ): 0.136ns
|
|
Phase Error (PE): 0.120ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock sys_clk rise edge) 0.000 0.000 r
|
|
K21 0.000 0.000 r clk (IN)
|
|
net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1
|
|
K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O
|
|
net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll
|
|
PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1)
|
|
-2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1
|
|
net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll
|
|
BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O
|
|
net (fo=10004, routed) 0.682 -0.580 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_30_35/WCLK
|
|
SLICE_X18Y74 RAMD32 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_30_35/RAMC/CLK
|
|
------------------------------------------------------------------- -------------------
|
|
SLICE_X18Y74 RAMD32 (Prop_ramd32_CLK_O)
|
|
0.390 -0.190 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_30_35/RAMC/O
|
|
net (fo=1, routed) 0.358 0.168 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/_zz_ram_port10__2[34]
|
|
SLICE_X23Y76 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/_zz_ram_port1_reg[34]/D
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock mlkem_clk_clk_pll rise edge)
|
|
0.000 0.000 r
|
|
K21 0.000 0.000 r clk (IN)
|
|
net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1
|
|
K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O
|
|
net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll
|
|
PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2)
|
|
-2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2
|
|
net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll
|
|
BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout3_buf/O
|
|
net (fo=26129, routed) 0.953 -0.355 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/mlkem_clk
|
|
SLICE_X23Y76 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/_zz_ram_port1_reg[34]/C
|
|
clock pessimism 0.099 -0.256
|
|
clock uncertainty 0.197 -0.060
|
|
SLICE_X23Y76 FDRE (Hold_fdre_C_D) 0.002 -0.058 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/_zz_ram_port1_reg[34]
|
|
-------------------------------------------------------------------
|
|
required time 0.058
|
|
arrival time 0.168
|
|
-------------------------------------------------------------------
|
|
slack 0.225
|
|
|
|
Slack (MET) : 0.227ns (arrival time - required time)
|
|
Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/pushCC_pushPtrGray_reg[0]/C
|
|
(rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/pushToPopGray_buffercc/buffers_0_reg[0]/D
|
|
(rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns})
|
|
Path Group: mlkem_clk_clk_pll
|
|
Path Type: Hold (Min at Fast Process Corner)
|
|
Requirement: 0.000ns (mlkem_clk_clk_pll rise@0.000ns - sys_clk rise@0.000ns)
|
|
Data Path Delay: 0.815ns (logic 0.141ns (17.291%) route 0.674ns (82.709%))
|
|
Logic Levels: 0
|
|
Clock Path Skew: 0.322ns (DCD - SCD - CPR)
|
|
Destination Clock Delay (DCD): -0.361ns
|
|
Source Clock Delay (SCD): -0.584ns
|
|
Clock Pessimism Removal (CPR): -0.099ns
|
|
Clock Uncertainty: 0.197ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Discrete Jitter (DJ): 0.136ns
|
|
Phase Error (PE): 0.120ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock sys_clk rise edge) 0.000 0.000 r
|
|
K21 0.000 0.000 r clk (IN)
|
|
net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1
|
|
K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O
|
|
net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll
|
|
PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1)
|
|
-2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1
|
|
net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll
|
|
BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O
|
|
net (fo=10004, routed) 0.678 -0.584 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/sys_clk
|
|
SLICE_X27Y73 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/pushCC_pushPtrGray_reg[0]/C
|
|
------------------------------------------------------------------- -------------------
|
|
SLICE_X27Y73 FDCE (Prop_fdce_C_Q) 0.141 -0.443 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/pushCC_pushPtrGray_reg[0]/Q
|
|
net (fo=2, routed) 0.674 0.231 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/pushToPopGray_buffercc/Q[0]
|
|
SLICE_X32Y74 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/pushToPopGray_buffercc/buffers_0_reg[0]/D
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock mlkem_clk_clk_pll rise edge)
|
|
0.000 0.000 r
|
|
K21 0.000 0.000 r clk (IN)
|
|
net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1
|
|
K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O
|
|
net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll
|
|
PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2)
|
|
-2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2
|
|
net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll
|
|
BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout3_buf/O
|
|
net (fo=26129, routed) 0.947 -0.361 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/pushToPopGray_buffercc/mlkem_clk
|
|
SLICE_X32Y74 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/pushToPopGray_buffercc/buffers_0_reg[0]/C
|
|
clock pessimism 0.099 -0.262
|
|
clock uncertainty 0.197 -0.066
|
|
SLICE_X32Y74 FDCE (Hold_fdce_C_D) 0.070 0.004 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/pushToPopGray_buffercc/buffers_0_reg[0]
|
|
-------------------------------------------------------------------
|
|
required time -0.004
|
|
arrival time 0.231
|
|
-------------------------------------------------------------------
|
|
slack 0.227
|
|
|
|
Slack (MET) : 0.228ns (arrival time - required time)
|
|
Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/pushCC_pushPtrGray_reg[2]/C
|
|
(rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/pushToPopGray_buffercc/buffers_0_reg[2]/D
|
|
(rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns})
|
|
Path Group: mlkem_clk_clk_pll
|
|
Path Type: Hold (Min at Fast Process Corner)
|
|
Requirement: 0.000ns (mlkem_clk_clk_pll rise@0.000ns - sys_clk rise@0.000ns)
|
|
Data Path Delay: 0.766ns (logic 0.128ns (16.716%) route 0.638ns (83.284%))
|
|
Logic Levels: 0
|
|
Clock Path Skew: 0.323ns (DCD - SCD - CPR)
|
|
Destination Clock Delay (DCD): -0.360ns
|
|
Source Clock Delay (SCD): -0.584ns
|
|
Clock Pessimism Removal (CPR): -0.099ns
|
|
Clock Uncertainty: 0.197ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Discrete Jitter (DJ): 0.136ns
|
|
Phase Error (PE): 0.120ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock sys_clk rise edge) 0.000 0.000 r
|
|
K21 0.000 0.000 r clk (IN)
|
|
net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1
|
|
K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O
|
|
net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll
|
|
PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1)
|
|
-2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1
|
|
net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll
|
|
BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O
|
|
net (fo=10004, routed) 0.678 -0.584 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/sys_clk
|
|
SLICE_X27Y73 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/pushCC_pushPtrGray_reg[2]/C
|
|
------------------------------------------------------------------- -------------------
|
|
SLICE_X27Y73 FDCE (Prop_fdce_C_Q) 0.128 -0.456 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/pushCC_pushPtrGray_reg[2]/Q
|
|
net (fo=4, routed) 0.638 0.181 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/pushToPopGray_buffercc/buffers_0_reg[2]_0
|
|
SLICE_X31Y74 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/pushToPopGray_buffercc/buffers_0_reg[2]/D
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock mlkem_clk_clk_pll rise edge)
|
|
0.000 0.000 r
|
|
K21 0.000 0.000 r clk (IN)
|
|
net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1
|
|
K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O
|
|
net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll
|
|
PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2)
|
|
-2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2
|
|
net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll
|
|
BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout3_buf/O
|
|
net (fo=26129, routed) 0.948 -0.360 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/pushToPopGray_buffercc/mlkem_clk
|
|
SLICE_X31Y74 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/pushToPopGray_buffercc/buffers_0_reg[2]/C
|
|
clock pessimism 0.099 -0.261
|
|
clock uncertainty 0.197 -0.065
|
|
SLICE_X31Y74 FDCE (Hold_fdce_C_D) 0.018 -0.047 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/pushToPopGray_buffercc/buffers_0_reg[2]
|
|
-------------------------------------------------------------------
|
|
required time 0.047
|
|
arrival time 0.181
|
|
-------------------------------------------------------------------
|
|
slack 0.228
|
|
|
|
Slack (MET) : 0.234ns (arrival time - required time)
|
|
Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/popCC_ptrToPush_reg[2]/C
|
|
(rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/popToPushGray_buffercc/buffers_0_reg[2]/D
|
|
(rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns})
|
|
Path Group: mlkem_clk_clk_pll
|
|
Path Type: Hold (Min at Fast Process Corner)
|
|
Requirement: 0.000ns (mlkem_clk_clk_pll rise@0.000ns - sys_clk rise@0.000ns)
|
|
Data Path Delay: 0.781ns (logic 0.148ns (18.960%) route 0.633ns (81.040%))
|
|
Logic Levels: 0
|
|
Clock Path Skew: 0.327ns (DCD - SCD - CPR)
|
|
Destination Clock Delay (DCD): -0.342ns
|
|
Source Clock Delay (SCD): -0.570ns
|
|
Clock Pessimism Removal (CPR): -0.099ns
|
|
Clock Uncertainty: 0.197ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Discrete Jitter (DJ): 0.136ns
|
|
Phase Error (PE): 0.120ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock sys_clk rise edge) 0.000 0.000 r
|
|
K21 0.000 0.000 r clk (IN)
|
|
net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1
|
|
K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O
|
|
net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll
|
|
PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1)
|
|
-2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1
|
|
net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll
|
|
BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O
|
|
net (fo=10004, routed) 0.692 -0.570 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/sys_clk
|
|
SLICE_X14Y87 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/popCC_ptrToPush_reg[2]/C
|
|
------------------------------------------------------------------- -------------------
|
|
SLICE_X14Y87 FDCE (Prop_fdce_C_Q) 0.148 -0.422 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/popCC_ptrToPush_reg[2]/Q
|
|
net (fo=1, routed) 0.633 0.210 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/popToPushGray_buffercc/Q[2]
|
|
SLICE_X14Y86 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/popToPushGray_buffercc/buffers_0_reg[2]/D
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock mlkem_clk_clk_pll rise edge)
|
|
0.000 0.000 r
|
|
K21 0.000 0.000 r clk (IN)
|
|
net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1
|
|
K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O
|
|
net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll
|
|
PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2)
|
|
-2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2
|
|
net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll
|
|
BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout3_buf/O
|
|
net (fo=26129, routed) 0.966 -0.342 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/popToPushGray_buffercc/mlkem_clk
|
|
SLICE_X14Y86 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/popToPushGray_buffercc/buffers_0_reg[2]/C
|
|
clock pessimism 0.099 -0.243
|
|
clock uncertainty 0.197 -0.047
|
|
SLICE_X14Y86 FDCE (Hold_fdce_C_D) 0.023 -0.024 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/popToPushGray_buffercc/buffers_0_reg[2]
|
|
-------------------------------------------------------------------
|
|
required time 0.024
|
|
arrival time 0.210
|
|
-------------------------------------------------------------------
|
|
slack 0.234
|
|
|
|
Slack (MET) : 0.236ns (arrival time - required time)
|
|
Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/ram_reg_0_3_30_35/RAMC_D1/CLK
|
|
(rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/_zz_ram_port1_reg[35]/D
|
|
(rising edge-triggered cell FDRE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns})
|
|
Path Group: mlkem_clk_clk_pll
|
|
Path Type: Hold (Min at Fast Process Corner)
|
|
Requirement: 0.000ns (mlkem_clk_clk_pll rise@0.000ns - sys_clk rise@0.000ns)
|
|
Data Path Delay: 0.831ns (logic 0.386ns (46.464%) route 0.445ns (53.536%))
|
|
Logic Levels: 0
|
|
Clock Path Skew: 0.326ns (DCD - SCD - CPR)
|
|
Destination Clock Delay (DCD): -0.353ns
|
|
Source Clock Delay (SCD): -0.580ns
|
|
Clock Pessimism Removal (CPR): -0.099ns
|
|
Clock Uncertainty: 0.197ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Discrete Jitter (DJ): 0.136ns
|
|
Phase Error (PE): 0.120ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock sys_clk rise edge) 0.000 0.000 r
|
|
K21 0.000 0.000 r clk (IN)
|
|
net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1
|
|
K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O
|
|
net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll
|
|
PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1)
|
|
-2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1
|
|
net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll
|
|
BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O
|
|
net (fo=10004, routed) 0.682 -0.580 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/ram_reg_0_3_30_35/WCLK
|
|
SLICE_X22Y71 RAMD32 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/ram_reg_0_3_30_35/RAMC_D1/CLK
|
|
------------------------------------------------------------------- -------------------
|
|
SLICE_X22Y71 RAMD32 (Prop_ramd32_CLK_O)
|
|
0.386 -0.194 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/ram_reg_0_3_30_35/RAMC_D1/O
|
|
net (fo=1, routed) 0.445 0.250 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/_zz_ram_port10[35]
|
|
SLICE_X25Y70 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/_zz_ram_port1_reg[35]/D
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock mlkem_clk_clk_pll rise edge)
|
|
0.000 0.000 r
|
|
K21 0.000 0.000 r clk (IN)
|
|
net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1
|
|
K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O
|
|
net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll
|
|
PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2)
|
|
-2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2
|
|
net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll
|
|
BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout3_buf/O
|
|
net (fo=26129, routed) 0.955 -0.353 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/mlkem_clk
|
|
SLICE_X25Y70 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/_zz_ram_port1_reg[35]/C
|
|
clock pessimism 0.099 -0.254
|
|
clock uncertainty 0.197 -0.058
|
|
SLICE_X25Y70 FDRE (Hold_fdre_C_D) 0.072 0.014 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/_zz_ram_port1_reg[35]
|
|
-------------------------------------------------------------------
|
|
required time -0.014
|
|
arrival time 0.250
|
|
-------------------------------------------------------------------
|
|
slack 0.236
|
|
|
|
Slack (MET) : 0.238ns (arrival time - required time)
|
|
Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/pushCC_pushPtrGray_reg[1]/C
|
|
(rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/pushToPopGray_buffercc/buffers_0_reg[1]/D
|
|
(rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns})
|
|
Path Group: mlkem_clk_clk_pll
|
|
Path Type: Hold (Min at Fast Process Corner)
|
|
Requirement: 0.000ns (mlkem_clk_clk_pll rise@0.000ns - sys_clk rise@0.000ns)
|
|
Data Path Delay: 0.827ns (logic 0.141ns (17.044%) route 0.686ns (82.956%))
|
|
Logic Levels: 0
|
|
Clock Path Skew: 0.323ns (DCD - SCD - CPR)
|
|
Destination Clock Delay (DCD): -0.360ns
|
|
Source Clock Delay (SCD): -0.584ns
|
|
Clock Pessimism Removal (CPR): -0.099ns
|
|
Clock Uncertainty: 0.197ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Discrete Jitter (DJ): 0.136ns
|
|
Phase Error (PE): 0.120ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock sys_clk rise edge) 0.000 0.000 r
|
|
K21 0.000 0.000 r clk (IN)
|
|
net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1
|
|
K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O
|
|
net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll
|
|
PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1)
|
|
-2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1
|
|
net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll
|
|
BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O
|
|
net (fo=10004, routed) 0.678 -0.584 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/sys_clk
|
|
SLICE_X27Y73 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/pushCC_pushPtrGray_reg[1]/C
|
|
------------------------------------------------------------------- -------------------
|
|
SLICE_X27Y73 FDCE (Prop_fdce_C_Q) 0.141 -0.443 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/pushCC_pushPtrGray_reg[1]/Q
|
|
net (fo=2, routed) 0.686 0.243 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/pushToPopGray_buffercc/Q[1]
|
|
SLICE_X31Y74 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/pushToPopGray_buffercc/buffers_0_reg[1]/D
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock mlkem_clk_clk_pll rise edge)
|
|
0.000 0.000 r
|
|
K21 0.000 0.000 r clk (IN)
|
|
net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1
|
|
K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O
|
|
net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll
|
|
PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2)
|
|
-2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2
|
|
net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll
|
|
BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout3_buf/O
|
|
net (fo=26129, routed) 0.948 -0.360 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/pushToPopGray_buffercc/mlkem_clk
|
|
SLICE_X31Y74 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/pushToPopGray_buffercc/buffers_0_reg[1]/C
|
|
clock pessimism 0.099 -0.261
|
|
clock uncertainty 0.197 -0.065
|
|
SLICE_X31Y74 FDCE (Hold_fdce_C_D) 0.070 0.005 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/pushToPopGray_buffercc/buffers_0_reg[1]
|
|
-------------------------------------------------------------------
|
|
required time -0.005
|
|
arrival time 0.243
|
|
-------------------------------------------------------------------
|
|
slack 0.238
|
|
|
|
Slack (MET) : 0.241ns (arrival time - required time)
|
|
Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_30_35/RAMB_D1/CLK
|
|
(rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/_zz_ram_port1_reg[33]/D
|
|
(rising edge-triggered cell FDRE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns})
|
|
Path Group: mlkem_clk_clk_pll
|
|
Path Type: Hold (Min at Fast Process Corner)
|
|
Requirement: 0.000ns (mlkem_clk_clk_pll rise@0.000ns - sys_clk rise@0.000ns)
|
|
Data Path Delay: 0.823ns (logic 0.388ns (47.171%) route 0.435ns (52.829%))
|
|
Logic Levels: 0
|
|
Clock Path Skew: 0.324ns (DCD - SCD - CPR)
|
|
Destination Clock Delay (DCD): -0.355ns
|
|
Source Clock Delay (SCD): -0.580ns
|
|
Clock Pessimism Removal (CPR): -0.099ns
|
|
Clock Uncertainty: 0.197ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Discrete Jitter (DJ): 0.136ns
|
|
Phase Error (PE): 0.120ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock sys_clk rise edge) 0.000 0.000 r
|
|
K21 0.000 0.000 r clk (IN)
|
|
net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1
|
|
K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O
|
|
net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll
|
|
PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1)
|
|
-2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1
|
|
net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll
|
|
BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O
|
|
net (fo=10004, routed) 0.682 -0.580 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_30_35/WCLK
|
|
SLICE_X18Y74 RAMD32 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_30_35/RAMB_D1/CLK
|
|
------------------------------------------------------------------- -------------------
|
|
SLICE_X18Y74 RAMD32 (Prop_ramd32_CLK_O)
|
|
0.388 -0.192 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_30_35/RAMB_D1/O
|
|
net (fo=1, routed) 0.435 0.242 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/_zz_ram_port10__2[33]
|
|
SLICE_X23Y76 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/_zz_ram_port1_reg[33]/D
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock mlkem_clk_clk_pll rise edge)
|
|
0.000 0.000 r
|
|
K21 0.000 0.000 r clk (IN)
|
|
net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1
|
|
K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O
|
|
net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll
|
|
PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2)
|
|
-2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2
|
|
net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll
|
|
BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout3_buf/O
|
|
net (fo=26129, routed) 0.953 -0.355 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/mlkem_clk
|
|
SLICE_X23Y76 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/_zz_ram_port1_reg[33]/C
|
|
clock pessimism 0.099 -0.256
|
|
clock uncertainty 0.197 -0.060
|
|
SLICE_X23Y76 FDRE (Hold_fdre_C_D) 0.061 0.001 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/_zz_ram_port1_reg[33]
|
|
-------------------------------------------------------------------
|
|
required time -0.001
|
|
arrival time 0.242
|
|
-------------------------------------------------------------------
|
|
slack 0.241
|
|
|
|
Slack (MET) : 0.257ns (arrival time - required time)
|
|
Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/popCC_ptrToPush_reg[1]/C
|
|
(rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/popToPushGray_buffercc/buffers_0_reg[1]/D
|
|
(rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns})
|
|
Path Group: mlkem_clk_clk_pll
|
|
Path Type: Hold (Min at Fast Process Corner)
|
|
Requirement: 0.000ns (mlkem_clk_clk_pll rise@0.000ns - sys_clk rise@0.000ns)
|
|
Data Path Delay: 0.827ns (logic 0.141ns (17.047%) route 0.686ns (82.953%))
|
|
Logic Levels: 0
|
|
Clock Path Skew: 0.326ns (DCD - SCD - CPR)
|
|
Destination Clock Delay (DCD): -0.355ns
|
|
Source Clock Delay (SCD): -0.582ns
|
|
Clock Pessimism Removal (CPR): -0.099ns
|
|
Clock Uncertainty: 0.197ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Discrete Jitter (DJ): 0.136ns
|
|
Phase Error (PE): 0.120ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock sys_clk rise edge) 0.000 0.000 r
|
|
K21 0.000 0.000 r clk (IN)
|
|
net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1
|
|
K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O
|
|
net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll
|
|
PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1)
|
|
-2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1
|
|
net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll
|
|
BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O
|
|
net (fo=10004, routed) 0.680 -0.582 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/sys_clk
|
|
SLICE_X26Y72 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/popCC_ptrToPush_reg[1]/C
|
|
------------------------------------------------------------------- -------------------
|
|
SLICE_X26Y72 FDCE (Prop_fdce_C_Q) 0.141 -0.441 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/popCC_ptrToPush_reg[1]/Q
|
|
net (fo=2, routed) 0.686 0.245 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/popToPushGray_buffercc/D[1]
|
|
SLICE_X27Y72 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/popToPushGray_buffercc/buffers_0_reg[1]/D
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock mlkem_clk_clk_pll rise edge)
|
|
0.000 0.000 r
|
|
K21 0.000 0.000 r clk (IN)
|
|
net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1
|
|
K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O
|
|
net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll
|
|
PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2)
|
|
-2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2
|
|
net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll
|
|
BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout3_buf/O
|
|
net (fo=26129, routed) 0.953 -0.355 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/popToPushGray_buffercc/mlkem_clk
|
|
SLICE_X27Y72 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/popToPushGray_buffercc/buffers_0_reg[1]/C
|
|
clock pessimism 0.099 -0.256
|
|
clock uncertainty 0.197 -0.060
|
|
SLICE_X27Y72 FDCE (Hold_fdce_C_D) 0.047 -0.013 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/popToPushGray_buffercc/buffers_0_reg[1]
|
|
-------------------------------------------------------------------
|
|
required time 0.013
|
|
arrival time 0.245
|
|
-------------------------------------------------------------------
|
|
slack 0.257
|
|
|
|
Slack (MET) : 0.259ns (arrival time - required time)
|
|
Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/popCC_ptrToPush_reg[0]/C
|
|
(rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/popToPushGray_buffercc/buffers_0_reg[0]/D
|
|
(rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns})
|
|
Path Group: mlkem_clk_clk_pll
|
|
Path Type: Hold (Min at Fast Process Corner)
|
|
Requirement: 0.000ns (mlkem_clk_clk_pll rise@0.000ns - sys_clk rise@0.000ns)
|
|
Data Path Delay: 0.857ns (logic 0.164ns (19.129%) route 0.693ns (80.871%))
|
|
Logic Levels: 0
|
|
Clock Path Skew: 0.327ns (DCD - SCD - CPR)
|
|
Destination Clock Delay (DCD): -0.342ns
|
|
Source Clock Delay (SCD): -0.570ns
|
|
Clock Pessimism Removal (CPR): -0.099ns
|
|
Clock Uncertainty: 0.197ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Discrete Jitter (DJ): 0.136ns
|
|
Phase Error (PE): 0.120ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock sys_clk rise edge) 0.000 0.000 r
|
|
K21 0.000 0.000 r clk (IN)
|
|
net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1
|
|
K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O
|
|
net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll
|
|
PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1)
|
|
-2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1
|
|
net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll
|
|
BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O
|
|
net (fo=10004, routed) 0.692 -0.570 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/sys_clk
|
|
SLICE_X14Y87 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/popCC_ptrToPush_reg[0]/C
|
|
------------------------------------------------------------------- -------------------
|
|
SLICE_X14Y87 FDCE (Prop_fdce_C_Q) 0.164 -0.406 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/popCC_ptrToPush_reg[0]/Q
|
|
net (fo=1, routed) 0.693 0.287 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/popToPushGray_buffercc/Q[0]
|
|
SLICE_X14Y86 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/popToPushGray_buffercc/buffers_0_reg[0]/D
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock mlkem_clk_clk_pll rise edge)
|
|
0.000 0.000 r
|
|
K21 0.000 0.000 r clk (IN)
|
|
net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1
|
|
K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O
|
|
net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll
|
|
PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2)
|
|
-2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2
|
|
net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll
|
|
BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout3_buf/O
|
|
net (fo=26129, routed) 0.966 -0.342 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/popToPushGray_buffercc/mlkem_clk
|
|
SLICE_X14Y86 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/popToPushGray_buffercc/buffers_0_reg[0]/C
|
|
clock pessimism 0.099 -0.243
|
|
clock uncertainty 0.197 -0.047
|
|
SLICE_X14Y86 FDCE (Hold_fdce_C_D) 0.075 0.028 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/popToPushGray_buffercc/buffers_0_reg[0]
|
|
-------------------------------------------------------------------
|
|
required time -0.028
|
|
arrival time 0.287
|
|
-------------------------------------------------------------------
|
|
slack 0.259
|
|
|
|
Slack (MET) : 0.259ns (arrival time - required time)
|
|
Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/ram_reg_0_3_36_41/RAMA/CLK
|
|
(rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/_zz_ram_port1_reg[36]/D
|
|
(rising edge-triggered cell FDRE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns})
|
|
Path Group: mlkem_clk_clk_pll
|
|
Path Type: Hold (Min at Fast Process Corner)
|
|
Requirement: 0.000ns (mlkem_clk_clk_pll rise@0.000ns - sys_clk rise@0.000ns)
|
|
Data Path Delay: 0.788ns (logic 0.492ns (62.440%) route 0.296ns (37.560%))
|
|
Logic Levels: 0
|
|
Clock Path Skew: 0.323ns (DCD - SCD - CPR)
|
|
Destination Clock Delay (DCD): -0.353ns
|
|
Source Clock Delay (SCD): -0.577ns
|
|
Clock Pessimism Removal (CPR): -0.099ns
|
|
Clock Uncertainty: 0.197ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Discrete Jitter (DJ): 0.136ns
|
|
Phase Error (PE): 0.120ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock sys_clk rise edge) 0.000 0.000 r
|
|
K21 0.000 0.000 r clk (IN)
|
|
net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1
|
|
K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O
|
|
net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll
|
|
PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1)
|
|
-2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1
|
|
net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll
|
|
BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O
|
|
net (fo=10004, routed) 0.685 -0.577 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/ram_reg_0_3_36_41/WCLK
|
|
SLICE_X22Y68 RAMD32 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/ram_reg_0_3_36_41/RAMA/CLK
|
|
------------------------------------------------------------------- -------------------
|
|
SLICE_X22Y68 RAMD32 (Prop_ramd32_CLK_O)
|
|
0.492 -0.085 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/ram_reg_0_3_36_41/RAMA/O
|
|
net (fo=1, routed) 0.296 0.211 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/_zz_ram_port10[36]
|
|
SLICE_X25Y70 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/_zz_ram_port1_reg[36]/D
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock mlkem_clk_clk_pll rise edge)
|
|
0.000 0.000 r
|
|
K21 0.000 0.000 r clk (IN)
|
|
net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1
|
|
K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O
|
|
net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll
|
|
PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2)
|
|
-2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2
|
|
net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll
|
|
BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout3_buf/O
|
|
net (fo=26129, routed) 0.955 -0.353 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/mlkem_clk
|
|
SLICE_X25Y70 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/_zz_ram_port1_reg[36]/C
|
|
clock pessimism 0.099 -0.254
|
|
clock uncertainty 0.197 -0.058
|
|
SLICE_X25Y70 FDRE (Hold_fdre_C_D) 0.009 -0.049 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/_zz_ram_port1_reg[36]
|
|
-------------------------------------------------------------------
|
|
required time 0.049
|
|
arrival time 0.211
|
|
-------------------------------------------------------------------
|
|
slack 0.259
|
|
|
|
Slack (MET) : 0.262ns (arrival time - required time)
|
|
Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/ram_reg_0_3_48_53/RAMA/CLK
|
|
(rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/_zz_ram_port1_reg[48]/D
|
|
(rising edge-triggered cell FDRE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns})
|
|
Path Group: mlkem_clk_clk_pll
|
|
Path Type: Hold (Min at Fast Process Corner)
|
|
Requirement: 0.000ns (mlkem_clk_clk_pll rise@0.000ns - sys_clk rise@0.000ns)
|
|
Data Path Delay: 0.788ns (logic 0.492ns (62.458%) route 0.296ns (37.542%))
|
|
Logic Levels: 0
|
|
Clock Path Skew: 0.325ns (DCD - SCD - CPR)
|
|
Destination Clock Delay (DCD): -0.353ns
|
|
Source Clock Delay (SCD): -0.579ns
|
|
Clock Pessimism Removal (CPR): -0.099ns
|
|
Clock Uncertainty: 0.197ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Discrete Jitter (DJ): 0.136ns
|
|
Phase Error (PE): 0.120ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock sys_clk rise edge) 0.000 0.000 r
|
|
K21 0.000 0.000 r clk (IN)
|
|
net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1
|
|
K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O
|
|
net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll
|
|
PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1)
|
|
-2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1
|
|
net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll
|
|
BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O
|
|
net (fo=10004, routed) 0.683 -0.579 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/ram_reg_0_3_48_53/WCLK
|
|
SLICE_X22Y70 RAMD32 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/ram_reg_0_3_48_53/RAMA/CLK
|
|
------------------------------------------------------------------- -------------------
|
|
SLICE_X22Y70 RAMD32 (Prop_ramd32_CLK_O)
|
|
0.492 -0.087 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/ram_reg_0_3_48_53/RAMA/O
|
|
net (fo=1, routed) 0.296 0.208 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/_zz_ram_port10[48]
|
|
SLICE_X26Y70 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/_zz_ram_port1_reg[48]/D
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock mlkem_clk_clk_pll rise edge)
|
|
0.000 0.000 r
|
|
K21 0.000 0.000 r clk (IN)
|
|
net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1
|
|
K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O
|
|
net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll
|
|
PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2)
|
|
-2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2
|
|
net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll
|
|
BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout3_buf/O
|
|
net (fo=26129, routed) 0.955 -0.353 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/mlkem_clk
|
|
SLICE_X26Y70 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/_zz_ram_port1_reg[48]/C
|
|
clock pessimism 0.099 -0.254
|
|
clock uncertainty 0.197 -0.058
|
|
SLICE_X26Y70 FDRE (Hold_fdre_C_D) 0.004 -0.054 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/_zz_ram_port1_reg[48]
|
|
-------------------------------------------------------------------
|
|
required time 0.054
|
|
arrival time 0.208
|
|
-------------------------------------------------------------------
|
|
slack 0.262
|
|
|
|
Slack (MET) : 0.272ns (arrival time - required time)
|
|
Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_12_17/RAMA/CLK
|
|
(rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/_zz_ram_port1_reg[12]/D
|
|
(rising edge-triggered cell FDRE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns})
|
|
Path Group: mlkem_clk_clk_pll
|
|
Path Type: Hold (Min at Fast Process Corner)
|
|
Requirement: 0.000ns (mlkem_clk_clk_pll rise@0.000ns - sys_clk rise@0.000ns)
|
|
Data Path Delay: 0.793ns (logic 0.492ns (62.032%) route 0.301ns (37.968%))
|
|
Logic Levels: 0
|
|
Clock Path Skew: 0.320ns (DCD - SCD - CPR)
|
|
Destination Clock Delay (DCD): -0.358ns
|
|
Source Clock Delay (SCD): -0.579ns
|
|
Clock Pessimism Removal (CPR): -0.099ns
|
|
Clock Uncertainty: 0.197ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Discrete Jitter (DJ): 0.136ns
|
|
Phase Error (PE): 0.120ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock sys_clk rise edge) 0.000 0.000 r
|
|
K21 0.000 0.000 r clk (IN)
|
|
net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1
|
|
K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O
|
|
net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll
|
|
PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1)
|
|
-2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1
|
|
net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll
|
|
BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O
|
|
net (fo=10004, routed) 0.683 -0.579 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_12_17/WCLK
|
|
SLICE_X20Y72 RAMD32 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_12_17/RAMA/CLK
|
|
------------------------------------------------------------------- -------------------
|
|
SLICE_X20Y72 RAMD32 (Prop_ramd32_CLK_O)
|
|
0.492 -0.087 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_12_17/RAMA/O
|
|
net (fo=1, routed) 0.301 0.214 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/_zz_ram_port10__2[12]
|
|
SLICE_X25Y74 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/_zz_ram_port1_reg[12]/D
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock mlkem_clk_clk_pll rise edge)
|
|
0.000 0.000 r
|
|
K21 0.000 0.000 r clk (IN)
|
|
net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1
|
|
K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O
|
|
net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll
|
|
PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2)
|
|
-2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2
|
|
net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll
|
|
BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout3_buf/O
|
|
net (fo=26129, routed) 0.950 -0.358 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/mlkem_clk
|
|
SLICE_X25Y74 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/_zz_ram_port1_reg[12]/C
|
|
clock pessimism 0.099 -0.259
|
|
clock uncertainty 0.197 -0.063
|
|
SLICE_X25Y74 FDRE (Hold_fdre_C_D) 0.004 -0.059 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/_zz_ram_port1_reg[12]
|
|
-------------------------------------------------------------------
|
|
required time 0.059
|
|
arrival time 0.214
|
|
-------------------------------------------------------------------
|
|
slack 0.272
|
|
|
|
Slack (MET) : 0.287ns (arrival time - required time)
|
|
Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/pushCC_pushPtrGray_reg[0]/C
|
|
(rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/pushToPopGray_buffercc/buffers_0_reg[0]/D
|
|
(rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns})
|
|
Path Group: mlkem_clk_clk_pll
|
|
Path Type: Hold (Min at Fast Process Corner)
|
|
Requirement: 0.000ns (mlkem_clk_clk_pll rise@0.000ns - sys_clk rise@0.000ns)
|
|
Data Path Delay: 0.856ns (logic 0.141ns (16.478%) route 0.715ns (83.522%))
|
|
Logic Levels: 0
|
|
Clock Path Skew: 0.326ns (DCD - SCD - CPR)
|
|
Destination Clock Delay (DCD): -0.389ns
|
|
Source Clock Delay (SCD): -0.616ns
|
|
Clock Pessimism Removal (CPR): -0.099ns
|
|
Clock Uncertainty: 0.197ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Discrete Jitter (DJ): 0.136ns
|
|
Phase Error (PE): 0.120ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock sys_clk rise edge) 0.000 0.000 r
|
|
K21 0.000 0.000 r clk (IN)
|
|
net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1
|
|
K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O
|
|
net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll
|
|
PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1)
|
|
-2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1
|
|
net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll
|
|
BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O
|
|
net (fo=10004, routed) 0.646 -0.616 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/sys_clk
|
|
SLICE_X111Y75 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/pushCC_pushPtrGray_reg[0]/C
|
|
------------------------------------------------------------------- -------------------
|
|
SLICE_X111Y75 FDCE (Prop_fdce_C_Q) 0.141 -0.475 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/pushCC_pushPtrGray_reg[0]/Q
|
|
net (fo=2, routed) 0.715 0.239 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/pushToPopGray_buffercc/D[0]
|
|
SLICE_X115Y75 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/pushToPopGray_buffercc/buffers_0_reg[0]/D
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock mlkem_clk_clk_pll rise edge)
|
|
0.000 0.000 r
|
|
K21 0.000 0.000 r clk (IN)
|
|
net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1
|
|
K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O
|
|
net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll
|
|
PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2)
|
|
-2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2
|
|
net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll
|
|
BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout3_buf/O
|
|
net (fo=26129, routed) 0.919 -0.389 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/pushToPopGray_buffercc/mlkem_clk
|
|
SLICE_X115Y75 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/pushToPopGray_buffercc/buffers_0_reg[0]/C
|
|
clock pessimism 0.099 -0.290
|
|
clock uncertainty 0.197 -0.094
|
|
SLICE_X115Y75 FDCE (Hold_fdce_C_D) 0.046 -0.048 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/pushToPopGray_buffercc/buffers_0_reg[0]
|
|
-------------------------------------------------------------------
|
|
required time 0.048
|
|
arrival time 0.239
|
|
-------------------------------------------------------------------
|
|
slack 0.287
|
|
|
|
Slack (MET) : 0.289ns (arrival time - required time)
|
|
Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/pushCC_pushPtrGray_reg[1]/C
|
|
(rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/pushToPopGray_buffercc/buffers_0_reg[1]/D
|
|
(rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns})
|
|
Path Group: mlkem_clk_clk_pll
|
|
Path Type: Hold (Min at Fast Process Corner)
|
|
Requirement: 0.000ns (mlkem_clk_clk_pll rise@0.000ns - sys_clk rise@0.000ns)
|
|
Data Path Delay: 0.861ns (logic 0.141ns (16.382%) route 0.720ns (83.618%))
|
|
Logic Levels: 0
|
|
Clock Path Skew: 0.328ns (DCD - SCD - CPR)
|
|
Destination Clock Delay (DCD): -0.353ns
|
|
Source Clock Delay (SCD): -0.582ns
|
|
Clock Pessimism Removal (CPR): -0.099ns
|
|
Clock Uncertainty: 0.197ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Discrete Jitter (DJ): 0.136ns
|
|
Phase Error (PE): 0.120ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock sys_clk rise edge) 0.000 0.000 r
|
|
K21 0.000 0.000 r clk (IN)
|
|
net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1
|
|
K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O
|
|
net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll
|
|
PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1)
|
|
-2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1
|
|
net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll
|
|
BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O
|
|
net (fo=10004, routed) 0.680 -0.582 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/sys_clk
|
|
SLICE_X27Y77 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/pushCC_pushPtrGray_reg[1]/C
|
|
------------------------------------------------------------------- -------------------
|
|
SLICE_X27Y77 FDCE (Prop_fdce_C_Q) 0.141 -0.441 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/pushCC_pushPtrGray_reg[1]/Q
|
|
net (fo=2, routed) 0.720 0.278 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/pushToPopGray_buffercc/Q[1]
|
|
SLICE_X27Y79 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/pushToPopGray_buffercc/buffers_0_reg[1]/D
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock mlkem_clk_clk_pll rise edge)
|
|
0.000 0.000 r
|
|
K21 0.000 0.000 r clk (IN)
|
|
net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1
|
|
K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O
|
|
net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll
|
|
PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2)
|
|
-2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2
|
|
net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll
|
|
BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout3_buf/O
|
|
net (fo=26129, routed) 0.955 -0.353 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/pushToPopGray_buffercc/mlkem_clk
|
|
SLICE_X27Y79 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/pushToPopGray_buffercc/buffers_0_reg[1]/C
|
|
clock pessimism 0.099 -0.254
|
|
clock uncertainty 0.197 -0.058
|
|
SLICE_X27Y79 FDCE (Hold_fdce_C_D) 0.047 -0.011 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/pushToPopGray_buffercc/buffers_0_reg[1]
|
|
-------------------------------------------------------------------
|
|
required time 0.011
|
|
arrival time 0.278
|
|
-------------------------------------------------------------------
|
|
slack 0.289
|
|
|
|
Slack (MET) : 0.319ns (arrival time - required time)
|
|
Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_42_47/RAMA_D1/CLK
|
|
(rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/_zz_ram_port1_reg[43]/D
|
|
(rising edge-triggered cell FDRE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns})
|
|
Path Group: mlkem_clk_clk_pll
|
|
Path Type: Hold (Min at Fast Process Corner)
|
|
Requirement: 0.000ns (mlkem_clk_clk_pll rise@0.000ns - sys_clk rise@0.000ns)
|
|
Data Path Delay: 0.916ns (logic 0.478ns (52.162%) route 0.438ns (47.838%))
|
|
Logic Levels: 0
|
|
Clock Path Skew: 0.326ns (DCD - SCD - CPR)
|
|
Destination Clock Delay (DCD): -0.355ns
|
|
Source Clock Delay (SCD): -0.582ns
|
|
Clock Pessimism Removal (CPR): -0.099ns
|
|
Clock Uncertainty: 0.197ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Discrete Jitter (DJ): 0.136ns
|
|
Phase Error (PE): 0.120ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock sys_clk rise edge) 0.000 0.000 r
|
|
K21 0.000 0.000 r clk (IN)
|
|
net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1
|
|
K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O
|
|
net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll
|
|
PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1)
|
|
-2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1
|
|
net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll
|
|
BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O
|
|
net (fo=10004, routed) 0.680 -0.582 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_42_47/WCLK
|
|
SLICE_X22Y73 RAMD32 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_42_47/RAMA_D1/CLK
|
|
------------------------------------------------------------------- -------------------
|
|
SLICE_X22Y73 RAMD32 (Prop_ramd32_CLK_O)
|
|
0.478 -0.104 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_42_47/RAMA_D1/O
|
|
net (fo=1, routed) 0.438 0.334 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/_zz_ram_port10__2[43]
|
|
SLICE_X23Y73 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/_zz_ram_port1_reg[43]/D
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock mlkem_clk_clk_pll rise edge)
|
|
0.000 0.000 r
|
|
K21 0.000 0.000 r clk (IN)
|
|
net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1
|
|
K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O
|
|
net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll
|
|
PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2)
|
|
-2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2
|
|
net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll
|
|
BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout3_buf/O
|
|
net (fo=26129, routed) 0.953 -0.355 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/mlkem_clk
|
|
SLICE_X23Y73 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/_zz_ram_port1_reg[43]/C
|
|
clock pessimism 0.099 -0.256
|
|
clock uncertainty 0.197 -0.060
|
|
SLICE_X23Y73 FDRE (Hold_fdre_C_D) 0.075 0.015 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/_zz_ram_port1_reg[43]
|
|
-------------------------------------------------------------------
|
|
required time -0.015
|
|
arrival time 0.334
|
|
-------------------------------------------------------------------
|
|
slack 0.319
|
|
|
|
Slack (MET) : 0.351ns (arrival time - required time)
|
|
Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_48_53/RAMA_D1/CLK
|
|
(rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/_zz_ram_port1_reg[49]/D
|
|
(rising edge-triggered cell FDRE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns})
|
|
Path Group: mlkem_clk_clk_pll
|
|
Path Type: Hold (Min at Fast Process Corner)
|
|
Requirement: 0.000ns (mlkem_clk_clk_pll rise@0.000ns - sys_clk rise@0.000ns)
|
|
Data Path Delay: 0.933ns (logic 0.478ns (51.242%) route 0.455ns (48.758%))
|
|
Logic Levels: 0
|
|
Clock Path Skew: 0.319ns (DCD - SCD - CPR)
|
|
Destination Clock Delay (DCD): -0.359ns
|
|
Source Clock Delay (SCD): -0.579ns
|
|
Clock Pessimism Removal (CPR): -0.099ns
|
|
Clock Uncertainty: 0.197ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Discrete Jitter (DJ): 0.136ns
|
|
Phase Error (PE): 0.120ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock sys_clk rise edge) 0.000 0.000 r
|
|
K21 0.000 0.000 r clk (IN)
|
|
net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1
|
|
K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O
|
|
net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll
|
|
PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1)
|
|
-2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1
|
|
net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll
|
|
BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O
|
|
net (fo=10004, routed) 0.683 -0.579 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_48_53/WCLK
|
|
SLICE_X18Y73 RAMD32 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_48_53/RAMA_D1/CLK
|
|
------------------------------------------------------------------- -------------------
|
|
SLICE_X18Y73 RAMD32 (Prop_ramd32_CLK_O)
|
|
0.478 -0.101 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_48_53/RAMA_D1/O
|
|
net (fo=1, routed) 0.455 0.353 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/_zz_ram_port10__2[49]
|
|
SLICE_X31Y76 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/_zz_ram_port1_reg[49]/D
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock mlkem_clk_clk_pll rise edge)
|
|
0.000 0.000 r
|
|
K21 0.000 0.000 r clk (IN)
|
|
net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1
|
|
K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O
|
|
net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll
|
|
PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2)
|
|
-2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2
|
|
net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll
|
|
BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout3_buf/O
|
|
net (fo=26129, routed) 0.949 -0.359 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/mlkem_clk
|
|
SLICE_X31Y76 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/_zz_ram_port1_reg[49]/C
|
|
clock pessimism 0.099 -0.260
|
|
clock uncertainty 0.197 -0.064
|
|
SLICE_X31Y76 FDRE (Hold_fdre_C_D) 0.066 0.002 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/_zz_ram_port1_reg[49]
|
|
-------------------------------------------------------------------
|
|
required time -0.002
|
|
arrival time 0.353
|
|
-------------------------------------------------------------------
|
|
slack 0.351
|
|
|
|
Slack (MET) : 0.363ns (arrival time - required time)
|
|
Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/popCC_ptrToPush_reg[2]/C
|
|
(rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/popToPushGray_buffercc/buffers_0_reg[2]/D
|
|
(rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns})
|
|
Path Group: mlkem_clk_clk_pll
|
|
Path Type: Hold (Min at Fast Process Corner)
|
|
Requirement: 0.000ns (mlkem_clk_clk_pll rise@0.000ns - sys_clk rise@0.000ns)
|
|
Data Path Delay: 0.879ns (logic 0.128ns (14.560%) route 0.751ns (85.440%))
|
|
Logic Levels: 0
|
|
Clock Path Skew: 0.326ns (DCD - SCD - CPR)
|
|
Destination Clock Delay (DCD): -0.355ns
|
|
Source Clock Delay (SCD): -0.582ns
|
|
Clock Pessimism Removal (CPR): -0.099ns
|
|
Clock Uncertainty: 0.197ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Discrete Jitter (DJ): 0.136ns
|
|
Phase Error (PE): 0.120ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock sys_clk rise edge) 0.000 0.000 r
|
|
K21 0.000 0.000 r clk (IN)
|
|
net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1
|
|
K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O
|
|
net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll
|
|
PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1)
|
|
-2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1
|
|
net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll
|
|
BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O
|
|
net (fo=10004, routed) 0.680 -0.582 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/sys_clk
|
|
SLICE_X26Y72 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/popCC_ptrToPush_reg[2]/C
|
|
------------------------------------------------------------------- -------------------
|
|
SLICE_X26Y72 FDCE (Prop_fdce_C_Q) 0.128 -0.454 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/popCC_ptrToPush_reg[2]/Q
|
|
net (fo=2, routed) 0.751 0.297 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/popToPushGray_buffercc/D[2]
|
|
SLICE_X27Y72 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/popToPushGray_buffercc/buffers_0_reg[2]/D
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock mlkem_clk_clk_pll rise edge)
|
|
0.000 0.000 r
|
|
K21 0.000 0.000 r clk (IN)
|
|
net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1
|
|
K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O
|
|
net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll
|
|
PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2)
|
|
-2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2
|
|
net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll
|
|
BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout3_buf/O
|
|
net (fo=26129, routed) 0.953 -0.355 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/popToPushGray_buffercc/mlkem_clk
|
|
SLICE_X27Y72 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/popToPushGray_buffercc/buffers_0_reg[2]/C
|
|
clock pessimism 0.099 -0.256
|
|
clock uncertainty 0.197 -0.060
|
|
SLICE_X27Y72 FDCE (Hold_fdce_C_D) -0.007 -0.067 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/popToPushGray_buffercc/buffers_0_reg[2]
|
|
-------------------------------------------------------------------
|
|
required time 0.067
|
|
arrival time 0.297
|
|
-------------------------------------------------------------------
|
|
slack 0.363
|
|
|
|
Slack (MET) : 0.364ns (arrival time - required time)
|
|
Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_12_17/RAMB_D1/CLK
|
|
(rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/_zz_ram_port1_reg[15]/D
|
|
(rising edge-triggered cell FDRE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns})
|
|
Path Group: mlkem_clk_clk_pll
|
|
Path Type: Hold (Min at Fast Process Corner)
|
|
Requirement: 0.000ns (mlkem_clk_clk_pll rise@0.000ns - sys_clk rise@0.000ns)
|
|
Data Path Delay: 0.953ns (logic 0.388ns (40.695%) route 0.565ns (59.305%))
|
|
Logic Levels: 0
|
|
Clock Path Skew: 0.323ns (DCD - SCD - CPR)
|
|
Destination Clock Delay (DCD): -0.355ns
|
|
Source Clock Delay (SCD): -0.579ns
|
|
Clock Pessimism Removal (CPR): -0.099ns
|
|
Clock Uncertainty: 0.197ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Discrete Jitter (DJ): 0.136ns
|
|
Phase Error (PE): 0.120ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock sys_clk rise edge) 0.000 0.000 r
|
|
K21 0.000 0.000 r clk (IN)
|
|
net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1
|
|
K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O
|
|
net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll
|
|
PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1)
|
|
-2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1
|
|
net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll
|
|
BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O
|
|
net (fo=10004, routed) 0.683 -0.579 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_12_17/WCLK
|
|
SLICE_X20Y72 RAMD32 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_12_17/RAMB_D1/CLK
|
|
------------------------------------------------------------------- -------------------
|
|
SLICE_X20Y72 RAMD32 (Prop_ramd32_CLK_O)
|
|
0.388 -0.191 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_12_17/RAMB_D1/O
|
|
net (fo=1, routed) 0.565 0.374 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/_zz_ram_port10__2[15]
|
|
SLICE_X23Y73 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/_zz_ram_port1_reg[15]/D
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock mlkem_clk_clk_pll rise edge)
|
|
0.000 0.000 r
|
|
K21 0.000 0.000 r clk (IN)
|
|
net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1
|
|
K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O
|
|
net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll
|
|
PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2)
|
|
-2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2
|
|
net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll
|
|
BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout3_buf/O
|
|
net (fo=26129, routed) 0.953 -0.355 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/mlkem_clk
|
|
SLICE_X23Y73 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/_zz_ram_port1_reg[15]/C
|
|
clock pessimism 0.099 -0.256
|
|
clock uncertainty 0.197 -0.060
|
|
SLICE_X23Y73 FDRE (Hold_fdre_C_D) 0.070 0.010 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/_zz_ram_port1_reg[15]
|
|
-------------------------------------------------------------------
|
|
required time -0.010
|
|
arrival time 0.374
|
|
-------------------------------------------------------------------
|
|
slack 0.364
|
|
|
|
Slack (MET) : 0.389ns (arrival time - required time)
|
|
Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/popCC_ptrToPush_reg[0]/C
|
|
(rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/popToPushGray_buffercc/buffers_0_reg[0]/D
|
|
(rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns})
|
|
Path Group: mlkem_clk_clk_pll
|
|
Path Type: Hold (Min at Fast Process Corner)
|
|
Requirement: 0.000ns (mlkem_clk_clk_pll rise@0.000ns - sys_clk rise@0.000ns)
|
|
Data Path Delay: 0.957ns (logic 0.141ns (14.730%) route 0.816ns (85.270%))
|
|
Logic Levels: 0
|
|
Clock Path Skew: 0.326ns (DCD - SCD - CPR)
|
|
Destination Clock Delay (DCD): -0.355ns
|
|
Source Clock Delay (SCD): -0.582ns
|
|
Clock Pessimism Removal (CPR): -0.099ns
|
|
Clock Uncertainty: 0.197ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Discrete Jitter (DJ): 0.136ns
|
|
Phase Error (PE): 0.120ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock sys_clk rise edge) 0.000 0.000 r
|
|
K21 0.000 0.000 r clk (IN)
|
|
net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1
|
|
K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O
|
|
net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll
|
|
PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1)
|
|
-2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1
|
|
net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll
|
|
BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O
|
|
net (fo=10004, routed) 0.680 -0.582 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/sys_clk
|
|
SLICE_X26Y72 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/popCC_ptrToPush_reg[0]/C
|
|
------------------------------------------------------------------- -------------------
|
|
SLICE_X26Y72 FDCE (Prop_fdce_C_Q) 0.141 -0.441 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/popCC_ptrToPush_reg[0]/Q
|
|
net (fo=2, routed) 0.816 0.375 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/popToPushGray_buffercc/D[0]
|
|
SLICE_X27Y72 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/popToPushGray_buffercc/buffers_0_reg[0]/D
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock mlkem_clk_clk_pll rise edge)
|
|
0.000 0.000 r
|
|
K21 0.000 0.000 r clk (IN)
|
|
net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1
|
|
K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O
|
|
net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll
|
|
PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2)
|
|
-2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2
|
|
net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll
|
|
BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout3_buf/O
|
|
net (fo=26129, routed) 0.953 -0.355 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/popToPushGray_buffercc/mlkem_clk
|
|
SLICE_X27Y72 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/popToPushGray_buffercc/buffers_0_reg[0]/C
|
|
clock pessimism 0.099 -0.256
|
|
clock uncertainty 0.197 -0.060
|
|
SLICE_X27Y72 FDCE (Hold_fdce_C_D) 0.046 -0.014 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/popToPushGray_buffercc/buffers_0_reg[0]
|
|
-------------------------------------------------------------------
|
|
required time 0.014
|
|
arrival time 0.375
|
|
-------------------------------------------------------------------
|
|
slack 0.389
|
|
|
|
Slack (MET) : 0.405ns (arrival time - required time)
|
|
Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/pushCC_pushPtrGray_reg[2]/C
|
|
(rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/pushToPopGray_buffercc/buffers_0_reg[2]/D
|
|
(rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns})
|
|
Path Group: mlkem_clk_clk_pll
|
|
Path Type: Hold (Min at Fast Process Corner)
|
|
Requirement: 0.000ns (mlkem_clk_clk_pll rise@0.000ns - sys_clk rise@0.000ns)
|
|
Data Path Delay: 0.922ns (logic 0.128ns (13.878%) route 0.794ns (86.122%))
|
|
Logic Levels: 0
|
|
Clock Path Skew: 0.328ns (DCD - SCD - CPR)
|
|
Destination Clock Delay (DCD): -0.353ns
|
|
Source Clock Delay (SCD): -0.582ns
|
|
Clock Pessimism Removal (CPR): -0.099ns
|
|
Clock Uncertainty: 0.197ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Discrete Jitter (DJ): 0.136ns
|
|
Phase Error (PE): 0.120ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock sys_clk rise edge) 0.000 0.000 r
|
|
K21 0.000 0.000 r clk (IN)
|
|
net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1
|
|
K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O
|
|
net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll
|
|
PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1)
|
|
-2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1
|
|
net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll
|
|
BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O
|
|
net (fo=10004, routed) 0.680 -0.582 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/sys_clk
|
|
SLICE_X27Y77 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/pushCC_pushPtrGray_reg[2]/C
|
|
------------------------------------------------------------------- -------------------
|
|
SLICE_X27Y77 FDCE (Prop_fdce_C_Q) 0.128 -0.454 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/pushCC_pushPtrGray_reg[2]/Q
|
|
net (fo=4, routed) 0.794 0.340 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/pushToPopGray_buffercc/buffers_0_reg[2]_0
|
|
SLICE_X27Y79 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/pushToPopGray_buffercc/buffers_0_reg[2]/D
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock mlkem_clk_clk_pll rise edge)
|
|
0.000 0.000 r
|
|
K21 0.000 0.000 r clk (IN)
|
|
net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1
|
|
K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O
|
|
net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll
|
|
PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2)
|
|
-2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2
|
|
net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll
|
|
BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout3_buf/O
|
|
net (fo=26129, routed) 0.955 -0.353 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/pushToPopGray_buffercc/mlkem_clk
|
|
SLICE_X27Y79 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/pushToPopGray_buffercc/buffers_0_reg[2]/C
|
|
clock pessimism 0.099 -0.254
|
|
clock uncertainty 0.197 -0.058
|
|
SLICE_X27Y79 FDCE (Hold_fdce_C_D) -0.007 -0.065 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/pushToPopGray_buffercc/buffers_0_reg[2]
|
|
-------------------------------------------------------------------
|
|
required time 0.065
|
|
arrival time 0.340
|
|
-------------------------------------------------------------------
|
|
slack 0.405
|
|
|
|
Slack (MET) : 0.464ns (arrival time - required time)
|
|
Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/pushCC_pushPtrGray_reg[2]/C
|
|
(rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/pushToPopGray_buffercc/buffers_0_reg[2]/D
|
|
(rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns})
|
|
Path Group: mlkem_clk_clk_pll
|
|
Path Type: Hold (Min at Fast Process Corner)
|
|
Requirement: 0.000ns (mlkem_clk_clk_pll rise@0.000ns - sys_clk rise@0.000ns)
|
|
Data Path Delay: 1.033ns (logic 0.141ns (13.645%) route 0.892ns (86.355%))
|
|
Logic Levels: 0
|
|
Clock Path Skew: 0.326ns (DCD - SCD - CPR)
|
|
Destination Clock Delay (DCD): -0.389ns
|
|
Source Clock Delay (SCD): -0.616ns
|
|
Clock Pessimism Removal (CPR): -0.099ns
|
|
Clock Uncertainty: 0.197ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Discrete Jitter (DJ): 0.136ns
|
|
Phase Error (PE): 0.120ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock sys_clk rise edge) 0.000 0.000 r
|
|
K21 0.000 0.000 r clk (IN)
|
|
net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1
|
|
K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O
|
|
net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll
|
|
PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1)
|
|
-2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1
|
|
net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll
|
|
BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O
|
|
net (fo=10004, routed) 0.646 -0.616 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/sys_clk
|
|
SLICE_X111Y75 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/pushCC_pushPtrGray_reg[2]/C
|
|
------------------------------------------------------------------- -------------------
|
|
SLICE_X111Y75 FDCE (Prop_fdce_C_Q) 0.141 -0.475 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/pushCC_pushPtrGray_reg[2]/Q
|
|
net (fo=2, routed) 0.892 0.417 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/pushToPopGray_buffercc/D[2]
|
|
SLICE_X115Y75 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/pushToPopGray_buffercc/buffers_0_reg[2]/D
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock mlkem_clk_clk_pll rise edge)
|
|
0.000 0.000 r
|
|
K21 0.000 0.000 r clk (IN)
|
|
net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1
|
|
K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O
|
|
net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll
|
|
PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2)
|
|
-2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2
|
|
net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll
|
|
BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout3_buf/O
|
|
net (fo=26129, routed) 0.919 -0.389 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/pushToPopGray_buffercc/mlkem_clk
|
|
SLICE_X115Y75 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/pushToPopGray_buffercc/buffers_0_reg[2]/C
|
|
clock pessimism 0.099 -0.290
|
|
clock uncertainty 0.197 -0.094
|
|
SLICE_X115Y75 FDCE (Hold_fdce_C_D) 0.047 -0.047 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/pushToPopGray_buffercc/buffers_0_reg[2]
|
|
-------------------------------------------------------------------
|
|
required time 0.047
|
|
arrival time 0.417
|
|
-------------------------------------------------------------------
|
|
slack 0.464
|
|
|
|
Slack (MET) : 0.480ns (arrival time - required time)
|
|
Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_48_53/RAMA/CLK
|
|
(rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/_zz_ram_port1_reg[48]/D
|
|
(rising edge-triggered cell FDRE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns})
|
|
Path Group: mlkem_clk_clk_pll
|
|
Path Type: Hold (Min at Fast Process Corner)
|
|
Requirement: 0.000ns (mlkem_clk_clk_pll rise@0.000ns - sys_clk rise@0.000ns)
|
|
Data Path Delay: 1.000ns (logic 0.492ns (49.207%) route 0.508ns (50.793%))
|
|
Logic Levels: 0
|
|
Clock Path Skew: 0.319ns (DCD - SCD - CPR)
|
|
Destination Clock Delay (DCD): -0.359ns
|
|
Source Clock Delay (SCD): -0.579ns
|
|
Clock Pessimism Removal (CPR): -0.099ns
|
|
Clock Uncertainty: 0.197ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Discrete Jitter (DJ): 0.136ns
|
|
Phase Error (PE): 0.120ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock sys_clk rise edge) 0.000 0.000 r
|
|
K21 0.000 0.000 r clk (IN)
|
|
net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1
|
|
K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O
|
|
net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll
|
|
PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1)
|
|
-2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1
|
|
net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll
|
|
BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O
|
|
net (fo=10004, routed) 0.683 -0.579 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_48_53/WCLK
|
|
SLICE_X18Y73 RAMD32 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_48_53/RAMA/CLK
|
|
------------------------------------------------------------------- -------------------
|
|
SLICE_X18Y73 RAMD32 (Prop_ramd32_CLK_O)
|
|
0.492 -0.087 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_48_53/RAMA/O
|
|
net (fo=1, routed) 0.508 0.420 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/_zz_ram_port10__2[48]
|
|
SLICE_X31Y76 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/_zz_ram_port1_reg[48]/D
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock mlkem_clk_clk_pll rise edge)
|
|
0.000 0.000 r
|
|
K21 0.000 0.000 r clk (IN)
|
|
net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1
|
|
K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O
|
|
net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll
|
|
PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2)
|
|
-2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2
|
|
net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll
|
|
BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout3_buf/O
|
|
net (fo=26129, routed) 0.949 -0.359 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/mlkem_clk
|
|
SLICE_X31Y76 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/_zz_ram_port1_reg[48]/C
|
|
clock pessimism 0.099 -0.260
|
|
clock uncertainty 0.197 -0.064
|
|
SLICE_X31Y76 FDRE (Hold_fdre_C_D) 0.004 -0.060 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/_zz_ram_port1_reg[48]
|
|
-------------------------------------------------------------------
|
|
required time 0.060
|
|
arrival time 0.420
|
|
-------------------------------------------------------------------
|
|
slack 0.480
|
|
|
|
Slack (MET) : 0.497ns (arrival time - required time)
|
|
Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/ram_reg_0_3_0_5/RAMB/CLK
|
|
(rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/_zz_ram_port1_reg[2]/D
|
|
(rising edge-triggered cell FDRE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns})
|
|
Path Group: mlkem_clk_clk_pll
|
|
Path Type: Hold (Min at Fast Process Corner)
|
|
Requirement: 0.000ns (mlkem_clk_clk_pll rise@0.000ns - sys_clk rise@0.000ns)
|
|
Data Path Delay: 0.967ns (logic 0.394ns (40.759%) route 0.573ns (59.241%))
|
|
Logic Levels: 0
|
|
Clock Path Skew: 0.283ns (DCD - SCD - CPR)
|
|
Destination Clock Delay (DCD): -0.400ns
|
|
Source Clock Delay (SCD): -0.584ns
|
|
Clock Pessimism Removal (CPR): -0.099ns
|
|
Clock Uncertainty: 0.197ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Discrete Jitter (DJ): 0.136ns
|
|
Phase Error (PE): 0.120ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock sys_clk rise edge) 0.000 0.000 r
|
|
K21 0.000 0.000 r clk (IN)
|
|
net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1
|
|
K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O
|
|
net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll
|
|
PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1)
|
|
-2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1
|
|
net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll
|
|
BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O
|
|
net (fo=10004, routed) 0.678 -0.584 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/ram_reg_0_3_0_5/WCLK
|
|
SLICE_X36Y68 RAMD32 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/ram_reg_0_3_0_5/RAMB/CLK
|
|
------------------------------------------------------------------- -------------------
|
|
SLICE_X36Y68 RAMD32 (Prop_ramd32_CLK_O)
|
|
0.394 -0.190 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/ram_reg_0_3_0_5/RAMB/O
|
|
net (fo=1, routed) 0.573 0.382 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/_zz_ram_port10[2]
|
|
SLICE_X76Y67 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/_zz_ram_port1_reg[2]/D
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock mlkem_clk_clk_pll rise edge)
|
|
0.000 0.000 r
|
|
K21 0.000 0.000 r clk (IN)
|
|
net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1
|
|
K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O
|
|
net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll
|
|
PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2)
|
|
-2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2
|
|
net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll
|
|
BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout3_buf/O
|
|
net (fo=26129, routed) 0.908 -0.400 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/mlkem_clk
|
|
SLICE_X76Y67 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/_zz_ram_port1_reg[2]/C
|
|
clock pessimism 0.099 -0.301
|
|
clock uncertainty 0.197 -0.105
|
|
SLICE_X76Y67 FDRE (Hold_fdre_C_D) -0.010 -0.115 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/_zz_ram_port1_reg[2]
|
|
-------------------------------------------------------------------
|
|
required time 0.115
|
|
arrival time 0.382
|
|
-------------------------------------------------------------------
|
|
slack 0.497
|
|
|
|
Slack (MET) : 0.502ns (arrival time - required time)
|
|
Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/ram_reg_0_7_6_11/RAMC_D1/CLK
|
|
(rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/_zz_ram_port1_reg[11]/D
|
|
(rising edge-triggered cell FDRE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns})
|
|
Path Group: mlkem_clk_clk_pll
|
|
Path Type: Hold (Min at Fast Process Corner)
|
|
Requirement: 0.000ns (mlkem_clk_clk_pll rise@0.000ns - sys_clk rise@0.000ns)
|
|
Data Path Delay: 1.108ns (logic 0.386ns (34.837%) route 0.722ns (65.163%))
|
|
Logic Levels: 0
|
|
Clock Path Skew: 0.339ns (DCD - SCD - CPR)
|
|
Destination Clock Delay (DCD): -0.387ns
|
|
Source Clock Delay (SCD): -0.627ns
|
|
Clock Pessimism Removal (CPR): -0.099ns
|
|
Clock Uncertainty: 0.197ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Discrete Jitter (DJ): 0.136ns
|
|
Phase Error (PE): 0.120ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock sys_clk rise edge) 0.000 0.000 r
|
|
K21 0.000 0.000 r clk (IN)
|
|
net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1
|
|
K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O
|
|
net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll
|
|
PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1)
|
|
-2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1
|
|
net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll
|
|
BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O
|
|
net (fo=10004, routed) 0.635 -0.627 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/ram_reg_0_7_6_11/WCLK
|
|
SLICE_X72Y72 RAMD32 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/ram_reg_0_7_6_11/RAMC_D1/CLK
|
|
------------------------------------------------------------------- -------------------
|
|
SLICE_X72Y72 RAMD32 (Prop_ramd32_CLK_O)
|
|
0.386 -0.241 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/ram_reg_0_7_6_11/RAMC_D1/O
|
|
net (fo=1, routed) 0.722 0.481 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/_zz_ram_port10__0[11]
|
|
SLICE_X110Y72 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/_zz_ram_port1_reg[11]/D
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock mlkem_clk_clk_pll rise edge)
|
|
0.000 0.000 r
|
|
K21 0.000 0.000 r clk (IN)
|
|
net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1
|
|
K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O
|
|
net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll
|
|
PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2)
|
|
-2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2
|
|
net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll
|
|
BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout3_buf/O
|
|
net (fo=26129, routed) 0.921 -0.387 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/mlkem_clk
|
|
SLICE_X110Y72 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/_zz_ram_port1_reg[11]/C
|
|
clock pessimism 0.099 -0.288
|
|
clock uncertainty 0.197 -0.092
|
|
SLICE_X110Y72 FDRE (Hold_fdre_C_D) 0.070 -0.022 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/_zz_ram_port1_reg[11]
|
|
-------------------------------------------------------------------
|
|
required time 0.022
|
|
arrival time 0.481
|
|
-------------------------------------------------------------------
|
|
slack 0.502
|
|
|
|
Slack (MET) : 0.533ns (arrival time - required time)
|
|
Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/ram_reg_0_7_6_11/RAMB_D1/CLK
|
|
(rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/_zz_ram_port1_reg[9]/D
|
|
(rising edge-triggered cell FDRE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns})
|
|
Path Group: mlkem_clk_clk_pll
|
|
Path Type: Hold (Min at Fast Process Corner)
|
|
Requirement: 0.000ns (mlkem_clk_clk_pll rise@0.000ns - sys_clk rise@0.000ns)
|
|
Data Path Delay: 1.124ns (logic 0.388ns (34.515%) route 0.736ns (65.485%))
|
|
Logic Levels: 0
|
|
Clock Path Skew: 0.331ns (DCD - SCD - CPR)
|
|
Destination Clock Delay (DCD): -0.395ns
|
|
Source Clock Delay (SCD): -0.627ns
|
|
Clock Pessimism Removal (CPR): -0.099ns
|
|
Clock Uncertainty: 0.197ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Discrete Jitter (DJ): 0.136ns
|
|
Phase Error (PE): 0.120ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock sys_clk rise edge) 0.000 0.000 r
|
|
K21 0.000 0.000 r clk (IN)
|
|
net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1
|
|
K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O
|
|
net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll
|
|
PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1)
|
|
-2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1
|
|
net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll
|
|
BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O
|
|
net (fo=10004, routed) 0.635 -0.627 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/ram_reg_0_7_6_11/WCLK
|
|
SLICE_X72Y72 RAMD32 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/ram_reg_0_7_6_11/RAMB_D1/CLK
|
|
------------------------------------------------------------------- -------------------
|
|
SLICE_X72Y72 RAMD32 (Prop_ramd32_CLK_O)
|
|
0.388 -0.239 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/ram_reg_0_7_6_11/RAMB_D1/O
|
|
net (fo=1, routed) 0.736 0.497 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/_zz_ram_port10__0[9]
|
|
SLICE_X100Y72 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/_zz_ram_port1_reg[9]/D
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock mlkem_clk_clk_pll rise edge)
|
|
0.000 0.000 r
|
|
K21 0.000 0.000 r clk (IN)
|
|
net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1
|
|
K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O
|
|
net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll
|
|
PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2)
|
|
-2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2
|
|
net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll
|
|
BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout3_buf/O
|
|
net (fo=26129, routed) 0.913 -0.395 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/mlkem_clk
|
|
SLICE_X100Y72 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/_zz_ram_port1_reg[9]/C
|
|
clock pessimism 0.099 -0.296
|
|
clock uncertainty 0.197 -0.100
|
|
SLICE_X100Y72 FDRE (Hold_fdre_C_D) 0.063 -0.037 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/_zz_ram_port1_reg[9]
|
|
-------------------------------------------------------------------
|
|
required time 0.037
|
|
arrival time 0.497
|
|
-------------------------------------------------------------------
|
|
slack 0.533
|
|
|
|
Slack (MET) : 0.632ns (arrival time - required time)
|
|
Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/ram_reg_0_3_6_11/RAMC_D1/CLK
|
|
(rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/_zz_ram_port1_reg[11]/D
|
|
(rising edge-triggered cell FDRE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns})
|
|
Path Group: mlkem_clk_clk_pll
|
|
Path Type: Hold (Min at Fast Process Corner)
|
|
Requirement: 0.000ns (mlkem_clk_clk_pll rise@0.000ns - sys_clk rise@0.000ns)
|
|
Data Path Delay: 1.187ns (logic 0.386ns (32.521%) route 0.801ns (67.479%))
|
|
Logic Levels: 0
|
|
Clock Path Skew: 0.282ns (DCD - SCD - CPR)
|
|
Destination Clock Delay (DCD): -0.400ns
|
|
Source Clock Delay (SCD): -0.583ns
|
|
Clock Pessimism Removal (CPR): -0.099ns
|
|
Clock Uncertainty: 0.197ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Discrete Jitter (DJ): 0.136ns
|
|
Phase Error (PE): 0.120ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock sys_clk rise edge) 0.000 0.000 r
|
|
K21 0.000 0.000 r clk (IN)
|
|
net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1
|
|
K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O
|
|
net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll
|
|
PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1)
|
|
-2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1
|
|
net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll
|
|
BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O
|
|
net (fo=10004, routed) 0.679 -0.583 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/ram_reg_0_3_6_11/WCLK
|
|
SLICE_X36Y67 RAMD32 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/ram_reg_0_3_6_11/RAMC_D1/CLK
|
|
------------------------------------------------------------------- -------------------
|
|
SLICE_X36Y67 RAMD32 (Prop_ramd32_CLK_O)
|
|
0.386 -0.197 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/ram_reg_0_3_6_11/RAMC_D1/O
|
|
net (fo=1, routed) 0.801 0.604 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/_zz_ram_port10[11]
|
|
SLICE_X76Y67 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/_zz_ram_port1_reg[11]/D
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock mlkem_clk_clk_pll rise edge)
|
|
0.000 0.000 r
|
|
K21 0.000 0.000 r clk (IN)
|
|
net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1
|
|
K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O
|
|
net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll
|
|
PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2)
|
|
-2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2
|
|
net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll
|
|
BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout3_buf/O
|
|
net (fo=26129, routed) 0.908 -0.400 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/mlkem_clk
|
|
SLICE_X76Y67 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/_zz_ram_port1_reg[11]/C
|
|
clock pessimism 0.099 -0.301
|
|
clock uncertainty 0.197 -0.105
|
|
SLICE_X76Y67 FDRE (Hold_fdre_C_D) 0.076 -0.029 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/_zz_ram_port1_reg[11]
|
|
-------------------------------------------------------------------
|
|
required time 0.029
|
|
arrival time 0.604
|
|
-------------------------------------------------------------------
|
|
slack 0.632
|
|
|
|
Slack (MET) : 0.642ns (arrival time - required time)
|
|
Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/ram_reg_0_7_6_11/RAMB/CLK
|
|
(rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/_zz_ram_port1_reg[8]/D
|
|
(rising edge-triggered cell FDRE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns})
|
|
Path Group: mlkem_clk_clk_pll
|
|
Path Type: Hold (Min at Fast Process Corner)
|
|
Requirement: 0.000ns (mlkem_clk_clk_pll rise@0.000ns - sys_clk rise@0.000ns)
|
|
Data Path Delay: 1.159ns (logic 0.394ns (33.980%) route 0.765ns (66.020%))
|
|
Logic Levels: 0
|
|
Clock Path Skew: 0.331ns (DCD - SCD - CPR)
|
|
Destination Clock Delay (DCD): -0.395ns
|
|
Source Clock Delay (SCD): -0.627ns
|
|
Clock Pessimism Removal (CPR): -0.099ns
|
|
Clock Uncertainty: 0.197ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Discrete Jitter (DJ): 0.136ns
|
|
Phase Error (PE): 0.120ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock sys_clk rise edge) 0.000 0.000 r
|
|
K21 0.000 0.000 r clk (IN)
|
|
net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1
|
|
K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O
|
|
net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll
|
|
PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1)
|
|
-2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1
|
|
net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll
|
|
BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O
|
|
net (fo=10004, routed) 0.635 -0.627 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/ram_reg_0_7_6_11/WCLK
|
|
SLICE_X72Y72 RAMD32 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/ram_reg_0_7_6_11/RAMB/CLK
|
|
------------------------------------------------------------------- -------------------
|
|
SLICE_X72Y72 RAMD32 (Prop_ramd32_CLK_O)
|
|
0.394 -0.233 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/ram_reg_0_7_6_11/RAMB/O
|
|
net (fo=1, routed) 0.765 0.532 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/_zz_ram_port10__0[8]
|
|
SLICE_X100Y72 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/_zz_ram_port1_reg[8]/D
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock mlkem_clk_clk_pll rise edge)
|
|
0.000 0.000 r
|
|
K21 0.000 0.000 r clk (IN)
|
|
net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1
|
|
K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O
|
|
net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll
|
|
PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2)
|
|
-2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2
|
|
net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll
|
|
BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout3_buf/O
|
|
net (fo=26129, routed) 0.913 -0.395 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/mlkem_clk
|
|
SLICE_X100Y72 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/_zz_ram_port1_reg[8]/C
|
|
clock pessimism 0.099 -0.296
|
|
clock uncertainty 0.197 -0.100
|
|
SLICE_X100Y72 FDRE (Hold_fdre_C_D) -0.010 -0.110 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/_zz_ram_port1_reg[8]
|
|
-------------------------------------------------------------------
|
|
required time 0.110
|
|
arrival time 0.532
|
|
-------------------------------------------------------------------
|
|
slack 0.642
|
|
|
|
Slack (MET) : 0.658ns (arrival time - required time)
|
|
Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/ram_reg_0_7_30_35/RAMC_D1/CLK
|
|
(rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/_zz_ram_port1_reg[35]/D
|
|
(rising edge-triggered cell FDRE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns})
|
|
Path Group: mlkem_clk_clk_pll
|
|
Path Type: Hold (Min at Fast Process Corner)
|
|
Requirement: 0.000ns (mlkem_clk_clk_pll rise@0.000ns - sys_clk rise@0.000ns)
|
|
Data Path Delay: 1.258ns (logic 0.386ns (30.689%) route 0.872ns (69.311%))
|
|
Logic Levels: 0
|
|
Clock Path Skew: 0.340ns (DCD - SCD - CPR)
|
|
Destination Clock Delay (DCD): -0.385ns
|
|
Source Clock Delay (SCD): -0.626ns
|
|
Clock Pessimism Removal (CPR): -0.099ns
|
|
Clock Uncertainty: 0.197ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Discrete Jitter (DJ): 0.136ns
|
|
Phase Error (PE): 0.120ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock sys_clk rise edge) 0.000 0.000 r
|
|
K21 0.000 0.000 r clk (IN)
|
|
net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1
|
|
K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O
|
|
net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll
|
|
PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1)
|
|
-2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1
|
|
net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll
|
|
BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O
|
|
net (fo=10004, routed) 0.636 -0.626 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/ram_reg_0_7_30_35/WCLK
|
|
SLICE_X68Y77 RAMD32 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/ram_reg_0_7_30_35/RAMC_D1/CLK
|
|
------------------------------------------------------------------- -------------------
|
|
SLICE_X68Y77 RAMD32 (Prop_ramd32_CLK_O)
|
|
0.386 -0.240 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/ram_reg_0_7_30_35/RAMC_D1/O
|
|
net (fo=1, routed) 0.872 0.631 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/_zz_ram_port10__0[35]
|
|
SLICE_X116Y77 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/_zz_ram_port1_reg[35]/D
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock mlkem_clk_clk_pll rise edge)
|
|
0.000 0.000 r
|
|
K21 0.000 0.000 r clk (IN)
|
|
net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1
|
|
K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O
|
|
net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll
|
|
PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2)
|
|
-2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2
|
|
net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll
|
|
BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout3_buf/O
|
|
net (fo=26129, routed) 0.923 -0.385 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/mlkem_clk
|
|
SLICE_X116Y77 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/_zz_ram_port1_reg[35]/C
|
|
clock pessimism 0.099 -0.286
|
|
clock uncertainty 0.197 -0.090
|
|
SLICE_X116Y77 FDRE (Hold_fdre_C_D) 0.063 -0.027 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/_zz_ram_port1_reg[35]
|
|
-------------------------------------------------------------------
|
|
required time 0.027
|
|
arrival time 0.631
|
|
-------------------------------------------------------------------
|
|
slack 0.658
|
|
|
|
Slack (MET) : 0.705ns (arrival time - required time)
|
|
Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/ram_reg_0_3_0_5/RAMC/CLK
|
|
(rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/_zz_ram_port1_reg[4]/D
|
|
(rising edge-triggered cell FDRE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns})
|
|
Path Group: mlkem_clk_clk_pll
|
|
Path Type: Hold (Min at Fast Process Corner)
|
|
Requirement: 0.000ns (mlkem_clk_clk_pll rise@0.000ns - sys_clk rise@0.000ns)
|
|
Data Path Delay: 1.170ns (logic 0.390ns (33.342%) route 0.780ns (66.658%))
|
|
Logic Levels: 0
|
|
Clock Path Skew: 0.283ns (DCD - SCD - CPR)
|
|
Destination Clock Delay (DCD): -0.400ns
|
|
Source Clock Delay (SCD): -0.584ns
|
|
Clock Pessimism Removal (CPR): -0.099ns
|
|
Clock Uncertainty: 0.197ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Discrete Jitter (DJ): 0.136ns
|
|
Phase Error (PE): 0.120ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock sys_clk rise edge) 0.000 0.000 r
|
|
K21 0.000 0.000 r clk (IN)
|
|
net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1
|
|
K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O
|
|
net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll
|
|
PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1)
|
|
-2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1
|
|
net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll
|
|
BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O
|
|
net (fo=10004, routed) 0.678 -0.584 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/ram_reg_0_3_0_5/WCLK
|
|
SLICE_X36Y68 RAMD32 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/ram_reg_0_3_0_5/RAMC/CLK
|
|
------------------------------------------------------------------- -------------------
|
|
SLICE_X36Y68 RAMD32 (Prop_ramd32_CLK_O)
|
|
0.390 -0.194 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/ram_reg_0_3_0_5/RAMC/O
|
|
net (fo=1, routed) 0.780 0.585 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/_zz_ram_port10[4]
|
|
SLICE_X76Y67 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/_zz_ram_port1_reg[4]/D
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock mlkem_clk_clk_pll rise edge)
|
|
0.000 0.000 r
|
|
K21 0.000 0.000 r clk (IN)
|
|
net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1
|
|
K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O
|
|
net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll
|
|
PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2)
|
|
-2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2
|
|
net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll
|
|
BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout3_buf/O
|
|
net (fo=26129, routed) 0.908 -0.400 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/mlkem_clk
|
|
SLICE_X76Y67 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/_zz_ram_port1_reg[4]/C
|
|
clock pessimism 0.099 -0.301
|
|
clock uncertainty 0.197 -0.105
|
|
SLICE_X76Y67 FDRE (Hold_fdre_C_D) -0.015 -0.120 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/_zz_ram_port1_reg[4]
|
|
-------------------------------------------------------------------
|
|
required time 0.120
|
|
arrival time 0.585
|
|
-------------------------------------------------------------------
|
|
slack 0.705
|
|
|
|
|
|
|
|
|
|
|
|
---------------------------------------------------------------------------------------------------
|
|
From Clock: mlkem_clk_clk_pll
|
|
To Clock: sys_clk
|
|
|
|
Setup : NA Failing Endpoints, Worst Slack NA , Total Violation NA
|
|
Hold : 0 Failing Endpoints, Worst Slack 0.032ns, Total Violation 0.000ns
|
|
---------------------------------------------------------------------------------------------------
|
|
|
|
|
|
Min Delay Paths
|
|
--------------------------------------------------------------------------------------
|
|
Slack (MET) : 0.032ns (arrival time - required time)
|
|
Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_30_35/RAMC/CLK
|
|
(rising edge-triggered cell RAMD32 clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns})
|
|
Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[34]/D
|
|
(rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Path Group: sys_clk
|
|
Path Type: Hold (Min at Fast Process Corner)
|
|
Requirement: 0.000ns (sys_clk rise@0.000ns - mlkem_clk_clk_pll rise@0.000ns)
|
|
Data Path Delay: 0.560ns (logic 0.390ns (69.595%) route 0.170ns (30.405%))
|
|
Logic Levels: 0
|
|
Clock Path Skew: 0.328ns (DCD - SCD - CPR)
|
|
Destination Clock Delay (DCD): -0.352ns
|
|
Source Clock Delay (SCD): -0.581ns
|
|
Clock Pessimism Removal (CPR): -0.099ns
|
|
Clock Uncertainty: 0.197ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Discrete Jitter (DJ): 0.136ns
|
|
Phase Error (PE): 0.120ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock mlkem_clk_clk_pll rise edge)
|
|
0.000 0.000 r
|
|
K21 0.000 0.000 r clk (IN)
|
|
net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1
|
|
K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O
|
|
net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll
|
|
PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2)
|
|
-2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2
|
|
net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll
|
|
BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout3_buf/O
|
|
net (fo=26129, routed) 0.681 -0.581 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_30_35/WCLK
|
|
SLICE_X20Y76 RAMD32 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_30_35/RAMC/CLK
|
|
------------------------------------------------------------------- -------------------
|
|
SLICE_X20Y76 RAMD32 (Prop_ramd32_CLK_O)
|
|
0.390 -0.191 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_30_35/RAMC/O
|
|
net (fo=1, routed) 0.170 -0.021 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port10__3[34]
|
|
SLICE_X19Y76 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[34]/D
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock sys_clk rise edge) 0.000 0.000 r
|
|
K21 0.000 0.000 r clk (IN)
|
|
net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1
|
|
K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O
|
|
net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll
|
|
PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1)
|
|
-2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1
|
|
net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll
|
|
BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O
|
|
net (fo=10004, routed) 0.956 -0.352 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/sys_clk
|
|
SLICE_X19Y76 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[34]/C
|
|
clock pessimism 0.099 -0.253
|
|
clock uncertainty 0.197 -0.057
|
|
SLICE_X19Y76 FDRE (Hold_fdre_C_D) 0.004 -0.053 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[34]
|
|
-------------------------------------------------------------------
|
|
required time 0.053
|
|
arrival time -0.021
|
|
-------------------------------------------------------------------
|
|
slack 0.032
|
|
|
|
Slack (MET) : 0.042ns (arrival time - required time)
|
|
Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_36_39/RAMB/CLK
|
|
(rising edge-triggered cell RAMD32 clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns})
|
|
Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[38]/D
|
|
(rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Path Group: sys_clk
|
|
Path Type: Hold (Min at Fast Process Corner)
|
|
Requirement: 0.000ns (sys_clk rise@0.000ns - mlkem_clk_clk_pll rise@0.000ns)
|
|
Data Path Delay: 0.558ns (logic 0.394ns (70.575%) route 0.164ns (29.425%))
|
|
Logic Levels: 0
|
|
Clock Path Skew: 0.327ns (DCD - SCD - CPR)
|
|
Destination Clock Delay (DCD): -0.349ns
|
|
Source Clock Delay (SCD): -0.577ns
|
|
Clock Pessimism Removal (CPR): -0.099ns
|
|
Clock Uncertainty: 0.197ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Discrete Jitter (DJ): 0.136ns
|
|
Phase Error (PE): 0.120ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock mlkem_clk_clk_pll rise edge)
|
|
0.000 0.000 r
|
|
K21 0.000 0.000 r clk (IN)
|
|
net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1
|
|
K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O
|
|
net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll
|
|
PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2)
|
|
-2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2
|
|
net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll
|
|
BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout3_buf/O
|
|
net (fo=26129, routed) 0.685 -0.577 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_36_39/WCLK
|
|
SLICE_X18Y78 RAMD32 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_36_39/RAMB/CLK
|
|
------------------------------------------------------------------- -------------------
|
|
SLICE_X18Y78 RAMD32 (Prop_ramd32_CLK_O)
|
|
0.394 -0.183 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_36_39/RAMB/O
|
|
net (fo=1, routed) 0.164 -0.019 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port10__3[38]
|
|
SLICE_X17Y78 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[38]/D
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock sys_clk rise edge) 0.000 0.000 r
|
|
K21 0.000 0.000 r clk (IN)
|
|
net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1
|
|
K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O
|
|
net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll
|
|
PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1)
|
|
-2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1
|
|
net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll
|
|
BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O
|
|
net (fo=10004, routed) 0.959 -0.349 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/sys_clk
|
|
SLICE_X17Y78 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[38]/C
|
|
clock pessimism 0.099 -0.250
|
|
clock uncertainty 0.197 -0.054
|
|
SLICE_X17Y78 FDRE (Hold_fdre_C_D) -0.007 -0.061 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[38]
|
|
-------------------------------------------------------------------
|
|
required time 0.061
|
|
arrival time -0.019
|
|
-------------------------------------------------------------------
|
|
slack 0.042
|
|
|
|
Slack (MET) : 0.066ns (arrival time - required time)
|
|
Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_18_23/RAMC_D1/CLK
|
|
(rising edge-triggered cell RAMD32 clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns})
|
|
Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[23]/D
|
|
(rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Path Group: sys_clk
|
|
Path Type: Hold (Min at Fast Process Corner)
|
|
Requirement: 0.000ns (sys_clk rise@0.000ns - mlkem_clk_clk_pll rise@0.000ns)
|
|
Data Path Delay: 0.647ns (logic 0.386ns (59.641%) route 0.261ns (40.359%))
|
|
Logic Levels: 0
|
|
Clock Path Skew: 0.333ns (DCD - SCD - CPR)
|
|
Destination Clock Delay (DCD): -0.393ns
|
|
Source Clock Delay (SCD): -0.627ns
|
|
Clock Pessimism Removal (CPR): -0.099ns
|
|
Clock Uncertainty: 0.197ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Discrete Jitter (DJ): 0.136ns
|
|
Phase Error (PE): 0.120ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock mlkem_clk_clk_pll rise edge)
|
|
0.000 0.000 r
|
|
K21 0.000 0.000 r clk (IN)
|
|
net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1
|
|
K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O
|
|
net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll
|
|
PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2)
|
|
-2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2
|
|
net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll
|
|
BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout3_buf/O
|
|
net (fo=26129, routed) 0.635 -0.627 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_18_23/WCLK
|
|
SLICE_X64Y75 RAMD32 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_18_23/RAMC_D1/CLK
|
|
------------------------------------------------------------------- -------------------
|
|
SLICE_X64Y75 RAMD32 (Prop_ramd32_CLK_O)
|
|
0.386 -0.241 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_18_23/RAMC_D1/O
|
|
net (fo=1, routed) 0.261 0.020 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port10__3[23]
|
|
SLICE_X62Y81 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[23]/D
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock sys_clk rise edge) 0.000 0.000 r
|
|
K21 0.000 0.000 r clk (IN)
|
|
net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1
|
|
K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O
|
|
net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll
|
|
PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1)
|
|
-2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1
|
|
net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll
|
|
BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O
|
|
net (fo=10004, routed) 0.915 -0.393 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/sys_clk
|
|
SLICE_X62Y81 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[23]/C
|
|
clock pessimism 0.099 -0.294
|
|
clock uncertainty 0.197 -0.098
|
|
SLICE_X62Y81 FDRE (Hold_fdre_C_D) 0.052 -0.046 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[23]
|
|
-------------------------------------------------------------------
|
|
required time 0.046
|
|
arrival time 0.020
|
|
-------------------------------------------------------------------
|
|
slack 0.066
|
|
|
|
Slack (MET) : 0.085ns (arrival time - required time)
|
|
Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_30_35/RAMC_D1/CLK
|
|
(rising edge-triggered cell RAMD32 clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns})
|
|
Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[35]/D
|
|
(rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Path Group: sys_clk
|
|
Path Type: Hold (Min at Fast Process Corner)
|
|
Requirement: 0.000ns (sys_clk rise@0.000ns - mlkem_clk_clk_pll rise@0.000ns)
|
|
Data Path Delay: 0.665ns (logic 0.386ns (58.079%) route 0.279ns (41.921%))
|
|
Logic Levels: 0
|
|
Clock Path Skew: 0.331ns (DCD - SCD - CPR)
|
|
Destination Clock Delay (DCD): -0.349ns
|
|
Source Clock Delay (SCD): -0.581ns
|
|
Clock Pessimism Removal (CPR): -0.099ns
|
|
Clock Uncertainty: 0.197ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Discrete Jitter (DJ): 0.136ns
|
|
Phase Error (PE): 0.120ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock mlkem_clk_clk_pll rise edge)
|
|
0.000 0.000 r
|
|
K21 0.000 0.000 r clk (IN)
|
|
net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1
|
|
K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O
|
|
net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll
|
|
PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2)
|
|
-2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2
|
|
net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll
|
|
BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout3_buf/O
|
|
net (fo=26129, routed) 0.681 -0.581 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_30_35/WCLK
|
|
SLICE_X20Y76 RAMD32 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_30_35/RAMC_D1/CLK
|
|
------------------------------------------------------------------- -------------------
|
|
SLICE_X20Y76 RAMD32 (Prop_ramd32_CLK_O)
|
|
0.386 -0.195 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_30_35/RAMC_D1/O
|
|
net (fo=1, routed) 0.279 0.083 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port10__3[35]
|
|
SLICE_X14Y78 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[35]/D
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock sys_clk rise edge) 0.000 0.000 r
|
|
K21 0.000 0.000 r clk (IN)
|
|
net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1
|
|
K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O
|
|
net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll
|
|
PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1)
|
|
-2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1
|
|
net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll
|
|
BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O
|
|
net (fo=10004, routed) 0.959 -0.349 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/sys_clk
|
|
SLICE_X14Y78 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[35]/C
|
|
clock pessimism 0.099 -0.250
|
|
clock uncertainty 0.197 -0.054
|
|
SLICE_X14Y78 FDRE (Hold_fdre_C_D) 0.052 -0.002 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[35]
|
|
-------------------------------------------------------------------
|
|
required time 0.002
|
|
arrival time 0.083
|
|
-------------------------------------------------------------------
|
|
slack 0.085
|
|
|
|
Slack (MET) : 0.087ns (arrival time - required time)
|
|
Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_30_35/RAMA/CLK
|
|
(rising edge-triggered cell RAMD32 clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns})
|
|
Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[30]/D
|
|
(rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Path Group: sys_clk
|
|
Path Type: Hold (Min at Fast Process Corner)
|
|
Requirement: 0.000ns (sys_clk rise@0.000ns - mlkem_clk_clk_pll rise@0.000ns)
|
|
Data Path Delay: 0.611ns (logic 0.492ns (80.558%) route 0.119ns (19.442%))
|
|
Logic Levels: 0
|
|
Clock Path Skew: 0.327ns (DCD - SCD - CPR)
|
|
Destination Clock Delay (DCD): -0.353ns
|
|
Source Clock Delay (SCD): -0.581ns
|
|
Clock Pessimism Removal (CPR): -0.099ns
|
|
Clock Uncertainty: 0.197ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Discrete Jitter (DJ): 0.136ns
|
|
Phase Error (PE): 0.120ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock mlkem_clk_clk_pll rise edge)
|
|
0.000 0.000 r
|
|
K21 0.000 0.000 r clk (IN)
|
|
net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1
|
|
K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O
|
|
net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll
|
|
PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2)
|
|
-2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2
|
|
net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll
|
|
BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout3_buf/O
|
|
net (fo=26129, routed) 0.681 -0.581 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_30_35/WCLK
|
|
SLICE_X20Y76 RAMD32 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_30_35/RAMA/CLK
|
|
------------------------------------------------------------------- -------------------
|
|
SLICE_X20Y76 RAMD32 (Prop_ramd32_CLK_O)
|
|
0.492 -0.089 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_30_35/RAMA/O
|
|
net (fo=1, routed) 0.119 0.029 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port10__3[30]
|
|
SLICE_X23Y77 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[30]/D
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock sys_clk rise edge) 0.000 0.000 r
|
|
K21 0.000 0.000 r clk (IN)
|
|
net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1
|
|
K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O
|
|
net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll
|
|
PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1)
|
|
-2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1
|
|
net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll
|
|
BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O
|
|
net (fo=10004, routed) 0.955 -0.353 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/sys_clk
|
|
SLICE_X23Y77 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[30]/C
|
|
clock pessimism 0.099 -0.254
|
|
clock uncertainty 0.197 -0.058
|
|
SLICE_X23Y77 FDRE (Hold_fdre_C_D) 0.000 -0.058 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[30]
|
|
-------------------------------------------------------------------
|
|
required time 0.058
|
|
arrival time 0.029
|
|
-------------------------------------------------------------------
|
|
slack 0.087
|
|
|
|
Slack (MET) : 0.103ns (arrival time - required time)
|
|
Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_36_39/RAMA_D1/CLK
|
|
(rising edge-triggered cell RAMD32 clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns})
|
|
Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[37]/D
|
|
(rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Path Group: sys_clk
|
|
Path Type: Hold (Min at Fast Process Corner)
|
|
Requirement: 0.000ns (sys_clk rise@0.000ns - mlkem_clk_clk_pll rise@0.000ns)
|
|
Data Path Delay: 0.697ns (logic 0.478ns (68.593%) route 0.219ns (31.407%))
|
|
Logic Levels: 0
|
|
Clock Path Skew: 0.327ns (DCD - SCD - CPR)
|
|
Destination Clock Delay (DCD): -0.349ns
|
|
Source Clock Delay (SCD): -0.577ns
|
|
Clock Pessimism Removal (CPR): -0.099ns
|
|
Clock Uncertainty: 0.197ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Discrete Jitter (DJ): 0.136ns
|
|
Phase Error (PE): 0.120ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock mlkem_clk_clk_pll rise edge)
|
|
0.000 0.000 r
|
|
K21 0.000 0.000 r clk (IN)
|
|
net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1
|
|
K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O
|
|
net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll
|
|
PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2)
|
|
-2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2
|
|
net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll
|
|
BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout3_buf/O
|
|
net (fo=26129, routed) 0.685 -0.577 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_36_39/WCLK
|
|
SLICE_X18Y78 RAMD32 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_36_39/RAMA_D1/CLK
|
|
------------------------------------------------------------------- -------------------
|
|
SLICE_X18Y78 RAMD32 (Prop_ramd32_CLK_O)
|
|
0.478 -0.099 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_36_39/RAMA_D1/O
|
|
net (fo=1, routed) 0.219 0.119 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port10__3[37]
|
|
SLICE_X15Y78 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[37]/D
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock sys_clk rise edge) 0.000 0.000 r
|
|
K21 0.000 0.000 r clk (IN)
|
|
net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1
|
|
K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O
|
|
net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll
|
|
PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1)
|
|
-2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1
|
|
net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll
|
|
BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O
|
|
net (fo=10004, routed) 0.959 -0.349 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/sys_clk
|
|
SLICE_X15Y78 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[37]/C
|
|
clock pessimism 0.099 -0.250
|
|
clock uncertainty 0.197 -0.054
|
|
SLICE_X15Y78 FDRE (Hold_fdre_C_D) 0.070 0.016 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[37]
|
|
-------------------------------------------------------------------
|
|
required time -0.016
|
|
arrival time 0.119
|
|
-------------------------------------------------------------------
|
|
slack 0.103
|
|
|
|
Slack (MET) : 0.108ns (arrival time - required time)
|
|
Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_12_17/RAMB_D1/CLK
|
|
(rising edge-triggered cell RAMD32 clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns})
|
|
Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[15]/D
|
|
(rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Path Group: sys_clk
|
|
Path Type: Hold (Min at Fast Process Corner)
|
|
Requirement: 0.000ns (sys_clk rise@0.000ns - mlkem_clk_clk_pll rise@0.000ns)
|
|
Data Path Delay: 0.707ns (logic 0.388ns (54.849%) route 0.319ns (45.151%))
|
|
Logic Levels: 0
|
|
Clock Path Skew: 0.333ns (DCD - SCD - CPR)
|
|
Destination Clock Delay (DCD): -0.392ns
|
|
Source Clock Delay (SCD): -0.626ns
|
|
Clock Pessimism Removal (CPR): -0.099ns
|
|
Clock Uncertainty: 0.197ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Discrete Jitter (DJ): 0.136ns
|
|
Phase Error (PE): 0.120ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock mlkem_clk_clk_pll rise edge)
|
|
0.000 0.000 r
|
|
K21 0.000 0.000 r clk (IN)
|
|
net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1
|
|
K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O
|
|
net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll
|
|
PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2)
|
|
-2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2
|
|
net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll
|
|
BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout3_buf/O
|
|
net (fo=26129, routed) 0.636 -0.626 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_12_17/WCLK
|
|
SLICE_X64Y76 RAMD32 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_12_17/RAMB_D1/CLK
|
|
------------------------------------------------------------------- -------------------
|
|
SLICE_X64Y76 RAMD32 (Prop_ramd32_CLK_O)
|
|
0.388 -0.238 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_12_17/RAMB_D1/O
|
|
net (fo=1, routed) 0.319 0.081 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port10__3[15]
|
|
SLICE_X57Y78 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[15]/D
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock sys_clk rise edge) 0.000 0.000 r
|
|
K21 0.000 0.000 r clk (IN)
|
|
net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1
|
|
K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O
|
|
net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll
|
|
PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1)
|
|
-2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1
|
|
net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll
|
|
BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O
|
|
net (fo=10004, routed) 0.916 -0.392 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/sys_clk
|
|
SLICE_X57Y78 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[15]/C
|
|
clock pessimism 0.099 -0.293
|
|
clock uncertainty 0.197 -0.097
|
|
SLICE_X57Y78 FDRE (Hold_fdre_C_D) 0.070 -0.027 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[15]
|
|
-------------------------------------------------------------------
|
|
required time 0.027
|
|
arrival time 0.081
|
|
-------------------------------------------------------------------
|
|
slack 0.108
|
|
|
|
Slack (MET) : 0.121ns (arrival time - required time)
|
|
Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_18_23/RAMB_D1/CLK
|
|
(rising edge-triggered cell RAMD32 clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns})
|
|
Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[21]/D
|
|
(rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Path Group: sys_clk
|
|
Path Type: Hold (Min at Fast Process Corner)
|
|
Requirement: 0.000ns (sys_clk rise@0.000ns - mlkem_clk_clk_pll rise@0.000ns)
|
|
Data Path Delay: 0.723ns (logic 0.388ns (53.631%) route 0.335ns (46.369%))
|
|
Logic Levels: 0
|
|
Clock Path Skew: 0.334ns (DCD - SCD - CPR)
|
|
Destination Clock Delay (DCD): -0.392ns
|
|
Source Clock Delay (SCD): -0.627ns
|
|
Clock Pessimism Removal (CPR): -0.099ns
|
|
Clock Uncertainty: 0.197ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Discrete Jitter (DJ): 0.136ns
|
|
Phase Error (PE): 0.120ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock mlkem_clk_clk_pll rise edge)
|
|
0.000 0.000 r
|
|
K21 0.000 0.000 r clk (IN)
|
|
net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1
|
|
K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O
|
|
net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll
|
|
PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2)
|
|
-2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2
|
|
net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll
|
|
BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout3_buf/O
|
|
net (fo=26129, routed) 0.635 -0.627 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_18_23/WCLK
|
|
SLICE_X64Y75 RAMD32 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_18_23/RAMB_D1/CLK
|
|
------------------------------------------------------------------- -------------------
|
|
SLICE_X64Y75 RAMD32 (Prop_ramd32_CLK_O)
|
|
0.388 -0.239 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_18_23/RAMB_D1/O
|
|
net (fo=1, routed) 0.335 0.096 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port10__3[21]
|
|
SLICE_X57Y78 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[21]/D
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock sys_clk rise edge) 0.000 0.000 r
|
|
K21 0.000 0.000 r clk (IN)
|
|
net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1
|
|
K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O
|
|
net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll
|
|
PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1)
|
|
-2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1
|
|
net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll
|
|
BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O
|
|
net (fo=10004, routed) 0.916 -0.392 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/sys_clk
|
|
SLICE_X57Y78 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[21]/C
|
|
clock pessimism 0.099 -0.293
|
|
clock uncertainty 0.197 -0.097
|
|
SLICE_X57Y78 FDRE (Hold_fdre_C_D) 0.072 -0.025 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[21]
|
|
-------------------------------------------------------------------
|
|
required time 0.025
|
|
arrival time 0.096
|
|
-------------------------------------------------------------------
|
|
slack 0.121
|
|
|
|
Slack (MET) : 0.128ns (arrival time - required time)
|
|
Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_36_39/RAMA/CLK
|
|
(rising edge-triggered cell RAMD32 clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns})
|
|
Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[36]/D
|
|
(rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Path Group: sys_clk
|
|
Path Type: Hold (Min at Fast Process Corner)
|
|
Requirement: 0.000ns (sys_clk rise@0.000ns - mlkem_clk_clk_pll rise@0.000ns)
|
|
Data Path Delay: 0.656ns (logic 0.492ns (75.032%) route 0.164ns (24.968%))
|
|
Logic Levels: 0
|
|
Clock Path Skew: 0.327ns (DCD - SCD - CPR)
|
|
Destination Clock Delay (DCD): -0.349ns
|
|
Source Clock Delay (SCD): -0.577ns
|
|
Clock Pessimism Removal (CPR): -0.099ns
|
|
Clock Uncertainty: 0.197ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Discrete Jitter (DJ): 0.136ns
|
|
Phase Error (PE): 0.120ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock mlkem_clk_clk_pll rise edge)
|
|
0.000 0.000 r
|
|
K21 0.000 0.000 r clk (IN)
|
|
net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1
|
|
K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O
|
|
net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll
|
|
PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2)
|
|
-2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2
|
|
net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll
|
|
BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout3_buf/O
|
|
net (fo=26129, routed) 0.685 -0.577 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_36_39/WCLK
|
|
SLICE_X18Y78 RAMD32 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_36_39/RAMA/CLK
|
|
------------------------------------------------------------------- -------------------
|
|
SLICE_X18Y78 RAMD32 (Prop_ramd32_CLK_O)
|
|
0.492 -0.085 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_36_39/RAMA/O
|
|
net (fo=1, routed) 0.164 0.078 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port10__3[36]
|
|
SLICE_X17Y78 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[36]/D
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock sys_clk rise edge) 0.000 0.000 r
|
|
K21 0.000 0.000 r clk (IN)
|
|
net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1
|
|
K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O
|
|
net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll
|
|
PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1)
|
|
-2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1
|
|
net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll
|
|
BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O
|
|
net (fo=10004, routed) 0.959 -0.349 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/sys_clk
|
|
SLICE_X17Y78 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[36]/C
|
|
clock pessimism 0.099 -0.250
|
|
clock uncertainty 0.197 -0.054
|
|
SLICE_X17Y78 FDRE (Hold_fdre_C_D) 0.004 -0.050 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[36]
|
|
-------------------------------------------------------------------
|
|
required time 0.050
|
|
arrival time 0.078
|
|
-------------------------------------------------------------------
|
|
slack 0.128
|
|
|
|
Slack (MET) : 0.130ns (arrival time - required time)
|
|
Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_30_35/RAMB/CLK
|
|
(rising edge-triggered cell RAMD32 clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns})
|
|
Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[32]/D
|
|
(rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Path Group: sys_clk
|
|
Path Type: Hold (Min at Fast Process Corner)
|
|
Requirement: 0.000ns (sys_clk rise@0.000ns - mlkem_clk_clk_pll rise@0.000ns)
|
|
Data Path Delay: 0.648ns (logic 0.394ns (60.840%) route 0.254ns (39.160%))
|
|
Logic Levels: 0
|
|
Clock Path Skew: 0.328ns (DCD - SCD - CPR)
|
|
Destination Clock Delay (DCD): -0.352ns
|
|
Source Clock Delay (SCD): -0.581ns
|
|
Clock Pessimism Removal (CPR): -0.099ns
|
|
Clock Uncertainty: 0.197ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Discrete Jitter (DJ): 0.136ns
|
|
Phase Error (PE): 0.120ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock mlkem_clk_clk_pll rise edge)
|
|
0.000 0.000 r
|
|
K21 0.000 0.000 r clk (IN)
|
|
net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1
|
|
K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O
|
|
net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll
|
|
PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2)
|
|
-2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2
|
|
net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll
|
|
BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout3_buf/O
|
|
net (fo=26129, routed) 0.681 -0.581 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_30_35/WCLK
|
|
SLICE_X20Y76 RAMD32 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_30_35/RAMB/CLK
|
|
------------------------------------------------------------------- -------------------
|
|
SLICE_X20Y76 RAMD32 (Prop_ramd32_CLK_O)
|
|
0.394 -0.187 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_30_35/RAMB/O
|
|
net (fo=1, routed) 0.254 0.066 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port10__3[32]
|
|
SLICE_X19Y76 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[32]/D
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock sys_clk rise edge) 0.000 0.000 r
|
|
K21 0.000 0.000 r clk (IN)
|
|
net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1
|
|
K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O
|
|
net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll
|
|
PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1)
|
|
-2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1
|
|
net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll
|
|
BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O
|
|
net (fo=10004, routed) 0.956 -0.352 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/sys_clk
|
|
SLICE_X19Y76 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[32]/C
|
|
clock pessimism 0.099 -0.253
|
|
clock uncertainty 0.197 -0.057
|
|
SLICE_X19Y76 FDRE (Hold_fdre_C_D) -0.007 -0.064 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[32]
|
|
-------------------------------------------------------------------
|
|
required time 0.064
|
|
arrival time 0.066
|
|
-------------------------------------------------------------------
|
|
slack 0.130
|
|
|
|
Slack (MET) : 0.142ns (arrival time - required time)
|
|
Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_24_29/RAMA_D1/CLK
|
|
(rising edge-triggered cell RAMD32 clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns})
|
|
Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[25]/D
|
|
(rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Path Group: sys_clk
|
|
Path Type: Hold (Min at Fast Process Corner)
|
|
Requirement: 0.000ns (sys_clk rise@0.000ns - mlkem_clk_clk_pll rise@0.000ns)
|
|
Data Path Delay: 0.739ns (logic 0.478ns (64.724%) route 0.261ns (35.276%))
|
|
Logic Levels: 0
|
|
Clock Path Skew: 0.328ns (DCD - SCD - CPR)
|
|
Destination Clock Delay (DCD): -0.395ns
|
|
Source Clock Delay (SCD): -0.624ns
|
|
Clock Pessimism Removal (CPR): -0.099ns
|
|
Clock Uncertainty: 0.197ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Discrete Jitter (DJ): 0.136ns
|
|
Phase Error (PE): 0.120ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock mlkem_clk_clk_pll rise edge)
|
|
0.000 0.000 r
|
|
K21 0.000 0.000 r clk (IN)
|
|
net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1
|
|
K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O
|
|
net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll
|
|
PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2)
|
|
-2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2
|
|
net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll
|
|
BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout3_buf/O
|
|
net (fo=26129, routed) 0.638 -0.624 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_24_29/WCLK
|
|
SLICE_X64Y77 RAMD32 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_24_29/RAMA_D1/CLK
|
|
------------------------------------------------------------------- -------------------
|
|
SLICE_X64Y77 RAMD32 (Prop_ramd32_CLK_O)
|
|
0.478 -0.146 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_24_29/RAMA_D1/O
|
|
net (fo=1, routed) 0.261 0.114 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port10__3[25]
|
|
SLICE_X61Y77 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[25]/D
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock sys_clk rise edge) 0.000 0.000 r
|
|
K21 0.000 0.000 r clk (IN)
|
|
net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1
|
|
K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O
|
|
net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll
|
|
PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1)
|
|
-2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1
|
|
net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll
|
|
BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O
|
|
net (fo=10004, routed) 0.913 -0.395 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/sys_clk
|
|
SLICE_X61Y77 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[25]/C
|
|
clock pessimism 0.099 -0.296
|
|
clock uncertainty 0.197 -0.100
|
|
SLICE_X61Y77 FDRE (Hold_fdre_C_D) 0.072 -0.028 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[25]
|
|
-------------------------------------------------------------------
|
|
required time 0.028
|
|
arrival time 0.114
|
|
-------------------------------------------------------------------
|
|
slack 0.142
|
|
|
|
Slack (MET) : 0.148ns (arrival time - required time)
|
|
Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_18_23/RAMA/CLK
|
|
(rising edge-triggered cell RAMD32 clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns})
|
|
Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[18]/D
|
|
(rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Path Group: sys_clk
|
|
Path Type: Hold (Min at Fast Process Corner)
|
|
Requirement: 0.000ns (sys_clk rise@0.000ns - mlkem_clk_clk_pll rise@0.000ns)
|
|
Data Path Delay: 0.665ns (logic 0.492ns (73.994%) route 0.173ns (26.006%))
|
|
Logic Levels: 0
|
|
Clock Path Skew: 0.327ns (DCD - SCD - CPR)
|
|
Destination Clock Delay (DCD): -0.399ns
|
|
Source Clock Delay (SCD): -0.627ns
|
|
Clock Pessimism Removal (CPR): -0.099ns
|
|
Clock Uncertainty: 0.197ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Discrete Jitter (DJ): 0.136ns
|
|
Phase Error (PE): 0.120ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock mlkem_clk_clk_pll rise edge)
|
|
0.000 0.000 r
|
|
K21 0.000 0.000 r clk (IN)
|
|
net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1
|
|
K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O
|
|
net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll
|
|
PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2)
|
|
-2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2
|
|
net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll
|
|
BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout3_buf/O
|
|
net (fo=26129, routed) 0.635 -0.627 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_18_23/WCLK
|
|
SLICE_X64Y75 RAMD32 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_18_23/RAMA/CLK
|
|
------------------------------------------------------------------- -------------------
|
|
SLICE_X64Y75 RAMD32 (Prop_ramd32_CLK_O)
|
|
0.492 -0.135 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_18_23/RAMA/O
|
|
net (fo=1, routed) 0.173 0.038 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port10__3[18]
|
|
SLICE_X62Y76 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[18]/D
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock sys_clk rise edge) 0.000 0.000 r
|
|
K21 0.000 0.000 r clk (IN)
|
|
net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1
|
|
K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O
|
|
net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll
|
|
PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1)
|
|
-2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1
|
|
net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll
|
|
BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O
|
|
net (fo=10004, routed) 0.909 -0.399 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/sys_clk
|
|
SLICE_X62Y76 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[18]/C
|
|
clock pessimism 0.099 -0.300
|
|
clock uncertainty 0.197 -0.104
|
|
SLICE_X62Y76 FDRE (Hold_fdre_C_D) -0.007 -0.111 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[18]
|
|
-------------------------------------------------------------------
|
|
required time 0.111
|
|
arrival time 0.038
|
|
-------------------------------------------------------------------
|
|
slack 0.148
|
|
|
|
Slack (MET) : 0.172ns (arrival time - required time)
|
|
Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_24_29/RAMC/CLK
|
|
(rising edge-triggered cell RAMD32 clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns})
|
|
Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[28]/D
|
|
(rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Path Group: sys_clk
|
|
Path Type: Hold (Min at Fast Process Corner)
|
|
Requirement: 0.000ns (sys_clk rise@0.000ns - mlkem_clk_clk_pll rise@0.000ns)
|
|
Data Path Delay: 0.699ns (logic 0.390ns (55.761%) route 0.309ns (44.239%))
|
|
Logic Levels: 0
|
|
Clock Path Skew: 0.328ns (DCD - SCD - CPR)
|
|
Destination Clock Delay (DCD): -0.395ns
|
|
Source Clock Delay (SCD): -0.624ns
|
|
Clock Pessimism Removal (CPR): -0.099ns
|
|
Clock Uncertainty: 0.197ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Discrete Jitter (DJ): 0.136ns
|
|
Phase Error (PE): 0.120ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock mlkem_clk_clk_pll rise edge)
|
|
0.000 0.000 r
|
|
K21 0.000 0.000 r clk (IN)
|
|
net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1
|
|
K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O
|
|
net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll
|
|
PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2)
|
|
-2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2
|
|
net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll
|
|
BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout3_buf/O
|
|
net (fo=26129, routed) 0.638 -0.624 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_24_29/WCLK
|
|
SLICE_X64Y77 RAMD32 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_24_29/RAMC/CLK
|
|
------------------------------------------------------------------- -------------------
|
|
SLICE_X64Y77 RAMD32 (Prop_ramd32_CLK_O)
|
|
0.390 -0.234 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_24_29/RAMC/O
|
|
net (fo=1, routed) 0.309 0.075 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port10__3[28]
|
|
SLICE_X61Y77 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[28]/D
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock sys_clk rise edge) 0.000 0.000 r
|
|
K21 0.000 0.000 r clk (IN)
|
|
net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1
|
|
K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O
|
|
net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll
|
|
PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1)
|
|
-2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1
|
|
net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll
|
|
BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O
|
|
net (fo=10004, routed) 0.913 -0.395 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/sys_clk
|
|
SLICE_X61Y77 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[28]/C
|
|
clock pessimism 0.099 -0.296
|
|
clock uncertainty 0.197 -0.100
|
|
SLICE_X61Y77 FDRE (Hold_fdre_C_D) 0.003 -0.097 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[28]
|
|
-------------------------------------------------------------------
|
|
required time 0.097
|
|
arrival time 0.075
|
|
-------------------------------------------------------------------
|
|
slack 0.172
|
|
|
|
Slack (MET) : 0.172ns (arrival time - required time)
|
|
Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/popCC_ptrToPush_reg[1]/C
|
|
(rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns})
|
|
Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/popToPushGray_buffercc/buffers_0_reg[1]/D
|
|
(rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Path Group: sys_clk
|
|
Path Type: Hold (Min at Fast Process Corner)
|
|
Requirement: 0.000ns (sys_clk rise@0.000ns - mlkem_clk_clk_pll rise@0.000ns)
|
|
Data Path Delay: 0.741ns (logic 0.141ns (19.033%) route 0.600ns (80.967%))
|
|
Logic Levels: 0
|
|
Clock Path Skew: 0.325ns (DCD - SCD - CPR)
|
|
Destination Clock Delay (DCD): -0.389ns
|
|
Source Clock Delay (SCD): -0.615ns
|
|
Clock Pessimism Removal (CPR): -0.099ns
|
|
Clock Uncertainty: 0.197ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Discrete Jitter (DJ): 0.136ns
|
|
Phase Error (PE): 0.120ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock mlkem_clk_clk_pll rise edge)
|
|
0.000 0.000 r
|
|
K21 0.000 0.000 r clk (IN)
|
|
net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1
|
|
K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O
|
|
net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll
|
|
PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2)
|
|
-2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2
|
|
net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll
|
|
BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout3_buf/O
|
|
net (fo=26129, routed) 0.647 -0.615 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/mlkem_clk
|
|
SLICE_X114Y75 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/popCC_ptrToPush_reg[1]/C
|
|
------------------------------------------------------------------- -------------------
|
|
SLICE_X114Y75 FDCE (Prop_fdce_C_Q) 0.141 -0.474 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/popCC_ptrToPush_reg[1]/Q
|
|
net (fo=1, routed) 0.600 0.125 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/popToPushGray_buffercc/Q[1]
|
|
SLICE_X113Y75 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/popToPushGray_buffercc/buffers_0_reg[1]/D
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock sys_clk rise edge) 0.000 0.000 r
|
|
K21 0.000 0.000 r clk (IN)
|
|
net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1
|
|
K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O
|
|
net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll
|
|
PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1)
|
|
-2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1
|
|
net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll
|
|
BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O
|
|
net (fo=10004, routed) 0.919 -0.389 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/popToPushGray_buffercc/sys_clk
|
|
SLICE_X113Y75 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/popToPushGray_buffercc/buffers_0_reg[1]/C
|
|
clock pessimism 0.099 -0.290
|
|
clock uncertainty 0.197 -0.094
|
|
SLICE_X113Y75 FDCE (Hold_fdce_C_D) 0.047 -0.047 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/popToPushGray_buffercc/buffers_0_reg[1]
|
|
-------------------------------------------------------------------
|
|
required time 0.047
|
|
arrival time 0.125
|
|
-------------------------------------------------------------------
|
|
slack 0.172
|
|
|
|
Slack (MET) : 0.173ns (arrival time - required time)
|
|
Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/ram_reg_0_3_0_5/RAMC/CLK
|
|
(rising edge-triggered cell RAMD32 clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns})
|
|
Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/_zz_ram_port1_reg[4]/D
|
|
(rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Path Group: sys_clk
|
|
Path Type: Hold (Min at Fast Process Corner)
|
|
Requirement: 0.000ns (sys_clk rise@0.000ns - mlkem_clk_clk_pll rise@0.000ns)
|
|
Data Path Delay: 0.695ns (logic 0.390ns (56.076%) route 0.305ns (43.924%))
|
|
Logic Levels: 0
|
|
Clock Path Skew: 0.322ns (DCD - SCD - CPR)
|
|
Destination Clock Delay (DCD): -0.357ns
|
|
Source Clock Delay (SCD): -0.580ns
|
|
Clock Pessimism Removal (CPR): -0.099ns
|
|
Clock Uncertainty: 0.197ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Discrete Jitter (DJ): 0.136ns
|
|
Phase Error (PE): 0.120ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock mlkem_clk_clk_pll rise edge)
|
|
0.000 0.000 r
|
|
K21 0.000 0.000 r clk (IN)
|
|
net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1
|
|
K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O
|
|
net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll
|
|
PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2)
|
|
-2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2
|
|
net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll
|
|
BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout3_buf/O
|
|
net (fo=26129, routed) 0.682 -0.580 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/ram_reg_0_3_0_5/WCLK
|
|
SLICE_X22Y72 RAMD32 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/ram_reg_0_3_0_5/RAMC/CLK
|
|
------------------------------------------------------------------- -------------------
|
|
SLICE_X22Y72 RAMD32 (Prop_ramd32_CLK_O)
|
|
0.390 -0.190 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/ram_reg_0_3_0_5/RAMC/O
|
|
net (fo=1, routed) 0.305 0.115 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/_zz_ram_port10__1[4]
|
|
SLICE_X28Y72 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/_zz_ram_port1_reg[4]/D
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock sys_clk rise edge) 0.000 0.000 r
|
|
K21 0.000 0.000 r clk (IN)
|
|
net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1
|
|
K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O
|
|
net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll
|
|
PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1)
|
|
-2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1
|
|
net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll
|
|
BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O
|
|
net (fo=10004, routed) 0.951 -0.357 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/sys_clk
|
|
SLICE_X28Y72 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/_zz_ram_port1_reg[4]/C
|
|
clock pessimism 0.099 -0.258
|
|
clock uncertainty 0.197 -0.062
|
|
SLICE_X28Y72 FDRE (Hold_fdre_C_D) 0.004 -0.058 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/_zz_ram_port1_reg[4]
|
|
-------------------------------------------------------------------
|
|
required time 0.058
|
|
arrival time 0.115
|
|
-------------------------------------------------------------------
|
|
slack 0.173
|
|
|
|
Slack (MET) : 0.178ns (arrival time - required time)
|
|
Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/pushCC_pushPtrGray_reg[2]/C
|
|
(rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns})
|
|
Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/pushToPopGray_buffercc/buffers_0_reg[2]/D
|
|
(rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Path Group: sys_clk
|
|
Path Type: Hold (Min at Fast Process Corner)
|
|
Requirement: 0.000ns (sys_clk rise@0.000ns - mlkem_clk_clk_pll rise@0.000ns)
|
|
Data Path Delay: 0.764ns (logic 0.141ns (18.448%) route 0.623ns (81.552%))
|
|
Logic Levels: 0
|
|
Clock Path Skew: 0.329ns (DCD - SCD - CPR)
|
|
Destination Clock Delay (DCD): -0.341ns
|
|
Source Clock Delay (SCD): -0.571ns
|
|
Clock Pessimism Removal (CPR): -0.099ns
|
|
Clock Uncertainty: 0.197ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Discrete Jitter (DJ): 0.136ns
|
|
Phase Error (PE): 0.120ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock mlkem_clk_clk_pll rise edge)
|
|
0.000 0.000 r
|
|
K21 0.000 0.000 r clk (IN)
|
|
net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1
|
|
K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O
|
|
net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll
|
|
PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2)
|
|
-2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2
|
|
net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll
|
|
BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout3_buf/O
|
|
net (fo=26129, routed) 0.691 -0.571 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/mlkem_clk
|
|
SLICE_X15Y86 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/pushCC_pushPtrGray_reg[2]/C
|
|
------------------------------------------------------------------- -------------------
|
|
SLICE_X15Y86 FDCE (Prop_fdce_C_Q) 0.141 -0.430 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/pushCC_pushPtrGray_reg[2]/Q
|
|
net (fo=3, routed) 0.623 0.193 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/pushToPopGray_buffercc/D[2]
|
|
SLICE_X15Y87 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/pushToPopGray_buffercc/buffers_0_reg[2]/D
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock sys_clk rise edge) 0.000 0.000 r
|
|
K21 0.000 0.000 r clk (IN)
|
|
net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1
|
|
K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O
|
|
net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll
|
|
PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1)
|
|
-2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1
|
|
net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll
|
|
BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O
|
|
net (fo=10004, routed) 0.967 -0.341 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/pushToPopGray_buffercc/sys_clk
|
|
SLICE_X15Y87 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/pushToPopGray_buffercc/buffers_0_reg[2]/C
|
|
clock pessimism 0.099 -0.242
|
|
clock uncertainty 0.197 -0.046
|
|
SLICE_X15Y87 FDCE (Hold_fdce_C_D) 0.061 0.015 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/pushToPopGray_buffercc/buffers_0_reg[2]
|
|
-------------------------------------------------------------------
|
|
required time -0.015
|
|
arrival time 0.193
|
|
-------------------------------------------------------------------
|
|
slack 0.178
|
|
|
|
Slack (MET) : 0.180ns (arrival time - required time)
|
|
Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_12_17/RAMC/CLK
|
|
(rising edge-triggered cell RAMD32 clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns})
|
|
Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[16]/D
|
|
(rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Path Group: sys_clk
|
|
Path Type: Hold (Min at Fast Process Corner)
|
|
Requirement: 0.000ns (sys_clk rise@0.000ns - mlkem_clk_clk_pll rise@0.000ns)
|
|
Data Path Delay: 0.709ns (logic 0.390ns (55.003%) route 0.319ns (44.997%))
|
|
Logic Levels: 0
|
|
Clock Path Skew: 0.330ns (DCD - SCD - CPR)
|
|
Destination Clock Delay (DCD): -0.395ns
|
|
Source Clock Delay (SCD): -0.626ns
|
|
Clock Pessimism Removal (CPR): -0.099ns
|
|
Clock Uncertainty: 0.197ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Discrete Jitter (DJ): 0.136ns
|
|
Phase Error (PE): 0.120ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock mlkem_clk_clk_pll rise edge)
|
|
0.000 0.000 r
|
|
K21 0.000 0.000 r clk (IN)
|
|
net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1
|
|
K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O
|
|
net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll
|
|
PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2)
|
|
-2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2
|
|
net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll
|
|
BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout3_buf/O
|
|
net (fo=26129, routed) 0.636 -0.626 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_12_17/WCLK
|
|
SLICE_X64Y76 RAMD32 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_12_17/RAMC/CLK
|
|
------------------------------------------------------------------- -------------------
|
|
SLICE_X64Y76 RAMD32 (Prop_ramd32_CLK_O)
|
|
0.390 -0.236 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_12_17/RAMC/O
|
|
net (fo=1, routed) 0.319 0.083 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port10__3[16]
|
|
SLICE_X61Y77 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[16]/D
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock sys_clk rise edge) 0.000 0.000 r
|
|
K21 0.000 0.000 r clk (IN)
|
|
net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1
|
|
K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O
|
|
net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll
|
|
PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1)
|
|
-2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1
|
|
net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll
|
|
BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O
|
|
net (fo=10004, routed) 0.913 -0.395 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/sys_clk
|
|
SLICE_X61Y77 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[16]/C
|
|
clock pessimism 0.099 -0.296
|
|
clock uncertainty 0.197 -0.100
|
|
SLICE_X61Y77 FDRE (Hold_fdre_C_D) 0.002 -0.098 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[16]
|
|
-------------------------------------------------------------------
|
|
required time 0.098
|
|
arrival time 0.083
|
|
-------------------------------------------------------------------
|
|
slack 0.180
|
|
|
|
Slack (MET) : 0.187ns (arrival time - required time)
|
|
Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/done_sync_reg[1]/C
|
|
(rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns})
|
|
Destination: u_fft_mlkem_axi_slave/mlkem_intr_sync_reg[0]/D
|
|
(rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Path Group: sys_clk
|
|
Path Type: Hold (Min at Fast Process Corner)
|
|
Requirement: 0.000ns (sys_clk rise@0.000ns - mlkem_clk_clk_pll rise@0.000ns)
|
|
Data Path Delay: 0.766ns (logic 0.164ns (21.399%) route 0.602ns (78.601%))
|
|
Logic Levels: 0
|
|
Clock Path Skew: 0.337ns (DCD - SCD - CPR)
|
|
Destination Clock Delay (DCD): -0.374ns
|
|
Source Clock Delay (SCD): -0.612ns
|
|
Clock Pessimism Removal (CPR): -0.099ns
|
|
Clock Uncertainty: 0.197ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Discrete Jitter (DJ): 0.136ns
|
|
Phase Error (PE): 0.120ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock mlkem_clk_clk_pll rise edge)
|
|
0.000 0.000 r
|
|
K21 0.000 0.000 r clk (IN)
|
|
net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1
|
|
K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O
|
|
net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll
|
|
PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2)
|
|
-2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2
|
|
net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll
|
|
BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout3_buf/O
|
|
net (fo=26129, routed) 0.650 -0.612 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/mlkem_clk
|
|
SLICE_X112Y71 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/done_sync_reg[1]/C
|
|
------------------------------------------------------------------- -------------------
|
|
SLICE_X112Y71 FDCE (Prop_fdce_C_Q) 0.164 -0.448 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/done_sync_reg[1]/Q
|
|
net (fo=2, routed) 0.602 0.154 u_fft_mlkem_axi_slave/mlkem_intr_m
|
|
SLICE_X117Y61 FDCE r u_fft_mlkem_axi_slave/mlkem_intr_sync_reg[0]/D
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock sys_clk rise edge) 0.000 0.000 r
|
|
K21 0.000 0.000 r clk (IN)
|
|
net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1
|
|
K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O
|
|
net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll
|
|
PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1)
|
|
-2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1
|
|
net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll
|
|
BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O
|
|
net (fo=10004, routed) 0.934 -0.374 u_fft_mlkem_axi_slave/sys_clk
|
|
SLICE_X117Y61 FDCE r u_fft_mlkem_axi_slave/mlkem_intr_sync_reg[0]/C
|
|
clock pessimism 0.099 -0.275
|
|
clock uncertainty 0.197 -0.079
|
|
SLICE_X117Y61 FDCE (Hold_fdce_C_D) 0.046 -0.033 u_fft_mlkem_axi_slave/mlkem_intr_sync_reg[0]
|
|
-------------------------------------------------------------------
|
|
required time 0.033
|
|
arrival time 0.154
|
|
-------------------------------------------------------------------
|
|
slack 0.187
|
|
|
|
Slack (MET) : 0.189ns (arrival time - required time)
|
|
Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/popCC_ptrToPush_reg[3]/C
|
|
(rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns})
|
|
Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/popToPushGray_buffercc/buffers_0_reg[3]/D
|
|
(rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Path Group: sys_clk
|
|
Path Type: Hold (Min at Fast Process Corner)
|
|
Requirement: 0.000ns (sys_clk rise@0.000ns - mlkem_clk_clk_pll rise@0.000ns)
|
|
Data Path Delay: 0.758ns (logic 0.141ns (18.596%) route 0.617ns (81.404%))
|
|
Logic Levels: 0
|
|
Clock Path Skew: 0.326ns (DCD - SCD - CPR)
|
|
Destination Clock Delay (DCD): -0.388ns
|
|
Source Clock Delay (SCD): -0.615ns
|
|
Clock Pessimism Removal (CPR): -0.099ns
|
|
Clock Uncertainty: 0.197ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Discrete Jitter (DJ): 0.136ns
|
|
Phase Error (PE): 0.120ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock mlkem_clk_clk_pll rise edge)
|
|
0.000 0.000 r
|
|
K21 0.000 0.000 r clk (IN)
|
|
net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1
|
|
K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O
|
|
net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll
|
|
PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2)
|
|
-2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2
|
|
net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll
|
|
BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout3_buf/O
|
|
net (fo=26129, routed) 0.647 -0.615 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/mlkem_clk
|
|
SLICE_X114Y75 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/popCC_ptrToPush_reg[3]/C
|
|
------------------------------------------------------------------- -------------------
|
|
SLICE_X114Y75 FDCE (Prop_fdce_C_Q) 0.141 -0.474 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/popCC_ptrToPush_reg[3]/Q
|
|
net (fo=1, routed) 0.617 0.143 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/popToPushGray_buffercc/Q[3]
|
|
SLICE_X114Y76 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/popToPushGray_buffercc/buffers_0_reg[3]/D
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock sys_clk rise edge) 0.000 0.000 r
|
|
K21 0.000 0.000 r clk (IN)
|
|
net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1
|
|
K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O
|
|
net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll
|
|
PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1)
|
|
-2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1
|
|
net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll
|
|
BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O
|
|
net (fo=10004, routed) 0.920 -0.388 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/popToPushGray_buffercc/sys_clk
|
|
SLICE_X114Y76 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/popToPushGray_buffercc/buffers_0_reg[3]/C
|
|
clock pessimism 0.099 -0.289
|
|
clock uncertainty 0.197 -0.093
|
|
SLICE_X114Y76 FDCE (Hold_fdce_C_D) 0.047 -0.046 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/popToPushGray_buffercc/buffers_0_reg[3]
|
|
-------------------------------------------------------------------
|
|
required time 0.046
|
|
arrival time 0.143
|
|
-------------------------------------------------------------------
|
|
slack 0.189
|
|
|
|
Slack (MET) : 0.199ns (arrival time - required time)
|
|
Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/popCC_ptrToPush_reg[0]/C
|
|
(rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns})
|
|
Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/popToPushGray_buffercc/buffers_0_reg[0]/D
|
|
(rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Path Group: sys_clk
|
|
Path Type: Hold (Min at Fast Process Corner)
|
|
Requirement: 0.000ns (sys_clk rise@0.000ns - mlkem_clk_clk_pll rise@0.000ns)
|
|
Data Path Delay: 0.767ns (logic 0.141ns (18.390%) route 0.626ns (81.610%))
|
|
Logic Levels: 0
|
|
Clock Path Skew: 0.325ns (DCD - SCD - CPR)
|
|
Destination Clock Delay (DCD): -0.389ns
|
|
Source Clock Delay (SCD): -0.615ns
|
|
Clock Pessimism Removal (CPR): -0.099ns
|
|
Clock Uncertainty: 0.197ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Discrete Jitter (DJ): 0.136ns
|
|
Phase Error (PE): 0.120ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock mlkem_clk_clk_pll rise edge)
|
|
0.000 0.000 r
|
|
K21 0.000 0.000 r clk (IN)
|
|
net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1
|
|
K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O
|
|
net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll
|
|
PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2)
|
|
-2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2
|
|
net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll
|
|
BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout3_buf/O
|
|
net (fo=26129, routed) 0.647 -0.615 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/mlkem_clk
|
|
SLICE_X114Y75 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/popCC_ptrToPush_reg[0]/C
|
|
------------------------------------------------------------------- -------------------
|
|
SLICE_X114Y75 FDCE (Prop_fdce_C_Q) 0.141 -0.474 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/popCC_ptrToPush_reg[0]/Q
|
|
net (fo=1, routed) 0.626 0.151 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/popToPushGray_buffercc/Q[0]
|
|
SLICE_X113Y75 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/popToPushGray_buffercc/buffers_0_reg[0]/D
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock sys_clk rise edge) 0.000 0.000 r
|
|
K21 0.000 0.000 r clk (IN)
|
|
net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1
|
|
K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O
|
|
net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll
|
|
PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1)
|
|
-2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1
|
|
net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll
|
|
BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O
|
|
net (fo=10004, routed) 0.919 -0.389 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/popToPushGray_buffercc/sys_clk
|
|
SLICE_X113Y75 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/popToPushGray_buffercc/buffers_0_reg[0]/C
|
|
clock pessimism 0.099 -0.290
|
|
clock uncertainty 0.197 -0.094
|
|
SLICE_X113Y75 FDCE (Hold_fdce_C_D) 0.046 -0.048 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/popToPushGray_buffercc/buffers_0_reg[0]
|
|
-------------------------------------------------------------------
|
|
required time 0.048
|
|
arrival time 0.151
|
|
-------------------------------------------------------------------
|
|
slack 0.199
|
|
|
|
Slack (MET) : 0.200ns (arrival time - required time)
|
|
Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_18_23/RAMC/CLK
|
|
(rising edge-triggered cell RAMD32 clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns})
|
|
Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[22]/D
|
|
(rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Path Group: sys_clk
|
|
Path Type: Hold (Min at Fast Process Corner)
|
|
Requirement: 0.000ns (sys_clk rise@0.000ns - mlkem_clk_clk_pll rise@0.000ns)
|
|
Data Path Delay: 0.721ns (logic 0.390ns (54.106%) route 0.331ns (45.894%))
|
|
Logic Levels: 0
|
|
Clock Path Skew: 0.333ns (DCD - SCD - CPR)
|
|
Destination Clock Delay (DCD): -0.393ns
|
|
Source Clock Delay (SCD): -0.627ns
|
|
Clock Pessimism Removal (CPR): -0.099ns
|
|
Clock Uncertainty: 0.197ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Discrete Jitter (DJ): 0.136ns
|
|
Phase Error (PE): 0.120ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock mlkem_clk_clk_pll rise edge)
|
|
0.000 0.000 r
|
|
K21 0.000 0.000 r clk (IN)
|
|
net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1
|
|
K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O
|
|
net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll
|
|
PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2)
|
|
-2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2
|
|
net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll
|
|
BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout3_buf/O
|
|
net (fo=26129, routed) 0.635 -0.627 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_18_23/WCLK
|
|
SLICE_X64Y75 RAMD32 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_18_23/RAMC/CLK
|
|
------------------------------------------------------------------- -------------------
|
|
SLICE_X64Y75 RAMD32 (Prop_ramd32_CLK_O)
|
|
0.390 -0.237 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_18_23/RAMC/O
|
|
net (fo=1, routed) 0.331 0.093 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port10__3[22]
|
|
SLICE_X62Y81 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[22]/D
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock sys_clk rise edge) 0.000 0.000 r
|
|
K21 0.000 0.000 r clk (IN)
|
|
net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1
|
|
K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O
|
|
net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll
|
|
PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1)
|
|
-2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1
|
|
net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll
|
|
BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O
|
|
net (fo=10004, routed) 0.915 -0.393 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/sys_clk
|
|
SLICE_X62Y81 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[22]/C
|
|
clock pessimism 0.099 -0.294
|
|
clock uncertainty 0.197 -0.098
|
|
SLICE_X62Y81 FDRE (Hold_fdre_C_D) -0.009 -0.107 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[22]
|
|
-------------------------------------------------------------------
|
|
required time 0.107
|
|
arrival time 0.093
|
|
-------------------------------------------------------------------
|
|
slack 0.200
|
|
|
|
Slack (MET) : 0.211ns (arrival time - required time)
|
|
Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/popCC_ptrToPush_reg[1]/C
|
|
(rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns})
|
|
Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/popToPushGray_buffercc/buffers_0_reg[1]/D
|
|
(rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Path Group: sys_clk
|
|
Path Type: Hold (Min at Fast Process Corner)
|
|
Requirement: 0.000ns (sys_clk rise@0.000ns - mlkem_clk_clk_pll rise@0.000ns)
|
|
Data Path Delay: 0.780ns (logic 0.141ns (18.081%) route 0.639ns (81.919%))
|
|
Logic Levels: 0
|
|
Clock Path Skew: 0.326ns (DCD - SCD - CPR)
|
|
Destination Clock Delay (DCD): -0.360ns
|
|
Source Clock Delay (SCD): -0.587ns
|
|
Clock Pessimism Removal (CPR): -0.099ns
|
|
Clock Uncertainty: 0.197ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Discrete Jitter (DJ): 0.136ns
|
|
Phase Error (PE): 0.120ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock mlkem_clk_clk_pll rise edge)
|
|
0.000 0.000 r
|
|
K21 0.000 0.000 r clk (IN)
|
|
net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1
|
|
K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O
|
|
net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll
|
|
PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2)
|
|
-2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2
|
|
net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll
|
|
BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout3_buf/O
|
|
net (fo=26129, routed) 0.675 -0.587 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/mlkem_clk
|
|
SLICE_X31Y74 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/popCC_ptrToPush_reg[1]/C
|
|
------------------------------------------------------------------- -------------------
|
|
SLICE_X31Y74 FDCE (Prop_fdce_C_Q) 0.141 -0.446 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/popCC_ptrToPush_reg[1]/Q
|
|
net (fo=2, routed) 0.639 0.192 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/popToPushGray_buffercc/D[1]
|
|
SLICE_X29Y74 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/popToPushGray_buffercc/buffers_0_reg[1]/D
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock sys_clk rise edge) 0.000 0.000 r
|
|
K21 0.000 0.000 r clk (IN)
|
|
net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1
|
|
K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O
|
|
net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll
|
|
PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1)
|
|
-2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1
|
|
net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll
|
|
BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O
|
|
net (fo=10004, routed) 0.948 -0.360 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/popToPushGray_buffercc/sys_clk
|
|
SLICE_X29Y74 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/popToPushGray_buffercc/buffers_0_reg[1]/C
|
|
clock pessimism 0.099 -0.261
|
|
clock uncertainty 0.197 -0.065
|
|
SLICE_X29Y74 FDCE (Hold_fdce_C_D) 0.046 -0.019 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/popToPushGray_buffercc/buffers_0_reg[1]
|
|
-------------------------------------------------------------------
|
|
required time 0.019
|
|
arrival time 0.192
|
|
-------------------------------------------------------------------
|
|
slack 0.211
|
|
|
|
Slack (MET) : 0.216ns (arrival time - required time)
|
|
Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/pushCC_pushPtrGray_reg[1]/C
|
|
(rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns})
|
|
Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/pushToPopGray_buffercc/buffers_0_reg[1]/D
|
|
(rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Path Group: sys_clk
|
|
Path Type: Hold (Min at Fast Process Corner)
|
|
Requirement: 0.000ns (sys_clk rise@0.000ns - mlkem_clk_clk_pll rise@0.000ns)
|
|
Data Path Delay: 0.790ns (logic 0.141ns (17.837%) route 0.649ns (82.163%))
|
|
Logic Levels: 0
|
|
Clock Path Skew: 0.331ns (DCD - SCD - CPR)
|
|
Destination Clock Delay (DCD): -0.339ns
|
|
Source Clock Delay (SCD): -0.571ns
|
|
Clock Pessimism Removal (CPR): -0.099ns
|
|
Clock Uncertainty: 0.197ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Discrete Jitter (DJ): 0.136ns
|
|
Phase Error (PE): 0.120ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock mlkem_clk_clk_pll rise edge)
|
|
0.000 0.000 r
|
|
K21 0.000 0.000 r clk (IN)
|
|
net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1
|
|
K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O
|
|
net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll
|
|
PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2)
|
|
-2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2
|
|
net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll
|
|
BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout3_buf/O
|
|
net (fo=26129, routed) 0.691 -0.571 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/mlkem_clk
|
|
SLICE_X15Y86 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/pushCC_pushPtrGray_reg[1]/C
|
|
------------------------------------------------------------------- -------------------
|
|
SLICE_X15Y86 FDCE (Prop_fdce_C_Q) 0.141 -0.430 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/pushCC_pushPtrGray_reg[1]/Q
|
|
net (fo=2, routed) 0.649 0.219 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/pushToPopGray_buffercc/D[1]
|
|
SLICE_X15Y88 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/pushToPopGray_buffercc/buffers_0_reg[1]/D
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock sys_clk rise edge) 0.000 0.000 r
|
|
K21 0.000 0.000 r clk (IN)
|
|
net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1
|
|
K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O
|
|
net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll
|
|
PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1)
|
|
-2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1
|
|
net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll
|
|
BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O
|
|
net (fo=10004, routed) 0.969 -0.339 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/pushToPopGray_buffercc/sys_clk
|
|
SLICE_X15Y88 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/pushToPopGray_buffercc/buffers_0_reg[1]/C
|
|
clock pessimism 0.099 -0.240
|
|
clock uncertainty 0.197 -0.044
|
|
SLICE_X15Y88 FDCE (Hold_fdce_C_D) 0.047 0.003 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/pushToPopGray_buffercc/buffers_0_reg[1]
|
|
-------------------------------------------------------------------
|
|
required time -0.003
|
|
arrival time 0.219
|
|
-------------------------------------------------------------------
|
|
slack 0.216
|
|
|
|
Slack (MET) : 0.221ns (arrival time - required time)
|
|
Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_6_11/RAMC_D1/CLK
|
|
(rising edge-triggered cell RAMD32 clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns})
|
|
Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[11]/D
|
|
(rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Path Group: sys_clk
|
|
Path Type: Hold (Min at Fast Process Corner)
|
|
Requirement: 0.000ns (sys_clk rise@0.000ns - mlkem_clk_clk_pll rise@0.000ns)
|
|
Data Path Delay: 0.844ns (logic 0.386ns (45.725%) route 0.458ns (54.275%))
|
|
Logic Levels: 0
|
|
Clock Path Skew: 0.361ns (DCD - SCD - CPR)
|
|
Destination Clock Delay (DCD): -0.359ns
|
|
Source Clock Delay (SCD): -0.621ns
|
|
Clock Pessimism Removal (CPR): -0.099ns
|
|
Clock Uncertainty: 0.197ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Discrete Jitter (DJ): 0.136ns
|
|
Phase Error (PE): 0.120ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock mlkem_clk_clk_pll rise edge)
|
|
0.000 0.000 r
|
|
K21 0.000 0.000 r clk (IN)
|
|
net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1
|
|
K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O
|
|
net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll
|
|
PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2)
|
|
-2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2
|
|
net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll
|
|
BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout3_buf/O
|
|
net (fo=26129, routed) 0.641 -0.621 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_6_11/WCLK
|
|
SLICE_X46Y75 RAMD32 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_6_11/RAMC_D1/CLK
|
|
------------------------------------------------------------------- -------------------
|
|
SLICE_X46Y75 RAMD32 (Prop_ramd32_CLK_O)
|
|
0.386 -0.235 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_6_11/RAMC_D1/O
|
|
net (fo=1, routed) 0.458 0.223 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port10__3[11]
|
|
SLICE_X29Y76 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[11]/D
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock sys_clk rise edge) 0.000 0.000 r
|
|
K21 0.000 0.000 r clk (IN)
|
|
net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1
|
|
K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O
|
|
net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll
|
|
PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1)
|
|
-2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1
|
|
net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll
|
|
BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O
|
|
net (fo=10004, routed) 0.949 -0.359 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/sys_clk
|
|
SLICE_X29Y76 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[11]/C
|
|
clock pessimism 0.099 -0.260
|
|
clock uncertainty 0.197 -0.064
|
|
SLICE_X29Y76 FDRE (Hold_fdre_C_D) 0.066 0.002 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[11]
|
|
-------------------------------------------------------------------
|
|
required time -0.002
|
|
arrival time 0.223
|
|
-------------------------------------------------------------------
|
|
slack 0.221
|
|
|
|
Slack (MET) : 0.228ns (arrival time - required time)
|
|
Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_36_39/RAMB_D1/CLK
|
|
(rising edge-triggered cell RAMD32 clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns})
|
|
Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[39]/D
|
|
(rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Path Group: sys_clk
|
|
Path Type: Hold (Min at Fast Process Corner)
|
|
Requirement: 0.000ns (sys_clk rise@0.000ns - mlkem_clk_clk_pll rise@0.000ns)
|
|
Data Path Delay: 0.822ns (logic 0.388ns (47.208%) route 0.434ns (52.792%))
|
|
Logic Levels: 0
|
|
Clock Path Skew: 0.327ns (DCD - SCD - CPR)
|
|
Destination Clock Delay (DCD): -0.349ns
|
|
Source Clock Delay (SCD): -0.577ns
|
|
Clock Pessimism Removal (CPR): -0.099ns
|
|
Clock Uncertainty: 0.197ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Discrete Jitter (DJ): 0.136ns
|
|
Phase Error (PE): 0.120ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock mlkem_clk_clk_pll rise edge)
|
|
0.000 0.000 r
|
|
K21 0.000 0.000 r clk (IN)
|
|
net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1
|
|
K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O
|
|
net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll
|
|
PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2)
|
|
-2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2
|
|
net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll
|
|
BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout3_buf/O
|
|
net (fo=26129, routed) 0.685 -0.577 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_36_39/WCLK
|
|
SLICE_X18Y78 RAMD32 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_36_39/RAMB_D1/CLK
|
|
------------------------------------------------------------------- -------------------
|
|
SLICE_X18Y78 RAMD32 (Prop_ramd32_CLK_O)
|
|
0.388 -0.189 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_36_39/RAMB_D1/O
|
|
net (fo=1, routed) 0.434 0.245 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port10__3[39]
|
|
SLICE_X17Y78 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[39]/D
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock sys_clk rise edge) 0.000 0.000 r
|
|
K21 0.000 0.000 r clk (IN)
|
|
net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1
|
|
K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O
|
|
net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll
|
|
PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1)
|
|
-2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1
|
|
net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll
|
|
BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O
|
|
net (fo=10004, routed) 0.959 -0.349 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/sys_clk
|
|
SLICE_X17Y78 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[39]/C
|
|
clock pessimism 0.099 -0.250
|
|
clock uncertainty 0.197 -0.054
|
|
SLICE_X17Y78 FDRE (Hold_fdre_C_D) 0.070 0.016 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[39]
|
|
-------------------------------------------------------------------
|
|
required time -0.016
|
|
arrival time 0.245
|
|
-------------------------------------------------------------------
|
|
slack 0.228
|
|
|
|
Slack (MET) : 0.233ns (arrival time - required time)
|
|
Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/pushCC_pushPtrGray_reg[1]/C
|
|
(rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns})
|
|
Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/pushToPopGray_buffercc/buffers_0_reg[1]/D
|
|
(rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Path Group: sys_clk
|
|
Path Type: Hold (Min at Fast Process Corner)
|
|
Requirement: 0.000ns (sys_clk rise@0.000ns - mlkem_clk_clk_pll rise@0.000ns)
|
|
Data Path Delay: 0.802ns (logic 0.141ns (17.574%) route 0.661ns (82.426%))
|
|
Logic Levels: 0
|
|
Clock Path Skew: 0.327ns (DCD - SCD - CPR)
|
|
Destination Clock Delay (DCD): -0.354ns
|
|
Source Clock Delay (SCD): -0.582ns
|
|
Clock Pessimism Removal (CPR): -0.099ns
|
|
Clock Uncertainty: 0.197ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Discrete Jitter (DJ): 0.136ns
|
|
Phase Error (PE): 0.120ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock mlkem_clk_clk_pll rise edge)
|
|
0.000 0.000 r
|
|
K21 0.000 0.000 r clk (IN)
|
|
net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1
|
|
K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O
|
|
net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll
|
|
PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2)
|
|
-2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2
|
|
net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll
|
|
BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout3_buf/O
|
|
net (fo=26129, routed) 0.680 -0.582 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/mlkem_clk
|
|
SLICE_X24Y72 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/pushCC_pushPtrGray_reg[1]/C
|
|
------------------------------------------------------------------- -------------------
|
|
SLICE_X24Y72 FDCE (Prop_fdce_C_Q) 0.141 -0.441 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/pushCC_pushPtrGray_reg[1]/Q
|
|
net (fo=2, routed) 0.661 0.220 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/pushToPopGray_buffercc/Q[1]
|
|
SLICE_X27Y71 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/pushToPopGray_buffercc/buffers_0_reg[1]/D
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock sys_clk rise edge) 0.000 0.000 r
|
|
K21 0.000 0.000 r clk (IN)
|
|
net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1
|
|
K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O
|
|
net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll
|
|
PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1)
|
|
-2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1
|
|
net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll
|
|
BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O
|
|
net (fo=10004, routed) 0.954 -0.354 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/pushToPopGray_buffercc/sys_clk
|
|
SLICE_X27Y71 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/pushToPopGray_buffercc/buffers_0_reg[1]/C
|
|
clock pessimism 0.099 -0.255
|
|
clock uncertainty 0.197 -0.059
|
|
SLICE_X27Y71 FDCE (Hold_fdce_C_D) 0.046 -0.013 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/pushToPopGray_buffercc/buffers_0_reg[1]
|
|
-------------------------------------------------------------------
|
|
required time 0.013
|
|
arrival time 0.220
|
|
-------------------------------------------------------------------
|
|
slack 0.233
|
|
|
|
Slack (MET) : 0.234ns (arrival time - required time)
|
|
Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/popCC_ptrToPush_reg[2]/C
|
|
(rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns})
|
|
Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/popToPushGray_buffercc/buffers_0_reg[2]/D
|
|
(rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Path Group: sys_clk
|
|
Path Type: Hold (Min at Fast Process Corner)
|
|
Requirement: 0.000ns (sys_clk rise@0.000ns - mlkem_clk_clk_pll rise@0.000ns)
|
|
Data Path Delay: 0.803ns (logic 0.141ns (17.555%) route 0.662ns (82.445%))
|
|
Logic Levels: 0
|
|
Clock Path Skew: 0.326ns (DCD - SCD - CPR)
|
|
Destination Clock Delay (DCD): -0.360ns
|
|
Source Clock Delay (SCD): -0.587ns
|
|
Clock Pessimism Removal (CPR): -0.099ns
|
|
Clock Uncertainty: 0.197ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Discrete Jitter (DJ): 0.136ns
|
|
Phase Error (PE): 0.120ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock mlkem_clk_clk_pll rise edge)
|
|
0.000 0.000 r
|
|
K21 0.000 0.000 r clk (IN)
|
|
net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1
|
|
K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O
|
|
net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll
|
|
PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2)
|
|
-2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2
|
|
net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll
|
|
BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout3_buf/O
|
|
net (fo=26129, routed) 0.675 -0.587 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/mlkem_clk
|
|
SLICE_X31Y74 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/popCC_ptrToPush_reg[2]/C
|
|
------------------------------------------------------------------- -------------------
|
|
SLICE_X31Y74 FDCE (Prop_fdce_C_Q) 0.141 -0.446 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/popCC_ptrToPush_reg[2]/Q
|
|
net (fo=2, routed) 0.662 0.216 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/popToPushGray_buffercc/D[2]
|
|
SLICE_X29Y74 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/popToPushGray_buffercc/buffers_0_reg[2]/D
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock sys_clk rise edge) 0.000 0.000 r
|
|
K21 0.000 0.000 r clk (IN)
|
|
net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1
|
|
K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O
|
|
net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll
|
|
PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1)
|
|
-2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1
|
|
net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll
|
|
BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O
|
|
net (fo=10004, routed) 0.948 -0.360 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/popToPushGray_buffercc/sys_clk
|
|
SLICE_X29Y74 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/popToPushGray_buffercc/buffers_0_reg[2]/C
|
|
clock pessimism 0.099 -0.261
|
|
clock uncertainty 0.197 -0.065
|
|
SLICE_X29Y74 FDCE (Hold_fdce_C_D) 0.047 -0.018 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/popToPushGray_buffercc/buffers_0_reg[2]
|
|
-------------------------------------------------------------------
|
|
required time 0.018
|
|
arrival time 0.216
|
|
-------------------------------------------------------------------
|
|
slack 0.234
|
|
|
|
Slack (MET) : 0.236ns (arrival time - required time)
|
|
Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/popCC_ptrToPush_reg[0]/C
|
|
(rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns})
|
|
Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/popToPushGray_buffercc/buffers_0_reg[0]/D
|
|
(rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Path Group: sys_clk
|
|
Path Type: Hold (Min at Fast Process Corner)
|
|
Requirement: 0.000ns (sys_clk rise@0.000ns - mlkem_clk_clk_pll rise@0.000ns)
|
|
Data Path Delay: 0.807ns (logic 0.141ns (17.466%) route 0.666ns (82.534%))
|
|
Logic Levels: 0
|
|
Clock Path Skew: 0.329ns (DCD - SCD - CPR)
|
|
Destination Clock Delay (DCD): -0.354ns
|
|
Source Clock Delay (SCD): -0.584ns
|
|
Clock Pessimism Removal (CPR): -0.099ns
|
|
Clock Uncertainty: 0.197ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Discrete Jitter (DJ): 0.136ns
|
|
Phase Error (PE): 0.120ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock mlkem_clk_clk_pll rise edge)
|
|
0.000 0.000 r
|
|
K21 0.000 0.000 r clk (IN)
|
|
net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1
|
|
K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O
|
|
net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll
|
|
PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2)
|
|
-2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2
|
|
net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll
|
|
BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout3_buf/O
|
|
net (fo=26129, routed) 0.678 -0.584 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/mlkem_clk
|
|
SLICE_X30Y78 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/popCC_ptrToPush_reg[0]/C
|
|
------------------------------------------------------------------- -------------------
|
|
SLICE_X30Y78 FDCE (Prop_fdce_C_Q) 0.141 -0.443 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/popCC_ptrToPush_reg[0]/Q
|
|
net (fo=2, routed) 0.666 0.223 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/popToPushGray_buffercc/D[0]
|
|
SLICE_X27Y78 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/popToPushGray_buffercc/buffers_0_reg[0]/D
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock sys_clk rise edge) 0.000 0.000 r
|
|
K21 0.000 0.000 r clk (IN)
|
|
net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1
|
|
K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O
|
|
net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll
|
|
PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1)
|
|
-2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1
|
|
net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll
|
|
BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O
|
|
net (fo=10004, routed) 0.954 -0.354 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/popToPushGray_buffercc/sys_clk
|
|
SLICE_X27Y78 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/popToPushGray_buffercc/buffers_0_reg[0]/C
|
|
clock pessimism 0.099 -0.255
|
|
clock uncertainty 0.197 -0.059
|
|
SLICE_X27Y78 FDCE (Hold_fdce_C_D) 0.046 -0.013 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/popToPushGray_buffercc/buffers_0_reg[0]
|
|
-------------------------------------------------------------------
|
|
required time 0.013
|
|
arrival time 0.223
|
|
-------------------------------------------------------------------
|
|
slack 0.236
|
|
|
|
Slack (MET) : 0.238ns (arrival time - required time)
|
|
Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/pushCC_pushPtrGray_reg[0]/C
|
|
(rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns})
|
|
Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/pushToPopGray_buffercc/buffers_0_reg[0]/D
|
|
(rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Path Group: sys_clk
|
|
Path Type: Hold (Min at Fast Process Corner)
|
|
Requirement: 0.000ns (sys_clk rise@0.000ns - mlkem_clk_clk_pll rise@0.000ns)
|
|
Data Path Delay: 0.811ns (logic 0.141ns (17.379%) route 0.670ns (82.621%))
|
|
Logic Levels: 0
|
|
Clock Path Skew: 0.331ns (DCD - SCD - CPR)
|
|
Destination Clock Delay (DCD): -0.339ns
|
|
Source Clock Delay (SCD): -0.571ns
|
|
Clock Pessimism Removal (CPR): -0.099ns
|
|
Clock Uncertainty: 0.197ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Discrete Jitter (DJ): 0.136ns
|
|
Phase Error (PE): 0.120ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock mlkem_clk_clk_pll rise edge)
|
|
0.000 0.000 r
|
|
K21 0.000 0.000 r clk (IN)
|
|
net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1
|
|
K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O
|
|
net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll
|
|
PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2)
|
|
-2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2
|
|
net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll
|
|
BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout3_buf/O
|
|
net (fo=26129, routed) 0.691 -0.571 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/mlkem_clk
|
|
SLICE_X15Y86 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/pushCC_pushPtrGray_reg[0]/C
|
|
------------------------------------------------------------------- -------------------
|
|
SLICE_X15Y86 FDCE (Prop_fdce_C_Q) 0.141 -0.430 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/pushCC_pushPtrGray_reg[0]/Q
|
|
net (fo=2, routed) 0.670 0.240 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/pushToPopGray_buffercc/D[0]
|
|
SLICE_X15Y88 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/pushToPopGray_buffercc/buffers_0_reg[0]/D
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock sys_clk rise edge) 0.000 0.000 r
|
|
K21 0.000 0.000 r clk (IN)
|
|
net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1
|
|
K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O
|
|
net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll
|
|
PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1)
|
|
-2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1
|
|
net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll
|
|
BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O
|
|
net (fo=10004, routed) 0.969 -0.339 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/pushToPopGray_buffercc/sys_clk
|
|
SLICE_X15Y88 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/pushToPopGray_buffercc/buffers_0_reg[0]/C
|
|
clock pessimism 0.099 -0.240
|
|
clock uncertainty 0.197 -0.044
|
|
SLICE_X15Y88 FDCE (Hold_fdce_C_D) 0.046 0.002 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/pushToPopGray_buffercc/buffers_0_reg[0]
|
|
-------------------------------------------------------------------
|
|
required time -0.002
|
|
arrival time 0.240
|
|
-------------------------------------------------------------------
|
|
slack 0.238
|
|
|
|
Slack (MET) : 0.241ns (arrival time - required time)
|
|
Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_24_29/RAMA/CLK
|
|
(rising edge-triggered cell RAMD32 clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns})
|
|
Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[24]/D
|
|
(rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Path Group: sys_clk
|
|
Path Type: Hold (Min at Fast Process Corner)
|
|
Requirement: 0.000ns (sys_clk rise@0.000ns - mlkem_clk_clk_pll rise@0.000ns)
|
|
Data Path Delay: 0.746ns (logic 0.492ns (65.912%) route 0.254ns (34.088%))
|
|
Logic Levels: 0
|
|
Clock Path Skew: 0.328ns (DCD - SCD - CPR)
|
|
Destination Clock Delay (DCD): -0.395ns
|
|
Source Clock Delay (SCD): -0.624ns
|
|
Clock Pessimism Removal (CPR): -0.099ns
|
|
Clock Uncertainty: 0.197ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Discrete Jitter (DJ): 0.136ns
|
|
Phase Error (PE): 0.120ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock mlkem_clk_clk_pll rise edge)
|
|
0.000 0.000 r
|
|
K21 0.000 0.000 r clk (IN)
|
|
net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1
|
|
K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O
|
|
net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll
|
|
PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2)
|
|
-2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2
|
|
net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll
|
|
BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout3_buf/O
|
|
net (fo=26129, routed) 0.638 -0.624 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_24_29/WCLK
|
|
SLICE_X64Y77 RAMD32 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_24_29/RAMA/CLK
|
|
------------------------------------------------------------------- -------------------
|
|
SLICE_X64Y77 RAMD32 (Prop_ramd32_CLK_O)
|
|
0.492 -0.132 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_24_29/RAMA/O
|
|
net (fo=1, routed) 0.254 0.122 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port10__3[24]
|
|
SLICE_X61Y77 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[24]/D
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock sys_clk rise edge) 0.000 0.000 r
|
|
K21 0.000 0.000 r clk (IN)
|
|
net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1
|
|
K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O
|
|
net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll
|
|
PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1)
|
|
-2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1
|
|
net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll
|
|
BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O
|
|
net (fo=10004, routed) 0.913 -0.395 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/sys_clk
|
|
SLICE_X61Y77 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[24]/C
|
|
clock pessimism 0.099 -0.296
|
|
clock uncertainty 0.197 -0.100
|
|
SLICE_X61Y77 FDRE (Hold_fdre_C_D) -0.019 -0.119 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[24]
|
|
-------------------------------------------------------------------
|
|
required time 0.119
|
|
arrival time 0.122
|
|
-------------------------------------------------------------------
|
|
slack 0.241
|
|
|
|
Slack (MET) : 0.246ns (arrival time - required time)
|
|
Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_24_29/RAMB_D1/CLK
|
|
(rising edge-triggered cell RAMD32 clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns})
|
|
Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[27]/D
|
|
(rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Path Group: sys_clk
|
|
Path Type: Hold (Min at Fast Process Corner)
|
|
Requirement: 0.000ns (sys_clk rise@0.000ns - mlkem_clk_clk_pll rise@0.000ns)
|
|
Data Path Delay: 0.850ns (logic 0.388ns (45.663%) route 0.462ns (54.337%))
|
|
Logic Levels: 0
|
|
Clock Path Skew: 0.331ns (DCD - SCD - CPR)
|
|
Destination Clock Delay (DCD): -0.392ns
|
|
Source Clock Delay (SCD): -0.624ns
|
|
Clock Pessimism Removal (CPR): -0.099ns
|
|
Clock Uncertainty: 0.197ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Discrete Jitter (DJ): 0.136ns
|
|
Phase Error (PE): 0.120ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock mlkem_clk_clk_pll rise edge)
|
|
0.000 0.000 r
|
|
K21 0.000 0.000 r clk (IN)
|
|
net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1
|
|
K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O
|
|
net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll
|
|
PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2)
|
|
-2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2
|
|
net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll
|
|
BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout3_buf/O
|
|
net (fo=26129, routed) 0.638 -0.624 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_24_29/WCLK
|
|
SLICE_X64Y77 RAMD32 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_24_29/RAMB_D1/CLK
|
|
------------------------------------------------------------------- -------------------
|
|
SLICE_X64Y77 RAMD32 (Prop_ramd32_CLK_O)
|
|
0.388 -0.236 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_24_29/RAMB_D1/O
|
|
net (fo=1, routed) 0.462 0.225 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port10__3[27]
|
|
SLICE_X57Y78 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[27]/D
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock sys_clk rise edge) 0.000 0.000 r
|
|
K21 0.000 0.000 r clk (IN)
|
|
net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1
|
|
K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O
|
|
net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll
|
|
PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1)
|
|
-2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1
|
|
net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll
|
|
BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O
|
|
net (fo=10004, routed) 0.916 -0.392 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/sys_clk
|
|
SLICE_X57Y78 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[27]/C
|
|
clock pessimism 0.099 -0.293
|
|
clock uncertainty 0.197 -0.097
|
|
SLICE_X57Y78 FDRE (Hold_fdre_C_D) 0.076 -0.021 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[27]
|
|
-------------------------------------------------------------------
|
|
required time 0.021
|
|
arrival time 0.225
|
|
-------------------------------------------------------------------
|
|
slack 0.246
|
|
|
|
Slack (MET) : 0.247ns (arrival time - required time)
|
|
Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_24_29/RAMC_D1/CLK
|
|
(rising edge-triggered cell RAMD32 clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns})
|
|
Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[29]/D
|
|
(rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Path Group: sys_clk
|
|
Path Type: Hold (Min at Fast Process Corner)
|
|
Requirement: 0.000ns (sys_clk rise@0.000ns - mlkem_clk_clk_pll rise@0.000ns)
|
|
Data Path Delay: 0.848ns (logic 0.386ns (45.530%) route 0.462ns (54.470%))
|
|
Logic Levels: 0
|
|
Clock Path Skew: 0.328ns (DCD - SCD - CPR)
|
|
Destination Clock Delay (DCD): -0.395ns
|
|
Source Clock Delay (SCD): -0.624ns
|
|
Clock Pessimism Removal (CPR): -0.099ns
|
|
Clock Uncertainty: 0.197ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Discrete Jitter (DJ): 0.136ns
|
|
Phase Error (PE): 0.120ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock mlkem_clk_clk_pll rise edge)
|
|
0.000 0.000 r
|
|
K21 0.000 0.000 r clk (IN)
|
|
net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1
|
|
K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O
|
|
net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll
|
|
PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2)
|
|
-2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2
|
|
net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll
|
|
BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout3_buf/O
|
|
net (fo=26129, routed) 0.638 -0.624 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_24_29/WCLK
|
|
SLICE_X64Y77 RAMD32 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_24_29/RAMC_D1/CLK
|
|
------------------------------------------------------------------- -------------------
|
|
SLICE_X64Y77 RAMD32 (Prop_ramd32_CLK_O)
|
|
0.386 -0.238 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_24_29/RAMC_D1/O
|
|
net (fo=1, routed) 0.462 0.223 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port10__3[29]
|
|
SLICE_X61Y77 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[29]/D
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock sys_clk rise edge) 0.000 0.000 r
|
|
K21 0.000 0.000 r clk (IN)
|
|
net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1
|
|
K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O
|
|
net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll
|
|
PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1)
|
|
-2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1
|
|
net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll
|
|
BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O
|
|
net (fo=10004, routed) 0.913 -0.395 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/sys_clk
|
|
SLICE_X61Y77 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[29]/C
|
|
clock pessimism 0.099 -0.296
|
|
clock uncertainty 0.197 -0.100
|
|
SLICE_X61Y77 FDRE (Hold_fdre_C_D) 0.076 -0.024 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[29]
|
|
-------------------------------------------------------------------
|
|
required time 0.024
|
|
arrival time 0.223
|
|
-------------------------------------------------------------------
|
|
slack 0.247
|
|
|
|
Slack (MET) : 0.249ns (arrival time - required time)
|
|
Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_12_17/RAMC_D1/CLK
|
|
(rising edge-triggered cell RAMD32 clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns})
|
|
Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[17]/D
|
|
(rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Path Group: sys_clk
|
|
Path Type: Hold (Min at Fast Process Corner)
|
|
Requirement: 0.000ns (sys_clk rise@0.000ns - mlkem_clk_clk_pll rise@0.000ns)
|
|
Data Path Delay: 0.822ns (logic 0.386ns (46.947%) route 0.436ns (53.053%))
|
|
Logic Levels: 0
|
|
Clock Path Skew: 0.330ns (DCD - SCD - CPR)
|
|
Destination Clock Delay (DCD): -0.395ns
|
|
Source Clock Delay (SCD): -0.626ns
|
|
Clock Pessimism Removal (CPR): -0.099ns
|
|
Clock Uncertainty: 0.197ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Discrete Jitter (DJ): 0.136ns
|
|
Phase Error (PE): 0.120ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock mlkem_clk_clk_pll rise edge)
|
|
0.000 0.000 r
|
|
K21 0.000 0.000 r clk (IN)
|
|
net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1
|
|
K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O
|
|
net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll
|
|
PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2)
|
|
-2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2
|
|
net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll
|
|
BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout3_buf/O
|
|
net (fo=26129, routed) 0.636 -0.626 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_12_17/WCLK
|
|
SLICE_X64Y76 RAMD32 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_12_17/RAMC_D1/CLK
|
|
------------------------------------------------------------------- -------------------
|
|
SLICE_X64Y76 RAMD32 (Prop_ramd32_CLK_O)
|
|
0.386 -0.240 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_12_17/RAMC_D1/O
|
|
net (fo=1, routed) 0.436 0.196 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port10__3[17]
|
|
SLICE_X61Y77 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[17]/D
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock sys_clk rise edge) 0.000 0.000 r
|
|
K21 0.000 0.000 r clk (IN)
|
|
net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1
|
|
K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O
|
|
net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll
|
|
PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1)
|
|
-2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1
|
|
net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll
|
|
BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O
|
|
net (fo=10004, routed) 0.913 -0.395 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/sys_clk
|
|
SLICE_X61Y77 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[17]/C
|
|
clock pessimism 0.099 -0.296
|
|
clock uncertainty 0.197 -0.100
|
|
SLICE_X61Y77 FDRE (Hold_fdre_C_D) 0.047 -0.053 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[17]
|
|
-------------------------------------------------------------------
|
|
required time 0.053
|
|
arrival time 0.196
|
|
-------------------------------------------------------------------
|
|
slack 0.249
|
|
|
|
Slack (MET) : 0.252ns (arrival time - required time)
|
|
Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/popCC_ptrToPush_reg[2]/C
|
|
(rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns})
|
|
Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/popToPushGray_buffercc/buffers_0_reg[2]/D
|
|
(rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Path Group: sys_clk
|
|
Path Type: Hold (Min at Fast Process Corner)
|
|
Requirement: 0.000ns (sys_clk rise@0.000ns - mlkem_clk_clk_pll rise@0.000ns)
|
|
Data Path Delay: 0.824ns (logic 0.141ns (17.122%) route 0.683ns (82.878%))
|
|
Logic Levels: 0
|
|
Clock Path Skew: 0.328ns (DCD - SCD - CPR)
|
|
Destination Clock Delay (DCD): -0.354ns
|
|
Source Clock Delay (SCD): -0.583ns
|
|
Clock Pessimism Removal (CPR): -0.099ns
|
|
Clock Uncertainty: 0.197ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Discrete Jitter (DJ): 0.136ns
|
|
Phase Error (PE): 0.120ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock mlkem_clk_clk_pll rise edge)
|
|
0.000 0.000 r
|
|
K21 0.000 0.000 r clk (IN)
|
|
net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1
|
|
K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O
|
|
net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll
|
|
PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2)
|
|
-2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2
|
|
net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll
|
|
BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout3_buf/O
|
|
net (fo=26129, routed) 0.679 -0.583 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/mlkem_clk
|
|
SLICE_X28Y79 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/popCC_ptrToPush_reg[2]/C
|
|
------------------------------------------------------------------- -------------------
|
|
SLICE_X28Y79 FDCE (Prop_fdce_C_Q) 0.141 -0.442 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/popCC_ptrToPush_reg[2]/Q
|
|
net (fo=2, routed) 0.683 0.240 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/popToPushGray_buffercc/D[2]
|
|
SLICE_X27Y78 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/popToPushGray_buffercc/buffers_0_reg[2]/D
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock sys_clk rise edge) 0.000 0.000 r
|
|
K21 0.000 0.000 r clk (IN)
|
|
net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1
|
|
K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O
|
|
net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll
|
|
PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1)
|
|
-2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1
|
|
net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll
|
|
BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O
|
|
net (fo=10004, routed) 0.954 -0.354 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/popToPushGray_buffercc/sys_clk
|
|
SLICE_X27Y78 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/popToPushGray_buffercc/buffers_0_reg[2]/C
|
|
clock pessimism 0.099 -0.255
|
|
clock uncertainty 0.197 -0.059
|
|
SLICE_X27Y78 FDCE (Hold_fdce_C_D) 0.047 -0.012 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/popToPushGray_buffercc/buffers_0_reg[2]
|
|
-------------------------------------------------------------------
|
|
required time 0.012
|
|
arrival time 0.240
|
|
-------------------------------------------------------------------
|
|
slack 0.252
|
|
|
|
Slack (MET) : 0.255ns (arrival time - required time)
|
|
Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_30_35/RAMA_D1/CLK
|
|
(rising edge-triggered cell RAMD32 clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns})
|
|
Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[31]/D
|
|
(rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Path Group: sys_clk
|
|
Path Type: Hold (Min at Fast Process Corner)
|
|
Requirement: 0.000ns (sys_clk rise@0.000ns - mlkem_clk_clk_pll rise@0.000ns)
|
|
Data Path Delay: 0.845ns (logic 0.478ns (56.587%) route 0.367ns (43.413%))
|
|
Logic Levels: 0
|
|
Clock Path Skew: 0.321ns (DCD - SCD - CPR)
|
|
Destination Clock Delay (DCD): -0.359ns
|
|
Source Clock Delay (SCD): -0.581ns
|
|
Clock Pessimism Removal (CPR): -0.099ns
|
|
Clock Uncertainty: 0.197ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Discrete Jitter (DJ): 0.136ns
|
|
Phase Error (PE): 0.120ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock mlkem_clk_clk_pll rise edge)
|
|
0.000 0.000 r
|
|
K21 0.000 0.000 r clk (IN)
|
|
net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1
|
|
K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O
|
|
net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll
|
|
PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2)
|
|
-2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2
|
|
net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll
|
|
BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout3_buf/O
|
|
net (fo=26129, routed) 0.681 -0.581 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_30_35/WCLK
|
|
SLICE_X20Y76 RAMD32 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_30_35/RAMA_D1/CLK
|
|
------------------------------------------------------------------- -------------------
|
|
SLICE_X20Y76 RAMD32 (Prop_ramd32_CLK_O)
|
|
0.478 -0.103 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_30_35/RAMA_D1/O
|
|
net (fo=1, routed) 0.367 0.263 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port10__3[31]
|
|
SLICE_X29Y76 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[31]/D
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock sys_clk rise edge) 0.000 0.000 r
|
|
K21 0.000 0.000 r clk (IN)
|
|
net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1
|
|
K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O
|
|
net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll
|
|
PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1)
|
|
-2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1
|
|
net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll
|
|
BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O
|
|
net (fo=10004, routed) 0.949 -0.359 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/sys_clk
|
|
SLICE_X29Y76 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[31]/C
|
|
clock pessimism 0.099 -0.260
|
|
clock uncertainty 0.197 -0.064
|
|
SLICE_X29Y76 FDRE (Hold_fdre_C_D) 0.072 0.008 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[31]
|
|
-------------------------------------------------------------------
|
|
required time -0.008
|
|
arrival time 0.263
|
|
-------------------------------------------------------------------
|
|
slack 0.255
|
|
|
|
Slack (MET) : 0.256ns (arrival time - required time)
|
|
Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/popCC_ptrToPush_reg[1]/C
|
|
(rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns})
|
|
Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/popToPushGray_buffercc/buffers_0_reg[1]/D
|
|
(rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Path Group: sys_clk
|
|
Path Type: Hold (Min at Fast Process Corner)
|
|
Requirement: 0.000ns (sys_clk rise@0.000ns - mlkem_clk_clk_pll rise@0.000ns)
|
|
Data Path Delay: 0.828ns (logic 0.141ns (17.038%) route 0.687ns (82.962%))
|
|
Logic Levels: 0
|
|
Clock Path Skew: 0.328ns (DCD - SCD - CPR)
|
|
Destination Clock Delay (DCD): -0.354ns
|
|
Source Clock Delay (SCD): -0.583ns
|
|
Clock Pessimism Removal (CPR): -0.099ns
|
|
Clock Uncertainty: 0.197ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Discrete Jitter (DJ): 0.136ns
|
|
Phase Error (PE): 0.120ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock mlkem_clk_clk_pll rise edge)
|
|
0.000 0.000 r
|
|
K21 0.000 0.000 r clk (IN)
|
|
net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1
|
|
K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O
|
|
net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll
|
|
PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2)
|
|
-2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2
|
|
net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll
|
|
BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout3_buf/O
|
|
net (fo=26129, routed) 0.679 -0.583 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/mlkem_clk
|
|
SLICE_X28Y79 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/popCC_ptrToPush_reg[1]/C
|
|
------------------------------------------------------------------- -------------------
|
|
SLICE_X28Y79 FDCE (Prop_fdce_C_Q) 0.141 -0.442 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/popCC_ptrToPush_reg[1]/Q
|
|
net (fo=2, routed) 0.687 0.244 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/popToPushGray_buffercc/D[1]
|
|
SLICE_X27Y78 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/popToPushGray_buffercc/buffers_0_reg[1]/D
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock sys_clk rise edge) 0.000 0.000 r
|
|
K21 0.000 0.000 r clk (IN)
|
|
net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1
|
|
K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O
|
|
net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll
|
|
PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1)
|
|
-2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1
|
|
net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll
|
|
BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O
|
|
net (fo=10004, routed) 0.954 -0.354 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/popToPushGray_buffercc/sys_clk
|
|
SLICE_X27Y78 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/popToPushGray_buffercc/buffers_0_reg[1]/C
|
|
clock pessimism 0.099 -0.255
|
|
clock uncertainty 0.197 -0.059
|
|
SLICE_X27Y78 FDCE (Hold_fdce_C_D) 0.047 -0.012 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/popToPushGray_buffercc/buffers_0_reg[1]
|
|
-------------------------------------------------------------------
|
|
required time 0.012
|
|
arrival time 0.244
|
|
-------------------------------------------------------------------
|
|
slack 0.256
|
|
|
|
Slack (MET) : 0.260ns (arrival time - required time)
|
|
Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/popCC_ptrToPush_reg[0]/C
|
|
(rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns})
|
|
Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/popToPushGray_buffercc/buffers_0_reg[0]/D
|
|
(rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Path Group: sys_clk
|
|
Path Type: Hold (Min at Fast Process Corner)
|
|
Requirement: 0.000ns (sys_clk rise@0.000ns - mlkem_clk_clk_pll rise@0.000ns)
|
|
Data Path Delay: 0.829ns (logic 0.141ns (16.998%) route 0.688ns (83.002%))
|
|
Logic Levels: 0
|
|
Clock Path Skew: 0.327ns (DCD - SCD - CPR)
|
|
Destination Clock Delay (DCD): -0.360ns
|
|
Source Clock Delay (SCD): -0.588ns
|
|
Clock Pessimism Removal (CPR): -0.099ns
|
|
Clock Uncertainty: 0.197ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Discrete Jitter (DJ): 0.136ns
|
|
Phase Error (PE): 0.120ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock mlkem_clk_clk_pll rise edge)
|
|
0.000 0.000 r
|
|
K21 0.000 0.000 r clk (IN)
|
|
net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1
|
|
K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O
|
|
net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll
|
|
PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2)
|
|
-2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2
|
|
net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll
|
|
BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout3_buf/O
|
|
net (fo=26129, routed) 0.674 -0.588 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/mlkem_clk
|
|
SLICE_X33Y74 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/popCC_ptrToPush_reg[0]/C
|
|
------------------------------------------------------------------- -------------------
|
|
SLICE_X33Y74 FDCE (Prop_fdce_C_Q) 0.141 -0.447 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/popCC_ptrToPush_reg[0]/Q
|
|
net (fo=2, routed) 0.688 0.241 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/popToPushGray_buffercc/D[0]
|
|
SLICE_X30Y74 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/popToPushGray_buffercc/buffers_0_reg[0]/D
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock sys_clk rise edge) 0.000 0.000 r
|
|
K21 0.000 0.000 r clk (IN)
|
|
net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1
|
|
K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O
|
|
net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll
|
|
PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1)
|
|
-2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1
|
|
net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll
|
|
BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O
|
|
net (fo=10004, routed) 0.948 -0.360 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/popToPushGray_buffercc/sys_clk
|
|
SLICE_X30Y74 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/popToPushGray_buffercc/buffers_0_reg[0]/C
|
|
clock pessimism 0.099 -0.261
|
|
clock uncertainty 0.197 -0.065
|
|
SLICE_X30Y74 FDCE (Hold_fdce_C_D) 0.046 -0.019 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/popToPushGray_buffercc/buffers_0_reg[0]
|
|
-------------------------------------------------------------------
|
|
required time 0.019
|
|
arrival time 0.241
|
|
-------------------------------------------------------------------
|
|
slack 0.260
|
|
|
|
Slack (MET) : 0.261ns (arrival time - required time)
|
|
Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/popCC_ptrToPush_reg[2]/C
|
|
(rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns})
|
|
Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/popToPushGray_buffercc/buffers_0_reg[2]/D
|
|
(rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Path Group: sys_clk
|
|
Path Type: Hold (Min at Fast Process Corner)
|
|
Requirement: 0.000ns (sys_clk rise@0.000ns - mlkem_clk_clk_pll rise@0.000ns)
|
|
Data Path Delay: 0.776ns (logic 0.128ns (16.502%) route 0.648ns (83.498%))
|
|
Logic Levels: 0
|
|
Clock Path Skew: 0.326ns (DCD - SCD - CPR)
|
|
Destination Clock Delay (DCD): -0.388ns
|
|
Source Clock Delay (SCD): -0.615ns
|
|
Clock Pessimism Removal (CPR): -0.099ns
|
|
Clock Uncertainty: 0.197ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Discrete Jitter (DJ): 0.136ns
|
|
Phase Error (PE): 0.120ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock mlkem_clk_clk_pll rise edge)
|
|
0.000 0.000 r
|
|
K21 0.000 0.000 r clk (IN)
|
|
net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1
|
|
K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O
|
|
net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll
|
|
PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2)
|
|
-2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2
|
|
net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll
|
|
BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout3_buf/O
|
|
net (fo=26129, routed) 0.647 -0.615 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/mlkem_clk
|
|
SLICE_X114Y75 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/popCC_ptrToPush_reg[2]/C
|
|
------------------------------------------------------------------- -------------------
|
|
SLICE_X114Y75 FDCE (Prop_fdce_C_Q) 0.128 -0.487 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/popCC_ptrToPush_reg[2]/Q
|
|
net (fo=1, routed) 0.648 0.160 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/popToPushGray_buffercc/Q[2]
|
|
SLICE_X114Y76 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/popToPushGray_buffercc/buffers_0_reg[2]/D
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock sys_clk rise edge) 0.000 0.000 r
|
|
K21 0.000 0.000 r clk (IN)
|
|
net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1
|
|
K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O
|
|
net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll
|
|
PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1)
|
|
-2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1
|
|
net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll
|
|
BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O
|
|
net (fo=10004, routed) 0.920 -0.388 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/popToPushGray_buffercc/sys_clk
|
|
SLICE_X114Y76 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/popToPushGray_buffercc/buffers_0_reg[2]/C
|
|
clock pessimism 0.099 -0.289
|
|
clock uncertainty 0.197 -0.093
|
|
SLICE_X114Y76 FDCE (Hold_fdce_C_D) -0.008 -0.101 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/popToPushGray_buffercc/buffers_0_reg[2]
|
|
-------------------------------------------------------------------
|
|
required time 0.101
|
|
arrival time 0.160
|
|
-------------------------------------------------------------------
|
|
slack 0.261
|
|
|
|
Slack (MET) : 0.266ns (arrival time - required time)
|
|
Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/pushCC_pushPtrGray_reg[3]/C
|
|
(rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns})
|
|
Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/pushToPopGray_buffercc/buffers_0_reg[3]/D
|
|
(rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Path Group: sys_clk
|
|
Path Type: Hold (Min at Fast Process Corner)
|
|
Requirement: 0.000ns (sys_clk rise@0.000ns - mlkem_clk_clk_pll rise@0.000ns)
|
|
Data Path Delay: 0.785ns (logic 0.128ns (16.296%) route 0.657ns (83.704%))
|
|
Logic Levels: 0
|
|
Clock Path Skew: 0.329ns (DCD - SCD - CPR)
|
|
Destination Clock Delay (DCD): -0.341ns
|
|
Source Clock Delay (SCD): -0.571ns
|
|
Clock Pessimism Removal (CPR): -0.099ns
|
|
Clock Uncertainty: 0.197ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Discrete Jitter (DJ): 0.136ns
|
|
Phase Error (PE): 0.120ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock mlkem_clk_clk_pll rise edge)
|
|
0.000 0.000 r
|
|
K21 0.000 0.000 r clk (IN)
|
|
net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1
|
|
K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O
|
|
net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll
|
|
PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2)
|
|
-2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2
|
|
net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll
|
|
BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout3_buf/O
|
|
net (fo=26129, routed) 0.691 -0.571 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/mlkem_clk
|
|
SLICE_X15Y86 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/pushCC_pushPtrGray_reg[3]/C
|
|
------------------------------------------------------------------- -------------------
|
|
SLICE_X15Y86 FDCE (Prop_fdce_C_Q) 0.128 -0.443 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/pushCC_pushPtrGray_reg[3]/Q
|
|
net (fo=5, routed) 0.657 0.214 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/pushToPopGray_buffercc/D[3]
|
|
SLICE_X15Y87 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/pushToPopGray_buffercc/buffers_0_reg[3]/D
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock sys_clk rise edge) 0.000 0.000 r
|
|
K21 0.000 0.000 r clk (IN)
|
|
net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1
|
|
K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O
|
|
net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll
|
|
PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1)
|
|
-2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1
|
|
net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll
|
|
BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O
|
|
net (fo=10004, routed) 0.967 -0.341 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/pushToPopGray_buffercc/sys_clk
|
|
SLICE_X15Y87 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/pushToPopGray_buffercc/buffers_0_reg[3]/C
|
|
clock pessimism 0.099 -0.242
|
|
clock uncertainty 0.197 -0.046
|
|
SLICE_X15Y87 FDCE (Hold_fdce_C_D) -0.006 -0.052 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/pushToPopGray_buffercc/buffers_0_reg[3]
|
|
-------------------------------------------------------------------
|
|
required time 0.052
|
|
arrival time 0.214
|
|
-------------------------------------------------------------------
|
|
slack 0.266
|
|
|
|
Slack (MET) : 0.268ns (arrival time - required time)
|
|
Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_6_11/RAMB/CLK
|
|
(rising edge-triggered cell RAMD32 clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns})
|
|
Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[8]/D
|
|
(rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Path Group: sys_clk
|
|
Path Type: Hold (Min at Fast Process Corner)
|
|
Requirement: 0.000ns (sys_clk rise@0.000ns - mlkem_clk_clk_pll rise@0.000ns)
|
|
Data Path Delay: 0.823ns (logic 0.394ns (47.859%) route 0.429ns (52.141%))
|
|
Logic Levels: 0
|
|
Clock Path Skew: 0.360ns (DCD - SCD - CPR)
|
|
Destination Clock Delay (DCD): -0.360ns
|
|
Source Clock Delay (SCD): -0.621ns
|
|
Clock Pessimism Removal (CPR): -0.099ns
|
|
Clock Uncertainty: 0.197ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Discrete Jitter (DJ): 0.136ns
|
|
Phase Error (PE): 0.120ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock mlkem_clk_clk_pll rise edge)
|
|
0.000 0.000 r
|
|
K21 0.000 0.000 r clk (IN)
|
|
net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1
|
|
K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O
|
|
net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll
|
|
PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2)
|
|
-2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2
|
|
net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll
|
|
BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout3_buf/O
|
|
net (fo=26129, routed) 0.641 -0.621 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_6_11/WCLK
|
|
SLICE_X46Y75 RAMD32 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_6_11/RAMB/CLK
|
|
------------------------------------------------------------------- -------------------
|
|
SLICE_X46Y75 RAMD32 (Prop_ramd32_CLK_O)
|
|
0.394 -0.227 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_6_11/RAMB/O
|
|
net (fo=1, routed) 0.429 0.202 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port10__3[8]
|
|
SLICE_X31Y75 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[8]/D
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock sys_clk rise edge) 0.000 0.000 r
|
|
K21 0.000 0.000 r clk (IN)
|
|
net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1
|
|
K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O
|
|
net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll
|
|
PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1)
|
|
-2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1
|
|
net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll
|
|
BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O
|
|
net (fo=10004, routed) 0.948 -0.360 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/sys_clk
|
|
SLICE_X31Y75 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[8]/C
|
|
clock pessimism 0.099 -0.261
|
|
clock uncertainty 0.197 -0.065
|
|
SLICE_X31Y75 FDRE (Hold_fdre_C_D) -0.001 -0.066 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[8]
|
|
-------------------------------------------------------------------
|
|
required time 0.066
|
|
arrival time 0.202
|
|
-------------------------------------------------------------------
|
|
slack 0.268
|
|
|
|
Slack (MET) : 0.290ns (arrival time - required time)
|
|
Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_18_23/RAMA_D1/CLK
|
|
(rising edge-triggered cell RAMD32 clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns})
|
|
Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[19]/D
|
|
(rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Path Group: sys_clk
|
|
Path Type: Hold (Min at Fast Process Corner)
|
|
Requirement: 0.000ns (sys_clk rise@0.000ns - mlkem_clk_clk_pll rise@0.000ns)
|
|
Data Path Delay: 0.868ns (logic 0.478ns (55.096%) route 0.390ns (44.904%))
|
|
Logic Levels: 0
|
|
Clock Path Skew: 0.334ns (DCD - SCD - CPR)
|
|
Destination Clock Delay (DCD): -0.392ns
|
|
Source Clock Delay (SCD): -0.627ns
|
|
Clock Pessimism Removal (CPR): -0.099ns
|
|
Clock Uncertainty: 0.197ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Discrete Jitter (DJ): 0.136ns
|
|
Phase Error (PE): 0.120ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock mlkem_clk_clk_pll rise edge)
|
|
0.000 0.000 r
|
|
K21 0.000 0.000 r clk (IN)
|
|
net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1
|
|
K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O
|
|
net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll
|
|
PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2)
|
|
-2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2
|
|
net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll
|
|
BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout3_buf/O
|
|
net (fo=26129, routed) 0.635 -0.627 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_18_23/WCLK
|
|
SLICE_X64Y75 RAMD32 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_18_23/RAMA_D1/CLK
|
|
------------------------------------------------------------------- -------------------
|
|
SLICE_X64Y75 RAMD32 (Prop_ramd32_CLK_O)
|
|
0.478 -0.149 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_18_23/RAMA_D1/O
|
|
net (fo=1, routed) 0.390 0.240 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port10__3[19]
|
|
SLICE_X57Y78 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[19]/D
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock sys_clk rise edge) 0.000 0.000 r
|
|
K21 0.000 0.000 r clk (IN)
|
|
net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1
|
|
K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O
|
|
net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll
|
|
PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1)
|
|
-2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1
|
|
net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll
|
|
BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O
|
|
net (fo=10004, routed) 0.916 -0.392 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/sys_clk
|
|
SLICE_X57Y78 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[19]/C
|
|
clock pessimism 0.099 -0.293
|
|
clock uncertainty 0.197 -0.097
|
|
SLICE_X57Y78 FDRE (Hold_fdre_C_D) 0.047 -0.050 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[19]
|
|
-------------------------------------------------------------------
|
|
required time 0.050
|
|
arrival time 0.240
|
|
-------------------------------------------------------------------
|
|
slack 0.290
|
|
|
|
Slack (MET) : 0.311ns (arrival time - required time)
|
|
Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_24_29/RAMB/CLK
|
|
(rising edge-triggered cell RAMD32 clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns})
|
|
Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[26]/D
|
|
(rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Path Group: sys_clk
|
|
Path Type: Hold (Min at Fast Process Corner)
|
|
Requirement: 0.000ns (sys_clk rise@0.000ns - mlkem_clk_clk_pll rise@0.000ns)
|
|
Data Path Delay: 0.837ns (logic 0.394ns (47.100%) route 0.443ns (52.900%))
|
|
Logic Levels: 0
|
|
Clock Path Skew: 0.331ns (DCD - SCD - CPR)
|
|
Destination Clock Delay (DCD): -0.392ns
|
|
Source Clock Delay (SCD): -0.624ns
|
|
Clock Pessimism Removal (CPR): -0.099ns
|
|
Clock Uncertainty: 0.197ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Discrete Jitter (DJ): 0.136ns
|
|
Phase Error (PE): 0.120ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock mlkem_clk_clk_pll rise edge)
|
|
0.000 0.000 r
|
|
K21 0.000 0.000 r clk (IN)
|
|
net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1
|
|
K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O
|
|
net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll
|
|
PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2)
|
|
-2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2
|
|
net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll
|
|
BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout3_buf/O
|
|
net (fo=26129, routed) 0.638 -0.624 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_24_29/WCLK
|
|
SLICE_X64Y77 RAMD32 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_24_29/RAMB/CLK
|
|
------------------------------------------------------------------- -------------------
|
|
SLICE_X64Y77 RAMD32 (Prop_ramd32_CLK_O)
|
|
0.394 -0.230 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_24_29/RAMB/O
|
|
net (fo=1, routed) 0.443 0.212 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port10__3[26]
|
|
SLICE_X57Y78 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[26]/D
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock sys_clk rise edge) 0.000 0.000 r
|
|
K21 0.000 0.000 r clk (IN)
|
|
net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1
|
|
K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O
|
|
net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll
|
|
PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1)
|
|
-2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1
|
|
net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll
|
|
BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O
|
|
net (fo=10004, routed) 0.916 -0.392 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/sys_clk
|
|
SLICE_X57Y78 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[26]/C
|
|
clock pessimism 0.099 -0.293
|
|
clock uncertainty 0.197 -0.097
|
|
SLICE_X57Y78 FDRE (Hold_fdre_C_D) -0.002 -0.099 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[26]
|
|
-------------------------------------------------------------------
|
|
required time 0.099
|
|
arrival time 0.212
|
|
-------------------------------------------------------------------
|
|
slack 0.311
|
|
|
|
Slack (MET) : 0.319ns (arrival time - required time)
|
|
Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_0_5/RAMB_D1/CLK
|
|
(rising edge-triggered cell RAMD32 clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns})
|
|
Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[3]/D
|
|
(rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Path Group: sys_clk
|
|
Path Type: Hold (Min at Fast Process Corner)
|
|
Requirement: 0.000ns (sys_clk rise@0.000ns - mlkem_clk_clk_pll rise@0.000ns)
|
|
Data Path Delay: 0.942ns (logic 0.388ns (41.191%) route 0.554ns (58.809%))
|
|
Logic Levels: 0
|
|
Clock Path Skew: 0.360ns (DCD - SCD - CPR)
|
|
Destination Clock Delay (DCD): -0.360ns
|
|
Source Clock Delay (SCD): -0.621ns
|
|
Clock Pessimism Removal (CPR): -0.099ns
|
|
Clock Uncertainty: 0.197ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Discrete Jitter (DJ): 0.136ns
|
|
Phase Error (PE): 0.120ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock mlkem_clk_clk_pll rise edge)
|
|
0.000 0.000 r
|
|
K21 0.000 0.000 r clk (IN)
|
|
net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1
|
|
K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O
|
|
net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll
|
|
PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2)
|
|
-2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2
|
|
net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll
|
|
BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout3_buf/O
|
|
net (fo=26129, routed) 0.641 -0.621 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_0_5/WCLK
|
|
SLICE_X52Y75 RAMD32 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_0_5/RAMB_D1/CLK
|
|
------------------------------------------------------------------- -------------------
|
|
SLICE_X52Y75 RAMD32 (Prop_ramd32_CLK_O)
|
|
0.388 -0.233 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_0_5/RAMB_D1/O
|
|
net (fo=1, routed) 0.554 0.321 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port10__3[3]
|
|
SLICE_X31Y75 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[3]/D
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock sys_clk rise edge) 0.000 0.000 r
|
|
K21 0.000 0.000 r clk (IN)
|
|
net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1
|
|
K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O
|
|
net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll
|
|
PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1)
|
|
-2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1
|
|
net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll
|
|
BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O
|
|
net (fo=10004, routed) 0.948 -0.360 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/sys_clk
|
|
SLICE_X31Y75 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[3]/C
|
|
clock pessimism 0.099 -0.261
|
|
clock uncertainty 0.197 -0.065
|
|
SLICE_X31Y75 FDRE (Hold_fdre_C_D) 0.066 0.001 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[3]
|
|
-------------------------------------------------------------------
|
|
required time -0.001
|
|
arrival time 0.321
|
|
-------------------------------------------------------------------
|
|
slack 0.319
|
|
|
|
Slack (MET) : 0.323ns (arrival time - required time)
|
|
Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_6_11/RAMB_D1/CLK
|
|
(rising edge-triggered cell RAMD32 clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns})
|
|
Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[9]/D
|
|
(rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Path Group: sys_clk
|
|
Path Type: Hold (Min at Fast Process Corner)
|
|
Requirement: 0.000ns (sys_clk rise@0.000ns - mlkem_clk_clk_pll rise@0.000ns)
|
|
Data Path Delay: 0.955ns (logic 0.388ns (40.612%) route 0.567ns (59.388%))
|
|
Logic Levels: 0
|
|
Clock Path Skew: 0.360ns (DCD - SCD - CPR)
|
|
Destination Clock Delay (DCD): -0.360ns
|
|
Source Clock Delay (SCD): -0.621ns
|
|
Clock Pessimism Removal (CPR): -0.099ns
|
|
Clock Uncertainty: 0.197ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Discrete Jitter (DJ): 0.136ns
|
|
Phase Error (PE): 0.120ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock mlkem_clk_clk_pll rise edge)
|
|
0.000 0.000 r
|
|
K21 0.000 0.000 r clk (IN)
|
|
net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1
|
|
K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O
|
|
net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll
|
|
PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2)
|
|
-2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2
|
|
net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll
|
|
BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout3_buf/O
|
|
net (fo=26129, routed) 0.641 -0.621 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_6_11/WCLK
|
|
SLICE_X46Y75 RAMD32 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_6_11/RAMB_D1/CLK
|
|
------------------------------------------------------------------- -------------------
|
|
SLICE_X46Y75 RAMD32 (Prop_ramd32_CLK_O)
|
|
0.388 -0.233 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_6_11/RAMB_D1/O
|
|
net (fo=1, routed) 0.567 0.334 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port10__3[9]
|
|
SLICE_X31Y75 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[9]/D
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock sys_clk rise edge) 0.000 0.000 r
|
|
K21 0.000 0.000 r clk (IN)
|
|
net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1
|
|
K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O
|
|
net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll
|
|
PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1)
|
|
-2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1
|
|
net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll
|
|
BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O
|
|
net (fo=10004, routed) 0.948 -0.360 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/sys_clk
|
|
SLICE_X31Y75 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[9]/C
|
|
clock pessimism 0.099 -0.261
|
|
clock uncertainty 0.197 -0.065
|
|
SLICE_X31Y75 FDRE (Hold_fdre_C_D) 0.076 0.011 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[9]
|
|
-------------------------------------------------------------------
|
|
required time -0.011
|
|
arrival time 0.334
|
|
-------------------------------------------------------------------
|
|
slack 0.323
|
|
|
|
Slack (MET) : 0.346ns (arrival time - required time)
|
|
Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/pushCC_pushPtrGray_reg[2]/C
|
|
(rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns})
|
|
Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/pushToPopGray_buffercc/buffers_0_reg[2]/D
|
|
(rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Path Group: sys_clk
|
|
Path Type: Hold (Min at Fast Process Corner)
|
|
Requirement: 0.000ns (sys_clk rise@0.000ns - mlkem_clk_clk_pll rise@0.000ns)
|
|
Data Path Delay: 0.883ns (logic 0.128ns (14.500%) route 0.755ns (85.500%))
|
|
Logic Levels: 0
|
|
Clock Path Skew: 0.324ns (DCD - SCD - CPR)
|
|
Destination Clock Delay (DCD): -0.357ns
|
|
Source Clock Delay (SCD): -0.582ns
|
|
Clock Pessimism Removal (CPR): -0.099ns
|
|
Clock Uncertainty: 0.197ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Discrete Jitter (DJ): 0.136ns
|
|
Phase Error (PE): 0.120ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock mlkem_clk_clk_pll rise edge)
|
|
0.000 0.000 r
|
|
K21 0.000 0.000 r clk (IN)
|
|
net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1
|
|
K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O
|
|
net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll
|
|
PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2)
|
|
-2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2
|
|
net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll
|
|
BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout3_buf/O
|
|
net (fo=26129, routed) 0.680 -0.582 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/mlkem_clk
|
|
SLICE_X24Y72 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/pushCC_pushPtrGray_reg[2]/C
|
|
------------------------------------------------------------------- -------------------
|
|
SLICE_X24Y72 FDCE (Prop_fdce_C_Q) 0.128 -0.454 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/pushCC_pushPtrGray_reg[2]/Q
|
|
net (fo=4, routed) 0.755 0.300 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/pushToPopGray_buffercc/buffers_0_reg[2]_0
|
|
SLICE_X26Y73 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/pushToPopGray_buffercc/buffers_0_reg[2]/D
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock sys_clk rise edge) 0.000 0.000 r
|
|
K21 0.000 0.000 r clk (IN)
|
|
net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1
|
|
K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O
|
|
net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll
|
|
PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1)
|
|
-2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1
|
|
net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll
|
|
BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O
|
|
net (fo=10004, routed) 0.951 -0.357 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/pushToPopGray_buffercc/sys_clk
|
|
SLICE_X26Y73 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/pushToPopGray_buffercc/buffers_0_reg[2]/C
|
|
clock pessimism 0.099 -0.258
|
|
clock uncertainty 0.197 -0.062
|
|
SLICE_X26Y73 FDCE (Hold_fdce_C_D) 0.016 -0.046 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/pushToPopGray_buffercc/buffers_0_reg[2]
|
|
-------------------------------------------------------------------
|
|
required time 0.046
|
|
arrival time 0.300
|
|
-------------------------------------------------------------------
|
|
slack 0.346
|
|
|
|
Slack (MET) : 0.347ns (arrival time - required time)
|
|
Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_18_23/RAMB/CLK
|
|
(rising edge-triggered cell RAMD32 clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns})
|
|
Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[20]/D
|
|
(rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Path Group: sys_clk
|
|
Path Type: Hold (Min at Fast Process Corner)
|
|
Requirement: 0.000ns (sys_clk rise@0.000ns - mlkem_clk_clk_pll rise@0.000ns)
|
|
Data Path Delay: 0.851ns (logic 0.394ns (46.280%) route 0.457ns (53.720%))
|
|
Logic Levels: 0
|
|
Clock Path Skew: 0.334ns (DCD - SCD - CPR)
|
|
Destination Clock Delay (DCD): -0.392ns
|
|
Source Clock Delay (SCD): -0.627ns
|
|
Clock Pessimism Removal (CPR): -0.099ns
|
|
Clock Uncertainty: 0.197ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Discrete Jitter (DJ): 0.136ns
|
|
Phase Error (PE): 0.120ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock mlkem_clk_clk_pll rise edge)
|
|
0.000 0.000 r
|
|
K21 0.000 0.000 r clk (IN)
|
|
net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1
|
|
K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O
|
|
net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll
|
|
PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2)
|
|
-2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2
|
|
net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll
|
|
BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout3_buf/O
|
|
net (fo=26129, routed) 0.635 -0.627 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_18_23/WCLK
|
|
SLICE_X64Y75 RAMD32 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_18_23/RAMB/CLK
|
|
------------------------------------------------------------------- -------------------
|
|
SLICE_X64Y75 RAMD32 (Prop_ramd32_CLK_O)
|
|
0.394 -0.233 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_18_23/RAMB/O
|
|
net (fo=1, routed) 0.457 0.224 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port10__3[20]
|
|
SLICE_X57Y78 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[20]/D
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock sys_clk rise edge) 0.000 0.000 r
|
|
K21 0.000 0.000 r clk (IN)
|
|
net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1
|
|
K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O
|
|
net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll
|
|
PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1)
|
|
-2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1
|
|
net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll
|
|
BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O
|
|
net (fo=10004, routed) 0.916 -0.392 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/sys_clk
|
|
SLICE_X57Y78 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[20]/C
|
|
clock pessimism 0.099 -0.293
|
|
clock uncertainty 0.197 -0.097
|
|
SLICE_X57Y78 FDRE (Hold_fdre_C_D) -0.026 -0.123 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[20]
|
|
-------------------------------------------------------------------
|
|
required time 0.123
|
|
arrival time 0.224
|
|
-------------------------------------------------------------------
|
|
slack 0.347
|
|
|
|
Slack (MET) : 0.402ns (arrival time - required time)
|
|
Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/pushCC_pushPtrGray_reg[0]/C
|
|
(rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns})
|
|
Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/pushToPopGray_buffercc/buffers_0_reg[0]/D
|
|
(rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Path Group: sys_clk
|
|
Path Type: Hold (Min at Fast Process Corner)
|
|
Requirement: 0.000ns (sys_clk rise@0.000ns - mlkem_clk_clk_pll rise@0.000ns)
|
|
Data Path Delay: 0.983ns (logic 0.141ns (14.340%) route 0.842ns (85.660%))
|
|
Logic Levels: 0
|
|
Clock Path Skew: 0.324ns (DCD - SCD - CPR)
|
|
Destination Clock Delay (DCD): -0.357ns
|
|
Source Clock Delay (SCD): -0.582ns
|
|
Clock Pessimism Removal (CPR): -0.099ns
|
|
Clock Uncertainty: 0.197ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Discrete Jitter (DJ): 0.136ns
|
|
Phase Error (PE): 0.120ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock mlkem_clk_clk_pll rise edge)
|
|
0.000 0.000 r
|
|
K21 0.000 0.000 r clk (IN)
|
|
net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1
|
|
K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O
|
|
net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll
|
|
PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2)
|
|
-2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2
|
|
net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll
|
|
BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout3_buf/O
|
|
net (fo=26129, routed) 0.680 -0.582 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/mlkem_clk
|
|
SLICE_X24Y72 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/pushCC_pushPtrGray_reg[0]/C
|
|
------------------------------------------------------------------- -------------------
|
|
SLICE_X24Y72 FDCE (Prop_fdce_C_Q) 0.141 -0.441 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/pushCC_pushPtrGray_reg[0]/Q
|
|
net (fo=2, routed) 0.842 0.401 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/pushToPopGray_buffercc/Q[0]
|
|
SLICE_X24Y73 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/pushToPopGray_buffercc/buffers_0_reg[0]/D
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock sys_clk rise edge) 0.000 0.000 r
|
|
K21 0.000 0.000 r clk (IN)
|
|
net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1
|
|
K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O
|
|
net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll
|
|
PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1)
|
|
-2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1
|
|
net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll
|
|
BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O
|
|
net (fo=10004, routed) 0.951 -0.357 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/pushToPopGray_buffercc/sys_clk
|
|
SLICE_X24Y73 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/pushToPopGray_buffercc/buffers_0_reg[0]/C
|
|
clock pessimism 0.099 -0.258
|
|
clock uncertainty 0.197 -0.062
|
|
SLICE_X24Y73 FDCE (Hold_fdce_C_D) 0.061 -0.001 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/pushToPopGray_buffercc/buffers_0_reg[0]
|
|
-------------------------------------------------------------------
|
|
required time 0.001
|
|
arrival time 0.401
|
|
-------------------------------------------------------------------
|
|
slack 0.402
|
|
|
|
Slack (MET) : 0.410ns (arrival time - required time)
|
|
Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_30_35/RAMB_D1/CLK
|
|
(rising edge-triggered cell RAMD32 clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns})
|
|
Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[33]/D
|
|
(rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Path Group: sys_clk
|
|
Path Type: Hold (Min at Fast Process Corner)
|
|
Requirement: 0.000ns (sys_clk rise@0.000ns - mlkem_clk_clk_pll rise@0.000ns)
|
|
Data Path Delay: 1.005ns (logic 0.388ns (38.609%) route 0.617ns (61.391%))
|
|
Logic Levels: 0
|
|
Clock Path Skew: 0.328ns (DCD - SCD - CPR)
|
|
Destination Clock Delay (DCD): -0.352ns
|
|
Source Clock Delay (SCD): -0.581ns
|
|
Clock Pessimism Removal (CPR): -0.099ns
|
|
Clock Uncertainty: 0.197ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Discrete Jitter (DJ): 0.136ns
|
|
Phase Error (PE): 0.120ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock mlkem_clk_clk_pll rise edge)
|
|
0.000 0.000 r
|
|
K21 0.000 0.000 r clk (IN)
|
|
net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1
|
|
K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O
|
|
net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll
|
|
PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2)
|
|
-2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2
|
|
net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll
|
|
BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout3_buf/O
|
|
net (fo=26129, routed) 0.681 -0.581 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_30_35/WCLK
|
|
SLICE_X20Y76 RAMD32 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_30_35/RAMB_D1/CLK
|
|
------------------------------------------------------------------- -------------------
|
|
SLICE_X20Y76 RAMD32 (Prop_ramd32_CLK_O)
|
|
0.388 -0.193 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_30_35/RAMB_D1/O
|
|
net (fo=1, routed) 0.617 0.424 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port10__3[33]
|
|
SLICE_X19Y76 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[33]/D
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock sys_clk rise edge) 0.000 0.000 r
|
|
K21 0.000 0.000 r clk (IN)
|
|
net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1
|
|
K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O
|
|
net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll
|
|
PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1)
|
|
-2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1
|
|
net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll
|
|
BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O
|
|
net (fo=10004, routed) 0.956 -0.352 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/sys_clk
|
|
SLICE_X19Y76 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[33]/C
|
|
clock pessimism 0.099 -0.253
|
|
clock uncertainty 0.197 -0.057
|
|
SLICE_X19Y76 FDRE (Hold_fdre_C_D) 0.070 0.013 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[33]
|
|
-------------------------------------------------------------------
|
|
required time -0.013
|
|
arrival time 0.424
|
|
-------------------------------------------------------------------
|
|
slack 0.410
|
|
|
|
Slack (MET) : 0.416ns (arrival time - required time)
|
|
Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_6_11/RAMA/CLK
|
|
(rising edge-triggered cell RAMD32 clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns})
|
|
Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[6]/D
|
|
(rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Path Group: sys_clk
|
|
Path Type: Hold (Min at Fast Process Corner)
|
|
Requirement: 0.000ns (sys_clk rise@0.000ns - mlkem_clk_clk_pll rise@0.000ns)
|
|
Data Path Delay: 0.986ns (logic 0.492ns (49.918%) route 0.494ns (50.082%))
|
|
Logic Levels: 0
|
|
Clock Path Skew: 0.361ns (DCD - SCD - CPR)
|
|
Destination Clock Delay (DCD): -0.359ns
|
|
Source Clock Delay (SCD): -0.621ns
|
|
Clock Pessimism Removal (CPR): -0.099ns
|
|
Clock Uncertainty: 0.197ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Discrete Jitter (DJ): 0.136ns
|
|
Phase Error (PE): 0.120ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock mlkem_clk_clk_pll rise edge)
|
|
0.000 0.000 r
|
|
K21 0.000 0.000 r clk (IN)
|
|
net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1
|
|
K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O
|
|
net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll
|
|
PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2)
|
|
-2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2
|
|
net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll
|
|
BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout3_buf/O
|
|
net (fo=26129, routed) 0.641 -0.621 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_6_11/WCLK
|
|
SLICE_X46Y75 RAMD32 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_6_11/RAMA/CLK
|
|
------------------------------------------------------------------- -------------------
|
|
SLICE_X46Y75 RAMD32 (Prop_ramd32_CLK_O)
|
|
0.492 -0.129 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_6_11/RAMA/O
|
|
net (fo=1, routed) 0.494 0.364 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port10__3[6]
|
|
SLICE_X28Y76 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[6]/D
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock sys_clk rise edge) 0.000 0.000 r
|
|
K21 0.000 0.000 r clk (IN)
|
|
net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1
|
|
K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O
|
|
net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll
|
|
PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1)
|
|
-2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1
|
|
net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll
|
|
BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O
|
|
net (fo=10004, routed) 0.949 -0.359 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/sys_clk
|
|
SLICE_X28Y76 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[6]/C
|
|
clock pessimism 0.099 -0.260
|
|
clock uncertainty 0.197 -0.064
|
|
SLICE_X28Y76 FDRE (Hold_fdre_C_D) 0.012 -0.052 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[6]
|
|
-------------------------------------------------------------------
|
|
required time 0.052
|
|
arrival time 0.364
|
|
-------------------------------------------------------------------
|
|
slack 0.416
|
|
|
|
Slack (MET) : 0.420ns (arrival time - required time)
|
|
Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_0_5/RAMC_D1/CLK
|
|
(rising edge-triggered cell RAMD32 clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns})
|
|
Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[5]/D
|
|
(rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Path Group: sys_clk
|
|
Path Type: Hold (Min at Fast Process Corner)
|
|
Requirement: 0.000ns (sys_clk rise@0.000ns - mlkem_clk_clk_pll rise@0.000ns)
|
|
Data Path Delay: 1.054ns (logic 0.386ns (36.630%) route 0.668ns (63.370%))
|
|
Logic Levels: 0
|
|
Clock Path Skew: 0.361ns (DCD - SCD - CPR)
|
|
Destination Clock Delay (DCD): -0.359ns
|
|
Source Clock Delay (SCD): -0.621ns
|
|
Clock Pessimism Removal (CPR): -0.099ns
|
|
Clock Uncertainty: 0.197ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Discrete Jitter (DJ): 0.136ns
|
|
Phase Error (PE): 0.120ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock mlkem_clk_clk_pll rise edge)
|
|
0.000 0.000 r
|
|
K21 0.000 0.000 r clk (IN)
|
|
net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1
|
|
K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O
|
|
net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll
|
|
PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2)
|
|
-2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2
|
|
net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll
|
|
BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout3_buf/O
|
|
net (fo=26129, routed) 0.641 -0.621 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_0_5/WCLK
|
|
SLICE_X52Y75 RAMD32 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_0_5/RAMC_D1/CLK
|
|
------------------------------------------------------------------- -------------------
|
|
SLICE_X52Y75 RAMD32 (Prop_ramd32_CLK_O)
|
|
0.386 -0.235 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_0_5/RAMC_D1/O
|
|
net (fo=1, routed) 0.668 0.432 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port10__3[5]
|
|
SLICE_X28Y76 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[5]/D
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock sys_clk rise edge) 0.000 0.000 r
|
|
K21 0.000 0.000 r clk (IN)
|
|
net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1
|
|
K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O
|
|
net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll
|
|
PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1)
|
|
-2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1
|
|
net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll
|
|
BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O
|
|
net (fo=10004, routed) 0.949 -0.359 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/sys_clk
|
|
SLICE_X28Y76 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[5]/C
|
|
clock pessimism 0.099 -0.260
|
|
clock uncertainty 0.197 -0.064
|
|
SLICE_X28Y76 FDRE (Hold_fdre_C_D) 0.076 0.012 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[5]
|
|
-------------------------------------------------------------------
|
|
required time -0.012
|
|
arrival time 0.432
|
|
-------------------------------------------------------------------
|
|
slack 0.420
|
|
|
|
|
|
|
|
|
|
|
|
---------------------------------------------------------------------------------------------------
|
|
Path Group: **async_default**
|
|
From Clock: cpu_clk
|
|
To Clock: cpu_clk
|
|
|
|
Setup : NA Failing Endpoints, Worst Slack NA , Total Violation NA
|
|
Hold : 0 Failing Endpoints, Worst Slack 0.651ns, Total Violation 0.000ns
|
|
---------------------------------------------------------------------------------------------------
|
|
|
|
|
|
Min Delay Paths
|
|
--------------------------------------------------------------------------------------
|
|
Slack (MET) : 0.651ns (arrival time - required time)
|
|
Source: pll_clk.u_rst_cpu/delay_reg[1]/C
|
|
(rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns})
|
|
Destination: u_Axi_CDC/wFifo/popToPushGray_buffercc/buffers_0_reg[2]/CLR
|
|
(removal check against rising-edge clock cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns})
|
|
Path Group: **async_default**
|
|
Path Type: Removal (Min at Fast Process Corner)
|
|
Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns)
|
|
Data Path Delay: 0.779ns (logic 0.186ns (23.880%) route 0.593ns (76.120%))
|
|
Logic Levels: 1 (LUT1=1)
|
|
Clock Path Skew: 0.194ns (DCD - SCD - CPR)
|
|
Destination Clock Delay (DCD): -0.307ns
|
|
Source Clock Delay (SCD): -0.465ns
|
|
Clock Pessimism Removal (CPR): -0.037ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock cpu_clk rise edge) 0.000 0.000 r
|
|
K21 0.000 0.000 r clk (IN)
|
|
net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1
|
|
K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O
|
|
net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll
|
|
PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0)
|
|
-2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0
|
|
net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll
|
|
BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout1_buf/O
|
|
net (fo=6484, routed) 0.798 -0.465 pll_clk.u_rst_cpu/cpu_clk
|
|
SLICE_X0Y48 FDCE r pll_clk.u_rst_cpu/delay_reg[1]/C
|
|
------------------------------------------------------------------- -------------------
|
|
SLICE_X0Y48 FDCE (Prop_fdce_C_Q) 0.141 -0.324 r pll_clk.u_rst_cpu/delay_reg[1]/Q
|
|
net (fo=1, routed) 0.221 -0.103 pll_clk.u_rst_cpu/cpu_resetn
|
|
SLICE_X0Y48 LUT1 (Prop_lut1_I0_O) 0.045 -0.058 f pll_clk.u_rst_cpu/reset_i_1/O
|
|
net (fo=40, routed) 0.372 0.314 u_Axi_CDC/wFifo/popToPushGray_buffercc/p_0_in
|
|
SLICE_X6Y50 FDCE f u_Axi_CDC/wFifo/popToPushGray_buffercc/buffers_0_reg[2]/CLR
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock cpu_clk rise edge) 0.000 0.000 r
|
|
K21 0.000 0.000 r clk (IN)
|
|
net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1
|
|
K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O
|
|
net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll
|
|
PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0)
|
|
-2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0
|
|
net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll
|
|
BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout1_buf/O
|
|
net (fo=6484, routed) 1.001 -0.307 u_Axi_CDC/wFifo/popToPushGray_buffercc/cpu_clk
|
|
SLICE_X6Y50 FDCE r u_Axi_CDC/wFifo/popToPushGray_buffercc/buffers_0_reg[2]/C
|
|
clock pessimism 0.037 -0.270
|
|
SLICE_X6Y50 FDCE (Remov_fdce_C_CLR) -0.067 -0.337 u_Axi_CDC/wFifo/popToPushGray_buffercc/buffers_0_reg[2]
|
|
-------------------------------------------------------------------
|
|
required time 0.337
|
|
arrival time 0.314
|
|
-------------------------------------------------------------------
|
|
slack 0.651
|
|
|
|
Slack (MET) : 0.651ns (arrival time - required time)
|
|
Source: pll_clk.u_rst_cpu/delay_reg[1]/C
|
|
(rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns})
|
|
Destination: u_Axi_CDC/wFifo/popToPushGray_buffercc/buffers_0_reg[3]/CLR
|
|
(removal check against rising-edge clock cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns})
|
|
Path Group: **async_default**
|
|
Path Type: Removal (Min at Fast Process Corner)
|
|
Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns)
|
|
Data Path Delay: 0.779ns (logic 0.186ns (23.880%) route 0.593ns (76.120%))
|
|
Logic Levels: 1 (LUT1=1)
|
|
Clock Path Skew: 0.194ns (DCD - SCD - CPR)
|
|
Destination Clock Delay (DCD): -0.307ns
|
|
Source Clock Delay (SCD): -0.465ns
|
|
Clock Pessimism Removal (CPR): -0.037ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock cpu_clk rise edge) 0.000 0.000 r
|
|
K21 0.000 0.000 r clk (IN)
|
|
net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1
|
|
K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O
|
|
net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll
|
|
PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0)
|
|
-2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0
|
|
net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll
|
|
BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout1_buf/O
|
|
net (fo=6484, routed) 0.798 -0.465 pll_clk.u_rst_cpu/cpu_clk
|
|
SLICE_X0Y48 FDCE r pll_clk.u_rst_cpu/delay_reg[1]/C
|
|
------------------------------------------------------------------- -------------------
|
|
SLICE_X0Y48 FDCE (Prop_fdce_C_Q) 0.141 -0.324 r pll_clk.u_rst_cpu/delay_reg[1]/Q
|
|
net (fo=1, routed) 0.221 -0.103 pll_clk.u_rst_cpu/cpu_resetn
|
|
SLICE_X0Y48 LUT1 (Prop_lut1_I0_O) 0.045 -0.058 f pll_clk.u_rst_cpu/reset_i_1/O
|
|
net (fo=40, routed) 0.372 0.314 u_Axi_CDC/wFifo/popToPushGray_buffercc/p_0_in
|
|
SLICE_X6Y50 FDCE f u_Axi_CDC/wFifo/popToPushGray_buffercc/buffers_0_reg[3]/CLR
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock cpu_clk rise edge) 0.000 0.000 r
|
|
K21 0.000 0.000 r clk (IN)
|
|
net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1
|
|
K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O
|
|
net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll
|
|
PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0)
|
|
-2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0
|
|
net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll
|
|
BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout1_buf/O
|
|
net (fo=6484, routed) 1.001 -0.307 u_Axi_CDC/wFifo/popToPushGray_buffercc/cpu_clk
|
|
SLICE_X6Y50 FDCE r u_Axi_CDC/wFifo/popToPushGray_buffercc/buffers_0_reg[3]/C
|
|
clock pessimism 0.037 -0.270
|
|
SLICE_X6Y50 FDCE (Remov_fdce_C_CLR) -0.067 -0.337 u_Axi_CDC/wFifo/popToPushGray_buffercc/buffers_0_reg[3]
|
|
-------------------------------------------------------------------
|
|
required time 0.337
|
|
arrival time 0.314
|
|
-------------------------------------------------------------------
|
|
slack 0.651
|
|
|
|
Slack (MET) : 0.651ns (arrival time - required time)
|
|
Source: pll_clk.u_rst_cpu/delay_reg[1]/C
|
|
(rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns})
|
|
Destination: u_Axi_CDC/wFifo/popToPushGray_buffercc/buffers_1_reg[2]/CLR
|
|
(removal check against rising-edge clock cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns})
|
|
Path Group: **async_default**
|
|
Path Type: Removal (Min at Fast Process Corner)
|
|
Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns)
|
|
Data Path Delay: 0.779ns (logic 0.186ns (23.880%) route 0.593ns (76.120%))
|
|
Logic Levels: 1 (LUT1=1)
|
|
Clock Path Skew: 0.194ns (DCD - SCD - CPR)
|
|
Destination Clock Delay (DCD): -0.307ns
|
|
Source Clock Delay (SCD): -0.465ns
|
|
Clock Pessimism Removal (CPR): -0.037ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock cpu_clk rise edge) 0.000 0.000 r
|
|
K21 0.000 0.000 r clk (IN)
|
|
net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1
|
|
K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O
|
|
net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll
|
|
PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0)
|
|
-2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0
|
|
net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll
|
|
BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout1_buf/O
|
|
net (fo=6484, routed) 0.798 -0.465 pll_clk.u_rst_cpu/cpu_clk
|
|
SLICE_X0Y48 FDCE r pll_clk.u_rst_cpu/delay_reg[1]/C
|
|
------------------------------------------------------------------- -------------------
|
|
SLICE_X0Y48 FDCE (Prop_fdce_C_Q) 0.141 -0.324 r pll_clk.u_rst_cpu/delay_reg[1]/Q
|
|
net (fo=1, routed) 0.221 -0.103 pll_clk.u_rst_cpu/cpu_resetn
|
|
SLICE_X0Y48 LUT1 (Prop_lut1_I0_O) 0.045 -0.058 f pll_clk.u_rst_cpu/reset_i_1/O
|
|
net (fo=40, routed) 0.372 0.314 u_Axi_CDC/wFifo/popToPushGray_buffercc/p_0_in
|
|
SLICE_X6Y50 FDCE f u_Axi_CDC/wFifo/popToPushGray_buffercc/buffers_1_reg[2]/CLR
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock cpu_clk rise edge) 0.000 0.000 r
|
|
K21 0.000 0.000 r clk (IN)
|
|
net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1
|
|
K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O
|
|
net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll
|
|
PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0)
|
|
-2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0
|
|
net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll
|
|
BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout1_buf/O
|
|
net (fo=6484, routed) 1.001 -0.307 u_Axi_CDC/wFifo/popToPushGray_buffercc/cpu_clk
|
|
SLICE_X6Y50 FDCE r u_Axi_CDC/wFifo/popToPushGray_buffercc/buffers_1_reg[2]/C
|
|
clock pessimism 0.037 -0.270
|
|
SLICE_X6Y50 FDCE (Remov_fdce_C_CLR) -0.067 -0.337 u_Axi_CDC/wFifo/popToPushGray_buffercc/buffers_1_reg[2]
|
|
-------------------------------------------------------------------
|
|
required time 0.337
|
|
arrival time 0.314
|
|
-------------------------------------------------------------------
|
|
slack 0.651
|
|
|
|
Slack (MET) : 0.651ns (arrival time - required time)
|
|
Source: pll_clk.u_rst_cpu/delay_reg[1]/C
|
|
(rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns})
|
|
Destination: u_Axi_CDC/wFifo/popToPushGray_buffercc/buffers_1_reg[3]/CLR
|
|
(removal check against rising-edge clock cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns})
|
|
Path Group: **async_default**
|
|
Path Type: Removal (Min at Fast Process Corner)
|
|
Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns)
|
|
Data Path Delay: 0.779ns (logic 0.186ns (23.880%) route 0.593ns (76.120%))
|
|
Logic Levels: 1 (LUT1=1)
|
|
Clock Path Skew: 0.194ns (DCD - SCD - CPR)
|
|
Destination Clock Delay (DCD): -0.307ns
|
|
Source Clock Delay (SCD): -0.465ns
|
|
Clock Pessimism Removal (CPR): -0.037ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock cpu_clk rise edge) 0.000 0.000 r
|
|
K21 0.000 0.000 r clk (IN)
|
|
net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1
|
|
K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O
|
|
net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll
|
|
PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0)
|
|
-2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0
|
|
net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll
|
|
BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout1_buf/O
|
|
net (fo=6484, routed) 0.798 -0.465 pll_clk.u_rst_cpu/cpu_clk
|
|
SLICE_X0Y48 FDCE r pll_clk.u_rst_cpu/delay_reg[1]/C
|
|
------------------------------------------------------------------- -------------------
|
|
SLICE_X0Y48 FDCE (Prop_fdce_C_Q) 0.141 -0.324 r pll_clk.u_rst_cpu/delay_reg[1]/Q
|
|
net (fo=1, routed) 0.221 -0.103 pll_clk.u_rst_cpu/cpu_resetn
|
|
SLICE_X0Y48 LUT1 (Prop_lut1_I0_O) 0.045 -0.058 f pll_clk.u_rst_cpu/reset_i_1/O
|
|
net (fo=40, routed) 0.372 0.314 u_Axi_CDC/wFifo/popToPushGray_buffercc/p_0_in
|
|
SLICE_X6Y50 FDCE f u_Axi_CDC/wFifo/popToPushGray_buffercc/buffers_1_reg[3]/CLR
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock cpu_clk rise edge) 0.000 0.000 r
|
|
K21 0.000 0.000 r clk (IN)
|
|
net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1
|
|
K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O
|
|
net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll
|
|
PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0)
|
|
-2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0
|
|
net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll
|
|
BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout1_buf/O
|
|
net (fo=6484, routed) 1.001 -0.307 u_Axi_CDC/wFifo/popToPushGray_buffercc/cpu_clk
|
|
SLICE_X6Y50 FDCE r u_Axi_CDC/wFifo/popToPushGray_buffercc/buffers_1_reg[3]/C
|
|
clock pessimism 0.037 -0.270
|
|
SLICE_X6Y50 FDCE (Remov_fdce_C_CLR) -0.067 -0.337 u_Axi_CDC/wFifo/popToPushGray_buffercc/buffers_1_reg[3]
|
|
-------------------------------------------------------------------
|
|
required time 0.337
|
|
arrival time 0.314
|
|
-------------------------------------------------------------------
|
|
slack 0.651
|
|
|
|
Slack (MET) : 0.703ns (arrival time - required time)
|
|
Source: pll_clk.u_rst_cpu/delay_reg[1]/C
|
|
(rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns})
|
|
Destination: u_Axi_CDC/wFifo/popToPushGray_buffercc/buffers_0_reg[0]/CLR
|
|
(removal check against rising-edge clock cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns})
|
|
Path Group: **async_default**
|
|
Path Type: Removal (Min at Fast Process Corner)
|
|
Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns)
|
|
Data Path Delay: 0.627ns (logic 0.186ns (29.656%) route 0.441ns (70.344%))
|
|
Logic Levels: 1 (LUT1=1)
|
|
Clock Path Skew: 0.016ns (DCD - SCD - CPR)
|
|
Destination Clock Delay (DCD): -0.229ns
|
|
Source Clock Delay (SCD): -0.465ns
|
|
Clock Pessimism Removal (CPR): 0.220ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock cpu_clk rise edge) 0.000 0.000 r
|
|
K21 0.000 0.000 r clk (IN)
|
|
net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1
|
|
K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O
|
|
net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll
|
|
PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0)
|
|
-2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0
|
|
net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll
|
|
BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout1_buf/O
|
|
net (fo=6484, routed) 0.798 -0.465 pll_clk.u_rst_cpu/cpu_clk
|
|
SLICE_X0Y48 FDCE r pll_clk.u_rst_cpu/delay_reg[1]/C
|
|
------------------------------------------------------------------- -------------------
|
|
SLICE_X0Y48 FDCE (Prop_fdce_C_Q) 0.141 -0.324 r pll_clk.u_rst_cpu/delay_reg[1]/Q
|
|
net (fo=1, routed) 0.221 -0.103 pll_clk.u_rst_cpu/cpu_resetn
|
|
SLICE_X0Y48 LUT1 (Prop_lut1_I0_O) 0.045 -0.058 f pll_clk.u_rst_cpu/reset_i_1/O
|
|
net (fo=40, routed) 0.220 0.162 u_Axi_CDC/wFifo/popToPushGray_buffercc/p_0_in
|
|
SLICE_X0Y49 FDCE f u_Axi_CDC/wFifo/popToPushGray_buffercc/buffers_0_reg[0]/CLR
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock cpu_clk rise edge) 0.000 0.000 r
|
|
K21 0.000 0.000 r clk (IN)
|
|
net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1
|
|
K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O
|
|
net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll
|
|
PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0)
|
|
-2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0
|
|
net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll
|
|
BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout1_buf/O
|
|
net (fo=6484, routed) 1.079 -0.229 u_Axi_CDC/wFifo/popToPushGray_buffercc/cpu_clk
|
|
SLICE_X0Y49 FDCE r u_Axi_CDC/wFifo/popToPushGray_buffercc/buffers_0_reg[0]/C
|
|
clock pessimism -0.220 -0.449
|
|
SLICE_X0Y49 FDCE (Remov_fdce_C_CLR) -0.092 -0.541 u_Axi_CDC/wFifo/popToPushGray_buffercc/buffers_0_reg[0]
|
|
-------------------------------------------------------------------
|
|
required time 0.541
|
|
arrival time 0.162
|
|
-------------------------------------------------------------------
|
|
slack 0.703
|
|
|
|
Slack (MET) : 0.703ns (arrival time - required time)
|
|
Source: pll_clk.u_rst_cpu/delay_reg[1]/C
|
|
(rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns})
|
|
Destination: u_Axi_CDC/wFifo/popToPushGray_buffercc/buffers_0_reg[1]/CLR
|
|
(removal check against rising-edge clock cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns})
|
|
Path Group: **async_default**
|
|
Path Type: Removal (Min at Fast Process Corner)
|
|
Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns)
|
|
Data Path Delay: 0.627ns (logic 0.186ns (29.656%) route 0.441ns (70.344%))
|
|
Logic Levels: 1 (LUT1=1)
|
|
Clock Path Skew: 0.016ns (DCD - SCD - CPR)
|
|
Destination Clock Delay (DCD): -0.229ns
|
|
Source Clock Delay (SCD): -0.465ns
|
|
Clock Pessimism Removal (CPR): 0.220ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock cpu_clk rise edge) 0.000 0.000 r
|
|
K21 0.000 0.000 r clk (IN)
|
|
net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1
|
|
K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O
|
|
net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll
|
|
PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0)
|
|
-2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0
|
|
net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll
|
|
BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout1_buf/O
|
|
net (fo=6484, routed) 0.798 -0.465 pll_clk.u_rst_cpu/cpu_clk
|
|
SLICE_X0Y48 FDCE r pll_clk.u_rst_cpu/delay_reg[1]/C
|
|
------------------------------------------------------------------- -------------------
|
|
SLICE_X0Y48 FDCE (Prop_fdce_C_Q) 0.141 -0.324 r pll_clk.u_rst_cpu/delay_reg[1]/Q
|
|
net (fo=1, routed) 0.221 -0.103 pll_clk.u_rst_cpu/cpu_resetn
|
|
SLICE_X0Y48 LUT1 (Prop_lut1_I0_O) 0.045 -0.058 f pll_clk.u_rst_cpu/reset_i_1/O
|
|
net (fo=40, routed) 0.220 0.162 u_Axi_CDC/wFifo/popToPushGray_buffercc/p_0_in
|
|
SLICE_X0Y49 FDCE f u_Axi_CDC/wFifo/popToPushGray_buffercc/buffers_0_reg[1]/CLR
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock cpu_clk rise edge) 0.000 0.000 r
|
|
K21 0.000 0.000 r clk (IN)
|
|
net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1
|
|
K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O
|
|
net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll
|
|
PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0)
|
|
-2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0
|
|
net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll
|
|
BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout1_buf/O
|
|
net (fo=6484, routed) 1.079 -0.229 u_Axi_CDC/wFifo/popToPushGray_buffercc/cpu_clk
|
|
SLICE_X0Y49 FDCE r u_Axi_CDC/wFifo/popToPushGray_buffercc/buffers_0_reg[1]/C
|
|
clock pessimism -0.220 -0.449
|
|
SLICE_X0Y49 FDCE (Remov_fdce_C_CLR) -0.092 -0.541 u_Axi_CDC/wFifo/popToPushGray_buffercc/buffers_0_reg[1]
|
|
-------------------------------------------------------------------
|
|
required time 0.541
|
|
arrival time 0.162
|
|
-------------------------------------------------------------------
|
|
slack 0.703
|
|
|
|
Slack (MET) : 0.703ns (arrival time - required time)
|
|
Source: pll_clk.u_rst_cpu/delay_reg[1]/C
|
|
(rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns})
|
|
Destination: u_Axi_CDC/wFifo/popToPushGray_buffercc/buffers_1_reg[0]/CLR
|
|
(removal check against rising-edge clock cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns})
|
|
Path Group: **async_default**
|
|
Path Type: Removal (Min at Fast Process Corner)
|
|
Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns)
|
|
Data Path Delay: 0.627ns (logic 0.186ns (29.656%) route 0.441ns (70.344%))
|
|
Logic Levels: 1 (LUT1=1)
|
|
Clock Path Skew: 0.016ns (DCD - SCD - CPR)
|
|
Destination Clock Delay (DCD): -0.229ns
|
|
Source Clock Delay (SCD): -0.465ns
|
|
Clock Pessimism Removal (CPR): 0.220ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock cpu_clk rise edge) 0.000 0.000 r
|
|
K21 0.000 0.000 r clk (IN)
|
|
net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1
|
|
K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O
|
|
net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll
|
|
PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0)
|
|
-2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0
|
|
net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll
|
|
BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout1_buf/O
|
|
net (fo=6484, routed) 0.798 -0.465 pll_clk.u_rst_cpu/cpu_clk
|
|
SLICE_X0Y48 FDCE r pll_clk.u_rst_cpu/delay_reg[1]/C
|
|
------------------------------------------------------------------- -------------------
|
|
SLICE_X0Y48 FDCE (Prop_fdce_C_Q) 0.141 -0.324 r pll_clk.u_rst_cpu/delay_reg[1]/Q
|
|
net (fo=1, routed) 0.221 -0.103 pll_clk.u_rst_cpu/cpu_resetn
|
|
SLICE_X0Y48 LUT1 (Prop_lut1_I0_O) 0.045 -0.058 f pll_clk.u_rst_cpu/reset_i_1/O
|
|
net (fo=40, routed) 0.220 0.162 u_Axi_CDC/wFifo/popToPushGray_buffercc/p_0_in
|
|
SLICE_X0Y49 FDCE f u_Axi_CDC/wFifo/popToPushGray_buffercc/buffers_1_reg[0]/CLR
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock cpu_clk rise edge) 0.000 0.000 r
|
|
K21 0.000 0.000 r clk (IN)
|
|
net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1
|
|
K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O
|
|
net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll
|
|
PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0)
|
|
-2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0
|
|
net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll
|
|
BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout1_buf/O
|
|
net (fo=6484, routed) 1.079 -0.229 u_Axi_CDC/wFifo/popToPushGray_buffercc/cpu_clk
|
|
SLICE_X0Y49 FDCE r u_Axi_CDC/wFifo/popToPushGray_buffercc/buffers_1_reg[0]/C
|
|
clock pessimism -0.220 -0.449
|
|
SLICE_X0Y49 FDCE (Remov_fdce_C_CLR) -0.092 -0.541 u_Axi_CDC/wFifo/popToPushGray_buffercc/buffers_1_reg[0]
|
|
-------------------------------------------------------------------
|
|
required time 0.541
|
|
arrival time 0.162
|
|
-------------------------------------------------------------------
|
|
slack 0.703
|
|
|
|
Slack (MET) : 0.703ns (arrival time - required time)
|
|
Source: pll_clk.u_rst_cpu/delay_reg[1]/C
|
|
(rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns})
|
|
Destination: u_Axi_CDC/wFifo/popToPushGray_buffercc/buffers_1_reg[1]/CLR
|
|
(removal check against rising-edge clock cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns})
|
|
Path Group: **async_default**
|
|
Path Type: Removal (Min at Fast Process Corner)
|
|
Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns)
|
|
Data Path Delay: 0.627ns (logic 0.186ns (29.656%) route 0.441ns (70.344%))
|
|
Logic Levels: 1 (LUT1=1)
|
|
Clock Path Skew: 0.016ns (DCD - SCD - CPR)
|
|
Destination Clock Delay (DCD): -0.229ns
|
|
Source Clock Delay (SCD): -0.465ns
|
|
Clock Pessimism Removal (CPR): 0.220ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock cpu_clk rise edge) 0.000 0.000 r
|
|
K21 0.000 0.000 r clk (IN)
|
|
net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1
|
|
K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O
|
|
net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll
|
|
PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0)
|
|
-2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0
|
|
net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll
|
|
BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout1_buf/O
|
|
net (fo=6484, routed) 0.798 -0.465 pll_clk.u_rst_cpu/cpu_clk
|
|
SLICE_X0Y48 FDCE r pll_clk.u_rst_cpu/delay_reg[1]/C
|
|
------------------------------------------------------------------- -------------------
|
|
SLICE_X0Y48 FDCE (Prop_fdce_C_Q) 0.141 -0.324 r pll_clk.u_rst_cpu/delay_reg[1]/Q
|
|
net (fo=1, routed) 0.221 -0.103 pll_clk.u_rst_cpu/cpu_resetn
|
|
SLICE_X0Y48 LUT1 (Prop_lut1_I0_O) 0.045 -0.058 f pll_clk.u_rst_cpu/reset_i_1/O
|
|
net (fo=40, routed) 0.220 0.162 u_Axi_CDC/wFifo/popToPushGray_buffercc/p_0_in
|
|
SLICE_X0Y49 FDCE f u_Axi_CDC/wFifo/popToPushGray_buffercc/buffers_1_reg[1]/CLR
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock cpu_clk rise edge) 0.000 0.000 r
|
|
K21 0.000 0.000 r clk (IN)
|
|
net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1
|
|
K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O
|
|
net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll
|
|
PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0)
|
|
-2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0
|
|
net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll
|
|
BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout1_buf/O
|
|
net (fo=6484, routed) 1.079 -0.229 u_Axi_CDC/wFifo/popToPushGray_buffercc/cpu_clk
|
|
SLICE_X0Y49 FDCE r u_Axi_CDC/wFifo/popToPushGray_buffercc/buffers_1_reg[1]/C
|
|
clock pessimism -0.220 -0.449
|
|
SLICE_X0Y49 FDCE (Remov_fdce_C_CLR) -0.092 -0.541 u_Axi_CDC/wFifo/popToPushGray_buffercc/buffers_1_reg[1]
|
|
-------------------------------------------------------------------
|
|
required time 0.541
|
|
arrival time 0.162
|
|
-------------------------------------------------------------------
|
|
slack 0.703
|
|
|
|
Slack (MET) : 0.885ns (arrival time - required time)
|
|
Source: u_Axi_CDC/bFifo/bufferCC_12/buffers_1_reg/C
|
|
(rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns})
|
|
Destination: u_Axi_CDC/bFifo/popCC_popPtr_reg[0]/CLR
|
|
(removal check against rising-edge clock cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns})
|
|
Path Group: **async_default**
|
|
Path Type: Removal (Min at Fast Process Corner)
|
|
Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns)
|
|
Data Path Delay: 0.838ns (logic 0.227ns (27.080%) route 0.611ns (72.920%))
|
|
Logic Levels: 1 (LUT1=1)
|
|
Clock Path Skew: 0.045ns (DCD - SCD - CPR)
|
|
Destination Clock Delay (DCD): -0.338ns
|
|
Source Clock Delay (SCD): -0.575ns
|
|
Clock Pessimism Removal (CPR): 0.192ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock cpu_clk rise edge) 0.000 0.000 r
|
|
K21 0.000 0.000 r clk (IN)
|
|
net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1
|
|
K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O
|
|
net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll
|
|
PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0)
|
|
-2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0
|
|
net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll
|
|
BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout1_buf/O
|
|
net (fo=6484, routed) 0.687 -0.575 u_Axi_CDC/bFifo/bufferCC_12/cpu_clk
|
|
SLICE_X30Y58 FDCE r u_Axi_CDC/bFifo/bufferCC_12/buffers_1_reg/C
|
|
------------------------------------------------------------------- -------------------
|
|
SLICE_X30Y58 FDCE (Prop_fdce_C_Q) 0.128 -0.447 r u_Axi_CDC/bFifo/bufferCC_12/buffers_1_reg/Q
|
|
net (fo=1, routed) 0.207 -0.241 u_Axi_CDC/bFifo/bufferCC_12/buffers_1
|
|
SLICE_X28Y58 LUT1 (Prop_lut1_I0_O) 0.099 -0.142 f u_Axi_CDC/bFifo/bufferCC_12/popCC_popPtr[2]_i_2__0/O
|
|
net (fo=30, routed) 0.404 0.263 u_Axi_CDC/bFifo/buffers_1_reg
|
|
SLICE_X19Y58 FDCE f u_Axi_CDC/bFifo/popCC_popPtr_reg[0]/CLR
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock cpu_clk rise edge) 0.000 0.000 r
|
|
K21 0.000 0.000 r clk (IN)
|
|
net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1
|
|
K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O
|
|
net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll
|
|
PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0)
|
|
-2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0
|
|
net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll
|
|
BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout1_buf/O
|
|
net (fo=6484, routed) 0.970 -0.338 u_Axi_CDC/bFifo/cpu_clk
|
|
SLICE_X19Y58 FDCE r u_Axi_CDC/bFifo/popCC_popPtr_reg[0]/C
|
|
clock pessimism -0.192 -0.530
|
|
SLICE_X19Y58 FDCE (Remov_fdce_C_CLR) -0.092 -0.622 u_Axi_CDC/bFifo/popCC_popPtr_reg[0]
|
|
-------------------------------------------------------------------
|
|
required time 0.622
|
|
arrival time 0.263
|
|
-------------------------------------------------------------------
|
|
slack 0.885
|
|
|
|
Slack (MET) : 0.885ns (arrival time - required time)
|
|
Source: u_Axi_CDC/bFifo/bufferCC_12/buffers_1_reg/C
|
|
(rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns})
|
|
Destination: u_Axi_CDC/bFifo/popCC_popPtr_reg[1]/CLR
|
|
(removal check against rising-edge clock cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns})
|
|
Path Group: **async_default**
|
|
Path Type: Removal (Min at Fast Process Corner)
|
|
Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns)
|
|
Data Path Delay: 0.838ns (logic 0.227ns (27.080%) route 0.611ns (72.920%))
|
|
Logic Levels: 1 (LUT1=1)
|
|
Clock Path Skew: 0.045ns (DCD - SCD - CPR)
|
|
Destination Clock Delay (DCD): -0.338ns
|
|
Source Clock Delay (SCD): -0.575ns
|
|
Clock Pessimism Removal (CPR): 0.192ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock cpu_clk rise edge) 0.000 0.000 r
|
|
K21 0.000 0.000 r clk (IN)
|
|
net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1
|
|
K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O
|
|
net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll
|
|
PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0)
|
|
-2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0
|
|
net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll
|
|
BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout1_buf/O
|
|
net (fo=6484, routed) 0.687 -0.575 u_Axi_CDC/bFifo/bufferCC_12/cpu_clk
|
|
SLICE_X30Y58 FDCE r u_Axi_CDC/bFifo/bufferCC_12/buffers_1_reg/C
|
|
------------------------------------------------------------------- -------------------
|
|
SLICE_X30Y58 FDCE (Prop_fdce_C_Q) 0.128 -0.447 r u_Axi_CDC/bFifo/bufferCC_12/buffers_1_reg/Q
|
|
net (fo=1, routed) 0.207 -0.241 u_Axi_CDC/bFifo/bufferCC_12/buffers_1
|
|
SLICE_X28Y58 LUT1 (Prop_lut1_I0_O) 0.099 -0.142 f u_Axi_CDC/bFifo/bufferCC_12/popCC_popPtr[2]_i_2__0/O
|
|
net (fo=30, routed) 0.404 0.263 u_Axi_CDC/bFifo/buffers_1_reg
|
|
SLICE_X19Y58 FDCE f u_Axi_CDC/bFifo/popCC_popPtr_reg[1]/CLR
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock cpu_clk rise edge) 0.000 0.000 r
|
|
K21 0.000 0.000 r clk (IN)
|
|
net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1
|
|
K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O
|
|
net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll
|
|
PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0)
|
|
-2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0
|
|
net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll
|
|
BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout1_buf/O
|
|
net (fo=6484, routed) 0.970 -0.338 u_Axi_CDC/bFifo/cpu_clk
|
|
SLICE_X19Y58 FDCE r u_Axi_CDC/bFifo/popCC_popPtr_reg[1]/C
|
|
clock pessimism -0.192 -0.530
|
|
SLICE_X19Y58 FDCE (Remov_fdce_C_CLR) -0.092 -0.622 u_Axi_CDC/bFifo/popCC_popPtr_reg[1]
|
|
-------------------------------------------------------------------
|
|
required time 0.622
|
|
arrival time 0.263
|
|
-------------------------------------------------------------------
|
|
slack 0.885
|
|
|
|
Slack (MET) : 0.885ns (arrival time - required time)
|
|
Source: u_Axi_CDC/bFifo/bufferCC_12/buffers_1_reg/C
|
|
(rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns})
|
|
Destination: u_Axi_CDC/bFifo/popCC_ptrToPush_reg[0]/CLR
|
|
(removal check against rising-edge clock cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns})
|
|
Path Group: **async_default**
|
|
Path Type: Removal (Min at Fast Process Corner)
|
|
Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns)
|
|
Data Path Delay: 0.838ns (logic 0.227ns (27.080%) route 0.611ns (72.920%))
|
|
Logic Levels: 1 (LUT1=1)
|
|
Clock Path Skew: 0.045ns (DCD - SCD - CPR)
|
|
Destination Clock Delay (DCD): -0.338ns
|
|
Source Clock Delay (SCD): -0.575ns
|
|
Clock Pessimism Removal (CPR): 0.192ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock cpu_clk rise edge) 0.000 0.000 r
|
|
K21 0.000 0.000 r clk (IN)
|
|
net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1
|
|
K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O
|
|
net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll
|
|
PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0)
|
|
-2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0
|
|
net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll
|
|
BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout1_buf/O
|
|
net (fo=6484, routed) 0.687 -0.575 u_Axi_CDC/bFifo/bufferCC_12/cpu_clk
|
|
SLICE_X30Y58 FDCE r u_Axi_CDC/bFifo/bufferCC_12/buffers_1_reg/C
|
|
------------------------------------------------------------------- -------------------
|
|
SLICE_X30Y58 FDCE (Prop_fdce_C_Q) 0.128 -0.447 r u_Axi_CDC/bFifo/bufferCC_12/buffers_1_reg/Q
|
|
net (fo=1, routed) 0.207 -0.241 u_Axi_CDC/bFifo/bufferCC_12/buffers_1
|
|
SLICE_X28Y58 LUT1 (Prop_lut1_I0_O) 0.099 -0.142 f u_Axi_CDC/bFifo/bufferCC_12/popCC_popPtr[2]_i_2__0/O
|
|
net (fo=30, routed) 0.404 0.263 u_Axi_CDC/bFifo/buffers_1_reg
|
|
SLICE_X19Y58 FDCE f u_Axi_CDC/bFifo/popCC_ptrToPush_reg[0]/CLR
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock cpu_clk rise edge) 0.000 0.000 r
|
|
K21 0.000 0.000 r clk (IN)
|
|
net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1
|
|
K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O
|
|
net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll
|
|
PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0)
|
|
-2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0
|
|
net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll
|
|
BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout1_buf/O
|
|
net (fo=6484, routed) 0.970 -0.338 u_Axi_CDC/bFifo/cpu_clk
|
|
SLICE_X19Y58 FDCE r u_Axi_CDC/bFifo/popCC_ptrToPush_reg[0]/C
|
|
clock pessimism -0.192 -0.530
|
|
SLICE_X19Y58 FDCE (Remov_fdce_C_CLR) -0.092 -0.622 u_Axi_CDC/bFifo/popCC_ptrToPush_reg[0]
|
|
-------------------------------------------------------------------
|
|
required time 0.622
|
|
arrival time 0.263
|
|
-------------------------------------------------------------------
|
|
slack 0.885
|
|
|
|
Slack (MET) : 0.936ns (arrival time - required time)
|
|
Source: pll_clk.u_rst_cpu/delay_reg[1]/C
|
|
(rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns})
|
|
Destination: u_Axi_CDC/wFifo/pushCC_pushPtrGray_reg[0]/CLR
|
|
(removal check against rising-edge clock cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns})
|
|
Path Group: **async_default**
|
|
Path Type: Removal (Min at Fast Process Corner)
|
|
Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns)
|
|
Data Path Delay: 0.860ns (logic 0.186ns (21.621%) route 0.674ns (78.379%))
|
|
Logic Levels: 1 (LUT1=1)
|
|
Clock Path Skew: 0.016ns (DCD - SCD - CPR)
|
|
Destination Clock Delay (DCD): -0.229ns
|
|
Source Clock Delay (SCD): -0.465ns
|
|
Clock Pessimism Removal (CPR): 0.220ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock cpu_clk rise edge) 0.000 0.000 r
|
|
K21 0.000 0.000 r clk (IN)
|
|
net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1
|
|
K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O
|
|
net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll
|
|
PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0)
|
|
-2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0
|
|
net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll
|
|
BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout1_buf/O
|
|
net (fo=6484, routed) 0.798 -0.465 pll_clk.u_rst_cpu/cpu_clk
|
|
SLICE_X0Y48 FDCE r pll_clk.u_rst_cpu/delay_reg[1]/C
|
|
------------------------------------------------------------------- -------------------
|
|
SLICE_X0Y48 FDCE (Prop_fdce_C_Q) 0.141 -0.324 r pll_clk.u_rst_cpu/delay_reg[1]/Q
|
|
net (fo=1, routed) 0.221 -0.103 pll_clk.u_rst_cpu/cpu_resetn
|
|
SLICE_X0Y48 LUT1 (Prop_lut1_I0_O) 0.045 -0.058 f pll_clk.u_rst_cpu/reset_i_1/O
|
|
net (fo=40, routed) 0.453 0.395 u_Axi_CDC/wFifo/p_0_in
|
|
SLICE_X3Y49 FDCE f u_Axi_CDC/wFifo/pushCC_pushPtrGray_reg[0]/CLR
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock cpu_clk rise edge) 0.000 0.000 r
|
|
K21 0.000 0.000 r clk (IN)
|
|
net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1
|
|
K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O
|
|
net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll
|
|
PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0)
|
|
-2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0
|
|
net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll
|
|
BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout1_buf/O
|
|
net (fo=6484, routed) 1.079 -0.229 u_Axi_CDC/wFifo/cpu_clk
|
|
SLICE_X3Y49 FDCE r u_Axi_CDC/wFifo/pushCC_pushPtrGray_reg[0]/C
|
|
clock pessimism -0.220 -0.449
|
|
SLICE_X3Y49 FDCE (Remov_fdce_C_CLR) -0.092 -0.541 u_Axi_CDC/wFifo/pushCC_pushPtrGray_reg[0]
|
|
-------------------------------------------------------------------
|
|
required time 0.541
|
|
arrival time 0.395
|
|
-------------------------------------------------------------------
|
|
slack 0.936
|
|
|
|
Slack (MET) : 0.936ns (arrival time - required time)
|
|
Source: pll_clk.u_rst_cpu/delay_reg[1]/C
|
|
(rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns})
|
|
Destination: u_Axi_CDC/wFifo/pushCC_pushPtrGray_reg[1]/CLR
|
|
(removal check against rising-edge clock cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns})
|
|
Path Group: **async_default**
|
|
Path Type: Removal (Min at Fast Process Corner)
|
|
Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns)
|
|
Data Path Delay: 0.860ns (logic 0.186ns (21.621%) route 0.674ns (78.379%))
|
|
Logic Levels: 1 (LUT1=1)
|
|
Clock Path Skew: 0.016ns (DCD - SCD - CPR)
|
|
Destination Clock Delay (DCD): -0.229ns
|
|
Source Clock Delay (SCD): -0.465ns
|
|
Clock Pessimism Removal (CPR): 0.220ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock cpu_clk rise edge) 0.000 0.000 r
|
|
K21 0.000 0.000 r clk (IN)
|
|
net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1
|
|
K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O
|
|
net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll
|
|
PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0)
|
|
-2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0
|
|
net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll
|
|
BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout1_buf/O
|
|
net (fo=6484, routed) 0.798 -0.465 pll_clk.u_rst_cpu/cpu_clk
|
|
SLICE_X0Y48 FDCE r pll_clk.u_rst_cpu/delay_reg[1]/C
|
|
------------------------------------------------------------------- -------------------
|
|
SLICE_X0Y48 FDCE (Prop_fdce_C_Q) 0.141 -0.324 r pll_clk.u_rst_cpu/delay_reg[1]/Q
|
|
net (fo=1, routed) 0.221 -0.103 pll_clk.u_rst_cpu/cpu_resetn
|
|
SLICE_X0Y48 LUT1 (Prop_lut1_I0_O) 0.045 -0.058 f pll_clk.u_rst_cpu/reset_i_1/O
|
|
net (fo=40, routed) 0.453 0.395 u_Axi_CDC/wFifo/p_0_in
|
|
SLICE_X3Y49 FDCE f u_Axi_CDC/wFifo/pushCC_pushPtrGray_reg[1]/CLR
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock cpu_clk rise edge) 0.000 0.000 r
|
|
K21 0.000 0.000 r clk (IN)
|
|
net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1
|
|
K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O
|
|
net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll
|
|
PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0)
|
|
-2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0
|
|
net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll
|
|
BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout1_buf/O
|
|
net (fo=6484, routed) 1.079 -0.229 u_Axi_CDC/wFifo/cpu_clk
|
|
SLICE_X3Y49 FDCE r u_Axi_CDC/wFifo/pushCC_pushPtrGray_reg[1]/C
|
|
clock pessimism -0.220 -0.449
|
|
SLICE_X3Y49 FDCE (Remov_fdce_C_CLR) -0.092 -0.541 u_Axi_CDC/wFifo/pushCC_pushPtrGray_reg[1]
|
|
-------------------------------------------------------------------
|
|
required time 0.541
|
|
arrival time 0.395
|
|
-------------------------------------------------------------------
|
|
slack 0.936
|
|
|
|
Slack (MET) : 0.936ns (arrival time - required time)
|
|
Source: pll_clk.u_rst_cpu/delay_reg[1]/C
|
|
(rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns})
|
|
Destination: u_Axi_CDC/wFifo/pushCC_pushPtrGray_reg[2]/CLR
|
|
(removal check against rising-edge clock cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns})
|
|
Path Group: **async_default**
|
|
Path Type: Removal (Min at Fast Process Corner)
|
|
Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns)
|
|
Data Path Delay: 0.860ns (logic 0.186ns (21.621%) route 0.674ns (78.379%))
|
|
Logic Levels: 1 (LUT1=1)
|
|
Clock Path Skew: 0.016ns (DCD - SCD - CPR)
|
|
Destination Clock Delay (DCD): -0.229ns
|
|
Source Clock Delay (SCD): -0.465ns
|
|
Clock Pessimism Removal (CPR): 0.220ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock cpu_clk rise edge) 0.000 0.000 r
|
|
K21 0.000 0.000 r clk (IN)
|
|
net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1
|
|
K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O
|
|
net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll
|
|
PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0)
|
|
-2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0
|
|
net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll
|
|
BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout1_buf/O
|
|
net (fo=6484, routed) 0.798 -0.465 pll_clk.u_rst_cpu/cpu_clk
|
|
SLICE_X0Y48 FDCE r pll_clk.u_rst_cpu/delay_reg[1]/C
|
|
------------------------------------------------------------------- -------------------
|
|
SLICE_X0Y48 FDCE (Prop_fdce_C_Q) 0.141 -0.324 r pll_clk.u_rst_cpu/delay_reg[1]/Q
|
|
net (fo=1, routed) 0.221 -0.103 pll_clk.u_rst_cpu/cpu_resetn
|
|
SLICE_X0Y48 LUT1 (Prop_lut1_I0_O) 0.045 -0.058 f pll_clk.u_rst_cpu/reset_i_1/O
|
|
net (fo=40, routed) 0.453 0.395 u_Axi_CDC/wFifo/p_0_in
|
|
SLICE_X3Y49 FDCE f u_Axi_CDC/wFifo/pushCC_pushPtrGray_reg[2]/CLR
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock cpu_clk rise edge) 0.000 0.000 r
|
|
K21 0.000 0.000 r clk (IN)
|
|
net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1
|
|
K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O
|
|
net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll
|
|
PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0)
|
|
-2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0
|
|
net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll
|
|
BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout1_buf/O
|
|
net (fo=6484, routed) 1.079 -0.229 u_Axi_CDC/wFifo/cpu_clk
|
|
SLICE_X3Y49 FDCE r u_Axi_CDC/wFifo/pushCC_pushPtrGray_reg[2]/C
|
|
clock pessimism -0.220 -0.449
|
|
SLICE_X3Y49 FDCE (Remov_fdce_C_CLR) -0.092 -0.541 u_Axi_CDC/wFifo/pushCC_pushPtrGray_reg[2]
|
|
-------------------------------------------------------------------
|
|
required time 0.541
|
|
arrival time 0.395
|
|
-------------------------------------------------------------------
|
|
slack 0.936
|
|
|
|
Slack (MET) : 0.936ns (arrival time - required time)
|
|
Source: pll_clk.u_rst_cpu/delay_reg[1]/C
|
|
(rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns})
|
|
Destination: u_Axi_CDC/wFifo/pushCC_pushPtrGray_reg[3]/CLR
|
|
(removal check against rising-edge clock cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns})
|
|
Path Group: **async_default**
|
|
Path Type: Removal (Min at Fast Process Corner)
|
|
Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns)
|
|
Data Path Delay: 0.860ns (logic 0.186ns (21.621%) route 0.674ns (78.379%))
|
|
Logic Levels: 1 (LUT1=1)
|
|
Clock Path Skew: 0.016ns (DCD - SCD - CPR)
|
|
Destination Clock Delay (DCD): -0.229ns
|
|
Source Clock Delay (SCD): -0.465ns
|
|
Clock Pessimism Removal (CPR): 0.220ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock cpu_clk rise edge) 0.000 0.000 r
|
|
K21 0.000 0.000 r clk (IN)
|
|
net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1
|
|
K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O
|
|
net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll
|
|
PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0)
|
|
-2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0
|
|
net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll
|
|
BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout1_buf/O
|
|
net (fo=6484, routed) 0.798 -0.465 pll_clk.u_rst_cpu/cpu_clk
|
|
SLICE_X0Y48 FDCE r pll_clk.u_rst_cpu/delay_reg[1]/C
|
|
------------------------------------------------------------------- -------------------
|
|
SLICE_X0Y48 FDCE (Prop_fdce_C_Q) 0.141 -0.324 r pll_clk.u_rst_cpu/delay_reg[1]/Q
|
|
net (fo=1, routed) 0.221 -0.103 pll_clk.u_rst_cpu/cpu_resetn
|
|
SLICE_X0Y48 LUT1 (Prop_lut1_I0_O) 0.045 -0.058 f pll_clk.u_rst_cpu/reset_i_1/O
|
|
net (fo=40, routed) 0.453 0.395 u_Axi_CDC/wFifo/p_0_in
|
|
SLICE_X3Y49 FDCE f u_Axi_CDC/wFifo/pushCC_pushPtrGray_reg[3]/CLR
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock cpu_clk rise edge) 0.000 0.000 r
|
|
K21 0.000 0.000 r clk (IN)
|
|
net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1
|
|
K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O
|
|
net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll
|
|
PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0)
|
|
-2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0
|
|
net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll
|
|
BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout1_buf/O
|
|
net (fo=6484, routed) 1.079 -0.229 u_Axi_CDC/wFifo/cpu_clk
|
|
SLICE_X3Y49 FDCE r u_Axi_CDC/wFifo/pushCC_pushPtrGray_reg[3]/C
|
|
clock pessimism -0.220 -0.449
|
|
SLICE_X3Y49 FDCE (Remov_fdce_C_CLR) -0.092 -0.541 u_Axi_CDC/wFifo/pushCC_pushPtrGray_reg[3]
|
|
-------------------------------------------------------------------
|
|
required time 0.541
|
|
arrival time 0.395
|
|
-------------------------------------------------------------------
|
|
slack 0.936
|
|
|
|
Slack (MET) : 0.936ns (arrival time - required time)
|
|
Source: pll_clk.u_rst_cpu/delay_reg[1]/C
|
|
(rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns})
|
|
Destination: u_Axi_CDC/wFifo/pushCC_pushPtr_reg[0]/CLR
|
|
(removal check against rising-edge clock cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns})
|
|
Path Group: **async_default**
|
|
Path Type: Removal (Min at Fast Process Corner)
|
|
Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns)
|
|
Data Path Delay: 0.860ns (logic 0.186ns (21.621%) route 0.674ns (78.379%))
|
|
Logic Levels: 1 (LUT1=1)
|
|
Clock Path Skew: 0.016ns (DCD - SCD - CPR)
|
|
Destination Clock Delay (DCD): -0.229ns
|
|
Source Clock Delay (SCD): -0.465ns
|
|
Clock Pessimism Removal (CPR): 0.220ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock cpu_clk rise edge) 0.000 0.000 r
|
|
K21 0.000 0.000 r clk (IN)
|
|
net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1
|
|
K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O
|
|
net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll
|
|
PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0)
|
|
-2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0
|
|
net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll
|
|
BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout1_buf/O
|
|
net (fo=6484, routed) 0.798 -0.465 pll_clk.u_rst_cpu/cpu_clk
|
|
SLICE_X0Y48 FDCE r pll_clk.u_rst_cpu/delay_reg[1]/C
|
|
------------------------------------------------------------------- -------------------
|
|
SLICE_X0Y48 FDCE (Prop_fdce_C_Q) 0.141 -0.324 r pll_clk.u_rst_cpu/delay_reg[1]/Q
|
|
net (fo=1, routed) 0.221 -0.103 pll_clk.u_rst_cpu/cpu_resetn
|
|
SLICE_X0Y48 LUT1 (Prop_lut1_I0_O) 0.045 -0.058 f pll_clk.u_rst_cpu/reset_i_1/O
|
|
net (fo=40, routed) 0.453 0.395 u_Axi_CDC/wFifo/p_0_in
|
|
SLICE_X3Y49 FDCE f u_Axi_CDC/wFifo/pushCC_pushPtr_reg[0]/CLR
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock cpu_clk rise edge) 0.000 0.000 r
|
|
K21 0.000 0.000 r clk (IN)
|
|
net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1
|
|
K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O
|
|
net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll
|
|
PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0)
|
|
-2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0
|
|
net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll
|
|
BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout1_buf/O
|
|
net (fo=6484, routed) 1.079 -0.229 u_Axi_CDC/wFifo/cpu_clk
|
|
SLICE_X3Y49 FDCE r u_Axi_CDC/wFifo/pushCC_pushPtr_reg[0]/C
|
|
clock pessimism -0.220 -0.449
|
|
SLICE_X3Y49 FDCE (Remov_fdce_C_CLR) -0.092 -0.541 u_Axi_CDC/wFifo/pushCC_pushPtr_reg[0]
|
|
-------------------------------------------------------------------
|
|
required time 0.541
|
|
arrival time 0.395
|
|
-------------------------------------------------------------------
|
|
slack 0.936
|
|
|
|
Slack (MET) : 0.936ns (arrival time - required time)
|
|
Source: pll_clk.u_rst_cpu/delay_reg[1]/C
|
|
(rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns})
|
|
Destination: u_Axi_CDC/wFifo/pushCC_pushPtr_reg[1]/CLR
|
|
(removal check against rising-edge clock cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns})
|
|
Path Group: **async_default**
|
|
Path Type: Removal (Min at Fast Process Corner)
|
|
Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns)
|
|
Data Path Delay: 0.860ns (logic 0.186ns (21.621%) route 0.674ns (78.379%))
|
|
Logic Levels: 1 (LUT1=1)
|
|
Clock Path Skew: 0.016ns (DCD - SCD - CPR)
|
|
Destination Clock Delay (DCD): -0.229ns
|
|
Source Clock Delay (SCD): -0.465ns
|
|
Clock Pessimism Removal (CPR): 0.220ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock cpu_clk rise edge) 0.000 0.000 r
|
|
K21 0.000 0.000 r clk (IN)
|
|
net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1
|
|
K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O
|
|
net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll
|
|
PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0)
|
|
-2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0
|
|
net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll
|
|
BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout1_buf/O
|
|
net (fo=6484, routed) 0.798 -0.465 pll_clk.u_rst_cpu/cpu_clk
|
|
SLICE_X0Y48 FDCE r pll_clk.u_rst_cpu/delay_reg[1]/C
|
|
------------------------------------------------------------------- -------------------
|
|
SLICE_X0Y48 FDCE (Prop_fdce_C_Q) 0.141 -0.324 r pll_clk.u_rst_cpu/delay_reg[1]/Q
|
|
net (fo=1, routed) 0.221 -0.103 pll_clk.u_rst_cpu/cpu_resetn
|
|
SLICE_X0Y48 LUT1 (Prop_lut1_I0_O) 0.045 -0.058 f pll_clk.u_rst_cpu/reset_i_1/O
|
|
net (fo=40, routed) 0.453 0.395 u_Axi_CDC/wFifo/p_0_in
|
|
SLICE_X3Y49 FDCE f u_Axi_CDC/wFifo/pushCC_pushPtr_reg[1]/CLR
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock cpu_clk rise edge) 0.000 0.000 r
|
|
K21 0.000 0.000 r clk (IN)
|
|
net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1
|
|
K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O
|
|
net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll
|
|
PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0)
|
|
-2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0
|
|
net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll
|
|
BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout1_buf/O
|
|
net (fo=6484, routed) 1.079 -0.229 u_Axi_CDC/wFifo/cpu_clk
|
|
SLICE_X3Y49 FDCE r u_Axi_CDC/wFifo/pushCC_pushPtr_reg[1]/C
|
|
clock pessimism -0.220 -0.449
|
|
SLICE_X3Y49 FDCE (Remov_fdce_C_CLR) -0.092 -0.541 u_Axi_CDC/wFifo/pushCC_pushPtr_reg[1]
|
|
-------------------------------------------------------------------
|
|
required time 0.541
|
|
arrival time 0.395
|
|
-------------------------------------------------------------------
|
|
slack 0.936
|
|
|
|
Slack (MET) : 0.936ns (arrival time - required time)
|
|
Source: pll_clk.u_rst_cpu/delay_reg[1]/C
|
|
(rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns})
|
|
Destination: u_Axi_CDC/wFifo/pushCC_pushPtr_reg[2]/CLR
|
|
(removal check against rising-edge clock cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns})
|
|
Path Group: **async_default**
|
|
Path Type: Removal (Min at Fast Process Corner)
|
|
Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns)
|
|
Data Path Delay: 0.860ns (logic 0.186ns (21.621%) route 0.674ns (78.379%))
|
|
Logic Levels: 1 (LUT1=1)
|
|
Clock Path Skew: 0.016ns (DCD - SCD - CPR)
|
|
Destination Clock Delay (DCD): -0.229ns
|
|
Source Clock Delay (SCD): -0.465ns
|
|
Clock Pessimism Removal (CPR): 0.220ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock cpu_clk rise edge) 0.000 0.000 r
|
|
K21 0.000 0.000 r clk (IN)
|
|
net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1
|
|
K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O
|
|
net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll
|
|
PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0)
|
|
-2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0
|
|
net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll
|
|
BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout1_buf/O
|
|
net (fo=6484, routed) 0.798 -0.465 pll_clk.u_rst_cpu/cpu_clk
|
|
SLICE_X0Y48 FDCE r pll_clk.u_rst_cpu/delay_reg[1]/C
|
|
------------------------------------------------------------------- -------------------
|
|
SLICE_X0Y48 FDCE (Prop_fdce_C_Q) 0.141 -0.324 r pll_clk.u_rst_cpu/delay_reg[1]/Q
|
|
net (fo=1, routed) 0.221 -0.103 pll_clk.u_rst_cpu/cpu_resetn
|
|
SLICE_X0Y48 LUT1 (Prop_lut1_I0_O) 0.045 -0.058 f pll_clk.u_rst_cpu/reset_i_1/O
|
|
net (fo=40, routed) 0.453 0.395 u_Axi_CDC/wFifo/p_0_in
|
|
SLICE_X3Y49 FDCE f u_Axi_CDC/wFifo/pushCC_pushPtr_reg[2]/CLR
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock cpu_clk rise edge) 0.000 0.000 r
|
|
K21 0.000 0.000 r clk (IN)
|
|
net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1
|
|
K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O
|
|
net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll
|
|
PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0)
|
|
-2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0
|
|
net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll
|
|
BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout1_buf/O
|
|
net (fo=6484, routed) 1.079 -0.229 u_Axi_CDC/wFifo/cpu_clk
|
|
SLICE_X3Y49 FDCE r u_Axi_CDC/wFifo/pushCC_pushPtr_reg[2]/C
|
|
clock pessimism -0.220 -0.449
|
|
SLICE_X3Y49 FDCE (Remov_fdce_C_CLR) -0.092 -0.541 u_Axi_CDC/wFifo/pushCC_pushPtr_reg[2]
|
|
-------------------------------------------------------------------
|
|
required time 0.541
|
|
arrival time 0.395
|
|
-------------------------------------------------------------------
|
|
slack 0.936
|
|
|
|
Slack (MET) : 1.005ns (arrival time - required time)
|
|
Source: u_Axi_CDC/bFifo/bufferCC_12/buffers_1_reg/C
|
|
(rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns})
|
|
Destination: u_Axi_CDC/bFifo/popCC_addressGen_rValid_reg/CLR
|
|
(removal check against rising-edge clock cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns})
|
|
Path Group: **async_default**
|
|
Path Type: Removal (Min at Fast Process Corner)
|
|
Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns)
|
|
Data Path Delay: 0.958ns (logic 0.227ns (23.685%) route 0.731ns (76.315%))
|
|
Logic Levels: 1 (LUT1=1)
|
|
Clock Path Skew: 0.045ns (DCD - SCD - CPR)
|
|
Destination Clock Delay (DCD): -0.338ns
|
|
Source Clock Delay (SCD): -0.575ns
|
|
Clock Pessimism Removal (CPR): 0.192ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock cpu_clk rise edge) 0.000 0.000 r
|
|
K21 0.000 0.000 r clk (IN)
|
|
net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1
|
|
K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O
|
|
net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll
|
|
PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0)
|
|
-2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0
|
|
net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll
|
|
BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout1_buf/O
|
|
net (fo=6484, routed) 0.687 -0.575 u_Axi_CDC/bFifo/bufferCC_12/cpu_clk
|
|
SLICE_X30Y58 FDCE r u_Axi_CDC/bFifo/bufferCC_12/buffers_1_reg/C
|
|
------------------------------------------------------------------- -------------------
|
|
SLICE_X30Y58 FDCE (Prop_fdce_C_Q) 0.128 -0.447 r u_Axi_CDC/bFifo/bufferCC_12/buffers_1_reg/Q
|
|
net (fo=1, routed) 0.207 -0.241 u_Axi_CDC/bFifo/bufferCC_12/buffers_1
|
|
SLICE_X28Y58 LUT1 (Prop_lut1_I0_O) 0.099 -0.142 f u_Axi_CDC/bFifo/bufferCC_12/popCC_popPtr[2]_i_2__0/O
|
|
net (fo=30, routed) 0.525 0.383 u_Axi_CDC/bFifo/buffers_1_reg
|
|
SLICE_X17Y58 FDCE f u_Axi_CDC/bFifo/popCC_addressGen_rValid_reg/CLR
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock cpu_clk rise edge) 0.000 0.000 r
|
|
K21 0.000 0.000 r clk (IN)
|
|
net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1
|
|
K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O
|
|
net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll
|
|
PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0)
|
|
-2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0
|
|
net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll
|
|
BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout1_buf/O
|
|
net (fo=6484, routed) 0.970 -0.338 u_Axi_CDC/bFifo/cpu_clk
|
|
SLICE_X17Y58 FDCE r u_Axi_CDC/bFifo/popCC_addressGen_rValid_reg/C
|
|
clock pessimism -0.192 -0.530
|
|
SLICE_X17Y58 FDCE (Remov_fdce_C_CLR) -0.092 -0.622 u_Axi_CDC/bFifo/popCC_addressGen_rValid_reg
|
|
-------------------------------------------------------------------
|
|
required time 0.622
|
|
arrival time 0.383
|
|
-------------------------------------------------------------------
|
|
slack 1.005
|
|
|
|
Slack (MET) : 1.005ns (arrival time - required time)
|
|
Source: u_Axi_CDC/bFifo/bufferCC_12/buffers_1_reg/C
|
|
(rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns})
|
|
Destination: u_Axi_CDC/bFifo/popCC_popPtr_reg[2]/CLR
|
|
(removal check against rising-edge clock cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns})
|
|
Path Group: **async_default**
|
|
Path Type: Removal (Min at Fast Process Corner)
|
|
Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns)
|
|
Data Path Delay: 0.958ns (logic 0.227ns (23.685%) route 0.731ns (76.315%))
|
|
Logic Levels: 1 (LUT1=1)
|
|
Clock Path Skew: 0.045ns (DCD - SCD - CPR)
|
|
Destination Clock Delay (DCD): -0.338ns
|
|
Source Clock Delay (SCD): -0.575ns
|
|
Clock Pessimism Removal (CPR): 0.192ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock cpu_clk rise edge) 0.000 0.000 r
|
|
K21 0.000 0.000 r clk (IN)
|
|
net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1
|
|
K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O
|
|
net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll
|
|
PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0)
|
|
-2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0
|
|
net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll
|
|
BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout1_buf/O
|
|
net (fo=6484, routed) 0.687 -0.575 u_Axi_CDC/bFifo/bufferCC_12/cpu_clk
|
|
SLICE_X30Y58 FDCE r u_Axi_CDC/bFifo/bufferCC_12/buffers_1_reg/C
|
|
------------------------------------------------------------------- -------------------
|
|
SLICE_X30Y58 FDCE (Prop_fdce_C_Q) 0.128 -0.447 r u_Axi_CDC/bFifo/bufferCC_12/buffers_1_reg/Q
|
|
net (fo=1, routed) 0.207 -0.241 u_Axi_CDC/bFifo/bufferCC_12/buffers_1
|
|
SLICE_X28Y58 LUT1 (Prop_lut1_I0_O) 0.099 -0.142 f u_Axi_CDC/bFifo/bufferCC_12/popCC_popPtr[2]_i_2__0/O
|
|
net (fo=30, routed) 0.525 0.383 u_Axi_CDC/bFifo/buffers_1_reg
|
|
SLICE_X17Y58 FDCE f u_Axi_CDC/bFifo/popCC_popPtr_reg[2]/CLR
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock cpu_clk rise edge) 0.000 0.000 r
|
|
K21 0.000 0.000 r clk (IN)
|
|
net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1
|
|
K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O
|
|
net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll
|
|
PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0)
|
|
-2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0
|
|
net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll
|
|
BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout1_buf/O
|
|
net (fo=6484, routed) 0.970 -0.338 u_Axi_CDC/bFifo/cpu_clk
|
|
SLICE_X17Y58 FDCE r u_Axi_CDC/bFifo/popCC_popPtr_reg[2]/C
|
|
clock pessimism -0.192 -0.530
|
|
SLICE_X17Y58 FDCE (Remov_fdce_C_CLR) -0.092 -0.622 u_Axi_CDC/bFifo/popCC_popPtr_reg[2]
|
|
-------------------------------------------------------------------
|
|
required time 0.622
|
|
arrival time 0.383
|
|
-------------------------------------------------------------------
|
|
slack 1.005
|
|
|
|
Slack (MET) : 1.005ns (arrival time - required time)
|
|
Source: u_Axi_CDC/bFifo/bufferCC_12/buffers_1_reg/C
|
|
(rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns})
|
|
Destination: u_Axi_CDC/bFifo/popCC_ptrToPush_reg[1]/CLR
|
|
(removal check against rising-edge clock cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns})
|
|
Path Group: **async_default**
|
|
Path Type: Removal (Min at Fast Process Corner)
|
|
Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns)
|
|
Data Path Delay: 0.958ns (logic 0.227ns (23.685%) route 0.731ns (76.315%))
|
|
Logic Levels: 1 (LUT1=1)
|
|
Clock Path Skew: 0.045ns (DCD - SCD - CPR)
|
|
Destination Clock Delay (DCD): -0.338ns
|
|
Source Clock Delay (SCD): -0.575ns
|
|
Clock Pessimism Removal (CPR): 0.192ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock cpu_clk rise edge) 0.000 0.000 r
|
|
K21 0.000 0.000 r clk (IN)
|
|
net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1
|
|
K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O
|
|
net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll
|
|
PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0)
|
|
-2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0
|
|
net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll
|
|
BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout1_buf/O
|
|
net (fo=6484, routed) 0.687 -0.575 u_Axi_CDC/bFifo/bufferCC_12/cpu_clk
|
|
SLICE_X30Y58 FDCE r u_Axi_CDC/bFifo/bufferCC_12/buffers_1_reg/C
|
|
------------------------------------------------------------------- -------------------
|
|
SLICE_X30Y58 FDCE (Prop_fdce_C_Q) 0.128 -0.447 r u_Axi_CDC/bFifo/bufferCC_12/buffers_1_reg/Q
|
|
net (fo=1, routed) 0.207 -0.241 u_Axi_CDC/bFifo/bufferCC_12/buffers_1
|
|
SLICE_X28Y58 LUT1 (Prop_lut1_I0_O) 0.099 -0.142 f u_Axi_CDC/bFifo/bufferCC_12/popCC_popPtr[2]_i_2__0/O
|
|
net (fo=30, routed) 0.525 0.383 u_Axi_CDC/bFifo/buffers_1_reg
|
|
SLICE_X17Y58 FDCE f u_Axi_CDC/bFifo/popCC_ptrToPush_reg[1]/CLR
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock cpu_clk rise edge) 0.000 0.000 r
|
|
K21 0.000 0.000 r clk (IN)
|
|
net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1
|
|
K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O
|
|
net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll
|
|
PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0)
|
|
-2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0
|
|
net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll
|
|
BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout1_buf/O
|
|
net (fo=6484, routed) 0.970 -0.338 u_Axi_CDC/bFifo/cpu_clk
|
|
SLICE_X17Y58 FDCE r u_Axi_CDC/bFifo/popCC_ptrToPush_reg[1]/C
|
|
clock pessimism -0.192 -0.530
|
|
SLICE_X17Y58 FDCE (Remov_fdce_C_CLR) -0.092 -0.622 u_Axi_CDC/bFifo/popCC_ptrToPush_reg[1]
|
|
-------------------------------------------------------------------
|
|
required time 0.622
|
|
arrival time 0.383
|
|
-------------------------------------------------------------------
|
|
slack 1.005
|
|
|
|
Slack (MET) : 1.005ns (arrival time - required time)
|
|
Source: u_Axi_CDC/bFifo/bufferCC_12/buffers_1_reg/C
|
|
(rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns})
|
|
Destination: u_Axi_CDC/bFifo/popCC_ptrToPush_reg[2]/CLR
|
|
(removal check against rising-edge clock cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns})
|
|
Path Group: **async_default**
|
|
Path Type: Removal (Min at Fast Process Corner)
|
|
Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns)
|
|
Data Path Delay: 0.958ns (logic 0.227ns (23.685%) route 0.731ns (76.315%))
|
|
Logic Levels: 1 (LUT1=1)
|
|
Clock Path Skew: 0.045ns (DCD - SCD - CPR)
|
|
Destination Clock Delay (DCD): -0.338ns
|
|
Source Clock Delay (SCD): -0.575ns
|
|
Clock Pessimism Removal (CPR): 0.192ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock cpu_clk rise edge) 0.000 0.000 r
|
|
K21 0.000 0.000 r clk (IN)
|
|
net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1
|
|
K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O
|
|
net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll
|
|
PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0)
|
|
-2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0
|
|
net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll
|
|
BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout1_buf/O
|
|
net (fo=6484, routed) 0.687 -0.575 u_Axi_CDC/bFifo/bufferCC_12/cpu_clk
|
|
SLICE_X30Y58 FDCE r u_Axi_CDC/bFifo/bufferCC_12/buffers_1_reg/C
|
|
------------------------------------------------------------------- -------------------
|
|
SLICE_X30Y58 FDCE (Prop_fdce_C_Q) 0.128 -0.447 r u_Axi_CDC/bFifo/bufferCC_12/buffers_1_reg/Q
|
|
net (fo=1, routed) 0.207 -0.241 u_Axi_CDC/bFifo/bufferCC_12/buffers_1
|
|
SLICE_X28Y58 LUT1 (Prop_lut1_I0_O) 0.099 -0.142 f u_Axi_CDC/bFifo/bufferCC_12/popCC_popPtr[2]_i_2__0/O
|
|
net (fo=30, routed) 0.525 0.383 u_Axi_CDC/bFifo/buffers_1_reg
|
|
SLICE_X17Y58 FDCE f u_Axi_CDC/bFifo/popCC_ptrToPush_reg[2]/CLR
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock cpu_clk rise edge) 0.000 0.000 r
|
|
K21 0.000 0.000 r clk (IN)
|
|
net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1
|
|
K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O
|
|
net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll
|
|
PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0)
|
|
-2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0
|
|
net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll
|
|
BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout1_buf/O
|
|
net (fo=6484, routed) 0.970 -0.338 u_Axi_CDC/bFifo/cpu_clk
|
|
SLICE_X17Y58 FDCE r u_Axi_CDC/bFifo/popCC_ptrToPush_reg[2]/C
|
|
clock pessimism -0.192 -0.530
|
|
SLICE_X17Y58 FDCE (Remov_fdce_C_CLR) -0.092 -0.622 u_Axi_CDC/bFifo/popCC_ptrToPush_reg[2]
|
|
-------------------------------------------------------------------
|
|
required time 0.622
|
|
arrival time 0.383
|
|
-------------------------------------------------------------------
|
|
slack 1.005
|
|
|
|
Slack (MET) : 1.012ns (arrival time - required time)
|
|
Source: u_Axi_CDC/bFifo/bufferCC_12/buffers_1_reg/C
|
|
(rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns})
|
|
Destination: u_Axi_CDC/bFifo/pushToPopGray_buffercc/buffers_0_reg[0]/CLR
|
|
(removal check against rising-edge clock cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns})
|
|
Path Group: **async_default**
|
|
Path Type: Removal (Min at Fast Process Corner)
|
|
Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns)
|
|
Data Path Delay: 0.965ns (logic 0.227ns (23.531%) route 0.738ns (76.469%))
|
|
Logic Levels: 1 (LUT1=1)
|
|
Clock Path Skew: 0.045ns (DCD - SCD - CPR)
|
|
Destination Clock Delay (DCD): -0.338ns
|
|
Source Clock Delay (SCD): -0.575ns
|
|
Clock Pessimism Removal (CPR): 0.192ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock cpu_clk rise edge) 0.000 0.000 r
|
|
K21 0.000 0.000 r clk (IN)
|
|
net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1
|
|
K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O
|
|
net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll
|
|
PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0)
|
|
-2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0
|
|
net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll
|
|
BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout1_buf/O
|
|
net (fo=6484, routed) 0.687 -0.575 u_Axi_CDC/bFifo/bufferCC_12/cpu_clk
|
|
SLICE_X30Y58 FDCE r u_Axi_CDC/bFifo/bufferCC_12/buffers_1_reg/C
|
|
------------------------------------------------------------------- -------------------
|
|
SLICE_X30Y58 FDCE (Prop_fdce_C_Q) 0.128 -0.447 r u_Axi_CDC/bFifo/bufferCC_12/buffers_1_reg/Q
|
|
net (fo=1, routed) 0.207 -0.241 u_Axi_CDC/bFifo/bufferCC_12/buffers_1
|
|
SLICE_X28Y58 LUT1 (Prop_lut1_I0_O) 0.099 -0.142 f u_Axi_CDC/bFifo/bufferCC_12/popCC_popPtr[2]_i_2__0/O
|
|
net (fo=30, routed) 0.531 0.389 u_Axi_CDC/bFifo/pushToPopGray_buffercc/buffers_0_reg[2]_1
|
|
SLICE_X19Y59 FDCE f u_Axi_CDC/bFifo/pushToPopGray_buffercc/buffers_0_reg[0]/CLR
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock cpu_clk rise edge) 0.000 0.000 r
|
|
K21 0.000 0.000 r clk (IN)
|
|
net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1
|
|
K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O
|
|
net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll
|
|
PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0)
|
|
-2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0
|
|
net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll
|
|
BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout1_buf/O
|
|
net (fo=6484, routed) 0.970 -0.338 u_Axi_CDC/bFifo/pushToPopGray_buffercc/cpu_clk
|
|
SLICE_X19Y59 FDCE r u_Axi_CDC/bFifo/pushToPopGray_buffercc/buffers_0_reg[0]/C
|
|
clock pessimism -0.192 -0.530
|
|
SLICE_X19Y59 FDCE (Remov_fdce_C_CLR) -0.092 -0.622 u_Axi_CDC/bFifo/pushToPopGray_buffercc/buffers_0_reg[0]
|
|
-------------------------------------------------------------------
|
|
required time 0.622
|
|
arrival time 0.389
|
|
-------------------------------------------------------------------
|
|
slack 1.012
|
|
|
|
Slack (MET) : 1.012ns (arrival time - required time)
|
|
Source: u_Axi_CDC/bFifo/bufferCC_12/buffers_1_reg/C
|
|
(rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns})
|
|
Destination: u_Axi_CDC/bFifo/pushToPopGray_buffercc/buffers_0_reg[1]/CLR
|
|
(removal check against rising-edge clock cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns})
|
|
Path Group: **async_default**
|
|
Path Type: Removal (Min at Fast Process Corner)
|
|
Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns)
|
|
Data Path Delay: 0.965ns (logic 0.227ns (23.531%) route 0.738ns (76.469%))
|
|
Logic Levels: 1 (LUT1=1)
|
|
Clock Path Skew: 0.045ns (DCD - SCD - CPR)
|
|
Destination Clock Delay (DCD): -0.338ns
|
|
Source Clock Delay (SCD): -0.575ns
|
|
Clock Pessimism Removal (CPR): 0.192ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock cpu_clk rise edge) 0.000 0.000 r
|
|
K21 0.000 0.000 r clk (IN)
|
|
net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1
|
|
K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O
|
|
net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll
|
|
PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0)
|
|
-2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0
|
|
net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll
|
|
BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout1_buf/O
|
|
net (fo=6484, routed) 0.687 -0.575 u_Axi_CDC/bFifo/bufferCC_12/cpu_clk
|
|
SLICE_X30Y58 FDCE r u_Axi_CDC/bFifo/bufferCC_12/buffers_1_reg/C
|
|
------------------------------------------------------------------- -------------------
|
|
SLICE_X30Y58 FDCE (Prop_fdce_C_Q) 0.128 -0.447 r u_Axi_CDC/bFifo/bufferCC_12/buffers_1_reg/Q
|
|
net (fo=1, routed) 0.207 -0.241 u_Axi_CDC/bFifo/bufferCC_12/buffers_1
|
|
SLICE_X28Y58 LUT1 (Prop_lut1_I0_O) 0.099 -0.142 f u_Axi_CDC/bFifo/bufferCC_12/popCC_popPtr[2]_i_2__0/O
|
|
net (fo=30, routed) 0.531 0.389 u_Axi_CDC/bFifo/pushToPopGray_buffercc/buffers_0_reg[2]_1
|
|
SLICE_X19Y59 FDCE f u_Axi_CDC/bFifo/pushToPopGray_buffercc/buffers_0_reg[1]/CLR
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock cpu_clk rise edge) 0.000 0.000 r
|
|
K21 0.000 0.000 r clk (IN)
|
|
net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1
|
|
K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O
|
|
net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll
|
|
PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0)
|
|
-2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0
|
|
net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll
|
|
BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout1_buf/O
|
|
net (fo=6484, routed) 0.970 -0.338 u_Axi_CDC/bFifo/pushToPopGray_buffercc/cpu_clk
|
|
SLICE_X19Y59 FDCE r u_Axi_CDC/bFifo/pushToPopGray_buffercc/buffers_0_reg[1]/C
|
|
clock pessimism -0.192 -0.530
|
|
SLICE_X19Y59 FDCE (Remov_fdce_C_CLR) -0.092 -0.622 u_Axi_CDC/bFifo/pushToPopGray_buffercc/buffers_0_reg[1]
|
|
-------------------------------------------------------------------
|
|
required time 0.622
|
|
arrival time 0.389
|
|
-------------------------------------------------------------------
|
|
slack 1.012
|
|
|
|
Slack (MET) : 1.012ns (arrival time - required time)
|
|
Source: u_Axi_CDC/bFifo/bufferCC_12/buffers_1_reg/C
|
|
(rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns})
|
|
Destination: u_Axi_CDC/bFifo/pushToPopGray_buffercc/buffers_0_reg[2]/CLR
|
|
(removal check against rising-edge clock cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns})
|
|
Path Group: **async_default**
|
|
Path Type: Removal (Min at Fast Process Corner)
|
|
Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns)
|
|
Data Path Delay: 0.965ns (logic 0.227ns (23.531%) route 0.738ns (76.469%))
|
|
Logic Levels: 1 (LUT1=1)
|
|
Clock Path Skew: 0.045ns (DCD - SCD - CPR)
|
|
Destination Clock Delay (DCD): -0.338ns
|
|
Source Clock Delay (SCD): -0.575ns
|
|
Clock Pessimism Removal (CPR): 0.192ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock cpu_clk rise edge) 0.000 0.000 r
|
|
K21 0.000 0.000 r clk (IN)
|
|
net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1
|
|
K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O
|
|
net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll
|
|
PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0)
|
|
-2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0
|
|
net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll
|
|
BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout1_buf/O
|
|
net (fo=6484, routed) 0.687 -0.575 u_Axi_CDC/bFifo/bufferCC_12/cpu_clk
|
|
SLICE_X30Y58 FDCE r u_Axi_CDC/bFifo/bufferCC_12/buffers_1_reg/C
|
|
------------------------------------------------------------------- -------------------
|
|
SLICE_X30Y58 FDCE (Prop_fdce_C_Q) 0.128 -0.447 r u_Axi_CDC/bFifo/bufferCC_12/buffers_1_reg/Q
|
|
net (fo=1, routed) 0.207 -0.241 u_Axi_CDC/bFifo/bufferCC_12/buffers_1
|
|
SLICE_X28Y58 LUT1 (Prop_lut1_I0_O) 0.099 -0.142 f u_Axi_CDC/bFifo/bufferCC_12/popCC_popPtr[2]_i_2__0/O
|
|
net (fo=30, routed) 0.531 0.389 u_Axi_CDC/bFifo/pushToPopGray_buffercc/buffers_0_reg[2]_1
|
|
SLICE_X19Y59 FDCE f u_Axi_CDC/bFifo/pushToPopGray_buffercc/buffers_0_reg[2]/CLR
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock cpu_clk rise edge) 0.000 0.000 r
|
|
K21 0.000 0.000 r clk (IN)
|
|
net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1
|
|
K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O
|
|
net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll
|
|
PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0)
|
|
-2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0
|
|
net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll
|
|
BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout1_buf/O
|
|
net (fo=6484, routed) 0.970 -0.338 u_Axi_CDC/bFifo/pushToPopGray_buffercc/cpu_clk
|
|
SLICE_X19Y59 FDCE r u_Axi_CDC/bFifo/pushToPopGray_buffercc/buffers_0_reg[2]/C
|
|
clock pessimism -0.192 -0.530
|
|
SLICE_X19Y59 FDCE (Remov_fdce_C_CLR) -0.092 -0.622 u_Axi_CDC/bFifo/pushToPopGray_buffercc/buffers_0_reg[2]
|
|
-------------------------------------------------------------------
|
|
required time 0.622
|
|
arrival time 0.389
|
|
-------------------------------------------------------------------
|
|
slack 1.012
|
|
|
|
Slack (MET) : 1.012ns (arrival time - required time)
|
|
Source: u_Axi_CDC/bFifo/bufferCC_12/buffers_1_reg/C
|
|
(rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns})
|
|
Destination: u_Axi_CDC/bFifo/pushToPopGray_buffercc/buffers_1_reg[0]/CLR
|
|
(removal check against rising-edge clock cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns})
|
|
Path Group: **async_default**
|
|
Path Type: Removal (Min at Fast Process Corner)
|
|
Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns)
|
|
Data Path Delay: 0.965ns (logic 0.227ns (23.531%) route 0.738ns (76.469%))
|
|
Logic Levels: 1 (LUT1=1)
|
|
Clock Path Skew: 0.045ns (DCD - SCD - CPR)
|
|
Destination Clock Delay (DCD): -0.338ns
|
|
Source Clock Delay (SCD): -0.575ns
|
|
Clock Pessimism Removal (CPR): 0.192ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock cpu_clk rise edge) 0.000 0.000 r
|
|
K21 0.000 0.000 r clk (IN)
|
|
net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1
|
|
K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O
|
|
net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll
|
|
PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0)
|
|
-2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0
|
|
net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll
|
|
BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout1_buf/O
|
|
net (fo=6484, routed) 0.687 -0.575 u_Axi_CDC/bFifo/bufferCC_12/cpu_clk
|
|
SLICE_X30Y58 FDCE r u_Axi_CDC/bFifo/bufferCC_12/buffers_1_reg/C
|
|
------------------------------------------------------------------- -------------------
|
|
SLICE_X30Y58 FDCE (Prop_fdce_C_Q) 0.128 -0.447 r u_Axi_CDC/bFifo/bufferCC_12/buffers_1_reg/Q
|
|
net (fo=1, routed) 0.207 -0.241 u_Axi_CDC/bFifo/bufferCC_12/buffers_1
|
|
SLICE_X28Y58 LUT1 (Prop_lut1_I0_O) 0.099 -0.142 f u_Axi_CDC/bFifo/bufferCC_12/popCC_popPtr[2]_i_2__0/O
|
|
net (fo=30, routed) 0.531 0.389 u_Axi_CDC/bFifo/pushToPopGray_buffercc/buffers_0_reg[2]_1
|
|
SLICE_X19Y59 FDCE f u_Axi_CDC/bFifo/pushToPopGray_buffercc/buffers_1_reg[0]/CLR
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock cpu_clk rise edge) 0.000 0.000 r
|
|
K21 0.000 0.000 r clk (IN)
|
|
net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1
|
|
K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O
|
|
net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll
|
|
PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0)
|
|
-2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0
|
|
net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll
|
|
BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout1_buf/O
|
|
net (fo=6484, routed) 0.970 -0.338 u_Axi_CDC/bFifo/pushToPopGray_buffercc/cpu_clk
|
|
SLICE_X19Y59 FDCE r u_Axi_CDC/bFifo/pushToPopGray_buffercc/buffers_1_reg[0]/C
|
|
clock pessimism -0.192 -0.530
|
|
SLICE_X19Y59 FDCE (Remov_fdce_C_CLR) -0.092 -0.622 u_Axi_CDC/bFifo/pushToPopGray_buffercc/buffers_1_reg[0]
|
|
-------------------------------------------------------------------
|
|
required time 0.622
|
|
arrival time 0.389
|
|
-------------------------------------------------------------------
|
|
slack 1.012
|
|
|
|
Slack (MET) : 1.012ns (arrival time - required time)
|
|
Source: u_Axi_CDC/bFifo/bufferCC_12/buffers_1_reg/C
|
|
(rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns})
|
|
Destination: u_Axi_CDC/bFifo/pushToPopGray_buffercc/buffers_1_reg[1]/CLR
|
|
(removal check against rising-edge clock cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns})
|
|
Path Group: **async_default**
|
|
Path Type: Removal (Min at Fast Process Corner)
|
|
Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns)
|
|
Data Path Delay: 0.965ns (logic 0.227ns (23.531%) route 0.738ns (76.469%))
|
|
Logic Levels: 1 (LUT1=1)
|
|
Clock Path Skew: 0.045ns (DCD - SCD - CPR)
|
|
Destination Clock Delay (DCD): -0.338ns
|
|
Source Clock Delay (SCD): -0.575ns
|
|
Clock Pessimism Removal (CPR): 0.192ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock cpu_clk rise edge) 0.000 0.000 r
|
|
K21 0.000 0.000 r clk (IN)
|
|
net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1
|
|
K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O
|
|
net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll
|
|
PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0)
|
|
-2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0
|
|
net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll
|
|
BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout1_buf/O
|
|
net (fo=6484, routed) 0.687 -0.575 u_Axi_CDC/bFifo/bufferCC_12/cpu_clk
|
|
SLICE_X30Y58 FDCE r u_Axi_CDC/bFifo/bufferCC_12/buffers_1_reg/C
|
|
------------------------------------------------------------------- -------------------
|
|
SLICE_X30Y58 FDCE (Prop_fdce_C_Q) 0.128 -0.447 r u_Axi_CDC/bFifo/bufferCC_12/buffers_1_reg/Q
|
|
net (fo=1, routed) 0.207 -0.241 u_Axi_CDC/bFifo/bufferCC_12/buffers_1
|
|
SLICE_X28Y58 LUT1 (Prop_lut1_I0_O) 0.099 -0.142 f u_Axi_CDC/bFifo/bufferCC_12/popCC_popPtr[2]_i_2__0/O
|
|
net (fo=30, routed) 0.531 0.389 u_Axi_CDC/bFifo/pushToPopGray_buffercc/buffers_0_reg[2]_1
|
|
SLICE_X19Y59 FDCE f u_Axi_CDC/bFifo/pushToPopGray_buffercc/buffers_1_reg[1]/CLR
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock cpu_clk rise edge) 0.000 0.000 r
|
|
K21 0.000 0.000 r clk (IN)
|
|
net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1
|
|
K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O
|
|
net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll
|
|
PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0)
|
|
-2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0
|
|
net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll
|
|
BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout1_buf/O
|
|
net (fo=6484, routed) 0.970 -0.338 u_Axi_CDC/bFifo/pushToPopGray_buffercc/cpu_clk
|
|
SLICE_X19Y59 FDCE r u_Axi_CDC/bFifo/pushToPopGray_buffercc/buffers_1_reg[1]/C
|
|
clock pessimism -0.192 -0.530
|
|
SLICE_X19Y59 FDCE (Remov_fdce_C_CLR) -0.092 -0.622 u_Axi_CDC/bFifo/pushToPopGray_buffercc/buffers_1_reg[1]
|
|
-------------------------------------------------------------------
|
|
required time 0.622
|
|
arrival time 0.389
|
|
-------------------------------------------------------------------
|
|
slack 1.012
|
|
|
|
Slack (MET) : 1.012ns (arrival time - required time)
|
|
Source: u_Axi_CDC/bFifo/bufferCC_12/buffers_1_reg/C
|
|
(rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns})
|
|
Destination: u_Axi_CDC/bFifo/pushToPopGray_buffercc/buffers_1_reg[2]/CLR
|
|
(removal check against rising-edge clock cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns})
|
|
Path Group: **async_default**
|
|
Path Type: Removal (Min at Fast Process Corner)
|
|
Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns)
|
|
Data Path Delay: 0.965ns (logic 0.227ns (23.531%) route 0.738ns (76.469%))
|
|
Logic Levels: 1 (LUT1=1)
|
|
Clock Path Skew: 0.045ns (DCD - SCD - CPR)
|
|
Destination Clock Delay (DCD): -0.338ns
|
|
Source Clock Delay (SCD): -0.575ns
|
|
Clock Pessimism Removal (CPR): 0.192ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock cpu_clk rise edge) 0.000 0.000 r
|
|
K21 0.000 0.000 r clk (IN)
|
|
net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1
|
|
K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O
|
|
net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll
|
|
PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0)
|
|
-2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0
|
|
net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll
|
|
BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout1_buf/O
|
|
net (fo=6484, routed) 0.687 -0.575 u_Axi_CDC/bFifo/bufferCC_12/cpu_clk
|
|
SLICE_X30Y58 FDCE r u_Axi_CDC/bFifo/bufferCC_12/buffers_1_reg/C
|
|
------------------------------------------------------------------- -------------------
|
|
SLICE_X30Y58 FDCE (Prop_fdce_C_Q) 0.128 -0.447 r u_Axi_CDC/bFifo/bufferCC_12/buffers_1_reg/Q
|
|
net (fo=1, routed) 0.207 -0.241 u_Axi_CDC/bFifo/bufferCC_12/buffers_1
|
|
SLICE_X28Y58 LUT1 (Prop_lut1_I0_O) 0.099 -0.142 f u_Axi_CDC/bFifo/bufferCC_12/popCC_popPtr[2]_i_2__0/O
|
|
net (fo=30, routed) 0.531 0.389 u_Axi_CDC/bFifo/pushToPopGray_buffercc/buffers_0_reg[2]_1
|
|
SLICE_X19Y59 FDCE f u_Axi_CDC/bFifo/pushToPopGray_buffercc/buffers_1_reg[2]/CLR
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock cpu_clk rise edge) 0.000 0.000 r
|
|
K21 0.000 0.000 r clk (IN)
|
|
net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1
|
|
K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O
|
|
net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll
|
|
PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0)
|
|
-2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0
|
|
net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll
|
|
BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout1_buf/O
|
|
net (fo=6484, routed) 0.970 -0.338 u_Axi_CDC/bFifo/pushToPopGray_buffercc/cpu_clk
|
|
SLICE_X19Y59 FDCE r u_Axi_CDC/bFifo/pushToPopGray_buffercc/buffers_1_reg[2]/C
|
|
clock pessimism -0.192 -0.530
|
|
SLICE_X19Y59 FDCE (Remov_fdce_C_CLR) -0.092 -0.622 u_Axi_CDC/bFifo/pushToPopGray_buffercc/buffers_1_reg[2]
|
|
-------------------------------------------------------------------
|
|
required time 0.622
|
|
arrival time 0.389
|
|
-------------------------------------------------------------------
|
|
slack 1.012
|
|
|
|
Slack (MET) : 1.012ns (arrival time - required time)
|
|
Source: u_Axi_CDC/bFifo/bufferCC_12/buffers_1_reg/C
|
|
(rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns})
|
|
Destination: u_Axi_CDC/rFifo/popCC_addressGen_rValid_reg/CLR
|
|
(removal check against rising-edge clock cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns})
|
|
Path Group: **async_default**
|
|
Path Type: Removal (Min at Fast Process Corner)
|
|
Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns)
|
|
Data Path Delay: 0.965ns (logic 0.227ns (23.531%) route 0.738ns (76.469%))
|
|
Logic Levels: 1 (LUT1=1)
|
|
Clock Path Skew: 0.045ns (DCD - SCD - CPR)
|
|
Destination Clock Delay (DCD): -0.338ns
|
|
Source Clock Delay (SCD): -0.575ns
|
|
Clock Pessimism Removal (CPR): 0.192ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock cpu_clk rise edge) 0.000 0.000 r
|
|
K21 0.000 0.000 r clk (IN)
|
|
net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1
|
|
K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O
|
|
net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll
|
|
PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0)
|
|
-2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0
|
|
net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll
|
|
BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout1_buf/O
|
|
net (fo=6484, routed) 0.687 -0.575 u_Axi_CDC/bFifo/bufferCC_12/cpu_clk
|
|
SLICE_X30Y58 FDCE r u_Axi_CDC/bFifo/bufferCC_12/buffers_1_reg/C
|
|
------------------------------------------------------------------- -------------------
|
|
SLICE_X30Y58 FDCE (Prop_fdce_C_Q) 0.128 -0.447 r u_Axi_CDC/bFifo/bufferCC_12/buffers_1_reg/Q
|
|
net (fo=1, routed) 0.207 -0.241 u_Axi_CDC/bFifo/bufferCC_12/buffers_1
|
|
SLICE_X28Y58 LUT1 (Prop_lut1_I0_O) 0.099 -0.142 f u_Axi_CDC/bFifo/bufferCC_12/popCC_popPtr[2]_i_2__0/O
|
|
net (fo=30, routed) 0.531 0.389 u_Axi_CDC/rFifo/buffers_0_reg[3]
|
|
SLICE_X19Y59 FDCE f u_Axi_CDC/rFifo/popCC_addressGen_rValid_reg/CLR
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock cpu_clk rise edge) 0.000 0.000 r
|
|
K21 0.000 0.000 r clk (IN)
|
|
net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1
|
|
K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O
|
|
net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll
|
|
PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0)
|
|
-2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0
|
|
net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll
|
|
BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout1_buf/O
|
|
net (fo=6484, routed) 0.970 -0.338 u_Axi_CDC/rFifo/cpu_clk
|
|
SLICE_X19Y59 FDCE r u_Axi_CDC/rFifo/popCC_addressGen_rValid_reg/C
|
|
clock pessimism -0.192 -0.530
|
|
SLICE_X19Y59 FDCE (Remov_fdce_C_CLR) -0.092 -0.622 u_Axi_CDC/rFifo/popCC_addressGen_rValid_reg
|
|
-------------------------------------------------------------------
|
|
required time 0.622
|
|
arrival time 0.389
|
|
-------------------------------------------------------------------
|
|
slack 1.012
|
|
|
|
Slack (MET) : 1.290ns (arrival time - required time)
|
|
Source: pll_clk.u_rst_cpu/delay_reg[1]/C
|
|
(rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns})
|
|
Destination: u_Axi_CDC/arFifo/popToPushGray_buffercc/buffers_0_reg[0]/CLR
|
|
(removal check against rising-edge clock cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns})
|
|
Path Group: **async_default**
|
|
Path Type: Removal (Min at Fast Process Corner)
|
|
Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns)
|
|
Data Path Delay: 1.378ns (logic 0.186ns (13.499%) route 1.192ns (86.501%))
|
|
Logic Levels: 1 (LUT1=1)
|
|
Clock Path Skew: 0.155ns (DCD - SCD - CPR)
|
|
Destination Clock Delay (DCD): -0.346ns
|
|
Source Clock Delay (SCD): -0.465ns
|
|
Clock Pessimism Removal (CPR): -0.037ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock cpu_clk rise edge) 0.000 0.000 r
|
|
K21 0.000 0.000 r clk (IN)
|
|
net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1
|
|
K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O
|
|
net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll
|
|
PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0)
|
|
-2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0
|
|
net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll
|
|
BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout1_buf/O
|
|
net (fo=6484, routed) 0.798 -0.465 pll_clk.u_rst_cpu/cpu_clk
|
|
SLICE_X0Y48 FDCE r pll_clk.u_rst_cpu/delay_reg[1]/C
|
|
------------------------------------------------------------------- -------------------
|
|
SLICE_X0Y48 FDCE (Prop_fdce_C_Q) 0.141 -0.324 r pll_clk.u_rst_cpu/delay_reg[1]/Q
|
|
net (fo=1, routed) 0.221 -0.103 pll_clk.u_rst_cpu/cpu_resetn
|
|
SLICE_X0Y48 LUT1 (Prop_lut1_I0_O) 0.045 -0.058 f pll_clk.u_rst_cpu/reset_i_1/O
|
|
net (fo=40, routed) 0.971 0.913 u_Axi_CDC/arFifo/popToPushGray_buffercc/p_0_in
|
|
SLICE_X14Y68 FDCE f u_Axi_CDC/arFifo/popToPushGray_buffercc/buffers_0_reg[0]/CLR
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock cpu_clk rise edge) 0.000 0.000 r
|
|
K21 0.000 0.000 r clk (IN)
|
|
net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1
|
|
K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O
|
|
net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll
|
|
PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0)
|
|
-2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0
|
|
net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll
|
|
BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout1_buf/O
|
|
net (fo=6484, routed) 0.962 -0.346 u_Axi_CDC/arFifo/popToPushGray_buffercc/cpu_clk
|
|
SLICE_X14Y68 FDCE r u_Axi_CDC/arFifo/popToPushGray_buffercc/buffers_0_reg[0]/C
|
|
clock pessimism 0.037 -0.309
|
|
SLICE_X14Y68 FDCE (Remov_fdce_C_CLR) -0.067 -0.376 u_Axi_CDC/arFifo/popToPushGray_buffercc/buffers_0_reg[0]
|
|
-------------------------------------------------------------------
|
|
required time 0.376
|
|
arrival time 0.913
|
|
-------------------------------------------------------------------
|
|
slack 1.290
|
|
|
|
Slack (MET) : 1.290ns (arrival time - required time)
|
|
Source: pll_clk.u_rst_cpu/delay_reg[1]/C
|
|
(rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns})
|
|
Destination: u_Axi_CDC/arFifo/popToPushGray_buffercc/buffers_0_reg[1]/CLR
|
|
(removal check against rising-edge clock cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns})
|
|
Path Group: **async_default**
|
|
Path Type: Removal (Min at Fast Process Corner)
|
|
Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns)
|
|
Data Path Delay: 1.378ns (logic 0.186ns (13.499%) route 1.192ns (86.501%))
|
|
Logic Levels: 1 (LUT1=1)
|
|
Clock Path Skew: 0.155ns (DCD - SCD - CPR)
|
|
Destination Clock Delay (DCD): -0.346ns
|
|
Source Clock Delay (SCD): -0.465ns
|
|
Clock Pessimism Removal (CPR): -0.037ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock cpu_clk rise edge) 0.000 0.000 r
|
|
K21 0.000 0.000 r clk (IN)
|
|
net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1
|
|
K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O
|
|
net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll
|
|
PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0)
|
|
-2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0
|
|
net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll
|
|
BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout1_buf/O
|
|
net (fo=6484, routed) 0.798 -0.465 pll_clk.u_rst_cpu/cpu_clk
|
|
SLICE_X0Y48 FDCE r pll_clk.u_rst_cpu/delay_reg[1]/C
|
|
------------------------------------------------------------------- -------------------
|
|
SLICE_X0Y48 FDCE (Prop_fdce_C_Q) 0.141 -0.324 r pll_clk.u_rst_cpu/delay_reg[1]/Q
|
|
net (fo=1, routed) 0.221 -0.103 pll_clk.u_rst_cpu/cpu_resetn
|
|
SLICE_X0Y48 LUT1 (Prop_lut1_I0_O) 0.045 -0.058 f pll_clk.u_rst_cpu/reset_i_1/O
|
|
net (fo=40, routed) 0.971 0.913 u_Axi_CDC/arFifo/popToPushGray_buffercc/p_0_in
|
|
SLICE_X14Y68 FDCE f u_Axi_CDC/arFifo/popToPushGray_buffercc/buffers_0_reg[1]/CLR
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock cpu_clk rise edge) 0.000 0.000 r
|
|
K21 0.000 0.000 r clk (IN)
|
|
net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1
|
|
K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O
|
|
net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll
|
|
PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0)
|
|
-2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0
|
|
net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll
|
|
BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout1_buf/O
|
|
net (fo=6484, routed) 0.962 -0.346 u_Axi_CDC/arFifo/popToPushGray_buffercc/cpu_clk
|
|
SLICE_X14Y68 FDCE r u_Axi_CDC/arFifo/popToPushGray_buffercc/buffers_0_reg[1]/C
|
|
clock pessimism 0.037 -0.309
|
|
SLICE_X14Y68 FDCE (Remov_fdce_C_CLR) -0.067 -0.376 u_Axi_CDC/arFifo/popToPushGray_buffercc/buffers_0_reg[1]
|
|
-------------------------------------------------------------------
|
|
required time 0.376
|
|
arrival time 0.913
|
|
-------------------------------------------------------------------
|
|
slack 1.290
|
|
|
|
Slack (MET) : 1.290ns (arrival time - required time)
|
|
Source: pll_clk.u_rst_cpu/delay_reg[1]/C
|
|
(rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns})
|
|
Destination: u_Axi_CDC/arFifo/popToPushGray_buffercc/buffers_0_reg[2]/CLR
|
|
(removal check against rising-edge clock cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns})
|
|
Path Group: **async_default**
|
|
Path Type: Removal (Min at Fast Process Corner)
|
|
Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns)
|
|
Data Path Delay: 1.378ns (logic 0.186ns (13.499%) route 1.192ns (86.501%))
|
|
Logic Levels: 1 (LUT1=1)
|
|
Clock Path Skew: 0.155ns (DCD - SCD - CPR)
|
|
Destination Clock Delay (DCD): -0.346ns
|
|
Source Clock Delay (SCD): -0.465ns
|
|
Clock Pessimism Removal (CPR): -0.037ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock cpu_clk rise edge) 0.000 0.000 r
|
|
K21 0.000 0.000 r clk (IN)
|
|
net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1
|
|
K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O
|
|
net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll
|
|
PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0)
|
|
-2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0
|
|
net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll
|
|
BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout1_buf/O
|
|
net (fo=6484, routed) 0.798 -0.465 pll_clk.u_rst_cpu/cpu_clk
|
|
SLICE_X0Y48 FDCE r pll_clk.u_rst_cpu/delay_reg[1]/C
|
|
------------------------------------------------------------------- -------------------
|
|
SLICE_X0Y48 FDCE (Prop_fdce_C_Q) 0.141 -0.324 r pll_clk.u_rst_cpu/delay_reg[1]/Q
|
|
net (fo=1, routed) 0.221 -0.103 pll_clk.u_rst_cpu/cpu_resetn
|
|
SLICE_X0Y48 LUT1 (Prop_lut1_I0_O) 0.045 -0.058 f pll_clk.u_rst_cpu/reset_i_1/O
|
|
net (fo=40, routed) 0.971 0.913 u_Axi_CDC/arFifo/popToPushGray_buffercc/p_0_in
|
|
SLICE_X14Y68 FDCE f u_Axi_CDC/arFifo/popToPushGray_buffercc/buffers_0_reg[2]/CLR
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock cpu_clk rise edge) 0.000 0.000 r
|
|
K21 0.000 0.000 r clk (IN)
|
|
net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1
|
|
K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O
|
|
net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll
|
|
PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0)
|
|
-2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0
|
|
net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll
|
|
BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout1_buf/O
|
|
net (fo=6484, routed) 0.962 -0.346 u_Axi_CDC/arFifo/popToPushGray_buffercc/cpu_clk
|
|
SLICE_X14Y68 FDCE r u_Axi_CDC/arFifo/popToPushGray_buffercc/buffers_0_reg[2]/C
|
|
clock pessimism 0.037 -0.309
|
|
SLICE_X14Y68 FDCE (Remov_fdce_C_CLR) -0.067 -0.376 u_Axi_CDC/arFifo/popToPushGray_buffercc/buffers_0_reg[2]
|
|
-------------------------------------------------------------------
|
|
required time 0.376
|
|
arrival time 0.913
|
|
-------------------------------------------------------------------
|
|
slack 1.290
|
|
|
|
Slack (MET) : 1.290ns (arrival time - required time)
|
|
Source: pll_clk.u_rst_cpu/delay_reg[1]/C
|
|
(rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns})
|
|
Destination: u_Axi_CDC/arFifo/popToPushGray_buffercc/buffers_1_reg[0]/CLR
|
|
(removal check against rising-edge clock cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns})
|
|
Path Group: **async_default**
|
|
Path Type: Removal (Min at Fast Process Corner)
|
|
Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns)
|
|
Data Path Delay: 1.378ns (logic 0.186ns (13.499%) route 1.192ns (86.501%))
|
|
Logic Levels: 1 (LUT1=1)
|
|
Clock Path Skew: 0.155ns (DCD - SCD - CPR)
|
|
Destination Clock Delay (DCD): -0.346ns
|
|
Source Clock Delay (SCD): -0.465ns
|
|
Clock Pessimism Removal (CPR): -0.037ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock cpu_clk rise edge) 0.000 0.000 r
|
|
K21 0.000 0.000 r clk (IN)
|
|
net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1
|
|
K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O
|
|
net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll
|
|
PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0)
|
|
-2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0
|
|
net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll
|
|
BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout1_buf/O
|
|
net (fo=6484, routed) 0.798 -0.465 pll_clk.u_rst_cpu/cpu_clk
|
|
SLICE_X0Y48 FDCE r pll_clk.u_rst_cpu/delay_reg[1]/C
|
|
------------------------------------------------------------------- -------------------
|
|
SLICE_X0Y48 FDCE (Prop_fdce_C_Q) 0.141 -0.324 r pll_clk.u_rst_cpu/delay_reg[1]/Q
|
|
net (fo=1, routed) 0.221 -0.103 pll_clk.u_rst_cpu/cpu_resetn
|
|
SLICE_X0Y48 LUT1 (Prop_lut1_I0_O) 0.045 -0.058 f pll_clk.u_rst_cpu/reset_i_1/O
|
|
net (fo=40, routed) 0.971 0.913 u_Axi_CDC/arFifo/popToPushGray_buffercc/p_0_in
|
|
SLICE_X14Y68 FDCE f u_Axi_CDC/arFifo/popToPushGray_buffercc/buffers_1_reg[0]/CLR
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock cpu_clk rise edge) 0.000 0.000 r
|
|
K21 0.000 0.000 r clk (IN)
|
|
net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1
|
|
K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O
|
|
net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll
|
|
PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0)
|
|
-2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0
|
|
net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll
|
|
BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout1_buf/O
|
|
net (fo=6484, routed) 0.962 -0.346 u_Axi_CDC/arFifo/popToPushGray_buffercc/cpu_clk
|
|
SLICE_X14Y68 FDCE r u_Axi_CDC/arFifo/popToPushGray_buffercc/buffers_1_reg[0]/C
|
|
clock pessimism 0.037 -0.309
|
|
SLICE_X14Y68 FDCE (Remov_fdce_C_CLR) -0.067 -0.376 u_Axi_CDC/arFifo/popToPushGray_buffercc/buffers_1_reg[0]
|
|
-------------------------------------------------------------------
|
|
required time 0.376
|
|
arrival time 0.913
|
|
-------------------------------------------------------------------
|
|
slack 1.290
|
|
|
|
Slack (MET) : 1.290ns (arrival time - required time)
|
|
Source: pll_clk.u_rst_cpu/delay_reg[1]/C
|
|
(rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns})
|
|
Destination: u_Axi_CDC/arFifo/popToPushGray_buffercc/buffers_1_reg[1]/CLR
|
|
(removal check against rising-edge clock cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns})
|
|
Path Group: **async_default**
|
|
Path Type: Removal (Min at Fast Process Corner)
|
|
Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns)
|
|
Data Path Delay: 1.378ns (logic 0.186ns (13.499%) route 1.192ns (86.501%))
|
|
Logic Levels: 1 (LUT1=1)
|
|
Clock Path Skew: 0.155ns (DCD - SCD - CPR)
|
|
Destination Clock Delay (DCD): -0.346ns
|
|
Source Clock Delay (SCD): -0.465ns
|
|
Clock Pessimism Removal (CPR): -0.037ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock cpu_clk rise edge) 0.000 0.000 r
|
|
K21 0.000 0.000 r clk (IN)
|
|
net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1
|
|
K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O
|
|
net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll
|
|
PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0)
|
|
-2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0
|
|
net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll
|
|
BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout1_buf/O
|
|
net (fo=6484, routed) 0.798 -0.465 pll_clk.u_rst_cpu/cpu_clk
|
|
SLICE_X0Y48 FDCE r pll_clk.u_rst_cpu/delay_reg[1]/C
|
|
------------------------------------------------------------------- -------------------
|
|
SLICE_X0Y48 FDCE (Prop_fdce_C_Q) 0.141 -0.324 r pll_clk.u_rst_cpu/delay_reg[1]/Q
|
|
net (fo=1, routed) 0.221 -0.103 pll_clk.u_rst_cpu/cpu_resetn
|
|
SLICE_X0Y48 LUT1 (Prop_lut1_I0_O) 0.045 -0.058 f pll_clk.u_rst_cpu/reset_i_1/O
|
|
net (fo=40, routed) 0.971 0.913 u_Axi_CDC/arFifo/popToPushGray_buffercc/p_0_in
|
|
SLICE_X14Y68 FDCE f u_Axi_CDC/arFifo/popToPushGray_buffercc/buffers_1_reg[1]/CLR
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock cpu_clk rise edge) 0.000 0.000 r
|
|
K21 0.000 0.000 r clk (IN)
|
|
net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1
|
|
K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O
|
|
net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll
|
|
PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0)
|
|
-2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0
|
|
net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll
|
|
BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout1_buf/O
|
|
net (fo=6484, routed) 0.962 -0.346 u_Axi_CDC/arFifo/popToPushGray_buffercc/cpu_clk
|
|
SLICE_X14Y68 FDCE r u_Axi_CDC/arFifo/popToPushGray_buffercc/buffers_1_reg[1]/C
|
|
clock pessimism 0.037 -0.309
|
|
SLICE_X14Y68 FDCE (Remov_fdce_C_CLR) -0.067 -0.376 u_Axi_CDC/arFifo/popToPushGray_buffercc/buffers_1_reg[1]
|
|
-------------------------------------------------------------------
|
|
required time 0.376
|
|
arrival time 0.913
|
|
-------------------------------------------------------------------
|
|
slack 1.290
|
|
|
|
Slack (MET) : 1.290ns (arrival time - required time)
|
|
Source: pll_clk.u_rst_cpu/delay_reg[1]/C
|
|
(rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns})
|
|
Destination: u_Axi_CDC/arFifo/popToPushGray_buffercc/buffers_1_reg[2]/CLR
|
|
(removal check against rising-edge clock cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns})
|
|
Path Group: **async_default**
|
|
Path Type: Removal (Min at Fast Process Corner)
|
|
Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns)
|
|
Data Path Delay: 1.378ns (logic 0.186ns (13.499%) route 1.192ns (86.501%))
|
|
Logic Levels: 1 (LUT1=1)
|
|
Clock Path Skew: 0.155ns (DCD - SCD - CPR)
|
|
Destination Clock Delay (DCD): -0.346ns
|
|
Source Clock Delay (SCD): -0.465ns
|
|
Clock Pessimism Removal (CPR): -0.037ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock cpu_clk rise edge) 0.000 0.000 r
|
|
K21 0.000 0.000 r clk (IN)
|
|
net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1
|
|
K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O
|
|
net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll
|
|
PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0)
|
|
-2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0
|
|
net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll
|
|
BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout1_buf/O
|
|
net (fo=6484, routed) 0.798 -0.465 pll_clk.u_rst_cpu/cpu_clk
|
|
SLICE_X0Y48 FDCE r pll_clk.u_rst_cpu/delay_reg[1]/C
|
|
------------------------------------------------------------------- -------------------
|
|
SLICE_X0Y48 FDCE (Prop_fdce_C_Q) 0.141 -0.324 r pll_clk.u_rst_cpu/delay_reg[1]/Q
|
|
net (fo=1, routed) 0.221 -0.103 pll_clk.u_rst_cpu/cpu_resetn
|
|
SLICE_X0Y48 LUT1 (Prop_lut1_I0_O) 0.045 -0.058 f pll_clk.u_rst_cpu/reset_i_1/O
|
|
net (fo=40, routed) 0.971 0.913 u_Axi_CDC/arFifo/popToPushGray_buffercc/p_0_in
|
|
SLICE_X14Y68 FDCE f u_Axi_CDC/arFifo/popToPushGray_buffercc/buffers_1_reg[2]/CLR
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock cpu_clk rise edge) 0.000 0.000 r
|
|
K21 0.000 0.000 r clk (IN)
|
|
net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1
|
|
K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O
|
|
net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll
|
|
PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0)
|
|
-2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0
|
|
net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll
|
|
BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout1_buf/O
|
|
net (fo=6484, routed) 0.962 -0.346 u_Axi_CDC/arFifo/popToPushGray_buffercc/cpu_clk
|
|
SLICE_X14Y68 FDCE r u_Axi_CDC/arFifo/popToPushGray_buffercc/buffers_1_reg[2]/C
|
|
clock pessimism 0.037 -0.309
|
|
SLICE_X14Y68 FDCE (Remov_fdce_C_CLR) -0.067 -0.376 u_Axi_CDC/arFifo/popToPushGray_buffercc/buffers_1_reg[2]
|
|
-------------------------------------------------------------------
|
|
required time 0.376
|
|
arrival time 0.913
|
|
-------------------------------------------------------------------
|
|
slack 1.290
|
|
|
|
Slack (MET) : 1.290ns (arrival time - required time)
|
|
Source: pll_clk.u_rst_cpu/delay_reg[1]/C
|
|
(rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns})
|
|
Destination: u_Axi_CDC/arFifo/pushCC_pushPtrGray_reg[0]/CLR
|
|
(removal check against rising-edge clock cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns})
|
|
Path Group: **async_default**
|
|
Path Type: Removal (Min at Fast Process Corner)
|
|
Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns)
|
|
Data Path Delay: 1.356ns (logic 0.186ns (13.719%) route 1.170ns (86.281%))
|
|
Logic Levels: 1 (LUT1=1)
|
|
Clock Path Skew: 0.157ns (DCD - SCD - CPR)
|
|
Destination Clock Delay (DCD): -0.344ns
|
|
Source Clock Delay (SCD): -0.465ns
|
|
Clock Pessimism Removal (CPR): -0.037ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock cpu_clk rise edge) 0.000 0.000 r
|
|
K21 0.000 0.000 r clk (IN)
|
|
net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1
|
|
K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O
|
|
net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll
|
|
PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0)
|
|
-2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0
|
|
net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll
|
|
BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout1_buf/O
|
|
net (fo=6484, routed) 0.798 -0.465 pll_clk.u_rst_cpu/cpu_clk
|
|
SLICE_X0Y48 FDCE r pll_clk.u_rst_cpu/delay_reg[1]/C
|
|
------------------------------------------------------------------- -------------------
|
|
SLICE_X0Y48 FDCE (Prop_fdce_C_Q) 0.141 -0.324 r pll_clk.u_rst_cpu/delay_reg[1]/Q
|
|
net (fo=1, routed) 0.221 -0.103 pll_clk.u_rst_cpu/cpu_resetn
|
|
SLICE_X0Y48 LUT1 (Prop_lut1_I0_O) 0.045 -0.058 f pll_clk.u_rst_cpu/reset_i_1/O
|
|
net (fo=40, routed) 0.949 0.891 u_Axi_CDC/arFifo/p_0_in
|
|
SLICE_X17Y66 FDCE f u_Axi_CDC/arFifo/pushCC_pushPtrGray_reg[0]/CLR
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock cpu_clk rise edge) 0.000 0.000 r
|
|
K21 0.000 0.000 r clk (IN)
|
|
net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1
|
|
K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O
|
|
net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll
|
|
PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0)
|
|
-2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0
|
|
net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll
|
|
BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout1_buf/O
|
|
net (fo=6484, routed) 0.964 -0.344 u_Axi_CDC/arFifo/cpu_clk
|
|
SLICE_X17Y66 FDCE r u_Axi_CDC/arFifo/pushCC_pushPtrGray_reg[0]/C
|
|
clock pessimism 0.037 -0.307
|
|
SLICE_X17Y66 FDCE (Remov_fdce_C_CLR) -0.092 -0.399 u_Axi_CDC/arFifo/pushCC_pushPtrGray_reg[0]
|
|
-------------------------------------------------------------------
|
|
required time 0.399
|
|
arrival time 0.891
|
|
-------------------------------------------------------------------
|
|
slack 1.290
|
|
|
|
Slack (MET) : 1.290ns (arrival time - required time)
|
|
Source: pll_clk.u_rst_cpu/delay_reg[1]/C
|
|
(rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns})
|
|
Destination: u_Axi_CDC/arFifo/pushCC_pushPtrGray_reg[1]/CLR
|
|
(removal check against rising-edge clock cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns})
|
|
Path Group: **async_default**
|
|
Path Type: Removal (Min at Fast Process Corner)
|
|
Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns)
|
|
Data Path Delay: 1.356ns (logic 0.186ns (13.719%) route 1.170ns (86.281%))
|
|
Logic Levels: 1 (LUT1=1)
|
|
Clock Path Skew: 0.157ns (DCD - SCD - CPR)
|
|
Destination Clock Delay (DCD): -0.344ns
|
|
Source Clock Delay (SCD): -0.465ns
|
|
Clock Pessimism Removal (CPR): -0.037ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock cpu_clk rise edge) 0.000 0.000 r
|
|
K21 0.000 0.000 r clk (IN)
|
|
net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1
|
|
K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O
|
|
net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll
|
|
PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0)
|
|
-2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0
|
|
net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll
|
|
BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout1_buf/O
|
|
net (fo=6484, routed) 0.798 -0.465 pll_clk.u_rst_cpu/cpu_clk
|
|
SLICE_X0Y48 FDCE r pll_clk.u_rst_cpu/delay_reg[1]/C
|
|
------------------------------------------------------------------- -------------------
|
|
SLICE_X0Y48 FDCE (Prop_fdce_C_Q) 0.141 -0.324 r pll_clk.u_rst_cpu/delay_reg[1]/Q
|
|
net (fo=1, routed) 0.221 -0.103 pll_clk.u_rst_cpu/cpu_resetn
|
|
SLICE_X0Y48 LUT1 (Prop_lut1_I0_O) 0.045 -0.058 f pll_clk.u_rst_cpu/reset_i_1/O
|
|
net (fo=40, routed) 0.949 0.891 u_Axi_CDC/arFifo/p_0_in
|
|
SLICE_X17Y66 FDCE f u_Axi_CDC/arFifo/pushCC_pushPtrGray_reg[1]/CLR
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock cpu_clk rise edge) 0.000 0.000 r
|
|
K21 0.000 0.000 r clk (IN)
|
|
net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1
|
|
K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O
|
|
net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll
|
|
PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0)
|
|
-2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0
|
|
net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll
|
|
BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout1_buf/O
|
|
net (fo=6484, routed) 0.964 -0.344 u_Axi_CDC/arFifo/cpu_clk
|
|
SLICE_X17Y66 FDCE r u_Axi_CDC/arFifo/pushCC_pushPtrGray_reg[1]/C
|
|
clock pessimism 0.037 -0.307
|
|
SLICE_X17Y66 FDCE (Remov_fdce_C_CLR) -0.092 -0.399 u_Axi_CDC/arFifo/pushCC_pushPtrGray_reg[1]
|
|
-------------------------------------------------------------------
|
|
required time 0.399
|
|
arrival time 0.891
|
|
-------------------------------------------------------------------
|
|
slack 1.290
|
|
|
|
Slack (MET) : 1.290ns (arrival time - required time)
|
|
Source: pll_clk.u_rst_cpu/delay_reg[1]/C
|
|
(rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns})
|
|
Destination: u_Axi_CDC/arFifo/pushCC_pushPtrGray_reg[2]/CLR
|
|
(removal check against rising-edge clock cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns})
|
|
Path Group: **async_default**
|
|
Path Type: Removal (Min at Fast Process Corner)
|
|
Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns)
|
|
Data Path Delay: 1.356ns (logic 0.186ns (13.719%) route 1.170ns (86.281%))
|
|
Logic Levels: 1 (LUT1=1)
|
|
Clock Path Skew: 0.157ns (DCD - SCD - CPR)
|
|
Destination Clock Delay (DCD): -0.344ns
|
|
Source Clock Delay (SCD): -0.465ns
|
|
Clock Pessimism Removal (CPR): -0.037ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock cpu_clk rise edge) 0.000 0.000 r
|
|
K21 0.000 0.000 r clk (IN)
|
|
net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1
|
|
K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O
|
|
net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll
|
|
PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0)
|
|
-2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0
|
|
net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll
|
|
BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout1_buf/O
|
|
net (fo=6484, routed) 0.798 -0.465 pll_clk.u_rst_cpu/cpu_clk
|
|
SLICE_X0Y48 FDCE r pll_clk.u_rst_cpu/delay_reg[1]/C
|
|
------------------------------------------------------------------- -------------------
|
|
SLICE_X0Y48 FDCE (Prop_fdce_C_Q) 0.141 -0.324 r pll_clk.u_rst_cpu/delay_reg[1]/Q
|
|
net (fo=1, routed) 0.221 -0.103 pll_clk.u_rst_cpu/cpu_resetn
|
|
SLICE_X0Y48 LUT1 (Prop_lut1_I0_O) 0.045 -0.058 f pll_clk.u_rst_cpu/reset_i_1/O
|
|
net (fo=40, routed) 0.949 0.891 u_Axi_CDC/arFifo/p_0_in
|
|
SLICE_X17Y66 FDCE f u_Axi_CDC/arFifo/pushCC_pushPtrGray_reg[2]/CLR
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock cpu_clk rise edge) 0.000 0.000 r
|
|
K21 0.000 0.000 r clk (IN)
|
|
net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1
|
|
K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O
|
|
net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll
|
|
PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0)
|
|
-2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0
|
|
net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll
|
|
BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout1_buf/O
|
|
net (fo=6484, routed) 0.964 -0.344 u_Axi_CDC/arFifo/cpu_clk
|
|
SLICE_X17Y66 FDCE r u_Axi_CDC/arFifo/pushCC_pushPtrGray_reg[2]/C
|
|
clock pessimism 0.037 -0.307
|
|
SLICE_X17Y66 FDCE (Remov_fdce_C_CLR) -0.092 -0.399 u_Axi_CDC/arFifo/pushCC_pushPtrGray_reg[2]
|
|
-------------------------------------------------------------------
|
|
required time 0.399
|
|
arrival time 0.891
|
|
-------------------------------------------------------------------
|
|
slack 1.290
|
|
|
|
Slack (MET) : 1.290ns (arrival time - required time)
|
|
Source: pll_clk.u_rst_cpu/delay_reg[1]/C
|
|
(rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns})
|
|
Destination: u_Axi_CDC/arFifo/pushCC_pushPtr_reg[0]/CLR
|
|
(removal check against rising-edge clock cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns})
|
|
Path Group: **async_default**
|
|
Path Type: Removal (Min at Fast Process Corner)
|
|
Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns)
|
|
Data Path Delay: 1.356ns (logic 0.186ns (13.719%) route 1.170ns (86.281%))
|
|
Logic Levels: 1 (LUT1=1)
|
|
Clock Path Skew: 0.157ns (DCD - SCD - CPR)
|
|
Destination Clock Delay (DCD): -0.344ns
|
|
Source Clock Delay (SCD): -0.465ns
|
|
Clock Pessimism Removal (CPR): -0.037ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock cpu_clk rise edge) 0.000 0.000 r
|
|
K21 0.000 0.000 r clk (IN)
|
|
net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1
|
|
K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O
|
|
net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll
|
|
PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0)
|
|
-2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0
|
|
net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll
|
|
BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout1_buf/O
|
|
net (fo=6484, routed) 0.798 -0.465 pll_clk.u_rst_cpu/cpu_clk
|
|
SLICE_X0Y48 FDCE r pll_clk.u_rst_cpu/delay_reg[1]/C
|
|
------------------------------------------------------------------- -------------------
|
|
SLICE_X0Y48 FDCE (Prop_fdce_C_Q) 0.141 -0.324 r pll_clk.u_rst_cpu/delay_reg[1]/Q
|
|
net (fo=1, routed) 0.221 -0.103 pll_clk.u_rst_cpu/cpu_resetn
|
|
SLICE_X0Y48 LUT1 (Prop_lut1_I0_O) 0.045 -0.058 f pll_clk.u_rst_cpu/reset_i_1/O
|
|
net (fo=40, routed) 0.949 0.891 u_Axi_CDC/arFifo/p_0_in
|
|
SLICE_X17Y66 FDCE f u_Axi_CDC/arFifo/pushCC_pushPtr_reg[0]/CLR
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock cpu_clk rise edge) 0.000 0.000 r
|
|
K21 0.000 0.000 r clk (IN)
|
|
net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1
|
|
K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O
|
|
net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll
|
|
PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0)
|
|
-2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0
|
|
net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll
|
|
BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout1_buf/O
|
|
net (fo=6484, routed) 0.964 -0.344 u_Axi_CDC/arFifo/cpu_clk
|
|
SLICE_X17Y66 FDCE r u_Axi_CDC/arFifo/pushCC_pushPtr_reg[0]/C
|
|
clock pessimism 0.037 -0.307
|
|
SLICE_X17Y66 FDCE (Remov_fdce_C_CLR) -0.092 -0.399 u_Axi_CDC/arFifo/pushCC_pushPtr_reg[0]
|
|
-------------------------------------------------------------------
|
|
required time 0.399
|
|
arrival time 0.891
|
|
-------------------------------------------------------------------
|
|
slack 1.290
|
|
|
|
Slack (MET) : 1.290ns (arrival time - required time)
|
|
Source: pll_clk.u_rst_cpu/delay_reg[1]/C
|
|
(rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns})
|
|
Destination: u_Axi_CDC/arFifo/pushCC_pushPtr_reg[1]/CLR
|
|
(removal check against rising-edge clock cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns})
|
|
Path Group: **async_default**
|
|
Path Type: Removal (Min at Fast Process Corner)
|
|
Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns)
|
|
Data Path Delay: 1.356ns (logic 0.186ns (13.719%) route 1.170ns (86.281%))
|
|
Logic Levels: 1 (LUT1=1)
|
|
Clock Path Skew: 0.157ns (DCD - SCD - CPR)
|
|
Destination Clock Delay (DCD): -0.344ns
|
|
Source Clock Delay (SCD): -0.465ns
|
|
Clock Pessimism Removal (CPR): -0.037ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock cpu_clk rise edge) 0.000 0.000 r
|
|
K21 0.000 0.000 r clk (IN)
|
|
net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1
|
|
K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O
|
|
net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll
|
|
PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0)
|
|
-2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0
|
|
net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll
|
|
BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout1_buf/O
|
|
net (fo=6484, routed) 0.798 -0.465 pll_clk.u_rst_cpu/cpu_clk
|
|
SLICE_X0Y48 FDCE r pll_clk.u_rst_cpu/delay_reg[1]/C
|
|
------------------------------------------------------------------- -------------------
|
|
SLICE_X0Y48 FDCE (Prop_fdce_C_Q) 0.141 -0.324 r pll_clk.u_rst_cpu/delay_reg[1]/Q
|
|
net (fo=1, routed) 0.221 -0.103 pll_clk.u_rst_cpu/cpu_resetn
|
|
SLICE_X0Y48 LUT1 (Prop_lut1_I0_O) 0.045 -0.058 f pll_clk.u_rst_cpu/reset_i_1/O
|
|
net (fo=40, routed) 0.949 0.891 u_Axi_CDC/arFifo/p_0_in
|
|
SLICE_X17Y66 FDCE f u_Axi_CDC/arFifo/pushCC_pushPtr_reg[1]/CLR
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock cpu_clk rise edge) 0.000 0.000 r
|
|
K21 0.000 0.000 r clk (IN)
|
|
net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1
|
|
K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O
|
|
net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll
|
|
PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0)
|
|
-2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0
|
|
net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll
|
|
BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout1_buf/O
|
|
net (fo=6484, routed) 0.964 -0.344 u_Axi_CDC/arFifo/cpu_clk
|
|
SLICE_X17Y66 FDCE r u_Axi_CDC/arFifo/pushCC_pushPtr_reg[1]/C
|
|
clock pessimism 0.037 -0.307
|
|
SLICE_X17Y66 FDCE (Remov_fdce_C_CLR) -0.092 -0.399 u_Axi_CDC/arFifo/pushCC_pushPtr_reg[1]
|
|
-------------------------------------------------------------------
|
|
required time 0.399
|
|
arrival time 0.891
|
|
-------------------------------------------------------------------
|
|
slack 1.290
|
|
|
|
Slack (MET) : 1.356ns (arrival time - required time)
|
|
Source: pll_clk.u_rst_cpu/delay_reg[1]/C
|
|
(rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns})
|
|
Destination: u_Axi_CDC/awFifo/pushCC_pushPtrGray_reg[0]/CLR
|
|
(removal check against rising-edge clock cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns})
|
|
Path Group: **async_default**
|
|
Path Type: Removal (Min at Fast Process Corner)
|
|
Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns)
|
|
Data Path Delay: 1.443ns (logic 0.186ns (12.888%) route 1.257ns (87.112%))
|
|
Logic Levels: 1 (LUT1=1)
|
|
Clock Path Skew: 0.154ns (DCD - SCD - CPR)
|
|
Destination Clock Delay (DCD): -0.347ns
|
|
Source Clock Delay (SCD): -0.465ns
|
|
Clock Pessimism Removal (CPR): -0.037ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock cpu_clk rise edge) 0.000 0.000 r
|
|
K21 0.000 0.000 r clk (IN)
|
|
net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1
|
|
K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O
|
|
net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll
|
|
PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0)
|
|
-2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0
|
|
net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll
|
|
BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout1_buf/O
|
|
net (fo=6484, routed) 0.798 -0.465 pll_clk.u_rst_cpu/cpu_clk
|
|
SLICE_X0Y48 FDCE r pll_clk.u_rst_cpu/delay_reg[1]/C
|
|
------------------------------------------------------------------- -------------------
|
|
SLICE_X0Y48 FDCE (Prop_fdce_C_Q) 0.141 -0.324 r pll_clk.u_rst_cpu/delay_reg[1]/Q
|
|
net (fo=1, routed) 0.221 -0.103 pll_clk.u_rst_cpu/cpu_resetn
|
|
SLICE_X0Y48 LUT1 (Prop_lut1_I0_O) 0.045 -0.058 f pll_clk.u_rst_cpu/reset_i_1/O
|
|
net (fo=40, routed) 1.036 0.978 u_Axi_CDC/awFifo/p_0_in
|
|
SLICE_X14Y69 FDCE f u_Axi_CDC/awFifo/pushCC_pushPtrGray_reg[0]/CLR
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock cpu_clk rise edge) 0.000 0.000 r
|
|
K21 0.000 0.000 r clk (IN)
|
|
net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1
|
|
K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O
|
|
net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll
|
|
PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0)
|
|
-2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0
|
|
net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll
|
|
BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout1_buf/O
|
|
net (fo=6484, routed) 0.961 -0.347 u_Axi_CDC/awFifo/cpu_clk
|
|
SLICE_X14Y69 FDCE r u_Axi_CDC/awFifo/pushCC_pushPtrGray_reg[0]/C
|
|
clock pessimism 0.037 -0.310
|
|
SLICE_X14Y69 FDCE (Remov_fdce_C_CLR) -0.067 -0.377 u_Axi_CDC/awFifo/pushCC_pushPtrGray_reg[0]
|
|
-------------------------------------------------------------------
|
|
required time 0.377
|
|
arrival time 0.978
|
|
-------------------------------------------------------------------
|
|
slack 1.356
|
|
|
|
Slack (MET) : 1.356ns (arrival time - required time)
|
|
Source: pll_clk.u_rst_cpu/delay_reg[1]/C
|
|
(rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns})
|
|
Destination: u_Axi_CDC/awFifo/pushCC_pushPtrGray_reg[1]/CLR
|
|
(removal check against rising-edge clock cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns})
|
|
Path Group: **async_default**
|
|
Path Type: Removal (Min at Fast Process Corner)
|
|
Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns)
|
|
Data Path Delay: 1.443ns (logic 0.186ns (12.888%) route 1.257ns (87.112%))
|
|
Logic Levels: 1 (LUT1=1)
|
|
Clock Path Skew: 0.154ns (DCD - SCD - CPR)
|
|
Destination Clock Delay (DCD): -0.347ns
|
|
Source Clock Delay (SCD): -0.465ns
|
|
Clock Pessimism Removal (CPR): -0.037ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock cpu_clk rise edge) 0.000 0.000 r
|
|
K21 0.000 0.000 r clk (IN)
|
|
net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1
|
|
K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O
|
|
net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll
|
|
PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0)
|
|
-2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0
|
|
net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll
|
|
BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout1_buf/O
|
|
net (fo=6484, routed) 0.798 -0.465 pll_clk.u_rst_cpu/cpu_clk
|
|
SLICE_X0Y48 FDCE r pll_clk.u_rst_cpu/delay_reg[1]/C
|
|
------------------------------------------------------------------- -------------------
|
|
SLICE_X0Y48 FDCE (Prop_fdce_C_Q) 0.141 -0.324 r pll_clk.u_rst_cpu/delay_reg[1]/Q
|
|
net (fo=1, routed) 0.221 -0.103 pll_clk.u_rst_cpu/cpu_resetn
|
|
SLICE_X0Y48 LUT1 (Prop_lut1_I0_O) 0.045 -0.058 f pll_clk.u_rst_cpu/reset_i_1/O
|
|
net (fo=40, routed) 1.036 0.978 u_Axi_CDC/awFifo/p_0_in
|
|
SLICE_X14Y69 FDCE f u_Axi_CDC/awFifo/pushCC_pushPtrGray_reg[1]/CLR
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock cpu_clk rise edge) 0.000 0.000 r
|
|
K21 0.000 0.000 r clk (IN)
|
|
net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1
|
|
K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O
|
|
net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll
|
|
PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0)
|
|
-2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0
|
|
net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll
|
|
BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout1_buf/O
|
|
net (fo=6484, routed) 0.961 -0.347 u_Axi_CDC/awFifo/cpu_clk
|
|
SLICE_X14Y69 FDCE r u_Axi_CDC/awFifo/pushCC_pushPtrGray_reg[1]/C
|
|
clock pessimism 0.037 -0.310
|
|
SLICE_X14Y69 FDCE (Remov_fdce_C_CLR) -0.067 -0.377 u_Axi_CDC/awFifo/pushCC_pushPtrGray_reg[1]
|
|
-------------------------------------------------------------------
|
|
required time 0.377
|
|
arrival time 0.978
|
|
-------------------------------------------------------------------
|
|
slack 1.356
|
|
|
|
Slack (MET) : 1.356ns (arrival time - required time)
|
|
Source: pll_clk.u_rst_cpu/delay_reg[1]/C
|
|
(rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns})
|
|
Destination: u_Axi_CDC/awFifo/pushCC_pushPtrGray_reg[2]/CLR
|
|
(removal check against rising-edge clock cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns})
|
|
Path Group: **async_default**
|
|
Path Type: Removal (Min at Fast Process Corner)
|
|
Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns)
|
|
Data Path Delay: 1.443ns (logic 0.186ns (12.888%) route 1.257ns (87.112%))
|
|
Logic Levels: 1 (LUT1=1)
|
|
Clock Path Skew: 0.154ns (DCD - SCD - CPR)
|
|
Destination Clock Delay (DCD): -0.347ns
|
|
Source Clock Delay (SCD): -0.465ns
|
|
Clock Pessimism Removal (CPR): -0.037ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock cpu_clk rise edge) 0.000 0.000 r
|
|
K21 0.000 0.000 r clk (IN)
|
|
net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1
|
|
K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O
|
|
net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll
|
|
PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0)
|
|
-2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0
|
|
net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll
|
|
BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout1_buf/O
|
|
net (fo=6484, routed) 0.798 -0.465 pll_clk.u_rst_cpu/cpu_clk
|
|
SLICE_X0Y48 FDCE r pll_clk.u_rst_cpu/delay_reg[1]/C
|
|
------------------------------------------------------------------- -------------------
|
|
SLICE_X0Y48 FDCE (Prop_fdce_C_Q) 0.141 -0.324 r pll_clk.u_rst_cpu/delay_reg[1]/Q
|
|
net (fo=1, routed) 0.221 -0.103 pll_clk.u_rst_cpu/cpu_resetn
|
|
SLICE_X0Y48 LUT1 (Prop_lut1_I0_O) 0.045 -0.058 f pll_clk.u_rst_cpu/reset_i_1/O
|
|
net (fo=40, routed) 1.036 0.978 u_Axi_CDC/awFifo/p_0_in
|
|
SLICE_X14Y69 FDCE f u_Axi_CDC/awFifo/pushCC_pushPtrGray_reg[2]/CLR
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock cpu_clk rise edge) 0.000 0.000 r
|
|
K21 0.000 0.000 r clk (IN)
|
|
net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1
|
|
K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O
|
|
net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll
|
|
PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0)
|
|
-2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0
|
|
net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll
|
|
BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout1_buf/O
|
|
net (fo=6484, routed) 0.961 -0.347 u_Axi_CDC/awFifo/cpu_clk
|
|
SLICE_X14Y69 FDCE r u_Axi_CDC/awFifo/pushCC_pushPtrGray_reg[2]/C
|
|
clock pessimism 0.037 -0.310
|
|
SLICE_X14Y69 FDCE (Remov_fdce_C_CLR) -0.067 -0.377 u_Axi_CDC/awFifo/pushCC_pushPtrGray_reg[2]
|
|
-------------------------------------------------------------------
|
|
required time 0.377
|
|
arrival time 0.978
|
|
-------------------------------------------------------------------
|
|
slack 1.356
|
|
|
|
Slack (MET) : 1.356ns (arrival time - required time)
|
|
Source: pll_clk.u_rst_cpu/delay_reg[1]/C
|
|
(rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns})
|
|
Destination: u_Axi_CDC/awFifo/pushCC_pushPtr_reg[0]/CLR
|
|
(removal check against rising-edge clock cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns})
|
|
Path Group: **async_default**
|
|
Path Type: Removal (Min at Fast Process Corner)
|
|
Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns)
|
|
Data Path Delay: 1.443ns (logic 0.186ns (12.888%) route 1.257ns (87.112%))
|
|
Logic Levels: 1 (LUT1=1)
|
|
Clock Path Skew: 0.154ns (DCD - SCD - CPR)
|
|
Destination Clock Delay (DCD): -0.347ns
|
|
Source Clock Delay (SCD): -0.465ns
|
|
Clock Pessimism Removal (CPR): -0.037ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock cpu_clk rise edge) 0.000 0.000 r
|
|
K21 0.000 0.000 r clk (IN)
|
|
net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1
|
|
K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O
|
|
net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll
|
|
PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0)
|
|
-2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0
|
|
net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll
|
|
BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout1_buf/O
|
|
net (fo=6484, routed) 0.798 -0.465 pll_clk.u_rst_cpu/cpu_clk
|
|
SLICE_X0Y48 FDCE r pll_clk.u_rst_cpu/delay_reg[1]/C
|
|
------------------------------------------------------------------- -------------------
|
|
SLICE_X0Y48 FDCE (Prop_fdce_C_Q) 0.141 -0.324 r pll_clk.u_rst_cpu/delay_reg[1]/Q
|
|
net (fo=1, routed) 0.221 -0.103 pll_clk.u_rst_cpu/cpu_resetn
|
|
SLICE_X0Y48 LUT1 (Prop_lut1_I0_O) 0.045 -0.058 f pll_clk.u_rst_cpu/reset_i_1/O
|
|
net (fo=40, routed) 1.036 0.978 u_Axi_CDC/awFifo/p_0_in
|
|
SLICE_X14Y69 FDCE f u_Axi_CDC/awFifo/pushCC_pushPtr_reg[0]/CLR
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock cpu_clk rise edge) 0.000 0.000 r
|
|
K21 0.000 0.000 r clk (IN)
|
|
net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1
|
|
K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O
|
|
net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll
|
|
PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0)
|
|
-2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0
|
|
net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll
|
|
BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout1_buf/O
|
|
net (fo=6484, routed) 0.961 -0.347 u_Axi_CDC/awFifo/cpu_clk
|
|
SLICE_X14Y69 FDCE r u_Axi_CDC/awFifo/pushCC_pushPtr_reg[0]/C
|
|
clock pessimism 0.037 -0.310
|
|
SLICE_X14Y69 FDCE (Remov_fdce_C_CLR) -0.067 -0.377 u_Axi_CDC/awFifo/pushCC_pushPtr_reg[0]
|
|
-------------------------------------------------------------------
|
|
required time 0.377
|
|
arrival time 0.978
|
|
-------------------------------------------------------------------
|
|
slack 1.356
|
|
|
|
Slack (MET) : 1.356ns (arrival time - required time)
|
|
Source: pll_clk.u_rst_cpu/delay_reg[1]/C
|
|
(rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns})
|
|
Destination: u_Axi_CDC/awFifo/pushCC_pushPtr_reg[1]/CLR
|
|
(removal check against rising-edge clock cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns})
|
|
Path Group: **async_default**
|
|
Path Type: Removal (Min at Fast Process Corner)
|
|
Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns)
|
|
Data Path Delay: 1.443ns (logic 0.186ns (12.888%) route 1.257ns (87.112%))
|
|
Logic Levels: 1 (LUT1=1)
|
|
Clock Path Skew: 0.154ns (DCD - SCD - CPR)
|
|
Destination Clock Delay (DCD): -0.347ns
|
|
Source Clock Delay (SCD): -0.465ns
|
|
Clock Pessimism Removal (CPR): -0.037ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock cpu_clk rise edge) 0.000 0.000 r
|
|
K21 0.000 0.000 r clk (IN)
|
|
net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1
|
|
K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O
|
|
net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll
|
|
PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0)
|
|
-2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0
|
|
net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll
|
|
BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout1_buf/O
|
|
net (fo=6484, routed) 0.798 -0.465 pll_clk.u_rst_cpu/cpu_clk
|
|
SLICE_X0Y48 FDCE r pll_clk.u_rst_cpu/delay_reg[1]/C
|
|
------------------------------------------------------------------- -------------------
|
|
SLICE_X0Y48 FDCE (Prop_fdce_C_Q) 0.141 -0.324 r pll_clk.u_rst_cpu/delay_reg[1]/Q
|
|
net (fo=1, routed) 0.221 -0.103 pll_clk.u_rst_cpu/cpu_resetn
|
|
SLICE_X0Y48 LUT1 (Prop_lut1_I0_O) 0.045 -0.058 f pll_clk.u_rst_cpu/reset_i_1/O
|
|
net (fo=40, routed) 1.036 0.978 u_Axi_CDC/awFifo/p_0_in
|
|
SLICE_X14Y69 FDCE f u_Axi_CDC/awFifo/pushCC_pushPtr_reg[1]/CLR
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock cpu_clk rise edge) 0.000 0.000 r
|
|
K21 0.000 0.000 r clk (IN)
|
|
net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1
|
|
K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O
|
|
net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll
|
|
PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0)
|
|
-2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0
|
|
net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll
|
|
BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout1_buf/O
|
|
net (fo=6484, routed) 0.961 -0.347 u_Axi_CDC/awFifo/cpu_clk
|
|
SLICE_X14Y69 FDCE r u_Axi_CDC/awFifo/pushCC_pushPtr_reg[1]/C
|
|
clock pessimism 0.037 -0.310
|
|
SLICE_X14Y69 FDCE (Remov_fdce_C_CLR) -0.067 -0.377 u_Axi_CDC/awFifo/pushCC_pushPtr_reg[1]
|
|
-------------------------------------------------------------------
|
|
required time 0.377
|
|
arrival time 0.978
|
|
-------------------------------------------------------------------
|
|
slack 1.356
|
|
|
|
Slack (MET) : 1.366ns (arrival time - required time)
|
|
Source: u_Axi_CDC/bFifo/bufferCC_12/buffers_1_reg/C
|
|
(rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns})
|
|
Destination: u_Axi_CDC/rFifo/popCC_popPtr_reg[1]/CLR
|
|
(removal check against rising-edge clock cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns})
|
|
Path Group: **async_default**
|
|
Path Type: Removal (Min at Fast Process Corner)
|
|
Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns)
|
|
Data Path Delay: 1.358ns (logic 0.227ns (16.717%) route 1.131ns (83.283%))
|
|
Logic Levels: 1 (LUT1=1)
|
|
Clock Path Skew: 0.059ns (DCD - SCD - CPR)
|
|
Destination Clock Delay (DCD): -0.324ns
|
|
Source Clock Delay (SCD): -0.575ns
|
|
Clock Pessimism Removal (CPR): 0.192ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock cpu_clk rise edge) 0.000 0.000 r
|
|
K21 0.000 0.000 r clk (IN)
|
|
net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1
|
|
K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O
|
|
net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll
|
|
PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0)
|
|
-2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0
|
|
net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll
|
|
BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout1_buf/O
|
|
net (fo=6484, routed) 0.687 -0.575 u_Axi_CDC/bFifo/bufferCC_12/cpu_clk
|
|
SLICE_X30Y58 FDCE r u_Axi_CDC/bFifo/bufferCC_12/buffers_1_reg/C
|
|
------------------------------------------------------------------- -------------------
|
|
SLICE_X30Y58 FDCE (Prop_fdce_C_Q) 0.128 -0.447 r u_Axi_CDC/bFifo/bufferCC_12/buffers_1_reg/Q
|
|
net (fo=1, routed) 0.207 -0.241 u_Axi_CDC/bFifo/bufferCC_12/buffers_1
|
|
SLICE_X28Y58 LUT1 (Prop_lut1_I0_O) 0.099 -0.142 f u_Axi_CDC/bFifo/bufferCC_12/popCC_popPtr[2]_i_2__0/O
|
|
net (fo=30, routed) 0.924 0.783 u_Axi_CDC/rFifo/buffers_0_reg[3]
|
|
SLICE_X6Y74 FDCE f u_Axi_CDC/rFifo/popCC_popPtr_reg[1]/CLR
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock cpu_clk rise edge) 0.000 0.000 r
|
|
K21 0.000 0.000 r clk (IN)
|
|
net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1
|
|
K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O
|
|
net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll
|
|
PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0)
|
|
-2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0
|
|
net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll
|
|
BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout1_buf/O
|
|
net (fo=6484, routed) 0.984 -0.324 u_Axi_CDC/rFifo/cpu_clk
|
|
SLICE_X6Y74 FDCE r u_Axi_CDC/rFifo/popCC_popPtr_reg[1]/C
|
|
clock pessimism -0.192 -0.516
|
|
SLICE_X6Y74 FDCE (Remov_fdce_C_CLR) -0.067 -0.583 u_Axi_CDC/rFifo/popCC_popPtr_reg[1]
|
|
-------------------------------------------------------------------
|
|
required time 0.583
|
|
arrival time 0.783
|
|
-------------------------------------------------------------------
|
|
slack 1.366
|
|
|
|
Slack (MET) : 1.381ns (arrival time - required time)
|
|
Source: pll_clk.u_rst_cpu/delay_reg[1]/C
|
|
(rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns})
|
|
Destination: u_Axi_CDC/awFifo/popToPushGray_buffercc/buffers_0_reg[0]/CLR
|
|
(removal check against rising-edge clock cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns})
|
|
Path Group: **async_default**
|
|
Path Type: Removal (Min at Fast Process Corner)
|
|
Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns)
|
|
Data Path Delay: 1.443ns (logic 0.186ns (12.888%) route 1.257ns (87.112%))
|
|
Logic Levels: 1 (LUT1=1)
|
|
Clock Path Skew: 0.154ns (DCD - SCD - CPR)
|
|
Destination Clock Delay (DCD): -0.347ns
|
|
Source Clock Delay (SCD): -0.465ns
|
|
Clock Pessimism Removal (CPR): -0.037ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock cpu_clk rise edge) 0.000 0.000 r
|
|
K21 0.000 0.000 r clk (IN)
|
|
net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1
|
|
K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O
|
|
net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll
|
|
PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0)
|
|
-2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0
|
|
net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll
|
|
BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout1_buf/O
|
|
net (fo=6484, routed) 0.798 -0.465 pll_clk.u_rst_cpu/cpu_clk
|
|
SLICE_X0Y48 FDCE r pll_clk.u_rst_cpu/delay_reg[1]/C
|
|
------------------------------------------------------------------- -------------------
|
|
SLICE_X0Y48 FDCE (Prop_fdce_C_Q) 0.141 -0.324 r pll_clk.u_rst_cpu/delay_reg[1]/Q
|
|
net (fo=1, routed) 0.221 -0.103 pll_clk.u_rst_cpu/cpu_resetn
|
|
SLICE_X0Y48 LUT1 (Prop_lut1_I0_O) 0.045 -0.058 f pll_clk.u_rst_cpu/reset_i_1/O
|
|
net (fo=40, routed) 1.036 0.978 u_Axi_CDC/awFifo/popToPushGray_buffercc/p_0_in
|
|
SLICE_X15Y69 FDCE f u_Axi_CDC/awFifo/popToPushGray_buffercc/buffers_0_reg[0]/CLR
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock cpu_clk rise edge) 0.000 0.000 r
|
|
K21 0.000 0.000 r clk (IN)
|
|
net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1
|
|
K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O
|
|
net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll
|
|
PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0)
|
|
-2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0
|
|
net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll
|
|
BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout1_buf/O
|
|
net (fo=6484, routed) 0.961 -0.347 u_Axi_CDC/awFifo/popToPushGray_buffercc/cpu_clk
|
|
SLICE_X15Y69 FDCE r u_Axi_CDC/awFifo/popToPushGray_buffercc/buffers_0_reg[0]/C
|
|
clock pessimism 0.037 -0.310
|
|
SLICE_X15Y69 FDCE (Remov_fdce_C_CLR) -0.092 -0.402 u_Axi_CDC/awFifo/popToPushGray_buffercc/buffers_0_reg[0]
|
|
-------------------------------------------------------------------
|
|
required time 0.402
|
|
arrival time 0.978
|
|
-------------------------------------------------------------------
|
|
slack 1.381
|
|
|
|
Slack (MET) : 1.381ns (arrival time - required time)
|
|
Source: pll_clk.u_rst_cpu/delay_reg[1]/C
|
|
(rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns})
|
|
Destination: u_Axi_CDC/awFifo/popToPushGray_buffercc/buffers_0_reg[1]/CLR
|
|
(removal check against rising-edge clock cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns})
|
|
Path Group: **async_default**
|
|
Path Type: Removal (Min at Fast Process Corner)
|
|
Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns)
|
|
Data Path Delay: 1.443ns (logic 0.186ns (12.888%) route 1.257ns (87.112%))
|
|
Logic Levels: 1 (LUT1=1)
|
|
Clock Path Skew: 0.154ns (DCD - SCD - CPR)
|
|
Destination Clock Delay (DCD): -0.347ns
|
|
Source Clock Delay (SCD): -0.465ns
|
|
Clock Pessimism Removal (CPR): -0.037ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock cpu_clk rise edge) 0.000 0.000 r
|
|
K21 0.000 0.000 r clk (IN)
|
|
net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1
|
|
K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O
|
|
net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll
|
|
PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0)
|
|
-2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0
|
|
net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll
|
|
BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout1_buf/O
|
|
net (fo=6484, routed) 0.798 -0.465 pll_clk.u_rst_cpu/cpu_clk
|
|
SLICE_X0Y48 FDCE r pll_clk.u_rst_cpu/delay_reg[1]/C
|
|
------------------------------------------------------------------- -------------------
|
|
SLICE_X0Y48 FDCE (Prop_fdce_C_Q) 0.141 -0.324 r pll_clk.u_rst_cpu/delay_reg[1]/Q
|
|
net (fo=1, routed) 0.221 -0.103 pll_clk.u_rst_cpu/cpu_resetn
|
|
SLICE_X0Y48 LUT1 (Prop_lut1_I0_O) 0.045 -0.058 f pll_clk.u_rst_cpu/reset_i_1/O
|
|
net (fo=40, routed) 1.036 0.978 u_Axi_CDC/awFifo/popToPushGray_buffercc/p_0_in
|
|
SLICE_X15Y69 FDCE f u_Axi_CDC/awFifo/popToPushGray_buffercc/buffers_0_reg[1]/CLR
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock cpu_clk rise edge) 0.000 0.000 r
|
|
K21 0.000 0.000 r clk (IN)
|
|
net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1
|
|
K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O
|
|
net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll
|
|
PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0)
|
|
-2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0
|
|
net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll
|
|
BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout1_buf/O
|
|
net (fo=6484, routed) 0.961 -0.347 u_Axi_CDC/awFifo/popToPushGray_buffercc/cpu_clk
|
|
SLICE_X15Y69 FDCE r u_Axi_CDC/awFifo/popToPushGray_buffercc/buffers_0_reg[1]/C
|
|
clock pessimism 0.037 -0.310
|
|
SLICE_X15Y69 FDCE (Remov_fdce_C_CLR) -0.092 -0.402 u_Axi_CDC/awFifo/popToPushGray_buffercc/buffers_0_reg[1]
|
|
-------------------------------------------------------------------
|
|
required time 0.402
|
|
arrival time 0.978
|
|
-------------------------------------------------------------------
|
|
slack 1.381
|
|
|
|
Slack (MET) : 1.381ns (arrival time - required time)
|
|
Source: pll_clk.u_rst_cpu/delay_reg[1]/C
|
|
(rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns})
|
|
Destination: u_Axi_CDC/awFifo/popToPushGray_buffercc/buffers_0_reg[2]/CLR
|
|
(removal check against rising-edge clock cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns})
|
|
Path Group: **async_default**
|
|
Path Type: Removal (Min at Fast Process Corner)
|
|
Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns)
|
|
Data Path Delay: 1.443ns (logic 0.186ns (12.888%) route 1.257ns (87.112%))
|
|
Logic Levels: 1 (LUT1=1)
|
|
Clock Path Skew: 0.154ns (DCD - SCD - CPR)
|
|
Destination Clock Delay (DCD): -0.347ns
|
|
Source Clock Delay (SCD): -0.465ns
|
|
Clock Pessimism Removal (CPR): -0.037ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock cpu_clk rise edge) 0.000 0.000 r
|
|
K21 0.000 0.000 r clk (IN)
|
|
net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1
|
|
K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O
|
|
net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll
|
|
PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0)
|
|
-2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0
|
|
net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll
|
|
BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout1_buf/O
|
|
net (fo=6484, routed) 0.798 -0.465 pll_clk.u_rst_cpu/cpu_clk
|
|
SLICE_X0Y48 FDCE r pll_clk.u_rst_cpu/delay_reg[1]/C
|
|
------------------------------------------------------------------- -------------------
|
|
SLICE_X0Y48 FDCE (Prop_fdce_C_Q) 0.141 -0.324 r pll_clk.u_rst_cpu/delay_reg[1]/Q
|
|
net (fo=1, routed) 0.221 -0.103 pll_clk.u_rst_cpu/cpu_resetn
|
|
SLICE_X0Y48 LUT1 (Prop_lut1_I0_O) 0.045 -0.058 f pll_clk.u_rst_cpu/reset_i_1/O
|
|
net (fo=40, routed) 1.036 0.978 u_Axi_CDC/awFifo/popToPushGray_buffercc/p_0_in
|
|
SLICE_X15Y69 FDCE f u_Axi_CDC/awFifo/popToPushGray_buffercc/buffers_0_reg[2]/CLR
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock cpu_clk rise edge) 0.000 0.000 r
|
|
K21 0.000 0.000 r clk (IN)
|
|
net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1
|
|
K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O
|
|
net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll
|
|
PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0)
|
|
-2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0
|
|
net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll
|
|
BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout1_buf/O
|
|
net (fo=6484, routed) 0.961 -0.347 u_Axi_CDC/awFifo/popToPushGray_buffercc/cpu_clk
|
|
SLICE_X15Y69 FDCE r u_Axi_CDC/awFifo/popToPushGray_buffercc/buffers_0_reg[2]/C
|
|
clock pessimism 0.037 -0.310
|
|
SLICE_X15Y69 FDCE (Remov_fdce_C_CLR) -0.092 -0.402 u_Axi_CDC/awFifo/popToPushGray_buffercc/buffers_0_reg[2]
|
|
-------------------------------------------------------------------
|
|
required time 0.402
|
|
arrival time 0.978
|
|
-------------------------------------------------------------------
|
|
slack 1.381
|
|
|
|
Slack (MET) : 1.381ns (arrival time - required time)
|
|
Source: pll_clk.u_rst_cpu/delay_reg[1]/C
|
|
(rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns})
|
|
Destination: u_Axi_CDC/awFifo/popToPushGray_buffercc/buffers_1_reg[0]/CLR
|
|
(removal check against rising-edge clock cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns})
|
|
Path Group: **async_default**
|
|
Path Type: Removal (Min at Fast Process Corner)
|
|
Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns)
|
|
Data Path Delay: 1.443ns (logic 0.186ns (12.888%) route 1.257ns (87.112%))
|
|
Logic Levels: 1 (LUT1=1)
|
|
Clock Path Skew: 0.154ns (DCD - SCD - CPR)
|
|
Destination Clock Delay (DCD): -0.347ns
|
|
Source Clock Delay (SCD): -0.465ns
|
|
Clock Pessimism Removal (CPR): -0.037ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock cpu_clk rise edge) 0.000 0.000 r
|
|
K21 0.000 0.000 r clk (IN)
|
|
net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1
|
|
K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O
|
|
net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll
|
|
PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0)
|
|
-2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0
|
|
net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll
|
|
BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout1_buf/O
|
|
net (fo=6484, routed) 0.798 -0.465 pll_clk.u_rst_cpu/cpu_clk
|
|
SLICE_X0Y48 FDCE r pll_clk.u_rst_cpu/delay_reg[1]/C
|
|
------------------------------------------------------------------- -------------------
|
|
SLICE_X0Y48 FDCE (Prop_fdce_C_Q) 0.141 -0.324 r pll_clk.u_rst_cpu/delay_reg[1]/Q
|
|
net (fo=1, routed) 0.221 -0.103 pll_clk.u_rst_cpu/cpu_resetn
|
|
SLICE_X0Y48 LUT1 (Prop_lut1_I0_O) 0.045 -0.058 f pll_clk.u_rst_cpu/reset_i_1/O
|
|
net (fo=40, routed) 1.036 0.978 u_Axi_CDC/awFifo/popToPushGray_buffercc/p_0_in
|
|
SLICE_X15Y69 FDCE f u_Axi_CDC/awFifo/popToPushGray_buffercc/buffers_1_reg[0]/CLR
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock cpu_clk rise edge) 0.000 0.000 r
|
|
K21 0.000 0.000 r clk (IN)
|
|
net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1
|
|
K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O
|
|
net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll
|
|
PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0)
|
|
-2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0
|
|
net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll
|
|
BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout1_buf/O
|
|
net (fo=6484, routed) 0.961 -0.347 u_Axi_CDC/awFifo/popToPushGray_buffercc/cpu_clk
|
|
SLICE_X15Y69 FDCE r u_Axi_CDC/awFifo/popToPushGray_buffercc/buffers_1_reg[0]/C
|
|
clock pessimism 0.037 -0.310
|
|
SLICE_X15Y69 FDCE (Remov_fdce_C_CLR) -0.092 -0.402 u_Axi_CDC/awFifo/popToPushGray_buffercc/buffers_1_reg[0]
|
|
-------------------------------------------------------------------
|
|
required time 0.402
|
|
arrival time 0.978
|
|
-------------------------------------------------------------------
|
|
slack 1.381
|
|
|
|
|
|
|
|
|
|
|
|
---------------------------------------------------------------------------------------------------
|
|
Path Group: **async_default**
|
|
From Clock: mlkem_clk_clk_pll
|
|
To Clock: mlkem_clk_clk_pll
|
|
|
|
Setup : NA Failing Endpoints, Worst Slack NA , Total Violation NA
|
|
Hold : 0 Failing Endpoints, Worst Slack 0.613ns, Total Violation 0.000ns
|
|
---------------------------------------------------------------------------------------------------
|
|
|
|
|
|
Min Delay Paths
|
|
--------------------------------------------------------------------------------------
|
|
Slack (MET) : 0.613ns (arrival time - required time)
|
|
Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/buffers_1_reg/C
|
|
(rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns})
|
|
Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/popCC_popPtr_reg[2]/CLR
|
|
(removal check against rising-edge clock mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns})
|
|
Path Group: **async_default**
|
|
Path Type: Removal (Min at Fast Process Corner)
|
|
Requirement: 0.000ns (mlkem_clk_clk_pll rise@0.000ns - mlkem_clk_clk_pll rise@0.000ns)
|
|
Data Path Delay: 0.555ns (logic 0.227ns (40.925%) route 0.328ns (59.075%))
|
|
Logic Levels: 1 (LUT1=1)
|
|
Clock Path Skew: 0.034ns (DCD - SCD - CPR)
|
|
Destination Clock Delay (DCD): -0.355ns
|
|
Source Clock Delay (SCD): -0.581ns
|
|
Clock Pessimism Removal (CPR): 0.192ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock mlkem_clk_clk_pll rise edge)
|
|
0.000 0.000 r
|
|
K21 0.000 0.000 r clk (IN)
|
|
net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1
|
|
K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O
|
|
net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll
|
|
PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2)
|
|
-2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2
|
|
net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll
|
|
BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout3_buf/O
|
|
net (fo=26129, routed) 0.681 -0.581 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/mlkem_clk
|
|
SLICE_X25Y79 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/buffers_1_reg/C
|
|
------------------------------------------------------------------- -------------------
|
|
SLICE_X25Y79 FDCE (Prop_fdce_C_Q) 0.128 -0.453 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/buffers_1_reg/Q
|
|
net (fo=1, routed) 0.139 -0.314 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/buffers_1
|
|
SLICE_X25Y79 LUT1 (Prop_lut1_I0_O) 0.099 -0.215 f u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/popCC_popPtr[2]_i_2__1/O
|
|
net (fo=43, routed) 0.188 -0.027 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/buffers_0_reg[2]
|
|
SLICE_X28Y79 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/popCC_popPtr_reg[2]/CLR
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock mlkem_clk_clk_pll rise edge)
|
|
0.000 0.000 r
|
|
K21 0.000 0.000 r clk (IN)
|
|
net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1
|
|
K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O
|
|
net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll
|
|
PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2)
|
|
-2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2
|
|
net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll
|
|
BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout3_buf/O
|
|
net (fo=26129, routed) 0.953 -0.355 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/mlkem_clk
|
|
SLICE_X28Y79 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/popCC_popPtr_reg[2]/C
|
|
clock pessimism -0.192 -0.547
|
|
SLICE_X28Y79 FDCE (Remov_fdce_C_CLR) -0.092 -0.639 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/popCC_popPtr_reg[2]
|
|
-------------------------------------------------------------------
|
|
required time 0.639
|
|
arrival time -0.027
|
|
-------------------------------------------------------------------
|
|
slack 0.613
|
|
|
|
Slack (MET) : 0.613ns (arrival time - required time)
|
|
Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/buffers_1_reg/C
|
|
(rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns})
|
|
Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/popCC_ptrToPush_reg[1]/CLR
|
|
(removal check against rising-edge clock mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns})
|
|
Path Group: **async_default**
|
|
Path Type: Removal (Min at Fast Process Corner)
|
|
Requirement: 0.000ns (mlkem_clk_clk_pll rise@0.000ns - mlkem_clk_clk_pll rise@0.000ns)
|
|
Data Path Delay: 0.555ns (logic 0.227ns (40.925%) route 0.328ns (59.075%))
|
|
Logic Levels: 1 (LUT1=1)
|
|
Clock Path Skew: 0.034ns (DCD - SCD - CPR)
|
|
Destination Clock Delay (DCD): -0.355ns
|
|
Source Clock Delay (SCD): -0.581ns
|
|
Clock Pessimism Removal (CPR): 0.192ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock mlkem_clk_clk_pll rise edge)
|
|
0.000 0.000 r
|
|
K21 0.000 0.000 r clk (IN)
|
|
net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1
|
|
K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O
|
|
net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll
|
|
PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2)
|
|
-2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2
|
|
net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll
|
|
BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout3_buf/O
|
|
net (fo=26129, routed) 0.681 -0.581 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/mlkem_clk
|
|
SLICE_X25Y79 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/buffers_1_reg/C
|
|
------------------------------------------------------------------- -------------------
|
|
SLICE_X25Y79 FDCE (Prop_fdce_C_Q) 0.128 -0.453 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/buffers_1_reg/Q
|
|
net (fo=1, routed) 0.139 -0.314 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/buffers_1
|
|
SLICE_X25Y79 LUT1 (Prop_lut1_I0_O) 0.099 -0.215 f u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/popCC_popPtr[2]_i_2__1/O
|
|
net (fo=43, routed) 0.188 -0.027 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/buffers_0_reg[2]
|
|
SLICE_X28Y79 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/popCC_ptrToPush_reg[1]/CLR
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock mlkem_clk_clk_pll rise edge)
|
|
0.000 0.000 r
|
|
K21 0.000 0.000 r clk (IN)
|
|
net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1
|
|
K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O
|
|
net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll
|
|
PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2)
|
|
-2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2
|
|
net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll
|
|
BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout3_buf/O
|
|
net (fo=26129, routed) 0.953 -0.355 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/mlkem_clk
|
|
SLICE_X28Y79 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/popCC_ptrToPush_reg[1]/C
|
|
clock pessimism -0.192 -0.547
|
|
SLICE_X28Y79 FDCE (Remov_fdce_C_CLR) -0.092 -0.639 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/popCC_ptrToPush_reg[1]
|
|
-------------------------------------------------------------------
|
|
required time 0.639
|
|
arrival time -0.027
|
|
-------------------------------------------------------------------
|
|
slack 0.613
|
|
|
|
Slack (MET) : 0.613ns (arrival time - required time)
|
|
Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/buffers_1_reg/C
|
|
(rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns})
|
|
Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/popCC_ptrToPush_reg[2]/CLR
|
|
(removal check against rising-edge clock mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns})
|
|
Path Group: **async_default**
|
|
Path Type: Removal (Min at Fast Process Corner)
|
|
Requirement: 0.000ns (mlkem_clk_clk_pll rise@0.000ns - mlkem_clk_clk_pll rise@0.000ns)
|
|
Data Path Delay: 0.555ns (logic 0.227ns (40.925%) route 0.328ns (59.075%))
|
|
Logic Levels: 1 (LUT1=1)
|
|
Clock Path Skew: 0.034ns (DCD - SCD - CPR)
|
|
Destination Clock Delay (DCD): -0.355ns
|
|
Source Clock Delay (SCD): -0.581ns
|
|
Clock Pessimism Removal (CPR): 0.192ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock mlkem_clk_clk_pll rise edge)
|
|
0.000 0.000 r
|
|
K21 0.000 0.000 r clk (IN)
|
|
net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1
|
|
K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O
|
|
net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll
|
|
PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2)
|
|
-2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2
|
|
net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll
|
|
BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout3_buf/O
|
|
net (fo=26129, routed) 0.681 -0.581 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/mlkem_clk
|
|
SLICE_X25Y79 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/buffers_1_reg/C
|
|
------------------------------------------------------------------- -------------------
|
|
SLICE_X25Y79 FDCE (Prop_fdce_C_Q) 0.128 -0.453 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/buffers_1_reg/Q
|
|
net (fo=1, routed) 0.139 -0.314 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/buffers_1
|
|
SLICE_X25Y79 LUT1 (Prop_lut1_I0_O) 0.099 -0.215 f u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/popCC_popPtr[2]_i_2__1/O
|
|
net (fo=43, routed) 0.188 -0.027 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/buffers_0_reg[2]
|
|
SLICE_X28Y79 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/popCC_ptrToPush_reg[2]/CLR
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock mlkem_clk_clk_pll rise edge)
|
|
0.000 0.000 r
|
|
K21 0.000 0.000 r clk (IN)
|
|
net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1
|
|
K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O
|
|
net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll
|
|
PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2)
|
|
-2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2
|
|
net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll
|
|
BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout3_buf/O
|
|
net (fo=26129, routed) 0.953 -0.355 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/mlkem_clk
|
|
SLICE_X28Y79 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/popCC_ptrToPush_reg[2]/C
|
|
clock pessimism -0.192 -0.547
|
|
SLICE_X28Y79 FDCE (Remov_fdce_C_CLR) -0.092 -0.639 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/popCC_ptrToPush_reg[2]
|
|
-------------------------------------------------------------------
|
|
required time 0.639
|
|
arrival time -0.027
|
|
-------------------------------------------------------------------
|
|
slack 0.613
|
|
|
|
Slack (MET) : 0.629ns (arrival time - required time)
|
|
Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/buffers_1_reg/C
|
|
(rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns})
|
|
Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/pushToPopGray_buffercc/buffers_0_reg[0]/CLR
|
|
(removal check against rising-edge clock mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns})
|
|
Path Group: **async_default**
|
|
Path Type: Removal (Min at Fast Process Corner)
|
|
Requirement: 0.000ns (mlkem_clk_clk_pll rise@0.000ns - mlkem_clk_clk_pll rise@0.000ns)
|
|
Data Path Delay: 0.551ns (logic 0.227ns (41.209%) route 0.324ns (58.791%))
|
|
Logic Levels: 1 (LUT1=1)
|
|
Clock Path Skew: 0.014ns (DCD - SCD - CPR)
|
|
Destination Clock Delay (DCD): -0.353ns
|
|
Source Clock Delay (SCD): -0.581ns
|
|
Clock Pessimism Removal (CPR): 0.214ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock mlkem_clk_clk_pll rise edge)
|
|
0.000 0.000 r
|
|
K21 0.000 0.000 r clk (IN)
|
|
net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1
|
|
K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O
|
|
net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll
|
|
PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2)
|
|
-2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2
|
|
net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll
|
|
BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout3_buf/O
|
|
net (fo=26129, routed) 0.681 -0.581 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/mlkem_clk
|
|
SLICE_X25Y79 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/buffers_1_reg/C
|
|
------------------------------------------------------------------- -------------------
|
|
SLICE_X25Y79 FDCE (Prop_fdce_C_Q) 0.128 -0.453 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/buffers_1_reg/Q
|
|
net (fo=1, routed) 0.139 -0.314 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/buffers_1
|
|
SLICE_X25Y79 LUT1 (Prop_lut1_I0_O) 0.099 -0.215 f u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/popCC_popPtr[2]_i_2__1/O
|
|
net (fo=43, routed) 0.184 -0.031 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/pushToPopGray_buffercc/buffers_0_reg[2]_1
|
|
SLICE_X27Y79 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/pushToPopGray_buffercc/buffers_0_reg[0]/CLR
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock mlkem_clk_clk_pll rise edge)
|
|
0.000 0.000 r
|
|
K21 0.000 0.000 r clk (IN)
|
|
net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1
|
|
K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O
|
|
net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll
|
|
PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2)
|
|
-2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2
|
|
net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll
|
|
BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout3_buf/O
|
|
net (fo=26129, routed) 0.955 -0.353 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/pushToPopGray_buffercc/mlkem_clk
|
|
SLICE_X27Y79 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/pushToPopGray_buffercc/buffers_0_reg[0]/C
|
|
clock pessimism -0.214 -0.567
|
|
SLICE_X27Y79 FDCE (Remov_fdce_C_CLR) -0.092 -0.659 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/pushToPopGray_buffercc/buffers_0_reg[0]
|
|
-------------------------------------------------------------------
|
|
required time 0.659
|
|
arrival time -0.031
|
|
-------------------------------------------------------------------
|
|
slack 0.629
|
|
|
|
Slack (MET) : 0.629ns (arrival time - required time)
|
|
Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/buffers_1_reg/C
|
|
(rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns})
|
|
Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/pushToPopGray_buffercc/buffers_0_reg[1]/CLR
|
|
(removal check against rising-edge clock mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns})
|
|
Path Group: **async_default**
|
|
Path Type: Removal (Min at Fast Process Corner)
|
|
Requirement: 0.000ns (mlkem_clk_clk_pll rise@0.000ns - mlkem_clk_clk_pll rise@0.000ns)
|
|
Data Path Delay: 0.551ns (logic 0.227ns (41.209%) route 0.324ns (58.791%))
|
|
Logic Levels: 1 (LUT1=1)
|
|
Clock Path Skew: 0.014ns (DCD - SCD - CPR)
|
|
Destination Clock Delay (DCD): -0.353ns
|
|
Source Clock Delay (SCD): -0.581ns
|
|
Clock Pessimism Removal (CPR): 0.214ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock mlkem_clk_clk_pll rise edge)
|
|
0.000 0.000 r
|
|
K21 0.000 0.000 r clk (IN)
|
|
net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1
|
|
K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O
|
|
net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll
|
|
PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2)
|
|
-2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2
|
|
net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll
|
|
BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout3_buf/O
|
|
net (fo=26129, routed) 0.681 -0.581 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/mlkem_clk
|
|
SLICE_X25Y79 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/buffers_1_reg/C
|
|
------------------------------------------------------------------- -------------------
|
|
SLICE_X25Y79 FDCE (Prop_fdce_C_Q) 0.128 -0.453 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/buffers_1_reg/Q
|
|
net (fo=1, routed) 0.139 -0.314 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/buffers_1
|
|
SLICE_X25Y79 LUT1 (Prop_lut1_I0_O) 0.099 -0.215 f u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/popCC_popPtr[2]_i_2__1/O
|
|
net (fo=43, routed) 0.184 -0.031 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/pushToPopGray_buffercc/buffers_0_reg[2]_1
|
|
SLICE_X27Y79 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/pushToPopGray_buffercc/buffers_0_reg[1]/CLR
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock mlkem_clk_clk_pll rise edge)
|
|
0.000 0.000 r
|
|
K21 0.000 0.000 r clk (IN)
|
|
net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1
|
|
K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O
|
|
net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll
|
|
PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2)
|
|
-2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2
|
|
net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll
|
|
BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout3_buf/O
|
|
net (fo=26129, routed) 0.955 -0.353 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/pushToPopGray_buffercc/mlkem_clk
|
|
SLICE_X27Y79 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/pushToPopGray_buffercc/buffers_0_reg[1]/C
|
|
clock pessimism -0.214 -0.567
|
|
SLICE_X27Y79 FDCE (Remov_fdce_C_CLR) -0.092 -0.659 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/pushToPopGray_buffercc/buffers_0_reg[1]
|
|
-------------------------------------------------------------------
|
|
required time 0.659
|
|
arrival time -0.031
|
|
-------------------------------------------------------------------
|
|
slack 0.629
|
|
|
|
Slack (MET) : 0.629ns (arrival time - required time)
|
|
Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/buffers_1_reg/C
|
|
(rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns})
|
|
Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/pushToPopGray_buffercc/buffers_0_reg[2]/CLR
|
|
(removal check against rising-edge clock mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns})
|
|
Path Group: **async_default**
|
|
Path Type: Removal (Min at Fast Process Corner)
|
|
Requirement: 0.000ns (mlkem_clk_clk_pll rise@0.000ns - mlkem_clk_clk_pll rise@0.000ns)
|
|
Data Path Delay: 0.551ns (logic 0.227ns (41.209%) route 0.324ns (58.791%))
|
|
Logic Levels: 1 (LUT1=1)
|
|
Clock Path Skew: 0.014ns (DCD - SCD - CPR)
|
|
Destination Clock Delay (DCD): -0.353ns
|
|
Source Clock Delay (SCD): -0.581ns
|
|
Clock Pessimism Removal (CPR): 0.214ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock mlkem_clk_clk_pll rise edge)
|
|
0.000 0.000 r
|
|
K21 0.000 0.000 r clk (IN)
|
|
net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1
|
|
K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O
|
|
net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll
|
|
PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2)
|
|
-2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2
|
|
net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll
|
|
BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout3_buf/O
|
|
net (fo=26129, routed) 0.681 -0.581 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/mlkem_clk
|
|
SLICE_X25Y79 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/buffers_1_reg/C
|
|
------------------------------------------------------------------- -------------------
|
|
SLICE_X25Y79 FDCE (Prop_fdce_C_Q) 0.128 -0.453 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/buffers_1_reg/Q
|
|
net (fo=1, routed) 0.139 -0.314 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/buffers_1
|
|
SLICE_X25Y79 LUT1 (Prop_lut1_I0_O) 0.099 -0.215 f u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/popCC_popPtr[2]_i_2__1/O
|
|
net (fo=43, routed) 0.184 -0.031 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/pushToPopGray_buffercc/buffers_0_reg[2]_1
|
|
SLICE_X27Y79 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/pushToPopGray_buffercc/buffers_0_reg[2]/CLR
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock mlkem_clk_clk_pll rise edge)
|
|
0.000 0.000 r
|
|
K21 0.000 0.000 r clk (IN)
|
|
net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1
|
|
K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O
|
|
net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll
|
|
PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2)
|
|
-2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2
|
|
net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll
|
|
BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout3_buf/O
|
|
net (fo=26129, routed) 0.955 -0.353 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/pushToPopGray_buffercc/mlkem_clk
|
|
SLICE_X27Y79 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/pushToPopGray_buffercc/buffers_0_reg[2]/C
|
|
clock pessimism -0.214 -0.567
|
|
SLICE_X27Y79 FDCE (Remov_fdce_C_CLR) -0.092 -0.659 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/pushToPopGray_buffercc/buffers_0_reg[2]
|
|
-------------------------------------------------------------------
|
|
required time 0.659
|
|
arrival time -0.031
|
|
-------------------------------------------------------------------
|
|
slack 0.629
|
|
|
|
Slack (MET) : 0.629ns (arrival time - required time)
|
|
Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/buffers_1_reg/C
|
|
(rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns})
|
|
Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/pushToPopGray_buffercc/buffers_1_reg[0]/CLR
|
|
(removal check against rising-edge clock mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns})
|
|
Path Group: **async_default**
|
|
Path Type: Removal (Min at Fast Process Corner)
|
|
Requirement: 0.000ns (mlkem_clk_clk_pll rise@0.000ns - mlkem_clk_clk_pll rise@0.000ns)
|
|
Data Path Delay: 0.551ns (logic 0.227ns (41.209%) route 0.324ns (58.791%))
|
|
Logic Levels: 1 (LUT1=1)
|
|
Clock Path Skew: 0.014ns (DCD - SCD - CPR)
|
|
Destination Clock Delay (DCD): -0.353ns
|
|
Source Clock Delay (SCD): -0.581ns
|
|
Clock Pessimism Removal (CPR): 0.214ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock mlkem_clk_clk_pll rise edge)
|
|
0.000 0.000 r
|
|
K21 0.000 0.000 r clk (IN)
|
|
net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1
|
|
K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O
|
|
net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll
|
|
PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2)
|
|
-2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2
|
|
net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll
|
|
BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout3_buf/O
|
|
net (fo=26129, routed) 0.681 -0.581 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/mlkem_clk
|
|
SLICE_X25Y79 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/buffers_1_reg/C
|
|
------------------------------------------------------------------- -------------------
|
|
SLICE_X25Y79 FDCE (Prop_fdce_C_Q) 0.128 -0.453 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/buffers_1_reg/Q
|
|
net (fo=1, routed) 0.139 -0.314 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/buffers_1
|
|
SLICE_X25Y79 LUT1 (Prop_lut1_I0_O) 0.099 -0.215 f u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/popCC_popPtr[2]_i_2__1/O
|
|
net (fo=43, routed) 0.184 -0.031 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/pushToPopGray_buffercc/buffers_0_reg[2]_1
|
|
SLICE_X27Y79 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/pushToPopGray_buffercc/buffers_1_reg[0]/CLR
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock mlkem_clk_clk_pll rise edge)
|
|
0.000 0.000 r
|
|
K21 0.000 0.000 r clk (IN)
|
|
net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1
|
|
K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O
|
|
net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll
|
|
PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2)
|
|
-2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2
|
|
net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll
|
|
BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout3_buf/O
|
|
net (fo=26129, routed) 0.955 -0.353 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/pushToPopGray_buffercc/mlkem_clk
|
|
SLICE_X27Y79 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/pushToPopGray_buffercc/buffers_1_reg[0]/C
|
|
clock pessimism -0.214 -0.567
|
|
SLICE_X27Y79 FDCE (Remov_fdce_C_CLR) -0.092 -0.659 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/pushToPopGray_buffercc/buffers_1_reg[0]
|
|
-------------------------------------------------------------------
|
|
required time 0.659
|
|
arrival time -0.031
|
|
-------------------------------------------------------------------
|
|
slack 0.629
|
|
|
|
Slack (MET) : 0.629ns (arrival time - required time)
|
|
Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/buffers_1_reg/C
|
|
(rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns})
|
|
Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/pushToPopGray_buffercc/buffers_1_reg[1]/CLR
|
|
(removal check against rising-edge clock mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns})
|
|
Path Group: **async_default**
|
|
Path Type: Removal (Min at Fast Process Corner)
|
|
Requirement: 0.000ns (mlkem_clk_clk_pll rise@0.000ns - mlkem_clk_clk_pll rise@0.000ns)
|
|
Data Path Delay: 0.551ns (logic 0.227ns (41.209%) route 0.324ns (58.791%))
|
|
Logic Levels: 1 (LUT1=1)
|
|
Clock Path Skew: 0.014ns (DCD - SCD - CPR)
|
|
Destination Clock Delay (DCD): -0.353ns
|
|
Source Clock Delay (SCD): -0.581ns
|
|
Clock Pessimism Removal (CPR): 0.214ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock mlkem_clk_clk_pll rise edge)
|
|
0.000 0.000 r
|
|
K21 0.000 0.000 r clk (IN)
|
|
net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1
|
|
K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O
|
|
net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll
|
|
PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2)
|
|
-2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2
|
|
net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll
|
|
BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout3_buf/O
|
|
net (fo=26129, routed) 0.681 -0.581 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/mlkem_clk
|
|
SLICE_X25Y79 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/buffers_1_reg/C
|
|
------------------------------------------------------------------- -------------------
|
|
SLICE_X25Y79 FDCE (Prop_fdce_C_Q) 0.128 -0.453 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/buffers_1_reg/Q
|
|
net (fo=1, routed) 0.139 -0.314 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/buffers_1
|
|
SLICE_X25Y79 LUT1 (Prop_lut1_I0_O) 0.099 -0.215 f u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/popCC_popPtr[2]_i_2__1/O
|
|
net (fo=43, routed) 0.184 -0.031 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/pushToPopGray_buffercc/buffers_0_reg[2]_1
|
|
SLICE_X27Y79 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/pushToPopGray_buffercc/buffers_1_reg[1]/CLR
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock mlkem_clk_clk_pll rise edge)
|
|
0.000 0.000 r
|
|
K21 0.000 0.000 r clk (IN)
|
|
net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1
|
|
K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O
|
|
net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll
|
|
PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2)
|
|
-2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2
|
|
net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll
|
|
BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout3_buf/O
|
|
net (fo=26129, routed) 0.955 -0.353 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/pushToPopGray_buffercc/mlkem_clk
|
|
SLICE_X27Y79 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/pushToPopGray_buffercc/buffers_1_reg[1]/C
|
|
clock pessimism -0.214 -0.567
|
|
SLICE_X27Y79 FDCE (Remov_fdce_C_CLR) -0.092 -0.659 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/pushToPopGray_buffercc/buffers_1_reg[1]
|
|
-------------------------------------------------------------------
|
|
required time 0.659
|
|
arrival time -0.031
|
|
-------------------------------------------------------------------
|
|
slack 0.629
|
|
|
|
Slack (MET) : 0.629ns (arrival time - required time)
|
|
Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/buffers_1_reg/C
|
|
(rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns})
|
|
Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/pushToPopGray_buffercc/buffers_1_reg[2]/CLR
|
|
(removal check against rising-edge clock mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns})
|
|
Path Group: **async_default**
|
|
Path Type: Removal (Min at Fast Process Corner)
|
|
Requirement: 0.000ns (mlkem_clk_clk_pll rise@0.000ns - mlkem_clk_clk_pll rise@0.000ns)
|
|
Data Path Delay: 0.551ns (logic 0.227ns (41.209%) route 0.324ns (58.791%))
|
|
Logic Levels: 1 (LUT1=1)
|
|
Clock Path Skew: 0.014ns (DCD - SCD - CPR)
|
|
Destination Clock Delay (DCD): -0.353ns
|
|
Source Clock Delay (SCD): -0.581ns
|
|
Clock Pessimism Removal (CPR): 0.214ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock mlkem_clk_clk_pll rise edge)
|
|
0.000 0.000 r
|
|
K21 0.000 0.000 r clk (IN)
|
|
net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1
|
|
K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O
|
|
net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll
|
|
PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2)
|
|
-2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2
|
|
net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll
|
|
BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout3_buf/O
|
|
net (fo=26129, routed) 0.681 -0.581 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/mlkem_clk
|
|
SLICE_X25Y79 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/buffers_1_reg/C
|
|
------------------------------------------------------------------- -------------------
|
|
SLICE_X25Y79 FDCE (Prop_fdce_C_Q) 0.128 -0.453 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/buffers_1_reg/Q
|
|
net (fo=1, routed) 0.139 -0.314 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/buffers_1
|
|
SLICE_X25Y79 LUT1 (Prop_lut1_I0_O) 0.099 -0.215 f u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/popCC_popPtr[2]_i_2__1/O
|
|
net (fo=43, routed) 0.184 -0.031 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/pushToPopGray_buffercc/buffers_0_reg[2]_1
|
|
SLICE_X27Y79 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/pushToPopGray_buffercc/buffers_1_reg[2]/CLR
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock mlkem_clk_clk_pll rise edge)
|
|
0.000 0.000 r
|
|
K21 0.000 0.000 r clk (IN)
|
|
net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1
|
|
K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O
|
|
net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll
|
|
PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2)
|
|
-2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2
|
|
net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll
|
|
BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout3_buf/O
|
|
net (fo=26129, routed) 0.955 -0.353 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/pushToPopGray_buffercc/mlkem_clk
|
|
SLICE_X27Y79 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/pushToPopGray_buffercc/buffers_1_reg[2]/C
|
|
clock pessimism -0.214 -0.567
|
|
SLICE_X27Y79 FDCE (Remov_fdce_C_CLR) -0.092 -0.659 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/pushToPopGray_buffercc/buffers_1_reg[2]
|
|
-------------------------------------------------------------------
|
|
required time 0.659
|
|
arrival time -0.031
|
|
-------------------------------------------------------------------
|
|
slack 0.629
|
|
|
|
Slack (MET) : 0.728ns (arrival time - required time)
|
|
Source: pll_clk.u_rst_mlkem/delay_reg[1]/C
|
|
(rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns})
|
|
Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/stream_wdata_reg[14]/CLR
|
|
(removal check against rising-edge clock mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns})
|
|
Path Group: **async_default**
|
|
Path Type: Removal (Min at Fast Process Corner)
|
|
Requirement: 0.000ns (mlkem_clk_clk_pll rise@0.000ns - mlkem_clk_clk_pll rise@0.000ns)
|
|
Data Path Delay: 0.695ns (logic 0.186ns (26.771%) route 0.509ns (73.229%))
|
|
Logic Levels: 1 (LUT1=1)
|
|
Clock Path Skew: 0.034ns (DCD - SCD - CPR)
|
|
Destination Clock Delay (DCD): -0.381ns
|
|
Source Clock Delay (SCD): -0.607ns
|
|
Clock Pessimism Removal (CPR): 0.192ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock mlkem_clk_clk_pll rise edge)
|
|
0.000 0.000 r
|
|
K21 0.000 0.000 r clk (IN)
|
|
net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1
|
|
K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O
|
|
net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll
|
|
PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2)
|
|
-2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2
|
|
net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll
|
|
BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout3_buf/O
|
|
net (fo=26129, routed) 0.655 -0.607 pll_clk.u_rst_mlkem/mlkem_clk
|
|
SLICE_X118Y67 FDCE r pll_clk.u_rst_mlkem/delay_reg[1]/C
|
|
------------------------------------------------------------------- -------------------
|
|
SLICE_X118Y67 FDCE (Prop_fdce_C_Q) 0.141 -0.466 r pll_clk.u_rst_mlkem/delay_reg[1]/Q
|
|
net (fo=4, routed) 0.297 -0.169 pll_clk.u_rst_mlkem/Q[0]
|
|
SLICE_X118Y67 LUT1 (Prop_lut1_I0_O) 0.045 -0.124 f pll_clk.u_rst_mlkem/rdb_addr[11]_i_2/O
|
|
net (fo=1069, routed) 0.211 0.087 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/pre_addr_l_reg[2]_rep__1_0
|
|
SLICE_X120Y68 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/stream_wdata_reg[14]/CLR
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock mlkem_clk_clk_pll rise edge)
|
|
0.000 0.000 r
|
|
K21 0.000 0.000 r clk (IN)
|
|
net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1
|
|
K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O
|
|
net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll
|
|
PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2)
|
|
-2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2
|
|
net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll
|
|
BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout3_buf/O
|
|
net (fo=26129, routed) 0.927 -0.381 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/mlkem_clk
|
|
SLICE_X120Y68 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/stream_wdata_reg[14]/C
|
|
clock pessimism -0.192 -0.573
|
|
SLICE_X120Y68 FDCE (Remov_fdce_C_CLR) -0.067 -0.640 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/stream_wdata_reg[14]
|
|
-------------------------------------------------------------------
|
|
required time 0.640
|
|
arrival time 0.087
|
|
-------------------------------------------------------------------
|
|
slack 0.728
|
|
|
|
Slack (MET) : 0.728ns (arrival time - required time)
|
|
Source: pll_clk.u_rst_mlkem/delay_reg[1]/C
|
|
(rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns})
|
|
Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/stream_wdata_reg[22]/CLR
|
|
(removal check against rising-edge clock mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns})
|
|
Path Group: **async_default**
|
|
Path Type: Removal (Min at Fast Process Corner)
|
|
Requirement: 0.000ns (mlkem_clk_clk_pll rise@0.000ns - mlkem_clk_clk_pll rise@0.000ns)
|
|
Data Path Delay: 0.695ns (logic 0.186ns (26.771%) route 0.509ns (73.229%))
|
|
Logic Levels: 1 (LUT1=1)
|
|
Clock Path Skew: 0.034ns (DCD - SCD - CPR)
|
|
Destination Clock Delay (DCD): -0.381ns
|
|
Source Clock Delay (SCD): -0.607ns
|
|
Clock Pessimism Removal (CPR): 0.192ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock mlkem_clk_clk_pll rise edge)
|
|
0.000 0.000 r
|
|
K21 0.000 0.000 r clk (IN)
|
|
net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1
|
|
K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O
|
|
net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll
|
|
PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2)
|
|
-2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2
|
|
net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll
|
|
BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout3_buf/O
|
|
net (fo=26129, routed) 0.655 -0.607 pll_clk.u_rst_mlkem/mlkem_clk
|
|
SLICE_X118Y67 FDCE r pll_clk.u_rst_mlkem/delay_reg[1]/C
|
|
------------------------------------------------------------------- -------------------
|
|
SLICE_X118Y67 FDCE (Prop_fdce_C_Q) 0.141 -0.466 r pll_clk.u_rst_mlkem/delay_reg[1]/Q
|
|
net (fo=4, routed) 0.297 -0.169 pll_clk.u_rst_mlkem/Q[0]
|
|
SLICE_X118Y67 LUT1 (Prop_lut1_I0_O) 0.045 -0.124 f pll_clk.u_rst_mlkem/rdb_addr[11]_i_2/O
|
|
net (fo=1069, routed) 0.211 0.087 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/pre_addr_l_reg[2]_rep__1_0
|
|
SLICE_X120Y68 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/stream_wdata_reg[22]/CLR
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock mlkem_clk_clk_pll rise edge)
|
|
0.000 0.000 r
|
|
K21 0.000 0.000 r clk (IN)
|
|
net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1
|
|
K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O
|
|
net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll
|
|
PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2)
|
|
-2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2
|
|
net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll
|
|
BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout3_buf/O
|
|
net (fo=26129, routed) 0.927 -0.381 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/mlkem_clk
|
|
SLICE_X120Y68 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/stream_wdata_reg[22]/C
|
|
clock pessimism -0.192 -0.573
|
|
SLICE_X120Y68 FDCE (Remov_fdce_C_CLR) -0.067 -0.640 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/stream_wdata_reg[22]
|
|
-------------------------------------------------------------------
|
|
required time 0.640
|
|
arrival time 0.087
|
|
-------------------------------------------------------------------
|
|
slack 0.728
|
|
|
|
Slack (MET) : 0.728ns (arrival time - required time)
|
|
Source: pll_clk.u_rst_mlkem/delay_reg[1]/C
|
|
(rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns})
|
|
Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/stream_wdata_reg[6]/CLR
|
|
(removal check against rising-edge clock mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns})
|
|
Path Group: **async_default**
|
|
Path Type: Removal (Min at Fast Process Corner)
|
|
Requirement: 0.000ns (mlkem_clk_clk_pll rise@0.000ns - mlkem_clk_clk_pll rise@0.000ns)
|
|
Data Path Delay: 0.695ns (logic 0.186ns (26.771%) route 0.509ns (73.229%))
|
|
Logic Levels: 1 (LUT1=1)
|
|
Clock Path Skew: 0.034ns (DCD - SCD - CPR)
|
|
Destination Clock Delay (DCD): -0.381ns
|
|
Source Clock Delay (SCD): -0.607ns
|
|
Clock Pessimism Removal (CPR): 0.192ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock mlkem_clk_clk_pll rise edge)
|
|
0.000 0.000 r
|
|
K21 0.000 0.000 r clk (IN)
|
|
net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1
|
|
K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O
|
|
net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll
|
|
PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2)
|
|
-2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2
|
|
net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll
|
|
BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout3_buf/O
|
|
net (fo=26129, routed) 0.655 -0.607 pll_clk.u_rst_mlkem/mlkem_clk
|
|
SLICE_X118Y67 FDCE r pll_clk.u_rst_mlkem/delay_reg[1]/C
|
|
------------------------------------------------------------------- -------------------
|
|
SLICE_X118Y67 FDCE (Prop_fdce_C_Q) 0.141 -0.466 r pll_clk.u_rst_mlkem/delay_reg[1]/Q
|
|
net (fo=4, routed) 0.297 -0.169 pll_clk.u_rst_mlkem/Q[0]
|
|
SLICE_X118Y67 LUT1 (Prop_lut1_I0_O) 0.045 -0.124 f pll_clk.u_rst_mlkem/rdb_addr[11]_i_2/O
|
|
net (fo=1069, routed) 0.211 0.087 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/pre_addr_l_reg[2]_rep__1_0
|
|
SLICE_X120Y68 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/stream_wdata_reg[6]/CLR
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock mlkem_clk_clk_pll rise edge)
|
|
0.000 0.000 r
|
|
K21 0.000 0.000 r clk (IN)
|
|
net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1
|
|
K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O
|
|
net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll
|
|
PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2)
|
|
-2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2
|
|
net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll
|
|
BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout3_buf/O
|
|
net (fo=26129, routed) 0.927 -0.381 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/mlkem_clk
|
|
SLICE_X120Y68 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/stream_wdata_reg[6]/C
|
|
clock pessimism -0.192 -0.573
|
|
SLICE_X120Y68 FDCE (Remov_fdce_C_CLR) -0.067 -0.640 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/stream_wdata_reg[6]
|
|
-------------------------------------------------------------------
|
|
required time 0.640
|
|
arrival time 0.087
|
|
-------------------------------------------------------------------
|
|
slack 0.728
|
|
|
|
Slack (MET) : 0.741ns (arrival time - required time)
|
|
Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/buffers_1_reg/C
|
|
(rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns})
|
|
Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/popCC_addressGen_rValid_reg/CLR
|
|
(removal check against rising-edge clock mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns})
|
|
Path Group: **async_default**
|
|
Path Type: Removal (Min at Fast Process Corner)
|
|
Requirement: 0.000ns (mlkem_clk_clk_pll rise@0.000ns - mlkem_clk_clk_pll rise@0.000ns)
|
|
Data Path Delay: 0.682ns (logic 0.227ns (33.271%) route 0.455ns (66.729%))
|
|
Logic Levels: 1 (LUT1=1)
|
|
Clock Path Skew: 0.033ns (DCD - SCD - CPR)
|
|
Destination Clock Delay (DCD): -0.356ns
|
|
Source Clock Delay (SCD): -0.581ns
|
|
Clock Pessimism Removal (CPR): 0.192ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock mlkem_clk_clk_pll rise edge)
|
|
0.000 0.000 r
|
|
K21 0.000 0.000 r clk (IN)
|
|
net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1
|
|
K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O
|
|
net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll
|
|
PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2)
|
|
-2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2
|
|
net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll
|
|
BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout3_buf/O
|
|
net (fo=26129, routed) 0.681 -0.581 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/mlkem_clk
|
|
SLICE_X25Y79 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/buffers_1_reg/C
|
|
------------------------------------------------------------------- -------------------
|
|
SLICE_X25Y79 FDCE (Prop_fdce_C_Q) 0.128 -0.453 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/buffers_1_reg/Q
|
|
net (fo=1, routed) 0.139 -0.314 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/buffers_1
|
|
SLICE_X25Y79 LUT1 (Prop_lut1_I0_O) 0.099 -0.215 f u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/popCC_popPtr[2]_i_2__1/O
|
|
net (fo=43, routed) 0.316 0.101 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/buffers_0_reg[2]
|
|
SLICE_X30Y78 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/popCC_addressGen_rValid_reg/CLR
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock mlkem_clk_clk_pll rise edge)
|
|
0.000 0.000 r
|
|
K21 0.000 0.000 r clk (IN)
|
|
net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1
|
|
K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O
|
|
net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll
|
|
PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2)
|
|
-2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2
|
|
net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll
|
|
BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout3_buf/O
|
|
net (fo=26129, routed) 0.952 -0.356 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/mlkem_clk
|
|
SLICE_X30Y78 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/popCC_addressGen_rValid_reg/C
|
|
clock pessimism -0.192 -0.548
|
|
SLICE_X30Y78 FDCE (Remov_fdce_C_CLR) -0.092 -0.640 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/popCC_addressGen_rValid_reg
|
|
-------------------------------------------------------------------
|
|
required time 0.640
|
|
arrival time 0.101
|
|
-------------------------------------------------------------------
|
|
slack 0.741
|
|
|
|
Slack (MET) : 0.741ns (arrival time - required time)
|
|
Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/buffers_1_reg/C
|
|
(rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns})
|
|
Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/popCC_popPtr_reg[0]/CLR
|
|
(removal check against rising-edge clock mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns})
|
|
Path Group: **async_default**
|
|
Path Type: Removal (Min at Fast Process Corner)
|
|
Requirement: 0.000ns (mlkem_clk_clk_pll rise@0.000ns - mlkem_clk_clk_pll rise@0.000ns)
|
|
Data Path Delay: 0.682ns (logic 0.227ns (33.271%) route 0.455ns (66.729%))
|
|
Logic Levels: 1 (LUT1=1)
|
|
Clock Path Skew: 0.033ns (DCD - SCD - CPR)
|
|
Destination Clock Delay (DCD): -0.356ns
|
|
Source Clock Delay (SCD): -0.581ns
|
|
Clock Pessimism Removal (CPR): 0.192ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock mlkem_clk_clk_pll rise edge)
|
|
0.000 0.000 r
|
|
K21 0.000 0.000 r clk (IN)
|
|
net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1
|
|
K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O
|
|
net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll
|
|
PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2)
|
|
-2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2
|
|
net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll
|
|
BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout3_buf/O
|
|
net (fo=26129, routed) 0.681 -0.581 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/mlkem_clk
|
|
SLICE_X25Y79 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/buffers_1_reg/C
|
|
------------------------------------------------------------------- -------------------
|
|
SLICE_X25Y79 FDCE (Prop_fdce_C_Q) 0.128 -0.453 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/buffers_1_reg/Q
|
|
net (fo=1, routed) 0.139 -0.314 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/buffers_1
|
|
SLICE_X25Y79 LUT1 (Prop_lut1_I0_O) 0.099 -0.215 f u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/popCC_popPtr[2]_i_2__1/O
|
|
net (fo=43, routed) 0.316 0.101 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/buffers_0_reg[2]
|
|
SLICE_X30Y78 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/popCC_popPtr_reg[0]/CLR
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock mlkem_clk_clk_pll rise edge)
|
|
0.000 0.000 r
|
|
K21 0.000 0.000 r clk (IN)
|
|
net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1
|
|
K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O
|
|
net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll
|
|
PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2)
|
|
-2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2
|
|
net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll
|
|
BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout3_buf/O
|
|
net (fo=26129, routed) 0.952 -0.356 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/mlkem_clk
|
|
SLICE_X30Y78 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/popCC_popPtr_reg[0]/C
|
|
clock pessimism -0.192 -0.548
|
|
SLICE_X30Y78 FDCE (Remov_fdce_C_CLR) -0.092 -0.640 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/popCC_popPtr_reg[0]
|
|
-------------------------------------------------------------------
|
|
required time 0.640
|
|
arrival time 0.101
|
|
-------------------------------------------------------------------
|
|
slack 0.741
|
|
|
|
Slack (MET) : 0.741ns (arrival time - required time)
|
|
Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/buffers_1_reg/C
|
|
(rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns})
|
|
Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/popCC_popPtr_reg[1]/CLR
|
|
(removal check against rising-edge clock mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns})
|
|
Path Group: **async_default**
|
|
Path Type: Removal (Min at Fast Process Corner)
|
|
Requirement: 0.000ns (mlkem_clk_clk_pll rise@0.000ns - mlkem_clk_clk_pll rise@0.000ns)
|
|
Data Path Delay: 0.682ns (logic 0.227ns (33.271%) route 0.455ns (66.729%))
|
|
Logic Levels: 1 (LUT1=1)
|
|
Clock Path Skew: 0.033ns (DCD - SCD - CPR)
|
|
Destination Clock Delay (DCD): -0.356ns
|
|
Source Clock Delay (SCD): -0.581ns
|
|
Clock Pessimism Removal (CPR): 0.192ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock mlkem_clk_clk_pll rise edge)
|
|
0.000 0.000 r
|
|
K21 0.000 0.000 r clk (IN)
|
|
net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1
|
|
K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O
|
|
net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll
|
|
PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2)
|
|
-2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2
|
|
net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll
|
|
BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout3_buf/O
|
|
net (fo=26129, routed) 0.681 -0.581 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/mlkem_clk
|
|
SLICE_X25Y79 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/buffers_1_reg/C
|
|
------------------------------------------------------------------- -------------------
|
|
SLICE_X25Y79 FDCE (Prop_fdce_C_Q) 0.128 -0.453 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/buffers_1_reg/Q
|
|
net (fo=1, routed) 0.139 -0.314 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/buffers_1
|
|
SLICE_X25Y79 LUT1 (Prop_lut1_I0_O) 0.099 -0.215 f u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/popCC_popPtr[2]_i_2__1/O
|
|
net (fo=43, routed) 0.316 0.101 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/buffers_0_reg[2]
|
|
SLICE_X30Y78 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/popCC_popPtr_reg[1]/CLR
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock mlkem_clk_clk_pll rise edge)
|
|
0.000 0.000 r
|
|
K21 0.000 0.000 r clk (IN)
|
|
net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1
|
|
K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O
|
|
net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll
|
|
PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2)
|
|
-2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2
|
|
net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll
|
|
BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout3_buf/O
|
|
net (fo=26129, routed) 0.952 -0.356 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/mlkem_clk
|
|
SLICE_X30Y78 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/popCC_popPtr_reg[1]/C
|
|
clock pessimism -0.192 -0.548
|
|
SLICE_X30Y78 FDCE (Remov_fdce_C_CLR) -0.092 -0.640 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/popCC_popPtr_reg[1]
|
|
-------------------------------------------------------------------
|
|
required time 0.640
|
|
arrival time 0.101
|
|
-------------------------------------------------------------------
|
|
slack 0.741
|
|
|
|
Slack (MET) : 0.741ns (arrival time - required time)
|
|
Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/buffers_1_reg/C
|
|
(rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns})
|
|
Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/popCC_ptrToPush_reg[0]/CLR
|
|
(removal check against rising-edge clock mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns})
|
|
Path Group: **async_default**
|
|
Path Type: Removal (Min at Fast Process Corner)
|
|
Requirement: 0.000ns (mlkem_clk_clk_pll rise@0.000ns - mlkem_clk_clk_pll rise@0.000ns)
|
|
Data Path Delay: 0.682ns (logic 0.227ns (33.271%) route 0.455ns (66.729%))
|
|
Logic Levels: 1 (LUT1=1)
|
|
Clock Path Skew: 0.033ns (DCD - SCD - CPR)
|
|
Destination Clock Delay (DCD): -0.356ns
|
|
Source Clock Delay (SCD): -0.581ns
|
|
Clock Pessimism Removal (CPR): 0.192ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock mlkem_clk_clk_pll rise edge)
|
|
0.000 0.000 r
|
|
K21 0.000 0.000 r clk (IN)
|
|
net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1
|
|
K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O
|
|
net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll
|
|
PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2)
|
|
-2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2
|
|
net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll
|
|
BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout3_buf/O
|
|
net (fo=26129, routed) 0.681 -0.581 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/mlkem_clk
|
|
SLICE_X25Y79 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/buffers_1_reg/C
|
|
------------------------------------------------------------------- -------------------
|
|
SLICE_X25Y79 FDCE (Prop_fdce_C_Q) 0.128 -0.453 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/buffers_1_reg/Q
|
|
net (fo=1, routed) 0.139 -0.314 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/buffers_1
|
|
SLICE_X25Y79 LUT1 (Prop_lut1_I0_O) 0.099 -0.215 f u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/popCC_popPtr[2]_i_2__1/O
|
|
net (fo=43, routed) 0.316 0.101 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/buffers_0_reg[2]
|
|
SLICE_X30Y78 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/popCC_ptrToPush_reg[0]/CLR
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock mlkem_clk_clk_pll rise edge)
|
|
0.000 0.000 r
|
|
K21 0.000 0.000 r clk (IN)
|
|
net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1
|
|
K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O
|
|
net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll
|
|
PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2)
|
|
-2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2
|
|
net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll
|
|
BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout3_buf/O
|
|
net (fo=26129, routed) 0.952 -0.356 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/mlkem_clk
|
|
SLICE_X30Y78 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/popCC_ptrToPush_reg[0]/C
|
|
clock pessimism -0.192 -0.548
|
|
SLICE_X30Y78 FDCE (Remov_fdce_C_CLR) -0.092 -0.640 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/popCC_ptrToPush_reg[0]
|
|
-------------------------------------------------------------------
|
|
required time 0.640
|
|
arrival time 0.101
|
|
-------------------------------------------------------------------
|
|
slack 0.741
|
|
|
|
Slack (MET) : 0.753ns (arrival time - required time)
|
|
Source: pll_clk.u_rst_mlkem/delay_reg[1]/C
|
|
(rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns})
|
|
Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/stream_byte_addr_reg[10]/CLR
|
|
(removal check against rising-edge clock mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns})
|
|
Path Group: **async_default**
|
|
Path Type: Removal (Min at Fast Process Corner)
|
|
Requirement: 0.000ns (mlkem_clk_clk_pll rise@0.000ns - mlkem_clk_clk_pll rise@0.000ns)
|
|
Data Path Delay: 0.695ns (logic 0.186ns (26.771%) route 0.509ns (73.229%))
|
|
Logic Levels: 1 (LUT1=1)
|
|
Clock Path Skew: 0.034ns (DCD - SCD - CPR)
|
|
Destination Clock Delay (DCD): -0.381ns
|
|
Source Clock Delay (SCD): -0.607ns
|
|
Clock Pessimism Removal (CPR): 0.192ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock mlkem_clk_clk_pll rise edge)
|
|
0.000 0.000 r
|
|
K21 0.000 0.000 r clk (IN)
|
|
net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1
|
|
K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O
|
|
net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll
|
|
PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2)
|
|
-2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2
|
|
net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll
|
|
BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout3_buf/O
|
|
net (fo=26129, routed) 0.655 -0.607 pll_clk.u_rst_mlkem/mlkem_clk
|
|
SLICE_X118Y67 FDCE r pll_clk.u_rst_mlkem/delay_reg[1]/C
|
|
------------------------------------------------------------------- -------------------
|
|
SLICE_X118Y67 FDCE (Prop_fdce_C_Q) 0.141 -0.466 r pll_clk.u_rst_mlkem/delay_reg[1]/Q
|
|
net (fo=4, routed) 0.297 -0.169 pll_clk.u_rst_mlkem/Q[0]
|
|
SLICE_X118Y67 LUT1 (Prop_lut1_I0_O) 0.045 -0.124 f pll_clk.u_rst_mlkem/rdb_addr[11]_i_2/O
|
|
net (fo=1069, routed) 0.211 0.087 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/pre_addr_l_reg[2]_rep__1_0
|
|
SLICE_X121Y68 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/stream_byte_addr_reg[10]/CLR
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock mlkem_clk_clk_pll rise edge)
|
|
0.000 0.000 r
|
|
K21 0.000 0.000 r clk (IN)
|
|
net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1
|
|
K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O
|
|
net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll
|
|
PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2)
|
|
-2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2
|
|
net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll
|
|
BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout3_buf/O
|
|
net (fo=26129, routed) 0.927 -0.381 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/mlkem_clk
|
|
SLICE_X121Y68 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/stream_byte_addr_reg[10]/C
|
|
clock pessimism -0.192 -0.573
|
|
SLICE_X121Y68 FDCE (Remov_fdce_C_CLR) -0.092 -0.665 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/stream_byte_addr_reg[10]
|
|
-------------------------------------------------------------------
|
|
required time 0.665
|
|
arrival time 0.087
|
|
-------------------------------------------------------------------
|
|
slack 0.753
|
|
|
|
Slack (MET) : 0.753ns (arrival time - required time)
|
|
Source: pll_clk.u_rst_mlkem/delay_reg[1]/C
|
|
(rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns})
|
|
Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/stream_byte_addr_reg[11]/CLR
|
|
(removal check against rising-edge clock mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns})
|
|
Path Group: **async_default**
|
|
Path Type: Removal (Min at Fast Process Corner)
|
|
Requirement: 0.000ns (mlkem_clk_clk_pll rise@0.000ns - mlkem_clk_clk_pll rise@0.000ns)
|
|
Data Path Delay: 0.695ns (logic 0.186ns (26.771%) route 0.509ns (73.229%))
|
|
Logic Levels: 1 (LUT1=1)
|
|
Clock Path Skew: 0.034ns (DCD - SCD - CPR)
|
|
Destination Clock Delay (DCD): -0.381ns
|
|
Source Clock Delay (SCD): -0.607ns
|
|
Clock Pessimism Removal (CPR): 0.192ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock mlkem_clk_clk_pll rise edge)
|
|
0.000 0.000 r
|
|
K21 0.000 0.000 r clk (IN)
|
|
net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1
|
|
K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O
|
|
net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll
|
|
PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2)
|
|
-2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2
|
|
net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll
|
|
BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout3_buf/O
|
|
net (fo=26129, routed) 0.655 -0.607 pll_clk.u_rst_mlkem/mlkem_clk
|
|
SLICE_X118Y67 FDCE r pll_clk.u_rst_mlkem/delay_reg[1]/C
|
|
------------------------------------------------------------------- -------------------
|
|
SLICE_X118Y67 FDCE (Prop_fdce_C_Q) 0.141 -0.466 r pll_clk.u_rst_mlkem/delay_reg[1]/Q
|
|
net (fo=4, routed) 0.297 -0.169 pll_clk.u_rst_mlkem/Q[0]
|
|
SLICE_X118Y67 LUT1 (Prop_lut1_I0_O) 0.045 -0.124 f pll_clk.u_rst_mlkem/rdb_addr[11]_i_2/O
|
|
net (fo=1069, routed) 0.211 0.087 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/pre_addr_l_reg[2]_rep__1_0
|
|
SLICE_X121Y68 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/stream_byte_addr_reg[11]/CLR
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock mlkem_clk_clk_pll rise edge)
|
|
0.000 0.000 r
|
|
K21 0.000 0.000 r clk (IN)
|
|
net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1
|
|
K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O
|
|
net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll
|
|
PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2)
|
|
-2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2
|
|
net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll
|
|
BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout3_buf/O
|
|
net (fo=26129, routed) 0.927 -0.381 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/mlkem_clk
|
|
SLICE_X121Y68 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/stream_byte_addr_reg[11]/C
|
|
clock pessimism -0.192 -0.573
|
|
SLICE_X121Y68 FDCE (Remov_fdce_C_CLR) -0.092 -0.665 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/stream_byte_addr_reg[11]
|
|
-------------------------------------------------------------------
|
|
required time 0.665
|
|
arrival time 0.087
|
|
-------------------------------------------------------------------
|
|
slack 0.753
|
|
|
|
Slack (MET) : 0.753ns (arrival time - required time)
|
|
Source: pll_clk.u_rst_mlkem/delay_reg[1]/C
|
|
(rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns})
|
|
Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/stream_byte_addr_reg[8]/CLR
|
|
(removal check against rising-edge clock mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns})
|
|
Path Group: **async_default**
|
|
Path Type: Removal (Min at Fast Process Corner)
|
|
Requirement: 0.000ns (mlkem_clk_clk_pll rise@0.000ns - mlkem_clk_clk_pll rise@0.000ns)
|
|
Data Path Delay: 0.695ns (logic 0.186ns (26.771%) route 0.509ns (73.229%))
|
|
Logic Levels: 1 (LUT1=1)
|
|
Clock Path Skew: 0.034ns (DCD - SCD - CPR)
|
|
Destination Clock Delay (DCD): -0.381ns
|
|
Source Clock Delay (SCD): -0.607ns
|
|
Clock Pessimism Removal (CPR): 0.192ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock mlkem_clk_clk_pll rise edge)
|
|
0.000 0.000 r
|
|
K21 0.000 0.000 r clk (IN)
|
|
net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1
|
|
K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O
|
|
net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll
|
|
PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2)
|
|
-2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2
|
|
net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll
|
|
BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout3_buf/O
|
|
net (fo=26129, routed) 0.655 -0.607 pll_clk.u_rst_mlkem/mlkem_clk
|
|
SLICE_X118Y67 FDCE r pll_clk.u_rst_mlkem/delay_reg[1]/C
|
|
------------------------------------------------------------------- -------------------
|
|
SLICE_X118Y67 FDCE (Prop_fdce_C_Q) 0.141 -0.466 r pll_clk.u_rst_mlkem/delay_reg[1]/Q
|
|
net (fo=4, routed) 0.297 -0.169 pll_clk.u_rst_mlkem/Q[0]
|
|
SLICE_X118Y67 LUT1 (Prop_lut1_I0_O) 0.045 -0.124 f pll_clk.u_rst_mlkem/rdb_addr[11]_i_2/O
|
|
net (fo=1069, routed) 0.211 0.087 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/pre_addr_l_reg[2]_rep__1_0
|
|
SLICE_X121Y68 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/stream_byte_addr_reg[8]/CLR
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock mlkem_clk_clk_pll rise edge)
|
|
0.000 0.000 r
|
|
K21 0.000 0.000 r clk (IN)
|
|
net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1
|
|
K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O
|
|
net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll
|
|
PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2)
|
|
-2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2
|
|
net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll
|
|
BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout3_buf/O
|
|
net (fo=26129, routed) 0.927 -0.381 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/mlkem_clk
|
|
SLICE_X121Y68 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/stream_byte_addr_reg[8]/C
|
|
clock pessimism -0.192 -0.573
|
|
SLICE_X121Y68 FDCE (Remov_fdce_C_CLR) -0.092 -0.665 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/stream_byte_addr_reg[8]
|
|
-------------------------------------------------------------------
|
|
required time 0.665
|
|
arrival time 0.087
|
|
-------------------------------------------------------------------
|
|
slack 0.753
|
|
|
|
Slack (MET) : 0.753ns (arrival time - required time)
|
|
Source: pll_clk.u_rst_mlkem/delay_reg[1]/C
|
|
(rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns})
|
|
Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/stream_byte_addr_reg[9]/CLR
|
|
(removal check against rising-edge clock mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns})
|
|
Path Group: **async_default**
|
|
Path Type: Removal (Min at Fast Process Corner)
|
|
Requirement: 0.000ns (mlkem_clk_clk_pll rise@0.000ns - mlkem_clk_clk_pll rise@0.000ns)
|
|
Data Path Delay: 0.695ns (logic 0.186ns (26.771%) route 0.509ns (73.229%))
|
|
Logic Levels: 1 (LUT1=1)
|
|
Clock Path Skew: 0.034ns (DCD - SCD - CPR)
|
|
Destination Clock Delay (DCD): -0.381ns
|
|
Source Clock Delay (SCD): -0.607ns
|
|
Clock Pessimism Removal (CPR): 0.192ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock mlkem_clk_clk_pll rise edge)
|
|
0.000 0.000 r
|
|
K21 0.000 0.000 r clk (IN)
|
|
net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1
|
|
K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O
|
|
net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll
|
|
PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2)
|
|
-2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2
|
|
net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll
|
|
BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout3_buf/O
|
|
net (fo=26129, routed) 0.655 -0.607 pll_clk.u_rst_mlkem/mlkem_clk
|
|
SLICE_X118Y67 FDCE r pll_clk.u_rst_mlkem/delay_reg[1]/C
|
|
------------------------------------------------------------------- -------------------
|
|
SLICE_X118Y67 FDCE (Prop_fdce_C_Q) 0.141 -0.466 r pll_clk.u_rst_mlkem/delay_reg[1]/Q
|
|
net (fo=4, routed) 0.297 -0.169 pll_clk.u_rst_mlkem/Q[0]
|
|
SLICE_X118Y67 LUT1 (Prop_lut1_I0_O) 0.045 -0.124 f pll_clk.u_rst_mlkem/rdb_addr[11]_i_2/O
|
|
net (fo=1069, routed) 0.211 0.087 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/pre_addr_l_reg[2]_rep__1_0
|
|
SLICE_X121Y68 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/stream_byte_addr_reg[9]/CLR
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock mlkem_clk_clk_pll rise edge)
|
|
0.000 0.000 r
|
|
K21 0.000 0.000 r clk (IN)
|
|
net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1
|
|
K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O
|
|
net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll
|
|
PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2)
|
|
-2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2
|
|
net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll
|
|
BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout3_buf/O
|
|
net (fo=26129, routed) 0.927 -0.381 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/mlkem_clk
|
|
SLICE_X121Y68 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/stream_byte_addr_reg[9]/C
|
|
clock pessimism -0.192 -0.573
|
|
SLICE_X121Y68 FDCE (Remov_fdce_C_CLR) -0.092 -0.665 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/stream_byte_addr_reg[9]
|
|
-------------------------------------------------------------------
|
|
required time 0.665
|
|
arrival time 0.087
|
|
-------------------------------------------------------------------
|
|
slack 0.753
|
|
|
|
Slack (MET) : 0.772ns (arrival time - required time)
|
|
Source: pll_clk.u_rst_mlkem/delay_reg[1]/C
|
|
(rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns})
|
|
Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/stream_wdata_reg[0]/CLR
|
|
(removal check against rising-edge clock mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns})
|
|
Path Group: **async_default**
|
|
Path Type: Removal (Min at Fast Process Corner)
|
|
Requirement: 0.000ns (mlkem_clk_clk_pll rise@0.000ns - mlkem_clk_clk_pll rise@0.000ns)
|
|
Data Path Delay: 0.692ns (logic 0.186ns (26.887%) route 0.506ns (73.113%))
|
|
Logic Levels: 1 (LUT1=1)
|
|
Clock Path Skew: 0.012ns (DCD - SCD - CPR)
|
|
Destination Clock Delay (DCD): -0.382ns
|
|
Source Clock Delay (SCD): -0.607ns
|
|
Clock Pessimism Removal (CPR): 0.213ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock mlkem_clk_clk_pll rise edge)
|
|
0.000 0.000 r
|
|
K21 0.000 0.000 r clk (IN)
|
|
net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1
|
|
K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O
|
|
net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll
|
|
PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2)
|
|
-2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2
|
|
net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll
|
|
BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout3_buf/O
|
|
net (fo=26129, routed) 0.655 -0.607 pll_clk.u_rst_mlkem/mlkem_clk
|
|
SLICE_X118Y67 FDCE r pll_clk.u_rst_mlkem/delay_reg[1]/C
|
|
------------------------------------------------------------------- -------------------
|
|
SLICE_X118Y67 FDCE (Prop_fdce_C_Q) 0.141 -0.466 r pll_clk.u_rst_mlkem/delay_reg[1]/Q
|
|
net (fo=4, routed) 0.297 -0.169 pll_clk.u_rst_mlkem/Q[0]
|
|
SLICE_X118Y67 LUT1 (Prop_lut1_I0_O) 0.045 -0.124 f pll_clk.u_rst_mlkem/rdb_addr[11]_i_2/O
|
|
net (fo=1069, routed) 0.208 0.084 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/pre_addr_l_reg[2]_rep__1_0
|
|
SLICE_X119Y69 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/stream_wdata_reg[0]/CLR
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock mlkem_clk_clk_pll rise edge)
|
|
0.000 0.000 r
|
|
K21 0.000 0.000 r clk (IN)
|
|
net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1
|
|
K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O
|
|
net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll
|
|
PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2)
|
|
-2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2
|
|
net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll
|
|
BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout3_buf/O
|
|
net (fo=26129, routed) 0.926 -0.382 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/mlkem_clk
|
|
SLICE_X119Y69 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/stream_wdata_reg[0]/C
|
|
clock pessimism -0.213 -0.595
|
|
SLICE_X119Y69 FDCE (Remov_fdce_C_CLR) -0.092 -0.687 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/stream_wdata_reg[0]
|
|
-------------------------------------------------------------------
|
|
required time 0.687
|
|
arrival time 0.084
|
|
-------------------------------------------------------------------
|
|
slack 0.772
|
|
|
|
Slack (MET) : 0.772ns (arrival time - required time)
|
|
Source: pll_clk.u_rst_mlkem/delay_reg[1]/C
|
|
(rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns})
|
|
Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/stream_wdata_reg[12]/CLR
|
|
(removal check against rising-edge clock mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns})
|
|
Path Group: **async_default**
|
|
Path Type: Removal (Min at Fast Process Corner)
|
|
Requirement: 0.000ns (mlkem_clk_clk_pll rise@0.000ns - mlkem_clk_clk_pll rise@0.000ns)
|
|
Data Path Delay: 0.692ns (logic 0.186ns (26.887%) route 0.506ns (73.113%))
|
|
Logic Levels: 1 (LUT1=1)
|
|
Clock Path Skew: 0.012ns (DCD - SCD - CPR)
|
|
Destination Clock Delay (DCD): -0.382ns
|
|
Source Clock Delay (SCD): -0.607ns
|
|
Clock Pessimism Removal (CPR): 0.213ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock mlkem_clk_clk_pll rise edge)
|
|
0.000 0.000 r
|
|
K21 0.000 0.000 r clk (IN)
|
|
net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1
|
|
K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O
|
|
net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll
|
|
PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2)
|
|
-2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2
|
|
net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll
|
|
BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout3_buf/O
|
|
net (fo=26129, routed) 0.655 -0.607 pll_clk.u_rst_mlkem/mlkem_clk
|
|
SLICE_X118Y67 FDCE r pll_clk.u_rst_mlkem/delay_reg[1]/C
|
|
------------------------------------------------------------------- -------------------
|
|
SLICE_X118Y67 FDCE (Prop_fdce_C_Q) 0.141 -0.466 r pll_clk.u_rst_mlkem/delay_reg[1]/Q
|
|
net (fo=4, routed) 0.297 -0.169 pll_clk.u_rst_mlkem/Q[0]
|
|
SLICE_X118Y67 LUT1 (Prop_lut1_I0_O) 0.045 -0.124 f pll_clk.u_rst_mlkem/rdb_addr[11]_i_2/O
|
|
net (fo=1069, routed) 0.208 0.084 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/pre_addr_l_reg[2]_rep__1_0
|
|
SLICE_X119Y69 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/stream_wdata_reg[12]/CLR
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock mlkem_clk_clk_pll rise edge)
|
|
0.000 0.000 r
|
|
K21 0.000 0.000 r clk (IN)
|
|
net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1
|
|
K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O
|
|
net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll
|
|
PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2)
|
|
-2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2
|
|
net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll
|
|
BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout3_buf/O
|
|
net (fo=26129, routed) 0.926 -0.382 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/mlkem_clk
|
|
SLICE_X119Y69 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/stream_wdata_reg[12]/C
|
|
clock pessimism -0.213 -0.595
|
|
SLICE_X119Y69 FDCE (Remov_fdce_C_CLR) -0.092 -0.687 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/stream_wdata_reg[12]
|
|
-------------------------------------------------------------------
|
|
required time 0.687
|
|
arrival time 0.084
|
|
-------------------------------------------------------------------
|
|
slack 0.772
|
|
|
|
Slack (MET) : 0.772ns (arrival time - required time)
|
|
Source: pll_clk.u_rst_mlkem/delay_reg[1]/C
|
|
(rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns})
|
|
Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/stream_wdata_reg[16]/CLR
|
|
(removal check against rising-edge clock mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns})
|
|
Path Group: **async_default**
|
|
Path Type: Removal (Min at Fast Process Corner)
|
|
Requirement: 0.000ns (mlkem_clk_clk_pll rise@0.000ns - mlkem_clk_clk_pll rise@0.000ns)
|
|
Data Path Delay: 0.692ns (logic 0.186ns (26.887%) route 0.506ns (73.113%))
|
|
Logic Levels: 1 (LUT1=1)
|
|
Clock Path Skew: 0.012ns (DCD - SCD - CPR)
|
|
Destination Clock Delay (DCD): -0.382ns
|
|
Source Clock Delay (SCD): -0.607ns
|
|
Clock Pessimism Removal (CPR): 0.213ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock mlkem_clk_clk_pll rise edge)
|
|
0.000 0.000 r
|
|
K21 0.000 0.000 r clk (IN)
|
|
net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1
|
|
K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O
|
|
net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll
|
|
PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2)
|
|
-2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2
|
|
net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll
|
|
BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout3_buf/O
|
|
net (fo=26129, routed) 0.655 -0.607 pll_clk.u_rst_mlkem/mlkem_clk
|
|
SLICE_X118Y67 FDCE r pll_clk.u_rst_mlkem/delay_reg[1]/C
|
|
------------------------------------------------------------------- -------------------
|
|
SLICE_X118Y67 FDCE (Prop_fdce_C_Q) 0.141 -0.466 r pll_clk.u_rst_mlkem/delay_reg[1]/Q
|
|
net (fo=4, routed) 0.297 -0.169 pll_clk.u_rst_mlkem/Q[0]
|
|
SLICE_X118Y67 LUT1 (Prop_lut1_I0_O) 0.045 -0.124 f pll_clk.u_rst_mlkem/rdb_addr[11]_i_2/O
|
|
net (fo=1069, routed) 0.208 0.084 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/pre_addr_l_reg[2]_rep__1_0
|
|
SLICE_X119Y69 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/stream_wdata_reg[16]/CLR
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock mlkem_clk_clk_pll rise edge)
|
|
0.000 0.000 r
|
|
K21 0.000 0.000 r clk (IN)
|
|
net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1
|
|
K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O
|
|
net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll
|
|
PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2)
|
|
-2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2
|
|
net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll
|
|
BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout3_buf/O
|
|
net (fo=26129, routed) 0.926 -0.382 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/mlkem_clk
|
|
SLICE_X119Y69 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/stream_wdata_reg[16]/C
|
|
clock pessimism -0.213 -0.595
|
|
SLICE_X119Y69 FDCE (Remov_fdce_C_CLR) -0.092 -0.687 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/stream_wdata_reg[16]
|
|
-------------------------------------------------------------------
|
|
required time 0.687
|
|
arrival time 0.084
|
|
-------------------------------------------------------------------
|
|
slack 0.772
|
|
|
|
Slack (MET) : 0.772ns (arrival time - required time)
|
|
Source: pll_clk.u_rst_mlkem/delay_reg[1]/C
|
|
(rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns})
|
|
Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/stream_wdata_reg[20]/CLR
|
|
(removal check against rising-edge clock mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns})
|
|
Path Group: **async_default**
|
|
Path Type: Removal (Min at Fast Process Corner)
|
|
Requirement: 0.000ns (mlkem_clk_clk_pll rise@0.000ns - mlkem_clk_clk_pll rise@0.000ns)
|
|
Data Path Delay: 0.692ns (logic 0.186ns (26.887%) route 0.506ns (73.113%))
|
|
Logic Levels: 1 (LUT1=1)
|
|
Clock Path Skew: 0.012ns (DCD - SCD - CPR)
|
|
Destination Clock Delay (DCD): -0.382ns
|
|
Source Clock Delay (SCD): -0.607ns
|
|
Clock Pessimism Removal (CPR): 0.213ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock mlkem_clk_clk_pll rise edge)
|
|
0.000 0.000 r
|
|
K21 0.000 0.000 r clk (IN)
|
|
net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1
|
|
K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O
|
|
net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll
|
|
PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2)
|
|
-2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2
|
|
net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll
|
|
BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout3_buf/O
|
|
net (fo=26129, routed) 0.655 -0.607 pll_clk.u_rst_mlkem/mlkem_clk
|
|
SLICE_X118Y67 FDCE r pll_clk.u_rst_mlkem/delay_reg[1]/C
|
|
------------------------------------------------------------------- -------------------
|
|
SLICE_X118Y67 FDCE (Prop_fdce_C_Q) 0.141 -0.466 r pll_clk.u_rst_mlkem/delay_reg[1]/Q
|
|
net (fo=4, routed) 0.297 -0.169 pll_clk.u_rst_mlkem/Q[0]
|
|
SLICE_X118Y67 LUT1 (Prop_lut1_I0_O) 0.045 -0.124 f pll_clk.u_rst_mlkem/rdb_addr[11]_i_2/O
|
|
net (fo=1069, routed) 0.208 0.084 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/pre_addr_l_reg[2]_rep__1_0
|
|
SLICE_X119Y69 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/stream_wdata_reg[20]/CLR
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock mlkem_clk_clk_pll rise edge)
|
|
0.000 0.000 r
|
|
K21 0.000 0.000 r clk (IN)
|
|
net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1
|
|
K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O
|
|
net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll
|
|
PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2)
|
|
-2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2
|
|
net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll
|
|
BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout3_buf/O
|
|
net (fo=26129, routed) 0.926 -0.382 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/mlkem_clk
|
|
SLICE_X119Y69 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/stream_wdata_reg[20]/C
|
|
clock pessimism -0.213 -0.595
|
|
SLICE_X119Y69 FDCE (Remov_fdce_C_CLR) -0.092 -0.687 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/stream_wdata_reg[20]
|
|
-------------------------------------------------------------------
|
|
required time 0.687
|
|
arrival time 0.084
|
|
-------------------------------------------------------------------
|
|
slack 0.772
|
|
|
|
Slack (MET) : 0.772ns (arrival time - required time)
|
|
Source: pll_clk.u_rst_mlkem/delay_reg[1]/C
|
|
(rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns})
|
|
Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/stream_wdata_reg[24]/CLR
|
|
(removal check against rising-edge clock mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns})
|
|
Path Group: **async_default**
|
|
Path Type: Removal (Min at Fast Process Corner)
|
|
Requirement: 0.000ns (mlkem_clk_clk_pll rise@0.000ns - mlkem_clk_clk_pll rise@0.000ns)
|
|
Data Path Delay: 0.692ns (logic 0.186ns (26.887%) route 0.506ns (73.113%))
|
|
Logic Levels: 1 (LUT1=1)
|
|
Clock Path Skew: 0.012ns (DCD - SCD - CPR)
|
|
Destination Clock Delay (DCD): -0.382ns
|
|
Source Clock Delay (SCD): -0.607ns
|
|
Clock Pessimism Removal (CPR): 0.213ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock mlkem_clk_clk_pll rise edge)
|
|
0.000 0.000 r
|
|
K21 0.000 0.000 r clk (IN)
|
|
net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1
|
|
K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O
|
|
net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll
|
|
PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2)
|
|
-2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2
|
|
net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll
|
|
BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout3_buf/O
|
|
net (fo=26129, routed) 0.655 -0.607 pll_clk.u_rst_mlkem/mlkem_clk
|
|
SLICE_X118Y67 FDCE r pll_clk.u_rst_mlkem/delay_reg[1]/C
|
|
------------------------------------------------------------------- -------------------
|
|
SLICE_X118Y67 FDCE (Prop_fdce_C_Q) 0.141 -0.466 r pll_clk.u_rst_mlkem/delay_reg[1]/Q
|
|
net (fo=4, routed) 0.297 -0.169 pll_clk.u_rst_mlkem/Q[0]
|
|
SLICE_X118Y67 LUT1 (Prop_lut1_I0_O) 0.045 -0.124 f pll_clk.u_rst_mlkem/rdb_addr[11]_i_2/O
|
|
net (fo=1069, routed) 0.208 0.084 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/pre_addr_l_reg[2]_rep__1_0
|
|
SLICE_X119Y69 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/stream_wdata_reg[24]/CLR
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock mlkem_clk_clk_pll rise edge)
|
|
0.000 0.000 r
|
|
K21 0.000 0.000 r clk (IN)
|
|
net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1
|
|
K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O
|
|
net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll
|
|
PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2)
|
|
-2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2
|
|
net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll
|
|
BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout3_buf/O
|
|
net (fo=26129, routed) 0.926 -0.382 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/mlkem_clk
|
|
SLICE_X119Y69 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/stream_wdata_reg[24]/C
|
|
clock pessimism -0.213 -0.595
|
|
SLICE_X119Y69 FDCE (Remov_fdce_C_CLR) -0.092 -0.687 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/stream_wdata_reg[24]
|
|
-------------------------------------------------------------------
|
|
required time 0.687
|
|
arrival time 0.084
|
|
-------------------------------------------------------------------
|
|
slack 0.772
|
|
|
|
Slack (MET) : 0.772ns (arrival time - required time)
|
|
Source: pll_clk.u_rst_mlkem/delay_reg[1]/C
|
|
(rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns})
|
|
Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/stream_wdata_reg[8]/CLR
|
|
(removal check against rising-edge clock mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns})
|
|
Path Group: **async_default**
|
|
Path Type: Removal (Min at Fast Process Corner)
|
|
Requirement: 0.000ns (mlkem_clk_clk_pll rise@0.000ns - mlkem_clk_clk_pll rise@0.000ns)
|
|
Data Path Delay: 0.692ns (logic 0.186ns (26.887%) route 0.506ns (73.113%))
|
|
Logic Levels: 1 (LUT1=1)
|
|
Clock Path Skew: 0.012ns (DCD - SCD - CPR)
|
|
Destination Clock Delay (DCD): -0.382ns
|
|
Source Clock Delay (SCD): -0.607ns
|
|
Clock Pessimism Removal (CPR): 0.213ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock mlkem_clk_clk_pll rise edge)
|
|
0.000 0.000 r
|
|
K21 0.000 0.000 r clk (IN)
|
|
net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1
|
|
K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O
|
|
net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll
|
|
PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2)
|
|
-2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2
|
|
net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll
|
|
BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout3_buf/O
|
|
net (fo=26129, routed) 0.655 -0.607 pll_clk.u_rst_mlkem/mlkem_clk
|
|
SLICE_X118Y67 FDCE r pll_clk.u_rst_mlkem/delay_reg[1]/C
|
|
------------------------------------------------------------------- -------------------
|
|
SLICE_X118Y67 FDCE (Prop_fdce_C_Q) 0.141 -0.466 r pll_clk.u_rst_mlkem/delay_reg[1]/Q
|
|
net (fo=4, routed) 0.297 -0.169 pll_clk.u_rst_mlkem/Q[0]
|
|
SLICE_X118Y67 LUT1 (Prop_lut1_I0_O) 0.045 -0.124 f pll_clk.u_rst_mlkem/rdb_addr[11]_i_2/O
|
|
net (fo=1069, routed) 0.208 0.084 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/pre_addr_l_reg[2]_rep__1_0
|
|
SLICE_X119Y69 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/stream_wdata_reg[8]/CLR
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock mlkem_clk_clk_pll rise edge)
|
|
0.000 0.000 r
|
|
K21 0.000 0.000 r clk (IN)
|
|
net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1
|
|
K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O
|
|
net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll
|
|
PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2)
|
|
-2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2
|
|
net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll
|
|
BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout3_buf/O
|
|
net (fo=26129, routed) 0.926 -0.382 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/mlkem_clk
|
|
SLICE_X119Y69 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/stream_wdata_reg[8]/C
|
|
clock pessimism -0.213 -0.595
|
|
SLICE_X119Y69 FDCE (Remov_fdce_C_CLR) -0.092 -0.687 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/stream_wdata_reg[8]
|
|
-------------------------------------------------------------------
|
|
required time 0.687
|
|
arrival time 0.084
|
|
-------------------------------------------------------------------
|
|
slack 0.772
|
|
|
|
Slack (MET) : 0.776ns (arrival time - required time)
|
|
Source: pll_clk.u_rst_mlkem/delay_reg[1]/C
|
|
(rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns})
|
|
Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/pre_byte_l_reg[0]/CLR
|
|
(removal check against rising-edge clock mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns})
|
|
Path Group: **async_default**
|
|
Path Type: Removal (Min at Fast Process Corner)
|
|
Requirement: 0.000ns (mlkem_clk_clk_pll rise@0.000ns - mlkem_clk_clk_pll rise@0.000ns)
|
|
Data Path Delay: 0.696ns (logic 0.186ns (26.719%) route 0.510ns (73.281%))
|
|
Logic Levels: 1 (LUT1=1)
|
|
Clock Path Skew: 0.012ns (DCD - SCD - CPR)
|
|
Destination Clock Delay (DCD): -0.382ns
|
|
Source Clock Delay (SCD): -0.607ns
|
|
Clock Pessimism Removal (CPR): 0.213ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock mlkem_clk_clk_pll rise edge)
|
|
0.000 0.000 r
|
|
K21 0.000 0.000 r clk (IN)
|
|
net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1
|
|
K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O
|
|
net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll
|
|
PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2)
|
|
-2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2
|
|
net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll
|
|
BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout3_buf/O
|
|
net (fo=26129, routed) 0.655 -0.607 pll_clk.u_rst_mlkem/mlkem_clk
|
|
SLICE_X118Y67 FDCE r pll_clk.u_rst_mlkem/delay_reg[1]/C
|
|
------------------------------------------------------------------- -------------------
|
|
SLICE_X118Y67 FDCE (Prop_fdce_C_Q) 0.141 -0.466 r pll_clk.u_rst_mlkem/delay_reg[1]/Q
|
|
net (fo=4, routed) 0.297 -0.169 pll_clk.u_rst_mlkem/Q[0]
|
|
SLICE_X118Y67 LUT1 (Prop_lut1_I0_O) 0.045 -0.124 f pll_clk.u_rst_mlkem/rdb_addr[11]_i_2/O
|
|
net (fo=1069, routed) 0.213 0.089 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/pre_addr_l_reg[2]_rep__1_0
|
|
SLICE_X118Y69 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/pre_byte_l_reg[0]/CLR
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock mlkem_clk_clk_pll rise edge)
|
|
0.000 0.000 r
|
|
K21 0.000 0.000 r clk (IN)
|
|
net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1
|
|
K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O
|
|
net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll
|
|
PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2)
|
|
-2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2
|
|
net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll
|
|
BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout3_buf/O
|
|
net (fo=26129, routed) 0.926 -0.382 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/mlkem_clk
|
|
SLICE_X118Y69 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/pre_byte_l_reg[0]/C
|
|
clock pessimism -0.213 -0.595
|
|
SLICE_X118Y69 FDCE (Remov_fdce_C_CLR) -0.092 -0.687 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/pre_byte_l_reg[0]
|
|
-------------------------------------------------------------------
|
|
required time 0.687
|
|
arrival time 0.089
|
|
-------------------------------------------------------------------
|
|
slack 0.776
|
|
|
|
Slack (MET) : 0.776ns (arrival time - required time)
|
|
Source: pll_clk.u_rst_mlkem/delay_reg[1]/C
|
|
(rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns})
|
|
Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/pre_byte_l_reg[4]/CLR
|
|
(removal check against rising-edge clock mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns})
|
|
Path Group: **async_default**
|
|
Path Type: Removal (Min at Fast Process Corner)
|
|
Requirement: 0.000ns (mlkem_clk_clk_pll rise@0.000ns - mlkem_clk_clk_pll rise@0.000ns)
|
|
Data Path Delay: 0.696ns (logic 0.186ns (26.719%) route 0.510ns (73.281%))
|
|
Logic Levels: 1 (LUT1=1)
|
|
Clock Path Skew: 0.012ns (DCD - SCD - CPR)
|
|
Destination Clock Delay (DCD): -0.382ns
|
|
Source Clock Delay (SCD): -0.607ns
|
|
Clock Pessimism Removal (CPR): 0.213ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock mlkem_clk_clk_pll rise edge)
|
|
0.000 0.000 r
|
|
K21 0.000 0.000 r clk (IN)
|
|
net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1
|
|
K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O
|
|
net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll
|
|
PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2)
|
|
-2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2
|
|
net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll
|
|
BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout3_buf/O
|
|
net (fo=26129, routed) 0.655 -0.607 pll_clk.u_rst_mlkem/mlkem_clk
|
|
SLICE_X118Y67 FDCE r pll_clk.u_rst_mlkem/delay_reg[1]/C
|
|
------------------------------------------------------------------- -------------------
|
|
SLICE_X118Y67 FDCE (Prop_fdce_C_Q) 0.141 -0.466 r pll_clk.u_rst_mlkem/delay_reg[1]/Q
|
|
net (fo=4, routed) 0.297 -0.169 pll_clk.u_rst_mlkem/Q[0]
|
|
SLICE_X118Y67 LUT1 (Prop_lut1_I0_O) 0.045 -0.124 f pll_clk.u_rst_mlkem/rdb_addr[11]_i_2/O
|
|
net (fo=1069, routed) 0.213 0.089 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/pre_addr_l_reg[2]_rep__1_0
|
|
SLICE_X118Y69 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/pre_byte_l_reg[4]/CLR
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock mlkem_clk_clk_pll rise edge)
|
|
0.000 0.000 r
|
|
K21 0.000 0.000 r clk (IN)
|
|
net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1
|
|
K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O
|
|
net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll
|
|
PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2)
|
|
-2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2
|
|
net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll
|
|
BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout3_buf/O
|
|
net (fo=26129, routed) 0.926 -0.382 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/mlkem_clk
|
|
SLICE_X118Y69 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/pre_byte_l_reg[4]/C
|
|
clock pessimism -0.213 -0.595
|
|
SLICE_X118Y69 FDCE (Remov_fdce_C_CLR) -0.092 -0.687 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/pre_byte_l_reg[4]
|
|
-------------------------------------------------------------------
|
|
required time 0.687
|
|
arrival time 0.089
|
|
-------------------------------------------------------------------
|
|
slack 0.776
|
|
|
|
Slack (MET) : 0.799ns (arrival time - required time)
|
|
Source: pll_clk.u_rst_mlkem/delay_reg[1]/C
|
|
(rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns})
|
|
Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/pre_addr_l_reg[10]/CLR
|
|
(removal check against rising-edge clock mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns})
|
|
Path Group: **async_default**
|
|
Path Type: Removal (Min at Fast Process Corner)
|
|
Requirement: 0.000ns (mlkem_clk_clk_pll rise@0.000ns - mlkem_clk_clk_pll rise@0.000ns)
|
|
Data Path Delay: 0.741ns (logic 0.186ns (25.097%) route 0.555ns (74.903%))
|
|
Logic Levels: 1 (LUT1=1)
|
|
Clock Path Skew: 0.034ns (DCD - SCD - CPR)
|
|
Destination Clock Delay (DCD): -0.381ns
|
|
Source Clock Delay (SCD): -0.607ns
|
|
Clock Pessimism Removal (CPR): 0.192ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock mlkem_clk_clk_pll rise edge)
|
|
0.000 0.000 r
|
|
K21 0.000 0.000 r clk (IN)
|
|
net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1
|
|
K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O
|
|
net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll
|
|
PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2)
|
|
-2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2
|
|
net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll
|
|
BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout3_buf/O
|
|
net (fo=26129, routed) 0.655 -0.607 pll_clk.u_rst_mlkem/mlkem_clk
|
|
SLICE_X118Y67 FDCE r pll_clk.u_rst_mlkem/delay_reg[1]/C
|
|
------------------------------------------------------------------- -------------------
|
|
SLICE_X118Y67 FDCE (Prop_fdce_C_Q) 0.141 -0.466 r pll_clk.u_rst_mlkem/delay_reg[1]/Q
|
|
net (fo=4, routed) 0.297 -0.169 pll_clk.u_rst_mlkem/Q[0]
|
|
SLICE_X118Y67 LUT1 (Prop_lut1_I0_O) 0.045 -0.124 f pll_clk.u_rst_mlkem/rdb_addr[11]_i_2/O
|
|
net (fo=1069, routed) 0.258 0.134 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/pre_addr_l_reg[2]_rep__1_0
|
|
SLICE_X123Y68 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/pre_addr_l_reg[10]/CLR
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock mlkem_clk_clk_pll rise edge)
|
|
0.000 0.000 r
|
|
K21 0.000 0.000 r clk (IN)
|
|
net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1
|
|
K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O
|
|
net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll
|
|
PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2)
|
|
-2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2
|
|
net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll
|
|
BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout3_buf/O
|
|
net (fo=26129, routed) 0.927 -0.381 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/mlkem_clk
|
|
SLICE_X123Y68 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/pre_addr_l_reg[10]/C
|
|
clock pessimism -0.192 -0.573
|
|
SLICE_X123Y68 FDCE (Remov_fdce_C_CLR) -0.092 -0.665 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/pre_addr_l_reg[10]
|
|
-------------------------------------------------------------------
|
|
required time 0.665
|
|
arrival time 0.134
|
|
-------------------------------------------------------------------
|
|
slack 0.799
|
|
|
|
Slack (MET) : 0.799ns (arrival time - required time)
|
|
Source: pll_clk.u_rst_mlkem/delay_reg[1]/C
|
|
(rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns})
|
|
Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/pre_addr_l_reg[11]/CLR
|
|
(removal check against rising-edge clock mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns})
|
|
Path Group: **async_default**
|
|
Path Type: Removal (Min at Fast Process Corner)
|
|
Requirement: 0.000ns (mlkem_clk_clk_pll rise@0.000ns - mlkem_clk_clk_pll rise@0.000ns)
|
|
Data Path Delay: 0.741ns (logic 0.186ns (25.097%) route 0.555ns (74.903%))
|
|
Logic Levels: 1 (LUT1=1)
|
|
Clock Path Skew: 0.034ns (DCD - SCD - CPR)
|
|
Destination Clock Delay (DCD): -0.381ns
|
|
Source Clock Delay (SCD): -0.607ns
|
|
Clock Pessimism Removal (CPR): 0.192ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock mlkem_clk_clk_pll rise edge)
|
|
0.000 0.000 r
|
|
K21 0.000 0.000 r clk (IN)
|
|
net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1
|
|
K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O
|
|
net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll
|
|
PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2)
|
|
-2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2
|
|
net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll
|
|
BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout3_buf/O
|
|
net (fo=26129, routed) 0.655 -0.607 pll_clk.u_rst_mlkem/mlkem_clk
|
|
SLICE_X118Y67 FDCE r pll_clk.u_rst_mlkem/delay_reg[1]/C
|
|
------------------------------------------------------------------- -------------------
|
|
SLICE_X118Y67 FDCE (Prop_fdce_C_Q) 0.141 -0.466 r pll_clk.u_rst_mlkem/delay_reg[1]/Q
|
|
net (fo=4, routed) 0.297 -0.169 pll_clk.u_rst_mlkem/Q[0]
|
|
SLICE_X118Y67 LUT1 (Prop_lut1_I0_O) 0.045 -0.124 f pll_clk.u_rst_mlkem/rdb_addr[11]_i_2/O
|
|
net (fo=1069, routed) 0.258 0.134 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/pre_addr_l_reg[2]_rep__1_0
|
|
SLICE_X123Y68 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/pre_addr_l_reg[11]/CLR
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock mlkem_clk_clk_pll rise edge)
|
|
0.000 0.000 r
|
|
K21 0.000 0.000 r clk (IN)
|
|
net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1
|
|
K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O
|
|
net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll
|
|
PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2)
|
|
-2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2
|
|
net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll
|
|
BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout3_buf/O
|
|
net (fo=26129, routed) 0.927 -0.381 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/mlkem_clk
|
|
SLICE_X123Y68 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/pre_addr_l_reg[11]/C
|
|
clock pessimism -0.192 -0.573
|
|
SLICE_X123Y68 FDCE (Remov_fdce_C_CLR) -0.092 -0.665 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/pre_addr_l_reg[11]
|
|
-------------------------------------------------------------------
|
|
required time 0.665
|
|
arrival time 0.134
|
|
-------------------------------------------------------------------
|
|
slack 0.799
|
|
|
|
Slack (MET) : 0.799ns (arrival time - required time)
|
|
Source: pll_clk.u_rst_mlkem/delay_reg[1]/C
|
|
(rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns})
|
|
Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/pre_addr_l_reg[8]/CLR
|
|
(removal check against rising-edge clock mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns})
|
|
Path Group: **async_default**
|
|
Path Type: Removal (Min at Fast Process Corner)
|
|
Requirement: 0.000ns (mlkem_clk_clk_pll rise@0.000ns - mlkem_clk_clk_pll rise@0.000ns)
|
|
Data Path Delay: 0.741ns (logic 0.186ns (25.097%) route 0.555ns (74.903%))
|
|
Logic Levels: 1 (LUT1=1)
|
|
Clock Path Skew: 0.034ns (DCD - SCD - CPR)
|
|
Destination Clock Delay (DCD): -0.381ns
|
|
Source Clock Delay (SCD): -0.607ns
|
|
Clock Pessimism Removal (CPR): 0.192ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock mlkem_clk_clk_pll rise edge)
|
|
0.000 0.000 r
|
|
K21 0.000 0.000 r clk (IN)
|
|
net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1
|
|
K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O
|
|
net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll
|
|
PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2)
|
|
-2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2
|
|
net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll
|
|
BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout3_buf/O
|
|
net (fo=26129, routed) 0.655 -0.607 pll_clk.u_rst_mlkem/mlkem_clk
|
|
SLICE_X118Y67 FDCE r pll_clk.u_rst_mlkem/delay_reg[1]/C
|
|
------------------------------------------------------------------- -------------------
|
|
SLICE_X118Y67 FDCE (Prop_fdce_C_Q) 0.141 -0.466 r pll_clk.u_rst_mlkem/delay_reg[1]/Q
|
|
net (fo=4, routed) 0.297 -0.169 pll_clk.u_rst_mlkem/Q[0]
|
|
SLICE_X118Y67 LUT1 (Prop_lut1_I0_O) 0.045 -0.124 f pll_clk.u_rst_mlkem/rdb_addr[11]_i_2/O
|
|
net (fo=1069, routed) 0.258 0.134 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/pre_addr_l_reg[2]_rep__1_0
|
|
SLICE_X123Y68 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/pre_addr_l_reg[8]/CLR
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock mlkem_clk_clk_pll rise edge)
|
|
0.000 0.000 r
|
|
K21 0.000 0.000 r clk (IN)
|
|
net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1
|
|
K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O
|
|
net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll
|
|
PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2)
|
|
-2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2
|
|
net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll
|
|
BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout3_buf/O
|
|
net (fo=26129, routed) 0.927 -0.381 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/mlkem_clk
|
|
SLICE_X123Y68 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/pre_addr_l_reg[8]/C
|
|
clock pessimism -0.192 -0.573
|
|
SLICE_X123Y68 FDCE (Remov_fdce_C_CLR) -0.092 -0.665 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/pre_addr_l_reg[8]
|
|
-------------------------------------------------------------------
|
|
required time 0.665
|
|
arrival time 0.134
|
|
-------------------------------------------------------------------
|
|
slack 0.799
|
|
|
|
Slack (MET) : 0.799ns (arrival time - required time)
|
|
Source: pll_clk.u_rst_mlkem/delay_reg[1]/C
|
|
(rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns})
|
|
Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/pre_addr_l_reg[9]/CLR
|
|
(removal check against rising-edge clock mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns})
|
|
Path Group: **async_default**
|
|
Path Type: Removal (Min at Fast Process Corner)
|
|
Requirement: 0.000ns (mlkem_clk_clk_pll rise@0.000ns - mlkem_clk_clk_pll rise@0.000ns)
|
|
Data Path Delay: 0.741ns (logic 0.186ns (25.097%) route 0.555ns (74.903%))
|
|
Logic Levels: 1 (LUT1=1)
|
|
Clock Path Skew: 0.034ns (DCD - SCD - CPR)
|
|
Destination Clock Delay (DCD): -0.381ns
|
|
Source Clock Delay (SCD): -0.607ns
|
|
Clock Pessimism Removal (CPR): 0.192ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock mlkem_clk_clk_pll rise edge)
|
|
0.000 0.000 r
|
|
K21 0.000 0.000 r clk (IN)
|
|
net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1
|
|
K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O
|
|
net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll
|
|
PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2)
|
|
-2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2
|
|
net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll
|
|
BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout3_buf/O
|
|
net (fo=26129, routed) 0.655 -0.607 pll_clk.u_rst_mlkem/mlkem_clk
|
|
SLICE_X118Y67 FDCE r pll_clk.u_rst_mlkem/delay_reg[1]/C
|
|
------------------------------------------------------------------- -------------------
|
|
SLICE_X118Y67 FDCE (Prop_fdce_C_Q) 0.141 -0.466 r pll_clk.u_rst_mlkem/delay_reg[1]/Q
|
|
net (fo=4, routed) 0.297 -0.169 pll_clk.u_rst_mlkem/Q[0]
|
|
SLICE_X118Y67 LUT1 (Prop_lut1_I0_O) 0.045 -0.124 f pll_clk.u_rst_mlkem/rdb_addr[11]_i_2/O
|
|
net (fo=1069, routed) 0.258 0.134 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/pre_addr_l_reg[2]_rep__1_0
|
|
SLICE_X123Y68 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/pre_addr_l_reg[9]/CLR
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock mlkem_clk_clk_pll rise edge)
|
|
0.000 0.000 r
|
|
K21 0.000 0.000 r clk (IN)
|
|
net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1
|
|
K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O
|
|
net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll
|
|
PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2)
|
|
-2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2
|
|
net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll
|
|
BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout3_buf/O
|
|
net (fo=26129, routed) 0.927 -0.381 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/mlkem_clk
|
|
SLICE_X123Y68 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/pre_addr_l_reg[9]/C
|
|
clock pessimism -0.192 -0.573
|
|
SLICE_X123Y68 FDCE (Remov_fdce_C_CLR) -0.092 -0.665 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/pre_addr_l_reg[9]
|
|
-------------------------------------------------------------------
|
|
required time 0.665
|
|
arrival time 0.134
|
|
-------------------------------------------------------------------
|
|
slack 0.799
|
|
|
|
Slack (MET) : 0.799ns (arrival time - required time)
|
|
Source: pll_clk.u_rst_mlkem/delay_reg[1]/C
|
|
(rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns})
|
|
Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/stream_wdata_reg[11]/CLR
|
|
(removal check against rising-edge clock mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns})
|
|
Path Group: **async_default**
|
|
Path Type: Removal (Min at Fast Process Corner)
|
|
Requirement: 0.000ns (mlkem_clk_clk_pll rise@0.000ns - mlkem_clk_clk_pll rise@0.000ns)
|
|
Data Path Delay: 0.765ns (logic 0.186ns (24.299%) route 0.579ns (75.701%))
|
|
Logic Levels: 1 (LUT1=1)
|
|
Clock Path Skew: 0.033ns (DCD - SCD - CPR)
|
|
Destination Clock Delay (DCD): -0.382ns
|
|
Source Clock Delay (SCD): -0.607ns
|
|
Clock Pessimism Removal (CPR): 0.192ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock mlkem_clk_clk_pll rise edge)
|
|
0.000 0.000 r
|
|
K21 0.000 0.000 r clk (IN)
|
|
net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1
|
|
K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O
|
|
net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll
|
|
PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2)
|
|
-2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2
|
|
net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll
|
|
BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout3_buf/O
|
|
net (fo=26129, routed) 0.655 -0.607 pll_clk.u_rst_mlkem/mlkem_clk
|
|
SLICE_X118Y67 FDCE r pll_clk.u_rst_mlkem/delay_reg[1]/C
|
|
------------------------------------------------------------------- -------------------
|
|
SLICE_X118Y67 FDCE (Prop_fdce_C_Q) 0.141 -0.466 r pll_clk.u_rst_mlkem/delay_reg[1]/Q
|
|
net (fo=4, routed) 0.297 -0.169 pll_clk.u_rst_mlkem/Q[0]
|
|
SLICE_X118Y67 LUT1 (Prop_lut1_I0_O) 0.045 -0.124 f pll_clk.u_rst_mlkem/rdb_addr[11]_i_2/O
|
|
net (fo=1069, routed) 0.282 0.158 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/pre_addr_l_reg[2]_rep__1_0
|
|
SLICE_X120Y69 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/stream_wdata_reg[11]/CLR
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock mlkem_clk_clk_pll rise edge)
|
|
0.000 0.000 r
|
|
K21 0.000 0.000 r clk (IN)
|
|
net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1
|
|
K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O
|
|
net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll
|
|
PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2)
|
|
-2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2
|
|
net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll
|
|
BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout3_buf/O
|
|
net (fo=26129, routed) 0.926 -0.382 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/mlkem_clk
|
|
SLICE_X120Y69 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/stream_wdata_reg[11]/C
|
|
clock pessimism -0.192 -0.574
|
|
SLICE_X120Y69 FDCE (Remov_fdce_C_CLR) -0.067 -0.641 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/stream_wdata_reg[11]
|
|
-------------------------------------------------------------------
|
|
required time 0.641
|
|
arrival time 0.158
|
|
-------------------------------------------------------------------
|
|
slack 0.799
|
|
|
|
Slack (MET) : 0.799ns (arrival time - required time)
|
|
Source: pll_clk.u_rst_mlkem/delay_reg[1]/C
|
|
(rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns})
|
|
Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/stream_wdata_reg[19]/CLR
|
|
(removal check against rising-edge clock mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns})
|
|
Path Group: **async_default**
|
|
Path Type: Removal (Min at Fast Process Corner)
|
|
Requirement: 0.000ns (mlkem_clk_clk_pll rise@0.000ns - mlkem_clk_clk_pll rise@0.000ns)
|
|
Data Path Delay: 0.765ns (logic 0.186ns (24.299%) route 0.579ns (75.701%))
|
|
Logic Levels: 1 (LUT1=1)
|
|
Clock Path Skew: 0.033ns (DCD - SCD - CPR)
|
|
Destination Clock Delay (DCD): -0.382ns
|
|
Source Clock Delay (SCD): -0.607ns
|
|
Clock Pessimism Removal (CPR): 0.192ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock mlkem_clk_clk_pll rise edge)
|
|
0.000 0.000 r
|
|
K21 0.000 0.000 r clk (IN)
|
|
net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1
|
|
K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O
|
|
net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll
|
|
PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2)
|
|
-2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2
|
|
net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll
|
|
BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout3_buf/O
|
|
net (fo=26129, routed) 0.655 -0.607 pll_clk.u_rst_mlkem/mlkem_clk
|
|
SLICE_X118Y67 FDCE r pll_clk.u_rst_mlkem/delay_reg[1]/C
|
|
------------------------------------------------------------------- -------------------
|
|
SLICE_X118Y67 FDCE (Prop_fdce_C_Q) 0.141 -0.466 r pll_clk.u_rst_mlkem/delay_reg[1]/Q
|
|
net (fo=4, routed) 0.297 -0.169 pll_clk.u_rst_mlkem/Q[0]
|
|
SLICE_X118Y67 LUT1 (Prop_lut1_I0_O) 0.045 -0.124 f pll_clk.u_rst_mlkem/rdb_addr[11]_i_2/O
|
|
net (fo=1069, routed) 0.282 0.158 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/pre_addr_l_reg[2]_rep__1_0
|
|
SLICE_X120Y69 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/stream_wdata_reg[19]/CLR
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock mlkem_clk_clk_pll rise edge)
|
|
0.000 0.000 r
|
|
K21 0.000 0.000 r clk (IN)
|
|
net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1
|
|
K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O
|
|
net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll
|
|
PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2)
|
|
-2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2
|
|
net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll
|
|
BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout3_buf/O
|
|
net (fo=26129, routed) 0.926 -0.382 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/mlkem_clk
|
|
SLICE_X120Y69 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/stream_wdata_reg[19]/C
|
|
clock pessimism -0.192 -0.574
|
|
SLICE_X120Y69 FDCE (Remov_fdce_C_CLR) -0.067 -0.641 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/stream_wdata_reg[19]
|
|
-------------------------------------------------------------------
|
|
required time 0.641
|
|
arrival time 0.158
|
|
-------------------------------------------------------------------
|
|
slack 0.799
|
|
|
|
Slack (MET) : 0.799ns (arrival time - required time)
|
|
Source: pll_clk.u_rst_mlkem/delay_reg[1]/C
|
|
(rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns})
|
|
Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/stream_wdata_reg[27]/CLR
|
|
(removal check against rising-edge clock mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns})
|
|
Path Group: **async_default**
|
|
Path Type: Removal (Min at Fast Process Corner)
|
|
Requirement: 0.000ns (mlkem_clk_clk_pll rise@0.000ns - mlkem_clk_clk_pll rise@0.000ns)
|
|
Data Path Delay: 0.765ns (logic 0.186ns (24.299%) route 0.579ns (75.701%))
|
|
Logic Levels: 1 (LUT1=1)
|
|
Clock Path Skew: 0.033ns (DCD - SCD - CPR)
|
|
Destination Clock Delay (DCD): -0.382ns
|
|
Source Clock Delay (SCD): -0.607ns
|
|
Clock Pessimism Removal (CPR): 0.192ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock mlkem_clk_clk_pll rise edge)
|
|
0.000 0.000 r
|
|
K21 0.000 0.000 r clk (IN)
|
|
net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1
|
|
K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O
|
|
net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll
|
|
PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2)
|
|
-2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2
|
|
net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll
|
|
BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout3_buf/O
|
|
net (fo=26129, routed) 0.655 -0.607 pll_clk.u_rst_mlkem/mlkem_clk
|
|
SLICE_X118Y67 FDCE r pll_clk.u_rst_mlkem/delay_reg[1]/C
|
|
------------------------------------------------------------------- -------------------
|
|
SLICE_X118Y67 FDCE (Prop_fdce_C_Q) 0.141 -0.466 r pll_clk.u_rst_mlkem/delay_reg[1]/Q
|
|
net (fo=4, routed) 0.297 -0.169 pll_clk.u_rst_mlkem/Q[0]
|
|
SLICE_X118Y67 LUT1 (Prop_lut1_I0_O) 0.045 -0.124 f pll_clk.u_rst_mlkem/rdb_addr[11]_i_2/O
|
|
net (fo=1069, routed) 0.282 0.158 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/pre_addr_l_reg[2]_rep__1_0
|
|
SLICE_X120Y69 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/stream_wdata_reg[27]/CLR
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock mlkem_clk_clk_pll rise edge)
|
|
0.000 0.000 r
|
|
K21 0.000 0.000 r clk (IN)
|
|
net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1
|
|
K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O
|
|
net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll
|
|
PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2)
|
|
-2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2
|
|
net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll
|
|
BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout3_buf/O
|
|
net (fo=26129, routed) 0.926 -0.382 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/mlkem_clk
|
|
SLICE_X120Y69 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/stream_wdata_reg[27]/C
|
|
clock pessimism -0.192 -0.574
|
|
SLICE_X120Y69 FDCE (Remov_fdce_C_CLR) -0.067 -0.641 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/stream_wdata_reg[27]
|
|
-------------------------------------------------------------------
|
|
required time 0.641
|
|
arrival time 0.158
|
|
-------------------------------------------------------------------
|
|
slack 0.799
|
|
|
|
Slack (MET) : 0.799ns (arrival time - required time)
|
|
Source: pll_clk.u_rst_mlkem/delay_reg[1]/C
|
|
(rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns})
|
|
Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/stream_wdata_reg[28]/CLR
|
|
(removal check against rising-edge clock mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns})
|
|
Path Group: **async_default**
|
|
Path Type: Removal (Min at Fast Process Corner)
|
|
Requirement: 0.000ns (mlkem_clk_clk_pll rise@0.000ns - mlkem_clk_clk_pll rise@0.000ns)
|
|
Data Path Delay: 0.765ns (logic 0.186ns (24.299%) route 0.579ns (75.701%))
|
|
Logic Levels: 1 (LUT1=1)
|
|
Clock Path Skew: 0.033ns (DCD - SCD - CPR)
|
|
Destination Clock Delay (DCD): -0.382ns
|
|
Source Clock Delay (SCD): -0.607ns
|
|
Clock Pessimism Removal (CPR): 0.192ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock mlkem_clk_clk_pll rise edge)
|
|
0.000 0.000 r
|
|
K21 0.000 0.000 r clk (IN)
|
|
net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1
|
|
K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O
|
|
net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll
|
|
PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2)
|
|
-2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2
|
|
net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll
|
|
BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout3_buf/O
|
|
net (fo=26129, routed) 0.655 -0.607 pll_clk.u_rst_mlkem/mlkem_clk
|
|
SLICE_X118Y67 FDCE r pll_clk.u_rst_mlkem/delay_reg[1]/C
|
|
------------------------------------------------------------------- -------------------
|
|
SLICE_X118Y67 FDCE (Prop_fdce_C_Q) 0.141 -0.466 r pll_clk.u_rst_mlkem/delay_reg[1]/Q
|
|
net (fo=4, routed) 0.297 -0.169 pll_clk.u_rst_mlkem/Q[0]
|
|
SLICE_X118Y67 LUT1 (Prop_lut1_I0_O) 0.045 -0.124 f pll_clk.u_rst_mlkem/rdb_addr[11]_i_2/O
|
|
net (fo=1069, routed) 0.282 0.158 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/pre_addr_l_reg[2]_rep__1_0
|
|
SLICE_X120Y69 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/stream_wdata_reg[28]/CLR
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock mlkem_clk_clk_pll rise edge)
|
|
0.000 0.000 r
|
|
K21 0.000 0.000 r clk (IN)
|
|
net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1
|
|
K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O
|
|
net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll
|
|
PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2)
|
|
-2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2
|
|
net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll
|
|
BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout3_buf/O
|
|
net (fo=26129, routed) 0.926 -0.382 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/mlkem_clk
|
|
SLICE_X120Y69 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/stream_wdata_reg[28]/C
|
|
clock pessimism -0.192 -0.574
|
|
SLICE_X120Y69 FDCE (Remov_fdce_C_CLR) -0.067 -0.641 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/stream_wdata_reg[28]
|
|
-------------------------------------------------------------------
|
|
required time 0.641
|
|
arrival time 0.158
|
|
-------------------------------------------------------------------
|
|
slack 0.799
|
|
|
|
Slack (MET) : 0.799ns (arrival time - required time)
|
|
Source: pll_clk.u_rst_mlkem/delay_reg[1]/C
|
|
(rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns})
|
|
Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/stream_wdata_reg[30]/CLR
|
|
(removal check against rising-edge clock mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns})
|
|
Path Group: **async_default**
|
|
Path Type: Removal (Min at Fast Process Corner)
|
|
Requirement: 0.000ns (mlkem_clk_clk_pll rise@0.000ns - mlkem_clk_clk_pll rise@0.000ns)
|
|
Data Path Delay: 0.765ns (logic 0.186ns (24.299%) route 0.579ns (75.701%))
|
|
Logic Levels: 1 (LUT1=1)
|
|
Clock Path Skew: 0.033ns (DCD - SCD - CPR)
|
|
Destination Clock Delay (DCD): -0.382ns
|
|
Source Clock Delay (SCD): -0.607ns
|
|
Clock Pessimism Removal (CPR): 0.192ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock mlkem_clk_clk_pll rise edge)
|
|
0.000 0.000 r
|
|
K21 0.000 0.000 r clk (IN)
|
|
net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1
|
|
K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O
|
|
net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll
|
|
PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2)
|
|
-2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2
|
|
net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll
|
|
BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout3_buf/O
|
|
net (fo=26129, routed) 0.655 -0.607 pll_clk.u_rst_mlkem/mlkem_clk
|
|
SLICE_X118Y67 FDCE r pll_clk.u_rst_mlkem/delay_reg[1]/C
|
|
------------------------------------------------------------------- -------------------
|
|
SLICE_X118Y67 FDCE (Prop_fdce_C_Q) 0.141 -0.466 r pll_clk.u_rst_mlkem/delay_reg[1]/Q
|
|
net (fo=4, routed) 0.297 -0.169 pll_clk.u_rst_mlkem/Q[0]
|
|
SLICE_X118Y67 LUT1 (Prop_lut1_I0_O) 0.045 -0.124 f pll_clk.u_rst_mlkem/rdb_addr[11]_i_2/O
|
|
net (fo=1069, routed) 0.282 0.158 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/pre_addr_l_reg[2]_rep__1_0
|
|
SLICE_X120Y69 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/stream_wdata_reg[30]/CLR
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock mlkem_clk_clk_pll rise edge)
|
|
0.000 0.000 r
|
|
K21 0.000 0.000 r clk (IN)
|
|
net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1
|
|
K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O
|
|
net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll
|
|
PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2)
|
|
-2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2
|
|
net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll
|
|
BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout3_buf/O
|
|
net (fo=26129, routed) 0.926 -0.382 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/mlkem_clk
|
|
SLICE_X120Y69 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/stream_wdata_reg[30]/C
|
|
clock pessimism -0.192 -0.574
|
|
SLICE_X120Y69 FDCE (Remov_fdce_C_CLR) -0.067 -0.641 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/stream_wdata_reg[30]
|
|
-------------------------------------------------------------------
|
|
required time 0.641
|
|
arrival time 0.158
|
|
-------------------------------------------------------------------
|
|
slack 0.799
|
|
|
|
Slack (MET) : 0.799ns (arrival time - required time)
|
|
Source: pll_clk.u_rst_mlkem/delay_reg[1]/C
|
|
(rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns})
|
|
Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/stream_wdata_reg[3]/CLR
|
|
(removal check against rising-edge clock mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns})
|
|
Path Group: **async_default**
|
|
Path Type: Removal (Min at Fast Process Corner)
|
|
Requirement: 0.000ns (mlkem_clk_clk_pll rise@0.000ns - mlkem_clk_clk_pll rise@0.000ns)
|
|
Data Path Delay: 0.765ns (logic 0.186ns (24.299%) route 0.579ns (75.701%))
|
|
Logic Levels: 1 (LUT1=1)
|
|
Clock Path Skew: 0.033ns (DCD - SCD - CPR)
|
|
Destination Clock Delay (DCD): -0.382ns
|
|
Source Clock Delay (SCD): -0.607ns
|
|
Clock Pessimism Removal (CPR): 0.192ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock mlkem_clk_clk_pll rise edge)
|
|
0.000 0.000 r
|
|
K21 0.000 0.000 r clk (IN)
|
|
net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1
|
|
K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O
|
|
net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll
|
|
PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2)
|
|
-2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2
|
|
net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll
|
|
BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout3_buf/O
|
|
net (fo=26129, routed) 0.655 -0.607 pll_clk.u_rst_mlkem/mlkem_clk
|
|
SLICE_X118Y67 FDCE r pll_clk.u_rst_mlkem/delay_reg[1]/C
|
|
------------------------------------------------------------------- -------------------
|
|
SLICE_X118Y67 FDCE (Prop_fdce_C_Q) 0.141 -0.466 r pll_clk.u_rst_mlkem/delay_reg[1]/Q
|
|
net (fo=4, routed) 0.297 -0.169 pll_clk.u_rst_mlkem/Q[0]
|
|
SLICE_X118Y67 LUT1 (Prop_lut1_I0_O) 0.045 -0.124 f pll_clk.u_rst_mlkem/rdb_addr[11]_i_2/O
|
|
net (fo=1069, routed) 0.282 0.158 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/pre_addr_l_reg[2]_rep__1_0
|
|
SLICE_X120Y69 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/stream_wdata_reg[3]/CLR
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock mlkem_clk_clk_pll rise edge)
|
|
0.000 0.000 r
|
|
K21 0.000 0.000 r clk (IN)
|
|
net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1
|
|
K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O
|
|
net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll
|
|
PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2)
|
|
-2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2
|
|
net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll
|
|
BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout3_buf/O
|
|
net (fo=26129, routed) 0.926 -0.382 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/mlkem_clk
|
|
SLICE_X120Y69 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/stream_wdata_reg[3]/C
|
|
clock pessimism -0.192 -0.574
|
|
SLICE_X120Y69 FDCE (Remov_fdce_C_CLR) -0.067 -0.641 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/stream_wdata_reg[3]
|
|
-------------------------------------------------------------------
|
|
required time 0.641
|
|
arrival time 0.158
|
|
-------------------------------------------------------------------
|
|
slack 0.799
|
|
|
|
Slack (MET) : 0.799ns (arrival time - required time)
|
|
Source: pll_clk.u_rst_mlkem/delay_reg[1]/C
|
|
(rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns})
|
|
Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/stream_wdata_reg[4]/CLR
|
|
(removal check against rising-edge clock mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns})
|
|
Path Group: **async_default**
|
|
Path Type: Removal (Min at Fast Process Corner)
|
|
Requirement: 0.000ns (mlkem_clk_clk_pll rise@0.000ns - mlkem_clk_clk_pll rise@0.000ns)
|
|
Data Path Delay: 0.765ns (logic 0.186ns (24.299%) route 0.579ns (75.701%))
|
|
Logic Levels: 1 (LUT1=1)
|
|
Clock Path Skew: 0.033ns (DCD - SCD - CPR)
|
|
Destination Clock Delay (DCD): -0.382ns
|
|
Source Clock Delay (SCD): -0.607ns
|
|
Clock Pessimism Removal (CPR): 0.192ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock mlkem_clk_clk_pll rise edge)
|
|
0.000 0.000 r
|
|
K21 0.000 0.000 r clk (IN)
|
|
net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1
|
|
K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O
|
|
net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll
|
|
PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2)
|
|
-2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2
|
|
net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll
|
|
BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout3_buf/O
|
|
net (fo=26129, routed) 0.655 -0.607 pll_clk.u_rst_mlkem/mlkem_clk
|
|
SLICE_X118Y67 FDCE r pll_clk.u_rst_mlkem/delay_reg[1]/C
|
|
------------------------------------------------------------------- -------------------
|
|
SLICE_X118Y67 FDCE (Prop_fdce_C_Q) 0.141 -0.466 r pll_clk.u_rst_mlkem/delay_reg[1]/Q
|
|
net (fo=4, routed) 0.297 -0.169 pll_clk.u_rst_mlkem/Q[0]
|
|
SLICE_X118Y67 LUT1 (Prop_lut1_I0_O) 0.045 -0.124 f pll_clk.u_rst_mlkem/rdb_addr[11]_i_2/O
|
|
net (fo=1069, routed) 0.282 0.158 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/pre_addr_l_reg[2]_rep__1_0
|
|
SLICE_X120Y69 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/stream_wdata_reg[4]/CLR
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock mlkem_clk_clk_pll rise edge)
|
|
0.000 0.000 r
|
|
K21 0.000 0.000 r clk (IN)
|
|
net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1
|
|
K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O
|
|
net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll
|
|
PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2)
|
|
-2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2
|
|
net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll
|
|
BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout3_buf/O
|
|
net (fo=26129, routed) 0.926 -0.382 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/mlkem_clk
|
|
SLICE_X120Y69 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/stream_wdata_reg[4]/C
|
|
clock pessimism -0.192 -0.574
|
|
SLICE_X120Y69 FDCE (Remov_fdce_C_CLR) -0.067 -0.641 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/stream_wdata_reg[4]
|
|
-------------------------------------------------------------------
|
|
required time 0.641
|
|
arrival time 0.158
|
|
-------------------------------------------------------------------
|
|
slack 0.799
|
|
|
|
Slack (MET) : 0.824ns (arrival time - required time)
|
|
Source: pll_clk.u_rst_mlkem/delay_reg[1]/C
|
|
(rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns})
|
|
Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/stream_lane_reg[0]/CLR
|
|
(removal check against rising-edge clock mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns})
|
|
Path Group: **async_default**
|
|
Path Type: Removal (Min at Fast Process Corner)
|
|
Requirement: 0.000ns (mlkem_clk_clk_pll rise@0.000ns - mlkem_clk_clk_pll rise@0.000ns)
|
|
Data Path Delay: 0.765ns (logic 0.186ns (24.299%) route 0.579ns (75.701%))
|
|
Logic Levels: 1 (LUT1=1)
|
|
Clock Path Skew: 0.033ns (DCD - SCD - CPR)
|
|
Destination Clock Delay (DCD): -0.382ns
|
|
Source Clock Delay (SCD): -0.607ns
|
|
Clock Pessimism Removal (CPR): 0.192ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock mlkem_clk_clk_pll rise edge)
|
|
0.000 0.000 r
|
|
K21 0.000 0.000 r clk (IN)
|
|
net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1
|
|
K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O
|
|
net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll
|
|
PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2)
|
|
-2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2
|
|
net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll
|
|
BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout3_buf/O
|
|
net (fo=26129, routed) 0.655 -0.607 pll_clk.u_rst_mlkem/mlkem_clk
|
|
SLICE_X118Y67 FDCE r pll_clk.u_rst_mlkem/delay_reg[1]/C
|
|
------------------------------------------------------------------- -------------------
|
|
SLICE_X118Y67 FDCE (Prop_fdce_C_Q) 0.141 -0.466 r pll_clk.u_rst_mlkem/delay_reg[1]/Q
|
|
net (fo=4, routed) 0.297 -0.169 pll_clk.u_rst_mlkem/Q[0]
|
|
SLICE_X118Y67 LUT1 (Prop_lut1_I0_O) 0.045 -0.124 f pll_clk.u_rst_mlkem/rdb_addr[11]_i_2/O
|
|
net (fo=1069, routed) 0.282 0.158 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/pre_addr_l_reg[2]_rep__1_0
|
|
SLICE_X121Y69 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/stream_lane_reg[0]/CLR
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock mlkem_clk_clk_pll rise edge)
|
|
0.000 0.000 r
|
|
K21 0.000 0.000 r clk (IN)
|
|
net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1
|
|
K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O
|
|
net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll
|
|
PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2)
|
|
-2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2
|
|
net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll
|
|
BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout3_buf/O
|
|
net (fo=26129, routed) 0.926 -0.382 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/mlkem_clk
|
|
SLICE_X121Y69 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/stream_lane_reg[0]/C
|
|
clock pessimism -0.192 -0.574
|
|
SLICE_X121Y69 FDCE (Remov_fdce_C_CLR) -0.092 -0.666 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/stream_lane_reg[0]
|
|
-------------------------------------------------------------------
|
|
required time 0.666
|
|
arrival time 0.158
|
|
-------------------------------------------------------------------
|
|
slack 0.824
|
|
|
|
Slack (MET) : 0.827ns (arrival time - required time)
|
|
Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/buffers_1_reg/C
|
|
(rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns})
|
|
Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/popCC_ptrToPush_reg[1]/CLR
|
|
(removal check against rising-edge clock mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns})
|
|
Path Group: **async_default**
|
|
Path Type: Removal (Min at Fast Process Corner)
|
|
Requirement: 0.000ns (mlkem_clk_clk_pll rise@0.000ns - mlkem_clk_clk_pll rise@0.000ns)
|
|
Data Path Delay: 0.764ns (logic 0.227ns (29.725%) route 0.537ns (70.275%))
|
|
Logic Levels: 1 (LUT1=1)
|
|
Clock Path Skew: 0.029ns (DCD - SCD - CPR)
|
|
Destination Clock Delay (DCD): -0.360ns
|
|
Source Clock Delay (SCD): -0.581ns
|
|
Clock Pessimism Removal (CPR): 0.192ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock mlkem_clk_clk_pll rise edge)
|
|
0.000 0.000 r
|
|
K21 0.000 0.000 r clk (IN)
|
|
net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1
|
|
K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O
|
|
net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll
|
|
PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2)
|
|
-2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2
|
|
net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll
|
|
BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout3_buf/O
|
|
net (fo=26129, routed) 0.681 -0.581 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/mlkem_clk
|
|
SLICE_X25Y79 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/buffers_1_reg/C
|
|
------------------------------------------------------------------- -------------------
|
|
SLICE_X25Y79 FDCE (Prop_fdce_C_Q) 0.128 -0.453 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/buffers_1_reg/Q
|
|
net (fo=1, routed) 0.139 -0.314 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/buffers_1
|
|
SLICE_X25Y79 LUT1 (Prop_lut1_I0_O) 0.099 -0.215 f u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/popCC_popPtr[2]_i_2__1/O
|
|
net (fo=43, routed) 0.397 0.182 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/buffers_1_reg
|
|
SLICE_X31Y74 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/popCC_ptrToPush_reg[1]/CLR
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock mlkem_clk_clk_pll rise edge)
|
|
0.000 0.000 r
|
|
K21 0.000 0.000 r clk (IN)
|
|
net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1
|
|
K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O
|
|
net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll
|
|
PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2)
|
|
-2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2
|
|
net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll
|
|
BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout3_buf/O
|
|
net (fo=26129, routed) 0.948 -0.360 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/mlkem_clk
|
|
SLICE_X31Y74 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/popCC_ptrToPush_reg[1]/C
|
|
clock pessimism -0.192 -0.552
|
|
SLICE_X31Y74 FDCE (Remov_fdce_C_CLR) -0.092 -0.644 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/popCC_ptrToPush_reg[1]
|
|
-------------------------------------------------------------------
|
|
required time 0.644
|
|
arrival time 0.182
|
|
-------------------------------------------------------------------
|
|
slack 0.827
|
|
|
|
Slack (MET) : 0.827ns (arrival time - required time)
|
|
Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/buffers_1_reg/C
|
|
(rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns})
|
|
Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/popCC_ptrToPush_reg[2]/CLR
|
|
(removal check against rising-edge clock mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns})
|
|
Path Group: **async_default**
|
|
Path Type: Removal (Min at Fast Process Corner)
|
|
Requirement: 0.000ns (mlkem_clk_clk_pll rise@0.000ns - mlkem_clk_clk_pll rise@0.000ns)
|
|
Data Path Delay: 0.764ns (logic 0.227ns (29.725%) route 0.537ns (70.275%))
|
|
Logic Levels: 1 (LUT1=1)
|
|
Clock Path Skew: 0.029ns (DCD - SCD - CPR)
|
|
Destination Clock Delay (DCD): -0.360ns
|
|
Source Clock Delay (SCD): -0.581ns
|
|
Clock Pessimism Removal (CPR): 0.192ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock mlkem_clk_clk_pll rise edge)
|
|
0.000 0.000 r
|
|
K21 0.000 0.000 r clk (IN)
|
|
net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1
|
|
K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O
|
|
net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll
|
|
PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2)
|
|
-2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2
|
|
net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll
|
|
BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout3_buf/O
|
|
net (fo=26129, routed) 0.681 -0.581 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/mlkem_clk
|
|
SLICE_X25Y79 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/buffers_1_reg/C
|
|
------------------------------------------------------------------- -------------------
|
|
SLICE_X25Y79 FDCE (Prop_fdce_C_Q) 0.128 -0.453 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/buffers_1_reg/Q
|
|
net (fo=1, routed) 0.139 -0.314 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/buffers_1
|
|
SLICE_X25Y79 LUT1 (Prop_lut1_I0_O) 0.099 -0.215 f u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/popCC_popPtr[2]_i_2__1/O
|
|
net (fo=43, routed) 0.397 0.182 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/buffers_1_reg
|
|
SLICE_X31Y74 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/popCC_ptrToPush_reg[2]/CLR
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock mlkem_clk_clk_pll rise edge)
|
|
0.000 0.000 r
|
|
K21 0.000 0.000 r clk (IN)
|
|
net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1
|
|
K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O
|
|
net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll
|
|
PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2)
|
|
-2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2
|
|
net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll
|
|
BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout3_buf/O
|
|
net (fo=26129, routed) 0.948 -0.360 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/mlkem_clk
|
|
SLICE_X31Y74 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/popCC_ptrToPush_reg[2]/C
|
|
clock pessimism -0.192 -0.552
|
|
SLICE_X31Y74 FDCE (Remov_fdce_C_CLR) -0.092 -0.644 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/popCC_ptrToPush_reg[2]
|
|
-------------------------------------------------------------------
|
|
required time 0.644
|
|
arrival time 0.182
|
|
-------------------------------------------------------------------
|
|
slack 0.827
|
|
|
|
Slack (MET) : 0.827ns (arrival time - required time)
|
|
Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/buffers_1_reg/C
|
|
(rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns})
|
|
Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/pushToPopGray_buffercc/buffers_0_reg[1]/CLR
|
|
(removal check against rising-edge clock mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns})
|
|
Path Group: **async_default**
|
|
Path Type: Removal (Min at Fast Process Corner)
|
|
Requirement: 0.000ns (mlkem_clk_clk_pll rise@0.000ns - mlkem_clk_clk_pll rise@0.000ns)
|
|
Data Path Delay: 0.764ns (logic 0.227ns (29.725%) route 0.537ns (70.275%))
|
|
Logic Levels: 1 (LUT1=1)
|
|
Clock Path Skew: 0.029ns (DCD - SCD - CPR)
|
|
Destination Clock Delay (DCD): -0.360ns
|
|
Source Clock Delay (SCD): -0.581ns
|
|
Clock Pessimism Removal (CPR): 0.192ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock mlkem_clk_clk_pll rise edge)
|
|
0.000 0.000 r
|
|
K21 0.000 0.000 r clk (IN)
|
|
net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1
|
|
K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O
|
|
net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll
|
|
PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2)
|
|
-2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2
|
|
net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll
|
|
BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout3_buf/O
|
|
net (fo=26129, routed) 0.681 -0.581 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/mlkem_clk
|
|
SLICE_X25Y79 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/buffers_1_reg/C
|
|
------------------------------------------------------------------- -------------------
|
|
SLICE_X25Y79 FDCE (Prop_fdce_C_Q) 0.128 -0.453 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/buffers_1_reg/Q
|
|
net (fo=1, routed) 0.139 -0.314 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/buffers_1
|
|
SLICE_X25Y79 LUT1 (Prop_lut1_I0_O) 0.099 -0.215 f u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/popCC_popPtr[2]_i_2__1/O
|
|
net (fo=43, routed) 0.397 0.182 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/pushToPopGray_buffercc/buffers_0_reg[2]_1
|
|
SLICE_X31Y74 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/pushToPopGray_buffercc/buffers_0_reg[1]/CLR
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock mlkem_clk_clk_pll rise edge)
|
|
0.000 0.000 r
|
|
K21 0.000 0.000 r clk (IN)
|
|
net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1
|
|
K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O
|
|
net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll
|
|
PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2)
|
|
-2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2
|
|
net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll
|
|
BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout3_buf/O
|
|
net (fo=26129, routed) 0.948 -0.360 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/pushToPopGray_buffercc/mlkem_clk
|
|
SLICE_X31Y74 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/pushToPopGray_buffercc/buffers_0_reg[1]/C
|
|
clock pessimism -0.192 -0.552
|
|
SLICE_X31Y74 FDCE (Remov_fdce_C_CLR) -0.092 -0.644 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/pushToPopGray_buffercc/buffers_0_reg[1]
|
|
-------------------------------------------------------------------
|
|
required time 0.644
|
|
arrival time 0.182
|
|
-------------------------------------------------------------------
|
|
slack 0.827
|
|
|
|
Slack (MET) : 0.827ns (arrival time - required time)
|
|
Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/buffers_1_reg/C
|
|
(rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns})
|
|
Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/pushToPopGray_buffercc/buffers_0_reg[2]/CLR
|
|
(removal check against rising-edge clock mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns})
|
|
Path Group: **async_default**
|
|
Path Type: Removal (Min at Fast Process Corner)
|
|
Requirement: 0.000ns (mlkem_clk_clk_pll rise@0.000ns - mlkem_clk_clk_pll rise@0.000ns)
|
|
Data Path Delay: 0.764ns (logic 0.227ns (29.725%) route 0.537ns (70.275%))
|
|
Logic Levels: 1 (LUT1=1)
|
|
Clock Path Skew: 0.029ns (DCD - SCD - CPR)
|
|
Destination Clock Delay (DCD): -0.360ns
|
|
Source Clock Delay (SCD): -0.581ns
|
|
Clock Pessimism Removal (CPR): 0.192ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock mlkem_clk_clk_pll rise edge)
|
|
0.000 0.000 r
|
|
K21 0.000 0.000 r clk (IN)
|
|
net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1
|
|
K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O
|
|
net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll
|
|
PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2)
|
|
-2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2
|
|
net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll
|
|
BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout3_buf/O
|
|
net (fo=26129, routed) 0.681 -0.581 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/mlkem_clk
|
|
SLICE_X25Y79 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/buffers_1_reg/C
|
|
------------------------------------------------------------------- -------------------
|
|
SLICE_X25Y79 FDCE (Prop_fdce_C_Q) 0.128 -0.453 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/buffers_1_reg/Q
|
|
net (fo=1, routed) 0.139 -0.314 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/buffers_1
|
|
SLICE_X25Y79 LUT1 (Prop_lut1_I0_O) 0.099 -0.215 f u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/popCC_popPtr[2]_i_2__1/O
|
|
net (fo=43, routed) 0.397 0.182 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/pushToPopGray_buffercc/buffers_0_reg[2]_1
|
|
SLICE_X31Y74 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/pushToPopGray_buffercc/buffers_0_reg[2]/CLR
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock mlkem_clk_clk_pll rise edge)
|
|
0.000 0.000 r
|
|
K21 0.000 0.000 r clk (IN)
|
|
net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1
|
|
K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O
|
|
net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll
|
|
PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2)
|
|
-2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2
|
|
net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll
|
|
BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout3_buf/O
|
|
net (fo=26129, routed) 0.948 -0.360 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/pushToPopGray_buffercc/mlkem_clk
|
|
SLICE_X31Y74 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/pushToPopGray_buffercc/buffers_0_reg[2]/C
|
|
clock pessimism -0.192 -0.552
|
|
SLICE_X31Y74 FDCE (Remov_fdce_C_CLR) -0.092 -0.644 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/pushToPopGray_buffercc/buffers_0_reg[2]
|
|
-------------------------------------------------------------------
|
|
required time 0.644
|
|
arrival time 0.182
|
|
-------------------------------------------------------------------
|
|
slack 0.827
|
|
|
|
Slack (MET) : 0.827ns (arrival time - required time)
|
|
Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/buffers_1_reg/C
|
|
(rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns})
|
|
Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/pushToPopGray_buffercc/buffers_1_reg[1]/CLR
|
|
(removal check against rising-edge clock mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns})
|
|
Path Group: **async_default**
|
|
Path Type: Removal (Min at Fast Process Corner)
|
|
Requirement: 0.000ns (mlkem_clk_clk_pll rise@0.000ns - mlkem_clk_clk_pll rise@0.000ns)
|
|
Data Path Delay: 0.764ns (logic 0.227ns (29.725%) route 0.537ns (70.275%))
|
|
Logic Levels: 1 (LUT1=1)
|
|
Clock Path Skew: 0.029ns (DCD - SCD - CPR)
|
|
Destination Clock Delay (DCD): -0.360ns
|
|
Source Clock Delay (SCD): -0.581ns
|
|
Clock Pessimism Removal (CPR): 0.192ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock mlkem_clk_clk_pll rise edge)
|
|
0.000 0.000 r
|
|
K21 0.000 0.000 r clk (IN)
|
|
net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1
|
|
K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O
|
|
net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll
|
|
PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2)
|
|
-2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2
|
|
net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll
|
|
BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout3_buf/O
|
|
net (fo=26129, routed) 0.681 -0.581 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/mlkem_clk
|
|
SLICE_X25Y79 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/buffers_1_reg/C
|
|
------------------------------------------------------------------- -------------------
|
|
SLICE_X25Y79 FDCE (Prop_fdce_C_Q) 0.128 -0.453 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/buffers_1_reg/Q
|
|
net (fo=1, routed) 0.139 -0.314 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/buffers_1
|
|
SLICE_X25Y79 LUT1 (Prop_lut1_I0_O) 0.099 -0.215 f u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/popCC_popPtr[2]_i_2__1/O
|
|
net (fo=43, routed) 0.397 0.182 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/pushToPopGray_buffercc/buffers_0_reg[2]_1
|
|
SLICE_X31Y74 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/pushToPopGray_buffercc/buffers_1_reg[1]/CLR
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock mlkem_clk_clk_pll rise edge)
|
|
0.000 0.000 r
|
|
K21 0.000 0.000 r clk (IN)
|
|
net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1
|
|
K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O
|
|
net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll
|
|
PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2)
|
|
-2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2
|
|
net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll
|
|
BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout3_buf/O
|
|
net (fo=26129, routed) 0.948 -0.360 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/pushToPopGray_buffercc/mlkem_clk
|
|
SLICE_X31Y74 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/pushToPopGray_buffercc/buffers_1_reg[1]/C
|
|
clock pessimism -0.192 -0.552
|
|
SLICE_X31Y74 FDCE (Remov_fdce_C_CLR) -0.092 -0.644 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/pushToPopGray_buffercc/buffers_1_reg[1]
|
|
-------------------------------------------------------------------
|
|
required time 0.644
|
|
arrival time 0.182
|
|
-------------------------------------------------------------------
|
|
slack 0.827
|
|
|
|
Slack (MET) : 0.827ns (arrival time - required time)
|
|
Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/buffers_1_reg/C
|
|
(rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns})
|
|
Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/pushToPopGray_buffercc/buffers_1_reg[2]/CLR
|
|
(removal check against rising-edge clock mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns})
|
|
Path Group: **async_default**
|
|
Path Type: Removal (Min at Fast Process Corner)
|
|
Requirement: 0.000ns (mlkem_clk_clk_pll rise@0.000ns - mlkem_clk_clk_pll rise@0.000ns)
|
|
Data Path Delay: 0.764ns (logic 0.227ns (29.725%) route 0.537ns (70.275%))
|
|
Logic Levels: 1 (LUT1=1)
|
|
Clock Path Skew: 0.029ns (DCD - SCD - CPR)
|
|
Destination Clock Delay (DCD): -0.360ns
|
|
Source Clock Delay (SCD): -0.581ns
|
|
Clock Pessimism Removal (CPR): 0.192ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock mlkem_clk_clk_pll rise edge)
|
|
0.000 0.000 r
|
|
K21 0.000 0.000 r clk (IN)
|
|
net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1
|
|
K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O
|
|
net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll
|
|
PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2)
|
|
-2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2
|
|
net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll
|
|
BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout3_buf/O
|
|
net (fo=26129, routed) 0.681 -0.581 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/mlkem_clk
|
|
SLICE_X25Y79 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/buffers_1_reg/C
|
|
------------------------------------------------------------------- -------------------
|
|
SLICE_X25Y79 FDCE (Prop_fdce_C_Q) 0.128 -0.453 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/buffers_1_reg/Q
|
|
net (fo=1, routed) 0.139 -0.314 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/buffers_1
|
|
SLICE_X25Y79 LUT1 (Prop_lut1_I0_O) 0.099 -0.215 f u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/popCC_popPtr[2]_i_2__1/O
|
|
net (fo=43, routed) 0.397 0.182 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/pushToPopGray_buffercc/buffers_0_reg[2]_1
|
|
SLICE_X31Y74 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/pushToPopGray_buffercc/buffers_1_reg[2]/CLR
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock mlkem_clk_clk_pll rise edge)
|
|
0.000 0.000 r
|
|
K21 0.000 0.000 r clk (IN)
|
|
net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1
|
|
K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O
|
|
net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll
|
|
PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2)
|
|
-2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2
|
|
net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll
|
|
BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout3_buf/O
|
|
net (fo=26129, routed) 0.948 -0.360 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/pushToPopGray_buffercc/mlkem_clk
|
|
SLICE_X31Y74 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/pushToPopGray_buffercc/buffers_1_reg[2]/C
|
|
clock pessimism -0.192 -0.552
|
|
SLICE_X31Y74 FDCE (Remov_fdce_C_CLR) -0.092 -0.644 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/pushToPopGray_buffercc/buffers_1_reg[2]
|
|
-------------------------------------------------------------------
|
|
required time 0.644
|
|
arrival time 0.182
|
|
-------------------------------------------------------------------
|
|
slack 0.827
|
|
|
|
Slack (MET) : 0.860ns (arrival time - required time)
|
|
Source: pll_clk.u_rst_mlkem/delay_reg[1]/C
|
|
(rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns})
|
|
Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/start_sync_reg[0]/CLR
|
|
(removal check against rising-edge clock mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns})
|
|
Path Group: **async_default**
|
|
Path Type: Removal (Min at Fast Process Corner)
|
|
Requirement: 0.000ns (mlkem_clk_clk_pll rise@0.000ns - mlkem_clk_clk_pll rise@0.000ns)
|
|
Data Path Delay: 0.779ns (logic 0.186ns (23.870%) route 0.593ns (76.130%))
|
|
Logic Levels: 1 (LUT1=1)
|
|
Clock Path Skew: 0.011ns (DCD - SCD - CPR)
|
|
Destination Clock Delay (DCD): -0.383ns
|
|
Source Clock Delay (SCD): -0.607ns
|
|
Clock Pessimism Removal (CPR): 0.213ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock mlkem_clk_clk_pll rise edge)
|
|
0.000 0.000 r
|
|
K21 0.000 0.000 r clk (IN)
|
|
net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1
|
|
K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O
|
|
net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll
|
|
PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2)
|
|
-2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2
|
|
net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll
|
|
BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout3_buf/O
|
|
net (fo=26129, routed) 0.655 -0.607 pll_clk.u_rst_mlkem/mlkem_clk
|
|
SLICE_X118Y67 FDCE r pll_clk.u_rst_mlkem/delay_reg[1]/C
|
|
------------------------------------------------------------------- -------------------
|
|
SLICE_X118Y67 FDCE (Prop_fdce_C_Q) 0.141 -0.466 r pll_clk.u_rst_mlkem/delay_reg[1]/Q
|
|
net (fo=4, routed) 0.297 -0.169 pll_clk.u_rst_mlkem/Q[0]
|
|
SLICE_X118Y67 LUT1 (Prop_lut1_I0_O) 0.045 -0.124 f pll_clk.u_rst_mlkem/rdb_addr[11]_i_2/O
|
|
net (fo=1069, routed) 0.296 0.172 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/pre_addr_l_reg[2]_rep__1_0
|
|
SLICE_X118Y70 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/start_sync_reg[0]/CLR
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock mlkem_clk_clk_pll rise edge)
|
|
0.000 0.000 r
|
|
K21 0.000 0.000 r clk (IN)
|
|
net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1
|
|
K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O
|
|
net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll
|
|
PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2)
|
|
-2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2
|
|
net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll
|
|
BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout3_buf/O
|
|
net (fo=26129, routed) 0.925 -0.383 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/mlkem_clk
|
|
SLICE_X118Y70 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/start_sync_reg[0]/C
|
|
clock pessimism -0.213 -0.596
|
|
SLICE_X118Y70 FDCE (Remov_fdce_C_CLR) -0.092 -0.688 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/start_sync_reg[0]
|
|
-------------------------------------------------------------------
|
|
required time 0.688
|
|
arrival time 0.172
|
|
-------------------------------------------------------------------
|
|
slack 0.860
|
|
|
|
Slack (MET) : 0.860ns (arrival time - required time)
|
|
Source: pll_clk.u_rst_mlkem/delay_reg[1]/C
|
|
(rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns})
|
|
Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/start_tg_reg/CLR
|
|
(removal check against rising-edge clock mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns})
|
|
Path Group: **async_default**
|
|
Path Type: Removal (Min at Fast Process Corner)
|
|
Requirement: 0.000ns (mlkem_clk_clk_pll rise@0.000ns - mlkem_clk_clk_pll rise@0.000ns)
|
|
Data Path Delay: 0.779ns (logic 0.186ns (23.870%) route 0.593ns (76.130%))
|
|
Logic Levels: 1 (LUT1=1)
|
|
Clock Path Skew: 0.011ns (DCD - SCD - CPR)
|
|
Destination Clock Delay (DCD): -0.383ns
|
|
Source Clock Delay (SCD): -0.607ns
|
|
Clock Pessimism Removal (CPR): 0.213ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock mlkem_clk_clk_pll rise edge)
|
|
0.000 0.000 r
|
|
K21 0.000 0.000 r clk (IN)
|
|
net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1
|
|
K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O
|
|
net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll
|
|
PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2)
|
|
-2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2
|
|
net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll
|
|
BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout3_buf/O
|
|
net (fo=26129, routed) 0.655 -0.607 pll_clk.u_rst_mlkem/mlkem_clk
|
|
SLICE_X118Y67 FDCE r pll_clk.u_rst_mlkem/delay_reg[1]/C
|
|
------------------------------------------------------------------- -------------------
|
|
SLICE_X118Y67 FDCE (Prop_fdce_C_Q) 0.141 -0.466 r pll_clk.u_rst_mlkem/delay_reg[1]/Q
|
|
net (fo=4, routed) 0.297 -0.169 pll_clk.u_rst_mlkem/Q[0]
|
|
SLICE_X118Y67 LUT1 (Prop_lut1_I0_O) 0.045 -0.124 f pll_clk.u_rst_mlkem/rdb_addr[11]_i_2/O
|
|
net (fo=1069, routed) 0.296 0.172 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/pre_addr_l_reg[2]_rep__1_0
|
|
SLICE_X118Y70 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/start_tg_reg/CLR
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock mlkem_clk_clk_pll rise edge)
|
|
0.000 0.000 r
|
|
K21 0.000 0.000 r clk (IN)
|
|
net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1
|
|
K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O
|
|
net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll
|
|
PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2)
|
|
-2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2
|
|
net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll
|
|
BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout3_buf/O
|
|
net (fo=26129, routed) 0.925 -0.383 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/mlkem_clk
|
|
SLICE_X118Y70 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/start_tg_reg/C
|
|
clock pessimism -0.213 -0.596
|
|
SLICE_X118Y70 FDCE (Remov_fdce_C_CLR) -0.092 -0.688 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/start_tg_reg
|
|
-------------------------------------------------------------------
|
|
required time 0.688
|
|
arrival time 0.172
|
|
-------------------------------------------------------------------
|
|
slack 0.860
|
|
|
|
Slack (MET) : 0.868ns (arrival time - required time)
|
|
Source: pll_clk.u_rst_mlkem/delay_reg[1]/C
|
|
(rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns})
|
|
Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/stream_wstrb_reg[0]/CLR
|
|
(removal check against rising-edge clock mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns})
|
|
Path Group: **async_default**
|
|
Path Type: Removal (Min at Fast Process Corner)
|
|
Requirement: 0.000ns (mlkem_clk_clk_pll rise@0.000ns - mlkem_clk_clk_pll rise@0.000ns)
|
|
Data Path Delay: 0.809ns (logic 0.186ns (22.998%) route 0.623ns (77.002%))
|
|
Logic Levels: 1 (LUT1=1)
|
|
Clock Path Skew: 0.033ns (DCD - SCD - CPR)
|
|
Destination Clock Delay (DCD): -0.382ns
|
|
Source Clock Delay (SCD): -0.607ns
|
|
Clock Pessimism Removal (CPR): 0.192ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock mlkem_clk_clk_pll rise edge)
|
|
0.000 0.000 r
|
|
K21 0.000 0.000 r clk (IN)
|
|
net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1
|
|
K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O
|
|
net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll
|
|
PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2)
|
|
-2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2
|
|
net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll
|
|
BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout3_buf/O
|
|
net (fo=26129, routed) 0.655 -0.607 pll_clk.u_rst_mlkem/mlkem_clk
|
|
SLICE_X118Y67 FDCE r pll_clk.u_rst_mlkem/delay_reg[1]/C
|
|
------------------------------------------------------------------- -------------------
|
|
SLICE_X118Y67 FDCE (Prop_fdce_C_Q) 0.141 -0.466 r pll_clk.u_rst_mlkem/delay_reg[1]/Q
|
|
net (fo=4, routed) 0.297 -0.169 pll_clk.u_rst_mlkem/Q[0]
|
|
SLICE_X118Y67 LUT1 (Prop_lut1_I0_O) 0.045 -0.124 f pll_clk.u_rst_mlkem/rdb_addr[11]_i_2/O
|
|
net (fo=1069, routed) 0.325 0.201 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/pre_addr_l_reg[2]_rep__1_0
|
|
SLICE_X122Y69 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/stream_wstrb_reg[0]/CLR
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock mlkem_clk_clk_pll rise edge)
|
|
0.000 0.000 r
|
|
K21 0.000 0.000 r clk (IN)
|
|
net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1
|
|
K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O
|
|
net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll
|
|
PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2)
|
|
-2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2
|
|
net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll
|
|
BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout3_buf/O
|
|
net (fo=26129, routed) 0.926 -0.382 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/mlkem_clk
|
|
SLICE_X122Y69 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/stream_wstrb_reg[0]/C
|
|
clock pessimism -0.192 -0.574
|
|
SLICE_X122Y69 FDCE (Remov_fdce_C_CLR) -0.092 -0.666 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/stream_wstrb_reg[0]
|
|
-------------------------------------------------------------------
|
|
required time 0.666
|
|
arrival time 0.201
|
|
-------------------------------------------------------------------
|
|
slack 0.868
|
|
|
|
Slack (MET) : 0.868ns (arrival time - required time)
|
|
Source: pll_clk.u_rst_mlkem/delay_reg[1]/C
|
|
(rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns})
|
|
Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/stream_wstrb_reg[1]/CLR
|
|
(removal check against rising-edge clock mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns})
|
|
Path Group: **async_default**
|
|
Path Type: Removal (Min at Fast Process Corner)
|
|
Requirement: 0.000ns (mlkem_clk_clk_pll rise@0.000ns - mlkem_clk_clk_pll rise@0.000ns)
|
|
Data Path Delay: 0.809ns (logic 0.186ns (22.998%) route 0.623ns (77.002%))
|
|
Logic Levels: 1 (LUT1=1)
|
|
Clock Path Skew: 0.033ns (DCD - SCD - CPR)
|
|
Destination Clock Delay (DCD): -0.382ns
|
|
Source Clock Delay (SCD): -0.607ns
|
|
Clock Pessimism Removal (CPR): 0.192ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock mlkem_clk_clk_pll rise edge)
|
|
0.000 0.000 r
|
|
K21 0.000 0.000 r clk (IN)
|
|
net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1
|
|
K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O
|
|
net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll
|
|
PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2)
|
|
-2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2
|
|
net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll
|
|
BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout3_buf/O
|
|
net (fo=26129, routed) 0.655 -0.607 pll_clk.u_rst_mlkem/mlkem_clk
|
|
SLICE_X118Y67 FDCE r pll_clk.u_rst_mlkem/delay_reg[1]/C
|
|
------------------------------------------------------------------- -------------------
|
|
SLICE_X118Y67 FDCE (Prop_fdce_C_Q) 0.141 -0.466 r pll_clk.u_rst_mlkem/delay_reg[1]/Q
|
|
net (fo=4, routed) 0.297 -0.169 pll_clk.u_rst_mlkem/Q[0]
|
|
SLICE_X118Y67 LUT1 (Prop_lut1_I0_O) 0.045 -0.124 f pll_clk.u_rst_mlkem/rdb_addr[11]_i_2/O
|
|
net (fo=1069, routed) 0.325 0.201 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/pre_addr_l_reg[2]_rep__1_0
|
|
SLICE_X122Y69 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/stream_wstrb_reg[1]/CLR
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock mlkem_clk_clk_pll rise edge)
|
|
0.000 0.000 r
|
|
K21 0.000 0.000 r clk (IN)
|
|
net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1
|
|
K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O
|
|
net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll
|
|
PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2)
|
|
-2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2
|
|
net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll
|
|
BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout3_buf/O
|
|
net (fo=26129, routed) 0.926 -0.382 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/mlkem_clk
|
|
SLICE_X122Y69 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/stream_wstrb_reg[1]/C
|
|
clock pessimism -0.192 -0.574
|
|
SLICE_X122Y69 FDCE (Remov_fdce_C_CLR) -0.092 -0.666 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/stream_wstrb_reg[1]
|
|
-------------------------------------------------------------------
|
|
required time 0.666
|
|
arrival time 0.201
|
|
-------------------------------------------------------------------
|
|
slack 0.868
|
|
|
|
|
|
|
|
|
|
|
|
---------------------------------------------------------------------------------------------------
|
|
Path Group: **async_default**
|
|
From Clock: sys_clk
|
|
To Clock: mlkem_clk_clk_pll
|
|
|
|
Setup : NA Failing Endpoints, Worst Slack NA , Total Violation NA
|
|
Hold : 0 Failing Endpoints, Worst Slack 2.861ns, Total Violation 0.000ns
|
|
---------------------------------------------------------------------------------------------------
|
|
|
|
|
|
Min Delay Paths
|
|
--------------------------------------------------------------------------------------
|
|
Slack (MET) : 2.861ns (arrival time - required time)
|
|
Source: pll_clk.u_rst_sys/delay_reg[1]/C
|
|
(rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/buffers_0_reg/CLR
|
|
(removal check against rising-edge clock mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns})
|
|
Path Group: **async_default**
|
|
Path Type: Removal (Min at Fast Process Corner)
|
|
Requirement: 0.000ns (mlkem_clk_clk_pll rise@0.000ns - sys_clk rise@0.000ns)
|
|
Data Path Delay: 3.250ns (logic 0.187ns (5.753%) route 3.063ns (94.247%))
|
|
Logic Levels: 1 (LUT1=1)
|
|
Clock Path Skew: 0.351ns (DCD - SCD - CPR)
|
|
Destination Clock Delay (DCD): -0.353ns
|
|
Source Clock Delay (SCD): -0.605ns
|
|
Clock Pessimism Removal (CPR): -0.099ns
|
|
Clock Uncertainty: 0.197ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Discrete Jitter (DJ): 0.136ns
|
|
Phase Error (PE): 0.120ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock sys_clk rise edge) 0.000 0.000 r
|
|
K21 0.000 0.000 r clk (IN)
|
|
net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1
|
|
K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O
|
|
net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll
|
|
PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1)
|
|
-2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1
|
|
net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll
|
|
BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O
|
|
net (fo=10004, routed) 0.658 -0.605 pll_clk.u_rst_sys/sys_clk
|
|
SLICE_X1Y101 FDCE r pll_clk.u_rst_sys/delay_reg[1]/C
|
|
------------------------------------------------------------------- -------------------
|
|
SLICE_X1Y101 FDCE (Prop_fdce_C_Q) 0.141 -0.464 r pll_clk.u_rst_sys/delay_reg[1]/Q
|
|
net (fo=115, routed) 1.600 1.136 pll_clk.u_rst_sys/Q[0]
|
|
SLICE_X14Y74 LUT1 (Prop_lut1_I0_O) 0.046 1.182 f pll_clk.u_rst_sys/bf2_do_en_i_1/O
|
|
net (fo=4130, routed) 1.463 2.645 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/p_0_in
|
|
SLICE_X25Y79 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/buffers_0_reg/CLR
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock mlkem_clk_clk_pll rise edge)
|
|
0.000 0.000 r
|
|
K21 0.000 0.000 r clk (IN)
|
|
net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1
|
|
K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O
|
|
net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll
|
|
PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2)
|
|
-2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2
|
|
net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll
|
|
BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout3_buf/O
|
|
net (fo=26129, routed) 0.955 -0.353 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/mlkem_clk
|
|
SLICE_X25Y79 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/buffers_0_reg/C
|
|
clock pessimism 0.099 -0.254
|
|
clock uncertainty 0.197 -0.058
|
|
SLICE_X25Y79 FDCE (Remov_fdce_C_CLR) -0.158 -0.216 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/buffers_0_reg
|
|
-------------------------------------------------------------------
|
|
required time 0.216
|
|
arrival time 2.645
|
|
-------------------------------------------------------------------
|
|
slack 2.861
|
|
|
|
Slack (MET) : 2.861ns (arrival time - required time)
|
|
Source: pll_clk.u_rst_sys/delay_reg[1]/C
|
|
(rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/buffers_1_reg/CLR
|
|
(removal check against rising-edge clock mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns})
|
|
Path Group: **async_default**
|
|
Path Type: Removal (Min at Fast Process Corner)
|
|
Requirement: 0.000ns (mlkem_clk_clk_pll rise@0.000ns - sys_clk rise@0.000ns)
|
|
Data Path Delay: 3.250ns (logic 0.187ns (5.753%) route 3.063ns (94.247%))
|
|
Logic Levels: 1 (LUT1=1)
|
|
Clock Path Skew: 0.351ns (DCD - SCD - CPR)
|
|
Destination Clock Delay (DCD): -0.353ns
|
|
Source Clock Delay (SCD): -0.605ns
|
|
Clock Pessimism Removal (CPR): -0.099ns
|
|
Clock Uncertainty: 0.197ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Discrete Jitter (DJ): 0.136ns
|
|
Phase Error (PE): 0.120ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock sys_clk rise edge) 0.000 0.000 r
|
|
K21 0.000 0.000 r clk (IN)
|
|
net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1
|
|
K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O
|
|
net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll
|
|
PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1)
|
|
-2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1
|
|
net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll
|
|
BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O
|
|
net (fo=10004, routed) 0.658 -0.605 pll_clk.u_rst_sys/sys_clk
|
|
SLICE_X1Y101 FDCE r pll_clk.u_rst_sys/delay_reg[1]/C
|
|
------------------------------------------------------------------- -------------------
|
|
SLICE_X1Y101 FDCE (Prop_fdce_C_Q) 0.141 -0.464 r pll_clk.u_rst_sys/delay_reg[1]/Q
|
|
net (fo=115, routed) 1.600 1.136 pll_clk.u_rst_sys/Q[0]
|
|
SLICE_X14Y74 LUT1 (Prop_lut1_I0_O) 0.046 1.182 f pll_clk.u_rst_sys/bf2_do_en_i_1/O
|
|
net (fo=4130, routed) 1.463 2.645 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/p_0_in
|
|
SLICE_X25Y79 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/buffers_1_reg/CLR
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock mlkem_clk_clk_pll rise edge)
|
|
0.000 0.000 r
|
|
K21 0.000 0.000 r clk (IN)
|
|
net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1
|
|
K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O
|
|
net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll
|
|
PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2)
|
|
-2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2
|
|
net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll
|
|
BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout3_buf/O
|
|
net (fo=26129, routed) 0.955 -0.353 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/mlkem_clk
|
|
SLICE_X25Y79 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/buffers_1_reg/C
|
|
clock pessimism 0.099 -0.254
|
|
clock uncertainty 0.197 -0.058
|
|
SLICE_X25Y79 FDCE (Remov_fdce_C_CLR) -0.158 -0.216 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/buffers_1_reg
|
|
-------------------------------------------------------------------
|
|
required time 0.216
|
|
arrival time 2.645
|
|
-------------------------------------------------------------------
|
|
slack 2.861
|
|
|
|
Slack (MET) : 4.207ns (arrival time - required time)
|
|
Source: pll_clk.u_rst_sys/delay_reg[1]/C
|
|
(rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Destination: pll_clk.u_rst_mlkem/delay_reg[0]/CLR
|
|
(removal check against rising-edge clock mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns})
|
|
Path Group: **async_default**
|
|
Path Type: Removal (Min at Fast Process Corner)
|
|
Requirement: 0.000ns (mlkem_clk_clk_pll rise@0.000ns - sys_clk rise@0.000ns)
|
|
Data Path Delay: 4.569ns (logic 0.187ns (4.093%) route 4.382ns (95.907%))
|
|
Logic Levels: 1 (LUT1=1)
|
|
Clock Path Skew: 0.324ns (DCD - SCD - CPR)
|
|
Destination Clock Delay (DCD): -0.380ns
|
|
Source Clock Delay (SCD): -0.605ns
|
|
Clock Pessimism Removal (CPR): -0.099ns
|
|
Clock Uncertainty: 0.197ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Discrete Jitter (DJ): 0.136ns
|
|
Phase Error (PE): 0.120ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock sys_clk rise edge) 0.000 0.000 r
|
|
K21 0.000 0.000 r clk (IN)
|
|
net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1
|
|
K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O
|
|
net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll
|
|
PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1)
|
|
-2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1
|
|
net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll
|
|
BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O
|
|
net (fo=10004, routed) 0.658 -0.605 pll_clk.u_rst_sys/sys_clk
|
|
SLICE_X1Y101 FDCE r pll_clk.u_rst_sys/delay_reg[1]/C
|
|
------------------------------------------------------------------- -------------------
|
|
SLICE_X1Y101 FDCE (Prop_fdce_C_Q) 0.141 -0.464 r pll_clk.u_rst_sys/delay_reg[1]/Q
|
|
net (fo=115, routed) 1.600 1.136 pll_clk.u_rst_sys/Q[0]
|
|
SLICE_X14Y74 LUT1 (Prop_lut1_I0_O) 0.046 1.182 f pll_clk.u_rst_sys/bf2_do_en_i_1/O
|
|
net (fo=4130, routed) 2.782 3.964 pll_clk.u_rst_mlkem/p_0_in
|
|
SLICE_X118Y67 FDCE f pll_clk.u_rst_mlkem/delay_reg[0]/CLR
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock mlkem_clk_clk_pll rise edge)
|
|
0.000 0.000 r
|
|
K21 0.000 0.000 r clk (IN)
|
|
net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1
|
|
K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O
|
|
net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll
|
|
PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2)
|
|
-2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2
|
|
net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll
|
|
BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout3_buf/O
|
|
net (fo=26129, routed) 0.928 -0.380 pll_clk.u_rst_mlkem/mlkem_clk
|
|
SLICE_X118Y67 FDCE r pll_clk.u_rst_mlkem/delay_reg[0]/C
|
|
clock pessimism 0.099 -0.281
|
|
clock uncertainty 0.197 -0.085
|
|
SLICE_X118Y67 FDCE (Remov_fdce_C_CLR) -0.158 -0.243 pll_clk.u_rst_mlkem/delay_reg[0]
|
|
-------------------------------------------------------------------
|
|
required time 0.243
|
|
arrival time 3.964
|
|
-------------------------------------------------------------------
|
|
slack 4.207
|
|
|
|
Slack (MET) : 4.207ns (arrival time - required time)
|
|
Source: pll_clk.u_rst_sys/delay_reg[1]/C
|
|
(rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Destination: pll_clk.u_rst_mlkem/delay_reg[1]/CLR
|
|
(removal check against rising-edge clock mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns})
|
|
Path Group: **async_default**
|
|
Path Type: Removal (Min at Fast Process Corner)
|
|
Requirement: 0.000ns (mlkem_clk_clk_pll rise@0.000ns - sys_clk rise@0.000ns)
|
|
Data Path Delay: 4.569ns (logic 0.187ns (4.093%) route 4.382ns (95.907%))
|
|
Logic Levels: 1 (LUT1=1)
|
|
Clock Path Skew: 0.324ns (DCD - SCD - CPR)
|
|
Destination Clock Delay (DCD): -0.380ns
|
|
Source Clock Delay (SCD): -0.605ns
|
|
Clock Pessimism Removal (CPR): -0.099ns
|
|
Clock Uncertainty: 0.197ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Discrete Jitter (DJ): 0.136ns
|
|
Phase Error (PE): 0.120ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock sys_clk rise edge) 0.000 0.000 r
|
|
K21 0.000 0.000 r clk (IN)
|
|
net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1
|
|
K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O
|
|
net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll
|
|
PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1)
|
|
-2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1
|
|
net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll
|
|
BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O
|
|
net (fo=10004, routed) 0.658 -0.605 pll_clk.u_rst_sys/sys_clk
|
|
SLICE_X1Y101 FDCE r pll_clk.u_rst_sys/delay_reg[1]/C
|
|
------------------------------------------------------------------- -------------------
|
|
SLICE_X1Y101 FDCE (Prop_fdce_C_Q) 0.141 -0.464 r pll_clk.u_rst_sys/delay_reg[1]/Q
|
|
net (fo=115, routed) 1.600 1.136 pll_clk.u_rst_sys/Q[0]
|
|
SLICE_X14Y74 LUT1 (Prop_lut1_I0_O) 0.046 1.182 f pll_clk.u_rst_sys/bf2_do_en_i_1/O
|
|
net (fo=4130, routed) 2.782 3.964 pll_clk.u_rst_mlkem/p_0_in
|
|
SLICE_X118Y67 FDCE f pll_clk.u_rst_mlkem/delay_reg[1]/CLR
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock mlkem_clk_clk_pll rise edge)
|
|
0.000 0.000 r
|
|
K21 0.000 0.000 r clk (IN)
|
|
net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1
|
|
K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O
|
|
net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll
|
|
PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2)
|
|
-2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2
|
|
net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll
|
|
BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout3_buf/O
|
|
net (fo=26129, routed) 0.928 -0.380 pll_clk.u_rst_mlkem/mlkem_clk
|
|
SLICE_X118Y67 FDCE r pll_clk.u_rst_mlkem/delay_reg[1]/C
|
|
clock pessimism 0.099 -0.281
|
|
clock uncertainty 0.197 -0.085
|
|
SLICE_X118Y67 FDCE (Remov_fdce_C_CLR) -0.158 -0.243 pll_clk.u_rst_mlkem/delay_reg[1]
|
|
-------------------------------------------------------------------
|
|
required time 0.243
|
|
arrival time 3.964
|
|
-------------------------------------------------------------------
|
|
slack 4.207
|
|
|
|
|
|
|
|
|
|
|
|
---------------------------------------------------------------------------------------------------
|
|
Path Group: **async_default**
|
|
From Clock: mlkem_clk_clk_pll
|
|
To Clock: sys_clk
|
|
|
|
Setup : NA Failing Endpoints, Worst Slack NA , Total Violation NA
|
|
Hold : 0 Failing Endpoints, Worst Slack 2.991ns, Total Violation 0.000ns
|
|
---------------------------------------------------------------------------------------------------
|
|
|
|
|
|
Min Delay Paths
|
|
--------------------------------------------------------------------------------------
|
|
Slack (MET) : 2.991ns (arrival time - required time)
|
|
Source: pll_clk.u_rst_mlkem/delay_reg[1]/C
|
|
(rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns})
|
|
Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/buffers_0_reg/CLR
|
|
(removal check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Path Group: **async_default**
|
|
Path Type: Removal (Min at Fast Process Corner)
|
|
Requirement: 0.000ns (sys_clk rise@0.000ns - mlkem_clk_clk_pll rise@0.000ns)
|
|
Data Path Delay: 3.460ns (logic 0.186ns (5.375%) route 3.274ns (94.625%))
|
|
Logic Levels: 1 (LUT1=1)
|
|
Clock Path Skew: 0.365ns (DCD - SCD - CPR)
|
|
Destination Clock Delay (DCD): -0.341ns
|
|
Source Clock Delay (SCD): -0.607ns
|
|
Clock Pessimism Removal (CPR): -0.099ns
|
|
Clock Uncertainty: 0.197ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Discrete Jitter (DJ): 0.136ns
|
|
Phase Error (PE): 0.120ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock mlkem_clk_clk_pll rise edge)
|
|
0.000 0.000 r
|
|
K21 0.000 0.000 r clk (IN)
|
|
net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1
|
|
K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O
|
|
net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll
|
|
PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2)
|
|
-2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2
|
|
net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll
|
|
BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout3_buf/O
|
|
net (fo=26129, routed) 0.655 -0.607 pll_clk.u_rst_mlkem/mlkem_clk
|
|
SLICE_X118Y67 FDCE r pll_clk.u_rst_mlkem/delay_reg[1]/C
|
|
------------------------------------------------------------------- -------------------
|
|
SLICE_X118Y67 FDCE (Prop_fdce_C_Q) 0.141 -0.466 r pll_clk.u_rst_mlkem/delay_reg[1]/Q
|
|
net (fo=4, routed) 0.297 -0.169 pll_clk.u_rst_mlkem/Q[0]
|
|
SLICE_X118Y67 LUT1 (Prop_lut1_I0_O) 0.045 -0.124 f pll_clk.u_rst_mlkem/rdb_addr[11]_i_2/O
|
|
net (fo=1069, routed) 2.977 2.853 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/buffers_0_reg_0
|
|
SLICE_X13Y87 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/buffers_0_reg/CLR
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock sys_clk rise edge) 0.000 0.000 r
|
|
K21 0.000 0.000 r clk (IN)
|
|
net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1
|
|
K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O
|
|
net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll
|
|
PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1)
|
|
-2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1
|
|
net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll
|
|
BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O
|
|
net (fo=10004, routed) 0.967 -0.341 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/sys_clk
|
|
SLICE_X13Y87 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/buffers_0_reg/C
|
|
clock pessimism 0.099 -0.242
|
|
clock uncertainty 0.197 -0.046
|
|
SLICE_X13Y87 FDCE (Remov_fdce_C_CLR) -0.092 -0.138 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/buffers_0_reg
|
|
-------------------------------------------------------------------
|
|
required time 0.138
|
|
arrival time 2.853
|
|
-------------------------------------------------------------------
|
|
slack 2.991
|
|
|
|
Slack (MET) : 2.991ns (arrival time - required time)
|
|
Source: pll_clk.u_rst_mlkem/delay_reg[1]/C
|
|
(rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns})
|
|
Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/buffers_1_reg/CLR
|
|
(removal check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Path Group: **async_default**
|
|
Path Type: Removal (Min at Fast Process Corner)
|
|
Requirement: 0.000ns (sys_clk rise@0.000ns - mlkem_clk_clk_pll rise@0.000ns)
|
|
Data Path Delay: 3.460ns (logic 0.186ns (5.375%) route 3.274ns (94.625%))
|
|
Logic Levels: 1 (LUT1=1)
|
|
Clock Path Skew: 0.365ns (DCD - SCD - CPR)
|
|
Destination Clock Delay (DCD): -0.341ns
|
|
Source Clock Delay (SCD): -0.607ns
|
|
Clock Pessimism Removal (CPR): -0.099ns
|
|
Clock Uncertainty: 0.197ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Discrete Jitter (DJ): 0.136ns
|
|
Phase Error (PE): 0.120ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock mlkem_clk_clk_pll rise edge)
|
|
0.000 0.000 r
|
|
K21 0.000 0.000 r clk (IN)
|
|
net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1
|
|
K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O
|
|
net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll
|
|
PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2)
|
|
-2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2
|
|
net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll
|
|
BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout3_buf/O
|
|
net (fo=26129, routed) 0.655 -0.607 pll_clk.u_rst_mlkem/mlkem_clk
|
|
SLICE_X118Y67 FDCE r pll_clk.u_rst_mlkem/delay_reg[1]/C
|
|
------------------------------------------------------------------- -------------------
|
|
SLICE_X118Y67 FDCE (Prop_fdce_C_Q) 0.141 -0.466 r pll_clk.u_rst_mlkem/delay_reg[1]/Q
|
|
net (fo=4, routed) 0.297 -0.169 pll_clk.u_rst_mlkem/Q[0]
|
|
SLICE_X118Y67 LUT1 (Prop_lut1_I0_O) 0.045 -0.124 f pll_clk.u_rst_mlkem/rdb_addr[11]_i_2/O
|
|
net (fo=1069, routed) 2.977 2.853 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/buffers_0_reg_0
|
|
SLICE_X13Y87 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/buffers_1_reg/CLR
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock sys_clk rise edge) 0.000 0.000 r
|
|
K21 0.000 0.000 r clk (IN)
|
|
net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1
|
|
K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O
|
|
net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll
|
|
PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1)
|
|
-2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1
|
|
net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll
|
|
BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O
|
|
net (fo=10004, routed) 0.967 -0.341 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/sys_clk
|
|
SLICE_X13Y87 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/buffers_1_reg/C
|
|
clock pessimism 0.099 -0.242
|
|
clock uncertainty 0.197 -0.046
|
|
SLICE_X13Y87 FDCE (Remov_fdce_C_CLR) -0.092 -0.138 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/buffers_1_reg
|
|
-------------------------------------------------------------------
|
|
required time 0.138
|
|
arrival time 2.853
|
|
-------------------------------------------------------------------
|
|
slack 2.991
|
|
|
|
|
|
|
|
|
|
|
|
---------------------------------------------------------------------------------------------------
|
|
Path Group: **async_default**
|
|
From Clock: sys_clk
|
|
To Clock: sys_clk
|
|
|
|
Setup : NA Failing Endpoints, Worst Slack NA , Total Violation NA
|
|
Hold : 0 Failing Endpoints, Worst Slack 0.479ns, Total Violation 0.000ns
|
|
---------------------------------------------------------------------------------------------------
|
|
|
|
|
|
Min Delay Paths
|
|
--------------------------------------------------------------------------------------
|
|
Slack (MET) : 0.479ns (arrival time - required time)
|
|
Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/buffers_1_reg/C
|
|
(rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/popCC_ptrToPush_reg[0]/CLR
|
|
(removal check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Path Group: **async_default**
|
|
Path Type: Removal (Min at Fast Process Corner)
|
|
Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns)
|
|
Data Path Delay: 0.427ns (logic 0.227ns (53.157%) route 0.200ns (46.843%))
|
|
Logic Levels: 1 (LUT1=1)
|
|
Clock Path Skew: 0.015ns (DCD - SCD - CPR)
|
|
Destination Clock Delay (DCD): -0.341ns
|
|
Source Clock Delay (SCD): -0.570ns
|
|
Clock Pessimism Removal (CPR): 0.214ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock sys_clk rise edge) 0.000 0.000 r
|
|
K21 0.000 0.000 r clk (IN)
|
|
net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1
|
|
K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O
|
|
net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll
|
|
PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1)
|
|
-2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1
|
|
net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll
|
|
BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O
|
|
net (fo=10004, routed) 0.692 -0.570 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/sys_clk
|
|
SLICE_X13Y87 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/buffers_1_reg/C
|
|
------------------------------------------------------------------- -------------------
|
|
SLICE_X13Y87 FDCE (Prop_fdce_C_Q) 0.128 -0.442 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/buffers_1_reg/Q
|
|
net (fo=1, routed) 0.053 -0.389 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/buffers_1
|
|
SLICE_X13Y87 LUT1 (Prop_lut1_I0_O) 0.099 -0.290 f u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/popCC_popPtr[2]_i_2__2/O
|
|
net (fo=30, routed) 0.147 -0.143 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/buffers_0_reg[3]
|
|
SLICE_X14Y87 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/popCC_ptrToPush_reg[0]/CLR
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock sys_clk rise edge) 0.000 0.000 r
|
|
K21 0.000 0.000 r clk (IN)
|
|
net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1
|
|
K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O
|
|
net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll
|
|
PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1)
|
|
-2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1
|
|
net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll
|
|
BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O
|
|
net (fo=10004, routed) 0.967 -0.341 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/sys_clk
|
|
SLICE_X14Y87 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/popCC_ptrToPush_reg[0]/C
|
|
clock pessimism -0.214 -0.555
|
|
SLICE_X14Y87 FDCE (Remov_fdce_C_CLR) -0.067 -0.622 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/popCC_ptrToPush_reg[0]
|
|
-------------------------------------------------------------------
|
|
required time 0.622
|
|
arrival time -0.143
|
|
-------------------------------------------------------------------
|
|
slack 0.479
|
|
|
|
Slack (MET) : 0.479ns (arrival time - required time)
|
|
Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/buffers_1_reg/C
|
|
(rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/popCC_ptrToPush_reg[1]/CLR
|
|
(removal check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Path Group: **async_default**
|
|
Path Type: Removal (Min at Fast Process Corner)
|
|
Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns)
|
|
Data Path Delay: 0.427ns (logic 0.227ns (53.157%) route 0.200ns (46.843%))
|
|
Logic Levels: 1 (LUT1=1)
|
|
Clock Path Skew: 0.015ns (DCD - SCD - CPR)
|
|
Destination Clock Delay (DCD): -0.341ns
|
|
Source Clock Delay (SCD): -0.570ns
|
|
Clock Pessimism Removal (CPR): 0.214ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock sys_clk rise edge) 0.000 0.000 r
|
|
K21 0.000 0.000 r clk (IN)
|
|
net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1
|
|
K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O
|
|
net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll
|
|
PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1)
|
|
-2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1
|
|
net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll
|
|
BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O
|
|
net (fo=10004, routed) 0.692 -0.570 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/sys_clk
|
|
SLICE_X13Y87 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/buffers_1_reg/C
|
|
------------------------------------------------------------------- -------------------
|
|
SLICE_X13Y87 FDCE (Prop_fdce_C_Q) 0.128 -0.442 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/buffers_1_reg/Q
|
|
net (fo=1, routed) 0.053 -0.389 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/buffers_1
|
|
SLICE_X13Y87 LUT1 (Prop_lut1_I0_O) 0.099 -0.290 f u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/popCC_popPtr[2]_i_2__2/O
|
|
net (fo=30, routed) 0.147 -0.143 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/buffers_0_reg[3]
|
|
SLICE_X14Y87 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/popCC_ptrToPush_reg[1]/CLR
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock sys_clk rise edge) 0.000 0.000 r
|
|
K21 0.000 0.000 r clk (IN)
|
|
net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1
|
|
K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O
|
|
net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll
|
|
PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1)
|
|
-2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1
|
|
net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll
|
|
BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O
|
|
net (fo=10004, routed) 0.967 -0.341 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/sys_clk
|
|
SLICE_X14Y87 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/popCC_ptrToPush_reg[1]/C
|
|
clock pessimism -0.214 -0.555
|
|
SLICE_X14Y87 FDCE (Remov_fdce_C_CLR) -0.067 -0.622 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/popCC_ptrToPush_reg[1]
|
|
-------------------------------------------------------------------
|
|
required time 0.622
|
|
arrival time -0.143
|
|
-------------------------------------------------------------------
|
|
slack 0.479
|
|
|
|
Slack (MET) : 0.479ns (arrival time - required time)
|
|
Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/buffers_1_reg/C
|
|
(rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/popCC_ptrToPush_reg[2]/CLR
|
|
(removal check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Path Group: **async_default**
|
|
Path Type: Removal (Min at Fast Process Corner)
|
|
Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns)
|
|
Data Path Delay: 0.427ns (logic 0.227ns (53.157%) route 0.200ns (46.843%))
|
|
Logic Levels: 1 (LUT1=1)
|
|
Clock Path Skew: 0.015ns (DCD - SCD - CPR)
|
|
Destination Clock Delay (DCD): -0.341ns
|
|
Source Clock Delay (SCD): -0.570ns
|
|
Clock Pessimism Removal (CPR): 0.214ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock sys_clk rise edge) 0.000 0.000 r
|
|
K21 0.000 0.000 r clk (IN)
|
|
net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1
|
|
K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O
|
|
net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll
|
|
PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1)
|
|
-2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1
|
|
net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll
|
|
BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O
|
|
net (fo=10004, routed) 0.692 -0.570 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/sys_clk
|
|
SLICE_X13Y87 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/buffers_1_reg/C
|
|
------------------------------------------------------------------- -------------------
|
|
SLICE_X13Y87 FDCE (Prop_fdce_C_Q) 0.128 -0.442 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/buffers_1_reg/Q
|
|
net (fo=1, routed) 0.053 -0.389 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/buffers_1
|
|
SLICE_X13Y87 LUT1 (Prop_lut1_I0_O) 0.099 -0.290 f u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/popCC_popPtr[2]_i_2__2/O
|
|
net (fo=30, routed) 0.147 -0.143 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/buffers_0_reg[3]
|
|
SLICE_X14Y87 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/popCC_ptrToPush_reg[2]/CLR
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock sys_clk rise edge) 0.000 0.000 r
|
|
K21 0.000 0.000 r clk (IN)
|
|
net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1
|
|
K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O
|
|
net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll
|
|
PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1)
|
|
-2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1
|
|
net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll
|
|
BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O
|
|
net (fo=10004, routed) 0.967 -0.341 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/sys_clk
|
|
SLICE_X14Y87 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/popCC_ptrToPush_reg[2]/C
|
|
clock pessimism -0.214 -0.555
|
|
SLICE_X14Y87 FDCE (Remov_fdce_C_CLR) -0.067 -0.622 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/popCC_ptrToPush_reg[2]
|
|
-------------------------------------------------------------------
|
|
required time 0.622
|
|
arrival time -0.143
|
|
-------------------------------------------------------------------
|
|
slack 0.479
|
|
|
|
Slack (MET) : 0.504ns (arrival time - required time)
|
|
Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/buffers_1_reg/C
|
|
(rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/pushToPopGray_buffercc/buffers_0_reg[2]/CLR
|
|
(removal check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Path Group: **async_default**
|
|
Path Type: Removal (Min at Fast Process Corner)
|
|
Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns)
|
|
Data Path Delay: 0.427ns (logic 0.227ns (53.157%) route 0.200ns (46.843%))
|
|
Logic Levels: 1 (LUT1=1)
|
|
Clock Path Skew: 0.015ns (DCD - SCD - CPR)
|
|
Destination Clock Delay (DCD): -0.341ns
|
|
Source Clock Delay (SCD): -0.570ns
|
|
Clock Pessimism Removal (CPR): 0.214ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock sys_clk rise edge) 0.000 0.000 r
|
|
K21 0.000 0.000 r clk (IN)
|
|
net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1
|
|
K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O
|
|
net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll
|
|
PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1)
|
|
-2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1
|
|
net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll
|
|
BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O
|
|
net (fo=10004, routed) 0.692 -0.570 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/sys_clk
|
|
SLICE_X13Y87 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/buffers_1_reg/C
|
|
------------------------------------------------------------------- -------------------
|
|
SLICE_X13Y87 FDCE (Prop_fdce_C_Q) 0.128 -0.442 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/buffers_1_reg/Q
|
|
net (fo=1, routed) 0.053 -0.389 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/buffers_1
|
|
SLICE_X13Y87 LUT1 (Prop_lut1_I0_O) 0.099 -0.290 f u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/popCC_popPtr[2]_i_2__2/O
|
|
net (fo=30, routed) 0.147 -0.143 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/pushToPopGray_buffercc/buffers_0_reg[3]_0
|
|
SLICE_X15Y87 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/pushToPopGray_buffercc/buffers_0_reg[2]/CLR
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock sys_clk rise edge) 0.000 0.000 r
|
|
K21 0.000 0.000 r clk (IN)
|
|
net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1
|
|
K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O
|
|
net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll
|
|
PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1)
|
|
-2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1
|
|
net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll
|
|
BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O
|
|
net (fo=10004, routed) 0.967 -0.341 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/pushToPopGray_buffercc/sys_clk
|
|
SLICE_X15Y87 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/pushToPopGray_buffercc/buffers_0_reg[2]/C
|
|
clock pessimism -0.214 -0.555
|
|
SLICE_X15Y87 FDCE (Remov_fdce_C_CLR) -0.092 -0.647 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/pushToPopGray_buffercc/buffers_0_reg[2]
|
|
-------------------------------------------------------------------
|
|
required time 0.647
|
|
arrival time -0.143
|
|
-------------------------------------------------------------------
|
|
slack 0.504
|
|
|
|
Slack (MET) : 0.504ns (arrival time - required time)
|
|
Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/buffers_1_reg/C
|
|
(rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/pushToPopGray_buffercc/buffers_0_reg[3]/CLR
|
|
(removal check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Path Group: **async_default**
|
|
Path Type: Removal (Min at Fast Process Corner)
|
|
Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns)
|
|
Data Path Delay: 0.427ns (logic 0.227ns (53.157%) route 0.200ns (46.843%))
|
|
Logic Levels: 1 (LUT1=1)
|
|
Clock Path Skew: 0.015ns (DCD - SCD - CPR)
|
|
Destination Clock Delay (DCD): -0.341ns
|
|
Source Clock Delay (SCD): -0.570ns
|
|
Clock Pessimism Removal (CPR): 0.214ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock sys_clk rise edge) 0.000 0.000 r
|
|
K21 0.000 0.000 r clk (IN)
|
|
net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1
|
|
K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O
|
|
net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll
|
|
PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1)
|
|
-2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1
|
|
net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll
|
|
BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O
|
|
net (fo=10004, routed) 0.692 -0.570 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/sys_clk
|
|
SLICE_X13Y87 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/buffers_1_reg/C
|
|
------------------------------------------------------------------- -------------------
|
|
SLICE_X13Y87 FDCE (Prop_fdce_C_Q) 0.128 -0.442 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/buffers_1_reg/Q
|
|
net (fo=1, routed) 0.053 -0.389 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/buffers_1
|
|
SLICE_X13Y87 LUT1 (Prop_lut1_I0_O) 0.099 -0.290 f u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/popCC_popPtr[2]_i_2__2/O
|
|
net (fo=30, routed) 0.147 -0.143 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/pushToPopGray_buffercc/buffers_0_reg[3]_0
|
|
SLICE_X15Y87 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/pushToPopGray_buffercc/buffers_0_reg[3]/CLR
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock sys_clk rise edge) 0.000 0.000 r
|
|
K21 0.000 0.000 r clk (IN)
|
|
net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1
|
|
K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O
|
|
net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll
|
|
PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1)
|
|
-2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1
|
|
net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll
|
|
BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O
|
|
net (fo=10004, routed) 0.967 -0.341 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/pushToPopGray_buffercc/sys_clk
|
|
SLICE_X15Y87 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/pushToPopGray_buffercc/buffers_0_reg[3]/C
|
|
clock pessimism -0.214 -0.555
|
|
SLICE_X15Y87 FDCE (Remov_fdce_C_CLR) -0.092 -0.647 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/pushToPopGray_buffercc/buffers_0_reg[3]
|
|
-------------------------------------------------------------------
|
|
required time 0.647
|
|
arrival time -0.143
|
|
-------------------------------------------------------------------
|
|
slack 0.504
|
|
|
|
Slack (MET) : 0.504ns (arrival time - required time)
|
|
Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/buffers_1_reg/C
|
|
(rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/pushToPopGray_buffercc/buffers_1_reg[2]/CLR
|
|
(removal check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Path Group: **async_default**
|
|
Path Type: Removal (Min at Fast Process Corner)
|
|
Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns)
|
|
Data Path Delay: 0.427ns (logic 0.227ns (53.157%) route 0.200ns (46.843%))
|
|
Logic Levels: 1 (LUT1=1)
|
|
Clock Path Skew: 0.015ns (DCD - SCD - CPR)
|
|
Destination Clock Delay (DCD): -0.341ns
|
|
Source Clock Delay (SCD): -0.570ns
|
|
Clock Pessimism Removal (CPR): 0.214ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock sys_clk rise edge) 0.000 0.000 r
|
|
K21 0.000 0.000 r clk (IN)
|
|
net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1
|
|
K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O
|
|
net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll
|
|
PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1)
|
|
-2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1
|
|
net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll
|
|
BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O
|
|
net (fo=10004, routed) 0.692 -0.570 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/sys_clk
|
|
SLICE_X13Y87 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/buffers_1_reg/C
|
|
------------------------------------------------------------------- -------------------
|
|
SLICE_X13Y87 FDCE (Prop_fdce_C_Q) 0.128 -0.442 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/buffers_1_reg/Q
|
|
net (fo=1, routed) 0.053 -0.389 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/buffers_1
|
|
SLICE_X13Y87 LUT1 (Prop_lut1_I0_O) 0.099 -0.290 f u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/popCC_popPtr[2]_i_2__2/O
|
|
net (fo=30, routed) 0.147 -0.143 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/pushToPopGray_buffercc/buffers_0_reg[3]_0
|
|
SLICE_X15Y87 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/pushToPopGray_buffercc/buffers_1_reg[2]/CLR
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock sys_clk rise edge) 0.000 0.000 r
|
|
K21 0.000 0.000 r clk (IN)
|
|
net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1
|
|
K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O
|
|
net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll
|
|
PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1)
|
|
-2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1
|
|
net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll
|
|
BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O
|
|
net (fo=10004, routed) 0.967 -0.341 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/pushToPopGray_buffercc/sys_clk
|
|
SLICE_X15Y87 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/pushToPopGray_buffercc/buffers_1_reg[2]/C
|
|
clock pessimism -0.214 -0.555
|
|
SLICE_X15Y87 FDCE (Remov_fdce_C_CLR) -0.092 -0.647 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/pushToPopGray_buffercc/buffers_1_reg[2]
|
|
-------------------------------------------------------------------
|
|
required time 0.647
|
|
arrival time -0.143
|
|
-------------------------------------------------------------------
|
|
slack 0.504
|
|
|
|
Slack (MET) : 0.504ns (arrival time - required time)
|
|
Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/buffers_1_reg/C
|
|
(rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/pushToPopGray_buffercc/buffers_1_reg[3]/CLR
|
|
(removal check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Path Group: **async_default**
|
|
Path Type: Removal (Min at Fast Process Corner)
|
|
Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns)
|
|
Data Path Delay: 0.427ns (logic 0.227ns (53.157%) route 0.200ns (46.843%))
|
|
Logic Levels: 1 (LUT1=1)
|
|
Clock Path Skew: 0.015ns (DCD - SCD - CPR)
|
|
Destination Clock Delay (DCD): -0.341ns
|
|
Source Clock Delay (SCD): -0.570ns
|
|
Clock Pessimism Removal (CPR): 0.214ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock sys_clk rise edge) 0.000 0.000 r
|
|
K21 0.000 0.000 r clk (IN)
|
|
net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1
|
|
K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O
|
|
net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll
|
|
PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1)
|
|
-2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1
|
|
net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll
|
|
BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O
|
|
net (fo=10004, routed) 0.692 -0.570 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/sys_clk
|
|
SLICE_X13Y87 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/buffers_1_reg/C
|
|
------------------------------------------------------------------- -------------------
|
|
SLICE_X13Y87 FDCE (Prop_fdce_C_Q) 0.128 -0.442 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/buffers_1_reg/Q
|
|
net (fo=1, routed) 0.053 -0.389 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/buffers_1
|
|
SLICE_X13Y87 LUT1 (Prop_lut1_I0_O) 0.099 -0.290 f u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/popCC_popPtr[2]_i_2__2/O
|
|
net (fo=30, routed) 0.147 -0.143 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/pushToPopGray_buffercc/buffers_0_reg[3]_0
|
|
SLICE_X15Y87 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/pushToPopGray_buffercc/buffers_1_reg[3]/CLR
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock sys_clk rise edge) 0.000 0.000 r
|
|
K21 0.000 0.000 r clk (IN)
|
|
net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1
|
|
K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O
|
|
net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll
|
|
PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1)
|
|
-2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1
|
|
net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll
|
|
BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O
|
|
net (fo=10004, routed) 0.967 -0.341 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/pushToPopGray_buffercc/sys_clk
|
|
SLICE_X15Y87 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/pushToPopGray_buffercc/buffers_1_reg[3]/C
|
|
clock pessimism -0.214 -0.555
|
|
SLICE_X15Y87 FDCE (Remov_fdce_C_CLR) -0.092 -0.647 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/pushToPopGray_buffercc/buffers_1_reg[3]
|
|
-------------------------------------------------------------------
|
|
required time 0.647
|
|
arrival time -0.143
|
|
-------------------------------------------------------------------
|
|
slack 0.504
|
|
|
|
Slack (MET) : 0.524ns (arrival time - required time)
|
|
Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/buffers_1_reg/C
|
|
(rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/popCC_ptrToPush_reg[3]/CLR
|
|
(removal check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Path Group: **async_default**
|
|
Path Type: Removal (Min at Fast Process Corner)
|
|
Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns)
|
|
Data Path Delay: 0.468ns (logic 0.227ns (48.556%) route 0.241ns (51.444%))
|
|
Logic Levels: 1 (LUT1=1)
|
|
Clock Path Skew: 0.036ns (DCD - SCD - CPR)
|
|
Destination Clock Delay (DCD): -0.342ns
|
|
Source Clock Delay (SCD): -0.570ns
|
|
Clock Pessimism Removal (CPR): 0.192ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock sys_clk rise edge) 0.000 0.000 r
|
|
K21 0.000 0.000 r clk (IN)
|
|
net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1
|
|
K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O
|
|
net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll
|
|
PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1)
|
|
-2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1
|
|
net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll
|
|
BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O
|
|
net (fo=10004, routed) 0.692 -0.570 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/sys_clk
|
|
SLICE_X13Y87 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/buffers_1_reg/C
|
|
------------------------------------------------------------------- -------------------
|
|
SLICE_X13Y87 FDCE (Prop_fdce_C_Q) 0.128 -0.442 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/buffers_1_reg/Q
|
|
net (fo=1, routed) 0.053 -0.389 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/buffers_1
|
|
SLICE_X13Y87 LUT1 (Prop_lut1_I0_O) 0.099 -0.290 f u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/popCC_popPtr[2]_i_2__2/O
|
|
net (fo=30, routed) 0.187 -0.103 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/buffers_0_reg[3]
|
|
SLICE_X17Y86 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/popCC_ptrToPush_reg[3]/CLR
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock sys_clk rise edge) 0.000 0.000 r
|
|
K21 0.000 0.000 r clk (IN)
|
|
net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1
|
|
K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O
|
|
net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll
|
|
PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1)
|
|
-2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1
|
|
net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll
|
|
BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O
|
|
net (fo=10004, routed) 0.966 -0.342 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/sys_clk
|
|
SLICE_X17Y86 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/popCC_ptrToPush_reg[3]/C
|
|
clock pessimism -0.192 -0.534
|
|
SLICE_X17Y86 FDCE (Remov_fdce_C_CLR) -0.092 -0.626 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/popCC_ptrToPush_reg[3]
|
|
-------------------------------------------------------------------
|
|
required time 0.626
|
|
arrival time -0.103
|
|
-------------------------------------------------------------------
|
|
slack 0.524
|
|
|
|
Slack (MET) : 0.548ns (arrival time - required time)
|
|
Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/buffers_1_reg/C
|
|
(rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/popCC_popPtr_reg[1]/CLR
|
|
(removal check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Path Group: **async_default**
|
|
Path Type: Removal (Min at Fast Process Corner)
|
|
Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns)
|
|
Data Path Delay: 0.470ns (logic 0.227ns (48.316%) route 0.243ns (51.684%))
|
|
Logic Levels: 1 (LUT1=1)
|
|
Clock Path Skew: 0.014ns (DCD - SCD - CPR)
|
|
Destination Clock Delay (DCD): -0.342ns
|
|
Source Clock Delay (SCD): -0.570ns
|
|
Clock Pessimism Removal (CPR): 0.214ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock sys_clk rise edge) 0.000 0.000 r
|
|
K21 0.000 0.000 r clk (IN)
|
|
net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1
|
|
K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O
|
|
net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll
|
|
PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1)
|
|
-2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1
|
|
net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll
|
|
BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O
|
|
net (fo=10004, routed) 0.692 -0.570 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/sys_clk
|
|
SLICE_X13Y87 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/buffers_1_reg/C
|
|
------------------------------------------------------------------- -------------------
|
|
SLICE_X13Y87 FDCE (Prop_fdce_C_Q) 0.128 -0.442 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/buffers_1_reg/Q
|
|
net (fo=1, routed) 0.053 -0.389 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/buffers_1
|
|
SLICE_X13Y87 LUT1 (Prop_lut1_I0_O) 0.099 -0.290 f u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/popCC_popPtr[2]_i_2__2/O
|
|
net (fo=30, routed) 0.189 -0.101 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/buffers_0_reg[3]
|
|
SLICE_X15Y85 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/popCC_popPtr_reg[1]/CLR
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock sys_clk rise edge) 0.000 0.000 r
|
|
K21 0.000 0.000 r clk (IN)
|
|
net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1
|
|
K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O
|
|
net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll
|
|
PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1)
|
|
-2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1
|
|
net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll
|
|
BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O
|
|
net (fo=10004, routed) 0.966 -0.342 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/sys_clk
|
|
SLICE_X15Y85 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/popCC_popPtr_reg[1]/C
|
|
clock pessimism -0.214 -0.556
|
|
SLICE_X15Y85 FDCE (Remov_fdce_C_CLR) -0.092 -0.648 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/popCC_popPtr_reg[1]
|
|
-------------------------------------------------------------------
|
|
required time 0.648
|
|
arrival time -0.101
|
|
-------------------------------------------------------------------
|
|
slack 0.548
|
|
|
|
Slack (MET) : 0.558ns (arrival time - required time)
|
|
Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/buffers_1_reg/C
|
|
(rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/popCC_addressGen_rValid_reg/CLR
|
|
(removal check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Path Group: **async_default**
|
|
Path Type: Removal (Min at Fast Process Corner)
|
|
Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns)
|
|
Data Path Delay: 0.508ns (logic 0.227ns (44.714%) route 0.281ns (55.286%))
|
|
Logic Levels: 1 (LUT1=1)
|
|
Clock Path Skew: 0.017ns (DCD - SCD - CPR)
|
|
Destination Clock Delay (DCD): -0.339ns
|
|
Source Clock Delay (SCD): -0.570ns
|
|
Clock Pessimism Removal (CPR): 0.214ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock sys_clk rise edge) 0.000 0.000 r
|
|
K21 0.000 0.000 r clk (IN)
|
|
net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1
|
|
K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O
|
|
net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll
|
|
PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1)
|
|
-2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1
|
|
net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll
|
|
BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O
|
|
net (fo=10004, routed) 0.692 -0.570 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/sys_clk
|
|
SLICE_X13Y87 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/buffers_1_reg/C
|
|
------------------------------------------------------------------- -------------------
|
|
SLICE_X13Y87 FDCE (Prop_fdce_C_Q) 0.128 -0.442 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/buffers_1_reg/Q
|
|
net (fo=1, routed) 0.053 -0.389 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/buffers_1
|
|
SLICE_X13Y87 LUT1 (Prop_lut1_I0_O) 0.099 -0.290 f u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/popCC_popPtr[2]_i_2__2/O
|
|
net (fo=30, routed) 0.227 -0.063 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/buffers_0_reg[3]
|
|
SLICE_X14Y88 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/popCC_addressGen_rValid_reg/CLR
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock sys_clk rise edge) 0.000 0.000 r
|
|
K21 0.000 0.000 r clk (IN)
|
|
net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1
|
|
K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O
|
|
net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll
|
|
PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1)
|
|
-2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1
|
|
net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll
|
|
BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O
|
|
net (fo=10004, routed) 0.969 -0.339 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/sys_clk
|
|
SLICE_X14Y88 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/popCC_addressGen_rValid_reg/C
|
|
clock pessimism -0.214 -0.553
|
|
SLICE_X14Y88 FDCE (Remov_fdce_C_CLR) -0.067 -0.620 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/popCC_addressGen_rValid_reg
|
|
-------------------------------------------------------------------
|
|
required time 0.620
|
|
arrival time -0.063
|
|
-------------------------------------------------------------------
|
|
slack 0.558
|
|
|
|
Slack (MET) : 0.583ns (arrival time - required time)
|
|
Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/buffers_1_reg/C
|
|
(rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/pushToPopGray_buffercc/buffers_0_reg[0]/CLR
|
|
(removal check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Path Group: **async_default**
|
|
Path Type: Removal (Min at Fast Process Corner)
|
|
Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns)
|
|
Data Path Delay: 0.508ns (logic 0.227ns (44.714%) route 0.281ns (55.286%))
|
|
Logic Levels: 1 (LUT1=1)
|
|
Clock Path Skew: 0.017ns (DCD - SCD - CPR)
|
|
Destination Clock Delay (DCD): -0.339ns
|
|
Source Clock Delay (SCD): -0.570ns
|
|
Clock Pessimism Removal (CPR): 0.214ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock sys_clk rise edge) 0.000 0.000 r
|
|
K21 0.000 0.000 r clk (IN)
|
|
net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1
|
|
K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O
|
|
net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll
|
|
PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1)
|
|
-2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1
|
|
net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll
|
|
BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O
|
|
net (fo=10004, routed) 0.692 -0.570 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/sys_clk
|
|
SLICE_X13Y87 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/buffers_1_reg/C
|
|
------------------------------------------------------------------- -------------------
|
|
SLICE_X13Y87 FDCE (Prop_fdce_C_Q) 0.128 -0.442 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/buffers_1_reg/Q
|
|
net (fo=1, routed) 0.053 -0.389 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/buffers_1
|
|
SLICE_X13Y87 LUT1 (Prop_lut1_I0_O) 0.099 -0.290 f u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/popCC_popPtr[2]_i_2__2/O
|
|
net (fo=30, routed) 0.227 -0.063 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/pushToPopGray_buffercc/buffers_0_reg[3]_0
|
|
SLICE_X15Y88 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/pushToPopGray_buffercc/buffers_0_reg[0]/CLR
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock sys_clk rise edge) 0.000 0.000 r
|
|
K21 0.000 0.000 r clk (IN)
|
|
net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1
|
|
K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O
|
|
net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll
|
|
PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1)
|
|
-2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1
|
|
net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll
|
|
BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O
|
|
net (fo=10004, routed) 0.969 -0.339 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/pushToPopGray_buffercc/sys_clk
|
|
SLICE_X15Y88 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/pushToPopGray_buffercc/buffers_0_reg[0]/C
|
|
clock pessimism -0.214 -0.553
|
|
SLICE_X15Y88 FDCE (Remov_fdce_C_CLR) -0.092 -0.645 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/pushToPopGray_buffercc/buffers_0_reg[0]
|
|
-------------------------------------------------------------------
|
|
required time 0.645
|
|
arrival time -0.063
|
|
-------------------------------------------------------------------
|
|
slack 0.583
|
|
|
|
Slack (MET) : 0.583ns (arrival time - required time)
|
|
Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/buffers_1_reg/C
|
|
(rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/pushToPopGray_buffercc/buffers_0_reg[1]/CLR
|
|
(removal check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Path Group: **async_default**
|
|
Path Type: Removal (Min at Fast Process Corner)
|
|
Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns)
|
|
Data Path Delay: 0.508ns (logic 0.227ns (44.714%) route 0.281ns (55.286%))
|
|
Logic Levels: 1 (LUT1=1)
|
|
Clock Path Skew: 0.017ns (DCD - SCD - CPR)
|
|
Destination Clock Delay (DCD): -0.339ns
|
|
Source Clock Delay (SCD): -0.570ns
|
|
Clock Pessimism Removal (CPR): 0.214ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock sys_clk rise edge) 0.000 0.000 r
|
|
K21 0.000 0.000 r clk (IN)
|
|
net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1
|
|
K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O
|
|
net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll
|
|
PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1)
|
|
-2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1
|
|
net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll
|
|
BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O
|
|
net (fo=10004, routed) 0.692 -0.570 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/sys_clk
|
|
SLICE_X13Y87 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/buffers_1_reg/C
|
|
------------------------------------------------------------------- -------------------
|
|
SLICE_X13Y87 FDCE (Prop_fdce_C_Q) 0.128 -0.442 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/buffers_1_reg/Q
|
|
net (fo=1, routed) 0.053 -0.389 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/buffers_1
|
|
SLICE_X13Y87 LUT1 (Prop_lut1_I0_O) 0.099 -0.290 f u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/popCC_popPtr[2]_i_2__2/O
|
|
net (fo=30, routed) 0.227 -0.063 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/pushToPopGray_buffercc/buffers_0_reg[3]_0
|
|
SLICE_X15Y88 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/pushToPopGray_buffercc/buffers_0_reg[1]/CLR
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock sys_clk rise edge) 0.000 0.000 r
|
|
K21 0.000 0.000 r clk (IN)
|
|
net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1
|
|
K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O
|
|
net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll
|
|
PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1)
|
|
-2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1
|
|
net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll
|
|
BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O
|
|
net (fo=10004, routed) 0.969 -0.339 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/pushToPopGray_buffercc/sys_clk
|
|
SLICE_X15Y88 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/pushToPopGray_buffercc/buffers_0_reg[1]/C
|
|
clock pessimism -0.214 -0.553
|
|
SLICE_X15Y88 FDCE (Remov_fdce_C_CLR) -0.092 -0.645 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/pushToPopGray_buffercc/buffers_0_reg[1]
|
|
-------------------------------------------------------------------
|
|
required time 0.645
|
|
arrival time -0.063
|
|
-------------------------------------------------------------------
|
|
slack 0.583
|
|
|
|
Slack (MET) : 0.583ns (arrival time - required time)
|
|
Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/buffers_1_reg/C
|
|
(rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/pushToPopGray_buffercc/buffers_1_reg[0]/CLR
|
|
(removal check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Path Group: **async_default**
|
|
Path Type: Removal (Min at Fast Process Corner)
|
|
Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns)
|
|
Data Path Delay: 0.508ns (logic 0.227ns (44.714%) route 0.281ns (55.286%))
|
|
Logic Levels: 1 (LUT1=1)
|
|
Clock Path Skew: 0.017ns (DCD - SCD - CPR)
|
|
Destination Clock Delay (DCD): -0.339ns
|
|
Source Clock Delay (SCD): -0.570ns
|
|
Clock Pessimism Removal (CPR): 0.214ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock sys_clk rise edge) 0.000 0.000 r
|
|
K21 0.000 0.000 r clk (IN)
|
|
net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1
|
|
K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O
|
|
net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll
|
|
PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1)
|
|
-2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1
|
|
net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll
|
|
BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O
|
|
net (fo=10004, routed) 0.692 -0.570 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/sys_clk
|
|
SLICE_X13Y87 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/buffers_1_reg/C
|
|
------------------------------------------------------------------- -------------------
|
|
SLICE_X13Y87 FDCE (Prop_fdce_C_Q) 0.128 -0.442 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/buffers_1_reg/Q
|
|
net (fo=1, routed) 0.053 -0.389 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/buffers_1
|
|
SLICE_X13Y87 LUT1 (Prop_lut1_I0_O) 0.099 -0.290 f u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/popCC_popPtr[2]_i_2__2/O
|
|
net (fo=30, routed) 0.227 -0.063 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/pushToPopGray_buffercc/buffers_0_reg[3]_0
|
|
SLICE_X15Y88 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/pushToPopGray_buffercc/buffers_1_reg[0]/CLR
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock sys_clk rise edge) 0.000 0.000 r
|
|
K21 0.000 0.000 r clk (IN)
|
|
net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1
|
|
K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O
|
|
net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll
|
|
PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1)
|
|
-2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1
|
|
net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll
|
|
BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O
|
|
net (fo=10004, routed) 0.969 -0.339 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/pushToPopGray_buffercc/sys_clk
|
|
SLICE_X15Y88 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/pushToPopGray_buffercc/buffers_1_reg[0]/C
|
|
clock pessimism -0.214 -0.553
|
|
SLICE_X15Y88 FDCE (Remov_fdce_C_CLR) -0.092 -0.645 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/pushToPopGray_buffercc/buffers_1_reg[0]
|
|
-------------------------------------------------------------------
|
|
required time 0.645
|
|
arrival time -0.063
|
|
-------------------------------------------------------------------
|
|
slack 0.583
|
|
|
|
Slack (MET) : 0.583ns (arrival time - required time)
|
|
Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/buffers_1_reg/C
|
|
(rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/pushToPopGray_buffercc/buffers_1_reg[1]/CLR
|
|
(removal check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Path Group: **async_default**
|
|
Path Type: Removal (Min at Fast Process Corner)
|
|
Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns)
|
|
Data Path Delay: 0.508ns (logic 0.227ns (44.714%) route 0.281ns (55.286%))
|
|
Logic Levels: 1 (LUT1=1)
|
|
Clock Path Skew: 0.017ns (DCD - SCD - CPR)
|
|
Destination Clock Delay (DCD): -0.339ns
|
|
Source Clock Delay (SCD): -0.570ns
|
|
Clock Pessimism Removal (CPR): 0.214ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock sys_clk rise edge) 0.000 0.000 r
|
|
K21 0.000 0.000 r clk (IN)
|
|
net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1
|
|
K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O
|
|
net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll
|
|
PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1)
|
|
-2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1
|
|
net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll
|
|
BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O
|
|
net (fo=10004, routed) 0.692 -0.570 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/sys_clk
|
|
SLICE_X13Y87 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/buffers_1_reg/C
|
|
------------------------------------------------------------------- -------------------
|
|
SLICE_X13Y87 FDCE (Prop_fdce_C_Q) 0.128 -0.442 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/buffers_1_reg/Q
|
|
net (fo=1, routed) 0.053 -0.389 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/buffers_1
|
|
SLICE_X13Y87 LUT1 (Prop_lut1_I0_O) 0.099 -0.290 f u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/popCC_popPtr[2]_i_2__2/O
|
|
net (fo=30, routed) 0.227 -0.063 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/pushToPopGray_buffercc/buffers_0_reg[3]_0
|
|
SLICE_X15Y88 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/pushToPopGray_buffercc/buffers_1_reg[1]/CLR
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock sys_clk rise edge) 0.000 0.000 r
|
|
K21 0.000 0.000 r clk (IN)
|
|
net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1
|
|
K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O
|
|
net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll
|
|
PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1)
|
|
-2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1
|
|
net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll
|
|
BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O
|
|
net (fo=10004, routed) 0.969 -0.339 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/pushToPopGray_buffercc/sys_clk
|
|
SLICE_X15Y88 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/pushToPopGray_buffercc/buffers_1_reg[1]/C
|
|
clock pessimism -0.214 -0.553
|
|
SLICE_X15Y88 FDCE (Remov_fdce_C_CLR) -0.092 -0.645 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/pushToPopGray_buffercc/buffers_1_reg[1]
|
|
-------------------------------------------------------------------
|
|
required time 0.645
|
|
arrival time -0.063
|
|
-------------------------------------------------------------------
|
|
slack 0.583
|
|
|
|
Slack (MET) : 0.650ns (arrival time - required time)
|
|
Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/buffers_1_reg/C
|
|
(rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/popCC_popPtr_reg[3]/CLR
|
|
(removal check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Path Group: **async_default**
|
|
Path Type: Removal (Min at Fast Process Corner)
|
|
Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns)
|
|
Data Path Delay: 0.622ns (logic 0.227ns (36.501%) route 0.395ns (63.499%))
|
|
Logic Levels: 1 (LUT1=1)
|
|
Clock Path Skew: 0.039ns (DCD - SCD - CPR)
|
|
Destination Clock Delay (DCD): -0.339ns
|
|
Source Clock Delay (SCD): -0.570ns
|
|
Clock Pessimism Removal (CPR): 0.192ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock sys_clk rise edge) 0.000 0.000 r
|
|
K21 0.000 0.000 r clk (IN)
|
|
net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1
|
|
K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O
|
|
net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll
|
|
PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1)
|
|
-2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1
|
|
net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll
|
|
BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O
|
|
net (fo=10004, routed) 0.692 -0.570 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/sys_clk
|
|
SLICE_X13Y87 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/buffers_1_reg/C
|
|
------------------------------------------------------------------- -------------------
|
|
SLICE_X13Y87 FDCE (Prop_fdce_C_Q) 0.128 -0.442 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/buffers_1_reg/Q
|
|
net (fo=1, routed) 0.053 -0.389 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/buffers_1
|
|
SLICE_X13Y87 LUT1 (Prop_lut1_I0_O) 0.099 -0.290 f u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/popCC_popPtr[2]_i_2__2/O
|
|
net (fo=30, routed) 0.341 0.052 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/buffers_0_reg[3]
|
|
SLICE_X16Y88 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/popCC_popPtr_reg[3]/CLR
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock sys_clk rise edge) 0.000 0.000 r
|
|
K21 0.000 0.000 r clk (IN)
|
|
net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1
|
|
K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O
|
|
net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll
|
|
PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1)
|
|
-2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1
|
|
net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll
|
|
BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O
|
|
net (fo=10004, routed) 0.969 -0.339 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/sys_clk
|
|
SLICE_X16Y88 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/popCC_popPtr_reg[3]/C
|
|
clock pessimism -0.192 -0.531
|
|
SLICE_X16Y88 FDCE (Remov_fdce_C_CLR) -0.067 -0.598 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/popCC_popPtr_reg[3]
|
|
-------------------------------------------------------------------
|
|
required time 0.598
|
|
arrival time 0.052
|
|
-------------------------------------------------------------------
|
|
slack 0.650
|
|
|
|
Slack (MET) : 0.800ns (arrival time - required time)
|
|
Source: u_Axi_CDC/awFifo/bufferCC_12/buffers_1_reg/C
|
|
(rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Destination: u_Axi_CDC/wFifo/popCC_ptrToPush_reg[0]/CLR
|
|
(removal check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Path Group: **async_default**
|
|
Path Type: Removal (Min at Fast Process Corner)
|
|
Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns)
|
|
Data Path Delay: 1.055ns (logic 0.227ns (21.508%) route 0.828ns (78.492%))
|
|
Logic Levels: 1 (LUT1=1)
|
|
Clock Path Skew: 0.347ns (DCD - SCD - CPR)
|
|
Destination Clock Delay (DCD): -0.231ns
|
|
Source Clock Delay (SCD): -0.541ns
|
|
Clock Pessimism Removal (CPR): -0.037ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock sys_clk rise edge) 0.000 0.000 r
|
|
K21 0.000 0.000 r clk (IN)
|
|
net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1
|
|
K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O
|
|
net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll
|
|
PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1)
|
|
-2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1
|
|
net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll
|
|
BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O
|
|
net (fo=10004, routed) 0.721 -0.541 u_Axi_CDC/awFifo/bufferCC_12/sys_clk
|
|
SLICE_X7Y59 FDCE r u_Axi_CDC/awFifo/bufferCC_12/buffers_1_reg/C
|
|
------------------------------------------------------------------- -------------------
|
|
SLICE_X7Y59 FDCE (Prop_fdce_C_Q) 0.128 -0.413 r u_Axi_CDC/awFifo/bufferCC_12/buffers_1_reg/Q
|
|
net (fo=1, routed) 0.283 -0.131 u_Axi_CDC/awFifo/bufferCC_12/buffers_1
|
|
SLICE_X7Y59 LUT1 (Prop_lut1_I0_O) 0.099 -0.032 f u_Axi_CDC/awFifo/bufferCC_12/popCC_popPtr[2]_i_2/O
|
|
net (fo=43, routed) 0.546 0.514 u_Axi_CDC/wFifo/buffers_0_reg[3]
|
|
SLICE_X5Y49 FDCE f u_Axi_CDC/wFifo/popCC_ptrToPush_reg[0]/CLR
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock sys_clk rise edge) 0.000 0.000 r
|
|
K21 0.000 0.000 r clk (IN)
|
|
net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1
|
|
K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O
|
|
net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll
|
|
PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1)
|
|
-2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1
|
|
net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll
|
|
BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O
|
|
net (fo=10004, routed) 1.077 -0.231 u_Axi_CDC/wFifo/sys_clk
|
|
SLICE_X5Y49 FDCE r u_Axi_CDC/wFifo/popCC_ptrToPush_reg[0]/C
|
|
clock pessimism 0.037 -0.194
|
|
SLICE_X5Y49 FDCE (Remov_fdce_C_CLR) -0.092 -0.286 u_Axi_CDC/wFifo/popCC_ptrToPush_reg[0]
|
|
-------------------------------------------------------------------
|
|
required time 0.286
|
|
arrival time 0.514
|
|
-------------------------------------------------------------------
|
|
slack 0.800
|
|
|
|
Slack (MET) : 0.800ns (arrival time - required time)
|
|
Source: u_Axi_CDC/awFifo/bufferCC_12/buffers_1_reg/C
|
|
(rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Destination: u_Axi_CDC/wFifo/popCC_ptrToPush_reg[1]/CLR
|
|
(removal check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Path Group: **async_default**
|
|
Path Type: Removal (Min at Fast Process Corner)
|
|
Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns)
|
|
Data Path Delay: 1.055ns (logic 0.227ns (21.508%) route 0.828ns (78.492%))
|
|
Logic Levels: 1 (LUT1=1)
|
|
Clock Path Skew: 0.347ns (DCD - SCD - CPR)
|
|
Destination Clock Delay (DCD): -0.231ns
|
|
Source Clock Delay (SCD): -0.541ns
|
|
Clock Pessimism Removal (CPR): -0.037ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock sys_clk rise edge) 0.000 0.000 r
|
|
K21 0.000 0.000 r clk (IN)
|
|
net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1
|
|
K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O
|
|
net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll
|
|
PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1)
|
|
-2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1
|
|
net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll
|
|
BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O
|
|
net (fo=10004, routed) 0.721 -0.541 u_Axi_CDC/awFifo/bufferCC_12/sys_clk
|
|
SLICE_X7Y59 FDCE r u_Axi_CDC/awFifo/bufferCC_12/buffers_1_reg/C
|
|
------------------------------------------------------------------- -------------------
|
|
SLICE_X7Y59 FDCE (Prop_fdce_C_Q) 0.128 -0.413 r u_Axi_CDC/awFifo/bufferCC_12/buffers_1_reg/Q
|
|
net (fo=1, routed) 0.283 -0.131 u_Axi_CDC/awFifo/bufferCC_12/buffers_1
|
|
SLICE_X7Y59 LUT1 (Prop_lut1_I0_O) 0.099 -0.032 f u_Axi_CDC/awFifo/bufferCC_12/popCC_popPtr[2]_i_2/O
|
|
net (fo=43, routed) 0.546 0.514 u_Axi_CDC/wFifo/buffers_0_reg[3]
|
|
SLICE_X5Y49 FDCE f u_Axi_CDC/wFifo/popCC_ptrToPush_reg[1]/CLR
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock sys_clk rise edge) 0.000 0.000 r
|
|
K21 0.000 0.000 r clk (IN)
|
|
net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1
|
|
K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O
|
|
net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll
|
|
PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1)
|
|
-2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1
|
|
net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll
|
|
BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O
|
|
net (fo=10004, routed) 1.077 -0.231 u_Axi_CDC/wFifo/sys_clk
|
|
SLICE_X5Y49 FDCE r u_Axi_CDC/wFifo/popCC_ptrToPush_reg[1]/C
|
|
clock pessimism 0.037 -0.194
|
|
SLICE_X5Y49 FDCE (Remov_fdce_C_CLR) -0.092 -0.286 u_Axi_CDC/wFifo/popCC_ptrToPush_reg[1]
|
|
-------------------------------------------------------------------
|
|
required time 0.286
|
|
arrival time 0.514
|
|
-------------------------------------------------------------------
|
|
slack 0.800
|
|
|
|
Slack (MET) : 0.800ns (arrival time - required time)
|
|
Source: u_Axi_CDC/awFifo/bufferCC_12/buffers_1_reg/C
|
|
(rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Destination: u_Axi_CDC/wFifo/popCC_ptrToPush_reg[2]/CLR
|
|
(removal check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Path Group: **async_default**
|
|
Path Type: Removal (Min at Fast Process Corner)
|
|
Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns)
|
|
Data Path Delay: 1.055ns (logic 0.227ns (21.508%) route 0.828ns (78.492%))
|
|
Logic Levels: 1 (LUT1=1)
|
|
Clock Path Skew: 0.347ns (DCD - SCD - CPR)
|
|
Destination Clock Delay (DCD): -0.231ns
|
|
Source Clock Delay (SCD): -0.541ns
|
|
Clock Pessimism Removal (CPR): -0.037ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock sys_clk rise edge) 0.000 0.000 r
|
|
K21 0.000 0.000 r clk (IN)
|
|
net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1
|
|
K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O
|
|
net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll
|
|
PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1)
|
|
-2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1
|
|
net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll
|
|
BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O
|
|
net (fo=10004, routed) 0.721 -0.541 u_Axi_CDC/awFifo/bufferCC_12/sys_clk
|
|
SLICE_X7Y59 FDCE r u_Axi_CDC/awFifo/bufferCC_12/buffers_1_reg/C
|
|
------------------------------------------------------------------- -------------------
|
|
SLICE_X7Y59 FDCE (Prop_fdce_C_Q) 0.128 -0.413 r u_Axi_CDC/awFifo/bufferCC_12/buffers_1_reg/Q
|
|
net (fo=1, routed) 0.283 -0.131 u_Axi_CDC/awFifo/bufferCC_12/buffers_1
|
|
SLICE_X7Y59 LUT1 (Prop_lut1_I0_O) 0.099 -0.032 f u_Axi_CDC/awFifo/bufferCC_12/popCC_popPtr[2]_i_2/O
|
|
net (fo=43, routed) 0.546 0.514 u_Axi_CDC/wFifo/buffers_0_reg[3]
|
|
SLICE_X5Y49 FDCE f u_Axi_CDC/wFifo/popCC_ptrToPush_reg[2]/CLR
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock sys_clk rise edge) 0.000 0.000 r
|
|
K21 0.000 0.000 r clk (IN)
|
|
net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1
|
|
K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O
|
|
net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll
|
|
PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1)
|
|
-2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1
|
|
net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll
|
|
BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O
|
|
net (fo=10004, routed) 1.077 -0.231 u_Axi_CDC/wFifo/sys_clk
|
|
SLICE_X5Y49 FDCE r u_Axi_CDC/wFifo/popCC_ptrToPush_reg[2]/C
|
|
clock pessimism 0.037 -0.194
|
|
SLICE_X5Y49 FDCE (Remov_fdce_C_CLR) -0.092 -0.286 u_Axi_CDC/wFifo/popCC_ptrToPush_reg[2]
|
|
-------------------------------------------------------------------
|
|
required time 0.286
|
|
arrival time 0.514
|
|
-------------------------------------------------------------------
|
|
slack 0.800
|
|
|
|
Slack (MET) : 0.800ns (arrival time - required time)
|
|
Source: u_Axi_CDC/awFifo/bufferCC_12/buffers_1_reg/C
|
|
(rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Destination: u_Axi_CDC/wFifo/popCC_ptrToPush_reg[3]/CLR
|
|
(removal check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Path Group: **async_default**
|
|
Path Type: Removal (Min at Fast Process Corner)
|
|
Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns)
|
|
Data Path Delay: 1.055ns (logic 0.227ns (21.508%) route 0.828ns (78.492%))
|
|
Logic Levels: 1 (LUT1=1)
|
|
Clock Path Skew: 0.347ns (DCD - SCD - CPR)
|
|
Destination Clock Delay (DCD): -0.231ns
|
|
Source Clock Delay (SCD): -0.541ns
|
|
Clock Pessimism Removal (CPR): -0.037ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock sys_clk rise edge) 0.000 0.000 r
|
|
K21 0.000 0.000 r clk (IN)
|
|
net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1
|
|
K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O
|
|
net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll
|
|
PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1)
|
|
-2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1
|
|
net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll
|
|
BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O
|
|
net (fo=10004, routed) 0.721 -0.541 u_Axi_CDC/awFifo/bufferCC_12/sys_clk
|
|
SLICE_X7Y59 FDCE r u_Axi_CDC/awFifo/bufferCC_12/buffers_1_reg/C
|
|
------------------------------------------------------------------- -------------------
|
|
SLICE_X7Y59 FDCE (Prop_fdce_C_Q) 0.128 -0.413 r u_Axi_CDC/awFifo/bufferCC_12/buffers_1_reg/Q
|
|
net (fo=1, routed) 0.283 -0.131 u_Axi_CDC/awFifo/bufferCC_12/buffers_1
|
|
SLICE_X7Y59 LUT1 (Prop_lut1_I0_O) 0.099 -0.032 f u_Axi_CDC/awFifo/bufferCC_12/popCC_popPtr[2]_i_2/O
|
|
net (fo=43, routed) 0.546 0.514 u_Axi_CDC/wFifo/buffers_0_reg[3]
|
|
SLICE_X5Y49 FDCE f u_Axi_CDC/wFifo/popCC_ptrToPush_reg[3]/CLR
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock sys_clk rise edge) 0.000 0.000 r
|
|
K21 0.000 0.000 r clk (IN)
|
|
net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1
|
|
K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O
|
|
net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll
|
|
PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1)
|
|
-2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1
|
|
net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll
|
|
BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O
|
|
net (fo=10004, routed) 1.077 -0.231 u_Axi_CDC/wFifo/sys_clk
|
|
SLICE_X5Y49 FDCE r u_Axi_CDC/wFifo/popCC_ptrToPush_reg[3]/C
|
|
clock pessimism 0.037 -0.194
|
|
SLICE_X5Y49 FDCE (Remov_fdce_C_CLR) -0.092 -0.286 u_Axi_CDC/wFifo/popCC_ptrToPush_reg[3]
|
|
-------------------------------------------------------------------
|
|
required time 0.286
|
|
arrival time 0.514
|
|
-------------------------------------------------------------------
|
|
slack 0.800
|
|
|
|
Slack (MET) : 0.805ns (arrival time - required time)
|
|
Source: u_Axi_CDC/awFifo/bufferCC_12/buffers_1_reg/C
|
|
(rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Destination: u_Axi_CDC/wFifo/pushToPopGray_buffercc/buffers_0_reg[0]/CLR
|
|
(removal check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Path Group: **async_default**
|
|
Path Type: Removal (Min at Fast Process Corner)
|
|
Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns)
|
|
Data Path Delay: 1.060ns (logic 0.227ns (21.419%) route 0.833ns (78.581%))
|
|
Logic Levels: 1 (LUT1=1)
|
|
Clock Path Skew: 0.347ns (DCD - SCD - CPR)
|
|
Destination Clock Delay (DCD): -0.231ns
|
|
Source Clock Delay (SCD): -0.541ns
|
|
Clock Pessimism Removal (CPR): -0.037ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock sys_clk rise edge) 0.000 0.000 r
|
|
K21 0.000 0.000 r clk (IN)
|
|
net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1
|
|
K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O
|
|
net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll
|
|
PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1)
|
|
-2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1
|
|
net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll
|
|
BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O
|
|
net (fo=10004, routed) 0.721 -0.541 u_Axi_CDC/awFifo/bufferCC_12/sys_clk
|
|
SLICE_X7Y59 FDCE r u_Axi_CDC/awFifo/bufferCC_12/buffers_1_reg/C
|
|
------------------------------------------------------------------- -------------------
|
|
SLICE_X7Y59 FDCE (Prop_fdce_C_Q) 0.128 -0.413 r u_Axi_CDC/awFifo/bufferCC_12/buffers_1_reg/Q
|
|
net (fo=1, routed) 0.283 -0.131 u_Axi_CDC/awFifo/bufferCC_12/buffers_1
|
|
SLICE_X7Y59 LUT1 (Prop_lut1_I0_O) 0.099 -0.032 f u_Axi_CDC/awFifo/bufferCC_12/popCC_popPtr[2]_i_2/O
|
|
net (fo=43, routed) 0.550 0.518 u_Axi_CDC/wFifo/pushToPopGray_buffercc/buffers_0_reg[3]_0
|
|
SLICE_X4Y49 FDCE f u_Axi_CDC/wFifo/pushToPopGray_buffercc/buffers_0_reg[0]/CLR
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock sys_clk rise edge) 0.000 0.000 r
|
|
K21 0.000 0.000 r clk (IN)
|
|
net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1
|
|
K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O
|
|
net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll
|
|
PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1)
|
|
-2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1
|
|
net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll
|
|
BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O
|
|
net (fo=10004, routed) 1.077 -0.231 u_Axi_CDC/wFifo/pushToPopGray_buffercc/sys_clk
|
|
SLICE_X4Y49 FDCE r u_Axi_CDC/wFifo/pushToPopGray_buffercc/buffers_0_reg[0]/C
|
|
clock pessimism 0.037 -0.194
|
|
SLICE_X4Y49 FDCE (Remov_fdce_C_CLR) -0.092 -0.286 u_Axi_CDC/wFifo/pushToPopGray_buffercc/buffers_0_reg[0]
|
|
-------------------------------------------------------------------
|
|
required time 0.286
|
|
arrival time 0.518
|
|
-------------------------------------------------------------------
|
|
slack 0.805
|
|
|
|
Slack (MET) : 0.805ns (arrival time - required time)
|
|
Source: u_Axi_CDC/awFifo/bufferCC_12/buffers_1_reg/C
|
|
(rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Destination: u_Axi_CDC/wFifo/pushToPopGray_buffercc/buffers_0_reg[1]/CLR
|
|
(removal check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Path Group: **async_default**
|
|
Path Type: Removal (Min at Fast Process Corner)
|
|
Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns)
|
|
Data Path Delay: 1.060ns (logic 0.227ns (21.419%) route 0.833ns (78.581%))
|
|
Logic Levels: 1 (LUT1=1)
|
|
Clock Path Skew: 0.347ns (DCD - SCD - CPR)
|
|
Destination Clock Delay (DCD): -0.231ns
|
|
Source Clock Delay (SCD): -0.541ns
|
|
Clock Pessimism Removal (CPR): -0.037ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock sys_clk rise edge) 0.000 0.000 r
|
|
K21 0.000 0.000 r clk (IN)
|
|
net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1
|
|
K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O
|
|
net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll
|
|
PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1)
|
|
-2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1
|
|
net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll
|
|
BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O
|
|
net (fo=10004, routed) 0.721 -0.541 u_Axi_CDC/awFifo/bufferCC_12/sys_clk
|
|
SLICE_X7Y59 FDCE r u_Axi_CDC/awFifo/bufferCC_12/buffers_1_reg/C
|
|
------------------------------------------------------------------- -------------------
|
|
SLICE_X7Y59 FDCE (Prop_fdce_C_Q) 0.128 -0.413 r u_Axi_CDC/awFifo/bufferCC_12/buffers_1_reg/Q
|
|
net (fo=1, routed) 0.283 -0.131 u_Axi_CDC/awFifo/bufferCC_12/buffers_1
|
|
SLICE_X7Y59 LUT1 (Prop_lut1_I0_O) 0.099 -0.032 f u_Axi_CDC/awFifo/bufferCC_12/popCC_popPtr[2]_i_2/O
|
|
net (fo=43, routed) 0.550 0.518 u_Axi_CDC/wFifo/pushToPopGray_buffercc/buffers_0_reg[3]_0
|
|
SLICE_X4Y49 FDCE f u_Axi_CDC/wFifo/pushToPopGray_buffercc/buffers_0_reg[1]/CLR
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock sys_clk rise edge) 0.000 0.000 r
|
|
K21 0.000 0.000 r clk (IN)
|
|
net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1
|
|
K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O
|
|
net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll
|
|
PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1)
|
|
-2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1
|
|
net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll
|
|
BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O
|
|
net (fo=10004, routed) 1.077 -0.231 u_Axi_CDC/wFifo/pushToPopGray_buffercc/sys_clk
|
|
SLICE_X4Y49 FDCE r u_Axi_CDC/wFifo/pushToPopGray_buffercc/buffers_0_reg[1]/C
|
|
clock pessimism 0.037 -0.194
|
|
SLICE_X4Y49 FDCE (Remov_fdce_C_CLR) -0.092 -0.286 u_Axi_CDC/wFifo/pushToPopGray_buffercc/buffers_0_reg[1]
|
|
-------------------------------------------------------------------
|
|
required time 0.286
|
|
arrival time 0.518
|
|
-------------------------------------------------------------------
|
|
slack 0.805
|
|
|
|
Slack (MET) : 0.805ns (arrival time - required time)
|
|
Source: u_Axi_CDC/awFifo/bufferCC_12/buffers_1_reg/C
|
|
(rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Destination: u_Axi_CDC/wFifo/pushToPopGray_buffercc/buffers_0_reg[2]/CLR
|
|
(removal check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Path Group: **async_default**
|
|
Path Type: Removal (Min at Fast Process Corner)
|
|
Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns)
|
|
Data Path Delay: 1.060ns (logic 0.227ns (21.419%) route 0.833ns (78.581%))
|
|
Logic Levels: 1 (LUT1=1)
|
|
Clock Path Skew: 0.347ns (DCD - SCD - CPR)
|
|
Destination Clock Delay (DCD): -0.231ns
|
|
Source Clock Delay (SCD): -0.541ns
|
|
Clock Pessimism Removal (CPR): -0.037ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock sys_clk rise edge) 0.000 0.000 r
|
|
K21 0.000 0.000 r clk (IN)
|
|
net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1
|
|
K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O
|
|
net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll
|
|
PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1)
|
|
-2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1
|
|
net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll
|
|
BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O
|
|
net (fo=10004, routed) 0.721 -0.541 u_Axi_CDC/awFifo/bufferCC_12/sys_clk
|
|
SLICE_X7Y59 FDCE r u_Axi_CDC/awFifo/bufferCC_12/buffers_1_reg/C
|
|
------------------------------------------------------------------- -------------------
|
|
SLICE_X7Y59 FDCE (Prop_fdce_C_Q) 0.128 -0.413 r u_Axi_CDC/awFifo/bufferCC_12/buffers_1_reg/Q
|
|
net (fo=1, routed) 0.283 -0.131 u_Axi_CDC/awFifo/bufferCC_12/buffers_1
|
|
SLICE_X7Y59 LUT1 (Prop_lut1_I0_O) 0.099 -0.032 f u_Axi_CDC/awFifo/bufferCC_12/popCC_popPtr[2]_i_2/O
|
|
net (fo=43, routed) 0.550 0.518 u_Axi_CDC/wFifo/pushToPopGray_buffercc/buffers_0_reg[3]_0
|
|
SLICE_X4Y49 FDCE f u_Axi_CDC/wFifo/pushToPopGray_buffercc/buffers_0_reg[2]/CLR
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock sys_clk rise edge) 0.000 0.000 r
|
|
K21 0.000 0.000 r clk (IN)
|
|
net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1
|
|
K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O
|
|
net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll
|
|
PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1)
|
|
-2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1
|
|
net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll
|
|
BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O
|
|
net (fo=10004, routed) 1.077 -0.231 u_Axi_CDC/wFifo/pushToPopGray_buffercc/sys_clk
|
|
SLICE_X4Y49 FDCE r u_Axi_CDC/wFifo/pushToPopGray_buffercc/buffers_0_reg[2]/C
|
|
clock pessimism 0.037 -0.194
|
|
SLICE_X4Y49 FDCE (Remov_fdce_C_CLR) -0.092 -0.286 u_Axi_CDC/wFifo/pushToPopGray_buffercc/buffers_0_reg[2]
|
|
-------------------------------------------------------------------
|
|
required time 0.286
|
|
arrival time 0.518
|
|
-------------------------------------------------------------------
|
|
slack 0.805
|
|
|
|
Slack (MET) : 0.805ns (arrival time - required time)
|
|
Source: u_Axi_CDC/awFifo/bufferCC_12/buffers_1_reg/C
|
|
(rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Destination: u_Axi_CDC/wFifo/pushToPopGray_buffercc/buffers_0_reg[3]/CLR
|
|
(removal check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Path Group: **async_default**
|
|
Path Type: Removal (Min at Fast Process Corner)
|
|
Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns)
|
|
Data Path Delay: 1.060ns (logic 0.227ns (21.419%) route 0.833ns (78.581%))
|
|
Logic Levels: 1 (LUT1=1)
|
|
Clock Path Skew: 0.347ns (DCD - SCD - CPR)
|
|
Destination Clock Delay (DCD): -0.231ns
|
|
Source Clock Delay (SCD): -0.541ns
|
|
Clock Pessimism Removal (CPR): -0.037ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock sys_clk rise edge) 0.000 0.000 r
|
|
K21 0.000 0.000 r clk (IN)
|
|
net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1
|
|
K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O
|
|
net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll
|
|
PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1)
|
|
-2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1
|
|
net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll
|
|
BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O
|
|
net (fo=10004, routed) 0.721 -0.541 u_Axi_CDC/awFifo/bufferCC_12/sys_clk
|
|
SLICE_X7Y59 FDCE r u_Axi_CDC/awFifo/bufferCC_12/buffers_1_reg/C
|
|
------------------------------------------------------------------- -------------------
|
|
SLICE_X7Y59 FDCE (Prop_fdce_C_Q) 0.128 -0.413 r u_Axi_CDC/awFifo/bufferCC_12/buffers_1_reg/Q
|
|
net (fo=1, routed) 0.283 -0.131 u_Axi_CDC/awFifo/bufferCC_12/buffers_1
|
|
SLICE_X7Y59 LUT1 (Prop_lut1_I0_O) 0.099 -0.032 f u_Axi_CDC/awFifo/bufferCC_12/popCC_popPtr[2]_i_2/O
|
|
net (fo=43, routed) 0.550 0.518 u_Axi_CDC/wFifo/pushToPopGray_buffercc/buffers_0_reg[3]_0
|
|
SLICE_X4Y49 FDCE f u_Axi_CDC/wFifo/pushToPopGray_buffercc/buffers_0_reg[3]/CLR
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock sys_clk rise edge) 0.000 0.000 r
|
|
K21 0.000 0.000 r clk (IN)
|
|
net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1
|
|
K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O
|
|
net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll
|
|
PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1)
|
|
-2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1
|
|
net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll
|
|
BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O
|
|
net (fo=10004, routed) 1.077 -0.231 u_Axi_CDC/wFifo/pushToPopGray_buffercc/sys_clk
|
|
SLICE_X4Y49 FDCE r u_Axi_CDC/wFifo/pushToPopGray_buffercc/buffers_0_reg[3]/C
|
|
clock pessimism 0.037 -0.194
|
|
SLICE_X4Y49 FDCE (Remov_fdce_C_CLR) -0.092 -0.286 u_Axi_CDC/wFifo/pushToPopGray_buffercc/buffers_0_reg[3]
|
|
-------------------------------------------------------------------
|
|
required time 0.286
|
|
arrival time 0.518
|
|
-------------------------------------------------------------------
|
|
slack 0.805
|
|
|
|
Slack (MET) : 0.805ns (arrival time - required time)
|
|
Source: u_Axi_CDC/awFifo/bufferCC_12/buffers_1_reg/C
|
|
(rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Destination: u_Axi_CDC/wFifo/pushToPopGray_buffercc/buffers_1_reg[0]/CLR
|
|
(removal check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Path Group: **async_default**
|
|
Path Type: Removal (Min at Fast Process Corner)
|
|
Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns)
|
|
Data Path Delay: 1.060ns (logic 0.227ns (21.419%) route 0.833ns (78.581%))
|
|
Logic Levels: 1 (LUT1=1)
|
|
Clock Path Skew: 0.347ns (DCD - SCD - CPR)
|
|
Destination Clock Delay (DCD): -0.231ns
|
|
Source Clock Delay (SCD): -0.541ns
|
|
Clock Pessimism Removal (CPR): -0.037ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock sys_clk rise edge) 0.000 0.000 r
|
|
K21 0.000 0.000 r clk (IN)
|
|
net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1
|
|
K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O
|
|
net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll
|
|
PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1)
|
|
-2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1
|
|
net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll
|
|
BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O
|
|
net (fo=10004, routed) 0.721 -0.541 u_Axi_CDC/awFifo/bufferCC_12/sys_clk
|
|
SLICE_X7Y59 FDCE r u_Axi_CDC/awFifo/bufferCC_12/buffers_1_reg/C
|
|
------------------------------------------------------------------- -------------------
|
|
SLICE_X7Y59 FDCE (Prop_fdce_C_Q) 0.128 -0.413 r u_Axi_CDC/awFifo/bufferCC_12/buffers_1_reg/Q
|
|
net (fo=1, routed) 0.283 -0.131 u_Axi_CDC/awFifo/bufferCC_12/buffers_1
|
|
SLICE_X7Y59 LUT1 (Prop_lut1_I0_O) 0.099 -0.032 f u_Axi_CDC/awFifo/bufferCC_12/popCC_popPtr[2]_i_2/O
|
|
net (fo=43, routed) 0.550 0.518 u_Axi_CDC/wFifo/pushToPopGray_buffercc/buffers_0_reg[3]_0
|
|
SLICE_X4Y49 FDCE f u_Axi_CDC/wFifo/pushToPopGray_buffercc/buffers_1_reg[0]/CLR
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock sys_clk rise edge) 0.000 0.000 r
|
|
K21 0.000 0.000 r clk (IN)
|
|
net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1
|
|
K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O
|
|
net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll
|
|
PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1)
|
|
-2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1
|
|
net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll
|
|
BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O
|
|
net (fo=10004, routed) 1.077 -0.231 u_Axi_CDC/wFifo/pushToPopGray_buffercc/sys_clk
|
|
SLICE_X4Y49 FDCE r u_Axi_CDC/wFifo/pushToPopGray_buffercc/buffers_1_reg[0]/C
|
|
clock pessimism 0.037 -0.194
|
|
SLICE_X4Y49 FDCE (Remov_fdce_C_CLR) -0.092 -0.286 u_Axi_CDC/wFifo/pushToPopGray_buffercc/buffers_1_reg[0]
|
|
-------------------------------------------------------------------
|
|
required time 0.286
|
|
arrival time 0.518
|
|
-------------------------------------------------------------------
|
|
slack 0.805
|
|
|
|
Slack (MET) : 0.805ns (arrival time - required time)
|
|
Source: u_Axi_CDC/awFifo/bufferCC_12/buffers_1_reg/C
|
|
(rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Destination: u_Axi_CDC/wFifo/pushToPopGray_buffercc/buffers_1_reg[1]/CLR
|
|
(removal check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Path Group: **async_default**
|
|
Path Type: Removal (Min at Fast Process Corner)
|
|
Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns)
|
|
Data Path Delay: 1.060ns (logic 0.227ns (21.419%) route 0.833ns (78.581%))
|
|
Logic Levels: 1 (LUT1=1)
|
|
Clock Path Skew: 0.347ns (DCD - SCD - CPR)
|
|
Destination Clock Delay (DCD): -0.231ns
|
|
Source Clock Delay (SCD): -0.541ns
|
|
Clock Pessimism Removal (CPR): -0.037ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock sys_clk rise edge) 0.000 0.000 r
|
|
K21 0.000 0.000 r clk (IN)
|
|
net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1
|
|
K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O
|
|
net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll
|
|
PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1)
|
|
-2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1
|
|
net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll
|
|
BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O
|
|
net (fo=10004, routed) 0.721 -0.541 u_Axi_CDC/awFifo/bufferCC_12/sys_clk
|
|
SLICE_X7Y59 FDCE r u_Axi_CDC/awFifo/bufferCC_12/buffers_1_reg/C
|
|
------------------------------------------------------------------- -------------------
|
|
SLICE_X7Y59 FDCE (Prop_fdce_C_Q) 0.128 -0.413 r u_Axi_CDC/awFifo/bufferCC_12/buffers_1_reg/Q
|
|
net (fo=1, routed) 0.283 -0.131 u_Axi_CDC/awFifo/bufferCC_12/buffers_1
|
|
SLICE_X7Y59 LUT1 (Prop_lut1_I0_O) 0.099 -0.032 f u_Axi_CDC/awFifo/bufferCC_12/popCC_popPtr[2]_i_2/O
|
|
net (fo=43, routed) 0.550 0.518 u_Axi_CDC/wFifo/pushToPopGray_buffercc/buffers_0_reg[3]_0
|
|
SLICE_X4Y49 FDCE f u_Axi_CDC/wFifo/pushToPopGray_buffercc/buffers_1_reg[1]/CLR
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock sys_clk rise edge) 0.000 0.000 r
|
|
K21 0.000 0.000 r clk (IN)
|
|
net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1
|
|
K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O
|
|
net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll
|
|
PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1)
|
|
-2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1
|
|
net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll
|
|
BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O
|
|
net (fo=10004, routed) 1.077 -0.231 u_Axi_CDC/wFifo/pushToPopGray_buffercc/sys_clk
|
|
SLICE_X4Y49 FDCE r u_Axi_CDC/wFifo/pushToPopGray_buffercc/buffers_1_reg[1]/C
|
|
clock pessimism 0.037 -0.194
|
|
SLICE_X4Y49 FDCE (Remov_fdce_C_CLR) -0.092 -0.286 u_Axi_CDC/wFifo/pushToPopGray_buffercc/buffers_1_reg[1]
|
|
-------------------------------------------------------------------
|
|
required time 0.286
|
|
arrival time 0.518
|
|
-------------------------------------------------------------------
|
|
slack 0.805
|
|
|
|
Slack (MET) : 0.805ns (arrival time - required time)
|
|
Source: u_Axi_CDC/awFifo/bufferCC_12/buffers_1_reg/C
|
|
(rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Destination: u_Axi_CDC/wFifo/pushToPopGray_buffercc/buffers_1_reg[2]/CLR
|
|
(removal check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Path Group: **async_default**
|
|
Path Type: Removal (Min at Fast Process Corner)
|
|
Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns)
|
|
Data Path Delay: 1.060ns (logic 0.227ns (21.419%) route 0.833ns (78.581%))
|
|
Logic Levels: 1 (LUT1=1)
|
|
Clock Path Skew: 0.347ns (DCD - SCD - CPR)
|
|
Destination Clock Delay (DCD): -0.231ns
|
|
Source Clock Delay (SCD): -0.541ns
|
|
Clock Pessimism Removal (CPR): -0.037ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock sys_clk rise edge) 0.000 0.000 r
|
|
K21 0.000 0.000 r clk (IN)
|
|
net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1
|
|
K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O
|
|
net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll
|
|
PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1)
|
|
-2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1
|
|
net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll
|
|
BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O
|
|
net (fo=10004, routed) 0.721 -0.541 u_Axi_CDC/awFifo/bufferCC_12/sys_clk
|
|
SLICE_X7Y59 FDCE r u_Axi_CDC/awFifo/bufferCC_12/buffers_1_reg/C
|
|
------------------------------------------------------------------- -------------------
|
|
SLICE_X7Y59 FDCE (Prop_fdce_C_Q) 0.128 -0.413 r u_Axi_CDC/awFifo/bufferCC_12/buffers_1_reg/Q
|
|
net (fo=1, routed) 0.283 -0.131 u_Axi_CDC/awFifo/bufferCC_12/buffers_1
|
|
SLICE_X7Y59 LUT1 (Prop_lut1_I0_O) 0.099 -0.032 f u_Axi_CDC/awFifo/bufferCC_12/popCC_popPtr[2]_i_2/O
|
|
net (fo=43, routed) 0.550 0.518 u_Axi_CDC/wFifo/pushToPopGray_buffercc/buffers_0_reg[3]_0
|
|
SLICE_X4Y49 FDCE f u_Axi_CDC/wFifo/pushToPopGray_buffercc/buffers_1_reg[2]/CLR
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock sys_clk rise edge) 0.000 0.000 r
|
|
K21 0.000 0.000 r clk (IN)
|
|
net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1
|
|
K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O
|
|
net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll
|
|
PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1)
|
|
-2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1
|
|
net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll
|
|
BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O
|
|
net (fo=10004, routed) 1.077 -0.231 u_Axi_CDC/wFifo/pushToPopGray_buffercc/sys_clk
|
|
SLICE_X4Y49 FDCE r u_Axi_CDC/wFifo/pushToPopGray_buffercc/buffers_1_reg[2]/C
|
|
clock pessimism 0.037 -0.194
|
|
SLICE_X4Y49 FDCE (Remov_fdce_C_CLR) -0.092 -0.286 u_Axi_CDC/wFifo/pushToPopGray_buffercc/buffers_1_reg[2]
|
|
-------------------------------------------------------------------
|
|
required time 0.286
|
|
arrival time 0.518
|
|
-------------------------------------------------------------------
|
|
slack 0.805
|
|
|
|
Slack (MET) : 0.805ns (arrival time - required time)
|
|
Source: u_Axi_CDC/awFifo/bufferCC_12/buffers_1_reg/C
|
|
(rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Destination: u_Axi_CDC/wFifo/pushToPopGray_buffercc/buffers_1_reg[3]/CLR
|
|
(removal check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Path Group: **async_default**
|
|
Path Type: Removal (Min at Fast Process Corner)
|
|
Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns)
|
|
Data Path Delay: 1.060ns (logic 0.227ns (21.419%) route 0.833ns (78.581%))
|
|
Logic Levels: 1 (LUT1=1)
|
|
Clock Path Skew: 0.347ns (DCD - SCD - CPR)
|
|
Destination Clock Delay (DCD): -0.231ns
|
|
Source Clock Delay (SCD): -0.541ns
|
|
Clock Pessimism Removal (CPR): -0.037ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock sys_clk rise edge) 0.000 0.000 r
|
|
K21 0.000 0.000 r clk (IN)
|
|
net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1
|
|
K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O
|
|
net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll
|
|
PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1)
|
|
-2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1
|
|
net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll
|
|
BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O
|
|
net (fo=10004, routed) 0.721 -0.541 u_Axi_CDC/awFifo/bufferCC_12/sys_clk
|
|
SLICE_X7Y59 FDCE r u_Axi_CDC/awFifo/bufferCC_12/buffers_1_reg/C
|
|
------------------------------------------------------------------- -------------------
|
|
SLICE_X7Y59 FDCE (Prop_fdce_C_Q) 0.128 -0.413 r u_Axi_CDC/awFifo/bufferCC_12/buffers_1_reg/Q
|
|
net (fo=1, routed) 0.283 -0.131 u_Axi_CDC/awFifo/bufferCC_12/buffers_1
|
|
SLICE_X7Y59 LUT1 (Prop_lut1_I0_O) 0.099 -0.032 f u_Axi_CDC/awFifo/bufferCC_12/popCC_popPtr[2]_i_2/O
|
|
net (fo=43, routed) 0.550 0.518 u_Axi_CDC/wFifo/pushToPopGray_buffercc/buffers_0_reg[3]_0
|
|
SLICE_X4Y49 FDCE f u_Axi_CDC/wFifo/pushToPopGray_buffercc/buffers_1_reg[3]/CLR
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock sys_clk rise edge) 0.000 0.000 r
|
|
K21 0.000 0.000 r clk (IN)
|
|
net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1
|
|
K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O
|
|
net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll
|
|
PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1)
|
|
-2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1
|
|
net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll
|
|
BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O
|
|
net (fo=10004, routed) 1.077 -0.231 u_Axi_CDC/wFifo/pushToPopGray_buffercc/sys_clk
|
|
SLICE_X4Y49 FDCE r u_Axi_CDC/wFifo/pushToPopGray_buffercc/buffers_1_reg[3]/C
|
|
clock pessimism 0.037 -0.194
|
|
SLICE_X4Y49 FDCE (Remov_fdce_C_CLR) -0.092 -0.286 u_Axi_CDC/wFifo/pushToPopGray_buffercc/buffers_1_reg[3]
|
|
-------------------------------------------------------------------
|
|
required time 0.286
|
|
arrival time 0.518
|
|
-------------------------------------------------------------------
|
|
slack 0.805
|
|
|
|
Slack (MET) : 0.859ns (arrival time - required time)
|
|
Source: u_Axi_CDC/awFifo/bufferCC_12/buffers_1_reg/C
|
|
(rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Destination: u_Axi_CDC/wFifo/popCC_popPtr_reg[0]/CLR
|
|
(removal check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Path Group: **async_default**
|
|
Path Type: Removal (Min at Fast Process Corner)
|
|
Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns)
|
|
Data Path Delay: 1.114ns (logic 0.227ns (20.373%) route 0.887ns (79.627%))
|
|
Logic Levels: 1 (LUT1=1)
|
|
Clock Path Skew: 0.347ns (DCD - SCD - CPR)
|
|
Destination Clock Delay (DCD): -0.231ns
|
|
Source Clock Delay (SCD): -0.541ns
|
|
Clock Pessimism Removal (CPR): -0.037ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock sys_clk rise edge) 0.000 0.000 r
|
|
K21 0.000 0.000 r clk (IN)
|
|
net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1
|
|
K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O
|
|
net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll
|
|
PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1)
|
|
-2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1
|
|
net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll
|
|
BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O
|
|
net (fo=10004, routed) 0.721 -0.541 u_Axi_CDC/awFifo/bufferCC_12/sys_clk
|
|
SLICE_X7Y59 FDCE r u_Axi_CDC/awFifo/bufferCC_12/buffers_1_reg/C
|
|
------------------------------------------------------------------- -------------------
|
|
SLICE_X7Y59 FDCE (Prop_fdce_C_Q) 0.128 -0.413 r u_Axi_CDC/awFifo/bufferCC_12/buffers_1_reg/Q
|
|
net (fo=1, routed) 0.283 -0.131 u_Axi_CDC/awFifo/bufferCC_12/buffers_1
|
|
SLICE_X7Y59 LUT1 (Prop_lut1_I0_O) 0.099 -0.032 f u_Axi_CDC/awFifo/bufferCC_12/popCC_popPtr[2]_i_2/O
|
|
net (fo=43, routed) 0.605 0.573 u_Axi_CDC/wFifo/buffers_0_reg[3]
|
|
SLICE_X4Y48 FDCE f u_Axi_CDC/wFifo/popCC_popPtr_reg[0]/CLR
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock sys_clk rise edge) 0.000 0.000 r
|
|
K21 0.000 0.000 r clk (IN)
|
|
net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1
|
|
K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O
|
|
net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll
|
|
PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1)
|
|
-2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1
|
|
net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll
|
|
BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O
|
|
net (fo=10004, routed) 1.077 -0.231 u_Axi_CDC/wFifo/sys_clk
|
|
SLICE_X4Y48 FDCE r u_Axi_CDC/wFifo/popCC_popPtr_reg[0]/C
|
|
clock pessimism 0.037 -0.194
|
|
SLICE_X4Y48 FDCE (Remov_fdce_C_CLR) -0.092 -0.286 u_Axi_CDC/wFifo/popCC_popPtr_reg[0]
|
|
-------------------------------------------------------------------
|
|
required time 0.286
|
|
arrival time 0.573
|
|
-------------------------------------------------------------------
|
|
slack 0.859
|
|
|
|
Slack (MET) : 0.859ns (arrival time - required time)
|
|
Source: u_Axi_CDC/awFifo/bufferCC_12/buffers_1_reg/C
|
|
(rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Destination: u_Axi_CDC/wFifo/popCC_popPtr_reg[1]/CLR
|
|
(removal check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Path Group: **async_default**
|
|
Path Type: Removal (Min at Fast Process Corner)
|
|
Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns)
|
|
Data Path Delay: 1.114ns (logic 0.227ns (20.373%) route 0.887ns (79.627%))
|
|
Logic Levels: 1 (LUT1=1)
|
|
Clock Path Skew: 0.347ns (DCD - SCD - CPR)
|
|
Destination Clock Delay (DCD): -0.231ns
|
|
Source Clock Delay (SCD): -0.541ns
|
|
Clock Pessimism Removal (CPR): -0.037ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock sys_clk rise edge) 0.000 0.000 r
|
|
K21 0.000 0.000 r clk (IN)
|
|
net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1
|
|
K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O
|
|
net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll
|
|
PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1)
|
|
-2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1
|
|
net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll
|
|
BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O
|
|
net (fo=10004, routed) 0.721 -0.541 u_Axi_CDC/awFifo/bufferCC_12/sys_clk
|
|
SLICE_X7Y59 FDCE r u_Axi_CDC/awFifo/bufferCC_12/buffers_1_reg/C
|
|
------------------------------------------------------------------- -------------------
|
|
SLICE_X7Y59 FDCE (Prop_fdce_C_Q) 0.128 -0.413 r u_Axi_CDC/awFifo/bufferCC_12/buffers_1_reg/Q
|
|
net (fo=1, routed) 0.283 -0.131 u_Axi_CDC/awFifo/bufferCC_12/buffers_1
|
|
SLICE_X7Y59 LUT1 (Prop_lut1_I0_O) 0.099 -0.032 f u_Axi_CDC/awFifo/bufferCC_12/popCC_popPtr[2]_i_2/O
|
|
net (fo=43, routed) 0.605 0.573 u_Axi_CDC/wFifo/buffers_0_reg[3]
|
|
SLICE_X4Y48 FDCE f u_Axi_CDC/wFifo/popCC_popPtr_reg[1]/CLR
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock sys_clk rise edge) 0.000 0.000 r
|
|
K21 0.000 0.000 r clk (IN)
|
|
net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1
|
|
K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O
|
|
net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll
|
|
PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1)
|
|
-2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1
|
|
net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll
|
|
BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O
|
|
net (fo=10004, routed) 1.077 -0.231 u_Axi_CDC/wFifo/sys_clk
|
|
SLICE_X4Y48 FDCE r u_Axi_CDC/wFifo/popCC_popPtr_reg[1]/C
|
|
clock pessimism 0.037 -0.194
|
|
SLICE_X4Y48 FDCE (Remov_fdce_C_CLR) -0.092 -0.286 u_Axi_CDC/wFifo/popCC_popPtr_reg[1]
|
|
-------------------------------------------------------------------
|
|
required time 0.286
|
|
arrival time 0.573
|
|
-------------------------------------------------------------------
|
|
slack 0.859
|
|
|
|
Slack (MET) : 0.859ns (arrival time - required time)
|
|
Source: u_Axi_CDC/awFifo/bufferCC_12/buffers_1_reg/C
|
|
(rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Destination: u_Axi_CDC/wFifo/popCC_popPtr_reg[2]/CLR
|
|
(removal check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Path Group: **async_default**
|
|
Path Type: Removal (Min at Fast Process Corner)
|
|
Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns)
|
|
Data Path Delay: 1.114ns (logic 0.227ns (20.373%) route 0.887ns (79.627%))
|
|
Logic Levels: 1 (LUT1=1)
|
|
Clock Path Skew: 0.347ns (DCD - SCD - CPR)
|
|
Destination Clock Delay (DCD): -0.231ns
|
|
Source Clock Delay (SCD): -0.541ns
|
|
Clock Pessimism Removal (CPR): -0.037ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock sys_clk rise edge) 0.000 0.000 r
|
|
K21 0.000 0.000 r clk (IN)
|
|
net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1
|
|
K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O
|
|
net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll
|
|
PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1)
|
|
-2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1
|
|
net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll
|
|
BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O
|
|
net (fo=10004, routed) 0.721 -0.541 u_Axi_CDC/awFifo/bufferCC_12/sys_clk
|
|
SLICE_X7Y59 FDCE r u_Axi_CDC/awFifo/bufferCC_12/buffers_1_reg/C
|
|
------------------------------------------------------------------- -------------------
|
|
SLICE_X7Y59 FDCE (Prop_fdce_C_Q) 0.128 -0.413 r u_Axi_CDC/awFifo/bufferCC_12/buffers_1_reg/Q
|
|
net (fo=1, routed) 0.283 -0.131 u_Axi_CDC/awFifo/bufferCC_12/buffers_1
|
|
SLICE_X7Y59 LUT1 (Prop_lut1_I0_O) 0.099 -0.032 f u_Axi_CDC/awFifo/bufferCC_12/popCC_popPtr[2]_i_2/O
|
|
net (fo=43, routed) 0.605 0.573 u_Axi_CDC/wFifo/buffers_0_reg[3]
|
|
SLICE_X4Y48 FDCE f u_Axi_CDC/wFifo/popCC_popPtr_reg[2]/CLR
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock sys_clk rise edge) 0.000 0.000 r
|
|
K21 0.000 0.000 r clk (IN)
|
|
net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1
|
|
K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O
|
|
net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll
|
|
PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1)
|
|
-2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1
|
|
net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll
|
|
BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O
|
|
net (fo=10004, routed) 1.077 -0.231 u_Axi_CDC/wFifo/sys_clk
|
|
SLICE_X4Y48 FDCE r u_Axi_CDC/wFifo/popCC_popPtr_reg[2]/C
|
|
clock pessimism 0.037 -0.194
|
|
SLICE_X4Y48 FDCE (Remov_fdce_C_CLR) -0.092 -0.286 u_Axi_CDC/wFifo/popCC_popPtr_reg[2]
|
|
-------------------------------------------------------------------
|
|
required time 0.286
|
|
arrival time 0.573
|
|
-------------------------------------------------------------------
|
|
slack 0.859
|
|
|
|
Slack (MET) : 0.859ns (arrival time - required time)
|
|
Source: u_Axi_CDC/awFifo/bufferCC_12/buffers_1_reg/C
|
|
(rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Destination: u_Axi_CDC/wFifo/popCC_popPtr_reg[3]/CLR
|
|
(removal check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Path Group: **async_default**
|
|
Path Type: Removal (Min at Fast Process Corner)
|
|
Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns)
|
|
Data Path Delay: 1.114ns (logic 0.227ns (20.373%) route 0.887ns (79.627%))
|
|
Logic Levels: 1 (LUT1=1)
|
|
Clock Path Skew: 0.347ns (DCD - SCD - CPR)
|
|
Destination Clock Delay (DCD): -0.231ns
|
|
Source Clock Delay (SCD): -0.541ns
|
|
Clock Pessimism Removal (CPR): -0.037ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock sys_clk rise edge) 0.000 0.000 r
|
|
K21 0.000 0.000 r clk (IN)
|
|
net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1
|
|
K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O
|
|
net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll
|
|
PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1)
|
|
-2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1
|
|
net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll
|
|
BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O
|
|
net (fo=10004, routed) 0.721 -0.541 u_Axi_CDC/awFifo/bufferCC_12/sys_clk
|
|
SLICE_X7Y59 FDCE r u_Axi_CDC/awFifo/bufferCC_12/buffers_1_reg/C
|
|
------------------------------------------------------------------- -------------------
|
|
SLICE_X7Y59 FDCE (Prop_fdce_C_Q) 0.128 -0.413 r u_Axi_CDC/awFifo/bufferCC_12/buffers_1_reg/Q
|
|
net (fo=1, routed) 0.283 -0.131 u_Axi_CDC/awFifo/bufferCC_12/buffers_1
|
|
SLICE_X7Y59 LUT1 (Prop_lut1_I0_O) 0.099 -0.032 f u_Axi_CDC/awFifo/bufferCC_12/popCC_popPtr[2]_i_2/O
|
|
net (fo=43, routed) 0.605 0.573 u_Axi_CDC/wFifo/buffers_0_reg[3]
|
|
SLICE_X4Y48 FDCE f u_Axi_CDC/wFifo/popCC_popPtr_reg[3]/CLR
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock sys_clk rise edge) 0.000 0.000 r
|
|
K21 0.000 0.000 r clk (IN)
|
|
net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1
|
|
K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O
|
|
net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll
|
|
PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1)
|
|
-2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1
|
|
net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll
|
|
BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O
|
|
net (fo=10004, routed) 1.077 -0.231 u_Axi_CDC/wFifo/sys_clk
|
|
SLICE_X4Y48 FDCE r u_Axi_CDC/wFifo/popCC_popPtr_reg[3]/C
|
|
clock pessimism 0.037 -0.194
|
|
SLICE_X4Y48 FDCE (Remov_fdce_C_CLR) -0.092 -0.286 u_Axi_CDC/wFifo/popCC_popPtr_reg[3]
|
|
-------------------------------------------------------------------
|
|
required time 0.286
|
|
arrival time 0.573
|
|
-------------------------------------------------------------------
|
|
slack 0.859
|
|
|
|
Slack (MET) : 1.001ns (arrival time - required time)
|
|
Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/buffers_1_reg/C
|
|
(rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/popCC_popPtr_reg[0]/CLR
|
|
(removal check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Path Group: **async_default**
|
|
Path Type: Removal (Min at Fast Process Corner)
|
|
Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns)
|
|
Data Path Delay: 0.933ns (logic 0.227ns (24.323%) route 0.706ns (75.677%))
|
|
Logic Levels: 1 (LUT1=1)
|
|
Clock Path Skew: 0.024ns (DCD - SCD - CPR)
|
|
Destination Clock Delay (DCD): -0.354ns
|
|
Source Clock Delay (SCD): -0.570ns
|
|
Clock Pessimism Removal (CPR): 0.192ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock sys_clk rise edge) 0.000 0.000 r
|
|
K21 0.000 0.000 r clk (IN)
|
|
net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1
|
|
K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O
|
|
net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll
|
|
PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1)
|
|
-2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1
|
|
net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll
|
|
BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O
|
|
net (fo=10004, routed) 0.692 -0.570 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/sys_clk
|
|
SLICE_X13Y87 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/buffers_1_reg/C
|
|
------------------------------------------------------------------- -------------------
|
|
SLICE_X13Y87 FDCE (Prop_fdce_C_Q) 0.128 -0.442 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/buffers_1_reg/Q
|
|
net (fo=1, routed) 0.053 -0.389 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/buffers_1
|
|
SLICE_X13Y87 LUT1 (Prop_lut1_I0_O) 0.099 -0.290 f u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/popCC_popPtr[2]_i_2__2/O
|
|
net (fo=30, routed) 0.653 0.363 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/buffers_0_reg[3]
|
|
SLICE_X30Y80 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/popCC_popPtr_reg[0]/CLR
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock sys_clk rise edge) 0.000 0.000 r
|
|
K21 0.000 0.000 r clk (IN)
|
|
net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1
|
|
K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O
|
|
net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll
|
|
PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1)
|
|
-2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1
|
|
net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll
|
|
BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O
|
|
net (fo=10004, routed) 0.954 -0.354 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/sys_clk
|
|
SLICE_X30Y80 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/popCC_popPtr_reg[0]/C
|
|
clock pessimism -0.192 -0.546
|
|
SLICE_X30Y80 FDCE (Remov_fdce_C_CLR) -0.092 -0.638 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/popCC_popPtr_reg[0]
|
|
-------------------------------------------------------------------
|
|
required time 0.638
|
|
arrival time 0.363
|
|
-------------------------------------------------------------------
|
|
slack 1.001
|
|
|
|
Slack (MET) : 1.001ns (arrival time - required time)
|
|
Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/buffers_1_reg/C
|
|
(rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/popCC_popPtr_reg[2]/CLR
|
|
(removal check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Path Group: **async_default**
|
|
Path Type: Removal (Min at Fast Process Corner)
|
|
Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns)
|
|
Data Path Delay: 0.933ns (logic 0.227ns (24.323%) route 0.706ns (75.677%))
|
|
Logic Levels: 1 (LUT1=1)
|
|
Clock Path Skew: 0.024ns (DCD - SCD - CPR)
|
|
Destination Clock Delay (DCD): -0.354ns
|
|
Source Clock Delay (SCD): -0.570ns
|
|
Clock Pessimism Removal (CPR): 0.192ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock sys_clk rise edge) 0.000 0.000 r
|
|
K21 0.000 0.000 r clk (IN)
|
|
net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1
|
|
K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O
|
|
net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll
|
|
PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1)
|
|
-2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1
|
|
net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll
|
|
BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O
|
|
net (fo=10004, routed) 0.692 -0.570 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/sys_clk
|
|
SLICE_X13Y87 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/buffers_1_reg/C
|
|
------------------------------------------------------------------- -------------------
|
|
SLICE_X13Y87 FDCE (Prop_fdce_C_Q) 0.128 -0.442 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/buffers_1_reg/Q
|
|
net (fo=1, routed) 0.053 -0.389 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/buffers_1
|
|
SLICE_X13Y87 LUT1 (Prop_lut1_I0_O) 0.099 -0.290 f u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/popCC_popPtr[2]_i_2__2/O
|
|
net (fo=30, routed) 0.653 0.363 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/buffers_0_reg[3]
|
|
SLICE_X30Y80 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/popCC_popPtr_reg[2]/CLR
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock sys_clk rise edge) 0.000 0.000 r
|
|
K21 0.000 0.000 r clk (IN)
|
|
net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1
|
|
K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O
|
|
net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll
|
|
PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1)
|
|
-2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1
|
|
net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll
|
|
BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O
|
|
net (fo=10004, routed) 0.954 -0.354 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/sys_clk
|
|
SLICE_X30Y80 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/popCC_popPtr_reg[2]/C
|
|
clock pessimism -0.192 -0.546
|
|
SLICE_X30Y80 FDCE (Remov_fdce_C_CLR) -0.092 -0.638 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/popCC_popPtr_reg[2]
|
|
-------------------------------------------------------------------
|
|
required time 0.638
|
|
arrival time 0.363
|
|
-------------------------------------------------------------------
|
|
slack 1.001
|
|
|
|
Slack (MET) : 1.086ns (arrival time - required time)
|
|
Source: u_Axi_CDC/awFifo/bufferCC_12/buffers_1_reg/C
|
|
(rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Destination: u_Axi_CDC/awFifo/popCC_popPtr_reg[1]/CLR
|
|
(removal check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Path Group: **async_default**
|
|
Path Type: Removal (Min at Fast Process Corner)
|
|
Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns)
|
|
Data Path Delay: 1.001ns (logic 0.227ns (22.676%) route 0.774ns (77.324%))
|
|
Logic Levels: 1 (LUT1=1)
|
|
Clock Path Skew: 0.007ns (DCD - SCD - CPR)
|
|
Destination Clock Delay (DCD): -0.342ns
|
|
Source Clock Delay (SCD): -0.541ns
|
|
Clock Pessimism Removal (CPR): 0.192ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock sys_clk rise edge) 0.000 0.000 r
|
|
K21 0.000 0.000 r clk (IN)
|
|
net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1
|
|
K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O
|
|
net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll
|
|
PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1)
|
|
-2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1
|
|
net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll
|
|
BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O
|
|
net (fo=10004, routed) 0.721 -0.541 u_Axi_CDC/awFifo/bufferCC_12/sys_clk
|
|
SLICE_X7Y59 FDCE r u_Axi_CDC/awFifo/bufferCC_12/buffers_1_reg/C
|
|
------------------------------------------------------------------- -------------------
|
|
SLICE_X7Y59 FDCE (Prop_fdce_C_Q) 0.128 -0.413 r u_Axi_CDC/awFifo/bufferCC_12/buffers_1_reg/Q
|
|
net (fo=1, routed) 0.283 -0.131 u_Axi_CDC/awFifo/bufferCC_12/buffers_1
|
|
SLICE_X7Y59 LUT1 (Prop_lut1_I0_O) 0.099 -0.032 f u_Axi_CDC/awFifo/bufferCC_12/popCC_popPtr[2]_i_2/O
|
|
net (fo=43, routed) 0.491 0.460 u_Axi_CDC/awFifo/buffers_1_reg
|
|
SLICE_X15Y64 FDCE f u_Axi_CDC/awFifo/popCC_popPtr_reg[1]/CLR
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock sys_clk rise edge) 0.000 0.000 r
|
|
K21 0.000 0.000 r clk (IN)
|
|
net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1
|
|
K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O
|
|
net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll
|
|
PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1)
|
|
-2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1
|
|
net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll
|
|
BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O
|
|
net (fo=10004, routed) 0.966 -0.342 u_Axi_CDC/awFifo/sys_clk
|
|
SLICE_X15Y64 FDCE r u_Axi_CDC/awFifo/popCC_popPtr_reg[1]/C
|
|
clock pessimism -0.192 -0.534
|
|
SLICE_X15Y64 FDCE (Remov_fdce_C_CLR) -0.092 -0.626 u_Axi_CDC/awFifo/popCC_popPtr_reg[1]
|
|
-------------------------------------------------------------------
|
|
required time 0.626
|
|
arrival time 0.460
|
|
-------------------------------------------------------------------
|
|
slack 1.086
|
|
|
|
Slack (MET) : 1.139ns (arrival time - required time)
|
|
Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/buffers_1_reg/C
|
|
(rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/popCC_popPtr_reg[0]/CLR
|
|
(removal check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Path Group: **async_default**
|
|
Path Type: Removal (Min at Fast Process Corner)
|
|
Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns)
|
|
Data Path Delay: 1.070ns (logic 0.227ns (21.214%) route 0.843ns (78.786%))
|
|
Logic Levels: 1 (LUT1=1)
|
|
Clock Path Skew: 0.023ns (DCD - SCD - CPR)
|
|
Destination Clock Delay (DCD): -0.355ns
|
|
Source Clock Delay (SCD): -0.570ns
|
|
Clock Pessimism Removal (CPR): 0.192ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock sys_clk rise edge) 0.000 0.000 r
|
|
K21 0.000 0.000 r clk (IN)
|
|
net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1
|
|
K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O
|
|
net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll
|
|
PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1)
|
|
-2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1
|
|
net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll
|
|
BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O
|
|
net (fo=10004, routed) 0.692 -0.570 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/sys_clk
|
|
SLICE_X13Y87 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/buffers_1_reg/C
|
|
------------------------------------------------------------------- -------------------
|
|
SLICE_X13Y87 FDCE (Prop_fdce_C_Q) 0.128 -0.442 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/buffers_1_reg/Q
|
|
net (fo=1, routed) 0.053 -0.389 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/buffers_1
|
|
SLICE_X13Y87 LUT1 (Prop_lut1_I0_O) 0.099 -0.290 f u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/popCC_popPtr[2]_i_2__2/O
|
|
net (fo=30, routed) 0.790 0.500 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/buffers_1_reg
|
|
SLICE_X26Y72 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/popCC_popPtr_reg[0]/CLR
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock sys_clk rise edge) 0.000 0.000 r
|
|
K21 0.000 0.000 r clk (IN)
|
|
net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1
|
|
K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O
|
|
net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll
|
|
PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1)
|
|
-2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1
|
|
net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll
|
|
BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O
|
|
net (fo=10004, routed) 0.953 -0.355 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/sys_clk
|
|
SLICE_X26Y72 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/popCC_popPtr_reg[0]/C
|
|
clock pessimism -0.192 -0.547
|
|
SLICE_X26Y72 FDCE (Remov_fdce_C_CLR) -0.092 -0.639 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/popCC_popPtr_reg[0]
|
|
-------------------------------------------------------------------
|
|
required time 0.639
|
|
arrival time 0.500
|
|
-------------------------------------------------------------------
|
|
slack 1.139
|
|
|
|
Slack (MET) : 1.139ns (arrival time - required time)
|
|
Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/buffers_1_reg/C
|
|
(rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/popCC_popPtr_reg[1]/CLR
|
|
(removal check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Path Group: **async_default**
|
|
Path Type: Removal (Min at Fast Process Corner)
|
|
Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns)
|
|
Data Path Delay: 1.070ns (logic 0.227ns (21.214%) route 0.843ns (78.786%))
|
|
Logic Levels: 1 (LUT1=1)
|
|
Clock Path Skew: 0.023ns (DCD - SCD - CPR)
|
|
Destination Clock Delay (DCD): -0.355ns
|
|
Source Clock Delay (SCD): -0.570ns
|
|
Clock Pessimism Removal (CPR): 0.192ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock sys_clk rise edge) 0.000 0.000 r
|
|
K21 0.000 0.000 r clk (IN)
|
|
net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1
|
|
K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O
|
|
net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll
|
|
PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1)
|
|
-2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1
|
|
net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll
|
|
BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O
|
|
net (fo=10004, routed) 0.692 -0.570 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/sys_clk
|
|
SLICE_X13Y87 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/buffers_1_reg/C
|
|
------------------------------------------------------------------- -------------------
|
|
SLICE_X13Y87 FDCE (Prop_fdce_C_Q) 0.128 -0.442 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/buffers_1_reg/Q
|
|
net (fo=1, routed) 0.053 -0.389 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/buffers_1
|
|
SLICE_X13Y87 LUT1 (Prop_lut1_I0_O) 0.099 -0.290 f u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/popCC_popPtr[2]_i_2__2/O
|
|
net (fo=30, routed) 0.790 0.500 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/buffers_1_reg
|
|
SLICE_X26Y72 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/popCC_popPtr_reg[1]/CLR
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock sys_clk rise edge) 0.000 0.000 r
|
|
K21 0.000 0.000 r clk (IN)
|
|
net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1
|
|
K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O
|
|
net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll
|
|
PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1)
|
|
-2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1
|
|
net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll
|
|
BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O
|
|
net (fo=10004, routed) 0.953 -0.355 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/sys_clk
|
|
SLICE_X26Y72 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/popCC_popPtr_reg[1]/C
|
|
clock pessimism -0.192 -0.547
|
|
SLICE_X26Y72 FDCE (Remov_fdce_C_CLR) -0.092 -0.639 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/popCC_popPtr_reg[1]
|
|
-------------------------------------------------------------------
|
|
required time 0.639
|
|
arrival time 0.500
|
|
-------------------------------------------------------------------
|
|
slack 1.139
|
|
|
|
Slack (MET) : 1.139ns (arrival time - required time)
|
|
Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/buffers_1_reg/C
|
|
(rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/popCC_ptrToPush_reg[0]/CLR
|
|
(removal check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Path Group: **async_default**
|
|
Path Type: Removal (Min at Fast Process Corner)
|
|
Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns)
|
|
Data Path Delay: 1.070ns (logic 0.227ns (21.214%) route 0.843ns (78.786%))
|
|
Logic Levels: 1 (LUT1=1)
|
|
Clock Path Skew: 0.023ns (DCD - SCD - CPR)
|
|
Destination Clock Delay (DCD): -0.355ns
|
|
Source Clock Delay (SCD): -0.570ns
|
|
Clock Pessimism Removal (CPR): 0.192ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock sys_clk rise edge) 0.000 0.000 r
|
|
K21 0.000 0.000 r clk (IN)
|
|
net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1
|
|
K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O
|
|
net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll
|
|
PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1)
|
|
-2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1
|
|
net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll
|
|
BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O
|
|
net (fo=10004, routed) 0.692 -0.570 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/sys_clk
|
|
SLICE_X13Y87 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/buffers_1_reg/C
|
|
------------------------------------------------------------------- -------------------
|
|
SLICE_X13Y87 FDCE (Prop_fdce_C_Q) 0.128 -0.442 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/buffers_1_reg/Q
|
|
net (fo=1, routed) 0.053 -0.389 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/buffers_1
|
|
SLICE_X13Y87 LUT1 (Prop_lut1_I0_O) 0.099 -0.290 f u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/popCC_popPtr[2]_i_2__2/O
|
|
net (fo=30, routed) 0.790 0.500 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/buffers_1_reg
|
|
SLICE_X26Y72 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/popCC_ptrToPush_reg[0]/CLR
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock sys_clk rise edge) 0.000 0.000 r
|
|
K21 0.000 0.000 r clk (IN)
|
|
net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1
|
|
K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O
|
|
net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll
|
|
PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1)
|
|
-2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1
|
|
net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll
|
|
BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O
|
|
net (fo=10004, routed) 0.953 -0.355 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/sys_clk
|
|
SLICE_X26Y72 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/popCC_ptrToPush_reg[0]/C
|
|
clock pessimism -0.192 -0.547
|
|
SLICE_X26Y72 FDCE (Remov_fdce_C_CLR) -0.092 -0.639 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/popCC_ptrToPush_reg[0]
|
|
-------------------------------------------------------------------
|
|
required time 0.639
|
|
arrival time 0.500
|
|
-------------------------------------------------------------------
|
|
slack 1.139
|
|
|
|
Slack (MET) : 1.139ns (arrival time - required time)
|
|
Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/buffers_1_reg/C
|
|
(rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/popCC_ptrToPush_reg[1]/CLR
|
|
(removal check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Path Group: **async_default**
|
|
Path Type: Removal (Min at Fast Process Corner)
|
|
Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns)
|
|
Data Path Delay: 1.070ns (logic 0.227ns (21.214%) route 0.843ns (78.786%))
|
|
Logic Levels: 1 (LUT1=1)
|
|
Clock Path Skew: 0.023ns (DCD - SCD - CPR)
|
|
Destination Clock Delay (DCD): -0.355ns
|
|
Source Clock Delay (SCD): -0.570ns
|
|
Clock Pessimism Removal (CPR): 0.192ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock sys_clk rise edge) 0.000 0.000 r
|
|
K21 0.000 0.000 r clk (IN)
|
|
net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1
|
|
K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O
|
|
net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll
|
|
PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1)
|
|
-2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1
|
|
net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll
|
|
BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O
|
|
net (fo=10004, routed) 0.692 -0.570 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/sys_clk
|
|
SLICE_X13Y87 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/buffers_1_reg/C
|
|
------------------------------------------------------------------- -------------------
|
|
SLICE_X13Y87 FDCE (Prop_fdce_C_Q) 0.128 -0.442 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/buffers_1_reg/Q
|
|
net (fo=1, routed) 0.053 -0.389 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/buffers_1
|
|
SLICE_X13Y87 LUT1 (Prop_lut1_I0_O) 0.099 -0.290 f u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/popCC_popPtr[2]_i_2__2/O
|
|
net (fo=30, routed) 0.790 0.500 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/buffers_1_reg
|
|
SLICE_X26Y72 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/popCC_ptrToPush_reg[1]/CLR
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock sys_clk rise edge) 0.000 0.000 r
|
|
K21 0.000 0.000 r clk (IN)
|
|
net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1
|
|
K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O
|
|
net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll
|
|
PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1)
|
|
-2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1
|
|
net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll
|
|
BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O
|
|
net (fo=10004, routed) 0.953 -0.355 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/sys_clk
|
|
SLICE_X26Y72 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/popCC_ptrToPush_reg[1]/C
|
|
clock pessimism -0.192 -0.547
|
|
SLICE_X26Y72 FDCE (Remov_fdce_C_CLR) -0.092 -0.639 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/popCC_ptrToPush_reg[1]
|
|
-------------------------------------------------------------------
|
|
required time 0.639
|
|
arrival time 0.500
|
|
-------------------------------------------------------------------
|
|
slack 1.139
|
|
|
|
Slack (MET) : 1.139ns (arrival time - required time)
|
|
Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/buffers_1_reg/C
|
|
(rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/popCC_ptrToPush_reg[2]/CLR
|
|
(removal check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Path Group: **async_default**
|
|
Path Type: Removal (Min at Fast Process Corner)
|
|
Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns)
|
|
Data Path Delay: 1.070ns (logic 0.227ns (21.214%) route 0.843ns (78.786%))
|
|
Logic Levels: 1 (LUT1=1)
|
|
Clock Path Skew: 0.023ns (DCD - SCD - CPR)
|
|
Destination Clock Delay (DCD): -0.355ns
|
|
Source Clock Delay (SCD): -0.570ns
|
|
Clock Pessimism Removal (CPR): 0.192ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock sys_clk rise edge) 0.000 0.000 r
|
|
K21 0.000 0.000 r clk (IN)
|
|
net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1
|
|
K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O
|
|
net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll
|
|
PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1)
|
|
-2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1
|
|
net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll
|
|
BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O
|
|
net (fo=10004, routed) 0.692 -0.570 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/sys_clk
|
|
SLICE_X13Y87 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/buffers_1_reg/C
|
|
------------------------------------------------------------------- -------------------
|
|
SLICE_X13Y87 FDCE (Prop_fdce_C_Q) 0.128 -0.442 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/buffers_1_reg/Q
|
|
net (fo=1, routed) 0.053 -0.389 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/buffers_1
|
|
SLICE_X13Y87 LUT1 (Prop_lut1_I0_O) 0.099 -0.290 f u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/popCC_popPtr[2]_i_2__2/O
|
|
net (fo=30, routed) 0.790 0.500 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/buffers_1_reg
|
|
SLICE_X26Y72 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/popCC_ptrToPush_reg[2]/CLR
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock sys_clk rise edge) 0.000 0.000 r
|
|
K21 0.000 0.000 r clk (IN)
|
|
net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1
|
|
K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O
|
|
net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll
|
|
PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1)
|
|
-2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1
|
|
net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll
|
|
BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O
|
|
net (fo=10004, routed) 0.953 -0.355 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/sys_clk
|
|
SLICE_X26Y72 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/popCC_ptrToPush_reg[2]/C
|
|
clock pessimism -0.192 -0.547
|
|
SLICE_X26Y72 FDCE (Remov_fdce_C_CLR) -0.092 -0.639 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/popCC_ptrToPush_reg[2]
|
|
-------------------------------------------------------------------
|
|
required time 0.639
|
|
arrival time 0.500
|
|
-------------------------------------------------------------------
|
|
slack 1.139
|
|
|
|
Slack (MET) : 1.207ns (arrival time - required time)
|
|
Source: u_Axi_CDC/awFifo/bufferCC_12/buffers_1_reg/C
|
|
(rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Destination: u_Axi_CDC/arFifo/pushToPopGray_buffercc/buffers_0_reg[0]/CLR
|
|
(removal check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Path Group: **async_default**
|
|
Path Type: Removal (Min at Fast Process Corner)
|
|
Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns)
|
|
Data Path Delay: 1.120ns (logic 0.227ns (20.264%) route 0.893ns (79.736%))
|
|
Logic Levels: 1 (LUT1=1)
|
|
Clock Path Skew: 0.005ns (DCD - SCD - CPR)
|
|
Destination Clock Delay (DCD): -0.344ns
|
|
Source Clock Delay (SCD): -0.541ns
|
|
Clock Pessimism Removal (CPR): 0.192ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock sys_clk rise edge) 0.000 0.000 r
|
|
K21 0.000 0.000 r clk (IN)
|
|
net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1
|
|
K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O
|
|
net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll
|
|
PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1)
|
|
-2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1
|
|
net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll
|
|
BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O
|
|
net (fo=10004, routed) 0.721 -0.541 u_Axi_CDC/awFifo/bufferCC_12/sys_clk
|
|
SLICE_X7Y59 FDCE r u_Axi_CDC/awFifo/bufferCC_12/buffers_1_reg/C
|
|
------------------------------------------------------------------- -------------------
|
|
SLICE_X7Y59 FDCE (Prop_fdce_C_Q) 0.128 -0.413 r u_Axi_CDC/awFifo/bufferCC_12/buffers_1_reg/Q
|
|
net (fo=1, routed) 0.283 -0.131 u_Axi_CDC/awFifo/bufferCC_12/buffers_1
|
|
SLICE_X7Y59 LUT1 (Prop_lut1_I0_O) 0.099 -0.032 f u_Axi_CDC/awFifo/bufferCC_12/popCC_popPtr[2]_i_2/O
|
|
net (fo=43, routed) 0.611 0.579 u_Axi_CDC/arFifo/pushToPopGray_buffercc/buffers_0_reg[2]_1
|
|
SLICE_X15Y66 FDCE f u_Axi_CDC/arFifo/pushToPopGray_buffercc/buffers_0_reg[0]/CLR
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock sys_clk rise edge) 0.000 0.000 r
|
|
K21 0.000 0.000 r clk (IN)
|
|
net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1
|
|
K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O
|
|
net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll
|
|
PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1)
|
|
-2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1
|
|
net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll
|
|
BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O
|
|
net (fo=10004, routed) 0.964 -0.344 u_Axi_CDC/arFifo/pushToPopGray_buffercc/sys_clk
|
|
SLICE_X15Y66 FDCE r u_Axi_CDC/arFifo/pushToPopGray_buffercc/buffers_0_reg[0]/C
|
|
clock pessimism -0.192 -0.536
|
|
SLICE_X15Y66 FDCE (Remov_fdce_C_CLR) -0.092 -0.628 u_Axi_CDC/arFifo/pushToPopGray_buffercc/buffers_0_reg[0]
|
|
-------------------------------------------------------------------
|
|
required time 0.628
|
|
arrival time 0.579
|
|
-------------------------------------------------------------------
|
|
slack 1.207
|
|
|
|
Slack (MET) : 1.207ns (arrival time - required time)
|
|
Source: u_Axi_CDC/awFifo/bufferCC_12/buffers_1_reg/C
|
|
(rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Destination: u_Axi_CDC/arFifo/pushToPopGray_buffercc/buffers_0_reg[1]/CLR
|
|
(removal check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Path Group: **async_default**
|
|
Path Type: Removal (Min at Fast Process Corner)
|
|
Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns)
|
|
Data Path Delay: 1.120ns (logic 0.227ns (20.264%) route 0.893ns (79.736%))
|
|
Logic Levels: 1 (LUT1=1)
|
|
Clock Path Skew: 0.005ns (DCD - SCD - CPR)
|
|
Destination Clock Delay (DCD): -0.344ns
|
|
Source Clock Delay (SCD): -0.541ns
|
|
Clock Pessimism Removal (CPR): 0.192ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock sys_clk rise edge) 0.000 0.000 r
|
|
K21 0.000 0.000 r clk (IN)
|
|
net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1
|
|
K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O
|
|
net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll
|
|
PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1)
|
|
-2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1
|
|
net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll
|
|
BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O
|
|
net (fo=10004, routed) 0.721 -0.541 u_Axi_CDC/awFifo/bufferCC_12/sys_clk
|
|
SLICE_X7Y59 FDCE r u_Axi_CDC/awFifo/bufferCC_12/buffers_1_reg/C
|
|
------------------------------------------------------------------- -------------------
|
|
SLICE_X7Y59 FDCE (Prop_fdce_C_Q) 0.128 -0.413 r u_Axi_CDC/awFifo/bufferCC_12/buffers_1_reg/Q
|
|
net (fo=1, routed) 0.283 -0.131 u_Axi_CDC/awFifo/bufferCC_12/buffers_1
|
|
SLICE_X7Y59 LUT1 (Prop_lut1_I0_O) 0.099 -0.032 f u_Axi_CDC/awFifo/bufferCC_12/popCC_popPtr[2]_i_2/O
|
|
net (fo=43, routed) 0.611 0.579 u_Axi_CDC/arFifo/pushToPopGray_buffercc/buffers_0_reg[2]_1
|
|
SLICE_X15Y66 FDCE f u_Axi_CDC/arFifo/pushToPopGray_buffercc/buffers_0_reg[1]/CLR
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock sys_clk rise edge) 0.000 0.000 r
|
|
K21 0.000 0.000 r clk (IN)
|
|
net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1
|
|
K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O
|
|
net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll
|
|
PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1)
|
|
-2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1
|
|
net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll
|
|
BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O
|
|
net (fo=10004, routed) 0.964 -0.344 u_Axi_CDC/arFifo/pushToPopGray_buffercc/sys_clk
|
|
SLICE_X15Y66 FDCE r u_Axi_CDC/arFifo/pushToPopGray_buffercc/buffers_0_reg[1]/C
|
|
clock pessimism -0.192 -0.536
|
|
SLICE_X15Y66 FDCE (Remov_fdce_C_CLR) -0.092 -0.628 u_Axi_CDC/arFifo/pushToPopGray_buffercc/buffers_0_reg[1]
|
|
-------------------------------------------------------------------
|
|
required time 0.628
|
|
arrival time 0.579
|
|
-------------------------------------------------------------------
|
|
slack 1.207
|
|
|
|
Slack (MET) : 1.207ns (arrival time - required time)
|
|
Source: u_Axi_CDC/awFifo/bufferCC_12/buffers_1_reg/C
|
|
(rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Destination: u_Axi_CDC/arFifo/pushToPopGray_buffercc/buffers_0_reg[2]/CLR
|
|
(removal check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Path Group: **async_default**
|
|
Path Type: Removal (Min at Fast Process Corner)
|
|
Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns)
|
|
Data Path Delay: 1.120ns (logic 0.227ns (20.264%) route 0.893ns (79.736%))
|
|
Logic Levels: 1 (LUT1=1)
|
|
Clock Path Skew: 0.005ns (DCD - SCD - CPR)
|
|
Destination Clock Delay (DCD): -0.344ns
|
|
Source Clock Delay (SCD): -0.541ns
|
|
Clock Pessimism Removal (CPR): 0.192ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock sys_clk rise edge) 0.000 0.000 r
|
|
K21 0.000 0.000 r clk (IN)
|
|
net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1
|
|
K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O
|
|
net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll
|
|
PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1)
|
|
-2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1
|
|
net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll
|
|
BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O
|
|
net (fo=10004, routed) 0.721 -0.541 u_Axi_CDC/awFifo/bufferCC_12/sys_clk
|
|
SLICE_X7Y59 FDCE r u_Axi_CDC/awFifo/bufferCC_12/buffers_1_reg/C
|
|
------------------------------------------------------------------- -------------------
|
|
SLICE_X7Y59 FDCE (Prop_fdce_C_Q) 0.128 -0.413 r u_Axi_CDC/awFifo/bufferCC_12/buffers_1_reg/Q
|
|
net (fo=1, routed) 0.283 -0.131 u_Axi_CDC/awFifo/bufferCC_12/buffers_1
|
|
SLICE_X7Y59 LUT1 (Prop_lut1_I0_O) 0.099 -0.032 f u_Axi_CDC/awFifo/bufferCC_12/popCC_popPtr[2]_i_2/O
|
|
net (fo=43, routed) 0.611 0.579 u_Axi_CDC/arFifo/pushToPopGray_buffercc/buffers_0_reg[2]_1
|
|
SLICE_X15Y66 FDCE f u_Axi_CDC/arFifo/pushToPopGray_buffercc/buffers_0_reg[2]/CLR
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock sys_clk rise edge) 0.000 0.000 r
|
|
K21 0.000 0.000 r clk (IN)
|
|
net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1
|
|
K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O
|
|
net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll
|
|
PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1)
|
|
-2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1
|
|
net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll
|
|
BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O
|
|
net (fo=10004, routed) 0.964 -0.344 u_Axi_CDC/arFifo/pushToPopGray_buffercc/sys_clk
|
|
SLICE_X15Y66 FDCE r u_Axi_CDC/arFifo/pushToPopGray_buffercc/buffers_0_reg[2]/C
|
|
clock pessimism -0.192 -0.536
|
|
SLICE_X15Y66 FDCE (Remov_fdce_C_CLR) -0.092 -0.628 u_Axi_CDC/arFifo/pushToPopGray_buffercc/buffers_0_reg[2]
|
|
-------------------------------------------------------------------
|
|
required time 0.628
|
|
arrival time 0.579
|
|
-------------------------------------------------------------------
|
|
slack 1.207
|
|
|
|
Slack (MET) : 1.207ns (arrival time - required time)
|
|
Source: u_Axi_CDC/awFifo/bufferCC_12/buffers_1_reg/C
|
|
(rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Destination: u_Axi_CDC/arFifo/pushToPopGray_buffercc/buffers_1_reg[0]/CLR
|
|
(removal check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Path Group: **async_default**
|
|
Path Type: Removal (Min at Fast Process Corner)
|
|
Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns)
|
|
Data Path Delay: 1.120ns (logic 0.227ns (20.264%) route 0.893ns (79.736%))
|
|
Logic Levels: 1 (LUT1=1)
|
|
Clock Path Skew: 0.005ns (DCD - SCD - CPR)
|
|
Destination Clock Delay (DCD): -0.344ns
|
|
Source Clock Delay (SCD): -0.541ns
|
|
Clock Pessimism Removal (CPR): 0.192ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock sys_clk rise edge) 0.000 0.000 r
|
|
K21 0.000 0.000 r clk (IN)
|
|
net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1
|
|
K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O
|
|
net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll
|
|
PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1)
|
|
-2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1
|
|
net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll
|
|
BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O
|
|
net (fo=10004, routed) 0.721 -0.541 u_Axi_CDC/awFifo/bufferCC_12/sys_clk
|
|
SLICE_X7Y59 FDCE r u_Axi_CDC/awFifo/bufferCC_12/buffers_1_reg/C
|
|
------------------------------------------------------------------- -------------------
|
|
SLICE_X7Y59 FDCE (Prop_fdce_C_Q) 0.128 -0.413 r u_Axi_CDC/awFifo/bufferCC_12/buffers_1_reg/Q
|
|
net (fo=1, routed) 0.283 -0.131 u_Axi_CDC/awFifo/bufferCC_12/buffers_1
|
|
SLICE_X7Y59 LUT1 (Prop_lut1_I0_O) 0.099 -0.032 f u_Axi_CDC/awFifo/bufferCC_12/popCC_popPtr[2]_i_2/O
|
|
net (fo=43, routed) 0.611 0.579 u_Axi_CDC/arFifo/pushToPopGray_buffercc/buffers_0_reg[2]_1
|
|
SLICE_X15Y66 FDCE f u_Axi_CDC/arFifo/pushToPopGray_buffercc/buffers_1_reg[0]/CLR
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock sys_clk rise edge) 0.000 0.000 r
|
|
K21 0.000 0.000 r clk (IN)
|
|
net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1
|
|
K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O
|
|
net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll
|
|
PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1)
|
|
-2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1
|
|
net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll
|
|
BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O
|
|
net (fo=10004, routed) 0.964 -0.344 u_Axi_CDC/arFifo/pushToPopGray_buffercc/sys_clk
|
|
SLICE_X15Y66 FDCE r u_Axi_CDC/arFifo/pushToPopGray_buffercc/buffers_1_reg[0]/C
|
|
clock pessimism -0.192 -0.536
|
|
SLICE_X15Y66 FDCE (Remov_fdce_C_CLR) -0.092 -0.628 u_Axi_CDC/arFifo/pushToPopGray_buffercc/buffers_1_reg[0]
|
|
-------------------------------------------------------------------
|
|
required time 0.628
|
|
arrival time 0.579
|
|
-------------------------------------------------------------------
|
|
slack 1.207
|
|
|
|
Slack (MET) : 1.207ns (arrival time - required time)
|
|
Source: u_Axi_CDC/awFifo/bufferCC_12/buffers_1_reg/C
|
|
(rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Destination: u_Axi_CDC/arFifo/pushToPopGray_buffercc/buffers_1_reg[1]/CLR
|
|
(removal check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Path Group: **async_default**
|
|
Path Type: Removal (Min at Fast Process Corner)
|
|
Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns)
|
|
Data Path Delay: 1.120ns (logic 0.227ns (20.264%) route 0.893ns (79.736%))
|
|
Logic Levels: 1 (LUT1=1)
|
|
Clock Path Skew: 0.005ns (DCD - SCD - CPR)
|
|
Destination Clock Delay (DCD): -0.344ns
|
|
Source Clock Delay (SCD): -0.541ns
|
|
Clock Pessimism Removal (CPR): 0.192ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock sys_clk rise edge) 0.000 0.000 r
|
|
K21 0.000 0.000 r clk (IN)
|
|
net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1
|
|
K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O
|
|
net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll
|
|
PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1)
|
|
-2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1
|
|
net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll
|
|
BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O
|
|
net (fo=10004, routed) 0.721 -0.541 u_Axi_CDC/awFifo/bufferCC_12/sys_clk
|
|
SLICE_X7Y59 FDCE r u_Axi_CDC/awFifo/bufferCC_12/buffers_1_reg/C
|
|
------------------------------------------------------------------- -------------------
|
|
SLICE_X7Y59 FDCE (Prop_fdce_C_Q) 0.128 -0.413 r u_Axi_CDC/awFifo/bufferCC_12/buffers_1_reg/Q
|
|
net (fo=1, routed) 0.283 -0.131 u_Axi_CDC/awFifo/bufferCC_12/buffers_1
|
|
SLICE_X7Y59 LUT1 (Prop_lut1_I0_O) 0.099 -0.032 f u_Axi_CDC/awFifo/bufferCC_12/popCC_popPtr[2]_i_2/O
|
|
net (fo=43, routed) 0.611 0.579 u_Axi_CDC/arFifo/pushToPopGray_buffercc/buffers_0_reg[2]_1
|
|
SLICE_X15Y66 FDCE f u_Axi_CDC/arFifo/pushToPopGray_buffercc/buffers_1_reg[1]/CLR
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock sys_clk rise edge) 0.000 0.000 r
|
|
K21 0.000 0.000 r clk (IN)
|
|
net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1
|
|
K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O
|
|
net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll
|
|
PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1)
|
|
-2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1
|
|
net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll
|
|
BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O
|
|
net (fo=10004, routed) 0.964 -0.344 u_Axi_CDC/arFifo/pushToPopGray_buffercc/sys_clk
|
|
SLICE_X15Y66 FDCE r u_Axi_CDC/arFifo/pushToPopGray_buffercc/buffers_1_reg[1]/C
|
|
clock pessimism -0.192 -0.536
|
|
SLICE_X15Y66 FDCE (Remov_fdce_C_CLR) -0.092 -0.628 u_Axi_CDC/arFifo/pushToPopGray_buffercc/buffers_1_reg[1]
|
|
-------------------------------------------------------------------
|
|
required time 0.628
|
|
arrival time 0.579
|
|
-------------------------------------------------------------------
|
|
slack 1.207
|
|
|
|
Slack (MET) : 1.207ns (arrival time - required time)
|
|
Source: u_Axi_CDC/awFifo/bufferCC_12/buffers_1_reg/C
|
|
(rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Destination: u_Axi_CDC/arFifo/pushToPopGray_buffercc/buffers_1_reg[2]/CLR
|
|
(removal check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Path Group: **async_default**
|
|
Path Type: Removal (Min at Fast Process Corner)
|
|
Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns)
|
|
Data Path Delay: 1.120ns (logic 0.227ns (20.264%) route 0.893ns (79.736%))
|
|
Logic Levels: 1 (LUT1=1)
|
|
Clock Path Skew: 0.005ns (DCD - SCD - CPR)
|
|
Destination Clock Delay (DCD): -0.344ns
|
|
Source Clock Delay (SCD): -0.541ns
|
|
Clock Pessimism Removal (CPR): 0.192ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock sys_clk rise edge) 0.000 0.000 r
|
|
K21 0.000 0.000 r clk (IN)
|
|
net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1
|
|
K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O
|
|
net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll
|
|
PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1)
|
|
-2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1
|
|
net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll
|
|
BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O
|
|
net (fo=10004, routed) 0.721 -0.541 u_Axi_CDC/awFifo/bufferCC_12/sys_clk
|
|
SLICE_X7Y59 FDCE r u_Axi_CDC/awFifo/bufferCC_12/buffers_1_reg/C
|
|
------------------------------------------------------------------- -------------------
|
|
SLICE_X7Y59 FDCE (Prop_fdce_C_Q) 0.128 -0.413 r u_Axi_CDC/awFifo/bufferCC_12/buffers_1_reg/Q
|
|
net (fo=1, routed) 0.283 -0.131 u_Axi_CDC/awFifo/bufferCC_12/buffers_1
|
|
SLICE_X7Y59 LUT1 (Prop_lut1_I0_O) 0.099 -0.032 f u_Axi_CDC/awFifo/bufferCC_12/popCC_popPtr[2]_i_2/O
|
|
net (fo=43, routed) 0.611 0.579 u_Axi_CDC/arFifo/pushToPopGray_buffercc/buffers_0_reg[2]_1
|
|
SLICE_X15Y66 FDCE f u_Axi_CDC/arFifo/pushToPopGray_buffercc/buffers_1_reg[2]/CLR
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock sys_clk rise edge) 0.000 0.000 r
|
|
K21 0.000 0.000 r clk (IN)
|
|
net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1
|
|
K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O
|
|
net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll
|
|
PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1)
|
|
-2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1
|
|
net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll
|
|
BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O
|
|
net (fo=10004, routed) 0.964 -0.344 u_Axi_CDC/arFifo/pushToPopGray_buffercc/sys_clk
|
|
SLICE_X15Y66 FDCE r u_Axi_CDC/arFifo/pushToPopGray_buffercc/buffers_1_reg[2]/C
|
|
clock pessimism -0.192 -0.536
|
|
SLICE_X15Y66 FDCE (Remov_fdce_C_CLR) -0.092 -0.628 u_Axi_CDC/arFifo/pushToPopGray_buffercc/buffers_1_reg[2]
|
|
-------------------------------------------------------------------
|
|
required time 0.628
|
|
arrival time 0.579
|
|
-------------------------------------------------------------------
|
|
slack 1.207
|
|
|
|
Slack (MET) : 1.256ns (arrival time - required time)
|
|
Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/buffers_1_reg/C
|
|
(rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/pushToPopGray_buffercc/buffers_0_reg[1]/CLR
|
|
(removal check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Path Group: **async_default**
|
|
Path Type: Removal (Min at Fast Process Corner)
|
|
Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns)
|
|
Data Path Delay: 1.188ns (logic 0.227ns (19.107%) route 0.961ns (80.893%))
|
|
Logic Levels: 1 (LUT1=1)
|
|
Clock Path Skew: 0.024ns (DCD - SCD - CPR)
|
|
Destination Clock Delay (DCD): -0.354ns
|
|
Source Clock Delay (SCD): -0.570ns
|
|
Clock Pessimism Removal (CPR): 0.192ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock sys_clk rise edge) 0.000 0.000 r
|
|
K21 0.000 0.000 r clk (IN)
|
|
net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1
|
|
K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O
|
|
net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll
|
|
PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1)
|
|
-2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1
|
|
net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll
|
|
BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O
|
|
net (fo=10004, routed) 0.692 -0.570 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/sys_clk
|
|
SLICE_X13Y87 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/buffers_1_reg/C
|
|
------------------------------------------------------------------- -------------------
|
|
SLICE_X13Y87 FDCE (Prop_fdce_C_Q) 0.128 -0.442 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/buffers_1_reg/Q
|
|
net (fo=1, routed) 0.053 -0.389 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/buffers_1
|
|
SLICE_X13Y87 LUT1 (Prop_lut1_I0_O) 0.099 -0.290 f u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/popCC_popPtr[2]_i_2__2/O
|
|
net (fo=30, routed) 0.908 0.618 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/pushToPopGray_buffercc/buffers_0_reg[2]_1
|
|
SLICE_X27Y71 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/pushToPopGray_buffercc/buffers_0_reg[1]/CLR
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock sys_clk rise edge) 0.000 0.000 r
|
|
K21 0.000 0.000 r clk (IN)
|
|
net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1
|
|
K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O
|
|
net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll
|
|
PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1)
|
|
-2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1
|
|
net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll
|
|
BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O
|
|
net (fo=10004, routed) 0.954 -0.354 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/pushToPopGray_buffercc/sys_clk
|
|
SLICE_X27Y71 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/pushToPopGray_buffercc/buffers_0_reg[1]/C
|
|
clock pessimism -0.192 -0.546
|
|
SLICE_X27Y71 FDCE (Remov_fdce_C_CLR) -0.092 -0.638 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/pushToPopGray_buffercc/buffers_0_reg[1]
|
|
-------------------------------------------------------------------
|
|
required time 0.638
|
|
arrival time 0.618
|
|
-------------------------------------------------------------------
|
|
slack 1.256
|
|
|
|
Slack (MET) : 1.256ns (arrival time - required time)
|
|
Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/buffers_1_reg/C
|
|
(rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/pushToPopGray_buffercc/buffers_1_reg[1]/CLR
|
|
(removal check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Path Group: **async_default**
|
|
Path Type: Removal (Min at Fast Process Corner)
|
|
Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns)
|
|
Data Path Delay: 1.188ns (logic 0.227ns (19.107%) route 0.961ns (80.893%))
|
|
Logic Levels: 1 (LUT1=1)
|
|
Clock Path Skew: 0.024ns (DCD - SCD - CPR)
|
|
Destination Clock Delay (DCD): -0.354ns
|
|
Source Clock Delay (SCD): -0.570ns
|
|
Clock Pessimism Removal (CPR): 0.192ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock sys_clk rise edge) 0.000 0.000 r
|
|
K21 0.000 0.000 r clk (IN)
|
|
net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1
|
|
K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O
|
|
net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll
|
|
PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1)
|
|
-2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1
|
|
net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll
|
|
BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O
|
|
net (fo=10004, routed) 0.692 -0.570 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/sys_clk
|
|
SLICE_X13Y87 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/buffers_1_reg/C
|
|
------------------------------------------------------------------- -------------------
|
|
SLICE_X13Y87 FDCE (Prop_fdce_C_Q) 0.128 -0.442 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/buffers_1_reg/Q
|
|
net (fo=1, routed) 0.053 -0.389 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/buffers_1
|
|
SLICE_X13Y87 LUT1 (Prop_lut1_I0_O) 0.099 -0.290 f u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/popCC_popPtr[2]_i_2__2/O
|
|
net (fo=30, routed) 0.908 0.618 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/pushToPopGray_buffercc/buffers_0_reg[2]_1
|
|
SLICE_X27Y71 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/pushToPopGray_buffercc/buffers_1_reg[1]/CLR
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock sys_clk rise edge) 0.000 0.000 r
|
|
K21 0.000 0.000 r clk (IN)
|
|
net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1
|
|
K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O
|
|
net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll
|
|
PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1)
|
|
-2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1
|
|
net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll
|
|
BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O
|
|
net (fo=10004, routed) 0.954 -0.354 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/pushToPopGray_buffercc/sys_clk
|
|
SLICE_X27Y71 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/pushToPopGray_buffercc/buffers_1_reg[1]/C
|
|
clock pessimism -0.192 -0.546
|
|
SLICE_X27Y71 FDCE (Remov_fdce_C_CLR) -0.092 -0.638 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/pushToPopGray_buffercc/buffers_1_reg[1]
|
|
-------------------------------------------------------------------
|
|
required time 0.638
|
|
arrival time 0.618
|
|
-------------------------------------------------------------------
|
|
slack 1.256
|
|
|
|
Slack (MET) : 1.359ns (arrival time - required time)
|
|
Source: u_Axi_CDC/awFifo/bufferCC_12/buffers_1_reg/C
|
|
(rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Destination: u_Axi_CDC/arFifo/popCC_popPtr_reg[0]/CLR
|
|
(removal check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Path Group: **async_default**
|
|
Path Type: Removal (Min at Fast Process Corner)
|
|
Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns)
|
|
Data Path Delay: 1.294ns (logic 0.227ns (17.540%) route 1.067ns (82.460%))
|
|
Logic Levels: 1 (LUT1=1)
|
|
Clock Path Skew: 0.002ns (DCD - SCD - CPR)
|
|
Destination Clock Delay (DCD): -0.347ns
|
|
Source Clock Delay (SCD): -0.541ns
|
|
Clock Pessimism Removal (CPR): 0.192ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock sys_clk rise edge) 0.000 0.000 r
|
|
K21 0.000 0.000 r clk (IN)
|
|
net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1
|
|
K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O
|
|
net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll
|
|
PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1)
|
|
-2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1
|
|
net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll
|
|
BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O
|
|
net (fo=10004, routed) 0.721 -0.541 u_Axi_CDC/awFifo/bufferCC_12/sys_clk
|
|
SLICE_X7Y59 FDCE r u_Axi_CDC/awFifo/bufferCC_12/buffers_1_reg/C
|
|
------------------------------------------------------------------- -------------------
|
|
SLICE_X7Y59 FDCE (Prop_fdce_C_Q) 0.128 -0.413 r u_Axi_CDC/awFifo/bufferCC_12/buffers_1_reg/Q
|
|
net (fo=1, routed) 0.283 -0.131 u_Axi_CDC/awFifo/bufferCC_12/buffers_1
|
|
SLICE_X7Y59 LUT1 (Prop_lut1_I0_O) 0.099 -0.032 f u_Axi_CDC/awFifo/bufferCC_12/popCC_popPtr[2]_i_2/O
|
|
net (fo=43, routed) 0.785 0.753 u_Axi_CDC/arFifo/buffers_0_reg[2]
|
|
SLICE_X12Y69 FDCE f u_Axi_CDC/arFifo/popCC_popPtr_reg[0]/CLR
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock sys_clk rise edge) 0.000 0.000 r
|
|
K21 0.000 0.000 r clk (IN)
|
|
net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1
|
|
K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O
|
|
net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll
|
|
PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1)
|
|
-2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1
|
|
net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll
|
|
BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O
|
|
net (fo=10004, routed) 0.961 -0.347 u_Axi_CDC/arFifo/sys_clk
|
|
SLICE_X12Y69 FDCE r u_Axi_CDC/arFifo/popCC_popPtr_reg[0]/C
|
|
clock pessimism -0.192 -0.539
|
|
SLICE_X12Y69 FDCE (Remov_fdce_C_CLR) -0.067 -0.606 u_Axi_CDC/arFifo/popCC_popPtr_reg[0]
|
|
-------------------------------------------------------------------
|
|
required time 0.606
|
|
arrival time 0.753
|
|
-------------------------------------------------------------------
|
|
slack 1.359
|
|
|
|
Slack (MET) : 1.359ns (arrival time - required time)
|
|
Source: u_Axi_CDC/awFifo/bufferCC_12/buffers_1_reg/C
|
|
(rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Destination: u_Axi_CDC/arFifo/popCC_popPtr_reg[1]/CLR
|
|
(removal check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Path Group: **async_default**
|
|
Path Type: Removal (Min at Fast Process Corner)
|
|
Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns)
|
|
Data Path Delay: 1.294ns (logic 0.227ns (17.540%) route 1.067ns (82.460%))
|
|
Logic Levels: 1 (LUT1=1)
|
|
Clock Path Skew: 0.002ns (DCD - SCD - CPR)
|
|
Destination Clock Delay (DCD): -0.347ns
|
|
Source Clock Delay (SCD): -0.541ns
|
|
Clock Pessimism Removal (CPR): 0.192ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock sys_clk rise edge) 0.000 0.000 r
|
|
K21 0.000 0.000 r clk (IN)
|
|
net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1
|
|
K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O
|
|
net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll
|
|
PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1)
|
|
-2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1
|
|
net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll
|
|
BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O
|
|
net (fo=10004, routed) 0.721 -0.541 u_Axi_CDC/awFifo/bufferCC_12/sys_clk
|
|
SLICE_X7Y59 FDCE r u_Axi_CDC/awFifo/bufferCC_12/buffers_1_reg/C
|
|
------------------------------------------------------------------- -------------------
|
|
SLICE_X7Y59 FDCE (Prop_fdce_C_Q) 0.128 -0.413 r u_Axi_CDC/awFifo/bufferCC_12/buffers_1_reg/Q
|
|
net (fo=1, routed) 0.283 -0.131 u_Axi_CDC/awFifo/bufferCC_12/buffers_1
|
|
SLICE_X7Y59 LUT1 (Prop_lut1_I0_O) 0.099 -0.032 f u_Axi_CDC/awFifo/bufferCC_12/popCC_popPtr[2]_i_2/O
|
|
net (fo=43, routed) 0.785 0.753 u_Axi_CDC/arFifo/buffers_0_reg[2]
|
|
SLICE_X12Y69 FDCE f u_Axi_CDC/arFifo/popCC_popPtr_reg[1]/CLR
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock sys_clk rise edge) 0.000 0.000 r
|
|
K21 0.000 0.000 r clk (IN)
|
|
net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1
|
|
K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O
|
|
net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll
|
|
PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1)
|
|
-2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1
|
|
net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll
|
|
BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O
|
|
net (fo=10004, routed) 0.961 -0.347 u_Axi_CDC/arFifo/sys_clk
|
|
SLICE_X12Y69 FDCE r u_Axi_CDC/arFifo/popCC_popPtr_reg[1]/C
|
|
clock pessimism -0.192 -0.539
|
|
SLICE_X12Y69 FDCE (Remov_fdce_C_CLR) -0.067 -0.606 u_Axi_CDC/arFifo/popCC_popPtr_reg[1]
|
|
-------------------------------------------------------------------
|
|
required time 0.606
|
|
arrival time 0.753
|
|
-------------------------------------------------------------------
|
|
slack 1.359
|
|
|
|
Slack (MET) : 1.359ns (arrival time - required time)
|
|
Source: u_Axi_CDC/awFifo/bufferCC_12/buffers_1_reg/C
|
|
(rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Destination: u_Axi_CDC/arFifo/popCC_popPtr_reg[2]/CLR
|
|
(removal check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Path Group: **async_default**
|
|
Path Type: Removal (Min at Fast Process Corner)
|
|
Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns)
|
|
Data Path Delay: 1.294ns (logic 0.227ns (17.540%) route 1.067ns (82.460%))
|
|
Logic Levels: 1 (LUT1=1)
|
|
Clock Path Skew: 0.002ns (DCD - SCD - CPR)
|
|
Destination Clock Delay (DCD): -0.347ns
|
|
Source Clock Delay (SCD): -0.541ns
|
|
Clock Pessimism Removal (CPR): 0.192ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock sys_clk rise edge) 0.000 0.000 r
|
|
K21 0.000 0.000 r clk (IN)
|
|
net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1
|
|
K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O
|
|
net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll
|
|
PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1)
|
|
-2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1
|
|
net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll
|
|
BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O
|
|
net (fo=10004, routed) 0.721 -0.541 u_Axi_CDC/awFifo/bufferCC_12/sys_clk
|
|
SLICE_X7Y59 FDCE r u_Axi_CDC/awFifo/bufferCC_12/buffers_1_reg/C
|
|
------------------------------------------------------------------- -------------------
|
|
SLICE_X7Y59 FDCE (Prop_fdce_C_Q) 0.128 -0.413 r u_Axi_CDC/awFifo/bufferCC_12/buffers_1_reg/Q
|
|
net (fo=1, routed) 0.283 -0.131 u_Axi_CDC/awFifo/bufferCC_12/buffers_1
|
|
SLICE_X7Y59 LUT1 (Prop_lut1_I0_O) 0.099 -0.032 f u_Axi_CDC/awFifo/bufferCC_12/popCC_popPtr[2]_i_2/O
|
|
net (fo=43, routed) 0.785 0.753 u_Axi_CDC/arFifo/buffers_0_reg[2]
|
|
SLICE_X12Y69 FDCE f u_Axi_CDC/arFifo/popCC_popPtr_reg[2]/CLR
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock sys_clk rise edge) 0.000 0.000 r
|
|
K21 0.000 0.000 r clk (IN)
|
|
net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1
|
|
K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O
|
|
net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll
|
|
PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1)
|
|
-2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1
|
|
net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll
|
|
BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O
|
|
net (fo=10004, routed) 0.961 -0.347 u_Axi_CDC/arFifo/sys_clk
|
|
SLICE_X12Y69 FDCE r u_Axi_CDC/arFifo/popCC_popPtr_reg[2]/C
|
|
clock pessimism -0.192 -0.539
|
|
SLICE_X12Y69 FDCE (Remov_fdce_C_CLR) -0.067 -0.606 u_Axi_CDC/arFifo/popCC_popPtr_reg[2]
|
|
-------------------------------------------------------------------
|
|
required time 0.606
|
|
arrival time 0.753
|
|
-------------------------------------------------------------------
|
|
slack 1.359
|
|
|
|
|
|
|
|
|
|
|
|
--------------------------------------------------------------------------------------
|
|
Path Group: (none)
|
|
From Clock: sys_clk
|
|
To Clock: cpu_clk
|
|
|
|
Max Delay 0 Endpoints
|
|
Min Delay 59 Endpoints
|
|
--------------------------------------------------------------------------------------
|
|
|
|
|
|
Min Delay Paths
|
|
--------------------------------------------------------------------------------------
|
|
Slack: inf
|
|
Source: u_Axi_CDC/awFifo/popCC_ptrToPush_reg[0]/C
|
|
(rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Destination: u_Axi_CDC/awFifo/popToPushGray_buffercc/buffers_0_reg[0]/D
|
|
(rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns})
|
|
Path Group: (none)
|
|
Path Type: Hold (Min at Slow Process Corner)
|
|
Data Path Delay: 0.686ns (logic 0.418ns (60.951%) route 0.268ns (39.049%))
|
|
Logic Levels: 0
|
|
Clock Path Skew: -0.388ns (DCD - SCD - CPR)
|
|
Destination Clock Delay (DCD): -2.407ns
|
|
Source Clock Delay (SCD): -2.018ns
|
|
Clock Pessimism Removal (CPR): -0.000ns
|
|
Clock Uncertainty: 0.194ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Discrete Jitter (DJ): 0.130ns
|
|
Phase Error (PE): 0.120ns
|
|
Timing Exception: Asynchronous Clock Groups
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock sys_clk rise edge) 0.000 0.000 r
|
|
K21 0.000 0.000 r clk (IN)
|
|
net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1
|
|
K21 IBUF (Prop_ibuf_I_O) 1.393 1.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O
|
|
net (fo=1, routed) 1.181 2.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll
|
|
PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1)
|
|
-8.248 -5.674 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1
|
|
net (fo=1, routed) 1.755 -3.919 pll_clk.u_clk_pll/inst/sys_clk_clk_pll
|
|
BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 -3.828 r pll_clk.u_clk_pll/inst/clkout2_buf/O
|
|
net (fo=10004, routed) 1.810 -2.018 u_Axi_CDC/awFifo/sys_clk
|
|
SLICE_X16Y69 FDCE r u_Axi_CDC/awFifo/popCC_ptrToPush_reg[0]/C
|
|
------------------------------------------------------------------- -------------------
|
|
SLICE_X16Y69 FDCE (Prop_fdce_C_Q) 0.418 -1.600 r u_Axi_CDC/awFifo/popCC_ptrToPush_reg[0]/Q
|
|
net (fo=2, routed) 0.268 -1.332 u_Axi_CDC/awFifo/popToPushGray_buffercc/D[0]
|
|
SLICE_X15Y69 FDCE r u_Axi_CDC/awFifo/popToPushGray_buffercc/buffers_0_reg[0]/D
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock cpu_clk rise edge) 0.000 0.000 r
|
|
K21 0.000 0.000 r clk (IN)
|
|
net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1
|
|
K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O
|
|
net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll
|
|
PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0)
|
|
-8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0
|
|
net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll
|
|
BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout1_buf/O
|
|
net (fo=6484, routed) 1.935 -2.407 u_Axi_CDC/awFifo/popToPushGray_buffercc/cpu_clk
|
|
SLICE_X15Y69 FDCE r u_Axi_CDC/awFifo/popToPushGray_buffercc/buffers_0_reg[0]/C
|
|
|
|
Slack: inf
|
|
Source: u_Axi_CDC/rFifo/pushCC_pushPtrGray_reg[2]/C
|
|
(rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Destination: u_Axi_CDC/rFifo/pushToPopGray_buffercc/buffers_0_reg[2]/D
|
|
(rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns})
|
|
Path Group: (none)
|
|
Path Type: Hold (Min at Slow Process Corner)
|
|
Data Path Delay: 0.622ns (logic 0.367ns (58.974%) route 0.255ns (41.026%))
|
|
Logic Levels: 0
|
|
Clock Path Skew: -0.391ns (DCD - SCD - CPR)
|
|
Destination Clock Delay (DCD): -2.335ns
|
|
Source Clock Delay (SCD): -1.943ns
|
|
Clock Pessimism Removal (CPR): -0.000ns
|
|
Clock Uncertainty: 0.194ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Discrete Jitter (DJ): 0.130ns
|
|
Phase Error (PE): 0.120ns
|
|
Timing Exception: Asynchronous Clock Groups
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock sys_clk rise edge) 0.000 0.000 r
|
|
K21 0.000 0.000 r clk (IN)
|
|
net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1
|
|
K21 IBUF (Prop_ibuf_I_O) 1.393 1.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O
|
|
net (fo=1, routed) 1.181 2.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll
|
|
PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1)
|
|
-8.248 -5.674 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1
|
|
net (fo=1, routed) 1.755 -3.919 pll_clk.u_clk_pll/inst/sys_clk_clk_pll
|
|
BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 -3.828 r pll_clk.u_clk_pll/inst/clkout2_buf/O
|
|
net (fo=10004, routed) 1.885 -1.943 u_Axi_CDC/rFifo/sys_clk
|
|
SLICE_X5Y77 FDCE r u_Axi_CDC/rFifo/pushCC_pushPtrGray_reg[2]/C
|
|
------------------------------------------------------------------- -------------------
|
|
SLICE_X5Y77 FDCE (Prop_fdce_C_Q) 0.367 -1.576 r u_Axi_CDC/rFifo/pushCC_pushPtrGray_reg[2]/Q
|
|
net (fo=2, routed) 0.255 -1.321 u_Axi_CDC/rFifo/pushToPopGray_buffercc/buffers_0_reg[2]_0[2]
|
|
SLICE_X5Y76 FDCE r u_Axi_CDC/rFifo/pushToPopGray_buffercc/buffers_0_reg[2]/D
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock cpu_clk rise edge) 0.000 0.000 r
|
|
K21 0.000 0.000 r clk (IN)
|
|
net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1
|
|
K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O
|
|
net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll
|
|
PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0)
|
|
-8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0
|
|
net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll
|
|
BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout1_buf/O
|
|
net (fo=6484, routed) 2.007 -2.335 u_Axi_CDC/rFifo/pushToPopGray_buffercc/cpu_clk
|
|
SLICE_X5Y76 FDCE r u_Axi_CDC/rFifo/pushToPopGray_buffercc/buffers_0_reg[2]/C
|
|
|
|
Slack: inf
|
|
Source: u_Axi_CDC/rFifo/pushCC_pushPtrGray_reg[0]/C
|
|
(rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Destination: u_Axi_CDC/rFifo/pushToPopGray_buffercc/buffers_0_reg[0]/D
|
|
(rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns})
|
|
Path Group: (none)
|
|
Path Type: Hold (Min at Slow Process Corner)
|
|
Data Path Delay: 0.623ns (logic 0.367ns (58.905%) route 0.256ns (41.095%))
|
|
Logic Levels: 0
|
|
Clock Path Skew: -0.391ns (DCD - SCD - CPR)
|
|
Destination Clock Delay (DCD): -2.335ns
|
|
Source Clock Delay (SCD): -1.943ns
|
|
Clock Pessimism Removal (CPR): -0.000ns
|
|
Clock Uncertainty: 0.194ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Discrete Jitter (DJ): 0.130ns
|
|
Phase Error (PE): 0.120ns
|
|
Timing Exception: Asynchronous Clock Groups
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock sys_clk rise edge) 0.000 0.000 r
|
|
K21 0.000 0.000 r clk (IN)
|
|
net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1
|
|
K21 IBUF (Prop_ibuf_I_O) 1.393 1.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O
|
|
net (fo=1, routed) 1.181 2.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll
|
|
PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1)
|
|
-8.248 -5.674 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1
|
|
net (fo=1, routed) 1.755 -3.919 pll_clk.u_clk_pll/inst/sys_clk_clk_pll
|
|
BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 -3.828 r pll_clk.u_clk_pll/inst/clkout2_buf/O
|
|
net (fo=10004, routed) 1.885 -1.943 u_Axi_CDC/rFifo/sys_clk
|
|
SLICE_X5Y77 FDCE r u_Axi_CDC/rFifo/pushCC_pushPtrGray_reg[0]/C
|
|
------------------------------------------------------------------- -------------------
|
|
SLICE_X5Y77 FDCE (Prop_fdce_C_Q) 0.367 -1.576 r u_Axi_CDC/rFifo/pushCC_pushPtrGray_reg[0]/Q
|
|
net (fo=2, routed) 0.256 -1.320 u_Axi_CDC/rFifo/pushToPopGray_buffercc/buffers_0_reg[2]_0[0]
|
|
SLICE_X5Y76 FDCE r u_Axi_CDC/rFifo/pushToPopGray_buffercc/buffers_0_reg[0]/D
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock cpu_clk rise edge) 0.000 0.000 r
|
|
K21 0.000 0.000 r clk (IN)
|
|
net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1
|
|
K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O
|
|
net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll
|
|
PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0)
|
|
-8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0
|
|
net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll
|
|
BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout1_buf/O
|
|
net (fo=6484, routed) 2.007 -2.335 u_Axi_CDC/rFifo/pushToPopGray_buffercc/cpu_clk
|
|
SLICE_X5Y76 FDCE r u_Axi_CDC/rFifo/pushToPopGray_buffercc/buffers_0_reg[0]/C
|
|
|
|
Slack: inf
|
|
Source: u_Axi_CDC/awFifo/popCC_ptrToPush_reg[2]/C
|
|
(rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Destination: u_Axi_CDC/awFifo/popToPushGray_buffercc/buffers_0_reg[2]/D
|
|
(rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns})
|
|
Path Group: (none)
|
|
Path Type: Hold (Min at Slow Process Corner)
|
|
Data Path Delay: 0.720ns (logic 0.337ns (46.825%) route 0.383ns (53.175%))
|
|
Logic Levels: 0
|
|
Clock Path Skew: -0.388ns (DCD - SCD - CPR)
|
|
Destination Clock Delay (DCD): -2.407ns
|
|
Source Clock Delay (SCD): -2.018ns
|
|
Clock Pessimism Removal (CPR): -0.000ns
|
|
Clock Uncertainty: 0.194ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Discrete Jitter (DJ): 0.130ns
|
|
Phase Error (PE): 0.120ns
|
|
Timing Exception: Asynchronous Clock Groups
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock sys_clk rise edge) 0.000 0.000 r
|
|
K21 0.000 0.000 r clk (IN)
|
|
net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1
|
|
K21 IBUF (Prop_ibuf_I_O) 1.393 1.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O
|
|
net (fo=1, routed) 1.181 2.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll
|
|
PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1)
|
|
-8.248 -5.674 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1
|
|
net (fo=1, routed) 1.755 -3.919 pll_clk.u_clk_pll/inst/sys_clk_clk_pll
|
|
BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 -3.828 r pll_clk.u_clk_pll/inst/clkout2_buf/O
|
|
net (fo=10004, routed) 1.810 -2.018 u_Axi_CDC/awFifo/sys_clk
|
|
SLICE_X15Y70 FDCE r u_Axi_CDC/awFifo/popCC_ptrToPush_reg[2]/C
|
|
------------------------------------------------------------------- -------------------
|
|
SLICE_X15Y70 FDCE (Prop_fdce_C_Q) 0.337 -1.681 r u_Axi_CDC/awFifo/popCC_ptrToPush_reg[2]/Q
|
|
net (fo=2, routed) 0.383 -1.299 u_Axi_CDC/awFifo/popToPushGray_buffercc/D[2]
|
|
SLICE_X15Y69 FDCE r u_Axi_CDC/awFifo/popToPushGray_buffercc/buffers_0_reg[2]/D
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock cpu_clk rise edge) 0.000 0.000 r
|
|
K21 0.000 0.000 r clk (IN)
|
|
net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1
|
|
K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O
|
|
net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll
|
|
PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0)
|
|
-8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0
|
|
net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll
|
|
BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout1_buf/O
|
|
net (fo=6484, routed) 1.935 -2.407 u_Axi_CDC/awFifo/popToPushGray_buffercc/cpu_clk
|
|
SLICE_X15Y69 FDCE r u_Axi_CDC/awFifo/popToPushGray_buffercc/buffers_0_reg[2]/C
|
|
|
|
Slack: inf
|
|
Source: u_Axi_CDC/arFifo/popCC_ptrToPush_reg[1]/C
|
|
(rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Destination: u_Axi_CDC/arFifo/popToPushGray_buffercc/buffers_0_reg[1]/D
|
|
(rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns})
|
|
Path Group: (none)
|
|
Path Type: Hold (Min at Slow Process Corner)
|
|
Data Path Delay: 0.743ns (logic 0.367ns (49.384%) route 0.376ns (50.616%))
|
|
Logic Levels: 0
|
|
Clock Path Skew: -0.387ns (DCD - SCD - CPR)
|
|
Destination Clock Delay (DCD): -2.406ns
|
|
Source Clock Delay (SCD): -2.018ns
|
|
Clock Pessimism Removal (CPR): -0.000ns
|
|
Clock Uncertainty: 0.194ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Discrete Jitter (DJ): 0.130ns
|
|
Phase Error (PE): 0.120ns
|
|
Timing Exception: Asynchronous Clock Groups
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock sys_clk rise edge) 0.000 0.000 r
|
|
K21 0.000 0.000 r clk (IN)
|
|
net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1
|
|
K21 IBUF (Prop_ibuf_I_O) 1.393 1.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O
|
|
net (fo=1, routed) 1.181 2.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll
|
|
PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1)
|
|
-8.248 -5.674 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1
|
|
net (fo=1, routed) 1.755 -3.919 pll_clk.u_clk_pll/inst/sys_clk_clk_pll
|
|
BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 -3.828 r pll_clk.u_clk_pll/inst/clkout2_buf/O
|
|
net (fo=10004, routed) 1.810 -2.018 u_Axi_CDC/arFifo/sys_clk
|
|
SLICE_X13Y69 FDCE r u_Axi_CDC/arFifo/popCC_ptrToPush_reg[1]/C
|
|
------------------------------------------------------------------- -------------------
|
|
SLICE_X13Y69 FDCE (Prop_fdce_C_Q) 0.367 -1.651 r u_Axi_CDC/arFifo/popCC_ptrToPush_reg[1]/Q
|
|
net (fo=2, routed) 0.376 -1.275 u_Axi_CDC/arFifo/popToPushGray_buffercc/D[1]
|
|
SLICE_X14Y68 FDCE r u_Axi_CDC/arFifo/popToPushGray_buffercc/buffers_0_reg[1]/D
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock cpu_clk rise edge) 0.000 0.000 r
|
|
K21 0.000 0.000 r clk (IN)
|
|
net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1
|
|
K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O
|
|
net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll
|
|
PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0)
|
|
-8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0
|
|
net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll
|
|
BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout1_buf/O
|
|
net (fo=6484, routed) 1.936 -2.406 u_Axi_CDC/arFifo/popToPushGray_buffercc/cpu_clk
|
|
SLICE_X14Y68 FDCE r u_Axi_CDC/arFifo/popToPushGray_buffercc/buffers_0_reg[1]/C
|
|
|
|
Slack: inf
|
|
Source: u_Axi_CDC/awFifo/popCC_ptrToPush_reg[1]/C
|
|
(rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Destination: u_Axi_CDC/awFifo/popToPushGray_buffercc/buffers_0_reg[1]/D
|
|
(rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns})
|
|
Path Group: (none)
|
|
Path Type: Hold (Min at Slow Process Corner)
|
|
Data Path Delay: 0.842ns (logic 0.418ns (49.650%) route 0.424ns (50.350%))
|
|
Logic Levels: 0
|
|
Clock Path Skew: -0.388ns (DCD - SCD - CPR)
|
|
Destination Clock Delay (DCD): -2.407ns
|
|
Source Clock Delay (SCD): -2.018ns
|
|
Clock Pessimism Removal (CPR): -0.000ns
|
|
Clock Uncertainty: 0.194ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Discrete Jitter (DJ): 0.130ns
|
|
Phase Error (PE): 0.120ns
|
|
Timing Exception: Asynchronous Clock Groups
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock sys_clk rise edge) 0.000 0.000 r
|
|
K21 0.000 0.000 r clk (IN)
|
|
net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1
|
|
K21 IBUF (Prop_ibuf_I_O) 1.393 1.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O
|
|
net (fo=1, routed) 1.181 2.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll
|
|
PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1)
|
|
-8.248 -5.674 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1
|
|
net (fo=1, routed) 1.755 -3.919 pll_clk.u_clk_pll/inst/sys_clk_clk_pll
|
|
BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 -3.828 r pll_clk.u_clk_pll/inst/clkout2_buf/O
|
|
net (fo=10004, routed) 1.810 -2.018 u_Axi_CDC/awFifo/sys_clk
|
|
SLICE_X16Y69 FDCE r u_Axi_CDC/awFifo/popCC_ptrToPush_reg[1]/C
|
|
------------------------------------------------------------------- -------------------
|
|
SLICE_X16Y69 FDCE (Prop_fdce_C_Q) 0.418 -1.600 r u_Axi_CDC/awFifo/popCC_ptrToPush_reg[1]/Q
|
|
net (fo=2, routed) 0.424 -1.176 u_Axi_CDC/awFifo/popToPushGray_buffercc/D[1]
|
|
SLICE_X15Y69 FDCE r u_Axi_CDC/awFifo/popToPushGray_buffercc/buffers_0_reg[1]/D
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock cpu_clk rise edge) 0.000 0.000 r
|
|
K21 0.000 0.000 r clk (IN)
|
|
net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1
|
|
K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O
|
|
net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll
|
|
PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0)
|
|
-8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0
|
|
net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll
|
|
BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout1_buf/O
|
|
net (fo=6484, routed) 1.935 -2.407 u_Axi_CDC/awFifo/popToPushGray_buffercc/cpu_clk
|
|
SLICE_X15Y69 FDCE r u_Axi_CDC/awFifo/popToPushGray_buffercc/buffers_0_reg[1]/C
|
|
|
|
Slack: inf
|
|
Source: u_Axi_CDC/arFifo/popCC_ptrToPush_reg[2]/C
|
|
(rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Destination: u_Axi_CDC/arFifo/popToPushGray_buffercc/buffers_0_reg[2]/D
|
|
(rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns})
|
|
Path Group: (none)
|
|
Path Type: Hold (Min at Slow Process Corner)
|
|
Data Path Delay: 0.843ns (logic 0.337ns (39.996%) route 0.506ns (60.004%))
|
|
Logic Levels: 0
|
|
Clock Path Skew: -0.387ns (DCD - SCD - CPR)
|
|
Destination Clock Delay (DCD): -2.406ns
|
|
Source Clock Delay (SCD): -2.018ns
|
|
Clock Pessimism Removal (CPR): -0.000ns
|
|
Clock Uncertainty: 0.194ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Discrete Jitter (DJ): 0.130ns
|
|
Phase Error (PE): 0.120ns
|
|
Timing Exception: Asynchronous Clock Groups
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock sys_clk rise edge) 0.000 0.000 r
|
|
K21 0.000 0.000 r clk (IN)
|
|
net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1
|
|
K21 IBUF (Prop_ibuf_I_O) 1.393 1.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O
|
|
net (fo=1, routed) 1.181 2.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll
|
|
PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1)
|
|
-8.248 -5.674 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1
|
|
net (fo=1, routed) 1.755 -3.919 pll_clk.u_clk_pll/inst/sys_clk_clk_pll
|
|
BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 -3.828 r pll_clk.u_clk_pll/inst/clkout2_buf/O
|
|
net (fo=10004, routed) 1.810 -2.018 u_Axi_CDC/arFifo/sys_clk
|
|
SLICE_X13Y69 FDCE r u_Axi_CDC/arFifo/popCC_ptrToPush_reg[2]/C
|
|
------------------------------------------------------------------- -------------------
|
|
SLICE_X13Y69 FDCE (Prop_fdce_C_Q) 0.337 -1.681 r u_Axi_CDC/arFifo/popCC_ptrToPush_reg[2]/Q
|
|
net (fo=2, routed) 0.506 -1.176 u_Axi_CDC/arFifo/popToPushGray_buffercc/D[2]
|
|
SLICE_X14Y68 FDCE r u_Axi_CDC/arFifo/popToPushGray_buffercc/buffers_0_reg[2]/D
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock cpu_clk rise edge) 0.000 0.000 r
|
|
K21 0.000 0.000 r clk (IN)
|
|
net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1
|
|
K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O
|
|
net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll
|
|
PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0)
|
|
-8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0
|
|
net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll
|
|
BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout1_buf/O
|
|
net (fo=6484, routed) 1.936 -2.406 u_Axi_CDC/arFifo/popToPushGray_buffercc/cpu_clk
|
|
SLICE_X14Y68 FDCE r u_Axi_CDC/arFifo/popToPushGray_buffercc/buffers_0_reg[2]/C
|
|
|
|
Slack: inf
|
|
Source: u_Axi_CDC/rFifo/pushCC_pushPtrGray_reg[1]/C
|
|
(rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Destination: u_Axi_CDC/rFifo/pushToPopGray_buffercc/buffers_0_reg[1]/D
|
|
(rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns})
|
|
Path Group: (none)
|
|
Path Type: Hold (Min at Slow Process Corner)
|
|
Data Path Delay: 0.782ns (logic 0.367ns (46.956%) route 0.415ns (53.044%))
|
|
Logic Levels: 0
|
|
Clock Path Skew: -0.391ns (DCD - SCD - CPR)
|
|
Destination Clock Delay (DCD): -2.335ns
|
|
Source Clock Delay (SCD): -1.943ns
|
|
Clock Pessimism Removal (CPR): -0.000ns
|
|
Clock Uncertainty: 0.194ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Discrete Jitter (DJ): 0.130ns
|
|
Phase Error (PE): 0.120ns
|
|
Timing Exception: Asynchronous Clock Groups
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock sys_clk rise edge) 0.000 0.000 r
|
|
K21 0.000 0.000 r clk (IN)
|
|
net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1
|
|
K21 IBUF (Prop_ibuf_I_O) 1.393 1.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O
|
|
net (fo=1, routed) 1.181 2.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll
|
|
PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1)
|
|
-8.248 -5.674 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1
|
|
net (fo=1, routed) 1.755 -3.919 pll_clk.u_clk_pll/inst/sys_clk_clk_pll
|
|
BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 -3.828 r pll_clk.u_clk_pll/inst/clkout2_buf/O
|
|
net (fo=10004, routed) 1.885 -1.943 u_Axi_CDC/rFifo/sys_clk
|
|
SLICE_X5Y77 FDCE r u_Axi_CDC/rFifo/pushCC_pushPtrGray_reg[1]/C
|
|
------------------------------------------------------------------- -------------------
|
|
SLICE_X5Y77 FDCE (Prop_fdce_C_Q) 0.367 -1.576 r u_Axi_CDC/rFifo/pushCC_pushPtrGray_reg[1]/Q
|
|
net (fo=2, routed) 0.415 -1.162 u_Axi_CDC/rFifo/pushToPopGray_buffercc/buffers_0_reg[2]_0[1]
|
|
SLICE_X5Y76 FDCE r u_Axi_CDC/rFifo/pushToPopGray_buffercc/buffers_0_reg[1]/D
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock cpu_clk rise edge) 0.000 0.000 r
|
|
K21 0.000 0.000 r clk (IN)
|
|
net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1
|
|
K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O
|
|
net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll
|
|
PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0)
|
|
-8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0
|
|
net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll
|
|
BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout1_buf/O
|
|
net (fo=6484, routed) 2.007 -2.335 u_Axi_CDC/rFifo/pushToPopGray_buffercc/cpu_clk
|
|
SLICE_X5Y76 FDCE r u_Axi_CDC/rFifo/pushToPopGray_buffercc/buffers_0_reg[1]/C
|
|
|
|
Slack: inf
|
|
Source: u_Axi_CDC/wFifo/popCC_ptrToPush_reg[3]/C
|
|
(rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Destination: u_Axi_CDC/wFifo/popToPushGray_buffercc/buffers_0_reg[3]/D
|
|
(rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns})
|
|
Path Group: (none)
|
|
Path Type: Hold (Min at Slow Process Corner)
|
|
Data Path Delay: 0.630ns (logic 0.367ns (58.287%) route 0.263ns (41.713%))
|
|
Logic Levels: 0
|
|
Clock Path Skew: -0.564ns (DCD - SCD - CPR)
|
|
Destination Clock Delay (DCD): -2.316ns
|
|
Source Clock Delay (SCD): -1.752ns
|
|
Clock Pessimism Removal (CPR): -0.000ns
|
|
Clock Uncertainty: 0.194ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Discrete Jitter (DJ): 0.130ns
|
|
Phase Error (PE): 0.120ns
|
|
Timing Exception: Asynchronous Clock Groups
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock sys_clk rise edge) 0.000 0.000 r
|
|
K21 0.000 0.000 r clk (IN)
|
|
net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1
|
|
K21 IBUF (Prop_ibuf_I_O) 1.393 1.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O
|
|
net (fo=1, routed) 1.181 2.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll
|
|
PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1)
|
|
-8.248 -5.674 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1
|
|
net (fo=1, routed) 1.755 -3.919 pll_clk.u_clk_pll/inst/sys_clk_clk_pll
|
|
BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 -3.828 r pll_clk.u_clk_pll/inst/clkout2_buf/O
|
|
net (fo=10004, routed) 2.077 -1.752 u_Axi_CDC/wFifo/sys_clk
|
|
SLICE_X5Y49 FDCE r u_Axi_CDC/wFifo/popCC_ptrToPush_reg[3]/C
|
|
------------------------------------------------------------------- -------------------
|
|
SLICE_X5Y49 FDCE (Prop_fdce_C_Q) 0.367 -1.385 r u_Axi_CDC/wFifo/popCC_ptrToPush_reg[3]/Q
|
|
net (fo=1, routed) 0.263 -1.122 u_Axi_CDC/wFifo/popToPushGray_buffercc/Q[3]
|
|
SLICE_X6Y50 FDCE r u_Axi_CDC/wFifo/popToPushGray_buffercc/buffers_0_reg[3]/D
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock cpu_clk rise edge) 0.000 0.000 r
|
|
K21 0.000 0.000 r clk (IN)
|
|
net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1
|
|
K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O
|
|
net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll
|
|
PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0)
|
|
-8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0
|
|
net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll
|
|
BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout1_buf/O
|
|
net (fo=6484, routed) 2.026 -2.316 u_Axi_CDC/wFifo/popToPushGray_buffercc/cpu_clk
|
|
SLICE_X6Y50 FDCE r u_Axi_CDC/wFifo/popToPushGray_buffercc/buffers_0_reg[3]/C
|
|
|
|
Slack: inf
|
|
Source: u_Axi_CDC/wFifo/popCC_ptrToPush_reg[0]/C
|
|
(rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Destination: u_Axi_CDC/wFifo/popToPushGray_buffercc/buffers_0_reg[0]/D
|
|
(rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns})
|
|
Path Group: (none)
|
|
Path Type: Hold (Min at Slow Process Corner)
|
|
Data Path Delay: 0.632ns (logic 0.367ns (58.089%) route 0.265ns (41.911%))
|
|
Logic Levels: 0
|
|
Clock Path Skew: -0.377ns (DCD - SCD - CPR)
|
|
Destination Clock Delay (DCD): -2.129ns
|
|
Source Clock Delay (SCD): -1.752ns
|
|
Clock Pessimism Removal (CPR): -0.000ns
|
|
Clock Uncertainty: 0.194ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Discrete Jitter (DJ): 0.130ns
|
|
Phase Error (PE): 0.120ns
|
|
Timing Exception: Asynchronous Clock Groups
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock sys_clk rise edge) 0.000 0.000 r
|
|
K21 0.000 0.000 r clk (IN)
|
|
net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1
|
|
K21 IBUF (Prop_ibuf_I_O) 1.393 1.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O
|
|
net (fo=1, routed) 1.181 2.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll
|
|
PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1)
|
|
-8.248 -5.674 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1
|
|
net (fo=1, routed) 1.755 -3.919 pll_clk.u_clk_pll/inst/sys_clk_clk_pll
|
|
BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 -3.828 r pll_clk.u_clk_pll/inst/clkout2_buf/O
|
|
net (fo=10004, routed) 2.077 -1.752 u_Axi_CDC/wFifo/sys_clk
|
|
SLICE_X5Y49 FDCE r u_Axi_CDC/wFifo/popCC_ptrToPush_reg[0]/C
|
|
------------------------------------------------------------------- -------------------
|
|
SLICE_X5Y49 FDCE (Prop_fdce_C_Q) 0.367 -1.385 r u_Axi_CDC/wFifo/popCC_ptrToPush_reg[0]/Q
|
|
net (fo=1, routed) 0.265 -1.120 u_Axi_CDC/wFifo/popToPushGray_buffercc/Q[0]
|
|
SLICE_X0Y49 FDCE r u_Axi_CDC/wFifo/popToPushGray_buffercc/buffers_0_reg[0]/D
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock cpu_clk rise edge) 0.000 0.000 r
|
|
K21 0.000 0.000 r clk (IN)
|
|
net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1
|
|
K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O
|
|
net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll
|
|
PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0)
|
|
-8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0
|
|
net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll
|
|
BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout1_buf/O
|
|
net (fo=6484, routed) 2.213 -2.129 u_Axi_CDC/wFifo/popToPushGray_buffercc/cpu_clk
|
|
SLICE_X0Y49 FDCE r u_Axi_CDC/wFifo/popToPushGray_buffercc/buffers_0_reg[0]/C
|
|
|
|
Slack: inf
|
|
Source: u_Axi_CDC/bFifo/pushCC_pushPtrGray_reg[0]/C
|
|
(rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Destination: u_Axi_CDC/bFifo/pushToPopGray_buffercc/buffers_0_reg[0]/D
|
|
(rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns})
|
|
Path Group: (none)
|
|
Path Type: Hold (Min at Slow Process Corner)
|
|
Data Path Delay: 0.922ns (logic 0.367ns (39.803%) route 0.555ns (60.197%))
|
|
Logic Levels: 0
|
|
Clock Path Skew: -0.379ns (DCD - SCD - CPR)
|
|
Destination Clock Delay (DCD): -2.397ns
|
|
Source Clock Delay (SCD): -2.017ns
|
|
Clock Pessimism Removal (CPR): -0.000ns
|
|
Clock Uncertainty: 0.194ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Discrete Jitter (DJ): 0.130ns
|
|
Phase Error (PE): 0.120ns
|
|
Timing Exception: Asynchronous Clock Groups
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock sys_clk rise edge) 0.000 0.000 r
|
|
K21 0.000 0.000 r clk (IN)
|
|
net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1
|
|
K21 IBUF (Prop_ibuf_I_O) 1.393 1.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O
|
|
net (fo=1, routed) 1.181 2.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll
|
|
PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1)
|
|
-8.248 -5.674 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1
|
|
net (fo=1, routed) 1.755 -3.919 pll_clk.u_clk_pll/inst/sys_clk_clk_pll
|
|
BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 -3.828 r pll_clk.u_clk_pll/inst/clkout2_buf/O
|
|
net (fo=10004, routed) 1.811 -2.017 u_Axi_CDC/bFifo/sys_clk
|
|
SLICE_X19Y68 FDCE r u_Axi_CDC/bFifo/pushCC_pushPtrGray_reg[0]/C
|
|
------------------------------------------------------------------- -------------------
|
|
SLICE_X19Y68 FDCE (Prop_fdce_C_Q) 0.367 -1.650 r u_Axi_CDC/bFifo/pushCC_pushPtrGray_reg[0]/Q
|
|
net (fo=2, routed) 0.555 -1.095 u_Axi_CDC/bFifo/pushToPopGray_buffercc/Q[0]
|
|
SLICE_X19Y59 FDCE r u_Axi_CDC/bFifo/pushToPopGray_buffercc/buffers_0_reg[0]/D
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock cpu_clk rise edge) 0.000 0.000 r
|
|
K21 0.000 0.000 r clk (IN)
|
|
net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1
|
|
K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O
|
|
net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll
|
|
PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0)
|
|
-8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0
|
|
net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll
|
|
BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout1_buf/O
|
|
net (fo=6484, routed) 1.945 -2.397 u_Axi_CDC/bFifo/pushToPopGray_buffercc/cpu_clk
|
|
SLICE_X19Y59 FDCE r u_Axi_CDC/bFifo/pushToPopGray_buffercc/buffers_0_reg[0]/C
|
|
|
|
Slack: inf
|
|
Source: u_Axi_CDC/rFifo/pushCC_pushPtrGray_reg[3]/C
|
|
(rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Destination: u_Axi_CDC/rFifo/pushToPopGray_buffercc/buffers_0_reg[3]/D
|
|
(rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns})
|
|
Path Group: (none)
|
|
Path Type: Hold (Min at Slow Process Corner)
|
|
Data Path Delay: 0.888ns (logic 0.337ns (37.964%) route 0.551ns (62.036%))
|
|
Logic Levels: 0
|
|
Clock Path Skew: -0.393ns (DCD - SCD - CPR)
|
|
Destination Clock Delay (DCD): -2.337ns
|
|
Source Clock Delay (SCD): -1.943ns
|
|
Clock Pessimism Removal (CPR): -0.000ns
|
|
Clock Uncertainty: 0.194ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Discrete Jitter (DJ): 0.130ns
|
|
Phase Error (PE): 0.120ns
|
|
Timing Exception: Asynchronous Clock Groups
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock sys_clk rise edge) 0.000 0.000 r
|
|
K21 0.000 0.000 r clk (IN)
|
|
net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1
|
|
K21 IBUF (Prop_ibuf_I_O) 1.393 1.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O
|
|
net (fo=1, routed) 1.181 2.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll
|
|
PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1)
|
|
-8.248 -5.674 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1
|
|
net (fo=1, routed) 1.755 -3.919 pll_clk.u_clk_pll/inst/sys_clk_clk_pll
|
|
BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 -3.828 r pll_clk.u_clk_pll/inst/clkout2_buf/O
|
|
net (fo=10004, routed) 1.885 -1.943 u_Axi_CDC/rFifo/sys_clk
|
|
SLICE_X5Y77 FDCE r u_Axi_CDC/rFifo/pushCC_pushPtrGray_reg[3]/C
|
|
------------------------------------------------------------------- -------------------
|
|
SLICE_X5Y77 FDCE (Prop_fdce_C_Q) 0.337 -1.606 r u_Axi_CDC/rFifo/pushCC_pushPtrGray_reg[3]/Q
|
|
net (fo=4, routed) 0.551 -1.056 u_Axi_CDC/rFifo/pushToPopGray_buffercc/buffers_0_reg[3]_0
|
|
SLICE_X5Y75 FDCE r u_Axi_CDC/rFifo/pushToPopGray_buffercc/buffers_0_reg[3]/D
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock cpu_clk rise edge) 0.000 0.000 r
|
|
K21 0.000 0.000 r clk (IN)
|
|
net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1
|
|
K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O
|
|
net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll
|
|
PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0)
|
|
-8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0
|
|
net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll
|
|
BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout1_buf/O
|
|
net (fo=6484, routed) 2.005 -2.337 u_Axi_CDC/rFifo/pushToPopGray_buffercc/cpu_clk
|
|
SLICE_X5Y75 FDCE r u_Axi_CDC/rFifo/pushToPopGray_buffercc/buffers_0_reg[3]/C
|
|
|
|
Slack: inf
|
|
Source: u_snix_axil_cdma_mux_8ch/ch_done_reg[2]/C
|
|
(rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Destination: u_cpu/u_csr/csr_estat_reg[3]/D
|
|
(rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns})
|
|
Path Group: (none)
|
|
Path Type: Hold (Min at Slow Process Corner)
|
|
Data Path Delay: 1.075ns (logic 0.518ns (48.184%) route 0.557ns (51.816%))
|
|
Logic Levels: 1 (LUT5=1)
|
|
Clock Path Skew: -0.382ns (DCD - SCD - CPR)
|
|
Destination Clock Delay (DCD): -2.498ns
|
|
Source Clock Delay (SCD): -2.115ns
|
|
Clock Pessimism Removal (CPR): -0.000ns
|
|
Clock Uncertainty: 0.194ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Discrete Jitter (DJ): 0.130ns
|
|
Phase Error (PE): 0.120ns
|
|
Timing Exception: Asynchronous Clock Groups
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock sys_clk rise edge) 0.000 0.000 r
|
|
K21 0.000 0.000 r clk (IN)
|
|
net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1
|
|
K21 IBUF (Prop_ibuf_I_O) 1.393 1.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O
|
|
net (fo=1, routed) 1.181 2.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll
|
|
PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1)
|
|
-8.248 -5.674 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1
|
|
net (fo=1, routed) 1.755 -3.919 pll_clk.u_clk_pll/inst/sys_clk_clk_pll
|
|
BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 -3.828 r pll_clk.u_clk_pll/inst/clkout2_buf/O
|
|
net (fo=10004, routed) 1.713 -2.115 u_snix_axil_cdma_mux_8ch/sys_clk
|
|
SLICE_X56Y62 FDRE r u_snix_axil_cdma_mux_8ch/ch_done_reg[2]/C
|
|
------------------------------------------------------------------- -------------------
|
|
SLICE_X56Y62 FDRE (Prop_fdre_C_Q) 0.418 -1.697 r u_snix_axil_cdma_mux_8ch/ch_done_reg[2]/Q
|
|
net (fo=3, routed) 0.557 -1.140 u_snix_axil_cdma_mux_8ch/ch_done_reg[2]_0
|
|
SLICE_X57Y58 LUT5 (Prop_lut5_I3_O) 0.100 -1.040 r u_snix_axil_cdma_mux_8ch/csr_estat[3]_i_1/O
|
|
net (fo=1, routed) 0.000 -1.040 u_cpu/u_csr/interrupt[1]
|
|
SLICE_X57Y58 FDRE r u_cpu/u_csr/csr_estat_reg[3]/D
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock cpu_clk rise edge) 0.000 0.000 r
|
|
K21 0.000 0.000 r clk (IN)
|
|
net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1
|
|
K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O
|
|
net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll
|
|
PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0)
|
|
-8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0
|
|
net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll
|
|
BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout1_buf/O
|
|
net (fo=6484, routed) 1.844 -2.498 u_cpu/u_csr/cpu_clk
|
|
SLICE_X57Y58 FDRE r u_cpu/u_csr/csr_estat_reg[3]/C
|
|
|
|
Slack: inf
|
|
Source: u_Axi_CDC/wFifo/popCC_ptrToPush_reg[1]/C
|
|
(rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Destination: u_Axi_CDC/wFifo/popToPushGray_buffercc/buffers_0_reg[1]/D
|
|
(rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns})
|
|
Path Group: (none)
|
|
Path Type: Hold (Min at Slow Process Corner)
|
|
Data Path Delay: 0.742ns (logic 0.367ns (49.468%) route 0.375ns (50.532%))
|
|
Logic Levels: 0
|
|
Clock Path Skew: -0.377ns (DCD - SCD - CPR)
|
|
Destination Clock Delay (DCD): -2.129ns
|
|
Source Clock Delay (SCD): -1.752ns
|
|
Clock Pessimism Removal (CPR): -0.000ns
|
|
Clock Uncertainty: 0.194ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Discrete Jitter (DJ): 0.130ns
|
|
Phase Error (PE): 0.120ns
|
|
Timing Exception: Asynchronous Clock Groups
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock sys_clk rise edge) 0.000 0.000 r
|
|
K21 0.000 0.000 r clk (IN)
|
|
net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1
|
|
K21 IBUF (Prop_ibuf_I_O) 1.393 1.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O
|
|
net (fo=1, routed) 1.181 2.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll
|
|
PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1)
|
|
-8.248 -5.674 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1
|
|
net (fo=1, routed) 1.755 -3.919 pll_clk.u_clk_pll/inst/sys_clk_clk_pll
|
|
BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 -3.828 r pll_clk.u_clk_pll/inst/clkout2_buf/O
|
|
net (fo=10004, routed) 2.077 -1.752 u_Axi_CDC/wFifo/sys_clk
|
|
SLICE_X5Y49 FDCE r u_Axi_CDC/wFifo/popCC_ptrToPush_reg[1]/C
|
|
------------------------------------------------------------------- -------------------
|
|
SLICE_X5Y49 FDCE (Prop_fdce_C_Q) 0.367 -1.385 r u_Axi_CDC/wFifo/popCC_ptrToPush_reg[1]/Q
|
|
net (fo=1, routed) 0.375 -1.010 u_Axi_CDC/wFifo/popToPushGray_buffercc/Q[1]
|
|
SLICE_X0Y49 FDCE r u_Axi_CDC/wFifo/popToPushGray_buffercc/buffers_0_reg[1]/D
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock cpu_clk rise edge) 0.000 0.000 r
|
|
K21 0.000 0.000 r clk (IN)
|
|
net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1
|
|
K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O
|
|
net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll
|
|
PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0)
|
|
-8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0
|
|
net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll
|
|
BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout1_buf/O
|
|
net (fo=6484, routed) 2.213 -2.129 u_Axi_CDC/wFifo/popToPushGray_buffercc/cpu_clk
|
|
SLICE_X0Y49 FDCE r u_Axi_CDC/wFifo/popToPushGray_buffercc/buffers_0_reg[1]/C
|
|
|
|
Slack: inf
|
|
Source: u_Axi_CDC/bFifo/pushCC_pushPtrGray_reg[2]/C
|
|
(rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Destination: u_Axi_CDC/bFifo/pushToPopGray_buffercc/buffers_0_reg[2]/D
|
|
(rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns})
|
|
Path Group: (none)
|
|
Path Type: Hold (Min at Slow Process Corner)
|
|
Data Path Delay: 1.025ns (logic 0.337ns (32.867%) route 0.688ns (67.133%))
|
|
Logic Levels: 0
|
|
Clock Path Skew: -0.379ns (DCD - SCD - CPR)
|
|
Destination Clock Delay (DCD): -2.397ns
|
|
Source Clock Delay (SCD): -2.017ns
|
|
Clock Pessimism Removal (CPR): -0.000ns
|
|
Clock Uncertainty: 0.194ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Discrete Jitter (DJ): 0.130ns
|
|
Phase Error (PE): 0.120ns
|
|
Timing Exception: Asynchronous Clock Groups
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock sys_clk rise edge) 0.000 0.000 r
|
|
K21 0.000 0.000 r clk (IN)
|
|
net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1
|
|
K21 IBUF (Prop_ibuf_I_O) 1.393 1.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O
|
|
net (fo=1, routed) 1.181 2.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll
|
|
PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1)
|
|
-8.248 -5.674 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1
|
|
net (fo=1, routed) 1.755 -3.919 pll_clk.u_clk_pll/inst/sys_clk_clk_pll
|
|
BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 -3.828 r pll_clk.u_clk_pll/inst/clkout2_buf/O
|
|
net (fo=10004, routed) 1.811 -2.017 u_Axi_CDC/bFifo/sys_clk
|
|
SLICE_X19Y68 FDCE r u_Axi_CDC/bFifo/pushCC_pushPtrGray_reg[2]/C
|
|
------------------------------------------------------------------- -------------------
|
|
SLICE_X19Y68 FDCE (Prop_fdce_C_Q) 0.337 -1.680 r u_Axi_CDC/bFifo/pushCC_pushPtrGray_reg[2]/Q
|
|
net (fo=4, routed) 0.688 -0.992 u_Axi_CDC/bFifo/pushToPopGray_buffercc/buffers_0_reg[2]_0
|
|
SLICE_X19Y59 FDCE r u_Axi_CDC/bFifo/pushToPopGray_buffercc/buffers_0_reg[2]/D
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock cpu_clk rise edge) 0.000 0.000 r
|
|
K21 0.000 0.000 r clk (IN)
|
|
net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1
|
|
K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O
|
|
net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll
|
|
PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0)
|
|
-8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0
|
|
net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll
|
|
BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout1_buf/O
|
|
net (fo=6484, routed) 1.945 -2.397 u_Axi_CDC/bFifo/pushToPopGray_buffercc/cpu_clk
|
|
SLICE_X19Y59 FDCE r u_Axi_CDC/bFifo/pushToPopGray_buffercc/buffers_0_reg[2]/C
|
|
|
|
Slack: inf
|
|
Source: u_Axi_CDC/bFifo/pushCC_pushPtrGray_reg[1]/C
|
|
(rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Destination: u_Axi_CDC/bFifo/pushToPopGray_buffercc/buffers_0_reg[1]/D
|
|
(rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns})
|
|
Path Group: (none)
|
|
Path Type: Hold (Min at Slow Process Corner)
|
|
Data Path Delay: 1.073ns (logic 0.367ns (34.191%) route 0.706ns (65.809%))
|
|
Logic Levels: 0
|
|
Clock Path Skew: -0.379ns (DCD - SCD - CPR)
|
|
Destination Clock Delay (DCD): -2.397ns
|
|
Source Clock Delay (SCD): -2.017ns
|
|
Clock Pessimism Removal (CPR): -0.000ns
|
|
Clock Uncertainty: 0.194ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Discrete Jitter (DJ): 0.130ns
|
|
Phase Error (PE): 0.120ns
|
|
Timing Exception: Asynchronous Clock Groups
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock sys_clk rise edge) 0.000 0.000 r
|
|
K21 0.000 0.000 r clk (IN)
|
|
net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1
|
|
K21 IBUF (Prop_ibuf_I_O) 1.393 1.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O
|
|
net (fo=1, routed) 1.181 2.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll
|
|
PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1)
|
|
-8.248 -5.674 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1
|
|
net (fo=1, routed) 1.755 -3.919 pll_clk.u_clk_pll/inst/sys_clk_clk_pll
|
|
BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 -3.828 r pll_clk.u_clk_pll/inst/clkout2_buf/O
|
|
net (fo=10004, routed) 1.811 -2.017 u_Axi_CDC/bFifo/sys_clk
|
|
SLICE_X19Y68 FDCE r u_Axi_CDC/bFifo/pushCC_pushPtrGray_reg[1]/C
|
|
------------------------------------------------------------------- -------------------
|
|
SLICE_X19Y68 FDCE (Prop_fdce_C_Q) 0.367 -1.650 r u_Axi_CDC/bFifo/pushCC_pushPtrGray_reg[1]/Q
|
|
net (fo=2, routed) 0.706 -0.944 u_Axi_CDC/bFifo/pushToPopGray_buffercc/Q[1]
|
|
SLICE_X19Y59 FDCE r u_Axi_CDC/bFifo/pushToPopGray_buffercc/buffers_0_reg[1]/D
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock cpu_clk rise edge) 0.000 0.000 r
|
|
K21 0.000 0.000 r clk (IN)
|
|
net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1
|
|
K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O
|
|
net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll
|
|
PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0)
|
|
-8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0
|
|
net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll
|
|
BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout1_buf/O
|
|
net (fo=6484, routed) 1.945 -2.397 u_Axi_CDC/bFifo/pushToPopGray_buffercc/cpu_clk
|
|
SLICE_X19Y59 FDCE r u_Axi_CDC/bFifo/pushToPopGray_buffercc/buffers_0_reg[1]/C
|
|
|
|
Slack: inf
|
|
Source: u_Axi_CDC/arFifo/popCC_ptrToPush_reg[0]/C
|
|
(rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Destination: u_Axi_CDC/arFifo/popToPushGray_buffercc/buffers_0_reg[0]/D
|
|
(rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns})
|
|
Path Group: (none)
|
|
Path Type: Hold (Min at Slow Process Corner)
|
|
Data Path Delay: 1.147ns (logic 0.367ns (31.992%) route 0.780ns (68.008%))
|
|
Logic Levels: 0
|
|
Clock Path Skew: -0.387ns (DCD - SCD - CPR)
|
|
Destination Clock Delay (DCD): -2.406ns
|
|
Source Clock Delay (SCD): -2.018ns
|
|
Clock Pessimism Removal (CPR): -0.000ns
|
|
Clock Uncertainty: 0.194ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Discrete Jitter (DJ): 0.130ns
|
|
Phase Error (PE): 0.120ns
|
|
Timing Exception: Asynchronous Clock Groups
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock sys_clk rise edge) 0.000 0.000 r
|
|
K21 0.000 0.000 r clk (IN)
|
|
net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1
|
|
K21 IBUF (Prop_ibuf_I_O) 1.393 1.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O
|
|
net (fo=1, routed) 1.181 2.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll
|
|
PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1)
|
|
-8.248 -5.674 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1
|
|
net (fo=1, routed) 1.755 -3.919 pll_clk.u_clk_pll/inst/sys_clk_clk_pll
|
|
BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 -3.828 r pll_clk.u_clk_pll/inst/clkout2_buf/O
|
|
net (fo=10004, routed) 1.810 -2.018 u_Axi_CDC/arFifo/sys_clk
|
|
SLICE_X13Y69 FDCE r u_Axi_CDC/arFifo/popCC_ptrToPush_reg[0]/C
|
|
------------------------------------------------------------------- -------------------
|
|
SLICE_X13Y69 FDCE (Prop_fdce_C_Q) 0.367 -1.651 r u_Axi_CDC/arFifo/popCC_ptrToPush_reg[0]/Q
|
|
net (fo=2, routed) 0.780 -0.871 u_Axi_CDC/arFifo/popToPushGray_buffercc/D[0]
|
|
SLICE_X14Y68 FDCE r u_Axi_CDC/arFifo/popToPushGray_buffercc/buffers_0_reg[0]/D
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock cpu_clk rise edge) 0.000 0.000 r
|
|
K21 0.000 0.000 r clk (IN)
|
|
net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1
|
|
K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O
|
|
net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll
|
|
PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0)
|
|
-8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0
|
|
net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll
|
|
BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout1_buf/O
|
|
net (fo=6484, routed) 1.936 -2.406 u_Axi_CDC/arFifo/popToPushGray_buffercc/cpu_clk
|
|
SLICE_X14Y68 FDCE r u_Axi_CDC/arFifo/popToPushGray_buffercc/buffers_0_reg[0]/C
|
|
|
|
Slack: inf
|
|
Source: u_Axi_CDC/wFifo/popCC_ptrToPush_reg[2]/C
|
|
(rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Destination: u_Axi_CDC/wFifo/popToPushGray_buffercc/buffers_0_reg[2]/D
|
|
(rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns})
|
|
Path Group: (none)
|
|
Path Type: Hold (Min at Slow Process Corner)
|
|
Data Path Delay: 1.043ns (logic 0.337ns (32.302%) route 0.706ns (67.698%))
|
|
Logic Levels: 0
|
|
Clock Path Skew: -0.564ns (DCD - SCD - CPR)
|
|
Destination Clock Delay (DCD): -2.316ns
|
|
Source Clock Delay (SCD): -1.752ns
|
|
Clock Pessimism Removal (CPR): -0.000ns
|
|
Clock Uncertainty: 0.194ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Discrete Jitter (DJ): 0.130ns
|
|
Phase Error (PE): 0.120ns
|
|
Timing Exception: Asynchronous Clock Groups
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock sys_clk rise edge) 0.000 0.000 r
|
|
K21 0.000 0.000 r clk (IN)
|
|
net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1
|
|
K21 IBUF (Prop_ibuf_I_O) 1.393 1.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O
|
|
net (fo=1, routed) 1.181 2.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll
|
|
PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1)
|
|
-8.248 -5.674 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1
|
|
net (fo=1, routed) 1.755 -3.919 pll_clk.u_clk_pll/inst/sys_clk_clk_pll
|
|
BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 -3.828 r pll_clk.u_clk_pll/inst/clkout2_buf/O
|
|
net (fo=10004, routed) 2.077 -1.752 u_Axi_CDC/wFifo/sys_clk
|
|
SLICE_X5Y49 FDCE r u_Axi_CDC/wFifo/popCC_ptrToPush_reg[2]/C
|
|
------------------------------------------------------------------- -------------------
|
|
SLICE_X5Y49 FDCE (Prop_fdce_C_Q) 0.337 -1.415 r u_Axi_CDC/wFifo/popCC_ptrToPush_reg[2]/Q
|
|
net (fo=1, routed) 0.706 -0.708 u_Axi_CDC/wFifo/popToPushGray_buffercc/Q[2]
|
|
SLICE_X6Y50 FDCE r u_Axi_CDC/wFifo/popToPushGray_buffercc/buffers_0_reg[2]/D
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock cpu_clk rise edge) 0.000 0.000 r
|
|
K21 0.000 0.000 r clk (IN)
|
|
net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1
|
|
K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O
|
|
net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll
|
|
PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0)
|
|
-8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0
|
|
net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll
|
|
BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout1_buf/O
|
|
net (fo=6484, routed) 2.026 -2.316 u_Axi_CDC/wFifo/popToPushGray_buffercc/cpu_clk
|
|
SLICE_X6Y50 FDCE r u_Axi_CDC/wFifo/popToPushGray_buffercc/buffers_0_reg[2]/C
|
|
|
|
Slack: inf
|
|
Source: u_matmul_axi_slave/done_reg/C
|
|
(rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Destination: u_cpu/u_csr/csr_estat_reg[4]/D
|
|
(rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns})
|
|
Path Group: (none)
|
|
Path Type: Hold (Min at Slow Process Corner)
|
|
Data Path Delay: 1.754ns (logic 0.418ns (23.829%) route 1.336ns (76.171%))
|
|
Logic Levels: 0
|
|
Clock Path Skew: -0.104ns (DCD - SCD - CPR)
|
|
Destination Clock Delay (DCD): -2.228ns
|
|
Source Clock Delay (SCD): -2.123ns
|
|
Clock Pessimism Removal (CPR): -0.000ns
|
|
Clock Uncertainty: 0.194ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Discrete Jitter (DJ): 0.130ns
|
|
Phase Error (PE): 0.120ns
|
|
Timing Exception: Asynchronous Clock Groups
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock sys_clk rise edge) 0.000 0.000 r
|
|
K21 0.000 0.000 r clk (IN)
|
|
net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1
|
|
K21 IBUF (Prop_ibuf_I_O) 1.393 1.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O
|
|
net (fo=1, routed) 1.181 2.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll
|
|
PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1)
|
|
-8.248 -5.674 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1
|
|
net (fo=1, routed) 1.755 -3.919 pll_clk.u_clk_pll/inst/sys_clk_clk_pll
|
|
BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 -3.828 r pll_clk.u_clk_pll/inst/clkout2_buf/O
|
|
net (fo=10004, routed) 1.705 -2.123 u_matmul_axi_slave/sys_clk
|
|
SLICE_X46Y72 FDRE r u_matmul_axi_slave/done_reg/C
|
|
------------------------------------------------------------------- -------------------
|
|
SLICE_X46Y72 FDRE (Prop_fdre_C_Q) 0.418 -1.705 r u_matmul_axi_slave/done_reg/Q
|
|
net (fo=12, routed) 1.336 -0.369 u_cpu/u_csr/interrupt[2]
|
|
SLICE_X41Y40 FDRE r u_cpu/u_csr/csr_estat_reg[4]/D
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock cpu_clk rise edge) 0.000 0.000 r
|
|
K21 0.000 0.000 r clk (IN)
|
|
net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1
|
|
K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O
|
|
net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll
|
|
PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0)
|
|
-8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0
|
|
net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll
|
|
BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout1_buf/O
|
|
net (fo=6484, routed) 2.114 -2.228 u_cpu/u_csr/cpu_clk
|
|
SLICE_X41Y40 FDRE r u_cpu/u_csr/csr_estat_reg[4]/C
|
|
|
|
Slack: inf
|
|
Source: u_confreg/int_out_or_q2_reg/C
|
|
(rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Destination: u_cpu/u_csr/csr_estat_reg[2]/D
|
|
(rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns})
|
|
Path Group: (none)
|
|
Path Type: Hold (Min at Slow Process Corner)
|
|
Data Path Delay: 2.063ns (logic 0.367ns (17.786%) route 1.696ns (82.214%))
|
|
Logic Levels: 0
|
|
Clock Path Skew: -0.223ns (DCD - SCD - CPR)
|
|
Destination Clock Delay (DCD): -2.231ns
|
|
Source Clock Delay (SCD): -2.007ns
|
|
Clock Pessimism Removal (CPR): -0.000ns
|
|
Clock Uncertainty: 0.194ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Discrete Jitter (DJ): 0.130ns
|
|
Phase Error (PE): 0.120ns
|
|
Timing Exception: Asynchronous Clock Groups
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock sys_clk rise edge) 0.000 0.000 r
|
|
K21 0.000 0.000 r clk (IN)
|
|
net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1
|
|
K21 IBUF (Prop_ibuf_I_O) 1.393 1.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O
|
|
net (fo=1, routed) 1.181 2.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll
|
|
PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1)
|
|
-8.248 -5.674 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1
|
|
net (fo=1, routed) 1.755 -3.919 pll_clk.u_clk_pll/inst/sys_clk_clk_pll
|
|
BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 -3.828 r pll_clk.u_clk_pll/inst/clkout2_buf/O
|
|
net (fo=10004, routed) 1.821 -2.007 u_confreg/sys_clk
|
|
SLICE_X11Y58 FDRE r u_confreg/int_out_or_q2_reg/C
|
|
------------------------------------------------------------------- -------------------
|
|
SLICE_X11Y58 FDRE (Prop_fdre_C_Q) 0.367 -1.640 r u_confreg/int_out_or_q2_reg/Q
|
|
net (fo=1, routed) 1.696 0.056 u_cpu/u_csr/interrupt[0]
|
|
SLICE_X30Y30 FDRE r u_cpu/u_csr/csr_estat_reg[2]/D
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock cpu_clk rise edge) 0.000 0.000 r
|
|
K21 0.000 0.000 r clk (IN)
|
|
net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1
|
|
K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O
|
|
net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll
|
|
PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0)
|
|
-8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0
|
|
net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll
|
|
BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout1_buf/O
|
|
net (fo=6484, routed) 2.111 -2.231 u_cpu/u_csr/cpu_clk
|
|
SLICE_X30Y30 FDRE r u_cpu/u_csr/csr_estat_reg[2]/C
|
|
|
|
Slack: inf
|
|
Source: u_Axi_CDC/rFifo/ram_reg_0_7_0_5/RAMC/CLK
|
|
(rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Destination: u_Axi_CDC/rFifo/_zz_ram_port1_reg[4]/D
|
|
(rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns})
|
|
Path Group: (none)
|
|
Path Type: Hold (Min at Slow Process Corner)
|
|
Data Path Delay: 2.149ns (logic 1.078ns (50.163%) route 1.071ns (49.837%))
|
|
Logic Levels: 0
|
|
Clock Path Skew: -0.371ns (DCD - SCD - CPR)
|
|
Destination Clock Delay (DCD): -2.394ns
|
|
Source Clock Delay (SCD): -2.022ns
|
|
Clock Pessimism Removal (CPR): -0.000ns
|
|
Clock Uncertainty: 0.194ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Discrete Jitter (DJ): 0.130ns
|
|
Phase Error (PE): 0.120ns
|
|
Timing Exception: Asynchronous Clock Groups
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock sys_clk rise edge) 0.000 0.000 r
|
|
K21 0.000 0.000 r clk (IN)
|
|
net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1
|
|
K21 IBUF (Prop_ibuf_I_O) 1.393 1.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O
|
|
net (fo=1, routed) 1.181 2.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll
|
|
PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1)
|
|
-8.248 -5.674 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1
|
|
net (fo=1, routed) 1.755 -3.919 pll_clk.u_clk_pll/inst/sys_clk_clk_pll
|
|
BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 -3.828 r pll_clk.u_clk_pll/inst/clkout2_buf/O
|
|
net (fo=10004, routed) 1.806 -2.022 u_Axi_CDC/rFifo/ram_reg_0_7_0_5/WCLK
|
|
SLICE_X18Y76 RAMD32 r u_Axi_CDC/rFifo/ram_reg_0_7_0_5/RAMC/CLK
|
|
------------------------------------------------------------------- -------------------
|
|
SLICE_X18Y76 RAMD32 (Prop_ramd32_CLK_O)
|
|
1.078 -0.944 r u_Axi_CDC/rFifo/ram_reg_0_7_0_5/RAMC/O
|
|
net (fo=1, routed) 1.071 0.127 u_Axi_CDC/rFifo/_zz_ram_port10__2[4]
|
|
SLICE_X19Y52 FDRE r u_Axi_CDC/rFifo/_zz_ram_port1_reg[4]/D
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock cpu_clk rise edge) 0.000 0.000 r
|
|
K21 0.000 0.000 r clk (IN)
|
|
net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1
|
|
K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O
|
|
net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll
|
|
PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0)
|
|
-8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0
|
|
net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll
|
|
BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout1_buf/O
|
|
net (fo=6484, routed) 1.948 -2.394 u_Axi_CDC/rFifo/cpu_clk
|
|
SLICE_X19Y52 FDRE r u_Axi_CDC/rFifo/_zz_ram_port1_reg[4]/C
|
|
|
|
Slack: inf
|
|
Source: u_Axi_CDC/rFifo/ram_reg_0_7_36_39/RAMB_D1/CLK
|
|
(rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Destination: u_Axi_CDC/rFifo/_zz_ram_port1_reg[39]/D
|
|
(rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns})
|
|
Path Group: (none)
|
|
Path Type: Hold (Min at Slow Process Corner)
|
|
Data Path Delay: 2.153ns (logic 1.062ns (49.332%) route 1.091ns (50.668%))
|
|
Logic Levels: 0
|
|
Clock Path Skew: -0.376ns (DCD - SCD - CPR)
|
|
Destination Clock Delay (DCD): -2.398ns
|
|
Source Clock Delay (SCD): -2.021ns
|
|
Clock Pessimism Removal (CPR): -0.000ns
|
|
Clock Uncertainty: 0.194ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Discrete Jitter (DJ): 0.130ns
|
|
Phase Error (PE): 0.120ns
|
|
Timing Exception: Asynchronous Clock Groups
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock sys_clk rise edge) 0.000 0.000 r
|
|
K21 0.000 0.000 r clk (IN)
|
|
net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1
|
|
K21 IBUF (Prop_ibuf_I_O) 1.393 1.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O
|
|
net (fo=1, routed) 1.181 2.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll
|
|
PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1)
|
|
-8.248 -5.674 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1
|
|
net (fo=1, routed) 1.755 -3.919 pll_clk.u_clk_pll/inst/sys_clk_clk_pll
|
|
BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 -3.828 r pll_clk.u_clk_pll/inst/clkout2_buf/O
|
|
net (fo=10004, routed) 1.807 -2.021 u_Axi_CDC/rFifo/ram_reg_0_7_36_39/WCLK
|
|
SLICE_X16Y77 RAMD32 r u_Axi_CDC/rFifo/ram_reg_0_7_36_39/RAMB_D1/CLK
|
|
------------------------------------------------------------------- -------------------
|
|
SLICE_X16Y77 RAMD32 (Prop_ramd32_CLK_O)
|
|
1.062 -0.959 r u_Axi_CDC/rFifo/ram_reg_0_7_36_39/RAMB_D1/O
|
|
net (fo=1, routed) 1.091 0.131 u_Axi_CDC/rFifo/_zz_ram_port10__2[39]
|
|
SLICE_X13Y61 FDRE r u_Axi_CDC/rFifo/_zz_ram_port1_reg[39]/D
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock cpu_clk rise edge) 0.000 0.000 r
|
|
K21 0.000 0.000 r clk (IN)
|
|
net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1
|
|
K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O
|
|
net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll
|
|
PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0)
|
|
-8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0
|
|
net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll
|
|
BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout1_buf/O
|
|
net (fo=6484, routed) 1.944 -2.398 u_Axi_CDC/rFifo/cpu_clk
|
|
SLICE_X13Y61 FDRE r u_Axi_CDC/rFifo/_zz_ram_port1_reg[39]/C
|
|
|
|
Slack: inf
|
|
Source: u_Axi_CDC/rFifo/ram_reg_0_7_30_35/RAMA_D1/CLK
|
|
(rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Destination: u_Axi_CDC/rFifo/_zz_ram_port1_reg[31]/D
|
|
(rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns})
|
|
Path Group: (none)
|
|
Path Type: Hold (Min at Slow Process Corner)
|
|
Data Path Delay: 2.174ns (logic 1.056ns (48.570%) route 1.118ns (51.430%))
|
|
Logic Levels: 0
|
|
Clock Path Skew: -0.183ns (DCD - SCD - CPR)
|
|
Destination Clock Delay (DCD): -2.208ns
|
|
Source Clock Delay (SCD): -2.024ns
|
|
Clock Pessimism Removal (CPR): -0.000ns
|
|
Clock Uncertainty: 0.194ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Discrete Jitter (DJ): 0.130ns
|
|
Phase Error (PE): 0.120ns
|
|
Timing Exception: Asynchronous Clock Groups
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock sys_clk rise edge) 0.000 0.000 r
|
|
K21 0.000 0.000 r clk (IN)
|
|
net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1
|
|
K21 IBUF (Prop_ibuf_I_O) 1.393 1.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O
|
|
net (fo=1, routed) 1.181 2.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll
|
|
PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1)
|
|
-8.248 -5.674 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1
|
|
net (fo=1, routed) 1.755 -3.919 pll_clk.u_clk_pll/inst/sys_clk_clk_pll
|
|
BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 -3.828 r pll_clk.u_clk_pll/inst/clkout2_buf/O
|
|
net (fo=10004, routed) 1.804 -2.024 u_Axi_CDC/rFifo/ram_reg_0_7_30_35/WCLK
|
|
SLICE_X14Y75 RAMD32 r u_Axi_CDC/rFifo/ram_reg_0_7_30_35/RAMA_D1/CLK
|
|
------------------------------------------------------------------- -------------------
|
|
SLICE_X14Y75 RAMD32 (Prop_ramd32_CLK_O)
|
|
1.056 -0.968 r u_Axi_CDC/rFifo/ram_reg_0_7_30_35/RAMA_D1/O
|
|
net (fo=1, routed) 1.118 0.150 u_Axi_CDC/rFifo/_zz_ram_port10__2[31]
|
|
SLICE_X15Y48 FDRE r u_Axi_CDC/rFifo/_zz_ram_port1_reg[31]/D
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock cpu_clk rise edge) 0.000 0.000 r
|
|
K21 0.000 0.000 r clk (IN)
|
|
net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1
|
|
K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O
|
|
net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll
|
|
PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0)
|
|
-8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0
|
|
net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll
|
|
BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout1_buf/O
|
|
net (fo=6484, routed) 2.134 -2.208 u_Axi_CDC/rFifo/cpu_clk
|
|
SLICE_X15Y48 FDRE r u_Axi_CDC/rFifo/_zz_ram_port1_reg[31]/C
|
|
|
|
Slack: inf
|
|
Source: u_Axi_CDC/rFifo/ram_reg_0_7_12_17/RAMC/CLK
|
|
(rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Destination: u_Axi_CDC/rFifo/_zz_ram_port1_reg[16]/D
|
|
(rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns})
|
|
Path Group: (none)
|
|
Path Type: Hold (Min at Slow Process Corner)
|
|
Data Path Delay: 2.202ns (logic 1.078ns (48.964%) route 1.124ns (51.036%))
|
|
Logic Levels: 0
|
|
Clock Path Skew: -0.185ns (DCD - SCD - CPR)
|
|
Destination Clock Delay (DCD): -2.210ns
|
|
Source Clock Delay (SCD): -2.024ns
|
|
Clock Pessimism Removal (CPR): -0.000ns
|
|
Clock Uncertainty: 0.194ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Discrete Jitter (DJ): 0.130ns
|
|
Phase Error (PE): 0.120ns
|
|
Timing Exception: Asynchronous Clock Groups
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock sys_clk rise edge) 0.000 0.000 r
|
|
K21 0.000 0.000 r clk (IN)
|
|
net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1
|
|
K21 IBUF (Prop_ibuf_I_O) 1.393 1.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O
|
|
net (fo=1, routed) 1.181 2.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll
|
|
PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1)
|
|
-8.248 -5.674 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1
|
|
net (fo=1, routed) 1.755 -3.919 pll_clk.u_clk_pll/inst/sys_clk_clk_pll
|
|
BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 -3.828 r pll_clk.u_clk_pll/inst/clkout2_buf/O
|
|
net (fo=10004, routed) 1.804 -2.024 u_Axi_CDC/rFifo/ram_reg_0_7_12_17/WCLK
|
|
SLICE_X18Y75 RAMD32 r u_Axi_CDC/rFifo/ram_reg_0_7_12_17/RAMC/CLK
|
|
------------------------------------------------------------------- -------------------
|
|
SLICE_X18Y75 RAMD32 (Prop_ramd32_CLK_O)
|
|
1.078 -0.946 r u_Axi_CDC/rFifo/ram_reg_0_7_12_17/RAMC/O
|
|
net (fo=1, routed) 1.124 0.177 u_Axi_CDC/rFifo/_zz_ram_port10__2[16]
|
|
SLICE_X19Y47 FDRE r u_Axi_CDC/rFifo/_zz_ram_port1_reg[16]/D
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock cpu_clk rise edge) 0.000 0.000 r
|
|
K21 0.000 0.000 r clk (IN)
|
|
net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1
|
|
K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O
|
|
net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll
|
|
PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0)
|
|
-8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0
|
|
net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll
|
|
BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout1_buf/O
|
|
net (fo=6484, routed) 2.132 -2.210 u_Axi_CDC/rFifo/cpu_clk
|
|
SLICE_X19Y47 FDRE r u_Axi_CDC/rFifo/_zz_ram_port1_reg[16]/C
|
|
|
|
Slack: inf
|
|
Source: u_Axi_CDC/rFifo/ram_reg_0_7_30_35/RAMB/CLK
|
|
(rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Destination: u_Axi_CDC/rFifo/_zz_ram_port1_reg[32]/D
|
|
(rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns})
|
|
Path Group: (none)
|
|
Path Type: Hold (Min at Slow Process Corner)
|
|
Data Path Delay: 2.203ns (logic 1.083ns (49.171%) route 1.120ns (50.829%))
|
|
Logic Levels: 0
|
|
Clock Path Skew: -0.183ns (DCD - SCD - CPR)
|
|
Destination Clock Delay (DCD): -2.208ns
|
|
Source Clock Delay (SCD): -2.024ns
|
|
Clock Pessimism Removal (CPR): -0.000ns
|
|
Clock Uncertainty: 0.194ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Discrete Jitter (DJ): 0.130ns
|
|
Phase Error (PE): 0.120ns
|
|
Timing Exception: Asynchronous Clock Groups
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock sys_clk rise edge) 0.000 0.000 r
|
|
K21 0.000 0.000 r clk (IN)
|
|
net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1
|
|
K21 IBUF (Prop_ibuf_I_O) 1.393 1.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O
|
|
net (fo=1, routed) 1.181 2.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll
|
|
PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1)
|
|
-8.248 -5.674 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1
|
|
net (fo=1, routed) 1.755 -3.919 pll_clk.u_clk_pll/inst/sys_clk_clk_pll
|
|
BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 -3.828 r pll_clk.u_clk_pll/inst/clkout2_buf/O
|
|
net (fo=10004, routed) 1.804 -2.024 u_Axi_CDC/rFifo/ram_reg_0_7_30_35/WCLK
|
|
SLICE_X14Y75 RAMD32 r u_Axi_CDC/rFifo/ram_reg_0_7_30_35/RAMB/CLK
|
|
------------------------------------------------------------------- -------------------
|
|
SLICE_X14Y75 RAMD32 (Prop_ramd32_CLK_O)
|
|
1.083 -0.941 r u_Axi_CDC/rFifo/ram_reg_0_7_30_35/RAMB/O
|
|
net (fo=1, routed) 1.120 0.178 u_Axi_CDC/rFifo/_zz_ram_port10__2[32]
|
|
SLICE_X15Y48 FDRE r u_Axi_CDC/rFifo/_zz_ram_port1_reg[32]/D
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock cpu_clk rise edge) 0.000 0.000 r
|
|
K21 0.000 0.000 r clk (IN)
|
|
net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1
|
|
K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O
|
|
net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll
|
|
PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0)
|
|
-8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0
|
|
net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll
|
|
BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout1_buf/O
|
|
net (fo=6484, routed) 2.134 -2.208 u_Axi_CDC/rFifo/cpu_clk
|
|
SLICE_X15Y48 FDRE r u_Axi_CDC/rFifo/_zz_ram_port1_reg[32]/C
|
|
|
|
Slack: inf
|
|
Source: u_Axi_CDC/rFifo/ram_reg_0_7_12_17/RAMB/CLK
|
|
(rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Destination: u_Axi_CDC/rFifo/_zz_ram_port1_reg[14]/D
|
|
(rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns})
|
|
Path Group: (none)
|
|
Path Type: Hold (Min at Slow Process Corner)
|
|
Data Path Delay: 2.208ns (logic 1.083ns (49.047%) route 1.125ns (50.953%))
|
|
Logic Levels: 0
|
|
Clock Path Skew: -0.370ns (DCD - SCD - CPR)
|
|
Destination Clock Delay (DCD): -2.395ns
|
|
Source Clock Delay (SCD): -2.024ns
|
|
Clock Pessimism Removal (CPR): -0.000ns
|
|
Clock Uncertainty: 0.194ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Discrete Jitter (DJ): 0.130ns
|
|
Phase Error (PE): 0.120ns
|
|
Timing Exception: Asynchronous Clock Groups
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock sys_clk rise edge) 0.000 0.000 r
|
|
K21 0.000 0.000 r clk (IN)
|
|
net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1
|
|
K21 IBUF (Prop_ibuf_I_O) 1.393 1.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O
|
|
net (fo=1, routed) 1.181 2.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll
|
|
PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1)
|
|
-8.248 -5.674 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1
|
|
net (fo=1, routed) 1.755 -3.919 pll_clk.u_clk_pll/inst/sys_clk_clk_pll
|
|
BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 -3.828 r pll_clk.u_clk_pll/inst/clkout2_buf/O
|
|
net (fo=10004, routed) 1.804 -2.024 u_Axi_CDC/rFifo/ram_reg_0_7_12_17/WCLK
|
|
SLICE_X18Y75 RAMD32 r u_Axi_CDC/rFifo/ram_reg_0_7_12_17/RAMB/CLK
|
|
------------------------------------------------------------------- -------------------
|
|
SLICE_X18Y75 RAMD32 (Prop_ramd32_CLK_O)
|
|
1.083 -0.941 r u_Axi_CDC/rFifo/ram_reg_0_7_12_17/RAMB/O
|
|
net (fo=1, routed) 1.125 0.184 u_Axi_CDC/rFifo/_zz_ram_port10__2[14]
|
|
SLICE_X19Y53 FDRE r u_Axi_CDC/rFifo/_zz_ram_port1_reg[14]/D
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock cpu_clk rise edge) 0.000 0.000 r
|
|
K21 0.000 0.000 r clk (IN)
|
|
net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1
|
|
K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O
|
|
net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll
|
|
PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0)
|
|
-8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0
|
|
net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll
|
|
BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout1_buf/O
|
|
net (fo=6484, routed) 1.947 -2.395 u_Axi_CDC/rFifo/cpu_clk
|
|
SLICE_X19Y53 FDRE r u_Axi_CDC/rFifo/_zz_ram_port1_reg[14]/C
|
|
|
|
Slack: inf
|
|
Source: u_Axi_CDC/rFifo/ram_reg_0_7_24_29/RAMC/CLK
|
|
(rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Destination: u_Axi_CDC/rFifo/_zz_ram_port1_reg[28]/D
|
|
(rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns})
|
|
Path Group: (none)
|
|
Path Type: Hold (Min at Slow Process Corner)
|
|
Data Path Delay: 2.216ns (logic 1.078ns (48.649%) route 1.138ns (51.351%))
|
|
Logic Levels: 0
|
|
Clock Path Skew: -0.372ns (DCD - SCD - CPR)
|
|
Destination Clock Delay (DCD): -2.394ns
|
|
Source Clock Delay (SCD): -2.021ns
|
|
Clock Pessimism Removal (CPR): -0.000ns
|
|
Clock Uncertainty: 0.194ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Discrete Jitter (DJ): 0.130ns
|
|
Phase Error (PE): 0.120ns
|
|
Timing Exception: Asynchronous Clock Groups
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock sys_clk rise edge) 0.000 0.000 r
|
|
K21 0.000 0.000 r clk (IN)
|
|
net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1
|
|
K21 IBUF (Prop_ibuf_I_O) 1.393 1.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O
|
|
net (fo=1, routed) 1.181 2.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll
|
|
PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1)
|
|
-8.248 -5.674 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1
|
|
net (fo=1, routed) 1.755 -3.919 pll_clk.u_clk_pll/inst/sys_clk_clk_pll
|
|
BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 -3.828 r pll_clk.u_clk_pll/inst/clkout2_buf/O
|
|
net (fo=10004, routed) 1.807 -2.021 u_Axi_CDC/rFifo/ram_reg_0_7_24_29/WCLK
|
|
SLICE_X14Y77 RAMD32 r u_Axi_CDC/rFifo/ram_reg_0_7_24_29/RAMC/CLK
|
|
------------------------------------------------------------------- -------------------
|
|
SLICE_X14Y77 RAMD32 (Prop_ramd32_CLK_O)
|
|
1.078 -0.943 r u_Axi_CDC/rFifo/ram_reg_0_7_24_29/RAMC/O
|
|
net (fo=1, routed) 1.138 0.195 u_Axi_CDC/rFifo/_zz_ram_port10__2[28]
|
|
SLICE_X17Y50 FDRE r u_Axi_CDC/rFifo/_zz_ram_port1_reg[28]/D
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock cpu_clk rise edge) 0.000 0.000 r
|
|
K21 0.000 0.000 r clk (IN)
|
|
net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1
|
|
K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O
|
|
net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll
|
|
PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0)
|
|
-8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0
|
|
net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll
|
|
BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout1_buf/O
|
|
net (fo=6484, routed) 1.948 -2.394 u_Axi_CDC/rFifo/cpu_clk
|
|
SLICE_X17Y50 FDRE r u_Axi_CDC/rFifo/_zz_ram_port1_reg[28]/C
|
|
|
|
Slack: inf
|
|
Source: u_Axi_CDC/rFifo/ram_reg_0_7_12_17/RAMA_D1/CLK
|
|
(rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Destination: u_Axi_CDC/rFifo/_zz_ram_port1_reg[13]/D
|
|
(rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns})
|
|
Path Group: (none)
|
|
Path Type: Hold (Min at Slow Process Corner)
|
|
Data Path Delay: 2.231ns (logic 1.056ns (47.336%) route 1.175ns (52.664%))
|
|
Logic Levels: 0
|
|
Clock Path Skew: -0.185ns (DCD - SCD - CPR)
|
|
Destination Clock Delay (DCD): -2.210ns
|
|
Source Clock Delay (SCD): -2.024ns
|
|
Clock Pessimism Removal (CPR): -0.000ns
|
|
Clock Uncertainty: 0.194ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Discrete Jitter (DJ): 0.130ns
|
|
Phase Error (PE): 0.120ns
|
|
Timing Exception: Asynchronous Clock Groups
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock sys_clk rise edge) 0.000 0.000 r
|
|
K21 0.000 0.000 r clk (IN)
|
|
net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1
|
|
K21 IBUF (Prop_ibuf_I_O) 1.393 1.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O
|
|
net (fo=1, routed) 1.181 2.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll
|
|
PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1)
|
|
-8.248 -5.674 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1
|
|
net (fo=1, routed) 1.755 -3.919 pll_clk.u_clk_pll/inst/sys_clk_clk_pll
|
|
BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 -3.828 r pll_clk.u_clk_pll/inst/clkout2_buf/O
|
|
net (fo=10004, routed) 1.804 -2.024 u_Axi_CDC/rFifo/ram_reg_0_7_12_17/WCLK
|
|
SLICE_X18Y75 RAMD32 r u_Axi_CDC/rFifo/ram_reg_0_7_12_17/RAMA_D1/CLK
|
|
------------------------------------------------------------------- -------------------
|
|
SLICE_X18Y75 RAMD32 (Prop_ramd32_CLK_O)
|
|
1.056 -0.968 r u_Axi_CDC/rFifo/ram_reg_0_7_12_17/RAMA_D1/O
|
|
net (fo=1, routed) 1.175 0.207 u_Axi_CDC/rFifo/_zz_ram_port10__2[13]
|
|
SLICE_X19Y49 FDRE r u_Axi_CDC/rFifo/_zz_ram_port1_reg[13]/D
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock cpu_clk rise edge) 0.000 0.000 r
|
|
K21 0.000 0.000 r clk (IN)
|
|
net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1
|
|
K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O
|
|
net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll
|
|
PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0)
|
|
-8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0
|
|
net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll
|
|
BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout1_buf/O
|
|
net (fo=6484, routed) 2.132 -2.210 u_Axi_CDC/rFifo/cpu_clk
|
|
SLICE_X19Y49 FDRE r u_Axi_CDC/rFifo/_zz_ram_port1_reg[13]/C
|
|
|
|
Slack: inf
|
|
Source: u_Axi_CDC/rFifo/ram_reg_0_7_0_5/RAMA_D1/CLK
|
|
(rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Destination: u_Axi_CDC/rFifo/_zz_ram_port1_reg[1]/D
|
|
(rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns})
|
|
Path Group: (none)
|
|
Path Type: Hold (Min at Slow Process Corner)
|
|
Data Path Delay: 2.300ns (logic 1.056ns (45.907%) route 1.244ns (54.093%))
|
|
Logic Levels: 0
|
|
Clock Path Skew: -0.187ns (DCD - SCD - CPR)
|
|
Destination Clock Delay (DCD): -2.210ns
|
|
Source Clock Delay (SCD): -2.022ns
|
|
Clock Pessimism Removal (CPR): -0.000ns
|
|
Clock Uncertainty: 0.194ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Discrete Jitter (DJ): 0.130ns
|
|
Phase Error (PE): 0.120ns
|
|
Timing Exception: Asynchronous Clock Groups
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock sys_clk rise edge) 0.000 0.000 r
|
|
K21 0.000 0.000 r clk (IN)
|
|
net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1
|
|
K21 IBUF (Prop_ibuf_I_O) 1.393 1.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O
|
|
net (fo=1, routed) 1.181 2.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll
|
|
PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1)
|
|
-8.248 -5.674 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1
|
|
net (fo=1, routed) 1.755 -3.919 pll_clk.u_clk_pll/inst/sys_clk_clk_pll
|
|
BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 -3.828 r pll_clk.u_clk_pll/inst/clkout2_buf/O
|
|
net (fo=10004, routed) 1.806 -2.022 u_Axi_CDC/rFifo/ram_reg_0_7_0_5/WCLK
|
|
SLICE_X18Y76 RAMD32 r u_Axi_CDC/rFifo/ram_reg_0_7_0_5/RAMA_D1/CLK
|
|
------------------------------------------------------------------- -------------------
|
|
SLICE_X18Y76 RAMD32 (Prop_ramd32_CLK_O)
|
|
1.056 -0.966 r u_Axi_CDC/rFifo/ram_reg_0_7_0_5/RAMA_D1/O
|
|
net (fo=1, routed) 1.244 0.278 u_Axi_CDC/rFifo/_zz_ram_port10__2[1]
|
|
SLICE_X19Y49 FDRE r u_Axi_CDC/rFifo/_zz_ram_port1_reg[1]/D
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock cpu_clk rise edge) 0.000 0.000 r
|
|
K21 0.000 0.000 r clk (IN)
|
|
net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1
|
|
K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O
|
|
net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll
|
|
PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0)
|
|
-8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0
|
|
net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll
|
|
BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout1_buf/O
|
|
net (fo=6484, routed) 2.132 -2.210 u_Axi_CDC/rFifo/cpu_clk
|
|
SLICE_X19Y49 FDRE r u_Axi_CDC/rFifo/_zz_ram_port1_reg[1]/C
|
|
|
|
Slack: inf
|
|
Source: u_Axi_CDC/rFifo/ram_reg_0_7_12_17/RAMA/CLK
|
|
(rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Destination: u_Axi_CDC/rFifo/_zz_ram_port1_reg[12]/D
|
|
(rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns})
|
|
Path Group: (none)
|
|
Path Type: Hold (Min at Slow Process Corner)
|
|
Data Path Delay: 2.329ns (logic 1.084ns (46.543%) route 1.245ns (53.457%))
|
|
Logic Levels: 0
|
|
Clock Path Skew: -0.369ns (DCD - SCD - CPR)
|
|
Destination Clock Delay (DCD): -2.394ns
|
|
Source Clock Delay (SCD): -2.024ns
|
|
Clock Pessimism Removal (CPR): -0.000ns
|
|
Clock Uncertainty: 0.194ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Discrete Jitter (DJ): 0.130ns
|
|
Phase Error (PE): 0.120ns
|
|
Timing Exception: Asynchronous Clock Groups
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock sys_clk rise edge) 0.000 0.000 r
|
|
K21 0.000 0.000 r clk (IN)
|
|
net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1
|
|
K21 IBUF (Prop_ibuf_I_O) 1.393 1.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O
|
|
net (fo=1, routed) 1.181 2.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll
|
|
PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1)
|
|
-8.248 -5.674 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1
|
|
net (fo=1, routed) 1.755 -3.919 pll_clk.u_clk_pll/inst/sys_clk_clk_pll
|
|
BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 -3.828 r pll_clk.u_clk_pll/inst/clkout2_buf/O
|
|
net (fo=10004, routed) 1.804 -2.024 u_Axi_CDC/rFifo/ram_reg_0_7_12_17/WCLK
|
|
SLICE_X18Y75 RAMD32 r u_Axi_CDC/rFifo/ram_reg_0_7_12_17/RAMA/CLK
|
|
------------------------------------------------------------------- -------------------
|
|
SLICE_X18Y75 RAMD32 (Prop_ramd32_CLK_O)
|
|
1.084 -0.940 r u_Axi_CDC/rFifo/ram_reg_0_7_12_17/RAMA/O
|
|
net (fo=1, routed) 1.245 0.305 u_Axi_CDC/rFifo/_zz_ram_port10__2[12]
|
|
SLICE_X19Y50 FDRE r u_Axi_CDC/rFifo/_zz_ram_port1_reg[12]/D
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock cpu_clk rise edge) 0.000 0.000 r
|
|
K21 0.000 0.000 r clk (IN)
|
|
net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1
|
|
K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O
|
|
net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll
|
|
PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0)
|
|
-8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0
|
|
net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll
|
|
BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout1_buf/O
|
|
net (fo=6484, routed) 1.948 -2.394 u_Axi_CDC/rFifo/cpu_clk
|
|
SLICE_X19Y50 FDRE r u_Axi_CDC/rFifo/_zz_ram_port1_reg[12]/C
|
|
|
|
Slack: inf
|
|
Source: u_Axi_CDC/rFifo/ram_reg_0_7_24_29/RAMC_D1/CLK
|
|
(rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Destination: u_Axi_CDC/rFifo/_zz_ram_port1_reg[29]/D
|
|
(rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns})
|
|
Path Group: (none)
|
|
Path Type: Hold (Min at Slow Process Corner)
|
|
Data Path Delay: 2.337ns (logic 1.059ns (45.323%) route 1.278ns (54.677%))
|
|
Logic Levels: 0
|
|
Clock Path Skew: -0.373ns (DCD - SCD - CPR)
|
|
Destination Clock Delay (DCD): -2.395ns
|
|
Source Clock Delay (SCD): -2.021ns
|
|
Clock Pessimism Removal (CPR): -0.000ns
|
|
Clock Uncertainty: 0.194ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Discrete Jitter (DJ): 0.130ns
|
|
Phase Error (PE): 0.120ns
|
|
Timing Exception: Asynchronous Clock Groups
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock sys_clk rise edge) 0.000 0.000 r
|
|
K21 0.000 0.000 r clk (IN)
|
|
net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1
|
|
K21 IBUF (Prop_ibuf_I_O) 1.393 1.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O
|
|
net (fo=1, routed) 1.181 2.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll
|
|
PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1)
|
|
-8.248 -5.674 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1
|
|
net (fo=1, routed) 1.755 -3.919 pll_clk.u_clk_pll/inst/sys_clk_clk_pll
|
|
BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 -3.828 r pll_clk.u_clk_pll/inst/clkout2_buf/O
|
|
net (fo=10004, routed) 1.807 -2.021 u_Axi_CDC/rFifo/ram_reg_0_7_24_29/WCLK
|
|
SLICE_X14Y77 RAMD32 r u_Axi_CDC/rFifo/ram_reg_0_7_24_29/RAMC_D1/CLK
|
|
------------------------------------------------------------------- -------------------
|
|
SLICE_X14Y77 RAMD32 (Prop_ramd32_CLK_O)
|
|
1.059 -0.962 r u_Axi_CDC/rFifo/ram_reg_0_7_24_29/RAMC_D1/O
|
|
net (fo=1, routed) 1.278 0.315 u_Axi_CDC/rFifo/_zz_ram_port10__2[29]
|
|
SLICE_X15Y54 FDRE r u_Axi_CDC/rFifo/_zz_ram_port1_reg[29]/D
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock cpu_clk rise edge) 0.000 0.000 r
|
|
K21 0.000 0.000 r clk (IN)
|
|
net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1
|
|
K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O
|
|
net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll
|
|
PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0)
|
|
-8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0
|
|
net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll
|
|
BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout1_buf/O
|
|
net (fo=6484, routed) 1.947 -2.395 u_Axi_CDC/rFifo/cpu_clk
|
|
SLICE_X15Y54 FDRE r u_Axi_CDC/rFifo/_zz_ram_port1_reg[29]/C
|
|
|
|
Slack: inf
|
|
Source: u_Axi_CDC/rFifo/ram_reg_0_7_0_5/RAMC_D1/CLK
|
|
(rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Destination: u_Axi_CDC/rFifo/_zz_ram_port1_reg[5]/D
|
|
(rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns})
|
|
Path Group: (none)
|
|
Path Type: Hold (Min at Slow Process Corner)
|
|
Data Path Delay: 2.340ns (logic 1.059ns (45.262%) route 1.281ns (54.738%))
|
|
Logic Levels: 0
|
|
Clock Path Skew: -0.187ns (DCD - SCD - CPR)
|
|
Destination Clock Delay (DCD): -2.210ns
|
|
Source Clock Delay (SCD): -2.022ns
|
|
Clock Pessimism Removal (CPR): -0.000ns
|
|
Clock Uncertainty: 0.194ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Discrete Jitter (DJ): 0.130ns
|
|
Phase Error (PE): 0.120ns
|
|
Timing Exception: Asynchronous Clock Groups
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock sys_clk rise edge) 0.000 0.000 r
|
|
K21 0.000 0.000 r clk (IN)
|
|
net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1
|
|
K21 IBUF (Prop_ibuf_I_O) 1.393 1.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O
|
|
net (fo=1, routed) 1.181 2.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll
|
|
PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1)
|
|
-8.248 -5.674 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1
|
|
net (fo=1, routed) 1.755 -3.919 pll_clk.u_clk_pll/inst/sys_clk_clk_pll
|
|
BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 -3.828 r pll_clk.u_clk_pll/inst/clkout2_buf/O
|
|
net (fo=10004, routed) 1.806 -2.022 u_Axi_CDC/rFifo/ram_reg_0_7_0_5/WCLK
|
|
SLICE_X18Y76 RAMD32 r u_Axi_CDC/rFifo/ram_reg_0_7_0_5/RAMC_D1/CLK
|
|
------------------------------------------------------------------- -------------------
|
|
SLICE_X18Y76 RAMD32 (Prop_ramd32_CLK_O)
|
|
1.059 -0.963 r u_Axi_CDC/rFifo/ram_reg_0_7_0_5/RAMC_D1/O
|
|
net (fo=1, routed) 1.281 0.317 u_Axi_CDC/rFifo/_zz_ram_port10__2[5]
|
|
SLICE_X19Y49 FDRE r u_Axi_CDC/rFifo/_zz_ram_port1_reg[5]/D
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock cpu_clk rise edge) 0.000 0.000 r
|
|
K21 0.000 0.000 r clk (IN)
|
|
net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1
|
|
K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O
|
|
net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll
|
|
PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0)
|
|
-8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0
|
|
net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll
|
|
BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout1_buf/O
|
|
net (fo=6484, routed) 2.132 -2.210 u_Axi_CDC/rFifo/cpu_clk
|
|
SLICE_X19Y49 FDRE r u_Axi_CDC/rFifo/_zz_ram_port1_reg[5]/C
|
|
|
|
Slack: inf
|
|
Source: u_Axi_CDC/rFifo/ram_reg_0_7_6_11/RAMA_D1/CLK
|
|
(rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Destination: u_Axi_CDC/rFifo/_zz_ram_port1_reg[7]/D
|
|
(rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns})
|
|
Path Group: (none)
|
|
Path Type: Hold (Min at Slow Process Corner)
|
|
Data Path Delay: 2.340ns (logic 1.056ns (45.123%) route 1.284ns (54.877%))
|
|
Logic Levels: 0
|
|
Clock Path Skew: -0.188ns (DCD - SCD - CPR)
|
|
Destination Clock Delay (DCD): -2.210ns
|
|
Source Clock Delay (SCD): -2.021ns
|
|
Clock Pessimism Removal (CPR): -0.000ns
|
|
Clock Uncertainty: 0.194ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Discrete Jitter (DJ): 0.130ns
|
|
Phase Error (PE): 0.120ns
|
|
Timing Exception: Asynchronous Clock Groups
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock sys_clk rise edge) 0.000 0.000 r
|
|
K21 0.000 0.000 r clk (IN)
|
|
net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1
|
|
K21 IBUF (Prop_ibuf_I_O) 1.393 1.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O
|
|
net (fo=1, routed) 1.181 2.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll
|
|
PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1)
|
|
-8.248 -5.674 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1
|
|
net (fo=1, routed) 1.755 -3.919 pll_clk.u_clk_pll/inst/sys_clk_clk_pll
|
|
BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 -3.828 r pll_clk.u_clk_pll/inst/clkout2_buf/O
|
|
net (fo=10004, routed) 1.807 -2.021 u_Axi_CDC/rFifo/ram_reg_0_7_6_11/WCLK
|
|
SLICE_X18Y77 RAMD32 r u_Axi_CDC/rFifo/ram_reg_0_7_6_11/RAMA_D1/CLK
|
|
------------------------------------------------------------------- -------------------
|
|
SLICE_X18Y77 RAMD32 (Prop_ramd32_CLK_O)
|
|
1.056 -0.965 r u_Axi_CDC/rFifo/ram_reg_0_7_6_11/RAMA_D1/O
|
|
net (fo=1, routed) 1.284 0.319 u_Axi_CDC/rFifo/_zz_ram_port10__2[7]
|
|
SLICE_X19Y49 FDRE r u_Axi_CDC/rFifo/_zz_ram_port1_reg[7]/D
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock cpu_clk rise edge) 0.000 0.000 r
|
|
K21 0.000 0.000 r clk (IN)
|
|
net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1
|
|
K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O
|
|
net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll
|
|
PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0)
|
|
-8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0
|
|
net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll
|
|
BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout1_buf/O
|
|
net (fo=6484, routed) 2.132 -2.210 u_Axi_CDC/rFifo/cpu_clk
|
|
SLICE_X19Y49 FDRE r u_Axi_CDC/rFifo/_zz_ram_port1_reg[7]/C
|
|
|
|
Slack: inf
|
|
Source: u_Axi_CDC/rFifo/ram_reg_0_7_30_35/RAMA/CLK
|
|
(rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Destination: u_Axi_CDC/rFifo/_zz_ram_port1_reg[30]/D
|
|
(rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns})
|
|
Path Group: (none)
|
|
Path Type: Hold (Min at Slow Process Corner)
|
|
Data Path Delay: 2.349ns (logic 1.084ns (46.148%) route 1.265ns (53.852%))
|
|
Logic Levels: 0
|
|
Clock Path Skew: -0.183ns (DCD - SCD - CPR)
|
|
Destination Clock Delay (DCD): -2.208ns
|
|
Source Clock Delay (SCD): -2.024ns
|
|
Clock Pessimism Removal (CPR): -0.000ns
|
|
Clock Uncertainty: 0.194ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Discrete Jitter (DJ): 0.130ns
|
|
Phase Error (PE): 0.120ns
|
|
Timing Exception: Asynchronous Clock Groups
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock sys_clk rise edge) 0.000 0.000 r
|
|
K21 0.000 0.000 r clk (IN)
|
|
net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1
|
|
K21 IBUF (Prop_ibuf_I_O) 1.393 1.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O
|
|
net (fo=1, routed) 1.181 2.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll
|
|
PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1)
|
|
-8.248 -5.674 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1
|
|
net (fo=1, routed) 1.755 -3.919 pll_clk.u_clk_pll/inst/sys_clk_clk_pll
|
|
BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 -3.828 r pll_clk.u_clk_pll/inst/clkout2_buf/O
|
|
net (fo=10004, routed) 1.804 -2.024 u_Axi_CDC/rFifo/ram_reg_0_7_30_35/WCLK
|
|
SLICE_X14Y75 RAMD32 r u_Axi_CDC/rFifo/ram_reg_0_7_30_35/RAMA/CLK
|
|
------------------------------------------------------------------- -------------------
|
|
SLICE_X14Y75 RAMD32 (Prop_ramd32_CLK_O)
|
|
1.084 -0.940 r u_Axi_CDC/rFifo/ram_reg_0_7_30_35/RAMA/O
|
|
net (fo=1, routed) 1.265 0.325 u_Axi_CDC/rFifo/_zz_ram_port10__2[30]
|
|
SLICE_X15Y48 FDRE r u_Axi_CDC/rFifo/_zz_ram_port1_reg[30]/D
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock cpu_clk rise edge) 0.000 0.000 r
|
|
K21 0.000 0.000 r clk (IN)
|
|
net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1
|
|
K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O
|
|
net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll
|
|
PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0)
|
|
-8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0
|
|
net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll
|
|
BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout1_buf/O
|
|
net (fo=6484, routed) 2.134 -2.208 u_Axi_CDC/rFifo/cpu_clk
|
|
SLICE_X15Y48 FDRE r u_Axi_CDC/rFifo/_zz_ram_port1_reg[30]/C
|
|
|
|
Slack: inf
|
|
Source: u_Axi_CDC/rFifo/ram_reg_0_7_0_5/RAMB/CLK
|
|
(rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Destination: u_Axi_CDC/rFifo/_zz_ram_port1_reg[2]/D
|
|
(rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns})
|
|
Path Group: (none)
|
|
Path Type: Hold (Min at Slow Process Corner)
|
|
Data Path Delay: 2.378ns (logic 1.083ns (45.550%) route 1.295ns (54.450%))
|
|
Logic Levels: 0
|
|
Clock Path Skew: -0.187ns (DCD - SCD - CPR)
|
|
Destination Clock Delay (DCD): -2.210ns
|
|
Source Clock Delay (SCD): -2.022ns
|
|
Clock Pessimism Removal (CPR): -0.000ns
|
|
Clock Uncertainty: 0.194ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Discrete Jitter (DJ): 0.130ns
|
|
Phase Error (PE): 0.120ns
|
|
Timing Exception: Asynchronous Clock Groups
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock sys_clk rise edge) 0.000 0.000 r
|
|
K21 0.000 0.000 r clk (IN)
|
|
net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1
|
|
K21 IBUF (Prop_ibuf_I_O) 1.393 1.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O
|
|
net (fo=1, routed) 1.181 2.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll
|
|
PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1)
|
|
-8.248 -5.674 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1
|
|
net (fo=1, routed) 1.755 -3.919 pll_clk.u_clk_pll/inst/sys_clk_clk_pll
|
|
BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 -3.828 r pll_clk.u_clk_pll/inst/clkout2_buf/O
|
|
net (fo=10004, routed) 1.806 -2.022 u_Axi_CDC/rFifo/ram_reg_0_7_0_5/WCLK
|
|
SLICE_X18Y76 RAMD32 r u_Axi_CDC/rFifo/ram_reg_0_7_0_5/RAMB/CLK
|
|
------------------------------------------------------------------- -------------------
|
|
SLICE_X18Y76 RAMD32 (Prop_ramd32_CLK_O)
|
|
1.083 -0.939 r u_Axi_CDC/rFifo/ram_reg_0_7_0_5/RAMB/O
|
|
net (fo=1, routed) 1.295 0.355 u_Axi_CDC/rFifo/_zz_ram_port10__2[2]
|
|
SLICE_X19Y47 FDRE r u_Axi_CDC/rFifo/_zz_ram_port1_reg[2]/D
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock cpu_clk rise edge) 0.000 0.000 r
|
|
K21 0.000 0.000 r clk (IN)
|
|
net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1
|
|
K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O
|
|
net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll
|
|
PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0)
|
|
-8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0
|
|
net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll
|
|
BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout1_buf/O
|
|
net (fo=6484, routed) 2.132 -2.210 u_Axi_CDC/rFifo/cpu_clk
|
|
SLICE_X19Y47 FDRE r u_Axi_CDC/rFifo/_zz_ram_port1_reg[2]/C
|
|
|
|
Slack: inf
|
|
Source: u_Axi_CDC/rFifo/ram_reg_0_7_0_5/RAMB_D1/CLK
|
|
(rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Destination: u_Axi_CDC/rFifo/_zz_ram_port1_reg[3]/D
|
|
(rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns})
|
|
Path Group: (none)
|
|
Path Type: Hold (Min at Slow Process Corner)
|
|
Data Path Delay: 2.380ns (logic 1.062ns (44.630%) route 1.318ns (55.370%))
|
|
Logic Levels: 0
|
|
Clock Path Skew: -0.187ns (DCD - SCD - CPR)
|
|
Destination Clock Delay (DCD): -2.210ns
|
|
Source Clock Delay (SCD): -2.022ns
|
|
Clock Pessimism Removal (CPR): -0.000ns
|
|
Clock Uncertainty: 0.194ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Discrete Jitter (DJ): 0.130ns
|
|
Phase Error (PE): 0.120ns
|
|
Timing Exception: Asynchronous Clock Groups
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock sys_clk rise edge) 0.000 0.000 r
|
|
K21 0.000 0.000 r clk (IN)
|
|
net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1
|
|
K21 IBUF (Prop_ibuf_I_O) 1.393 1.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O
|
|
net (fo=1, routed) 1.181 2.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll
|
|
PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1)
|
|
-8.248 -5.674 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1
|
|
net (fo=1, routed) 1.755 -3.919 pll_clk.u_clk_pll/inst/sys_clk_clk_pll
|
|
BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 -3.828 r pll_clk.u_clk_pll/inst/clkout2_buf/O
|
|
net (fo=10004, routed) 1.806 -2.022 u_Axi_CDC/rFifo/ram_reg_0_7_0_5/WCLK
|
|
SLICE_X18Y76 RAMD32 r u_Axi_CDC/rFifo/ram_reg_0_7_0_5/RAMB_D1/CLK
|
|
------------------------------------------------------------------- -------------------
|
|
SLICE_X18Y76 RAMD32 (Prop_ramd32_CLK_O)
|
|
1.062 -0.960 r u_Axi_CDC/rFifo/ram_reg_0_7_0_5/RAMB_D1/O
|
|
net (fo=1, routed) 1.318 0.357 u_Axi_CDC/rFifo/_zz_ram_port10__2[3]
|
|
SLICE_X19Y47 FDRE r u_Axi_CDC/rFifo/_zz_ram_port1_reg[3]/D
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock cpu_clk rise edge) 0.000 0.000 r
|
|
K21 0.000 0.000 r clk (IN)
|
|
net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1
|
|
K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O
|
|
net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll
|
|
PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0)
|
|
-8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0
|
|
net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll
|
|
BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout1_buf/O
|
|
net (fo=6484, routed) 2.132 -2.210 u_Axi_CDC/rFifo/cpu_clk
|
|
SLICE_X19Y47 FDRE r u_Axi_CDC/rFifo/_zz_ram_port1_reg[3]/C
|
|
|
|
Slack: inf
|
|
Source: u_Axi_CDC/rFifo/ram_reg_0_7_24_29/RAMB_D1/CLK
|
|
(rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Destination: u_Axi_CDC/rFifo/_zz_ram_port1_reg[27]/D
|
|
(rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns})
|
|
Path Group: (none)
|
|
Path Type: Hold (Min at Slow Process Corner)
|
|
Data Path Delay: 2.383ns (logic 1.062ns (44.564%) route 1.321ns (55.436%))
|
|
Logic Levels: 0
|
|
Clock Path Skew: -0.186ns (DCD - SCD - CPR)
|
|
Destination Clock Delay (DCD): -2.208ns
|
|
Source Clock Delay (SCD): -2.021ns
|
|
Clock Pessimism Removal (CPR): -0.000ns
|
|
Clock Uncertainty: 0.194ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Discrete Jitter (DJ): 0.130ns
|
|
Phase Error (PE): 0.120ns
|
|
Timing Exception: Asynchronous Clock Groups
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock sys_clk rise edge) 0.000 0.000 r
|
|
K21 0.000 0.000 r clk (IN)
|
|
net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1
|
|
K21 IBUF (Prop_ibuf_I_O) 1.393 1.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O
|
|
net (fo=1, routed) 1.181 2.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll
|
|
PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1)
|
|
-8.248 -5.674 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1
|
|
net (fo=1, routed) 1.755 -3.919 pll_clk.u_clk_pll/inst/sys_clk_clk_pll
|
|
BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 -3.828 r pll_clk.u_clk_pll/inst/clkout2_buf/O
|
|
net (fo=10004, routed) 1.807 -2.021 u_Axi_CDC/rFifo/ram_reg_0_7_24_29/WCLK
|
|
SLICE_X14Y77 RAMD32 r u_Axi_CDC/rFifo/ram_reg_0_7_24_29/RAMB_D1/CLK
|
|
------------------------------------------------------------------- -------------------
|
|
SLICE_X14Y77 RAMD32 (Prop_ramd32_CLK_O)
|
|
1.062 -0.959 r u_Axi_CDC/rFifo/ram_reg_0_7_24_29/RAMB_D1/O
|
|
net (fo=1, routed) 1.321 0.362 u_Axi_CDC/rFifo/_zz_ram_port10__2[27]
|
|
SLICE_X15Y48 FDRE r u_Axi_CDC/rFifo/_zz_ram_port1_reg[27]/D
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock cpu_clk rise edge) 0.000 0.000 r
|
|
K21 0.000 0.000 r clk (IN)
|
|
net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1
|
|
K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O
|
|
net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll
|
|
PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0)
|
|
-8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0
|
|
net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll
|
|
BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout1_buf/O
|
|
net (fo=6484, routed) 2.134 -2.208 u_Axi_CDC/rFifo/cpu_clk
|
|
SLICE_X15Y48 FDRE r u_Axi_CDC/rFifo/_zz_ram_port1_reg[27]/C
|
|
|
|
Slack: inf
|
|
Source: u_Axi_CDC/rFifo/ram_reg_0_7_6_11/RAMB_D1/CLK
|
|
(rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Destination: u_Axi_CDC/rFifo/_zz_ram_port1_reg[9]/D
|
|
(rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns})
|
|
Path Group: (none)
|
|
Path Type: Hold (Min at Slow Process Corner)
|
|
Data Path Delay: 2.393ns (logic 1.062ns (44.383%) route 1.331ns (55.617%))
|
|
Logic Levels: 0
|
|
Clock Path Skew: -0.188ns (DCD - SCD - CPR)
|
|
Destination Clock Delay (DCD): -2.210ns
|
|
Source Clock Delay (SCD): -2.021ns
|
|
Clock Pessimism Removal (CPR): -0.000ns
|
|
Clock Uncertainty: 0.194ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Discrete Jitter (DJ): 0.130ns
|
|
Phase Error (PE): 0.120ns
|
|
Timing Exception: Asynchronous Clock Groups
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock sys_clk rise edge) 0.000 0.000 r
|
|
K21 0.000 0.000 r clk (IN)
|
|
net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1
|
|
K21 IBUF (Prop_ibuf_I_O) 1.393 1.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O
|
|
net (fo=1, routed) 1.181 2.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll
|
|
PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1)
|
|
-8.248 -5.674 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1
|
|
net (fo=1, routed) 1.755 -3.919 pll_clk.u_clk_pll/inst/sys_clk_clk_pll
|
|
BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 -3.828 r pll_clk.u_clk_pll/inst/clkout2_buf/O
|
|
net (fo=10004, routed) 1.807 -2.021 u_Axi_CDC/rFifo/ram_reg_0_7_6_11/WCLK
|
|
SLICE_X18Y77 RAMD32 r u_Axi_CDC/rFifo/ram_reg_0_7_6_11/RAMB_D1/CLK
|
|
------------------------------------------------------------------- -------------------
|
|
SLICE_X18Y77 RAMD32 (Prop_ramd32_CLK_O)
|
|
1.062 -0.959 r u_Axi_CDC/rFifo/ram_reg_0_7_6_11/RAMB_D1/O
|
|
net (fo=1, routed) 1.331 0.372 u_Axi_CDC/rFifo/_zz_ram_port10__2[9]
|
|
SLICE_X19Y47 FDRE r u_Axi_CDC/rFifo/_zz_ram_port1_reg[9]/D
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock cpu_clk rise edge) 0.000 0.000 r
|
|
K21 0.000 0.000 r clk (IN)
|
|
net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1
|
|
K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O
|
|
net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll
|
|
PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0)
|
|
-8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0
|
|
net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll
|
|
BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout1_buf/O
|
|
net (fo=6484, routed) 2.132 -2.210 u_Axi_CDC/rFifo/cpu_clk
|
|
SLICE_X19Y47 FDRE r u_Axi_CDC/rFifo/_zz_ram_port1_reg[9]/C
|
|
|
|
Slack: inf
|
|
Source: u_Axi_CDC/rFifo/ram_reg_0_7_18_23/RAMB/CLK
|
|
(rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Destination: u_Axi_CDC/rFifo/_zz_ram_port1_reg[20]/D
|
|
(rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns})
|
|
Path Group: (none)
|
|
Path Type: Hold (Min at Slow Process Corner)
|
|
Data Path Delay: 2.414ns (logic 1.083ns (44.858%) route 1.331ns (55.142%))
|
|
Logic Levels: 0
|
|
Clock Path Skew: -0.187ns (DCD - SCD - CPR)
|
|
Destination Clock Delay (DCD): -2.210ns
|
|
Source Clock Delay (SCD): -2.022ns
|
|
Clock Pessimism Removal (CPR): -0.000ns
|
|
Clock Uncertainty: 0.194ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Discrete Jitter (DJ): 0.130ns
|
|
Phase Error (PE): 0.120ns
|
|
Timing Exception: Asynchronous Clock Groups
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock sys_clk rise edge) 0.000 0.000 r
|
|
K21 0.000 0.000 r clk (IN)
|
|
net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1
|
|
K21 IBUF (Prop_ibuf_I_O) 1.393 1.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O
|
|
net (fo=1, routed) 1.181 2.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll
|
|
PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1)
|
|
-8.248 -5.674 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1
|
|
net (fo=1, routed) 1.755 -3.919 pll_clk.u_clk_pll/inst/sys_clk_clk_pll
|
|
BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 -3.828 r pll_clk.u_clk_pll/inst/clkout2_buf/O
|
|
net (fo=10004, routed) 1.806 -2.022 u_Axi_CDC/rFifo/ram_reg_0_7_18_23/WCLK
|
|
SLICE_X16Y76 RAMD32 r u_Axi_CDC/rFifo/ram_reg_0_7_18_23/RAMB/CLK
|
|
------------------------------------------------------------------- -------------------
|
|
SLICE_X16Y76 RAMD32 (Prop_ramd32_CLK_O)
|
|
1.083 -0.939 r u_Axi_CDC/rFifo/ram_reg_0_7_18_23/RAMB/O
|
|
net (fo=1, routed) 1.331 0.392 u_Axi_CDC/rFifo/_zz_ram_port10__2[20]
|
|
SLICE_X19Y49 FDRE r u_Axi_CDC/rFifo/_zz_ram_port1_reg[20]/D
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock cpu_clk rise edge) 0.000 0.000 r
|
|
K21 0.000 0.000 r clk (IN)
|
|
net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1
|
|
K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O
|
|
net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll
|
|
PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0)
|
|
-8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0
|
|
net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll
|
|
BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout1_buf/O
|
|
net (fo=6484, routed) 2.132 -2.210 u_Axi_CDC/rFifo/cpu_clk
|
|
SLICE_X19Y49 FDRE r u_Axi_CDC/rFifo/_zz_ram_port1_reg[20]/C
|
|
|
|
Slack: inf
|
|
Source: u_Axi_CDC/rFifo/ram_reg_0_7_12_17/RAMB_D1/CLK
|
|
(rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Destination: u_Axi_CDC/rFifo/_zz_ram_port1_reg[15]/D
|
|
(rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns})
|
|
Path Group: (none)
|
|
Path Type: Hold (Min at Slow Process Corner)
|
|
Data Path Delay: 2.434ns (logic 1.062ns (43.637%) route 1.372ns (56.363%))
|
|
Logic Levels: 0
|
|
Clock Path Skew: -0.185ns (DCD - SCD - CPR)
|
|
Destination Clock Delay (DCD): -2.210ns
|
|
Source Clock Delay (SCD): -2.024ns
|
|
Clock Pessimism Removal (CPR): -0.000ns
|
|
Clock Uncertainty: 0.194ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Discrete Jitter (DJ): 0.130ns
|
|
Phase Error (PE): 0.120ns
|
|
Timing Exception: Asynchronous Clock Groups
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock sys_clk rise edge) 0.000 0.000 r
|
|
K21 0.000 0.000 r clk (IN)
|
|
net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1
|
|
K21 IBUF (Prop_ibuf_I_O) 1.393 1.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O
|
|
net (fo=1, routed) 1.181 2.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll
|
|
PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1)
|
|
-8.248 -5.674 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1
|
|
net (fo=1, routed) 1.755 -3.919 pll_clk.u_clk_pll/inst/sys_clk_clk_pll
|
|
BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 -3.828 r pll_clk.u_clk_pll/inst/clkout2_buf/O
|
|
net (fo=10004, routed) 1.804 -2.024 u_Axi_CDC/rFifo/ram_reg_0_7_12_17/WCLK
|
|
SLICE_X18Y75 RAMD32 r u_Axi_CDC/rFifo/ram_reg_0_7_12_17/RAMB_D1/CLK
|
|
------------------------------------------------------------------- -------------------
|
|
SLICE_X18Y75 RAMD32 (Prop_ramd32_CLK_O)
|
|
1.062 -0.962 r u_Axi_CDC/rFifo/ram_reg_0_7_12_17/RAMB_D1/O
|
|
net (fo=1, routed) 1.372 0.409 u_Axi_CDC/rFifo/_zz_ram_port10__2[15]
|
|
SLICE_X19Y49 FDRE r u_Axi_CDC/rFifo/_zz_ram_port1_reg[15]/D
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock cpu_clk rise edge) 0.000 0.000 r
|
|
K21 0.000 0.000 r clk (IN)
|
|
net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1
|
|
K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O
|
|
net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll
|
|
PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0)
|
|
-8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0
|
|
net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll
|
|
BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout1_buf/O
|
|
net (fo=6484, routed) 2.132 -2.210 u_Axi_CDC/rFifo/cpu_clk
|
|
SLICE_X19Y49 FDRE r u_Axi_CDC/rFifo/_zz_ram_port1_reg[15]/C
|
|
|
|
Slack: inf
|
|
Source: u_Axi_CDC/rFifo/ram_reg_0_7_18_23/RAMC/CLK
|
|
(rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Destination: u_Axi_CDC/rFifo/_zz_ram_port1_reg[22]/D
|
|
(rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns})
|
|
Path Group: (none)
|
|
Path Type: Hold (Min at Slow Process Corner)
|
|
Data Path Delay: 2.441ns (logic 1.078ns (44.167%) route 1.363ns (55.833%))
|
|
Logic Levels: 0
|
|
Clock Path Skew: -0.187ns (DCD - SCD - CPR)
|
|
Destination Clock Delay (DCD): -2.210ns
|
|
Source Clock Delay (SCD): -2.022ns
|
|
Clock Pessimism Removal (CPR): -0.000ns
|
|
Clock Uncertainty: 0.194ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Discrete Jitter (DJ): 0.130ns
|
|
Phase Error (PE): 0.120ns
|
|
Timing Exception: Asynchronous Clock Groups
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock sys_clk rise edge) 0.000 0.000 r
|
|
K21 0.000 0.000 r clk (IN)
|
|
net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1
|
|
K21 IBUF (Prop_ibuf_I_O) 1.393 1.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O
|
|
net (fo=1, routed) 1.181 2.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll
|
|
PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1)
|
|
-8.248 -5.674 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1
|
|
net (fo=1, routed) 1.755 -3.919 pll_clk.u_clk_pll/inst/sys_clk_clk_pll
|
|
BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 -3.828 r pll_clk.u_clk_pll/inst/clkout2_buf/O
|
|
net (fo=10004, routed) 1.806 -2.022 u_Axi_CDC/rFifo/ram_reg_0_7_18_23/WCLK
|
|
SLICE_X16Y76 RAMD32 r u_Axi_CDC/rFifo/ram_reg_0_7_18_23/RAMC/CLK
|
|
------------------------------------------------------------------- -------------------
|
|
SLICE_X16Y76 RAMD32 (Prop_ramd32_CLK_O)
|
|
1.078 -0.944 r u_Axi_CDC/rFifo/ram_reg_0_7_18_23/RAMC/O
|
|
net (fo=1, routed) 1.363 0.418 u_Axi_CDC/rFifo/_zz_ram_port10__2[22]
|
|
SLICE_X19Y49 FDRE r u_Axi_CDC/rFifo/_zz_ram_port1_reg[22]/D
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock cpu_clk rise edge) 0.000 0.000 r
|
|
K21 0.000 0.000 r clk (IN)
|
|
net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1
|
|
K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O
|
|
net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll
|
|
PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0)
|
|
-8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0
|
|
net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll
|
|
BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout1_buf/O
|
|
net (fo=6484, routed) 2.132 -2.210 u_Axi_CDC/rFifo/cpu_clk
|
|
SLICE_X19Y49 FDRE r u_Axi_CDC/rFifo/_zz_ram_port1_reg[22]/C
|
|
|
|
Slack: inf
|
|
Source: u_Axi_CDC/rFifo/ram_reg_0_7_6_11/RAMB/CLK
|
|
(rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Destination: u_Axi_CDC/rFifo/_zz_ram_port1_reg[8]/D
|
|
(rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns})
|
|
Path Group: (none)
|
|
Path Type: Hold (Min at Slow Process Corner)
|
|
Data Path Delay: 2.491ns (logic 1.083ns (43.479%) route 1.408ns (56.521%))
|
|
Logic Levels: 0
|
|
Clock Path Skew: -0.190ns (DCD - SCD - CPR)
|
|
Destination Clock Delay (DCD): -2.212ns
|
|
Source Clock Delay (SCD): -2.021ns
|
|
Clock Pessimism Removal (CPR): -0.000ns
|
|
Clock Uncertainty: 0.194ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Discrete Jitter (DJ): 0.130ns
|
|
Phase Error (PE): 0.120ns
|
|
Timing Exception: Asynchronous Clock Groups
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock sys_clk rise edge) 0.000 0.000 r
|
|
K21 0.000 0.000 r clk (IN)
|
|
net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1
|
|
K21 IBUF (Prop_ibuf_I_O) 1.393 1.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O
|
|
net (fo=1, routed) 1.181 2.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll
|
|
PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1)
|
|
-8.248 -5.674 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1
|
|
net (fo=1, routed) 1.755 -3.919 pll_clk.u_clk_pll/inst/sys_clk_clk_pll
|
|
BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 -3.828 r pll_clk.u_clk_pll/inst/clkout2_buf/O
|
|
net (fo=10004, routed) 1.807 -2.021 u_Axi_CDC/rFifo/ram_reg_0_7_6_11/WCLK
|
|
SLICE_X18Y77 RAMD32 r u_Axi_CDC/rFifo/ram_reg_0_7_6_11/RAMB/CLK
|
|
------------------------------------------------------------------- -------------------
|
|
SLICE_X18Y77 RAMD32 (Prop_ramd32_CLK_O)
|
|
1.083 -0.938 r u_Axi_CDC/rFifo/ram_reg_0_7_6_11/RAMB/O
|
|
net (fo=1, routed) 1.408 0.470 u_Axi_CDC/rFifo/_zz_ram_port10__2[8]
|
|
SLICE_X19Y42 FDRE r u_Axi_CDC/rFifo/_zz_ram_port1_reg[8]/D
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock cpu_clk rise edge) 0.000 0.000 r
|
|
K21 0.000 0.000 r clk (IN)
|
|
net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1
|
|
K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O
|
|
net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll
|
|
PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0)
|
|
-8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0
|
|
net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll
|
|
BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout1_buf/O
|
|
net (fo=6484, routed) 2.130 -2.212 u_Axi_CDC/rFifo/cpu_clk
|
|
SLICE_X19Y42 FDRE r u_Axi_CDC/rFifo/_zz_ram_port1_reg[8]/C
|
|
|
|
Slack: inf
|
|
Source: u_Axi_CDC/rFifo/ram_reg_0_7_24_29/RAMA_D1/CLK
|
|
(rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Destination: u_Axi_CDC/rFifo/_zz_ram_port1_reg[25]/D
|
|
(rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns})
|
|
Path Group: (none)
|
|
Path Type: Hold (Min at Slow Process Corner)
|
|
Data Path Delay: 2.529ns (logic 1.056ns (41.755%) route 1.473ns (58.245%))
|
|
Logic Levels: 0
|
|
Clock Path Skew: -0.188ns (DCD - SCD - CPR)
|
|
Destination Clock Delay (DCD): -2.210ns
|
|
Source Clock Delay (SCD): -2.021ns
|
|
Clock Pessimism Removal (CPR): -0.000ns
|
|
Clock Uncertainty: 0.194ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Discrete Jitter (DJ): 0.130ns
|
|
Phase Error (PE): 0.120ns
|
|
Timing Exception: Asynchronous Clock Groups
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock sys_clk rise edge) 0.000 0.000 r
|
|
K21 0.000 0.000 r clk (IN)
|
|
net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1
|
|
K21 IBUF (Prop_ibuf_I_O) 1.393 1.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O
|
|
net (fo=1, routed) 1.181 2.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll
|
|
PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1)
|
|
-8.248 -5.674 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1
|
|
net (fo=1, routed) 1.755 -3.919 pll_clk.u_clk_pll/inst/sys_clk_clk_pll
|
|
BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 -3.828 r pll_clk.u_clk_pll/inst/clkout2_buf/O
|
|
net (fo=10004, routed) 1.807 -2.021 u_Axi_CDC/rFifo/ram_reg_0_7_24_29/WCLK
|
|
SLICE_X14Y77 RAMD32 r u_Axi_CDC/rFifo/ram_reg_0_7_24_29/RAMA_D1/CLK
|
|
------------------------------------------------------------------- -------------------
|
|
SLICE_X14Y77 RAMD32 (Prop_ramd32_CLK_O)
|
|
1.056 -0.965 r u_Axi_CDC/rFifo/ram_reg_0_7_24_29/RAMA_D1/O
|
|
net (fo=1, routed) 1.473 0.508 u_Axi_CDC/rFifo/_zz_ram_port10__2[25]
|
|
SLICE_X15Y41 FDRE r u_Axi_CDC/rFifo/_zz_ram_port1_reg[25]/D
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock cpu_clk rise edge) 0.000 0.000 r
|
|
K21 0.000 0.000 r clk (IN)
|
|
net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1
|
|
K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O
|
|
net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll
|
|
PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0)
|
|
-8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0
|
|
net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll
|
|
BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout1_buf/O
|
|
net (fo=6484, routed) 2.132 -2.210 u_Axi_CDC/rFifo/cpu_clk
|
|
SLICE_X15Y41 FDRE r u_Axi_CDC/rFifo/_zz_ram_port1_reg[25]/C
|
|
|
|
Slack: inf
|
|
Source: u_Axi_CDC/rFifo/ram_reg_0_7_6_11/RAMA/CLK
|
|
(rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Destination: u_Axi_CDC/rFifo/_zz_ram_port1_reg[6]/D
|
|
(rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns})
|
|
Path Group: (none)
|
|
Path Type: Hold (Min at Slow Process Corner)
|
|
Data Path Delay: 2.538ns (logic 1.084ns (42.711%) route 1.454ns (57.289%))
|
|
Logic Levels: 0
|
|
Clock Path Skew: -0.188ns (DCD - SCD - CPR)
|
|
Destination Clock Delay (DCD): -2.210ns
|
|
Source Clock Delay (SCD): -2.021ns
|
|
Clock Pessimism Removal (CPR): -0.000ns
|
|
Clock Uncertainty: 0.194ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Discrete Jitter (DJ): 0.130ns
|
|
Phase Error (PE): 0.120ns
|
|
Timing Exception: Asynchronous Clock Groups
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock sys_clk rise edge) 0.000 0.000 r
|
|
K21 0.000 0.000 r clk (IN)
|
|
net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1
|
|
K21 IBUF (Prop_ibuf_I_O) 1.393 1.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O
|
|
net (fo=1, routed) 1.181 2.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll
|
|
PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1)
|
|
-8.248 -5.674 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1
|
|
net (fo=1, routed) 1.755 -3.919 pll_clk.u_clk_pll/inst/sys_clk_clk_pll
|
|
BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 -3.828 r pll_clk.u_clk_pll/inst/clkout2_buf/O
|
|
net (fo=10004, routed) 1.807 -2.021 u_Axi_CDC/rFifo/ram_reg_0_7_6_11/WCLK
|
|
SLICE_X18Y77 RAMD32 r u_Axi_CDC/rFifo/ram_reg_0_7_6_11/RAMA/CLK
|
|
------------------------------------------------------------------- -------------------
|
|
SLICE_X18Y77 RAMD32 (Prop_ramd32_CLK_O)
|
|
1.084 -0.937 r u_Axi_CDC/rFifo/ram_reg_0_7_6_11/RAMA/O
|
|
net (fo=1, routed) 1.454 0.517 u_Axi_CDC/rFifo/_zz_ram_port10__2[6]
|
|
SLICE_X19Y47 FDRE r u_Axi_CDC/rFifo/_zz_ram_port1_reg[6]/D
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock cpu_clk rise edge) 0.000 0.000 r
|
|
K21 0.000 0.000 r clk (IN)
|
|
net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1
|
|
K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O
|
|
net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll
|
|
PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0)
|
|
-8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0
|
|
net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll
|
|
BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout1_buf/O
|
|
net (fo=6484, routed) 2.132 -2.210 u_Axi_CDC/rFifo/cpu_clk
|
|
SLICE_X19Y47 FDRE r u_Axi_CDC/rFifo/_zz_ram_port1_reg[6]/C
|
|
|
|
Slack: inf
|
|
Source: u_Axi_CDC/rFifo/ram_reg_0_7_6_11/RAMC/CLK
|
|
(rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Destination: u_Axi_CDC/rFifo/_zz_ram_port1_reg[10]/D
|
|
(rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns})
|
|
Path Group: (none)
|
|
Path Type: Hold (Min at Slow Process Corner)
|
|
Data Path Delay: 2.565ns (logic 1.078ns (42.030%) route 1.487ns (57.970%))
|
|
Logic Levels: 0
|
|
Clock Path Skew: -0.190ns (DCD - SCD - CPR)
|
|
Destination Clock Delay (DCD): -2.212ns
|
|
Source Clock Delay (SCD): -2.021ns
|
|
Clock Pessimism Removal (CPR): -0.000ns
|
|
Clock Uncertainty: 0.194ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Discrete Jitter (DJ): 0.130ns
|
|
Phase Error (PE): 0.120ns
|
|
Timing Exception: Asynchronous Clock Groups
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock sys_clk rise edge) 0.000 0.000 r
|
|
K21 0.000 0.000 r clk (IN)
|
|
net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1
|
|
K21 IBUF (Prop_ibuf_I_O) 1.393 1.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O
|
|
net (fo=1, routed) 1.181 2.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll
|
|
PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1)
|
|
-8.248 -5.674 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1
|
|
net (fo=1, routed) 1.755 -3.919 pll_clk.u_clk_pll/inst/sys_clk_clk_pll
|
|
BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 -3.828 r pll_clk.u_clk_pll/inst/clkout2_buf/O
|
|
net (fo=10004, routed) 1.807 -2.021 u_Axi_CDC/rFifo/ram_reg_0_7_6_11/WCLK
|
|
SLICE_X18Y77 RAMD32 r u_Axi_CDC/rFifo/ram_reg_0_7_6_11/RAMC/CLK
|
|
------------------------------------------------------------------- -------------------
|
|
SLICE_X18Y77 RAMD32 (Prop_ramd32_CLK_O)
|
|
1.078 -0.943 r u_Axi_CDC/rFifo/ram_reg_0_7_6_11/RAMC/O
|
|
net (fo=1, routed) 1.487 0.544 u_Axi_CDC/rFifo/_zz_ram_port10__2[10]
|
|
SLICE_X19Y42 FDRE r u_Axi_CDC/rFifo/_zz_ram_port1_reg[10]/D
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock cpu_clk rise edge) 0.000 0.000 r
|
|
K21 0.000 0.000 r clk (IN)
|
|
net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1
|
|
K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O
|
|
net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll
|
|
PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0)
|
|
-8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0
|
|
net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll
|
|
BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout1_buf/O
|
|
net (fo=6484, routed) 2.130 -2.212 u_Axi_CDC/rFifo/cpu_clk
|
|
SLICE_X19Y42 FDRE r u_Axi_CDC/rFifo/_zz_ram_port1_reg[10]/C
|
|
|
|
Slack: inf
|
|
Source: u_Axi_CDC/rFifo/ram_reg_0_7_0_5/RAMA/CLK
|
|
(rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Destination: u_Axi_CDC/rFifo/_zz_ram_port1_reg[0]/D
|
|
(rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns})
|
|
Path Group: (none)
|
|
Path Type: Hold (Min at Slow Process Corner)
|
|
Data Path Delay: 2.570ns (logic 1.084ns (42.178%) route 1.486ns (57.822%))
|
|
Logic Levels: 0
|
|
Clock Path Skew: -0.189ns (DCD - SCD - CPR)
|
|
Destination Clock Delay (DCD): -2.212ns
|
|
Source Clock Delay (SCD): -2.022ns
|
|
Clock Pessimism Removal (CPR): -0.000ns
|
|
Clock Uncertainty: 0.194ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Discrete Jitter (DJ): 0.130ns
|
|
Phase Error (PE): 0.120ns
|
|
Timing Exception: Asynchronous Clock Groups
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock sys_clk rise edge) 0.000 0.000 r
|
|
K21 0.000 0.000 r clk (IN)
|
|
net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1
|
|
K21 IBUF (Prop_ibuf_I_O) 1.393 1.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O
|
|
net (fo=1, routed) 1.181 2.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll
|
|
PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1)
|
|
-8.248 -5.674 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1
|
|
net (fo=1, routed) 1.755 -3.919 pll_clk.u_clk_pll/inst/sys_clk_clk_pll
|
|
BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 -3.828 r pll_clk.u_clk_pll/inst/clkout2_buf/O
|
|
net (fo=10004, routed) 1.806 -2.022 u_Axi_CDC/rFifo/ram_reg_0_7_0_5/WCLK
|
|
SLICE_X18Y76 RAMD32 r u_Axi_CDC/rFifo/ram_reg_0_7_0_5/RAMA/CLK
|
|
------------------------------------------------------------------- -------------------
|
|
SLICE_X18Y76 RAMD32 (Prop_ramd32_CLK_O)
|
|
1.084 -0.938 r u_Axi_CDC/rFifo/ram_reg_0_7_0_5/RAMA/O
|
|
net (fo=1, routed) 1.486 0.548 u_Axi_CDC/rFifo/_zz_ram_port10__2[0]
|
|
SLICE_X19Y42 FDRE r u_Axi_CDC/rFifo/_zz_ram_port1_reg[0]/D
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock cpu_clk rise edge) 0.000 0.000 r
|
|
K21 0.000 0.000 r clk (IN)
|
|
net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1
|
|
K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O
|
|
net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll
|
|
PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0)
|
|
-8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0
|
|
net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll
|
|
BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout1_buf/O
|
|
net (fo=6484, routed) 2.130 -2.212 u_Axi_CDC/rFifo/cpu_clk
|
|
SLICE_X19Y42 FDRE r u_Axi_CDC/rFifo/_zz_ram_port1_reg[0]/C
|
|
|
|
Slack: inf
|
|
Source: u_Axi_CDC/rFifo/ram_reg_0_7_18_23/RAMC_D1/CLK
|
|
(rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Destination: u_Axi_CDC/rFifo/_zz_ram_port1_reg[23]/D
|
|
(rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns})
|
|
Path Group: (none)
|
|
Path Type: Hold (Min at Fast Process Corner)
|
|
Data Path Delay: 1.131ns (logic 0.386ns (34.129%) route 0.745ns (65.871%))
|
|
Logic Levels: 0
|
|
Clock Path Skew: 0.317ns (DCD - SCD - CPR)
|
|
Destination Clock Delay (DCD): -0.262ns
|
|
Source Clock Delay (SCD): -0.579ns
|
|
Clock Pessimism Removal (CPR): -0.000ns
|
|
Clock Uncertainty: 0.194ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Discrete Jitter (DJ): 0.130ns
|
|
Phase Error (PE): 0.120ns
|
|
Timing Exception: Asynchronous Clock Groups
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock sys_clk rise edge) 0.000 0.000 r
|
|
K21 0.000 0.000 r clk (IN)
|
|
net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1
|
|
K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O
|
|
net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll
|
|
PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1)
|
|
-2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1
|
|
net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll
|
|
BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O
|
|
net (fo=10004, routed) 0.683 -0.579 u_Axi_CDC/rFifo/ram_reg_0_7_18_23/WCLK
|
|
SLICE_X16Y76 RAMD32 r u_Axi_CDC/rFifo/ram_reg_0_7_18_23/RAMC_D1/CLK
|
|
------------------------------------------------------------------- -------------------
|
|
SLICE_X16Y76 RAMD32 (Prop_ramd32_CLK_O)
|
|
0.386 -0.193 r u_Axi_CDC/rFifo/ram_reg_0_7_18_23/RAMC_D1/O
|
|
net (fo=1, routed) 0.745 0.552 u_Axi_CDC/rFifo/_zz_ram_port10__2[23]
|
|
SLICE_X17Y44 FDRE r u_Axi_CDC/rFifo/_zz_ram_port1_reg[23]/D
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock cpu_clk rise edge) 0.000 0.000 r
|
|
K21 0.000 0.000 r clk (IN)
|
|
net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1
|
|
K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O
|
|
net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll
|
|
PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0)
|
|
-2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0
|
|
net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll
|
|
BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout1_buf/O
|
|
net (fo=6484, routed) 1.046 -0.262 u_Axi_CDC/rFifo/cpu_clk
|
|
SLICE_X17Y44 FDRE r u_Axi_CDC/rFifo/_zz_ram_port1_reg[23]/C
|
|
|
|
Slack: inf
|
|
Source: u_Axi_CDC/rFifo/ram_reg_0_7_6_11/RAMC_D1/CLK
|
|
(rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Destination: u_Axi_CDC/rFifo/_zz_ram_port1_reg[11]/D
|
|
(rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns})
|
|
Path Group: (none)
|
|
Path Type: Hold (Min at Fast Process Corner)
|
|
Data Path Delay: 1.175ns (logic 0.386ns (32.837%) route 0.789ns (67.163%))
|
|
Logic Levels: 0
|
|
Clock Path Skew: 0.314ns (DCD - SCD - CPR)
|
|
Destination Clock Delay (DCD): -0.263ns
|
|
Source Clock Delay (SCD): -0.577ns
|
|
Clock Pessimism Removal (CPR): -0.000ns
|
|
Clock Uncertainty: 0.194ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Discrete Jitter (DJ): 0.130ns
|
|
Phase Error (PE): 0.120ns
|
|
Timing Exception: Asynchronous Clock Groups
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock sys_clk rise edge) 0.000 0.000 r
|
|
K21 0.000 0.000 r clk (IN)
|
|
net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1
|
|
K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O
|
|
net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll
|
|
PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1)
|
|
-2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1
|
|
net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll
|
|
BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O
|
|
net (fo=10004, routed) 0.685 -0.577 u_Axi_CDC/rFifo/ram_reg_0_7_6_11/WCLK
|
|
SLICE_X18Y77 RAMD32 r u_Axi_CDC/rFifo/ram_reg_0_7_6_11/RAMC_D1/CLK
|
|
------------------------------------------------------------------- -------------------
|
|
SLICE_X18Y77 RAMD32 (Prop_ramd32_CLK_O)
|
|
0.386 -0.191 r u_Axi_CDC/rFifo/ram_reg_0_7_6_11/RAMC_D1/O
|
|
net (fo=1, routed) 0.789 0.598 u_Axi_CDC/rFifo/_zz_ram_port10__2[11]
|
|
SLICE_X19Y42 FDRE r u_Axi_CDC/rFifo/_zz_ram_port1_reg[11]/D
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock cpu_clk rise edge) 0.000 0.000 r
|
|
K21 0.000 0.000 r clk (IN)
|
|
net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1
|
|
K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O
|
|
net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll
|
|
PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0)
|
|
-2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0
|
|
net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll
|
|
BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout1_buf/O
|
|
net (fo=6484, routed) 1.045 -0.263 u_Axi_CDC/rFifo/cpu_clk
|
|
SLICE_X19Y42 FDRE r u_Axi_CDC/rFifo/_zz_ram_port1_reg[11]/C
|
|
|
|
Slack: inf
|
|
Source: u_Axi_CDC/rFifo/ram_reg_0_7_24_29/RAMB/CLK
|
|
(rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Destination: u_Axi_CDC/rFifo/_zz_ram_port1_reg[26]/D
|
|
(rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns})
|
|
Path Group: (none)
|
|
Path Type: Hold (Min at Fast Process Corner)
|
|
Data Path Delay: 1.178ns (logic 0.394ns (33.456%) route 0.784ns (66.544%))
|
|
Logic Levels: 0
|
|
Clock Path Skew: 0.315ns (DCD - SCD - CPR)
|
|
Destination Clock Delay (DCD): -0.262ns
|
|
Source Clock Delay (SCD): -0.577ns
|
|
Clock Pessimism Removal (CPR): -0.000ns
|
|
Clock Uncertainty: 0.194ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Discrete Jitter (DJ): 0.130ns
|
|
Phase Error (PE): 0.120ns
|
|
Timing Exception: Asynchronous Clock Groups
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock sys_clk rise edge) 0.000 0.000 r
|
|
K21 0.000 0.000 r clk (IN)
|
|
net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1
|
|
K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O
|
|
net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll
|
|
PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1)
|
|
-2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1
|
|
net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll
|
|
BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O
|
|
net (fo=10004, routed) 0.685 -0.577 u_Axi_CDC/rFifo/ram_reg_0_7_24_29/WCLK
|
|
SLICE_X14Y77 RAMD32 r u_Axi_CDC/rFifo/ram_reg_0_7_24_29/RAMB/CLK
|
|
------------------------------------------------------------------- -------------------
|
|
SLICE_X14Y77 RAMD32 (Prop_ramd32_CLK_O)
|
|
0.394 -0.183 r u_Axi_CDC/rFifo/ram_reg_0_7_24_29/RAMB/O
|
|
net (fo=1, routed) 0.784 0.600 u_Axi_CDC/rFifo/_zz_ram_port10__2[26]
|
|
SLICE_X15Y41 FDRE r u_Axi_CDC/rFifo/_zz_ram_port1_reg[26]/D
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock cpu_clk rise edge) 0.000 0.000 r
|
|
K21 0.000 0.000 r clk (IN)
|
|
net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1
|
|
K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O
|
|
net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll
|
|
PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0)
|
|
-2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0
|
|
net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll
|
|
BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout1_buf/O
|
|
net (fo=6484, routed) 1.046 -0.262 u_Axi_CDC/rFifo/cpu_clk
|
|
SLICE_X15Y41 FDRE r u_Axi_CDC/rFifo/_zz_ram_port1_reg[26]/C
|
|
|
|
Slack: inf
|
|
Source: u_Axi_CDC/rFifo/ram_reg_0_7_12_17/RAMC_D1/CLK
|
|
(rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Destination: u_Axi_CDC/rFifo/_zz_ram_port1_reg[17]/D
|
|
(rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns})
|
|
Path Group: (none)
|
|
Path Type: Hold (Min at Fast Process Corner)
|
|
Data Path Delay: 1.182ns (logic 0.386ns (32.666%) route 0.796ns (67.334%))
|
|
Logic Levels: 0
|
|
Clock Path Skew: 0.317ns (DCD - SCD - CPR)
|
|
Destination Clock Delay (DCD): -0.263ns
|
|
Source Clock Delay (SCD): -0.580ns
|
|
Clock Pessimism Removal (CPR): -0.000ns
|
|
Clock Uncertainty: 0.194ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Discrete Jitter (DJ): 0.130ns
|
|
Phase Error (PE): 0.120ns
|
|
Timing Exception: Asynchronous Clock Groups
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock sys_clk rise edge) 0.000 0.000 r
|
|
K21 0.000 0.000 r clk (IN)
|
|
net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1
|
|
K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O
|
|
net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll
|
|
PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1)
|
|
-2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1
|
|
net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll
|
|
BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O
|
|
net (fo=10004, routed) 0.682 -0.580 u_Axi_CDC/rFifo/ram_reg_0_7_12_17/WCLK
|
|
SLICE_X18Y75 RAMD32 r u_Axi_CDC/rFifo/ram_reg_0_7_12_17/RAMC_D1/CLK
|
|
------------------------------------------------------------------- -------------------
|
|
SLICE_X18Y75 RAMD32 (Prop_ramd32_CLK_O)
|
|
0.386 -0.194 r u_Axi_CDC/rFifo/ram_reg_0_7_12_17/RAMC_D1/O
|
|
net (fo=1, routed) 0.796 0.601 u_Axi_CDC/rFifo/_zz_ram_port10__2[17]
|
|
SLICE_X19Y42 FDRE r u_Axi_CDC/rFifo/_zz_ram_port1_reg[17]/D
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock cpu_clk rise edge) 0.000 0.000 r
|
|
K21 0.000 0.000 r clk (IN)
|
|
net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1
|
|
K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O
|
|
net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll
|
|
PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0)
|
|
-2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0
|
|
net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll
|
|
BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout1_buf/O
|
|
net (fo=6484, routed) 1.045 -0.263 u_Axi_CDC/rFifo/cpu_clk
|
|
SLICE_X19Y42 FDRE r u_Axi_CDC/rFifo/_zz_ram_port1_reg[17]/C
|
|
|
|
|
|
|
|
|
|
|
|
--------------------------------------------------------------------------------------
|
|
Path Group: (none)
|
|
From Clock: cpu_clk
|
|
To Clock: sys_clk
|
|
|
|
Max Delay 0 Endpoints
|
|
Min Delay 162 Endpoints
|
|
--------------------------------------------------------------------------------------
|
|
|
|
|
|
Min Delay Paths
|
|
--------------------------------------------------------------------------------------
|
|
Slack: inf
|
|
Source: u_Axi_CDC/bFifo/popCC_ptrToPush_reg[2]/C
|
|
(rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns})
|
|
Destination: u_Axi_CDC/bFifo/popToPushGray_buffercc/buffers_0_reg[2]/D
|
|
(rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Path Group: (none)
|
|
Path Type: Hold (Min at Slow Process Corner)
|
|
Data Path Delay: 0.597ns (logic 0.337ns (56.456%) route 0.260ns (43.544%))
|
|
Logic Levels: 0
|
|
Clock Path Skew: -0.388ns (DCD - SCD - CPR)
|
|
Destination Clock Delay (DCD): -2.397ns
|
|
Source Clock Delay (SCD): -2.008ns
|
|
Clock Pessimism Removal (CPR): -0.000ns
|
|
Clock Uncertainty: 0.194ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Discrete Jitter (DJ): 0.130ns
|
|
Phase Error (PE): 0.120ns
|
|
Timing Exception: Asynchronous Clock Groups
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock cpu_clk rise edge) 0.000 0.000 r
|
|
K21 0.000 0.000 r clk (IN)
|
|
net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1
|
|
K21 IBUF (Prop_ibuf_I_O) 1.393 1.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O
|
|
net (fo=1, routed) 1.181 2.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll
|
|
PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0)
|
|
-8.248 -5.674 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0
|
|
net (fo=1, routed) 1.755 -3.919 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll
|
|
BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.091 -3.828 r pll_clk.u_clk_pll/inst/clkout1_buf/O
|
|
net (fo=6484, routed) 1.820 -2.008 u_Axi_CDC/bFifo/cpu_clk
|
|
SLICE_X17Y58 FDCE r u_Axi_CDC/bFifo/popCC_ptrToPush_reg[2]/C
|
|
------------------------------------------------------------------- -------------------
|
|
SLICE_X17Y58 FDCE (Prop_fdce_C_Q) 0.337 -1.671 r u_Axi_CDC/bFifo/popCC_ptrToPush_reg[2]/Q
|
|
net (fo=2, routed) 0.260 -1.411 u_Axi_CDC/bFifo/popToPushGray_buffercc/D[2]
|
|
SLICE_X17Y59 FDCE r u_Axi_CDC/bFifo/popToPushGray_buffercc/buffers_0_reg[2]/D
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock sys_clk rise edge) 0.000 0.000 r
|
|
K21 0.000 0.000 r clk (IN)
|
|
net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1
|
|
K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O
|
|
net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll
|
|
PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1)
|
|
-8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1
|
|
net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll
|
|
BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O
|
|
net (fo=10004, routed) 1.945 -2.397 u_Axi_CDC/bFifo/popToPushGray_buffercc/sys_clk
|
|
SLICE_X17Y59 FDCE r u_Axi_CDC/bFifo/popToPushGray_buffercc/buffers_0_reg[2]/C
|
|
|
|
Slack: inf
|
|
Source: u_Axi_CDC/arFifo/pushCC_pushPtrGray_reg[2]/C
|
|
(rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns})
|
|
Destination: u_Axi_CDC/arFifo/pushToPopGray_buffercc/buffers_0_reg[2]/D
|
|
(rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Path Group: (none)
|
|
Path Type: Hold (Min at Slow Process Corner)
|
|
Data Path Delay: 0.617ns (logic 0.337ns (54.608%) route 0.280ns (45.392%))
|
|
Logic Levels: 0
|
|
Clock Path Skew: -0.388ns (DCD - SCD - CPR)
|
|
Destination Clock Delay (DCD): -2.403ns
|
|
Source Clock Delay (SCD): -2.014ns
|
|
Clock Pessimism Removal (CPR): -0.000ns
|
|
Clock Uncertainty: 0.194ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Discrete Jitter (DJ): 0.130ns
|
|
Phase Error (PE): 0.120ns
|
|
Timing Exception: Asynchronous Clock Groups
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock cpu_clk rise edge) 0.000 0.000 r
|
|
K21 0.000 0.000 r clk (IN)
|
|
net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1
|
|
K21 IBUF (Prop_ibuf_I_O) 1.393 1.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O
|
|
net (fo=1, routed) 1.181 2.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll
|
|
PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0)
|
|
-8.248 -5.674 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0
|
|
net (fo=1, routed) 1.755 -3.919 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll
|
|
BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.091 -3.828 r pll_clk.u_clk_pll/inst/clkout1_buf/O
|
|
net (fo=6484, routed) 1.814 -2.014 u_Axi_CDC/arFifo/cpu_clk
|
|
SLICE_X17Y66 FDCE r u_Axi_CDC/arFifo/pushCC_pushPtrGray_reg[2]/C
|
|
------------------------------------------------------------------- -------------------
|
|
SLICE_X17Y66 FDCE (Prop_fdce_C_Q) 0.337 -1.677 r u_Axi_CDC/arFifo/pushCC_pushPtrGray_reg[2]/Q
|
|
net (fo=4, routed) 0.280 -1.397 u_Axi_CDC/arFifo/pushToPopGray_buffercc/buffers_0_reg[2]_0
|
|
SLICE_X15Y66 FDCE r u_Axi_CDC/arFifo/pushToPopGray_buffercc/buffers_0_reg[2]/D
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock sys_clk rise edge) 0.000 0.000 r
|
|
K21 0.000 0.000 r clk (IN)
|
|
net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1
|
|
K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O
|
|
net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll
|
|
PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1)
|
|
-8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1
|
|
net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll
|
|
BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O
|
|
net (fo=10004, routed) 1.939 -2.403 u_Axi_CDC/arFifo/pushToPopGray_buffercc/sys_clk
|
|
SLICE_X15Y66 FDCE r u_Axi_CDC/arFifo/pushToPopGray_buffercc/buffers_0_reg[2]/C
|
|
|
|
Slack: inf
|
|
Source: u_Axi_CDC/arFifo/pushCC_pushPtrGray_reg[0]/C
|
|
(rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns})
|
|
Destination: u_Axi_CDC/arFifo/pushToPopGray_buffercc/buffers_0_reg[0]/D
|
|
(rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Path Group: (none)
|
|
Path Type: Hold (Min at Slow Process Corner)
|
|
Data Path Delay: 0.634ns (logic 0.367ns (57.910%) route 0.267ns (42.090%))
|
|
Logic Levels: 0
|
|
Clock Path Skew: -0.388ns (DCD - SCD - CPR)
|
|
Destination Clock Delay (DCD): -2.403ns
|
|
Source Clock Delay (SCD): -2.014ns
|
|
Clock Pessimism Removal (CPR): -0.000ns
|
|
Clock Uncertainty: 0.194ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Discrete Jitter (DJ): 0.130ns
|
|
Phase Error (PE): 0.120ns
|
|
Timing Exception: Asynchronous Clock Groups
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock cpu_clk rise edge) 0.000 0.000 r
|
|
K21 0.000 0.000 r clk (IN)
|
|
net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1
|
|
K21 IBUF (Prop_ibuf_I_O) 1.393 1.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O
|
|
net (fo=1, routed) 1.181 2.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll
|
|
PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0)
|
|
-8.248 -5.674 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0
|
|
net (fo=1, routed) 1.755 -3.919 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll
|
|
BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.091 -3.828 r pll_clk.u_clk_pll/inst/clkout1_buf/O
|
|
net (fo=6484, routed) 1.814 -2.014 u_Axi_CDC/arFifo/cpu_clk
|
|
SLICE_X17Y66 FDCE r u_Axi_CDC/arFifo/pushCC_pushPtrGray_reg[0]/C
|
|
------------------------------------------------------------------- -------------------
|
|
SLICE_X17Y66 FDCE (Prop_fdce_C_Q) 0.367 -1.647 r u_Axi_CDC/arFifo/pushCC_pushPtrGray_reg[0]/Q
|
|
net (fo=2, routed) 0.267 -1.381 u_Axi_CDC/arFifo/pushToPopGray_buffercc/Q[0]
|
|
SLICE_X15Y66 FDCE r u_Axi_CDC/arFifo/pushToPopGray_buffercc/buffers_0_reg[0]/D
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock sys_clk rise edge) 0.000 0.000 r
|
|
K21 0.000 0.000 r clk (IN)
|
|
net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1
|
|
K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O
|
|
net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll
|
|
PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1)
|
|
-8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1
|
|
net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll
|
|
BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O
|
|
net (fo=10004, routed) 1.939 -2.403 u_Axi_CDC/arFifo/pushToPopGray_buffercc/sys_clk
|
|
SLICE_X15Y66 FDCE r u_Axi_CDC/arFifo/pushToPopGray_buffercc/buffers_0_reg[0]/C
|
|
|
|
Slack: inf
|
|
Source: u_Axi_CDC/awFifo/pushCC_pushPtrGray_reg[2]/C
|
|
(rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns})
|
|
Destination: u_Axi_CDC/awFifo/pushToPopGray_buffercc/buffers_0_reg[2]/D
|
|
(rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Path Group: (none)
|
|
Path Type: Hold (Min at Slow Process Corner)
|
|
Data Path Delay: 0.654ns (logic 0.385ns (58.892%) route 0.269ns (41.108%))
|
|
Logic Levels: 0
|
|
Clock Path Skew: -0.389ns (DCD - SCD - CPR)
|
|
Destination Clock Delay (DCD): -2.408ns
|
|
Source Clock Delay (SCD): -2.018ns
|
|
Clock Pessimism Removal (CPR): -0.000ns
|
|
Clock Uncertainty: 0.194ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Discrete Jitter (DJ): 0.130ns
|
|
Phase Error (PE): 0.120ns
|
|
Timing Exception: Asynchronous Clock Groups
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock cpu_clk rise edge) 0.000 0.000 r
|
|
K21 0.000 0.000 r clk (IN)
|
|
net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1
|
|
K21 IBUF (Prop_ibuf_I_O) 1.393 1.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O
|
|
net (fo=1, routed) 1.181 2.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll
|
|
PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0)
|
|
-8.248 -5.674 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0
|
|
net (fo=1, routed) 1.755 -3.919 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll
|
|
BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.091 -3.828 r pll_clk.u_clk_pll/inst/clkout1_buf/O
|
|
net (fo=6484, routed) 1.810 -2.018 u_Axi_CDC/awFifo/cpu_clk
|
|
SLICE_X14Y69 FDCE r u_Axi_CDC/awFifo/pushCC_pushPtrGray_reg[2]/C
|
|
------------------------------------------------------------------- -------------------
|
|
SLICE_X14Y69 FDCE (Prop_fdce_C_Q) 0.385 -1.633 r u_Axi_CDC/awFifo/pushCC_pushPtrGray_reg[2]/Q
|
|
net (fo=4, routed) 0.269 -1.365 u_Axi_CDC/awFifo/pushToPopGray_buffercc/buffers_0_reg[2]_0
|
|
SLICE_X15Y70 FDCE r u_Axi_CDC/awFifo/pushToPopGray_buffercc/buffers_0_reg[2]/D
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock sys_clk rise edge) 0.000 0.000 r
|
|
K21 0.000 0.000 r clk (IN)
|
|
net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1
|
|
K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O
|
|
net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll
|
|
PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1)
|
|
-8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1
|
|
net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll
|
|
BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O
|
|
net (fo=10004, routed) 1.934 -2.408 u_Axi_CDC/awFifo/pushToPopGray_buffercc/sys_clk
|
|
SLICE_X15Y70 FDCE r u_Axi_CDC/awFifo/pushToPopGray_buffercc/buffers_0_reg[2]/C
|
|
|
|
Slack: inf
|
|
Source: u_Axi_CDC/rFifo/popCC_ptrToPush_reg[2]/C
|
|
(rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns})
|
|
Destination: u_Axi_CDC/rFifo/popToPushGray_buffercc/buffers_0_reg[2]/D
|
|
(rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Path Group: (none)
|
|
Path Type: Hold (Min at Slow Process Corner)
|
|
Data Path Delay: 0.621ns (logic 0.337ns (54.306%) route 0.284ns (45.694%))
|
|
Logic Levels: 0
|
|
Clock Path Skew: -0.390ns (DCD - SCD - CPR)
|
|
Destination Clock Delay (DCD): -2.337ns
|
|
Source Clock Delay (SCD): -1.946ns
|
|
Clock Pessimism Removal (CPR): -0.000ns
|
|
Clock Uncertainty: 0.194ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Discrete Jitter (DJ): 0.130ns
|
|
Phase Error (PE): 0.120ns
|
|
Timing Exception: Asynchronous Clock Groups
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock cpu_clk rise edge) 0.000 0.000 r
|
|
K21 0.000 0.000 r clk (IN)
|
|
net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1
|
|
K21 IBUF (Prop_ibuf_I_O) 1.393 1.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O
|
|
net (fo=1, routed) 1.181 2.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll
|
|
PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0)
|
|
-8.248 -5.674 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0
|
|
net (fo=1, routed) 1.755 -3.919 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll
|
|
BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.091 -3.828 r pll_clk.u_clk_pll/inst/clkout1_buf/O
|
|
net (fo=6484, routed) 1.882 -1.946 u_Axi_CDC/rFifo/cpu_clk
|
|
SLICE_X5Y74 FDCE r u_Axi_CDC/rFifo/popCC_ptrToPush_reg[2]/C
|
|
------------------------------------------------------------------- -------------------
|
|
SLICE_X5Y74 FDCE (Prop_fdce_C_Q) 0.337 -1.609 r u_Axi_CDC/rFifo/popCC_ptrToPush_reg[2]/Q
|
|
net (fo=1, routed) 0.284 -1.326 u_Axi_CDC/rFifo/popToPushGray_buffercc/buffers_0_reg[3]_0[2]
|
|
SLICE_X4Y75 FDCE r u_Axi_CDC/rFifo/popToPushGray_buffercc/buffers_0_reg[2]/D
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock sys_clk rise edge) 0.000 0.000 r
|
|
K21 0.000 0.000 r clk (IN)
|
|
net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1
|
|
K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O
|
|
net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll
|
|
PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1)
|
|
-8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1
|
|
net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll
|
|
BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O
|
|
net (fo=10004, routed) 2.005 -2.337 u_Axi_CDC/rFifo/popToPushGray_buffercc/sys_clk
|
|
SLICE_X4Y75 FDCE r u_Axi_CDC/rFifo/popToPushGray_buffercc/buffers_0_reg[2]/C
|
|
|
|
Slack: inf
|
|
Source: u_Axi_CDC/bFifo/popCC_ptrToPush_reg[0]/C
|
|
(rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns})
|
|
Destination: u_Axi_CDC/bFifo/popToPushGray_buffercc/buffers_0_reg[0]/D
|
|
(rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Path Group: (none)
|
|
Path Type: Hold (Min at Slow Process Corner)
|
|
Data Path Delay: 0.736ns (logic 0.367ns (49.854%) route 0.369ns (50.146%))
|
|
Logic Levels: 0
|
|
Clock Path Skew: -0.388ns (DCD - SCD - CPR)
|
|
Destination Clock Delay (DCD): -2.397ns
|
|
Source Clock Delay (SCD): -2.008ns
|
|
Clock Pessimism Removal (CPR): -0.000ns
|
|
Clock Uncertainty: 0.194ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Discrete Jitter (DJ): 0.130ns
|
|
Phase Error (PE): 0.120ns
|
|
Timing Exception: Asynchronous Clock Groups
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock cpu_clk rise edge) 0.000 0.000 r
|
|
K21 0.000 0.000 r clk (IN)
|
|
net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1
|
|
K21 IBUF (Prop_ibuf_I_O) 1.393 1.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O
|
|
net (fo=1, routed) 1.181 2.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll
|
|
PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0)
|
|
-8.248 -5.674 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0
|
|
net (fo=1, routed) 1.755 -3.919 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll
|
|
BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.091 -3.828 r pll_clk.u_clk_pll/inst/clkout1_buf/O
|
|
net (fo=6484, routed) 1.820 -2.008 u_Axi_CDC/bFifo/cpu_clk
|
|
SLICE_X19Y58 FDCE r u_Axi_CDC/bFifo/popCC_ptrToPush_reg[0]/C
|
|
------------------------------------------------------------------- -------------------
|
|
SLICE_X19Y58 FDCE (Prop_fdce_C_Q) 0.367 -1.641 r u_Axi_CDC/bFifo/popCC_ptrToPush_reg[0]/Q
|
|
net (fo=2, routed) 0.369 -1.272 u_Axi_CDC/bFifo/popToPushGray_buffercc/D[0]
|
|
SLICE_X17Y59 FDCE r u_Axi_CDC/bFifo/popToPushGray_buffercc/buffers_0_reg[0]/D
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock sys_clk rise edge) 0.000 0.000 r
|
|
K21 0.000 0.000 r clk (IN)
|
|
net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1
|
|
K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O
|
|
net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll
|
|
PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1)
|
|
-8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1
|
|
net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll
|
|
BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O
|
|
net (fo=10004, routed) 1.945 -2.397 u_Axi_CDC/bFifo/popToPushGray_buffercc/sys_clk
|
|
SLICE_X17Y59 FDCE r u_Axi_CDC/bFifo/popToPushGray_buffercc/buffers_0_reg[0]/C
|
|
|
|
Slack: inf
|
|
Source: u_Axi_CDC/bFifo/popCC_ptrToPush_reg[1]/C
|
|
(rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns})
|
|
Destination: u_Axi_CDC/bFifo/popToPushGray_buffercc/buffers_0_reg[1]/D
|
|
(rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Path Group: (none)
|
|
Path Type: Hold (Min at Slow Process Corner)
|
|
Data Path Delay: 0.740ns (logic 0.367ns (49.584%) route 0.373ns (50.416%))
|
|
Logic Levels: 0
|
|
Clock Path Skew: -0.388ns (DCD - SCD - CPR)
|
|
Destination Clock Delay (DCD): -2.397ns
|
|
Source Clock Delay (SCD): -2.008ns
|
|
Clock Pessimism Removal (CPR): -0.000ns
|
|
Clock Uncertainty: 0.194ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Discrete Jitter (DJ): 0.130ns
|
|
Phase Error (PE): 0.120ns
|
|
Timing Exception: Asynchronous Clock Groups
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock cpu_clk rise edge) 0.000 0.000 r
|
|
K21 0.000 0.000 r clk (IN)
|
|
net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1
|
|
K21 IBUF (Prop_ibuf_I_O) 1.393 1.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O
|
|
net (fo=1, routed) 1.181 2.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll
|
|
PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0)
|
|
-8.248 -5.674 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0
|
|
net (fo=1, routed) 1.755 -3.919 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll
|
|
BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.091 -3.828 r pll_clk.u_clk_pll/inst/clkout1_buf/O
|
|
net (fo=6484, routed) 1.820 -2.008 u_Axi_CDC/bFifo/cpu_clk
|
|
SLICE_X17Y58 FDCE r u_Axi_CDC/bFifo/popCC_ptrToPush_reg[1]/C
|
|
------------------------------------------------------------------- -------------------
|
|
SLICE_X17Y58 FDCE (Prop_fdce_C_Q) 0.367 -1.641 r u_Axi_CDC/bFifo/popCC_ptrToPush_reg[1]/Q
|
|
net (fo=2, routed) 0.373 -1.268 u_Axi_CDC/bFifo/popToPushGray_buffercc/D[1]
|
|
SLICE_X17Y59 FDCE r u_Axi_CDC/bFifo/popToPushGray_buffercc/buffers_0_reg[1]/D
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock sys_clk rise edge) 0.000 0.000 r
|
|
K21 0.000 0.000 r clk (IN)
|
|
net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1
|
|
K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O
|
|
net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll
|
|
PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1)
|
|
-8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1
|
|
net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll
|
|
BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O
|
|
net (fo=10004, routed) 1.945 -2.397 u_Axi_CDC/bFifo/popToPushGray_buffercc/sys_clk
|
|
SLICE_X17Y59 FDCE r u_Axi_CDC/bFifo/popToPushGray_buffercc/buffers_0_reg[1]/C
|
|
|
|
Slack: inf
|
|
Source: u_Axi_CDC/arFifo/pushCC_pushPtrGray_reg[1]/C
|
|
(rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns})
|
|
Destination: u_Axi_CDC/arFifo/pushToPopGray_buffercc/buffers_0_reg[1]/D
|
|
(rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Path Group: (none)
|
|
Path Type: Hold (Min at Slow Process Corner)
|
|
Data Path Delay: 0.792ns (logic 0.367ns (46.311%) route 0.425ns (53.689%))
|
|
Logic Levels: 0
|
|
Clock Path Skew: -0.388ns (DCD - SCD - CPR)
|
|
Destination Clock Delay (DCD): -2.403ns
|
|
Source Clock Delay (SCD): -2.014ns
|
|
Clock Pessimism Removal (CPR): -0.000ns
|
|
Clock Uncertainty: 0.194ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Discrete Jitter (DJ): 0.130ns
|
|
Phase Error (PE): 0.120ns
|
|
Timing Exception: Asynchronous Clock Groups
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock cpu_clk rise edge) 0.000 0.000 r
|
|
K21 0.000 0.000 r clk (IN)
|
|
net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1
|
|
K21 IBUF (Prop_ibuf_I_O) 1.393 1.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O
|
|
net (fo=1, routed) 1.181 2.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll
|
|
PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0)
|
|
-8.248 -5.674 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0
|
|
net (fo=1, routed) 1.755 -3.919 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll
|
|
BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.091 -3.828 r pll_clk.u_clk_pll/inst/clkout1_buf/O
|
|
net (fo=6484, routed) 1.814 -2.014 u_Axi_CDC/arFifo/cpu_clk
|
|
SLICE_X17Y66 FDCE r u_Axi_CDC/arFifo/pushCC_pushPtrGray_reg[1]/C
|
|
------------------------------------------------------------------- -------------------
|
|
SLICE_X17Y66 FDCE (Prop_fdce_C_Q) 0.367 -1.647 r u_Axi_CDC/arFifo/pushCC_pushPtrGray_reg[1]/Q
|
|
net (fo=2, routed) 0.425 -1.222 u_Axi_CDC/arFifo/pushToPopGray_buffercc/Q[1]
|
|
SLICE_X15Y66 FDCE r u_Axi_CDC/arFifo/pushToPopGray_buffercc/buffers_0_reg[1]/D
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock sys_clk rise edge) 0.000 0.000 r
|
|
K21 0.000 0.000 r clk (IN)
|
|
net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1
|
|
K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O
|
|
net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll
|
|
PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1)
|
|
-8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1
|
|
net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll
|
|
BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O
|
|
net (fo=10004, routed) 1.939 -2.403 u_Axi_CDC/arFifo/pushToPopGray_buffercc/sys_clk
|
|
SLICE_X15Y66 FDCE r u_Axi_CDC/arFifo/pushToPopGray_buffercc/buffers_0_reg[1]/C
|
|
|
|
Slack: inf
|
|
Source: u_Axi_CDC/awFifo/pushCC_pushPtrGray_reg[0]/C
|
|
(rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns})
|
|
Destination: u_Axi_CDC/awFifo/pushToPopGray_buffercc/buffers_0_reg[0]/D
|
|
(rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Path Group: (none)
|
|
Path Type: Hold (Min at Slow Process Corner)
|
|
Data Path Delay: 0.817ns (logic 0.418ns (51.164%) route 0.399ns (48.836%))
|
|
Logic Levels: 0
|
|
Clock Path Skew: -0.388ns (DCD - SCD - CPR)
|
|
Destination Clock Delay (DCD): -2.407ns
|
|
Source Clock Delay (SCD): -2.018ns
|
|
Clock Pessimism Removal (CPR): -0.000ns
|
|
Clock Uncertainty: 0.194ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Discrete Jitter (DJ): 0.130ns
|
|
Phase Error (PE): 0.120ns
|
|
Timing Exception: Asynchronous Clock Groups
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock cpu_clk rise edge) 0.000 0.000 r
|
|
K21 0.000 0.000 r clk (IN)
|
|
net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1
|
|
K21 IBUF (Prop_ibuf_I_O) 1.393 1.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O
|
|
net (fo=1, routed) 1.181 2.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll
|
|
PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0)
|
|
-8.248 -5.674 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0
|
|
net (fo=1, routed) 1.755 -3.919 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll
|
|
BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.091 -3.828 r pll_clk.u_clk_pll/inst/clkout1_buf/O
|
|
net (fo=6484, routed) 1.810 -2.018 u_Axi_CDC/awFifo/cpu_clk
|
|
SLICE_X14Y69 FDCE r u_Axi_CDC/awFifo/pushCC_pushPtrGray_reg[0]/C
|
|
------------------------------------------------------------------- -------------------
|
|
SLICE_X14Y69 FDCE (Prop_fdce_C_Q) 0.418 -1.600 r u_Axi_CDC/awFifo/pushCC_pushPtrGray_reg[0]/Q
|
|
net (fo=2, routed) 0.399 -1.201 u_Axi_CDC/awFifo/pushToPopGray_buffercc/Q[0]
|
|
SLICE_X13Y69 FDCE r u_Axi_CDC/awFifo/pushToPopGray_buffercc/buffers_0_reg[0]/D
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock sys_clk rise edge) 0.000 0.000 r
|
|
K21 0.000 0.000 r clk (IN)
|
|
net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1
|
|
K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O
|
|
net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll
|
|
PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1)
|
|
-8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1
|
|
net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll
|
|
BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O
|
|
net (fo=10004, routed) 1.935 -2.407 u_Axi_CDC/awFifo/pushToPopGray_buffercc/sys_clk
|
|
SLICE_X13Y69 FDCE r u_Axi_CDC/awFifo/pushToPopGray_buffercc/buffers_0_reg[0]/C
|
|
|
|
Slack: inf
|
|
Source: u_Axi_CDC/awFifo/pushCC_pushPtrGray_reg[1]/C
|
|
(rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns})
|
|
Destination: u_Axi_CDC/awFifo/pushToPopGray_buffercc/buffers_0_reg[1]/D
|
|
(rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Path Group: (none)
|
|
Path Type: Hold (Min at Slow Process Corner)
|
|
Data Path Delay: 0.833ns (logic 0.418ns (50.157%) route 0.415ns (49.843%))
|
|
Logic Levels: 0
|
|
Clock Path Skew: -0.389ns (DCD - SCD - CPR)
|
|
Destination Clock Delay (DCD): -2.408ns
|
|
Source Clock Delay (SCD): -2.018ns
|
|
Clock Pessimism Removal (CPR): -0.000ns
|
|
Clock Uncertainty: 0.194ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Discrete Jitter (DJ): 0.130ns
|
|
Phase Error (PE): 0.120ns
|
|
Timing Exception: Asynchronous Clock Groups
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock cpu_clk rise edge) 0.000 0.000 r
|
|
K21 0.000 0.000 r clk (IN)
|
|
net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1
|
|
K21 IBUF (Prop_ibuf_I_O) 1.393 1.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O
|
|
net (fo=1, routed) 1.181 2.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll
|
|
PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0)
|
|
-8.248 -5.674 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0
|
|
net (fo=1, routed) 1.755 -3.919 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll
|
|
BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.091 -3.828 r pll_clk.u_clk_pll/inst/clkout1_buf/O
|
|
net (fo=6484, routed) 1.810 -2.018 u_Axi_CDC/awFifo/cpu_clk
|
|
SLICE_X14Y69 FDCE r u_Axi_CDC/awFifo/pushCC_pushPtrGray_reg[1]/C
|
|
------------------------------------------------------------------- -------------------
|
|
SLICE_X14Y69 FDCE (Prop_fdce_C_Q) 0.418 -1.600 r u_Axi_CDC/awFifo/pushCC_pushPtrGray_reg[1]/Q
|
|
net (fo=2, routed) 0.415 -1.185 u_Axi_CDC/awFifo/pushToPopGray_buffercc/Q[1]
|
|
SLICE_X15Y70 FDCE r u_Axi_CDC/awFifo/pushToPopGray_buffercc/buffers_0_reg[1]/D
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock sys_clk rise edge) 0.000 0.000 r
|
|
K21 0.000 0.000 r clk (IN)
|
|
net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1
|
|
K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O
|
|
net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll
|
|
PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1)
|
|
-8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1
|
|
net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll
|
|
BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O
|
|
net (fo=10004, routed) 1.934 -2.408 u_Axi_CDC/awFifo/pushToPopGray_buffercc/sys_clk
|
|
SLICE_X15Y70 FDCE r u_Axi_CDC/awFifo/pushToPopGray_buffercc/buffers_0_reg[1]/C
|
|
|
|
Slack: inf
|
|
Source: u_Axi_CDC/rFifo/popCC_ptrToPush_reg[3]/C
|
|
(rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns})
|
|
Destination: u_Axi_CDC/rFifo/popToPushGray_buffercc/buffers_0_reg[3]/D
|
|
(rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Path Group: (none)
|
|
Path Type: Hold (Min at Slow Process Corner)
|
|
Data Path Delay: 0.793ns (logic 0.367ns (46.283%) route 0.426ns (53.717%))
|
|
Logic Levels: 0
|
|
Clock Path Skew: -0.390ns (DCD - SCD - CPR)
|
|
Destination Clock Delay (DCD): -2.337ns
|
|
Source Clock Delay (SCD): -1.946ns
|
|
Clock Pessimism Removal (CPR): -0.000ns
|
|
Clock Uncertainty: 0.194ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Discrete Jitter (DJ): 0.130ns
|
|
Phase Error (PE): 0.120ns
|
|
Timing Exception: Asynchronous Clock Groups
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock cpu_clk rise edge) 0.000 0.000 r
|
|
K21 0.000 0.000 r clk (IN)
|
|
net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1
|
|
K21 IBUF (Prop_ibuf_I_O) 1.393 1.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O
|
|
net (fo=1, routed) 1.181 2.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll
|
|
PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0)
|
|
-8.248 -5.674 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0
|
|
net (fo=1, routed) 1.755 -3.919 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll
|
|
BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.091 -3.828 r pll_clk.u_clk_pll/inst/clkout1_buf/O
|
|
net (fo=6484, routed) 1.882 -1.946 u_Axi_CDC/rFifo/cpu_clk
|
|
SLICE_X5Y74 FDCE r u_Axi_CDC/rFifo/popCC_ptrToPush_reg[3]/C
|
|
------------------------------------------------------------------- -------------------
|
|
SLICE_X5Y74 FDCE (Prop_fdce_C_Q) 0.367 -1.579 r u_Axi_CDC/rFifo/popCC_ptrToPush_reg[3]/Q
|
|
net (fo=1, routed) 0.426 -1.153 u_Axi_CDC/rFifo/popToPushGray_buffercc/buffers_0_reg[3]_0[3]
|
|
SLICE_X4Y75 FDCE r u_Axi_CDC/rFifo/popToPushGray_buffercc/buffers_0_reg[3]/D
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock sys_clk rise edge) 0.000 0.000 r
|
|
K21 0.000 0.000 r clk (IN)
|
|
net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1
|
|
K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O
|
|
net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll
|
|
PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1)
|
|
-8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1
|
|
net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll
|
|
BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O
|
|
net (fo=10004, routed) 2.005 -2.337 u_Axi_CDC/rFifo/popToPushGray_buffercc/sys_clk
|
|
SLICE_X4Y75 FDCE r u_Axi_CDC/rFifo/popToPushGray_buffercc/buffers_0_reg[3]/C
|
|
|
|
Slack: inf
|
|
Source: u_Axi_CDC/wFifo/pushCC_pushPtrGray_reg[3]/C
|
|
(rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns})
|
|
Destination: u_Axi_CDC/wFifo/pushToPopGray_buffercc/buffers_0_reg[3]/D
|
|
(rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Path Group: (none)
|
|
Path Type: Hold (Min at Slow Process Corner)
|
|
Data Path Delay: 0.632ns (logic 0.337ns (53.354%) route 0.295ns (46.646%))
|
|
Logic Levels: 0
|
|
Clock Path Skew: -0.381ns (DCD - SCD - CPR)
|
|
Destination Clock Delay (DCD): -2.131ns
|
|
Source Clock Delay (SCD): -1.750ns
|
|
Clock Pessimism Removal (CPR): -0.000ns
|
|
Clock Uncertainty: 0.194ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Discrete Jitter (DJ): 0.130ns
|
|
Phase Error (PE): 0.120ns
|
|
Timing Exception: Asynchronous Clock Groups
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock cpu_clk rise edge) 0.000 0.000 r
|
|
K21 0.000 0.000 r clk (IN)
|
|
net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1
|
|
K21 IBUF (Prop_ibuf_I_O) 1.393 1.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O
|
|
net (fo=1, routed) 1.181 2.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll
|
|
PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0)
|
|
-8.248 -5.674 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0
|
|
net (fo=1, routed) 1.755 -3.919 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll
|
|
BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.091 -3.828 r pll_clk.u_clk_pll/inst/clkout1_buf/O
|
|
net (fo=6484, routed) 2.079 -1.750 u_Axi_CDC/wFifo/cpu_clk
|
|
SLICE_X3Y49 FDCE r u_Axi_CDC/wFifo/pushCC_pushPtrGray_reg[3]/C
|
|
------------------------------------------------------------------- -------------------
|
|
SLICE_X3Y49 FDCE (Prop_fdce_C_Q) 0.337 -1.413 r u_Axi_CDC/wFifo/pushCC_pushPtrGray_reg[3]/Q
|
|
net (fo=5, routed) 0.295 -1.118 u_Axi_CDC/wFifo/pushToPopGray_buffercc/D[3]
|
|
SLICE_X4Y49 FDCE r u_Axi_CDC/wFifo/pushToPopGray_buffercc/buffers_0_reg[3]/D
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock sys_clk rise edge) 0.000 0.000 r
|
|
K21 0.000 0.000 r clk (IN)
|
|
net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1
|
|
K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O
|
|
net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll
|
|
PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1)
|
|
-8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1
|
|
net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll
|
|
BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O
|
|
net (fo=10004, routed) 2.211 -2.131 u_Axi_CDC/wFifo/pushToPopGray_buffercc/sys_clk
|
|
SLICE_X4Y49 FDCE r u_Axi_CDC/wFifo/pushToPopGray_buffercc/buffers_0_reg[3]/C
|
|
|
|
Slack: inf
|
|
Source: u_Axi_CDC/wFifo/pushCC_pushPtrGray_reg[1]/C
|
|
(rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns})
|
|
Destination: u_Axi_CDC/wFifo/pushToPopGray_buffercc/buffers_0_reg[1]/D
|
|
(rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Path Group: (none)
|
|
Path Type: Hold (Min at Slow Process Corner)
|
|
Data Path Delay: 0.641ns (logic 0.367ns (57.215%) route 0.274ns (42.785%))
|
|
Logic Levels: 0
|
|
Clock Path Skew: -0.381ns (DCD - SCD - CPR)
|
|
Destination Clock Delay (DCD): -2.131ns
|
|
Source Clock Delay (SCD): -1.750ns
|
|
Clock Pessimism Removal (CPR): -0.000ns
|
|
Clock Uncertainty: 0.194ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Discrete Jitter (DJ): 0.130ns
|
|
Phase Error (PE): 0.120ns
|
|
Timing Exception: Asynchronous Clock Groups
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock cpu_clk rise edge) 0.000 0.000 r
|
|
K21 0.000 0.000 r clk (IN)
|
|
net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1
|
|
K21 IBUF (Prop_ibuf_I_O) 1.393 1.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O
|
|
net (fo=1, routed) 1.181 2.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll
|
|
PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0)
|
|
-8.248 -5.674 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0
|
|
net (fo=1, routed) 1.755 -3.919 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll
|
|
BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.091 -3.828 r pll_clk.u_clk_pll/inst/clkout1_buf/O
|
|
net (fo=6484, routed) 2.079 -1.750 u_Axi_CDC/wFifo/cpu_clk
|
|
SLICE_X3Y49 FDCE r u_Axi_CDC/wFifo/pushCC_pushPtrGray_reg[1]/C
|
|
------------------------------------------------------------------- -------------------
|
|
SLICE_X3Y49 FDCE (Prop_fdce_C_Q) 0.367 -1.383 r u_Axi_CDC/wFifo/pushCC_pushPtrGray_reg[1]/Q
|
|
net (fo=2, routed) 0.274 -1.108 u_Axi_CDC/wFifo/pushToPopGray_buffercc/D[1]
|
|
SLICE_X4Y49 FDCE r u_Axi_CDC/wFifo/pushToPopGray_buffercc/buffers_0_reg[1]/D
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock sys_clk rise edge) 0.000 0.000 r
|
|
K21 0.000 0.000 r clk (IN)
|
|
net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1
|
|
K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O
|
|
net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll
|
|
PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1)
|
|
-8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1
|
|
net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll
|
|
BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O
|
|
net (fo=10004, routed) 2.211 -2.131 u_Axi_CDC/wFifo/pushToPopGray_buffercc/sys_clk
|
|
SLICE_X4Y49 FDCE r u_Axi_CDC/wFifo/pushToPopGray_buffercc/buffers_0_reg[1]/C
|
|
|
|
Slack: inf
|
|
Source: u_Axi_CDC/rFifo/popCC_ptrToPush_reg[1]/C
|
|
(rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns})
|
|
Destination: u_Axi_CDC/rFifo/popToPushGray_buffercc/buffers_0_reg[1]/D
|
|
(rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Path Group: (none)
|
|
Path Type: Hold (Min at Slow Process Corner)
|
|
Data Path Delay: 0.928ns (logic 0.367ns (39.555%) route 0.561ns (60.445%))
|
|
Logic Levels: 0
|
|
Clock Path Skew: -0.387ns (DCD - SCD - CPR)
|
|
Destination Clock Delay (DCD): -2.334ns
|
|
Source Clock Delay (SCD): -1.946ns
|
|
Clock Pessimism Removal (CPR): -0.000ns
|
|
Clock Uncertainty: 0.194ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Discrete Jitter (DJ): 0.130ns
|
|
Phase Error (PE): 0.120ns
|
|
Timing Exception: Asynchronous Clock Groups
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock cpu_clk rise edge) 0.000 0.000 r
|
|
K21 0.000 0.000 r clk (IN)
|
|
net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1
|
|
K21 IBUF (Prop_ibuf_I_O) 1.393 1.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O
|
|
net (fo=1, routed) 1.181 2.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll
|
|
PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0)
|
|
-8.248 -5.674 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0
|
|
net (fo=1, routed) 1.755 -3.919 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll
|
|
BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.091 -3.828 r pll_clk.u_clk_pll/inst/clkout1_buf/O
|
|
net (fo=6484, routed) 1.882 -1.946 u_Axi_CDC/rFifo/cpu_clk
|
|
SLICE_X5Y74 FDCE r u_Axi_CDC/rFifo/popCC_ptrToPush_reg[1]/C
|
|
------------------------------------------------------------------- -------------------
|
|
SLICE_X5Y74 FDCE (Prop_fdce_C_Q) 0.367 -1.579 r u_Axi_CDC/rFifo/popCC_ptrToPush_reg[1]/Q
|
|
net (fo=1, routed) 0.561 -1.018 u_Axi_CDC/rFifo/popToPushGray_buffercc/buffers_0_reg[3]_0[1]
|
|
SLICE_X4Y77 FDCE r u_Axi_CDC/rFifo/popToPushGray_buffercc/buffers_0_reg[1]/D
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock sys_clk rise edge) 0.000 0.000 r
|
|
K21 0.000 0.000 r clk (IN)
|
|
net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1
|
|
K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O
|
|
net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll
|
|
PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1)
|
|
-8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1
|
|
net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll
|
|
BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O
|
|
net (fo=10004, routed) 2.008 -2.334 u_Axi_CDC/rFifo/popToPushGray_buffercc/sys_clk
|
|
SLICE_X4Y77 FDCE r u_Axi_CDC/rFifo/popToPushGray_buffercc/buffers_0_reg[1]/C
|
|
|
|
Slack: inf
|
|
Source: u_Axi_CDC/wFifo/pushCC_pushPtrGray_reg[2]/C
|
|
(rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns})
|
|
Destination: u_Axi_CDC/wFifo/pushToPopGray_buffercc/buffers_0_reg[2]/D
|
|
(rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Path Group: (none)
|
|
Path Type: Hold (Min at Slow Process Corner)
|
|
Data Path Delay: 0.770ns (logic 0.367ns (47.632%) route 0.403ns (52.368%))
|
|
Logic Levels: 0
|
|
Clock Path Skew: -0.381ns (DCD - SCD - CPR)
|
|
Destination Clock Delay (DCD): -2.131ns
|
|
Source Clock Delay (SCD): -1.750ns
|
|
Clock Pessimism Removal (CPR): -0.000ns
|
|
Clock Uncertainty: 0.194ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Discrete Jitter (DJ): 0.130ns
|
|
Phase Error (PE): 0.120ns
|
|
Timing Exception: Asynchronous Clock Groups
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock cpu_clk rise edge) 0.000 0.000 r
|
|
K21 0.000 0.000 r clk (IN)
|
|
net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1
|
|
K21 IBUF (Prop_ibuf_I_O) 1.393 1.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O
|
|
net (fo=1, routed) 1.181 2.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll
|
|
PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0)
|
|
-8.248 -5.674 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0
|
|
net (fo=1, routed) 1.755 -3.919 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll
|
|
BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.091 -3.828 r pll_clk.u_clk_pll/inst/clkout1_buf/O
|
|
net (fo=6484, routed) 2.079 -1.750 u_Axi_CDC/wFifo/cpu_clk
|
|
SLICE_X3Y49 FDCE r u_Axi_CDC/wFifo/pushCC_pushPtrGray_reg[2]/C
|
|
------------------------------------------------------------------- -------------------
|
|
SLICE_X3Y49 FDCE (Prop_fdce_C_Q) 0.367 -1.383 r u_Axi_CDC/wFifo/pushCC_pushPtrGray_reg[2]/Q
|
|
net (fo=3, routed) 0.403 -0.979 u_Axi_CDC/wFifo/pushToPopGray_buffercc/D[2]
|
|
SLICE_X4Y49 FDCE r u_Axi_CDC/wFifo/pushToPopGray_buffercc/buffers_0_reg[2]/D
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock sys_clk rise edge) 0.000 0.000 r
|
|
K21 0.000 0.000 r clk (IN)
|
|
net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1
|
|
K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O
|
|
net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll
|
|
PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1)
|
|
-8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1
|
|
net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll
|
|
BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O
|
|
net (fo=10004, routed) 2.211 -2.131 u_Axi_CDC/wFifo/pushToPopGray_buffercc/sys_clk
|
|
SLICE_X4Y49 FDCE r u_Axi_CDC/wFifo/pushToPopGray_buffercc/buffers_0_reg[2]/C
|
|
|
|
Slack: inf
|
|
Source: u_Axi_CDC/rFifo/popCC_ptrToPush_reg[0]/C
|
|
(rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns})
|
|
Destination: u_Axi_CDC/rFifo/popToPushGray_buffercc/buffers_0_reg[0]/D
|
|
(rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Path Group: (none)
|
|
Path Type: Hold (Min at Slow Process Corner)
|
|
Data Path Delay: 1.000ns (logic 0.367ns (36.693%) route 0.633ns (63.307%))
|
|
Logic Levels: 0
|
|
Clock Path Skew: -0.387ns (DCD - SCD - CPR)
|
|
Destination Clock Delay (DCD): -2.334ns
|
|
Source Clock Delay (SCD): -1.946ns
|
|
Clock Pessimism Removal (CPR): -0.000ns
|
|
Clock Uncertainty: 0.194ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Discrete Jitter (DJ): 0.130ns
|
|
Phase Error (PE): 0.120ns
|
|
Timing Exception: Asynchronous Clock Groups
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock cpu_clk rise edge) 0.000 0.000 r
|
|
K21 0.000 0.000 r clk (IN)
|
|
net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1
|
|
K21 IBUF (Prop_ibuf_I_O) 1.393 1.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O
|
|
net (fo=1, routed) 1.181 2.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll
|
|
PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0)
|
|
-8.248 -5.674 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0
|
|
net (fo=1, routed) 1.755 -3.919 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll
|
|
BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.091 -3.828 r pll_clk.u_clk_pll/inst/clkout1_buf/O
|
|
net (fo=6484, routed) 1.882 -1.946 u_Axi_CDC/rFifo/cpu_clk
|
|
SLICE_X5Y74 FDCE r u_Axi_CDC/rFifo/popCC_ptrToPush_reg[0]/C
|
|
------------------------------------------------------------------- -------------------
|
|
SLICE_X5Y74 FDCE (Prop_fdce_C_Q) 0.367 -1.579 r u_Axi_CDC/rFifo/popCC_ptrToPush_reg[0]/Q
|
|
net (fo=1, routed) 0.633 -0.946 u_Axi_CDC/rFifo/popToPushGray_buffercc/buffers_0_reg[3]_0[0]
|
|
SLICE_X4Y77 FDCE r u_Axi_CDC/rFifo/popToPushGray_buffercc/buffers_0_reg[0]/D
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock sys_clk rise edge) 0.000 0.000 r
|
|
K21 0.000 0.000 r clk (IN)
|
|
net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1
|
|
K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O
|
|
net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll
|
|
PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1)
|
|
-8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1
|
|
net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll
|
|
BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O
|
|
net (fo=10004, routed) 2.008 -2.334 u_Axi_CDC/rFifo/popToPushGray_buffercc/sys_clk
|
|
SLICE_X4Y77 FDCE r u_Axi_CDC/rFifo/popToPushGray_buffercc/buffers_0_reg[0]/C
|
|
|
|
Slack: inf
|
|
Source: u_Axi_CDC/wFifo/pushCC_pushPtrGray_reg[0]/C
|
|
(rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns})
|
|
Destination: u_Axi_CDC/wFifo/pushToPopGray_buffercc/buffers_0_reg[0]/D
|
|
(rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Path Group: (none)
|
|
Path Type: Hold (Min at Slow Process Corner)
|
|
Data Path Delay: 0.892ns (logic 0.367ns (41.149%) route 0.525ns (58.851%))
|
|
Logic Levels: 0
|
|
Clock Path Skew: -0.381ns (DCD - SCD - CPR)
|
|
Destination Clock Delay (DCD): -2.131ns
|
|
Source Clock Delay (SCD): -1.750ns
|
|
Clock Pessimism Removal (CPR): -0.000ns
|
|
Clock Uncertainty: 0.194ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Discrete Jitter (DJ): 0.130ns
|
|
Phase Error (PE): 0.120ns
|
|
Timing Exception: Asynchronous Clock Groups
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock cpu_clk rise edge) 0.000 0.000 r
|
|
K21 0.000 0.000 r clk (IN)
|
|
net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1
|
|
K21 IBUF (Prop_ibuf_I_O) 1.393 1.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O
|
|
net (fo=1, routed) 1.181 2.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll
|
|
PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0)
|
|
-8.248 -5.674 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0
|
|
net (fo=1, routed) 1.755 -3.919 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll
|
|
BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.091 -3.828 r pll_clk.u_clk_pll/inst/clkout1_buf/O
|
|
net (fo=6484, routed) 2.079 -1.750 u_Axi_CDC/wFifo/cpu_clk
|
|
SLICE_X3Y49 FDCE r u_Axi_CDC/wFifo/pushCC_pushPtrGray_reg[0]/C
|
|
------------------------------------------------------------------- -------------------
|
|
SLICE_X3Y49 FDCE (Prop_fdce_C_Q) 0.367 -1.383 r u_Axi_CDC/wFifo/pushCC_pushPtrGray_reg[0]/Q
|
|
net (fo=2, routed) 0.525 -0.858 u_Axi_CDC/wFifo/pushToPopGray_buffercc/D[0]
|
|
SLICE_X4Y49 FDCE r u_Axi_CDC/wFifo/pushToPopGray_buffercc/buffers_0_reg[0]/D
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock sys_clk rise edge) 0.000 0.000 r
|
|
K21 0.000 0.000 r clk (IN)
|
|
net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1
|
|
K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O
|
|
net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll
|
|
PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1)
|
|
-8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1
|
|
net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll
|
|
BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O
|
|
net (fo=10004, routed) 2.211 -2.131 u_Axi_CDC/wFifo/pushToPopGray_buffercc/sys_clk
|
|
SLICE_X4Y49 FDCE r u_Axi_CDC/wFifo/pushToPopGray_buffercc/buffers_0_reg[0]/C
|
|
|
|
Slack: inf
|
|
Source: u_Axi_CDC/awFifo/ram_reg_0_3_0_5/RAMA_D1/CLK
|
|
(rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns})
|
|
Destination: u_Axi_CDC/awFifo/_zz_ram_port1_reg[1]/D
|
|
(rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Path Group: (none)
|
|
Path Type: Hold (Min at Slow Process Corner)
|
|
Data Path Delay: 1.215ns (logic 1.056ns (86.901%) route 0.159ns (13.099%))
|
|
Logic Levels: 0
|
|
Clock Path Skew: -0.387ns (DCD - SCD - CPR)
|
|
Destination Clock Delay (DCD): -2.397ns
|
|
Source Clock Delay (SCD): -2.009ns
|
|
Clock Pessimism Removal (CPR): -0.000ns
|
|
Clock Uncertainty: 0.194ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Discrete Jitter (DJ): 0.130ns
|
|
Phase Error (PE): 0.120ns
|
|
Timing Exception: Asynchronous Clock Groups
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock cpu_clk rise edge) 0.000 0.000 r
|
|
K21 0.000 0.000 r clk (IN)
|
|
net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1
|
|
K21 IBUF (Prop_ibuf_I_O) 1.393 1.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O
|
|
net (fo=1, routed) 1.181 2.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll
|
|
PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0)
|
|
-8.248 -5.674 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0
|
|
net (fo=1, routed) 1.755 -3.919 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll
|
|
BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.091 -3.828 r pll_clk.u_clk_pll/inst/clkout1_buf/O
|
|
net (fo=6484, routed) 1.819 -2.009 u_Axi_CDC/awFifo/ram_reg_0_3_0_5/WCLK
|
|
SLICE_X20Y58 RAMD32 r u_Axi_CDC/awFifo/ram_reg_0_3_0_5/RAMA_D1/CLK
|
|
------------------------------------------------------------------- -------------------
|
|
SLICE_X20Y58 RAMD32 (Prop_ramd32_CLK_O)
|
|
1.056 -0.953 r u_Axi_CDC/awFifo/ram_reg_0_3_0_5/RAMA_D1/O
|
|
net (fo=1, routed) 0.159 -0.794 u_Axi_CDC/awFifo/_zz_ram_port10[1]
|
|
SLICE_X21Y58 FDRE r u_Axi_CDC/awFifo/_zz_ram_port1_reg[1]/D
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock sys_clk rise edge) 0.000 0.000 r
|
|
K21 0.000 0.000 r clk (IN)
|
|
net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1
|
|
K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O
|
|
net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll
|
|
PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1)
|
|
-8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1
|
|
net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll
|
|
BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O
|
|
net (fo=10004, routed) 1.945 -2.397 u_Axi_CDC/awFifo/sys_clk
|
|
SLICE_X21Y58 FDRE r u_Axi_CDC/awFifo/_zz_ram_port1_reg[1]/C
|
|
|
|
Slack: inf
|
|
Source: u_Axi_CDC/awFifo/ram_reg_0_3_0_5/RAMC_D1/CLK
|
|
(rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns})
|
|
Destination: u_Axi_CDC/awFifo/_zz_ram_port1_reg[5]/D
|
|
(rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Path Group: (none)
|
|
Path Type: Hold (Min at Slow Process Corner)
|
|
Data Path Delay: 1.218ns (logic 1.059ns (86.968%) route 0.159ns (13.032%))
|
|
Logic Levels: 0
|
|
Clock Path Skew: -0.387ns (DCD - SCD - CPR)
|
|
Destination Clock Delay (DCD): -2.397ns
|
|
Source Clock Delay (SCD): -2.009ns
|
|
Clock Pessimism Removal (CPR): -0.000ns
|
|
Clock Uncertainty: 0.194ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Discrete Jitter (DJ): 0.130ns
|
|
Phase Error (PE): 0.120ns
|
|
Timing Exception: Asynchronous Clock Groups
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock cpu_clk rise edge) 0.000 0.000 r
|
|
K21 0.000 0.000 r clk (IN)
|
|
net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1
|
|
K21 IBUF (Prop_ibuf_I_O) 1.393 1.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O
|
|
net (fo=1, routed) 1.181 2.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll
|
|
PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0)
|
|
-8.248 -5.674 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0
|
|
net (fo=1, routed) 1.755 -3.919 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll
|
|
BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.091 -3.828 r pll_clk.u_clk_pll/inst/clkout1_buf/O
|
|
net (fo=6484, routed) 1.819 -2.009 u_Axi_CDC/awFifo/ram_reg_0_3_0_5/WCLK
|
|
SLICE_X20Y58 RAMD32 r u_Axi_CDC/awFifo/ram_reg_0_3_0_5/RAMC_D1/CLK
|
|
------------------------------------------------------------------- -------------------
|
|
SLICE_X20Y58 RAMD32 (Prop_ramd32_CLK_O)
|
|
1.059 -0.950 r u_Axi_CDC/awFifo/ram_reg_0_3_0_5/RAMC_D1/O
|
|
net (fo=1, routed) 0.159 -0.792 u_Axi_CDC/awFifo/_zz_ram_port10[5]
|
|
SLICE_X21Y58 FDRE r u_Axi_CDC/awFifo/_zz_ram_port1_reg[5]/D
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock sys_clk rise edge) 0.000 0.000 r
|
|
K21 0.000 0.000 r clk (IN)
|
|
net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1
|
|
K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O
|
|
net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll
|
|
PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1)
|
|
-8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1
|
|
net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll
|
|
BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O
|
|
net (fo=10004, routed) 1.945 -2.397 u_Axi_CDC/awFifo/sys_clk
|
|
SLICE_X21Y58 FDRE r u_Axi_CDC/awFifo/_zz_ram_port1_reg[5]/C
|
|
|
|
Slack: inf
|
|
Source: u_Axi_CDC/awFifo/ram_reg_0_3_42_47/RAMB_D1/CLK
|
|
(rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns})
|
|
Destination: u_Axi_CDC/awFifo/_zz_ram_port1_reg[45]/D
|
|
(rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Path Group: (none)
|
|
Path Type: Hold (Min at Slow Process Corner)
|
|
Data Path Delay: 1.221ns (logic 1.062ns (86.996%) route 0.159ns (13.004%))
|
|
Logic Levels: 0
|
|
Clock Path Skew: -0.387ns (DCD - SCD - CPR)
|
|
Destination Clock Delay (DCD): -2.399ns
|
|
Source Clock Delay (SCD): -2.011ns
|
|
Clock Pessimism Removal (CPR): -0.000ns
|
|
Clock Uncertainty: 0.194ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Discrete Jitter (DJ): 0.130ns
|
|
Phase Error (PE): 0.120ns
|
|
Timing Exception: Asynchronous Clock Groups
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock cpu_clk rise edge) 0.000 0.000 r
|
|
K21 0.000 0.000 r clk (IN)
|
|
net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1
|
|
K21 IBUF (Prop_ibuf_I_O) 1.393 1.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O
|
|
net (fo=1, routed) 1.181 2.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll
|
|
PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0)
|
|
-8.248 -5.674 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0
|
|
net (fo=1, routed) 1.755 -3.919 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll
|
|
BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.091 -3.828 r pll_clk.u_clk_pll/inst/clkout1_buf/O
|
|
net (fo=6484, routed) 1.817 -2.011 u_Axi_CDC/awFifo/ram_reg_0_3_42_47/WCLK
|
|
SLICE_X18Y62 RAMD32 r u_Axi_CDC/awFifo/ram_reg_0_3_42_47/RAMB_D1/CLK
|
|
------------------------------------------------------------------- -------------------
|
|
SLICE_X18Y62 RAMD32 (Prop_ramd32_CLK_O)
|
|
1.062 -0.949 r u_Axi_CDC/awFifo/ram_reg_0_3_42_47/RAMB_D1/O
|
|
net (fo=1, routed) 0.159 -0.791 u_Axi_CDC/awFifo/_zz_ram_port10[45]
|
|
SLICE_X19Y62 FDRE r u_Axi_CDC/awFifo/_zz_ram_port1_reg[45]/D
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock sys_clk rise edge) 0.000 0.000 r
|
|
K21 0.000 0.000 r clk (IN)
|
|
net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1
|
|
K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O
|
|
net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll
|
|
PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1)
|
|
-8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1
|
|
net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll
|
|
BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O
|
|
net (fo=10004, routed) 1.943 -2.399 u_Axi_CDC/awFifo/sys_clk
|
|
SLICE_X19Y62 FDRE r u_Axi_CDC/awFifo/_zz_ram_port1_reg[45]/C
|
|
|
|
Slack: inf
|
|
Source: u_Axi_CDC/awFifo/ram_reg_0_3_0_5/RAMB_D1/CLK
|
|
(rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns})
|
|
Destination: u_Axi_CDC/awFifo/_zz_ram_port1_reg[3]/D
|
|
(rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Path Group: (none)
|
|
Path Type: Hold (Min at Slow Process Corner)
|
|
Data Path Delay: 1.221ns (logic 1.062ns (86.996%) route 0.159ns (13.004%))
|
|
Logic Levels: 0
|
|
Clock Path Skew: -0.387ns (DCD - SCD - CPR)
|
|
Destination Clock Delay (DCD): -2.397ns
|
|
Source Clock Delay (SCD): -2.009ns
|
|
Clock Pessimism Removal (CPR): -0.000ns
|
|
Clock Uncertainty: 0.194ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Discrete Jitter (DJ): 0.130ns
|
|
Phase Error (PE): 0.120ns
|
|
Timing Exception: Asynchronous Clock Groups
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock cpu_clk rise edge) 0.000 0.000 r
|
|
K21 0.000 0.000 r clk (IN)
|
|
net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1
|
|
K21 IBUF (Prop_ibuf_I_O) 1.393 1.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O
|
|
net (fo=1, routed) 1.181 2.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll
|
|
PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0)
|
|
-8.248 -5.674 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0
|
|
net (fo=1, routed) 1.755 -3.919 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll
|
|
BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.091 -3.828 r pll_clk.u_clk_pll/inst/clkout1_buf/O
|
|
net (fo=6484, routed) 1.819 -2.009 u_Axi_CDC/awFifo/ram_reg_0_3_0_5/WCLK
|
|
SLICE_X20Y58 RAMD32 r u_Axi_CDC/awFifo/ram_reg_0_3_0_5/RAMB_D1/CLK
|
|
------------------------------------------------------------------- -------------------
|
|
SLICE_X20Y58 RAMD32 (Prop_ramd32_CLK_O)
|
|
1.062 -0.947 r u_Axi_CDC/awFifo/ram_reg_0_3_0_5/RAMB_D1/O
|
|
net (fo=1, routed) 0.159 -0.789 u_Axi_CDC/awFifo/_zz_ram_port10[3]
|
|
SLICE_X21Y58 FDRE r u_Axi_CDC/awFifo/_zz_ram_port1_reg[3]/D
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock sys_clk rise edge) 0.000 0.000 r
|
|
K21 0.000 0.000 r clk (IN)
|
|
net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1
|
|
K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O
|
|
net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll
|
|
PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1)
|
|
-8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1
|
|
net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll
|
|
BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O
|
|
net (fo=10004, routed) 1.945 -2.397 u_Axi_CDC/awFifo/sys_clk
|
|
SLICE_X21Y58 FDRE r u_Axi_CDC/awFifo/_zz_ram_port1_reg[3]/C
|
|
|
|
Slack: inf
|
|
Source: u_Axi_CDC/arFifo/ram_reg_0_3_6_11/RAMA/CLK
|
|
(rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns})
|
|
Destination: u_Axi_CDC/arFifo/_zz_ram_port1_reg[6]/D
|
|
(rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Path Group: (none)
|
|
Path Type: Hold (Min at Slow Process Corner)
|
|
Data Path Delay: 1.246ns (logic 1.084ns (86.999%) route 0.162ns (13.001%))
|
|
Logic Levels: 0
|
|
Clock Path Skew: -0.386ns (DCD - SCD - CPR)
|
|
Destination Clock Delay (DCD): -2.411ns
|
|
Source Clock Delay (SCD): -2.024ns
|
|
Clock Pessimism Removal (CPR): -0.000ns
|
|
Clock Uncertainty: 0.194ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Discrete Jitter (DJ): 0.130ns
|
|
Phase Error (PE): 0.120ns
|
|
Timing Exception: Asynchronous Clock Groups
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock cpu_clk rise edge) 0.000 0.000 r
|
|
K21 0.000 0.000 r clk (IN)
|
|
net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1
|
|
K21 IBUF (Prop_ibuf_I_O) 1.393 1.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O
|
|
net (fo=1, routed) 1.181 2.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll
|
|
PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0)
|
|
-8.248 -5.674 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0
|
|
net (fo=1, routed) 1.755 -3.919 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll
|
|
BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.091 -3.828 r pll_clk.u_clk_pll/inst/clkout1_buf/O
|
|
net (fo=6484, routed) 1.804 -2.024 u_Axi_CDC/arFifo/ram_reg_0_3_6_11/WCLK
|
|
SLICE_X36Y60 RAMD32 r u_Axi_CDC/arFifo/ram_reg_0_3_6_11/RAMA/CLK
|
|
------------------------------------------------------------------- -------------------
|
|
SLICE_X36Y60 RAMD32 (Prop_ramd32_CLK_O)
|
|
1.084 -0.940 r u_Axi_CDC/arFifo/ram_reg_0_3_6_11/RAMA/O
|
|
net (fo=1, routed) 0.162 -0.778 u_Axi_CDC/arFifo/_zz_ram_port10__1[6]
|
|
SLICE_X37Y60 FDRE r u_Axi_CDC/arFifo/_zz_ram_port1_reg[6]/D
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock sys_clk rise edge) 0.000 0.000 r
|
|
K21 0.000 0.000 r clk (IN)
|
|
net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1
|
|
K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O
|
|
net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll
|
|
PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1)
|
|
-8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1
|
|
net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll
|
|
BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O
|
|
net (fo=10004, routed) 1.931 -2.411 u_Axi_CDC/arFifo/sys_clk
|
|
SLICE_X37Y60 FDRE r u_Axi_CDC/arFifo/_zz_ram_port1_reg[6]/C
|
|
|
|
Slack: inf
|
|
Source: u_Axi_CDC/arFifo/ram_reg_0_3_48_53/RAMA/CLK
|
|
(rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns})
|
|
Destination: u_Axi_CDC/arFifo/_zz_ram_port1_reg[48]/D
|
|
(rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Path Group: (none)
|
|
Path Type: Hold (Min at Slow Process Corner)
|
|
Data Path Delay: 1.246ns (logic 1.084ns (86.999%) route 0.162ns (13.001%))
|
|
Logic Levels: 0
|
|
Clock Path Skew: -0.389ns (DCD - SCD - CPR)
|
|
Destination Clock Delay (DCD): -2.408ns
|
|
Source Clock Delay (SCD): -2.018ns
|
|
Clock Pessimism Removal (CPR): -0.000ns
|
|
Clock Uncertainty: 0.194ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Discrete Jitter (DJ): 0.130ns
|
|
Phase Error (PE): 0.120ns
|
|
Timing Exception: Asynchronous Clock Groups
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock cpu_clk rise edge) 0.000 0.000 r
|
|
K21 0.000 0.000 r clk (IN)
|
|
net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1
|
|
K21 IBUF (Prop_ibuf_I_O) 1.393 1.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O
|
|
net (fo=1, routed) 1.181 2.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll
|
|
PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0)
|
|
-8.248 -5.674 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0
|
|
net (fo=1, routed) 1.755 -3.919 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll
|
|
BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.091 -3.828 r pll_clk.u_clk_pll/inst/clkout1_buf/O
|
|
net (fo=6484, routed) 1.810 -2.018 u_Axi_CDC/arFifo/ram_reg_0_3_48_53/WCLK
|
|
SLICE_X18Y70 RAMD32 r u_Axi_CDC/arFifo/ram_reg_0_3_48_53/RAMA/CLK
|
|
------------------------------------------------------------------- -------------------
|
|
SLICE_X18Y70 RAMD32 (Prop_ramd32_CLK_O)
|
|
1.084 -0.934 r u_Axi_CDC/arFifo/ram_reg_0_3_48_53/RAMA/O
|
|
net (fo=1, routed) 0.162 -0.772 u_Axi_CDC/arFifo/_zz_ram_port10__1[48]
|
|
SLICE_X19Y70 FDRE r u_Axi_CDC/arFifo/_zz_ram_port1_reg[48]/D
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock sys_clk rise edge) 0.000 0.000 r
|
|
K21 0.000 0.000 r clk (IN)
|
|
net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1
|
|
K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O
|
|
net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll
|
|
PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1)
|
|
-8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1
|
|
net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll
|
|
BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O
|
|
net (fo=10004, routed) 1.934 -2.408 u_Axi_CDC/arFifo/sys_clk
|
|
SLICE_X19Y70 FDRE r u_Axi_CDC/arFifo/_zz_ram_port1_reg[48]/C
|
|
|
|
Slack: inf
|
|
Source: u_Axi_CDC/arFifo/ram_reg_0_3_42_47/RAMB/CLK
|
|
(rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns})
|
|
Destination: u_Axi_CDC/arFifo/_zz_ram_port1_reg[44]/D
|
|
(rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Path Group: (none)
|
|
Path Type: Hold (Min at Slow Process Corner)
|
|
Data Path Delay: 1.245ns (logic 1.083ns (86.954%) route 0.162ns (13.046%))
|
|
Logic Levels: 0
|
|
Clock Path Skew: -0.388ns (DCD - SCD - CPR)
|
|
Destination Clock Delay (DCD): -2.404ns
|
|
Source Clock Delay (SCD): -2.015ns
|
|
Clock Pessimism Removal (CPR): -0.000ns
|
|
Clock Uncertainty: 0.194ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Discrete Jitter (DJ): 0.130ns
|
|
Phase Error (PE): 0.120ns
|
|
Timing Exception: Asynchronous Clock Groups
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock cpu_clk rise edge) 0.000 0.000 r
|
|
K21 0.000 0.000 r clk (IN)
|
|
net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1
|
|
K21 IBUF (Prop_ibuf_I_O) 1.393 1.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O
|
|
net (fo=1, routed) 1.181 2.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll
|
|
PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0)
|
|
-8.248 -5.674 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0
|
|
net (fo=1, routed) 1.755 -3.919 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll
|
|
BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.091 -3.828 r pll_clk.u_clk_pll/inst/clkout1_buf/O
|
|
net (fo=6484, routed) 1.813 -2.015 u_Axi_CDC/arFifo/ram_reg_0_3_42_47/WCLK
|
|
SLICE_X18Y67 RAMD32 r u_Axi_CDC/arFifo/ram_reg_0_3_42_47/RAMB/CLK
|
|
------------------------------------------------------------------- -------------------
|
|
SLICE_X18Y67 RAMD32 (Prop_ramd32_CLK_O)
|
|
1.083 -0.932 r u_Axi_CDC/arFifo/ram_reg_0_3_42_47/RAMB/O
|
|
net (fo=1, routed) 0.162 -0.770 u_Axi_CDC/arFifo/_zz_ram_port10__1[44]
|
|
SLICE_X19Y67 FDRE r u_Axi_CDC/arFifo/_zz_ram_port1_reg[44]/D
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock sys_clk rise edge) 0.000 0.000 r
|
|
K21 0.000 0.000 r clk (IN)
|
|
net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1
|
|
K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O
|
|
net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll
|
|
PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1)
|
|
-8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1
|
|
net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll
|
|
BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O
|
|
net (fo=10004, routed) 1.938 -2.404 u_Axi_CDC/arFifo/sys_clk
|
|
SLICE_X19Y67 FDRE r u_Axi_CDC/arFifo/_zz_ram_port1_reg[44]/C
|
|
|
|
Slack: inf
|
|
Source: u_Axi_CDC/arFifo/ram_reg_0_3_42_47/RAMA/CLK
|
|
(rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns})
|
|
Destination: u_Axi_CDC/arFifo/_zz_ram_port1_reg[42]/D
|
|
(rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Path Group: (none)
|
|
Path Type: Hold (Min at Slow Process Corner)
|
|
Data Path Delay: 1.246ns (logic 1.084ns (86.999%) route 0.162ns (13.001%))
|
|
Logic Levels: 0
|
|
Clock Path Skew: -0.388ns (DCD - SCD - CPR)
|
|
Destination Clock Delay (DCD): -2.404ns
|
|
Source Clock Delay (SCD): -2.015ns
|
|
Clock Pessimism Removal (CPR): -0.000ns
|
|
Clock Uncertainty: 0.194ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Discrete Jitter (DJ): 0.130ns
|
|
Phase Error (PE): 0.120ns
|
|
Timing Exception: Asynchronous Clock Groups
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock cpu_clk rise edge) 0.000 0.000 r
|
|
K21 0.000 0.000 r clk (IN)
|
|
net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1
|
|
K21 IBUF (Prop_ibuf_I_O) 1.393 1.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O
|
|
net (fo=1, routed) 1.181 2.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll
|
|
PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0)
|
|
-8.248 -5.674 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0
|
|
net (fo=1, routed) 1.755 -3.919 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll
|
|
BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.091 -3.828 r pll_clk.u_clk_pll/inst/clkout1_buf/O
|
|
net (fo=6484, routed) 1.813 -2.015 u_Axi_CDC/arFifo/ram_reg_0_3_42_47/WCLK
|
|
SLICE_X18Y67 RAMD32 r u_Axi_CDC/arFifo/ram_reg_0_3_42_47/RAMA/CLK
|
|
------------------------------------------------------------------- -------------------
|
|
SLICE_X18Y67 RAMD32 (Prop_ramd32_CLK_O)
|
|
1.084 -0.931 r u_Axi_CDC/arFifo/ram_reg_0_3_42_47/RAMA/O
|
|
net (fo=1, routed) 0.162 -0.769 u_Axi_CDC/arFifo/_zz_ram_port10__1[42]
|
|
SLICE_X19Y67 FDRE r u_Axi_CDC/arFifo/_zz_ram_port1_reg[42]/D
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock sys_clk rise edge) 0.000 0.000 r
|
|
K21 0.000 0.000 r clk (IN)
|
|
net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1
|
|
K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O
|
|
net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll
|
|
PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1)
|
|
-8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1
|
|
net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll
|
|
BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O
|
|
net (fo=10004, routed) 1.938 -2.404 u_Axi_CDC/arFifo/sys_clk
|
|
SLICE_X19Y67 FDRE r u_Axi_CDC/arFifo/_zz_ram_port1_reg[42]/C
|
|
|
|
Slack: inf
|
|
Source: u_Axi_CDC/arFifo/ram_reg_0_3_6_11/RAMC/CLK
|
|
(rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns})
|
|
Destination: u_Axi_CDC/arFifo/_zz_ram_port1_reg[10]/D
|
|
(rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Path Group: (none)
|
|
Path Type: Hold (Min at Slow Process Corner)
|
|
Data Path Delay: 1.329ns (logic 1.078ns (81.137%) route 0.251ns (18.863%))
|
|
Logic Levels: 0
|
|
Clock Path Skew: -0.386ns (DCD - SCD - CPR)
|
|
Destination Clock Delay (DCD): -2.411ns
|
|
Source Clock Delay (SCD): -2.024ns
|
|
Clock Pessimism Removal (CPR): -0.000ns
|
|
Clock Uncertainty: 0.194ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Discrete Jitter (DJ): 0.130ns
|
|
Phase Error (PE): 0.120ns
|
|
Timing Exception: Asynchronous Clock Groups
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock cpu_clk rise edge) 0.000 0.000 r
|
|
K21 0.000 0.000 r clk (IN)
|
|
net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1
|
|
K21 IBUF (Prop_ibuf_I_O) 1.393 1.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O
|
|
net (fo=1, routed) 1.181 2.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll
|
|
PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0)
|
|
-8.248 -5.674 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0
|
|
net (fo=1, routed) 1.755 -3.919 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll
|
|
BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.091 -3.828 r pll_clk.u_clk_pll/inst/clkout1_buf/O
|
|
net (fo=6484, routed) 1.804 -2.024 u_Axi_CDC/arFifo/ram_reg_0_3_6_11/WCLK
|
|
SLICE_X36Y60 RAMD32 r u_Axi_CDC/arFifo/ram_reg_0_3_6_11/RAMC/CLK
|
|
------------------------------------------------------------------- -------------------
|
|
SLICE_X36Y60 RAMD32 (Prop_ramd32_CLK_O)
|
|
1.078 -0.946 r u_Axi_CDC/arFifo/ram_reg_0_3_6_11/RAMC/O
|
|
net (fo=1, routed) 0.251 -0.696 u_Axi_CDC/arFifo/_zz_ram_port10__1[10]
|
|
SLICE_X37Y60 FDRE r u_Axi_CDC/arFifo/_zz_ram_port1_reg[10]/D
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock sys_clk rise edge) 0.000 0.000 r
|
|
K21 0.000 0.000 r clk (IN)
|
|
net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1
|
|
K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O
|
|
net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll
|
|
PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1)
|
|
-8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1
|
|
net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll
|
|
BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O
|
|
net (fo=10004, routed) 1.931 -2.411 u_Axi_CDC/arFifo/sys_clk
|
|
SLICE_X37Y60 FDRE r u_Axi_CDC/arFifo/_zz_ram_port1_reg[10]/C
|
|
|
|
Slack: inf
|
|
Source: u_Axi_CDC/arFifo/ram_reg_0_3_0_5/RAMB_D1/CLK
|
|
(rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns})
|
|
Destination: u_Axi_CDC/arFifo/_zz_ram_port1_reg[3]/D
|
|
(rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Path Group: (none)
|
|
Path Type: Hold (Min at Slow Process Corner)
|
|
Data Path Delay: 1.340ns (logic 1.062ns (79.263%) route 0.278ns (20.737%))
|
|
Logic Levels: 0
|
|
Clock Path Skew: -0.386ns (DCD - SCD - CPR)
|
|
Destination Clock Delay (DCD): -2.411ns
|
|
Source Clock Delay (SCD): -2.024ns
|
|
Clock Pessimism Removal (CPR): -0.000ns
|
|
Clock Uncertainty: 0.194ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Discrete Jitter (DJ): 0.130ns
|
|
Phase Error (PE): 0.120ns
|
|
Timing Exception: Asynchronous Clock Groups
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock cpu_clk rise edge) 0.000 0.000 r
|
|
K21 0.000 0.000 r clk (IN)
|
|
net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1
|
|
K21 IBUF (Prop_ibuf_I_O) 1.393 1.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O
|
|
net (fo=1, routed) 1.181 2.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll
|
|
PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0)
|
|
-8.248 -5.674 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0
|
|
net (fo=1, routed) 1.755 -3.919 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll
|
|
BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.091 -3.828 r pll_clk.u_clk_pll/inst/clkout1_buf/O
|
|
net (fo=6484, routed) 1.804 -2.024 u_Axi_CDC/arFifo/ram_reg_0_3_0_5/WCLK
|
|
SLICE_X36Y59 RAMD32 r u_Axi_CDC/arFifo/ram_reg_0_3_0_5/RAMB_D1/CLK
|
|
------------------------------------------------------------------- -------------------
|
|
SLICE_X36Y59 RAMD32 (Prop_ramd32_CLK_O)
|
|
1.062 -0.962 r u_Axi_CDC/arFifo/ram_reg_0_3_0_5/RAMB_D1/O
|
|
net (fo=1, routed) 0.278 -0.684 u_Axi_CDC/arFifo/_zz_ram_port10__1[3]
|
|
SLICE_X37Y60 FDRE r u_Axi_CDC/arFifo/_zz_ram_port1_reg[3]/D
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock sys_clk rise edge) 0.000 0.000 r
|
|
K21 0.000 0.000 r clk (IN)
|
|
net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1
|
|
K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O
|
|
net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll
|
|
PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1)
|
|
-8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1
|
|
net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll
|
|
BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O
|
|
net (fo=10004, routed) 1.931 -2.411 u_Axi_CDC/arFifo/sys_clk
|
|
SLICE_X37Y60 FDRE r u_Axi_CDC/arFifo/_zz_ram_port1_reg[3]/C
|
|
|
|
Slack: inf
|
|
Source: u_Axi_CDC/awFifo/ram_reg_0_3_48_53/RAMC_D1/CLK
|
|
(rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns})
|
|
Destination: u_Axi_CDC/awFifo/_zz_ram_port1_reg[53]/D
|
|
(rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Path Group: (none)
|
|
Path Type: Hold (Min at Slow Process Corner)
|
|
Data Path Delay: 1.338ns (logic 1.059ns (79.147%) route 0.279ns (20.853%))
|
|
Logic Levels: 0
|
|
Clock Path Skew: -0.389ns (DCD - SCD - CPR)
|
|
Destination Clock Delay (DCD): -2.411ns
|
|
Source Clock Delay (SCD): -2.021ns
|
|
Clock Pessimism Removal (CPR): -0.000ns
|
|
Clock Uncertainty: 0.194ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Discrete Jitter (DJ): 0.130ns
|
|
Phase Error (PE): 0.120ns
|
|
Timing Exception: Asynchronous Clock Groups
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock cpu_clk rise edge) 0.000 0.000 r
|
|
K21 0.000 0.000 r clk (IN)
|
|
net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1
|
|
K21 IBUF (Prop_ibuf_I_O) 1.393 1.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O
|
|
net (fo=1, routed) 1.181 2.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll
|
|
PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0)
|
|
-8.248 -5.674 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0
|
|
net (fo=1, routed) 1.755 -3.919 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll
|
|
BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.091 -3.828 r pll_clk.u_clk_pll/inst/clkout1_buf/O
|
|
net (fo=6484, routed) 1.807 -2.021 u_Axi_CDC/awFifo/ram_reg_0_3_48_53/WCLK
|
|
SLICE_X22Y69 RAMD32 r u_Axi_CDC/awFifo/ram_reg_0_3_48_53/RAMC_D1/CLK
|
|
------------------------------------------------------------------- -------------------
|
|
SLICE_X22Y69 RAMD32 (Prop_ramd32_CLK_O)
|
|
1.059 -0.962 r u_Axi_CDC/awFifo/ram_reg_0_3_48_53/RAMC_D1/O
|
|
net (fo=1, routed) 0.279 -0.683 u_Axi_CDC/awFifo/_zz_ram_port10[53]
|
|
SLICE_X23Y71 FDRE r u_Axi_CDC/awFifo/_zz_ram_port1_reg[53]/D
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock sys_clk rise edge) 0.000 0.000 r
|
|
K21 0.000 0.000 r clk (IN)
|
|
net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1
|
|
K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O
|
|
net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll
|
|
PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1)
|
|
-8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1
|
|
net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll
|
|
BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O
|
|
net (fo=10004, routed) 1.931 -2.411 u_Axi_CDC/awFifo/sys_clk
|
|
SLICE_X23Y71 FDRE r u_Axi_CDC/awFifo/_zz_ram_port1_reg[53]/C
|
|
|
|
Slack: inf
|
|
Source: u_Axi_CDC/arFifo/ram_reg_0_3_36_41/RAMA_D1/CLK
|
|
(rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns})
|
|
Destination: u_Axi_CDC/arFifo/_zz_ram_port1_reg[37]/D
|
|
(rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Path Group: (none)
|
|
Path Type: Hold (Min at Slow Process Corner)
|
|
Data Path Delay: 1.334ns (logic 1.056ns (79.142%) route 0.278ns (20.858%))
|
|
Logic Levels: 0
|
|
Clock Path Skew: -0.386ns (DCD - SCD - CPR)
|
|
Destination Clock Delay (DCD): -2.404ns
|
|
Source Clock Delay (SCD): -2.017ns
|
|
Clock Pessimism Removal (CPR): -0.000ns
|
|
Clock Uncertainty: 0.194ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Discrete Jitter (DJ): 0.130ns
|
|
Phase Error (PE): 0.120ns
|
|
Timing Exception: Asynchronous Clock Groups
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock cpu_clk rise edge) 0.000 0.000 r
|
|
K21 0.000 0.000 r clk (IN)
|
|
net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1
|
|
K21 IBUF (Prop_ibuf_I_O) 1.393 1.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O
|
|
net (fo=1, routed) 1.181 2.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll
|
|
PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0)
|
|
-8.248 -5.674 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0
|
|
net (fo=1, routed) 1.755 -3.919 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll
|
|
BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.091 -3.828 r pll_clk.u_clk_pll/inst/clkout1_buf/O
|
|
net (fo=6484, routed) 1.811 -2.017 u_Axi_CDC/arFifo/ram_reg_0_3_36_41/WCLK
|
|
SLICE_X18Y68 RAMD32 r u_Axi_CDC/arFifo/ram_reg_0_3_36_41/RAMA_D1/CLK
|
|
------------------------------------------------------------------- -------------------
|
|
SLICE_X18Y68 RAMD32 (Prop_ramd32_CLK_O)
|
|
1.056 -0.961 r u_Axi_CDC/arFifo/ram_reg_0_3_36_41/RAMA_D1/O
|
|
net (fo=1, routed) 0.278 -0.683 u_Axi_CDC/arFifo/_zz_ram_port10__1[37]
|
|
SLICE_X19Y67 FDRE r u_Axi_CDC/arFifo/_zz_ram_port1_reg[37]/D
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock sys_clk rise edge) 0.000 0.000 r
|
|
K21 0.000 0.000 r clk (IN)
|
|
net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1
|
|
K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O
|
|
net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll
|
|
PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1)
|
|
-8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1
|
|
net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll
|
|
BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O
|
|
net (fo=10004, routed) 1.938 -2.404 u_Axi_CDC/arFifo/sys_clk
|
|
SLICE_X19Y67 FDRE r u_Axi_CDC/arFifo/_zz_ram_port1_reg[37]/C
|
|
|
|
Slack: inf
|
|
Source: u_Axi_CDC/arFifo/ram_reg_0_3_48_53/RAMB_D1/CLK
|
|
(rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns})
|
|
Destination: u_Axi_CDC/arFifo/_zz_ram_port1_reg[51]/D
|
|
(rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Path Group: (none)
|
|
Path Type: Hold (Min at Slow Process Corner)
|
|
Data Path Delay: 1.340ns (logic 1.062ns (79.249%) route 0.278ns (20.751%))
|
|
Logic Levels: 0
|
|
Clock Path Skew: -0.393ns (DCD - SCD - CPR)
|
|
Destination Clock Delay (DCD): -2.412ns
|
|
Source Clock Delay (SCD): -2.018ns
|
|
Clock Pessimism Removal (CPR): -0.000ns
|
|
Clock Uncertainty: 0.194ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Discrete Jitter (DJ): 0.130ns
|
|
Phase Error (PE): 0.120ns
|
|
Timing Exception: Asynchronous Clock Groups
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock cpu_clk rise edge) 0.000 0.000 r
|
|
K21 0.000 0.000 r clk (IN)
|
|
net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1
|
|
K21 IBUF (Prop_ibuf_I_O) 1.393 1.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O
|
|
net (fo=1, routed) 1.181 2.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll
|
|
PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0)
|
|
-8.248 -5.674 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0
|
|
net (fo=1, routed) 1.755 -3.919 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll
|
|
BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.091 -3.828 r pll_clk.u_clk_pll/inst/clkout1_buf/O
|
|
net (fo=6484, routed) 1.810 -2.018 u_Axi_CDC/arFifo/ram_reg_0_3_48_53/WCLK
|
|
SLICE_X18Y70 RAMD32 r u_Axi_CDC/arFifo/ram_reg_0_3_48_53/RAMB_D1/CLK
|
|
------------------------------------------------------------------- -------------------
|
|
SLICE_X18Y70 RAMD32 (Prop_ramd32_CLK_O)
|
|
1.062 -0.956 r u_Axi_CDC/arFifo/ram_reg_0_3_48_53/RAMB_D1/O
|
|
net (fo=1, routed) 0.278 -0.678 u_Axi_CDC/arFifo/_zz_ram_port10__1[51]
|
|
SLICE_X18Y72 FDRE r u_Axi_CDC/arFifo/_zz_ram_port1_reg[51]/D
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock sys_clk rise edge) 0.000 0.000 r
|
|
K21 0.000 0.000 r clk (IN)
|
|
net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1
|
|
K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O
|
|
net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll
|
|
PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1)
|
|
-8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1
|
|
net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll
|
|
BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O
|
|
net (fo=10004, routed) 1.930 -2.412 u_Axi_CDC/arFifo/sys_clk
|
|
SLICE_X18Y72 FDRE r u_Axi_CDC/arFifo/_zz_ram_port1_reg[51]/C
|
|
|
|
Slack: inf
|
|
Source: u_Axi_CDC/awFifo/ram_reg_0_3_36_41/RAMA_D1/CLK
|
|
(rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns})
|
|
Destination: u_Axi_CDC/awFifo/_zz_ram_port1_reg[37]/D
|
|
(rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Path Group: (none)
|
|
Path Type: Hold (Min at Slow Process Corner)
|
|
Data Path Delay: 1.337ns (logic 1.056ns (79.009%) route 0.281ns (20.991%))
|
|
Logic Levels: 0
|
|
Clock Path Skew: -0.389ns (DCD - SCD - CPR)
|
|
Destination Clock Delay (DCD): -2.403ns
|
|
Source Clock Delay (SCD): -2.013ns
|
|
Clock Pessimism Removal (CPR): -0.000ns
|
|
Clock Uncertainty: 0.194ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Discrete Jitter (DJ): 0.130ns
|
|
Phase Error (PE): 0.120ns
|
|
Timing Exception: Asynchronous Clock Groups
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock cpu_clk rise edge) 0.000 0.000 r
|
|
K21 0.000 0.000 r clk (IN)
|
|
net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1
|
|
K21 IBUF (Prop_ibuf_I_O) 1.393 1.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O
|
|
net (fo=1, routed) 1.181 2.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll
|
|
PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0)
|
|
-8.248 -5.674 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0
|
|
net (fo=1, routed) 1.755 -3.919 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll
|
|
BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.091 -3.828 r pll_clk.u_clk_pll/inst/clkout1_buf/O
|
|
net (fo=6484, routed) 1.815 -2.013 u_Axi_CDC/awFifo/ram_reg_0_3_36_41/WCLK
|
|
SLICE_X16Y65 RAMD32 r u_Axi_CDC/awFifo/ram_reg_0_3_36_41/RAMA_D1/CLK
|
|
------------------------------------------------------------------- -------------------
|
|
SLICE_X16Y65 RAMD32 (Prop_ramd32_CLK_O)
|
|
1.056 -0.957 r u_Axi_CDC/awFifo/ram_reg_0_3_36_41/RAMA_D1/O
|
|
net (fo=1, routed) 0.281 -0.677 u_Axi_CDC/awFifo/_zz_ram_port10[37]
|
|
SLICE_X19Y66 FDRE r u_Axi_CDC/awFifo/_zz_ram_port1_reg[37]/D
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock sys_clk rise edge) 0.000 0.000 r
|
|
K21 0.000 0.000 r clk (IN)
|
|
net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1
|
|
K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O
|
|
net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll
|
|
PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1)
|
|
-8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1
|
|
net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll
|
|
BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O
|
|
net (fo=10004, routed) 1.939 -2.403 u_Axi_CDC/awFifo/sys_clk
|
|
SLICE_X19Y66 FDRE r u_Axi_CDC/awFifo/_zz_ram_port1_reg[37]/C
|
|
|
|
Slack: inf
|
|
Source: u_Axi_CDC/awFifo/ram_reg_0_3_48_53/RAMC/CLK
|
|
(rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns})
|
|
Destination: u_Axi_CDC/awFifo/_zz_ram_port1_reg[52]/D
|
|
(rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Path Group: (none)
|
|
Path Type: Hold (Min at Slow Process Corner)
|
|
Data Path Delay: 1.360ns (logic 1.078ns (79.282%) route 0.282ns (20.718%))
|
|
Logic Levels: 0
|
|
Clock Path Skew: -0.388ns (DCD - SCD - CPR)
|
|
Destination Clock Delay (DCD): -2.410ns
|
|
Source Clock Delay (SCD): -2.021ns
|
|
Clock Pessimism Removal (CPR): -0.000ns
|
|
Clock Uncertainty: 0.194ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Discrete Jitter (DJ): 0.130ns
|
|
Phase Error (PE): 0.120ns
|
|
Timing Exception: Asynchronous Clock Groups
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock cpu_clk rise edge) 0.000 0.000 r
|
|
K21 0.000 0.000 r clk (IN)
|
|
net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1
|
|
K21 IBUF (Prop_ibuf_I_O) 1.393 1.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O
|
|
net (fo=1, routed) 1.181 2.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll
|
|
PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0)
|
|
-8.248 -5.674 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0
|
|
net (fo=1, routed) 1.755 -3.919 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll
|
|
BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.091 -3.828 r pll_clk.u_clk_pll/inst/clkout1_buf/O
|
|
net (fo=6484, routed) 1.807 -2.021 u_Axi_CDC/awFifo/ram_reg_0_3_48_53/WCLK
|
|
SLICE_X22Y69 RAMD32 r u_Axi_CDC/awFifo/ram_reg_0_3_48_53/RAMC/CLK
|
|
------------------------------------------------------------------- -------------------
|
|
SLICE_X22Y69 RAMD32 (Prop_ramd32_CLK_O)
|
|
1.078 -0.943 r u_Axi_CDC/awFifo/ram_reg_0_3_48_53/RAMC/O
|
|
net (fo=1, routed) 0.282 -0.662 u_Axi_CDC/awFifo/_zz_ram_port10[52]
|
|
SLICE_X23Y70 FDRE r u_Axi_CDC/awFifo/_zz_ram_port1_reg[52]/D
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock sys_clk rise edge) 0.000 0.000 r
|
|
K21 0.000 0.000 r clk (IN)
|
|
net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1
|
|
K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O
|
|
net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll
|
|
PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1)
|
|
-8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1
|
|
net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll
|
|
BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O
|
|
net (fo=10004, routed) 1.932 -2.410 u_Axi_CDC/awFifo/sys_clk
|
|
SLICE_X23Y70 FDRE r u_Axi_CDC/awFifo/_zz_ram_port1_reg[52]/C
|
|
|
|
Slack: inf
|
|
Source: u_Axi_CDC/awFifo/ram_reg_0_3_0_5/RAMB/CLK
|
|
(rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns})
|
|
Destination: u_Axi_CDC/awFifo/_zz_ram_port1_reg[2]/D
|
|
(rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Path Group: (none)
|
|
Path Type: Hold (Min at Slow Process Corner)
|
|
Data Path Delay: 1.364ns (logic 1.083ns (79.398%) route 0.281ns (20.602%))
|
|
Logic Levels: 0
|
|
Clock Path Skew: -0.388ns (DCD - SCD - CPR)
|
|
Destination Clock Delay (DCD): -2.398ns
|
|
Source Clock Delay (SCD): -2.009ns
|
|
Clock Pessimism Removal (CPR): -0.000ns
|
|
Clock Uncertainty: 0.194ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Discrete Jitter (DJ): 0.130ns
|
|
Phase Error (PE): 0.120ns
|
|
Timing Exception: Asynchronous Clock Groups
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock cpu_clk rise edge) 0.000 0.000 r
|
|
K21 0.000 0.000 r clk (IN)
|
|
net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1
|
|
K21 IBUF (Prop_ibuf_I_O) 1.393 1.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O
|
|
net (fo=1, routed) 1.181 2.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll
|
|
PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0)
|
|
-8.248 -5.674 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0
|
|
net (fo=1, routed) 1.755 -3.919 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll
|
|
BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.091 -3.828 r pll_clk.u_clk_pll/inst/clkout1_buf/O
|
|
net (fo=6484, routed) 1.819 -2.009 u_Axi_CDC/awFifo/ram_reg_0_3_0_5/WCLK
|
|
SLICE_X20Y58 RAMD32 r u_Axi_CDC/awFifo/ram_reg_0_3_0_5/RAMB/CLK
|
|
------------------------------------------------------------------- -------------------
|
|
SLICE_X20Y58 RAMD32 (Prop_ramd32_CLK_O)
|
|
1.083 -0.926 r u_Axi_CDC/awFifo/ram_reg_0_3_0_5/RAMB/O
|
|
net (fo=1, routed) 0.281 -0.645 u_Axi_CDC/awFifo/_zz_ram_port10[2]
|
|
SLICE_X21Y59 FDRE r u_Axi_CDC/awFifo/_zz_ram_port1_reg[2]/D
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock sys_clk rise edge) 0.000 0.000 r
|
|
K21 0.000 0.000 r clk (IN)
|
|
net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1
|
|
K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O
|
|
net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll
|
|
PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1)
|
|
-8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1
|
|
net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll
|
|
BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O
|
|
net (fo=10004, routed) 1.944 -2.398 u_Axi_CDC/awFifo/sys_clk
|
|
SLICE_X21Y59 FDRE r u_Axi_CDC/awFifo/_zz_ram_port1_reg[2]/C
|
|
|
|
Slack: inf
|
|
Source: u_Axi_CDC/awFifo/ram_reg_0_3_36_41/RAMB_D1/CLK
|
|
(rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns})
|
|
Destination: u_Axi_CDC/awFifo/_zz_ram_port1_reg[39]/D
|
|
(rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Path Group: (none)
|
|
Path Type: Hold (Min at Slow Process Corner)
|
|
Data Path Delay: 1.411ns (logic 1.062ns (75.266%) route 0.349ns (24.734%))
|
|
Logic Levels: 0
|
|
Clock Path Skew: -0.388ns (DCD - SCD - CPR)
|
|
Destination Clock Delay (DCD): -2.402ns
|
|
Source Clock Delay (SCD): -2.013ns
|
|
Clock Pessimism Removal (CPR): -0.000ns
|
|
Clock Uncertainty: 0.194ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Discrete Jitter (DJ): 0.130ns
|
|
Phase Error (PE): 0.120ns
|
|
Timing Exception: Asynchronous Clock Groups
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock cpu_clk rise edge) 0.000 0.000 r
|
|
K21 0.000 0.000 r clk (IN)
|
|
net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1
|
|
K21 IBUF (Prop_ibuf_I_O) 1.393 1.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O
|
|
net (fo=1, routed) 1.181 2.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll
|
|
PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0)
|
|
-8.248 -5.674 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0
|
|
net (fo=1, routed) 1.755 -3.919 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll
|
|
BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.091 -3.828 r pll_clk.u_clk_pll/inst/clkout1_buf/O
|
|
net (fo=6484, routed) 1.815 -2.013 u_Axi_CDC/awFifo/ram_reg_0_3_36_41/WCLK
|
|
SLICE_X16Y65 RAMD32 r u_Axi_CDC/awFifo/ram_reg_0_3_36_41/RAMB_D1/CLK
|
|
------------------------------------------------------------------- -------------------
|
|
SLICE_X16Y65 RAMD32 (Prop_ramd32_CLK_O)
|
|
1.062 -0.951 r u_Axi_CDC/awFifo/ram_reg_0_3_36_41/RAMB_D1/O
|
|
net (fo=1, routed) 0.349 -0.602 u_Axi_CDC/awFifo/_zz_ram_port10[39]
|
|
SLICE_X18Y65 FDRE r u_Axi_CDC/awFifo/_zz_ram_port1_reg[39]/D
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock sys_clk rise edge) 0.000 0.000 r
|
|
K21 0.000 0.000 r clk (IN)
|
|
net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1
|
|
K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O
|
|
net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll
|
|
PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1)
|
|
-8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1
|
|
net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll
|
|
BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O
|
|
net (fo=10004, routed) 1.940 -2.402 u_Axi_CDC/awFifo/sys_clk
|
|
SLICE_X18Y65 FDRE r u_Axi_CDC/awFifo/_zz_ram_port1_reg[39]/C
|
|
|
|
Slack: inf
|
|
Source: u_Axi_CDC/awFifo/ram_reg_0_3_6_11/RAMB/CLK
|
|
(rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns})
|
|
Destination: u_Axi_CDC/awFifo/_zz_ram_port1_reg[8]/D
|
|
(rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Path Group: (none)
|
|
Path Type: Hold (Min at Slow Process Corner)
|
|
Data Path Delay: 1.432ns (logic 1.083ns (75.645%) route 0.349ns (24.355%))
|
|
Logic Levels: 0
|
|
Clock Path Skew: -0.387ns (DCD - SCD - CPR)
|
|
Destination Clock Delay (DCD): -2.396ns
|
|
Source Clock Delay (SCD): -2.008ns
|
|
Clock Pessimism Removal (CPR): -0.000ns
|
|
Clock Uncertainty: 0.194ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Discrete Jitter (DJ): 0.130ns
|
|
Phase Error (PE): 0.120ns
|
|
Timing Exception: Asynchronous Clock Groups
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock cpu_clk rise edge) 0.000 0.000 r
|
|
K21 0.000 0.000 r clk (IN)
|
|
net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1
|
|
K21 IBUF (Prop_ibuf_I_O) 1.393 1.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O
|
|
net (fo=1, routed) 1.181 2.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll
|
|
PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0)
|
|
-8.248 -5.674 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0
|
|
net (fo=1, routed) 1.755 -3.919 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll
|
|
BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.091 -3.828 r pll_clk.u_clk_pll/inst/clkout1_buf/O
|
|
net (fo=6484, routed) 1.820 -2.008 u_Axi_CDC/awFifo/ram_reg_0_3_6_11/WCLK
|
|
SLICE_X16Y57 RAMD32 r u_Axi_CDC/awFifo/ram_reg_0_3_6_11/RAMB/CLK
|
|
------------------------------------------------------------------- -------------------
|
|
SLICE_X16Y57 RAMD32 (Prop_ramd32_CLK_O)
|
|
1.083 -0.925 r u_Axi_CDC/awFifo/ram_reg_0_3_6_11/RAMB/O
|
|
net (fo=1, routed) 0.349 -0.577 u_Axi_CDC/awFifo/_zz_ram_port10[8]
|
|
SLICE_X15Y58 FDRE r u_Axi_CDC/awFifo/_zz_ram_port1_reg[8]/D
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock sys_clk rise edge) 0.000 0.000 r
|
|
K21 0.000 0.000 r clk (IN)
|
|
net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1
|
|
K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O
|
|
net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll
|
|
PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1)
|
|
-8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1
|
|
net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll
|
|
BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O
|
|
net (fo=10004, routed) 1.946 -2.396 u_Axi_CDC/awFifo/sys_clk
|
|
SLICE_X15Y58 FDRE r u_Axi_CDC/awFifo/_zz_ram_port1_reg[8]/C
|
|
|
|
Slack: inf
|
|
Source: u_Axi_CDC/awFifo/ram_reg_0_3_48_53/RAMA_D1/CLK
|
|
(rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns})
|
|
Destination: u_Axi_CDC/awFifo/_zz_ram_port1_reg[49]/D
|
|
(rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Path Group: (none)
|
|
Path Type: Hold (Min at Slow Process Corner)
|
|
Data Path Delay: 1.451ns (logic 1.056ns (72.768%) route 0.395ns (27.232%))
|
|
Logic Levels: 0
|
|
Clock Path Skew: -0.388ns (DCD - SCD - CPR)
|
|
Destination Clock Delay (DCD): -2.410ns
|
|
Source Clock Delay (SCD): -2.021ns
|
|
Clock Pessimism Removal (CPR): -0.000ns
|
|
Clock Uncertainty: 0.194ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Discrete Jitter (DJ): 0.130ns
|
|
Phase Error (PE): 0.120ns
|
|
Timing Exception: Asynchronous Clock Groups
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock cpu_clk rise edge) 0.000 0.000 r
|
|
K21 0.000 0.000 r clk (IN)
|
|
net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1
|
|
K21 IBUF (Prop_ibuf_I_O) 1.393 1.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O
|
|
net (fo=1, routed) 1.181 2.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll
|
|
PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0)
|
|
-8.248 -5.674 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0
|
|
net (fo=1, routed) 1.755 -3.919 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll
|
|
BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.091 -3.828 r pll_clk.u_clk_pll/inst/clkout1_buf/O
|
|
net (fo=6484, routed) 1.807 -2.021 u_Axi_CDC/awFifo/ram_reg_0_3_48_53/WCLK
|
|
SLICE_X22Y69 RAMD32 r u_Axi_CDC/awFifo/ram_reg_0_3_48_53/RAMA_D1/CLK
|
|
------------------------------------------------------------------- -------------------
|
|
SLICE_X22Y69 RAMD32 (Prop_ramd32_CLK_O)
|
|
1.056 -0.965 r u_Axi_CDC/awFifo/ram_reg_0_3_48_53/RAMA_D1/O
|
|
net (fo=1, routed) 0.395 -0.570 u_Axi_CDC/awFifo/_zz_ram_port10[49]
|
|
SLICE_X23Y70 FDRE r u_Axi_CDC/awFifo/_zz_ram_port1_reg[49]/D
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock sys_clk rise edge) 0.000 0.000 r
|
|
K21 0.000 0.000 r clk (IN)
|
|
net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1
|
|
K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O
|
|
net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll
|
|
PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1)
|
|
-8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1
|
|
net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll
|
|
BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O
|
|
net (fo=10004, routed) 1.932 -2.410 u_Axi_CDC/awFifo/sys_clk
|
|
SLICE_X23Y70 FDRE r u_Axi_CDC/awFifo/_zz_ram_port1_reg[49]/C
|
|
|
|
Slack: inf
|
|
Source: u_Axi_CDC/awFifo/ram_reg_0_3_48_53/RAMB_D1/CLK
|
|
(rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns})
|
|
Destination: u_Axi_CDC/awFifo/_zz_ram_port1_reg[51]/D
|
|
(rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Path Group: (none)
|
|
Path Type: Hold (Min at Slow Process Corner)
|
|
Data Path Delay: 1.454ns (logic 1.062ns (73.041%) route 0.392ns (26.959%))
|
|
Logic Levels: 0
|
|
Clock Path Skew: -0.388ns (DCD - SCD - CPR)
|
|
Destination Clock Delay (DCD): -2.410ns
|
|
Source Clock Delay (SCD): -2.021ns
|
|
Clock Pessimism Removal (CPR): -0.000ns
|
|
Clock Uncertainty: 0.194ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Discrete Jitter (DJ): 0.130ns
|
|
Phase Error (PE): 0.120ns
|
|
Timing Exception: Asynchronous Clock Groups
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock cpu_clk rise edge) 0.000 0.000 r
|
|
K21 0.000 0.000 r clk (IN)
|
|
net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1
|
|
K21 IBUF (Prop_ibuf_I_O) 1.393 1.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O
|
|
net (fo=1, routed) 1.181 2.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll
|
|
PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0)
|
|
-8.248 -5.674 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0
|
|
net (fo=1, routed) 1.755 -3.919 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll
|
|
BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.091 -3.828 r pll_clk.u_clk_pll/inst/clkout1_buf/O
|
|
net (fo=6484, routed) 1.807 -2.021 u_Axi_CDC/awFifo/ram_reg_0_3_48_53/WCLK
|
|
SLICE_X22Y69 RAMD32 r u_Axi_CDC/awFifo/ram_reg_0_3_48_53/RAMB_D1/CLK
|
|
------------------------------------------------------------------- -------------------
|
|
SLICE_X22Y69 RAMD32 (Prop_ramd32_CLK_O)
|
|
1.062 -0.959 r u_Axi_CDC/awFifo/ram_reg_0_3_48_53/RAMB_D1/O
|
|
net (fo=1, routed) 0.392 -0.567 u_Axi_CDC/awFifo/_zz_ram_port10[51]
|
|
SLICE_X23Y70 FDRE r u_Axi_CDC/awFifo/_zz_ram_port1_reg[51]/D
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock sys_clk rise edge) 0.000 0.000 r
|
|
K21 0.000 0.000 r clk (IN)
|
|
net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1
|
|
K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O
|
|
net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll
|
|
PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1)
|
|
-8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1
|
|
net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll
|
|
BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O
|
|
net (fo=10004, routed) 1.932 -2.410 u_Axi_CDC/awFifo/sys_clk
|
|
SLICE_X23Y70 FDRE r u_Axi_CDC/awFifo/_zz_ram_port1_reg[51]/C
|
|
|
|
Slack: inf
|
|
Source: u_Axi_CDC/awFifo/ram_reg_0_3_30_35/RAMC_D1/CLK
|
|
(rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns})
|
|
Destination: u_Axi_CDC/awFifo/_zz_ram_port1_reg[35]/D
|
|
(rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Path Group: (none)
|
|
Path Type: Hold (Min at Slow Process Corner)
|
|
Data Path Delay: 1.454ns (logic 1.059ns (72.851%) route 0.395ns (27.149%))
|
|
Logic Levels: 0
|
|
Clock Path Skew: -0.390ns (DCD - SCD - CPR)
|
|
Destination Clock Delay (DCD): -2.409ns
|
|
Source Clock Delay (SCD): -2.018ns
|
|
Clock Pessimism Removal (CPR): -0.000ns
|
|
Clock Uncertainty: 0.194ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Discrete Jitter (DJ): 0.130ns
|
|
Phase Error (PE): 0.120ns
|
|
Timing Exception: Asynchronous Clock Groups
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock cpu_clk rise edge) 0.000 0.000 r
|
|
K21 0.000 0.000 r clk (IN)
|
|
net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1
|
|
K21 IBUF (Prop_ibuf_I_O) 1.393 1.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O
|
|
net (fo=1, routed) 1.181 2.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll
|
|
PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0)
|
|
-8.248 -5.674 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0
|
|
net (fo=1, routed) 1.755 -3.919 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll
|
|
BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.091 -3.828 r pll_clk.u_clk_pll/inst/clkout1_buf/O
|
|
net (fo=6484, routed) 1.810 -2.018 u_Axi_CDC/awFifo/ram_reg_0_3_30_35/WCLK
|
|
SLICE_X22Y67 RAMD32 r u_Axi_CDC/awFifo/ram_reg_0_3_30_35/RAMC_D1/CLK
|
|
------------------------------------------------------------------- -------------------
|
|
SLICE_X22Y67 RAMD32 (Prop_ramd32_CLK_O)
|
|
1.059 -0.959 r u_Axi_CDC/awFifo/ram_reg_0_3_30_35/RAMC_D1/O
|
|
net (fo=1, routed) 0.395 -0.565 u_Axi_CDC/awFifo/_zz_ram_port10[35]
|
|
SLICE_X23Y69 FDRE r u_Axi_CDC/awFifo/_zz_ram_port1_reg[35]/D
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock sys_clk rise edge) 0.000 0.000 r
|
|
K21 0.000 0.000 r clk (IN)
|
|
net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1
|
|
K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O
|
|
net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll
|
|
PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1)
|
|
-8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1
|
|
net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll
|
|
BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O
|
|
net (fo=10004, routed) 1.933 -2.409 u_Axi_CDC/awFifo/sys_clk
|
|
SLICE_X23Y69 FDRE r u_Axi_CDC/awFifo/_zz_ram_port1_reg[35]/C
|
|
|
|
Slack: inf
|
|
Source: u_Axi_CDC/arFifo/ram_reg_0_3_30_35/RAMA_D1/CLK
|
|
(rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns})
|
|
Destination: u_Axi_CDC/arFifo/_zz_ram_port1_reg[31]/D
|
|
(rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Path Group: (none)
|
|
Path Type: Hold (Min at Slow Process Corner)
|
|
Data Path Delay: 1.453ns (logic 1.056ns (72.668%) route 0.397ns (27.332%))
|
|
Logic Levels: 0
|
|
Clock Path Skew: -0.390ns (DCD - SCD - CPR)
|
|
Destination Clock Delay (DCD): -2.408ns
|
|
Source Clock Delay (SCD): -2.017ns
|
|
Clock Pessimism Removal (CPR): -0.000ns
|
|
Clock Uncertainty: 0.194ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Discrete Jitter (DJ): 0.130ns
|
|
Phase Error (PE): 0.120ns
|
|
Timing Exception: Asynchronous Clock Groups
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock cpu_clk rise edge) 0.000 0.000 r
|
|
K21 0.000 0.000 r clk (IN)
|
|
net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1
|
|
K21 IBUF (Prop_ibuf_I_O) 1.393 1.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O
|
|
net (fo=1, routed) 1.181 2.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll
|
|
PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0)
|
|
-8.248 -5.674 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0
|
|
net (fo=1, routed) 1.755 -3.919 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll
|
|
BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.091 -3.828 r pll_clk.u_clk_pll/inst/clkout1_buf/O
|
|
net (fo=6484, routed) 1.811 -2.017 u_Axi_CDC/arFifo/ram_reg_0_3_30_35/WCLK
|
|
SLICE_X16Y68 RAMD32 r u_Axi_CDC/arFifo/ram_reg_0_3_30_35/RAMA_D1/CLK
|
|
------------------------------------------------------------------- -------------------
|
|
SLICE_X16Y68 RAMD32 (Prop_ramd32_CLK_O)
|
|
1.056 -0.961 r u_Axi_CDC/arFifo/ram_reg_0_3_30_35/RAMA_D1/O
|
|
net (fo=1, routed) 0.397 -0.564 u_Axi_CDC/arFifo/_zz_ram_port10__1[31]
|
|
SLICE_X16Y70 FDRE r u_Axi_CDC/arFifo/_zz_ram_port1_reg[31]/D
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock sys_clk rise edge) 0.000 0.000 r
|
|
K21 0.000 0.000 r clk (IN)
|
|
net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1
|
|
K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O
|
|
net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll
|
|
PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1)
|
|
-8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1
|
|
net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll
|
|
BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O
|
|
net (fo=10004, routed) 1.934 -2.408 u_Axi_CDC/arFifo/sys_clk
|
|
SLICE_X16Y70 FDRE r u_Axi_CDC/arFifo/_zz_ram_port1_reg[31]/C
|
|
|
|
Slack: inf
|
|
Source: u_Axi_CDC/awFifo/ram_reg_0_3_30_35/RAMB_D1/CLK
|
|
(rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns})
|
|
Destination: u_Axi_CDC/awFifo/_zz_ram_port1_reg[33]/D
|
|
(rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Path Group: (none)
|
|
Path Type: Hold (Min at Slow Process Corner)
|
|
Data Path Delay: 1.457ns (logic 1.062ns (72.904%) route 0.395ns (27.096%))
|
|
Logic Levels: 0
|
|
Clock Path Skew: -0.390ns (DCD - SCD - CPR)
|
|
Destination Clock Delay (DCD): -2.409ns
|
|
Source Clock Delay (SCD): -2.018ns
|
|
Clock Pessimism Removal (CPR): -0.000ns
|
|
Clock Uncertainty: 0.194ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Discrete Jitter (DJ): 0.130ns
|
|
Phase Error (PE): 0.120ns
|
|
Timing Exception: Asynchronous Clock Groups
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock cpu_clk rise edge) 0.000 0.000 r
|
|
K21 0.000 0.000 r clk (IN)
|
|
net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1
|
|
K21 IBUF (Prop_ibuf_I_O) 1.393 1.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O
|
|
net (fo=1, routed) 1.181 2.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll
|
|
PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0)
|
|
-8.248 -5.674 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0
|
|
net (fo=1, routed) 1.755 -3.919 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll
|
|
BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.091 -3.828 r pll_clk.u_clk_pll/inst/clkout1_buf/O
|
|
net (fo=6484, routed) 1.810 -2.018 u_Axi_CDC/awFifo/ram_reg_0_3_30_35/WCLK
|
|
SLICE_X22Y67 RAMD32 r u_Axi_CDC/awFifo/ram_reg_0_3_30_35/RAMB_D1/CLK
|
|
------------------------------------------------------------------- -------------------
|
|
SLICE_X22Y67 RAMD32 (Prop_ramd32_CLK_O)
|
|
1.062 -0.956 r u_Axi_CDC/awFifo/ram_reg_0_3_30_35/RAMB_D1/O
|
|
net (fo=1, routed) 0.395 -0.562 u_Axi_CDC/awFifo/_zz_ram_port10[33]
|
|
SLICE_X23Y69 FDRE r u_Axi_CDC/awFifo/_zz_ram_port1_reg[33]/D
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock sys_clk rise edge) 0.000 0.000 r
|
|
K21 0.000 0.000 r clk (IN)
|
|
net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1
|
|
K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O
|
|
net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll
|
|
PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1)
|
|
-8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1
|
|
net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll
|
|
BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O
|
|
net (fo=10004, routed) 1.933 -2.409 u_Axi_CDC/awFifo/sys_clk
|
|
SLICE_X23Y69 FDRE r u_Axi_CDC/awFifo/_zz_ram_port1_reg[33]/C
|
|
|
|
Slack: inf
|
|
Source: u_Axi_CDC/arFifo/ram_reg_0_3_6_11/RAMB/CLK
|
|
(rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns})
|
|
Destination: u_Axi_CDC/arFifo/_zz_ram_port1_reg[8]/D
|
|
(rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Path Group: (none)
|
|
Path Type: Hold (Min at Slow Process Corner)
|
|
Data Path Delay: 1.482ns (logic 1.083ns (73.069%) route 0.399ns (26.931%))
|
|
Logic Levels: 0
|
|
Clock Path Skew: -0.386ns (DCD - SCD - CPR)
|
|
Destination Clock Delay (DCD): -2.411ns
|
|
Source Clock Delay (SCD): -2.024ns
|
|
Clock Pessimism Removal (CPR): -0.000ns
|
|
Clock Uncertainty: 0.194ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Discrete Jitter (DJ): 0.130ns
|
|
Phase Error (PE): 0.120ns
|
|
Timing Exception: Asynchronous Clock Groups
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock cpu_clk rise edge) 0.000 0.000 r
|
|
K21 0.000 0.000 r clk (IN)
|
|
net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1
|
|
K21 IBUF (Prop_ibuf_I_O) 1.393 1.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O
|
|
net (fo=1, routed) 1.181 2.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll
|
|
PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0)
|
|
-8.248 -5.674 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0
|
|
net (fo=1, routed) 1.755 -3.919 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll
|
|
BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.091 -3.828 r pll_clk.u_clk_pll/inst/clkout1_buf/O
|
|
net (fo=6484, routed) 1.804 -2.024 u_Axi_CDC/arFifo/ram_reg_0_3_6_11/WCLK
|
|
SLICE_X36Y60 RAMD32 r u_Axi_CDC/arFifo/ram_reg_0_3_6_11/RAMB/CLK
|
|
------------------------------------------------------------------- -------------------
|
|
SLICE_X36Y60 RAMD32 (Prop_ramd32_CLK_O)
|
|
1.083 -0.941 r u_Axi_CDC/arFifo/ram_reg_0_3_6_11/RAMB/O
|
|
net (fo=1, routed) 0.399 -0.542 u_Axi_CDC/arFifo/_zz_ram_port10__1[8]
|
|
SLICE_X37Y60 FDRE r u_Axi_CDC/arFifo/_zz_ram_port1_reg[8]/D
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock sys_clk rise edge) 0.000 0.000 r
|
|
K21 0.000 0.000 r clk (IN)
|
|
net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1
|
|
K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O
|
|
net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll
|
|
PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1)
|
|
-8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1
|
|
net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll
|
|
BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O
|
|
net (fo=10004, routed) 1.931 -2.411 u_Axi_CDC/arFifo/sys_clk
|
|
SLICE_X37Y60 FDRE r u_Axi_CDC/arFifo/_zz_ram_port1_reg[8]/C
|
|
|
|
Slack: inf
|
|
Source: u_Axi_CDC/awFifo/ram_reg_0_3_48_53/RAMB/CLK
|
|
(rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns})
|
|
Destination: u_Axi_CDC/awFifo/_zz_ram_port1_reg[50]/D
|
|
(rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Path Group: (none)
|
|
Path Type: Hold (Min at Slow Process Corner)
|
|
Data Path Delay: 1.482ns (logic 1.083ns (73.083%) route 0.399ns (26.917%))
|
|
Logic Levels: 0
|
|
Clock Path Skew: -0.389ns (DCD - SCD - CPR)
|
|
Destination Clock Delay (DCD): -2.411ns
|
|
Source Clock Delay (SCD): -2.021ns
|
|
Clock Pessimism Removal (CPR): -0.000ns
|
|
Clock Uncertainty: 0.194ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Discrete Jitter (DJ): 0.130ns
|
|
Phase Error (PE): 0.120ns
|
|
Timing Exception: Asynchronous Clock Groups
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock cpu_clk rise edge) 0.000 0.000 r
|
|
K21 0.000 0.000 r clk (IN)
|
|
net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1
|
|
K21 IBUF (Prop_ibuf_I_O) 1.393 1.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O
|
|
net (fo=1, routed) 1.181 2.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll
|
|
PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0)
|
|
-8.248 -5.674 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0
|
|
net (fo=1, routed) 1.755 -3.919 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll
|
|
BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.091 -3.828 r pll_clk.u_clk_pll/inst/clkout1_buf/O
|
|
net (fo=6484, routed) 1.807 -2.021 u_Axi_CDC/awFifo/ram_reg_0_3_48_53/WCLK
|
|
SLICE_X22Y69 RAMD32 r u_Axi_CDC/awFifo/ram_reg_0_3_48_53/RAMB/CLK
|
|
------------------------------------------------------------------- -------------------
|
|
SLICE_X22Y69 RAMD32 (Prop_ramd32_CLK_O)
|
|
1.083 -0.938 r u_Axi_CDC/awFifo/ram_reg_0_3_48_53/RAMB/O
|
|
net (fo=1, routed) 0.399 -0.539 u_Axi_CDC/awFifo/_zz_ram_port10[50]
|
|
SLICE_X23Y71 FDRE r u_Axi_CDC/awFifo/_zz_ram_port1_reg[50]/D
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock sys_clk rise edge) 0.000 0.000 r
|
|
K21 0.000 0.000 r clk (IN)
|
|
net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1
|
|
K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O
|
|
net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll
|
|
PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1)
|
|
-8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1
|
|
net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll
|
|
BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O
|
|
net (fo=10004, routed) 1.931 -2.411 u_Axi_CDC/awFifo/sys_clk
|
|
SLICE_X23Y71 FDRE r u_Axi_CDC/awFifo/_zz_ram_port1_reg[50]/C
|
|
|
|
Slack: inf
|
|
Source: u_Axi_CDC/arFifo/ram_reg_0_3_30_35/RAMC/CLK
|
|
(rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns})
|
|
Destination: u_Axi_CDC/arFifo/_zz_ram_port1_reg[34]/D
|
|
(rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Path Group: (none)
|
|
Path Type: Hold (Min at Slow Process Corner)
|
|
Data Path Delay: 1.479ns (logic 1.078ns (72.907%) route 0.401ns (27.093%))
|
|
Logic Levels: 0
|
|
Clock Path Skew: -0.391ns (DCD - SCD - CPR)
|
|
Destination Clock Delay (DCD): -2.409ns
|
|
Source Clock Delay (SCD): -2.017ns
|
|
Clock Pessimism Removal (CPR): -0.000ns
|
|
Clock Uncertainty: 0.194ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Discrete Jitter (DJ): 0.130ns
|
|
Phase Error (PE): 0.120ns
|
|
Timing Exception: Asynchronous Clock Groups
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock cpu_clk rise edge) 0.000 0.000 r
|
|
K21 0.000 0.000 r clk (IN)
|
|
net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1
|
|
K21 IBUF (Prop_ibuf_I_O) 1.393 1.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O
|
|
net (fo=1, routed) 1.181 2.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll
|
|
PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0)
|
|
-8.248 -5.674 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0
|
|
net (fo=1, routed) 1.755 -3.919 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll
|
|
BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.091 -3.828 r pll_clk.u_clk_pll/inst/clkout1_buf/O
|
|
net (fo=6484, routed) 1.811 -2.017 u_Axi_CDC/arFifo/ram_reg_0_3_30_35/WCLK
|
|
SLICE_X16Y68 RAMD32 r u_Axi_CDC/arFifo/ram_reg_0_3_30_35/RAMC/CLK
|
|
------------------------------------------------------------------- -------------------
|
|
SLICE_X16Y68 RAMD32 (Prop_ramd32_CLK_O)
|
|
1.078 -0.939 r u_Axi_CDC/arFifo/ram_reg_0_3_30_35/RAMC/O
|
|
net (fo=1, routed) 0.401 -0.539 u_Axi_CDC/arFifo/_zz_ram_port10__1[34]
|
|
SLICE_X17Y71 FDRE r u_Axi_CDC/arFifo/_zz_ram_port1_reg[34]/D
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock sys_clk rise edge) 0.000 0.000 r
|
|
K21 0.000 0.000 r clk (IN)
|
|
net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1
|
|
K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O
|
|
net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll
|
|
PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1)
|
|
-8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1
|
|
net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll
|
|
BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O
|
|
net (fo=10004, routed) 1.933 -2.409 u_Axi_CDC/arFifo/sys_clk
|
|
SLICE_X17Y71 FDRE r u_Axi_CDC/arFifo/_zz_ram_port1_reg[34]/C
|
|
|
|
Slack: inf
|
|
Source: u_Axi_CDC/arFifo/ram_reg_0_3_6_11/RAMA_D1/CLK
|
|
(rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns})
|
|
Destination: u_Axi_CDC/arFifo/_zz_ram_port1_reg[7]/D
|
|
(rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Path Group: (none)
|
|
Path Type: Hold (Min at Slow Process Corner)
|
|
Data Path Delay: 1.493ns (logic 1.056ns (70.750%) route 0.437ns (29.250%))
|
|
Logic Levels: 0
|
|
Clock Path Skew: -0.386ns (DCD - SCD - CPR)
|
|
Destination Clock Delay (DCD): -2.411ns
|
|
Source Clock Delay (SCD): -2.024ns
|
|
Clock Pessimism Removal (CPR): -0.000ns
|
|
Clock Uncertainty: 0.194ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Discrete Jitter (DJ): 0.130ns
|
|
Phase Error (PE): 0.120ns
|
|
Timing Exception: Asynchronous Clock Groups
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock cpu_clk rise edge) 0.000 0.000 r
|
|
K21 0.000 0.000 r clk (IN)
|
|
net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1
|
|
K21 IBUF (Prop_ibuf_I_O) 1.393 1.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O
|
|
net (fo=1, routed) 1.181 2.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll
|
|
PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0)
|
|
-8.248 -5.674 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0
|
|
net (fo=1, routed) 1.755 -3.919 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll
|
|
BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.091 -3.828 r pll_clk.u_clk_pll/inst/clkout1_buf/O
|
|
net (fo=6484, routed) 1.804 -2.024 u_Axi_CDC/arFifo/ram_reg_0_3_6_11/WCLK
|
|
SLICE_X36Y60 RAMD32 r u_Axi_CDC/arFifo/ram_reg_0_3_6_11/RAMA_D1/CLK
|
|
------------------------------------------------------------------- -------------------
|
|
SLICE_X36Y60 RAMD32 (Prop_ramd32_CLK_O)
|
|
1.056 -0.968 r u_Axi_CDC/arFifo/ram_reg_0_3_6_11/RAMA_D1/O
|
|
net (fo=1, routed) 0.437 -0.532 u_Axi_CDC/arFifo/_zz_ram_port10__1[7]
|
|
SLICE_X37Y60 FDRE r u_Axi_CDC/arFifo/_zz_ram_port1_reg[7]/D
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock sys_clk rise edge) 0.000 0.000 r
|
|
K21 0.000 0.000 r clk (IN)
|
|
net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1
|
|
K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O
|
|
net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll
|
|
PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1)
|
|
-8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1
|
|
net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll
|
|
BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O
|
|
net (fo=10004, routed) 1.931 -2.411 u_Axi_CDC/arFifo/sys_clk
|
|
SLICE_X37Y60 FDRE r u_Axi_CDC/arFifo/_zz_ram_port1_reg[7]/C
|
|
|
|
Slack: inf
|
|
Source: u_Axi_CDC/arFifo/ram_reg_0_3_48_53/RAMA_D1/CLK
|
|
(rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns})
|
|
Destination: u_Axi_CDC/arFifo/_zz_ram_port1_reg[49]/D
|
|
(rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Path Group: (none)
|
|
Path Type: Hold (Min at Slow Process Corner)
|
|
Data Path Delay: 1.493ns (logic 1.056ns (70.750%) route 0.437ns (29.250%))
|
|
Logic Levels: 0
|
|
Clock Path Skew: -0.389ns (DCD - SCD - CPR)
|
|
Destination Clock Delay (DCD): -2.408ns
|
|
Source Clock Delay (SCD): -2.018ns
|
|
Clock Pessimism Removal (CPR): -0.000ns
|
|
Clock Uncertainty: 0.194ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Discrete Jitter (DJ): 0.130ns
|
|
Phase Error (PE): 0.120ns
|
|
Timing Exception: Asynchronous Clock Groups
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock cpu_clk rise edge) 0.000 0.000 r
|
|
K21 0.000 0.000 r clk (IN)
|
|
net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1
|
|
K21 IBUF (Prop_ibuf_I_O) 1.393 1.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O
|
|
net (fo=1, routed) 1.181 2.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll
|
|
PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0)
|
|
-8.248 -5.674 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0
|
|
net (fo=1, routed) 1.755 -3.919 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll
|
|
BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.091 -3.828 r pll_clk.u_clk_pll/inst/clkout1_buf/O
|
|
net (fo=6484, routed) 1.810 -2.018 u_Axi_CDC/arFifo/ram_reg_0_3_48_53/WCLK
|
|
SLICE_X18Y70 RAMD32 r u_Axi_CDC/arFifo/ram_reg_0_3_48_53/RAMA_D1/CLK
|
|
------------------------------------------------------------------- -------------------
|
|
SLICE_X18Y70 RAMD32 (Prop_ramd32_CLK_O)
|
|
1.056 -0.962 r u_Axi_CDC/arFifo/ram_reg_0_3_48_53/RAMA_D1/O
|
|
net (fo=1, routed) 0.437 -0.526 u_Axi_CDC/arFifo/_zz_ram_port10__1[49]
|
|
SLICE_X19Y70 FDRE r u_Axi_CDC/arFifo/_zz_ram_port1_reg[49]/D
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock sys_clk rise edge) 0.000 0.000 r
|
|
K21 0.000 0.000 r clk (IN)
|
|
net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1
|
|
K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O
|
|
net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll
|
|
PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1)
|
|
-8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1
|
|
net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll
|
|
BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O
|
|
net (fo=10004, routed) 1.934 -2.408 u_Axi_CDC/arFifo/sys_clk
|
|
SLICE_X19Y70 FDRE r u_Axi_CDC/arFifo/_zz_ram_port1_reg[49]/C
|
|
|
|
Slack: inf
|
|
Source: u_Axi_CDC/arFifo/ram_reg_0_3_48_53/RAMC_D1/CLK
|
|
(rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns})
|
|
Destination: u_Axi_CDC/arFifo/_zz_ram_port1_reg[53]/D
|
|
(rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Path Group: (none)
|
|
Path Type: Hold (Min at Slow Process Corner)
|
|
Data Path Delay: 1.496ns (logic 1.059ns (70.775%) route 0.437ns (29.225%))
|
|
Logic Levels: 0
|
|
Clock Path Skew: -0.393ns (DCD - SCD - CPR)
|
|
Destination Clock Delay (DCD): -2.412ns
|
|
Source Clock Delay (SCD): -2.018ns
|
|
Clock Pessimism Removal (CPR): -0.000ns
|
|
Clock Uncertainty: 0.194ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Discrete Jitter (DJ): 0.130ns
|
|
Phase Error (PE): 0.120ns
|
|
Timing Exception: Asynchronous Clock Groups
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock cpu_clk rise edge) 0.000 0.000 r
|
|
K21 0.000 0.000 r clk (IN)
|
|
net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1
|
|
K21 IBUF (Prop_ibuf_I_O) 1.393 1.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O
|
|
net (fo=1, routed) 1.181 2.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll
|
|
PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0)
|
|
-8.248 -5.674 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0
|
|
net (fo=1, routed) 1.755 -3.919 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll
|
|
BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.091 -3.828 r pll_clk.u_clk_pll/inst/clkout1_buf/O
|
|
net (fo=6484, routed) 1.810 -2.018 u_Axi_CDC/arFifo/ram_reg_0_3_48_53/WCLK
|
|
SLICE_X18Y70 RAMD32 r u_Axi_CDC/arFifo/ram_reg_0_3_48_53/RAMC_D1/CLK
|
|
------------------------------------------------------------------- -------------------
|
|
SLICE_X18Y70 RAMD32 (Prop_ramd32_CLK_O)
|
|
1.059 -0.959 r u_Axi_CDC/arFifo/ram_reg_0_3_48_53/RAMC_D1/O
|
|
net (fo=1, routed) 0.437 -0.522 u_Axi_CDC/arFifo/_zz_ram_port10__1[53]
|
|
SLICE_X18Y72 FDRE r u_Axi_CDC/arFifo/_zz_ram_port1_reg[53]/D
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock sys_clk rise edge) 0.000 0.000 r
|
|
K21 0.000 0.000 r clk (IN)
|
|
net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1
|
|
K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O
|
|
net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll
|
|
PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1)
|
|
-8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1
|
|
net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll
|
|
BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O
|
|
net (fo=10004, routed) 1.930 -2.412 u_Axi_CDC/arFifo/sys_clk
|
|
SLICE_X18Y72 FDRE r u_Axi_CDC/arFifo/_zz_ram_port1_reg[53]/C
|
|
|
|
Slack: inf
|
|
Source: u_Axi_CDC/arFifo/ram_reg_0_3_36_41/RAMC_D1/CLK
|
|
(rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns})
|
|
Destination: u_Axi_CDC/arFifo/_zz_ram_port1_reg[41]/D
|
|
(rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Path Group: (none)
|
|
Path Type: Hold (Min at Slow Process Corner)
|
|
Data Path Delay: 1.497ns (logic 1.059ns (70.746%) route 0.438ns (29.254%))
|
|
Logic Levels: 0
|
|
Clock Path Skew: -0.389ns (DCD - SCD - CPR)
|
|
Destination Clock Delay (DCD): -2.407ns
|
|
Source Clock Delay (SCD): -2.017ns
|
|
Clock Pessimism Removal (CPR): -0.000ns
|
|
Clock Uncertainty: 0.194ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Discrete Jitter (DJ): 0.130ns
|
|
Phase Error (PE): 0.120ns
|
|
Timing Exception: Asynchronous Clock Groups
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock cpu_clk rise edge) 0.000 0.000 r
|
|
K21 0.000 0.000 r clk (IN)
|
|
net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1
|
|
K21 IBUF (Prop_ibuf_I_O) 1.393 1.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O
|
|
net (fo=1, routed) 1.181 2.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll
|
|
PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0)
|
|
-8.248 -5.674 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0
|
|
net (fo=1, routed) 1.755 -3.919 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll
|
|
BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.091 -3.828 r pll_clk.u_clk_pll/inst/clkout1_buf/O
|
|
net (fo=6484, routed) 1.811 -2.017 u_Axi_CDC/arFifo/ram_reg_0_3_36_41/WCLK
|
|
SLICE_X18Y68 RAMD32 r u_Axi_CDC/arFifo/ram_reg_0_3_36_41/RAMC_D1/CLK
|
|
------------------------------------------------------------------- -------------------
|
|
SLICE_X18Y68 RAMD32 (Prop_ramd32_CLK_O)
|
|
1.059 -0.958 r u_Axi_CDC/arFifo/ram_reg_0_3_36_41/RAMC_D1/O
|
|
net (fo=1, routed) 0.438 -0.520 u_Axi_CDC/arFifo/_zz_ram_port10__1[41]
|
|
SLICE_X20Y68 FDRE r u_Axi_CDC/arFifo/_zz_ram_port1_reg[41]/D
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock sys_clk rise edge) 0.000 0.000 r
|
|
K21 0.000 0.000 r clk (IN)
|
|
net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1
|
|
K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O
|
|
net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll
|
|
PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1)
|
|
-8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1
|
|
net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll
|
|
BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O
|
|
net (fo=10004, routed) 1.935 -2.407 u_Axi_CDC/arFifo/sys_clk
|
|
SLICE_X20Y68 FDRE r u_Axi_CDC/arFifo/_zz_ram_port1_reg[41]/C
|
|
|
|
Slack: inf
|
|
Source: u_Axi_CDC/awFifo/ram_reg_0_3_42_47/RAMC_D1/CLK
|
|
(rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns})
|
|
Destination: u_Axi_CDC/awFifo/_zz_ram_port1_reg[47]/D
|
|
(rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Path Group: (none)
|
|
Path Type: Hold (Min at Slow Process Corner)
|
|
Data Path Delay: 1.493ns (logic 1.059ns (70.929%) route 0.434ns (29.071%))
|
|
Logic Levels: 0
|
|
Clock Path Skew: -0.387ns (DCD - SCD - CPR)
|
|
Destination Clock Delay (DCD): -2.399ns
|
|
Source Clock Delay (SCD): -2.011ns
|
|
Clock Pessimism Removal (CPR): -0.000ns
|
|
Clock Uncertainty: 0.194ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Discrete Jitter (DJ): 0.130ns
|
|
Phase Error (PE): 0.120ns
|
|
Timing Exception: Asynchronous Clock Groups
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock cpu_clk rise edge) 0.000 0.000 r
|
|
K21 0.000 0.000 r clk (IN)
|
|
net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1
|
|
K21 IBUF (Prop_ibuf_I_O) 1.393 1.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O
|
|
net (fo=1, routed) 1.181 2.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll
|
|
PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0)
|
|
-8.248 -5.674 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0
|
|
net (fo=1, routed) 1.755 -3.919 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll
|
|
BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.091 -3.828 r pll_clk.u_clk_pll/inst/clkout1_buf/O
|
|
net (fo=6484, routed) 1.817 -2.011 u_Axi_CDC/awFifo/ram_reg_0_3_42_47/WCLK
|
|
SLICE_X18Y62 RAMD32 r u_Axi_CDC/awFifo/ram_reg_0_3_42_47/RAMC_D1/CLK
|
|
------------------------------------------------------------------- -------------------
|
|
SLICE_X18Y62 RAMD32 (Prop_ramd32_CLK_O)
|
|
1.059 -0.952 r u_Axi_CDC/awFifo/ram_reg_0_3_42_47/RAMC_D1/O
|
|
net (fo=1, routed) 0.434 -0.518 u_Axi_CDC/awFifo/_zz_ram_port10[47]
|
|
SLICE_X19Y62 FDRE r u_Axi_CDC/awFifo/_zz_ram_port1_reg[47]/D
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock sys_clk rise edge) 0.000 0.000 r
|
|
K21 0.000 0.000 r clk (IN)
|
|
net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1
|
|
K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O
|
|
net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll
|
|
PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1)
|
|
-8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1
|
|
net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll
|
|
BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O
|
|
net (fo=10004, routed) 1.943 -2.399 u_Axi_CDC/awFifo/sys_clk
|
|
SLICE_X19Y62 FDRE r u_Axi_CDC/awFifo/_zz_ram_port1_reg[47]/C
|
|
|
|
Slack: inf
|
|
Source: u_Axi_CDC/arFifo/ram_reg_0_3_0_5/RAMB/CLK
|
|
(rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns})
|
|
Destination: u_Axi_CDC/arFifo/_zz_ram_port1_reg[2]/D
|
|
(rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Path Group: (none)
|
|
Path Type: Hold (Min at Slow Process Corner)
|
|
Data Path Delay: 1.511ns (logic 1.083ns (71.691%) route 0.428ns (28.309%))
|
|
Logic Levels: 0
|
|
Clock Path Skew: -0.382ns (DCD - SCD - CPR)
|
|
Destination Clock Delay (DCD): -2.407ns
|
|
Source Clock Delay (SCD): -2.024ns
|
|
Clock Pessimism Removal (CPR): -0.000ns
|
|
Clock Uncertainty: 0.194ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Discrete Jitter (DJ): 0.130ns
|
|
Phase Error (PE): 0.120ns
|
|
Timing Exception: Asynchronous Clock Groups
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock cpu_clk rise edge) 0.000 0.000 r
|
|
K21 0.000 0.000 r clk (IN)
|
|
net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1
|
|
K21 IBUF (Prop_ibuf_I_O) 1.393 1.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O
|
|
net (fo=1, routed) 1.181 2.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll
|
|
PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0)
|
|
-8.248 -5.674 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0
|
|
net (fo=1, routed) 1.755 -3.919 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll
|
|
BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.091 -3.828 r pll_clk.u_clk_pll/inst/clkout1_buf/O
|
|
net (fo=6484, routed) 1.804 -2.024 u_Axi_CDC/arFifo/ram_reg_0_3_0_5/WCLK
|
|
SLICE_X36Y59 RAMD32 r u_Axi_CDC/arFifo/ram_reg_0_3_0_5/RAMB/CLK
|
|
------------------------------------------------------------------- -------------------
|
|
SLICE_X36Y59 RAMD32 (Prop_ramd32_CLK_O)
|
|
1.083 -0.941 r u_Axi_CDC/arFifo/ram_reg_0_3_0_5/RAMB/O
|
|
net (fo=1, routed) 0.428 -0.514 u_Axi_CDC/arFifo/_zz_ram_port10__1[2]
|
|
SLICE_X32Y60 FDRE r u_Axi_CDC/arFifo/_zz_ram_port1_reg[2]/D
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock sys_clk rise edge) 0.000 0.000 r
|
|
K21 0.000 0.000 r clk (IN)
|
|
net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1
|
|
K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O
|
|
net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll
|
|
PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1)
|
|
-8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1
|
|
net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll
|
|
BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O
|
|
net (fo=10004, routed) 1.935 -2.407 u_Axi_CDC/arFifo/sys_clk
|
|
SLICE_X32Y60 FDRE r u_Axi_CDC/arFifo/_zz_ram_port1_reg[2]/C
|
|
|
|
Slack: inf
|
|
Source: u_Axi_CDC/awFifo/ram_reg_0_3_36_41/RAMC_D1/CLK
|
|
(rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns})
|
|
Destination: u_Axi_CDC/awFifo/_zz_ram_port1_reg[41]/D
|
|
(rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Path Group: (none)
|
|
Path Type: Hold (Min at Slow Process Corner)
|
|
Data Path Delay: 1.504ns (logic 1.059ns (70.415%) route 0.445ns (29.585%))
|
|
Logic Levels: 0
|
|
Clock Path Skew: -0.388ns (DCD - SCD - CPR)
|
|
Destination Clock Delay (DCD): -2.402ns
|
|
Source Clock Delay (SCD): -2.013ns
|
|
Clock Pessimism Removal (CPR): -0.000ns
|
|
Clock Uncertainty: 0.194ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Discrete Jitter (DJ): 0.130ns
|
|
Phase Error (PE): 0.120ns
|
|
Timing Exception: Asynchronous Clock Groups
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock cpu_clk rise edge) 0.000 0.000 r
|
|
K21 0.000 0.000 r clk (IN)
|
|
net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1
|
|
K21 IBUF (Prop_ibuf_I_O) 1.393 1.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O
|
|
net (fo=1, routed) 1.181 2.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll
|
|
PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0)
|
|
-8.248 -5.674 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0
|
|
net (fo=1, routed) 1.755 -3.919 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll
|
|
BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.091 -3.828 r pll_clk.u_clk_pll/inst/clkout1_buf/O
|
|
net (fo=6484, routed) 1.815 -2.013 u_Axi_CDC/awFifo/ram_reg_0_3_36_41/WCLK
|
|
SLICE_X16Y65 RAMD32 r u_Axi_CDC/awFifo/ram_reg_0_3_36_41/RAMC_D1/CLK
|
|
------------------------------------------------------------------- -------------------
|
|
SLICE_X16Y65 RAMD32 (Prop_ramd32_CLK_O)
|
|
1.059 -0.954 r u_Axi_CDC/awFifo/ram_reg_0_3_36_41/RAMC_D1/O
|
|
net (fo=1, routed) 0.445 -0.509 u_Axi_CDC/awFifo/_zz_ram_port10[41]
|
|
SLICE_X18Y65 FDRE r u_Axi_CDC/awFifo/_zz_ram_port1_reg[41]/D
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock sys_clk rise edge) 0.000 0.000 r
|
|
K21 0.000 0.000 r clk (IN)
|
|
net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1
|
|
K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O
|
|
net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll
|
|
PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1)
|
|
-8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1
|
|
net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll
|
|
BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O
|
|
net (fo=10004, routed) 1.940 -2.402 u_Axi_CDC/awFifo/sys_clk
|
|
SLICE_X18Y65 FDRE r u_Axi_CDC/awFifo/_zz_ram_port1_reg[41]/C
|
|
|
|
|
|
|
|
|
|
|
|
--------------------------------------------------------------------------------------
|
|
Path Group: (none)
|
|
From Clock: clkfbout_clk_pll
|
|
To Clock:
|
|
|
|
Max Delay 0 Endpoints
|
|
Min Delay 1 Endpoint
|
|
--------------------------------------------------------------------------------------
|
|
|
|
|
|
Min Delay Paths
|
|
--------------------------------------------------------------------------------------
|
|
Slack: inf
|
|
Source: pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKFBOUT
|
|
(clock source 'clkfbout_clk_pll' {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Destination: pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKFBIN
|
|
Path Group: (none)
|
|
Path Type: Min at Slow Process Corner
|
|
Data Path Delay: 3.498ns (logic 0.091ns (2.602%) route 3.407ns (97.398%))
|
|
Logic Levels: 1 (BUFG=1)
|
|
Clock Uncertainty: 0.169ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
|
Total System Jitter (TSJ): 0.050ns
|
|
Discrete Jitter (DJ): 0.075ns
|
|
Phase Error (PE): 0.124ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock clkfbout_clk_pll rise edge)
|
|
0.000 0.000 r
|
|
K21 0.000 0.000 r clk (IN)
|
|
net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1
|
|
K21 IBUF (Prop_ibuf_I_O) 1.393 1.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O
|
|
net (fo=1, routed) 1.181 2.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll
|
|
------------------------------------------------------------------- -------------------
|
|
PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKFBOUT)
|
|
-8.248 -5.674 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKFBOUT
|
|
net (fo=1, routed) 1.755 -3.919 pll_clk.u_clk_pll/inst/clkfbout_clk_pll
|
|
BUFGCTRL_X0Y19 BUFG (Prop_bufg_I_O) 0.091 -3.828 r pll_clk.u_clk_pll/inst/clkf_buf/O
|
|
net (fo=1, routed) 1.652 -2.177 pll_clk.u_clk_pll/inst/clkfbout_buf_clk_pll
|
|
PLLE2_ADV_X0Y3 PLLE2_ADV r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKFBIN
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
|
|
|
|
|
|
|
|
--------------------------------------------------------------------------------------
|
|
Path Group: (none)
|
|
From Clock: sys_clk
|
|
To Clock:
|
|
|
|
Max Delay 0 Endpoints
|
|
Min Delay 41 Endpoints
|
|
--------------------------------------------------------------------------------------
|
|
|
|
|
|
Min Delay Paths
|
|
--------------------------------------------------------------------------------------
|
|
Slack: inf
|
|
Source: pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1
|
|
(clock source 'sys_clk' {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Destination: video_clk
|
|
(output port)
|
|
Path Group: (none)
|
|
Path Type: Min at Fast Process Corner
|
|
Data Path Delay: 2.614ns (logic 1.260ns (48.196%) route 1.354ns (51.804%))
|
|
Logic Levels: 2 (BUFG=1 OBUF=1)
|
|
Clock Uncertainty: 0.190ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
|
Total System Jitter (TSJ): 0.050ns
|
|
Discrete Jitter (DJ): 0.122ns
|
|
Phase Error (PE): 0.124ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock sys_clk rise edge) 0.000 0.000 r
|
|
K21 0.000 0.000 r clk (IN)
|
|
net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1
|
|
K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O
|
|
net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll
|
|
------------------------------------------------------------------- -------------------
|
|
PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1)
|
|
-2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1
|
|
net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll
|
|
BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O
|
|
net (fo=10004, routed) 0.794 -0.468 video_clk_OBUF
|
|
H22 OBUF (Prop_obuf_I_O) 1.234 0.766 r video_clk_OBUF_inst/O
|
|
net (fo=0) 0.000 0.766 video_clk
|
|
H22 r video_clk (OUT)
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
Slack: inf
|
|
Source: u_confreg/led_data_reg[0]_lopt_replica/C
|
|
(rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Destination: leds[0]
|
|
(output port)
|
|
Path Group: (none)
|
|
Path Type: Min at Fast Process Corner
|
|
Data Path Delay: 2.665ns (logic 1.416ns (53.147%) route 1.249ns (46.853%))
|
|
Logic Levels: 1 (OBUF=1)
|
|
Clock Uncertainty: 0.190ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
|
Total System Jitter (TSJ): 0.050ns
|
|
Discrete Jitter (DJ): 0.122ns
|
|
Phase Error (PE): 0.124ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock sys_clk rise edge) 0.000 0.000 r
|
|
K21 0.000 0.000 r clk (IN)
|
|
net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1
|
|
K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O
|
|
net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll
|
|
PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1)
|
|
-2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1
|
|
net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll
|
|
BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O
|
|
net (fo=10004, routed) 0.725 -0.537 u_confreg/sys_clk
|
|
SLICE_X0Y96 FDRE r u_confreg/led_data_reg[0]_lopt_replica/C
|
|
------------------------------------------------------------------- -------------------
|
|
SLICE_X0Y96 FDRE (Prop_fdre_C_Q) 0.141 -0.396 r u_confreg/led_data_reg[0]_lopt_replica/Q
|
|
net (fo=1, routed) 1.249 0.852 lopt
|
|
B24 OBUF (Prop_obuf_I_O) 1.275 2.128 r leds_OBUF[0]_inst/O
|
|
net (fo=0) 0.000 2.128 leds[0]
|
|
B24 r leds[0] (OUT)
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
Slack: inf
|
|
Source: u_confreg/led_data_reg[1]_lopt_replica/C
|
|
(rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Destination: leds[1]
|
|
(output port)
|
|
Path Group: (none)
|
|
Path Type: Min at Fast Process Corner
|
|
Data Path Delay: 2.771ns (logic 1.383ns (49.914%) route 1.388ns (50.086%))
|
|
Logic Levels: 1 (OBUF=1)
|
|
Clock Uncertainty: 0.190ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
|
Total System Jitter (TSJ): 0.050ns
|
|
Discrete Jitter (DJ): 0.122ns
|
|
Phase Error (PE): 0.124ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock sys_clk rise edge) 0.000 0.000 r
|
|
K21 0.000 0.000 r clk (IN)
|
|
net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1
|
|
K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O
|
|
net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll
|
|
PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1)
|
|
-2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1
|
|
net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll
|
|
BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O
|
|
net (fo=10004, routed) 0.726 -0.536 u_confreg/sys_clk
|
|
SLICE_X0Y98 FDRE r u_confreg/led_data_reg[1]_lopt_replica/C
|
|
------------------------------------------------------------------- -------------------
|
|
SLICE_X0Y98 FDRE (Prop_fdre_C_Q) 0.141 -0.395 r u_confreg/led_data_reg[1]_lopt_replica/Q
|
|
net (fo=1, routed) 1.388 0.992 lopt_7
|
|
E21 OBUF (Prop_obuf_I_O) 1.242 2.234 r leds_OBUF[1]_inst/O
|
|
net (fo=0) 0.000 2.234 leds[1]
|
|
E21 r leds[1] (OUT)
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
Slack: inf
|
|
Source: u_confreg/led_data_reg[7]_lopt_replica/C
|
|
(rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Destination: leds[7]
|
|
(output port)
|
|
Path Group: (none)
|
|
Path Type: Min at Fast Process Corner
|
|
Data Path Delay: 2.806ns (logic 1.454ns (51.806%) route 1.352ns (48.194%))
|
|
Logic Levels: 1 (OBUF=1)
|
|
Clock Uncertainty: 0.190ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
|
Total System Jitter (TSJ): 0.050ns
|
|
Discrete Jitter (DJ): 0.122ns
|
|
Phase Error (PE): 0.124ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock sys_clk rise edge) 0.000 0.000 r
|
|
K21 0.000 0.000 r clk (IN)
|
|
net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1
|
|
K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O
|
|
net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll
|
|
PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1)
|
|
-2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1
|
|
net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll
|
|
BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O
|
|
net (fo=10004, routed) 0.725 -0.537 u_confreg/sys_clk
|
|
SLICE_X0Y95 FDRE r u_confreg/led_data_reg[7]_lopt_replica/C
|
|
------------------------------------------------------------------- -------------------
|
|
SLICE_X0Y95 FDRE (Prop_fdre_C_Q) 0.128 -0.409 r u_confreg/led_data_reg[7]_lopt_replica/Q
|
|
net (fo=1, routed) 1.352 0.943 lopt_13
|
|
B22 OBUF (Prop_obuf_I_O) 1.326 2.268 r leds_OBUF[7]_inst/O
|
|
net (fo=0) 0.000 2.268 leds[7]
|
|
B22 r leds[7] (OUT)
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
Slack: inf
|
|
Source: u_confreg/u_digitaltube_controller/dpy1_reg_reg[7]/C
|
|
(rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Destination: dpy1[7]
|
|
(output port)
|
|
Path Group: (none)
|
|
Path Type: Min at Fast Process Corner
|
|
Data Path Delay: 2.807ns (logic 1.362ns (48.520%) route 1.445ns (51.480%))
|
|
Logic Levels: 1 (OBUF=1)
|
|
Clock Uncertainty: 0.190ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
|
Total System Jitter (TSJ): 0.050ns
|
|
Discrete Jitter (DJ): 0.122ns
|
|
Phase Error (PE): 0.124ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock sys_clk rise edge) 0.000 0.000 r
|
|
K21 0.000 0.000 r clk (IN)
|
|
net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1
|
|
K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O
|
|
net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll
|
|
PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1)
|
|
-2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1
|
|
net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll
|
|
BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O
|
|
net (fo=10004, routed) 0.726 -0.536 u_confreg/u_digitaltube_controller/sys_clk
|
|
SLICE_X1Y97 FDCE r u_confreg/u_digitaltube_controller/dpy1_reg_reg[7]/C
|
|
------------------------------------------------------------------- -------------------
|
|
SLICE_X1Y97 FDCE (Prop_fdce_C_Q) 0.141 -0.395 r u_confreg/u_digitaltube_controller/dpy1_reg_reg[7]/Q
|
|
net (fo=1, routed) 1.445 1.050 dpy1_OBUF[7]
|
|
G17 OBUF (Prop_obuf_I_O) 1.221 2.271 r dpy1_OBUF[7]_inst/O
|
|
net (fo=0) 0.000 2.271 dpy1[7]
|
|
G17 r dpy1[7] (OUT)
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
Slack: inf
|
|
Source: u_confreg/led_data_reg[13]_lopt_replica/C
|
|
(rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Destination: leds[13]
|
|
(output port)
|
|
Path Group: (none)
|
|
Path Type: Min at Fast Process Corner
|
|
Data Path Delay: 2.809ns (logic 1.412ns (50.266%) route 1.397ns (49.734%))
|
|
Logic Levels: 1 (OBUF=1)
|
|
Clock Uncertainty: 0.190ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
|
Total System Jitter (TSJ): 0.050ns
|
|
Discrete Jitter (DJ): 0.122ns
|
|
Phase Error (PE): 0.124ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock sys_clk rise edge) 0.000 0.000 r
|
|
K21 0.000 0.000 r clk (IN)
|
|
net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1
|
|
K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O
|
|
net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll
|
|
PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1)
|
|
-2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1
|
|
net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll
|
|
BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O
|
|
net (fo=10004, routed) 0.726 -0.536 u_confreg/sys_clk
|
|
SLICE_X1Y98 FDRE r u_confreg/led_data_reg[13]_lopt_replica/C
|
|
------------------------------------------------------------------- -------------------
|
|
SLICE_X1Y98 FDRE (Prop_fdre_C_Q) 0.141 -0.395 r u_confreg/led_data_reg[13]_lopt_replica/Q
|
|
net (fo=1, routed) 1.397 1.002 lopt_4
|
|
A22 OBUF (Prop_obuf_I_O) 1.271 2.273 r leds_OBUF[13]_inst/O
|
|
net (fo=0) 0.000 2.273 leds[13]
|
|
A22 r leds[13] (OUT)
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
Slack: inf
|
|
Source: u_confreg/led_data_reg[10]_lopt_replica/C
|
|
(rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Destination: leds[10]
|
|
(output port)
|
|
Path Group: (none)
|
|
Path Type: Min at Fast Process Corner
|
|
Data Path Delay: 2.819ns (logic 1.389ns (49.262%) route 1.430ns (50.738%))
|
|
Logic Levels: 1 (OBUF=1)
|
|
Clock Uncertainty: 0.190ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
|
Total System Jitter (TSJ): 0.050ns
|
|
Discrete Jitter (DJ): 0.122ns
|
|
Phase Error (PE): 0.124ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock sys_clk rise edge) 0.000 0.000 r
|
|
K21 0.000 0.000 r clk (IN)
|
|
net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1
|
|
K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O
|
|
net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll
|
|
PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1)
|
|
-2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1
|
|
net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll
|
|
BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O
|
|
net (fo=10004, routed) 0.721 -0.541 u_confreg/sys_clk
|
|
SLICE_X0Y86 FDRE r u_confreg/led_data_reg[10]_lopt_replica/C
|
|
------------------------------------------------------------------- -------------------
|
|
SLICE_X0Y86 FDRE (Prop_fdre_C_Q) 0.141 -0.400 r u_confreg/led_data_reg[10]_lopt_replica/Q
|
|
net (fo=1, routed) 1.430 1.030 lopt_1
|
|
D21 OBUF (Prop_obuf_I_O) 1.248 2.278 r leds_OBUF[10]_inst/O
|
|
net (fo=0) 0.000 2.278 leds[10]
|
|
D21 r leds[10] (OUT)
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
Slack: inf
|
|
Source: u_confreg/led_data_reg[14]_lopt_replica/C
|
|
(rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Destination: leds[14]
|
|
(output port)
|
|
Path Group: (none)
|
|
Path Type: Min at Fast Process Corner
|
|
Data Path Delay: 2.815ns (logic 1.404ns (49.886%) route 1.411ns (50.114%))
|
|
Logic Levels: 1 (OBUF=1)
|
|
Clock Uncertainty: 0.190ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
|
Total System Jitter (TSJ): 0.050ns
|
|
Discrete Jitter (DJ): 0.122ns
|
|
Phase Error (PE): 0.124ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock sys_clk rise edge) 0.000 0.000 r
|
|
K21 0.000 0.000 r clk (IN)
|
|
net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1
|
|
K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O
|
|
net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll
|
|
PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1)
|
|
-2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1
|
|
net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll
|
|
BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O
|
|
net (fo=10004, routed) 0.725 -0.537 u_confreg/sys_clk
|
|
SLICE_X0Y95 FDRE r u_confreg/led_data_reg[14]_lopt_replica/C
|
|
------------------------------------------------------------------- -------------------
|
|
SLICE_X0Y95 FDRE (Prop_fdre_C_Q) 0.141 -0.396 r u_confreg/led_data_reg[14]_lopt_replica/Q
|
|
net (fo=1, routed) 1.411 1.014 lopt_5
|
|
A20 OBUF (Prop_obuf_I_O) 1.263 2.278 r leds_OBUF[14]_inst/O
|
|
net (fo=0) 0.000 2.278 leds[14]
|
|
A20 r leds[14] (OUT)
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
Slack: inf
|
|
Source: u_axi_uart_controller/uart0/regs/transmitter/tx2rx_en_reg/C
|
|
(rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Destination: UART_TX
|
|
(output port)
|
|
Path Group: (none)
|
|
Path Type: Min at Fast Process Corner
|
|
Data Path Delay: 2.818ns (logic 1.033ns (36.656%) route 1.785ns (63.344%))
|
|
Logic Levels: 2 (LUT3=1 OBUFT=1)
|
|
Clock Uncertainty: 0.190ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
|
Total System Jitter (TSJ): 0.050ns
|
|
Discrete Jitter (DJ): 0.122ns
|
|
Phase Error (PE): 0.124ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock sys_clk rise edge) 0.000 0.000 r
|
|
K21 0.000 0.000 r clk (IN)
|
|
net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1
|
|
K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O
|
|
net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll
|
|
PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1)
|
|
-2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1
|
|
net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll
|
|
BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O
|
|
net (fo=10004, routed) 0.723 -0.539 u_axi_uart_controller/uart0/regs/transmitter/sys_clk
|
|
SLICE_X2Y60 FDRE r u_axi_uart_controller/uart0/regs/transmitter/tx2rx_en_reg/C
|
|
------------------------------------------------------------------- -------------------
|
|
SLICE_X2Y60 FDRE (Prop_fdre_C_Q) 0.164 -0.375 r u_axi_uart_controller/uart0/regs/transmitter/tx2rx_en_reg/Q
|
|
net (fo=2, routed) 0.232 -0.143 u_axi_uart_controller/uart0/regs/transmitter/tx2rx_en
|
|
SLICE_X3Y60 LUT3 (Prop_lut3_I0_O) 0.045 -0.098 r u_axi_uart_controller/uart0/regs/transmitter/UART_TX_IOBUF_inst_i_3/O
|
|
net (fo=1, routed) 1.553 1.455 UART_TX_IOBUF_inst/T
|
|
H18 OBUFT (TriStatD_obuft_T_O)
|
|
0.824 2.279 r UART_TX_IOBUF_inst/OBUFT/O
|
|
net (fo=1, unset) 0.000 2.279 UART_TX
|
|
H18 r UART_TX (INOUT)
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
Slack: inf
|
|
Source: u_axi_uart_controller/uart0/regs/mode_reg_reg[1]/C
|
|
(rising edge-triggered cell FDSE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Destination: UART_RX
|
|
(output port)
|
|
Path Group: (none)
|
|
Path Type: Min at Fast Process Corner
|
|
Data Path Delay: 2.902ns (logic 0.965ns (33.253%) route 1.937ns (66.747%))
|
|
Logic Levels: 1 (OBUFT=1)
|
|
Clock Uncertainty: 0.190ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
|
Total System Jitter (TSJ): 0.050ns
|
|
Discrete Jitter (DJ): 0.122ns
|
|
Phase Error (PE): 0.124ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock sys_clk rise edge) 0.000 0.000 r
|
|
K21 0.000 0.000 r clk (IN)
|
|
net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1
|
|
K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O
|
|
net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll
|
|
PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1)
|
|
-2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1
|
|
net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll
|
|
BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O
|
|
net (fo=10004, routed) 0.689 -0.573 u_axi_uart_controller/uart0/regs/sys_clk
|
|
SLICE_X9Y67 FDSE r u_axi_uart_controller/uart0/regs/mode_reg_reg[1]/C
|
|
------------------------------------------------------------------- -------------------
|
|
SLICE_X9Y67 FDSE (Prop_fdse_C_Q) 0.141 -0.432 r u_axi_uart_controller/uart0/regs/mode_reg_reg[1]/Q
|
|
net (fo=28, routed) 1.937 1.505 UART_RX_IOBUF_inst/T
|
|
J20 OBUFT (TriStatD_obuft_T_O)
|
|
0.824 2.329 r UART_RX_IOBUF_inst/OBUFT/O
|
|
net (fo=1, unset) 0.000 2.329 UART_RX
|
|
J20 r UART_RX (INOUT)
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
Slack: inf
|
|
Source: u_confreg/u_digitaltube_controller/dpy1_reg_reg[0]/C
|
|
(rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Destination: dpy1[0]
|
|
(output port)
|
|
Path Group: (none)
|
|
Path Type: Min at Fast Process Corner
|
|
Data Path Delay: 2.872ns (logic 1.407ns (48.983%) route 1.465ns (51.017%))
|
|
Logic Levels: 1 (OBUF=1)
|
|
Clock Uncertainty: 0.190ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
|
Total System Jitter (TSJ): 0.050ns
|
|
Discrete Jitter (DJ): 0.122ns
|
|
Phase Error (PE): 0.124ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock sys_clk rise edge) 0.000 0.000 r
|
|
K21 0.000 0.000 r clk (IN)
|
|
net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1
|
|
K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O
|
|
net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll
|
|
PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1)
|
|
-2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1
|
|
net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll
|
|
BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O
|
|
net (fo=10004, routed) 0.726 -0.536 u_confreg/u_digitaltube_controller/sys_clk
|
|
SLICE_X1Y97 FDCE r u_confreg/u_digitaltube_controller/dpy1_reg_reg[0]/C
|
|
------------------------------------------------------------------- -------------------
|
|
SLICE_X1Y97 FDCE (Prop_fdce_C_Q) 0.141 -0.395 r u_confreg/u_digitaltube_controller/dpy1_reg_reg[0]/Q
|
|
net (fo=1, routed) 1.465 1.070 dpy1_OBUF[0]
|
|
A17 OBUF (Prop_obuf_I_O) 1.266 2.336 r dpy1_OBUF[0]_inst/O
|
|
net (fo=0) 0.000 2.336 dpy1[0]
|
|
A17 r dpy1[0] (OUT)
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
Slack: inf
|
|
Source: u_confreg/u_digitaltube_controller/dpy1_reg_reg[5]/C
|
|
(rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Destination: dpy1[5]
|
|
(output port)
|
|
Path Group: (none)
|
|
Path Type: Min at Fast Process Corner
|
|
Data Path Delay: 2.877ns (logic 1.376ns (47.814%) route 1.502ns (52.186%))
|
|
Logic Levels: 1 (OBUF=1)
|
|
Clock Uncertainty: 0.190ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
|
Total System Jitter (TSJ): 0.050ns
|
|
Discrete Jitter (DJ): 0.122ns
|
|
Phase Error (PE): 0.124ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock sys_clk rise edge) 0.000 0.000 r
|
|
K21 0.000 0.000 r clk (IN)
|
|
net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1
|
|
K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O
|
|
net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll
|
|
PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1)
|
|
-2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1
|
|
net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll
|
|
BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O
|
|
net (fo=10004, routed) 0.726 -0.536 u_confreg/u_digitaltube_controller/sys_clk
|
|
SLICE_X0Y97 FDCE r u_confreg/u_digitaltube_controller/dpy1_reg_reg[5]/C
|
|
------------------------------------------------------------------- -------------------
|
|
SLICE_X0Y97 FDCE (Prop_fdce_C_Q) 0.141 -0.395 r u_confreg/u_digitaltube_controller/dpy1_reg_reg[5]/Q
|
|
net (fo=1, routed) 1.502 1.106 dpy1_OBUF[5]
|
|
G16 OBUF (Prop_obuf_I_O) 1.235 2.341 r dpy1_OBUF[5]_inst/O
|
|
net (fo=0) 0.000 2.341 dpy1[5]
|
|
G16 r dpy1[5] (OUT)
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
Slack: inf
|
|
Source: u_confreg/u_digitaltube_controller/dpy0_reg_reg[7]/C
|
|
(rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Destination: dpy0[7]
|
|
(output port)
|
|
Path Group: (none)
|
|
Path Type: Min at Fast Process Corner
|
|
Data Path Delay: 2.946ns (logic 1.386ns (47.054%) route 1.560ns (52.946%))
|
|
Logic Levels: 1 (OBUF=1)
|
|
Clock Uncertainty: 0.190ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
|
Total System Jitter (TSJ): 0.050ns
|
|
Discrete Jitter (DJ): 0.122ns
|
|
Phase Error (PE): 0.124ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock sys_clk rise edge) 0.000 0.000 r
|
|
K21 0.000 0.000 r clk (IN)
|
|
net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1
|
|
K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O
|
|
net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll
|
|
PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1)
|
|
-2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1
|
|
net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll
|
|
BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O
|
|
net (fo=10004, routed) 0.658 -0.605 u_confreg/u_digitaltube_controller/sys_clk
|
|
SLICE_X0Y101 FDCE r u_confreg/u_digitaltube_controller/dpy0_reg_reg[7]/C
|
|
------------------------------------------------------------------- -------------------
|
|
SLICE_X0Y101 FDCE (Prop_fdce_C_Q) 0.141 -0.464 r u_confreg/u_digitaltube_controller/dpy0_reg_reg[7]/Q
|
|
net (fo=1, routed) 1.560 1.096 dpy0_OBUF[7]
|
|
C17 OBUF (Prop_obuf_I_O) 1.245 2.341 r dpy0_OBUF[7]_inst/O
|
|
net (fo=0) 0.000 2.341 dpy0[7]
|
|
C17 r dpy0[7] (OUT)
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
Slack: inf
|
|
Source: u_confreg/u_digitaltube_controller/dpy0_reg_reg[6]/C
|
|
(rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Destination: dpy0[6]
|
|
(output port)
|
|
Path Group: (none)
|
|
Path Type: Min at Fast Process Corner
|
|
Data Path Delay: 2.958ns (logic 1.398ns (47.262%) route 1.560ns (52.738%))
|
|
Logic Levels: 1 (OBUF=1)
|
|
Clock Uncertainty: 0.190ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
|
Total System Jitter (TSJ): 0.050ns
|
|
Discrete Jitter (DJ): 0.122ns
|
|
Phase Error (PE): 0.124ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock sys_clk rise edge) 0.000 0.000 r
|
|
K21 0.000 0.000 r clk (IN)
|
|
net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1
|
|
K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O
|
|
net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll
|
|
PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1)
|
|
-2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1
|
|
net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll
|
|
BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O
|
|
net (fo=10004, routed) 0.658 -0.605 u_confreg/u_digitaltube_controller/sys_clk
|
|
SLICE_X0Y100 FDCE r u_confreg/u_digitaltube_controller/dpy0_reg_reg[6]/C
|
|
------------------------------------------------------------------- -------------------
|
|
SLICE_X0Y100 FDCE (Prop_fdce_C_Q) 0.141 -0.464 r u_confreg/u_digitaltube_controller/dpy0_reg_reg[6]/Q
|
|
net (fo=1, routed) 1.560 1.096 dpy0_OBUF[6]
|
|
B17 OBUF (Prop_obuf_I_O) 1.257 2.353 r dpy0_OBUF[6]_inst/O
|
|
net (fo=0) 0.000 2.353 dpy0[6]
|
|
B17 r dpy0[6] (OUT)
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
Slack: inf
|
|
Source: u_confreg/u_digitaltube_controller/dpy1_reg_reg[1]/C
|
|
(rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Destination: dpy1[1]
|
|
(output port)
|
|
Path Group: (none)
|
|
Path Type: Min at Fast Process Corner
|
|
Data Path Delay: 2.927ns (logic 1.391ns (47.509%) route 1.537ns (52.491%))
|
|
Logic Levels: 1 (OBUF=1)
|
|
Clock Uncertainty: 0.190ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
|
Total System Jitter (TSJ): 0.050ns
|
|
Discrete Jitter (DJ): 0.122ns
|
|
Phase Error (PE): 0.124ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock sys_clk rise edge) 0.000 0.000 r
|
|
K21 0.000 0.000 r clk (IN)
|
|
net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1
|
|
K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O
|
|
net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll
|
|
PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1)
|
|
-2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1
|
|
net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll
|
|
BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O
|
|
net (fo=10004, routed) 0.726 -0.536 u_confreg/u_digitaltube_controller/sys_clk
|
|
SLICE_X0Y97 FDCE r u_confreg/u_digitaltube_controller/dpy1_reg_reg[1]/C
|
|
------------------------------------------------------------------- -------------------
|
|
SLICE_X0Y97 FDCE (Prop_fdce_C_Q) 0.141 -0.395 r u_confreg/u_digitaltube_controller/dpy1_reg_reg[1]/Q
|
|
net (fo=1, routed) 1.537 1.141 dpy1_OBUF[1]
|
|
D16 OBUF (Prop_obuf_I_O) 1.250 2.391 r dpy1_OBUF[1]_inst/O
|
|
net (fo=0) 0.000 2.391 dpy1[1]
|
|
D16 r dpy1[1] (OUT)
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
Slack: inf
|
|
Source: u_confreg/u_digitaltube_controller/dpy1_reg_reg[4]/C
|
|
(rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Destination: dpy1[4]
|
|
(output port)
|
|
Path Group: (none)
|
|
Path Type: Min at Fast Process Corner
|
|
Data Path Delay: 2.966ns (logic 1.383ns (46.637%) route 1.583ns (53.363%))
|
|
Logic Levels: 1 (OBUF=1)
|
|
Clock Uncertainty: 0.190ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
|
Total System Jitter (TSJ): 0.050ns
|
|
Discrete Jitter (DJ): 0.122ns
|
|
Phase Error (PE): 0.124ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock sys_clk rise edge) 0.000 0.000 r
|
|
K21 0.000 0.000 r clk (IN)
|
|
net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1
|
|
K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O
|
|
net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll
|
|
PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1)
|
|
-2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1
|
|
net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll
|
|
BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O
|
|
net (fo=10004, routed) 0.726 -0.536 u_confreg/u_digitaltube_controller/sys_clk
|
|
SLICE_X1Y97 FDCE r u_confreg/u_digitaltube_controller/dpy1_reg_reg[4]/C
|
|
------------------------------------------------------------------- -------------------
|
|
SLICE_X1Y97 FDCE (Prop_fdce_C_Q) 0.141 -0.395 r u_confreg/u_digitaltube_controller/dpy1_reg_reg[4]/Q
|
|
net (fo=1, routed) 1.583 1.188 dpy1_OBUF[4]
|
|
E16 OBUF (Prop_obuf_I_O) 1.242 2.430 r dpy1_OBUF[4]_inst/O
|
|
net (fo=0) 0.000 2.430 dpy1[4]
|
|
E16 r dpy1[4] (OUT)
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
Slack: inf
|
|
Source: u_confreg/u_digitaltube_controller/dpy0_reg_reg[3]/C
|
|
(rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Destination: dpy0[3]
|
|
(output port)
|
|
Path Group: (none)
|
|
Path Type: Min at Fast Process Corner
|
|
Data Path Delay: 3.046ns (logic 1.415ns (46.436%) route 1.632ns (53.564%))
|
|
Logic Levels: 1 (OBUF=1)
|
|
Clock Uncertainty: 0.190ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
|
Total System Jitter (TSJ): 0.050ns
|
|
Discrete Jitter (DJ): 0.122ns
|
|
Phase Error (PE): 0.124ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock sys_clk rise edge) 0.000 0.000 r
|
|
K21 0.000 0.000 r clk (IN)
|
|
net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1
|
|
K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O
|
|
net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll
|
|
PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1)
|
|
-2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1
|
|
net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll
|
|
BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O
|
|
net (fo=10004, routed) 0.658 -0.605 u_confreg/u_digitaltube_controller/sys_clk
|
|
SLICE_X0Y100 FDCE r u_confreg/u_digitaltube_controller/dpy0_reg_reg[3]/C
|
|
------------------------------------------------------------------- -------------------
|
|
SLICE_X0Y100 FDCE (Prop_fdce_C_Q) 0.141 -0.464 r u_confreg/u_digitaltube_controller/dpy0_reg_reg[3]/Q
|
|
net (fo=1, routed) 1.632 1.168 dpy0_OBUF[3]
|
|
A19 OBUF (Prop_obuf_I_O) 1.274 2.441 r dpy0_OBUF[3]_inst/O
|
|
net (fo=0) 0.000 2.441 dpy0[3]
|
|
A19 r dpy0[3] (OUT)
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
Slack: inf
|
|
Source: u_confreg/led_data_reg[12]_lopt_replica/C
|
|
(rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Destination: leds[12]
|
|
(output port)
|
|
Path Group: (none)
|
|
Path Type: Min at Fast Process Corner
|
|
Data Path Delay: 3.006ns (logic 1.384ns (46.047%) route 1.622ns (53.953%))
|
|
Logic Levels: 1 (OBUF=1)
|
|
Clock Uncertainty: 0.190ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
|
Total System Jitter (TSJ): 0.050ns
|
|
Discrete Jitter (DJ): 0.122ns
|
|
Phase Error (PE): 0.124ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock sys_clk rise edge) 0.000 0.000 r
|
|
K21 0.000 0.000 r clk (IN)
|
|
net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1
|
|
K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O
|
|
net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll
|
|
PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1)
|
|
-2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1
|
|
net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll
|
|
BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O
|
|
net (fo=10004, routed) 0.723 -0.539 u_confreg/sys_clk
|
|
SLICE_X3Y89 FDRE r u_confreg/led_data_reg[12]_lopt_replica/C
|
|
------------------------------------------------------------------- -------------------
|
|
SLICE_X3Y89 FDRE (Prop_fdre_C_Q) 0.141 -0.398 r u_confreg/led_data_reg[12]_lopt_replica/Q
|
|
net (fo=1, routed) 1.622 1.223 lopt_3
|
|
D20 OBUF (Prop_obuf_I_O) 1.243 2.467 r leds_OBUF[12]_inst/O
|
|
net (fo=0) 0.000 2.467 leds[12]
|
|
D20 r leds[12] (OUT)
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
Slack: inf
|
|
Source: u_confreg/u_digitaltube_controller/dpy0_reg_reg[0]/C
|
|
(rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Destination: dpy0[0]
|
|
(output port)
|
|
Path Group: (none)
|
|
Path Type: Min at Fast Process Corner
|
|
Data Path Delay: 3.083ns (logic 1.402ns (45.458%) route 1.682ns (54.542%))
|
|
Logic Levels: 1 (OBUF=1)
|
|
Clock Uncertainty: 0.190ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
|
Total System Jitter (TSJ): 0.050ns
|
|
Discrete Jitter (DJ): 0.122ns
|
|
Phase Error (PE): 0.124ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock sys_clk rise edge) 0.000 0.000 r
|
|
K21 0.000 0.000 r clk (IN)
|
|
net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1
|
|
K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O
|
|
net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll
|
|
PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1)
|
|
-2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1
|
|
net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll
|
|
BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O
|
|
net (fo=10004, routed) 0.658 -0.605 u_confreg/u_digitaltube_controller/sys_clk
|
|
SLICE_X0Y100 FDCE r u_confreg/u_digitaltube_controller/dpy0_reg_reg[0]/C
|
|
------------------------------------------------------------------- -------------------
|
|
SLICE_X0Y100 FDCE (Prop_fdce_C_Q) 0.141 -0.464 r u_confreg/u_digitaltube_controller/dpy0_reg_reg[0]/Q
|
|
net (fo=1, routed) 1.682 1.218 dpy0_OBUF[0]
|
|
B19 OBUF (Prop_obuf_I_O) 1.261 2.478 r dpy0_OBUF[0]_inst/O
|
|
net (fo=0) 0.000 2.478 dpy0[0]
|
|
B19 r dpy0[0] (OUT)
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
Slack: inf
|
|
Source: u_confreg/u_digitaltube_controller/dpy1_reg_reg[6]/C
|
|
(rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Destination: dpy1[6]
|
|
(output port)
|
|
Path Group: (none)
|
|
Path Type: Min at Fast Process Corner
|
|
Data Path Delay: 3.165ns (logic 1.379ns (43.565%) route 1.786ns (56.435%))
|
|
Logic Levels: 1 (OBUF=1)
|
|
Clock Uncertainty: 0.190ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
|
Total System Jitter (TSJ): 0.050ns
|
|
Discrete Jitter (DJ): 0.122ns
|
|
Phase Error (PE): 0.124ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock sys_clk rise edge) 0.000 0.000 r
|
|
K21 0.000 0.000 r clk (IN)
|
|
net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1
|
|
K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O
|
|
net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll
|
|
PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1)
|
|
-2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1
|
|
net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll
|
|
BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O
|
|
net (fo=10004, routed) 0.726 -0.536 u_confreg/u_digitaltube_controller/sys_clk
|
|
SLICE_X1Y97 FDCE r u_confreg/u_digitaltube_controller/dpy1_reg_reg[6]/C
|
|
------------------------------------------------------------------- -------------------
|
|
SLICE_X1Y97 FDCE (Prop_fdce_C_Q) 0.141 -0.395 r u_confreg/u_digitaltube_controller/dpy1_reg_reg[6]/Q
|
|
net (fo=1, routed) 1.786 1.391 dpy1_OBUF[6]
|
|
F15 OBUF (Prop_obuf_I_O) 1.238 2.629 r dpy1_OBUF[6]_inst/O
|
|
net (fo=0) 0.000 2.629 dpy1[6]
|
|
F15 r dpy1[6] (OUT)
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
Slack: inf
|
|
Source: u_confreg/u_digitaltube_controller/dpy0_reg_reg[1]/C
|
|
(rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Destination: dpy0[1]
|
|
(output port)
|
|
Path Group: (none)
|
|
Path Type: Min at Fast Process Corner
|
|
Data Path Delay: 3.248ns (logic 1.387ns (42.702%) route 1.861ns (57.298%))
|
|
Logic Levels: 1 (OBUF=1)
|
|
Clock Uncertainty: 0.190ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
|
Total System Jitter (TSJ): 0.050ns
|
|
Discrete Jitter (DJ): 0.122ns
|
|
Phase Error (PE): 0.124ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock sys_clk rise edge) 0.000 0.000 r
|
|
K21 0.000 0.000 r clk (IN)
|
|
net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1
|
|
K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O
|
|
net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll
|
|
PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1)
|
|
-2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1
|
|
net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll
|
|
BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O
|
|
net (fo=10004, routed) 0.658 -0.605 u_confreg/u_digitaltube_controller/sys_clk
|
|
SLICE_X0Y101 FDCE r u_confreg/u_digitaltube_controller/dpy0_reg_reg[1]/C
|
|
------------------------------------------------------------------- -------------------
|
|
SLICE_X0Y101 FDCE (Prop_fdce_C_Q) 0.141 -0.464 r u_confreg/u_digitaltube_controller/dpy0_reg_reg[1]/Q
|
|
net (fo=1, routed) 1.861 1.397 dpy0_OBUF[1]
|
|
D19 OBUF (Prop_obuf_I_O) 1.246 2.643 r dpy0_OBUF[1]_inst/O
|
|
net (fo=0) 0.000 2.643 dpy0[1]
|
|
D19 r dpy0[1] (OUT)
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
Slack: inf
|
|
Source: u_confreg/u_digitaltube_controller/dpy0_reg_reg[5]/C
|
|
(rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Destination: dpy0[5]
|
|
(output port)
|
|
Path Group: (none)
|
|
Path Type: Min at Fast Process Corner
|
|
Data Path Delay: 3.258ns (logic 1.388ns (42.591%) route 1.870ns (57.409%))
|
|
Logic Levels: 1 (OBUF=1)
|
|
Clock Uncertainty: 0.190ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
|
Total System Jitter (TSJ): 0.050ns
|
|
Discrete Jitter (DJ): 0.122ns
|
|
Phase Error (PE): 0.124ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock sys_clk rise edge) 0.000 0.000 r
|
|
K21 0.000 0.000 r clk (IN)
|
|
net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1
|
|
K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O
|
|
net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll
|
|
PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1)
|
|
-2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1
|
|
net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll
|
|
BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O
|
|
net (fo=10004, routed) 0.658 -0.605 u_confreg/u_digitaltube_controller/sys_clk
|
|
SLICE_X0Y101 FDCE r u_confreg/u_digitaltube_controller/dpy0_reg_reg[5]/C
|
|
------------------------------------------------------------------- -------------------
|
|
SLICE_X0Y101 FDCE (Prop_fdce_C_Q) 0.141 -0.464 r u_confreg/u_digitaltube_controller/dpy0_reg_reg[5]/Q
|
|
net (fo=1, routed) 1.870 1.406 dpy0_OBUF[5]
|
|
C19 OBUF (Prop_obuf_I_O) 1.247 2.653 r dpy0_OBUF[5]_inst/O
|
|
net (fo=0) 0.000 2.653 dpy0[5]
|
|
C19 r dpy0[5] (OUT)
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
Slack: inf
|
|
Source: u_confreg/u_digitaltube_controller/dpy1_reg_reg[2]/C
|
|
(rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Destination: dpy1[2]
|
|
(output port)
|
|
Path Group: (none)
|
|
Path Type: Min at Fast Process Corner
|
|
Data Path Delay: 3.236ns (logic 1.383ns (42.747%) route 1.853ns (57.253%))
|
|
Logic Levels: 1 (OBUF=1)
|
|
Clock Uncertainty: 0.190ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
|
Total System Jitter (TSJ): 0.050ns
|
|
Discrete Jitter (DJ): 0.122ns
|
|
Phase Error (PE): 0.124ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock sys_clk rise edge) 0.000 0.000 r
|
|
K21 0.000 0.000 r clk (IN)
|
|
net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1
|
|
K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O
|
|
net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll
|
|
PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1)
|
|
-2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1
|
|
net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll
|
|
BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O
|
|
net (fo=10004, routed) 0.726 -0.536 u_confreg/u_digitaltube_controller/sys_clk
|
|
SLICE_X0Y97 FDCE r u_confreg/u_digitaltube_controller/dpy1_reg_reg[2]/C
|
|
------------------------------------------------------------------- -------------------
|
|
SLICE_X0Y97 FDCE (Prop_fdce_C_Q) 0.141 -0.395 r u_confreg/u_digitaltube_controller/dpy1_reg_reg[2]/Q
|
|
net (fo=1, routed) 1.853 1.457 dpy1_OBUF[2]
|
|
E17 OBUF (Prop_obuf_I_O) 1.242 2.700 r dpy1_OBUF[2]_inst/O
|
|
net (fo=0) 0.000 2.700 dpy1[2]
|
|
E17 r dpy1[2] (OUT)
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
Slack: inf
|
|
Source: u_confreg/led_data_reg[6]_lopt_replica/C
|
|
(rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Destination: leds[6]
|
|
(output port)
|
|
Path Group: (none)
|
|
Path Type: Min at Fast Process Corner
|
|
Data Path Delay: 3.273ns (logic 1.423ns (43.486%) route 1.850ns (56.514%))
|
|
Logic Levels: 1 (OBUF=1)
|
|
Clock Uncertainty: 0.190ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
|
Total System Jitter (TSJ): 0.050ns
|
|
Discrete Jitter (DJ): 0.122ns
|
|
Phase Error (PE): 0.124ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock sys_clk rise edge) 0.000 0.000 r
|
|
K21 0.000 0.000 r clk (IN)
|
|
net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1
|
|
K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O
|
|
net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll
|
|
PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1)
|
|
-2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1
|
|
net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll
|
|
BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O
|
|
net (fo=10004, routed) 0.725 -0.537 u_confreg/sys_clk
|
|
SLICE_X0Y95 FDRE r u_confreg/led_data_reg[6]_lopt_replica/C
|
|
------------------------------------------------------------------- -------------------
|
|
SLICE_X0Y95 FDRE (Prop_fdre_C_Q) 0.128 -0.409 r u_confreg/led_data_reg[6]_lopt_replica/Q
|
|
net (fo=1, routed) 1.850 1.440 lopt_12
|
|
E20 OBUF (Prop_obuf_I_O) 1.295 2.736 r leds_OBUF[6]_inst/O
|
|
net (fo=0) 0.000 2.736 leds[6]
|
|
E20 r leds[6] (OUT)
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
Slack: inf
|
|
Source: u_confreg/led_data_reg[11]_lopt_replica/C
|
|
(rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Destination: leds[11]
|
|
(output port)
|
|
Path Group: (none)
|
|
Path Type: Min at Fast Process Corner
|
|
Data Path Delay: 3.362ns (logic 1.408ns (41.889%) route 1.954ns (58.111%))
|
|
Logic Levels: 1 (OBUF=1)
|
|
Clock Uncertainty: 0.190ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
|
Total System Jitter (TSJ): 0.050ns
|
|
Discrete Jitter (DJ): 0.122ns
|
|
Phase Error (PE): 0.124ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock sys_clk rise edge) 0.000 0.000 r
|
|
K21 0.000 0.000 r clk (IN)
|
|
net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1
|
|
K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O
|
|
net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll
|
|
PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1)
|
|
-2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1
|
|
net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll
|
|
BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O
|
|
net (fo=10004, routed) 0.725 -0.537 u_confreg/sys_clk
|
|
SLICE_X0Y96 FDRE r u_confreg/led_data_reg[11]_lopt_replica/C
|
|
------------------------------------------------------------------- -------------------
|
|
SLICE_X0Y96 FDRE (Prop_fdre_C_Q) 0.141 -0.396 r u_confreg/led_data_reg[11]_lopt_replica/Q
|
|
net (fo=1, routed) 1.954 1.557 lopt_2
|
|
A18 OBUF (Prop_obuf_I_O) 1.267 2.825 r leds_OBUF[11]_inst/O
|
|
net (fo=0) 0.000 2.825 leds[11]
|
|
A18 r leds[11] (OUT)
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
Slack: inf
|
|
Source: u_axi_dvi/hdata_reg[11]/C
|
|
(rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Destination: video_de
|
|
(output port)
|
|
Path Group: (none)
|
|
Path Type: Min at Fast Process Corner
|
|
Data Path Delay: 3.419ns (logic 1.470ns (42.999%) route 1.949ns (57.001%))
|
|
Logic Levels: 2 (LUT6=1 OBUF=1)
|
|
Clock Uncertainty: 0.190ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
|
Total System Jitter (TSJ): 0.050ns
|
|
Discrete Jitter (DJ): 0.122ns
|
|
Phase Error (PE): 0.124ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock sys_clk rise edge) 0.000 0.000 r
|
|
K21 0.000 0.000 r clk (IN)
|
|
net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1
|
|
K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O
|
|
net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll
|
|
PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1)
|
|
-2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1
|
|
net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll
|
|
BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O
|
|
net (fo=10004, routed) 0.690 -0.572 u_axi_dvi/sys_clk
|
|
SLICE_X12Y83 FDRE r u_axi_dvi/hdata_reg[11]/C
|
|
------------------------------------------------------------------- -------------------
|
|
SLICE_X12Y83 FDRE (Prop_fdre_C_Q) 0.164 -0.408 f u_axi_dvi/hdata_reg[11]/Q
|
|
net (fo=12, routed) 0.247 -0.161 u_axi_dvi/hdata_reg_n_0_[11]
|
|
SLICE_X14Y86 LUT6 (Prop_lut6_I3_O) 0.045 -0.116 r u_axi_dvi/video_de_OBUF_inst_i_1/O
|
|
net (fo=1, routed) 1.702 1.586 video_de_OBUF
|
|
G24 OBUF (Prop_obuf_I_O) 1.261 2.847 r video_de_OBUF_inst/O
|
|
net (fo=0) 0.000 2.847 video_de
|
|
G24 r video_de (OUT)
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
Slack: inf
|
|
Source: u_axi_dvi/hdata_reg[11]/C
|
|
(rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Destination: video_hsync
|
|
(output port)
|
|
Path Group: (none)
|
|
Path Type: Min at Fast Process Corner
|
|
Data Path Delay: 3.614ns (logic 1.455ns (40.253%) route 2.159ns (59.747%))
|
|
Logic Levels: 2 (LUT5=1 OBUF=1)
|
|
Clock Uncertainty: 0.190ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
|
Total System Jitter (TSJ): 0.050ns
|
|
Discrete Jitter (DJ): 0.122ns
|
|
Phase Error (PE): 0.124ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock sys_clk rise edge) 0.000 0.000 r
|
|
K21 0.000 0.000 r clk (IN)
|
|
net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1
|
|
K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O
|
|
net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll
|
|
PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1)
|
|
-2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1
|
|
net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll
|
|
BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O
|
|
net (fo=10004, routed) 0.690 -0.572 u_axi_dvi/sys_clk
|
|
SLICE_X12Y83 FDRE r u_axi_dvi/hdata_reg[11]/C
|
|
------------------------------------------------------------------- -------------------
|
|
SLICE_X12Y83 FDRE (Prop_fdre_C_Q) 0.164 -0.408 f u_axi_dvi/hdata_reg[11]/Q
|
|
net (fo=12, routed) 0.447 0.038 u_axi_dvi/hdata_reg_n_0_[11]
|
|
SLICE_X9Y86 LUT5 (Prop_lut5_I1_O) 0.045 0.083 r u_axi_dvi/video_hsync_OBUF_inst_i_1/O
|
|
net (fo=1, routed) 1.713 1.796 video_hsync_OBUF
|
|
J24 OBUF (Prop_obuf_I_O) 1.246 3.041 r video_hsync_OBUF_inst/O
|
|
net (fo=0) 0.000 3.041 video_hsync
|
|
J24 r video_hsync (OUT)
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
Slack: inf
|
|
Source: u_axi_dvi/vdata_reg[8]/C
|
|
(rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Destination: video_vsync
|
|
(output port)
|
|
Path Group: (none)
|
|
Path Type: Min at Fast Process Corner
|
|
Data Path Delay: 3.713ns (logic 1.505ns (40.539%) route 2.208ns (59.461%))
|
|
Logic Levels: 3 (LUT4=2 OBUF=1)
|
|
Clock Uncertainty: 0.190ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
|
Total System Jitter (TSJ): 0.050ns
|
|
Discrete Jitter (DJ): 0.122ns
|
|
Phase Error (PE): 0.124ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock sys_clk rise edge) 0.000 0.000 r
|
|
K21 0.000 0.000 r clk (IN)
|
|
net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1
|
|
K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O
|
|
net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll
|
|
PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1)
|
|
-2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1
|
|
net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll
|
|
BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O
|
|
net (fo=10004, routed) 0.687 -0.575 u_axi_dvi/sys_clk
|
|
SLICE_X18Y80 FDRE r u_axi_dvi/vdata_reg[8]/C
|
|
------------------------------------------------------------------- -------------------
|
|
SLICE_X18Y80 FDRE (Prop_fdre_C_Q) 0.164 -0.411 f u_axi_dvi/vdata_reg[8]/Q
|
|
net (fo=11, routed) 0.333 -0.079 u_axi_dvi/vdata_reg_n_0_[8]
|
|
SLICE_X17Y86 LUT4 (Prop_lut4_I3_O) 0.045 -0.034 f u_axi_dvi/video_vsync_OBUF_inst_i_4/O
|
|
net (fo=2, routed) 0.093 0.059 u_axi_dvi/video_vsync_OBUF_inst_i_4_n_0
|
|
SLICE_X17Y86 LUT4 (Prop_lut4_I3_O) 0.045 0.104 r u_axi_dvi/video_vsync_OBUF_inst_i_1/O
|
|
net (fo=1, routed) 1.782 1.886 video_vsync_OBUF
|
|
H24 OBUF (Prop_obuf_I_O) 1.251 3.138 r video_vsync_OBUF_inst/O
|
|
net (fo=0) 0.000 3.138 video_vsync
|
|
H24 r video_vsync (OUT)
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
Slack: inf
|
|
Source: u_axi_dvi/hdata_reg[11]/C
|
|
(rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Destination: video_red[2]
|
|
(output port)
|
|
Path Group: (none)
|
|
Path Type: Min at Fast Process Corner
|
|
Data Path Delay: 3.728ns (logic 1.648ns (44.198%) route 2.081ns (55.802%))
|
|
Logic Levels: 4 (CARRY4=2 LUT5=1 OBUF=1)
|
|
Clock Uncertainty: 0.190ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
|
Total System Jitter (TSJ): 0.050ns
|
|
Discrete Jitter (DJ): 0.122ns
|
|
Phase Error (PE): 0.124ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock sys_clk rise edge) 0.000 0.000 r
|
|
K21 0.000 0.000 r clk (IN)
|
|
net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1
|
|
K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O
|
|
net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll
|
|
PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1)
|
|
-2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1
|
|
net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll
|
|
BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O
|
|
net (fo=10004, routed) 0.690 -0.572 u_axi_dvi/sys_clk
|
|
SLICE_X12Y83 FDRE r u_axi_dvi/hdata_reg[11]/C
|
|
------------------------------------------------------------------- -------------------
|
|
SLICE_X12Y83 FDRE (Prop_fdre_C_Q) 0.164 -0.408 r u_axi_dvi/hdata_reg[11]/Q
|
|
net (fo=12, routed) 0.257 -0.152 u_axi_dvi/hdata_reg_n_0_[11]
|
|
SLICE_X15Y84 CARRY4 (Prop_carry4_DI[3]_CO[3])
|
|
0.113 -0.039 r u_axi_dvi/video_red_OBUF[2]_inst_i_26/CO[3]
|
|
net (fo=1, routed) 0.000 -0.039 u_axi_dvi/video_red_OBUF[2]_inst_i_26_n_0
|
|
SLICE_X15Y85 CARRY4 (Prop_carry4_CI_CO[3])
|
|
0.039 0.000 f u_axi_dvi/video_red_OBUF[2]_inst_i_5/CO[3]
|
|
net (fo=1, routed) 0.257 0.257 u_axi_dvi/video_red_OBUF[2]_inst_i_5_n_0
|
|
SLICE_X16Y85 LUT5 (Prop_lut5_I3_O) 0.045 0.302 r u_axi_dvi/video_red_OBUF[2]_inst_i_1/O
|
|
net (fo=3, routed) 1.568 1.869 video_red_OBUF[0]
|
|
E26 OBUF (Prop_obuf_I_O) 1.287 3.156 r video_red_OBUF[2]_inst/O
|
|
net (fo=0) 0.000 3.156 video_red[2]
|
|
E26 r video_red[2] (OUT)
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
Slack: inf
|
|
Source: u_confreg/u_digitaltube_controller/dpy1_reg_reg[3]/C
|
|
(rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Destination: dpy1[3]
|
|
(output port)
|
|
Path Group: (none)
|
|
Path Type: Min at Fast Process Corner
|
|
Data Path Delay: 3.728ns (logic 1.356ns (36.384%) route 2.371ns (63.616%))
|
|
Logic Levels: 1 (OBUF=1)
|
|
Clock Uncertainty: 0.190ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
|
Total System Jitter (TSJ): 0.050ns
|
|
Discrete Jitter (DJ): 0.122ns
|
|
Phase Error (PE): 0.124ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock sys_clk rise edge) 0.000 0.000 r
|
|
K21 0.000 0.000 r clk (IN)
|
|
net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1
|
|
K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O
|
|
net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll
|
|
PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1)
|
|
-2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1
|
|
net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll
|
|
BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O
|
|
net (fo=10004, routed) 0.726 -0.536 u_confreg/u_digitaltube_controller/sys_clk
|
|
SLICE_X0Y97 FDCE r u_confreg/u_digitaltube_controller/dpy1_reg_reg[3]/C
|
|
------------------------------------------------------------------- -------------------
|
|
SLICE_X0Y97 FDCE (Prop_fdce_C_Q) 0.141 -0.395 r u_confreg/u_digitaltube_controller/dpy1_reg_reg[3]/Q
|
|
net (fo=1, routed) 2.371 1.976 dpy1_OBUF[3]
|
|
F17 OBUF (Prop_obuf_I_O) 1.215 3.191 r dpy1_OBUF[3]_inst/O
|
|
net (fo=0) 0.000 3.191 dpy1[3]
|
|
F17 r dpy1[3] (OUT)
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
Slack: inf
|
|
Source: u_axi_dvi/hdata_reg[11]/C
|
|
(rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Destination: video_red[1]
|
|
(output port)
|
|
Path Group: (none)
|
|
Path Type: Min at Fast Process Corner
|
|
Data Path Delay: 3.827ns (logic 1.622ns (42.374%) route 2.206ns (57.626%))
|
|
Logic Levels: 4 (CARRY4=2 LUT5=1 OBUF=1)
|
|
Clock Uncertainty: 0.190ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
|
Total System Jitter (TSJ): 0.050ns
|
|
Discrete Jitter (DJ): 0.122ns
|
|
Phase Error (PE): 0.124ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock sys_clk rise edge) 0.000 0.000 r
|
|
K21 0.000 0.000 r clk (IN)
|
|
net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1
|
|
K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O
|
|
net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll
|
|
PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1)
|
|
-2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1
|
|
net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll
|
|
BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O
|
|
net (fo=10004, routed) 0.690 -0.572 u_axi_dvi/sys_clk
|
|
SLICE_X12Y83 FDRE r u_axi_dvi/hdata_reg[11]/C
|
|
------------------------------------------------------------------- -------------------
|
|
SLICE_X12Y83 FDRE (Prop_fdre_C_Q) 0.164 -0.408 r u_axi_dvi/hdata_reg[11]/Q
|
|
net (fo=12, routed) 0.257 -0.152 u_axi_dvi/hdata_reg_n_0_[11]
|
|
SLICE_X15Y84 CARRY4 (Prop_carry4_DI[3]_CO[3])
|
|
0.113 -0.039 r u_axi_dvi/video_red_OBUF[2]_inst_i_26/CO[3]
|
|
net (fo=1, routed) 0.000 -0.039 u_axi_dvi/video_red_OBUF[2]_inst_i_26_n_0
|
|
SLICE_X15Y85 CARRY4 (Prop_carry4_CI_CO[3])
|
|
0.039 0.000 f u_axi_dvi/video_red_OBUF[2]_inst_i_5/CO[3]
|
|
net (fo=1, routed) 0.257 0.257 u_axi_dvi/video_red_OBUF[2]_inst_i_5_n_0
|
|
SLICE_X16Y85 LUT5 (Prop_lut5_I3_O) 0.045 0.302 r u_axi_dvi/video_red_OBUF[2]_inst_i_1/O
|
|
net (fo=3, routed) 1.693 1.994 video_red_OBUF[0]
|
|
F24 OBUF (Prop_obuf_I_O) 1.261 3.255 r video_red_OBUF[1]_inst/O
|
|
net (fo=0) 0.000 3.255 video_red[1]
|
|
F24 r video_red[1] (OUT)
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
Slack: inf
|
|
Source: u_axi_dvi/hdata_reg[11]/C
|
|
(rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Destination: video_red[0]
|
|
(output port)
|
|
Path Group: (none)
|
|
Path Type: Min at Fast Process Corner
|
|
Data Path Delay: 3.859ns (logic 1.594ns (41.315%) route 2.265ns (58.685%))
|
|
Logic Levels: 4 (CARRY4=2 LUT5=1 OBUF=1)
|
|
Clock Uncertainty: 0.190ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
|
Total System Jitter (TSJ): 0.050ns
|
|
Discrete Jitter (DJ): 0.122ns
|
|
Phase Error (PE): 0.124ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock sys_clk rise edge) 0.000 0.000 r
|
|
K21 0.000 0.000 r clk (IN)
|
|
net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1
|
|
K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O
|
|
net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll
|
|
PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1)
|
|
-2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1
|
|
net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll
|
|
BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O
|
|
net (fo=10004, routed) 0.690 -0.572 u_axi_dvi/sys_clk
|
|
SLICE_X12Y83 FDRE r u_axi_dvi/hdata_reg[11]/C
|
|
------------------------------------------------------------------- -------------------
|
|
SLICE_X12Y83 FDRE (Prop_fdre_C_Q) 0.164 -0.408 r u_axi_dvi/hdata_reg[11]/Q
|
|
net (fo=12, routed) 0.257 -0.152 u_axi_dvi/hdata_reg_n_0_[11]
|
|
SLICE_X15Y84 CARRY4 (Prop_carry4_DI[3]_CO[3])
|
|
0.113 -0.039 r u_axi_dvi/video_red_OBUF[2]_inst_i_26/CO[3]
|
|
net (fo=1, routed) 0.000 -0.039 u_axi_dvi/video_red_OBUF[2]_inst_i_26_n_0
|
|
SLICE_X15Y85 CARRY4 (Prop_carry4_CI_CO[3])
|
|
0.039 0.000 f u_axi_dvi/video_red_OBUF[2]_inst_i_5/CO[3]
|
|
net (fo=1, routed) 0.257 0.257 u_axi_dvi/video_red_OBUF[2]_inst_i_5_n_0
|
|
SLICE_X16Y85 LUT5 (Prop_lut5_I3_O) 0.045 0.302 r u_axi_dvi/video_red_OBUF[2]_inst_i_1/O
|
|
net (fo=3, routed) 1.752 2.053 video_red_OBUF[0]
|
|
K23 OBUF (Prop_obuf_I_O) 1.233 3.287 r video_red_OBUF[0]_inst/O
|
|
net (fo=0) 0.000 3.287 video_red[0]
|
|
K23 r video_red[0] (OUT)
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
Slack: inf
|
|
Source: u_confreg/u_digitaltube_controller/dpy0_reg_reg[2]/C
|
|
(rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Destination: dpy0[2]
|
|
(output port)
|
|
Path Group: (none)
|
|
Path Type: Min at Fast Process Corner
|
|
Data Path Delay: 3.903ns (logic 1.400ns (35.872%) route 2.503ns (64.128%))
|
|
Logic Levels: 1 (OBUF=1)
|
|
Clock Uncertainty: 0.190ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
|
Total System Jitter (TSJ): 0.050ns
|
|
Discrete Jitter (DJ): 0.122ns
|
|
Phase Error (PE): 0.124ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock sys_clk rise edge) 0.000 0.000 r
|
|
K21 0.000 0.000 r clk (IN)
|
|
net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1
|
|
K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O
|
|
net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll
|
|
PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1)
|
|
-2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1
|
|
net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll
|
|
BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O
|
|
net (fo=10004, routed) 0.658 -0.605 u_confreg/u_digitaltube_controller/sys_clk
|
|
SLICE_X0Y101 FDCE r u_confreg/u_digitaltube_controller/dpy0_reg_reg[2]/C
|
|
------------------------------------------------------------------- -------------------
|
|
SLICE_X0Y101 FDCE (Prop_fdce_C_Q) 0.141 -0.464 r u_confreg/u_digitaltube_controller/dpy0_reg_reg[2]/Q
|
|
net (fo=1, routed) 2.503 2.039 dpy0_OBUF[2]
|
|
B21 OBUF (Prop_obuf_I_O) 1.259 3.298 r dpy0_OBUF[2]_inst/O
|
|
net (fo=0) 0.000 3.298 dpy0[2]
|
|
B21 r dpy0[2] (OUT)
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
Slack: inf
|
|
Source: u_confreg/led_data_reg[2]_lopt_replica/C
|
|
(rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Destination: leds[2]
|
|
(output port)
|
|
Path Group: (none)
|
|
Path Type: Min at Fast Process Corner
|
|
Data Path Delay: 3.877ns (logic 1.428ns (36.839%) route 2.448ns (63.161%))
|
|
Logic Levels: 1 (OBUF=1)
|
|
Clock Uncertainty: 0.190ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
|
Total System Jitter (TSJ): 0.050ns
|
|
Discrete Jitter (DJ): 0.122ns
|
|
Phase Error (PE): 0.124ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock sys_clk rise edge) 0.000 0.000 r
|
|
K21 0.000 0.000 r clk (IN)
|
|
net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1
|
|
K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O
|
|
net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll
|
|
PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1)
|
|
-2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1
|
|
net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll
|
|
BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O
|
|
net (fo=10004, routed) 0.726 -0.536 u_confreg/sys_clk
|
|
SLICE_X0Y98 FDRE r u_confreg/led_data_reg[2]_lopt_replica/C
|
|
------------------------------------------------------------------- -------------------
|
|
SLICE_X0Y98 FDRE (Prop_fdre_C_Q) 0.141 -0.395 r u_confreg/led_data_reg[2]_lopt_replica/Q
|
|
net (fo=1, routed) 2.448 2.053 lopt_8
|
|
A24 OBUF (Prop_obuf_I_O) 1.287 3.340 r leds_OBUF[2]_inst/O
|
|
net (fo=0) 0.000 3.340 leds[2]
|
|
A24 r leds[2] (OUT)
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
Slack: inf
|
|
Source: u_confreg/led_data_reg[3]_lopt_replica/C
|
|
(rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Destination: leds[3]
|
|
(output port)
|
|
Path Group: (none)
|
|
Path Type: Min at Fast Process Corner
|
|
Data Path Delay: 3.896ns (logic 1.404ns (36.025%) route 2.493ns (63.975%))
|
|
Logic Levels: 1 (OBUF=1)
|
|
Clock Uncertainty: 0.190ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
|
Total System Jitter (TSJ): 0.050ns
|
|
Discrete Jitter (DJ): 0.122ns
|
|
Phase Error (PE): 0.124ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock sys_clk rise edge) 0.000 0.000 r
|
|
K21 0.000 0.000 r clk (IN)
|
|
net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1
|
|
K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O
|
|
net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll
|
|
PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1)
|
|
-2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1
|
|
net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll
|
|
BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O
|
|
net (fo=10004, routed) 0.726 -0.536 u_confreg/sys_clk
|
|
SLICE_X0Y98 FDRE r u_confreg/led_data_reg[3]_lopt_replica/C
|
|
------------------------------------------------------------------- -------------------
|
|
SLICE_X0Y98 FDRE (Prop_fdre_C_Q) 0.141 -0.395 r u_confreg/led_data_reg[3]_lopt_replica/Q
|
|
net (fo=1, routed) 2.493 2.097 lopt_9
|
|
D23 OBUF (Prop_obuf_I_O) 1.263 3.360 r leds_OBUF[3]_inst/O
|
|
net (fo=0) 0.000 3.360 leds[3]
|
|
D23 r leds[3] (OUT)
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
Slack: inf
|
|
Source: u_confreg/led_data_reg[9]_lopt_replica/C
|
|
(rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Destination: leds[9]
|
|
(output port)
|
|
Path Group: (none)
|
|
Path Type: Min at Fast Process Corner
|
|
Data Path Delay: 4.250ns (logic 1.424ns (33.494%) route 2.827ns (66.506%))
|
|
Logic Levels: 1 (OBUF=1)
|
|
Clock Uncertainty: 0.190ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
|
Total System Jitter (TSJ): 0.050ns
|
|
Discrete Jitter (DJ): 0.122ns
|
|
Phase Error (PE): 0.124ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock sys_clk rise edge) 0.000 0.000 r
|
|
K21 0.000 0.000 r clk (IN)
|
|
net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1
|
|
K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O
|
|
net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll
|
|
PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1)
|
|
-2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1
|
|
net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll
|
|
BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O
|
|
net (fo=10004, routed) 0.721 -0.541 u_confreg/sys_clk
|
|
SLICE_X0Y86 FDRE r u_confreg/led_data_reg[9]_lopt_replica/C
|
|
------------------------------------------------------------------- -------------------
|
|
SLICE_X0Y86 FDRE (Prop_fdre_C_Q) 0.141 -0.400 r u_confreg/led_data_reg[9]_lopt_replica/Q
|
|
net (fo=1, routed) 2.827 2.426 lopt_15
|
|
A23 OBUF (Prop_obuf_I_O) 1.283 3.709 r leds_OBUF[9]_inst/O
|
|
net (fo=0) 0.000 3.709 leds[9]
|
|
A23 r leds[9] (OUT)
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
Slack: inf
|
|
Source: u_confreg/led_data_reg[5]_lopt_replica/C
|
|
(rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Destination: leds[5]
|
|
(output port)
|
|
Path Group: (none)
|
|
Path Type: Min at Fast Process Corner
|
|
Data Path Delay: 4.428ns (logic 1.436ns (32.434%) route 2.992ns (67.566%))
|
|
Logic Levels: 1 (OBUF=1)
|
|
Clock Uncertainty: 0.190ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
|
Total System Jitter (TSJ): 0.050ns
|
|
Discrete Jitter (DJ): 0.122ns
|
|
Phase Error (PE): 0.124ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock sys_clk rise edge) 0.000 0.000 r
|
|
K21 0.000 0.000 r clk (IN)
|
|
net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1
|
|
K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O
|
|
net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll
|
|
PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1)
|
|
-2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1
|
|
net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll
|
|
BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O
|
|
net (fo=10004, routed) 0.725 -0.537 u_confreg/sys_clk
|
|
SLICE_X0Y95 FDRE r u_confreg/led_data_reg[5]_lopt_replica/C
|
|
------------------------------------------------------------------- -------------------
|
|
SLICE_X0Y95 FDRE (Prop_fdre_C_Q) 0.128 -0.409 r u_confreg/led_data_reg[5]_lopt_replica/Q
|
|
net (fo=1, routed) 2.992 2.582 lopt_11
|
|
C21 OBUF (Prop_obuf_I_O) 1.308 3.890 r leds_OBUF[5]_inst/O
|
|
net (fo=0) 0.000 3.890 leds[5]
|
|
C21 r leds[5] (OUT)
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
Slack: inf
|
|
Source: u_confreg/u_digitaltube_controller/dpy0_reg_reg[4]/C
|
|
(rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Destination: dpy0[4]
|
|
(output port)
|
|
Path Group: (none)
|
|
Path Type: Min at Fast Process Corner
|
|
Data Path Delay: 4.536ns (logic 1.381ns (30.449%) route 3.155ns (69.551%))
|
|
Logic Levels: 1 (OBUF=1)
|
|
Clock Uncertainty: 0.190ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
|
Total System Jitter (TSJ): 0.050ns
|
|
Discrete Jitter (DJ): 0.122ns
|
|
Phase Error (PE): 0.124ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock sys_clk rise edge) 0.000 0.000 r
|
|
K21 0.000 0.000 r clk (IN)
|
|
net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1
|
|
K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O
|
|
net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll
|
|
PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1)
|
|
-2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1
|
|
net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll
|
|
BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O
|
|
net (fo=10004, routed) 0.658 -0.605 u_confreg/u_digitaltube_controller/sys_clk
|
|
SLICE_X0Y100 FDCE r u_confreg/u_digitaltube_controller/dpy0_reg_reg[4]/C
|
|
------------------------------------------------------------------- -------------------
|
|
SLICE_X0Y100 FDCE (Prop_fdce_C_Q) 0.141 -0.464 r u_confreg/u_digitaltube_controller/dpy0_reg_reg[4]/Q
|
|
net (fo=1, routed) 3.155 2.691 dpy0_OBUF[4]
|
|
E18 OBUF (Prop_obuf_I_O) 1.240 3.931 r dpy0_OBUF[4]_inst/O
|
|
net (fo=0) 0.000 3.931 dpy0[4]
|
|
E18 r dpy0[4] (OUT)
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
Slack: inf
|
|
Source: u_confreg/led_data_reg[4]_lopt_replica/C
|
|
(rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Destination: leds[4]
|
|
(output port)
|
|
Path Group: (none)
|
|
Path Type: Min at Fast Process Corner
|
|
Data Path Delay: 4.540ns (logic 1.404ns (30.920%) route 3.136ns (69.080%))
|
|
Logic Levels: 1 (OBUF=1)
|
|
Clock Uncertainty: 0.190ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
|
Total System Jitter (TSJ): 0.050ns
|
|
Discrete Jitter (DJ): 0.122ns
|
|
Phase Error (PE): 0.124ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock sys_clk rise edge) 0.000 0.000 r
|
|
K21 0.000 0.000 r clk (IN)
|
|
net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1
|
|
K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O
|
|
net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll
|
|
PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1)
|
|
-2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1
|
|
net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll
|
|
BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O
|
|
net (fo=10004, routed) 0.723 -0.539 u_confreg/sys_clk
|
|
SLICE_X3Y89 FDRE r u_confreg/led_data_reg[4]_lopt_replica/C
|
|
------------------------------------------------------------------- -------------------
|
|
SLICE_X3Y89 FDRE (Prop_fdre_C_Q) 0.141 -0.398 r u_confreg/led_data_reg[4]_lopt_replica/Q
|
|
net (fo=1, routed) 3.136 2.738 lopt_10
|
|
C22 OBUF (Prop_obuf_I_O) 1.263 4.001 r leds_OBUF[4]_inst/O
|
|
net (fo=0) 0.000 4.001 leds[4]
|
|
C22 r leds[4] (OUT)
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
Slack: inf
|
|
Source: u_confreg/led_data_reg[8]_lopt_replica/C
|
|
(rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Destination: leds[8]
|
|
(output port)
|
|
Path Group: (none)
|
|
Path Type: Min at Fast Process Corner
|
|
Data Path Delay: 4.629ns (logic 1.426ns (30.799%) route 3.203ns (69.201%))
|
|
Logic Levels: 1 (OBUF=1)
|
|
Clock Uncertainty: 0.190ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
|
Total System Jitter (TSJ): 0.050ns
|
|
Discrete Jitter (DJ): 0.122ns
|
|
Phase Error (PE): 0.124ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock sys_clk rise edge) 0.000 0.000 r
|
|
K21 0.000 0.000 r clk (IN)
|
|
net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1
|
|
K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O
|
|
net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll
|
|
PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1)
|
|
-2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1
|
|
net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll
|
|
BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O
|
|
net (fo=10004, routed) 0.718 -0.544 u_confreg/sys_clk
|
|
SLICE_X2Y81 FDRE r u_confreg/led_data_reg[8]_lopt_replica/C
|
|
------------------------------------------------------------------- -------------------
|
|
SLICE_X2Y81 FDRE (Prop_fdre_C_Q) 0.164 -0.380 r u_confreg/led_data_reg[8]_lopt_replica/Q
|
|
net (fo=1, routed) 3.203 2.823 lopt_14
|
|
C23 OBUF (Prop_obuf_I_O) 1.262 4.084 r leds_OBUF[8]_inst/O
|
|
net (fo=0) 0.000 4.084 leds[8]
|
|
C23 r leds[8] (OUT)
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
Slack: inf
|
|
Source: u_confreg/led_data_reg[15]_lopt_replica/C
|
|
(rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Destination: leds[15]
|
|
(output port)
|
|
Path Group: (none)
|
|
Path Type: Min at Fast Process Corner
|
|
Data Path Delay: 4.721ns (logic 1.404ns (29.752%) route 3.316ns (70.248%))
|
|
Logic Levels: 1 (OBUF=1)
|
|
Clock Uncertainty: 0.190ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
|
Total System Jitter (TSJ): 0.050ns
|
|
Discrete Jitter (DJ): 0.122ns
|
|
Phase Error (PE): 0.124ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock sys_clk rise edge) 0.000 0.000 r
|
|
K21 0.000 0.000 r clk (IN)
|
|
net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1
|
|
K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O
|
|
net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll
|
|
PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1)
|
|
-2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1
|
|
net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll
|
|
BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O
|
|
net (fo=10004, routed) 0.725 -0.537 u_confreg/sys_clk
|
|
SLICE_X0Y95 FDRE r u_confreg/led_data_reg[15]_lopt_replica/C
|
|
------------------------------------------------------------------- -------------------
|
|
SLICE_X0Y95 FDRE (Prop_fdre_C_Q) 0.141 -0.396 r u_confreg/led_data_reg[15]_lopt_replica/Q
|
|
net (fo=1, routed) 3.316 2.920 lopt_6
|
|
B20 OBUF (Prop_obuf_I_O) 1.263 4.183 r leds_OBUF[15]_inst/O
|
|
net (fo=0) 0.000 4.183 leds[15]
|
|
B20 r leds[15] (OUT)
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
|
|
|
|
|
|
|
|
--------------------------------------------------------------------------------------
|
|
Path Group: (none)
|
|
From Clock:
|
|
To Clock: sys_clk
|
|
|
|
Max Delay 0 Endpoints
|
|
Min Delay 43 Endpoints
|
|
--------------------------------------------------------------------------------------
|
|
|
|
|
|
Min Delay Paths
|
|
--------------------------------------------------------------------------------------
|
|
Slack: inf
|
|
Source: UART_TX
|
|
(input port)
|
|
Destination: u_axi_uart_controller/uart0/regs/transmitter/tx_error_reg/D
|
|
(rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Path Group: (none)
|
|
Path Type: Hold (Min at Fast Process Corner)
|
|
Data Path Delay: 1.811ns (logic 0.287ns (15.865%) route 1.523ns (84.135%))
|
|
Logic Levels: 2 (IBUF=1 LUT5=1)
|
|
Clock Path Skew: -0.310ns (DCD - SCD - CPR)
|
|
Destination Clock Delay (DCD): -0.310ns
|
|
Source Clock Delay (SCD): 0.000ns
|
|
Clock Pessimism Removal (CPR): -0.000ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
H18 0.000 0.000 f UART_TX (INOUT)
|
|
net (fo=1, unset) 0.000 0.000 UART_TX_IOBUF_inst/IO
|
|
H18 IBUF (Prop_ibuf_I_O) 0.242 0.242 f UART_TX_IOBUF_inst/IBUF/O
|
|
net (fo=4, routed) 1.523 1.766 u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/UART_TX_IBUF
|
|
SLICE_X4Y61 LUT5 (Prop_lut5_I2_O) 0.045 1.811 r u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/tx_error_i_1/O
|
|
net (fo=1, routed) 0.000 1.811 u_axi_uart_controller/uart0/regs/transmitter/fifo_tx_n_21
|
|
SLICE_X4Y61 FDRE r u_axi_uart_controller/uart0/regs/transmitter/tx_error_reg/D
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock sys_clk rise edge) 0.000 0.000 r
|
|
K21 0.000 0.000 r clk (IN)
|
|
net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1
|
|
K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O
|
|
net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll
|
|
PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1)
|
|
-2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1
|
|
net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll
|
|
BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O
|
|
net (fo=10004, routed) 0.998 -0.310 u_axi_uart_controller/uart0/regs/transmitter/sys_clk
|
|
SLICE_X4Y61 FDRE r u_axi_uart_controller/uart0/regs/transmitter/tx_error_reg/C
|
|
|
|
Slack: inf
|
|
Source: UART_TX
|
|
(input port)
|
|
Destination: u_axi_uart_controller/uart0/regs/i_uart_sync_flops/flop_0_reg[0]/D
|
|
(rising edge-triggered cell FDSE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Path Group: (none)
|
|
Path Type: Hold (Min at Fast Process Corner)
|
|
Data Path Delay: 1.893ns (logic 0.287ns (15.179%) route 1.605ns (84.821%))
|
|
Logic Levels: 2 (IBUF=1 LUT4=1)
|
|
Clock Path Skew: -0.308ns (DCD - SCD - CPR)
|
|
Destination Clock Delay (DCD): -0.308ns
|
|
Source Clock Delay (SCD): 0.000ns
|
|
Clock Pessimism Removal (CPR): -0.000ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
H18 0.000 0.000 r UART_TX (INOUT)
|
|
net (fo=1, unset) 0.000 0.000 UART_TX_IOBUF_inst/IO
|
|
H18 IBUF (Prop_ibuf_I_O) 0.242 0.242 r UART_TX_IOBUF_inst/IBUF/O
|
|
net (fo=4, routed) 1.605 1.848 u_axi_uart_controller/uart0/regs/i_uart_sync_flops/UART_TX_IBUF
|
|
SLICE_X1Y61 LUT4 (Prop_lut4_I2_O) 0.045 1.893 r u_axi_uart_controller/uart0/regs/i_uart_sync_flops/flop_0[0]_i_1/O
|
|
net (fo=1, routed) 0.000 1.893 u_axi_uart_controller/uart0/regs/i_uart_sync_flops/rcv_pad_i
|
|
SLICE_X1Y61 FDSE r u_axi_uart_controller/uart0/regs/i_uart_sync_flops/flop_0_reg[0]/D
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock sys_clk rise edge) 0.000 0.000 r
|
|
K21 0.000 0.000 r clk (IN)
|
|
net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1
|
|
K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O
|
|
net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll
|
|
PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1)
|
|
-2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1
|
|
net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll
|
|
BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O
|
|
net (fo=10004, routed) 1.000 -0.308 u_axi_uart_controller/uart0/regs/i_uart_sync_flops/sys_clk
|
|
SLICE_X1Y61 FDSE r u_axi_uart_controller/uart0/regs/i_uart_sync_flops/flop_0_reg[0]/C
|
|
|
|
Slack: inf
|
|
Source: pll_clk.u_clk_pll/inst/plle2_adv_inst/LOCKED
|
|
(internal pin)
|
|
Destination: pll_clk.u_rst_sys/delay_reg[0]/CLR
|
|
(removal check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Path Group: (none)
|
|
Path Type: Removal (Min at Fast Process Corner)
|
|
Data Path Delay: 1.899ns (logic 0.045ns (2.370%) route 1.854ns (97.630%))
|
|
Logic Levels: 1 (LUT1=1)
|
|
Clock Uncertainty: 0.190ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
|
Total System Jitter (TSJ): 0.050ns
|
|
Discrete Jitter (DJ): 0.122ns
|
|
Phase Error (PE): 0.124ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
PLLE2_ADV_X0Y3 PLLE2_ADV 0.000 0.000 r pll_clk.u_clk_pll/inst/plle2_adv_inst/LOCKED
|
|
net (fo=1, routed) 1.417 1.417 pll_clk.u_rst_sys/locked
|
|
SLICE_X0Y121 LUT1 (Prop_lut1_I0_O) 0.045 1.462 f pll_clk.u_rst_sys/delay[1]_i_1/O
|
|
net (fo=2, routed) 0.437 1.899 pll_clk.u_rst_sys/delay[1]_i_1_n_0
|
|
SLICE_X1Y101 FDCE f pll_clk.u_rst_sys/delay_reg[0]/CLR
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock sys_clk rise edge) 0.000 0.000 r
|
|
K21 0.000 0.000 r clk (IN)
|
|
net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1
|
|
K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O
|
|
net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll
|
|
PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1)
|
|
-2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1
|
|
net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll
|
|
BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O
|
|
net (fo=10004, routed) 0.932 -0.376 pll_clk.u_rst_sys/sys_clk
|
|
SLICE_X1Y101 FDCE r pll_clk.u_rst_sys/delay_reg[0]/C
|
|
|
|
Slack: inf
|
|
Source: pll_clk.u_clk_pll/inst/plle2_adv_inst/LOCKED
|
|
(internal pin)
|
|
Destination: pll_clk.u_rst_sys/delay_reg[1]/CLR
|
|
(removal check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Path Group: (none)
|
|
Path Type: Removal (Min at Fast Process Corner)
|
|
Data Path Delay: 1.899ns (logic 0.045ns (2.370%) route 1.854ns (97.630%))
|
|
Logic Levels: 1 (LUT1=1)
|
|
Clock Uncertainty: 0.190ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
|
Total System Jitter (TSJ): 0.050ns
|
|
Discrete Jitter (DJ): 0.122ns
|
|
Phase Error (PE): 0.124ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
PLLE2_ADV_X0Y3 PLLE2_ADV 0.000 0.000 r pll_clk.u_clk_pll/inst/plle2_adv_inst/LOCKED
|
|
net (fo=1, routed) 1.417 1.417 pll_clk.u_rst_sys/locked
|
|
SLICE_X0Y121 LUT1 (Prop_lut1_I0_O) 0.045 1.462 f pll_clk.u_rst_sys/delay[1]_i_1/O
|
|
net (fo=2, routed) 0.437 1.899 pll_clk.u_rst_sys/delay[1]_i_1_n_0
|
|
SLICE_X1Y101 FDCE f pll_clk.u_rst_sys/delay_reg[1]/CLR
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock sys_clk rise edge) 0.000 0.000 r
|
|
K21 0.000 0.000 r clk (IN)
|
|
net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1
|
|
K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O
|
|
net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll
|
|
PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1)
|
|
-2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1
|
|
net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll
|
|
BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O
|
|
net (fo=10004, routed) 0.932 -0.376 pll_clk.u_rst_sys/sys_clk
|
|
SLICE_X1Y101 FDCE r pll_clk.u_rst_sys/delay_reg[1]/C
|
|
|
|
Slack: inf
|
|
Source: UART_TX
|
|
(input port)
|
|
Destination: u_axi_uart_controller/uart0/regs/transmitter/error_time_reg[0]/D
|
|
(rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Path Group: (none)
|
|
Path Type: Hold (Min at Fast Process Corner)
|
|
Data Path Delay: 2.058ns (logic 0.287ns (13.959%) route 1.771ns (86.041%))
|
|
Logic Levels: 2 (IBUF=1 LUT5=1)
|
|
Clock Path Skew: -0.308ns (DCD - SCD - CPR)
|
|
Destination Clock Delay (DCD): -0.308ns
|
|
Source Clock Delay (SCD): 0.000ns
|
|
Clock Pessimism Removal (CPR): -0.000ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
H18 0.000 0.000 r UART_TX (INOUT)
|
|
net (fo=1, unset) 0.000 0.000 UART_TX_IOBUF_inst/IO
|
|
H18 IBUF (Prop_ibuf_I_O) 0.242 0.242 r UART_TX_IOBUF_inst/IBUF/O
|
|
net (fo=4, routed) 1.550 1.793 u_axi_uart_controller/uart0/regs/transmitter/UART_TX_IBUF
|
|
SLICE_X2Y60 LUT5 (Prop_lut5_I0_O) 0.045 1.838 r u_axi_uart_controller/uart0/regs/transmitter/error_time[0]_i_1/O
|
|
net (fo=1, routed) 0.220 2.058 u_axi_uart_controller/uart0/regs/transmitter/error_time[0]_i_1_n_0
|
|
SLICE_X2Y60 FDRE r u_axi_uart_controller/uart0/regs/transmitter/error_time_reg[0]/D
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock sys_clk rise edge) 0.000 0.000 r
|
|
K21 0.000 0.000 r clk (IN)
|
|
net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1
|
|
K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O
|
|
net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll
|
|
PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1)
|
|
-2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1
|
|
net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll
|
|
BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O
|
|
net (fo=10004, routed) 1.000 -0.308 u_axi_uart_controller/uart0/regs/transmitter/sys_clk
|
|
SLICE_X2Y60 FDRE r u_axi_uart_controller/uart0/regs/transmitter/error_time_reg[0]/C
|
|
|
|
Slack: inf
|
|
Source: UART_TX
|
|
(input port)
|
|
Destination: u_axi_uart_controller/uart0/regs/transmitter/error_time_reg[2]/D
|
|
(rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Path Group: (none)
|
|
Path Type: Hold (Min at Fast Process Corner)
|
|
Data Path Delay: 2.089ns (logic 0.408ns (19.545%) route 1.681ns (80.455%))
|
|
Logic Levels: 3 (IBUF=1 LUT2=1 LUT6=1)
|
|
Clock Path Skew: -0.308ns (DCD - SCD - CPR)
|
|
Destination Clock Delay (DCD): -0.308ns
|
|
Source Clock Delay (SCD): 0.000ns
|
|
Clock Pessimism Removal (CPR): -0.000ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
H18 0.000 0.000 f UART_TX (INOUT)
|
|
net (fo=1, unset) 0.000 0.000 UART_TX_IOBUF_inst/IO
|
|
H18 IBUF (Prop_ibuf_I_O) 0.242 0.242 f UART_TX_IOBUF_inst/IBUF/O
|
|
net (fo=4, routed) 1.550 1.793 u_axi_uart_controller/uart0/regs/transmitter/UART_TX_IBUF
|
|
SLICE_X2Y60 LUT2 (Prop_lut2_I1_O) 0.048 1.841 r u_axi_uart_controller/uart0/regs/transmitter/error_time[2]_i_2/O
|
|
net (fo=2, routed) 0.130 1.971 u_axi_uart_controller/uart0/regs/transmitter/error_time[2]_i_2_n_0
|
|
SLICE_X2Y61 LUT6 (Prop_lut6_I2_O) 0.118 2.089 r u_axi_uart_controller/uart0/regs/transmitter/error_time[2]_i_1/O
|
|
net (fo=1, routed) 0.000 2.089 u_axi_uart_controller/uart0/regs/transmitter/error_time[2]_i_1_n_0
|
|
SLICE_X2Y61 FDRE r u_axi_uart_controller/uart0/regs/transmitter/error_time_reg[2]/D
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock sys_clk rise edge) 0.000 0.000 r
|
|
K21 0.000 0.000 r clk (IN)
|
|
net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1
|
|
K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O
|
|
net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll
|
|
PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1)
|
|
-2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1
|
|
net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll
|
|
BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O
|
|
net (fo=10004, routed) 1.000 -0.308 u_axi_uart_controller/uart0/regs/transmitter/sys_clk
|
|
SLICE_X2Y61 FDRE r u_axi_uart_controller/uart0/regs/transmitter/error_time_reg[2]/C
|
|
|
|
Slack: inf
|
|
Source: touch_btn[0]
|
|
(input port)
|
|
Destination: u_confreg/u_int_ctrl/int_in_sync_d1_reg[0]/D
|
|
(rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Path Group: (none)
|
|
Path Type: Hold (Min at Fast Process Corner)
|
|
Data Path Delay: 2.121ns (logic 0.267ns (12.568%) route 1.855ns (87.432%))
|
|
Logic Levels: 1 (IBUF=1)
|
|
Clock Path Skew: -0.339ns (DCD - SCD - CPR)
|
|
Destination Clock Delay (DCD): -0.339ns
|
|
Source Clock Delay (SCD): 0.000ns
|
|
Clock Pessimism Removal (CPR): -0.000ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
T2 0.000 0.000 r touch_btn[0] (IN)
|
|
net (fo=0) 0.000 0.000 touch_btn[0]
|
|
T2 IBUF (Prop_ibuf_I_O) 0.267 0.267 r touch_btn_IBUF[0]_inst/O
|
|
net (fo=1, routed) 1.855 2.121 u_confreg/u_int_ctrl/int_in_sync_d1_reg[6]_0[0]
|
|
SLICE_X13Y89 FDCE r u_confreg/u_int_ctrl/int_in_sync_d1_reg[0]/D
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock sys_clk rise edge) 0.000 0.000 r
|
|
K21 0.000 0.000 r clk (IN)
|
|
net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1
|
|
K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O
|
|
net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll
|
|
PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1)
|
|
-2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1
|
|
net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll
|
|
BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O
|
|
net (fo=10004, routed) 0.969 -0.339 u_confreg/u_int_ctrl/sys_clk
|
|
SLICE_X13Y89 FDCE r u_confreg/u_int_ctrl/int_in_sync_d1_reg[0]/C
|
|
|
|
Slack: inf
|
|
Source: UART_TX
|
|
(input port)
|
|
Destination: u_axi_uart_controller/uart0/regs/transmitter/error_time_reg[1]/D
|
|
(rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Path Group: (none)
|
|
Path Type: Hold (Min at Fast Process Corner)
|
|
Data Path Delay: 2.315ns (logic 0.406ns (17.548%) route 1.909ns (82.452%))
|
|
Logic Levels: 3 (IBUF=1 LUT2=1 LUT5=1)
|
|
Clock Path Skew: -0.308ns (DCD - SCD - CPR)
|
|
Destination Clock Delay (DCD): -0.308ns
|
|
Source Clock Delay (SCD): 0.000ns
|
|
Clock Pessimism Removal (CPR): -0.000ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
H18 0.000 0.000 f UART_TX (INOUT)
|
|
net (fo=1, unset) 0.000 0.000 UART_TX_IOBUF_inst/IO
|
|
H18 IBUF (Prop_ibuf_I_O) 0.242 0.242 f UART_TX_IOBUF_inst/IBUF/O
|
|
net (fo=4, routed) 1.550 1.793 u_axi_uart_controller/uart0/regs/transmitter/UART_TX_IBUF
|
|
SLICE_X2Y60 LUT2 (Prop_lut2_I1_O) 0.048 1.841 r u_axi_uart_controller/uart0/regs/transmitter/error_time[2]_i_2/O
|
|
net (fo=2, routed) 0.239 2.080 u_axi_uart_controller/uart0/regs/transmitter/error_time[2]_i_2_n_0
|
|
SLICE_X2Y60 LUT5 (Prop_lut5_I1_O) 0.116 2.196 r u_axi_uart_controller/uart0/regs/transmitter/error_time[1]_i_1/O
|
|
net (fo=1, routed) 0.119 2.315 u_axi_uart_controller/uart0/regs/transmitter/error_time[1]_i_1_n_0
|
|
SLICE_X2Y60 FDRE r u_axi_uart_controller/uart0/regs/transmitter/error_time_reg[1]/D
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock sys_clk rise edge) 0.000 0.000 r
|
|
K21 0.000 0.000 r clk (IN)
|
|
net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1
|
|
K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O
|
|
net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll
|
|
PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1)
|
|
-2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1
|
|
net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll
|
|
BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O
|
|
net (fo=10004, routed) 1.000 -0.308 u_axi_uart_controller/uart0/regs/transmitter/sys_clk
|
|
SLICE_X2Y60 FDRE r u_axi_uart_controller/uart0/regs/transmitter/error_time_reg[1]/C
|
|
|
|
Slack: inf
|
|
Source: dip_sw[31]
|
|
(input port)
|
|
Destination: u_confreg/s_rdata_reg[31]/D
|
|
(rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Path Group: (none)
|
|
Path Type: Hold (Min at Fast Process Corner)
|
|
Data Path Delay: 2.513ns (logic 0.351ns (13.984%) route 2.162ns (86.016%))
|
|
Logic Levels: 3 (IBUF=1 LUT5=1 LUT6=1)
|
|
Clock Path Skew: -0.310ns (DCD - SCD - CPR)
|
|
Destination Clock Delay (DCD): -0.310ns
|
|
Source Clock Delay (SCD): 0.000ns
|
|
Clock Pessimism Removal (CPR): -0.000ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
R2 0.000 0.000 r dip_sw[31] (IN)
|
|
net (fo=0) 0.000 0.000 dip_sw[31]
|
|
R2 IBUF (Prop_ibuf_I_O) 0.261 0.261 r dip_sw_IBUF[31]_inst/O
|
|
net (fo=1, routed) 1.988 2.249 u_confreg/dip_sw_IBUF[31]
|
|
SLICE_X2Y92 LUT5 (Prop_lut5_I4_O) 0.045 2.294 r u_confreg/s_rdata[31]_i_6/O
|
|
net (fo=1, routed) 0.174 2.468 u_confreg/u_int_ctrl/s_rdata_reg[31]_2
|
|
SLICE_X5Y88 LUT6 (Prop_lut6_I4_O) 0.045 2.513 r u_confreg/u_int_ctrl/s_rdata[31]_i_1/O
|
|
net (fo=1, routed) 0.000 2.513 u_confreg/u_int_ctrl_n_0
|
|
SLICE_X5Y88 FDRE r u_confreg/s_rdata_reg[31]/D
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock sys_clk rise edge) 0.000 0.000 r
|
|
K21 0.000 0.000 r clk (IN)
|
|
net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1
|
|
K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O
|
|
net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll
|
|
PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1)
|
|
-2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1
|
|
net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll
|
|
BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O
|
|
net (fo=10004, routed) 0.998 -0.310 u_confreg/sys_clk
|
|
SLICE_X5Y88 FDRE r u_confreg/s_rdata_reg[31]/C
|
|
|
|
Slack: inf
|
|
Source: dip_sw[27]
|
|
(input port)
|
|
Destination: u_confreg/s_rdata_reg[27]/D
|
|
(rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Path Group: (none)
|
|
Path Type: Hold (Min at Fast Process Corner)
|
|
Data Path Delay: 2.522ns (logic 0.362ns (14.372%) route 2.159ns (85.628%))
|
|
Logic Levels: 3 (IBUF=1 LUT5=1 LUT6=1)
|
|
Clock Path Skew: -0.338ns (DCD - SCD - CPR)
|
|
Destination Clock Delay (DCD): -0.338ns
|
|
Source Clock Delay (SCD): 0.000ns
|
|
Clock Pessimism Removal (CPR): -0.000ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
R1 0.000 0.000 r dip_sw[27] (IN)
|
|
net (fo=0) 0.000 0.000 dip_sw[27]
|
|
R1 IBUF (Prop_ibuf_I_O) 0.272 0.272 r dip_sw_IBUF[27]_inst/O
|
|
net (fo=1, routed) 1.804 2.076 u_confreg/dip_sw_IBUF[27]
|
|
SLICE_X6Y93 LUT5 (Prop_lut5_I4_O) 0.045 2.121 r u_confreg/s_rdata[27]_i_4/O
|
|
net (fo=1, routed) 0.356 2.477 u_confreg/u_int_ctrl/s_rdata_reg[27]_0
|
|
SLICE_X8Y88 LUT6 (Prop_lut6_I4_O) 0.045 2.522 r u_confreg/u_int_ctrl/s_rdata[27]_i_1/O
|
|
net (fo=1, routed) 0.000 2.522 u_confreg/u_int_ctrl_n_4
|
|
SLICE_X8Y88 FDRE r u_confreg/s_rdata_reg[27]/D
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock sys_clk rise edge) 0.000 0.000 r
|
|
K21 0.000 0.000 r clk (IN)
|
|
net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1
|
|
K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O
|
|
net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll
|
|
PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1)
|
|
-2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1
|
|
net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll
|
|
BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O
|
|
net (fo=10004, routed) 0.970 -0.338 u_confreg/sys_clk
|
|
SLICE_X8Y88 FDRE r u_confreg/s_rdata_reg[27]/C
|
|
|
|
Slack: inf
|
|
Source: dip_sw[22]
|
|
(input port)
|
|
Destination: u_confreg/s_rdata_reg[22]/D
|
|
(rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Path Group: (none)
|
|
Path Type: Hold (Min at Fast Process Corner)
|
|
Data Path Delay: 2.618ns (logic 0.320ns (12.234%) route 2.298ns (87.766%))
|
|
Logic Levels: 3 (IBUF=1 LUT5=1 LUT6=1)
|
|
Clock Path Skew: -0.310ns (DCD - SCD - CPR)
|
|
Destination Clock Delay (DCD): -0.310ns
|
|
Source Clock Delay (SCD): 0.000ns
|
|
Clock Pessimism Removal (CPR): -0.000ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
P6 0.000 0.000 r dip_sw[22] (IN)
|
|
net (fo=0) 0.000 0.000 dip_sw[22]
|
|
P6 IBUF (Prop_ibuf_I_O) 0.230 0.230 r dip_sw_IBUF[22]_inst/O
|
|
net (fo=1, routed) 1.991 2.221 u_confreg/dip_sw_IBUF[22]
|
|
SLICE_X1Y94 LUT5 (Prop_lut5_I4_O) 0.045 2.266 r u_confreg/s_rdata[22]_i_4/O
|
|
net (fo=1, routed) 0.307 2.573 u_confreg/u_int_ctrl/s_rdata_reg[22]_0
|
|
SLICE_X4Y88 LUT6 (Prop_lut6_I4_O) 0.045 2.618 r u_confreg/u_int_ctrl/s_rdata[22]_i_1/O
|
|
net (fo=1, routed) 0.000 2.618 u_confreg/u_int_ctrl_n_9
|
|
SLICE_X4Y88 FDRE r u_confreg/s_rdata_reg[22]/D
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock sys_clk rise edge) 0.000 0.000 r
|
|
K21 0.000 0.000 r clk (IN)
|
|
net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1
|
|
K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O
|
|
net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll
|
|
PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1)
|
|
-2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1
|
|
net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll
|
|
BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O
|
|
net (fo=10004, routed) 0.998 -0.310 u_confreg/sys_clk
|
|
SLICE_X4Y88 FDRE r u_confreg/s_rdata_reg[22]/C
|
|
|
|
Slack: inf
|
|
Source: dip_sw[28]
|
|
(input port)
|
|
Destination: u_confreg/s_rdata_reg[28]/D
|
|
(rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Path Group: (none)
|
|
Path Type: Hold (Min at Fast Process Corner)
|
|
Data Path Delay: 2.622ns (logic 0.326ns (12.419%) route 2.296ns (87.581%))
|
|
Logic Levels: 3 (IBUF=1 LUT5=1 LUT6=1)
|
|
Clock Path Skew: -0.310ns (DCD - SCD - CPR)
|
|
Destination Clock Delay (DCD): -0.310ns
|
|
Source Clock Delay (SCD): 0.000ns
|
|
Clock Pessimism Removal (CPR): -0.000ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
R5 0.000 0.000 r dip_sw[28] (IN)
|
|
net (fo=0) 0.000 0.000 dip_sw[28]
|
|
R5 IBUF (Prop_ibuf_I_O) 0.236 0.236 r dip_sw_IBUF[28]_inst/O
|
|
net (fo=1, routed) 2.141 2.376 u_confreg/dip_sw_IBUF[28]
|
|
SLICE_X6Y92 LUT5 (Prop_lut5_I4_O) 0.045 2.421 r u_confreg/s_rdata[28]_i_4/O
|
|
net (fo=1, routed) 0.155 2.577 u_confreg/u_int_ctrl/s_rdata_reg[28]_0
|
|
SLICE_X5Y89 LUT6 (Prop_lut6_I4_O) 0.045 2.622 r u_confreg/u_int_ctrl/s_rdata[28]_i_1/O
|
|
net (fo=1, routed) 0.000 2.622 u_confreg/u_int_ctrl_n_3
|
|
SLICE_X5Y89 FDRE r u_confreg/s_rdata_reg[28]/D
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock sys_clk rise edge) 0.000 0.000 r
|
|
K21 0.000 0.000 r clk (IN)
|
|
net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1
|
|
K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O
|
|
net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll
|
|
PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1)
|
|
-2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1
|
|
net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll
|
|
BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O
|
|
net (fo=10004, routed) 0.998 -0.310 u_confreg/sys_clk
|
|
SLICE_X5Y89 FDRE r u_confreg/s_rdata_reg[28]/C
|
|
|
|
Slack: inf
|
|
Source: dip_sw[30]
|
|
(input port)
|
|
Destination: u_confreg/s_rdata_reg[30]/D
|
|
(rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Path Group: (none)
|
|
Path Type: Hold (Min at Fast Process Corner)
|
|
Data Path Delay: 2.648ns (logic 0.317ns (11.976%) route 2.331ns (88.024%))
|
|
Logic Levels: 3 (IBUF=1 LUT5=1 LUT6=1)
|
|
Clock Path Skew: -0.308ns (DCD - SCD - CPR)
|
|
Destination Clock Delay (DCD): -0.308ns
|
|
Source Clock Delay (SCD): 0.000ns
|
|
Clock Pessimism Removal (CPR): -0.000ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
R6 0.000 0.000 r dip_sw[30] (IN)
|
|
net (fo=0) 0.000 0.000 dip_sw[30]
|
|
R6 IBUF (Prop_ibuf_I_O) 0.227 0.227 r dip_sw_IBUF[30]_inst/O
|
|
net (fo=1, routed) 1.934 2.162 u_confreg/dip_sw_IBUF[30]
|
|
SLICE_X2Y93 LUT5 (Prop_lut5_I4_O) 0.045 2.207 r u_confreg/s_rdata[30]_i_4/O
|
|
net (fo=1, routed) 0.396 2.603 u_confreg/u_int_ctrl/s_rdata_reg[30]_0
|
|
SLICE_X2Y88 LUT6 (Prop_lut6_I4_O) 0.045 2.648 r u_confreg/u_int_ctrl/s_rdata[30]_i_1/O
|
|
net (fo=1, routed) 0.000 2.648 u_confreg/u_int_ctrl_n_1
|
|
SLICE_X2Y88 FDRE r u_confreg/s_rdata_reg[30]/D
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock sys_clk rise edge) 0.000 0.000 r
|
|
K21 0.000 0.000 r clk (IN)
|
|
net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1
|
|
K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O
|
|
net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll
|
|
PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1)
|
|
-2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1
|
|
net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll
|
|
BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O
|
|
net (fo=10004, routed) 1.000 -0.308 u_confreg/sys_clk
|
|
SLICE_X2Y88 FDRE r u_confreg/s_rdata_reg[30]/C
|
|
|
|
Slack: inf
|
|
Source: dip_sw[18]
|
|
(input port)
|
|
Destination: u_confreg/s_rdata_reg[18]/D
|
|
(rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Path Group: (none)
|
|
Path Type: Hold (Min at Fast Process Corner)
|
|
Data Path Delay: 2.666ns (logic 0.347ns (13.011%) route 2.319ns (86.989%))
|
|
Logic Levels: 3 (IBUF=1 LUT5=1 LUT6=1)
|
|
Clock Path Skew: -0.340ns (DCD - SCD - CPR)
|
|
Destination Clock Delay (DCD): -0.340ns
|
|
Source Clock Delay (SCD): 0.000ns
|
|
Clock Pessimism Removal (CPR): -0.000ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
N3 0.000 0.000 r dip_sw[18] (IN)
|
|
net (fo=0) 0.000 0.000 dip_sw[18]
|
|
N3 IBUF (Prop_ibuf_I_O) 0.257 0.257 r dip_sw_IBUF[18]_inst/O
|
|
net (fo=1, routed) 2.090 2.347 u_confreg/dip_sw_IBUF[18]
|
|
SLICE_X8Y87 LUT5 (Prop_lut5_I4_O) 0.045 2.392 r u_confreg/s_rdata[18]_i_4/O
|
|
net (fo=1, routed) 0.229 2.621 u_confreg/u_int_ctrl/s_rdata_reg[18]_0
|
|
SLICE_X8Y87 LUT6 (Prop_lut6_I4_O) 0.045 2.666 r u_confreg/u_int_ctrl/s_rdata[18]_i_1/O
|
|
net (fo=1, routed) 0.000 2.666 u_confreg/u_int_ctrl_n_13
|
|
SLICE_X8Y87 FDRE r u_confreg/s_rdata_reg[18]/D
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock sys_clk rise edge) 0.000 0.000 r
|
|
K21 0.000 0.000 r clk (IN)
|
|
net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1
|
|
K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O
|
|
net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll
|
|
PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1)
|
|
-2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1
|
|
net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll
|
|
BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O
|
|
net (fo=10004, routed) 0.968 -0.340 u_confreg/sys_clk
|
|
SLICE_X8Y87 FDRE r u_confreg/s_rdata_reg[18]/C
|
|
|
|
Slack: inf
|
|
Source: dip_sw[29]
|
|
(input port)
|
|
Destination: u_confreg/s_rdata_reg[29]/D
|
|
(rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Path Group: (none)
|
|
Path Type: Hold (Min at Fast Process Corner)
|
|
Data Path Delay: 2.680ns (logic 0.336ns (12.535%) route 2.344ns (87.465%))
|
|
Logic Levels: 3 (IBUF=1 LUT5=1 LUT6=1)
|
|
Clock Path Skew: -0.308ns (DCD - SCD - CPR)
|
|
Destination Clock Delay (DCD): -0.308ns
|
|
Source Clock Delay (SCD): 0.000ns
|
|
Clock Pessimism Removal (CPR): -0.000ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
T5 0.000 0.000 r dip_sw[29] (IN)
|
|
net (fo=0) 0.000 0.000 dip_sw[29]
|
|
T5 IBUF (Prop_ibuf_I_O) 0.246 0.246 r dip_sw_IBUF[29]_inst/O
|
|
net (fo=1, routed) 1.991 2.237 u_confreg/dip_sw_IBUF[29]
|
|
SLICE_X1Y94 LUT5 (Prop_lut5_I4_O) 0.045 2.282 r u_confreg/s_rdata[29]_i_4/O
|
|
net (fo=1, routed) 0.353 2.635 u_confreg/u_int_ctrl/s_rdata_reg[29]_0
|
|
SLICE_X2Y88 LUT6 (Prop_lut6_I4_O) 0.045 2.680 r u_confreg/u_int_ctrl/s_rdata[29]_i_1/O
|
|
net (fo=1, routed) 0.000 2.680 u_confreg/u_int_ctrl_n_2
|
|
SLICE_X2Y88 FDRE r u_confreg/s_rdata_reg[29]/D
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock sys_clk rise edge) 0.000 0.000 r
|
|
K21 0.000 0.000 r clk (IN)
|
|
net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1
|
|
K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O
|
|
net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll
|
|
PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1)
|
|
-2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1
|
|
net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll
|
|
BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O
|
|
net (fo=10004, routed) 1.000 -0.308 u_confreg/sys_clk
|
|
SLICE_X2Y88 FDRE r u_confreg/s_rdata_reg[29]/C
|
|
|
|
Slack: inf
|
|
Source: dip_sw[12]
|
|
(input port)
|
|
Destination: u_confreg/s_rdata_reg[12]/D
|
|
(rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Path Group: (none)
|
|
Path Type: Hold (Min at Fast Process Corner)
|
|
Data Path Delay: 2.685ns (logic 0.327ns (12.182%) route 2.358ns (87.818%))
|
|
Logic Levels: 3 (IBUF=1 LUT5=1 LUT6=1)
|
|
Clock Path Skew: -0.315ns (DCD - SCD - CPR)
|
|
Destination Clock Delay (DCD): -0.315ns
|
|
Source Clock Delay (SCD): 0.000ns
|
|
Clock Pessimism Removal (CPR): -0.000ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
M5 0.000 0.000 r dip_sw[12] (IN)
|
|
net (fo=0) 0.000 0.000 dip_sw[12]
|
|
M5 IBUF (Prop_ibuf_I_O) 0.237 0.237 r dip_sw_IBUF[12]_inst/O
|
|
net (fo=1, routed) 2.193 2.430 u_confreg/dip_sw_IBUF[12]
|
|
SLICE_X5Y86 LUT5 (Prop_lut5_I4_O) 0.045 2.475 r u_confreg/s_rdata[12]_i_4/O
|
|
net (fo=1, routed) 0.165 2.640 u_confreg/u_int_ctrl/s_rdata_reg[12]_0
|
|
SLICE_X5Y83 LUT6 (Prop_lut6_I4_O) 0.045 2.685 r u_confreg/u_int_ctrl/s_rdata[12]_i_1/O
|
|
net (fo=1, routed) 0.000 2.685 u_confreg/u_int_ctrl_n_19
|
|
SLICE_X5Y83 FDRE r u_confreg/s_rdata_reg[12]/D
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock sys_clk rise edge) 0.000 0.000 r
|
|
K21 0.000 0.000 r clk (IN)
|
|
net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1
|
|
K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O
|
|
net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll
|
|
PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1)
|
|
-2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1
|
|
net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll
|
|
BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O
|
|
net (fo=10004, routed) 0.993 -0.315 u_confreg/sys_clk
|
|
SLICE_X5Y83 FDRE r u_confreg/s_rdata_reg[12]/C
|
|
|
|
Slack: inf
|
|
Source: dip_sw[7]
|
|
(input port)
|
|
Destination: u_confreg/s_rdata_reg[7]/D
|
|
(rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Path Group: (none)
|
|
Path Type: Hold (Min at Fast Process Corner)
|
|
Data Path Delay: 2.753ns (logic 0.329ns (11.958%) route 2.424ns (88.042%))
|
|
Logic Levels: 3 (IBUF=1 LUT5=1 LUT6=1)
|
|
Clock Path Skew: -0.312ns (DCD - SCD - CPR)
|
|
Destination Clock Delay (DCD): -0.312ns
|
|
Source Clock Delay (SCD): 0.000ns
|
|
Clock Pessimism Removal (CPR): -0.000ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
N6 0.000 0.000 r dip_sw[7] (IN)
|
|
net (fo=0) 0.000 0.000 dip_sw[7]
|
|
N6 IBUF (Prop_ibuf_I_O) 0.239 0.239 r dip_sw_IBUF[7]_inst/O
|
|
net (fo=1, routed) 2.373 2.612 u_confreg/dip_sw_IBUF[7]
|
|
SLICE_X1Y84 LUT5 (Prop_lut5_I4_O) 0.045 2.657 r u_confreg/s_rdata[7]_i_4/O
|
|
net (fo=1, routed) 0.051 2.708 u_confreg/u_int_ctrl/s_rdata_reg[7]_0
|
|
SLICE_X1Y84 LUT6 (Prop_lut6_I4_O) 0.045 2.753 r u_confreg/u_int_ctrl/s_rdata[7]_i_1/O
|
|
net (fo=1, routed) 0.000 2.753 u_confreg/u_int_ctrl_n_24
|
|
SLICE_X1Y84 FDRE r u_confreg/s_rdata_reg[7]/D
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock sys_clk rise edge) 0.000 0.000 r
|
|
K21 0.000 0.000 r clk (IN)
|
|
net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1
|
|
K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O
|
|
net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll
|
|
PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1)
|
|
-2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1
|
|
net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll
|
|
BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O
|
|
net (fo=10004, routed) 0.996 -0.312 u_confreg/sys_clk
|
|
SLICE_X1Y84 FDRE r u_confreg/s_rdata_reg[7]/C
|
|
|
|
Slack: inf
|
|
Source: dip_sw[24]
|
|
(input port)
|
|
Destination: u_confreg/s_rdata_reg[24]/D
|
|
(rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Path Group: (none)
|
|
Path Type: Hold (Min at Fast Process Corner)
|
|
Data Path Delay: 2.843ns (logic 0.324ns (11.413%) route 2.518ns (88.587%))
|
|
Logic Levels: 3 (IBUF=1 LUT5=1 LUT6=1)
|
|
Clock Path Skew: -0.310ns (DCD - SCD - CPR)
|
|
Destination Clock Delay (DCD): -0.310ns
|
|
Source Clock Delay (SCD): 0.000ns
|
|
Clock Pessimism Removal (CPR): -0.000ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
P5 0.000 0.000 r dip_sw[24] (IN)
|
|
net (fo=0) 0.000 0.000 dip_sw[24]
|
|
P5 IBUF (Prop_ibuf_I_O) 0.234 0.234 r dip_sw_IBUF[24]_inst/O
|
|
net (fo=1, routed) 2.106 2.340 u_confreg/dip_sw_IBUF[24]
|
|
SLICE_X5Y93 LUT5 (Prop_lut5_I4_O) 0.045 2.385 r u_confreg/s_rdata[24]_i_4/O
|
|
net (fo=1, routed) 0.412 2.798 u_confreg/u_int_ctrl/s_rdata_reg[24]_0
|
|
SLICE_X5Y89 LUT6 (Prop_lut6_I4_O) 0.045 2.843 r u_confreg/u_int_ctrl/s_rdata[24]_i_1/O
|
|
net (fo=1, routed) 0.000 2.843 u_confreg/u_int_ctrl_n_7
|
|
SLICE_X5Y89 FDRE r u_confreg/s_rdata_reg[24]/D
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock sys_clk rise edge) 0.000 0.000 r
|
|
K21 0.000 0.000 r clk (IN)
|
|
net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1
|
|
K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O
|
|
net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll
|
|
PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1)
|
|
-2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1
|
|
net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll
|
|
BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O
|
|
net (fo=10004, routed) 0.998 -0.310 u_confreg/sys_clk
|
|
SLICE_X5Y89 FDRE r u_confreg/s_rdata_reg[24]/C
|
|
|
|
Slack: inf
|
|
Source: touch_btn[1]
|
|
(input port)
|
|
Destination: u_confreg/u_int_ctrl/int_in_sync_d1_reg[1]/D
|
|
(rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Path Group: (none)
|
|
Path Type: Hold (Min at Fast Process Corner)
|
|
Data Path Delay: 2.881ns (logic 0.283ns (9.807%) route 2.599ns (90.193%))
|
|
Logic Levels: 1 (IBUF=1)
|
|
Clock Path Skew: -0.339ns (DCD - SCD - CPR)
|
|
Destination Clock Delay (DCD): -0.339ns
|
|
Source Clock Delay (SCD): 0.000ns
|
|
Clock Pessimism Removal (CPR): -0.000ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
M1 0.000 0.000 r touch_btn[1] (IN)
|
|
net (fo=0) 0.000 0.000 touch_btn[1]
|
|
M1 IBUF (Prop_ibuf_I_O) 0.283 0.283 r touch_btn_IBUF[1]_inst/O
|
|
net (fo=1, routed) 2.599 2.881 u_confreg/u_int_ctrl/int_in_sync_d1_reg[6]_0[1]
|
|
SLICE_X13Y89 FDCE r u_confreg/u_int_ctrl/int_in_sync_d1_reg[1]/D
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock sys_clk rise edge) 0.000 0.000 r
|
|
K21 0.000 0.000 r clk (IN)
|
|
net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1
|
|
K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O
|
|
net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll
|
|
PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1)
|
|
-2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1
|
|
net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll
|
|
BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O
|
|
net (fo=10004, routed) 0.969 -0.339 u_confreg/u_int_ctrl/sys_clk
|
|
SLICE_X13Y89 FDCE r u_confreg/u_int_ctrl/int_in_sync_d1_reg[1]/C
|
|
|
|
Slack: inf
|
|
Source: dip_sw[3]
|
|
(input port)
|
|
Destination: u_confreg/s_rdata_reg[3]/D
|
|
(rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Path Group: (none)
|
|
Path Type: Hold (Min at Fast Process Corner)
|
|
Data Path Delay: 2.900ns (logic 0.362ns (12.483%) route 2.538ns (87.517%))
|
|
Logic Levels: 3 (IBUF=1 LUT5=1 LUT6=1)
|
|
Clock Path Skew: -0.319ns (DCD - SCD - CPR)
|
|
Destination Clock Delay (DCD): -0.319ns
|
|
Source Clock Delay (SCD): 0.000ns
|
|
Clock Pessimism Removal (CPR): -0.000ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
P1 0.000 0.000 r dip_sw[3] (IN)
|
|
net (fo=0) 0.000 0.000 dip_sw[3]
|
|
P1 IBUF (Prop_ibuf_I_O) 0.272 0.272 r dip_sw_IBUF[3]_inst/O
|
|
net (fo=1, routed) 2.197 2.469 u_confreg/dip_sw_IBUF[3]
|
|
SLICE_X4Y92 LUT5 (Prop_lut5_I4_O) 0.045 2.514 r u_confreg/s_rdata[3]_i_4/O
|
|
net (fo=1, routed) 0.340 2.855 u_confreg/u_int_ctrl/s_rdata_reg[3]_0
|
|
SLICE_X5Y79 LUT6 (Prop_lut6_I4_O) 0.045 2.900 r u_confreg/u_int_ctrl/s_rdata[3]_i_1/O
|
|
net (fo=1, routed) 0.000 2.900 u_confreg/u_int_ctrl_n_28
|
|
SLICE_X5Y79 FDRE r u_confreg/s_rdata_reg[3]/D
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock sys_clk rise edge) 0.000 0.000 r
|
|
K21 0.000 0.000 r clk (IN)
|
|
net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1
|
|
K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O
|
|
net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll
|
|
PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1)
|
|
-2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1
|
|
net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll
|
|
BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O
|
|
net (fo=10004, routed) 0.989 -0.319 u_confreg/sys_clk
|
|
SLICE_X5Y79 FDRE r u_confreg/s_rdata_reg[3]/C
|
|
|
|
Slack: inf
|
|
Source: dip_sw[16]
|
|
(input port)
|
|
Destination: u_confreg/s_rdata_reg[16]/D
|
|
(rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Path Group: (none)
|
|
Path Type: Hold (Min at Fast Process Corner)
|
|
Data Path Delay: 2.965ns (logic 0.358ns (12.066%) route 2.607ns (87.934%))
|
|
Logic Levels: 3 (IBUF=1 LUT5=1 LUT6=1)
|
|
Clock Path Skew: -0.310ns (DCD - SCD - CPR)
|
|
Destination Clock Delay (DCD): -0.310ns
|
|
Source Clock Delay (SCD): 0.000ns
|
|
Clock Pessimism Removal (CPR): -0.000ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
K2 0.000 0.000 r dip_sw[16] (IN)
|
|
net (fo=0) 0.000 0.000 dip_sw[16]
|
|
K2 IBUF (Prop_ibuf_I_O) 0.268 0.268 r dip_sw_IBUF[16]_inst/O
|
|
net (fo=1, routed) 2.496 2.764 u_confreg/dip_sw_IBUF[16]
|
|
SLICE_X7Y91 LUT5 (Prop_lut5_I4_O) 0.045 2.809 r u_confreg/s_rdata[16]_i_4/O
|
|
net (fo=1, routed) 0.111 2.920 u_confreg/u_int_ctrl/s_rdata_reg[16]_0
|
|
SLICE_X7Y89 LUT6 (Prop_lut6_I4_O) 0.045 2.965 r u_confreg/u_int_ctrl/s_rdata[16]_i_1/O
|
|
net (fo=1, routed) 0.000 2.965 u_confreg/u_int_ctrl_n_15
|
|
SLICE_X7Y89 FDRE r u_confreg/s_rdata_reg[16]/D
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock sys_clk rise edge) 0.000 0.000 r
|
|
K21 0.000 0.000 r clk (IN)
|
|
net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1
|
|
K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O
|
|
net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll
|
|
PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1)
|
|
-2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1
|
|
net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll
|
|
BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O
|
|
net (fo=10004, routed) 0.998 -0.310 u_confreg/sys_clk
|
|
SLICE_X7Y89 FDRE r u_confreg/s_rdata_reg[16]/C
|
|
|
|
Slack: inf
|
|
Source: dip_sw[0]
|
|
(input port)
|
|
Destination: u_confreg/s_rdata_reg[0]/D
|
|
(rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Path Group: (none)
|
|
Path Type: Hold (Min at Fast Process Corner)
|
|
Data Path Delay: 2.973ns (logic 0.353ns (11.866%) route 2.620ns (88.134%))
|
|
Logic Levels: 3 (IBUF=1 LUT5=1 LUT6=1)
|
|
Clock Path Skew: -0.316ns (DCD - SCD - CPR)
|
|
Destination Clock Delay (DCD): -0.316ns
|
|
Source Clock Delay (SCD): 0.000ns
|
|
Clock Pessimism Removal (CPR): -0.000ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
T3 0.000 0.000 r dip_sw[0] (IN)
|
|
net (fo=0) 0.000 0.000 dip_sw[0]
|
|
T3 IBUF (Prop_ibuf_I_O) 0.263 0.263 r dip_sw_IBUF[0]_inst/O
|
|
net (fo=1, routed) 2.278 2.541 u_confreg/dip_sw_IBUF[0]
|
|
SLICE_X5Y93 LUT5 (Prop_lut5_I4_O) 0.045 2.586 r u_confreg/s_rdata[0]_i_4/O
|
|
net (fo=1, routed) 0.342 2.928 u_confreg/u_int_ctrl/s_rdata_reg[0]_0
|
|
SLICE_X5Y82 LUT6 (Prop_lut6_I4_O) 0.045 2.973 r u_confreg/u_int_ctrl/s_rdata[0]_i_1/O
|
|
net (fo=1, routed) 0.000 2.973 u_confreg/u_int_ctrl_n_31
|
|
SLICE_X5Y82 FDRE r u_confreg/s_rdata_reg[0]/D
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock sys_clk rise edge) 0.000 0.000 r
|
|
K21 0.000 0.000 r clk (IN)
|
|
net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1
|
|
K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O
|
|
net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll
|
|
PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1)
|
|
-2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1
|
|
net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll
|
|
BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O
|
|
net (fo=10004, routed) 0.992 -0.316 u_confreg/sys_clk
|
|
SLICE_X5Y82 FDRE r u_confreg/s_rdata_reg[0]/C
|
|
|
|
Slack: inf
|
|
Source: touch_btn[3]
|
|
(input port)
|
|
Destination: u_confreg/u_int_ctrl/int_in_sync_d1_reg[3]/D
|
|
(rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Path Group: (none)
|
|
Path Type: Hold (Min at Fast Process Corner)
|
|
Data Path Delay: 2.974ns (logic 0.280ns (9.424%) route 2.694ns (90.576%))
|
|
Logic Levels: 1 (IBUF=1)
|
|
Clock Path Skew: -0.317ns (DCD - SCD - CPR)
|
|
Destination Clock Delay (DCD): -0.317ns
|
|
Source Clock Delay (SCD): 0.000ns
|
|
Clock Pessimism Removal (CPR): -0.000ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
U2 0.000 0.000 r touch_btn[3] (IN)
|
|
net (fo=0) 0.000 0.000 touch_btn[3]
|
|
U2 IBUF (Prop_ibuf_I_O) 0.280 0.280 r touch_btn_IBUF[3]_inst/O
|
|
net (fo=1, routed) 2.694 2.974 u_confreg/u_int_ctrl/int_in_sync_d1_reg[6]_0[3]
|
|
SLICE_X1Y79 FDCE r u_confreg/u_int_ctrl/int_in_sync_d1_reg[3]/D
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock sys_clk rise edge) 0.000 0.000 r
|
|
K21 0.000 0.000 r clk (IN)
|
|
net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1
|
|
K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O
|
|
net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll
|
|
PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1)
|
|
-2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1
|
|
net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll
|
|
BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O
|
|
net (fo=10004, routed) 0.991 -0.317 u_confreg/u_int_ctrl/sys_clk
|
|
SLICE_X1Y79 FDCE r u_confreg/u_int_ctrl/int_in_sync_d1_reg[3]/C
|
|
|
|
Slack: inf
|
|
Source: dip_sw[14]
|
|
(input port)
|
|
Destination: u_confreg/s_rdata_reg[14]/D
|
|
(rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Path Group: (none)
|
|
Path Type: Hold (Min at Fast Process Corner)
|
|
Data Path Delay: 2.984ns (logic 0.373ns (12.482%) route 2.612ns (87.518%))
|
|
Logic Levels: 3 (IBUF=1 LUT5=1 LUT6=1)
|
|
Clock Path Skew: -0.310ns (DCD - SCD - CPR)
|
|
Destination Clock Delay (DCD): -0.310ns
|
|
Source Clock Delay (SCD): 0.000ns
|
|
Clock Pessimism Removal (CPR): -0.000ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
J1 0.000 0.000 r dip_sw[14] (IN)
|
|
net (fo=0) 0.000 0.000 dip_sw[14]
|
|
J1 IBUF (Prop_ibuf_I_O) 0.283 0.283 r dip_sw_IBUF[14]_inst/O
|
|
net (fo=1, routed) 2.273 2.555 u_confreg/dip_sw_IBUF[14]
|
|
SLICE_X5Y93 LUT5 (Prop_lut5_I4_O) 0.045 2.600 r u_confreg/s_rdata[14]_i_4/O
|
|
net (fo=1, routed) 0.339 2.939 u_confreg/u_int_ctrl/s_rdata_reg[14]_0
|
|
SLICE_X5Y89 LUT6 (Prop_lut6_I4_O) 0.045 2.984 r u_confreg/u_int_ctrl/s_rdata[14]_i_1/O
|
|
net (fo=1, routed) 0.000 2.984 u_confreg/u_int_ctrl_n_17
|
|
SLICE_X5Y89 FDRE r u_confreg/s_rdata_reg[14]/D
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock sys_clk rise edge) 0.000 0.000 r
|
|
K21 0.000 0.000 r clk (IN)
|
|
net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1
|
|
K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O
|
|
net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll
|
|
PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1)
|
|
-2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1
|
|
net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll
|
|
BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O
|
|
net (fo=10004, routed) 0.998 -0.310 u_confreg/sys_clk
|
|
SLICE_X5Y89 FDRE r u_confreg/s_rdata_reg[14]/C
|
|
|
|
Slack: inf
|
|
Source: dip_sw[21]
|
|
(input port)
|
|
Destination: u_confreg/s_rdata_reg[21]/D
|
|
(rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Path Group: (none)
|
|
Path Type: Hold (Min at Fast Process Corner)
|
|
Data Path Delay: 2.997ns (logic 0.346ns (11.544%) route 2.651ns (88.456%))
|
|
Logic Levels: 3 (IBUF=1 LUT5=1 LUT6=1)
|
|
Clock Path Skew: -0.338ns (DCD - SCD - CPR)
|
|
Destination Clock Delay (DCD): -0.338ns
|
|
Source Clock Delay (SCD): 0.000ns
|
|
Clock Pessimism Removal (CPR): -0.000ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
N2 0.000 0.000 r dip_sw[21] (IN)
|
|
net (fo=0) 0.000 0.000 dip_sw[21]
|
|
N2 IBUF (Prop_ibuf_I_O) 0.256 0.256 r dip_sw_IBUF[21]_inst/O
|
|
net (fo=1, routed) 2.278 2.534 u_confreg/dip_sw_IBUF[21]
|
|
SLICE_X7Y93 LUT5 (Prop_lut5_I4_O) 0.045 2.579 r u_confreg/s_rdata[21]_i_4/O
|
|
net (fo=1, routed) 0.373 2.952 u_confreg/u_int_ctrl/s_rdata_reg[21]_0
|
|
SLICE_X8Y88 LUT6 (Prop_lut6_I4_O) 0.045 2.997 r u_confreg/u_int_ctrl/s_rdata[21]_i_1/O
|
|
net (fo=1, routed) 0.000 2.997 u_confreg/u_int_ctrl_n_10
|
|
SLICE_X8Y88 FDRE r u_confreg/s_rdata_reg[21]/D
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock sys_clk rise edge) 0.000 0.000 r
|
|
K21 0.000 0.000 r clk (IN)
|
|
net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1
|
|
K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O
|
|
net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll
|
|
PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1)
|
|
-2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1
|
|
net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll
|
|
BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O
|
|
net (fo=10004, routed) 0.970 -0.338 u_confreg/sys_clk
|
|
SLICE_X8Y88 FDRE r u_confreg/s_rdata_reg[21]/C
|
|
|
|
Slack: inf
|
|
Source: dip_sw[6]
|
|
(input port)
|
|
Destination: u_confreg/s_rdata_reg[6]/D
|
|
(rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Path Group: (none)
|
|
Path Type: Hold (Min at Fast Process Corner)
|
|
Data Path Delay: 3.000ns (logic 0.346ns (11.523%) route 2.655ns (88.477%))
|
|
Logic Levels: 3 (IBUF=1 LUT5=1 LUT6=1)
|
|
Clock Path Skew: -0.315ns (DCD - SCD - CPR)
|
|
Destination Clock Delay (DCD): -0.315ns
|
|
Source Clock Delay (SCD): 0.000ns
|
|
Clock Pessimism Removal (CPR): -0.000ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
L3 0.000 0.000 r dip_sw[6] (IN)
|
|
net (fo=0) 0.000 0.000 dip_sw[6]
|
|
L3 IBUF (Prop_ibuf_I_O) 0.256 0.256 r dip_sw_IBUF[6]_inst/O
|
|
net (fo=1, routed) 2.297 2.553 u_confreg/dip_sw_IBUF[6]
|
|
SLICE_X5Y92 LUT5 (Prop_lut5_I4_O) 0.045 2.598 r u_confreg/s_rdata[6]_i_4/O
|
|
net (fo=1, routed) 0.358 2.955 u_confreg/u_int_ctrl/s_rdata_reg[6]_0
|
|
SLICE_X5Y83 LUT6 (Prop_lut6_I4_O) 0.045 3.000 r u_confreg/u_int_ctrl/s_rdata[6]_i_1/O
|
|
net (fo=1, routed) 0.000 3.000 u_confreg/u_int_ctrl_n_25
|
|
SLICE_X5Y83 FDRE r u_confreg/s_rdata_reg[6]/D
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock sys_clk rise edge) 0.000 0.000 r
|
|
K21 0.000 0.000 r clk (IN)
|
|
net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1
|
|
K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O
|
|
net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll
|
|
PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1)
|
|
-2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1
|
|
net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll
|
|
BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O
|
|
net (fo=10004, routed) 0.993 -0.315 u_confreg/sys_clk
|
|
SLICE_X5Y83 FDRE r u_confreg/s_rdata_reg[6]/C
|
|
|
|
Slack: inf
|
|
Source: dip_sw[26]
|
|
(input port)
|
|
Destination: u_confreg/s_rdata_reg[26]/D
|
|
(rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Path Group: (none)
|
|
Path Type: Hold (Min at Fast Process Corner)
|
|
Data Path Delay: 3.025ns (logic 0.367ns (12.128%) route 2.658ns (87.872%))
|
|
Logic Levels: 3 (IBUF=1 LUT5=1 LUT6=1)
|
|
Clock Path Skew: -0.340ns (DCD - SCD - CPR)
|
|
Destination Clock Delay (DCD): -0.340ns
|
|
Source Clock Delay (SCD): 0.000ns
|
|
Clock Pessimism Removal (CPR): -0.000ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
T4 0.000 0.000 r dip_sw[26] (IN)
|
|
net (fo=0) 0.000 0.000 dip_sw[26]
|
|
T4 IBUF (Prop_ibuf_I_O) 0.277 0.277 r dip_sw_IBUF[26]_inst/O
|
|
net (fo=1, routed) 2.208 2.485 u_confreg/dip_sw_IBUF[26]
|
|
SLICE_X6Y93 LUT5 (Prop_lut5_I4_O) 0.045 2.530 r u_confreg/s_rdata[26]_i_4/O
|
|
net (fo=1, routed) 0.450 2.980 u_confreg/u_int_ctrl/s_rdata_reg[26]_0
|
|
SLICE_X8Y87 LUT6 (Prop_lut6_I4_O) 0.045 3.025 r u_confreg/u_int_ctrl/s_rdata[26]_i_1/O
|
|
net (fo=1, routed) 0.000 3.025 u_confreg/u_int_ctrl_n_5
|
|
SLICE_X8Y87 FDRE r u_confreg/s_rdata_reg[26]/D
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock sys_clk rise edge) 0.000 0.000 r
|
|
K21 0.000 0.000 r clk (IN)
|
|
net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1
|
|
K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O
|
|
net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll
|
|
PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1)
|
|
-2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1
|
|
net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll
|
|
BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O
|
|
net (fo=10004, routed) 0.968 -0.340 u_confreg/sys_clk
|
|
SLICE_X8Y87 FDRE r u_confreg/s_rdata_reg[26]/C
|
|
|
|
Slack: inf
|
|
Source: dip_sw[10]
|
|
(input port)
|
|
Destination: u_confreg/s_rdata_reg[10]/D
|
|
(rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Path Group: (none)
|
|
Path Type: Hold (Min at Fast Process Corner)
|
|
Data Path Delay: 3.067ns (logic 0.330ns (10.763%) route 2.737ns (89.237%))
|
|
Logic Levels: 3 (IBUF=1 LUT5=1 LUT6=1)
|
|
Clock Path Skew: -0.345ns (DCD - SCD - CPR)
|
|
Destination Clock Delay (DCD): -0.345ns
|
|
Source Clock Delay (SCD): 0.000ns
|
|
Clock Pessimism Removal (CPR): -0.000ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
M7 0.000 0.000 r dip_sw[10] (IN)
|
|
net (fo=0) 0.000 0.000 dip_sw[10]
|
|
M7 IBUF (Prop_ibuf_I_O) 0.240 0.240 r dip_sw_IBUF[10]_inst/O
|
|
net (fo=1, routed) 2.590 2.830 u_confreg/dip_sw_IBUF[10]
|
|
SLICE_X8Y80 LUT5 (Prop_lut5_I4_O) 0.045 2.875 r u_confreg/s_rdata[10]_i_4/O
|
|
net (fo=1, routed) 0.147 3.022 u_confreg/u_int_ctrl/s_rdata_reg[10]_0
|
|
SLICE_X8Y81 LUT6 (Prop_lut6_I4_O) 0.045 3.067 r u_confreg/u_int_ctrl/s_rdata[10]_i_1/O
|
|
net (fo=1, routed) 0.000 3.067 u_confreg/u_int_ctrl_n_21
|
|
SLICE_X8Y81 FDRE r u_confreg/s_rdata_reg[10]/D
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock sys_clk rise edge) 0.000 0.000 r
|
|
K21 0.000 0.000 r clk (IN)
|
|
net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1
|
|
K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O
|
|
net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll
|
|
PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1)
|
|
-2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1
|
|
net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll
|
|
BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O
|
|
net (fo=10004, routed) 0.963 -0.345 u_confreg/sys_clk
|
|
SLICE_X8Y81 FDRE r u_confreg/s_rdata_reg[10]/C
|
|
|
|
Slack: inf
|
|
Source: dip_sw[15]
|
|
(input port)
|
|
Destination: u_confreg/s_rdata_reg[15]/D
|
|
(rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Path Group: (none)
|
|
Path Type: Hold (Min at Fast Process Corner)
|
|
Data Path Delay: 3.091ns (logic 0.352ns (11.385%) route 2.739ns (88.615%))
|
|
Logic Levels: 3 (IBUF=1 LUT5=1 LUT6=1)
|
|
Clock Path Skew: -0.310ns (DCD - SCD - CPR)
|
|
Destination Clock Delay (DCD): -0.310ns
|
|
Source Clock Delay (SCD): 0.000ns
|
|
Clock Pessimism Removal (CPR): -0.000ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
L2 0.000 0.000 r dip_sw[15] (IN)
|
|
net (fo=0) 0.000 0.000 dip_sw[15]
|
|
L2 IBUF (Prop_ibuf_I_O) 0.262 0.262 r dip_sw_IBUF[15]_inst/O
|
|
net (fo=1, routed) 2.453 2.715 u_confreg/dip_sw_IBUF[15]
|
|
SLICE_X1Y95 LUT5 (Prop_lut5_I4_O) 0.045 2.760 r u_confreg/s_rdata[15]_i_4/O
|
|
net (fo=1, routed) 0.285 3.046 u_confreg/u_int_ctrl/s_rdata_reg[15]_0
|
|
SLICE_X5Y89 LUT6 (Prop_lut6_I4_O) 0.045 3.091 r u_confreg/u_int_ctrl/s_rdata[15]_i_1/O
|
|
net (fo=1, routed) 0.000 3.091 u_confreg/u_int_ctrl_n_16
|
|
SLICE_X5Y89 FDRE r u_confreg/s_rdata_reg[15]/D
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock sys_clk rise edge) 0.000 0.000 r
|
|
K21 0.000 0.000 r clk (IN)
|
|
net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1
|
|
K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O
|
|
net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll
|
|
PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1)
|
|
-2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1
|
|
net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll
|
|
BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O
|
|
net (fo=10004, routed) 0.998 -0.310 u_confreg/sys_clk
|
|
SLICE_X5Y89 FDRE r u_confreg/s_rdata_reg[15]/C
|
|
|
|
Slack: inf
|
|
Source: dip_sw[5]
|
|
(input port)
|
|
Destination: u_confreg/s_rdata_reg[5]/D
|
|
(rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Path Group: (none)
|
|
Path Type: Hold (Min at Fast Process Corner)
|
|
Data Path Delay: 3.122ns (logic 0.328ns (10.518%) route 2.794ns (89.482%))
|
|
Logic Levels: 3 (IBUF=1 LUT5=1 LUT6=1)
|
|
Clock Path Skew: -0.345ns (DCD - SCD - CPR)
|
|
Destination Clock Delay (DCD): -0.345ns
|
|
Source Clock Delay (SCD): 0.000ns
|
|
Clock Pessimism Removal (CPR): -0.000ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
L5 0.000 0.000 r dip_sw[5] (IN)
|
|
net (fo=0) 0.000 0.000 dip_sw[5]
|
|
L5 IBUF (Prop_ibuf_I_O) 0.238 0.238 r dip_sw_IBUF[5]_inst/O
|
|
net (fo=1, routed) 2.365 2.604 u_confreg/dip_sw_IBUF[5]
|
|
SLICE_X7Y91 LUT5 (Prop_lut5_I4_O) 0.045 2.649 r u_confreg/s_rdata[5]_i_4/O
|
|
net (fo=1, routed) 0.428 3.077 u_confreg/u_int_ctrl/s_rdata_reg[5]_0
|
|
SLICE_X8Y81 LUT6 (Prop_lut6_I4_O) 0.045 3.122 r u_confreg/u_int_ctrl/s_rdata[5]_i_1/O
|
|
net (fo=1, routed) 0.000 3.122 u_confreg/u_int_ctrl_n_26
|
|
SLICE_X8Y81 FDRE r u_confreg/s_rdata_reg[5]/D
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock sys_clk rise edge) 0.000 0.000 r
|
|
K21 0.000 0.000 r clk (IN)
|
|
net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1
|
|
K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O
|
|
net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll
|
|
PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1)
|
|
-2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1
|
|
net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll
|
|
BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O
|
|
net (fo=10004, routed) 0.963 -0.345 u_confreg/sys_clk
|
|
SLICE_X8Y81 FDRE r u_confreg/s_rdata_reg[5]/C
|
|
|
|
Slack: inf
|
|
Source: dip_sw[2]
|
|
(input port)
|
|
Destination: u_confreg/s_rdata_reg[2]/D
|
|
(rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Path Group: (none)
|
|
Path Type: Hold (Min at Fast Process Corner)
|
|
Data Path Delay: 3.123ns (logic 0.353ns (11.299%) route 2.770ns (88.701%))
|
|
Logic Levels: 3 (IBUF=1 LUT5=1 LUT6=1)
|
|
Clock Path Skew: -0.345ns (DCD - SCD - CPR)
|
|
Destination Clock Delay (DCD): -0.345ns
|
|
Source Clock Delay (SCD): 0.000ns
|
|
Clock Pessimism Removal (CPR): -0.000ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
M2 0.000 0.000 r dip_sw[2] (IN)
|
|
net (fo=0) 0.000 0.000 dip_sw[2]
|
|
M2 IBUF (Prop_ibuf_I_O) 0.263 0.263 r dip_sw_IBUF[2]_inst/O
|
|
net (fo=1, routed) 2.335 2.598 u_confreg/dip_sw_IBUF[2]
|
|
SLICE_X6Y92 LUT5 (Prop_lut5_I4_O) 0.045 2.643 r u_confreg/s_rdata[2]_i_4/O
|
|
net (fo=1, routed) 0.435 3.078 u_confreg/u_int_ctrl/s_rdata_reg[2]_0
|
|
SLICE_X8Y81 LUT6 (Prop_lut6_I4_O) 0.045 3.123 r u_confreg/u_int_ctrl/s_rdata[2]_i_1/O
|
|
net (fo=1, routed) 0.000 3.123 u_confreg/u_int_ctrl_n_29
|
|
SLICE_X8Y81 FDRE r u_confreg/s_rdata_reg[2]/D
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock sys_clk rise edge) 0.000 0.000 r
|
|
K21 0.000 0.000 r clk (IN)
|
|
net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1
|
|
K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O
|
|
net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll
|
|
PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1)
|
|
-2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1
|
|
net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll
|
|
BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O
|
|
net (fo=10004, routed) 0.963 -0.345 u_confreg/sys_clk
|
|
SLICE_X8Y81 FDRE r u_confreg/s_rdata_reg[2]/C
|
|
|
|
Slack: inf
|
|
Source: dip_sw[17]
|
|
(input port)
|
|
Destination: u_confreg/s_rdata_reg[17]/D
|
|
(rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Path Group: (none)
|
|
Path Type: Hold (Min at Fast Process Corner)
|
|
Data Path Delay: 3.171ns (logic 0.362ns (11.408%) route 2.809ns (88.593%))
|
|
Logic Levels: 3 (IBUF=1 LUT5=1 LUT6=1)
|
|
Clock Path Skew: -0.310ns (DCD - SCD - CPR)
|
|
Destination Clock Delay (DCD): -0.310ns
|
|
Source Clock Delay (SCD): 0.000ns
|
|
Clock Pessimism Removal (CPR): -0.000ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
K1 0.000 0.000 r dip_sw[17] (IN)
|
|
net (fo=0) 0.000 0.000 dip_sw[17]
|
|
K1 IBUF (Prop_ibuf_I_O) 0.272 0.272 r dip_sw_IBUF[17]_inst/O
|
|
net (fo=1, routed) 2.515 2.787 u_confreg/dip_sw_IBUF[17]
|
|
SLICE_X5Y92 LUT5 (Prop_lut5_I4_O) 0.045 2.832 r u_confreg/s_rdata[17]_i_4/O
|
|
net (fo=1, routed) 0.294 3.126 u_confreg/u_int_ctrl/s_rdata_reg[17]_0
|
|
SLICE_X7Y89 LUT6 (Prop_lut6_I4_O) 0.045 3.171 r u_confreg/u_int_ctrl/s_rdata[17]_i_1/O
|
|
net (fo=1, routed) 0.000 3.171 u_confreg/u_int_ctrl_n_14
|
|
SLICE_X7Y89 FDRE r u_confreg/s_rdata_reg[17]/D
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock sys_clk rise edge) 0.000 0.000 r
|
|
K21 0.000 0.000 r clk (IN)
|
|
net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1
|
|
K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O
|
|
net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll
|
|
PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1)
|
|
-2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1
|
|
net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll
|
|
BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O
|
|
net (fo=10004, routed) 0.998 -0.310 u_confreg/sys_clk
|
|
SLICE_X7Y89 FDRE r u_confreg/s_rdata_reg[17]/C
|
|
|
|
Slack: inf
|
|
Source: dip_sw[23]
|
|
(input port)
|
|
Destination: u_confreg/s_rdata_reg[23]/D
|
|
(rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Path Group: (none)
|
|
Path Type: Hold (Min at Fast Process Corner)
|
|
Data Path Delay: 3.218ns (logic 0.376ns (11.683%) route 2.842ns (88.317%))
|
|
Logic Levels: 3 (IBUF=1 LUT5=1 LUT6=1)
|
|
Clock Path Skew: -0.338ns (DCD - SCD - CPR)
|
|
Destination Clock Delay (DCD): -0.338ns
|
|
Source Clock Delay (SCD): 0.000ns
|
|
Clock Pessimism Removal (CPR): -0.000ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
N1 0.000 0.000 r dip_sw[23] (IN)
|
|
net (fo=0) 0.000 0.000 dip_sw[23]
|
|
N1 IBUF (Prop_ibuf_I_O) 0.286 0.286 r dip_sw_IBUF[23]_inst/O
|
|
net (fo=1, routed) 2.402 2.688 u_confreg/dip_sw_IBUF[23]
|
|
SLICE_X7Y93 LUT5 (Prop_lut5_I4_O) 0.045 2.733 r u_confreg/s_rdata[23]_i_4/O
|
|
net (fo=1, routed) 0.440 3.173 u_confreg/u_int_ctrl/s_rdata_reg[23]_0
|
|
SLICE_X8Y88 LUT6 (Prop_lut6_I4_O) 0.045 3.218 r u_confreg/u_int_ctrl/s_rdata[23]_i_1/O
|
|
net (fo=1, routed) 0.000 3.218 u_confreg/u_int_ctrl_n_8
|
|
SLICE_X8Y88 FDRE r u_confreg/s_rdata_reg[23]/D
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock sys_clk rise edge) 0.000 0.000 r
|
|
K21 0.000 0.000 r clk (IN)
|
|
net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1
|
|
K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O
|
|
net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll
|
|
PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1)
|
|
-2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1
|
|
net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll
|
|
BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O
|
|
net (fo=10004, routed) 0.970 -0.338 u_confreg/sys_clk
|
|
SLICE_X8Y88 FDRE r u_confreg/s_rdata_reg[23]/C
|
|
|
|
Slack: inf
|
|
Source: dip_sw[4]
|
|
(input port)
|
|
Destination: u_confreg/s_rdata_reg[4]/D
|
|
(rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Path Group: (none)
|
|
Path Type: Hold (Min at Fast Process Corner)
|
|
Data Path Delay: 3.278ns (logic 0.346ns (10.553%) route 2.932ns (89.447%))
|
|
Logic Levels: 3 (IBUF=1 LUT5=1 LUT6=1)
|
|
Clock Path Skew: -0.313ns (DCD - SCD - CPR)
|
|
Destination Clock Delay (DCD): -0.313ns
|
|
Source Clock Delay (SCD): 0.000ns
|
|
Clock Pessimism Removal (CPR): -0.000ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
P4 0.000 0.000 r dip_sw[4] (IN)
|
|
net (fo=0) 0.000 0.000 dip_sw[4]
|
|
P4 IBUF (Prop_ibuf_I_O) 0.256 0.256 r dip_sw_IBUF[4]_inst/O
|
|
net (fo=1, routed) 2.708 2.964 u_confreg/dip_sw_IBUF[4]
|
|
SLICE_X2Y85 LUT5 (Prop_lut5_I4_O) 0.045 3.009 r u_confreg/s_rdata[4]_i_4/O
|
|
net (fo=1, routed) 0.224 3.233 u_confreg/u_int_ctrl/s_rdata_reg[4]_0
|
|
SLICE_X2Y83 LUT6 (Prop_lut6_I4_O) 0.045 3.278 r u_confreg/u_int_ctrl/s_rdata[4]_i_1/O
|
|
net (fo=1, routed) 0.000 3.278 u_confreg/u_int_ctrl_n_27
|
|
SLICE_X2Y83 FDRE r u_confreg/s_rdata_reg[4]/D
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock sys_clk rise edge) 0.000 0.000 r
|
|
K21 0.000 0.000 r clk (IN)
|
|
net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1
|
|
K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O
|
|
net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll
|
|
PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1)
|
|
-2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1
|
|
net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll
|
|
BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O
|
|
net (fo=10004, routed) 0.995 -0.313 u_confreg/sys_clk
|
|
SLICE_X2Y83 FDRE r u_confreg/s_rdata_reg[4]/C
|
|
|
|
Slack: inf
|
|
Source: dip_sw[9]
|
|
(input port)
|
|
Destination: u_confreg/s_rdata_reg[9]/D
|
|
(rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Path Group: (none)
|
|
Path Type: Hold (Min at Fast Process Corner)
|
|
Data Path Delay: 3.293ns (logic 0.328ns (9.951%) route 2.965ns (90.049%))
|
|
Logic Levels: 3 (IBUF=1 LUT5=1 LUT6=1)
|
|
Clock Path Skew: -0.316ns (DCD - SCD - CPR)
|
|
Destination Clock Delay (DCD): -0.316ns
|
|
Source Clock Delay (SCD): 0.000ns
|
|
Clock Pessimism Removal (CPR): -0.000ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
N7 0.000 0.000 r dip_sw[9] (IN)
|
|
net (fo=0) 0.000 0.000 dip_sw[9]
|
|
N7 IBUF (Prop_ibuf_I_O) 0.238 0.238 r dip_sw_IBUF[9]_inst/O
|
|
net (fo=1, routed) 2.752 2.990 u_confreg/dip_sw_IBUF[9]
|
|
SLICE_X1Y80 LUT5 (Prop_lut5_I4_O) 0.045 3.035 r u_confreg/s_rdata[9]_i_4/O
|
|
net (fo=1, routed) 0.213 3.248 u_confreg/u_int_ctrl/s_rdata_reg[9]_0
|
|
SLICE_X1Y80 LUT6 (Prop_lut6_I4_O) 0.045 3.293 r u_confreg/u_int_ctrl/s_rdata[9]_i_1/O
|
|
net (fo=1, routed) 0.000 3.293 u_confreg/u_int_ctrl_n_22
|
|
SLICE_X1Y80 FDRE r u_confreg/s_rdata_reg[9]/D
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock sys_clk rise edge) 0.000 0.000 r
|
|
K21 0.000 0.000 r clk (IN)
|
|
net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1
|
|
K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O
|
|
net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll
|
|
PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1)
|
|
-2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1
|
|
net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll
|
|
BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O
|
|
net (fo=10004, routed) 0.992 -0.316 u_confreg/sys_clk
|
|
SLICE_X1Y80 FDRE r u_confreg/s_rdata_reg[9]/C
|
|
|
|
Slack: inf
|
|
Source: touch_btn[2]
|
|
(input port)
|
|
Destination: u_confreg/u_int_ctrl/int_in_sync_d1_reg[2]/D
|
|
(rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Path Group: (none)
|
|
Path Type: Hold (Min at Fast Process Corner)
|
|
Data Path Delay: 4.287ns (logic 0.255ns (5.940%) route 4.032ns (94.060%))
|
|
Logic Levels: 1 (IBUF=1)
|
|
Clock Path Skew: -0.315ns (DCD - SCD - CPR)
|
|
Destination Clock Delay (DCD): -0.315ns
|
|
Source Clock Delay (SCD): 0.000ns
|
|
Clock Pessimism Removal (CPR): -0.000ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
P3 0.000 0.000 r touch_btn[2] (IN)
|
|
net (fo=0) 0.000 0.000 touch_btn[2]
|
|
P3 IBUF (Prop_ibuf_I_O) 0.255 0.255 r touch_btn_IBUF[2]_inst/O
|
|
net (fo=1, routed) 4.032 4.287 u_confreg/u_int_ctrl/int_in_sync_d1_reg[6]_0[2]
|
|
SLICE_X7Y83 FDCE r u_confreg/u_int_ctrl/int_in_sync_d1_reg[2]/D
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock sys_clk rise edge) 0.000 0.000 r
|
|
K21 0.000 0.000 r clk (IN)
|
|
net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1
|
|
K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O
|
|
net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll
|
|
PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1)
|
|
-2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1
|
|
net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll
|
|
BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O
|
|
net (fo=10004, routed) 0.993 -0.315 u_confreg/u_int_ctrl/sys_clk
|
|
SLICE_X7Y83 FDCE r u_confreg/u_int_ctrl/int_in_sync_d1_reg[2]/C
|
|
|
|
Slack: inf
|
|
Source: dip_sw[19]
|
|
(input port)
|
|
Destination: u_confreg/s_rdata_reg[19]/D
|
|
(rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Path Group: (none)
|
|
Path Type: Hold (Min at Fast Process Corner)
|
|
Data Path Delay: 4.396ns (logic 0.336ns (7.645%) route 4.060ns (92.355%))
|
|
Logic Levels: 3 (IBUF=1 LUT5=1 LUT6=1)
|
|
Clock Path Skew: -0.313ns (DCD - SCD - CPR)
|
|
Destination Clock Delay (DCD): -0.313ns
|
|
Source Clock Delay (SCD): 0.000ns
|
|
Clock Pessimism Removal (CPR): -0.000ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
L4 0.000 0.000 r dip_sw[19] (IN)
|
|
net (fo=0) 0.000 0.000 dip_sw[19]
|
|
L4 IBUF (Prop_ibuf_I_O) 0.246 0.246 r dip_sw_IBUF[19]_inst/O
|
|
net (fo=1, routed) 4.009 4.255 u_confreg/dip_sw_IBUF[19]
|
|
SLICE_X7Y86 LUT5 (Prop_lut5_I4_O) 0.045 4.300 r u_confreg/s_rdata[19]_i_4/O
|
|
net (fo=1, routed) 0.051 4.351 u_confreg/u_int_ctrl/s_rdata_reg[19]_0
|
|
SLICE_X7Y86 LUT6 (Prop_lut6_I4_O) 0.045 4.396 r u_confreg/u_int_ctrl/s_rdata[19]_i_1/O
|
|
net (fo=1, routed) 0.000 4.396 u_confreg/u_int_ctrl_n_12
|
|
SLICE_X7Y86 FDRE r u_confreg/s_rdata_reg[19]/D
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock sys_clk rise edge) 0.000 0.000 r
|
|
K21 0.000 0.000 r clk (IN)
|
|
net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1
|
|
K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O
|
|
net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll
|
|
PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1)
|
|
-2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1
|
|
net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll
|
|
BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O
|
|
net (fo=10004, routed) 0.995 -0.313 u_confreg/sys_clk
|
|
SLICE_X7Y86 FDRE r u_confreg/s_rdata_reg[19]/C
|
|
|
|
Slack: inf
|
|
Source: dip_sw[25]
|
|
(input port)
|
|
Destination: u_confreg/s_rdata_reg[25]/D
|
|
(rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Path Group: (none)
|
|
Path Type: Hold (Min at Fast Process Corner)
|
|
Data Path Delay: 4.440ns (logic 0.347ns (7.817%) route 4.093ns (92.183%))
|
|
Logic Levels: 3 (IBUF=1 LUT5=1 LUT6=1)
|
|
Clock Path Skew: -0.338ns (DCD - SCD - CPR)
|
|
Destination Clock Delay (DCD): -0.338ns
|
|
Source Clock Delay (SCD): 0.000ns
|
|
Clock Pessimism Removal (CPR): -0.000ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
R3 0.000 0.000 r dip_sw[25] (IN)
|
|
net (fo=0) 0.000 0.000 dip_sw[25]
|
|
R3 IBUF (Prop_ibuf_I_O) 0.257 0.257 r dip_sw_IBUF[25]_inst/O
|
|
net (fo=1, routed) 3.854 4.111 u_confreg/dip_sw_IBUF[25]
|
|
SLICE_X9Y88 LUT5 (Prop_lut5_I4_O) 0.045 4.156 r u_confreg/s_rdata[25]_i_4/O
|
|
net (fo=1, routed) 0.239 4.395 u_confreg/u_int_ctrl/s_rdata_reg[25]_0
|
|
SLICE_X8Y88 LUT6 (Prop_lut6_I4_O) 0.045 4.440 r u_confreg/u_int_ctrl/s_rdata[25]_i_1/O
|
|
net (fo=1, routed) 0.000 4.440 u_confreg/u_int_ctrl_n_6
|
|
SLICE_X8Y88 FDRE r u_confreg/s_rdata_reg[25]/D
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock sys_clk rise edge) 0.000 0.000 r
|
|
K21 0.000 0.000 r clk (IN)
|
|
net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1
|
|
K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O
|
|
net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll
|
|
PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1)
|
|
-2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1
|
|
net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll
|
|
BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O
|
|
net (fo=10004, routed) 0.970 -0.338 u_confreg/sys_clk
|
|
SLICE_X8Y88 FDRE r u_confreg/s_rdata_reg[25]/C
|
|
|
|
Slack: inf
|
|
Source: dip_sw[11]
|
|
(input port)
|
|
Destination: u_confreg/s_rdata_reg[11]/D
|
|
(rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Path Group: (none)
|
|
Path Type: Hold (Min at Fast Process Corner)
|
|
Data Path Delay: 4.518ns (logic 0.329ns (7.286%) route 4.189ns (92.714%))
|
|
Logic Levels: 3 (IBUF=1 LUT5=1 LUT6=1)
|
|
Clock Path Skew: -0.316ns (DCD - SCD - CPR)
|
|
Destination Clock Delay (DCD): -0.316ns
|
|
Source Clock Delay (SCD): 0.000ns
|
|
Clock Pessimism Removal (CPR): -0.000ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
L7 0.000 0.000 r dip_sw[11] (IN)
|
|
net (fo=0) 0.000 0.000 dip_sw[11]
|
|
L7 IBUF (Prop_ibuf_I_O) 0.239 0.239 r dip_sw_IBUF[11]_inst/O
|
|
net (fo=1, routed) 3.969 4.208 u_confreg/dip_sw_IBUF[11]
|
|
SLICE_X4Y82 LUT5 (Prop_lut5_I4_O) 0.045 4.253 r u_confreg/s_rdata[11]_i_4/O
|
|
net (fo=1, routed) 0.220 4.473 u_confreg/u_int_ctrl/s_rdata_reg[11]_0
|
|
SLICE_X5Y82 LUT6 (Prop_lut6_I4_O) 0.045 4.518 r u_confreg/u_int_ctrl/s_rdata[11]_i_1/O
|
|
net (fo=1, routed) 0.000 4.518 u_confreg/u_int_ctrl_n_20
|
|
SLICE_X5Y82 FDRE r u_confreg/s_rdata_reg[11]/D
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock sys_clk rise edge) 0.000 0.000 r
|
|
K21 0.000 0.000 r clk (IN)
|
|
net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1
|
|
K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O
|
|
net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll
|
|
PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1)
|
|
-2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1
|
|
net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll
|
|
BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O
|
|
net (fo=10004, routed) 0.992 -0.316 u_confreg/sys_clk
|
|
SLICE_X5Y82 FDRE r u_confreg/s_rdata_reg[11]/C
|
|
|
|
Slack: inf
|
|
Source: dip_sw[13]
|
|
(input port)
|
|
Destination: u_confreg/s_rdata_reg[13]/D
|
|
(rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Path Group: (none)
|
|
Path Type: Hold (Min at Fast Process Corner)
|
|
Data Path Delay: 4.727ns (logic 0.344ns (7.270%) route 4.383ns (92.730%))
|
|
Logic Levels: 3 (IBUF=1 LUT5=1 LUT6=1)
|
|
Clock Path Skew: -0.310ns (DCD - SCD - CPR)
|
|
Destination Clock Delay (DCD): -0.310ns
|
|
Source Clock Delay (SCD): 0.000ns
|
|
Clock Pessimism Removal (CPR): -0.000ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
K3 0.000 0.000 r dip_sw[13] (IN)
|
|
net (fo=0) 0.000 0.000 dip_sw[13]
|
|
K3 IBUF (Prop_ibuf_I_O) 0.254 0.254 r dip_sw_IBUF[13]_inst/O
|
|
net (fo=1, routed) 4.162 4.416 u_confreg/dip_sw_IBUF[13]
|
|
SLICE_X4Y92 LUT5 (Prop_lut5_I4_O) 0.045 4.461 r u_confreg/s_rdata[13]_i_4/O
|
|
net (fo=1, routed) 0.221 4.682 u_confreg/u_int_ctrl/s_rdata_reg[13]_0
|
|
SLICE_X5Y88 LUT6 (Prop_lut6_I4_O) 0.045 4.727 r u_confreg/u_int_ctrl/s_rdata[13]_i_1/O
|
|
net (fo=1, routed) 0.000 4.727 u_confreg/u_int_ctrl_n_18
|
|
SLICE_X5Y88 FDRE r u_confreg/s_rdata_reg[13]/D
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock sys_clk rise edge) 0.000 0.000 r
|
|
K21 0.000 0.000 r clk (IN)
|
|
net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1
|
|
K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O
|
|
net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll
|
|
PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1)
|
|
-2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1
|
|
net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll
|
|
BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O
|
|
net (fo=10004, routed) 0.998 -0.310 u_confreg/sys_clk
|
|
SLICE_X5Y88 FDRE r u_confreg/s_rdata_reg[13]/C
|
|
|
|
Slack: inf
|
|
Source: dip_sw[1]
|
|
(input port)
|
|
Destination: u_confreg/s_rdata_reg[1]/D
|
|
(rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Path Group: (none)
|
|
Path Type: Hold (Min at Fast Process Corner)
|
|
Data Path Delay: 4.729ns (logic 0.355ns (7.516%) route 4.374ns (92.484%))
|
|
Logic Levels: 3 (IBUF=1 LUT5=1 LUT6=1)
|
|
Clock Path Skew: -0.345ns (DCD - SCD - CPR)
|
|
Destination Clock Delay (DCD): -0.345ns
|
|
Source Clock Delay (SCD): 0.000ns
|
|
Clock Pessimism Removal (CPR): -0.000ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
J3 0.000 0.000 r dip_sw[1] (IN)
|
|
net (fo=0) 0.000 0.000 dip_sw[1]
|
|
J3 IBUF (Prop_ibuf_I_O) 0.265 0.265 r dip_sw_IBUF[1]_inst/O
|
|
net (fo=1, routed) 3.965 4.231 u_confreg/dip_sw_IBUF[1]
|
|
SLICE_X6Y92 LUT5 (Prop_lut5_I4_O) 0.045 4.276 r u_confreg/s_rdata[1]_i_4/O
|
|
net (fo=1, routed) 0.409 4.684 u_confreg/u_int_ctrl/s_rdata_reg[1]_0
|
|
SLICE_X8Y81 LUT6 (Prop_lut6_I4_O) 0.045 4.729 r u_confreg/u_int_ctrl/s_rdata[1]_i_1/O
|
|
net (fo=1, routed) 0.000 4.729 u_confreg/u_int_ctrl_n_30
|
|
SLICE_X8Y81 FDRE r u_confreg/s_rdata_reg[1]/D
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock sys_clk rise edge) 0.000 0.000 r
|
|
K21 0.000 0.000 r clk (IN)
|
|
net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1
|
|
K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O
|
|
net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll
|
|
PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1)
|
|
-2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1
|
|
net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll
|
|
BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O
|
|
net (fo=10004, routed) 0.963 -0.345 u_confreg/sys_clk
|
|
SLICE_X8Y81 FDRE r u_confreg/s_rdata_reg[1]/C
|
|
|
|
Slack: inf
|
|
Source: dip_sw[20]
|
|
(input port)
|
|
Destination: u_confreg/s_rdata_reg[20]/D
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(rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
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Path Group: (none)
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Path Type: Hold (Min at Fast Process Corner)
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Data Path Delay: 4.977ns (logic 0.333ns (6.690%) route 4.644ns (93.310%))
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Logic Levels: 3 (IBUF=1 LUT5=1 LUT6=1)
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Clock Path Skew: -0.310ns (DCD - SCD - CPR)
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Destination Clock Delay (DCD): -0.310ns
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Source Clock Delay (SCD): 0.000ns
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Clock Pessimism Removal (CPR): -0.000ns
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Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
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------------------------------------------------------------------- -------------------
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M4 0.000 0.000 r dip_sw[20] (IN)
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net (fo=0) 0.000 0.000 dip_sw[20]
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M4 IBUF (Prop_ibuf_I_O) 0.243 0.243 r dip_sw_IBUF[20]_inst/O
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net (fo=1, routed) 4.258 4.501 u_confreg/dip_sw_IBUF[20]
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SLICE_X7Y92 LUT5 (Prop_lut5_I4_O) 0.045 4.546 r u_confreg/s_rdata[20]_i_4/O
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net (fo=1, routed) 0.386 4.932 u_confreg/u_int_ctrl/s_rdata_reg[20]_0
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SLICE_X7Y89 LUT6 (Prop_lut6_I4_O) 0.045 4.977 r u_confreg/u_int_ctrl/s_rdata[20]_i_1/O
|
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net (fo=1, routed) 0.000 4.977 u_confreg/u_int_ctrl_n_11
|
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SLICE_X7Y89 FDRE r u_confreg/s_rdata_reg[20]/D
|
|
------------------------------------------------------------------- -------------------
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|
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(clock sys_clk rise edge) 0.000 0.000 r
|
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K21 0.000 0.000 r clk (IN)
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net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1
|
|
K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O
|
|
net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll
|
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PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1)
|
|
-2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1
|
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net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll
|
|
BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O
|
|
net (fo=10004, routed) 0.998 -0.310 u_confreg/sys_clk
|
|
SLICE_X7Y89 FDRE r u_confreg/s_rdata_reg[20]/C
|
|
|
|
Slack: inf
|
|
Source: dip_sw[8]
|
|
(input port)
|
|
Destination: u_confreg/s_rdata_reg[8]/D
|
|
(rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Path Group: (none)
|
|
Path Type: Hold (Min at Fast Process Corner)
|
|
Data Path Delay: 5.044ns (logic 0.334ns (6.614%) route 4.711ns (93.386%))
|
|
Logic Levels: 3 (IBUF=1 LUT5=1 LUT6=1)
|
|
Clock Path Skew: -0.319ns (DCD - SCD - CPR)
|
|
Destination Clock Delay (DCD): -0.319ns
|
|
Source Clock Delay (SCD): 0.000ns
|
|
Clock Pessimism Removal (CPR): -0.000ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
M6 0.000 0.000 r dip_sw[8] (IN)
|
|
net (fo=0) 0.000 0.000 dip_sw[8]
|
|
M6 IBUF (Prop_ibuf_I_O) 0.244 0.244 r dip_sw_IBUF[8]_inst/O
|
|
net (fo=1, routed) 4.491 4.735 u_confreg/dip_sw_IBUF[8]
|
|
SLICE_X5Y79 LUT5 (Prop_lut5_I4_O) 0.045 4.780 r u_confreg/s_rdata[8]_i_4/O
|
|
net (fo=1, routed) 0.220 4.999 u_confreg/u_int_ctrl/s_rdata_reg[8]_0
|
|
SLICE_X5Y79 LUT6 (Prop_lut6_I4_O) 0.045 5.044 r u_confreg/u_int_ctrl/s_rdata[8]_i_1/O
|
|
net (fo=1, routed) 0.000 5.044 u_confreg/u_int_ctrl_n_23
|
|
SLICE_X5Y79 FDRE r u_confreg/s_rdata_reg[8]/D
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock sys_clk rise edge) 0.000 0.000 r
|
|
K21 0.000 0.000 r clk (IN)
|
|
net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1
|
|
K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O
|
|
net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll
|
|
PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1)
|
|
-2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1
|
|
net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll
|
|
BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O
|
|
net (fo=10004, routed) 0.989 -0.319 u_confreg/sys_clk
|
|
SLICE_X5Y79 FDRE r u_confreg/s_rdata_reg[8]/C
|
|
|
|
|
|
|
|
|
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|