5217 lines
422 KiB
Plaintext
5217 lines
422 KiB
Plaintext
Copyright 1986-2019 Xilinx, Inc. All Rights Reserved.
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----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
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| Tool Version : Vivado v.2019.2 (lin64) Build 2708876 Wed Nov 6 21:39:14 MST 2019
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| Date : Wed Jul 8 03:34:13 2026
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| Host : fedora running 64-bit unknown
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| Command : report_timing -from [get_clocks mlkem_clk_clk_pll] -to [get_clocks mlkem_clk_clk_pll] -delay_type max -max_paths 100 -nworst 10 -path_type full -input_pins -file /home/fallensigh/vivado_reports_nodsp/mlkem_clk_timing.rpt
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| Design : soc_top
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| Device : 7a200t-fbg676
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| Speed File : -1 PRODUCTION 1.23 2018-06-13
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----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
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Timing Report
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Slack (MET) : 10.807ns (required time - arrival time)
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Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/C
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(rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns})
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Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[827]/D
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(rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns})
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Path Group: mlkem_clk_clk_pll
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Path Type: Setup (Max at Slow Process Corner)
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Requirement: 40.000ns (mlkem_clk_clk_pll rise@40.000ns - mlkem_clk_clk_pll rise@0.000ns)
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Data Path Delay: 29.049ns (logic 0.704ns (2.423%) route 28.345ns (97.577%))
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Logic Levels: 2 (LUT5=1 LUT6=1)
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Clock Path Skew: -0.096ns (DCD - SCD + CPR)
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Destination Clock Delay (DCD): -2.279ns = ( 37.721 - 40.000 )
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Source Clock Delay (SCD): -2.690ns
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Clock Pessimism Removal (CPR): -0.507ns
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Clock Uncertainty: 0.077ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
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Total System Jitter (TSJ): 0.071ns
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Discrete Jitter (DJ): 0.136ns
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Phase Error (PE): 0.000ns
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Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
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------------------------------------------------------------------- -------------------
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(clock mlkem_clk_clk_pll rise edge)
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0.000 0.000 r
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clock source latency -6.275 -6.275
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propagated clock network latency
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3.586 -2.690
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SLICE_X91Y121 FDCE 0.000 -2.690 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/C
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SLICE_X91Y121 FDCE (Prop_fdce_C_Q) 0.456 -2.234 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/Q
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net (fo=169, routed) 6.237 4.004 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st[4]
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SLICE_X157Y96 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/I0
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SLICE_X157Y96 LUT5 (Prop_lut5_I0_O) 0.124 4.128 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/O
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net (fo=936, routed) 22.108 26.236 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/sha3_mb_en0
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SLICE_X45Y135 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[827]_i_1/I1
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SLICE_X45Y135 LUT6 (Prop_lut6_I1_O) 0.124 26.360 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[827]_i_1/O
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net (fo=1, routed) 0.000 26.360 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram_n_470
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SLICE_X45Y135 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[827]/D
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------------------------------------------------------------------- -------------------
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(clock mlkem_clk_clk_pll rise edge)
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40.000 40.000 r
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clock source latency -5.674 34.326
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propagated clock network latency
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3.396 37.721
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clock pessimism -0.507 37.214
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clock uncertainty -0.077 37.138
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SLICE_X45Y135 FDCE (Setup_fdce_C_D) 0.029 37.167 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[827]
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-------------------------------------------------------------------
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required time 37.167
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arrival time -26.360
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-------------------------------------------------------------------
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slack 10.807
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Slack (MET) : 10.807ns (required time - arrival time)
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Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/C
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(rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns})
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Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[827]/D
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(rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns})
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Path Group: mlkem_clk_clk_pll
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Path Type: Setup (Max at Slow Process Corner)
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Requirement: 40.000ns (mlkem_clk_clk_pll rise@40.000ns - mlkem_clk_clk_pll rise@0.000ns)
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Data Path Delay: 29.049ns (logic 0.704ns (2.423%) route 28.345ns (97.577%))
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Logic Levels: 2 (LUT5=1 LUT6=1)
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Clock Path Skew: -0.096ns (DCD - SCD + CPR)
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Destination Clock Delay (DCD): -2.279ns = ( 37.721 - 40.000 )
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Source Clock Delay (SCD): -2.690ns
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Clock Pessimism Removal (CPR): -0.507ns
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Clock Uncertainty: 0.077ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
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Total System Jitter (TSJ): 0.071ns
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Discrete Jitter (DJ): 0.136ns
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Phase Error (PE): 0.000ns
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Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
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------------------------------------------------------------------- -------------------
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(clock mlkem_clk_clk_pll rise edge)
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0.000 0.000 r
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clock source latency -6.275 -6.275
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propagated clock network latency
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3.586 -2.690
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SLICE_X91Y121 FDCE 0.000 -2.690 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/C
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SLICE_X91Y121 FDCE (Prop_fdce_C_Q) 0.456 -2.234 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/Q
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net (fo=169, routed) 6.237 4.004 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st[4]
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SLICE_X157Y96 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/I0
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SLICE_X157Y96 LUT5 (Prop_lut5_I0_O) 0.124 4.128 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/O
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net (fo=936, routed) 22.108 26.236 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/sha3_mb_en0
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SLICE_X45Y135 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[827]_i_1/I1
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SLICE_X45Y135 LUT6 (Prop_lut6_I1_O) 0.124 26.360 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[827]_i_1/O
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net (fo=1, routed) 0.000 26.360 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram_n_470
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SLICE_X45Y135 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[827]/D
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------------------------------------------------------------------- -------------------
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(clock mlkem_clk_clk_pll rise edge)
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40.000 40.000 r
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clock source latency -5.674 34.326
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propagated clock network latency
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3.396 37.721
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clock pessimism -0.507 37.214
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clock uncertainty -0.077 37.138
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SLICE_X45Y135 FDCE (Setup_fdce_C_D) 0.029 37.167 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[827]
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-------------------------------------------------------------------
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required time 37.167
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arrival time -26.360
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-------------------------------------------------------------------
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slack 10.807
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Slack (MET) : 10.807ns (required time - arrival time)
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Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/C
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(rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns})
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Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[827]/D
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(rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns})
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Path Group: mlkem_clk_clk_pll
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Path Type: Setup (Max at Slow Process Corner)
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Requirement: 40.000ns (mlkem_clk_clk_pll rise@40.000ns - mlkem_clk_clk_pll rise@0.000ns)
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Data Path Delay: 29.049ns (logic 0.704ns (2.423%) route 28.345ns (97.577%))
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Logic Levels: 2 (LUT5=1 LUT6=1)
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Clock Path Skew: -0.096ns (DCD - SCD + CPR)
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Destination Clock Delay (DCD): -2.279ns = ( 37.721 - 40.000 )
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Source Clock Delay (SCD): -2.690ns
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Clock Pessimism Removal (CPR): -0.507ns
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Clock Uncertainty: 0.077ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
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Total System Jitter (TSJ): 0.071ns
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Discrete Jitter (DJ): 0.136ns
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Phase Error (PE): 0.000ns
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Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
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------------------------------------------------------------------- -------------------
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(clock mlkem_clk_clk_pll rise edge)
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0.000 0.000 r
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clock source latency -6.275 -6.275
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propagated clock network latency
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3.586 -2.690
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SLICE_X91Y121 FDCE 0.000 -2.690 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/C
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SLICE_X91Y121 FDCE (Prop_fdce_C_Q) 0.456 -2.234 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/Q
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net (fo=169, routed) 6.237 4.004 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st[4]
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SLICE_X157Y96 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/I0
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SLICE_X157Y96 LUT5 (Prop_lut5_I0_O) 0.124 4.128 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/O
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net (fo=936, routed) 22.108 26.236 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/sha3_mb_en0
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SLICE_X45Y135 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[827]_i_1/I1
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SLICE_X45Y135 LUT6 (Prop_lut6_I1_O) 0.124 26.360 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[827]_i_1/O
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net (fo=1, routed) 0.000 26.360 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram_n_470
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SLICE_X45Y135 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[827]/D
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------------------------------------------------------------------- -------------------
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(clock mlkem_clk_clk_pll rise edge)
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40.000 40.000 r
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clock source latency -5.674 34.326
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propagated clock network latency
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3.396 37.721
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clock pessimism -0.507 37.214
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clock uncertainty -0.077 37.138
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SLICE_X45Y135 FDCE (Setup_fdce_C_D) 0.029 37.167 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[827]
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-------------------------------------------------------------------
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required time 37.167
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arrival time -26.360
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-------------------------------------------------------------------
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slack 10.807
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Slack (MET) : 10.807ns (required time - arrival time)
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Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/C
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(rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns})
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Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[827]/D
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(rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns})
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Path Group: mlkem_clk_clk_pll
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Path Type: Setup (Max at Slow Process Corner)
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Requirement: 40.000ns (mlkem_clk_clk_pll rise@40.000ns - mlkem_clk_clk_pll rise@0.000ns)
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Data Path Delay: 29.049ns (logic 0.704ns (2.423%) route 28.345ns (97.577%))
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Logic Levels: 2 (LUT5=1 LUT6=1)
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Clock Path Skew: -0.096ns (DCD - SCD + CPR)
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Destination Clock Delay (DCD): -2.279ns = ( 37.721 - 40.000 )
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Source Clock Delay (SCD): -2.690ns
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Clock Pessimism Removal (CPR): -0.507ns
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Clock Uncertainty: 0.077ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
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Total System Jitter (TSJ): 0.071ns
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Discrete Jitter (DJ): 0.136ns
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Phase Error (PE): 0.000ns
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Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
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------------------------------------------------------------------- -------------------
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(clock mlkem_clk_clk_pll rise edge)
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0.000 0.000 r
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clock source latency -6.275 -6.275
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propagated clock network latency
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3.586 -2.690
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SLICE_X91Y121 FDCE 0.000 -2.690 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/C
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SLICE_X91Y121 FDCE (Prop_fdce_C_Q) 0.456 -2.234 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/Q
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net (fo=169, routed) 6.237 4.004 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st[4]
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SLICE_X157Y96 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/I0
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SLICE_X157Y96 LUT5 (Prop_lut5_I0_O) 0.124 4.128 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/O
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net (fo=936, routed) 22.108 26.236 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/sha3_mb_en0
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SLICE_X45Y135 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[827]_i_1/I1
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SLICE_X45Y135 LUT6 (Prop_lut6_I1_O) 0.124 26.360 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[827]_i_1/O
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net (fo=1, routed) 0.000 26.360 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram_n_470
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SLICE_X45Y135 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[827]/D
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------------------------------------------------------------------- -------------------
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(clock mlkem_clk_clk_pll rise edge)
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40.000 40.000 r
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clock source latency -5.674 34.326
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propagated clock network latency
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3.396 37.721
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clock pessimism -0.507 37.214
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clock uncertainty -0.077 37.138
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SLICE_X45Y135 FDCE (Setup_fdce_C_D) 0.029 37.167 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[827]
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-------------------------------------------------------------------
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required time 37.167
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arrival time -26.360
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-------------------------------------------------------------------
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slack 10.807
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Slack (MET) : 10.904ns (required time - arrival time)
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Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/C
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(rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns})
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Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[780]/D
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(rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns})
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Path Group: mlkem_clk_clk_pll
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Path Type: Setup (Max at Slow Process Corner)
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Requirement: 40.000ns (mlkem_clk_clk_pll rise@40.000ns - mlkem_clk_clk_pll rise@0.000ns)
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Data Path Delay: 29.004ns (logic 0.704ns (2.427%) route 28.300ns (97.573%))
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Logic Levels: 2 (LUT5=1 LUT6=1)
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Clock Path Skew: -0.096ns (DCD - SCD + CPR)
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Destination Clock Delay (DCD): -2.279ns = ( 37.721 - 40.000 )
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Source Clock Delay (SCD): -2.690ns
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Clock Pessimism Removal (CPR): -0.507ns
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Clock Uncertainty: 0.077ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
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Total System Jitter (TSJ): 0.071ns
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Discrete Jitter (DJ): 0.136ns
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Phase Error (PE): 0.000ns
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Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
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------------------------------------------------------------------- -------------------
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(clock mlkem_clk_clk_pll rise edge)
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0.000 0.000 r
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clock source latency -6.275 -6.275
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propagated clock network latency
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3.586 -2.690
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SLICE_X91Y121 FDCE 0.000 -2.690 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/C
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SLICE_X91Y121 FDCE (Prop_fdce_C_Q) 0.456 -2.234 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/Q
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net (fo=169, routed) 6.237 4.004 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st[4]
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SLICE_X157Y96 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/I0
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SLICE_X157Y96 LUT5 (Prop_lut5_I0_O) 0.124 4.128 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/O
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net (fo=936, routed) 22.063 26.191 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/sha3_mb_en0
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SLICE_X46Y135 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[780]_i_1/I1
|
|
SLICE_X46Y135 LUT6 (Prop_lut6_I1_O) 0.124 26.315 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[780]_i_1/O
|
|
net (fo=1, routed) 0.000 26.315 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram_n_912
|
|
SLICE_X46Y135 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[780]/D
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock mlkem_clk_clk_pll rise edge)
|
|
40.000 40.000 r
|
|
clock source latency -5.674 34.326
|
|
propagated clock network latency
|
|
3.396 37.721
|
|
clock pessimism -0.507 37.214
|
|
clock uncertainty -0.077 37.138
|
|
SLICE_X46Y135 FDCE (Setup_fdce_C_D) 0.081 37.219 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[780]
|
|
-------------------------------------------------------------------
|
|
required time 37.219
|
|
arrival time -26.315
|
|
-------------------------------------------------------------------
|
|
slack 10.904
|
|
|
|
Slack (MET) : 10.904ns (required time - arrival time)
|
|
Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/C
|
|
(rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns})
|
|
Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[780]/D
|
|
(rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns})
|
|
Path Group: mlkem_clk_clk_pll
|
|
Path Type: Setup (Max at Slow Process Corner)
|
|
Requirement: 40.000ns (mlkem_clk_clk_pll rise@40.000ns - mlkem_clk_clk_pll rise@0.000ns)
|
|
Data Path Delay: 29.004ns (logic 0.704ns (2.427%) route 28.300ns (97.573%))
|
|
Logic Levels: 2 (LUT5=1 LUT6=1)
|
|
Clock Path Skew: -0.096ns (DCD - SCD + CPR)
|
|
Destination Clock Delay (DCD): -2.279ns = ( 37.721 - 40.000 )
|
|
Source Clock Delay (SCD): -2.690ns
|
|
Clock Pessimism Removal (CPR): -0.507ns
|
|
Clock Uncertainty: 0.077ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Discrete Jitter (DJ): 0.136ns
|
|
Phase Error (PE): 0.000ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock mlkem_clk_clk_pll rise edge)
|
|
0.000 0.000 r
|
|
clock source latency -6.275 -6.275
|
|
propagated clock network latency
|
|
3.586 -2.690
|
|
SLICE_X91Y121 FDCE 0.000 -2.690 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/C
|
|
SLICE_X91Y121 FDCE (Prop_fdce_C_Q) 0.456 -2.234 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/Q
|
|
net (fo=169, routed) 6.237 4.004 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st[4]
|
|
SLICE_X157Y96 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/I0
|
|
SLICE_X157Y96 LUT5 (Prop_lut5_I0_O) 0.124 4.128 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/O
|
|
net (fo=936, routed) 22.063 26.191 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/sha3_mb_en0
|
|
SLICE_X46Y135 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[780]_i_1/I1
|
|
SLICE_X46Y135 LUT6 (Prop_lut6_I1_O) 0.124 26.315 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[780]_i_1/O
|
|
net (fo=1, routed) 0.000 26.315 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram_n_912
|
|
SLICE_X46Y135 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[780]/D
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock mlkem_clk_clk_pll rise edge)
|
|
40.000 40.000 r
|
|
clock source latency -5.674 34.326
|
|
propagated clock network latency
|
|
3.396 37.721
|
|
clock pessimism -0.507 37.214
|
|
clock uncertainty -0.077 37.138
|
|
SLICE_X46Y135 FDCE (Setup_fdce_C_D) 0.081 37.219 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[780]
|
|
-------------------------------------------------------------------
|
|
required time 37.219
|
|
arrival time -26.315
|
|
-------------------------------------------------------------------
|
|
slack 10.904
|
|
|
|
Slack (MET) : 10.904ns (required time - arrival time)
|
|
Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/C
|
|
(rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns})
|
|
Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[780]/D
|
|
(rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns})
|
|
Path Group: mlkem_clk_clk_pll
|
|
Path Type: Setup (Max at Slow Process Corner)
|
|
Requirement: 40.000ns (mlkem_clk_clk_pll rise@40.000ns - mlkem_clk_clk_pll rise@0.000ns)
|
|
Data Path Delay: 29.004ns (logic 0.704ns (2.427%) route 28.300ns (97.573%))
|
|
Logic Levels: 2 (LUT5=1 LUT6=1)
|
|
Clock Path Skew: -0.096ns (DCD - SCD + CPR)
|
|
Destination Clock Delay (DCD): -2.279ns = ( 37.721 - 40.000 )
|
|
Source Clock Delay (SCD): -2.690ns
|
|
Clock Pessimism Removal (CPR): -0.507ns
|
|
Clock Uncertainty: 0.077ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Discrete Jitter (DJ): 0.136ns
|
|
Phase Error (PE): 0.000ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock mlkem_clk_clk_pll rise edge)
|
|
0.000 0.000 r
|
|
clock source latency -6.275 -6.275
|
|
propagated clock network latency
|
|
3.586 -2.690
|
|
SLICE_X91Y121 FDCE 0.000 -2.690 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/C
|
|
SLICE_X91Y121 FDCE (Prop_fdce_C_Q) 0.456 -2.234 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/Q
|
|
net (fo=169, routed) 6.237 4.004 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st[4]
|
|
SLICE_X157Y96 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/I0
|
|
SLICE_X157Y96 LUT5 (Prop_lut5_I0_O) 0.124 4.128 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/O
|
|
net (fo=936, routed) 22.063 26.191 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/sha3_mb_en0
|
|
SLICE_X46Y135 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[780]_i_1/I1
|
|
SLICE_X46Y135 LUT6 (Prop_lut6_I1_O) 0.124 26.315 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[780]_i_1/O
|
|
net (fo=1, routed) 0.000 26.315 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram_n_912
|
|
SLICE_X46Y135 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[780]/D
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock mlkem_clk_clk_pll rise edge)
|
|
40.000 40.000 r
|
|
clock source latency -5.674 34.326
|
|
propagated clock network latency
|
|
3.396 37.721
|
|
clock pessimism -0.507 37.214
|
|
clock uncertainty -0.077 37.138
|
|
SLICE_X46Y135 FDCE (Setup_fdce_C_D) 0.081 37.219 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[780]
|
|
-------------------------------------------------------------------
|
|
required time 37.219
|
|
arrival time -26.315
|
|
-------------------------------------------------------------------
|
|
slack 10.904
|
|
|
|
Slack (MET) : 10.904ns (required time - arrival time)
|
|
Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/C
|
|
(rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns})
|
|
Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[780]/D
|
|
(rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns})
|
|
Path Group: mlkem_clk_clk_pll
|
|
Path Type: Setup (Max at Slow Process Corner)
|
|
Requirement: 40.000ns (mlkem_clk_clk_pll rise@40.000ns - mlkem_clk_clk_pll rise@0.000ns)
|
|
Data Path Delay: 29.004ns (logic 0.704ns (2.427%) route 28.300ns (97.573%))
|
|
Logic Levels: 2 (LUT5=1 LUT6=1)
|
|
Clock Path Skew: -0.096ns (DCD - SCD + CPR)
|
|
Destination Clock Delay (DCD): -2.279ns = ( 37.721 - 40.000 )
|
|
Source Clock Delay (SCD): -2.690ns
|
|
Clock Pessimism Removal (CPR): -0.507ns
|
|
Clock Uncertainty: 0.077ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Discrete Jitter (DJ): 0.136ns
|
|
Phase Error (PE): 0.000ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock mlkem_clk_clk_pll rise edge)
|
|
0.000 0.000 r
|
|
clock source latency -6.275 -6.275
|
|
propagated clock network latency
|
|
3.586 -2.690
|
|
SLICE_X91Y121 FDCE 0.000 -2.690 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/C
|
|
SLICE_X91Y121 FDCE (Prop_fdce_C_Q) 0.456 -2.234 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/Q
|
|
net (fo=169, routed) 6.237 4.004 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st[4]
|
|
SLICE_X157Y96 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/I0
|
|
SLICE_X157Y96 LUT5 (Prop_lut5_I0_O) 0.124 4.128 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/O
|
|
net (fo=936, routed) 22.063 26.191 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/sha3_mb_en0
|
|
SLICE_X46Y135 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[780]_i_1/I1
|
|
SLICE_X46Y135 LUT6 (Prop_lut6_I1_O) 0.124 26.315 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[780]_i_1/O
|
|
net (fo=1, routed) 0.000 26.315 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram_n_912
|
|
SLICE_X46Y135 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[780]/D
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock mlkem_clk_clk_pll rise edge)
|
|
40.000 40.000 r
|
|
clock source latency -5.674 34.326
|
|
propagated clock network latency
|
|
3.396 37.721
|
|
clock pessimism -0.507 37.214
|
|
clock uncertainty -0.077 37.138
|
|
SLICE_X46Y135 FDCE (Setup_fdce_C_D) 0.081 37.219 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[780]
|
|
-------------------------------------------------------------------
|
|
required time 37.219
|
|
arrival time -26.315
|
|
-------------------------------------------------------------------
|
|
slack 10.904
|
|
|
|
Slack (MET) : 10.918ns (required time - arrival time)
|
|
Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/C
|
|
(rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns})
|
|
Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[782]/D
|
|
(rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns})
|
|
Path Group: mlkem_clk_clk_pll
|
|
Path Type: Setup (Max at Slow Process Corner)
|
|
Requirement: 40.000ns (mlkem_clk_clk_pll rise@40.000ns - mlkem_clk_clk_pll rise@0.000ns)
|
|
Data Path Delay: 28.987ns (logic 0.704ns (2.429%) route 28.283ns (97.571%))
|
|
Logic Levels: 2 (LUT5=1 LUT6=1)
|
|
Clock Path Skew: -0.096ns (DCD - SCD + CPR)
|
|
Destination Clock Delay (DCD): -2.279ns = ( 37.721 - 40.000 )
|
|
Source Clock Delay (SCD): -2.690ns
|
|
Clock Pessimism Removal (CPR): -0.507ns
|
|
Clock Uncertainty: 0.077ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Discrete Jitter (DJ): 0.136ns
|
|
Phase Error (PE): 0.000ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock mlkem_clk_clk_pll rise edge)
|
|
0.000 0.000 r
|
|
clock source latency -6.275 -6.275
|
|
propagated clock network latency
|
|
3.586 -2.690
|
|
SLICE_X91Y121 FDCE 0.000 -2.690 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/C
|
|
SLICE_X91Y121 FDCE (Prop_fdce_C_Q) 0.456 -2.234 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/Q
|
|
net (fo=169, routed) 6.237 4.004 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st[4]
|
|
SLICE_X157Y96 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/I0
|
|
SLICE_X157Y96 LUT5 (Prop_lut5_I0_O) 0.124 4.128 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/O
|
|
net (fo=936, routed) 22.045 26.173 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/sha3_mb_en0
|
|
SLICE_X44Y136 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[782]_i_1/I1
|
|
SLICE_X44Y136 LUT6 (Prop_lut6_I1_O) 0.124 26.297 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[782]_i_1/O
|
|
net (fo=1, routed) 0.000 26.297 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram_n_914
|
|
SLICE_X44Y136 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[782]/D
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock mlkem_clk_clk_pll rise edge)
|
|
40.000 40.000 r
|
|
clock source latency -5.674 34.326
|
|
propagated clock network latency
|
|
3.396 37.721
|
|
clock pessimism -0.507 37.214
|
|
clock uncertainty -0.077 37.138
|
|
SLICE_X44Y136 FDCE (Setup_fdce_C_D) 0.077 37.215 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[782]
|
|
-------------------------------------------------------------------
|
|
required time 37.215
|
|
arrival time -26.297
|
|
-------------------------------------------------------------------
|
|
slack 10.918
|
|
|
|
Slack (MET) : 10.918ns (required time - arrival time)
|
|
Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/C
|
|
(rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns})
|
|
Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[782]/D
|
|
(rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns})
|
|
Path Group: mlkem_clk_clk_pll
|
|
Path Type: Setup (Max at Slow Process Corner)
|
|
Requirement: 40.000ns (mlkem_clk_clk_pll rise@40.000ns - mlkem_clk_clk_pll rise@0.000ns)
|
|
Data Path Delay: 28.987ns (logic 0.704ns (2.429%) route 28.283ns (97.571%))
|
|
Logic Levels: 2 (LUT5=1 LUT6=1)
|
|
Clock Path Skew: -0.096ns (DCD - SCD + CPR)
|
|
Destination Clock Delay (DCD): -2.279ns = ( 37.721 - 40.000 )
|
|
Source Clock Delay (SCD): -2.690ns
|
|
Clock Pessimism Removal (CPR): -0.507ns
|
|
Clock Uncertainty: 0.077ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Discrete Jitter (DJ): 0.136ns
|
|
Phase Error (PE): 0.000ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock mlkem_clk_clk_pll rise edge)
|
|
0.000 0.000 r
|
|
clock source latency -6.275 -6.275
|
|
propagated clock network latency
|
|
3.586 -2.690
|
|
SLICE_X91Y121 FDCE 0.000 -2.690 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/C
|
|
SLICE_X91Y121 FDCE (Prop_fdce_C_Q) 0.456 -2.234 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/Q
|
|
net (fo=169, routed) 6.237 4.004 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st[4]
|
|
SLICE_X157Y96 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/I0
|
|
SLICE_X157Y96 LUT5 (Prop_lut5_I0_O) 0.124 4.128 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/O
|
|
net (fo=936, routed) 22.045 26.173 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/sha3_mb_en0
|
|
SLICE_X44Y136 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[782]_i_1/I1
|
|
SLICE_X44Y136 LUT6 (Prop_lut6_I1_O) 0.124 26.297 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[782]_i_1/O
|
|
net (fo=1, routed) 0.000 26.297 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram_n_914
|
|
SLICE_X44Y136 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[782]/D
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock mlkem_clk_clk_pll rise edge)
|
|
40.000 40.000 r
|
|
clock source latency -5.674 34.326
|
|
propagated clock network latency
|
|
3.396 37.721
|
|
clock pessimism -0.507 37.214
|
|
clock uncertainty -0.077 37.138
|
|
SLICE_X44Y136 FDCE (Setup_fdce_C_D) 0.077 37.215 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[782]
|
|
-------------------------------------------------------------------
|
|
required time 37.215
|
|
arrival time -26.297
|
|
-------------------------------------------------------------------
|
|
slack 10.918
|
|
|
|
Slack (MET) : 10.918ns (required time - arrival time)
|
|
Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/C
|
|
(rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns})
|
|
Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[782]/D
|
|
(rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns})
|
|
Path Group: mlkem_clk_clk_pll
|
|
Path Type: Setup (Max at Slow Process Corner)
|
|
Requirement: 40.000ns (mlkem_clk_clk_pll rise@40.000ns - mlkem_clk_clk_pll rise@0.000ns)
|
|
Data Path Delay: 28.987ns (logic 0.704ns (2.429%) route 28.283ns (97.571%))
|
|
Logic Levels: 2 (LUT5=1 LUT6=1)
|
|
Clock Path Skew: -0.096ns (DCD - SCD + CPR)
|
|
Destination Clock Delay (DCD): -2.279ns = ( 37.721 - 40.000 )
|
|
Source Clock Delay (SCD): -2.690ns
|
|
Clock Pessimism Removal (CPR): -0.507ns
|
|
Clock Uncertainty: 0.077ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Discrete Jitter (DJ): 0.136ns
|
|
Phase Error (PE): 0.000ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock mlkem_clk_clk_pll rise edge)
|
|
0.000 0.000 r
|
|
clock source latency -6.275 -6.275
|
|
propagated clock network latency
|
|
3.586 -2.690
|
|
SLICE_X91Y121 FDCE 0.000 -2.690 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/C
|
|
SLICE_X91Y121 FDCE (Prop_fdce_C_Q) 0.456 -2.234 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/Q
|
|
net (fo=169, routed) 6.237 4.004 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st[4]
|
|
SLICE_X157Y96 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/I0
|
|
SLICE_X157Y96 LUT5 (Prop_lut5_I0_O) 0.124 4.128 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/O
|
|
net (fo=936, routed) 22.045 26.173 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/sha3_mb_en0
|
|
SLICE_X44Y136 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[782]_i_1/I1
|
|
SLICE_X44Y136 LUT6 (Prop_lut6_I1_O) 0.124 26.297 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[782]_i_1/O
|
|
net (fo=1, routed) 0.000 26.297 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram_n_914
|
|
SLICE_X44Y136 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[782]/D
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock mlkem_clk_clk_pll rise edge)
|
|
40.000 40.000 r
|
|
clock source latency -5.674 34.326
|
|
propagated clock network latency
|
|
3.396 37.721
|
|
clock pessimism -0.507 37.214
|
|
clock uncertainty -0.077 37.138
|
|
SLICE_X44Y136 FDCE (Setup_fdce_C_D) 0.077 37.215 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[782]
|
|
-------------------------------------------------------------------
|
|
required time 37.215
|
|
arrival time -26.297
|
|
-------------------------------------------------------------------
|
|
slack 10.918
|
|
|
|
Slack (MET) : 10.918ns (required time - arrival time)
|
|
Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/C
|
|
(rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns})
|
|
Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[782]/D
|
|
(rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns})
|
|
Path Group: mlkem_clk_clk_pll
|
|
Path Type: Setup (Max at Slow Process Corner)
|
|
Requirement: 40.000ns (mlkem_clk_clk_pll rise@40.000ns - mlkem_clk_clk_pll rise@0.000ns)
|
|
Data Path Delay: 28.987ns (logic 0.704ns (2.429%) route 28.283ns (97.571%))
|
|
Logic Levels: 2 (LUT5=1 LUT6=1)
|
|
Clock Path Skew: -0.096ns (DCD - SCD + CPR)
|
|
Destination Clock Delay (DCD): -2.279ns = ( 37.721 - 40.000 )
|
|
Source Clock Delay (SCD): -2.690ns
|
|
Clock Pessimism Removal (CPR): -0.507ns
|
|
Clock Uncertainty: 0.077ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Discrete Jitter (DJ): 0.136ns
|
|
Phase Error (PE): 0.000ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock mlkem_clk_clk_pll rise edge)
|
|
0.000 0.000 r
|
|
clock source latency -6.275 -6.275
|
|
propagated clock network latency
|
|
3.586 -2.690
|
|
SLICE_X91Y121 FDCE 0.000 -2.690 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/C
|
|
SLICE_X91Y121 FDCE (Prop_fdce_C_Q) 0.456 -2.234 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/Q
|
|
net (fo=169, routed) 6.237 4.004 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st[4]
|
|
SLICE_X157Y96 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/I0
|
|
SLICE_X157Y96 LUT5 (Prop_lut5_I0_O) 0.124 4.128 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/O
|
|
net (fo=936, routed) 22.045 26.173 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/sha3_mb_en0
|
|
SLICE_X44Y136 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[782]_i_1/I1
|
|
SLICE_X44Y136 LUT6 (Prop_lut6_I1_O) 0.124 26.297 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[782]_i_1/O
|
|
net (fo=1, routed) 0.000 26.297 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram_n_914
|
|
SLICE_X44Y136 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[782]/D
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock mlkem_clk_clk_pll rise edge)
|
|
40.000 40.000 r
|
|
clock source latency -5.674 34.326
|
|
propagated clock network latency
|
|
3.396 37.721
|
|
clock pessimism -0.507 37.214
|
|
clock uncertainty -0.077 37.138
|
|
SLICE_X44Y136 FDCE (Setup_fdce_C_D) 0.077 37.215 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[782]
|
|
-------------------------------------------------------------------
|
|
required time 37.215
|
|
arrival time -26.297
|
|
-------------------------------------------------------------------
|
|
slack 10.918
|
|
|
|
Slack (MET) : 11.034ns (required time - arrival time)
|
|
Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/C
|
|
(rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns})
|
|
Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[829]/D
|
|
(rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns})
|
|
Path Group: mlkem_clk_clk_pll
|
|
Path Type: Setup (Max at Slow Process Corner)
|
|
Requirement: 40.000ns (mlkem_clk_clk_pll rise@40.000ns - mlkem_clk_clk_pll rise@0.000ns)
|
|
Data Path Delay: 28.824ns (logic 0.704ns (2.442%) route 28.120ns (97.558%))
|
|
Logic Levels: 2 (LUT5=1 LUT6=1)
|
|
Clock Path Skew: -0.096ns (DCD - SCD + CPR)
|
|
Destination Clock Delay (DCD): -2.279ns = ( 37.721 - 40.000 )
|
|
Source Clock Delay (SCD): -2.690ns
|
|
Clock Pessimism Removal (CPR): -0.507ns
|
|
Clock Uncertainty: 0.077ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Discrete Jitter (DJ): 0.136ns
|
|
Phase Error (PE): 0.000ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock mlkem_clk_clk_pll rise edge)
|
|
0.000 0.000 r
|
|
clock source latency -6.275 -6.275
|
|
propagated clock network latency
|
|
3.586 -2.690
|
|
SLICE_X91Y121 FDCE 0.000 -2.690 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/C
|
|
SLICE_X91Y121 FDCE (Prop_fdce_C_Q) 0.456 -2.234 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/Q
|
|
net (fo=169, routed) 6.237 4.004 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st[4]
|
|
SLICE_X157Y96 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/I0
|
|
SLICE_X157Y96 LUT5 (Prop_lut5_I0_O) 0.124 4.128 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/O
|
|
net (fo=936, routed) 21.883 26.011 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/sha3_mb_en0
|
|
SLICE_X45Y135 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[829]_i_1/I1
|
|
SLICE_X45Y135 LUT6 (Prop_lut6_I1_O) 0.124 26.135 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[829]_i_1/O
|
|
net (fo=1, routed) 0.000 26.135 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram_n_472
|
|
SLICE_X45Y135 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[829]/D
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock mlkem_clk_clk_pll rise edge)
|
|
40.000 40.000 r
|
|
clock source latency -5.674 34.326
|
|
propagated clock network latency
|
|
3.396 37.721
|
|
clock pessimism -0.507 37.214
|
|
clock uncertainty -0.077 37.138
|
|
SLICE_X45Y135 FDCE (Setup_fdce_C_D) 0.031 37.169 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[829]
|
|
-------------------------------------------------------------------
|
|
required time 37.169
|
|
arrival time -26.135
|
|
-------------------------------------------------------------------
|
|
slack 11.034
|
|
|
|
Slack (MET) : 11.034ns (required time - arrival time)
|
|
Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/C
|
|
(rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns})
|
|
Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[829]/D
|
|
(rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns})
|
|
Path Group: mlkem_clk_clk_pll
|
|
Path Type: Setup (Max at Slow Process Corner)
|
|
Requirement: 40.000ns (mlkem_clk_clk_pll rise@40.000ns - mlkem_clk_clk_pll rise@0.000ns)
|
|
Data Path Delay: 28.824ns (logic 0.704ns (2.442%) route 28.120ns (97.558%))
|
|
Logic Levels: 2 (LUT5=1 LUT6=1)
|
|
Clock Path Skew: -0.096ns (DCD - SCD + CPR)
|
|
Destination Clock Delay (DCD): -2.279ns = ( 37.721 - 40.000 )
|
|
Source Clock Delay (SCD): -2.690ns
|
|
Clock Pessimism Removal (CPR): -0.507ns
|
|
Clock Uncertainty: 0.077ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Discrete Jitter (DJ): 0.136ns
|
|
Phase Error (PE): 0.000ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock mlkem_clk_clk_pll rise edge)
|
|
0.000 0.000 r
|
|
clock source latency -6.275 -6.275
|
|
propagated clock network latency
|
|
3.586 -2.690
|
|
SLICE_X91Y121 FDCE 0.000 -2.690 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/C
|
|
SLICE_X91Y121 FDCE (Prop_fdce_C_Q) 0.456 -2.234 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/Q
|
|
net (fo=169, routed) 6.237 4.004 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st[4]
|
|
SLICE_X157Y96 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/I0
|
|
SLICE_X157Y96 LUT5 (Prop_lut5_I0_O) 0.124 4.128 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/O
|
|
net (fo=936, routed) 21.883 26.011 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/sha3_mb_en0
|
|
SLICE_X45Y135 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[829]_i_1/I1
|
|
SLICE_X45Y135 LUT6 (Prop_lut6_I1_O) 0.124 26.135 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[829]_i_1/O
|
|
net (fo=1, routed) 0.000 26.135 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram_n_472
|
|
SLICE_X45Y135 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[829]/D
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock mlkem_clk_clk_pll rise edge)
|
|
40.000 40.000 r
|
|
clock source latency -5.674 34.326
|
|
propagated clock network latency
|
|
3.396 37.721
|
|
clock pessimism -0.507 37.214
|
|
clock uncertainty -0.077 37.138
|
|
SLICE_X45Y135 FDCE (Setup_fdce_C_D) 0.031 37.169 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[829]
|
|
-------------------------------------------------------------------
|
|
required time 37.169
|
|
arrival time -26.135
|
|
-------------------------------------------------------------------
|
|
slack 11.034
|
|
|
|
Slack (MET) : 11.034ns (required time - arrival time)
|
|
Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/C
|
|
(rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns})
|
|
Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[829]/D
|
|
(rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns})
|
|
Path Group: mlkem_clk_clk_pll
|
|
Path Type: Setup (Max at Slow Process Corner)
|
|
Requirement: 40.000ns (mlkem_clk_clk_pll rise@40.000ns - mlkem_clk_clk_pll rise@0.000ns)
|
|
Data Path Delay: 28.824ns (logic 0.704ns (2.442%) route 28.120ns (97.558%))
|
|
Logic Levels: 2 (LUT5=1 LUT6=1)
|
|
Clock Path Skew: -0.096ns (DCD - SCD + CPR)
|
|
Destination Clock Delay (DCD): -2.279ns = ( 37.721 - 40.000 )
|
|
Source Clock Delay (SCD): -2.690ns
|
|
Clock Pessimism Removal (CPR): -0.507ns
|
|
Clock Uncertainty: 0.077ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Discrete Jitter (DJ): 0.136ns
|
|
Phase Error (PE): 0.000ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock mlkem_clk_clk_pll rise edge)
|
|
0.000 0.000 r
|
|
clock source latency -6.275 -6.275
|
|
propagated clock network latency
|
|
3.586 -2.690
|
|
SLICE_X91Y121 FDCE 0.000 -2.690 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/C
|
|
SLICE_X91Y121 FDCE (Prop_fdce_C_Q) 0.456 -2.234 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/Q
|
|
net (fo=169, routed) 6.237 4.004 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st[4]
|
|
SLICE_X157Y96 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/I0
|
|
SLICE_X157Y96 LUT5 (Prop_lut5_I0_O) 0.124 4.128 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/O
|
|
net (fo=936, routed) 21.883 26.011 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/sha3_mb_en0
|
|
SLICE_X45Y135 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[829]_i_1/I1
|
|
SLICE_X45Y135 LUT6 (Prop_lut6_I1_O) 0.124 26.135 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[829]_i_1/O
|
|
net (fo=1, routed) 0.000 26.135 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram_n_472
|
|
SLICE_X45Y135 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[829]/D
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock mlkem_clk_clk_pll rise edge)
|
|
40.000 40.000 r
|
|
clock source latency -5.674 34.326
|
|
propagated clock network latency
|
|
3.396 37.721
|
|
clock pessimism -0.507 37.214
|
|
clock uncertainty -0.077 37.138
|
|
SLICE_X45Y135 FDCE (Setup_fdce_C_D) 0.031 37.169 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[829]
|
|
-------------------------------------------------------------------
|
|
required time 37.169
|
|
arrival time -26.135
|
|
-------------------------------------------------------------------
|
|
slack 11.034
|
|
|
|
Slack (MET) : 11.034ns (required time - arrival time)
|
|
Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/C
|
|
(rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns})
|
|
Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[829]/D
|
|
(rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns})
|
|
Path Group: mlkem_clk_clk_pll
|
|
Path Type: Setup (Max at Slow Process Corner)
|
|
Requirement: 40.000ns (mlkem_clk_clk_pll rise@40.000ns - mlkem_clk_clk_pll rise@0.000ns)
|
|
Data Path Delay: 28.824ns (logic 0.704ns (2.442%) route 28.120ns (97.558%))
|
|
Logic Levels: 2 (LUT5=1 LUT6=1)
|
|
Clock Path Skew: -0.096ns (DCD - SCD + CPR)
|
|
Destination Clock Delay (DCD): -2.279ns = ( 37.721 - 40.000 )
|
|
Source Clock Delay (SCD): -2.690ns
|
|
Clock Pessimism Removal (CPR): -0.507ns
|
|
Clock Uncertainty: 0.077ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Discrete Jitter (DJ): 0.136ns
|
|
Phase Error (PE): 0.000ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock mlkem_clk_clk_pll rise edge)
|
|
0.000 0.000 r
|
|
clock source latency -6.275 -6.275
|
|
propagated clock network latency
|
|
3.586 -2.690
|
|
SLICE_X91Y121 FDCE 0.000 -2.690 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/C
|
|
SLICE_X91Y121 FDCE (Prop_fdce_C_Q) 0.456 -2.234 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/Q
|
|
net (fo=169, routed) 6.237 4.004 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st[4]
|
|
SLICE_X157Y96 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/I0
|
|
SLICE_X157Y96 LUT5 (Prop_lut5_I0_O) 0.124 4.128 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/O
|
|
net (fo=936, routed) 21.883 26.011 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/sha3_mb_en0
|
|
SLICE_X45Y135 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[829]_i_1/I1
|
|
SLICE_X45Y135 LUT6 (Prop_lut6_I1_O) 0.124 26.135 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[829]_i_1/O
|
|
net (fo=1, routed) 0.000 26.135 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram_n_472
|
|
SLICE_X45Y135 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[829]/D
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock mlkem_clk_clk_pll rise edge)
|
|
40.000 40.000 r
|
|
clock source latency -5.674 34.326
|
|
propagated clock network latency
|
|
3.396 37.721
|
|
clock pessimism -0.507 37.214
|
|
clock uncertainty -0.077 37.138
|
|
SLICE_X45Y135 FDCE (Setup_fdce_C_D) 0.031 37.169 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[829]
|
|
-------------------------------------------------------------------
|
|
required time 37.169
|
|
arrival time -26.135
|
|
-------------------------------------------------------------------
|
|
slack 11.034
|
|
|
|
Slack (MET) : 11.059ns (required time - arrival time)
|
|
Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/C
|
|
(rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns})
|
|
Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[777]/D
|
|
(rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns})
|
|
Path Group: mlkem_clk_clk_pll
|
|
Path Type: Setup (Max at Slow Process Corner)
|
|
Requirement: 40.000ns (mlkem_clk_clk_pll rise@40.000ns - mlkem_clk_clk_pll rise@0.000ns)
|
|
Data Path Delay: 28.845ns (logic 0.704ns (2.441%) route 28.141ns (97.559%))
|
|
Logic Levels: 2 (LUT5=1 LUT6=1)
|
|
Clock Path Skew: -0.096ns (DCD - SCD + CPR)
|
|
Destination Clock Delay (DCD): -2.279ns = ( 37.721 - 40.000 )
|
|
Source Clock Delay (SCD): -2.690ns
|
|
Clock Pessimism Removal (CPR): -0.507ns
|
|
Clock Uncertainty: 0.077ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Discrete Jitter (DJ): 0.136ns
|
|
Phase Error (PE): 0.000ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock mlkem_clk_clk_pll rise edge)
|
|
0.000 0.000 r
|
|
clock source latency -6.275 -6.275
|
|
propagated clock network latency
|
|
3.586 -2.690
|
|
SLICE_X91Y121 FDCE 0.000 -2.690 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/C
|
|
SLICE_X91Y121 FDCE (Prop_fdce_C_Q) 0.456 -2.234 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/Q
|
|
net (fo=169, routed) 6.237 4.004 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st[4]
|
|
SLICE_X157Y96 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/I0
|
|
SLICE_X157Y96 LUT5 (Prop_lut5_I0_O) 0.124 4.128 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/O
|
|
net (fo=936, routed) 21.904 26.032 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/sha3_mb_en0
|
|
SLICE_X44Y135 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[777]_i_1/I1
|
|
SLICE_X44Y135 LUT6 (Prop_lut6_I1_O) 0.124 26.156 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[777]_i_1/O
|
|
net (fo=1, routed) 0.000 26.156 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram_n_909
|
|
SLICE_X44Y135 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[777]/D
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock mlkem_clk_clk_pll rise edge)
|
|
40.000 40.000 r
|
|
clock source latency -5.674 34.326
|
|
propagated clock network latency
|
|
3.396 37.721
|
|
clock pessimism -0.507 37.214
|
|
clock uncertainty -0.077 37.138
|
|
SLICE_X44Y135 FDCE (Setup_fdce_C_D) 0.077 37.215 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[777]
|
|
-------------------------------------------------------------------
|
|
required time 37.215
|
|
arrival time -26.156
|
|
-------------------------------------------------------------------
|
|
slack 11.059
|
|
|
|
Slack (MET) : 11.059ns (required time - arrival time)
|
|
Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/C
|
|
(rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns})
|
|
Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[777]/D
|
|
(rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns})
|
|
Path Group: mlkem_clk_clk_pll
|
|
Path Type: Setup (Max at Slow Process Corner)
|
|
Requirement: 40.000ns (mlkem_clk_clk_pll rise@40.000ns - mlkem_clk_clk_pll rise@0.000ns)
|
|
Data Path Delay: 28.845ns (logic 0.704ns (2.441%) route 28.141ns (97.559%))
|
|
Logic Levels: 2 (LUT5=1 LUT6=1)
|
|
Clock Path Skew: -0.096ns (DCD - SCD + CPR)
|
|
Destination Clock Delay (DCD): -2.279ns = ( 37.721 - 40.000 )
|
|
Source Clock Delay (SCD): -2.690ns
|
|
Clock Pessimism Removal (CPR): -0.507ns
|
|
Clock Uncertainty: 0.077ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Discrete Jitter (DJ): 0.136ns
|
|
Phase Error (PE): 0.000ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock mlkem_clk_clk_pll rise edge)
|
|
0.000 0.000 r
|
|
clock source latency -6.275 -6.275
|
|
propagated clock network latency
|
|
3.586 -2.690
|
|
SLICE_X91Y121 FDCE 0.000 -2.690 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/C
|
|
SLICE_X91Y121 FDCE (Prop_fdce_C_Q) 0.456 -2.234 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/Q
|
|
net (fo=169, routed) 6.237 4.004 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st[4]
|
|
SLICE_X157Y96 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/I0
|
|
SLICE_X157Y96 LUT5 (Prop_lut5_I0_O) 0.124 4.128 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/O
|
|
net (fo=936, routed) 21.904 26.032 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/sha3_mb_en0
|
|
SLICE_X44Y135 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[777]_i_1/I1
|
|
SLICE_X44Y135 LUT6 (Prop_lut6_I1_O) 0.124 26.156 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[777]_i_1/O
|
|
net (fo=1, routed) 0.000 26.156 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram_n_909
|
|
SLICE_X44Y135 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[777]/D
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock mlkem_clk_clk_pll rise edge)
|
|
40.000 40.000 r
|
|
clock source latency -5.674 34.326
|
|
propagated clock network latency
|
|
3.396 37.721
|
|
clock pessimism -0.507 37.214
|
|
clock uncertainty -0.077 37.138
|
|
SLICE_X44Y135 FDCE (Setup_fdce_C_D) 0.077 37.215 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[777]
|
|
-------------------------------------------------------------------
|
|
required time 37.215
|
|
arrival time -26.156
|
|
-------------------------------------------------------------------
|
|
slack 11.059
|
|
|
|
Slack (MET) : 11.059ns (required time - arrival time)
|
|
Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/C
|
|
(rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns})
|
|
Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[777]/D
|
|
(rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns})
|
|
Path Group: mlkem_clk_clk_pll
|
|
Path Type: Setup (Max at Slow Process Corner)
|
|
Requirement: 40.000ns (mlkem_clk_clk_pll rise@40.000ns - mlkem_clk_clk_pll rise@0.000ns)
|
|
Data Path Delay: 28.845ns (logic 0.704ns (2.441%) route 28.141ns (97.559%))
|
|
Logic Levels: 2 (LUT5=1 LUT6=1)
|
|
Clock Path Skew: -0.096ns (DCD - SCD + CPR)
|
|
Destination Clock Delay (DCD): -2.279ns = ( 37.721 - 40.000 )
|
|
Source Clock Delay (SCD): -2.690ns
|
|
Clock Pessimism Removal (CPR): -0.507ns
|
|
Clock Uncertainty: 0.077ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Discrete Jitter (DJ): 0.136ns
|
|
Phase Error (PE): 0.000ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock mlkem_clk_clk_pll rise edge)
|
|
0.000 0.000 r
|
|
clock source latency -6.275 -6.275
|
|
propagated clock network latency
|
|
3.586 -2.690
|
|
SLICE_X91Y121 FDCE 0.000 -2.690 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/C
|
|
SLICE_X91Y121 FDCE (Prop_fdce_C_Q) 0.456 -2.234 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/Q
|
|
net (fo=169, routed) 6.237 4.004 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st[4]
|
|
SLICE_X157Y96 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/I0
|
|
SLICE_X157Y96 LUT5 (Prop_lut5_I0_O) 0.124 4.128 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/O
|
|
net (fo=936, routed) 21.904 26.032 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/sha3_mb_en0
|
|
SLICE_X44Y135 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[777]_i_1/I1
|
|
SLICE_X44Y135 LUT6 (Prop_lut6_I1_O) 0.124 26.156 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[777]_i_1/O
|
|
net (fo=1, routed) 0.000 26.156 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram_n_909
|
|
SLICE_X44Y135 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[777]/D
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock mlkem_clk_clk_pll rise edge)
|
|
40.000 40.000 r
|
|
clock source latency -5.674 34.326
|
|
propagated clock network latency
|
|
3.396 37.721
|
|
clock pessimism -0.507 37.214
|
|
clock uncertainty -0.077 37.138
|
|
SLICE_X44Y135 FDCE (Setup_fdce_C_D) 0.077 37.215 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[777]
|
|
-------------------------------------------------------------------
|
|
required time 37.215
|
|
arrival time -26.156
|
|
-------------------------------------------------------------------
|
|
slack 11.059
|
|
|
|
Slack (MET) : 11.059ns (required time - arrival time)
|
|
Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/C
|
|
(rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns})
|
|
Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[777]/D
|
|
(rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns})
|
|
Path Group: mlkem_clk_clk_pll
|
|
Path Type: Setup (Max at Slow Process Corner)
|
|
Requirement: 40.000ns (mlkem_clk_clk_pll rise@40.000ns - mlkem_clk_clk_pll rise@0.000ns)
|
|
Data Path Delay: 28.845ns (logic 0.704ns (2.441%) route 28.141ns (97.559%))
|
|
Logic Levels: 2 (LUT5=1 LUT6=1)
|
|
Clock Path Skew: -0.096ns (DCD - SCD + CPR)
|
|
Destination Clock Delay (DCD): -2.279ns = ( 37.721 - 40.000 )
|
|
Source Clock Delay (SCD): -2.690ns
|
|
Clock Pessimism Removal (CPR): -0.507ns
|
|
Clock Uncertainty: 0.077ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Discrete Jitter (DJ): 0.136ns
|
|
Phase Error (PE): 0.000ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock mlkem_clk_clk_pll rise edge)
|
|
0.000 0.000 r
|
|
clock source latency -6.275 -6.275
|
|
propagated clock network latency
|
|
3.586 -2.690
|
|
SLICE_X91Y121 FDCE 0.000 -2.690 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/C
|
|
SLICE_X91Y121 FDCE (Prop_fdce_C_Q) 0.456 -2.234 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/Q
|
|
net (fo=169, routed) 6.237 4.004 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st[4]
|
|
SLICE_X157Y96 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/I0
|
|
SLICE_X157Y96 LUT5 (Prop_lut5_I0_O) 0.124 4.128 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/O
|
|
net (fo=936, routed) 21.904 26.032 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/sha3_mb_en0
|
|
SLICE_X44Y135 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[777]_i_1/I1
|
|
SLICE_X44Y135 LUT6 (Prop_lut6_I1_O) 0.124 26.156 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[777]_i_1/O
|
|
net (fo=1, routed) 0.000 26.156 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram_n_909
|
|
SLICE_X44Y135 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[777]/D
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock mlkem_clk_clk_pll rise edge)
|
|
40.000 40.000 r
|
|
clock source latency -5.674 34.326
|
|
propagated clock network latency
|
|
3.396 37.721
|
|
clock pessimism -0.507 37.214
|
|
clock uncertainty -0.077 37.138
|
|
SLICE_X44Y135 FDCE (Setup_fdce_C_D) 0.077 37.215 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[777]
|
|
-------------------------------------------------------------------
|
|
required time 37.215
|
|
arrival time -26.156
|
|
-------------------------------------------------------------------
|
|
slack 11.059
|
|
|
|
Slack (MET) : 11.066ns (required time - arrival time)
|
|
Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/C
|
|
(rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns})
|
|
Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[969]/D
|
|
(rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns})
|
|
Path Group: mlkem_clk_clk_pll
|
|
Path Type: Setup (Max at Slow Process Corner)
|
|
Requirement: 40.000ns (mlkem_clk_clk_pll rise@40.000ns - mlkem_clk_clk_pll rise@0.000ns)
|
|
Data Path Delay: 28.842ns (logic 0.704ns (2.441%) route 28.138ns (97.559%))
|
|
Logic Levels: 2 (LUT5=1 LUT6=1)
|
|
Clock Path Skew: -0.096ns (DCD - SCD + CPR)
|
|
Destination Clock Delay (DCD): -2.279ns = ( 37.721 - 40.000 )
|
|
Source Clock Delay (SCD): -2.690ns
|
|
Clock Pessimism Removal (CPR): -0.507ns
|
|
Clock Uncertainty: 0.077ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Discrete Jitter (DJ): 0.136ns
|
|
Phase Error (PE): 0.000ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock mlkem_clk_clk_pll rise edge)
|
|
0.000 0.000 r
|
|
clock source latency -6.275 -6.275
|
|
propagated clock network latency
|
|
3.586 -2.690
|
|
SLICE_X91Y121 FDCE 0.000 -2.690 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/C
|
|
SLICE_X91Y121 FDCE (Prop_fdce_C_Q) 0.456 -2.234 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/Q
|
|
net (fo=169, routed) 6.237 4.004 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st[4]
|
|
SLICE_X157Y96 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/I0
|
|
SLICE_X157Y96 LUT5 (Prop_lut5_I0_O) 0.124 4.128 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/O
|
|
net (fo=936, routed) 21.901 26.029 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/sha3_mb_en0
|
|
SLICE_X44Y135 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[969]_i_1/I1
|
|
SLICE_X44Y135 LUT6 (Prop_lut6_I1_O) 0.124 26.153 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[969]_i_1/O
|
|
net (fo=1, routed) 0.000 26.153 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram_n_1143
|
|
SLICE_X44Y135 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[969]/D
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock mlkem_clk_clk_pll rise edge)
|
|
40.000 40.000 r
|
|
clock source latency -5.674 34.326
|
|
propagated clock network latency
|
|
3.396 37.721
|
|
clock pessimism -0.507 37.214
|
|
clock uncertainty -0.077 37.138
|
|
SLICE_X44Y135 FDCE (Setup_fdce_C_D) 0.081 37.219 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[969]
|
|
-------------------------------------------------------------------
|
|
required time 37.219
|
|
arrival time -26.153
|
|
-------------------------------------------------------------------
|
|
slack 11.066
|
|
|
|
Slack (MET) : 11.066ns (required time - arrival time)
|
|
Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/C
|
|
(rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns})
|
|
Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[969]/D
|
|
(rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns})
|
|
Path Group: mlkem_clk_clk_pll
|
|
Path Type: Setup (Max at Slow Process Corner)
|
|
Requirement: 40.000ns (mlkem_clk_clk_pll rise@40.000ns - mlkem_clk_clk_pll rise@0.000ns)
|
|
Data Path Delay: 28.842ns (logic 0.704ns (2.441%) route 28.138ns (97.559%))
|
|
Logic Levels: 2 (LUT5=1 LUT6=1)
|
|
Clock Path Skew: -0.096ns (DCD - SCD + CPR)
|
|
Destination Clock Delay (DCD): -2.279ns = ( 37.721 - 40.000 )
|
|
Source Clock Delay (SCD): -2.690ns
|
|
Clock Pessimism Removal (CPR): -0.507ns
|
|
Clock Uncertainty: 0.077ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Discrete Jitter (DJ): 0.136ns
|
|
Phase Error (PE): 0.000ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock mlkem_clk_clk_pll rise edge)
|
|
0.000 0.000 r
|
|
clock source latency -6.275 -6.275
|
|
propagated clock network latency
|
|
3.586 -2.690
|
|
SLICE_X91Y121 FDCE 0.000 -2.690 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/C
|
|
SLICE_X91Y121 FDCE (Prop_fdce_C_Q) 0.456 -2.234 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/Q
|
|
net (fo=169, routed) 6.237 4.004 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st[4]
|
|
SLICE_X157Y96 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/I0
|
|
SLICE_X157Y96 LUT5 (Prop_lut5_I0_O) 0.124 4.128 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/O
|
|
net (fo=936, routed) 21.901 26.029 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/sha3_mb_en0
|
|
SLICE_X44Y135 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[969]_i_1/I1
|
|
SLICE_X44Y135 LUT6 (Prop_lut6_I1_O) 0.124 26.153 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[969]_i_1/O
|
|
net (fo=1, routed) 0.000 26.153 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram_n_1143
|
|
SLICE_X44Y135 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[969]/D
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock mlkem_clk_clk_pll rise edge)
|
|
40.000 40.000 r
|
|
clock source latency -5.674 34.326
|
|
propagated clock network latency
|
|
3.396 37.721
|
|
clock pessimism -0.507 37.214
|
|
clock uncertainty -0.077 37.138
|
|
SLICE_X44Y135 FDCE (Setup_fdce_C_D) 0.081 37.219 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[969]
|
|
-------------------------------------------------------------------
|
|
required time 37.219
|
|
arrival time -26.153
|
|
-------------------------------------------------------------------
|
|
slack 11.066
|
|
|
|
Slack (MET) : 11.066ns (required time - arrival time)
|
|
Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/C
|
|
(rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns})
|
|
Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[969]/D
|
|
(rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns})
|
|
Path Group: mlkem_clk_clk_pll
|
|
Path Type: Setup (Max at Slow Process Corner)
|
|
Requirement: 40.000ns (mlkem_clk_clk_pll rise@40.000ns - mlkem_clk_clk_pll rise@0.000ns)
|
|
Data Path Delay: 28.842ns (logic 0.704ns (2.441%) route 28.138ns (97.559%))
|
|
Logic Levels: 2 (LUT5=1 LUT6=1)
|
|
Clock Path Skew: -0.096ns (DCD - SCD + CPR)
|
|
Destination Clock Delay (DCD): -2.279ns = ( 37.721 - 40.000 )
|
|
Source Clock Delay (SCD): -2.690ns
|
|
Clock Pessimism Removal (CPR): -0.507ns
|
|
Clock Uncertainty: 0.077ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Discrete Jitter (DJ): 0.136ns
|
|
Phase Error (PE): 0.000ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock mlkem_clk_clk_pll rise edge)
|
|
0.000 0.000 r
|
|
clock source latency -6.275 -6.275
|
|
propagated clock network latency
|
|
3.586 -2.690
|
|
SLICE_X91Y121 FDCE 0.000 -2.690 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/C
|
|
SLICE_X91Y121 FDCE (Prop_fdce_C_Q) 0.456 -2.234 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/Q
|
|
net (fo=169, routed) 6.237 4.004 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st[4]
|
|
SLICE_X157Y96 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/I0
|
|
SLICE_X157Y96 LUT5 (Prop_lut5_I0_O) 0.124 4.128 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/O
|
|
net (fo=936, routed) 21.901 26.029 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/sha3_mb_en0
|
|
SLICE_X44Y135 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[969]_i_1/I1
|
|
SLICE_X44Y135 LUT6 (Prop_lut6_I1_O) 0.124 26.153 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[969]_i_1/O
|
|
net (fo=1, routed) 0.000 26.153 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram_n_1143
|
|
SLICE_X44Y135 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[969]/D
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock mlkem_clk_clk_pll rise edge)
|
|
40.000 40.000 r
|
|
clock source latency -5.674 34.326
|
|
propagated clock network latency
|
|
3.396 37.721
|
|
clock pessimism -0.507 37.214
|
|
clock uncertainty -0.077 37.138
|
|
SLICE_X44Y135 FDCE (Setup_fdce_C_D) 0.081 37.219 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[969]
|
|
-------------------------------------------------------------------
|
|
required time 37.219
|
|
arrival time -26.153
|
|
-------------------------------------------------------------------
|
|
slack 11.066
|
|
|
|
Slack (MET) : 11.066ns (required time - arrival time)
|
|
Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/C
|
|
(rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns})
|
|
Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[969]/D
|
|
(rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns})
|
|
Path Group: mlkem_clk_clk_pll
|
|
Path Type: Setup (Max at Slow Process Corner)
|
|
Requirement: 40.000ns (mlkem_clk_clk_pll rise@40.000ns - mlkem_clk_clk_pll rise@0.000ns)
|
|
Data Path Delay: 28.842ns (logic 0.704ns (2.441%) route 28.138ns (97.559%))
|
|
Logic Levels: 2 (LUT5=1 LUT6=1)
|
|
Clock Path Skew: -0.096ns (DCD - SCD + CPR)
|
|
Destination Clock Delay (DCD): -2.279ns = ( 37.721 - 40.000 )
|
|
Source Clock Delay (SCD): -2.690ns
|
|
Clock Pessimism Removal (CPR): -0.507ns
|
|
Clock Uncertainty: 0.077ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Discrete Jitter (DJ): 0.136ns
|
|
Phase Error (PE): 0.000ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock mlkem_clk_clk_pll rise edge)
|
|
0.000 0.000 r
|
|
clock source latency -6.275 -6.275
|
|
propagated clock network latency
|
|
3.586 -2.690
|
|
SLICE_X91Y121 FDCE 0.000 -2.690 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/C
|
|
SLICE_X91Y121 FDCE (Prop_fdce_C_Q) 0.456 -2.234 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/Q
|
|
net (fo=169, routed) 6.237 4.004 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st[4]
|
|
SLICE_X157Y96 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/I0
|
|
SLICE_X157Y96 LUT5 (Prop_lut5_I0_O) 0.124 4.128 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/O
|
|
net (fo=936, routed) 21.901 26.029 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/sha3_mb_en0
|
|
SLICE_X44Y135 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[969]_i_1/I1
|
|
SLICE_X44Y135 LUT6 (Prop_lut6_I1_O) 0.124 26.153 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[969]_i_1/O
|
|
net (fo=1, routed) 0.000 26.153 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram_n_1143
|
|
SLICE_X44Y135 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[969]/D
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock mlkem_clk_clk_pll rise edge)
|
|
40.000 40.000 r
|
|
clock source latency -5.674 34.326
|
|
propagated clock network latency
|
|
3.396 37.721
|
|
clock pessimism -0.507 37.214
|
|
clock uncertainty -0.077 37.138
|
|
SLICE_X44Y135 FDCE (Setup_fdce_C_D) 0.081 37.219 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[969]
|
|
-------------------------------------------------------------------
|
|
required time 37.219
|
|
arrival time -26.153
|
|
-------------------------------------------------------------------
|
|
slack 11.066
|
|
|
|
Slack (MET) : 11.144ns (required time - arrival time)
|
|
Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[2]_rep/C
|
|
(rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns})
|
|
Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[827]/D
|
|
(rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns})
|
|
Path Group: mlkem_clk_clk_pll
|
|
Path Type: Setup (Max at Slow Process Corner)
|
|
Requirement: 40.000ns (mlkem_clk_clk_pll rise@40.000ns - mlkem_clk_clk_pll rise@0.000ns)
|
|
Data Path Delay: 28.692ns (logic 0.704ns (2.454%) route 27.988ns (97.546%))
|
|
Logic Levels: 2 (LUT5=1 LUT6=1)
|
|
Clock Path Skew: -0.117ns (DCD - SCD + CPR)
|
|
Destination Clock Delay (DCD): -2.279ns = ( 37.721 - 40.000 )
|
|
Source Clock Delay (SCD): -2.669ns
|
|
Clock Pessimism Removal (CPR): -0.507ns
|
|
Clock Uncertainty: 0.077ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Discrete Jitter (DJ): 0.136ns
|
|
Phase Error (PE): 0.000ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock mlkem_clk_clk_pll rise edge)
|
|
0.000 0.000 r
|
|
clock source latency -6.275 -6.275
|
|
propagated clock network latency
|
|
3.607 -2.669
|
|
SLICE_X107Y119 FDCE 0.000 -2.669 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[2]_rep/C
|
|
SLICE_X107Y119 FDCE (Prop_fdce_C_Q) 0.456 -2.213 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[2]_rep/Q
|
|
net (fo=109, routed) 5.879 3.667 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[2]_rep_n_0
|
|
SLICE_X157Y96 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/I3
|
|
SLICE_X157Y96 LUT5 (Prop_lut5_I3_O) 0.124 3.791 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/O
|
|
net (fo=936, routed) 22.108 25.899 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/sha3_mb_en0
|
|
SLICE_X45Y135 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[827]_i_1/I1
|
|
SLICE_X45Y135 LUT6 (Prop_lut6_I1_O) 0.124 26.023 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[827]_i_1/O
|
|
net (fo=1, routed) 0.000 26.023 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram_n_470
|
|
SLICE_X45Y135 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[827]/D
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock mlkem_clk_clk_pll rise edge)
|
|
40.000 40.000 r
|
|
clock source latency -5.674 34.326
|
|
propagated clock network latency
|
|
3.396 37.721
|
|
clock pessimism -0.507 37.214
|
|
clock uncertainty -0.077 37.138
|
|
SLICE_X45Y135 FDCE (Setup_fdce_C_D) 0.029 37.167 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[827]
|
|
-------------------------------------------------------------------
|
|
required time 37.167
|
|
arrival time -26.023
|
|
-------------------------------------------------------------------
|
|
slack 11.144
|
|
|
|
Slack (MET) : 11.144ns (required time - arrival time)
|
|
Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[2]_rep/C
|
|
(rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns})
|
|
Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[827]/D
|
|
(rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns})
|
|
Path Group: mlkem_clk_clk_pll
|
|
Path Type: Setup (Max at Slow Process Corner)
|
|
Requirement: 40.000ns (mlkem_clk_clk_pll rise@40.000ns - mlkem_clk_clk_pll rise@0.000ns)
|
|
Data Path Delay: 28.692ns (logic 0.704ns (2.454%) route 27.988ns (97.546%))
|
|
Logic Levels: 2 (LUT5=1 LUT6=1)
|
|
Clock Path Skew: -0.117ns (DCD - SCD + CPR)
|
|
Destination Clock Delay (DCD): -2.279ns = ( 37.721 - 40.000 )
|
|
Source Clock Delay (SCD): -2.669ns
|
|
Clock Pessimism Removal (CPR): -0.507ns
|
|
Clock Uncertainty: 0.077ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Discrete Jitter (DJ): 0.136ns
|
|
Phase Error (PE): 0.000ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock mlkem_clk_clk_pll rise edge)
|
|
0.000 0.000 r
|
|
clock source latency -6.275 -6.275
|
|
propagated clock network latency
|
|
3.607 -2.669
|
|
SLICE_X107Y119 FDCE 0.000 -2.669 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[2]_rep/C
|
|
SLICE_X107Y119 FDCE (Prop_fdce_C_Q) 0.456 -2.213 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[2]_rep/Q
|
|
net (fo=109, routed) 5.879 3.667 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[2]_rep_n_0
|
|
SLICE_X157Y96 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/I3
|
|
SLICE_X157Y96 LUT5 (Prop_lut5_I3_O) 0.124 3.791 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/O
|
|
net (fo=936, routed) 22.108 25.899 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/sha3_mb_en0
|
|
SLICE_X45Y135 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[827]_i_1/I1
|
|
SLICE_X45Y135 LUT6 (Prop_lut6_I1_O) 0.124 26.023 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[827]_i_1/O
|
|
net (fo=1, routed) 0.000 26.023 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram_n_470
|
|
SLICE_X45Y135 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[827]/D
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock mlkem_clk_clk_pll rise edge)
|
|
40.000 40.000 r
|
|
clock source latency -5.674 34.326
|
|
propagated clock network latency
|
|
3.396 37.721
|
|
clock pessimism -0.507 37.214
|
|
clock uncertainty -0.077 37.138
|
|
SLICE_X45Y135 FDCE (Setup_fdce_C_D) 0.029 37.167 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[827]
|
|
-------------------------------------------------------------------
|
|
required time 37.167
|
|
arrival time -26.023
|
|
-------------------------------------------------------------------
|
|
slack 11.144
|
|
|
|
Slack (MET) : 11.144ns (required time - arrival time)
|
|
Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[2]_rep/C
|
|
(rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns})
|
|
Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[827]/D
|
|
(rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns})
|
|
Path Group: mlkem_clk_clk_pll
|
|
Path Type: Setup (Max at Slow Process Corner)
|
|
Requirement: 40.000ns (mlkem_clk_clk_pll rise@40.000ns - mlkem_clk_clk_pll rise@0.000ns)
|
|
Data Path Delay: 28.692ns (logic 0.704ns (2.454%) route 27.988ns (97.546%))
|
|
Logic Levels: 2 (LUT5=1 LUT6=1)
|
|
Clock Path Skew: -0.117ns (DCD - SCD + CPR)
|
|
Destination Clock Delay (DCD): -2.279ns = ( 37.721 - 40.000 )
|
|
Source Clock Delay (SCD): -2.669ns
|
|
Clock Pessimism Removal (CPR): -0.507ns
|
|
Clock Uncertainty: 0.077ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Discrete Jitter (DJ): 0.136ns
|
|
Phase Error (PE): 0.000ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock mlkem_clk_clk_pll rise edge)
|
|
0.000 0.000 r
|
|
clock source latency -6.275 -6.275
|
|
propagated clock network latency
|
|
3.607 -2.669
|
|
SLICE_X107Y119 FDCE 0.000 -2.669 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[2]_rep/C
|
|
SLICE_X107Y119 FDCE (Prop_fdce_C_Q) 0.456 -2.213 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[2]_rep/Q
|
|
net (fo=109, routed) 5.879 3.667 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[2]_rep_n_0
|
|
SLICE_X157Y96 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/I3
|
|
SLICE_X157Y96 LUT5 (Prop_lut5_I3_O) 0.124 3.791 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/O
|
|
net (fo=936, routed) 22.108 25.899 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/sha3_mb_en0
|
|
SLICE_X45Y135 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[827]_i_1/I1
|
|
SLICE_X45Y135 LUT6 (Prop_lut6_I1_O) 0.124 26.023 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[827]_i_1/O
|
|
net (fo=1, routed) 0.000 26.023 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram_n_470
|
|
SLICE_X45Y135 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[827]/D
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock mlkem_clk_clk_pll rise edge)
|
|
40.000 40.000 r
|
|
clock source latency -5.674 34.326
|
|
propagated clock network latency
|
|
3.396 37.721
|
|
clock pessimism -0.507 37.214
|
|
clock uncertainty -0.077 37.138
|
|
SLICE_X45Y135 FDCE (Setup_fdce_C_D) 0.029 37.167 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[827]
|
|
-------------------------------------------------------------------
|
|
required time 37.167
|
|
arrival time -26.023
|
|
-------------------------------------------------------------------
|
|
slack 11.144
|
|
|
|
Slack (MET) : 11.144ns (required time - arrival time)
|
|
Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[2]_rep/C
|
|
(rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns})
|
|
Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[827]/D
|
|
(rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns})
|
|
Path Group: mlkem_clk_clk_pll
|
|
Path Type: Setup (Max at Slow Process Corner)
|
|
Requirement: 40.000ns (mlkem_clk_clk_pll rise@40.000ns - mlkem_clk_clk_pll rise@0.000ns)
|
|
Data Path Delay: 28.692ns (logic 0.704ns (2.454%) route 27.988ns (97.546%))
|
|
Logic Levels: 2 (LUT5=1 LUT6=1)
|
|
Clock Path Skew: -0.117ns (DCD - SCD + CPR)
|
|
Destination Clock Delay (DCD): -2.279ns = ( 37.721 - 40.000 )
|
|
Source Clock Delay (SCD): -2.669ns
|
|
Clock Pessimism Removal (CPR): -0.507ns
|
|
Clock Uncertainty: 0.077ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Discrete Jitter (DJ): 0.136ns
|
|
Phase Error (PE): 0.000ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock mlkem_clk_clk_pll rise edge)
|
|
0.000 0.000 r
|
|
clock source latency -6.275 -6.275
|
|
propagated clock network latency
|
|
3.607 -2.669
|
|
SLICE_X107Y119 FDCE 0.000 -2.669 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[2]_rep/C
|
|
SLICE_X107Y119 FDCE (Prop_fdce_C_Q) 0.456 -2.213 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[2]_rep/Q
|
|
net (fo=109, routed) 5.879 3.667 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[2]_rep_n_0
|
|
SLICE_X157Y96 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/I3
|
|
SLICE_X157Y96 LUT5 (Prop_lut5_I3_O) 0.124 3.791 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/O
|
|
net (fo=936, routed) 22.108 25.899 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/sha3_mb_en0
|
|
SLICE_X45Y135 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[827]_i_1/I1
|
|
SLICE_X45Y135 LUT6 (Prop_lut6_I1_O) 0.124 26.023 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[827]_i_1/O
|
|
net (fo=1, routed) 0.000 26.023 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram_n_470
|
|
SLICE_X45Y135 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[827]/D
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock mlkem_clk_clk_pll rise edge)
|
|
40.000 40.000 r
|
|
clock source latency -5.674 34.326
|
|
propagated clock network latency
|
|
3.396 37.721
|
|
clock pessimism -0.507 37.214
|
|
clock uncertainty -0.077 37.138
|
|
SLICE_X45Y135 FDCE (Setup_fdce_C_D) 0.029 37.167 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[827]
|
|
-------------------------------------------------------------------
|
|
required time 37.167
|
|
arrival time -26.023
|
|
-------------------------------------------------------------------
|
|
slack 11.144
|
|
|
|
Slack (MET) : 11.144ns (required time - arrival time)
|
|
Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[2]_rep/C
|
|
(rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns})
|
|
Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[827]/D
|
|
(rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns})
|
|
Path Group: mlkem_clk_clk_pll
|
|
Path Type: Setup (Max at Slow Process Corner)
|
|
Requirement: 40.000ns (mlkem_clk_clk_pll rise@40.000ns - mlkem_clk_clk_pll rise@0.000ns)
|
|
Data Path Delay: 28.692ns (logic 0.704ns (2.454%) route 27.988ns (97.546%))
|
|
Logic Levels: 2 (LUT5=1 LUT6=1)
|
|
Clock Path Skew: -0.117ns (DCD - SCD + CPR)
|
|
Destination Clock Delay (DCD): -2.279ns = ( 37.721 - 40.000 )
|
|
Source Clock Delay (SCD): -2.669ns
|
|
Clock Pessimism Removal (CPR): -0.507ns
|
|
Clock Uncertainty: 0.077ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Discrete Jitter (DJ): 0.136ns
|
|
Phase Error (PE): 0.000ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock mlkem_clk_clk_pll rise edge)
|
|
0.000 0.000 r
|
|
clock source latency -6.275 -6.275
|
|
propagated clock network latency
|
|
3.607 -2.669
|
|
SLICE_X107Y119 FDCE 0.000 -2.669 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[2]_rep/C
|
|
SLICE_X107Y119 FDCE (Prop_fdce_C_Q) 0.456 -2.213 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[2]_rep/Q
|
|
net (fo=109, routed) 5.879 3.667 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[2]_rep_n_0
|
|
SLICE_X157Y96 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/I3
|
|
SLICE_X157Y96 LUT5 (Prop_lut5_I3_O) 0.124 3.791 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/O
|
|
net (fo=936, routed) 22.108 25.899 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/sha3_mb_en0
|
|
SLICE_X45Y135 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[827]_i_1/I1
|
|
SLICE_X45Y135 LUT6 (Prop_lut6_I1_O) 0.124 26.023 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[827]_i_1/O
|
|
net (fo=1, routed) 0.000 26.023 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram_n_470
|
|
SLICE_X45Y135 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[827]/D
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock mlkem_clk_clk_pll rise edge)
|
|
40.000 40.000 r
|
|
clock source latency -5.674 34.326
|
|
propagated clock network latency
|
|
3.396 37.721
|
|
clock pessimism -0.507 37.214
|
|
clock uncertainty -0.077 37.138
|
|
SLICE_X45Y135 FDCE (Setup_fdce_C_D) 0.029 37.167 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[827]
|
|
-------------------------------------------------------------------
|
|
required time 37.167
|
|
arrival time -26.023
|
|
-------------------------------------------------------------------
|
|
slack 11.144
|
|
|
|
Slack (MET) : 11.144ns (required time - arrival time)
|
|
Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[2]_rep/C
|
|
(rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns})
|
|
Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[827]/D
|
|
(rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns})
|
|
Path Group: mlkem_clk_clk_pll
|
|
Path Type: Setup (Max at Slow Process Corner)
|
|
Requirement: 40.000ns (mlkem_clk_clk_pll rise@40.000ns - mlkem_clk_clk_pll rise@0.000ns)
|
|
Data Path Delay: 28.692ns (logic 0.704ns (2.454%) route 27.988ns (97.546%))
|
|
Logic Levels: 2 (LUT5=1 LUT6=1)
|
|
Clock Path Skew: -0.117ns (DCD - SCD + CPR)
|
|
Destination Clock Delay (DCD): -2.279ns = ( 37.721 - 40.000 )
|
|
Source Clock Delay (SCD): -2.669ns
|
|
Clock Pessimism Removal (CPR): -0.507ns
|
|
Clock Uncertainty: 0.077ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Discrete Jitter (DJ): 0.136ns
|
|
Phase Error (PE): 0.000ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock mlkem_clk_clk_pll rise edge)
|
|
0.000 0.000 r
|
|
clock source latency -6.275 -6.275
|
|
propagated clock network latency
|
|
3.607 -2.669
|
|
SLICE_X107Y119 FDCE 0.000 -2.669 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[2]_rep/C
|
|
SLICE_X107Y119 FDCE (Prop_fdce_C_Q) 0.456 -2.213 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[2]_rep/Q
|
|
net (fo=109, routed) 5.879 3.667 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[2]_rep_n_0
|
|
SLICE_X157Y96 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/I3
|
|
SLICE_X157Y96 LUT5 (Prop_lut5_I3_O) 0.124 3.791 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/O
|
|
net (fo=936, routed) 22.108 25.899 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/sha3_mb_en0
|
|
SLICE_X45Y135 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[827]_i_1/I1
|
|
SLICE_X45Y135 LUT6 (Prop_lut6_I1_O) 0.124 26.023 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[827]_i_1/O
|
|
net (fo=1, routed) 0.000 26.023 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram_n_470
|
|
SLICE_X45Y135 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[827]/D
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock mlkem_clk_clk_pll rise edge)
|
|
40.000 40.000 r
|
|
clock source latency -5.674 34.326
|
|
propagated clock network latency
|
|
3.396 37.721
|
|
clock pessimism -0.507 37.214
|
|
clock uncertainty -0.077 37.138
|
|
SLICE_X45Y135 FDCE (Setup_fdce_C_D) 0.029 37.167 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[827]
|
|
-------------------------------------------------------------------
|
|
required time 37.167
|
|
arrival time -26.023
|
|
-------------------------------------------------------------------
|
|
slack 11.144
|
|
|
|
Slack (MET) : 11.162ns (required time - arrival time)
|
|
Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/C
|
|
(rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns})
|
|
Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[828]/D
|
|
(rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns})
|
|
Path Group: mlkem_clk_clk_pll
|
|
Path Type: Setup (Max at Slow Process Corner)
|
|
Requirement: 40.000ns (mlkem_clk_clk_pll rise@40.000ns - mlkem_clk_clk_pll rise@0.000ns)
|
|
Data Path Delay: 28.693ns (logic 0.704ns (2.454%) route 27.989ns (97.546%))
|
|
Logic Levels: 2 (LUT5=1 LUT6=1)
|
|
Clock Path Skew: -0.098ns (DCD - SCD + CPR)
|
|
Destination Clock Delay (DCD): -2.281ns = ( 37.719 - 40.000 )
|
|
Source Clock Delay (SCD): -2.690ns
|
|
Clock Pessimism Removal (CPR): -0.507ns
|
|
Clock Uncertainty: 0.077ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Discrete Jitter (DJ): 0.136ns
|
|
Phase Error (PE): 0.000ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock mlkem_clk_clk_pll rise edge)
|
|
0.000 0.000 r
|
|
clock source latency -6.275 -6.275
|
|
propagated clock network latency
|
|
3.586 -2.690
|
|
SLICE_X91Y121 FDCE 0.000 -2.690 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/C
|
|
SLICE_X91Y121 FDCE (Prop_fdce_C_Q) 0.456 -2.234 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/Q
|
|
net (fo=169, routed) 6.237 4.004 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st[4]
|
|
SLICE_X157Y96 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/I0
|
|
SLICE_X157Y96 LUT5 (Prop_lut5_I0_O) 0.124 4.128 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/O
|
|
net (fo=936, routed) 21.751 25.879 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/sha3_mb_en0
|
|
SLICE_X45Y133 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[828]_i_1/I1
|
|
SLICE_X45Y133 LUT6 (Prop_lut6_I1_O) 0.124 26.003 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[828]_i_1/O
|
|
net (fo=1, routed) 0.000 26.003 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram_n_471
|
|
SLICE_X45Y133 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[828]/D
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock mlkem_clk_clk_pll rise edge)
|
|
40.000 40.000 r
|
|
clock source latency -5.674 34.326
|
|
propagated clock network latency
|
|
3.394 37.719
|
|
clock pessimism -0.507 37.212
|
|
clock uncertainty -0.077 37.136
|
|
SLICE_X45Y133 FDCE (Setup_fdce_C_D) 0.029 37.165 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[828]
|
|
-------------------------------------------------------------------
|
|
required time 37.165
|
|
arrival time -26.003
|
|
-------------------------------------------------------------------
|
|
slack 11.162
|
|
|
|
Slack (MET) : 11.162ns (required time - arrival time)
|
|
Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/C
|
|
(rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns})
|
|
Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[828]/D
|
|
(rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns})
|
|
Path Group: mlkem_clk_clk_pll
|
|
Path Type: Setup (Max at Slow Process Corner)
|
|
Requirement: 40.000ns (mlkem_clk_clk_pll rise@40.000ns - mlkem_clk_clk_pll rise@0.000ns)
|
|
Data Path Delay: 28.693ns (logic 0.704ns (2.454%) route 27.989ns (97.546%))
|
|
Logic Levels: 2 (LUT5=1 LUT6=1)
|
|
Clock Path Skew: -0.098ns (DCD - SCD + CPR)
|
|
Destination Clock Delay (DCD): -2.281ns = ( 37.719 - 40.000 )
|
|
Source Clock Delay (SCD): -2.690ns
|
|
Clock Pessimism Removal (CPR): -0.507ns
|
|
Clock Uncertainty: 0.077ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Discrete Jitter (DJ): 0.136ns
|
|
Phase Error (PE): 0.000ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock mlkem_clk_clk_pll rise edge)
|
|
0.000 0.000 r
|
|
clock source latency -6.275 -6.275
|
|
propagated clock network latency
|
|
3.586 -2.690
|
|
SLICE_X91Y121 FDCE 0.000 -2.690 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/C
|
|
SLICE_X91Y121 FDCE (Prop_fdce_C_Q) 0.456 -2.234 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/Q
|
|
net (fo=169, routed) 6.237 4.004 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st[4]
|
|
SLICE_X157Y96 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/I0
|
|
SLICE_X157Y96 LUT5 (Prop_lut5_I0_O) 0.124 4.128 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/O
|
|
net (fo=936, routed) 21.751 25.879 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/sha3_mb_en0
|
|
SLICE_X45Y133 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[828]_i_1/I1
|
|
SLICE_X45Y133 LUT6 (Prop_lut6_I1_O) 0.124 26.003 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[828]_i_1/O
|
|
net (fo=1, routed) 0.000 26.003 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram_n_471
|
|
SLICE_X45Y133 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[828]/D
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock mlkem_clk_clk_pll rise edge)
|
|
40.000 40.000 r
|
|
clock source latency -5.674 34.326
|
|
propagated clock network latency
|
|
3.394 37.719
|
|
clock pessimism -0.507 37.212
|
|
clock uncertainty -0.077 37.136
|
|
SLICE_X45Y133 FDCE (Setup_fdce_C_D) 0.029 37.165 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[828]
|
|
-------------------------------------------------------------------
|
|
required time 37.165
|
|
arrival time -26.003
|
|
-------------------------------------------------------------------
|
|
slack 11.162
|
|
|
|
Slack (MET) : 11.162ns (required time - arrival time)
|
|
Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/C
|
|
(rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns})
|
|
Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[828]/D
|
|
(rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns})
|
|
Path Group: mlkem_clk_clk_pll
|
|
Path Type: Setup (Max at Slow Process Corner)
|
|
Requirement: 40.000ns (mlkem_clk_clk_pll rise@40.000ns - mlkem_clk_clk_pll rise@0.000ns)
|
|
Data Path Delay: 28.693ns (logic 0.704ns (2.454%) route 27.989ns (97.546%))
|
|
Logic Levels: 2 (LUT5=1 LUT6=1)
|
|
Clock Path Skew: -0.098ns (DCD - SCD + CPR)
|
|
Destination Clock Delay (DCD): -2.281ns = ( 37.719 - 40.000 )
|
|
Source Clock Delay (SCD): -2.690ns
|
|
Clock Pessimism Removal (CPR): -0.507ns
|
|
Clock Uncertainty: 0.077ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Discrete Jitter (DJ): 0.136ns
|
|
Phase Error (PE): 0.000ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock mlkem_clk_clk_pll rise edge)
|
|
0.000 0.000 r
|
|
clock source latency -6.275 -6.275
|
|
propagated clock network latency
|
|
3.586 -2.690
|
|
SLICE_X91Y121 FDCE 0.000 -2.690 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/C
|
|
SLICE_X91Y121 FDCE (Prop_fdce_C_Q) 0.456 -2.234 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/Q
|
|
net (fo=169, routed) 6.237 4.004 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st[4]
|
|
SLICE_X157Y96 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/I0
|
|
SLICE_X157Y96 LUT5 (Prop_lut5_I0_O) 0.124 4.128 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/O
|
|
net (fo=936, routed) 21.751 25.879 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/sha3_mb_en0
|
|
SLICE_X45Y133 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[828]_i_1/I1
|
|
SLICE_X45Y133 LUT6 (Prop_lut6_I1_O) 0.124 26.003 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[828]_i_1/O
|
|
net (fo=1, routed) 0.000 26.003 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram_n_471
|
|
SLICE_X45Y133 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[828]/D
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock mlkem_clk_clk_pll rise edge)
|
|
40.000 40.000 r
|
|
clock source latency -5.674 34.326
|
|
propagated clock network latency
|
|
3.394 37.719
|
|
clock pessimism -0.507 37.212
|
|
clock uncertainty -0.077 37.136
|
|
SLICE_X45Y133 FDCE (Setup_fdce_C_D) 0.029 37.165 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[828]
|
|
-------------------------------------------------------------------
|
|
required time 37.165
|
|
arrival time -26.003
|
|
-------------------------------------------------------------------
|
|
slack 11.162
|
|
|
|
Slack (MET) : 11.162ns (required time - arrival time)
|
|
Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/C
|
|
(rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns})
|
|
Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[828]/D
|
|
(rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns})
|
|
Path Group: mlkem_clk_clk_pll
|
|
Path Type: Setup (Max at Slow Process Corner)
|
|
Requirement: 40.000ns (mlkem_clk_clk_pll rise@40.000ns - mlkem_clk_clk_pll rise@0.000ns)
|
|
Data Path Delay: 28.693ns (logic 0.704ns (2.454%) route 27.989ns (97.546%))
|
|
Logic Levels: 2 (LUT5=1 LUT6=1)
|
|
Clock Path Skew: -0.098ns (DCD - SCD + CPR)
|
|
Destination Clock Delay (DCD): -2.281ns = ( 37.719 - 40.000 )
|
|
Source Clock Delay (SCD): -2.690ns
|
|
Clock Pessimism Removal (CPR): -0.507ns
|
|
Clock Uncertainty: 0.077ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Discrete Jitter (DJ): 0.136ns
|
|
Phase Error (PE): 0.000ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock mlkem_clk_clk_pll rise edge)
|
|
0.000 0.000 r
|
|
clock source latency -6.275 -6.275
|
|
propagated clock network latency
|
|
3.586 -2.690
|
|
SLICE_X91Y121 FDCE 0.000 -2.690 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/C
|
|
SLICE_X91Y121 FDCE (Prop_fdce_C_Q) 0.456 -2.234 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/Q
|
|
net (fo=169, routed) 6.237 4.004 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st[4]
|
|
SLICE_X157Y96 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/I0
|
|
SLICE_X157Y96 LUT5 (Prop_lut5_I0_O) 0.124 4.128 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/O
|
|
net (fo=936, routed) 21.751 25.879 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/sha3_mb_en0
|
|
SLICE_X45Y133 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[828]_i_1/I1
|
|
SLICE_X45Y133 LUT6 (Prop_lut6_I1_O) 0.124 26.003 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[828]_i_1/O
|
|
net (fo=1, routed) 0.000 26.003 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram_n_471
|
|
SLICE_X45Y133 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[828]/D
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock mlkem_clk_clk_pll rise edge)
|
|
40.000 40.000 r
|
|
clock source latency -5.674 34.326
|
|
propagated clock network latency
|
|
3.394 37.719
|
|
clock pessimism -0.507 37.212
|
|
clock uncertainty -0.077 37.136
|
|
SLICE_X45Y133 FDCE (Setup_fdce_C_D) 0.029 37.165 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[828]
|
|
-------------------------------------------------------------------
|
|
required time 37.165
|
|
arrival time -26.003
|
|
-------------------------------------------------------------------
|
|
slack 11.162
|
|
|
|
Slack (MET) : 11.217ns (required time - arrival time)
|
|
Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/C
|
|
(rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns})
|
|
Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[906]/D
|
|
(rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns})
|
|
Path Group: mlkem_clk_clk_pll
|
|
Path Type: Setup (Max at Slow Process Corner)
|
|
Requirement: 40.000ns (mlkem_clk_clk_pll rise@40.000ns - mlkem_clk_clk_pll rise@0.000ns)
|
|
Data Path Delay: 28.639ns (logic 0.704ns (2.458%) route 27.935ns (97.542%))
|
|
Logic Levels: 2 (LUT5=1 LUT6=1)
|
|
Clock Path Skew: -0.097ns (DCD - SCD + CPR)
|
|
Destination Clock Delay (DCD): -2.280ns = ( 37.720 - 40.000 )
|
|
Source Clock Delay (SCD): -2.690ns
|
|
Clock Pessimism Removal (CPR): -0.507ns
|
|
Clock Uncertainty: 0.077ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Discrete Jitter (DJ): 0.136ns
|
|
Phase Error (PE): 0.000ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock mlkem_clk_clk_pll rise edge)
|
|
0.000 0.000 r
|
|
clock source latency -6.275 -6.275
|
|
propagated clock network latency
|
|
3.586 -2.690
|
|
SLICE_X91Y121 FDCE 0.000 -2.690 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/C
|
|
SLICE_X91Y121 FDCE (Prop_fdce_C_Q) 0.456 -2.234 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/Q
|
|
net (fo=169, routed) 6.237 4.004 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st[4]
|
|
SLICE_X157Y96 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/I0
|
|
SLICE_X157Y96 LUT5 (Prop_lut5_I0_O) 0.124 4.128 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/O
|
|
net (fo=936, routed) 21.697 25.825 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/sha3_mb_en0
|
|
SLICE_X45Y134 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[906]_i_1/I1
|
|
SLICE_X45Y134 LUT6 (Prop_lut6_I1_O) 0.124 25.949 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[906]_i_1/O
|
|
net (fo=1, routed) 0.000 25.949 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram_n_917
|
|
SLICE_X45Y134 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[906]/D
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock mlkem_clk_clk_pll rise edge)
|
|
40.000 40.000 r
|
|
clock source latency -5.674 34.326
|
|
propagated clock network latency
|
|
3.395 37.720
|
|
clock pessimism -0.507 37.213
|
|
clock uncertainty -0.077 37.137
|
|
SLICE_X45Y134 FDCE (Setup_fdce_C_D) 0.029 37.166 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[906]
|
|
-------------------------------------------------------------------
|
|
required time 37.166
|
|
arrival time -25.949
|
|
-------------------------------------------------------------------
|
|
slack 11.217
|
|
|
|
Slack (MET) : 11.217ns (required time - arrival time)
|
|
Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/C
|
|
(rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns})
|
|
Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[906]/D
|
|
(rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns})
|
|
Path Group: mlkem_clk_clk_pll
|
|
Path Type: Setup (Max at Slow Process Corner)
|
|
Requirement: 40.000ns (mlkem_clk_clk_pll rise@40.000ns - mlkem_clk_clk_pll rise@0.000ns)
|
|
Data Path Delay: 28.639ns (logic 0.704ns (2.458%) route 27.935ns (97.542%))
|
|
Logic Levels: 2 (LUT5=1 LUT6=1)
|
|
Clock Path Skew: -0.097ns (DCD - SCD + CPR)
|
|
Destination Clock Delay (DCD): -2.280ns = ( 37.720 - 40.000 )
|
|
Source Clock Delay (SCD): -2.690ns
|
|
Clock Pessimism Removal (CPR): -0.507ns
|
|
Clock Uncertainty: 0.077ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Discrete Jitter (DJ): 0.136ns
|
|
Phase Error (PE): 0.000ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock mlkem_clk_clk_pll rise edge)
|
|
0.000 0.000 r
|
|
clock source latency -6.275 -6.275
|
|
propagated clock network latency
|
|
3.586 -2.690
|
|
SLICE_X91Y121 FDCE 0.000 -2.690 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/C
|
|
SLICE_X91Y121 FDCE (Prop_fdce_C_Q) 0.456 -2.234 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/Q
|
|
net (fo=169, routed) 6.237 4.004 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st[4]
|
|
SLICE_X157Y96 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/I0
|
|
SLICE_X157Y96 LUT5 (Prop_lut5_I0_O) 0.124 4.128 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/O
|
|
net (fo=936, routed) 21.697 25.825 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/sha3_mb_en0
|
|
SLICE_X45Y134 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[906]_i_1/I1
|
|
SLICE_X45Y134 LUT6 (Prop_lut6_I1_O) 0.124 25.949 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[906]_i_1/O
|
|
net (fo=1, routed) 0.000 25.949 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram_n_917
|
|
SLICE_X45Y134 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[906]/D
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock mlkem_clk_clk_pll rise edge)
|
|
40.000 40.000 r
|
|
clock source latency -5.674 34.326
|
|
propagated clock network latency
|
|
3.395 37.720
|
|
clock pessimism -0.507 37.213
|
|
clock uncertainty -0.077 37.137
|
|
SLICE_X45Y134 FDCE (Setup_fdce_C_D) 0.029 37.166 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[906]
|
|
-------------------------------------------------------------------
|
|
required time 37.166
|
|
arrival time -25.949
|
|
-------------------------------------------------------------------
|
|
slack 11.217
|
|
|
|
Slack (MET) : 11.217ns (required time - arrival time)
|
|
Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/C
|
|
(rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns})
|
|
Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[906]/D
|
|
(rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns})
|
|
Path Group: mlkem_clk_clk_pll
|
|
Path Type: Setup (Max at Slow Process Corner)
|
|
Requirement: 40.000ns (mlkem_clk_clk_pll rise@40.000ns - mlkem_clk_clk_pll rise@0.000ns)
|
|
Data Path Delay: 28.639ns (logic 0.704ns (2.458%) route 27.935ns (97.542%))
|
|
Logic Levels: 2 (LUT5=1 LUT6=1)
|
|
Clock Path Skew: -0.097ns (DCD - SCD + CPR)
|
|
Destination Clock Delay (DCD): -2.280ns = ( 37.720 - 40.000 )
|
|
Source Clock Delay (SCD): -2.690ns
|
|
Clock Pessimism Removal (CPR): -0.507ns
|
|
Clock Uncertainty: 0.077ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Discrete Jitter (DJ): 0.136ns
|
|
Phase Error (PE): 0.000ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock mlkem_clk_clk_pll rise edge)
|
|
0.000 0.000 r
|
|
clock source latency -6.275 -6.275
|
|
propagated clock network latency
|
|
3.586 -2.690
|
|
SLICE_X91Y121 FDCE 0.000 -2.690 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/C
|
|
SLICE_X91Y121 FDCE (Prop_fdce_C_Q) 0.456 -2.234 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/Q
|
|
net (fo=169, routed) 6.237 4.004 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st[4]
|
|
SLICE_X157Y96 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/I0
|
|
SLICE_X157Y96 LUT5 (Prop_lut5_I0_O) 0.124 4.128 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/O
|
|
net (fo=936, routed) 21.697 25.825 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/sha3_mb_en0
|
|
SLICE_X45Y134 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[906]_i_1/I1
|
|
SLICE_X45Y134 LUT6 (Prop_lut6_I1_O) 0.124 25.949 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[906]_i_1/O
|
|
net (fo=1, routed) 0.000 25.949 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram_n_917
|
|
SLICE_X45Y134 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[906]/D
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock mlkem_clk_clk_pll rise edge)
|
|
40.000 40.000 r
|
|
clock source latency -5.674 34.326
|
|
propagated clock network latency
|
|
3.395 37.720
|
|
clock pessimism -0.507 37.213
|
|
clock uncertainty -0.077 37.137
|
|
SLICE_X45Y134 FDCE (Setup_fdce_C_D) 0.029 37.166 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[906]
|
|
-------------------------------------------------------------------
|
|
required time 37.166
|
|
arrival time -25.949
|
|
-------------------------------------------------------------------
|
|
slack 11.217
|
|
|
|
Slack (MET) : 11.217ns (required time - arrival time)
|
|
Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/C
|
|
(rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns})
|
|
Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[906]/D
|
|
(rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns})
|
|
Path Group: mlkem_clk_clk_pll
|
|
Path Type: Setup (Max at Slow Process Corner)
|
|
Requirement: 40.000ns (mlkem_clk_clk_pll rise@40.000ns - mlkem_clk_clk_pll rise@0.000ns)
|
|
Data Path Delay: 28.639ns (logic 0.704ns (2.458%) route 27.935ns (97.542%))
|
|
Logic Levels: 2 (LUT5=1 LUT6=1)
|
|
Clock Path Skew: -0.097ns (DCD - SCD + CPR)
|
|
Destination Clock Delay (DCD): -2.280ns = ( 37.720 - 40.000 )
|
|
Source Clock Delay (SCD): -2.690ns
|
|
Clock Pessimism Removal (CPR): -0.507ns
|
|
Clock Uncertainty: 0.077ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Discrete Jitter (DJ): 0.136ns
|
|
Phase Error (PE): 0.000ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock mlkem_clk_clk_pll rise edge)
|
|
0.000 0.000 r
|
|
clock source latency -6.275 -6.275
|
|
propagated clock network latency
|
|
3.586 -2.690
|
|
SLICE_X91Y121 FDCE 0.000 -2.690 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/C
|
|
SLICE_X91Y121 FDCE (Prop_fdce_C_Q) 0.456 -2.234 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/Q
|
|
net (fo=169, routed) 6.237 4.004 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st[4]
|
|
SLICE_X157Y96 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/I0
|
|
SLICE_X157Y96 LUT5 (Prop_lut5_I0_O) 0.124 4.128 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/O
|
|
net (fo=936, routed) 21.697 25.825 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/sha3_mb_en0
|
|
SLICE_X45Y134 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[906]_i_1/I1
|
|
SLICE_X45Y134 LUT6 (Prop_lut6_I1_O) 0.124 25.949 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[906]_i_1/O
|
|
net (fo=1, routed) 0.000 25.949 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram_n_917
|
|
SLICE_X45Y134 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[906]/D
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock mlkem_clk_clk_pll rise edge)
|
|
40.000 40.000 r
|
|
clock source latency -5.674 34.326
|
|
propagated clock network latency
|
|
3.395 37.720
|
|
clock pessimism -0.507 37.213
|
|
clock uncertainty -0.077 37.137
|
|
SLICE_X45Y134 FDCE (Setup_fdce_C_D) 0.029 37.166 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[906]
|
|
-------------------------------------------------------------------
|
|
required time 37.166
|
|
arrival time -25.949
|
|
-------------------------------------------------------------------
|
|
slack 11.217
|
|
|
|
Slack (MET) : 11.241ns (required time - arrival time)
|
|
Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[2]_rep/C
|
|
(rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns})
|
|
Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[780]/D
|
|
(rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns})
|
|
Path Group: mlkem_clk_clk_pll
|
|
Path Type: Setup (Max at Slow Process Corner)
|
|
Requirement: 40.000ns (mlkem_clk_clk_pll rise@40.000ns - mlkem_clk_clk_pll rise@0.000ns)
|
|
Data Path Delay: 28.646ns (logic 0.704ns (2.458%) route 27.942ns (97.542%))
|
|
Logic Levels: 2 (LUT5=1 LUT6=1)
|
|
Clock Path Skew: -0.117ns (DCD - SCD + CPR)
|
|
Destination Clock Delay (DCD): -2.279ns = ( 37.721 - 40.000 )
|
|
Source Clock Delay (SCD): -2.669ns
|
|
Clock Pessimism Removal (CPR): -0.507ns
|
|
Clock Uncertainty: 0.077ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Discrete Jitter (DJ): 0.136ns
|
|
Phase Error (PE): 0.000ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock mlkem_clk_clk_pll rise edge)
|
|
0.000 0.000 r
|
|
clock source latency -6.275 -6.275
|
|
propagated clock network latency
|
|
3.607 -2.669
|
|
SLICE_X107Y119 FDCE 0.000 -2.669 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[2]_rep/C
|
|
SLICE_X107Y119 FDCE (Prop_fdce_C_Q) 0.456 -2.213 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[2]_rep/Q
|
|
net (fo=109, routed) 5.879 3.667 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[2]_rep_n_0
|
|
SLICE_X157Y96 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/I3
|
|
SLICE_X157Y96 LUT5 (Prop_lut5_I3_O) 0.124 3.791 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/O
|
|
net (fo=936, routed) 22.063 25.854 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/sha3_mb_en0
|
|
SLICE_X46Y135 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[780]_i_1/I1
|
|
SLICE_X46Y135 LUT6 (Prop_lut6_I1_O) 0.124 25.978 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[780]_i_1/O
|
|
net (fo=1, routed) 0.000 25.978 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram_n_912
|
|
SLICE_X46Y135 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[780]/D
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock mlkem_clk_clk_pll rise edge)
|
|
40.000 40.000 r
|
|
clock source latency -5.674 34.326
|
|
propagated clock network latency
|
|
3.396 37.721
|
|
clock pessimism -0.507 37.214
|
|
clock uncertainty -0.077 37.138
|
|
SLICE_X46Y135 FDCE (Setup_fdce_C_D) 0.081 37.219 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[780]
|
|
-------------------------------------------------------------------
|
|
required time 37.219
|
|
arrival time -25.978
|
|
-------------------------------------------------------------------
|
|
slack 11.241
|
|
|
|
Slack (MET) : 11.241ns (required time - arrival time)
|
|
Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[2]_rep/C
|
|
(rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns})
|
|
Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[780]/D
|
|
(rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns})
|
|
Path Group: mlkem_clk_clk_pll
|
|
Path Type: Setup (Max at Slow Process Corner)
|
|
Requirement: 40.000ns (mlkem_clk_clk_pll rise@40.000ns - mlkem_clk_clk_pll rise@0.000ns)
|
|
Data Path Delay: 28.646ns (logic 0.704ns (2.458%) route 27.942ns (97.542%))
|
|
Logic Levels: 2 (LUT5=1 LUT6=1)
|
|
Clock Path Skew: -0.117ns (DCD - SCD + CPR)
|
|
Destination Clock Delay (DCD): -2.279ns = ( 37.721 - 40.000 )
|
|
Source Clock Delay (SCD): -2.669ns
|
|
Clock Pessimism Removal (CPR): -0.507ns
|
|
Clock Uncertainty: 0.077ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Discrete Jitter (DJ): 0.136ns
|
|
Phase Error (PE): 0.000ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock mlkem_clk_clk_pll rise edge)
|
|
0.000 0.000 r
|
|
clock source latency -6.275 -6.275
|
|
propagated clock network latency
|
|
3.607 -2.669
|
|
SLICE_X107Y119 FDCE 0.000 -2.669 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[2]_rep/C
|
|
SLICE_X107Y119 FDCE (Prop_fdce_C_Q) 0.456 -2.213 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[2]_rep/Q
|
|
net (fo=109, routed) 5.879 3.667 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[2]_rep_n_0
|
|
SLICE_X157Y96 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/I3
|
|
SLICE_X157Y96 LUT5 (Prop_lut5_I3_O) 0.124 3.791 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/O
|
|
net (fo=936, routed) 22.063 25.854 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/sha3_mb_en0
|
|
SLICE_X46Y135 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[780]_i_1/I1
|
|
SLICE_X46Y135 LUT6 (Prop_lut6_I1_O) 0.124 25.978 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[780]_i_1/O
|
|
net (fo=1, routed) 0.000 25.978 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram_n_912
|
|
SLICE_X46Y135 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[780]/D
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock mlkem_clk_clk_pll rise edge)
|
|
40.000 40.000 r
|
|
clock source latency -5.674 34.326
|
|
propagated clock network latency
|
|
3.396 37.721
|
|
clock pessimism -0.507 37.214
|
|
clock uncertainty -0.077 37.138
|
|
SLICE_X46Y135 FDCE (Setup_fdce_C_D) 0.081 37.219 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[780]
|
|
-------------------------------------------------------------------
|
|
required time 37.219
|
|
arrival time -25.978
|
|
-------------------------------------------------------------------
|
|
slack 11.241
|
|
|
|
Slack (MET) : 11.241ns (required time - arrival time)
|
|
Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[2]_rep/C
|
|
(rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns})
|
|
Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[780]/D
|
|
(rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns})
|
|
Path Group: mlkem_clk_clk_pll
|
|
Path Type: Setup (Max at Slow Process Corner)
|
|
Requirement: 40.000ns (mlkem_clk_clk_pll rise@40.000ns - mlkem_clk_clk_pll rise@0.000ns)
|
|
Data Path Delay: 28.646ns (logic 0.704ns (2.458%) route 27.942ns (97.542%))
|
|
Logic Levels: 2 (LUT5=1 LUT6=1)
|
|
Clock Path Skew: -0.117ns (DCD - SCD + CPR)
|
|
Destination Clock Delay (DCD): -2.279ns = ( 37.721 - 40.000 )
|
|
Source Clock Delay (SCD): -2.669ns
|
|
Clock Pessimism Removal (CPR): -0.507ns
|
|
Clock Uncertainty: 0.077ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Discrete Jitter (DJ): 0.136ns
|
|
Phase Error (PE): 0.000ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock mlkem_clk_clk_pll rise edge)
|
|
0.000 0.000 r
|
|
clock source latency -6.275 -6.275
|
|
propagated clock network latency
|
|
3.607 -2.669
|
|
SLICE_X107Y119 FDCE 0.000 -2.669 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[2]_rep/C
|
|
SLICE_X107Y119 FDCE (Prop_fdce_C_Q) 0.456 -2.213 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[2]_rep/Q
|
|
net (fo=109, routed) 5.879 3.667 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[2]_rep_n_0
|
|
SLICE_X157Y96 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/I3
|
|
SLICE_X157Y96 LUT5 (Prop_lut5_I3_O) 0.124 3.791 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/O
|
|
net (fo=936, routed) 22.063 25.854 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/sha3_mb_en0
|
|
SLICE_X46Y135 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[780]_i_1/I1
|
|
SLICE_X46Y135 LUT6 (Prop_lut6_I1_O) 0.124 25.978 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[780]_i_1/O
|
|
net (fo=1, routed) 0.000 25.978 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram_n_912
|
|
SLICE_X46Y135 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[780]/D
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock mlkem_clk_clk_pll rise edge)
|
|
40.000 40.000 r
|
|
clock source latency -5.674 34.326
|
|
propagated clock network latency
|
|
3.396 37.721
|
|
clock pessimism -0.507 37.214
|
|
clock uncertainty -0.077 37.138
|
|
SLICE_X46Y135 FDCE (Setup_fdce_C_D) 0.081 37.219 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[780]
|
|
-------------------------------------------------------------------
|
|
required time 37.219
|
|
arrival time -25.978
|
|
-------------------------------------------------------------------
|
|
slack 11.241
|
|
|
|
Slack (MET) : 11.241ns (required time - arrival time)
|
|
Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[2]_rep/C
|
|
(rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns})
|
|
Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[780]/D
|
|
(rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns})
|
|
Path Group: mlkem_clk_clk_pll
|
|
Path Type: Setup (Max at Slow Process Corner)
|
|
Requirement: 40.000ns (mlkem_clk_clk_pll rise@40.000ns - mlkem_clk_clk_pll rise@0.000ns)
|
|
Data Path Delay: 28.646ns (logic 0.704ns (2.458%) route 27.942ns (97.542%))
|
|
Logic Levels: 2 (LUT5=1 LUT6=1)
|
|
Clock Path Skew: -0.117ns (DCD - SCD + CPR)
|
|
Destination Clock Delay (DCD): -2.279ns = ( 37.721 - 40.000 )
|
|
Source Clock Delay (SCD): -2.669ns
|
|
Clock Pessimism Removal (CPR): -0.507ns
|
|
Clock Uncertainty: 0.077ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Discrete Jitter (DJ): 0.136ns
|
|
Phase Error (PE): 0.000ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock mlkem_clk_clk_pll rise edge)
|
|
0.000 0.000 r
|
|
clock source latency -6.275 -6.275
|
|
propagated clock network latency
|
|
3.607 -2.669
|
|
SLICE_X107Y119 FDCE 0.000 -2.669 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[2]_rep/C
|
|
SLICE_X107Y119 FDCE (Prop_fdce_C_Q) 0.456 -2.213 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[2]_rep/Q
|
|
net (fo=109, routed) 5.879 3.667 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[2]_rep_n_0
|
|
SLICE_X157Y96 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/I3
|
|
SLICE_X157Y96 LUT5 (Prop_lut5_I3_O) 0.124 3.791 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/O
|
|
net (fo=936, routed) 22.063 25.854 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/sha3_mb_en0
|
|
SLICE_X46Y135 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[780]_i_1/I1
|
|
SLICE_X46Y135 LUT6 (Prop_lut6_I1_O) 0.124 25.978 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[780]_i_1/O
|
|
net (fo=1, routed) 0.000 25.978 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram_n_912
|
|
SLICE_X46Y135 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[780]/D
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock mlkem_clk_clk_pll rise edge)
|
|
40.000 40.000 r
|
|
clock source latency -5.674 34.326
|
|
propagated clock network latency
|
|
3.396 37.721
|
|
clock pessimism -0.507 37.214
|
|
clock uncertainty -0.077 37.138
|
|
SLICE_X46Y135 FDCE (Setup_fdce_C_D) 0.081 37.219 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[780]
|
|
-------------------------------------------------------------------
|
|
required time 37.219
|
|
arrival time -25.978
|
|
-------------------------------------------------------------------
|
|
slack 11.241
|
|
|
|
Slack (MET) : 11.241ns (required time - arrival time)
|
|
Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[2]_rep/C
|
|
(rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns})
|
|
Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[780]/D
|
|
(rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns})
|
|
Path Group: mlkem_clk_clk_pll
|
|
Path Type: Setup (Max at Slow Process Corner)
|
|
Requirement: 40.000ns (mlkem_clk_clk_pll rise@40.000ns - mlkem_clk_clk_pll rise@0.000ns)
|
|
Data Path Delay: 28.646ns (logic 0.704ns (2.458%) route 27.942ns (97.542%))
|
|
Logic Levels: 2 (LUT5=1 LUT6=1)
|
|
Clock Path Skew: -0.117ns (DCD - SCD + CPR)
|
|
Destination Clock Delay (DCD): -2.279ns = ( 37.721 - 40.000 )
|
|
Source Clock Delay (SCD): -2.669ns
|
|
Clock Pessimism Removal (CPR): -0.507ns
|
|
Clock Uncertainty: 0.077ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Discrete Jitter (DJ): 0.136ns
|
|
Phase Error (PE): 0.000ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock mlkem_clk_clk_pll rise edge)
|
|
0.000 0.000 r
|
|
clock source latency -6.275 -6.275
|
|
propagated clock network latency
|
|
3.607 -2.669
|
|
SLICE_X107Y119 FDCE 0.000 -2.669 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[2]_rep/C
|
|
SLICE_X107Y119 FDCE (Prop_fdce_C_Q) 0.456 -2.213 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[2]_rep/Q
|
|
net (fo=109, routed) 5.879 3.667 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[2]_rep_n_0
|
|
SLICE_X157Y96 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/I3
|
|
SLICE_X157Y96 LUT5 (Prop_lut5_I3_O) 0.124 3.791 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/O
|
|
net (fo=936, routed) 22.063 25.854 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/sha3_mb_en0
|
|
SLICE_X46Y135 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[780]_i_1/I1
|
|
SLICE_X46Y135 LUT6 (Prop_lut6_I1_O) 0.124 25.978 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[780]_i_1/O
|
|
net (fo=1, routed) 0.000 25.978 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram_n_912
|
|
SLICE_X46Y135 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[780]/D
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock mlkem_clk_clk_pll rise edge)
|
|
40.000 40.000 r
|
|
clock source latency -5.674 34.326
|
|
propagated clock network latency
|
|
3.396 37.721
|
|
clock pessimism -0.507 37.214
|
|
clock uncertainty -0.077 37.138
|
|
SLICE_X46Y135 FDCE (Setup_fdce_C_D) 0.081 37.219 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[780]
|
|
-------------------------------------------------------------------
|
|
required time 37.219
|
|
arrival time -25.978
|
|
-------------------------------------------------------------------
|
|
slack 11.241
|
|
|
|
Slack (MET) : 11.241ns (required time - arrival time)
|
|
Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[2]_rep/C
|
|
(rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns})
|
|
Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[780]/D
|
|
(rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns})
|
|
Path Group: mlkem_clk_clk_pll
|
|
Path Type: Setup (Max at Slow Process Corner)
|
|
Requirement: 40.000ns (mlkem_clk_clk_pll rise@40.000ns - mlkem_clk_clk_pll rise@0.000ns)
|
|
Data Path Delay: 28.646ns (logic 0.704ns (2.458%) route 27.942ns (97.542%))
|
|
Logic Levels: 2 (LUT5=1 LUT6=1)
|
|
Clock Path Skew: -0.117ns (DCD - SCD + CPR)
|
|
Destination Clock Delay (DCD): -2.279ns = ( 37.721 - 40.000 )
|
|
Source Clock Delay (SCD): -2.669ns
|
|
Clock Pessimism Removal (CPR): -0.507ns
|
|
Clock Uncertainty: 0.077ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Discrete Jitter (DJ): 0.136ns
|
|
Phase Error (PE): 0.000ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock mlkem_clk_clk_pll rise edge)
|
|
0.000 0.000 r
|
|
clock source latency -6.275 -6.275
|
|
propagated clock network latency
|
|
3.607 -2.669
|
|
SLICE_X107Y119 FDCE 0.000 -2.669 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[2]_rep/C
|
|
SLICE_X107Y119 FDCE (Prop_fdce_C_Q) 0.456 -2.213 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[2]_rep/Q
|
|
net (fo=109, routed) 5.879 3.667 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[2]_rep_n_0
|
|
SLICE_X157Y96 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/I3
|
|
SLICE_X157Y96 LUT5 (Prop_lut5_I3_O) 0.124 3.791 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/O
|
|
net (fo=936, routed) 22.063 25.854 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/sha3_mb_en0
|
|
SLICE_X46Y135 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[780]_i_1/I1
|
|
SLICE_X46Y135 LUT6 (Prop_lut6_I1_O) 0.124 25.978 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[780]_i_1/O
|
|
net (fo=1, routed) 0.000 25.978 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram_n_912
|
|
SLICE_X46Y135 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[780]/D
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock mlkem_clk_clk_pll rise edge)
|
|
40.000 40.000 r
|
|
clock source latency -5.674 34.326
|
|
propagated clock network latency
|
|
3.396 37.721
|
|
clock pessimism -0.507 37.214
|
|
clock uncertainty -0.077 37.138
|
|
SLICE_X46Y135 FDCE (Setup_fdce_C_D) 0.081 37.219 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[780]
|
|
-------------------------------------------------------------------
|
|
required time 37.219
|
|
arrival time -25.978
|
|
-------------------------------------------------------------------
|
|
slack 11.241
|
|
|
|
Slack (MET) : 11.246ns (required time - arrival time)
|
|
Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/C
|
|
(rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns})
|
|
Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[830]/D
|
|
(rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns})
|
|
Path Group: mlkem_clk_clk_pll
|
|
Path Type: Setup (Max at Slow Process Corner)
|
|
Requirement: 40.000ns (mlkem_clk_clk_pll rise@40.000ns - mlkem_clk_clk_pll rise@0.000ns)
|
|
Data Path Delay: 28.658ns (logic 0.704ns (2.457%) route 27.954ns (97.543%))
|
|
Logic Levels: 2 (LUT5=1 LUT6=1)
|
|
Clock Path Skew: -0.097ns (DCD - SCD + CPR)
|
|
Destination Clock Delay (DCD): -2.280ns = ( 37.720 - 40.000 )
|
|
Source Clock Delay (SCD): -2.690ns
|
|
Clock Pessimism Removal (CPR): -0.507ns
|
|
Clock Uncertainty: 0.077ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Discrete Jitter (DJ): 0.136ns
|
|
Phase Error (PE): 0.000ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock mlkem_clk_clk_pll rise edge)
|
|
0.000 0.000 r
|
|
clock source latency -6.275 -6.275
|
|
propagated clock network latency
|
|
3.586 -2.690
|
|
SLICE_X91Y121 FDCE 0.000 -2.690 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/C
|
|
SLICE_X91Y121 FDCE (Prop_fdce_C_Q) 0.456 -2.234 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/Q
|
|
net (fo=169, routed) 6.237 4.004 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st[4]
|
|
SLICE_X157Y96 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/I0
|
|
SLICE_X157Y96 LUT5 (Prop_lut5_I0_O) 0.124 4.128 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/O
|
|
net (fo=936, routed) 21.716 25.844 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/sha3_mb_en0
|
|
SLICE_X44Y134 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[830]_i_1/I1
|
|
SLICE_X44Y134 LUT6 (Prop_lut6_I1_O) 0.124 25.968 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[830]_i_1/O
|
|
net (fo=1, routed) 0.000 25.968 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram_n_473
|
|
SLICE_X44Y134 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[830]/D
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock mlkem_clk_clk_pll rise edge)
|
|
40.000 40.000 r
|
|
clock source latency -5.674 34.326
|
|
propagated clock network latency
|
|
3.395 37.720
|
|
clock pessimism -0.507 37.213
|
|
clock uncertainty -0.077 37.137
|
|
SLICE_X44Y134 FDCE (Setup_fdce_C_D) 0.077 37.214 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[830]
|
|
-------------------------------------------------------------------
|
|
required time 37.214
|
|
arrival time -25.968
|
|
-------------------------------------------------------------------
|
|
slack 11.246
|
|
|
|
Slack (MET) : 11.246ns (required time - arrival time)
|
|
Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/C
|
|
(rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns})
|
|
Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[830]/D
|
|
(rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns})
|
|
Path Group: mlkem_clk_clk_pll
|
|
Path Type: Setup (Max at Slow Process Corner)
|
|
Requirement: 40.000ns (mlkem_clk_clk_pll rise@40.000ns - mlkem_clk_clk_pll rise@0.000ns)
|
|
Data Path Delay: 28.658ns (logic 0.704ns (2.457%) route 27.954ns (97.543%))
|
|
Logic Levels: 2 (LUT5=1 LUT6=1)
|
|
Clock Path Skew: -0.097ns (DCD - SCD + CPR)
|
|
Destination Clock Delay (DCD): -2.280ns = ( 37.720 - 40.000 )
|
|
Source Clock Delay (SCD): -2.690ns
|
|
Clock Pessimism Removal (CPR): -0.507ns
|
|
Clock Uncertainty: 0.077ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Discrete Jitter (DJ): 0.136ns
|
|
Phase Error (PE): 0.000ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock mlkem_clk_clk_pll rise edge)
|
|
0.000 0.000 r
|
|
clock source latency -6.275 -6.275
|
|
propagated clock network latency
|
|
3.586 -2.690
|
|
SLICE_X91Y121 FDCE 0.000 -2.690 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/C
|
|
SLICE_X91Y121 FDCE (Prop_fdce_C_Q) 0.456 -2.234 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/Q
|
|
net (fo=169, routed) 6.237 4.004 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st[4]
|
|
SLICE_X157Y96 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/I0
|
|
SLICE_X157Y96 LUT5 (Prop_lut5_I0_O) 0.124 4.128 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/O
|
|
net (fo=936, routed) 21.716 25.844 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/sha3_mb_en0
|
|
SLICE_X44Y134 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[830]_i_1/I1
|
|
SLICE_X44Y134 LUT6 (Prop_lut6_I1_O) 0.124 25.968 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[830]_i_1/O
|
|
net (fo=1, routed) 0.000 25.968 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram_n_473
|
|
SLICE_X44Y134 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[830]/D
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock mlkem_clk_clk_pll rise edge)
|
|
40.000 40.000 r
|
|
clock source latency -5.674 34.326
|
|
propagated clock network latency
|
|
3.395 37.720
|
|
clock pessimism -0.507 37.213
|
|
clock uncertainty -0.077 37.137
|
|
SLICE_X44Y134 FDCE (Setup_fdce_C_D) 0.077 37.214 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[830]
|
|
-------------------------------------------------------------------
|
|
required time 37.214
|
|
arrival time -25.968
|
|
-------------------------------------------------------------------
|
|
slack 11.246
|
|
|
|
Slack (MET) : 11.246ns (required time - arrival time)
|
|
Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/C
|
|
(rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns})
|
|
Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[830]/D
|
|
(rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns})
|
|
Path Group: mlkem_clk_clk_pll
|
|
Path Type: Setup (Max at Slow Process Corner)
|
|
Requirement: 40.000ns (mlkem_clk_clk_pll rise@40.000ns - mlkem_clk_clk_pll rise@0.000ns)
|
|
Data Path Delay: 28.658ns (logic 0.704ns (2.457%) route 27.954ns (97.543%))
|
|
Logic Levels: 2 (LUT5=1 LUT6=1)
|
|
Clock Path Skew: -0.097ns (DCD - SCD + CPR)
|
|
Destination Clock Delay (DCD): -2.280ns = ( 37.720 - 40.000 )
|
|
Source Clock Delay (SCD): -2.690ns
|
|
Clock Pessimism Removal (CPR): -0.507ns
|
|
Clock Uncertainty: 0.077ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Discrete Jitter (DJ): 0.136ns
|
|
Phase Error (PE): 0.000ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock mlkem_clk_clk_pll rise edge)
|
|
0.000 0.000 r
|
|
clock source latency -6.275 -6.275
|
|
propagated clock network latency
|
|
3.586 -2.690
|
|
SLICE_X91Y121 FDCE 0.000 -2.690 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/C
|
|
SLICE_X91Y121 FDCE (Prop_fdce_C_Q) 0.456 -2.234 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/Q
|
|
net (fo=169, routed) 6.237 4.004 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st[4]
|
|
SLICE_X157Y96 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/I0
|
|
SLICE_X157Y96 LUT5 (Prop_lut5_I0_O) 0.124 4.128 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/O
|
|
net (fo=936, routed) 21.716 25.844 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/sha3_mb_en0
|
|
SLICE_X44Y134 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[830]_i_1/I1
|
|
SLICE_X44Y134 LUT6 (Prop_lut6_I1_O) 0.124 25.968 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[830]_i_1/O
|
|
net (fo=1, routed) 0.000 25.968 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram_n_473
|
|
SLICE_X44Y134 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[830]/D
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock mlkem_clk_clk_pll rise edge)
|
|
40.000 40.000 r
|
|
clock source latency -5.674 34.326
|
|
propagated clock network latency
|
|
3.395 37.720
|
|
clock pessimism -0.507 37.213
|
|
clock uncertainty -0.077 37.137
|
|
SLICE_X44Y134 FDCE (Setup_fdce_C_D) 0.077 37.214 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[830]
|
|
-------------------------------------------------------------------
|
|
required time 37.214
|
|
arrival time -25.968
|
|
-------------------------------------------------------------------
|
|
slack 11.246
|
|
|
|
Slack (MET) : 11.246ns (required time - arrival time)
|
|
Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/C
|
|
(rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns})
|
|
Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[830]/D
|
|
(rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns})
|
|
Path Group: mlkem_clk_clk_pll
|
|
Path Type: Setup (Max at Slow Process Corner)
|
|
Requirement: 40.000ns (mlkem_clk_clk_pll rise@40.000ns - mlkem_clk_clk_pll rise@0.000ns)
|
|
Data Path Delay: 28.658ns (logic 0.704ns (2.457%) route 27.954ns (97.543%))
|
|
Logic Levels: 2 (LUT5=1 LUT6=1)
|
|
Clock Path Skew: -0.097ns (DCD - SCD + CPR)
|
|
Destination Clock Delay (DCD): -2.280ns = ( 37.720 - 40.000 )
|
|
Source Clock Delay (SCD): -2.690ns
|
|
Clock Pessimism Removal (CPR): -0.507ns
|
|
Clock Uncertainty: 0.077ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Discrete Jitter (DJ): 0.136ns
|
|
Phase Error (PE): 0.000ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock mlkem_clk_clk_pll rise edge)
|
|
0.000 0.000 r
|
|
clock source latency -6.275 -6.275
|
|
propagated clock network latency
|
|
3.586 -2.690
|
|
SLICE_X91Y121 FDCE 0.000 -2.690 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/C
|
|
SLICE_X91Y121 FDCE (Prop_fdce_C_Q) 0.456 -2.234 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/Q
|
|
net (fo=169, routed) 6.237 4.004 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st[4]
|
|
SLICE_X157Y96 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/I0
|
|
SLICE_X157Y96 LUT5 (Prop_lut5_I0_O) 0.124 4.128 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/O
|
|
net (fo=936, routed) 21.716 25.844 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/sha3_mb_en0
|
|
SLICE_X44Y134 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[830]_i_1/I1
|
|
SLICE_X44Y134 LUT6 (Prop_lut6_I1_O) 0.124 25.968 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[830]_i_1/O
|
|
net (fo=1, routed) 0.000 25.968 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram_n_473
|
|
SLICE_X44Y134 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[830]/D
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock mlkem_clk_clk_pll rise edge)
|
|
40.000 40.000 r
|
|
clock source latency -5.674 34.326
|
|
propagated clock network latency
|
|
3.395 37.720
|
|
clock pessimism -0.507 37.213
|
|
clock uncertainty -0.077 37.137
|
|
SLICE_X44Y134 FDCE (Setup_fdce_C_D) 0.077 37.214 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[830]
|
|
-------------------------------------------------------------------
|
|
required time 37.214
|
|
arrival time -25.968
|
|
-------------------------------------------------------------------
|
|
slack 11.246
|
|
|
|
Slack (MET) : 11.255ns (required time - arrival time)
|
|
Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[2]_rep/C
|
|
(rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns})
|
|
Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[782]/D
|
|
(rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns})
|
|
Path Group: mlkem_clk_clk_pll
|
|
Path Type: Setup (Max at Slow Process Corner)
|
|
Requirement: 40.000ns (mlkem_clk_clk_pll rise@40.000ns - mlkem_clk_clk_pll rise@0.000ns)
|
|
Data Path Delay: 28.629ns (logic 0.704ns (2.459%) route 27.925ns (97.541%))
|
|
Logic Levels: 2 (LUT5=1 LUT6=1)
|
|
Clock Path Skew: -0.117ns (DCD - SCD + CPR)
|
|
Destination Clock Delay (DCD): -2.279ns = ( 37.721 - 40.000 )
|
|
Source Clock Delay (SCD): -2.669ns
|
|
Clock Pessimism Removal (CPR): -0.507ns
|
|
Clock Uncertainty: 0.077ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Discrete Jitter (DJ): 0.136ns
|
|
Phase Error (PE): 0.000ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock mlkem_clk_clk_pll rise edge)
|
|
0.000 0.000 r
|
|
clock source latency -6.275 -6.275
|
|
propagated clock network latency
|
|
3.607 -2.669
|
|
SLICE_X107Y119 FDCE 0.000 -2.669 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[2]_rep/C
|
|
SLICE_X107Y119 FDCE (Prop_fdce_C_Q) 0.456 -2.213 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[2]_rep/Q
|
|
net (fo=109, routed) 5.879 3.667 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[2]_rep_n_0
|
|
SLICE_X157Y96 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/I3
|
|
SLICE_X157Y96 LUT5 (Prop_lut5_I3_O) 0.124 3.791 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/O
|
|
net (fo=936, routed) 22.045 25.836 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/sha3_mb_en0
|
|
SLICE_X44Y136 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[782]_i_1/I1
|
|
SLICE_X44Y136 LUT6 (Prop_lut6_I1_O) 0.124 25.960 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[782]_i_1/O
|
|
net (fo=1, routed) 0.000 25.960 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram_n_914
|
|
SLICE_X44Y136 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[782]/D
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock mlkem_clk_clk_pll rise edge)
|
|
40.000 40.000 r
|
|
clock source latency -5.674 34.326
|
|
propagated clock network latency
|
|
3.396 37.721
|
|
clock pessimism -0.507 37.214
|
|
clock uncertainty -0.077 37.138
|
|
SLICE_X44Y136 FDCE (Setup_fdce_C_D) 0.077 37.215 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[782]
|
|
-------------------------------------------------------------------
|
|
required time 37.215
|
|
arrival time -25.960
|
|
-------------------------------------------------------------------
|
|
slack 11.255
|
|
|
|
Slack (MET) : 11.255ns (required time - arrival time)
|
|
Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[2]_rep/C
|
|
(rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns})
|
|
Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[782]/D
|
|
(rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns})
|
|
Path Group: mlkem_clk_clk_pll
|
|
Path Type: Setup (Max at Slow Process Corner)
|
|
Requirement: 40.000ns (mlkem_clk_clk_pll rise@40.000ns - mlkem_clk_clk_pll rise@0.000ns)
|
|
Data Path Delay: 28.629ns (logic 0.704ns (2.459%) route 27.925ns (97.541%))
|
|
Logic Levels: 2 (LUT5=1 LUT6=1)
|
|
Clock Path Skew: -0.117ns (DCD - SCD + CPR)
|
|
Destination Clock Delay (DCD): -2.279ns = ( 37.721 - 40.000 )
|
|
Source Clock Delay (SCD): -2.669ns
|
|
Clock Pessimism Removal (CPR): -0.507ns
|
|
Clock Uncertainty: 0.077ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Discrete Jitter (DJ): 0.136ns
|
|
Phase Error (PE): 0.000ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock mlkem_clk_clk_pll rise edge)
|
|
0.000 0.000 r
|
|
clock source latency -6.275 -6.275
|
|
propagated clock network latency
|
|
3.607 -2.669
|
|
SLICE_X107Y119 FDCE 0.000 -2.669 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[2]_rep/C
|
|
SLICE_X107Y119 FDCE (Prop_fdce_C_Q) 0.456 -2.213 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[2]_rep/Q
|
|
net (fo=109, routed) 5.879 3.667 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[2]_rep_n_0
|
|
SLICE_X157Y96 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/I3
|
|
SLICE_X157Y96 LUT5 (Prop_lut5_I3_O) 0.124 3.791 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/O
|
|
net (fo=936, routed) 22.045 25.836 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/sha3_mb_en0
|
|
SLICE_X44Y136 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[782]_i_1/I1
|
|
SLICE_X44Y136 LUT6 (Prop_lut6_I1_O) 0.124 25.960 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[782]_i_1/O
|
|
net (fo=1, routed) 0.000 25.960 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram_n_914
|
|
SLICE_X44Y136 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[782]/D
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock mlkem_clk_clk_pll rise edge)
|
|
40.000 40.000 r
|
|
clock source latency -5.674 34.326
|
|
propagated clock network latency
|
|
3.396 37.721
|
|
clock pessimism -0.507 37.214
|
|
clock uncertainty -0.077 37.138
|
|
SLICE_X44Y136 FDCE (Setup_fdce_C_D) 0.077 37.215 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[782]
|
|
-------------------------------------------------------------------
|
|
required time 37.215
|
|
arrival time -25.960
|
|
-------------------------------------------------------------------
|
|
slack 11.255
|
|
|
|
Slack (MET) : 11.255ns (required time - arrival time)
|
|
Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[2]_rep/C
|
|
(rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns})
|
|
Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[782]/D
|
|
(rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns})
|
|
Path Group: mlkem_clk_clk_pll
|
|
Path Type: Setup (Max at Slow Process Corner)
|
|
Requirement: 40.000ns (mlkem_clk_clk_pll rise@40.000ns - mlkem_clk_clk_pll rise@0.000ns)
|
|
Data Path Delay: 28.629ns (logic 0.704ns (2.459%) route 27.925ns (97.541%))
|
|
Logic Levels: 2 (LUT5=1 LUT6=1)
|
|
Clock Path Skew: -0.117ns (DCD - SCD + CPR)
|
|
Destination Clock Delay (DCD): -2.279ns = ( 37.721 - 40.000 )
|
|
Source Clock Delay (SCD): -2.669ns
|
|
Clock Pessimism Removal (CPR): -0.507ns
|
|
Clock Uncertainty: 0.077ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Discrete Jitter (DJ): 0.136ns
|
|
Phase Error (PE): 0.000ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock mlkem_clk_clk_pll rise edge)
|
|
0.000 0.000 r
|
|
clock source latency -6.275 -6.275
|
|
propagated clock network latency
|
|
3.607 -2.669
|
|
SLICE_X107Y119 FDCE 0.000 -2.669 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[2]_rep/C
|
|
SLICE_X107Y119 FDCE (Prop_fdce_C_Q) 0.456 -2.213 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[2]_rep/Q
|
|
net (fo=109, routed) 5.879 3.667 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[2]_rep_n_0
|
|
SLICE_X157Y96 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/I3
|
|
SLICE_X157Y96 LUT5 (Prop_lut5_I3_O) 0.124 3.791 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/O
|
|
net (fo=936, routed) 22.045 25.836 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/sha3_mb_en0
|
|
SLICE_X44Y136 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[782]_i_1/I1
|
|
SLICE_X44Y136 LUT6 (Prop_lut6_I1_O) 0.124 25.960 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[782]_i_1/O
|
|
net (fo=1, routed) 0.000 25.960 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram_n_914
|
|
SLICE_X44Y136 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[782]/D
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock mlkem_clk_clk_pll rise edge)
|
|
40.000 40.000 r
|
|
clock source latency -5.674 34.326
|
|
propagated clock network latency
|
|
3.396 37.721
|
|
clock pessimism -0.507 37.214
|
|
clock uncertainty -0.077 37.138
|
|
SLICE_X44Y136 FDCE (Setup_fdce_C_D) 0.077 37.215 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[782]
|
|
-------------------------------------------------------------------
|
|
required time 37.215
|
|
arrival time -25.960
|
|
-------------------------------------------------------------------
|
|
slack 11.255
|
|
|
|
Slack (MET) : 11.255ns (required time - arrival time)
|
|
Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[2]_rep/C
|
|
(rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns})
|
|
Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[782]/D
|
|
(rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns})
|
|
Path Group: mlkem_clk_clk_pll
|
|
Path Type: Setup (Max at Slow Process Corner)
|
|
Requirement: 40.000ns (mlkem_clk_clk_pll rise@40.000ns - mlkem_clk_clk_pll rise@0.000ns)
|
|
Data Path Delay: 28.629ns (logic 0.704ns (2.459%) route 27.925ns (97.541%))
|
|
Logic Levels: 2 (LUT5=1 LUT6=1)
|
|
Clock Path Skew: -0.117ns (DCD - SCD + CPR)
|
|
Destination Clock Delay (DCD): -2.279ns = ( 37.721 - 40.000 )
|
|
Source Clock Delay (SCD): -2.669ns
|
|
Clock Pessimism Removal (CPR): -0.507ns
|
|
Clock Uncertainty: 0.077ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Discrete Jitter (DJ): 0.136ns
|
|
Phase Error (PE): 0.000ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock mlkem_clk_clk_pll rise edge)
|
|
0.000 0.000 r
|
|
clock source latency -6.275 -6.275
|
|
propagated clock network latency
|
|
3.607 -2.669
|
|
SLICE_X107Y119 FDCE 0.000 -2.669 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[2]_rep/C
|
|
SLICE_X107Y119 FDCE (Prop_fdce_C_Q) 0.456 -2.213 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[2]_rep/Q
|
|
net (fo=109, routed) 5.879 3.667 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[2]_rep_n_0
|
|
SLICE_X157Y96 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/I3
|
|
SLICE_X157Y96 LUT5 (Prop_lut5_I3_O) 0.124 3.791 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/O
|
|
net (fo=936, routed) 22.045 25.836 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/sha3_mb_en0
|
|
SLICE_X44Y136 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[782]_i_1/I1
|
|
SLICE_X44Y136 LUT6 (Prop_lut6_I1_O) 0.124 25.960 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[782]_i_1/O
|
|
net (fo=1, routed) 0.000 25.960 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram_n_914
|
|
SLICE_X44Y136 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[782]/D
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock mlkem_clk_clk_pll rise edge)
|
|
40.000 40.000 r
|
|
clock source latency -5.674 34.326
|
|
propagated clock network latency
|
|
3.396 37.721
|
|
clock pessimism -0.507 37.214
|
|
clock uncertainty -0.077 37.138
|
|
SLICE_X44Y136 FDCE (Setup_fdce_C_D) 0.077 37.215 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[782]
|
|
-------------------------------------------------------------------
|
|
required time 37.215
|
|
arrival time -25.960
|
|
-------------------------------------------------------------------
|
|
slack 11.255
|
|
|
|
Slack (MET) : 11.255ns (required time - arrival time)
|
|
Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[2]_rep/C
|
|
(rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns})
|
|
Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[782]/D
|
|
(rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns})
|
|
Path Group: mlkem_clk_clk_pll
|
|
Path Type: Setup (Max at Slow Process Corner)
|
|
Requirement: 40.000ns (mlkem_clk_clk_pll rise@40.000ns - mlkem_clk_clk_pll rise@0.000ns)
|
|
Data Path Delay: 28.629ns (logic 0.704ns (2.459%) route 27.925ns (97.541%))
|
|
Logic Levels: 2 (LUT5=1 LUT6=1)
|
|
Clock Path Skew: -0.117ns (DCD - SCD + CPR)
|
|
Destination Clock Delay (DCD): -2.279ns = ( 37.721 - 40.000 )
|
|
Source Clock Delay (SCD): -2.669ns
|
|
Clock Pessimism Removal (CPR): -0.507ns
|
|
Clock Uncertainty: 0.077ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Discrete Jitter (DJ): 0.136ns
|
|
Phase Error (PE): 0.000ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock mlkem_clk_clk_pll rise edge)
|
|
0.000 0.000 r
|
|
clock source latency -6.275 -6.275
|
|
propagated clock network latency
|
|
3.607 -2.669
|
|
SLICE_X107Y119 FDCE 0.000 -2.669 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[2]_rep/C
|
|
SLICE_X107Y119 FDCE (Prop_fdce_C_Q) 0.456 -2.213 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[2]_rep/Q
|
|
net (fo=109, routed) 5.879 3.667 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[2]_rep_n_0
|
|
SLICE_X157Y96 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/I3
|
|
SLICE_X157Y96 LUT5 (Prop_lut5_I3_O) 0.124 3.791 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/O
|
|
net (fo=936, routed) 22.045 25.836 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/sha3_mb_en0
|
|
SLICE_X44Y136 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[782]_i_1/I1
|
|
SLICE_X44Y136 LUT6 (Prop_lut6_I1_O) 0.124 25.960 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[782]_i_1/O
|
|
net (fo=1, routed) 0.000 25.960 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram_n_914
|
|
SLICE_X44Y136 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[782]/D
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock mlkem_clk_clk_pll rise edge)
|
|
40.000 40.000 r
|
|
clock source latency -5.674 34.326
|
|
propagated clock network latency
|
|
3.396 37.721
|
|
clock pessimism -0.507 37.214
|
|
clock uncertainty -0.077 37.138
|
|
SLICE_X44Y136 FDCE (Setup_fdce_C_D) 0.077 37.215 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[782]
|
|
-------------------------------------------------------------------
|
|
required time 37.215
|
|
arrival time -25.960
|
|
-------------------------------------------------------------------
|
|
slack 11.255
|
|
|
|
Slack (MET) : 11.255ns (required time - arrival time)
|
|
Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[2]_rep/C
|
|
(rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns})
|
|
Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[782]/D
|
|
(rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns})
|
|
Path Group: mlkem_clk_clk_pll
|
|
Path Type: Setup (Max at Slow Process Corner)
|
|
Requirement: 40.000ns (mlkem_clk_clk_pll rise@40.000ns - mlkem_clk_clk_pll rise@0.000ns)
|
|
Data Path Delay: 28.629ns (logic 0.704ns (2.459%) route 27.925ns (97.541%))
|
|
Logic Levels: 2 (LUT5=1 LUT6=1)
|
|
Clock Path Skew: -0.117ns (DCD - SCD + CPR)
|
|
Destination Clock Delay (DCD): -2.279ns = ( 37.721 - 40.000 )
|
|
Source Clock Delay (SCD): -2.669ns
|
|
Clock Pessimism Removal (CPR): -0.507ns
|
|
Clock Uncertainty: 0.077ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Discrete Jitter (DJ): 0.136ns
|
|
Phase Error (PE): 0.000ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock mlkem_clk_clk_pll rise edge)
|
|
0.000 0.000 r
|
|
clock source latency -6.275 -6.275
|
|
propagated clock network latency
|
|
3.607 -2.669
|
|
SLICE_X107Y119 FDCE 0.000 -2.669 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[2]_rep/C
|
|
SLICE_X107Y119 FDCE (Prop_fdce_C_Q) 0.456 -2.213 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[2]_rep/Q
|
|
net (fo=109, routed) 5.879 3.667 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[2]_rep_n_0
|
|
SLICE_X157Y96 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/I3
|
|
SLICE_X157Y96 LUT5 (Prop_lut5_I3_O) 0.124 3.791 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/O
|
|
net (fo=936, routed) 22.045 25.836 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/sha3_mb_en0
|
|
SLICE_X44Y136 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[782]_i_1/I1
|
|
SLICE_X44Y136 LUT6 (Prop_lut6_I1_O) 0.124 25.960 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[782]_i_1/O
|
|
net (fo=1, routed) 0.000 25.960 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram_n_914
|
|
SLICE_X44Y136 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[782]/D
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock mlkem_clk_clk_pll rise edge)
|
|
40.000 40.000 r
|
|
clock source latency -5.674 34.326
|
|
propagated clock network latency
|
|
3.396 37.721
|
|
clock pessimism -0.507 37.214
|
|
clock uncertainty -0.077 37.138
|
|
SLICE_X44Y136 FDCE (Setup_fdce_C_D) 0.077 37.215 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[782]
|
|
-------------------------------------------------------------------
|
|
required time 37.215
|
|
arrival time -25.960
|
|
-------------------------------------------------------------------
|
|
slack 11.255
|
|
|
|
Slack (MET) : 11.322ns (required time - arrival time)
|
|
Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/C
|
|
(rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns})
|
|
Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[953]/D
|
|
(rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns})
|
|
Path Group: mlkem_clk_clk_pll
|
|
Path Type: Setup (Max at Slow Process Corner)
|
|
Requirement: 40.000ns (mlkem_clk_clk_pll rise@40.000ns - mlkem_clk_clk_pll rise@0.000ns)
|
|
Data Path Delay: 28.534ns (logic 0.704ns (2.467%) route 27.830ns (97.533%))
|
|
Logic Levels: 2 (LUT5=1 LUT6=1)
|
|
Clock Path Skew: -0.099ns (DCD - SCD + CPR)
|
|
Destination Clock Delay (DCD): -2.282ns = ( 37.718 - 40.000 )
|
|
Source Clock Delay (SCD): -2.690ns
|
|
Clock Pessimism Removal (CPR): -0.507ns
|
|
Clock Uncertainty: 0.077ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Discrete Jitter (DJ): 0.136ns
|
|
Phase Error (PE): 0.000ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock mlkem_clk_clk_pll rise edge)
|
|
0.000 0.000 r
|
|
clock source latency -6.275 -6.275
|
|
propagated clock network latency
|
|
3.586 -2.690
|
|
SLICE_X91Y121 FDCE 0.000 -2.690 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/C
|
|
SLICE_X91Y121 FDCE (Prop_fdce_C_Q) 0.456 -2.234 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/Q
|
|
net (fo=169, routed) 6.237 4.004 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st[4]
|
|
SLICE_X157Y96 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/I0
|
|
SLICE_X157Y96 LUT5 (Prop_lut5_I0_O) 0.124 4.128 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/O
|
|
net (fo=936, routed) 21.592 25.720 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/sha3_mb_en0
|
|
SLICE_X45Y132 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[953]_i_1/I1
|
|
SLICE_X45Y132 LUT6 (Prop_lut6_I1_O) 0.124 25.844 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[953]_i_1/O
|
|
net (fo=1, routed) 0.000 25.844 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram_n_475
|
|
SLICE_X45Y132 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[953]/D
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock mlkem_clk_clk_pll rise edge)
|
|
40.000 40.000 r
|
|
clock source latency -5.674 34.326
|
|
propagated clock network latency
|
|
3.393 37.718
|
|
clock pessimism -0.507 37.211
|
|
clock uncertainty -0.077 37.135
|
|
SLICE_X45Y132 FDCE (Setup_fdce_C_D) 0.031 37.166 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[953]
|
|
-------------------------------------------------------------------
|
|
required time 37.166
|
|
arrival time -25.844
|
|
-------------------------------------------------------------------
|
|
slack 11.322
|
|
|
|
Slack (MET) : 11.322ns (required time - arrival time)
|
|
Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/C
|
|
(rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns})
|
|
Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[953]/D
|
|
(rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns})
|
|
Path Group: mlkem_clk_clk_pll
|
|
Path Type: Setup (Max at Slow Process Corner)
|
|
Requirement: 40.000ns (mlkem_clk_clk_pll rise@40.000ns - mlkem_clk_clk_pll rise@0.000ns)
|
|
Data Path Delay: 28.534ns (logic 0.704ns (2.467%) route 27.830ns (97.533%))
|
|
Logic Levels: 2 (LUT5=1 LUT6=1)
|
|
Clock Path Skew: -0.099ns (DCD - SCD + CPR)
|
|
Destination Clock Delay (DCD): -2.282ns = ( 37.718 - 40.000 )
|
|
Source Clock Delay (SCD): -2.690ns
|
|
Clock Pessimism Removal (CPR): -0.507ns
|
|
Clock Uncertainty: 0.077ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Discrete Jitter (DJ): 0.136ns
|
|
Phase Error (PE): 0.000ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock mlkem_clk_clk_pll rise edge)
|
|
0.000 0.000 r
|
|
clock source latency -6.275 -6.275
|
|
propagated clock network latency
|
|
3.586 -2.690
|
|
SLICE_X91Y121 FDCE 0.000 -2.690 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/C
|
|
SLICE_X91Y121 FDCE (Prop_fdce_C_Q) 0.456 -2.234 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/Q
|
|
net (fo=169, routed) 6.237 4.004 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st[4]
|
|
SLICE_X157Y96 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/I0
|
|
SLICE_X157Y96 LUT5 (Prop_lut5_I0_O) 0.124 4.128 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/O
|
|
net (fo=936, routed) 21.592 25.720 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/sha3_mb_en0
|
|
SLICE_X45Y132 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[953]_i_1/I1
|
|
SLICE_X45Y132 LUT6 (Prop_lut6_I1_O) 0.124 25.844 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[953]_i_1/O
|
|
net (fo=1, routed) 0.000 25.844 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram_n_475
|
|
SLICE_X45Y132 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[953]/D
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock mlkem_clk_clk_pll rise edge)
|
|
40.000 40.000 r
|
|
clock source latency -5.674 34.326
|
|
propagated clock network latency
|
|
3.393 37.718
|
|
clock pessimism -0.507 37.211
|
|
clock uncertainty -0.077 37.135
|
|
SLICE_X45Y132 FDCE (Setup_fdce_C_D) 0.031 37.166 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[953]
|
|
-------------------------------------------------------------------
|
|
required time 37.166
|
|
arrival time -25.844
|
|
-------------------------------------------------------------------
|
|
slack 11.322
|
|
|
|
Slack (MET) : 11.322ns (required time - arrival time)
|
|
Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/C
|
|
(rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns})
|
|
Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[953]/D
|
|
(rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns})
|
|
Path Group: mlkem_clk_clk_pll
|
|
Path Type: Setup (Max at Slow Process Corner)
|
|
Requirement: 40.000ns (mlkem_clk_clk_pll rise@40.000ns - mlkem_clk_clk_pll rise@0.000ns)
|
|
Data Path Delay: 28.534ns (logic 0.704ns (2.467%) route 27.830ns (97.533%))
|
|
Logic Levels: 2 (LUT5=1 LUT6=1)
|
|
Clock Path Skew: -0.099ns (DCD - SCD + CPR)
|
|
Destination Clock Delay (DCD): -2.282ns = ( 37.718 - 40.000 )
|
|
Source Clock Delay (SCD): -2.690ns
|
|
Clock Pessimism Removal (CPR): -0.507ns
|
|
Clock Uncertainty: 0.077ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Discrete Jitter (DJ): 0.136ns
|
|
Phase Error (PE): 0.000ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock mlkem_clk_clk_pll rise edge)
|
|
0.000 0.000 r
|
|
clock source latency -6.275 -6.275
|
|
propagated clock network latency
|
|
3.586 -2.690
|
|
SLICE_X91Y121 FDCE 0.000 -2.690 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/C
|
|
SLICE_X91Y121 FDCE (Prop_fdce_C_Q) 0.456 -2.234 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/Q
|
|
net (fo=169, routed) 6.237 4.004 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st[4]
|
|
SLICE_X157Y96 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/I0
|
|
SLICE_X157Y96 LUT5 (Prop_lut5_I0_O) 0.124 4.128 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/O
|
|
net (fo=936, routed) 21.592 25.720 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/sha3_mb_en0
|
|
SLICE_X45Y132 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[953]_i_1/I1
|
|
SLICE_X45Y132 LUT6 (Prop_lut6_I1_O) 0.124 25.844 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[953]_i_1/O
|
|
net (fo=1, routed) 0.000 25.844 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram_n_475
|
|
SLICE_X45Y132 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[953]/D
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock mlkem_clk_clk_pll rise edge)
|
|
40.000 40.000 r
|
|
clock source latency -5.674 34.326
|
|
propagated clock network latency
|
|
3.393 37.718
|
|
clock pessimism -0.507 37.211
|
|
clock uncertainty -0.077 37.135
|
|
SLICE_X45Y132 FDCE (Setup_fdce_C_D) 0.031 37.166 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[953]
|
|
-------------------------------------------------------------------
|
|
required time 37.166
|
|
arrival time -25.844
|
|
-------------------------------------------------------------------
|
|
slack 11.322
|
|
|
|
Slack (MET) : 11.322ns (required time - arrival time)
|
|
Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/C
|
|
(rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns})
|
|
Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[953]/D
|
|
(rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns})
|
|
Path Group: mlkem_clk_clk_pll
|
|
Path Type: Setup (Max at Slow Process Corner)
|
|
Requirement: 40.000ns (mlkem_clk_clk_pll rise@40.000ns - mlkem_clk_clk_pll rise@0.000ns)
|
|
Data Path Delay: 28.534ns (logic 0.704ns (2.467%) route 27.830ns (97.533%))
|
|
Logic Levels: 2 (LUT5=1 LUT6=1)
|
|
Clock Path Skew: -0.099ns (DCD - SCD + CPR)
|
|
Destination Clock Delay (DCD): -2.282ns = ( 37.718 - 40.000 )
|
|
Source Clock Delay (SCD): -2.690ns
|
|
Clock Pessimism Removal (CPR): -0.507ns
|
|
Clock Uncertainty: 0.077ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Discrete Jitter (DJ): 0.136ns
|
|
Phase Error (PE): 0.000ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock mlkem_clk_clk_pll rise edge)
|
|
0.000 0.000 r
|
|
clock source latency -6.275 -6.275
|
|
propagated clock network latency
|
|
3.586 -2.690
|
|
SLICE_X91Y121 FDCE 0.000 -2.690 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/C
|
|
SLICE_X91Y121 FDCE (Prop_fdce_C_Q) 0.456 -2.234 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/Q
|
|
net (fo=169, routed) 6.237 4.004 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st[4]
|
|
SLICE_X157Y96 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/I0
|
|
SLICE_X157Y96 LUT5 (Prop_lut5_I0_O) 0.124 4.128 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/O
|
|
net (fo=936, routed) 21.592 25.720 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/sha3_mb_en0
|
|
SLICE_X45Y132 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[953]_i_1/I1
|
|
SLICE_X45Y132 LUT6 (Prop_lut6_I1_O) 0.124 25.844 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[953]_i_1/O
|
|
net (fo=1, routed) 0.000 25.844 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram_n_475
|
|
SLICE_X45Y132 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[953]/D
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock mlkem_clk_clk_pll rise edge)
|
|
40.000 40.000 r
|
|
clock source latency -5.674 34.326
|
|
propagated clock network latency
|
|
3.393 37.718
|
|
clock pessimism -0.507 37.211
|
|
clock uncertainty -0.077 37.135
|
|
SLICE_X45Y132 FDCE (Setup_fdce_C_D) 0.031 37.166 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[953]
|
|
-------------------------------------------------------------------
|
|
required time 37.166
|
|
arrival time -25.844
|
|
-------------------------------------------------------------------
|
|
slack 11.322
|
|
|
|
Slack (MET) : 11.371ns (required time - arrival time)
|
|
Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[2]_rep/C
|
|
(rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns})
|
|
Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[829]/D
|
|
(rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns})
|
|
Path Group: mlkem_clk_clk_pll
|
|
Path Type: Setup (Max at Slow Process Corner)
|
|
Requirement: 40.000ns (mlkem_clk_clk_pll rise@40.000ns - mlkem_clk_clk_pll rise@0.000ns)
|
|
Data Path Delay: 28.467ns (logic 0.704ns (2.473%) route 27.763ns (97.527%))
|
|
Logic Levels: 2 (LUT5=1 LUT6=1)
|
|
Clock Path Skew: -0.117ns (DCD - SCD + CPR)
|
|
Destination Clock Delay (DCD): -2.279ns = ( 37.721 - 40.000 )
|
|
Source Clock Delay (SCD): -2.669ns
|
|
Clock Pessimism Removal (CPR): -0.507ns
|
|
Clock Uncertainty: 0.077ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Discrete Jitter (DJ): 0.136ns
|
|
Phase Error (PE): 0.000ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock mlkem_clk_clk_pll rise edge)
|
|
0.000 0.000 r
|
|
clock source latency -6.275 -6.275
|
|
propagated clock network latency
|
|
3.607 -2.669
|
|
SLICE_X107Y119 FDCE 0.000 -2.669 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[2]_rep/C
|
|
SLICE_X107Y119 FDCE (Prop_fdce_C_Q) 0.456 -2.213 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[2]_rep/Q
|
|
net (fo=109, routed) 5.879 3.667 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[2]_rep_n_0
|
|
SLICE_X157Y96 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/I3
|
|
SLICE_X157Y96 LUT5 (Prop_lut5_I3_O) 0.124 3.791 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/O
|
|
net (fo=936, routed) 21.883 25.674 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/sha3_mb_en0
|
|
SLICE_X45Y135 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[829]_i_1/I1
|
|
SLICE_X45Y135 LUT6 (Prop_lut6_I1_O) 0.124 25.798 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[829]_i_1/O
|
|
net (fo=1, routed) 0.000 25.798 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram_n_472
|
|
SLICE_X45Y135 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[829]/D
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock mlkem_clk_clk_pll rise edge)
|
|
40.000 40.000 r
|
|
clock source latency -5.674 34.326
|
|
propagated clock network latency
|
|
3.396 37.721
|
|
clock pessimism -0.507 37.214
|
|
clock uncertainty -0.077 37.138
|
|
SLICE_X45Y135 FDCE (Setup_fdce_C_D) 0.031 37.169 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[829]
|
|
-------------------------------------------------------------------
|
|
required time 37.169
|
|
arrival time -25.798
|
|
-------------------------------------------------------------------
|
|
slack 11.371
|
|
|
|
Slack (MET) : 11.371ns (required time - arrival time)
|
|
Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[2]_rep/C
|
|
(rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns})
|
|
Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[829]/D
|
|
(rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns})
|
|
Path Group: mlkem_clk_clk_pll
|
|
Path Type: Setup (Max at Slow Process Corner)
|
|
Requirement: 40.000ns (mlkem_clk_clk_pll rise@40.000ns - mlkem_clk_clk_pll rise@0.000ns)
|
|
Data Path Delay: 28.467ns (logic 0.704ns (2.473%) route 27.763ns (97.527%))
|
|
Logic Levels: 2 (LUT5=1 LUT6=1)
|
|
Clock Path Skew: -0.117ns (DCD - SCD + CPR)
|
|
Destination Clock Delay (DCD): -2.279ns = ( 37.721 - 40.000 )
|
|
Source Clock Delay (SCD): -2.669ns
|
|
Clock Pessimism Removal (CPR): -0.507ns
|
|
Clock Uncertainty: 0.077ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Discrete Jitter (DJ): 0.136ns
|
|
Phase Error (PE): 0.000ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock mlkem_clk_clk_pll rise edge)
|
|
0.000 0.000 r
|
|
clock source latency -6.275 -6.275
|
|
propagated clock network latency
|
|
3.607 -2.669
|
|
SLICE_X107Y119 FDCE 0.000 -2.669 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[2]_rep/C
|
|
SLICE_X107Y119 FDCE (Prop_fdce_C_Q) 0.456 -2.213 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[2]_rep/Q
|
|
net (fo=109, routed) 5.879 3.667 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[2]_rep_n_0
|
|
SLICE_X157Y96 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/I3
|
|
SLICE_X157Y96 LUT5 (Prop_lut5_I3_O) 0.124 3.791 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/O
|
|
net (fo=936, routed) 21.883 25.674 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/sha3_mb_en0
|
|
SLICE_X45Y135 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[829]_i_1/I1
|
|
SLICE_X45Y135 LUT6 (Prop_lut6_I1_O) 0.124 25.798 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[829]_i_1/O
|
|
net (fo=1, routed) 0.000 25.798 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram_n_472
|
|
SLICE_X45Y135 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[829]/D
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock mlkem_clk_clk_pll rise edge)
|
|
40.000 40.000 r
|
|
clock source latency -5.674 34.326
|
|
propagated clock network latency
|
|
3.396 37.721
|
|
clock pessimism -0.507 37.214
|
|
clock uncertainty -0.077 37.138
|
|
SLICE_X45Y135 FDCE (Setup_fdce_C_D) 0.031 37.169 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[829]
|
|
-------------------------------------------------------------------
|
|
required time 37.169
|
|
arrival time -25.798
|
|
-------------------------------------------------------------------
|
|
slack 11.371
|
|
|
|
Slack (MET) : 11.371ns (required time - arrival time)
|
|
Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[2]_rep/C
|
|
(rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns})
|
|
Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[829]/D
|
|
(rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns})
|
|
Path Group: mlkem_clk_clk_pll
|
|
Path Type: Setup (Max at Slow Process Corner)
|
|
Requirement: 40.000ns (mlkem_clk_clk_pll rise@40.000ns - mlkem_clk_clk_pll rise@0.000ns)
|
|
Data Path Delay: 28.467ns (logic 0.704ns (2.473%) route 27.763ns (97.527%))
|
|
Logic Levels: 2 (LUT5=1 LUT6=1)
|
|
Clock Path Skew: -0.117ns (DCD - SCD + CPR)
|
|
Destination Clock Delay (DCD): -2.279ns = ( 37.721 - 40.000 )
|
|
Source Clock Delay (SCD): -2.669ns
|
|
Clock Pessimism Removal (CPR): -0.507ns
|
|
Clock Uncertainty: 0.077ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Discrete Jitter (DJ): 0.136ns
|
|
Phase Error (PE): 0.000ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock mlkem_clk_clk_pll rise edge)
|
|
0.000 0.000 r
|
|
clock source latency -6.275 -6.275
|
|
propagated clock network latency
|
|
3.607 -2.669
|
|
SLICE_X107Y119 FDCE 0.000 -2.669 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[2]_rep/C
|
|
SLICE_X107Y119 FDCE (Prop_fdce_C_Q) 0.456 -2.213 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[2]_rep/Q
|
|
net (fo=109, routed) 5.879 3.667 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[2]_rep_n_0
|
|
SLICE_X157Y96 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/I3
|
|
SLICE_X157Y96 LUT5 (Prop_lut5_I3_O) 0.124 3.791 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/O
|
|
net (fo=936, routed) 21.883 25.674 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/sha3_mb_en0
|
|
SLICE_X45Y135 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[829]_i_1/I1
|
|
SLICE_X45Y135 LUT6 (Prop_lut6_I1_O) 0.124 25.798 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[829]_i_1/O
|
|
net (fo=1, routed) 0.000 25.798 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram_n_472
|
|
SLICE_X45Y135 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[829]/D
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock mlkem_clk_clk_pll rise edge)
|
|
40.000 40.000 r
|
|
clock source latency -5.674 34.326
|
|
propagated clock network latency
|
|
3.396 37.721
|
|
clock pessimism -0.507 37.214
|
|
clock uncertainty -0.077 37.138
|
|
SLICE_X45Y135 FDCE (Setup_fdce_C_D) 0.031 37.169 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[829]
|
|
-------------------------------------------------------------------
|
|
required time 37.169
|
|
arrival time -25.798
|
|
-------------------------------------------------------------------
|
|
slack 11.371
|
|
|
|
Slack (MET) : 11.371ns (required time - arrival time)
|
|
Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[2]_rep/C
|
|
(rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns})
|
|
Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[829]/D
|
|
(rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns})
|
|
Path Group: mlkem_clk_clk_pll
|
|
Path Type: Setup (Max at Slow Process Corner)
|
|
Requirement: 40.000ns (mlkem_clk_clk_pll rise@40.000ns - mlkem_clk_clk_pll rise@0.000ns)
|
|
Data Path Delay: 28.467ns (logic 0.704ns (2.473%) route 27.763ns (97.527%))
|
|
Logic Levels: 2 (LUT5=1 LUT6=1)
|
|
Clock Path Skew: -0.117ns (DCD - SCD + CPR)
|
|
Destination Clock Delay (DCD): -2.279ns = ( 37.721 - 40.000 )
|
|
Source Clock Delay (SCD): -2.669ns
|
|
Clock Pessimism Removal (CPR): -0.507ns
|
|
Clock Uncertainty: 0.077ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Discrete Jitter (DJ): 0.136ns
|
|
Phase Error (PE): 0.000ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock mlkem_clk_clk_pll rise edge)
|
|
0.000 0.000 r
|
|
clock source latency -6.275 -6.275
|
|
propagated clock network latency
|
|
3.607 -2.669
|
|
SLICE_X107Y119 FDCE 0.000 -2.669 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[2]_rep/C
|
|
SLICE_X107Y119 FDCE (Prop_fdce_C_Q) 0.456 -2.213 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[2]_rep/Q
|
|
net (fo=109, routed) 5.879 3.667 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[2]_rep_n_0
|
|
SLICE_X157Y96 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/I3
|
|
SLICE_X157Y96 LUT5 (Prop_lut5_I3_O) 0.124 3.791 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/O
|
|
net (fo=936, routed) 21.883 25.674 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/sha3_mb_en0
|
|
SLICE_X45Y135 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[829]_i_1/I1
|
|
SLICE_X45Y135 LUT6 (Prop_lut6_I1_O) 0.124 25.798 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[829]_i_1/O
|
|
net (fo=1, routed) 0.000 25.798 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram_n_472
|
|
SLICE_X45Y135 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[829]/D
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock mlkem_clk_clk_pll rise edge)
|
|
40.000 40.000 r
|
|
clock source latency -5.674 34.326
|
|
propagated clock network latency
|
|
3.396 37.721
|
|
clock pessimism -0.507 37.214
|
|
clock uncertainty -0.077 37.138
|
|
SLICE_X45Y135 FDCE (Setup_fdce_C_D) 0.031 37.169 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[829]
|
|
-------------------------------------------------------------------
|
|
required time 37.169
|
|
arrival time -25.798
|
|
-------------------------------------------------------------------
|
|
slack 11.371
|
|
|
|
Slack (MET) : 11.371ns (required time - arrival time)
|
|
Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[2]_rep/C
|
|
(rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns})
|
|
Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[829]/D
|
|
(rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns})
|
|
Path Group: mlkem_clk_clk_pll
|
|
Path Type: Setup (Max at Slow Process Corner)
|
|
Requirement: 40.000ns (mlkem_clk_clk_pll rise@40.000ns - mlkem_clk_clk_pll rise@0.000ns)
|
|
Data Path Delay: 28.467ns (logic 0.704ns (2.473%) route 27.763ns (97.527%))
|
|
Logic Levels: 2 (LUT5=1 LUT6=1)
|
|
Clock Path Skew: -0.117ns (DCD - SCD + CPR)
|
|
Destination Clock Delay (DCD): -2.279ns = ( 37.721 - 40.000 )
|
|
Source Clock Delay (SCD): -2.669ns
|
|
Clock Pessimism Removal (CPR): -0.507ns
|
|
Clock Uncertainty: 0.077ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Discrete Jitter (DJ): 0.136ns
|
|
Phase Error (PE): 0.000ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock mlkem_clk_clk_pll rise edge)
|
|
0.000 0.000 r
|
|
clock source latency -6.275 -6.275
|
|
propagated clock network latency
|
|
3.607 -2.669
|
|
SLICE_X107Y119 FDCE 0.000 -2.669 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[2]_rep/C
|
|
SLICE_X107Y119 FDCE (Prop_fdce_C_Q) 0.456 -2.213 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[2]_rep/Q
|
|
net (fo=109, routed) 5.879 3.667 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[2]_rep_n_0
|
|
SLICE_X157Y96 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/I3
|
|
SLICE_X157Y96 LUT5 (Prop_lut5_I3_O) 0.124 3.791 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/O
|
|
net (fo=936, routed) 21.883 25.674 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/sha3_mb_en0
|
|
SLICE_X45Y135 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[829]_i_1/I1
|
|
SLICE_X45Y135 LUT6 (Prop_lut6_I1_O) 0.124 25.798 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[829]_i_1/O
|
|
net (fo=1, routed) 0.000 25.798 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram_n_472
|
|
SLICE_X45Y135 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[829]/D
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock mlkem_clk_clk_pll rise edge)
|
|
40.000 40.000 r
|
|
clock source latency -5.674 34.326
|
|
propagated clock network latency
|
|
3.396 37.721
|
|
clock pessimism -0.507 37.214
|
|
clock uncertainty -0.077 37.138
|
|
SLICE_X45Y135 FDCE (Setup_fdce_C_D) 0.031 37.169 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[829]
|
|
-------------------------------------------------------------------
|
|
required time 37.169
|
|
arrival time -25.798
|
|
-------------------------------------------------------------------
|
|
slack 11.371
|
|
|
|
Slack (MET) : 11.371ns (required time - arrival time)
|
|
Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[2]_rep/C
|
|
(rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns})
|
|
Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[829]/D
|
|
(rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns})
|
|
Path Group: mlkem_clk_clk_pll
|
|
Path Type: Setup (Max at Slow Process Corner)
|
|
Requirement: 40.000ns (mlkem_clk_clk_pll rise@40.000ns - mlkem_clk_clk_pll rise@0.000ns)
|
|
Data Path Delay: 28.467ns (logic 0.704ns (2.473%) route 27.763ns (97.527%))
|
|
Logic Levels: 2 (LUT5=1 LUT6=1)
|
|
Clock Path Skew: -0.117ns (DCD - SCD + CPR)
|
|
Destination Clock Delay (DCD): -2.279ns = ( 37.721 - 40.000 )
|
|
Source Clock Delay (SCD): -2.669ns
|
|
Clock Pessimism Removal (CPR): -0.507ns
|
|
Clock Uncertainty: 0.077ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Discrete Jitter (DJ): 0.136ns
|
|
Phase Error (PE): 0.000ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock mlkem_clk_clk_pll rise edge)
|
|
0.000 0.000 r
|
|
clock source latency -6.275 -6.275
|
|
propagated clock network latency
|
|
3.607 -2.669
|
|
SLICE_X107Y119 FDCE 0.000 -2.669 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[2]_rep/C
|
|
SLICE_X107Y119 FDCE (Prop_fdce_C_Q) 0.456 -2.213 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[2]_rep/Q
|
|
net (fo=109, routed) 5.879 3.667 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[2]_rep_n_0
|
|
SLICE_X157Y96 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/I3
|
|
SLICE_X157Y96 LUT5 (Prop_lut5_I3_O) 0.124 3.791 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/O
|
|
net (fo=936, routed) 21.883 25.674 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/sha3_mb_en0
|
|
SLICE_X45Y135 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[829]_i_1/I1
|
|
SLICE_X45Y135 LUT6 (Prop_lut6_I1_O) 0.124 25.798 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[829]_i_1/O
|
|
net (fo=1, routed) 0.000 25.798 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram_n_472
|
|
SLICE_X45Y135 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[829]/D
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock mlkem_clk_clk_pll rise edge)
|
|
40.000 40.000 r
|
|
clock source latency -5.674 34.326
|
|
propagated clock network latency
|
|
3.396 37.721
|
|
clock pessimism -0.507 37.214
|
|
clock uncertainty -0.077 37.138
|
|
SLICE_X45Y135 FDCE (Setup_fdce_C_D) 0.031 37.169 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[829]
|
|
-------------------------------------------------------------------
|
|
required time 37.169
|
|
arrival time -25.798
|
|
-------------------------------------------------------------------
|
|
slack 11.371
|
|
|
|
Slack (MET) : 11.396ns (required time - arrival time)
|
|
Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[2]_rep/C
|
|
(rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns})
|
|
Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[777]/D
|
|
(rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns})
|
|
Path Group: mlkem_clk_clk_pll
|
|
Path Type: Setup (Max at Slow Process Corner)
|
|
Requirement: 40.000ns (mlkem_clk_clk_pll rise@40.000ns - mlkem_clk_clk_pll rise@0.000ns)
|
|
Data Path Delay: 28.488ns (logic 0.704ns (2.471%) route 27.784ns (97.529%))
|
|
Logic Levels: 2 (LUT5=1 LUT6=1)
|
|
Clock Path Skew: -0.117ns (DCD - SCD + CPR)
|
|
Destination Clock Delay (DCD): -2.279ns = ( 37.721 - 40.000 )
|
|
Source Clock Delay (SCD): -2.669ns
|
|
Clock Pessimism Removal (CPR): -0.507ns
|
|
Clock Uncertainty: 0.077ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Discrete Jitter (DJ): 0.136ns
|
|
Phase Error (PE): 0.000ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock mlkem_clk_clk_pll rise edge)
|
|
0.000 0.000 r
|
|
clock source latency -6.275 -6.275
|
|
propagated clock network latency
|
|
3.607 -2.669
|
|
SLICE_X107Y119 FDCE 0.000 -2.669 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[2]_rep/C
|
|
SLICE_X107Y119 FDCE (Prop_fdce_C_Q) 0.456 -2.213 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[2]_rep/Q
|
|
net (fo=109, routed) 5.879 3.667 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[2]_rep_n_0
|
|
SLICE_X157Y96 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/I3
|
|
SLICE_X157Y96 LUT5 (Prop_lut5_I3_O) 0.124 3.791 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/O
|
|
net (fo=936, routed) 21.904 25.695 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/sha3_mb_en0
|
|
SLICE_X44Y135 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[777]_i_1/I1
|
|
SLICE_X44Y135 LUT6 (Prop_lut6_I1_O) 0.124 25.819 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[777]_i_1/O
|
|
net (fo=1, routed) 0.000 25.819 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram_n_909
|
|
SLICE_X44Y135 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[777]/D
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock mlkem_clk_clk_pll rise edge)
|
|
40.000 40.000 r
|
|
clock source latency -5.674 34.326
|
|
propagated clock network latency
|
|
3.396 37.721
|
|
clock pessimism -0.507 37.214
|
|
clock uncertainty -0.077 37.138
|
|
SLICE_X44Y135 FDCE (Setup_fdce_C_D) 0.077 37.215 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[777]
|
|
-------------------------------------------------------------------
|
|
required time 37.215
|
|
arrival time -25.819
|
|
-------------------------------------------------------------------
|
|
slack 11.396
|
|
|
|
Slack (MET) : 11.396ns (required time - arrival time)
|
|
Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[2]_rep/C
|
|
(rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns})
|
|
Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[777]/D
|
|
(rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns})
|
|
Path Group: mlkem_clk_clk_pll
|
|
Path Type: Setup (Max at Slow Process Corner)
|
|
Requirement: 40.000ns (mlkem_clk_clk_pll rise@40.000ns - mlkem_clk_clk_pll rise@0.000ns)
|
|
Data Path Delay: 28.488ns (logic 0.704ns (2.471%) route 27.784ns (97.529%))
|
|
Logic Levels: 2 (LUT5=1 LUT6=1)
|
|
Clock Path Skew: -0.117ns (DCD - SCD + CPR)
|
|
Destination Clock Delay (DCD): -2.279ns = ( 37.721 - 40.000 )
|
|
Source Clock Delay (SCD): -2.669ns
|
|
Clock Pessimism Removal (CPR): -0.507ns
|
|
Clock Uncertainty: 0.077ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Discrete Jitter (DJ): 0.136ns
|
|
Phase Error (PE): 0.000ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock mlkem_clk_clk_pll rise edge)
|
|
0.000 0.000 r
|
|
clock source latency -6.275 -6.275
|
|
propagated clock network latency
|
|
3.607 -2.669
|
|
SLICE_X107Y119 FDCE 0.000 -2.669 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[2]_rep/C
|
|
SLICE_X107Y119 FDCE (Prop_fdce_C_Q) 0.456 -2.213 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[2]_rep/Q
|
|
net (fo=109, routed) 5.879 3.667 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[2]_rep_n_0
|
|
SLICE_X157Y96 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/I3
|
|
SLICE_X157Y96 LUT5 (Prop_lut5_I3_O) 0.124 3.791 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/O
|
|
net (fo=936, routed) 21.904 25.695 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/sha3_mb_en0
|
|
SLICE_X44Y135 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[777]_i_1/I1
|
|
SLICE_X44Y135 LUT6 (Prop_lut6_I1_O) 0.124 25.819 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[777]_i_1/O
|
|
net (fo=1, routed) 0.000 25.819 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram_n_909
|
|
SLICE_X44Y135 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[777]/D
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock mlkem_clk_clk_pll rise edge)
|
|
40.000 40.000 r
|
|
clock source latency -5.674 34.326
|
|
propagated clock network latency
|
|
3.396 37.721
|
|
clock pessimism -0.507 37.214
|
|
clock uncertainty -0.077 37.138
|
|
SLICE_X44Y135 FDCE (Setup_fdce_C_D) 0.077 37.215 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[777]
|
|
-------------------------------------------------------------------
|
|
required time 37.215
|
|
arrival time -25.819
|
|
-------------------------------------------------------------------
|
|
slack 11.396
|
|
|
|
Slack (MET) : 11.396ns (required time - arrival time)
|
|
Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[2]_rep/C
|
|
(rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns})
|
|
Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[777]/D
|
|
(rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns})
|
|
Path Group: mlkem_clk_clk_pll
|
|
Path Type: Setup (Max at Slow Process Corner)
|
|
Requirement: 40.000ns (mlkem_clk_clk_pll rise@40.000ns - mlkem_clk_clk_pll rise@0.000ns)
|
|
Data Path Delay: 28.488ns (logic 0.704ns (2.471%) route 27.784ns (97.529%))
|
|
Logic Levels: 2 (LUT5=1 LUT6=1)
|
|
Clock Path Skew: -0.117ns (DCD - SCD + CPR)
|
|
Destination Clock Delay (DCD): -2.279ns = ( 37.721 - 40.000 )
|
|
Source Clock Delay (SCD): -2.669ns
|
|
Clock Pessimism Removal (CPR): -0.507ns
|
|
Clock Uncertainty: 0.077ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Discrete Jitter (DJ): 0.136ns
|
|
Phase Error (PE): 0.000ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock mlkem_clk_clk_pll rise edge)
|
|
0.000 0.000 r
|
|
clock source latency -6.275 -6.275
|
|
propagated clock network latency
|
|
3.607 -2.669
|
|
SLICE_X107Y119 FDCE 0.000 -2.669 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[2]_rep/C
|
|
SLICE_X107Y119 FDCE (Prop_fdce_C_Q) 0.456 -2.213 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[2]_rep/Q
|
|
net (fo=109, routed) 5.879 3.667 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[2]_rep_n_0
|
|
SLICE_X157Y96 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/I3
|
|
SLICE_X157Y96 LUT5 (Prop_lut5_I3_O) 0.124 3.791 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/O
|
|
net (fo=936, routed) 21.904 25.695 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/sha3_mb_en0
|
|
SLICE_X44Y135 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[777]_i_1/I1
|
|
SLICE_X44Y135 LUT6 (Prop_lut6_I1_O) 0.124 25.819 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[777]_i_1/O
|
|
net (fo=1, routed) 0.000 25.819 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram_n_909
|
|
SLICE_X44Y135 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[777]/D
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock mlkem_clk_clk_pll rise edge)
|
|
40.000 40.000 r
|
|
clock source latency -5.674 34.326
|
|
propagated clock network latency
|
|
3.396 37.721
|
|
clock pessimism -0.507 37.214
|
|
clock uncertainty -0.077 37.138
|
|
SLICE_X44Y135 FDCE (Setup_fdce_C_D) 0.077 37.215 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[777]
|
|
-------------------------------------------------------------------
|
|
required time 37.215
|
|
arrival time -25.819
|
|
-------------------------------------------------------------------
|
|
slack 11.396
|
|
|
|
Slack (MET) : 11.396ns (required time - arrival time)
|
|
Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[2]_rep/C
|
|
(rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns})
|
|
Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[777]/D
|
|
(rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns})
|
|
Path Group: mlkem_clk_clk_pll
|
|
Path Type: Setup (Max at Slow Process Corner)
|
|
Requirement: 40.000ns (mlkem_clk_clk_pll rise@40.000ns - mlkem_clk_clk_pll rise@0.000ns)
|
|
Data Path Delay: 28.488ns (logic 0.704ns (2.471%) route 27.784ns (97.529%))
|
|
Logic Levels: 2 (LUT5=1 LUT6=1)
|
|
Clock Path Skew: -0.117ns (DCD - SCD + CPR)
|
|
Destination Clock Delay (DCD): -2.279ns = ( 37.721 - 40.000 )
|
|
Source Clock Delay (SCD): -2.669ns
|
|
Clock Pessimism Removal (CPR): -0.507ns
|
|
Clock Uncertainty: 0.077ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Discrete Jitter (DJ): 0.136ns
|
|
Phase Error (PE): 0.000ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock mlkem_clk_clk_pll rise edge)
|
|
0.000 0.000 r
|
|
clock source latency -6.275 -6.275
|
|
propagated clock network latency
|
|
3.607 -2.669
|
|
SLICE_X107Y119 FDCE 0.000 -2.669 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[2]_rep/C
|
|
SLICE_X107Y119 FDCE (Prop_fdce_C_Q) 0.456 -2.213 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[2]_rep/Q
|
|
net (fo=109, routed) 5.879 3.667 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[2]_rep_n_0
|
|
SLICE_X157Y96 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/I3
|
|
SLICE_X157Y96 LUT5 (Prop_lut5_I3_O) 0.124 3.791 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/O
|
|
net (fo=936, routed) 21.904 25.695 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/sha3_mb_en0
|
|
SLICE_X44Y135 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[777]_i_1/I1
|
|
SLICE_X44Y135 LUT6 (Prop_lut6_I1_O) 0.124 25.819 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[777]_i_1/O
|
|
net (fo=1, routed) 0.000 25.819 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram_n_909
|
|
SLICE_X44Y135 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[777]/D
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock mlkem_clk_clk_pll rise edge)
|
|
40.000 40.000 r
|
|
clock source latency -5.674 34.326
|
|
propagated clock network latency
|
|
3.396 37.721
|
|
clock pessimism -0.507 37.214
|
|
clock uncertainty -0.077 37.138
|
|
SLICE_X44Y135 FDCE (Setup_fdce_C_D) 0.077 37.215 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[777]
|
|
-------------------------------------------------------------------
|
|
required time 37.215
|
|
arrival time -25.819
|
|
-------------------------------------------------------------------
|
|
slack 11.396
|
|
|
|
Slack (MET) : 11.396ns (required time - arrival time)
|
|
Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[2]_rep/C
|
|
(rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns})
|
|
Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[777]/D
|
|
(rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns})
|
|
Path Group: mlkem_clk_clk_pll
|
|
Path Type: Setup (Max at Slow Process Corner)
|
|
Requirement: 40.000ns (mlkem_clk_clk_pll rise@40.000ns - mlkem_clk_clk_pll rise@0.000ns)
|
|
Data Path Delay: 28.488ns (logic 0.704ns (2.471%) route 27.784ns (97.529%))
|
|
Logic Levels: 2 (LUT5=1 LUT6=1)
|
|
Clock Path Skew: -0.117ns (DCD - SCD + CPR)
|
|
Destination Clock Delay (DCD): -2.279ns = ( 37.721 - 40.000 )
|
|
Source Clock Delay (SCD): -2.669ns
|
|
Clock Pessimism Removal (CPR): -0.507ns
|
|
Clock Uncertainty: 0.077ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Discrete Jitter (DJ): 0.136ns
|
|
Phase Error (PE): 0.000ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock mlkem_clk_clk_pll rise edge)
|
|
0.000 0.000 r
|
|
clock source latency -6.275 -6.275
|
|
propagated clock network latency
|
|
3.607 -2.669
|
|
SLICE_X107Y119 FDCE 0.000 -2.669 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[2]_rep/C
|
|
SLICE_X107Y119 FDCE (Prop_fdce_C_Q) 0.456 -2.213 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[2]_rep/Q
|
|
net (fo=109, routed) 5.879 3.667 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[2]_rep_n_0
|
|
SLICE_X157Y96 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/I3
|
|
SLICE_X157Y96 LUT5 (Prop_lut5_I3_O) 0.124 3.791 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/O
|
|
net (fo=936, routed) 21.904 25.695 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/sha3_mb_en0
|
|
SLICE_X44Y135 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[777]_i_1/I1
|
|
SLICE_X44Y135 LUT6 (Prop_lut6_I1_O) 0.124 25.819 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[777]_i_1/O
|
|
net (fo=1, routed) 0.000 25.819 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram_n_909
|
|
SLICE_X44Y135 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[777]/D
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock mlkem_clk_clk_pll rise edge)
|
|
40.000 40.000 r
|
|
clock source latency -5.674 34.326
|
|
propagated clock network latency
|
|
3.396 37.721
|
|
clock pessimism -0.507 37.214
|
|
clock uncertainty -0.077 37.138
|
|
SLICE_X44Y135 FDCE (Setup_fdce_C_D) 0.077 37.215 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[777]
|
|
-------------------------------------------------------------------
|
|
required time 37.215
|
|
arrival time -25.819
|
|
-------------------------------------------------------------------
|
|
slack 11.396
|
|
|
|
Slack (MET) : 11.396ns (required time - arrival time)
|
|
Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[2]_rep/C
|
|
(rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns})
|
|
Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[777]/D
|
|
(rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns})
|
|
Path Group: mlkem_clk_clk_pll
|
|
Path Type: Setup (Max at Slow Process Corner)
|
|
Requirement: 40.000ns (mlkem_clk_clk_pll rise@40.000ns - mlkem_clk_clk_pll rise@0.000ns)
|
|
Data Path Delay: 28.488ns (logic 0.704ns (2.471%) route 27.784ns (97.529%))
|
|
Logic Levels: 2 (LUT5=1 LUT6=1)
|
|
Clock Path Skew: -0.117ns (DCD - SCD + CPR)
|
|
Destination Clock Delay (DCD): -2.279ns = ( 37.721 - 40.000 )
|
|
Source Clock Delay (SCD): -2.669ns
|
|
Clock Pessimism Removal (CPR): -0.507ns
|
|
Clock Uncertainty: 0.077ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Discrete Jitter (DJ): 0.136ns
|
|
Phase Error (PE): 0.000ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock mlkem_clk_clk_pll rise edge)
|
|
0.000 0.000 r
|
|
clock source latency -6.275 -6.275
|
|
propagated clock network latency
|
|
3.607 -2.669
|
|
SLICE_X107Y119 FDCE 0.000 -2.669 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[2]_rep/C
|
|
SLICE_X107Y119 FDCE (Prop_fdce_C_Q) 0.456 -2.213 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[2]_rep/Q
|
|
net (fo=109, routed) 5.879 3.667 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[2]_rep_n_0
|
|
SLICE_X157Y96 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/I3
|
|
SLICE_X157Y96 LUT5 (Prop_lut5_I3_O) 0.124 3.791 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/O
|
|
net (fo=936, routed) 21.904 25.695 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/sha3_mb_en0
|
|
SLICE_X44Y135 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[777]_i_1/I1
|
|
SLICE_X44Y135 LUT6 (Prop_lut6_I1_O) 0.124 25.819 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[777]_i_1/O
|
|
net (fo=1, routed) 0.000 25.819 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram_n_909
|
|
SLICE_X44Y135 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[777]/D
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock mlkem_clk_clk_pll rise edge)
|
|
40.000 40.000 r
|
|
clock source latency -5.674 34.326
|
|
propagated clock network latency
|
|
3.396 37.721
|
|
clock pessimism -0.507 37.214
|
|
clock uncertainty -0.077 37.138
|
|
SLICE_X44Y135 FDCE (Setup_fdce_C_D) 0.077 37.215 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[777]
|
|
-------------------------------------------------------------------
|
|
required time 37.215
|
|
arrival time -25.819
|
|
-------------------------------------------------------------------
|
|
slack 11.396
|
|
|
|
Slack (MET) : 11.403ns (required time - arrival time)
|
|
Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[2]_rep/C
|
|
(rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns})
|
|
Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[969]/D
|
|
(rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns})
|
|
Path Group: mlkem_clk_clk_pll
|
|
Path Type: Setup (Max at Slow Process Corner)
|
|
Requirement: 40.000ns (mlkem_clk_clk_pll rise@40.000ns - mlkem_clk_clk_pll rise@0.000ns)
|
|
Data Path Delay: 28.485ns (logic 0.704ns (2.472%) route 27.781ns (97.528%))
|
|
Logic Levels: 2 (LUT5=1 LUT6=1)
|
|
Clock Path Skew: -0.117ns (DCD - SCD + CPR)
|
|
Destination Clock Delay (DCD): -2.279ns = ( 37.721 - 40.000 )
|
|
Source Clock Delay (SCD): -2.669ns
|
|
Clock Pessimism Removal (CPR): -0.507ns
|
|
Clock Uncertainty: 0.077ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Discrete Jitter (DJ): 0.136ns
|
|
Phase Error (PE): 0.000ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock mlkem_clk_clk_pll rise edge)
|
|
0.000 0.000 r
|
|
clock source latency -6.275 -6.275
|
|
propagated clock network latency
|
|
3.607 -2.669
|
|
SLICE_X107Y119 FDCE 0.000 -2.669 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[2]_rep/C
|
|
SLICE_X107Y119 FDCE (Prop_fdce_C_Q) 0.456 -2.213 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[2]_rep/Q
|
|
net (fo=109, routed) 5.879 3.667 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[2]_rep_n_0
|
|
SLICE_X157Y96 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/I3
|
|
SLICE_X157Y96 LUT5 (Prop_lut5_I3_O) 0.124 3.791 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/O
|
|
net (fo=936, routed) 21.901 25.692 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/sha3_mb_en0
|
|
SLICE_X44Y135 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[969]_i_1/I1
|
|
SLICE_X44Y135 LUT6 (Prop_lut6_I1_O) 0.124 25.816 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[969]_i_1/O
|
|
net (fo=1, routed) 0.000 25.816 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram_n_1143
|
|
SLICE_X44Y135 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[969]/D
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock mlkem_clk_clk_pll rise edge)
|
|
40.000 40.000 r
|
|
clock source latency -5.674 34.326
|
|
propagated clock network latency
|
|
3.396 37.721
|
|
clock pessimism -0.507 37.214
|
|
clock uncertainty -0.077 37.138
|
|
SLICE_X44Y135 FDCE (Setup_fdce_C_D) 0.081 37.219 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[969]
|
|
-------------------------------------------------------------------
|
|
required time 37.219
|
|
arrival time -25.816
|
|
-------------------------------------------------------------------
|
|
slack 11.403
|
|
|
|
Slack (MET) : 11.403ns (required time - arrival time)
|
|
Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[2]_rep/C
|
|
(rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns})
|
|
Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[969]/D
|
|
(rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns})
|
|
Path Group: mlkem_clk_clk_pll
|
|
Path Type: Setup (Max at Slow Process Corner)
|
|
Requirement: 40.000ns (mlkem_clk_clk_pll rise@40.000ns - mlkem_clk_clk_pll rise@0.000ns)
|
|
Data Path Delay: 28.485ns (logic 0.704ns (2.472%) route 27.781ns (97.528%))
|
|
Logic Levels: 2 (LUT5=1 LUT6=1)
|
|
Clock Path Skew: -0.117ns (DCD - SCD + CPR)
|
|
Destination Clock Delay (DCD): -2.279ns = ( 37.721 - 40.000 )
|
|
Source Clock Delay (SCD): -2.669ns
|
|
Clock Pessimism Removal (CPR): -0.507ns
|
|
Clock Uncertainty: 0.077ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Discrete Jitter (DJ): 0.136ns
|
|
Phase Error (PE): 0.000ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock mlkem_clk_clk_pll rise edge)
|
|
0.000 0.000 r
|
|
clock source latency -6.275 -6.275
|
|
propagated clock network latency
|
|
3.607 -2.669
|
|
SLICE_X107Y119 FDCE 0.000 -2.669 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[2]_rep/C
|
|
SLICE_X107Y119 FDCE (Prop_fdce_C_Q) 0.456 -2.213 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[2]_rep/Q
|
|
net (fo=109, routed) 5.879 3.667 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[2]_rep_n_0
|
|
SLICE_X157Y96 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/I3
|
|
SLICE_X157Y96 LUT5 (Prop_lut5_I3_O) 0.124 3.791 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/O
|
|
net (fo=936, routed) 21.901 25.692 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/sha3_mb_en0
|
|
SLICE_X44Y135 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[969]_i_1/I1
|
|
SLICE_X44Y135 LUT6 (Prop_lut6_I1_O) 0.124 25.816 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[969]_i_1/O
|
|
net (fo=1, routed) 0.000 25.816 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram_n_1143
|
|
SLICE_X44Y135 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[969]/D
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock mlkem_clk_clk_pll rise edge)
|
|
40.000 40.000 r
|
|
clock source latency -5.674 34.326
|
|
propagated clock network latency
|
|
3.396 37.721
|
|
clock pessimism -0.507 37.214
|
|
clock uncertainty -0.077 37.138
|
|
SLICE_X44Y135 FDCE (Setup_fdce_C_D) 0.081 37.219 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[969]
|
|
-------------------------------------------------------------------
|
|
required time 37.219
|
|
arrival time -25.816
|
|
-------------------------------------------------------------------
|
|
slack 11.403
|
|
|
|
Slack (MET) : 11.403ns (required time - arrival time)
|
|
Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[2]_rep/C
|
|
(rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns})
|
|
Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[969]/D
|
|
(rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns})
|
|
Path Group: mlkem_clk_clk_pll
|
|
Path Type: Setup (Max at Slow Process Corner)
|
|
Requirement: 40.000ns (mlkem_clk_clk_pll rise@40.000ns - mlkem_clk_clk_pll rise@0.000ns)
|
|
Data Path Delay: 28.485ns (logic 0.704ns (2.472%) route 27.781ns (97.528%))
|
|
Logic Levels: 2 (LUT5=1 LUT6=1)
|
|
Clock Path Skew: -0.117ns (DCD - SCD + CPR)
|
|
Destination Clock Delay (DCD): -2.279ns = ( 37.721 - 40.000 )
|
|
Source Clock Delay (SCD): -2.669ns
|
|
Clock Pessimism Removal (CPR): -0.507ns
|
|
Clock Uncertainty: 0.077ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Discrete Jitter (DJ): 0.136ns
|
|
Phase Error (PE): 0.000ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock mlkem_clk_clk_pll rise edge)
|
|
0.000 0.000 r
|
|
clock source latency -6.275 -6.275
|
|
propagated clock network latency
|
|
3.607 -2.669
|
|
SLICE_X107Y119 FDCE 0.000 -2.669 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[2]_rep/C
|
|
SLICE_X107Y119 FDCE (Prop_fdce_C_Q) 0.456 -2.213 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[2]_rep/Q
|
|
net (fo=109, routed) 5.879 3.667 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[2]_rep_n_0
|
|
SLICE_X157Y96 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/I3
|
|
SLICE_X157Y96 LUT5 (Prop_lut5_I3_O) 0.124 3.791 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/O
|
|
net (fo=936, routed) 21.901 25.692 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/sha3_mb_en0
|
|
SLICE_X44Y135 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[969]_i_1/I1
|
|
SLICE_X44Y135 LUT6 (Prop_lut6_I1_O) 0.124 25.816 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[969]_i_1/O
|
|
net (fo=1, routed) 0.000 25.816 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram_n_1143
|
|
SLICE_X44Y135 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[969]/D
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock mlkem_clk_clk_pll rise edge)
|
|
40.000 40.000 r
|
|
clock source latency -5.674 34.326
|
|
propagated clock network latency
|
|
3.396 37.721
|
|
clock pessimism -0.507 37.214
|
|
clock uncertainty -0.077 37.138
|
|
SLICE_X44Y135 FDCE (Setup_fdce_C_D) 0.081 37.219 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[969]
|
|
-------------------------------------------------------------------
|
|
required time 37.219
|
|
arrival time -25.816
|
|
-------------------------------------------------------------------
|
|
slack 11.403
|
|
|
|
Slack (MET) : 11.403ns (required time - arrival time)
|
|
Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[2]_rep/C
|
|
(rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns})
|
|
Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[969]/D
|
|
(rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns})
|
|
Path Group: mlkem_clk_clk_pll
|
|
Path Type: Setup (Max at Slow Process Corner)
|
|
Requirement: 40.000ns (mlkem_clk_clk_pll rise@40.000ns - mlkem_clk_clk_pll rise@0.000ns)
|
|
Data Path Delay: 28.485ns (logic 0.704ns (2.472%) route 27.781ns (97.528%))
|
|
Logic Levels: 2 (LUT5=1 LUT6=1)
|
|
Clock Path Skew: -0.117ns (DCD - SCD + CPR)
|
|
Destination Clock Delay (DCD): -2.279ns = ( 37.721 - 40.000 )
|
|
Source Clock Delay (SCD): -2.669ns
|
|
Clock Pessimism Removal (CPR): -0.507ns
|
|
Clock Uncertainty: 0.077ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Discrete Jitter (DJ): 0.136ns
|
|
Phase Error (PE): 0.000ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock mlkem_clk_clk_pll rise edge)
|
|
0.000 0.000 r
|
|
clock source latency -6.275 -6.275
|
|
propagated clock network latency
|
|
3.607 -2.669
|
|
SLICE_X107Y119 FDCE 0.000 -2.669 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[2]_rep/C
|
|
SLICE_X107Y119 FDCE (Prop_fdce_C_Q) 0.456 -2.213 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[2]_rep/Q
|
|
net (fo=109, routed) 5.879 3.667 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[2]_rep_n_0
|
|
SLICE_X157Y96 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/I3
|
|
SLICE_X157Y96 LUT5 (Prop_lut5_I3_O) 0.124 3.791 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/O
|
|
net (fo=936, routed) 21.901 25.692 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/sha3_mb_en0
|
|
SLICE_X44Y135 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[969]_i_1/I1
|
|
SLICE_X44Y135 LUT6 (Prop_lut6_I1_O) 0.124 25.816 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[969]_i_1/O
|
|
net (fo=1, routed) 0.000 25.816 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram_n_1143
|
|
SLICE_X44Y135 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[969]/D
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock mlkem_clk_clk_pll rise edge)
|
|
40.000 40.000 r
|
|
clock source latency -5.674 34.326
|
|
propagated clock network latency
|
|
3.396 37.721
|
|
clock pessimism -0.507 37.214
|
|
clock uncertainty -0.077 37.138
|
|
SLICE_X44Y135 FDCE (Setup_fdce_C_D) 0.081 37.219 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[969]
|
|
-------------------------------------------------------------------
|
|
required time 37.219
|
|
arrival time -25.816
|
|
-------------------------------------------------------------------
|
|
slack 11.403
|
|
|
|
Slack (MET) : 11.403ns (required time - arrival time)
|
|
Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[2]_rep/C
|
|
(rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns})
|
|
Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[969]/D
|
|
(rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns})
|
|
Path Group: mlkem_clk_clk_pll
|
|
Path Type: Setup (Max at Slow Process Corner)
|
|
Requirement: 40.000ns (mlkem_clk_clk_pll rise@40.000ns - mlkem_clk_clk_pll rise@0.000ns)
|
|
Data Path Delay: 28.485ns (logic 0.704ns (2.472%) route 27.781ns (97.528%))
|
|
Logic Levels: 2 (LUT5=1 LUT6=1)
|
|
Clock Path Skew: -0.117ns (DCD - SCD + CPR)
|
|
Destination Clock Delay (DCD): -2.279ns = ( 37.721 - 40.000 )
|
|
Source Clock Delay (SCD): -2.669ns
|
|
Clock Pessimism Removal (CPR): -0.507ns
|
|
Clock Uncertainty: 0.077ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Discrete Jitter (DJ): 0.136ns
|
|
Phase Error (PE): 0.000ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock mlkem_clk_clk_pll rise edge)
|
|
0.000 0.000 r
|
|
clock source latency -6.275 -6.275
|
|
propagated clock network latency
|
|
3.607 -2.669
|
|
SLICE_X107Y119 FDCE 0.000 -2.669 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[2]_rep/C
|
|
SLICE_X107Y119 FDCE (Prop_fdce_C_Q) 0.456 -2.213 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[2]_rep/Q
|
|
net (fo=109, routed) 5.879 3.667 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[2]_rep_n_0
|
|
SLICE_X157Y96 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/I3
|
|
SLICE_X157Y96 LUT5 (Prop_lut5_I3_O) 0.124 3.791 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/O
|
|
net (fo=936, routed) 21.901 25.692 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/sha3_mb_en0
|
|
SLICE_X44Y135 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[969]_i_1/I1
|
|
SLICE_X44Y135 LUT6 (Prop_lut6_I1_O) 0.124 25.816 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[969]_i_1/O
|
|
net (fo=1, routed) 0.000 25.816 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram_n_1143
|
|
SLICE_X44Y135 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[969]/D
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock mlkem_clk_clk_pll rise edge)
|
|
40.000 40.000 r
|
|
clock source latency -5.674 34.326
|
|
propagated clock network latency
|
|
3.396 37.721
|
|
clock pessimism -0.507 37.214
|
|
clock uncertainty -0.077 37.138
|
|
SLICE_X44Y135 FDCE (Setup_fdce_C_D) 0.081 37.219 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[969]
|
|
-------------------------------------------------------------------
|
|
required time 37.219
|
|
arrival time -25.816
|
|
-------------------------------------------------------------------
|
|
slack 11.403
|
|
|
|
Slack (MET) : 11.403ns (required time - arrival time)
|
|
Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[2]_rep/C
|
|
(rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns})
|
|
Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[969]/D
|
|
(rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns})
|
|
Path Group: mlkem_clk_clk_pll
|
|
Path Type: Setup (Max at Slow Process Corner)
|
|
Requirement: 40.000ns (mlkem_clk_clk_pll rise@40.000ns - mlkem_clk_clk_pll rise@0.000ns)
|
|
Data Path Delay: 28.485ns (logic 0.704ns (2.472%) route 27.781ns (97.528%))
|
|
Logic Levels: 2 (LUT5=1 LUT6=1)
|
|
Clock Path Skew: -0.117ns (DCD - SCD + CPR)
|
|
Destination Clock Delay (DCD): -2.279ns = ( 37.721 - 40.000 )
|
|
Source Clock Delay (SCD): -2.669ns
|
|
Clock Pessimism Removal (CPR): -0.507ns
|
|
Clock Uncertainty: 0.077ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Discrete Jitter (DJ): 0.136ns
|
|
Phase Error (PE): 0.000ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock mlkem_clk_clk_pll rise edge)
|
|
0.000 0.000 r
|
|
clock source latency -6.275 -6.275
|
|
propagated clock network latency
|
|
3.607 -2.669
|
|
SLICE_X107Y119 FDCE 0.000 -2.669 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[2]_rep/C
|
|
SLICE_X107Y119 FDCE (Prop_fdce_C_Q) 0.456 -2.213 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[2]_rep/Q
|
|
net (fo=109, routed) 5.879 3.667 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[2]_rep_n_0
|
|
SLICE_X157Y96 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/I3
|
|
SLICE_X157Y96 LUT5 (Prop_lut5_I3_O) 0.124 3.791 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/O
|
|
net (fo=936, routed) 21.901 25.692 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/sha3_mb_en0
|
|
SLICE_X44Y135 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[969]_i_1/I1
|
|
SLICE_X44Y135 LUT6 (Prop_lut6_I1_O) 0.124 25.816 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[969]_i_1/O
|
|
net (fo=1, routed) 0.000 25.816 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram_n_1143
|
|
SLICE_X44Y135 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[969]/D
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock mlkem_clk_clk_pll rise edge)
|
|
40.000 40.000 r
|
|
clock source latency -5.674 34.326
|
|
propagated clock network latency
|
|
3.396 37.721
|
|
clock pessimism -0.507 37.214
|
|
clock uncertainty -0.077 37.138
|
|
SLICE_X44Y135 FDCE (Setup_fdce_C_D) 0.081 37.219 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[969]
|
|
-------------------------------------------------------------------
|
|
required time 37.219
|
|
arrival time -25.816
|
|
-------------------------------------------------------------------
|
|
slack 11.403
|
|
|
|
Slack (MET) : 11.414ns (required time - arrival time)
|
|
Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/C
|
|
(rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns})
|
|
Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[778]/D
|
|
(rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns})
|
|
Path Group: mlkem_clk_clk_pll
|
|
Path Type: Setup (Max at Slow Process Corner)
|
|
Requirement: 40.000ns (mlkem_clk_clk_pll rise@40.000ns - mlkem_clk_clk_pll rise@0.000ns)
|
|
Data Path Delay: 28.489ns (logic 0.704ns (2.471%) route 27.785ns (97.529%))
|
|
Logic Levels: 2 (LUT5=1 LUT6=1)
|
|
Clock Path Skew: -0.098ns (DCD - SCD + CPR)
|
|
Destination Clock Delay (DCD): -2.281ns = ( 37.719 - 40.000 )
|
|
Source Clock Delay (SCD): -2.690ns
|
|
Clock Pessimism Removal (CPR): -0.507ns
|
|
Clock Uncertainty: 0.077ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Discrete Jitter (DJ): 0.136ns
|
|
Phase Error (PE): 0.000ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock mlkem_clk_clk_pll rise edge)
|
|
0.000 0.000 r
|
|
clock source latency -6.275 -6.275
|
|
propagated clock network latency
|
|
3.586 -2.690
|
|
SLICE_X91Y121 FDCE 0.000 -2.690 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/C
|
|
SLICE_X91Y121 FDCE (Prop_fdce_C_Q) 0.456 -2.234 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/Q
|
|
net (fo=169, routed) 6.237 4.004 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st[4]
|
|
SLICE_X157Y96 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/I0
|
|
SLICE_X157Y96 LUT5 (Prop_lut5_I0_O) 0.124 4.128 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/O
|
|
net (fo=936, routed) 21.547 25.675 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/sha3_mb_en0
|
|
SLICE_X44Y133 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[778]_i_1/I1
|
|
SLICE_X44Y133 LUT6 (Prop_lut6_I1_O) 0.124 25.799 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[778]_i_1/O
|
|
net (fo=1, routed) 0.000 25.799 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram_n_910
|
|
SLICE_X44Y133 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[778]/D
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock mlkem_clk_clk_pll rise edge)
|
|
40.000 40.000 r
|
|
clock source latency -5.674 34.326
|
|
propagated clock network latency
|
|
3.394 37.719
|
|
clock pessimism -0.507 37.212
|
|
clock uncertainty -0.077 37.136
|
|
SLICE_X44Y133 FDCE (Setup_fdce_C_D) 0.077 37.213 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[778]
|
|
-------------------------------------------------------------------
|
|
required time 37.213
|
|
arrival time -25.799
|
|
-------------------------------------------------------------------
|
|
slack 11.414
|
|
|
|
Slack (MET) : 11.414ns (required time - arrival time)
|
|
Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/C
|
|
(rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns})
|
|
Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[778]/D
|
|
(rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns})
|
|
Path Group: mlkem_clk_clk_pll
|
|
Path Type: Setup (Max at Slow Process Corner)
|
|
Requirement: 40.000ns (mlkem_clk_clk_pll rise@40.000ns - mlkem_clk_clk_pll rise@0.000ns)
|
|
Data Path Delay: 28.489ns (logic 0.704ns (2.471%) route 27.785ns (97.529%))
|
|
Logic Levels: 2 (LUT5=1 LUT6=1)
|
|
Clock Path Skew: -0.098ns (DCD - SCD + CPR)
|
|
Destination Clock Delay (DCD): -2.281ns = ( 37.719 - 40.000 )
|
|
Source Clock Delay (SCD): -2.690ns
|
|
Clock Pessimism Removal (CPR): -0.507ns
|
|
Clock Uncertainty: 0.077ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Discrete Jitter (DJ): 0.136ns
|
|
Phase Error (PE): 0.000ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock mlkem_clk_clk_pll rise edge)
|
|
0.000 0.000 r
|
|
clock source latency -6.275 -6.275
|
|
propagated clock network latency
|
|
3.586 -2.690
|
|
SLICE_X91Y121 FDCE 0.000 -2.690 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/C
|
|
SLICE_X91Y121 FDCE (Prop_fdce_C_Q) 0.456 -2.234 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/Q
|
|
net (fo=169, routed) 6.237 4.004 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st[4]
|
|
SLICE_X157Y96 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/I0
|
|
SLICE_X157Y96 LUT5 (Prop_lut5_I0_O) 0.124 4.128 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/O
|
|
net (fo=936, routed) 21.547 25.675 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/sha3_mb_en0
|
|
SLICE_X44Y133 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[778]_i_1/I1
|
|
SLICE_X44Y133 LUT6 (Prop_lut6_I1_O) 0.124 25.799 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[778]_i_1/O
|
|
net (fo=1, routed) 0.000 25.799 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram_n_910
|
|
SLICE_X44Y133 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[778]/D
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock mlkem_clk_clk_pll rise edge)
|
|
40.000 40.000 r
|
|
clock source latency -5.674 34.326
|
|
propagated clock network latency
|
|
3.394 37.719
|
|
clock pessimism -0.507 37.212
|
|
clock uncertainty -0.077 37.136
|
|
SLICE_X44Y133 FDCE (Setup_fdce_C_D) 0.077 37.213 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[778]
|
|
-------------------------------------------------------------------
|
|
required time 37.213
|
|
arrival time -25.799
|
|
-------------------------------------------------------------------
|
|
slack 11.414
|
|
|
|
Slack (MET) : 11.414ns (required time - arrival time)
|
|
Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/C
|
|
(rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns})
|
|
Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[778]/D
|
|
(rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns})
|
|
Path Group: mlkem_clk_clk_pll
|
|
Path Type: Setup (Max at Slow Process Corner)
|
|
Requirement: 40.000ns (mlkem_clk_clk_pll rise@40.000ns - mlkem_clk_clk_pll rise@0.000ns)
|
|
Data Path Delay: 28.489ns (logic 0.704ns (2.471%) route 27.785ns (97.529%))
|
|
Logic Levels: 2 (LUT5=1 LUT6=1)
|
|
Clock Path Skew: -0.098ns (DCD - SCD + CPR)
|
|
Destination Clock Delay (DCD): -2.281ns = ( 37.719 - 40.000 )
|
|
Source Clock Delay (SCD): -2.690ns
|
|
Clock Pessimism Removal (CPR): -0.507ns
|
|
Clock Uncertainty: 0.077ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Discrete Jitter (DJ): 0.136ns
|
|
Phase Error (PE): 0.000ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock mlkem_clk_clk_pll rise edge)
|
|
0.000 0.000 r
|
|
clock source latency -6.275 -6.275
|
|
propagated clock network latency
|
|
3.586 -2.690
|
|
SLICE_X91Y121 FDCE 0.000 -2.690 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/C
|
|
SLICE_X91Y121 FDCE (Prop_fdce_C_Q) 0.456 -2.234 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/Q
|
|
net (fo=169, routed) 6.237 4.004 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st[4]
|
|
SLICE_X157Y96 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/I0
|
|
SLICE_X157Y96 LUT5 (Prop_lut5_I0_O) 0.124 4.128 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/O
|
|
net (fo=936, routed) 21.547 25.675 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/sha3_mb_en0
|
|
SLICE_X44Y133 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[778]_i_1/I1
|
|
SLICE_X44Y133 LUT6 (Prop_lut6_I1_O) 0.124 25.799 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[778]_i_1/O
|
|
net (fo=1, routed) 0.000 25.799 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram_n_910
|
|
SLICE_X44Y133 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[778]/D
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock mlkem_clk_clk_pll rise edge)
|
|
40.000 40.000 r
|
|
clock source latency -5.674 34.326
|
|
propagated clock network latency
|
|
3.394 37.719
|
|
clock pessimism -0.507 37.212
|
|
clock uncertainty -0.077 37.136
|
|
SLICE_X44Y133 FDCE (Setup_fdce_C_D) 0.077 37.213 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[778]
|
|
-------------------------------------------------------------------
|
|
required time 37.213
|
|
arrival time -25.799
|
|
-------------------------------------------------------------------
|
|
slack 11.414
|
|
|
|
Slack (MET) : 11.414ns (required time - arrival time)
|
|
Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/C
|
|
(rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns})
|
|
Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[778]/D
|
|
(rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns})
|
|
Path Group: mlkem_clk_clk_pll
|
|
Path Type: Setup (Max at Slow Process Corner)
|
|
Requirement: 40.000ns (mlkem_clk_clk_pll rise@40.000ns - mlkem_clk_clk_pll rise@0.000ns)
|
|
Data Path Delay: 28.489ns (logic 0.704ns (2.471%) route 27.785ns (97.529%))
|
|
Logic Levels: 2 (LUT5=1 LUT6=1)
|
|
Clock Path Skew: -0.098ns (DCD - SCD + CPR)
|
|
Destination Clock Delay (DCD): -2.281ns = ( 37.719 - 40.000 )
|
|
Source Clock Delay (SCD): -2.690ns
|
|
Clock Pessimism Removal (CPR): -0.507ns
|
|
Clock Uncertainty: 0.077ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Discrete Jitter (DJ): 0.136ns
|
|
Phase Error (PE): 0.000ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock mlkem_clk_clk_pll rise edge)
|
|
0.000 0.000 r
|
|
clock source latency -6.275 -6.275
|
|
propagated clock network latency
|
|
3.586 -2.690
|
|
SLICE_X91Y121 FDCE 0.000 -2.690 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/C
|
|
SLICE_X91Y121 FDCE (Prop_fdce_C_Q) 0.456 -2.234 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/Q
|
|
net (fo=169, routed) 6.237 4.004 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st[4]
|
|
SLICE_X157Y96 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/I0
|
|
SLICE_X157Y96 LUT5 (Prop_lut5_I0_O) 0.124 4.128 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/O
|
|
net (fo=936, routed) 21.547 25.675 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/sha3_mb_en0
|
|
SLICE_X44Y133 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[778]_i_1/I1
|
|
SLICE_X44Y133 LUT6 (Prop_lut6_I1_O) 0.124 25.799 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[778]_i_1/O
|
|
net (fo=1, routed) 0.000 25.799 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram_n_910
|
|
SLICE_X44Y133 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[778]/D
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock mlkem_clk_clk_pll rise edge)
|
|
40.000 40.000 r
|
|
clock source latency -5.674 34.326
|
|
propagated clock network latency
|
|
3.394 37.719
|
|
clock pessimism -0.507 37.212
|
|
clock uncertainty -0.077 37.136
|
|
SLICE_X44Y133 FDCE (Setup_fdce_C_D) 0.077 37.213 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[778]
|
|
-------------------------------------------------------------------
|
|
required time 37.213
|
|
arrival time -25.799
|
|
-------------------------------------------------------------------
|
|
slack 11.414
|
|
|
|
Slack (MET) : 11.421ns (required time - arrival time)
|
|
Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/C
|
|
(rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns})
|
|
Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[826]/D
|
|
(rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns})
|
|
Path Group: mlkem_clk_clk_pll
|
|
Path Type: Setup (Max at Slow Process Corner)
|
|
Requirement: 40.000ns (mlkem_clk_clk_pll rise@40.000ns - mlkem_clk_clk_pll rise@0.000ns)
|
|
Data Path Delay: 28.486ns (logic 0.704ns (2.471%) route 27.782ns (97.529%))
|
|
Logic Levels: 2 (LUT5=1 LUT6=1)
|
|
Clock Path Skew: -0.098ns (DCD - SCD + CPR)
|
|
Destination Clock Delay (DCD): -2.281ns = ( 37.719 - 40.000 )
|
|
Source Clock Delay (SCD): -2.690ns
|
|
Clock Pessimism Removal (CPR): -0.507ns
|
|
Clock Uncertainty: 0.077ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Discrete Jitter (DJ): 0.136ns
|
|
Phase Error (PE): 0.000ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock mlkem_clk_clk_pll rise edge)
|
|
0.000 0.000 r
|
|
clock source latency -6.275 -6.275
|
|
propagated clock network latency
|
|
3.586 -2.690
|
|
SLICE_X91Y121 FDCE 0.000 -2.690 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/C
|
|
SLICE_X91Y121 FDCE (Prop_fdce_C_Q) 0.456 -2.234 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/Q
|
|
net (fo=169, routed) 6.237 4.004 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st[4]
|
|
SLICE_X157Y96 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/I0
|
|
SLICE_X157Y96 LUT5 (Prop_lut5_I0_O) 0.124 4.128 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/O
|
|
net (fo=936, routed) 21.544 25.672 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/sha3_mb_en0
|
|
SLICE_X44Y133 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[826]_i_1/I1
|
|
SLICE_X44Y133 LUT6 (Prop_lut6_I1_O) 0.124 25.796 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[826]_i_1/O
|
|
net (fo=1, routed) 0.000 25.796 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram_n_469
|
|
SLICE_X44Y133 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[826]/D
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock mlkem_clk_clk_pll rise edge)
|
|
40.000 40.000 r
|
|
clock source latency -5.674 34.326
|
|
propagated clock network latency
|
|
3.394 37.719
|
|
clock pessimism -0.507 37.212
|
|
clock uncertainty -0.077 37.136
|
|
SLICE_X44Y133 FDCE (Setup_fdce_C_D) 0.081 37.217 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[826]
|
|
-------------------------------------------------------------------
|
|
required time 37.217
|
|
arrival time -25.796
|
|
-------------------------------------------------------------------
|
|
slack 11.421
|
|
|
|
Slack (MET) : 11.421ns (required time - arrival time)
|
|
Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/C
|
|
(rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns})
|
|
Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[826]/D
|
|
(rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns})
|
|
Path Group: mlkem_clk_clk_pll
|
|
Path Type: Setup (Max at Slow Process Corner)
|
|
Requirement: 40.000ns (mlkem_clk_clk_pll rise@40.000ns - mlkem_clk_clk_pll rise@0.000ns)
|
|
Data Path Delay: 28.486ns (logic 0.704ns (2.471%) route 27.782ns (97.529%))
|
|
Logic Levels: 2 (LUT5=1 LUT6=1)
|
|
Clock Path Skew: -0.098ns (DCD - SCD + CPR)
|
|
Destination Clock Delay (DCD): -2.281ns = ( 37.719 - 40.000 )
|
|
Source Clock Delay (SCD): -2.690ns
|
|
Clock Pessimism Removal (CPR): -0.507ns
|
|
Clock Uncertainty: 0.077ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Discrete Jitter (DJ): 0.136ns
|
|
Phase Error (PE): 0.000ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock mlkem_clk_clk_pll rise edge)
|
|
0.000 0.000 r
|
|
clock source latency -6.275 -6.275
|
|
propagated clock network latency
|
|
3.586 -2.690
|
|
SLICE_X91Y121 FDCE 0.000 -2.690 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/C
|
|
SLICE_X91Y121 FDCE (Prop_fdce_C_Q) 0.456 -2.234 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/Q
|
|
net (fo=169, routed) 6.237 4.004 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st[4]
|
|
SLICE_X157Y96 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/I0
|
|
SLICE_X157Y96 LUT5 (Prop_lut5_I0_O) 0.124 4.128 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/O
|
|
net (fo=936, routed) 21.544 25.672 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/sha3_mb_en0
|
|
SLICE_X44Y133 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[826]_i_1/I1
|
|
SLICE_X44Y133 LUT6 (Prop_lut6_I1_O) 0.124 25.796 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[826]_i_1/O
|
|
net (fo=1, routed) 0.000 25.796 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram_n_469
|
|
SLICE_X44Y133 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[826]/D
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock mlkem_clk_clk_pll rise edge)
|
|
40.000 40.000 r
|
|
clock source latency -5.674 34.326
|
|
propagated clock network latency
|
|
3.394 37.719
|
|
clock pessimism -0.507 37.212
|
|
clock uncertainty -0.077 37.136
|
|
SLICE_X44Y133 FDCE (Setup_fdce_C_D) 0.081 37.217 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[826]
|
|
-------------------------------------------------------------------
|
|
required time 37.217
|
|
arrival time -25.796
|
|
-------------------------------------------------------------------
|
|
slack 11.421
|
|
|
|
Slack (MET) : 11.421ns (required time - arrival time)
|
|
Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/C
|
|
(rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns})
|
|
Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[826]/D
|
|
(rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns})
|
|
Path Group: mlkem_clk_clk_pll
|
|
Path Type: Setup (Max at Slow Process Corner)
|
|
Requirement: 40.000ns (mlkem_clk_clk_pll rise@40.000ns - mlkem_clk_clk_pll rise@0.000ns)
|
|
Data Path Delay: 28.486ns (logic 0.704ns (2.471%) route 27.782ns (97.529%))
|
|
Logic Levels: 2 (LUT5=1 LUT6=1)
|
|
Clock Path Skew: -0.098ns (DCD - SCD + CPR)
|
|
Destination Clock Delay (DCD): -2.281ns = ( 37.719 - 40.000 )
|
|
Source Clock Delay (SCD): -2.690ns
|
|
Clock Pessimism Removal (CPR): -0.507ns
|
|
Clock Uncertainty: 0.077ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Discrete Jitter (DJ): 0.136ns
|
|
Phase Error (PE): 0.000ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock mlkem_clk_clk_pll rise edge)
|
|
0.000 0.000 r
|
|
clock source latency -6.275 -6.275
|
|
propagated clock network latency
|
|
3.586 -2.690
|
|
SLICE_X91Y121 FDCE 0.000 -2.690 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/C
|
|
SLICE_X91Y121 FDCE (Prop_fdce_C_Q) 0.456 -2.234 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/Q
|
|
net (fo=169, routed) 6.237 4.004 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st[4]
|
|
SLICE_X157Y96 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/I0
|
|
SLICE_X157Y96 LUT5 (Prop_lut5_I0_O) 0.124 4.128 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/O
|
|
net (fo=936, routed) 21.544 25.672 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/sha3_mb_en0
|
|
SLICE_X44Y133 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[826]_i_1/I1
|
|
SLICE_X44Y133 LUT6 (Prop_lut6_I1_O) 0.124 25.796 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[826]_i_1/O
|
|
net (fo=1, routed) 0.000 25.796 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram_n_469
|
|
SLICE_X44Y133 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[826]/D
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock mlkem_clk_clk_pll rise edge)
|
|
40.000 40.000 r
|
|
clock source latency -5.674 34.326
|
|
propagated clock network latency
|
|
3.394 37.719
|
|
clock pessimism -0.507 37.212
|
|
clock uncertainty -0.077 37.136
|
|
SLICE_X44Y133 FDCE (Setup_fdce_C_D) 0.081 37.217 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[826]
|
|
-------------------------------------------------------------------
|
|
required time 37.217
|
|
arrival time -25.796
|
|
-------------------------------------------------------------------
|
|
slack 11.421
|
|
|
|
Slack (MET) : 11.421ns (required time - arrival time)
|
|
Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/C
|
|
(rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns})
|
|
Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[826]/D
|
|
(rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns})
|
|
Path Group: mlkem_clk_clk_pll
|
|
Path Type: Setup (Max at Slow Process Corner)
|
|
Requirement: 40.000ns (mlkem_clk_clk_pll rise@40.000ns - mlkem_clk_clk_pll rise@0.000ns)
|
|
Data Path Delay: 28.486ns (logic 0.704ns (2.471%) route 27.782ns (97.529%))
|
|
Logic Levels: 2 (LUT5=1 LUT6=1)
|
|
Clock Path Skew: -0.098ns (DCD - SCD + CPR)
|
|
Destination Clock Delay (DCD): -2.281ns = ( 37.719 - 40.000 )
|
|
Source Clock Delay (SCD): -2.690ns
|
|
Clock Pessimism Removal (CPR): -0.507ns
|
|
Clock Uncertainty: 0.077ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Discrete Jitter (DJ): 0.136ns
|
|
Phase Error (PE): 0.000ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock mlkem_clk_clk_pll rise edge)
|
|
0.000 0.000 r
|
|
clock source latency -6.275 -6.275
|
|
propagated clock network latency
|
|
3.586 -2.690
|
|
SLICE_X91Y121 FDCE 0.000 -2.690 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/C
|
|
SLICE_X91Y121 FDCE (Prop_fdce_C_Q) 0.456 -2.234 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/Q
|
|
net (fo=169, routed) 6.237 4.004 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st[4]
|
|
SLICE_X157Y96 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/I0
|
|
SLICE_X157Y96 LUT5 (Prop_lut5_I0_O) 0.124 4.128 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/O
|
|
net (fo=936, routed) 21.544 25.672 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/sha3_mb_en0
|
|
SLICE_X44Y133 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[826]_i_1/I1
|
|
SLICE_X44Y133 LUT6 (Prop_lut6_I1_O) 0.124 25.796 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[826]_i_1/O
|
|
net (fo=1, routed) 0.000 25.796 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram_n_469
|
|
SLICE_X44Y133 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[826]/D
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock mlkem_clk_clk_pll rise edge)
|
|
40.000 40.000 r
|
|
clock source latency -5.674 34.326
|
|
propagated clock network latency
|
|
3.394 37.719
|
|
clock pessimism -0.507 37.212
|
|
clock uncertainty -0.077 37.136
|
|
SLICE_X44Y133 FDCE (Setup_fdce_C_D) 0.081 37.217 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[826]
|
|
-------------------------------------------------------------------
|
|
required time 37.217
|
|
arrival time -25.796
|
|
-------------------------------------------------------------------
|
|
slack 11.421
|
|
|
|
Slack (MET) : 11.499ns (required time - arrival time)
|
|
Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[2]_rep/C
|
|
(rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns})
|
|
Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[828]/D
|
|
(rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns})
|
|
Path Group: mlkem_clk_clk_pll
|
|
Path Type: Setup (Max at Slow Process Corner)
|
|
Requirement: 40.000ns (mlkem_clk_clk_pll rise@40.000ns - mlkem_clk_clk_pll rise@0.000ns)
|
|
Data Path Delay: 28.335ns (logic 0.704ns (2.485%) route 27.631ns (97.515%))
|
|
Logic Levels: 2 (LUT5=1 LUT6=1)
|
|
Clock Path Skew: -0.119ns (DCD - SCD + CPR)
|
|
Destination Clock Delay (DCD): -2.281ns = ( 37.719 - 40.000 )
|
|
Source Clock Delay (SCD): -2.669ns
|
|
Clock Pessimism Removal (CPR): -0.507ns
|
|
Clock Uncertainty: 0.077ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Discrete Jitter (DJ): 0.136ns
|
|
Phase Error (PE): 0.000ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock mlkem_clk_clk_pll rise edge)
|
|
0.000 0.000 r
|
|
clock source latency -6.275 -6.275
|
|
propagated clock network latency
|
|
3.607 -2.669
|
|
SLICE_X107Y119 FDCE 0.000 -2.669 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[2]_rep/C
|
|
SLICE_X107Y119 FDCE (Prop_fdce_C_Q) 0.456 -2.213 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[2]_rep/Q
|
|
net (fo=109, routed) 5.879 3.667 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[2]_rep_n_0
|
|
SLICE_X157Y96 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/I3
|
|
SLICE_X157Y96 LUT5 (Prop_lut5_I3_O) 0.124 3.791 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/O
|
|
net (fo=936, routed) 21.751 25.542 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/sha3_mb_en0
|
|
SLICE_X45Y133 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[828]_i_1/I1
|
|
SLICE_X45Y133 LUT6 (Prop_lut6_I1_O) 0.124 25.666 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[828]_i_1/O
|
|
net (fo=1, routed) 0.000 25.666 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram_n_471
|
|
SLICE_X45Y133 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[828]/D
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock mlkem_clk_clk_pll rise edge)
|
|
40.000 40.000 r
|
|
clock source latency -5.674 34.326
|
|
propagated clock network latency
|
|
3.394 37.719
|
|
clock pessimism -0.507 37.212
|
|
clock uncertainty -0.077 37.136
|
|
SLICE_X45Y133 FDCE (Setup_fdce_C_D) 0.029 37.165 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[828]
|
|
-------------------------------------------------------------------
|
|
required time 37.165
|
|
arrival time -25.666
|
|
-------------------------------------------------------------------
|
|
slack 11.499
|
|
|
|
Slack (MET) : 11.499ns (required time - arrival time)
|
|
Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[2]_rep/C
|
|
(rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns})
|
|
Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[828]/D
|
|
(rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns})
|
|
Path Group: mlkem_clk_clk_pll
|
|
Path Type: Setup (Max at Slow Process Corner)
|
|
Requirement: 40.000ns (mlkem_clk_clk_pll rise@40.000ns - mlkem_clk_clk_pll rise@0.000ns)
|
|
Data Path Delay: 28.335ns (logic 0.704ns (2.485%) route 27.631ns (97.515%))
|
|
Logic Levels: 2 (LUT5=1 LUT6=1)
|
|
Clock Path Skew: -0.119ns (DCD - SCD + CPR)
|
|
Destination Clock Delay (DCD): -2.281ns = ( 37.719 - 40.000 )
|
|
Source Clock Delay (SCD): -2.669ns
|
|
Clock Pessimism Removal (CPR): -0.507ns
|
|
Clock Uncertainty: 0.077ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Discrete Jitter (DJ): 0.136ns
|
|
Phase Error (PE): 0.000ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock mlkem_clk_clk_pll rise edge)
|
|
0.000 0.000 r
|
|
clock source latency -6.275 -6.275
|
|
propagated clock network latency
|
|
3.607 -2.669
|
|
SLICE_X107Y119 FDCE 0.000 -2.669 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[2]_rep/C
|
|
SLICE_X107Y119 FDCE (Prop_fdce_C_Q) 0.456 -2.213 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[2]_rep/Q
|
|
net (fo=109, routed) 5.879 3.667 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[2]_rep_n_0
|
|
SLICE_X157Y96 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/I3
|
|
SLICE_X157Y96 LUT5 (Prop_lut5_I3_O) 0.124 3.791 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/O
|
|
net (fo=936, routed) 21.751 25.542 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/sha3_mb_en0
|
|
SLICE_X45Y133 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[828]_i_1/I1
|
|
SLICE_X45Y133 LUT6 (Prop_lut6_I1_O) 0.124 25.666 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[828]_i_1/O
|
|
net (fo=1, routed) 0.000 25.666 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram_n_471
|
|
SLICE_X45Y133 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[828]/D
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock mlkem_clk_clk_pll rise edge)
|
|
40.000 40.000 r
|
|
clock source latency -5.674 34.326
|
|
propagated clock network latency
|
|
3.394 37.719
|
|
clock pessimism -0.507 37.212
|
|
clock uncertainty -0.077 37.136
|
|
SLICE_X45Y133 FDCE (Setup_fdce_C_D) 0.029 37.165 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[828]
|
|
-------------------------------------------------------------------
|
|
required time 37.165
|
|
arrival time -25.666
|
|
-------------------------------------------------------------------
|
|
slack 11.499
|
|
|
|
Slack (MET) : 11.499ns (required time - arrival time)
|
|
Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[2]_rep/C
|
|
(rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns})
|
|
Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[828]/D
|
|
(rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns})
|
|
Path Group: mlkem_clk_clk_pll
|
|
Path Type: Setup (Max at Slow Process Corner)
|
|
Requirement: 40.000ns (mlkem_clk_clk_pll rise@40.000ns - mlkem_clk_clk_pll rise@0.000ns)
|
|
Data Path Delay: 28.335ns (logic 0.704ns (2.485%) route 27.631ns (97.515%))
|
|
Logic Levels: 2 (LUT5=1 LUT6=1)
|
|
Clock Path Skew: -0.119ns (DCD - SCD + CPR)
|
|
Destination Clock Delay (DCD): -2.281ns = ( 37.719 - 40.000 )
|
|
Source Clock Delay (SCD): -2.669ns
|
|
Clock Pessimism Removal (CPR): -0.507ns
|
|
Clock Uncertainty: 0.077ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Discrete Jitter (DJ): 0.136ns
|
|
Phase Error (PE): 0.000ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock mlkem_clk_clk_pll rise edge)
|
|
0.000 0.000 r
|
|
clock source latency -6.275 -6.275
|
|
propagated clock network latency
|
|
3.607 -2.669
|
|
SLICE_X107Y119 FDCE 0.000 -2.669 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[2]_rep/C
|
|
SLICE_X107Y119 FDCE (Prop_fdce_C_Q) 0.456 -2.213 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[2]_rep/Q
|
|
net (fo=109, routed) 5.879 3.667 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[2]_rep_n_0
|
|
SLICE_X157Y96 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/I3
|
|
SLICE_X157Y96 LUT5 (Prop_lut5_I3_O) 0.124 3.791 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/O
|
|
net (fo=936, routed) 21.751 25.542 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/sha3_mb_en0
|
|
SLICE_X45Y133 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[828]_i_1/I1
|
|
SLICE_X45Y133 LUT6 (Prop_lut6_I1_O) 0.124 25.666 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[828]_i_1/O
|
|
net (fo=1, routed) 0.000 25.666 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram_n_471
|
|
SLICE_X45Y133 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[828]/D
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock mlkem_clk_clk_pll rise edge)
|
|
40.000 40.000 r
|
|
clock source latency -5.674 34.326
|
|
propagated clock network latency
|
|
3.394 37.719
|
|
clock pessimism -0.507 37.212
|
|
clock uncertainty -0.077 37.136
|
|
SLICE_X45Y133 FDCE (Setup_fdce_C_D) 0.029 37.165 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[828]
|
|
-------------------------------------------------------------------
|
|
required time 37.165
|
|
arrival time -25.666
|
|
-------------------------------------------------------------------
|
|
slack 11.499
|
|
|
|
Slack (MET) : 11.499ns (required time - arrival time)
|
|
Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[2]_rep/C
|
|
(rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns})
|
|
Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[828]/D
|
|
(rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns})
|
|
Path Group: mlkem_clk_clk_pll
|
|
Path Type: Setup (Max at Slow Process Corner)
|
|
Requirement: 40.000ns (mlkem_clk_clk_pll rise@40.000ns - mlkem_clk_clk_pll rise@0.000ns)
|
|
Data Path Delay: 28.335ns (logic 0.704ns (2.485%) route 27.631ns (97.515%))
|
|
Logic Levels: 2 (LUT5=1 LUT6=1)
|
|
Clock Path Skew: -0.119ns (DCD - SCD + CPR)
|
|
Destination Clock Delay (DCD): -2.281ns = ( 37.719 - 40.000 )
|
|
Source Clock Delay (SCD): -2.669ns
|
|
Clock Pessimism Removal (CPR): -0.507ns
|
|
Clock Uncertainty: 0.077ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Discrete Jitter (DJ): 0.136ns
|
|
Phase Error (PE): 0.000ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock mlkem_clk_clk_pll rise edge)
|
|
0.000 0.000 r
|
|
clock source latency -6.275 -6.275
|
|
propagated clock network latency
|
|
3.607 -2.669
|
|
SLICE_X107Y119 FDCE 0.000 -2.669 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[2]_rep/C
|
|
SLICE_X107Y119 FDCE (Prop_fdce_C_Q) 0.456 -2.213 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[2]_rep/Q
|
|
net (fo=109, routed) 5.879 3.667 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[2]_rep_n_0
|
|
SLICE_X157Y96 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/I3
|
|
SLICE_X157Y96 LUT5 (Prop_lut5_I3_O) 0.124 3.791 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/O
|
|
net (fo=936, routed) 21.751 25.542 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/sha3_mb_en0
|
|
SLICE_X45Y133 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[828]_i_1/I1
|
|
SLICE_X45Y133 LUT6 (Prop_lut6_I1_O) 0.124 25.666 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[828]_i_1/O
|
|
net (fo=1, routed) 0.000 25.666 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram_n_471
|
|
SLICE_X45Y133 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[828]/D
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock mlkem_clk_clk_pll rise edge)
|
|
40.000 40.000 r
|
|
clock source latency -5.674 34.326
|
|
propagated clock network latency
|
|
3.394 37.719
|
|
clock pessimism -0.507 37.212
|
|
clock uncertainty -0.077 37.136
|
|
SLICE_X45Y133 FDCE (Setup_fdce_C_D) 0.029 37.165 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[828]
|
|
-------------------------------------------------------------------
|
|
required time 37.165
|
|
arrival time -25.666
|
|
-------------------------------------------------------------------
|
|
slack 11.499
|
|
|
|
Slack (MET) : 11.499ns (required time - arrival time)
|
|
Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[2]_rep/C
|
|
(rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns})
|
|
Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[828]/D
|
|
(rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns})
|
|
Path Group: mlkem_clk_clk_pll
|
|
Path Type: Setup (Max at Slow Process Corner)
|
|
Requirement: 40.000ns (mlkem_clk_clk_pll rise@40.000ns - mlkem_clk_clk_pll rise@0.000ns)
|
|
Data Path Delay: 28.335ns (logic 0.704ns (2.485%) route 27.631ns (97.515%))
|
|
Logic Levels: 2 (LUT5=1 LUT6=1)
|
|
Clock Path Skew: -0.119ns (DCD - SCD + CPR)
|
|
Destination Clock Delay (DCD): -2.281ns = ( 37.719 - 40.000 )
|
|
Source Clock Delay (SCD): -2.669ns
|
|
Clock Pessimism Removal (CPR): -0.507ns
|
|
Clock Uncertainty: 0.077ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Discrete Jitter (DJ): 0.136ns
|
|
Phase Error (PE): 0.000ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock mlkem_clk_clk_pll rise edge)
|
|
0.000 0.000 r
|
|
clock source latency -6.275 -6.275
|
|
propagated clock network latency
|
|
3.607 -2.669
|
|
SLICE_X107Y119 FDCE 0.000 -2.669 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[2]_rep/C
|
|
SLICE_X107Y119 FDCE (Prop_fdce_C_Q) 0.456 -2.213 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[2]_rep/Q
|
|
net (fo=109, routed) 5.879 3.667 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[2]_rep_n_0
|
|
SLICE_X157Y96 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/I3
|
|
SLICE_X157Y96 LUT5 (Prop_lut5_I3_O) 0.124 3.791 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/O
|
|
net (fo=936, routed) 21.751 25.542 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/sha3_mb_en0
|
|
SLICE_X45Y133 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[828]_i_1/I1
|
|
SLICE_X45Y133 LUT6 (Prop_lut6_I1_O) 0.124 25.666 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[828]_i_1/O
|
|
net (fo=1, routed) 0.000 25.666 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram_n_471
|
|
SLICE_X45Y133 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[828]/D
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock mlkem_clk_clk_pll rise edge)
|
|
40.000 40.000 r
|
|
clock source latency -5.674 34.326
|
|
propagated clock network latency
|
|
3.394 37.719
|
|
clock pessimism -0.507 37.212
|
|
clock uncertainty -0.077 37.136
|
|
SLICE_X45Y133 FDCE (Setup_fdce_C_D) 0.029 37.165 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[828]
|
|
-------------------------------------------------------------------
|
|
required time 37.165
|
|
arrival time -25.666
|
|
-------------------------------------------------------------------
|
|
slack 11.499
|
|
|
|
Slack (MET) : 11.499ns (required time - arrival time)
|
|
Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[2]_rep/C
|
|
(rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns})
|
|
Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[828]/D
|
|
(rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns})
|
|
Path Group: mlkem_clk_clk_pll
|
|
Path Type: Setup (Max at Slow Process Corner)
|
|
Requirement: 40.000ns (mlkem_clk_clk_pll rise@40.000ns - mlkem_clk_clk_pll rise@0.000ns)
|
|
Data Path Delay: 28.335ns (logic 0.704ns (2.485%) route 27.631ns (97.515%))
|
|
Logic Levels: 2 (LUT5=1 LUT6=1)
|
|
Clock Path Skew: -0.119ns (DCD - SCD + CPR)
|
|
Destination Clock Delay (DCD): -2.281ns = ( 37.719 - 40.000 )
|
|
Source Clock Delay (SCD): -2.669ns
|
|
Clock Pessimism Removal (CPR): -0.507ns
|
|
Clock Uncertainty: 0.077ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Discrete Jitter (DJ): 0.136ns
|
|
Phase Error (PE): 0.000ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock mlkem_clk_clk_pll rise edge)
|
|
0.000 0.000 r
|
|
clock source latency -6.275 -6.275
|
|
propagated clock network latency
|
|
3.607 -2.669
|
|
SLICE_X107Y119 FDCE 0.000 -2.669 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[2]_rep/C
|
|
SLICE_X107Y119 FDCE (Prop_fdce_C_Q) 0.456 -2.213 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[2]_rep/Q
|
|
net (fo=109, routed) 5.879 3.667 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[2]_rep_n_0
|
|
SLICE_X157Y96 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/I3
|
|
SLICE_X157Y96 LUT5 (Prop_lut5_I3_O) 0.124 3.791 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/O
|
|
net (fo=936, routed) 21.751 25.542 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/sha3_mb_en0
|
|
SLICE_X45Y133 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[828]_i_1/I1
|
|
SLICE_X45Y133 LUT6 (Prop_lut6_I1_O) 0.124 25.666 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[828]_i_1/O
|
|
net (fo=1, routed) 0.000 25.666 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram_n_471
|
|
SLICE_X45Y133 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[828]/D
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock mlkem_clk_clk_pll rise edge)
|
|
40.000 40.000 r
|
|
clock source latency -5.674 34.326
|
|
propagated clock network latency
|
|
3.394 37.719
|
|
clock pessimism -0.507 37.212
|
|
clock uncertainty -0.077 37.136
|
|
SLICE_X45Y133 FDCE (Setup_fdce_C_D) 0.029 37.165 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[828]
|
|
-------------------------------------------------------------------
|
|
required time 37.165
|
|
arrival time -25.666
|
|
-------------------------------------------------------------------
|
|
slack 11.499
|
|
|
|
Slack (MET) : 11.503ns (required time - arrival time)
|
|
Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/C
|
|
(rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns})
|
|
Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[908]/D
|
|
(rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns})
|
|
Path Group: mlkem_clk_clk_pll
|
|
Path Type: Setup (Max at Slow Process Corner)
|
|
Requirement: 40.000ns (mlkem_clk_clk_pll rise@40.000ns - mlkem_clk_clk_pll rise@0.000ns)
|
|
Data Path Delay: 28.355ns (logic 0.704ns (2.483%) route 27.651ns (97.517%))
|
|
Logic Levels: 2 (LUT5=1 LUT6=1)
|
|
Clock Path Skew: -0.097ns (DCD - SCD + CPR)
|
|
Destination Clock Delay (DCD): -2.280ns = ( 37.720 - 40.000 )
|
|
Source Clock Delay (SCD): -2.690ns
|
|
Clock Pessimism Removal (CPR): -0.507ns
|
|
Clock Uncertainty: 0.077ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Discrete Jitter (DJ): 0.136ns
|
|
Phase Error (PE): 0.000ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock mlkem_clk_clk_pll rise edge)
|
|
0.000 0.000 r
|
|
clock source latency -6.275 -6.275
|
|
propagated clock network latency
|
|
3.586 -2.690
|
|
SLICE_X91Y121 FDCE 0.000 -2.690 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/C
|
|
SLICE_X91Y121 FDCE (Prop_fdce_C_Q) 0.456 -2.234 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/Q
|
|
net (fo=169, routed) 6.237 4.004 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st[4]
|
|
SLICE_X157Y96 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/I0
|
|
SLICE_X157Y96 LUT5 (Prop_lut5_I0_O) 0.124 4.128 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/O
|
|
net (fo=936, routed) 21.413 25.541 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/sha3_mb_en0
|
|
SLICE_X45Y134 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[908]_i_1/I1
|
|
SLICE_X45Y134 LUT6 (Prop_lut6_I1_O) 0.124 25.665 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[908]_i_1/O
|
|
net (fo=1, routed) 0.000 25.665 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram_n_919
|
|
SLICE_X45Y134 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[908]/D
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock mlkem_clk_clk_pll rise edge)
|
|
40.000 40.000 r
|
|
clock source latency -5.674 34.326
|
|
propagated clock network latency
|
|
3.395 37.720
|
|
clock pessimism -0.507 37.213
|
|
clock uncertainty -0.077 37.137
|
|
SLICE_X45Y134 FDCE (Setup_fdce_C_D) 0.031 37.168 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[908]
|
|
-------------------------------------------------------------------
|
|
required time 37.168
|
|
arrival time -25.665
|
|
-------------------------------------------------------------------
|
|
slack 11.503
|
|
|
|
Slack (MET) : 11.503ns (required time - arrival time)
|
|
Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/C
|
|
(rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns})
|
|
Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[908]/D
|
|
(rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns})
|
|
Path Group: mlkem_clk_clk_pll
|
|
Path Type: Setup (Max at Slow Process Corner)
|
|
Requirement: 40.000ns (mlkem_clk_clk_pll rise@40.000ns - mlkem_clk_clk_pll rise@0.000ns)
|
|
Data Path Delay: 28.355ns (logic 0.704ns (2.483%) route 27.651ns (97.517%))
|
|
Logic Levels: 2 (LUT5=1 LUT6=1)
|
|
Clock Path Skew: -0.097ns (DCD - SCD + CPR)
|
|
Destination Clock Delay (DCD): -2.280ns = ( 37.720 - 40.000 )
|
|
Source Clock Delay (SCD): -2.690ns
|
|
Clock Pessimism Removal (CPR): -0.507ns
|
|
Clock Uncertainty: 0.077ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Discrete Jitter (DJ): 0.136ns
|
|
Phase Error (PE): 0.000ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock mlkem_clk_clk_pll rise edge)
|
|
0.000 0.000 r
|
|
clock source latency -6.275 -6.275
|
|
propagated clock network latency
|
|
3.586 -2.690
|
|
SLICE_X91Y121 FDCE 0.000 -2.690 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/C
|
|
SLICE_X91Y121 FDCE (Prop_fdce_C_Q) 0.456 -2.234 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/Q
|
|
net (fo=169, routed) 6.237 4.004 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st[4]
|
|
SLICE_X157Y96 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/I0
|
|
SLICE_X157Y96 LUT5 (Prop_lut5_I0_O) 0.124 4.128 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/O
|
|
net (fo=936, routed) 21.413 25.541 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/sha3_mb_en0
|
|
SLICE_X45Y134 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[908]_i_1/I1
|
|
SLICE_X45Y134 LUT6 (Prop_lut6_I1_O) 0.124 25.665 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[908]_i_1/O
|
|
net (fo=1, routed) 0.000 25.665 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram_n_919
|
|
SLICE_X45Y134 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[908]/D
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock mlkem_clk_clk_pll rise edge)
|
|
40.000 40.000 r
|
|
clock source latency -5.674 34.326
|
|
propagated clock network latency
|
|
3.395 37.720
|
|
clock pessimism -0.507 37.213
|
|
clock uncertainty -0.077 37.137
|
|
SLICE_X45Y134 FDCE (Setup_fdce_C_D) 0.031 37.168 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[908]
|
|
-------------------------------------------------------------------
|
|
required time 37.168
|
|
arrival time -25.665
|
|
-------------------------------------------------------------------
|
|
slack 11.503
|
|
|
|
Slack (MET) : 11.503ns (required time - arrival time)
|
|
Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/C
|
|
(rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns})
|
|
Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[908]/D
|
|
(rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns})
|
|
Path Group: mlkem_clk_clk_pll
|
|
Path Type: Setup (Max at Slow Process Corner)
|
|
Requirement: 40.000ns (mlkem_clk_clk_pll rise@40.000ns - mlkem_clk_clk_pll rise@0.000ns)
|
|
Data Path Delay: 28.355ns (logic 0.704ns (2.483%) route 27.651ns (97.517%))
|
|
Logic Levels: 2 (LUT5=1 LUT6=1)
|
|
Clock Path Skew: -0.097ns (DCD - SCD + CPR)
|
|
Destination Clock Delay (DCD): -2.280ns = ( 37.720 - 40.000 )
|
|
Source Clock Delay (SCD): -2.690ns
|
|
Clock Pessimism Removal (CPR): -0.507ns
|
|
Clock Uncertainty: 0.077ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Discrete Jitter (DJ): 0.136ns
|
|
Phase Error (PE): 0.000ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock mlkem_clk_clk_pll rise edge)
|
|
0.000 0.000 r
|
|
clock source latency -6.275 -6.275
|
|
propagated clock network latency
|
|
3.586 -2.690
|
|
SLICE_X91Y121 FDCE 0.000 -2.690 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/C
|
|
SLICE_X91Y121 FDCE (Prop_fdce_C_Q) 0.456 -2.234 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/Q
|
|
net (fo=169, routed) 6.237 4.004 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st[4]
|
|
SLICE_X157Y96 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/I0
|
|
SLICE_X157Y96 LUT5 (Prop_lut5_I0_O) 0.124 4.128 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/O
|
|
net (fo=936, routed) 21.413 25.541 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/sha3_mb_en0
|
|
SLICE_X45Y134 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[908]_i_1/I1
|
|
SLICE_X45Y134 LUT6 (Prop_lut6_I1_O) 0.124 25.665 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[908]_i_1/O
|
|
net (fo=1, routed) 0.000 25.665 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram_n_919
|
|
SLICE_X45Y134 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[908]/D
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock mlkem_clk_clk_pll rise edge)
|
|
40.000 40.000 r
|
|
clock source latency -5.674 34.326
|
|
propagated clock network latency
|
|
3.395 37.720
|
|
clock pessimism -0.507 37.213
|
|
clock uncertainty -0.077 37.137
|
|
SLICE_X45Y134 FDCE (Setup_fdce_C_D) 0.031 37.168 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[908]
|
|
-------------------------------------------------------------------
|
|
required time 37.168
|
|
arrival time -25.665
|
|
-------------------------------------------------------------------
|
|
slack 11.503
|
|
|
|
Slack (MET) : 11.503ns (required time - arrival time)
|
|
Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/C
|
|
(rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns})
|
|
Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[908]/D
|
|
(rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns})
|
|
Path Group: mlkem_clk_clk_pll
|
|
Path Type: Setup (Max at Slow Process Corner)
|
|
Requirement: 40.000ns (mlkem_clk_clk_pll rise@40.000ns - mlkem_clk_clk_pll rise@0.000ns)
|
|
Data Path Delay: 28.355ns (logic 0.704ns (2.483%) route 27.651ns (97.517%))
|
|
Logic Levels: 2 (LUT5=1 LUT6=1)
|
|
Clock Path Skew: -0.097ns (DCD - SCD + CPR)
|
|
Destination Clock Delay (DCD): -2.280ns = ( 37.720 - 40.000 )
|
|
Source Clock Delay (SCD): -2.690ns
|
|
Clock Pessimism Removal (CPR): -0.507ns
|
|
Clock Uncertainty: 0.077ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Discrete Jitter (DJ): 0.136ns
|
|
Phase Error (PE): 0.000ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock mlkem_clk_clk_pll rise edge)
|
|
0.000 0.000 r
|
|
clock source latency -6.275 -6.275
|
|
propagated clock network latency
|
|
3.586 -2.690
|
|
SLICE_X91Y121 FDCE 0.000 -2.690 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/C
|
|
SLICE_X91Y121 FDCE (Prop_fdce_C_Q) 0.456 -2.234 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/Q
|
|
net (fo=169, routed) 6.237 4.004 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st[4]
|
|
SLICE_X157Y96 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/I0
|
|
SLICE_X157Y96 LUT5 (Prop_lut5_I0_O) 0.124 4.128 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/O
|
|
net (fo=936, routed) 21.413 25.541 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/sha3_mb_en0
|
|
SLICE_X45Y134 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[908]_i_1/I1
|
|
SLICE_X45Y134 LUT6 (Prop_lut6_I1_O) 0.124 25.665 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[908]_i_1/O
|
|
net (fo=1, routed) 0.000 25.665 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram_n_919
|
|
SLICE_X45Y134 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[908]/D
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock mlkem_clk_clk_pll rise edge)
|
|
40.000 40.000 r
|
|
clock source latency -5.674 34.326
|
|
propagated clock network latency
|
|
3.395 37.720
|
|
clock pessimism -0.507 37.213
|
|
clock uncertainty -0.077 37.137
|
|
SLICE_X45Y134 FDCE (Setup_fdce_C_D) 0.031 37.168 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[908]
|
|
-------------------------------------------------------------------
|
|
required time 37.168
|
|
arrival time -25.665
|
|
-------------------------------------------------------------------
|
|
slack 11.503
|
|
|
|
Slack (MET) : 11.505ns (required time - arrival time)
|
|
Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/C
|
|
(rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns})
|
|
Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[909]/D
|
|
(rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns})
|
|
Path Group: mlkem_clk_clk_pll
|
|
Path Type: Setup (Max at Slow Process Corner)
|
|
Requirement: 40.000ns (mlkem_clk_clk_pll rise@40.000ns - mlkem_clk_clk_pll rise@0.000ns)
|
|
Data Path Delay: 28.347ns (logic 0.704ns (2.484%) route 27.643ns (97.516%))
|
|
Logic Levels: 2 (LUT5=1 LUT6=1)
|
|
Clock Path Skew: -0.101ns (DCD - SCD + CPR)
|
|
Destination Clock Delay (DCD): -2.284ns = ( 37.716 - 40.000 )
|
|
Source Clock Delay (SCD): -2.690ns
|
|
Clock Pessimism Removal (CPR): -0.507ns
|
|
Clock Uncertainty: 0.077ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Discrete Jitter (DJ): 0.136ns
|
|
Phase Error (PE): 0.000ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock mlkem_clk_clk_pll rise edge)
|
|
0.000 0.000 r
|
|
clock source latency -6.275 -6.275
|
|
propagated clock network latency
|
|
3.586 -2.690
|
|
SLICE_X91Y121 FDCE 0.000 -2.690 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/C
|
|
SLICE_X91Y121 FDCE (Prop_fdce_C_Q) 0.456 -2.234 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/Q
|
|
net (fo=169, routed) 6.237 4.004 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st[4]
|
|
SLICE_X157Y96 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/I0
|
|
SLICE_X157Y96 LUT5 (Prop_lut5_I0_O) 0.124 4.128 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/O
|
|
net (fo=936, routed) 21.405 25.533 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/sha3_mb_en0
|
|
SLICE_X45Y131 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[909]_i_1/I1
|
|
SLICE_X45Y131 LUT6 (Prop_lut6_I1_O) 0.124 25.657 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[909]_i_1/O
|
|
net (fo=1, routed) 0.000 25.657 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram_n_920
|
|
SLICE_X45Y131 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[909]/D
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock mlkem_clk_clk_pll rise edge)
|
|
40.000 40.000 r
|
|
clock source latency -5.674 34.326
|
|
propagated clock network latency
|
|
3.391 37.716
|
|
clock pessimism -0.507 37.209
|
|
clock uncertainty -0.077 37.133
|
|
SLICE_X45Y131 FDCE (Setup_fdce_C_D) 0.029 37.162 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[909]
|
|
-------------------------------------------------------------------
|
|
required time 37.162
|
|
arrival time -25.657
|
|
-------------------------------------------------------------------
|
|
slack 11.505
|
|
|
|
Slack (MET) : 11.505ns (required time - arrival time)
|
|
Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/C
|
|
(rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns})
|
|
Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[909]/D
|
|
(rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns})
|
|
Path Group: mlkem_clk_clk_pll
|
|
Path Type: Setup (Max at Slow Process Corner)
|
|
Requirement: 40.000ns (mlkem_clk_clk_pll rise@40.000ns - mlkem_clk_clk_pll rise@0.000ns)
|
|
Data Path Delay: 28.347ns (logic 0.704ns (2.484%) route 27.643ns (97.516%))
|
|
Logic Levels: 2 (LUT5=1 LUT6=1)
|
|
Clock Path Skew: -0.101ns (DCD - SCD + CPR)
|
|
Destination Clock Delay (DCD): -2.284ns = ( 37.716 - 40.000 )
|
|
Source Clock Delay (SCD): -2.690ns
|
|
Clock Pessimism Removal (CPR): -0.507ns
|
|
Clock Uncertainty: 0.077ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Discrete Jitter (DJ): 0.136ns
|
|
Phase Error (PE): 0.000ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock mlkem_clk_clk_pll rise edge)
|
|
0.000 0.000 r
|
|
clock source latency -6.275 -6.275
|
|
propagated clock network latency
|
|
3.586 -2.690
|
|
SLICE_X91Y121 FDCE 0.000 -2.690 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/C
|
|
SLICE_X91Y121 FDCE (Prop_fdce_C_Q) 0.456 -2.234 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/Q
|
|
net (fo=169, routed) 6.237 4.004 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st[4]
|
|
SLICE_X157Y96 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/I0
|
|
SLICE_X157Y96 LUT5 (Prop_lut5_I0_O) 0.124 4.128 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/O
|
|
net (fo=936, routed) 21.405 25.533 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/sha3_mb_en0
|
|
SLICE_X45Y131 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[909]_i_1/I1
|
|
SLICE_X45Y131 LUT6 (Prop_lut6_I1_O) 0.124 25.657 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[909]_i_1/O
|
|
net (fo=1, routed) 0.000 25.657 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram_n_920
|
|
SLICE_X45Y131 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[909]/D
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock mlkem_clk_clk_pll rise edge)
|
|
40.000 40.000 r
|
|
clock source latency -5.674 34.326
|
|
propagated clock network latency
|
|
3.391 37.716
|
|
clock pessimism -0.507 37.209
|
|
clock uncertainty -0.077 37.133
|
|
SLICE_X45Y131 FDCE (Setup_fdce_C_D) 0.029 37.162 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[909]
|
|
-------------------------------------------------------------------
|
|
required time 37.162
|
|
arrival time -25.657
|
|
-------------------------------------------------------------------
|
|
slack 11.505
|
|
|
|
Slack (MET) : 11.505ns (required time - arrival time)
|
|
Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/C
|
|
(rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns})
|
|
Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[909]/D
|
|
(rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns})
|
|
Path Group: mlkem_clk_clk_pll
|
|
Path Type: Setup (Max at Slow Process Corner)
|
|
Requirement: 40.000ns (mlkem_clk_clk_pll rise@40.000ns - mlkem_clk_clk_pll rise@0.000ns)
|
|
Data Path Delay: 28.347ns (logic 0.704ns (2.484%) route 27.643ns (97.516%))
|
|
Logic Levels: 2 (LUT5=1 LUT6=1)
|
|
Clock Path Skew: -0.101ns (DCD - SCD + CPR)
|
|
Destination Clock Delay (DCD): -2.284ns = ( 37.716 - 40.000 )
|
|
Source Clock Delay (SCD): -2.690ns
|
|
Clock Pessimism Removal (CPR): -0.507ns
|
|
Clock Uncertainty: 0.077ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Discrete Jitter (DJ): 0.136ns
|
|
Phase Error (PE): 0.000ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock mlkem_clk_clk_pll rise edge)
|
|
0.000 0.000 r
|
|
clock source latency -6.275 -6.275
|
|
propagated clock network latency
|
|
3.586 -2.690
|
|
SLICE_X91Y121 FDCE 0.000 -2.690 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/C
|
|
SLICE_X91Y121 FDCE (Prop_fdce_C_Q) 0.456 -2.234 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/Q
|
|
net (fo=169, routed) 6.237 4.004 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st[4]
|
|
SLICE_X157Y96 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/I0
|
|
SLICE_X157Y96 LUT5 (Prop_lut5_I0_O) 0.124 4.128 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/O
|
|
net (fo=936, routed) 21.405 25.533 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/sha3_mb_en0
|
|
SLICE_X45Y131 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[909]_i_1/I1
|
|
SLICE_X45Y131 LUT6 (Prop_lut6_I1_O) 0.124 25.657 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[909]_i_1/O
|
|
net (fo=1, routed) 0.000 25.657 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram_n_920
|
|
SLICE_X45Y131 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[909]/D
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock mlkem_clk_clk_pll rise edge)
|
|
40.000 40.000 r
|
|
clock source latency -5.674 34.326
|
|
propagated clock network latency
|
|
3.391 37.716
|
|
clock pessimism -0.507 37.209
|
|
clock uncertainty -0.077 37.133
|
|
SLICE_X45Y131 FDCE (Setup_fdce_C_D) 0.029 37.162 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[909]
|
|
-------------------------------------------------------------------
|
|
required time 37.162
|
|
arrival time -25.657
|
|
-------------------------------------------------------------------
|
|
slack 11.505
|
|
|
|
Slack (MET) : 11.505ns (required time - arrival time)
|
|
Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/C
|
|
(rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns})
|
|
Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[909]/D
|
|
(rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns})
|
|
Path Group: mlkem_clk_clk_pll
|
|
Path Type: Setup (Max at Slow Process Corner)
|
|
Requirement: 40.000ns (mlkem_clk_clk_pll rise@40.000ns - mlkem_clk_clk_pll rise@0.000ns)
|
|
Data Path Delay: 28.347ns (logic 0.704ns (2.484%) route 27.643ns (97.516%))
|
|
Logic Levels: 2 (LUT5=1 LUT6=1)
|
|
Clock Path Skew: -0.101ns (DCD - SCD + CPR)
|
|
Destination Clock Delay (DCD): -2.284ns = ( 37.716 - 40.000 )
|
|
Source Clock Delay (SCD): -2.690ns
|
|
Clock Pessimism Removal (CPR): -0.507ns
|
|
Clock Uncertainty: 0.077ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Discrete Jitter (DJ): 0.136ns
|
|
Phase Error (PE): 0.000ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock mlkem_clk_clk_pll rise edge)
|
|
0.000 0.000 r
|
|
clock source latency -6.275 -6.275
|
|
propagated clock network latency
|
|
3.586 -2.690
|
|
SLICE_X91Y121 FDCE 0.000 -2.690 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/C
|
|
SLICE_X91Y121 FDCE (Prop_fdce_C_Q) 0.456 -2.234 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/Q
|
|
net (fo=169, routed) 6.237 4.004 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st[4]
|
|
SLICE_X157Y96 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/I0
|
|
SLICE_X157Y96 LUT5 (Prop_lut5_I0_O) 0.124 4.128 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/O
|
|
net (fo=936, routed) 21.405 25.533 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/sha3_mb_en0
|
|
SLICE_X45Y131 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[909]_i_1/I1
|
|
SLICE_X45Y131 LUT6 (Prop_lut6_I1_O) 0.124 25.657 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[909]_i_1/O
|
|
net (fo=1, routed) 0.000 25.657 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram_n_920
|
|
SLICE_X45Y131 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[909]/D
|
|
------------------------------------------------------------------- -------------------
|
|
|
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(clock mlkem_clk_clk_pll rise edge)
|
|
40.000 40.000 r
|
|
clock source latency -5.674 34.326
|
|
propagated clock network latency
|
|
3.391 37.716
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clock pessimism -0.507 37.209
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|
clock uncertainty -0.077 37.133
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SLICE_X45Y131 FDCE (Setup_fdce_C_D) 0.029 37.162 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[909]
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-------------------------------------------------------------------
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required time 37.162
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|
arrival time -25.657
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-------------------------------------------------------------------
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slack 11.505
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Slack (MET) : 11.519ns (required time - arrival time)
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Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/C
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(rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns})
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Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[956]/D
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(rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns})
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Path Group: mlkem_clk_clk_pll
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Path Type: Setup (Max at Slow Process Corner)
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|
Requirement: 40.000ns (mlkem_clk_clk_pll rise@40.000ns - mlkem_clk_clk_pll rise@0.000ns)
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|
Data Path Delay: 28.387ns (logic 0.704ns (2.480%) route 27.683ns (97.520%))
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Logic Levels: 2 (LUT5=1 LUT6=1)
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|
Clock Path Skew: -0.099ns (DCD - SCD + CPR)
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Destination Clock Delay (DCD): -2.282ns = ( 37.718 - 40.000 )
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|
Source Clock Delay (SCD): -2.690ns
|
|
Clock Pessimism Removal (CPR): -0.507ns
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|
Clock Uncertainty: 0.077ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Discrete Jitter (DJ): 0.136ns
|
|
Phase Error (PE): 0.000ns
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|
|
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Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
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|
------------------------------------------------------------------- -------------------
|
|
(clock mlkem_clk_clk_pll rise edge)
|
|
0.000 0.000 r
|
|
clock source latency -6.275 -6.275
|
|
propagated clock network latency
|
|
3.586 -2.690
|
|
SLICE_X91Y121 FDCE 0.000 -2.690 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/C
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SLICE_X91Y121 FDCE (Prop_fdce_C_Q) 0.456 -2.234 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/Q
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net (fo=169, routed) 6.237 4.004 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st[4]
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SLICE_X157Y96 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/I0
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|
SLICE_X157Y96 LUT5 (Prop_lut5_I0_O) 0.124 4.128 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/O
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|
net (fo=936, routed) 21.445 25.573 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/sha3_mb_en0
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|
SLICE_X44Y132 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[956]_i_1/I1
|
|
SLICE_X44Y132 LUT6 (Prop_lut6_I1_O) 0.124 25.697 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[956]_i_1/O
|
|
net (fo=1, routed) 0.000 25.697 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram_n_478
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|
SLICE_X44Y132 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[956]/D
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock mlkem_clk_clk_pll rise edge)
|
|
40.000 40.000 r
|
|
clock source latency -5.674 34.326
|
|
propagated clock network latency
|
|
3.393 37.718
|
|
clock pessimism -0.507 37.211
|
|
clock uncertainty -0.077 37.135
|
|
SLICE_X44Y132 FDCE (Setup_fdce_C_D) 0.081 37.216 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[956]
|
|
-------------------------------------------------------------------
|
|
required time 37.216
|
|
arrival time -25.697
|
|
-------------------------------------------------------------------
|
|
slack 11.519
|
|
|
|
Slack (MET) : 11.519ns (required time - arrival time)
|
|
Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/C
|
|
(rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns})
|
|
Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[956]/D
|
|
(rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns})
|
|
Path Group: mlkem_clk_clk_pll
|
|
Path Type: Setup (Max at Slow Process Corner)
|
|
Requirement: 40.000ns (mlkem_clk_clk_pll rise@40.000ns - mlkem_clk_clk_pll rise@0.000ns)
|
|
Data Path Delay: 28.387ns (logic 0.704ns (2.480%) route 27.683ns (97.520%))
|
|
Logic Levels: 2 (LUT5=1 LUT6=1)
|
|
Clock Path Skew: -0.099ns (DCD - SCD + CPR)
|
|
Destination Clock Delay (DCD): -2.282ns = ( 37.718 - 40.000 )
|
|
Source Clock Delay (SCD): -2.690ns
|
|
Clock Pessimism Removal (CPR): -0.507ns
|
|
Clock Uncertainty: 0.077ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Discrete Jitter (DJ): 0.136ns
|
|
Phase Error (PE): 0.000ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock mlkem_clk_clk_pll rise edge)
|
|
0.000 0.000 r
|
|
clock source latency -6.275 -6.275
|
|
propagated clock network latency
|
|
3.586 -2.690
|
|
SLICE_X91Y121 FDCE 0.000 -2.690 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/C
|
|
SLICE_X91Y121 FDCE (Prop_fdce_C_Q) 0.456 -2.234 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/Q
|
|
net (fo=169, routed) 6.237 4.004 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st[4]
|
|
SLICE_X157Y96 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/I0
|
|
SLICE_X157Y96 LUT5 (Prop_lut5_I0_O) 0.124 4.128 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/O
|
|
net (fo=936, routed) 21.445 25.573 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/sha3_mb_en0
|
|
SLICE_X44Y132 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[956]_i_1/I1
|
|
SLICE_X44Y132 LUT6 (Prop_lut6_I1_O) 0.124 25.697 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[956]_i_1/O
|
|
net (fo=1, routed) 0.000 25.697 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram_n_478
|
|
SLICE_X44Y132 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[956]/D
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock mlkem_clk_clk_pll rise edge)
|
|
40.000 40.000 r
|
|
clock source latency -5.674 34.326
|
|
propagated clock network latency
|
|
3.393 37.718
|
|
clock pessimism -0.507 37.211
|
|
clock uncertainty -0.077 37.135
|
|
SLICE_X44Y132 FDCE (Setup_fdce_C_D) 0.081 37.216 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[956]
|
|
-------------------------------------------------------------------
|
|
required time 37.216
|
|
arrival time -25.697
|
|
-------------------------------------------------------------------
|
|
slack 11.519
|
|
|
|
|
|
|
|
|