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FallenSigh c4d36515cc fix samples ntt bugs & set PLL & optimize matmul

2026-07-15 10:36:38 +08:00

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cdma_matmul_bridge.sv

fix samples ntt bugs & set PLL & optimize matmul

2026-07-15 10:36:38 +08:00

snix_async_fifo.sv

Initial commit: Loongson FPGA SoC project for 2026 CIC-IEC

2026-06-23 01:22:45 +08:00

snix_axi_cdma_csr.sv

Initial commit: Loongson FPGA SoC project for 2026 CIC-IEC

2026-06-23 01:22:45 +08:00

snix_axi_cdma.sv

Initial commit: Loongson FPGA SoC project for 2026 CIC-IEC

2026-06-23 01:22:45 +08:00

snix_axi_mm2mm.sv

Initial commit: Loongson FPGA SoC project for 2026 CIC-IEC

2026-06-23 01:22:45 +08:00

snix_axil_cdma_mux.sv

fix samples ntt bugs & set PLL & optimize matmul

2026-07-15 10:36:38 +08:00

snix_axis_fifo.sv

Initial commit: Loongson FPGA SoC project for 2026 CIC-IEC

2026-06-23 01:22:45 +08:00

snix_register_slice.sv

Initial commit: Loongson FPGA SoC project for 2026 CIC-IEC

2026-06-23 01:22:45 +08:00

snix_sync_fifo.sv

Initial commit: Loongson FPGA SoC project for 2026 CIC-IEC

2026-06-23 01:22:45 +08:00