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FallenSigh 9202327dd0 perf: batch UART FIFO writes — poll once per 16 bytes instead of per byte ...

uart_puts: burst-write up to 16 chars before polling LSR
uart_puthex: write all 8 hex digits without polling (8 < 16 FIFO depth)

Reduces AXI register reads from ~50 to ~3 per CRC output.
Each saved poll: -1 uncached AXI read (~390ns)

2026-06-26 23:48:23 +08:00

..

bsp

Restore timing + switch to polling + disable CPU interrupts (IE=0)

2026-06-26 01:01:48 +08:00

examples

perf: batch UART FIFO writes — poll once per 16 bytes instead of per byte

2026-06-26 23:48:23 +08:00