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FallenSigh 8e86d8693e Increase DMA FIFO depth to 128 (512 bytes) for burst support

2026-06-25 01:54:07 +08:00

..

ip

Add missing AXI4 ports: awlock/awcache/awprot/arlock/arcache/arprot

2026-06-25 00:53:28 +08:00

config.h

Initial commit: Loongson FPGA SoC project for 2026 CIC-IEC

2026-06-23 01:22:45 +08:00

soc_top.v

Increase DMA FIFO depth to 128 (512 bytes) for burst support

2026-06-25 01:54:07 +08:00