11495 lines
1.1 MiB
11495 lines
1.1 MiB
Copyright 1986-2019 Xilinx, Inc. All Rights Reserved.
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| Tool Version : Vivado v.2019.2 (lin64) Build 2708876 Wed Nov 6 21:39:14 MST 2019
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| Date : Sun Jul 5 23:35:11 2026
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| Host : fedora running 64-bit unknown
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| Command : report_timing -delay_type max -max_paths 100 -sort_by slack -path_type full_clock_expanded -input_pins -file ./vivado_reports/impl_worst_setup_paths.rpt
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| Design : soc_top
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| Device : 7a200t-fbg676
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| Speed File : -1 PRODUCTION 1.23 2018-06-13
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Timing Report
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Slack (MET) : 2.111ns (required time - arrival time)
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Source: u_matmul_axi_slave/mult_inst[0].u_mult/p_reg[1]/C
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(rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
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Destination: u_matmul_axi_slave/crc_reg_reg[18]/D
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(rising edge-triggered cell FDSE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
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Path Group: sys_clk
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Path Type: Setup (Max at Slow Process Corner)
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Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns)
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Data Path Delay: 17.702ns (logic 4.444ns (25.105%) route 13.258ns (74.895%))
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Logic Levels: 18 (CARRY4=3 LUT2=2 LUT5=5 LUT6=8)
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Clock Path Skew: -0.145ns (DCD - SCD + CPR)
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Destination Clock Delay (DCD): -2.703ns = ( 17.297 - 20.000 )
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Source Clock Delay (SCD): -3.025ns
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Clock Pessimism Removal (CPR): -0.468ns
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Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
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Total System Jitter (TSJ): 0.071ns
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Discrete Jitter (DJ): 0.122ns
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Phase Error (PE): 0.000ns
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Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
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------------------------------------------------------------------- -------------------
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(clock sys_clk rise edge) 0.000 0.000 r
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K21 0.000 0.000 r clk (IN)
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net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1
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K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I
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K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O
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net (fo=1, unplaced) 0.584 2.047 pll_clk.u_clk_pll/inst/clk_in1_clk_pll
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r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1
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PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1)
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-6.768 -4.721 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1
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net (fo=1, unplaced) 0.800 -3.921 pll_clk.u_clk_pll/inst/sys_clk_clk_pll
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r pll_clk.u_clk_pll/inst/clkout2_buf/I
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BUFG (Prop_bufg_I_O) 0.096 -3.825 r pll_clk.u_clk_pll/inst/clkout2_buf/O
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net (fo=10994, unplaced) 0.800 -3.025 u_matmul_axi_slave/mult_inst[0].u_mult/sys_clk
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FDRE r u_matmul_axi_slave/mult_inst[0].u_mult/p_reg[1]/C
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------------------------------------------------------------------- -------------------
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FDRE (Prop_fdre_C_Q) 0.456 -2.569 r u_matmul_axi_slave/mult_inst[0].u_mult/p_reg[1]/Q
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net (fo=2, unplaced) 0.481 -2.088 u_matmul_axi_slave/mult_inst[0].u_mult/mult_p[0]_0[1]
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r u_matmul_axi_slave/mult_inst[0].u_mult/b1_c_reg_r1_0_15_0_5_i_20/I0
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LUT2 (Prop_lut2_I0_O) 0.295 -1.793 r u_matmul_axi_slave/mult_inst[0].u_mult/b1_c_reg_r1_0_15_0_5_i_20/O
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net (fo=1, unplaced) 0.000 -1.793 u_matmul_axi_slave/mult_inst[0].u_mult/b1_c_reg_r1_0_15_0_5_i_20_n_0
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r u_matmul_axi_slave/mult_inst[0].u_mult/b1_c_reg_r1_0_15_0_5_i_8/S[1]
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CARRY4 (Prop_carry4_S[1]_CO[3])
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0.550 -1.243 r u_matmul_axi_slave/mult_inst[0].u_mult/b1_c_reg_r1_0_15_0_5_i_8/CO[3]
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net (fo=1, unplaced) 0.009 -1.234 u_matmul_axi_slave/mult_inst[0].u_mult/b1_c_reg_r1_0_15_0_5_i_8_n_0
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r u_matmul_axi_slave/mult_inst[0].u_mult/b1_c_reg_r1_0_15_0_5_i_13/CI
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CARRY4 (Prop_carry4_CI_O[1])
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0.348 -0.886 r u_matmul_axi_slave/mult_inst[0].u_mult/b1_c_reg_r1_0_15_0_5_i_13/O[1]
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net (fo=2, unplaced) 0.622 -0.264 u_matmul_axi_slave/calc_c_result02_out[5]
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r u_matmul_axi_slave/b1_c_reg_r1_0_15_0_5_i_16/I0
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LUT2 (Prop_lut2_I0_O) 0.306 0.042 r u_matmul_axi_slave/b1_c_reg_r1_0_15_0_5_i_16/O
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net (fo=1, unplaced) 0.000 0.042 u_matmul_axi_slave/b1_c_reg_r1_0_15_0_5_i_16_n_0
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r u_matmul_axi_slave/b1_c_reg_r1_0_15_0_5_i_3/S[1]
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CARRY4 (Prop_carry4_S[1]_O[3])
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0.640 0.682 r u_matmul_axi_slave/b1_c_reg_r1_0_15_0_5_i_3/O[3]
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net (fo=15, unplaced) 0.671 1.353 u_matmul_axi_slave/b1_c_reg_r1_0_15_0_5_i_3_n_4
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r u_matmul_axi_slave/crc_reg[12]_i_91/I2
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LUT6 (Prop_lut6_I2_O) 0.307 1.660 r u_matmul_axi_slave/crc_reg[12]_i_91/O
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net (fo=3, unplaced) 0.920 2.580 u_matmul_axi_slave/crc_reg[12]_i_91_n_0
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r u_matmul_axi_slave/crc_reg[12]_i_72/I3
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LUT6 (Prop_lut6_I3_O) 0.124 2.704 r u_matmul_axi_slave/crc_reg[12]_i_72/O
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net (fo=7, unplaced) 0.484 3.188 u_matmul_axi_slave/crc_reg[12]_i_72_n_0
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r u_matmul_axi_slave/crc_reg[12]_i_64/I1
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LUT6 (Prop_lut6_I1_O) 0.124 3.312 r u_matmul_axi_slave/crc_reg[12]_i_64/O
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net (fo=11, unplaced) 0.948 4.260 u_matmul_axi_slave/crc32_word_next_return4[3]
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r u_matmul_axi_slave/crc_reg[12]_i_52/I1
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LUT6 (Prop_lut6_I1_O) 0.124 4.384 r u_matmul_axi_slave/crc_reg[12]_i_52/O
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net (fo=11, unplaced) 1.157 5.541 u_matmul_axi_slave/crc32_word_next_return1[1]
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r u_matmul_axi_slave/crc_reg[12]_i_39/I4
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LUT6 (Prop_lut6_I4_O) 0.124 5.665 r u_matmul_axi_slave/crc_reg[12]_i_39/O
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net (fo=10, unplaced) 0.945 6.610 u_matmul_axi_slave/crc32_word_next0_return10[5]
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r u_matmul_axi_slave/crc_reg[12]_i_22/I1
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LUT5 (Prop_lut5_I1_O) 0.124 6.734 r u_matmul_axi_slave/crc_reg[12]_i_22/O
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net (fo=14, unplaced) 0.953 7.687 u_matmul_axi_slave/crc32_word_next0_return7[7]
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r u_matmul_axi_slave/crc_reg[20]_i_16/I2
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LUT6 (Prop_lut6_I2_O) 0.124 7.811 r u_matmul_axi_slave/crc_reg[20]_i_16/O
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net (fo=11, unplaced) 0.948 8.759 u_matmul_axi_slave/crc32_word_next0_return4[5]
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r u_matmul_axi_slave/crc_reg[31]_i_18/I1
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LUT5 (Prop_lut5_I1_O) 0.124 8.883 r u_matmul_axi_slave/crc_reg[31]_i_18/O
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net (fo=16, unplaced) 0.956 9.839 u_matmul_axi_slave/crc32_word_next0_return1[7]
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r u_matmul_axi_slave/crc_reg[30]_i_10/I1
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LUT5 (Prop_lut5_I1_O) 0.150 9.989 r u_matmul_axi_slave/crc_reg[30]_i_10/O
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net (fo=1, unplaced) 1.111 11.100 u_matmul_axi_slave/crc32_word_next0_return0[22]
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r u_matmul_axi_slave/crc_reg[30]_i_4/I0
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LUT5 (Prop_lut5_I0_O) 0.152 11.252 r u_matmul_axi_slave/crc_reg[30]_i_4/O
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net (fo=1, unplaced) 0.902 12.154 u_matmul_axi_slave/p_0_in0_in[8]
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r u_matmul_axi_slave/crc_reg[30]_i_2/I2
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LUT5 (Prop_lut5_I2_O) 0.124 12.278 r u_matmul_axi_slave/crc_reg[30]_i_2/O
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net (fo=9, unplaced) 1.005 13.283 u_matmul_axi_slave/crc32_word_next1_return1[0]
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r u_matmul_axi_slave/crc_reg[28]_i_2/I0
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LUT6 (Prop_lut6_I0_O) 0.124 13.407 r u_matmul_axi_slave/crc_reg[28]_i_2/O
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net (fo=7, unplaced) 1.146 14.553 u_matmul_axi_slave/crc_reg[28]_i_2_n_0
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r u_matmul_axi_slave/crc_reg[18]_i_1/I1
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LUT6 (Prop_lut6_I1_O) 0.124 14.677 r u_matmul_axi_slave/crc_reg[18]_i_1/O
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net (fo=1, unplaced) 0.000 14.677 u_matmul_axi_slave/crc32_word_next1_return[18]
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FDSE r u_matmul_axi_slave/crc_reg_reg[18]/D
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------------------------------------------------------------------- -------------------
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(clock sys_clk rise edge) 20.000 20.000 r
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K21 0.000 20.000 r clk (IN)
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net (fo=0) 0.000 20.000 pll_clk.u_clk_pll/inst/clk_in1
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K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I
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K21 IBUF (Prop_ibuf_I_O) 1.393 21.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O
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net (fo=1, unplaced) 0.439 21.832 pll_clk.u_clk_pll/inst/clk_in1_clk_pll
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r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1
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PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1)
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-6.040 15.792 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1
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net (fo=1, unplaced) 0.760 16.552 pll_clk.u_clk_pll/inst/sys_clk_clk_pll
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r pll_clk.u_clk_pll/inst/clkout2_buf/I
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BUFG (Prop_bufg_I_O) 0.091 16.643 r pll_clk.u_clk_pll/inst/clkout2_buf/O
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net (fo=10994, unplaced) 0.655 17.297 u_matmul_axi_slave/sys_clk
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FDSE r u_matmul_axi_slave/crc_reg_reg[18]/C
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clock pessimism -0.468 16.830
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clock uncertainty -0.071 16.759
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FDSE (Setup_fdse_C_D) 0.029 16.788 u_matmul_axi_slave/crc_reg_reg[18]
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-------------------------------------------------------------------
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required time 16.788
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arrival time -14.677
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-------------------------------------------------------------------
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slack 2.111
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Slack (MET) : 2.141ns (required time - arrival time)
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Source: u_matmul_axi_slave/mult_inst[0].u_mult/p_reg[1]/C
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(rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
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Destination: u_matmul_axi_slave/crc_reg_reg[17]/D
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(rising edge-triggered cell FDSE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
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Path Group: sys_clk
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Path Type: Setup (Max at Slow Process Corner)
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Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns)
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Data Path Delay: 17.672ns (logic 4.444ns (25.147%) route 13.228ns (74.853%))
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Logic Levels: 18 (CARRY4=3 LUT2=2 LUT4=1 LUT5=5 LUT6=7)
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Clock Path Skew: -0.145ns (DCD - SCD + CPR)
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Destination Clock Delay (DCD): -2.703ns = ( 17.297 - 20.000 )
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Source Clock Delay (SCD): -3.025ns
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Clock Pessimism Removal (CPR): -0.468ns
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Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
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Total System Jitter (TSJ): 0.071ns
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Discrete Jitter (DJ): 0.122ns
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Phase Error (PE): 0.000ns
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Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
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------------------------------------------------------------------- -------------------
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(clock sys_clk rise edge) 0.000 0.000 r
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K21 0.000 0.000 r clk (IN)
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net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1
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K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I
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K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O
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net (fo=1, unplaced) 0.584 2.047 pll_clk.u_clk_pll/inst/clk_in1_clk_pll
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r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1
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PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1)
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-6.768 -4.721 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1
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net (fo=1, unplaced) 0.800 -3.921 pll_clk.u_clk_pll/inst/sys_clk_clk_pll
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r pll_clk.u_clk_pll/inst/clkout2_buf/I
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BUFG (Prop_bufg_I_O) 0.096 -3.825 r pll_clk.u_clk_pll/inst/clkout2_buf/O
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net (fo=10994, unplaced) 0.800 -3.025 u_matmul_axi_slave/mult_inst[0].u_mult/sys_clk
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FDRE r u_matmul_axi_slave/mult_inst[0].u_mult/p_reg[1]/C
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------------------------------------------------------------------- -------------------
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FDRE (Prop_fdre_C_Q) 0.456 -2.569 r u_matmul_axi_slave/mult_inst[0].u_mult/p_reg[1]/Q
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net (fo=2, unplaced) 0.481 -2.088 u_matmul_axi_slave/mult_inst[0].u_mult/mult_p[0]_0[1]
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r u_matmul_axi_slave/mult_inst[0].u_mult/b1_c_reg_r1_0_15_0_5_i_20/I0
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LUT2 (Prop_lut2_I0_O) 0.295 -1.793 r u_matmul_axi_slave/mult_inst[0].u_mult/b1_c_reg_r1_0_15_0_5_i_20/O
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net (fo=1, unplaced) 0.000 -1.793 u_matmul_axi_slave/mult_inst[0].u_mult/b1_c_reg_r1_0_15_0_5_i_20_n_0
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r u_matmul_axi_slave/mult_inst[0].u_mult/b1_c_reg_r1_0_15_0_5_i_8/S[1]
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CARRY4 (Prop_carry4_S[1]_CO[3])
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0.550 -1.243 r u_matmul_axi_slave/mult_inst[0].u_mult/b1_c_reg_r1_0_15_0_5_i_8/CO[3]
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net (fo=1, unplaced) 0.009 -1.234 u_matmul_axi_slave/mult_inst[0].u_mult/b1_c_reg_r1_0_15_0_5_i_8_n_0
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r u_matmul_axi_slave/mult_inst[0].u_mult/b1_c_reg_r1_0_15_0_5_i_13/CI
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CARRY4 (Prop_carry4_CI_O[1])
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0.348 -0.886 r u_matmul_axi_slave/mult_inst[0].u_mult/b1_c_reg_r1_0_15_0_5_i_13/O[1]
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net (fo=2, unplaced) 0.622 -0.264 u_matmul_axi_slave/calc_c_result02_out[5]
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r u_matmul_axi_slave/b1_c_reg_r1_0_15_0_5_i_16/I0
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LUT2 (Prop_lut2_I0_O) 0.306 0.042 r u_matmul_axi_slave/b1_c_reg_r1_0_15_0_5_i_16/O
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net (fo=1, unplaced) 0.000 0.042 u_matmul_axi_slave/b1_c_reg_r1_0_15_0_5_i_16_n_0
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r u_matmul_axi_slave/b1_c_reg_r1_0_15_0_5_i_3/S[1]
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CARRY4 (Prop_carry4_S[1]_O[3])
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0.640 0.682 r u_matmul_axi_slave/b1_c_reg_r1_0_15_0_5_i_3/O[3]
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net (fo=15, unplaced) 0.671 1.353 u_matmul_axi_slave/b1_c_reg_r1_0_15_0_5_i_3_n_4
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r u_matmul_axi_slave/crc_reg[12]_i_91/I2
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LUT6 (Prop_lut6_I2_O) 0.307 1.660 r u_matmul_axi_slave/crc_reg[12]_i_91/O
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net (fo=3, unplaced) 0.920 2.580 u_matmul_axi_slave/crc_reg[12]_i_91_n_0
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r u_matmul_axi_slave/crc_reg[12]_i_72/I3
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LUT6 (Prop_lut6_I3_O) 0.124 2.704 r u_matmul_axi_slave/crc_reg[12]_i_72/O
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net (fo=7, unplaced) 0.484 3.188 u_matmul_axi_slave/crc_reg[12]_i_72_n_0
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r u_matmul_axi_slave/crc_reg[12]_i_64/I1
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LUT6 (Prop_lut6_I1_O) 0.124 3.312 r u_matmul_axi_slave/crc_reg[12]_i_64/O
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net (fo=11, unplaced) 1.010 4.322 u_matmul_axi_slave/crc32_word_next_return4[3]
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r u_matmul_axi_slave/crc_reg[31]_i_30/I1
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LUT6 (Prop_lut6_I1_O) 0.124 4.446 r u_matmul_axi_slave/crc_reg[31]_i_30/O
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net (fo=10, unplaced) 0.945 5.391 u_matmul_axi_slave/crc32_word_next_return1[5]
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r u_matmul_axi_slave/crc_reg[23]_i_18/I1
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LUT5 (Prop_lut5_I1_O) 0.124 5.515 r u_matmul_axi_slave/crc_reg[23]_i_18/O
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net (fo=14, unplaced) 0.953 6.468 u_matmul_axi_slave/crc32_word_next0_return10[7]
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r u_matmul_axi_slave/crc_reg[12]_i_33/I2
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LUT6 (Prop_lut6_I2_O) 0.124 6.592 r u_matmul_axi_slave/crc_reg[12]_i_33/O
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net (fo=11, unplaced) 0.948 7.540 u_matmul_axi_slave/crc32_word_next0_return7[5]
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r u_matmul_axi_slave/crc_reg[23]_i_10/I1
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LUT5 (Prop_lut5_I1_O) 0.124 7.664 r u_matmul_axi_slave/crc_reg[23]_i_10/O
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net (fo=15, unplaced) 0.955 8.619 u_matmul_axi_slave/crc32_word_next0_return4[7]
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r u_matmul_axi_slave/crc_reg[12]_i_32/I1
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LUT4 (Prop_lut4_I1_O) 0.124 8.743 r u_matmul_axi_slave/crc_reg[12]_i_32/O
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net (fo=1, unplaced) 0.902 9.645 u_matmul_axi_slave/crc32_word_next0_return3[21]
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r u_matmul_axi_slave/crc_reg[12]_i_16/I0
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LUT6 (Prop_lut6_I0_O) 0.124 9.769 r u_matmul_axi_slave/crc_reg[12]_i_16/O
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net (fo=2, unplaced) 1.122 10.891 u_matmul_axi_slave/crc_reg[12]_i_16_n_0
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r u_matmul_axi_slave/crc_reg[20]_i_8/I0
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LUT5 (Prop_lut5_I0_O) 0.152 11.043 r u_matmul_axi_slave/crc_reg[20]_i_8/O
|
|
net (fo=6, unplaced) 0.934 11.977 u_matmul_axi_slave/crc32_word_next1_return7[4]
|
|
r u_matmul_axi_slave/crc_reg[20]_i_3/I2
|
|
LUT5 (Prop_lut5_I2_O) 0.150 12.127 r u_matmul_axi_slave/crc_reg[20]_i_3/O
|
|
net (fo=13, unplaced) 1.161 13.288 u_matmul_axi_slave/crc32_word_next1_return4[5]
|
|
r u_matmul_axi_slave/crc_reg[17]_i_2/I1
|
|
LUT6 (Prop_lut6_I1_O) 0.124 13.412 r u_matmul_axi_slave/crc_reg[17]_i_2/O
|
|
net (fo=1, unplaced) 1.111 14.523 u_matmul_axi_slave/crc32_word_next1_return3[23]
|
|
r u_matmul_axi_slave/crc_reg[17]_i_1/I0
|
|
LUT5 (Prop_lut5_I0_O) 0.124 14.647 r u_matmul_axi_slave/crc_reg[17]_i_1/O
|
|
net (fo=1, unplaced) 0.000 14.647 u_matmul_axi_slave/crc32_word_next1_return[17]
|
|
FDSE r u_matmul_axi_slave/crc_reg_reg[17]/D
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock sys_clk rise edge) 20.000 20.000 r
|
|
K21 0.000 20.000 r clk (IN)
|
|
net (fo=0) 0.000 20.000 pll_clk.u_clk_pll/inst/clk_in1
|
|
K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I
|
|
K21 IBUF (Prop_ibuf_I_O) 1.393 21.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O
|
|
net (fo=1, unplaced) 0.439 21.832 pll_clk.u_clk_pll/inst/clk_in1_clk_pll
|
|
r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1
|
|
PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1)
|
|
-6.040 15.792 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1
|
|
net (fo=1, unplaced) 0.760 16.552 pll_clk.u_clk_pll/inst/sys_clk_clk_pll
|
|
r pll_clk.u_clk_pll/inst/clkout2_buf/I
|
|
BUFG (Prop_bufg_I_O) 0.091 16.643 r pll_clk.u_clk_pll/inst/clkout2_buf/O
|
|
net (fo=10994, unplaced) 0.655 17.297 u_matmul_axi_slave/sys_clk
|
|
FDSE r u_matmul_axi_slave/crc_reg_reg[17]/C
|
|
clock pessimism -0.468 16.830
|
|
clock uncertainty -0.071 16.759
|
|
FDSE (Setup_fdse_C_D) 0.029 16.788 u_matmul_axi_slave/crc_reg_reg[17]
|
|
-------------------------------------------------------------------
|
|
required time 16.788
|
|
arrival time -14.647
|
|
-------------------------------------------------------------------
|
|
slack 2.141
|
|
|
|
Slack (MET) : 2.178ns (required time - arrival time)
|
|
Source: u_matmul_axi_slave/mult_inst[0].u_mult/p_reg[1]/C
|
|
(rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Destination: u_matmul_axi_slave/crc_reg_reg[25]/D
|
|
(rising edge-triggered cell FDSE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Path Group: sys_clk
|
|
Path Type: Setup (Max at Slow Process Corner)
|
|
Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns)
|
|
Data Path Delay: 17.635ns (logic 4.418ns (25.052%) route 13.217ns (74.948%))
|
|
Logic Levels: 18 (CARRY4=3 LUT2=2 LUT4=1 LUT5=4 LUT6=8)
|
|
Clock Path Skew: -0.145ns (DCD - SCD + CPR)
|
|
Destination Clock Delay (DCD): -2.703ns = ( 17.297 - 20.000 )
|
|
Source Clock Delay (SCD): -3.025ns
|
|
Clock Pessimism Removal (CPR): -0.468ns
|
|
Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Discrete Jitter (DJ): 0.122ns
|
|
Phase Error (PE): 0.000ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock sys_clk rise edge) 0.000 0.000 r
|
|
K21 0.000 0.000 r clk (IN)
|
|
net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1
|
|
K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I
|
|
K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O
|
|
net (fo=1, unplaced) 0.584 2.047 pll_clk.u_clk_pll/inst/clk_in1_clk_pll
|
|
r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1
|
|
PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1)
|
|
-6.768 -4.721 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1
|
|
net (fo=1, unplaced) 0.800 -3.921 pll_clk.u_clk_pll/inst/sys_clk_clk_pll
|
|
r pll_clk.u_clk_pll/inst/clkout2_buf/I
|
|
BUFG (Prop_bufg_I_O) 0.096 -3.825 r pll_clk.u_clk_pll/inst/clkout2_buf/O
|
|
net (fo=10994, unplaced) 0.800 -3.025 u_matmul_axi_slave/mult_inst[0].u_mult/sys_clk
|
|
FDRE r u_matmul_axi_slave/mult_inst[0].u_mult/p_reg[1]/C
|
|
------------------------------------------------------------------- -------------------
|
|
FDRE (Prop_fdre_C_Q) 0.456 -2.569 r u_matmul_axi_slave/mult_inst[0].u_mult/p_reg[1]/Q
|
|
net (fo=2, unplaced) 0.481 -2.088 u_matmul_axi_slave/mult_inst[0].u_mult/mult_p[0]_0[1]
|
|
r u_matmul_axi_slave/mult_inst[0].u_mult/b1_c_reg_r1_0_15_0_5_i_20/I0
|
|
LUT2 (Prop_lut2_I0_O) 0.295 -1.793 r u_matmul_axi_slave/mult_inst[0].u_mult/b1_c_reg_r1_0_15_0_5_i_20/O
|
|
net (fo=1, unplaced) 0.000 -1.793 u_matmul_axi_slave/mult_inst[0].u_mult/b1_c_reg_r1_0_15_0_5_i_20_n_0
|
|
r u_matmul_axi_slave/mult_inst[0].u_mult/b1_c_reg_r1_0_15_0_5_i_8/S[1]
|
|
CARRY4 (Prop_carry4_S[1]_CO[3])
|
|
0.550 -1.243 r u_matmul_axi_slave/mult_inst[0].u_mult/b1_c_reg_r1_0_15_0_5_i_8/CO[3]
|
|
net (fo=1, unplaced) 0.009 -1.234 u_matmul_axi_slave/mult_inst[0].u_mult/b1_c_reg_r1_0_15_0_5_i_8_n_0
|
|
r u_matmul_axi_slave/mult_inst[0].u_mult/b1_c_reg_r1_0_15_0_5_i_13/CI
|
|
CARRY4 (Prop_carry4_CI_O[1])
|
|
0.348 -0.886 r u_matmul_axi_slave/mult_inst[0].u_mult/b1_c_reg_r1_0_15_0_5_i_13/O[1]
|
|
net (fo=2, unplaced) 0.622 -0.264 u_matmul_axi_slave/calc_c_result02_out[5]
|
|
r u_matmul_axi_slave/b1_c_reg_r1_0_15_0_5_i_16/I0
|
|
LUT2 (Prop_lut2_I0_O) 0.306 0.042 r u_matmul_axi_slave/b1_c_reg_r1_0_15_0_5_i_16/O
|
|
net (fo=1, unplaced) 0.000 0.042 u_matmul_axi_slave/b1_c_reg_r1_0_15_0_5_i_16_n_0
|
|
r u_matmul_axi_slave/b1_c_reg_r1_0_15_0_5_i_3/S[1]
|
|
CARRY4 (Prop_carry4_S[1]_O[3])
|
|
0.640 0.682 r u_matmul_axi_slave/b1_c_reg_r1_0_15_0_5_i_3/O[3]
|
|
net (fo=15, unplaced) 0.671 1.353 u_matmul_axi_slave/b1_c_reg_r1_0_15_0_5_i_3_n_4
|
|
r u_matmul_axi_slave/crc_reg[12]_i_91/I2
|
|
LUT6 (Prop_lut6_I2_O) 0.307 1.660 r u_matmul_axi_slave/crc_reg[12]_i_91/O
|
|
net (fo=3, unplaced) 0.920 2.580 u_matmul_axi_slave/crc_reg[12]_i_91_n_0
|
|
r u_matmul_axi_slave/crc_reg[12]_i_72/I3
|
|
LUT6 (Prop_lut6_I3_O) 0.124 2.704 r u_matmul_axi_slave/crc_reg[12]_i_72/O
|
|
net (fo=7, unplaced) 0.484 3.188 u_matmul_axi_slave/crc_reg[12]_i_72_n_0
|
|
r u_matmul_axi_slave/crc_reg[12]_i_64/I1
|
|
LUT6 (Prop_lut6_I1_O) 0.124 3.312 r u_matmul_axi_slave/crc_reg[12]_i_64/O
|
|
net (fo=11, unplaced) 0.948 4.260 u_matmul_axi_slave/crc32_word_next_return4[3]
|
|
r u_matmul_axi_slave/crc_reg[12]_i_52/I1
|
|
LUT6 (Prop_lut6_I1_O) 0.124 4.384 r u_matmul_axi_slave/crc_reg[12]_i_52/O
|
|
net (fo=11, unplaced) 1.157 5.541 u_matmul_axi_slave/crc32_word_next_return1[1]
|
|
r u_matmul_axi_slave/crc_reg[12]_i_39/I4
|
|
LUT6 (Prop_lut6_I4_O) 0.124 5.665 r u_matmul_axi_slave/crc_reg[12]_i_39/O
|
|
net (fo=10, unplaced) 0.945 6.610 u_matmul_axi_slave/crc32_word_next0_return10[5]
|
|
r u_matmul_axi_slave/crc_reg[12]_i_22/I1
|
|
LUT5 (Prop_lut5_I1_O) 0.124 6.734 r u_matmul_axi_slave/crc_reg[12]_i_22/O
|
|
net (fo=14, unplaced) 0.953 7.687 u_matmul_axi_slave/crc32_word_next0_return7[7]
|
|
r u_matmul_axi_slave/crc_reg[20]_i_16/I2
|
|
LUT6 (Prop_lut6_I2_O) 0.124 7.811 r u_matmul_axi_slave/crc_reg[20]_i_16/O
|
|
net (fo=11, unplaced) 0.948 8.759 u_matmul_axi_slave/crc32_word_next0_return4[5]
|
|
r u_matmul_axi_slave/crc_reg[31]_i_18/I1
|
|
LUT5 (Prop_lut5_I1_O) 0.124 8.883 r u_matmul_axi_slave/crc_reg[31]_i_18/O
|
|
net (fo=16, unplaced) 0.956 9.839 u_matmul_axi_slave/crc32_word_next0_return1[7]
|
|
r u_matmul_axi_slave/crc_reg[20]_i_14/I1
|
|
LUT4 (Prop_lut4_I1_O) 0.124 9.963 r u_matmul_axi_slave/crc_reg[20]_i_14/O
|
|
net (fo=1, unplaced) 0.902 10.865 u_matmul_axi_slave/crc32_word_next0_return0[21]
|
|
r u_matmul_axi_slave/crc_reg[20]_i_6/I0
|
|
LUT6 (Prop_lut6_I0_O) 0.124 10.989 r u_matmul_axi_slave/crc_reg[20]_i_6/O
|
|
net (fo=2, unplaced) 1.122 12.111 u_matmul_axi_slave/p_0_in0_in[4]
|
|
r u_matmul_axi_slave/crc_reg[30]_i_9/I0
|
|
LUT5 (Prop_lut5_I0_O) 0.152 12.263 r u_matmul_axi_slave/crc_reg[30]_i_9/O
|
|
net (fo=7, unplaced) 0.937 13.200 u_matmul_axi_slave/crc32_word_next1_return4[4]
|
|
r u_matmul_axi_slave/crc_reg[29]_i_2/I2
|
|
LUT5 (Prop_lut5_I2_O) 0.124 13.324 r u_matmul_axi_slave/crc_reg[29]_i_2/O
|
|
net (fo=14, unplaced) 1.162 14.486 u_matmul_axi_slave/crc32_word_next1_return1[5]
|
|
r u_matmul_axi_slave/crc_reg[25]_i_1/I1
|
|
LUT6 (Prop_lut6_I1_O) 0.124 14.610 r u_matmul_axi_slave/crc_reg[25]_i_1/O
|
|
net (fo=1, unplaced) 0.000 14.610 u_matmul_axi_slave/crc32_word_next1_return0[23]
|
|
FDSE r u_matmul_axi_slave/crc_reg_reg[25]/D
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock sys_clk rise edge) 20.000 20.000 r
|
|
K21 0.000 20.000 r clk (IN)
|
|
net (fo=0) 0.000 20.000 pll_clk.u_clk_pll/inst/clk_in1
|
|
K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I
|
|
K21 IBUF (Prop_ibuf_I_O) 1.393 21.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O
|
|
net (fo=1, unplaced) 0.439 21.832 pll_clk.u_clk_pll/inst/clk_in1_clk_pll
|
|
r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1
|
|
PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1)
|
|
-6.040 15.792 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1
|
|
net (fo=1, unplaced) 0.760 16.552 pll_clk.u_clk_pll/inst/sys_clk_clk_pll
|
|
r pll_clk.u_clk_pll/inst/clkout2_buf/I
|
|
BUFG (Prop_bufg_I_O) 0.091 16.643 r pll_clk.u_clk_pll/inst/clkout2_buf/O
|
|
net (fo=10994, unplaced) 0.655 17.297 u_matmul_axi_slave/sys_clk
|
|
FDSE r u_matmul_axi_slave/crc_reg_reg[25]/C
|
|
clock pessimism -0.468 16.830
|
|
clock uncertainty -0.071 16.759
|
|
FDSE (Setup_fdse_C_D) 0.029 16.788 u_matmul_axi_slave/crc_reg_reg[25]
|
|
-------------------------------------------------------------------
|
|
required time 16.788
|
|
arrival time -14.610
|
|
-------------------------------------------------------------------
|
|
slack 2.178
|
|
|
|
Slack (MET) : 2.350ns (required time - arrival time)
|
|
Source: u_matmul_axi_slave/mult_inst[0].u_mult/p_reg[1]/C
|
|
(rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Destination: u_matmul_axi_slave/crc_reg_reg[19]/D
|
|
(rising edge-triggered cell FDSE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Path Group: sys_clk
|
|
Path Type: Setup (Max at Slow Process Corner)
|
|
Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns)
|
|
Data Path Delay: 17.463ns (logic 4.444ns (25.448%) route 13.019ns (74.552%))
|
|
Logic Levels: 18 (CARRY4=3 LUT2=2 LUT4=1 LUT5=5 LUT6=7)
|
|
Clock Path Skew: -0.145ns (DCD - SCD + CPR)
|
|
Destination Clock Delay (DCD): -2.703ns = ( 17.297 - 20.000 )
|
|
Source Clock Delay (SCD): -3.025ns
|
|
Clock Pessimism Removal (CPR): -0.468ns
|
|
Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Discrete Jitter (DJ): 0.122ns
|
|
Phase Error (PE): 0.000ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock sys_clk rise edge) 0.000 0.000 r
|
|
K21 0.000 0.000 r clk (IN)
|
|
net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1
|
|
K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I
|
|
K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O
|
|
net (fo=1, unplaced) 0.584 2.047 pll_clk.u_clk_pll/inst/clk_in1_clk_pll
|
|
r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1
|
|
PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1)
|
|
-6.768 -4.721 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1
|
|
net (fo=1, unplaced) 0.800 -3.921 pll_clk.u_clk_pll/inst/sys_clk_clk_pll
|
|
r pll_clk.u_clk_pll/inst/clkout2_buf/I
|
|
BUFG (Prop_bufg_I_O) 0.096 -3.825 r pll_clk.u_clk_pll/inst/clkout2_buf/O
|
|
net (fo=10994, unplaced) 0.800 -3.025 u_matmul_axi_slave/mult_inst[0].u_mult/sys_clk
|
|
FDRE r u_matmul_axi_slave/mult_inst[0].u_mult/p_reg[1]/C
|
|
------------------------------------------------------------------- -------------------
|
|
FDRE (Prop_fdre_C_Q) 0.456 -2.569 r u_matmul_axi_slave/mult_inst[0].u_mult/p_reg[1]/Q
|
|
net (fo=2, unplaced) 0.481 -2.088 u_matmul_axi_slave/mult_inst[0].u_mult/mult_p[0]_0[1]
|
|
r u_matmul_axi_slave/mult_inst[0].u_mult/b1_c_reg_r1_0_15_0_5_i_20/I0
|
|
LUT2 (Prop_lut2_I0_O) 0.295 -1.793 r u_matmul_axi_slave/mult_inst[0].u_mult/b1_c_reg_r1_0_15_0_5_i_20/O
|
|
net (fo=1, unplaced) 0.000 -1.793 u_matmul_axi_slave/mult_inst[0].u_mult/b1_c_reg_r1_0_15_0_5_i_20_n_0
|
|
r u_matmul_axi_slave/mult_inst[0].u_mult/b1_c_reg_r1_0_15_0_5_i_8/S[1]
|
|
CARRY4 (Prop_carry4_S[1]_CO[3])
|
|
0.550 -1.243 r u_matmul_axi_slave/mult_inst[0].u_mult/b1_c_reg_r1_0_15_0_5_i_8/CO[3]
|
|
net (fo=1, unplaced) 0.009 -1.234 u_matmul_axi_slave/mult_inst[0].u_mult/b1_c_reg_r1_0_15_0_5_i_8_n_0
|
|
r u_matmul_axi_slave/mult_inst[0].u_mult/b1_c_reg_r1_0_15_0_5_i_13/CI
|
|
CARRY4 (Prop_carry4_CI_O[1])
|
|
0.348 -0.886 r u_matmul_axi_slave/mult_inst[0].u_mult/b1_c_reg_r1_0_15_0_5_i_13/O[1]
|
|
net (fo=2, unplaced) 0.622 -0.264 u_matmul_axi_slave/calc_c_result02_out[5]
|
|
r u_matmul_axi_slave/b1_c_reg_r1_0_15_0_5_i_16/I0
|
|
LUT2 (Prop_lut2_I0_O) 0.306 0.042 r u_matmul_axi_slave/b1_c_reg_r1_0_15_0_5_i_16/O
|
|
net (fo=1, unplaced) 0.000 0.042 u_matmul_axi_slave/b1_c_reg_r1_0_15_0_5_i_16_n_0
|
|
r u_matmul_axi_slave/b1_c_reg_r1_0_15_0_5_i_3/S[1]
|
|
CARRY4 (Prop_carry4_S[1]_O[3])
|
|
0.640 0.682 r u_matmul_axi_slave/b1_c_reg_r1_0_15_0_5_i_3/O[3]
|
|
net (fo=15, unplaced) 0.671 1.353 u_matmul_axi_slave/b1_c_reg_r1_0_15_0_5_i_3_n_4
|
|
r u_matmul_axi_slave/crc_reg[12]_i_91/I2
|
|
LUT6 (Prop_lut6_I2_O) 0.307 1.660 r u_matmul_axi_slave/crc_reg[12]_i_91/O
|
|
net (fo=3, unplaced) 0.920 2.580 u_matmul_axi_slave/crc_reg[12]_i_91_n_0
|
|
r u_matmul_axi_slave/crc_reg[12]_i_72/I3
|
|
LUT6 (Prop_lut6_I3_O) 0.124 2.704 r u_matmul_axi_slave/crc_reg[12]_i_72/O
|
|
net (fo=7, unplaced) 0.484 3.188 u_matmul_axi_slave/crc_reg[12]_i_72_n_0
|
|
r u_matmul_axi_slave/crc_reg[12]_i_64/I1
|
|
LUT6 (Prop_lut6_I1_O) 0.124 3.312 r u_matmul_axi_slave/crc_reg[12]_i_64/O
|
|
net (fo=11, unplaced) 1.010 4.322 u_matmul_axi_slave/crc32_word_next_return4[3]
|
|
r u_matmul_axi_slave/crc_reg[31]_i_30/I1
|
|
LUT6 (Prop_lut6_I1_O) 0.124 4.446 r u_matmul_axi_slave/crc_reg[31]_i_30/O
|
|
net (fo=10, unplaced) 0.945 5.391 u_matmul_axi_slave/crc32_word_next_return1[5]
|
|
r u_matmul_axi_slave/crc_reg[23]_i_18/I1
|
|
LUT5 (Prop_lut5_I1_O) 0.124 5.515 r u_matmul_axi_slave/crc_reg[23]_i_18/O
|
|
net (fo=14, unplaced) 0.953 6.468 u_matmul_axi_slave/crc32_word_next0_return10[7]
|
|
r u_matmul_axi_slave/crc_reg[12]_i_33/I2
|
|
LUT6 (Prop_lut6_I2_O) 0.124 6.592 r u_matmul_axi_slave/crc_reg[12]_i_33/O
|
|
net (fo=11, unplaced) 0.948 7.540 u_matmul_axi_slave/crc32_word_next0_return7[5]
|
|
r u_matmul_axi_slave/crc_reg[23]_i_10/I1
|
|
LUT5 (Prop_lut5_I1_O) 0.124 7.664 r u_matmul_axi_slave/crc_reg[23]_i_10/O
|
|
net (fo=15, unplaced) 0.955 8.619 u_matmul_axi_slave/crc32_word_next0_return4[7]
|
|
r u_matmul_axi_slave/crc_reg[12]_i_32/I1
|
|
LUT4 (Prop_lut4_I1_O) 0.124 8.743 r u_matmul_axi_slave/crc_reg[12]_i_32/O
|
|
net (fo=1, unplaced) 0.902 9.645 u_matmul_axi_slave/crc32_word_next0_return3[21]
|
|
r u_matmul_axi_slave/crc_reg[12]_i_16/I0
|
|
LUT6 (Prop_lut6_I0_O) 0.124 9.769 r u_matmul_axi_slave/crc_reg[12]_i_16/O
|
|
net (fo=2, unplaced) 1.122 10.891 u_matmul_axi_slave/crc_reg[12]_i_16_n_0
|
|
r u_matmul_axi_slave/crc_reg[20]_i_8/I0
|
|
LUT5 (Prop_lut5_I0_O) 0.152 11.043 r u_matmul_axi_slave/crc_reg[20]_i_8/O
|
|
net (fo=6, unplaced) 0.934 11.977 u_matmul_axi_slave/crc32_word_next1_return7[4]
|
|
r u_matmul_axi_slave/crc_reg[20]_i_3/I2
|
|
LUT5 (Prop_lut5_I2_O) 0.150 12.127 r u_matmul_axi_slave/crc_reg[20]_i_3/O
|
|
net (fo=13, unplaced) 0.952 13.079 u_matmul_axi_slave/crc32_word_next1_return4[5]
|
|
r u_matmul_axi_slave/crc_reg[19]_i_3/I2
|
|
LUT5 (Prop_lut5_I2_O) 0.124 13.203 r u_matmul_axi_slave/crc_reg[19]_i_3/O
|
|
net (fo=1, unplaced) 1.111 14.314 u_matmul_axi_slave/crc_reg[19]_i_3_n_0
|
|
r u_matmul_axi_slave/crc_reg[19]_i_1/I1
|
|
LUT6 (Prop_lut6_I1_O) 0.124 14.438 r u_matmul_axi_slave/crc_reg[19]_i_1/O
|
|
net (fo=1, unplaced) 0.000 14.438 u_matmul_axi_slave/crc32_word_next1_return[19]
|
|
FDSE r u_matmul_axi_slave/crc_reg_reg[19]/D
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock sys_clk rise edge) 20.000 20.000 r
|
|
K21 0.000 20.000 r clk (IN)
|
|
net (fo=0) 0.000 20.000 pll_clk.u_clk_pll/inst/clk_in1
|
|
K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I
|
|
K21 IBUF (Prop_ibuf_I_O) 1.393 21.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O
|
|
net (fo=1, unplaced) 0.439 21.832 pll_clk.u_clk_pll/inst/clk_in1_clk_pll
|
|
r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1
|
|
PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1)
|
|
-6.040 15.792 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1
|
|
net (fo=1, unplaced) 0.760 16.552 pll_clk.u_clk_pll/inst/sys_clk_clk_pll
|
|
r pll_clk.u_clk_pll/inst/clkout2_buf/I
|
|
BUFG (Prop_bufg_I_O) 0.091 16.643 r pll_clk.u_clk_pll/inst/clkout2_buf/O
|
|
net (fo=10994, unplaced) 0.655 17.297 u_matmul_axi_slave/sys_clk
|
|
FDSE r u_matmul_axi_slave/crc_reg_reg[19]/C
|
|
clock pessimism -0.468 16.830
|
|
clock uncertainty -0.071 16.759
|
|
FDSE (Setup_fdse_C_D) 0.029 16.788 u_matmul_axi_slave/crc_reg_reg[19]
|
|
-------------------------------------------------------------------
|
|
required time 16.788
|
|
arrival time -14.438
|
|
-------------------------------------------------------------------
|
|
slack 2.350
|
|
|
|
Slack (MET) : 2.438ns (required time - arrival time)
|
|
Source: u_matmul_axi_slave/mult_inst[0].u_mult/p_reg[1]/C
|
|
(rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Destination: u_matmul_axi_slave/crc_reg_reg[13]/D
|
|
(rising edge-triggered cell FDSE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Path Group: sys_clk
|
|
Path Type: Setup (Max at Slow Process Corner)
|
|
Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns)
|
|
Data Path Delay: 17.375ns (logic 4.418ns (25.427%) route 12.957ns (74.573%))
|
|
Logic Levels: 18 (CARRY4=3 LUT2=2 LUT4=2 LUT5=4 LUT6=7)
|
|
Clock Path Skew: -0.145ns (DCD - SCD + CPR)
|
|
Destination Clock Delay (DCD): -2.703ns = ( 17.297 - 20.000 )
|
|
Source Clock Delay (SCD): -3.025ns
|
|
Clock Pessimism Removal (CPR): -0.468ns
|
|
Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Discrete Jitter (DJ): 0.122ns
|
|
Phase Error (PE): 0.000ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock sys_clk rise edge) 0.000 0.000 r
|
|
K21 0.000 0.000 r clk (IN)
|
|
net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1
|
|
K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I
|
|
K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O
|
|
net (fo=1, unplaced) 0.584 2.047 pll_clk.u_clk_pll/inst/clk_in1_clk_pll
|
|
r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1
|
|
PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1)
|
|
-6.768 -4.721 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1
|
|
net (fo=1, unplaced) 0.800 -3.921 pll_clk.u_clk_pll/inst/sys_clk_clk_pll
|
|
r pll_clk.u_clk_pll/inst/clkout2_buf/I
|
|
BUFG (Prop_bufg_I_O) 0.096 -3.825 r pll_clk.u_clk_pll/inst/clkout2_buf/O
|
|
net (fo=10994, unplaced) 0.800 -3.025 u_matmul_axi_slave/mult_inst[0].u_mult/sys_clk
|
|
FDRE r u_matmul_axi_slave/mult_inst[0].u_mult/p_reg[1]/C
|
|
------------------------------------------------------------------- -------------------
|
|
FDRE (Prop_fdre_C_Q) 0.456 -2.569 r u_matmul_axi_slave/mult_inst[0].u_mult/p_reg[1]/Q
|
|
net (fo=2, unplaced) 0.481 -2.088 u_matmul_axi_slave/mult_inst[0].u_mult/mult_p[0]_0[1]
|
|
r u_matmul_axi_slave/mult_inst[0].u_mult/b1_c_reg_r1_0_15_0_5_i_20/I0
|
|
LUT2 (Prop_lut2_I0_O) 0.295 -1.793 r u_matmul_axi_slave/mult_inst[0].u_mult/b1_c_reg_r1_0_15_0_5_i_20/O
|
|
net (fo=1, unplaced) 0.000 -1.793 u_matmul_axi_slave/mult_inst[0].u_mult/b1_c_reg_r1_0_15_0_5_i_20_n_0
|
|
r u_matmul_axi_slave/mult_inst[0].u_mult/b1_c_reg_r1_0_15_0_5_i_8/S[1]
|
|
CARRY4 (Prop_carry4_S[1]_CO[3])
|
|
0.550 -1.243 r u_matmul_axi_slave/mult_inst[0].u_mult/b1_c_reg_r1_0_15_0_5_i_8/CO[3]
|
|
net (fo=1, unplaced) 0.009 -1.234 u_matmul_axi_slave/mult_inst[0].u_mult/b1_c_reg_r1_0_15_0_5_i_8_n_0
|
|
r u_matmul_axi_slave/mult_inst[0].u_mult/b1_c_reg_r1_0_15_0_5_i_13/CI
|
|
CARRY4 (Prop_carry4_CI_O[1])
|
|
0.348 -0.886 r u_matmul_axi_slave/mult_inst[0].u_mult/b1_c_reg_r1_0_15_0_5_i_13/O[1]
|
|
net (fo=2, unplaced) 0.622 -0.264 u_matmul_axi_slave/calc_c_result02_out[5]
|
|
r u_matmul_axi_slave/b1_c_reg_r1_0_15_0_5_i_16/I0
|
|
LUT2 (Prop_lut2_I0_O) 0.306 0.042 r u_matmul_axi_slave/b1_c_reg_r1_0_15_0_5_i_16/O
|
|
net (fo=1, unplaced) 0.000 0.042 u_matmul_axi_slave/b1_c_reg_r1_0_15_0_5_i_16_n_0
|
|
r u_matmul_axi_slave/b1_c_reg_r1_0_15_0_5_i_3/S[1]
|
|
CARRY4 (Prop_carry4_S[1]_O[3])
|
|
0.640 0.682 r u_matmul_axi_slave/b1_c_reg_r1_0_15_0_5_i_3/O[3]
|
|
net (fo=15, unplaced) 0.671 1.353 u_matmul_axi_slave/b1_c_reg_r1_0_15_0_5_i_3_n_4
|
|
r u_matmul_axi_slave/crc_reg[12]_i_91/I2
|
|
LUT6 (Prop_lut6_I2_O) 0.307 1.660 r u_matmul_axi_slave/crc_reg[12]_i_91/O
|
|
net (fo=3, unplaced) 0.920 2.580 u_matmul_axi_slave/crc_reg[12]_i_91_n_0
|
|
r u_matmul_axi_slave/crc_reg[12]_i_72/I3
|
|
LUT6 (Prop_lut6_I3_O) 0.124 2.704 r u_matmul_axi_slave/crc_reg[12]_i_72/O
|
|
net (fo=7, unplaced) 0.484 3.188 u_matmul_axi_slave/crc_reg[12]_i_72_n_0
|
|
r u_matmul_axi_slave/crc_reg[12]_i_64/I1
|
|
LUT6 (Prop_lut6_I1_O) 0.124 3.312 r u_matmul_axi_slave/crc_reg[12]_i_64/O
|
|
net (fo=11, unplaced) 0.948 4.260 u_matmul_axi_slave/crc32_word_next_return4[3]
|
|
r u_matmul_axi_slave/crc_reg[12]_i_52/I1
|
|
LUT6 (Prop_lut6_I1_O) 0.124 4.384 r u_matmul_axi_slave/crc_reg[12]_i_52/O
|
|
net (fo=11, unplaced) 1.157 5.541 u_matmul_axi_slave/crc32_word_next_return1[1]
|
|
r u_matmul_axi_slave/crc_reg[12]_i_39/I4
|
|
LUT6 (Prop_lut6_I4_O) 0.124 5.665 r u_matmul_axi_slave/crc_reg[12]_i_39/O
|
|
net (fo=10, unplaced) 0.945 6.610 u_matmul_axi_slave/crc32_word_next0_return10[5]
|
|
r u_matmul_axi_slave/crc_reg[12]_i_22/I1
|
|
LUT5 (Prop_lut5_I1_O) 0.124 6.734 r u_matmul_axi_slave/crc_reg[12]_i_22/O
|
|
net (fo=14, unplaced) 0.953 7.687 u_matmul_axi_slave/crc32_word_next0_return7[7]
|
|
r u_matmul_axi_slave/crc_reg[20]_i_16/I2
|
|
LUT6 (Prop_lut6_I2_O) 0.124 7.811 r u_matmul_axi_slave/crc_reg[20]_i_16/O
|
|
net (fo=11, unplaced) 0.948 8.759 u_matmul_axi_slave/crc32_word_next0_return4[5]
|
|
r u_matmul_axi_slave/crc_reg[31]_i_18/I1
|
|
LUT5 (Prop_lut5_I1_O) 0.124 8.883 r u_matmul_axi_slave/crc_reg[31]_i_18/O
|
|
net (fo=16, unplaced) 0.956 9.839 u_matmul_axi_slave/crc32_word_next0_return1[7]
|
|
r u_matmul_axi_slave/crc_reg[20]_i_14/I1
|
|
LUT4 (Prop_lut4_I1_O) 0.124 9.963 r u_matmul_axi_slave/crc_reg[20]_i_14/O
|
|
net (fo=1, unplaced) 0.902 10.865 u_matmul_axi_slave/crc32_word_next0_return0[21]
|
|
r u_matmul_axi_slave/crc_reg[20]_i_6/I0
|
|
LUT6 (Prop_lut6_I0_O) 0.124 10.989 r u_matmul_axi_slave/crc_reg[20]_i_6/O
|
|
net (fo=2, unplaced) 1.122 12.111 u_matmul_axi_slave/p_0_in0_in[4]
|
|
r u_matmul_axi_slave/crc_reg[30]_i_9/I0
|
|
LUT5 (Prop_lut5_I0_O) 0.152 12.263 r u_matmul_axi_slave/crc_reg[30]_i_9/O
|
|
net (fo=7, unplaced) 0.937 13.200 u_matmul_axi_slave/crc32_word_next1_return4[4]
|
|
r u_matmul_axi_slave/crc_reg[13]_i_2/I2
|
|
LUT5 (Prop_lut5_I2_O) 0.124 13.324 r u_matmul_axi_slave/crc_reg[13]_i_2/O
|
|
net (fo=1, unplaced) 0.902 14.226 u_matmul_axi_slave/p_0_in4_in[13]
|
|
r u_matmul_axi_slave/crc_reg[13]_i_1/I0
|
|
LUT4 (Prop_lut4_I0_O) 0.124 14.350 r u_matmul_axi_slave/crc_reg[13]_i_1/O
|
|
net (fo=1, unplaced) 0.000 14.350 u_matmul_axi_slave/crc32_word_next1_return[13]
|
|
FDSE r u_matmul_axi_slave/crc_reg_reg[13]/D
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock sys_clk rise edge) 20.000 20.000 r
|
|
K21 0.000 20.000 r clk (IN)
|
|
net (fo=0) 0.000 20.000 pll_clk.u_clk_pll/inst/clk_in1
|
|
K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I
|
|
K21 IBUF (Prop_ibuf_I_O) 1.393 21.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O
|
|
net (fo=1, unplaced) 0.439 21.832 pll_clk.u_clk_pll/inst/clk_in1_clk_pll
|
|
r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1
|
|
PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1)
|
|
-6.040 15.792 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1
|
|
net (fo=1, unplaced) 0.760 16.552 pll_clk.u_clk_pll/inst/sys_clk_clk_pll
|
|
r pll_clk.u_clk_pll/inst/clkout2_buf/I
|
|
BUFG (Prop_bufg_I_O) 0.091 16.643 r pll_clk.u_clk_pll/inst/clkout2_buf/O
|
|
net (fo=10994, unplaced) 0.655 17.297 u_matmul_axi_slave/sys_clk
|
|
FDSE r u_matmul_axi_slave/crc_reg_reg[13]/C
|
|
clock pessimism -0.468 16.830
|
|
clock uncertainty -0.071 16.759
|
|
FDSE (Setup_fdse_C_D) 0.029 16.788 u_matmul_axi_slave/crc_reg_reg[13]
|
|
-------------------------------------------------------------------
|
|
required time 16.788
|
|
arrival time -14.350
|
|
-------------------------------------------------------------------
|
|
slack 2.438
|
|
|
|
Slack (MET) : 2.557ns (required time - arrival time)
|
|
Source: u_matmul_axi_slave/mult_inst[0].u_mult/p_reg[1]/C
|
|
(rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Destination: u_matmul_axi_slave/crc_reg_reg[26]/D
|
|
(rising edge-triggered cell FDSE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Path Group: sys_clk
|
|
Path Type: Setup (Max at Slow Process Corner)
|
|
Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns)
|
|
Data Path Delay: 17.256ns (logic 4.444ns (25.753%) route 12.812ns (74.247%))
|
|
Logic Levels: 18 (CARRY4=3 LUT2=2 LUT5=5 LUT6=8)
|
|
Clock Path Skew: -0.145ns (DCD - SCD + CPR)
|
|
Destination Clock Delay (DCD): -2.703ns = ( 17.297 - 20.000 )
|
|
Source Clock Delay (SCD): -3.025ns
|
|
Clock Pessimism Removal (CPR): -0.468ns
|
|
Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Discrete Jitter (DJ): 0.122ns
|
|
Phase Error (PE): 0.000ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock sys_clk rise edge) 0.000 0.000 r
|
|
K21 0.000 0.000 r clk (IN)
|
|
net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1
|
|
K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I
|
|
K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O
|
|
net (fo=1, unplaced) 0.584 2.047 pll_clk.u_clk_pll/inst/clk_in1_clk_pll
|
|
r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1
|
|
PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1)
|
|
-6.768 -4.721 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1
|
|
net (fo=1, unplaced) 0.800 -3.921 pll_clk.u_clk_pll/inst/sys_clk_clk_pll
|
|
r pll_clk.u_clk_pll/inst/clkout2_buf/I
|
|
BUFG (Prop_bufg_I_O) 0.096 -3.825 r pll_clk.u_clk_pll/inst/clkout2_buf/O
|
|
net (fo=10994, unplaced) 0.800 -3.025 u_matmul_axi_slave/mult_inst[0].u_mult/sys_clk
|
|
FDRE r u_matmul_axi_slave/mult_inst[0].u_mult/p_reg[1]/C
|
|
------------------------------------------------------------------- -------------------
|
|
FDRE (Prop_fdre_C_Q) 0.456 -2.569 r u_matmul_axi_slave/mult_inst[0].u_mult/p_reg[1]/Q
|
|
net (fo=2, unplaced) 0.481 -2.088 u_matmul_axi_slave/mult_inst[0].u_mult/mult_p[0]_0[1]
|
|
r u_matmul_axi_slave/mult_inst[0].u_mult/b1_c_reg_r1_0_15_0_5_i_20/I0
|
|
LUT2 (Prop_lut2_I0_O) 0.295 -1.793 r u_matmul_axi_slave/mult_inst[0].u_mult/b1_c_reg_r1_0_15_0_5_i_20/O
|
|
net (fo=1, unplaced) 0.000 -1.793 u_matmul_axi_slave/mult_inst[0].u_mult/b1_c_reg_r1_0_15_0_5_i_20_n_0
|
|
r u_matmul_axi_slave/mult_inst[0].u_mult/b1_c_reg_r1_0_15_0_5_i_8/S[1]
|
|
CARRY4 (Prop_carry4_S[1]_CO[3])
|
|
0.550 -1.243 r u_matmul_axi_slave/mult_inst[0].u_mult/b1_c_reg_r1_0_15_0_5_i_8/CO[3]
|
|
net (fo=1, unplaced) 0.009 -1.234 u_matmul_axi_slave/mult_inst[0].u_mult/b1_c_reg_r1_0_15_0_5_i_8_n_0
|
|
r u_matmul_axi_slave/mult_inst[0].u_mult/b1_c_reg_r1_0_15_0_5_i_13/CI
|
|
CARRY4 (Prop_carry4_CI_O[1])
|
|
0.348 -0.886 r u_matmul_axi_slave/mult_inst[0].u_mult/b1_c_reg_r1_0_15_0_5_i_13/O[1]
|
|
net (fo=2, unplaced) 0.622 -0.264 u_matmul_axi_slave/calc_c_result02_out[5]
|
|
r u_matmul_axi_slave/b1_c_reg_r1_0_15_0_5_i_16/I0
|
|
LUT2 (Prop_lut2_I0_O) 0.306 0.042 r u_matmul_axi_slave/b1_c_reg_r1_0_15_0_5_i_16/O
|
|
net (fo=1, unplaced) 0.000 0.042 u_matmul_axi_slave/b1_c_reg_r1_0_15_0_5_i_16_n_0
|
|
r u_matmul_axi_slave/b1_c_reg_r1_0_15_0_5_i_3/S[1]
|
|
CARRY4 (Prop_carry4_S[1]_O[3])
|
|
0.640 0.682 r u_matmul_axi_slave/b1_c_reg_r1_0_15_0_5_i_3/O[3]
|
|
net (fo=15, unplaced) 0.671 1.353 u_matmul_axi_slave/b1_c_reg_r1_0_15_0_5_i_3_n_4
|
|
r u_matmul_axi_slave/crc_reg[12]_i_91/I2
|
|
LUT6 (Prop_lut6_I2_O) 0.307 1.660 r u_matmul_axi_slave/crc_reg[12]_i_91/O
|
|
net (fo=3, unplaced) 0.920 2.580 u_matmul_axi_slave/crc_reg[12]_i_91_n_0
|
|
r u_matmul_axi_slave/crc_reg[12]_i_72/I3
|
|
LUT6 (Prop_lut6_I3_O) 0.124 2.704 r u_matmul_axi_slave/crc_reg[12]_i_72/O
|
|
net (fo=7, unplaced) 0.484 3.188 u_matmul_axi_slave/crc_reg[12]_i_72_n_0
|
|
r u_matmul_axi_slave/crc_reg[12]_i_64/I1
|
|
LUT6 (Prop_lut6_I1_O) 0.124 3.312 r u_matmul_axi_slave/crc_reg[12]_i_64/O
|
|
net (fo=11, unplaced) 0.948 4.260 u_matmul_axi_slave/crc32_word_next_return4[3]
|
|
r u_matmul_axi_slave/crc_reg[12]_i_52/I1
|
|
LUT6 (Prop_lut6_I1_O) 0.124 4.384 r u_matmul_axi_slave/crc_reg[12]_i_52/O
|
|
net (fo=11, unplaced) 1.157 5.541 u_matmul_axi_slave/crc32_word_next_return1[1]
|
|
r u_matmul_axi_slave/crc_reg[12]_i_39/I4
|
|
LUT6 (Prop_lut6_I4_O) 0.124 5.665 r u_matmul_axi_slave/crc_reg[12]_i_39/O
|
|
net (fo=10, unplaced) 0.945 6.610 u_matmul_axi_slave/crc32_word_next0_return10[5]
|
|
r u_matmul_axi_slave/crc_reg[12]_i_22/I1
|
|
LUT5 (Prop_lut5_I1_O) 0.124 6.734 r u_matmul_axi_slave/crc_reg[12]_i_22/O
|
|
net (fo=14, unplaced) 0.953 7.687 u_matmul_axi_slave/crc32_word_next0_return7[7]
|
|
r u_matmul_axi_slave/crc_reg[20]_i_16/I2
|
|
LUT6 (Prop_lut6_I2_O) 0.124 7.811 r u_matmul_axi_slave/crc_reg[20]_i_16/O
|
|
net (fo=11, unplaced) 0.948 8.759 u_matmul_axi_slave/crc32_word_next0_return4[5]
|
|
r u_matmul_axi_slave/crc_reg[31]_i_18/I1
|
|
LUT5 (Prop_lut5_I1_O) 0.124 8.883 r u_matmul_axi_slave/crc_reg[31]_i_18/O
|
|
net (fo=16, unplaced) 0.956 9.839 u_matmul_axi_slave/crc32_word_next0_return1[7]
|
|
r u_matmul_axi_slave/crc_reg[30]_i_10/I1
|
|
LUT5 (Prop_lut5_I1_O) 0.150 9.989 r u_matmul_axi_slave/crc_reg[30]_i_10/O
|
|
net (fo=1, unplaced) 1.111 11.100 u_matmul_axi_slave/crc32_word_next0_return0[22]
|
|
r u_matmul_axi_slave/crc_reg[30]_i_4/I0
|
|
LUT5 (Prop_lut5_I0_O) 0.152 11.252 r u_matmul_axi_slave/crc_reg[30]_i_4/O
|
|
net (fo=1, unplaced) 0.902 12.154 u_matmul_axi_slave/p_0_in0_in[8]
|
|
r u_matmul_axi_slave/crc_reg[30]_i_2/I2
|
|
LUT5 (Prop_lut5_I2_O) 0.124 12.278 r u_matmul_axi_slave/crc_reg[30]_i_2/O
|
|
net (fo=9, unplaced) 1.005 13.283 u_matmul_axi_slave/crc32_word_next1_return1[0]
|
|
r u_matmul_axi_slave/crc_reg[28]_i_2/I0
|
|
LUT6 (Prop_lut6_I0_O) 0.124 13.407 r u_matmul_axi_slave/crc_reg[28]_i_2/O
|
|
net (fo=7, unplaced) 0.700 14.107 u_matmul_axi_slave/crc_reg[28]_i_2_n_0
|
|
r u_matmul_axi_slave/crc_reg[26]_i_1/I2
|
|
LUT6 (Prop_lut6_I2_O) 0.124 14.231 r u_matmul_axi_slave/crc_reg[26]_i_1/O
|
|
net (fo=1, unplaced) 0.000 14.231 u_matmul_axi_slave/crc32_word_next1_return0[24]
|
|
FDSE r u_matmul_axi_slave/crc_reg_reg[26]/D
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock sys_clk rise edge) 20.000 20.000 r
|
|
K21 0.000 20.000 r clk (IN)
|
|
net (fo=0) 0.000 20.000 pll_clk.u_clk_pll/inst/clk_in1
|
|
K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I
|
|
K21 IBUF (Prop_ibuf_I_O) 1.393 21.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O
|
|
net (fo=1, unplaced) 0.439 21.832 pll_clk.u_clk_pll/inst/clk_in1_clk_pll
|
|
r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1
|
|
PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1)
|
|
-6.040 15.792 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1
|
|
net (fo=1, unplaced) 0.760 16.552 pll_clk.u_clk_pll/inst/sys_clk_clk_pll
|
|
r pll_clk.u_clk_pll/inst/clkout2_buf/I
|
|
BUFG (Prop_bufg_I_O) 0.091 16.643 r pll_clk.u_clk_pll/inst/clkout2_buf/O
|
|
net (fo=10994, unplaced) 0.655 17.297 u_matmul_axi_slave/sys_clk
|
|
FDSE r u_matmul_axi_slave/crc_reg_reg[26]/C
|
|
clock pessimism -0.468 16.830
|
|
clock uncertainty -0.071 16.759
|
|
FDSE (Setup_fdse_C_D) 0.029 16.788 u_matmul_axi_slave/crc_reg_reg[26]
|
|
-------------------------------------------------------------------
|
|
required time 16.788
|
|
arrival time -14.231
|
|
-------------------------------------------------------------------
|
|
slack 2.557
|
|
|
|
Slack (MET) : 2.624ns (required time - arrival time)
|
|
Source: u_matmul_axi_slave/mult_inst[0].u_mult/p_reg[1]/C
|
|
(rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Destination: u_matmul_axi_slave/crc_reg_reg[22]/D
|
|
(rising edge-triggered cell FDSE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Path Group: sys_clk
|
|
Path Type: Setup (Max at Slow Process Corner)
|
|
Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns)
|
|
Data Path Delay: 17.189ns (logic 4.418ns (25.702%) route 12.771ns (74.298%))
|
|
Logic Levels: 18 (CARRY4=3 LUT2=2 LUT4=1 LUT5=5 LUT6=7)
|
|
Clock Path Skew: -0.145ns (DCD - SCD + CPR)
|
|
Destination Clock Delay (DCD): -2.703ns = ( 17.297 - 20.000 )
|
|
Source Clock Delay (SCD): -3.025ns
|
|
Clock Pessimism Removal (CPR): -0.468ns
|
|
Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Discrete Jitter (DJ): 0.122ns
|
|
Phase Error (PE): 0.000ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock sys_clk rise edge) 0.000 0.000 r
|
|
K21 0.000 0.000 r clk (IN)
|
|
net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1
|
|
K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I
|
|
K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O
|
|
net (fo=1, unplaced) 0.584 2.047 pll_clk.u_clk_pll/inst/clk_in1_clk_pll
|
|
r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1
|
|
PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1)
|
|
-6.768 -4.721 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1
|
|
net (fo=1, unplaced) 0.800 -3.921 pll_clk.u_clk_pll/inst/sys_clk_clk_pll
|
|
r pll_clk.u_clk_pll/inst/clkout2_buf/I
|
|
BUFG (Prop_bufg_I_O) 0.096 -3.825 r pll_clk.u_clk_pll/inst/clkout2_buf/O
|
|
net (fo=10994, unplaced) 0.800 -3.025 u_matmul_axi_slave/mult_inst[0].u_mult/sys_clk
|
|
FDRE r u_matmul_axi_slave/mult_inst[0].u_mult/p_reg[1]/C
|
|
------------------------------------------------------------------- -------------------
|
|
FDRE (Prop_fdre_C_Q) 0.456 -2.569 r u_matmul_axi_slave/mult_inst[0].u_mult/p_reg[1]/Q
|
|
net (fo=2, unplaced) 0.481 -2.088 u_matmul_axi_slave/mult_inst[0].u_mult/mult_p[0]_0[1]
|
|
r u_matmul_axi_slave/mult_inst[0].u_mult/b1_c_reg_r1_0_15_0_5_i_20/I0
|
|
LUT2 (Prop_lut2_I0_O) 0.295 -1.793 r u_matmul_axi_slave/mult_inst[0].u_mult/b1_c_reg_r1_0_15_0_5_i_20/O
|
|
net (fo=1, unplaced) 0.000 -1.793 u_matmul_axi_slave/mult_inst[0].u_mult/b1_c_reg_r1_0_15_0_5_i_20_n_0
|
|
r u_matmul_axi_slave/mult_inst[0].u_mult/b1_c_reg_r1_0_15_0_5_i_8/S[1]
|
|
CARRY4 (Prop_carry4_S[1]_CO[3])
|
|
0.550 -1.243 r u_matmul_axi_slave/mult_inst[0].u_mult/b1_c_reg_r1_0_15_0_5_i_8/CO[3]
|
|
net (fo=1, unplaced) 0.009 -1.234 u_matmul_axi_slave/mult_inst[0].u_mult/b1_c_reg_r1_0_15_0_5_i_8_n_0
|
|
r u_matmul_axi_slave/mult_inst[0].u_mult/b1_c_reg_r1_0_15_0_5_i_13/CI
|
|
CARRY4 (Prop_carry4_CI_O[1])
|
|
0.348 -0.886 r u_matmul_axi_slave/mult_inst[0].u_mult/b1_c_reg_r1_0_15_0_5_i_13/O[1]
|
|
net (fo=2, unplaced) 0.622 -0.264 u_matmul_axi_slave/calc_c_result02_out[5]
|
|
r u_matmul_axi_slave/b1_c_reg_r1_0_15_0_5_i_16/I0
|
|
LUT2 (Prop_lut2_I0_O) 0.306 0.042 r u_matmul_axi_slave/b1_c_reg_r1_0_15_0_5_i_16/O
|
|
net (fo=1, unplaced) 0.000 0.042 u_matmul_axi_slave/b1_c_reg_r1_0_15_0_5_i_16_n_0
|
|
r u_matmul_axi_slave/b1_c_reg_r1_0_15_0_5_i_3/S[1]
|
|
CARRY4 (Prop_carry4_S[1]_O[3])
|
|
0.640 0.682 r u_matmul_axi_slave/b1_c_reg_r1_0_15_0_5_i_3/O[3]
|
|
net (fo=15, unplaced) 0.671 1.353 u_matmul_axi_slave/b1_c_reg_r1_0_15_0_5_i_3_n_4
|
|
r u_matmul_axi_slave/crc_reg[12]_i_91/I2
|
|
LUT6 (Prop_lut6_I2_O) 0.307 1.660 r u_matmul_axi_slave/crc_reg[12]_i_91/O
|
|
net (fo=3, unplaced) 0.920 2.580 u_matmul_axi_slave/crc_reg[12]_i_91_n_0
|
|
r u_matmul_axi_slave/crc_reg[12]_i_72/I3
|
|
LUT6 (Prop_lut6_I3_O) 0.124 2.704 r u_matmul_axi_slave/crc_reg[12]_i_72/O
|
|
net (fo=7, unplaced) 0.484 3.188 u_matmul_axi_slave/crc_reg[12]_i_72_n_0
|
|
r u_matmul_axi_slave/crc_reg[12]_i_64/I1
|
|
LUT6 (Prop_lut6_I1_O) 0.124 3.312 r u_matmul_axi_slave/crc_reg[12]_i_64/O
|
|
net (fo=11, unplaced) 0.948 4.260 u_matmul_axi_slave/crc32_word_next_return4[3]
|
|
r u_matmul_axi_slave/crc_reg[12]_i_52/I1
|
|
LUT6 (Prop_lut6_I1_O) 0.124 4.384 r u_matmul_axi_slave/crc_reg[12]_i_52/O
|
|
net (fo=11, unplaced) 1.157 5.541 u_matmul_axi_slave/crc32_word_next_return1[1]
|
|
r u_matmul_axi_slave/crc_reg[12]_i_39/I4
|
|
LUT6 (Prop_lut6_I4_O) 0.124 5.665 r u_matmul_axi_slave/crc_reg[12]_i_39/O
|
|
net (fo=10, unplaced) 0.945 6.610 u_matmul_axi_slave/crc32_word_next0_return10[5]
|
|
r u_matmul_axi_slave/crc_reg[12]_i_22/I1
|
|
LUT5 (Prop_lut5_I1_O) 0.124 6.734 r u_matmul_axi_slave/crc_reg[12]_i_22/O
|
|
net (fo=14, unplaced) 0.953 7.687 u_matmul_axi_slave/crc32_word_next0_return7[7]
|
|
r u_matmul_axi_slave/crc_reg[20]_i_16/I2
|
|
LUT6 (Prop_lut6_I2_O) 0.124 7.811 r u_matmul_axi_slave/crc_reg[20]_i_16/O
|
|
net (fo=11, unplaced) 0.948 8.759 u_matmul_axi_slave/crc32_word_next0_return4[5]
|
|
r u_matmul_axi_slave/crc_reg[31]_i_18/I1
|
|
LUT5 (Prop_lut5_I1_O) 0.124 8.883 r u_matmul_axi_slave/crc_reg[31]_i_18/O
|
|
net (fo=16, unplaced) 0.956 9.839 u_matmul_axi_slave/crc32_word_next0_return1[7]
|
|
r u_matmul_axi_slave/crc_reg[20]_i_14/I1
|
|
LUT4 (Prop_lut4_I1_O) 0.124 9.963 r u_matmul_axi_slave/crc_reg[20]_i_14/O
|
|
net (fo=1, unplaced) 0.902 10.865 u_matmul_axi_slave/crc32_word_next0_return0[21]
|
|
r u_matmul_axi_slave/crc_reg[20]_i_6/I0
|
|
LUT6 (Prop_lut6_I0_O) 0.124 10.989 r u_matmul_axi_slave/crc_reg[20]_i_6/O
|
|
net (fo=2, unplaced) 1.122 12.111 u_matmul_axi_slave/p_0_in0_in[4]
|
|
r u_matmul_axi_slave/crc_reg[30]_i_9/I0
|
|
LUT5 (Prop_lut5_I0_O) 0.152 12.263 r u_matmul_axi_slave/crc_reg[30]_i_9/O
|
|
net (fo=7, unplaced) 0.937 13.200 u_matmul_axi_slave/crc32_word_next1_return4[4]
|
|
r u_matmul_axi_slave/crc_reg[29]_i_2/I2
|
|
LUT5 (Prop_lut5_I2_O) 0.124 13.324 r u_matmul_axi_slave/crc_reg[29]_i_2/O
|
|
net (fo=14, unplaced) 0.716 14.040 u_matmul_axi_slave/crc32_word_next1_return1[5]
|
|
r u_matmul_axi_slave/crc_reg[22]_i_1/I1
|
|
LUT5 (Prop_lut5_I1_O) 0.124 14.164 r u_matmul_axi_slave/crc_reg[22]_i_1/O
|
|
net (fo=1, unplaced) 0.000 14.164 u_matmul_axi_slave/crc32_word_next1_return[22]
|
|
FDSE r u_matmul_axi_slave/crc_reg_reg[22]/D
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock sys_clk rise edge) 20.000 20.000 r
|
|
K21 0.000 20.000 r clk (IN)
|
|
net (fo=0) 0.000 20.000 pll_clk.u_clk_pll/inst/clk_in1
|
|
K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I
|
|
K21 IBUF (Prop_ibuf_I_O) 1.393 21.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O
|
|
net (fo=1, unplaced) 0.439 21.832 pll_clk.u_clk_pll/inst/clk_in1_clk_pll
|
|
r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1
|
|
PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1)
|
|
-6.040 15.792 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1
|
|
net (fo=1, unplaced) 0.760 16.552 pll_clk.u_clk_pll/inst/sys_clk_clk_pll
|
|
r pll_clk.u_clk_pll/inst/clkout2_buf/I
|
|
BUFG (Prop_bufg_I_O) 0.091 16.643 r pll_clk.u_clk_pll/inst/clkout2_buf/O
|
|
net (fo=10994, unplaced) 0.655 17.297 u_matmul_axi_slave/sys_clk
|
|
FDSE r u_matmul_axi_slave/crc_reg_reg[22]/C
|
|
clock pessimism -0.468 16.830
|
|
clock uncertainty -0.071 16.759
|
|
FDSE (Setup_fdse_C_D) 0.029 16.788 u_matmul_axi_slave/crc_reg_reg[22]
|
|
-------------------------------------------------------------------
|
|
required time 16.788
|
|
arrival time -14.164
|
|
-------------------------------------------------------------------
|
|
slack 2.624
|
|
|
|
Slack (MET) : 2.635ns (required time - arrival time)
|
|
Source: u_matmul_axi_slave/mult_inst[0].u_mult/p_reg[1]/C
|
|
(rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Destination: u_matmul_axi_slave/crc_reg_reg[5]/D
|
|
(rising edge-triggered cell FDSE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Path Group: sys_clk
|
|
Path Type: Setup (Max at Slow Process Corner)
|
|
Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns)
|
|
Data Path Delay: 17.178ns (logic 4.446ns (25.882%) route 12.732ns (74.118%))
|
|
Logic Levels: 18 (CARRY4=3 LUT2=2 LUT4=2 LUT5=5 LUT6=6)
|
|
Clock Path Skew: -0.145ns (DCD - SCD + CPR)
|
|
Destination Clock Delay (DCD): -2.703ns = ( 17.297 - 20.000 )
|
|
Source Clock Delay (SCD): -3.025ns
|
|
Clock Pessimism Removal (CPR): -0.468ns
|
|
Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Discrete Jitter (DJ): 0.122ns
|
|
Phase Error (PE): 0.000ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock sys_clk rise edge) 0.000 0.000 r
|
|
K21 0.000 0.000 r clk (IN)
|
|
net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1
|
|
K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I
|
|
K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O
|
|
net (fo=1, unplaced) 0.584 2.047 pll_clk.u_clk_pll/inst/clk_in1_clk_pll
|
|
r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1
|
|
PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1)
|
|
-6.768 -4.721 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1
|
|
net (fo=1, unplaced) 0.800 -3.921 pll_clk.u_clk_pll/inst/sys_clk_clk_pll
|
|
r pll_clk.u_clk_pll/inst/clkout2_buf/I
|
|
BUFG (Prop_bufg_I_O) 0.096 -3.825 r pll_clk.u_clk_pll/inst/clkout2_buf/O
|
|
net (fo=10994, unplaced) 0.800 -3.025 u_matmul_axi_slave/mult_inst[0].u_mult/sys_clk
|
|
FDRE r u_matmul_axi_slave/mult_inst[0].u_mult/p_reg[1]/C
|
|
------------------------------------------------------------------- -------------------
|
|
FDRE (Prop_fdre_C_Q) 0.456 -2.569 r u_matmul_axi_slave/mult_inst[0].u_mult/p_reg[1]/Q
|
|
net (fo=2, unplaced) 0.481 -2.088 u_matmul_axi_slave/mult_inst[0].u_mult/mult_p[0]_0[1]
|
|
r u_matmul_axi_slave/mult_inst[0].u_mult/b1_c_reg_r1_0_15_0_5_i_20/I0
|
|
LUT2 (Prop_lut2_I0_O) 0.295 -1.793 r u_matmul_axi_slave/mult_inst[0].u_mult/b1_c_reg_r1_0_15_0_5_i_20/O
|
|
net (fo=1, unplaced) 0.000 -1.793 u_matmul_axi_slave/mult_inst[0].u_mult/b1_c_reg_r1_0_15_0_5_i_20_n_0
|
|
r u_matmul_axi_slave/mult_inst[0].u_mult/b1_c_reg_r1_0_15_0_5_i_8/S[1]
|
|
CARRY4 (Prop_carry4_S[1]_CO[3])
|
|
0.550 -1.243 r u_matmul_axi_slave/mult_inst[0].u_mult/b1_c_reg_r1_0_15_0_5_i_8/CO[3]
|
|
net (fo=1, unplaced) 0.009 -1.234 u_matmul_axi_slave/mult_inst[0].u_mult/b1_c_reg_r1_0_15_0_5_i_8_n_0
|
|
r u_matmul_axi_slave/mult_inst[0].u_mult/b1_c_reg_r1_0_15_0_5_i_13/CI
|
|
CARRY4 (Prop_carry4_CI_O[1])
|
|
0.348 -0.886 r u_matmul_axi_slave/mult_inst[0].u_mult/b1_c_reg_r1_0_15_0_5_i_13/O[1]
|
|
net (fo=2, unplaced) 0.622 -0.264 u_matmul_axi_slave/calc_c_result02_out[5]
|
|
r u_matmul_axi_slave/b1_c_reg_r1_0_15_0_5_i_16/I0
|
|
LUT2 (Prop_lut2_I0_O) 0.306 0.042 r u_matmul_axi_slave/b1_c_reg_r1_0_15_0_5_i_16/O
|
|
net (fo=1, unplaced) 0.000 0.042 u_matmul_axi_slave/b1_c_reg_r1_0_15_0_5_i_16_n_0
|
|
r u_matmul_axi_slave/b1_c_reg_r1_0_15_0_5_i_3/S[1]
|
|
CARRY4 (Prop_carry4_S[1]_O[3])
|
|
0.640 0.682 r u_matmul_axi_slave/b1_c_reg_r1_0_15_0_5_i_3/O[3]
|
|
net (fo=15, unplaced) 0.671 1.353 u_matmul_axi_slave/b1_c_reg_r1_0_15_0_5_i_3_n_4
|
|
r u_matmul_axi_slave/crc_reg[12]_i_91/I2
|
|
LUT6 (Prop_lut6_I2_O) 0.307 1.660 r u_matmul_axi_slave/crc_reg[12]_i_91/O
|
|
net (fo=3, unplaced) 0.920 2.580 u_matmul_axi_slave/crc_reg[12]_i_91_n_0
|
|
r u_matmul_axi_slave/crc_reg[12]_i_72/I3
|
|
LUT6 (Prop_lut6_I3_O) 0.124 2.704 r u_matmul_axi_slave/crc_reg[12]_i_72/O
|
|
net (fo=7, unplaced) 0.484 3.188 u_matmul_axi_slave/crc_reg[12]_i_72_n_0
|
|
r u_matmul_axi_slave/crc_reg[12]_i_64/I1
|
|
LUT6 (Prop_lut6_I1_O) 0.124 3.312 r u_matmul_axi_slave/crc_reg[12]_i_64/O
|
|
net (fo=11, unplaced) 1.010 4.322 u_matmul_axi_slave/crc32_word_next_return4[3]
|
|
r u_matmul_axi_slave/crc_reg[31]_i_30/I1
|
|
LUT6 (Prop_lut6_I1_O) 0.124 4.446 r u_matmul_axi_slave/crc_reg[31]_i_30/O
|
|
net (fo=10, unplaced) 0.945 5.391 u_matmul_axi_slave/crc32_word_next_return1[5]
|
|
r u_matmul_axi_slave/crc_reg[23]_i_18/I1
|
|
LUT5 (Prop_lut5_I1_O) 0.124 5.515 r u_matmul_axi_slave/crc_reg[23]_i_18/O
|
|
net (fo=14, unplaced) 0.953 6.468 u_matmul_axi_slave/crc32_word_next0_return10[7]
|
|
r u_matmul_axi_slave/crc_reg[12]_i_33/I2
|
|
LUT6 (Prop_lut6_I2_O) 0.124 6.592 r u_matmul_axi_slave/crc_reg[12]_i_33/O
|
|
net (fo=11, unplaced) 0.948 7.540 u_matmul_axi_slave/crc32_word_next0_return7[5]
|
|
r u_matmul_axi_slave/crc_reg[23]_i_10/I1
|
|
LUT5 (Prop_lut5_I1_O) 0.124 7.664 r u_matmul_axi_slave/crc_reg[23]_i_10/O
|
|
net (fo=15, unplaced) 0.955 8.619 u_matmul_axi_slave/crc32_word_next0_return4[7]
|
|
r u_matmul_axi_slave/crc_reg[12]_i_32/I1
|
|
LUT4 (Prop_lut4_I1_O) 0.124 8.743 r u_matmul_axi_slave/crc_reg[12]_i_32/O
|
|
net (fo=1, unplaced) 0.902 9.645 u_matmul_axi_slave/crc32_word_next0_return3[21]
|
|
r u_matmul_axi_slave/crc_reg[12]_i_16/I0
|
|
LUT6 (Prop_lut6_I0_O) 0.124 9.769 r u_matmul_axi_slave/crc_reg[12]_i_16/O
|
|
net (fo=2, unplaced) 1.122 10.891 u_matmul_axi_slave/crc_reg[12]_i_16_n_0
|
|
r u_matmul_axi_slave/crc_reg[20]_i_8/I0
|
|
LUT5 (Prop_lut5_I0_O) 0.152 11.043 r u_matmul_axi_slave/crc_reg[20]_i_8/O
|
|
net (fo=6, unplaced) 0.934 11.977 u_matmul_axi_slave/crc32_word_next1_return7[4]
|
|
r u_matmul_axi_slave/crc_reg[5]_i_3/I2
|
|
LUT5 (Prop_lut5_I2_O) 0.124 12.101 r u_matmul_axi_slave/crc_reg[5]_i_3/O
|
|
net (fo=1, unplaced) 0.665 12.766 u_matmul_axi_slave/crc_reg[5]_i_3_n_0
|
|
r u_matmul_axi_slave/crc_reg[5]_i_2/I0
|
|
LUT4 (Prop_lut4_I0_O) 0.124 12.890 r u_matmul_axi_slave/crc_reg[5]_i_2/O
|
|
net (fo=1, unplaced) 1.111 14.001 u_matmul_axi_slave/p_0_in4_in[5]
|
|
r u_matmul_axi_slave/crc_reg[5]_i_1/I0
|
|
LUT5 (Prop_lut5_I0_O) 0.152 14.153 r u_matmul_axi_slave/crc_reg[5]_i_1/O
|
|
net (fo=1, unplaced) 0.000 14.153 u_matmul_axi_slave/crc32_word_next1_return[5]
|
|
FDSE r u_matmul_axi_slave/crc_reg_reg[5]/D
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock sys_clk rise edge) 20.000 20.000 r
|
|
K21 0.000 20.000 r clk (IN)
|
|
net (fo=0) 0.000 20.000 pll_clk.u_clk_pll/inst/clk_in1
|
|
K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I
|
|
K21 IBUF (Prop_ibuf_I_O) 1.393 21.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O
|
|
net (fo=1, unplaced) 0.439 21.832 pll_clk.u_clk_pll/inst/clk_in1_clk_pll
|
|
r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1
|
|
PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1)
|
|
-6.040 15.792 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1
|
|
net (fo=1, unplaced) 0.760 16.552 pll_clk.u_clk_pll/inst/sys_clk_clk_pll
|
|
r pll_clk.u_clk_pll/inst/clkout2_buf/I
|
|
BUFG (Prop_bufg_I_O) 0.091 16.643 r pll_clk.u_clk_pll/inst/clkout2_buf/O
|
|
net (fo=10994, unplaced) 0.655 17.297 u_matmul_axi_slave/sys_clk
|
|
FDSE r u_matmul_axi_slave/crc_reg_reg[5]/C
|
|
clock pessimism -0.468 16.830
|
|
clock uncertainty -0.071 16.759
|
|
FDSE (Setup_fdse_C_D) 0.029 16.788 u_matmul_axi_slave/crc_reg_reg[5]
|
|
-------------------------------------------------------------------
|
|
required time 16.788
|
|
arrival time -14.153
|
|
-------------------------------------------------------------------
|
|
slack 2.635
|
|
|
|
Slack (MET) : 2.675ns (required time - arrival time)
|
|
Source: u_matmul_axi_slave/mult_inst[0].u_mult/p_reg[1]/C
|
|
(rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Destination: u_matmul_axi_slave/crc_reg_reg[15]/D
|
|
(rising edge-triggered cell FDSE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Path Group: sys_clk
|
|
Path Type: Setup (Max at Slow Process Corner)
|
|
Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns)
|
|
Data Path Delay: 17.138ns (logic 4.418ns (25.779%) route 12.720ns (74.221%))
|
|
Logic Levels: 18 (CARRY4=3 LUT2=2 LUT3=1 LUT4=1 LUT5=3 LUT6=8)
|
|
Clock Path Skew: -0.145ns (DCD - SCD + CPR)
|
|
Destination Clock Delay (DCD): -2.703ns = ( 17.297 - 20.000 )
|
|
Source Clock Delay (SCD): -3.025ns
|
|
Clock Pessimism Removal (CPR): -0.468ns
|
|
Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Discrete Jitter (DJ): 0.122ns
|
|
Phase Error (PE): 0.000ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock sys_clk rise edge) 0.000 0.000 r
|
|
K21 0.000 0.000 r clk (IN)
|
|
net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1
|
|
K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I
|
|
K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O
|
|
net (fo=1, unplaced) 0.584 2.047 pll_clk.u_clk_pll/inst/clk_in1_clk_pll
|
|
r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1
|
|
PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1)
|
|
-6.768 -4.721 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1
|
|
net (fo=1, unplaced) 0.800 -3.921 pll_clk.u_clk_pll/inst/sys_clk_clk_pll
|
|
r pll_clk.u_clk_pll/inst/clkout2_buf/I
|
|
BUFG (Prop_bufg_I_O) 0.096 -3.825 r pll_clk.u_clk_pll/inst/clkout2_buf/O
|
|
net (fo=10994, unplaced) 0.800 -3.025 u_matmul_axi_slave/mult_inst[0].u_mult/sys_clk
|
|
FDRE r u_matmul_axi_slave/mult_inst[0].u_mult/p_reg[1]/C
|
|
------------------------------------------------------------------- -------------------
|
|
FDRE (Prop_fdre_C_Q) 0.456 -2.569 r u_matmul_axi_slave/mult_inst[0].u_mult/p_reg[1]/Q
|
|
net (fo=2, unplaced) 0.481 -2.088 u_matmul_axi_slave/mult_inst[0].u_mult/mult_p[0]_0[1]
|
|
r u_matmul_axi_slave/mult_inst[0].u_mult/b1_c_reg_r1_0_15_0_5_i_20/I0
|
|
LUT2 (Prop_lut2_I0_O) 0.295 -1.793 r u_matmul_axi_slave/mult_inst[0].u_mult/b1_c_reg_r1_0_15_0_5_i_20/O
|
|
net (fo=1, unplaced) 0.000 -1.793 u_matmul_axi_slave/mult_inst[0].u_mult/b1_c_reg_r1_0_15_0_5_i_20_n_0
|
|
r u_matmul_axi_slave/mult_inst[0].u_mult/b1_c_reg_r1_0_15_0_5_i_8/S[1]
|
|
CARRY4 (Prop_carry4_S[1]_CO[3])
|
|
0.550 -1.243 r u_matmul_axi_slave/mult_inst[0].u_mult/b1_c_reg_r1_0_15_0_5_i_8/CO[3]
|
|
net (fo=1, unplaced) 0.009 -1.234 u_matmul_axi_slave/mult_inst[0].u_mult/b1_c_reg_r1_0_15_0_5_i_8_n_0
|
|
r u_matmul_axi_slave/mult_inst[0].u_mult/b1_c_reg_r1_0_15_0_5_i_13/CI
|
|
CARRY4 (Prop_carry4_CI_O[1])
|
|
0.348 -0.886 r u_matmul_axi_slave/mult_inst[0].u_mult/b1_c_reg_r1_0_15_0_5_i_13/O[1]
|
|
net (fo=2, unplaced) 0.622 -0.264 u_matmul_axi_slave/calc_c_result02_out[5]
|
|
r u_matmul_axi_slave/b1_c_reg_r1_0_15_0_5_i_16/I0
|
|
LUT2 (Prop_lut2_I0_O) 0.306 0.042 r u_matmul_axi_slave/b1_c_reg_r1_0_15_0_5_i_16/O
|
|
net (fo=1, unplaced) 0.000 0.042 u_matmul_axi_slave/b1_c_reg_r1_0_15_0_5_i_16_n_0
|
|
r u_matmul_axi_slave/b1_c_reg_r1_0_15_0_5_i_3/S[1]
|
|
CARRY4 (Prop_carry4_S[1]_O[3])
|
|
0.640 0.682 r u_matmul_axi_slave/b1_c_reg_r1_0_15_0_5_i_3/O[3]
|
|
net (fo=15, unplaced) 0.671 1.353 u_matmul_axi_slave/b1_c_reg_r1_0_15_0_5_i_3_n_4
|
|
r u_matmul_axi_slave/crc_reg[12]_i_91/I2
|
|
LUT6 (Prop_lut6_I2_O) 0.307 1.660 r u_matmul_axi_slave/crc_reg[12]_i_91/O
|
|
net (fo=3, unplaced) 0.920 2.580 u_matmul_axi_slave/crc_reg[12]_i_91_n_0
|
|
r u_matmul_axi_slave/crc_reg[12]_i_72/I3
|
|
LUT6 (Prop_lut6_I3_O) 0.124 2.704 r u_matmul_axi_slave/crc_reg[12]_i_72/O
|
|
net (fo=7, unplaced) 0.484 3.188 u_matmul_axi_slave/crc_reg[12]_i_72_n_0
|
|
r u_matmul_axi_slave/crc_reg[12]_i_64/I1
|
|
LUT6 (Prop_lut6_I1_O) 0.124 3.312 r u_matmul_axi_slave/crc_reg[12]_i_64/O
|
|
net (fo=11, unplaced) 0.948 4.260 u_matmul_axi_slave/crc32_word_next_return4[3]
|
|
r u_matmul_axi_slave/crc_reg[12]_i_52/I1
|
|
LUT6 (Prop_lut6_I1_O) 0.124 4.384 r u_matmul_axi_slave/crc_reg[12]_i_52/O
|
|
net (fo=11, unplaced) 1.157 5.541 u_matmul_axi_slave/crc32_word_next_return1[1]
|
|
r u_matmul_axi_slave/crc_reg[12]_i_39/I4
|
|
LUT6 (Prop_lut6_I4_O) 0.124 5.665 r u_matmul_axi_slave/crc_reg[12]_i_39/O
|
|
net (fo=10, unplaced) 0.945 6.610 u_matmul_axi_slave/crc32_word_next0_return10[5]
|
|
r u_matmul_axi_slave/crc_reg[12]_i_22/I1
|
|
LUT5 (Prop_lut5_I1_O) 0.124 6.734 r u_matmul_axi_slave/crc_reg[12]_i_22/O
|
|
net (fo=14, unplaced) 0.953 7.687 u_matmul_axi_slave/crc32_word_next0_return7[7]
|
|
r u_matmul_axi_slave/crc_reg[20]_i_16/I2
|
|
LUT6 (Prop_lut6_I2_O) 0.124 7.811 r u_matmul_axi_slave/crc_reg[20]_i_16/O
|
|
net (fo=11, unplaced) 0.948 8.759 u_matmul_axi_slave/crc32_word_next0_return4[5]
|
|
r u_matmul_axi_slave/crc_reg[31]_i_18/I1
|
|
LUT5 (Prop_lut5_I1_O) 0.124 8.883 r u_matmul_axi_slave/crc_reg[31]_i_18/O
|
|
net (fo=16, unplaced) 0.956 9.839 u_matmul_axi_slave/crc32_word_next0_return1[7]
|
|
r u_matmul_axi_slave/crc_reg[20]_i_14/I1
|
|
LUT4 (Prop_lut4_I1_O) 0.124 9.963 r u_matmul_axi_slave/crc_reg[20]_i_14/O
|
|
net (fo=1, unplaced) 0.902 10.865 u_matmul_axi_slave/crc32_word_next0_return0[21]
|
|
r u_matmul_axi_slave/crc_reg[20]_i_6/I0
|
|
LUT6 (Prop_lut6_I0_O) 0.124 10.989 r u_matmul_axi_slave/crc_reg[20]_i_6/O
|
|
net (fo=2, unplaced) 1.122 12.111 u_matmul_axi_slave/p_0_in0_in[4]
|
|
r u_matmul_axi_slave/crc_reg[30]_i_9/I0
|
|
LUT5 (Prop_lut5_I0_O) 0.152 12.263 r u_matmul_axi_slave/crc_reg[30]_i_9/O
|
|
net (fo=7, unplaced) 0.937 13.200 u_matmul_axi_slave/crc32_word_next1_return4[4]
|
|
r u_matmul_axi_slave/crc_reg[15]_i_2/I0
|
|
LUT3 (Prop_lut3_I0_O) 0.124 13.324 r u_matmul_axi_slave/crc_reg[15]_i_2/O
|
|
net (fo=1, unplaced) 0.665 13.989 u_matmul_axi_slave/crc_reg[15]_i_2_n_0
|
|
r u_matmul_axi_slave/crc_reg[15]_i_1/I0
|
|
LUT6 (Prop_lut6_I0_O) 0.124 14.113 r u_matmul_axi_slave/crc_reg[15]_i_1/O
|
|
net (fo=1, unplaced) 0.000 14.113 u_matmul_axi_slave/crc32_word_next1_return[15]
|
|
FDSE r u_matmul_axi_slave/crc_reg_reg[15]/D
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock sys_clk rise edge) 20.000 20.000 r
|
|
K21 0.000 20.000 r clk (IN)
|
|
net (fo=0) 0.000 20.000 pll_clk.u_clk_pll/inst/clk_in1
|
|
K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I
|
|
K21 IBUF (Prop_ibuf_I_O) 1.393 21.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O
|
|
net (fo=1, unplaced) 0.439 21.832 pll_clk.u_clk_pll/inst/clk_in1_clk_pll
|
|
r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1
|
|
PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1)
|
|
-6.040 15.792 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1
|
|
net (fo=1, unplaced) 0.760 16.552 pll_clk.u_clk_pll/inst/sys_clk_clk_pll
|
|
r pll_clk.u_clk_pll/inst/clkout2_buf/I
|
|
BUFG (Prop_bufg_I_O) 0.091 16.643 r pll_clk.u_clk_pll/inst/clkout2_buf/O
|
|
net (fo=10994, unplaced) 0.655 17.297 u_matmul_axi_slave/sys_clk
|
|
FDSE r u_matmul_axi_slave/crc_reg_reg[15]/C
|
|
clock pessimism -0.468 16.830
|
|
clock uncertainty -0.071 16.759
|
|
FDSE (Setup_fdse_C_D) 0.029 16.788 u_matmul_axi_slave/crc_reg_reg[15]
|
|
-------------------------------------------------------------------
|
|
required time 16.788
|
|
arrival time -14.113
|
|
-------------------------------------------------------------------
|
|
slack 2.675
|
|
|
|
Slack (MET) : 2.753ns (required time - arrival time)
|
|
Source: u_matmul_axi_slave/mult_inst[0].u_mult/p_reg[1]/C
|
|
(rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Destination: u_matmul_axi_slave/crc_reg_reg[21]/D
|
|
(rising edge-triggered cell FDSE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Path Group: sys_clk
|
|
Path Type: Setup (Max at Slow Process Corner)
|
|
Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns)
|
|
Data Path Delay: 17.060ns (logic 4.416ns (25.885%) route 12.644ns (74.115%))
|
|
Logic Levels: 18 (CARRY4=3 LUT2=2 LUT3=1 LUT4=2 LUT5=2 LUT6=8)
|
|
Clock Path Skew: -0.145ns (DCD - SCD + CPR)
|
|
Destination Clock Delay (DCD): -2.703ns = ( 17.297 - 20.000 )
|
|
Source Clock Delay (SCD): -3.025ns
|
|
Clock Pessimism Removal (CPR): -0.468ns
|
|
Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Discrete Jitter (DJ): 0.122ns
|
|
Phase Error (PE): 0.000ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock sys_clk rise edge) 0.000 0.000 r
|
|
K21 0.000 0.000 r clk (IN)
|
|
net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1
|
|
K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I
|
|
K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O
|
|
net (fo=1, unplaced) 0.584 2.047 pll_clk.u_clk_pll/inst/clk_in1_clk_pll
|
|
r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1
|
|
PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1)
|
|
-6.768 -4.721 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1
|
|
net (fo=1, unplaced) 0.800 -3.921 pll_clk.u_clk_pll/inst/sys_clk_clk_pll
|
|
r pll_clk.u_clk_pll/inst/clkout2_buf/I
|
|
BUFG (Prop_bufg_I_O) 0.096 -3.825 r pll_clk.u_clk_pll/inst/clkout2_buf/O
|
|
net (fo=10994, unplaced) 0.800 -3.025 u_matmul_axi_slave/mult_inst[0].u_mult/sys_clk
|
|
FDRE r u_matmul_axi_slave/mult_inst[0].u_mult/p_reg[1]/C
|
|
------------------------------------------------------------------- -------------------
|
|
FDRE (Prop_fdre_C_Q) 0.456 -2.569 r u_matmul_axi_slave/mult_inst[0].u_mult/p_reg[1]/Q
|
|
net (fo=2, unplaced) 0.481 -2.088 u_matmul_axi_slave/mult_inst[0].u_mult/mult_p[0]_0[1]
|
|
r u_matmul_axi_slave/mult_inst[0].u_mult/b1_c_reg_r1_0_15_0_5_i_20/I0
|
|
LUT2 (Prop_lut2_I0_O) 0.295 -1.793 r u_matmul_axi_slave/mult_inst[0].u_mult/b1_c_reg_r1_0_15_0_5_i_20/O
|
|
net (fo=1, unplaced) 0.000 -1.793 u_matmul_axi_slave/mult_inst[0].u_mult/b1_c_reg_r1_0_15_0_5_i_20_n_0
|
|
r u_matmul_axi_slave/mult_inst[0].u_mult/b1_c_reg_r1_0_15_0_5_i_8/S[1]
|
|
CARRY4 (Prop_carry4_S[1]_CO[3])
|
|
0.550 -1.243 r u_matmul_axi_slave/mult_inst[0].u_mult/b1_c_reg_r1_0_15_0_5_i_8/CO[3]
|
|
net (fo=1, unplaced) 0.009 -1.234 u_matmul_axi_slave/mult_inst[0].u_mult/b1_c_reg_r1_0_15_0_5_i_8_n_0
|
|
r u_matmul_axi_slave/mult_inst[0].u_mult/b1_c_reg_r1_0_15_0_5_i_13/CI
|
|
CARRY4 (Prop_carry4_CI_O[1])
|
|
0.348 -0.886 r u_matmul_axi_slave/mult_inst[0].u_mult/b1_c_reg_r1_0_15_0_5_i_13/O[1]
|
|
net (fo=2, unplaced) 0.622 -0.264 u_matmul_axi_slave/calc_c_result02_out[5]
|
|
r u_matmul_axi_slave/b1_c_reg_r1_0_15_0_5_i_16/I0
|
|
LUT2 (Prop_lut2_I0_O) 0.306 0.042 r u_matmul_axi_slave/b1_c_reg_r1_0_15_0_5_i_16/O
|
|
net (fo=1, unplaced) 0.000 0.042 u_matmul_axi_slave/b1_c_reg_r1_0_15_0_5_i_16_n_0
|
|
r u_matmul_axi_slave/b1_c_reg_r1_0_15_0_5_i_3/S[1]
|
|
CARRY4 (Prop_carry4_S[1]_O[3])
|
|
0.640 0.682 r u_matmul_axi_slave/b1_c_reg_r1_0_15_0_5_i_3/O[3]
|
|
net (fo=15, unplaced) 0.671 1.353 u_matmul_axi_slave/b1_c_reg_r1_0_15_0_5_i_3_n_4
|
|
r u_matmul_axi_slave/crc_reg[12]_i_91/I2
|
|
LUT6 (Prop_lut6_I2_O) 0.307 1.660 r u_matmul_axi_slave/crc_reg[12]_i_91/O
|
|
net (fo=3, unplaced) 0.920 2.580 u_matmul_axi_slave/crc_reg[12]_i_91_n_0
|
|
r u_matmul_axi_slave/crc_reg[12]_i_72/I3
|
|
LUT6 (Prop_lut6_I3_O) 0.124 2.704 r u_matmul_axi_slave/crc_reg[12]_i_72/O
|
|
net (fo=7, unplaced) 0.484 3.188 u_matmul_axi_slave/crc_reg[12]_i_72_n_0
|
|
r u_matmul_axi_slave/crc_reg[12]_i_64/I1
|
|
LUT6 (Prop_lut6_I1_O) 0.124 3.312 r u_matmul_axi_slave/crc_reg[12]_i_64/O
|
|
net (fo=11, unplaced) 0.948 4.260 u_matmul_axi_slave/crc32_word_next_return4[3]
|
|
r u_matmul_axi_slave/crc_reg[12]_i_52/I1
|
|
LUT6 (Prop_lut6_I1_O) 0.124 4.384 r u_matmul_axi_slave/crc_reg[12]_i_52/O
|
|
net (fo=11, unplaced) 1.157 5.541 u_matmul_axi_slave/crc32_word_next_return1[1]
|
|
r u_matmul_axi_slave/crc_reg[12]_i_39/I4
|
|
LUT6 (Prop_lut6_I4_O) 0.124 5.665 r u_matmul_axi_slave/crc_reg[12]_i_39/O
|
|
net (fo=10, unplaced) 0.945 6.610 u_matmul_axi_slave/crc32_word_next0_return10[5]
|
|
r u_matmul_axi_slave/crc_reg[12]_i_22/I1
|
|
LUT5 (Prop_lut5_I1_O) 0.124 6.734 r u_matmul_axi_slave/crc_reg[12]_i_22/O
|
|
net (fo=14, unplaced) 0.953 7.687 u_matmul_axi_slave/crc32_word_next0_return7[7]
|
|
r u_matmul_axi_slave/crc_reg[12]_i_55/I1
|
|
LUT4 (Prop_lut4_I1_O) 0.124 7.811 r u_matmul_axi_slave/crc_reg[12]_i_55/O
|
|
net (fo=1, unplaced) 0.902 8.713 u_matmul_axi_slave/crc32_word_next0_return6[21]
|
|
r u_matmul_axi_slave/crc_reg[12]_i_27/I0
|
|
LUT6 (Prop_lut6_I0_O) 0.124 8.837 r u_matmul_axi_slave/crc_reg[12]_i_27/O
|
|
net (fo=1, unplaced) 1.111 9.948 u_matmul_axi_slave/p_0_in11_in[4]
|
|
r u_matmul_axi_slave/crc_reg[12]_i_11/I0
|
|
LUT5 (Prop_lut5_I0_O) 0.124 10.072 r u_matmul_axi_slave/crc_reg[12]_i_11/O
|
|
net (fo=9, unplaced) 0.943 11.015 u_matmul_axi_slave/crc_reg[12]_i_11_n_0
|
|
r u_matmul_axi_slave/crc_reg[3]_i_3/I0
|
|
LUT3 (Prop_lut3_I0_O) 0.150 11.165 r u_matmul_axi_slave/crc_reg[3]_i_3/O
|
|
net (fo=3, unplaced) 0.683 11.848 u_matmul_axi_slave/crc_reg[3]_i_3_n_0
|
|
r u_matmul_axi_slave/crc_reg[21]_i_5/I0
|
|
LUT6 (Prop_lut6_I0_O) 0.124 11.972 r u_matmul_axi_slave/crc_reg[21]_i_5/O
|
|
net (fo=1, unplaced) 0.902 12.874 u_matmul_axi_slave/crc_reg[21]_i_5_n_0
|
|
r u_matmul_axi_slave/crc_reg[21]_i_4/I1
|
|
LUT4 (Prop_lut4_I1_O) 0.124 12.998 r u_matmul_axi_slave/crc_reg[21]_i_4/O
|
|
net (fo=2, unplaced) 0.913 13.911 u_matmul_axi_slave/crc_reg[21]_i_4_n_0
|
|
r u_matmul_axi_slave/crc_reg[21]_i_1/I3
|
|
LUT6 (Prop_lut6_I3_O) 0.124 14.035 r u_matmul_axi_slave/crc_reg[21]_i_1/O
|
|
net (fo=1, unplaced) 0.000 14.035 u_matmul_axi_slave/crc32_word_next1_return[21]
|
|
FDSE r u_matmul_axi_slave/crc_reg_reg[21]/D
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock sys_clk rise edge) 20.000 20.000 r
|
|
K21 0.000 20.000 r clk (IN)
|
|
net (fo=0) 0.000 20.000 pll_clk.u_clk_pll/inst/clk_in1
|
|
K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I
|
|
K21 IBUF (Prop_ibuf_I_O) 1.393 21.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O
|
|
net (fo=1, unplaced) 0.439 21.832 pll_clk.u_clk_pll/inst/clk_in1_clk_pll
|
|
r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1
|
|
PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1)
|
|
-6.040 15.792 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1
|
|
net (fo=1, unplaced) 0.760 16.552 pll_clk.u_clk_pll/inst/sys_clk_clk_pll
|
|
r pll_clk.u_clk_pll/inst/clkout2_buf/I
|
|
BUFG (Prop_bufg_I_O) 0.091 16.643 r pll_clk.u_clk_pll/inst/clkout2_buf/O
|
|
net (fo=10994, unplaced) 0.655 17.297 u_matmul_axi_slave/sys_clk
|
|
FDSE r u_matmul_axi_slave/crc_reg_reg[21]/C
|
|
clock pessimism -0.468 16.830
|
|
clock uncertainty -0.071 16.759
|
|
FDSE (Setup_fdse_C_D) 0.029 16.788 u_matmul_axi_slave/crc_reg_reg[21]
|
|
-------------------------------------------------------------------
|
|
required time 16.788
|
|
arrival time -14.035
|
|
-------------------------------------------------------------------
|
|
slack 2.753
|
|
|
|
Slack (MET) : 2.757ns (required time - arrival time)
|
|
Source: u_matmul_axi_slave/mult_inst[0].u_mult/p_reg[1]/C
|
|
(rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Destination: u_matmul_axi_slave/crc_reg_reg[27]/D
|
|
(rising edge-triggered cell FDSE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Path Group: sys_clk
|
|
Path Type: Setup (Max at Slow Process Corner)
|
|
Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns)
|
|
Data Path Delay: 17.056ns (logic 4.470ns (26.208%) route 12.586ns (73.792%))
|
|
Logic Levels: 18 (CARRY4=3 LUT2=2 LUT4=1 LUT5=6 LUT6=6)
|
|
Clock Path Skew: -0.145ns (DCD - SCD + CPR)
|
|
Destination Clock Delay (DCD): -2.703ns = ( 17.297 - 20.000 )
|
|
Source Clock Delay (SCD): -3.025ns
|
|
Clock Pessimism Removal (CPR): -0.468ns
|
|
Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Discrete Jitter (DJ): 0.122ns
|
|
Phase Error (PE): 0.000ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock sys_clk rise edge) 0.000 0.000 r
|
|
K21 0.000 0.000 r clk (IN)
|
|
net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1
|
|
K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I
|
|
K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O
|
|
net (fo=1, unplaced) 0.584 2.047 pll_clk.u_clk_pll/inst/clk_in1_clk_pll
|
|
r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1
|
|
PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1)
|
|
-6.768 -4.721 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1
|
|
net (fo=1, unplaced) 0.800 -3.921 pll_clk.u_clk_pll/inst/sys_clk_clk_pll
|
|
r pll_clk.u_clk_pll/inst/clkout2_buf/I
|
|
BUFG (Prop_bufg_I_O) 0.096 -3.825 r pll_clk.u_clk_pll/inst/clkout2_buf/O
|
|
net (fo=10994, unplaced) 0.800 -3.025 u_matmul_axi_slave/mult_inst[0].u_mult/sys_clk
|
|
FDRE r u_matmul_axi_slave/mult_inst[0].u_mult/p_reg[1]/C
|
|
------------------------------------------------------------------- -------------------
|
|
FDRE (Prop_fdre_C_Q) 0.456 -2.569 r u_matmul_axi_slave/mult_inst[0].u_mult/p_reg[1]/Q
|
|
net (fo=2, unplaced) 0.481 -2.088 u_matmul_axi_slave/mult_inst[0].u_mult/mult_p[0]_0[1]
|
|
r u_matmul_axi_slave/mult_inst[0].u_mult/b1_c_reg_r1_0_15_0_5_i_20/I0
|
|
LUT2 (Prop_lut2_I0_O) 0.295 -1.793 r u_matmul_axi_slave/mult_inst[0].u_mult/b1_c_reg_r1_0_15_0_5_i_20/O
|
|
net (fo=1, unplaced) 0.000 -1.793 u_matmul_axi_slave/mult_inst[0].u_mult/b1_c_reg_r1_0_15_0_5_i_20_n_0
|
|
r u_matmul_axi_slave/mult_inst[0].u_mult/b1_c_reg_r1_0_15_0_5_i_8/S[1]
|
|
CARRY4 (Prop_carry4_S[1]_CO[3])
|
|
0.550 -1.243 r u_matmul_axi_slave/mult_inst[0].u_mult/b1_c_reg_r1_0_15_0_5_i_8/CO[3]
|
|
net (fo=1, unplaced) 0.009 -1.234 u_matmul_axi_slave/mult_inst[0].u_mult/b1_c_reg_r1_0_15_0_5_i_8_n_0
|
|
r u_matmul_axi_slave/mult_inst[0].u_mult/b1_c_reg_r1_0_15_0_5_i_13/CI
|
|
CARRY4 (Prop_carry4_CI_O[1])
|
|
0.348 -0.886 r u_matmul_axi_slave/mult_inst[0].u_mult/b1_c_reg_r1_0_15_0_5_i_13/O[1]
|
|
net (fo=2, unplaced) 0.622 -0.264 u_matmul_axi_slave/calc_c_result02_out[5]
|
|
r u_matmul_axi_slave/b1_c_reg_r1_0_15_0_5_i_16/I0
|
|
LUT2 (Prop_lut2_I0_O) 0.306 0.042 r u_matmul_axi_slave/b1_c_reg_r1_0_15_0_5_i_16/O
|
|
net (fo=1, unplaced) 0.000 0.042 u_matmul_axi_slave/b1_c_reg_r1_0_15_0_5_i_16_n_0
|
|
r u_matmul_axi_slave/b1_c_reg_r1_0_15_0_5_i_3/S[1]
|
|
CARRY4 (Prop_carry4_S[1]_O[3])
|
|
0.640 0.682 r u_matmul_axi_slave/b1_c_reg_r1_0_15_0_5_i_3/O[3]
|
|
net (fo=15, unplaced) 0.671 1.353 u_matmul_axi_slave/b1_c_reg_r1_0_15_0_5_i_3_n_4
|
|
r u_matmul_axi_slave/crc_reg[12]_i_91/I2
|
|
LUT6 (Prop_lut6_I2_O) 0.307 1.660 r u_matmul_axi_slave/crc_reg[12]_i_91/O
|
|
net (fo=3, unplaced) 0.920 2.580 u_matmul_axi_slave/crc_reg[12]_i_91_n_0
|
|
r u_matmul_axi_slave/crc_reg[12]_i_72/I3
|
|
LUT6 (Prop_lut6_I3_O) 0.124 2.704 r u_matmul_axi_slave/crc_reg[12]_i_72/O
|
|
net (fo=7, unplaced) 0.484 3.188 u_matmul_axi_slave/crc_reg[12]_i_72_n_0
|
|
r u_matmul_axi_slave/crc_reg[12]_i_64/I1
|
|
LUT6 (Prop_lut6_I1_O) 0.124 3.312 r u_matmul_axi_slave/crc_reg[12]_i_64/O
|
|
net (fo=11, unplaced) 1.010 4.322 u_matmul_axi_slave/crc32_word_next_return4[3]
|
|
r u_matmul_axi_slave/crc_reg[31]_i_30/I1
|
|
LUT6 (Prop_lut6_I1_O) 0.124 4.446 r u_matmul_axi_slave/crc_reg[31]_i_30/O
|
|
net (fo=10, unplaced) 0.945 5.391 u_matmul_axi_slave/crc32_word_next_return1[5]
|
|
r u_matmul_axi_slave/crc_reg[23]_i_18/I1
|
|
LUT5 (Prop_lut5_I1_O) 0.124 5.515 r u_matmul_axi_slave/crc_reg[23]_i_18/O
|
|
net (fo=14, unplaced) 0.953 6.468 u_matmul_axi_slave/crc32_word_next0_return10[7]
|
|
r u_matmul_axi_slave/crc_reg[12]_i_33/I2
|
|
LUT6 (Prop_lut6_I2_O) 0.124 6.592 r u_matmul_axi_slave/crc_reg[12]_i_33/O
|
|
net (fo=11, unplaced) 0.948 7.540 u_matmul_axi_slave/crc32_word_next0_return7[5]
|
|
r u_matmul_axi_slave/crc_reg[23]_i_10/I1
|
|
LUT5 (Prop_lut5_I1_O) 0.124 7.664 r u_matmul_axi_slave/crc_reg[23]_i_10/O
|
|
net (fo=15, unplaced) 0.955 8.619 u_matmul_axi_slave/crc32_word_next0_return4[7]
|
|
r u_matmul_axi_slave/crc_reg[12]_i_32/I1
|
|
LUT4 (Prop_lut4_I1_O) 0.124 8.743 r u_matmul_axi_slave/crc_reg[12]_i_32/O
|
|
net (fo=1, unplaced) 0.902 9.645 u_matmul_axi_slave/crc32_word_next0_return3[21]
|
|
r u_matmul_axi_slave/crc_reg[12]_i_16/I0
|
|
LUT6 (Prop_lut6_I0_O) 0.124 9.769 r u_matmul_axi_slave/crc_reg[12]_i_16/O
|
|
net (fo=2, unplaced) 1.122 10.891 u_matmul_axi_slave/crc_reg[12]_i_16_n_0
|
|
r u_matmul_axi_slave/crc_reg[20]_i_8/I0
|
|
LUT5 (Prop_lut5_I0_O) 0.152 11.043 r u_matmul_axi_slave/crc_reg[20]_i_8/O
|
|
net (fo=6, unplaced) 0.934 11.977 u_matmul_axi_slave/crc32_word_next1_return7[4]
|
|
r u_matmul_axi_slave/crc_reg[20]_i_3/I2
|
|
LUT5 (Prop_lut5_I2_O) 0.150 12.127 r u_matmul_axi_slave/crc_reg[20]_i_3/O
|
|
net (fo=13, unplaced) 0.469 12.596 u_matmul_axi_slave/crc32_word_next1_return4[5]
|
|
r u_matmul_axi_slave/crc_reg[27]_i_2/I3
|
|
LUT5 (Prop_lut5_I3_O) 0.150 12.746 r u_matmul_axi_slave/crc_reg[27]_i_2/O
|
|
net (fo=13, unplaced) 1.161 13.907 u_matmul_axi_slave/crc32_word_next1_return1[3]
|
|
r u_matmul_axi_slave/crc_reg[27]_i_1/I0
|
|
LUT5 (Prop_lut5_I0_O) 0.124 14.031 r u_matmul_axi_slave/crc_reg[27]_i_1/O
|
|
net (fo=1, unplaced) 0.000 14.031 u_matmul_axi_slave/crc32_word_next1_return0[25]
|
|
FDSE r u_matmul_axi_slave/crc_reg_reg[27]/D
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock sys_clk rise edge) 20.000 20.000 r
|
|
K21 0.000 20.000 r clk (IN)
|
|
net (fo=0) 0.000 20.000 pll_clk.u_clk_pll/inst/clk_in1
|
|
K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I
|
|
K21 IBUF (Prop_ibuf_I_O) 1.393 21.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O
|
|
net (fo=1, unplaced) 0.439 21.832 pll_clk.u_clk_pll/inst/clk_in1_clk_pll
|
|
r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1
|
|
PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1)
|
|
-6.040 15.792 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1
|
|
net (fo=1, unplaced) 0.760 16.552 pll_clk.u_clk_pll/inst/sys_clk_clk_pll
|
|
r pll_clk.u_clk_pll/inst/clkout2_buf/I
|
|
BUFG (Prop_bufg_I_O) 0.091 16.643 r pll_clk.u_clk_pll/inst/clkout2_buf/O
|
|
net (fo=10994, unplaced) 0.655 17.297 u_matmul_axi_slave/sys_clk
|
|
FDSE r u_matmul_axi_slave/crc_reg_reg[27]/C
|
|
clock pessimism -0.468 16.830
|
|
clock uncertainty -0.071 16.759
|
|
FDSE (Setup_fdse_C_D) 0.029 16.788 u_matmul_axi_slave/crc_reg_reg[27]
|
|
-------------------------------------------------------------------
|
|
required time 16.788
|
|
arrival time -14.031
|
|
-------------------------------------------------------------------
|
|
slack 2.757
|
|
|
|
Slack (MET) : 2.771ns (required time - arrival time)
|
|
Source: u_matmul_axi_slave/mult_inst[0].u_mult/p_reg[1]/C
|
|
(rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Destination: u_matmul_axi_slave/crc_reg_reg[23]/D
|
|
(rising edge-triggered cell FDSE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Path Group: sys_clk
|
|
Path Type: Setup (Max at Slow Process Corner)
|
|
Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns)
|
|
Data Path Delay: 17.042ns (logic 4.418ns (25.924%) route 12.624ns (74.076%))
|
|
Logic Levels: 18 (CARRY4=3 LUT2=2 LUT4=2 LUT5=3 LUT6=8)
|
|
Clock Path Skew: -0.145ns (DCD - SCD + CPR)
|
|
Destination Clock Delay (DCD): -2.703ns = ( 17.297 - 20.000 )
|
|
Source Clock Delay (SCD): -3.025ns
|
|
Clock Pessimism Removal (CPR): -0.468ns
|
|
Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Discrete Jitter (DJ): 0.122ns
|
|
Phase Error (PE): 0.000ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock sys_clk rise edge) 0.000 0.000 r
|
|
K21 0.000 0.000 r clk (IN)
|
|
net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1
|
|
K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I
|
|
K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O
|
|
net (fo=1, unplaced) 0.584 2.047 pll_clk.u_clk_pll/inst/clk_in1_clk_pll
|
|
r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1
|
|
PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1)
|
|
-6.768 -4.721 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1
|
|
net (fo=1, unplaced) 0.800 -3.921 pll_clk.u_clk_pll/inst/sys_clk_clk_pll
|
|
r pll_clk.u_clk_pll/inst/clkout2_buf/I
|
|
BUFG (Prop_bufg_I_O) 0.096 -3.825 r pll_clk.u_clk_pll/inst/clkout2_buf/O
|
|
net (fo=10994, unplaced) 0.800 -3.025 u_matmul_axi_slave/mult_inst[0].u_mult/sys_clk
|
|
FDRE r u_matmul_axi_slave/mult_inst[0].u_mult/p_reg[1]/C
|
|
------------------------------------------------------------------- -------------------
|
|
FDRE (Prop_fdre_C_Q) 0.456 -2.569 r u_matmul_axi_slave/mult_inst[0].u_mult/p_reg[1]/Q
|
|
net (fo=2, unplaced) 0.481 -2.088 u_matmul_axi_slave/mult_inst[0].u_mult/mult_p[0]_0[1]
|
|
r u_matmul_axi_slave/mult_inst[0].u_mult/b1_c_reg_r1_0_15_0_5_i_20/I0
|
|
LUT2 (Prop_lut2_I0_O) 0.295 -1.793 r u_matmul_axi_slave/mult_inst[0].u_mult/b1_c_reg_r1_0_15_0_5_i_20/O
|
|
net (fo=1, unplaced) 0.000 -1.793 u_matmul_axi_slave/mult_inst[0].u_mult/b1_c_reg_r1_0_15_0_5_i_20_n_0
|
|
r u_matmul_axi_slave/mult_inst[0].u_mult/b1_c_reg_r1_0_15_0_5_i_8/S[1]
|
|
CARRY4 (Prop_carry4_S[1]_CO[3])
|
|
0.550 -1.243 r u_matmul_axi_slave/mult_inst[0].u_mult/b1_c_reg_r1_0_15_0_5_i_8/CO[3]
|
|
net (fo=1, unplaced) 0.009 -1.234 u_matmul_axi_slave/mult_inst[0].u_mult/b1_c_reg_r1_0_15_0_5_i_8_n_0
|
|
r u_matmul_axi_slave/mult_inst[0].u_mult/b1_c_reg_r1_0_15_0_5_i_13/CI
|
|
CARRY4 (Prop_carry4_CI_O[1])
|
|
0.348 -0.886 r u_matmul_axi_slave/mult_inst[0].u_mult/b1_c_reg_r1_0_15_0_5_i_13/O[1]
|
|
net (fo=2, unplaced) 0.622 -0.264 u_matmul_axi_slave/calc_c_result02_out[5]
|
|
r u_matmul_axi_slave/b1_c_reg_r1_0_15_0_5_i_16/I0
|
|
LUT2 (Prop_lut2_I0_O) 0.306 0.042 r u_matmul_axi_slave/b1_c_reg_r1_0_15_0_5_i_16/O
|
|
net (fo=1, unplaced) 0.000 0.042 u_matmul_axi_slave/b1_c_reg_r1_0_15_0_5_i_16_n_0
|
|
r u_matmul_axi_slave/b1_c_reg_r1_0_15_0_5_i_3/S[1]
|
|
CARRY4 (Prop_carry4_S[1]_O[3])
|
|
0.640 0.682 r u_matmul_axi_slave/b1_c_reg_r1_0_15_0_5_i_3/O[3]
|
|
net (fo=15, unplaced) 0.671 1.353 u_matmul_axi_slave/b1_c_reg_r1_0_15_0_5_i_3_n_4
|
|
r u_matmul_axi_slave/crc_reg[12]_i_91/I2
|
|
LUT6 (Prop_lut6_I2_O) 0.307 1.660 r u_matmul_axi_slave/crc_reg[12]_i_91/O
|
|
net (fo=3, unplaced) 0.920 2.580 u_matmul_axi_slave/crc_reg[12]_i_91_n_0
|
|
r u_matmul_axi_slave/crc_reg[12]_i_72/I3
|
|
LUT6 (Prop_lut6_I3_O) 0.124 2.704 r u_matmul_axi_slave/crc_reg[12]_i_72/O
|
|
net (fo=7, unplaced) 0.484 3.188 u_matmul_axi_slave/crc_reg[12]_i_72_n_0
|
|
r u_matmul_axi_slave/crc_reg[12]_i_64/I1
|
|
LUT6 (Prop_lut6_I1_O) 0.124 3.312 r u_matmul_axi_slave/crc_reg[12]_i_64/O
|
|
net (fo=11, unplaced) 0.948 4.260 u_matmul_axi_slave/crc32_word_next_return4[3]
|
|
r u_matmul_axi_slave/crc_reg[12]_i_52/I1
|
|
LUT6 (Prop_lut6_I1_O) 0.124 4.384 r u_matmul_axi_slave/crc_reg[12]_i_52/O
|
|
net (fo=11, unplaced) 1.157 5.541 u_matmul_axi_slave/crc32_word_next_return1[1]
|
|
r u_matmul_axi_slave/crc_reg[12]_i_39/I4
|
|
LUT6 (Prop_lut6_I4_O) 0.124 5.665 r u_matmul_axi_slave/crc_reg[12]_i_39/O
|
|
net (fo=10, unplaced) 0.945 6.610 u_matmul_axi_slave/crc32_word_next0_return10[5]
|
|
r u_matmul_axi_slave/crc_reg[12]_i_22/I1
|
|
LUT5 (Prop_lut5_I1_O) 0.124 6.734 r u_matmul_axi_slave/crc_reg[12]_i_22/O
|
|
net (fo=14, unplaced) 0.953 7.687 u_matmul_axi_slave/crc32_word_next0_return7[7]
|
|
r u_matmul_axi_slave/crc_reg[12]_i_55/I1
|
|
LUT4 (Prop_lut4_I1_O) 0.124 7.811 r u_matmul_axi_slave/crc_reg[12]_i_55/O
|
|
net (fo=1, unplaced) 0.902 8.713 u_matmul_axi_slave/crc32_word_next0_return6[21]
|
|
r u_matmul_axi_slave/crc_reg[12]_i_27/I0
|
|
LUT6 (Prop_lut6_I0_O) 0.124 8.837 r u_matmul_axi_slave/crc_reg[12]_i_27/O
|
|
net (fo=1, unplaced) 1.111 9.948 u_matmul_axi_slave/p_0_in11_in[4]
|
|
r u_matmul_axi_slave/crc_reg[12]_i_11/I0
|
|
LUT5 (Prop_lut5_I0_O) 0.124 10.072 r u_matmul_axi_slave/crc_reg[12]_i_11/O
|
|
net (fo=9, unplaced) 0.460 10.532 u_matmul_axi_slave/crc_reg[12]_i_11_n_0
|
|
r u_matmul_axi_slave/crc_reg[28]_i_4/I2
|
|
LUT4 (Prop_lut4_I2_O) 0.124 10.656 r u_matmul_axi_slave/crc_reg[28]_i_4/O
|
|
net (fo=1, unplaced) 0.902 11.558 u_matmul_axi_slave/crc32_word_next1_return9[21]
|
|
r u_matmul_axi_slave/crc_reg[28]_i_3/I0
|
|
LUT6 (Prop_lut6_I0_O) 0.124 11.682 r u_matmul_axi_slave/crc_reg[28]_i_3/O
|
|
net (fo=3, unplaced) 1.129 12.811 u_matmul_axi_slave/crc_reg[28]_i_3_n_0
|
|
r u_matmul_axi_slave/crc_reg[27]_i_3/I0
|
|
LUT5 (Prop_lut5_I0_O) 0.152 12.963 r u_matmul_axi_slave/crc_reg[27]_i_3/O
|
|
net (fo=5, unplaced) 0.930 13.893 u_matmul_axi_slave/crc32_word_next1_return1[4]
|
|
r u_matmul_axi_slave/crc_reg[23]_i_1/I3
|
|
LUT6 (Prop_lut6_I3_O) 0.124 14.017 r u_matmul_axi_slave/crc_reg[23]_i_1/O
|
|
net (fo=1, unplaced) 0.000 14.017 u_matmul_axi_slave/crc32_word_next1_return[23]
|
|
FDSE r u_matmul_axi_slave/crc_reg_reg[23]/D
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock sys_clk rise edge) 20.000 20.000 r
|
|
K21 0.000 20.000 r clk (IN)
|
|
net (fo=0) 0.000 20.000 pll_clk.u_clk_pll/inst/clk_in1
|
|
K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I
|
|
K21 IBUF (Prop_ibuf_I_O) 1.393 21.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O
|
|
net (fo=1, unplaced) 0.439 21.832 pll_clk.u_clk_pll/inst/clk_in1_clk_pll
|
|
r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1
|
|
PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1)
|
|
-6.040 15.792 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1
|
|
net (fo=1, unplaced) 0.760 16.552 pll_clk.u_clk_pll/inst/sys_clk_clk_pll
|
|
r pll_clk.u_clk_pll/inst/clkout2_buf/I
|
|
BUFG (Prop_bufg_I_O) 0.091 16.643 r pll_clk.u_clk_pll/inst/clkout2_buf/O
|
|
net (fo=10994, unplaced) 0.655 17.297 u_matmul_axi_slave/sys_clk
|
|
FDSE r u_matmul_axi_slave/crc_reg_reg[23]/C
|
|
clock pessimism -0.468 16.830
|
|
clock uncertainty -0.071 16.759
|
|
FDSE (Setup_fdse_C_D) 0.029 16.788 u_matmul_axi_slave/crc_reg_reg[23]
|
|
-------------------------------------------------------------------
|
|
required time 16.788
|
|
arrival time -14.017
|
|
-------------------------------------------------------------------
|
|
slack 2.771
|
|
|
|
Slack (MET) : 2.773ns (required time - arrival time)
|
|
Source: u_matmul_axi_slave/mult_inst[0].u_mult/p_reg[1]/C
|
|
(rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Destination: u_matmul_axi_slave/crc_reg_reg[16]/D
|
|
(rising edge-triggered cell FDSE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Path Group: sys_clk
|
|
Path Type: Setup (Max at Slow Process Corner)
|
|
Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns)
|
|
Data Path Delay: 17.040ns (logic 4.444ns (26.080%) route 12.596ns (73.920%))
|
|
Logic Levels: 18 (CARRY4=3 LUT2=2 LUT4=1 LUT5=5 LUT6=7)
|
|
Clock Path Skew: -0.145ns (DCD - SCD + CPR)
|
|
Destination Clock Delay (DCD): -2.703ns = ( 17.297 - 20.000 )
|
|
Source Clock Delay (SCD): -3.025ns
|
|
Clock Pessimism Removal (CPR): -0.468ns
|
|
Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Discrete Jitter (DJ): 0.122ns
|
|
Phase Error (PE): 0.000ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock sys_clk rise edge) 0.000 0.000 r
|
|
K21 0.000 0.000 r clk (IN)
|
|
net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1
|
|
K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I
|
|
K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O
|
|
net (fo=1, unplaced) 0.584 2.047 pll_clk.u_clk_pll/inst/clk_in1_clk_pll
|
|
r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1
|
|
PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1)
|
|
-6.768 -4.721 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1
|
|
net (fo=1, unplaced) 0.800 -3.921 pll_clk.u_clk_pll/inst/sys_clk_clk_pll
|
|
r pll_clk.u_clk_pll/inst/clkout2_buf/I
|
|
BUFG (Prop_bufg_I_O) 0.096 -3.825 r pll_clk.u_clk_pll/inst/clkout2_buf/O
|
|
net (fo=10994, unplaced) 0.800 -3.025 u_matmul_axi_slave/mult_inst[0].u_mult/sys_clk
|
|
FDRE r u_matmul_axi_slave/mult_inst[0].u_mult/p_reg[1]/C
|
|
------------------------------------------------------------------- -------------------
|
|
FDRE (Prop_fdre_C_Q) 0.456 -2.569 r u_matmul_axi_slave/mult_inst[0].u_mult/p_reg[1]/Q
|
|
net (fo=2, unplaced) 0.481 -2.088 u_matmul_axi_slave/mult_inst[0].u_mult/mult_p[0]_0[1]
|
|
r u_matmul_axi_slave/mult_inst[0].u_mult/b1_c_reg_r1_0_15_0_5_i_20/I0
|
|
LUT2 (Prop_lut2_I0_O) 0.295 -1.793 r u_matmul_axi_slave/mult_inst[0].u_mult/b1_c_reg_r1_0_15_0_5_i_20/O
|
|
net (fo=1, unplaced) 0.000 -1.793 u_matmul_axi_slave/mult_inst[0].u_mult/b1_c_reg_r1_0_15_0_5_i_20_n_0
|
|
r u_matmul_axi_slave/mult_inst[0].u_mult/b1_c_reg_r1_0_15_0_5_i_8/S[1]
|
|
CARRY4 (Prop_carry4_S[1]_CO[3])
|
|
0.550 -1.243 r u_matmul_axi_slave/mult_inst[0].u_mult/b1_c_reg_r1_0_15_0_5_i_8/CO[3]
|
|
net (fo=1, unplaced) 0.009 -1.234 u_matmul_axi_slave/mult_inst[0].u_mult/b1_c_reg_r1_0_15_0_5_i_8_n_0
|
|
r u_matmul_axi_slave/mult_inst[0].u_mult/b1_c_reg_r1_0_15_0_5_i_13/CI
|
|
CARRY4 (Prop_carry4_CI_O[1])
|
|
0.348 -0.886 r u_matmul_axi_slave/mult_inst[0].u_mult/b1_c_reg_r1_0_15_0_5_i_13/O[1]
|
|
net (fo=2, unplaced) 0.622 -0.264 u_matmul_axi_slave/calc_c_result02_out[5]
|
|
r u_matmul_axi_slave/b1_c_reg_r1_0_15_0_5_i_16/I0
|
|
LUT2 (Prop_lut2_I0_O) 0.306 0.042 r u_matmul_axi_slave/b1_c_reg_r1_0_15_0_5_i_16/O
|
|
net (fo=1, unplaced) 0.000 0.042 u_matmul_axi_slave/b1_c_reg_r1_0_15_0_5_i_16_n_0
|
|
r u_matmul_axi_slave/b1_c_reg_r1_0_15_0_5_i_3/S[1]
|
|
CARRY4 (Prop_carry4_S[1]_O[3])
|
|
0.640 0.682 r u_matmul_axi_slave/b1_c_reg_r1_0_15_0_5_i_3/O[3]
|
|
net (fo=15, unplaced) 0.671 1.353 u_matmul_axi_slave/b1_c_reg_r1_0_15_0_5_i_3_n_4
|
|
r u_matmul_axi_slave/crc_reg[12]_i_91/I2
|
|
LUT6 (Prop_lut6_I2_O) 0.307 1.660 r u_matmul_axi_slave/crc_reg[12]_i_91/O
|
|
net (fo=3, unplaced) 0.920 2.580 u_matmul_axi_slave/crc_reg[12]_i_91_n_0
|
|
r u_matmul_axi_slave/crc_reg[12]_i_72/I3
|
|
LUT6 (Prop_lut6_I3_O) 0.124 2.704 r u_matmul_axi_slave/crc_reg[12]_i_72/O
|
|
net (fo=7, unplaced) 0.484 3.188 u_matmul_axi_slave/crc_reg[12]_i_72_n_0
|
|
r u_matmul_axi_slave/crc_reg[12]_i_64/I1
|
|
LUT6 (Prop_lut6_I1_O) 0.124 3.312 r u_matmul_axi_slave/crc_reg[12]_i_64/O
|
|
net (fo=11, unplaced) 0.948 4.260 u_matmul_axi_slave/crc32_word_next_return4[3]
|
|
r u_matmul_axi_slave/crc_reg[12]_i_52/I1
|
|
LUT6 (Prop_lut6_I1_O) 0.124 4.384 r u_matmul_axi_slave/crc_reg[12]_i_52/O
|
|
net (fo=11, unplaced) 1.157 5.541 u_matmul_axi_slave/crc32_word_next_return1[1]
|
|
r u_matmul_axi_slave/crc_reg[12]_i_39/I4
|
|
LUT6 (Prop_lut6_I4_O) 0.124 5.665 r u_matmul_axi_slave/crc_reg[12]_i_39/O
|
|
net (fo=10, unplaced) 0.945 6.610 u_matmul_axi_slave/crc32_word_next0_return10[5]
|
|
r u_matmul_axi_slave/crc_reg[12]_i_22/I1
|
|
LUT5 (Prop_lut5_I1_O) 0.124 6.734 r u_matmul_axi_slave/crc_reg[12]_i_22/O
|
|
net (fo=14, unplaced) 0.953 7.687 u_matmul_axi_slave/crc32_word_next0_return7[7]
|
|
r u_matmul_axi_slave/crc_reg[20]_i_16/I2
|
|
LUT6 (Prop_lut6_I2_O) 0.124 7.811 r u_matmul_axi_slave/crc_reg[20]_i_16/O
|
|
net (fo=11, unplaced) 0.948 8.759 u_matmul_axi_slave/crc32_word_next0_return4[5]
|
|
r u_matmul_axi_slave/crc_reg[31]_i_18/I1
|
|
LUT5 (Prop_lut5_I1_O) 0.124 8.883 r u_matmul_axi_slave/crc_reg[31]_i_18/O
|
|
net (fo=16, unplaced) 0.956 9.839 u_matmul_axi_slave/crc32_word_next0_return1[7]
|
|
r u_matmul_axi_slave/crc_reg[30]_i_10/I1
|
|
LUT5 (Prop_lut5_I1_O) 0.150 9.989 r u_matmul_axi_slave/crc_reg[30]_i_10/O
|
|
net (fo=1, unplaced) 1.111 11.100 u_matmul_axi_slave/crc32_word_next0_return0[22]
|
|
r u_matmul_axi_slave/crc_reg[30]_i_4/I0
|
|
LUT5 (Prop_lut5_I0_O) 0.152 11.252 r u_matmul_axi_slave/crc_reg[30]_i_4/O
|
|
net (fo=1, unplaced) 0.902 12.154 u_matmul_axi_slave/p_0_in0_in[8]
|
|
r u_matmul_axi_slave/crc_reg[30]_i_2/I2
|
|
LUT5 (Prop_lut5_I2_O) 0.124 12.278 r u_matmul_axi_slave/crc_reg[30]_i_2/O
|
|
net (fo=9, unplaced) 1.005 13.283 u_matmul_axi_slave/crc32_word_next1_return1[0]
|
|
r u_matmul_axi_slave/crc_reg[28]_i_2/I0
|
|
LUT6 (Prop_lut6_I0_O) 0.124 13.407 r u_matmul_axi_slave/crc_reg[28]_i_2/O
|
|
net (fo=7, unplaced) 0.484 13.891 u_matmul_axi_slave/crc_reg[28]_i_2_n_0
|
|
r u_matmul_axi_slave/crc_reg[16]_i_1/I3
|
|
LUT4 (Prop_lut4_I3_O) 0.124 14.015 r u_matmul_axi_slave/crc_reg[16]_i_1/O
|
|
net (fo=1, unplaced) 0.000 14.015 u_matmul_axi_slave/crc32_word_next1_return[16]
|
|
FDSE r u_matmul_axi_slave/crc_reg_reg[16]/D
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock sys_clk rise edge) 20.000 20.000 r
|
|
K21 0.000 20.000 r clk (IN)
|
|
net (fo=0) 0.000 20.000 pll_clk.u_clk_pll/inst/clk_in1
|
|
K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I
|
|
K21 IBUF (Prop_ibuf_I_O) 1.393 21.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O
|
|
net (fo=1, unplaced) 0.439 21.832 pll_clk.u_clk_pll/inst/clk_in1_clk_pll
|
|
r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1
|
|
PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1)
|
|
-6.040 15.792 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1
|
|
net (fo=1, unplaced) 0.760 16.552 pll_clk.u_clk_pll/inst/sys_clk_clk_pll
|
|
r pll_clk.u_clk_pll/inst/clkout2_buf/I
|
|
BUFG (Prop_bufg_I_O) 0.091 16.643 r pll_clk.u_clk_pll/inst/clkout2_buf/O
|
|
net (fo=10994, unplaced) 0.655 17.297 u_matmul_axi_slave/sys_clk
|
|
FDSE r u_matmul_axi_slave/crc_reg_reg[16]/C
|
|
clock pessimism -0.468 16.830
|
|
clock uncertainty -0.071 16.759
|
|
FDSE (Setup_fdse_C_D) 0.029 16.788 u_matmul_axi_slave/crc_reg_reg[16]
|
|
-------------------------------------------------------------------
|
|
required time 16.788
|
|
arrival time -14.015
|
|
-------------------------------------------------------------------
|
|
slack 2.773
|
|
|
|
Slack (MET) : 2.773ns (required time - arrival time)
|
|
Source: u_matmul_axi_slave/mult_inst[0].u_mult/p_reg[1]/C
|
|
(rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Destination: u_matmul_axi_slave/crc_reg_reg[24]/D
|
|
(rising edge-triggered cell FDSE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Path Group: sys_clk
|
|
Path Type: Setup (Max at Slow Process Corner)
|
|
Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns)
|
|
Data Path Delay: 17.040ns (logic 4.444ns (26.080%) route 12.596ns (73.920%))
|
|
Logic Levels: 18 (CARRY4=3 LUT2=2 LUT4=1 LUT5=5 LUT6=7)
|
|
Clock Path Skew: -0.145ns (DCD - SCD + CPR)
|
|
Destination Clock Delay (DCD): -2.703ns = ( 17.297 - 20.000 )
|
|
Source Clock Delay (SCD): -3.025ns
|
|
Clock Pessimism Removal (CPR): -0.468ns
|
|
Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Discrete Jitter (DJ): 0.122ns
|
|
Phase Error (PE): 0.000ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock sys_clk rise edge) 0.000 0.000 r
|
|
K21 0.000 0.000 r clk (IN)
|
|
net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1
|
|
K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I
|
|
K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O
|
|
net (fo=1, unplaced) 0.584 2.047 pll_clk.u_clk_pll/inst/clk_in1_clk_pll
|
|
r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1
|
|
PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1)
|
|
-6.768 -4.721 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1
|
|
net (fo=1, unplaced) 0.800 -3.921 pll_clk.u_clk_pll/inst/sys_clk_clk_pll
|
|
r pll_clk.u_clk_pll/inst/clkout2_buf/I
|
|
BUFG (Prop_bufg_I_O) 0.096 -3.825 r pll_clk.u_clk_pll/inst/clkout2_buf/O
|
|
net (fo=10994, unplaced) 0.800 -3.025 u_matmul_axi_slave/mult_inst[0].u_mult/sys_clk
|
|
FDRE r u_matmul_axi_slave/mult_inst[0].u_mult/p_reg[1]/C
|
|
------------------------------------------------------------------- -------------------
|
|
FDRE (Prop_fdre_C_Q) 0.456 -2.569 r u_matmul_axi_slave/mult_inst[0].u_mult/p_reg[1]/Q
|
|
net (fo=2, unplaced) 0.481 -2.088 u_matmul_axi_slave/mult_inst[0].u_mult/mult_p[0]_0[1]
|
|
r u_matmul_axi_slave/mult_inst[0].u_mult/b1_c_reg_r1_0_15_0_5_i_20/I0
|
|
LUT2 (Prop_lut2_I0_O) 0.295 -1.793 r u_matmul_axi_slave/mult_inst[0].u_mult/b1_c_reg_r1_0_15_0_5_i_20/O
|
|
net (fo=1, unplaced) 0.000 -1.793 u_matmul_axi_slave/mult_inst[0].u_mult/b1_c_reg_r1_0_15_0_5_i_20_n_0
|
|
r u_matmul_axi_slave/mult_inst[0].u_mult/b1_c_reg_r1_0_15_0_5_i_8/S[1]
|
|
CARRY4 (Prop_carry4_S[1]_CO[3])
|
|
0.550 -1.243 r u_matmul_axi_slave/mult_inst[0].u_mult/b1_c_reg_r1_0_15_0_5_i_8/CO[3]
|
|
net (fo=1, unplaced) 0.009 -1.234 u_matmul_axi_slave/mult_inst[0].u_mult/b1_c_reg_r1_0_15_0_5_i_8_n_0
|
|
r u_matmul_axi_slave/mult_inst[0].u_mult/b1_c_reg_r1_0_15_0_5_i_13/CI
|
|
CARRY4 (Prop_carry4_CI_O[1])
|
|
0.348 -0.886 r u_matmul_axi_slave/mult_inst[0].u_mult/b1_c_reg_r1_0_15_0_5_i_13/O[1]
|
|
net (fo=2, unplaced) 0.622 -0.264 u_matmul_axi_slave/calc_c_result02_out[5]
|
|
r u_matmul_axi_slave/b1_c_reg_r1_0_15_0_5_i_16/I0
|
|
LUT2 (Prop_lut2_I0_O) 0.306 0.042 r u_matmul_axi_slave/b1_c_reg_r1_0_15_0_5_i_16/O
|
|
net (fo=1, unplaced) 0.000 0.042 u_matmul_axi_slave/b1_c_reg_r1_0_15_0_5_i_16_n_0
|
|
r u_matmul_axi_slave/b1_c_reg_r1_0_15_0_5_i_3/S[1]
|
|
CARRY4 (Prop_carry4_S[1]_O[3])
|
|
0.640 0.682 r u_matmul_axi_slave/b1_c_reg_r1_0_15_0_5_i_3/O[3]
|
|
net (fo=15, unplaced) 0.671 1.353 u_matmul_axi_slave/b1_c_reg_r1_0_15_0_5_i_3_n_4
|
|
r u_matmul_axi_slave/crc_reg[12]_i_91/I2
|
|
LUT6 (Prop_lut6_I2_O) 0.307 1.660 r u_matmul_axi_slave/crc_reg[12]_i_91/O
|
|
net (fo=3, unplaced) 0.920 2.580 u_matmul_axi_slave/crc_reg[12]_i_91_n_0
|
|
r u_matmul_axi_slave/crc_reg[12]_i_72/I3
|
|
LUT6 (Prop_lut6_I3_O) 0.124 2.704 r u_matmul_axi_slave/crc_reg[12]_i_72/O
|
|
net (fo=7, unplaced) 0.484 3.188 u_matmul_axi_slave/crc_reg[12]_i_72_n_0
|
|
r u_matmul_axi_slave/crc_reg[12]_i_64/I1
|
|
LUT6 (Prop_lut6_I1_O) 0.124 3.312 r u_matmul_axi_slave/crc_reg[12]_i_64/O
|
|
net (fo=11, unplaced) 0.948 4.260 u_matmul_axi_slave/crc32_word_next_return4[3]
|
|
r u_matmul_axi_slave/crc_reg[12]_i_52/I1
|
|
LUT6 (Prop_lut6_I1_O) 0.124 4.384 r u_matmul_axi_slave/crc_reg[12]_i_52/O
|
|
net (fo=11, unplaced) 1.157 5.541 u_matmul_axi_slave/crc32_word_next_return1[1]
|
|
r u_matmul_axi_slave/crc_reg[12]_i_39/I4
|
|
LUT6 (Prop_lut6_I4_O) 0.124 5.665 r u_matmul_axi_slave/crc_reg[12]_i_39/O
|
|
net (fo=10, unplaced) 0.945 6.610 u_matmul_axi_slave/crc32_word_next0_return10[5]
|
|
r u_matmul_axi_slave/crc_reg[12]_i_22/I1
|
|
LUT5 (Prop_lut5_I1_O) 0.124 6.734 r u_matmul_axi_slave/crc_reg[12]_i_22/O
|
|
net (fo=14, unplaced) 0.953 7.687 u_matmul_axi_slave/crc32_word_next0_return7[7]
|
|
r u_matmul_axi_slave/crc_reg[20]_i_16/I2
|
|
LUT6 (Prop_lut6_I2_O) 0.124 7.811 r u_matmul_axi_slave/crc_reg[20]_i_16/O
|
|
net (fo=11, unplaced) 0.948 8.759 u_matmul_axi_slave/crc32_word_next0_return4[5]
|
|
r u_matmul_axi_slave/crc_reg[31]_i_18/I1
|
|
LUT5 (Prop_lut5_I1_O) 0.124 8.883 r u_matmul_axi_slave/crc_reg[31]_i_18/O
|
|
net (fo=16, unplaced) 0.956 9.839 u_matmul_axi_slave/crc32_word_next0_return1[7]
|
|
r u_matmul_axi_slave/crc_reg[30]_i_10/I1
|
|
LUT5 (Prop_lut5_I1_O) 0.150 9.989 r u_matmul_axi_slave/crc_reg[30]_i_10/O
|
|
net (fo=1, unplaced) 1.111 11.100 u_matmul_axi_slave/crc32_word_next0_return0[22]
|
|
r u_matmul_axi_slave/crc_reg[30]_i_4/I0
|
|
LUT5 (Prop_lut5_I0_O) 0.152 11.252 r u_matmul_axi_slave/crc_reg[30]_i_4/O
|
|
net (fo=1, unplaced) 0.902 12.154 u_matmul_axi_slave/p_0_in0_in[8]
|
|
r u_matmul_axi_slave/crc_reg[30]_i_2/I2
|
|
LUT5 (Prop_lut5_I2_O) 0.124 12.278 r u_matmul_axi_slave/crc_reg[30]_i_2/O
|
|
net (fo=9, unplaced) 1.005 13.283 u_matmul_axi_slave/crc32_word_next1_return1[0]
|
|
r u_matmul_axi_slave/crc_reg[28]_i_2/I0
|
|
LUT6 (Prop_lut6_I0_O) 0.124 13.407 r u_matmul_axi_slave/crc_reg[28]_i_2/O
|
|
net (fo=7, unplaced) 0.484 13.891 u_matmul_axi_slave/crc_reg[28]_i_2_n_0
|
|
r u_matmul_axi_slave/crc_reg[24]_i_1/I3
|
|
LUT4 (Prop_lut4_I3_O) 0.124 14.015 r u_matmul_axi_slave/crc_reg[24]_i_1/O
|
|
net (fo=1, unplaced) 0.000 14.015 u_matmul_axi_slave/crc32_word_next1_return0[22]
|
|
FDSE r u_matmul_axi_slave/crc_reg_reg[24]/D
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock sys_clk rise edge) 20.000 20.000 r
|
|
K21 0.000 20.000 r clk (IN)
|
|
net (fo=0) 0.000 20.000 pll_clk.u_clk_pll/inst/clk_in1
|
|
K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I
|
|
K21 IBUF (Prop_ibuf_I_O) 1.393 21.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O
|
|
net (fo=1, unplaced) 0.439 21.832 pll_clk.u_clk_pll/inst/clk_in1_clk_pll
|
|
r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1
|
|
PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1)
|
|
-6.040 15.792 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1
|
|
net (fo=1, unplaced) 0.760 16.552 pll_clk.u_clk_pll/inst/sys_clk_clk_pll
|
|
r pll_clk.u_clk_pll/inst/clkout2_buf/I
|
|
BUFG (Prop_bufg_I_O) 0.091 16.643 r pll_clk.u_clk_pll/inst/clkout2_buf/O
|
|
net (fo=10994, unplaced) 0.655 17.297 u_matmul_axi_slave/sys_clk
|
|
FDSE r u_matmul_axi_slave/crc_reg_reg[24]/C
|
|
clock pessimism -0.468 16.830
|
|
clock uncertainty -0.071 16.759
|
|
FDSE (Setup_fdse_C_D) 0.029 16.788 u_matmul_axi_slave/crc_reg_reg[24]
|
|
-------------------------------------------------------------------
|
|
required time 16.788
|
|
arrival time -14.015
|
|
-------------------------------------------------------------------
|
|
slack 2.773
|
|
|
|
Slack (MET) : 2.773ns (required time - arrival time)
|
|
Source: u_matmul_axi_slave/mult_inst[0].u_mult/p_reg[1]/C
|
|
(rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Destination: u_matmul_axi_slave/crc_reg_reg[2]/D
|
|
(rising edge-triggered cell FDSE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Path Group: sys_clk
|
|
Path Type: Setup (Max at Slow Process Corner)
|
|
Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns)
|
|
Data Path Delay: 17.040ns (logic 4.444ns (26.080%) route 12.596ns (73.920%))
|
|
Logic Levels: 18 (CARRY4=3 LUT2=2 LUT3=1 LUT5=5 LUT6=7)
|
|
Clock Path Skew: -0.145ns (DCD - SCD + CPR)
|
|
Destination Clock Delay (DCD): -2.703ns = ( 17.297 - 20.000 )
|
|
Source Clock Delay (SCD): -3.025ns
|
|
Clock Pessimism Removal (CPR): -0.468ns
|
|
Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Discrete Jitter (DJ): 0.122ns
|
|
Phase Error (PE): 0.000ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock sys_clk rise edge) 0.000 0.000 r
|
|
K21 0.000 0.000 r clk (IN)
|
|
net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1
|
|
K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I
|
|
K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O
|
|
net (fo=1, unplaced) 0.584 2.047 pll_clk.u_clk_pll/inst/clk_in1_clk_pll
|
|
r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1
|
|
PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1)
|
|
-6.768 -4.721 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1
|
|
net (fo=1, unplaced) 0.800 -3.921 pll_clk.u_clk_pll/inst/sys_clk_clk_pll
|
|
r pll_clk.u_clk_pll/inst/clkout2_buf/I
|
|
BUFG (Prop_bufg_I_O) 0.096 -3.825 r pll_clk.u_clk_pll/inst/clkout2_buf/O
|
|
net (fo=10994, unplaced) 0.800 -3.025 u_matmul_axi_slave/mult_inst[0].u_mult/sys_clk
|
|
FDRE r u_matmul_axi_slave/mult_inst[0].u_mult/p_reg[1]/C
|
|
------------------------------------------------------------------- -------------------
|
|
FDRE (Prop_fdre_C_Q) 0.456 -2.569 r u_matmul_axi_slave/mult_inst[0].u_mult/p_reg[1]/Q
|
|
net (fo=2, unplaced) 0.481 -2.088 u_matmul_axi_slave/mult_inst[0].u_mult/mult_p[0]_0[1]
|
|
r u_matmul_axi_slave/mult_inst[0].u_mult/b1_c_reg_r1_0_15_0_5_i_20/I0
|
|
LUT2 (Prop_lut2_I0_O) 0.295 -1.793 r u_matmul_axi_slave/mult_inst[0].u_mult/b1_c_reg_r1_0_15_0_5_i_20/O
|
|
net (fo=1, unplaced) 0.000 -1.793 u_matmul_axi_slave/mult_inst[0].u_mult/b1_c_reg_r1_0_15_0_5_i_20_n_0
|
|
r u_matmul_axi_slave/mult_inst[0].u_mult/b1_c_reg_r1_0_15_0_5_i_8/S[1]
|
|
CARRY4 (Prop_carry4_S[1]_CO[3])
|
|
0.550 -1.243 r u_matmul_axi_slave/mult_inst[0].u_mult/b1_c_reg_r1_0_15_0_5_i_8/CO[3]
|
|
net (fo=1, unplaced) 0.009 -1.234 u_matmul_axi_slave/mult_inst[0].u_mult/b1_c_reg_r1_0_15_0_5_i_8_n_0
|
|
r u_matmul_axi_slave/mult_inst[0].u_mult/b1_c_reg_r1_0_15_0_5_i_13/CI
|
|
CARRY4 (Prop_carry4_CI_O[1])
|
|
0.348 -0.886 r u_matmul_axi_slave/mult_inst[0].u_mult/b1_c_reg_r1_0_15_0_5_i_13/O[1]
|
|
net (fo=2, unplaced) 0.622 -0.264 u_matmul_axi_slave/calc_c_result02_out[5]
|
|
r u_matmul_axi_slave/b1_c_reg_r1_0_15_0_5_i_16/I0
|
|
LUT2 (Prop_lut2_I0_O) 0.306 0.042 r u_matmul_axi_slave/b1_c_reg_r1_0_15_0_5_i_16/O
|
|
net (fo=1, unplaced) 0.000 0.042 u_matmul_axi_slave/b1_c_reg_r1_0_15_0_5_i_16_n_0
|
|
r u_matmul_axi_slave/b1_c_reg_r1_0_15_0_5_i_3/S[1]
|
|
CARRY4 (Prop_carry4_S[1]_O[3])
|
|
0.640 0.682 r u_matmul_axi_slave/b1_c_reg_r1_0_15_0_5_i_3/O[3]
|
|
net (fo=15, unplaced) 0.671 1.353 u_matmul_axi_slave/b1_c_reg_r1_0_15_0_5_i_3_n_4
|
|
r u_matmul_axi_slave/crc_reg[12]_i_91/I2
|
|
LUT6 (Prop_lut6_I2_O) 0.307 1.660 r u_matmul_axi_slave/crc_reg[12]_i_91/O
|
|
net (fo=3, unplaced) 0.920 2.580 u_matmul_axi_slave/crc_reg[12]_i_91_n_0
|
|
r u_matmul_axi_slave/crc_reg[12]_i_72/I3
|
|
LUT6 (Prop_lut6_I3_O) 0.124 2.704 r u_matmul_axi_slave/crc_reg[12]_i_72/O
|
|
net (fo=7, unplaced) 0.484 3.188 u_matmul_axi_slave/crc_reg[12]_i_72_n_0
|
|
r u_matmul_axi_slave/crc_reg[12]_i_64/I1
|
|
LUT6 (Prop_lut6_I1_O) 0.124 3.312 r u_matmul_axi_slave/crc_reg[12]_i_64/O
|
|
net (fo=11, unplaced) 0.948 4.260 u_matmul_axi_slave/crc32_word_next_return4[3]
|
|
r u_matmul_axi_slave/crc_reg[12]_i_52/I1
|
|
LUT6 (Prop_lut6_I1_O) 0.124 4.384 r u_matmul_axi_slave/crc_reg[12]_i_52/O
|
|
net (fo=11, unplaced) 1.157 5.541 u_matmul_axi_slave/crc32_word_next_return1[1]
|
|
r u_matmul_axi_slave/crc_reg[12]_i_39/I4
|
|
LUT6 (Prop_lut6_I4_O) 0.124 5.665 r u_matmul_axi_slave/crc_reg[12]_i_39/O
|
|
net (fo=10, unplaced) 0.945 6.610 u_matmul_axi_slave/crc32_word_next0_return10[5]
|
|
r u_matmul_axi_slave/crc_reg[12]_i_22/I1
|
|
LUT5 (Prop_lut5_I1_O) 0.124 6.734 r u_matmul_axi_slave/crc_reg[12]_i_22/O
|
|
net (fo=14, unplaced) 0.953 7.687 u_matmul_axi_slave/crc32_word_next0_return7[7]
|
|
r u_matmul_axi_slave/crc_reg[20]_i_16/I2
|
|
LUT6 (Prop_lut6_I2_O) 0.124 7.811 r u_matmul_axi_slave/crc_reg[20]_i_16/O
|
|
net (fo=11, unplaced) 0.948 8.759 u_matmul_axi_slave/crc32_word_next0_return4[5]
|
|
r u_matmul_axi_slave/crc_reg[31]_i_18/I1
|
|
LUT5 (Prop_lut5_I1_O) 0.124 8.883 r u_matmul_axi_slave/crc_reg[31]_i_18/O
|
|
net (fo=16, unplaced) 0.956 9.839 u_matmul_axi_slave/crc32_word_next0_return1[7]
|
|
r u_matmul_axi_slave/crc_reg[30]_i_10/I1
|
|
LUT5 (Prop_lut5_I1_O) 0.150 9.989 r u_matmul_axi_slave/crc_reg[30]_i_10/O
|
|
net (fo=1, unplaced) 1.111 11.100 u_matmul_axi_slave/crc32_word_next0_return0[22]
|
|
r u_matmul_axi_slave/crc_reg[30]_i_4/I0
|
|
LUT5 (Prop_lut5_I0_O) 0.152 11.252 r u_matmul_axi_slave/crc_reg[30]_i_4/O
|
|
net (fo=1, unplaced) 0.902 12.154 u_matmul_axi_slave/p_0_in0_in[8]
|
|
r u_matmul_axi_slave/crc_reg[30]_i_2/I2
|
|
LUT5 (Prop_lut5_I2_O) 0.124 12.278 r u_matmul_axi_slave/crc_reg[30]_i_2/O
|
|
net (fo=9, unplaced) 1.005 13.283 u_matmul_axi_slave/crc32_word_next1_return1[0]
|
|
r u_matmul_axi_slave/crc_reg[28]_i_2/I0
|
|
LUT6 (Prop_lut6_I0_O) 0.124 13.407 r u_matmul_axi_slave/crc_reg[28]_i_2/O
|
|
net (fo=7, unplaced) 0.484 13.891 u_matmul_axi_slave/crc_reg[28]_i_2_n_0
|
|
r u_matmul_axi_slave/crc_reg[2]_i_1/I2
|
|
LUT3 (Prop_lut3_I2_O) 0.124 14.015 r u_matmul_axi_slave/crc_reg[2]_i_1/O
|
|
net (fo=1, unplaced) 0.000 14.015 u_matmul_axi_slave/crc32_word_next1_return[2]
|
|
FDSE r u_matmul_axi_slave/crc_reg_reg[2]/D
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock sys_clk rise edge) 20.000 20.000 r
|
|
K21 0.000 20.000 r clk (IN)
|
|
net (fo=0) 0.000 20.000 pll_clk.u_clk_pll/inst/clk_in1
|
|
K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I
|
|
K21 IBUF (Prop_ibuf_I_O) 1.393 21.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O
|
|
net (fo=1, unplaced) 0.439 21.832 pll_clk.u_clk_pll/inst/clk_in1_clk_pll
|
|
r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1
|
|
PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1)
|
|
-6.040 15.792 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1
|
|
net (fo=1, unplaced) 0.760 16.552 pll_clk.u_clk_pll/inst/sys_clk_clk_pll
|
|
r pll_clk.u_clk_pll/inst/clkout2_buf/I
|
|
BUFG (Prop_bufg_I_O) 0.091 16.643 r pll_clk.u_clk_pll/inst/clkout2_buf/O
|
|
net (fo=10994, unplaced) 0.655 17.297 u_matmul_axi_slave/sys_clk
|
|
FDSE r u_matmul_axi_slave/crc_reg_reg[2]/C
|
|
clock pessimism -0.468 16.830
|
|
clock uncertainty -0.071 16.759
|
|
FDSE (Setup_fdse_C_D) 0.029 16.788 u_matmul_axi_slave/crc_reg_reg[2]
|
|
-------------------------------------------------------------------
|
|
required time 16.788
|
|
arrival time -14.015
|
|
-------------------------------------------------------------------
|
|
slack 2.773
|
|
|
|
Slack (MET) : 2.779ns (required time - arrival time)
|
|
Source: u_matmul_axi_slave/mult_inst[0].u_mult/p_reg[1]/C
|
|
(rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Destination: u_matmul_axi_slave/crc_reg_reg[28]/D
|
|
(rising edge-triggered cell FDSE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Path Group: sys_clk
|
|
Path Type: Setup (Max at Slow Process Corner)
|
|
Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns)
|
|
Data Path Delay: 17.034ns (logic 4.438ns (26.054%) route 12.596ns (73.946%))
|
|
Logic Levels: 18 (CARRY4=3 LUT2=2 LUT3=1 LUT5=5 LUT6=7)
|
|
Clock Path Skew: -0.145ns (DCD - SCD + CPR)
|
|
Destination Clock Delay (DCD): -2.703ns = ( 17.297 - 20.000 )
|
|
Source Clock Delay (SCD): -3.025ns
|
|
Clock Pessimism Removal (CPR): -0.468ns
|
|
Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Discrete Jitter (DJ): 0.122ns
|
|
Phase Error (PE): 0.000ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock sys_clk rise edge) 0.000 0.000 r
|
|
K21 0.000 0.000 r clk (IN)
|
|
net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1
|
|
K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I
|
|
K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O
|
|
net (fo=1, unplaced) 0.584 2.047 pll_clk.u_clk_pll/inst/clk_in1_clk_pll
|
|
r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1
|
|
PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1)
|
|
-6.768 -4.721 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1
|
|
net (fo=1, unplaced) 0.800 -3.921 pll_clk.u_clk_pll/inst/sys_clk_clk_pll
|
|
r pll_clk.u_clk_pll/inst/clkout2_buf/I
|
|
BUFG (Prop_bufg_I_O) 0.096 -3.825 r pll_clk.u_clk_pll/inst/clkout2_buf/O
|
|
net (fo=10994, unplaced) 0.800 -3.025 u_matmul_axi_slave/mult_inst[0].u_mult/sys_clk
|
|
FDRE r u_matmul_axi_slave/mult_inst[0].u_mult/p_reg[1]/C
|
|
------------------------------------------------------------------- -------------------
|
|
FDRE (Prop_fdre_C_Q) 0.456 -2.569 r u_matmul_axi_slave/mult_inst[0].u_mult/p_reg[1]/Q
|
|
net (fo=2, unplaced) 0.481 -2.088 u_matmul_axi_slave/mult_inst[0].u_mult/mult_p[0]_0[1]
|
|
r u_matmul_axi_slave/mult_inst[0].u_mult/b1_c_reg_r1_0_15_0_5_i_20/I0
|
|
LUT2 (Prop_lut2_I0_O) 0.295 -1.793 r u_matmul_axi_slave/mult_inst[0].u_mult/b1_c_reg_r1_0_15_0_5_i_20/O
|
|
net (fo=1, unplaced) 0.000 -1.793 u_matmul_axi_slave/mult_inst[0].u_mult/b1_c_reg_r1_0_15_0_5_i_20_n_0
|
|
r u_matmul_axi_slave/mult_inst[0].u_mult/b1_c_reg_r1_0_15_0_5_i_8/S[1]
|
|
CARRY4 (Prop_carry4_S[1]_CO[3])
|
|
0.550 -1.243 r u_matmul_axi_slave/mult_inst[0].u_mult/b1_c_reg_r1_0_15_0_5_i_8/CO[3]
|
|
net (fo=1, unplaced) 0.009 -1.234 u_matmul_axi_slave/mult_inst[0].u_mult/b1_c_reg_r1_0_15_0_5_i_8_n_0
|
|
r u_matmul_axi_slave/mult_inst[0].u_mult/b1_c_reg_r1_0_15_0_5_i_13/CI
|
|
CARRY4 (Prop_carry4_CI_O[1])
|
|
0.348 -0.886 r u_matmul_axi_slave/mult_inst[0].u_mult/b1_c_reg_r1_0_15_0_5_i_13/O[1]
|
|
net (fo=2, unplaced) 0.622 -0.264 u_matmul_axi_slave/calc_c_result02_out[5]
|
|
r u_matmul_axi_slave/b1_c_reg_r1_0_15_0_5_i_16/I0
|
|
LUT2 (Prop_lut2_I0_O) 0.306 0.042 r u_matmul_axi_slave/b1_c_reg_r1_0_15_0_5_i_16/O
|
|
net (fo=1, unplaced) 0.000 0.042 u_matmul_axi_slave/b1_c_reg_r1_0_15_0_5_i_16_n_0
|
|
r u_matmul_axi_slave/b1_c_reg_r1_0_15_0_5_i_3/S[1]
|
|
CARRY4 (Prop_carry4_S[1]_O[3])
|
|
0.640 0.682 r u_matmul_axi_slave/b1_c_reg_r1_0_15_0_5_i_3/O[3]
|
|
net (fo=15, unplaced) 0.671 1.353 u_matmul_axi_slave/b1_c_reg_r1_0_15_0_5_i_3_n_4
|
|
r u_matmul_axi_slave/crc_reg[12]_i_91/I2
|
|
LUT6 (Prop_lut6_I2_O) 0.307 1.660 r u_matmul_axi_slave/crc_reg[12]_i_91/O
|
|
net (fo=3, unplaced) 0.920 2.580 u_matmul_axi_slave/crc_reg[12]_i_91_n_0
|
|
r u_matmul_axi_slave/crc_reg[12]_i_72/I3
|
|
LUT6 (Prop_lut6_I3_O) 0.124 2.704 r u_matmul_axi_slave/crc_reg[12]_i_72/O
|
|
net (fo=7, unplaced) 0.484 3.188 u_matmul_axi_slave/crc_reg[12]_i_72_n_0
|
|
r u_matmul_axi_slave/crc_reg[12]_i_64/I1
|
|
LUT6 (Prop_lut6_I1_O) 0.124 3.312 r u_matmul_axi_slave/crc_reg[12]_i_64/O
|
|
net (fo=11, unplaced) 0.948 4.260 u_matmul_axi_slave/crc32_word_next_return4[3]
|
|
r u_matmul_axi_slave/crc_reg[12]_i_52/I1
|
|
LUT6 (Prop_lut6_I1_O) 0.124 4.384 r u_matmul_axi_slave/crc_reg[12]_i_52/O
|
|
net (fo=11, unplaced) 1.157 5.541 u_matmul_axi_slave/crc32_word_next_return1[1]
|
|
r u_matmul_axi_slave/crc_reg[12]_i_39/I4
|
|
LUT6 (Prop_lut6_I4_O) 0.124 5.665 r u_matmul_axi_slave/crc_reg[12]_i_39/O
|
|
net (fo=10, unplaced) 0.945 6.610 u_matmul_axi_slave/crc32_word_next0_return10[5]
|
|
r u_matmul_axi_slave/crc_reg[12]_i_22/I1
|
|
LUT5 (Prop_lut5_I1_O) 0.124 6.734 r u_matmul_axi_slave/crc_reg[12]_i_22/O
|
|
net (fo=14, unplaced) 0.953 7.687 u_matmul_axi_slave/crc32_word_next0_return7[7]
|
|
r u_matmul_axi_slave/crc_reg[20]_i_16/I2
|
|
LUT6 (Prop_lut6_I2_O) 0.124 7.811 r u_matmul_axi_slave/crc_reg[20]_i_16/O
|
|
net (fo=11, unplaced) 0.948 8.759 u_matmul_axi_slave/crc32_word_next0_return4[5]
|
|
r u_matmul_axi_slave/crc_reg[31]_i_18/I1
|
|
LUT5 (Prop_lut5_I1_O) 0.124 8.883 r u_matmul_axi_slave/crc_reg[31]_i_18/O
|
|
net (fo=16, unplaced) 0.956 9.839 u_matmul_axi_slave/crc32_word_next0_return1[7]
|
|
r u_matmul_axi_slave/crc_reg[30]_i_10/I1
|
|
LUT5 (Prop_lut5_I1_O) 0.150 9.989 r u_matmul_axi_slave/crc_reg[30]_i_10/O
|
|
net (fo=1, unplaced) 1.111 11.100 u_matmul_axi_slave/crc32_word_next0_return0[22]
|
|
r u_matmul_axi_slave/crc_reg[30]_i_4/I0
|
|
LUT5 (Prop_lut5_I0_O) 0.152 11.252 r u_matmul_axi_slave/crc_reg[30]_i_4/O
|
|
net (fo=1, unplaced) 0.902 12.154 u_matmul_axi_slave/p_0_in0_in[8]
|
|
r u_matmul_axi_slave/crc_reg[30]_i_2/I2
|
|
LUT5 (Prop_lut5_I2_O) 0.124 12.278 r u_matmul_axi_slave/crc_reg[30]_i_2/O
|
|
net (fo=9, unplaced) 1.005 13.283 u_matmul_axi_slave/crc32_word_next1_return1[0]
|
|
r u_matmul_axi_slave/crc_reg[28]_i_2/I0
|
|
LUT6 (Prop_lut6_I0_O) 0.124 13.407 r u_matmul_axi_slave/crc_reg[28]_i_2/O
|
|
net (fo=7, unplaced) 0.484 13.891 u_matmul_axi_slave/crc_reg[28]_i_2_n_0
|
|
r u_matmul_axi_slave/crc_reg[28]_i_1/I2
|
|
LUT3 (Prop_lut3_I2_O) 0.118 14.009 r u_matmul_axi_slave/crc_reg[28]_i_1/O
|
|
net (fo=1, unplaced) 0.000 14.009 u_matmul_axi_slave/crc32_word_next1_return0[26]
|
|
FDSE r u_matmul_axi_slave/crc_reg_reg[28]/D
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock sys_clk rise edge) 20.000 20.000 r
|
|
K21 0.000 20.000 r clk (IN)
|
|
net (fo=0) 0.000 20.000 pll_clk.u_clk_pll/inst/clk_in1
|
|
K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I
|
|
K21 IBUF (Prop_ibuf_I_O) 1.393 21.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O
|
|
net (fo=1, unplaced) 0.439 21.832 pll_clk.u_clk_pll/inst/clk_in1_clk_pll
|
|
r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1
|
|
PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1)
|
|
-6.040 15.792 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1
|
|
net (fo=1, unplaced) 0.760 16.552 pll_clk.u_clk_pll/inst/sys_clk_clk_pll
|
|
r pll_clk.u_clk_pll/inst/clkout2_buf/I
|
|
BUFG (Prop_bufg_I_O) 0.091 16.643 r pll_clk.u_clk_pll/inst/clkout2_buf/O
|
|
net (fo=10994, unplaced) 0.655 17.297 u_matmul_axi_slave/sys_clk
|
|
FDSE r u_matmul_axi_slave/crc_reg_reg[28]/C
|
|
clock pessimism -0.468 16.830
|
|
clock uncertainty -0.071 16.759
|
|
FDSE (Setup_fdse_C_D) 0.029 16.788 u_matmul_axi_slave/crc_reg_reg[28]
|
|
-------------------------------------------------------------------
|
|
required time 16.788
|
|
arrival time -14.009
|
|
-------------------------------------------------------------------
|
|
slack 2.779
|
|
|
|
Slack (MET) : 2.814ns (required time - arrival time)
|
|
Source: u_matmul_axi_slave/mult_inst[0].u_mult/p_reg[1]/C
|
|
(rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Destination: u_matmul_axi_slave/crc_reg_reg[30]/D
|
|
(rising edge-triggered cell FDSE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Path Group: sys_clk
|
|
Path Type: Setup (Max at Slow Process Corner)
|
|
Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns)
|
|
Data Path Delay: 16.999ns (logic 4.444ns (26.143%) route 12.555ns (73.857%))
|
|
Logic Levels: 18 (CARRY4=3 LUT2=2 LUT4=2 LUT5=3 LUT6=8)
|
|
Clock Path Skew: -0.145ns (DCD - SCD + CPR)
|
|
Destination Clock Delay (DCD): -2.703ns = ( 17.297 - 20.000 )
|
|
Source Clock Delay (SCD): -3.025ns
|
|
Clock Pessimism Removal (CPR): -0.468ns
|
|
Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Discrete Jitter (DJ): 0.122ns
|
|
Phase Error (PE): 0.000ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock sys_clk rise edge) 0.000 0.000 r
|
|
K21 0.000 0.000 r clk (IN)
|
|
net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1
|
|
K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I
|
|
K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O
|
|
net (fo=1, unplaced) 0.584 2.047 pll_clk.u_clk_pll/inst/clk_in1_clk_pll
|
|
r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1
|
|
PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1)
|
|
-6.768 -4.721 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1
|
|
net (fo=1, unplaced) 0.800 -3.921 pll_clk.u_clk_pll/inst/sys_clk_clk_pll
|
|
r pll_clk.u_clk_pll/inst/clkout2_buf/I
|
|
BUFG (Prop_bufg_I_O) 0.096 -3.825 r pll_clk.u_clk_pll/inst/clkout2_buf/O
|
|
net (fo=10994, unplaced) 0.800 -3.025 u_matmul_axi_slave/mult_inst[0].u_mult/sys_clk
|
|
FDRE r u_matmul_axi_slave/mult_inst[0].u_mult/p_reg[1]/C
|
|
------------------------------------------------------------------- -------------------
|
|
FDRE (Prop_fdre_C_Q) 0.456 -2.569 r u_matmul_axi_slave/mult_inst[0].u_mult/p_reg[1]/Q
|
|
net (fo=2, unplaced) 0.481 -2.088 u_matmul_axi_slave/mult_inst[0].u_mult/mult_p[0]_0[1]
|
|
r u_matmul_axi_slave/mult_inst[0].u_mult/b1_c_reg_r1_0_15_0_5_i_20/I0
|
|
LUT2 (Prop_lut2_I0_O) 0.295 -1.793 r u_matmul_axi_slave/mult_inst[0].u_mult/b1_c_reg_r1_0_15_0_5_i_20/O
|
|
net (fo=1, unplaced) 0.000 -1.793 u_matmul_axi_slave/mult_inst[0].u_mult/b1_c_reg_r1_0_15_0_5_i_20_n_0
|
|
r u_matmul_axi_slave/mult_inst[0].u_mult/b1_c_reg_r1_0_15_0_5_i_8/S[1]
|
|
CARRY4 (Prop_carry4_S[1]_CO[3])
|
|
0.550 -1.243 r u_matmul_axi_slave/mult_inst[0].u_mult/b1_c_reg_r1_0_15_0_5_i_8/CO[3]
|
|
net (fo=1, unplaced) 0.009 -1.234 u_matmul_axi_slave/mult_inst[0].u_mult/b1_c_reg_r1_0_15_0_5_i_8_n_0
|
|
r u_matmul_axi_slave/mult_inst[0].u_mult/b1_c_reg_r1_0_15_0_5_i_13/CI
|
|
CARRY4 (Prop_carry4_CI_O[1])
|
|
0.348 -0.886 r u_matmul_axi_slave/mult_inst[0].u_mult/b1_c_reg_r1_0_15_0_5_i_13/O[1]
|
|
net (fo=2, unplaced) 0.622 -0.264 u_matmul_axi_slave/calc_c_result02_out[5]
|
|
r u_matmul_axi_slave/b1_c_reg_r1_0_15_0_5_i_16/I0
|
|
LUT2 (Prop_lut2_I0_O) 0.306 0.042 r u_matmul_axi_slave/b1_c_reg_r1_0_15_0_5_i_16/O
|
|
net (fo=1, unplaced) 0.000 0.042 u_matmul_axi_slave/b1_c_reg_r1_0_15_0_5_i_16_n_0
|
|
r u_matmul_axi_slave/b1_c_reg_r1_0_15_0_5_i_3/S[1]
|
|
CARRY4 (Prop_carry4_S[1]_O[3])
|
|
0.640 0.682 r u_matmul_axi_slave/b1_c_reg_r1_0_15_0_5_i_3/O[3]
|
|
net (fo=15, unplaced) 0.671 1.353 u_matmul_axi_slave/b1_c_reg_r1_0_15_0_5_i_3_n_4
|
|
r u_matmul_axi_slave/crc_reg[12]_i_91/I2
|
|
LUT6 (Prop_lut6_I2_O) 0.307 1.660 r u_matmul_axi_slave/crc_reg[12]_i_91/O
|
|
net (fo=3, unplaced) 0.920 2.580 u_matmul_axi_slave/crc_reg[12]_i_91_n_0
|
|
r u_matmul_axi_slave/crc_reg[12]_i_72/I3
|
|
LUT6 (Prop_lut6_I3_O) 0.124 2.704 r u_matmul_axi_slave/crc_reg[12]_i_72/O
|
|
net (fo=7, unplaced) 0.484 3.188 u_matmul_axi_slave/crc_reg[12]_i_72_n_0
|
|
r u_matmul_axi_slave/crc_reg[12]_i_64/I1
|
|
LUT6 (Prop_lut6_I1_O) 0.124 3.312 r u_matmul_axi_slave/crc_reg[12]_i_64/O
|
|
net (fo=11, unplaced) 0.948 4.260 u_matmul_axi_slave/crc32_word_next_return4[3]
|
|
r u_matmul_axi_slave/crc_reg[12]_i_52/I1
|
|
LUT6 (Prop_lut6_I1_O) 0.124 4.384 r u_matmul_axi_slave/crc_reg[12]_i_52/O
|
|
net (fo=11, unplaced) 1.157 5.541 u_matmul_axi_slave/crc32_word_next_return1[1]
|
|
r u_matmul_axi_slave/crc_reg[12]_i_39/I4
|
|
LUT6 (Prop_lut6_I4_O) 0.124 5.665 r u_matmul_axi_slave/crc_reg[12]_i_39/O
|
|
net (fo=10, unplaced) 0.945 6.610 u_matmul_axi_slave/crc32_word_next0_return10[5]
|
|
r u_matmul_axi_slave/crc_reg[12]_i_22/I1
|
|
LUT5 (Prop_lut5_I1_O) 0.124 6.734 r u_matmul_axi_slave/crc_reg[12]_i_22/O
|
|
net (fo=14, unplaced) 0.953 7.687 u_matmul_axi_slave/crc32_word_next0_return7[7]
|
|
r u_matmul_axi_slave/crc_reg[20]_i_16/I2
|
|
LUT6 (Prop_lut6_I2_O) 0.124 7.811 r u_matmul_axi_slave/crc_reg[20]_i_16/O
|
|
net (fo=11, unplaced) 0.948 8.759 u_matmul_axi_slave/crc32_word_next0_return4[5]
|
|
r u_matmul_axi_slave/crc_reg[31]_i_18/I1
|
|
LUT5 (Prop_lut5_I1_O) 0.124 8.883 r u_matmul_axi_slave/crc_reg[31]_i_18/O
|
|
net (fo=16, unplaced) 0.956 9.839 u_matmul_axi_slave/crc32_word_next0_return1[7]
|
|
r u_matmul_axi_slave/crc_reg[20]_i_14/I1
|
|
LUT4 (Prop_lut4_I1_O) 0.124 9.963 r u_matmul_axi_slave/crc_reg[20]_i_14/O
|
|
net (fo=1, unplaced) 0.902 10.865 u_matmul_axi_slave/crc32_word_next0_return0[21]
|
|
r u_matmul_axi_slave/crc_reg[20]_i_6/I0
|
|
LUT6 (Prop_lut6_I0_O) 0.124 10.989 r u_matmul_axi_slave/crc_reg[20]_i_6/O
|
|
net (fo=2, unplaced) 1.122 12.111 u_matmul_axi_slave/p_0_in0_in[4]
|
|
r u_matmul_axi_slave/crc_reg[30]_i_9/I0
|
|
LUT5 (Prop_lut5_I0_O) 0.152 12.263 r u_matmul_axi_slave/crc_reg[30]_i_9/O
|
|
net (fo=7, unplaced) 0.484 12.747 u_matmul_axi_slave/crc32_word_next1_return4[4]
|
|
r u_matmul_axi_slave/crc_reg[30]_i_3/I5
|
|
LUT6 (Prop_lut6_I5_O) 0.124 12.871 r u_matmul_axi_slave/crc_reg[30]_i_3/O
|
|
net (fo=14, unplaced) 0.953 13.824 u_matmul_axi_slave/crc32_word_next1_return1[6]
|
|
r u_matmul_axi_slave/crc_reg[30]_i_1/I1
|
|
LUT4 (Prop_lut4_I1_O) 0.150 13.974 r u_matmul_axi_slave/crc_reg[30]_i_1/O
|
|
net (fo=1, unplaced) 0.000 13.974 u_matmul_axi_slave/crc32_word_next1_return0[28]
|
|
FDSE r u_matmul_axi_slave/crc_reg_reg[30]/D
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock sys_clk rise edge) 20.000 20.000 r
|
|
K21 0.000 20.000 r clk (IN)
|
|
net (fo=0) 0.000 20.000 pll_clk.u_clk_pll/inst/clk_in1
|
|
K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I
|
|
K21 IBUF (Prop_ibuf_I_O) 1.393 21.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O
|
|
net (fo=1, unplaced) 0.439 21.832 pll_clk.u_clk_pll/inst/clk_in1_clk_pll
|
|
r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1
|
|
PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1)
|
|
-6.040 15.792 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1
|
|
net (fo=1, unplaced) 0.760 16.552 pll_clk.u_clk_pll/inst/sys_clk_clk_pll
|
|
r pll_clk.u_clk_pll/inst/clkout2_buf/I
|
|
BUFG (Prop_bufg_I_O) 0.091 16.643 r pll_clk.u_clk_pll/inst/clkout2_buf/O
|
|
net (fo=10994, unplaced) 0.655 17.297 u_matmul_axi_slave/sys_clk
|
|
FDSE r u_matmul_axi_slave/crc_reg_reg[30]/C
|
|
clock pessimism -0.468 16.830
|
|
clock uncertainty -0.071 16.759
|
|
FDSE (Setup_fdse_C_D) 0.029 16.788 u_matmul_axi_slave/crc_reg_reg[30]
|
|
-------------------------------------------------------------------
|
|
required time 16.788
|
|
arrival time -13.974
|
|
-------------------------------------------------------------------
|
|
slack 2.814
|
|
|
|
Slack (MET) : 2.840ns (required time - arrival time)
|
|
Source: u_matmul_axi_slave/mult_inst[0].u_mult/p_reg[1]/C
|
|
(rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Destination: u_matmul_axi_slave/crc_reg_reg[20]/D
|
|
(rising edge-triggered cell FDSE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Path Group: sys_clk
|
|
Path Type: Setup (Max at Slow Process Corner)
|
|
Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns)
|
|
Data Path Delay: 16.973ns (logic 4.418ns (26.030%) route 12.555ns (73.970%))
|
|
Logic Levels: 18 (CARRY4=3 LUT2=2 LUT4=1 LUT5=3 LUT6=9)
|
|
Clock Path Skew: -0.145ns (DCD - SCD + CPR)
|
|
Destination Clock Delay (DCD): -2.703ns = ( 17.297 - 20.000 )
|
|
Source Clock Delay (SCD): -3.025ns
|
|
Clock Pessimism Removal (CPR): -0.468ns
|
|
Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Discrete Jitter (DJ): 0.122ns
|
|
Phase Error (PE): 0.000ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock sys_clk rise edge) 0.000 0.000 r
|
|
K21 0.000 0.000 r clk (IN)
|
|
net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1
|
|
K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I
|
|
K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O
|
|
net (fo=1, unplaced) 0.584 2.047 pll_clk.u_clk_pll/inst/clk_in1_clk_pll
|
|
r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1
|
|
PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1)
|
|
-6.768 -4.721 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1
|
|
net (fo=1, unplaced) 0.800 -3.921 pll_clk.u_clk_pll/inst/sys_clk_clk_pll
|
|
r pll_clk.u_clk_pll/inst/clkout2_buf/I
|
|
BUFG (Prop_bufg_I_O) 0.096 -3.825 r pll_clk.u_clk_pll/inst/clkout2_buf/O
|
|
net (fo=10994, unplaced) 0.800 -3.025 u_matmul_axi_slave/mult_inst[0].u_mult/sys_clk
|
|
FDRE r u_matmul_axi_slave/mult_inst[0].u_mult/p_reg[1]/C
|
|
------------------------------------------------------------------- -------------------
|
|
FDRE (Prop_fdre_C_Q) 0.456 -2.569 r u_matmul_axi_slave/mult_inst[0].u_mult/p_reg[1]/Q
|
|
net (fo=2, unplaced) 0.481 -2.088 u_matmul_axi_slave/mult_inst[0].u_mult/mult_p[0]_0[1]
|
|
r u_matmul_axi_slave/mult_inst[0].u_mult/b1_c_reg_r1_0_15_0_5_i_20/I0
|
|
LUT2 (Prop_lut2_I0_O) 0.295 -1.793 r u_matmul_axi_slave/mult_inst[0].u_mult/b1_c_reg_r1_0_15_0_5_i_20/O
|
|
net (fo=1, unplaced) 0.000 -1.793 u_matmul_axi_slave/mult_inst[0].u_mult/b1_c_reg_r1_0_15_0_5_i_20_n_0
|
|
r u_matmul_axi_slave/mult_inst[0].u_mult/b1_c_reg_r1_0_15_0_5_i_8/S[1]
|
|
CARRY4 (Prop_carry4_S[1]_CO[3])
|
|
0.550 -1.243 r u_matmul_axi_slave/mult_inst[0].u_mult/b1_c_reg_r1_0_15_0_5_i_8/CO[3]
|
|
net (fo=1, unplaced) 0.009 -1.234 u_matmul_axi_slave/mult_inst[0].u_mult/b1_c_reg_r1_0_15_0_5_i_8_n_0
|
|
r u_matmul_axi_slave/mult_inst[0].u_mult/b1_c_reg_r1_0_15_0_5_i_13/CI
|
|
CARRY4 (Prop_carry4_CI_O[1])
|
|
0.348 -0.886 r u_matmul_axi_slave/mult_inst[0].u_mult/b1_c_reg_r1_0_15_0_5_i_13/O[1]
|
|
net (fo=2, unplaced) 0.622 -0.264 u_matmul_axi_slave/calc_c_result02_out[5]
|
|
r u_matmul_axi_slave/b1_c_reg_r1_0_15_0_5_i_16/I0
|
|
LUT2 (Prop_lut2_I0_O) 0.306 0.042 r u_matmul_axi_slave/b1_c_reg_r1_0_15_0_5_i_16/O
|
|
net (fo=1, unplaced) 0.000 0.042 u_matmul_axi_slave/b1_c_reg_r1_0_15_0_5_i_16_n_0
|
|
r u_matmul_axi_slave/b1_c_reg_r1_0_15_0_5_i_3/S[1]
|
|
CARRY4 (Prop_carry4_S[1]_O[3])
|
|
0.640 0.682 r u_matmul_axi_slave/b1_c_reg_r1_0_15_0_5_i_3/O[3]
|
|
net (fo=15, unplaced) 0.671 1.353 u_matmul_axi_slave/b1_c_reg_r1_0_15_0_5_i_3_n_4
|
|
r u_matmul_axi_slave/crc_reg[12]_i_91/I2
|
|
LUT6 (Prop_lut6_I2_O) 0.307 1.660 r u_matmul_axi_slave/crc_reg[12]_i_91/O
|
|
net (fo=3, unplaced) 0.920 2.580 u_matmul_axi_slave/crc_reg[12]_i_91_n_0
|
|
r u_matmul_axi_slave/crc_reg[12]_i_72/I3
|
|
LUT6 (Prop_lut6_I3_O) 0.124 2.704 r u_matmul_axi_slave/crc_reg[12]_i_72/O
|
|
net (fo=7, unplaced) 0.484 3.188 u_matmul_axi_slave/crc_reg[12]_i_72_n_0
|
|
r u_matmul_axi_slave/crc_reg[12]_i_64/I1
|
|
LUT6 (Prop_lut6_I1_O) 0.124 3.312 r u_matmul_axi_slave/crc_reg[12]_i_64/O
|
|
net (fo=11, unplaced) 0.948 4.260 u_matmul_axi_slave/crc32_word_next_return4[3]
|
|
r u_matmul_axi_slave/crc_reg[12]_i_52/I1
|
|
LUT6 (Prop_lut6_I1_O) 0.124 4.384 r u_matmul_axi_slave/crc_reg[12]_i_52/O
|
|
net (fo=11, unplaced) 1.157 5.541 u_matmul_axi_slave/crc32_word_next_return1[1]
|
|
r u_matmul_axi_slave/crc_reg[12]_i_39/I4
|
|
LUT6 (Prop_lut6_I4_O) 0.124 5.665 r u_matmul_axi_slave/crc_reg[12]_i_39/O
|
|
net (fo=10, unplaced) 0.945 6.610 u_matmul_axi_slave/crc32_word_next0_return10[5]
|
|
r u_matmul_axi_slave/crc_reg[12]_i_22/I1
|
|
LUT5 (Prop_lut5_I1_O) 0.124 6.734 r u_matmul_axi_slave/crc_reg[12]_i_22/O
|
|
net (fo=14, unplaced) 0.953 7.687 u_matmul_axi_slave/crc32_word_next0_return7[7]
|
|
r u_matmul_axi_slave/crc_reg[20]_i_16/I2
|
|
LUT6 (Prop_lut6_I2_O) 0.124 7.811 r u_matmul_axi_slave/crc_reg[20]_i_16/O
|
|
net (fo=11, unplaced) 0.948 8.759 u_matmul_axi_slave/crc32_word_next0_return4[5]
|
|
r u_matmul_axi_slave/crc_reg[31]_i_18/I1
|
|
LUT5 (Prop_lut5_I1_O) 0.124 8.883 r u_matmul_axi_slave/crc_reg[31]_i_18/O
|
|
net (fo=16, unplaced) 0.956 9.839 u_matmul_axi_slave/crc32_word_next0_return1[7]
|
|
r u_matmul_axi_slave/crc_reg[20]_i_14/I1
|
|
LUT4 (Prop_lut4_I1_O) 0.124 9.963 r u_matmul_axi_slave/crc_reg[20]_i_14/O
|
|
net (fo=1, unplaced) 0.902 10.865 u_matmul_axi_slave/crc32_word_next0_return0[21]
|
|
r u_matmul_axi_slave/crc_reg[20]_i_6/I0
|
|
LUT6 (Prop_lut6_I0_O) 0.124 10.989 r u_matmul_axi_slave/crc_reg[20]_i_6/O
|
|
net (fo=2, unplaced) 1.122 12.111 u_matmul_axi_slave/p_0_in0_in[4]
|
|
r u_matmul_axi_slave/crc_reg[30]_i_9/I0
|
|
LUT5 (Prop_lut5_I0_O) 0.152 12.263 r u_matmul_axi_slave/crc_reg[30]_i_9/O
|
|
net (fo=7, unplaced) 0.484 12.747 u_matmul_axi_slave/crc32_word_next1_return4[4]
|
|
r u_matmul_axi_slave/crc_reg[30]_i_3/I5
|
|
LUT6 (Prop_lut6_I5_O) 0.124 12.871 r u_matmul_axi_slave/crc_reg[30]_i_3/O
|
|
net (fo=14, unplaced) 0.953 13.824 u_matmul_axi_slave/crc32_word_next1_return1[6]
|
|
r u_matmul_axi_slave/crc_reg[20]_i_1/I3
|
|
LUT6 (Prop_lut6_I3_O) 0.124 13.948 r u_matmul_axi_slave/crc_reg[20]_i_1/O
|
|
net (fo=1, unplaced) 0.000 13.948 u_matmul_axi_slave/crc32_word_next1_return[20]
|
|
FDSE r u_matmul_axi_slave/crc_reg_reg[20]/D
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock sys_clk rise edge) 20.000 20.000 r
|
|
K21 0.000 20.000 r clk (IN)
|
|
net (fo=0) 0.000 20.000 pll_clk.u_clk_pll/inst/clk_in1
|
|
K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I
|
|
K21 IBUF (Prop_ibuf_I_O) 1.393 21.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O
|
|
net (fo=1, unplaced) 0.439 21.832 pll_clk.u_clk_pll/inst/clk_in1_clk_pll
|
|
r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1
|
|
PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1)
|
|
-6.040 15.792 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1
|
|
net (fo=1, unplaced) 0.760 16.552 pll_clk.u_clk_pll/inst/sys_clk_clk_pll
|
|
r pll_clk.u_clk_pll/inst/clkout2_buf/I
|
|
BUFG (Prop_bufg_I_O) 0.091 16.643 r pll_clk.u_clk_pll/inst/clkout2_buf/O
|
|
net (fo=10994, unplaced) 0.655 17.297 u_matmul_axi_slave/sys_clk
|
|
FDSE r u_matmul_axi_slave/crc_reg_reg[20]/C
|
|
clock pessimism -0.468 16.830
|
|
clock uncertainty -0.071 16.759
|
|
FDSE (Setup_fdse_C_D) 0.029 16.788 u_matmul_axi_slave/crc_reg_reg[20]
|
|
-------------------------------------------------------------------
|
|
required time 16.788
|
|
arrival time -13.948
|
|
-------------------------------------------------------------------
|
|
slack 2.840
|
|
|
|
Slack (MET) : 2.840ns (required time - arrival time)
|
|
Source: u_matmul_axi_slave/mult_inst[0].u_mult/p_reg[1]/C
|
|
(rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Destination: u_matmul_axi_slave/crc_reg_reg[7]/D
|
|
(rising edge-triggered cell FDSE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Path Group: sys_clk
|
|
Path Type: Setup (Max at Slow Process Corner)
|
|
Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns)
|
|
Data Path Delay: 16.973ns (logic 4.418ns (26.030%) route 12.555ns (73.970%))
|
|
Logic Levels: 18 (CARRY4=3 LUT2=2 LUT4=2 LUT5=4 LUT6=7)
|
|
Clock Path Skew: -0.145ns (DCD - SCD + CPR)
|
|
Destination Clock Delay (DCD): -2.703ns = ( 17.297 - 20.000 )
|
|
Source Clock Delay (SCD): -3.025ns
|
|
Clock Pessimism Removal (CPR): -0.468ns
|
|
Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Discrete Jitter (DJ): 0.122ns
|
|
Phase Error (PE): 0.000ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock sys_clk rise edge) 0.000 0.000 r
|
|
K21 0.000 0.000 r clk (IN)
|
|
net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1
|
|
K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I
|
|
K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O
|
|
net (fo=1, unplaced) 0.584 2.047 pll_clk.u_clk_pll/inst/clk_in1_clk_pll
|
|
r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1
|
|
PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1)
|
|
-6.768 -4.721 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1
|
|
net (fo=1, unplaced) 0.800 -3.921 pll_clk.u_clk_pll/inst/sys_clk_clk_pll
|
|
r pll_clk.u_clk_pll/inst/clkout2_buf/I
|
|
BUFG (Prop_bufg_I_O) 0.096 -3.825 r pll_clk.u_clk_pll/inst/clkout2_buf/O
|
|
net (fo=10994, unplaced) 0.800 -3.025 u_matmul_axi_slave/mult_inst[0].u_mult/sys_clk
|
|
FDRE r u_matmul_axi_slave/mult_inst[0].u_mult/p_reg[1]/C
|
|
------------------------------------------------------------------- -------------------
|
|
FDRE (Prop_fdre_C_Q) 0.456 -2.569 r u_matmul_axi_slave/mult_inst[0].u_mult/p_reg[1]/Q
|
|
net (fo=2, unplaced) 0.481 -2.088 u_matmul_axi_slave/mult_inst[0].u_mult/mult_p[0]_0[1]
|
|
r u_matmul_axi_slave/mult_inst[0].u_mult/b1_c_reg_r1_0_15_0_5_i_20/I0
|
|
LUT2 (Prop_lut2_I0_O) 0.295 -1.793 r u_matmul_axi_slave/mult_inst[0].u_mult/b1_c_reg_r1_0_15_0_5_i_20/O
|
|
net (fo=1, unplaced) 0.000 -1.793 u_matmul_axi_slave/mult_inst[0].u_mult/b1_c_reg_r1_0_15_0_5_i_20_n_0
|
|
r u_matmul_axi_slave/mult_inst[0].u_mult/b1_c_reg_r1_0_15_0_5_i_8/S[1]
|
|
CARRY4 (Prop_carry4_S[1]_CO[3])
|
|
0.550 -1.243 r u_matmul_axi_slave/mult_inst[0].u_mult/b1_c_reg_r1_0_15_0_5_i_8/CO[3]
|
|
net (fo=1, unplaced) 0.009 -1.234 u_matmul_axi_slave/mult_inst[0].u_mult/b1_c_reg_r1_0_15_0_5_i_8_n_0
|
|
r u_matmul_axi_slave/mult_inst[0].u_mult/b1_c_reg_r1_0_15_0_5_i_13/CI
|
|
CARRY4 (Prop_carry4_CI_O[1])
|
|
0.348 -0.886 r u_matmul_axi_slave/mult_inst[0].u_mult/b1_c_reg_r1_0_15_0_5_i_13/O[1]
|
|
net (fo=2, unplaced) 0.622 -0.264 u_matmul_axi_slave/calc_c_result02_out[5]
|
|
r u_matmul_axi_slave/b1_c_reg_r1_0_15_0_5_i_16/I0
|
|
LUT2 (Prop_lut2_I0_O) 0.306 0.042 r u_matmul_axi_slave/b1_c_reg_r1_0_15_0_5_i_16/O
|
|
net (fo=1, unplaced) 0.000 0.042 u_matmul_axi_slave/b1_c_reg_r1_0_15_0_5_i_16_n_0
|
|
r u_matmul_axi_slave/b1_c_reg_r1_0_15_0_5_i_3/S[1]
|
|
CARRY4 (Prop_carry4_S[1]_O[3])
|
|
0.640 0.682 r u_matmul_axi_slave/b1_c_reg_r1_0_15_0_5_i_3/O[3]
|
|
net (fo=15, unplaced) 0.671 1.353 u_matmul_axi_slave/b1_c_reg_r1_0_15_0_5_i_3_n_4
|
|
r u_matmul_axi_slave/crc_reg[12]_i_91/I2
|
|
LUT6 (Prop_lut6_I2_O) 0.307 1.660 r u_matmul_axi_slave/crc_reg[12]_i_91/O
|
|
net (fo=3, unplaced) 0.920 2.580 u_matmul_axi_slave/crc_reg[12]_i_91_n_0
|
|
r u_matmul_axi_slave/crc_reg[12]_i_72/I3
|
|
LUT6 (Prop_lut6_I3_O) 0.124 2.704 r u_matmul_axi_slave/crc_reg[12]_i_72/O
|
|
net (fo=7, unplaced) 0.484 3.188 u_matmul_axi_slave/crc_reg[12]_i_72_n_0
|
|
r u_matmul_axi_slave/crc_reg[12]_i_64/I1
|
|
LUT6 (Prop_lut6_I1_O) 0.124 3.312 r u_matmul_axi_slave/crc_reg[12]_i_64/O
|
|
net (fo=11, unplaced) 0.948 4.260 u_matmul_axi_slave/crc32_word_next_return4[3]
|
|
r u_matmul_axi_slave/crc_reg[12]_i_52/I1
|
|
LUT6 (Prop_lut6_I1_O) 0.124 4.384 r u_matmul_axi_slave/crc_reg[12]_i_52/O
|
|
net (fo=11, unplaced) 1.157 5.541 u_matmul_axi_slave/crc32_word_next_return1[1]
|
|
r u_matmul_axi_slave/crc_reg[12]_i_39/I4
|
|
LUT6 (Prop_lut6_I4_O) 0.124 5.665 r u_matmul_axi_slave/crc_reg[12]_i_39/O
|
|
net (fo=10, unplaced) 0.945 6.610 u_matmul_axi_slave/crc32_word_next0_return10[5]
|
|
r u_matmul_axi_slave/crc_reg[12]_i_22/I1
|
|
LUT5 (Prop_lut5_I1_O) 0.124 6.734 r u_matmul_axi_slave/crc_reg[12]_i_22/O
|
|
net (fo=14, unplaced) 0.953 7.687 u_matmul_axi_slave/crc32_word_next0_return7[7]
|
|
r u_matmul_axi_slave/crc_reg[20]_i_16/I2
|
|
LUT6 (Prop_lut6_I2_O) 0.124 7.811 r u_matmul_axi_slave/crc_reg[20]_i_16/O
|
|
net (fo=11, unplaced) 0.948 8.759 u_matmul_axi_slave/crc32_word_next0_return4[5]
|
|
r u_matmul_axi_slave/crc_reg[31]_i_18/I1
|
|
LUT5 (Prop_lut5_I1_O) 0.124 8.883 r u_matmul_axi_slave/crc_reg[31]_i_18/O
|
|
net (fo=16, unplaced) 0.956 9.839 u_matmul_axi_slave/crc32_word_next0_return1[7]
|
|
r u_matmul_axi_slave/crc_reg[20]_i_14/I1
|
|
LUT4 (Prop_lut4_I1_O) 0.124 9.963 r u_matmul_axi_slave/crc_reg[20]_i_14/O
|
|
net (fo=1, unplaced) 0.902 10.865 u_matmul_axi_slave/crc32_word_next0_return0[21]
|
|
r u_matmul_axi_slave/crc_reg[20]_i_6/I0
|
|
LUT6 (Prop_lut6_I0_O) 0.124 10.989 r u_matmul_axi_slave/crc_reg[20]_i_6/O
|
|
net (fo=2, unplaced) 1.122 12.111 u_matmul_axi_slave/p_0_in0_in[4]
|
|
r u_matmul_axi_slave/crc_reg[30]_i_9/I0
|
|
LUT5 (Prop_lut5_I0_O) 0.152 12.263 r u_matmul_axi_slave/crc_reg[30]_i_9/O
|
|
net (fo=7, unplaced) 0.937 13.200 u_matmul_axi_slave/crc32_word_next1_return4[4]
|
|
r u_matmul_axi_slave/crc_reg[29]_i_2/I2
|
|
LUT5 (Prop_lut5_I2_O) 0.124 13.324 r u_matmul_axi_slave/crc_reg[29]_i_2/O
|
|
net (fo=14, unplaced) 0.500 13.824 u_matmul_axi_slave/crc32_word_next1_return1[5]
|
|
r u_matmul_axi_slave/crc_reg[7]_i_1/I3
|
|
LUT4 (Prop_lut4_I3_O) 0.124 13.948 r u_matmul_axi_slave/crc_reg[7]_i_1/O
|
|
net (fo=1, unplaced) 0.000 13.948 u_matmul_axi_slave/crc32_word_next1_return[7]
|
|
FDSE r u_matmul_axi_slave/crc_reg_reg[7]/D
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock sys_clk rise edge) 20.000 20.000 r
|
|
K21 0.000 20.000 r clk (IN)
|
|
net (fo=0) 0.000 20.000 pll_clk.u_clk_pll/inst/clk_in1
|
|
K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I
|
|
K21 IBUF (Prop_ibuf_I_O) 1.393 21.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O
|
|
net (fo=1, unplaced) 0.439 21.832 pll_clk.u_clk_pll/inst/clk_in1_clk_pll
|
|
r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1
|
|
PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1)
|
|
-6.040 15.792 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1
|
|
net (fo=1, unplaced) 0.760 16.552 pll_clk.u_clk_pll/inst/sys_clk_clk_pll
|
|
r pll_clk.u_clk_pll/inst/clkout2_buf/I
|
|
BUFG (Prop_bufg_I_O) 0.091 16.643 r pll_clk.u_clk_pll/inst/clkout2_buf/O
|
|
net (fo=10994, unplaced) 0.655 17.297 u_matmul_axi_slave/sys_clk
|
|
FDSE r u_matmul_axi_slave/crc_reg_reg[7]/C
|
|
clock pessimism -0.468 16.830
|
|
clock uncertainty -0.071 16.759
|
|
FDSE (Setup_fdse_C_D) 0.029 16.788 u_matmul_axi_slave/crc_reg_reg[7]
|
|
-------------------------------------------------------------------
|
|
required time 16.788
|
|
arrival time -13.948
|
|
-------------------------------------------------------------------
|
|
slack 2.840
|
|
|
|
Slack (MET) : 2.870ns (required time - arrival time)
|
|
Source: u_matmul_axi_slave/mult_inst[0].u_mult/p_reg[1]/C
|
|
(rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Destination: u_matmul_axi_slave/crc_reg_reg[29]/D
|
|
(rising edge-triggered cell FDSE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Path Group: sys_clk
|
|
Path Type: Setup (Max at Slow Process Corner)
|
|
Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns)
|
|
Data Path Delay: 16.943ns (logic 4.418ns (26.076%) route 12.525ns (73.924%))
|
|
Logic Levels: 18 (CARRY4=3 LUT2=2 LUT4=1 LUT5=5 LUT6=7)
|
|
Clock Path Skew: -0.145ns (DCD - SCD + CPR)
|
|
Destination Clock Delay (DCD): -2.703ns = ( 17.297 - 20.000 )
|
|
Source Clock Delay (SCD): -3.025ns
|
|
Clock Pessimism Removal (CPR): -0.468ns
|
|
Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Discrete Jitter (DJ): 0.122ns
|
|
Phase Error (PE): 0.000ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock sys_clk rise edge) 0.000 0.000 r
|
|
K21 0.000 0.000 r clk (IN)
|
|
net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1
|
|
K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I
|
|
K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O
|
|
net (fo=1, unplaced) 0.584 2.047 pll_clk.u_clk_pll/inst/clk_in1_clk_pll
|
|
r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1
|
|
PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1)
|
|
-6.768 -4.721 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1
|
|
net (fo=1, unplaced) 0.800 -3.921 pll_clk.u_clk_pll/inst/sys_clk_clk_pll
|
|
r pll_clk.u_clk_pll/inst/clkout2_buf/I
|
|
BUFG (Prop_bufg_I_O) 0.096 -3.825 r pll_clk.u_clk_pll/inst/clkout2_buf/O
|
|
net (fo=10994, unplaced) 0.800 -3.025 u_matmul_axi_slave/mult_inst[0].u_mult/sys_clk
|
|
FDRE r u_matmul_axi_slave/mult_inst[0].u_mult/p_reg[1]/C
|
|
------------------------------------------------------------------- -------------------
|
|
FDRE (Prop_fdre_C_Q) 0.456 -2.569 r u_matmul_axi_slave/mult_inst[0].u_mult/p_reg[1]/Q
|
|
net (fo=2, unplaced) 0.481 -2.088 u_matmul_axi_slave/mult_inst[0].u_mult/mult_p[0]_0[1]
|
|
r u_matmul_axi_slave/mult_inst[0].u_mult/b1_c_reg_r1_0_15_0_5_i_20/I0
|
|
LUT2 (Prop_lut2_I0_O) 0.295 -1.793 r u_matmul_axi_slave/mult_inst[0].u_mult/b1_c_reg_r1_0_15_0_5_i_20/O
|
|
net (fo=1, unplaced) 0.000 -1.793 u_matmul_axi_slave/mult_inst[0].u_mult/b1_c_reg_r1_0_15_0_5_i_20_n_0
|
|
r u_matmul_axi_slave/mult_inst[0].u_mult/b1_c_reg_r1_0_15_0_5_i_8/S[1]
|
|
CARRY4 (Prop_carry4_S[1]_CO[3])
|
|
0.550 -1.243 r u_matmul_axi_slave/mult_inst[0].u_mult/b1_c_reg_r1_0_15_0_5_i_8/CO[3]
|
|
net (fo=1, unplaced) 0.009 -1.234 u_matmul_axi_slave/mult_inst[0].u_mult/b1_c_reg_r1_0_15_0_5_i_8_n_0
|
|
r u_matmul_axi_slave/mult_inst[0].u_mult/b1_c_reg_r1_0_15_0_5_i_13/CI
|
|
CARRY4 (Prop_carry4_CI_O[1])
|
|
0.348 -0.886 r u_matmul_axi_slave/mult_inst[0].u_mult/b1_c_reg_r1_0_15_0_5_i_13/O[1]
|
|
net (fo=2, unplaced) 0.622 -0.264 u_matmul_axi_slave/calc_c_result02_out[5]
|
|
r u_matmul_axi_slave/b1_c_reg_r1_0_15_0_5_i_16/I0
|
|
LUT2 (Prop_lut2_I0_O) 0.306 0.042 r u_matmul_axi_slave/b1_c_reg_r1_0_15_0_5_i_16/O
|
|
net (fo=1, unplaced) 0.000 0.042 u_matmul_axi_slave/b1_c_reg_r1_0_15_0_5_i_16_n_0
|
|
r u_matmul_axi_slave/b1_c_reg_r1_0_15_0_5_i_3/S[1]
|
|
CARRY4 (Prop_carry4_S[1]_O[3])
|
|
0.640 0.682 r u_matmul_axi_slave/b1_c_reg_r1_0_15_0_5_i_3/O[3]
|
|
net (fo=15, unplaced) 0.671 1.353 u_matmul_axi_slave/b1_c_reg_r1_0_15_0_5_i_3_n_4
|
|
r u_matmul_axi_slave/crc_reg[12]_i_91/I2
|
|
LUT6 (Prop_lut6_I2_O) 0.307 1.660 r u_matmul_axi_slave/crc_reg[12]_i_91/O
|
|
net (fo=3, unplaced) 0.920 2.580 u_matmul_axi_slave/crc_reg[12]_i_91_n_0
|
|
r u_matmul_axi_slave/crc_reg[12]_i_72/I3
|
|
LUT6 (Prop_lut6_I3_O) 0.124 2.704 r u_matmul_axi_slave/crc_reg[12]_i_72/O
|
|
net (fo=7, unplaced) 0.484 3.188 u_matmul_axi_slave/crc_reg[12]_i_72_n_0
|
|
r u_matmul_axi_slave/crc_reg[12]_i_64/I1
|
|
LUT6 (Prop_lut6_I1_O) 0.124 3.312 r u_matmul_axi_slave/crc_reg[12]_i_64/O
|
|
net (fo=11, unplaced) 0.948 4.260 u_matmul_axi_slave/crc32_word_next_return4[3]
|
|
r u_matmul_axi_slave/crc_reg[12]_i_52/I1
|
|
LUT6 (Prop_lut6_I1_O) 0.124 4.384 r u_matmul_axi_slave/crc_reg[12]_i_52/O
|
|
net (fo=11, unplaced) 1.157 5.541 u_matmul_axi_slave/crc32_word_next_return1[1]
|
|
r u_matmul_axi_slave/crc_reg[12]_i_39/I4
|
|
LUT6 (Prop_lut6_I4_O) 0.124 5.665 r u_matmul_axi_slave/crc_reg[12]_i_39/O
|
|
net (fo=10, unplaced) 0.945 6.610 u_matmul_axi_slave/crc32_word_next0_return10[5]
|
|
r u_matmul_axi_slave/crc_reg[12]_i_22/I1
|
|
LUT5 (Prop_lut5_I1_O) 0.124 6.734 r u_matmul_axi_slave/crc_reg[12]_i_22/O
|
|
net (fo=14, unplaced) 0.953 7.687 u_matmul_axi_slave/crc32_word_next0_return7[7]
|
|
r u_matmul_axi_slave/crc_reg[20]_i_16/I2
|
|
LUT6 (Prop_lut6_I2_O) 0.124 7.811 r u_matmul_axi_slave/crc_reg[20]_i_16/O
|
|
net (fo=11, unplaced) 0.948 8.759 u_matmul_axi_slave/crc32_word_next0_return4[5]
|
|
r u_matmul_axi_slave/crc_reg[31]_i_18/I1
|
|
LUT5 (Prop_lut5_I1_O) 0.124 8.883 r u_matmul_axi_slave/crc_reg[31]_i_18/O
|
|
net (fo=16, unplaced) 0.956 9.839 u_matmul_axi_slave/crc32_word_next0_return1[7]
|
|
r u_matmul_axi_slave/crc_reg[20]_i_14/I1
|
|
LUT4 (Prop_lut4_I1_O) 0.124 9.963 r u_matmul_axi_slave/crc_reg[20]_i_14/O
|
|
net (fo=1, unplaced) 0.902 10.865 u_matmul_axi_slave/crc32_word_next0_return0[21]
|
|
r u_matmul_axi_slave/crc_reg[20]_i_6/I0
|
|
LUT6 (Prop_lut6_I0_O) 0.124 10.989 r u_matmul_axi_slave/crc_reg[20]_i_6/O
|
|
net (fo=2, unplaced) 1.122 12.111 u_matmul_axi_slave/p_0_in0_in[4]
|
|
r u_matmul_axi_slave/crc_reg[30]_i_9/I0
|
|
LUT5 (Prop_lut5_I0_O) 0.152 12.263 r u_matmul_axi_slave/crc_reg[30]_i_9/O
|
|
net (fo=7, unplaced) 0.937 13.200 u_matmul_axi_slave/crc32_word_next1_return4[4]
|
|
r u_matmul_axi_slave/crc_reg[29]_i_2/I2
|
|
LUT5 (Prop_lut5_I2_O) 0.124 13.324 r u_matmul_axi_slave/crc_reg[29]_i_2/O
|
|
net (fo=14, unplaced) 0.470 13.794 u_matmul_axi_slave/crc32_word_next1_return1[5]
|
|
r u_matmul_axi_slave/crc_reg[29]_i_1/I3
|
|
LUT5 (Prop_lut5_I3_O) 0.124 13.918 r u_matmul_axi_slave/crc_reg[29]_i_1/O
|
|
net (fo=1, unplaced) 0.000 13.918 u_matmul_axi_slave/crc32_word_next1_return0[27]
|
|
FDSE r u_matmul_axi_slave/crc_reg_reg[29]/D
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock sys_clk rise edge) 20.000 20.000 r
|
|
K21 0.000 20.000 r clk (IN)
|
|
net (fo=0) 0.000 20.000 pll_clk.u_clk_pll/inst/clk_in1
|
|
K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I
|
|
K21 IBUF (Prop_ibuf_I_O) 1.393 21.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O
|
|
net (fo=1, unplaced) 0.439 21.832 pll_clk.u_clk_pll/inst/clk_in1_clk_pll
|
|
r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1
|
|
PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1)
|
|
-6.040 15.792 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1
|
|
net (fo=1, unplaced) 0.760 16.552 pll_clk.u_clk_pll/inst/sys_clk_clk_pll
|
|
r pll_clk.u_clk_pll/inst/clkout2_buf/I
|
|
BUFG (Prop_bufg_I_O) 0.091 16.643 r pll_clk.u_clk_pll/inst/clkout2_buf/O
|
|
net (fo=10994, unplaced) 0.655 17.297 u_matmul_axi_slave/sys_clk
|
|
FDSE r u_matmul_axi_slave/crc_reg_reg[29]/C
|
|
clock pessimism -0.468 16.830
|
|
clock uncertainty -0.071 16.759
|
|
FDSE (Setup_fdse_C_D) 0.029 16.788 u_matmul_axi_slave/crc_reg_reg[29]
|
|
-------------------------------------------------------------------
|
|
required time 16.788
|
|
arrival time -13.918
|
|
-------------------------------------------------------------------
|
|
slack 2.870
|
|
|
|
Slack (MET) : 2.870ns (required time - arrival time)
|
|
Source: u_matmul_axi_slave/mult_inst[0].u_mult/p_reg[1]/C
|
|
(rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Destination: u_matmul_axi_slave/crc_reg_reg[3]/D
|
|
(rising edge-triggered cell FDSE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Path Group: sys_clk
|
|
Path Type: Setup (Max at Slow Process Corner)
|
|
Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns)
|
|
Data Path Delay: 16.943ns (logic 4.418ns (26.076%) route 12.525ns (73.924%))
|
|
Logic Levels: 18 (CARRY4=3 LUT2=2 LUT4=2 LUT5=4 LUT6=7)
|
|
Clock Path Skew: -0.145ns (DCD - SCD + CPR)
|
|
Destination Clock Delay (DCD): -2.703ns = ( 17.297 - 20.000 )
|
|
Source Clock Delay (SCD): -3.025ns
|
|
Clock Pessimism Removal (CPR): -0.468ns
|
|
Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Discrete Jitter (DJ): 0.122ns
|
|
Phase Error (PE): 0.000ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock sys_clk rise edge) 0.000 0.000 r
|
|
K21 0.000 0.000 r clk (IN)
|
|
net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1
|
|
K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I
|
|
K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O
|
|
net (fo=1, unplaced) 0.584 2.047 pll_clk.u_clk_pll/inst/clk_in1_clk_pll
|
|
r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1
|
|
PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1)
|
|
-6.768 -4.721 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1
|
|
net (fo=1, unplaced) 0.800 -3.921 pll_clk.u_clk_pll/inst/sys_clk_clk_pll
|
|
r pll_clk.u_clk_pll/inst/clkout2_buf/I
|
|
BUFG (Prop_bufg_I_O) 0.096 -3.825 r pll_clk.u_clk_pll/inst/clkout2_buf/O
|
|
net (fo=10994, unplaced) 0.800 -3.025 u_matmul_axi_slave/mult_inst[0].u_mult/sys_clk
|
|
FDRE r u_matmul_axi_slave/mult_inst[0].u_mult/p_reg[1]/C
|
|
------------------------------------------------------------------- -------------------
|
|
FDRE (Prop_fdre_C_Q) 0.456 -2.569 r u_matmul_axi_slave/mult_inst[0].u_mult/p_reg[1]/Q
|
|
net (fo=2, unplaced) 0.481 -2.088 u_matmul_axi_slave/mult_inst[0].u_mult/mult_p[0]_0[1]
|
|
r u_matmul_axi_slave/mult_inst[0].u_mult/b1_c_reg_r1_0_15_0_5_i_20/I0
|
|
LUT2 (Prop_lut2_I0_O) 0.295 -1.793 r u_matmul_axi_slave/mult_inst[0].u_mult/b1_c_reg_r1_0_15_0_5_i_20/O
|
|
net (fo=1, unplaced) 0.000 -1.793 u_matmul_axi_slave/mult_inst[0].u_mult/b1_c_reg_r1_0_15_0_5_i_20_n_0
|
|
r u_matmul_axi_slave/mult_inst[0].u_mult/b1_c_reg_r1_0_15_0_5_i_8/S[1]
|
|
CARRY4 (Prop_carry4_S[1]_CO[3])
|
|
0.550 -1.243 r u_matmul_axi_slave/mult_inst[0].u_mult/b1_c_reg_r1_0_15_0_5_i_8/CO[3]
|
|
net (fo=1, unplaced) 0.009 -1.234 u_matmul_axi_slave/mult_inst[0].u_mult/b1_c_reg_r1_0_15_0_5_i_8_n_0
|
|
r u_matmul_axi_slave/mult_inst[0].u_mult/b1_c_reg_r1_0_15_0_5_i_13/CI
|
|
CARRY4 (Prop_carry4_CI_O[1])
|
|
0.348 -0.886 r u_matmul_axi_slave/mult_inst[0].u_mult/b1_c_reg_r1_0_15_0_5_i_13/O[1]
|
|
net (fo=2, unplaced) 0.622 -0.264 u_matmul_axi_slave/calc_c_result02_out[5]
|
|
r u_matmul_axi_slave/b1_c_reg_r1_0_15_0_5_i_16/I0
|
|
LUT2 (Prop_lut2_I0_O) 0.306 0.042 r u_matmul_axi_slave/b1_c_reg_r1_0_15_0_5_i_16/O
|
|
net (fo=1, unplaced) 0.000 0.042 u_matmul_axi_slave/b1_c_reg_r1_0_15_0_5_i_16_n_0
|
|
r u_matmul_axi_slave/b1_c_reg_r1_0_15_0_5_i_3/S[1]
|
|
CARRY4 (Prop_carry4_S[1]_O[3])
|
|
0.640 0.682 r u_matmul_axi_slave/b1_c_reg_r1_0_15_0_5_i_3/O[3]
|
|
net (fo=15, unplaced) 0.671 1.353 u_matmul_axi_slave/b1_c_reg_r1_0_15_0_5_i_3_n_4
|
|
r u_matmul_axi_slave/crc_reg[12]_i_91/I2
|
|
LUT6 (Prop_lut6_I2_O) 0.307 1.660 r u_matmul_axi_slave/crc_reg[12]_i_91/O
|
|
net (fo=3, unplaced) 0.920 2.580 u_matmul_axi_slave/crc_reg[12]_i_91_n_0
|
|
r u_matmul_axi_slave/crc_reg[12]_i_72/I3
|
|
LUT6 (Prop_lut6_I3_O) 0.124 2.704 r u_matmul_axi_slave/crc_reg[12]_i_72/O
|
|
net (fo=7, unplaced) 0.484 3.188 u_matmul_axi_slave/crc_reg[12]_i_72_n_0
|
|
r u_matmul_axi_slave/crc_reg[12]_i_64/I1
|
|
LUT6 (Prop_lut6_I1_O) 0.124 3.312 r u_matmul_axi_slave/crc_reg[12]_i_64/O
|
|
net (fo=11, unplaced) 0.948 4.260 u_matmul_axi_slave/crc32_word_next_return4[3]
|
|
r u_matmul_axi_slave/crc_reg[12]_i_52/I1
|
|
LUT6 (Prop_lut6_I1_O) 0.124 4.384 r u_matmul_axi_slave/crc_reg[12]_i_52/O
|
|
net (fo=11, unplaced) 1.157 5.541 u_matmul_axi_slave/crc32_word_next_return1[1]
|
|
r u_matmul_axi_slave/crc_reg[12]_i_39/I4
|
|
LUT6 (Prop_lut6_I4_O) 0.124 5.665 r u_matmul_axi_slave/crc_reg[12]_i_39/O
|
|
net (fo=10, unplaced) 0.945 6.610 u_matmul_axi_slave/crc32_word_next0_return10[5]
|
|
r u_matmul_axi_slave/crc_reg[12]_i_22/I1
|
|
LUT5 (Prop_lut5_I1_O) 0.124 6.734 r u_matmul_axi_slave/crc_reg[12]_i_22/O
|
|
net (fo=14, unplaced) 0.953 7.687 u_matmul_axi_slave/crc32_word_next0_return7[7]
|
|
r u_matmul_axi_slave/crc_reg[20]_i_16/I2
|
|
LUT6 (Prop_lut6_I2_O) 0.124 7.811 r u_matmul_axi_slave/crc_reg[20]_i_16/O
|
|
net (fo=11, unplaced) 0.948 8.759 u_matmul_axi_slave/crc32_word_next0_return4[5]
|
|
r u_matmul_axi_slave/crc_reg[31]_i_18/I1
|
|
LUT5 (Prop_lut5_I1_O) 0.124 8.883 r u_matmul_axi_slave/crc_reg[31]_i_18/O
|
|
net (fo=16, unplaced) 0.956 9.839 u_matmul_axi_slave/crc32_word_next0_return1[7]
|
|
r u_matmul_axi_slave/crc_reg[20]_i_14/I1
|
|
LUT4 (Prop_lut4_I1_O) 0.124 9.963 r u_matmul_axi_slave/crc_reg[20]_i_14/O
|
|
net (fo=1, unplaced) 0.902 10.865 u_matmul_axi_slave/crc32_word_next0_return0[21]
|
|
r u_matmul_axi_slave/crc_reg[20]_i_6/I0
|
|
LUT6 (Prop_lut6_I0_O) 0.124 10.989 r u_matmul_axi_slave/crc_reg[20]_i_6/O
|
|
net (fo=2, unplaced) 1.122 12.111 u_matmul_axi_slave/p_0_in0_in[4]
|
|
r u_matmul_axi_slave/crc_reg[30]_i_9/I0
|
|
LUT5 (Prop_lut5_I0_O) 0.152 12.263 r u_matmul_axi_slave/crc_reg[30]_i_9/O
|
|
net (fo=7, unplaced) 0.937 13.200 u_matmul_axi_slave/crc32_word_next1_return4[4]
|
|
r u_matmul_axi_slave/crc_reg[29]_i_2/I2
|
|
LUT5 (Prop_lut5_I2_O) 0.124 13.324 r u_matmul_axi_slave/crc_reg[29]_i_2/O
|
|
net (fo=14, unplaced) 0.470 13.794 u_matmul_axi_slave/crc32_word_next1_return1[5]
|
|
r u_matmul_axi_slave/crc_reg[3]_i_1/I2
|
|
LUT4 (Prop_lut4_I2_O) 0.124 13.918 r u_matmul_axi_slave/crc_reg[3]_i_1/O
|
|
net (fo=1, unplaced) 0.000 13.918 u_matmul_axi_slave/crc32_word_next1_return[3]
|
|
FDSE r u_matmul_axi_slave/crc_reg_reg[3]/D
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock sys_clk rise edge) 20.000 20.000 r
|
|
K21 0.000 20.000 r clk (IN)
|
|
net (fo=0) 0.000 20.000 pll_clk.u_clk_pll/inst/clk_in1
|
|
K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I
|
|
K21 IBUF (Prop_ibuf_I_O) 1.393 21.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O
|
|
net (fo=1, unplaced) 0.439 21.832 pll_clk.u_clk_pll/inst/clk_in1_clk_pll
|
|
r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1
|
|
PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1)
|
|
-6.040 15.792 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1
|
|
net (fo=1, unplaced) 0.760 16.552 pll_clk.u_clk_pll/inst/sys_clk_clk_pll
|
|
r pll_clk.u_clk_pll/inst/clkout2_buf/I
|
|
BUFG (Prop_bufg_I_O) 0.091 16.643 r pll_clk.u_clk_pll/inst/clkout2_buf/O
|
|
net (fo=10994, unplaced) 0.655 17.297 u_matmul_axi_slave/sys_clk
|
|
FDSE r u_matmul_axi_slave/crc_reg_reg[3]/C
|
|
clock pessimism -0.468 16.830
|
|
clock uncertainty -0.071 16.759
|
|
FDSE (Setup_fdse_C_D) 0.029 16.788 u_matmul_axi_slave/crc_reg_reg[3]
|
|
-------------------------------------------------------------------
|
|
required time 16.788
|
|
arrival time -13.918
|
|
-------------------------------------------------------------------
|
|
slack 2.870
|
|
|
|
Slack (MET) : 2.870ns (required time - arrival time)
|
|
Source: u_matmul_axi_slave/mult_inst[0].u_mult/p_reg[1]/C
|
|
(rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Destination: u_matmul_axi_slave/crc_reg_reg[6]/D
|
|
(rising edge-triggered cell FDSE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Path Group: sys_clk
|
|
Path Type: Setup (Max at Slow Process Corner)
|
|
Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns)
|
|
Data Path Delay: 16.943ns (logic 4.418ns (26.076%) route 12.525ns (73.924%))
|
|
Logic Levels: 18 (CARRY4=3 LUT2=2 LUT4=1 LUT5=4 LUT6=8)
|
|
Clock Path Skew: -0.145ns (DCD - SCD + CPR)
|
|
Destination Clock Delay (DCD): -2.703ns = ( 17.297 - 20.000 )
|
|
Source Clock Delay (SCD): -3.025ns
|
|
Clock Pessimism Removal (CPR): -0.468ns
|
|
Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Discrete Jitter (DJ): 0.122ns
|
|
Phase Error (PE): 0.000ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock sys_clk rise edge) 0.000 0.000 r
|
|
K21 0.000 0.000 r clk (IN)
|
|
net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1
|
|
K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I
|
|
K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O
|
|
net (fo=1, unplaced) 0.584 2.047 pll_clk.u_clk_pll/inst/clk_in1_clk_pll
|
|
r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1
|
|
PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1)
|
|
-6.768 -4.721 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1
|
|
net (fo=1, unplaced) 0.800 -3.921 pll_clk.u_clk_pll/inst/sys_clk_clk_pll
|
|
r pll_clk.u_clk_pll/inst/clkout2_buf/I
|
|
BUFG (Prop_bufg_I_O) 0.096 -3.825 r pll_clk.u_clk_pll/inst/clkout2_buf/O
|
|
net (fo=10994, unplaced) 0.800 -3.025 u_matmul_axi_slave/mult_inst[0].u_mult/sys_clk
|
|
FDRE r u_matmul_axi_slave/mult_inst[0].u_mult/p_reg[1]/C
|
|
------------------------------------------------------------------- -------------------
|
|
FDRE (Prop_fdre_C_Q) 0.456 -2.569 r u_matmul_axi_slave/mult_inst[0].u_mult/p_reg[1]/Q
|
|
net (fo=2, unplaced) 0.481 -2.088 u_matmul_axi_slave/mult_inst[0].u_mult/mult_p[0]_0[1]
|
|
r u_matmul_axi_slave/mult_inst[0].u_mult/b1_c_reg_r1_0_15_0_5_i_20/I0
|
|
LUT2 (Prop_lut2_I0_O) 0.295 -1.793 r u_matmul_axi_slave/mult_inst[0].u_mult/b1_c_reg_r1_0_15_0_5_i_20/O
|
|
net (fo=1, unplaced) 0.000 -1.793 u_matmul_axi_slave/mult_inst[0].u_mult/b1_c_reg_r1_0_15_0_5_i_20_n_0
|
|
r u_matmul_axi_slave/mult_inst[0].u_mult/b1_c_reg_r1_0_15_0_5_i_8/S[1]
|
|
CARRY4 (Prop_carry4_S[1]_CO[3])
|
|
0.550 -1.243 r u_matmul_axi_slave/mult_inst[0].u_mult/b1_c_reg_r1_0_15_0_5_i_8/CO[3]
|
|
net (fo=1, unplaced) 0.009 -1.234 u_matmul_axi_slave/mult_inst[0].u_mult/b1_c_reg_r1_0_15_0_5_i_8_n_0
|
|
r u_matmul_axi_slave/mult_inst[0].u_mult/b1_c_reg_r1_0_15_0_5_i_13/CI
|
|
CARRY4 (Prop_carry4_CI_O[1])
|
|
0.348 -0.886 r u_matmul_axi_slave/mult_inst[0].u_mult/b1_c_reg_r1_0_15_0_5_i_13/O[1]
|
|
net (fo=2, unplaced) 0.622 -0.264 u_matmul_axi_slave/calc_c_result02_out[5]
|
|
r u_matmul_axi_slave/b1_c_reg_r1_0_15_0_5_i_16/I0
|
|
LUT2 (Prop_lut2_I0_O) 0.306 0.042 r u_matmul_axi_slave/b1_c_reg_r1_0_15_0_5_i_16/O
|
|
net (fo=1, unplaced) 0.000 0.042 u_matmul_axi_slave/b1_c_reg_r1_0_15_0_5_i_16_n_0
|
|
r u_matmul_axi_slave/b1_c_reg_r1_0_15_0_5_i_3/S[1]
|
|
CARRY4 (Prop_carry4_S[1]_O[3])
|
|
0.640 0.682 r u_matmul_axi_slave/b1_c_reg_r1_0_15_0_5_i_3/O[3]
|
|
net (fo=15, unplaced) 0.671 1.353 u_matmul_axi_slave/b1_c_reg_r1_0_15_0_5_i_3_n_4
|
|
r u_matmul_axi_slave/crc_reg[12]_i_91/I2
|
|
LUT6 (Prop_lut6_I2_O) 0.307 1.660 r u_matmul_axi_slave/crc_reg[12]_i_91/O
|
|
net (fo=3, unplaced) 0.920 2.580 u_matmul_axi_slave/crc_reg[12]_i_91_n_0
|
|
r u_matmul_axi_slave/crc_reg[12]_i_72/I3
|
|
LUT6 (Prop_lut6_I3_O) 0.124 2.704 r u_matmul_axi_slave/crc_reg[12]_i_72/O
|
|
net (fo=7, unplaced) 0.484 3.188 u_matmul_axi_slave/crc_reg[12]_i_72_n_0
|
|
r u_matmul_axi_slave/crc_reg[12]_i_64/I1
|
|
LUT6 (Prop_lut6_I1_O) 0.124 3.312 r u_matmul_axi_slave/crc_reg[12]_i_64/O
|
|
net (fo=11, unplaced) 0.948 4.260 u_matmul_axi_slave/crc32_word_next_return4[3]
|
|
r u_matmul_axi_slave/crc_reg[12]_i_52/I1
|
|
LUT6 (Prop_lut6_I1_O) 0.124 4.384 r u_matmul_axi_slave/crc_reg[12]_i_52/O
|
|
net (fo=11, unplaced) 1.157 5.541 u_matmul_axi_slave/crc32_word_next_return1[1]
|
|
r u_matmul_axi_slave/crc_reg[12]_i_39/I4
|
|
LUT6 (Prop_lut6_I4_O) 0.124 5.665 r u_matmul_axi_slave/crc_reg[12]_i_39/O
|
|
net (fo=10, unplaced) 0.945 6.610 u_matmul_axi_slave/crc32_word_next0_return10[5]
|
|
r u_matmul_axi_slave/crc_reg[12]_i_22/I1
|
|
LUT5 (Prop_lut5_I1_O) 0.124 6.734 r u_matmul_axi_slave/crc_reg[12]_i_22/O
|
|
net (fo=14, unplaced) 0.953 7.687 u_matmul_axi_slave/crc32_word_next0_return7[7]
|
|
r u_matmul_axi_slave/crc_reg[20]_i_16/I2
|
|
LUT6 (Prop_lut6_I2_O) 0.124 7.811 r u_matmul_axi_slave/crc_reg[20]_i_16/O
|
|
net (fo=11, unplaced) 0.948 8.759 u_matmul_axi_slave/crc32_word_next0_return4[5]
|
|
r u_matmul_axi_slave/crc_reg[31]_i_18/I1
|
|
LUT5 (Prop_lut5_I1_O) 0.124 8.883 r u_matmul_axi_slave/crc_reg[31]_i_18/O
|
|
net (fo=16, unplaced) 0.956 9.839 u_matmul_axi_slave/crc32_word_next0_return1[7]
|
|
r u_matmul_axi_slave/crc_reg[20]_i_14/I1
|
|
LUT4 (Prop_lut4_I1_O) 0.124 9.963 r u_matmul_axi_slave/crc_reg[20]_i_14/O
|
|
net (fo=1, unplaced) 0.902 10.865 u_matmul_axi_slave/crc32_word_next0_return0[21]
|
|
r u_matmul_axi_slave/crc_reg[20]_i_6/I0
|
|
LUT6 (Prop_lut6_I0_O) 0.124 10.989 r u_matmul_axi_slave/crc_reg[20]_i_6/O
|
|
net (fo=2, unplaced) 1.122 12.111 u_matmul_axi_slave/p_0_in0_in[4]
|
|
r u_matmul_axi_slave/crc_reg[30]_i_9/I0
|
|
LUT5 (Prop_lut5_I0_O) 0.152 12.263 r u_matmul_axi_slave/crc_reg[30]_i_9/O
|
|
net (fo=7, unplaced) 0.937 13.200 u_matmul_axi_slave/crc32_word_next1_return4[4]
|
|
r u_matmul_axi_slave/crc_reg[29]_i_2/I2
|
|
LUT5 (Prop_lut5_I2_O) 0.124 13.324 r u_matmul_axi_slave/crc_reg[29]_i_2/O
|
|
net (fo=14, unplaced) 0.470 13.794 u_matmul_axi_slave/crc32_word_next1_return1[5]
|
|
r u_matmul_axi_slave/crc_reg[6]_i_1/I4
|
|
LUT6 (Prop_lut6_I4_O) 0.124 13.918 r u_matmul_axi_slave/crc_reg[6]_i_1/O
|
|
net (fo=1, unplaced) 0.000 13.918 u_matmul_axi_slave/crc32_word_next1_return[6]
|
|
FDSE r u_matmul_axi_slave/crc_reg_reg[6]/D
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock sys_clk rise edge) 20.000 20.000 r
|
|
K21 0.000 20.000 r clk (IN)
|
|
net (fo=0) 0.000 20.000 pll_clk.u_clk_pll/inst/clk_in1
|
|
K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I
|
|
K21 IBUF (Prop_ibuf_I_O) 1.393 21.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O
|
|
net (fo=1, unplaced) 0.439 21.832 pll_clk.u_clk_pll/inst/clk_in1_clk_pll
|
|
r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1
|
|
PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1)
|
|
-6.040 15.792 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1
|
|
net (fo=1, unplaced) 0.760 16.552 pll_clk.u_clk_pll/inst/sys_clk_clk_pll
|
|
r pll_clk.u_clk_pll/inst/clkout2_buf/I
|
|
BUFG (Prop_bufg_I_O) 0.091 16.643 r pll_clk.u_clk_pll/inst/clkout2_buf/O
|
|
net (fo=10994, unplaced) 0.655 17.297 u_matmul_axi_slave/sys_clk
|
|
FDSE r u_matmul_axi_slave/crc_reg_reg[6]/C
|
|
clock pessimism -0.468 16.830
|
|
clock uncertainty -0.071 16.759
|
|
FDSE (Setup_fdse_C_D) 0.029 16.788 u_matmul_axi_slave/crc_reg_reg[6]
|
|
-------------------------------------------------------------------
|
|
required time 16.788
|
|
arrival time -13.918
|
|
-------------------------------------------------------------------
|
|
slack 2.870
|
|
|
|
Slack (MET) : 2.966ns (required time - arrival time)
|
|
Source: u_matmul_axi_slave/mult_inst[0].u_mult/p_reg[1]/C
|
|
(rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Destination: u_matmul_axi_slave/crc_reg_reg[4]/D
|
|
(rising edge-triggered cell FDSE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Path Group: sys_clk
|
|
Path Type: Setup (Max at Slow Process Corner)
|
|
Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns)
|
|
Data Path Delay: 16.847ns (logic 4.470ns (26.533%) route 12.377ns (73.467%))
|
|
Logic Levels: 18 (CARRY4=3 LUT2=2 LUT4=1 LUT5=6 LUT6=6)
|
|
Clock Path Skew: -0.145ns (DCD - SCD + CPR)
|
|
Destination Clock Delay (DCD): -2.703ns = ( 17.297 - 20.000 )
|
|
Source Clock Delay (SCD): -3.025ns
|
|
Clock Pessimism Removal (CPR): -0.468ns
|
|
Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Discrete Jitter (DJ): 0.122ns
|
|
Phase Error (PE): 0.000ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock sys_clk rise edge) 0.000 0.000 r
|
|
K21 0.000 0.000 r clk (IN)
|
|
net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1
|
|
K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I
|
|
K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O
|
|
net (fo=1, unplaced) 0.584 2.047 pll_clk.u_clk_pll/inst/clk_in1_clk_pll
|
|
r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1
|
|
PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1)
|
|
-6.768 -4.721 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1
|
|
net (fo=1, unplaced) 0.800 -3.921 pll_clk.u_clk_pll/inst/sys_clk_clk_pll
|
|
r pll_clk.u_clk_pll/inst/clkout2_buf/I
|
|
BUFG (Prop_bufg_I_O) 0.096 -3.825 r pll_clk.u_clk_pll/inst/clkout2_buf/O
|
|
net (fo=10994, unplaced) 0.800 -3.025 u_matmul_axi_slave/mult_inst[0].u_mult/sys_clk
|
|
FDRE r u_matmul_axi_slave/mult_inst[0].u_mult/p_reg[1]/C
|
|
------------------------------------------------------------------- -------------------
|
|
FDRE (Prop_fdre_C_Q) 0.456 -2.569 r u_matmul_axi_slave/mult_inst[0].u_mult/p_reg[1]/Q
|
|
net (fo=2, unplaced) 0.481 -2.088 u_matmul_axi_slave/mult_inst[0].u_mult/mult_p[0]_0[1]
|
|
r u_matmul_axi_slave/mult_inst[0].u_mult/b1_c_reg_r1_0_15_0_5_i_20/I0
|
|
LUT2 (Prop_lut2_I0_O) 0.295 -1.793 r u_matmul_axi_slave/mult_inst[0].u_mult/b1_c_reg_r1_0_15_0_5_i_20/O
|
|
net (fo=1, unplaced) 0.000 -1.793 u_matmul_axi_slave/mult_inst[0].u_mult/b1_c_reg_r1_0_15_0_5_i_20_n_0
|
|
r u_matmul_axi_slave/mult_inst[0].u_mult/b1_c_reg_r1_0_15_0_5_i_8/S[1]
|
|
CARRY4 (Prop_carry4_S[1]_CO[3])
|
|
0.550 -1.243 r u_matmul_axi_slave/mult_inst[0].u_mult/b1_c_reg_r1_0_15_0_5_i_8/CO[3]
|
|
net (fo=1, unplaced) 0.009 -1.234 u_matmul_axi_slave/mult_inst[0].u_mult/b1_c_reg_r1_0_15_0_5_i_8_n_0
|
|
r u_matmul_axi_slave/mult_inst[0].u_mult/b1_c_reg_r1_0_15_0_5_i_13/CI
|
|
CARRY4 (Prop_carry4_CI_O[1])
|
|
0.348 -0.886 r u_matmul_axi_slave/mult_inst[0].u_mult/b1_c_reg_r1_0_15_0_5_i_13/O[1]
|
|
net (fo=2, unplaced) 0.622 -0.264 u_matmul_axi_slave/calc_c_result02_out[5]
|
|
r u_matmul_axi_slave/b1_c_reg_r1_0_15_0_5_i_16/I0
|
|
LUT2 (Prop_lut2_I0_O) 0.306 0.042 r u_matmul_axi_slave/b1_c_reg_r1_0_15_0_5_i_16/O
|
|
net (fo=1, unplaced) 0.000 0.042 u_matmul_axi_slave/b1_c_reg_r1_0_15_0_5_i_16_n_0
|
|
r u_matmul_axi_slave/b1_c_reg_r1_0_15_0_5_i_3/S[1]
|
|
CARRY4 (Prop_carry4_S[1]_O[3])
|
|
0.640 0.682 r u_matmul_axi_slave/b1_c_reg_r1_0_15_0_5_i_3/O[3]
|
|
net (fo=15, unplaced) 0.671 1.353 u_matmul_axi_slave/b1_c_reg_r1_0_15_0_5_i_3_n_4
|
|
r u_matmul_axi_slave/crc_reg[12]_i_91/I2
|
|
LUT6 (Prop_lut6_I2_O) 0.307 1.660 r u_matmul_axi_slave/crc_reg[12]_i_91/O
|
|
net (fo=3, unplaced) 0.920 2.580 u_matmul_axi_slave/crc_reg[12]_i_91_n_0
|
|
r u_matmul_axi_slave/crc_reg[12]_i_72/I3
|
|
LUT6 (Prop_lut6_I3_O) 0.124 2.704 r u_matmul_axi_slave/crc_reg[12]_i_72/O
|
|
net (fo=7, unplaced) 0.484 3.188 u_matmul_axi_slave/crc_reg[12]_i_72_n_0
|
|
r u_matmul_axi_slave/crc_reg[12]_i_64/I1
|
|
LUT6 (Prop_lut6_I1_O) 0.124 3.312 r u_matmul_axi_slave/crc_reg[12]_i_64/O
|
|
net (fo=11, unplaced) 1.010 4.322 u_matmul_axi_slave/crc32_word_next_return4[3]
|
|
r u_matmul_axi_slave/crc_reg[31]_i_30/I1
|
|
LUT6 (Prop_lut6_I1_O) 0.124 4.446 r u_matmul_axi_slave/crc_reg[31]_i_30/O
|
|
net (fo=10, unplaced) 0.945 5.391 u_matmul_axi_slave/crc32_word_next_return1[5]
|
|
r u_matmul_axi_slave/crc_reg[23]_i_18/I1
|
|
LUT5 (Prop_lut5_I1_O) 0.124 5.515 r u_matmul_axi_slave/crc_reg[23]_i_18/O
|
|
net (fo=14, unplaced) 0.953 6.468 u_matmul_axi_slave/crc32_word_next0_return10[7]
|
|
r u_matmul_axi_slave/crc_reg[12]_i_33/I2
|
|
LUT6 (Prop_lut6_I2_O) 0.124 6.592 r u_matmul_axi_slave/crc_reg[12]_i_33/O
|
|
net (fo=11, unplaced) 0.948 7.540 u_matmul_axi_slave/crc32_word_next0_return7[5]
|
|
r u_matmul_axi_slave/crc_reg[23]_i_10/I1
|
|
LUT5 (Prop_lut5_I1_O) 0.124 7.664 r u_matmul_axi_slave/crc_reg[23]_i_10/O
|
|
net (fo=15, unplaced) 0.955 8.619 u_matmul_axi_slave/crc32_word_next0_return4[7]
|
|
r u_matmul_axi_slave/crc_reg[12]_i_32/I1
|
|
LUT4 (Prop_lut4_I1_O) 0.124 8.743 r u_matmul_axi_slave/crc_reg[12]_i_32/O
|
|
net (fo=1, unplaced) 0.902 9.645 u_matmul_axi_slave/crc32_word_next0_return3[21]
|
|
r u_matmul_axi_slave/crc_reg[12]_i_16/I0
|
|
LUT6 (Prop_lut6_I0_O) 0.124 9.769 r u_matmul_axi_slave/crc_reg[12]_i_16/O
|
|
net (fo=2, unplaced) 1.122 10.891 u_matmul_axi_slave/crc_reg[12]_i_16_n_0
|
|
r u_matmul_axi_slave/crc_reg[20]_i_8/I0
|
|
LUT5 (Prop_lut5_I0_O) 0.152 11.043 r u_matmul_axi_slave/crc_reg[20]_i_8/O
|
|
net (fo=6, unplaced) 0.934 11.977 u_matmul_axi_slave/crc32_word_next1_return7[4]
|
|
r u_matmul_axi_slave/crc_reg[20]_i_3/I2
|
|
LUT5 (Prop_lut5_I2_O) 0.150 12.127 r u_matmul_axi_slave/crc_reg[20]_i_3/O
|
|
net (fo=13, unplaced) 0.469 12.596 u_matmul_axi_slave/crc32_word_next1_return4[5]
|
|
r u_matmul_axi_slave/crc_reg[27]_i_2/I3
|
|
LUT5 (Prop_lut5_I3_O) 0.150 12.746 r u_matmul_axi_slave/crc_reg[27]_i_2/O
|
|
net (fo=13, unplaced) 0.952 13.698 u_matmul_axi_slave/crc32_word_next1_return1[3]
|
|
r u_matmul_axi_slave/crc_reg[4]_i_1/I2
|
|
LUT5 (Prop_lut5_I2_O) 0.124 13.822 r u_matmul_axi_slave/crc_reg[4]_i_1/O
|
|
net (fo=1, unplaced) 0.000 13.822 u_matmul_axi_slave/crc32_word_next1_return[4]
|
|
FDSE r u_matmul_axi_slave/crc_reg_reg[4]/D
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock sys_clk rise edge) 20.000 20.000 r
|
|
K21 0.000 20.000 r clk (IN)
|
|
net (fo=0) 0.000 20.000 pll_clk.u_clk_pll/inst/clk_in1
|
|
K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I
|
|
K21 IBUF (Prop_ibuf_I_O) 1.393 21.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O
|
|
net (fo=1, unplaced) 0.439 21.832 pll_clk.u_clk_pll/inst/clk_in1_clk_pll
|
|
r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1
|
|
PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1)
|
|
-6.040 15.792 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1
|
|
net (fo=1, unplaced) 0.760 16.552 pll_clk.u_clk_pll/inst/sys_clk_clk_pll
|
|
r pll_clk.u_clk_pll/inst/clkout2_buf/I
|
|
BUFG (Prop_bufg_I_O) 0.091 16.643 r pll_clk.u_clk_pll/inst/clkout2_buf/O
|
|
net (fo=10994, unplaced) 0.655 17.297 u_matmul_axi_slave/sys_clk
|
|
FDSE r u_matmul_axi_slave/crc_reg_reg[4]/C
|
|
clock pessimism -0.468 16.830
|
|
clock uncertainty -0.071 16.759
|
|
FDSE (Setup_fdse_C_D) 0.029 16.788 u_matmul_axi_slave/crc_reg_reg[4]
|
|
-------------------------------------------------------------------
|
|
required time 16.788
|
|
arrival time -13.822
|
|
-------------------------------------------------------------------
|
|
slack 2.966
|
|
|
|
Slack (MET) : 3.018ns (required time - arrival time)
|
|
Source: u_matmul_axi_slave/mult_inst[0].u_mult/p_reg[1]/C
|
|
(rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Destination: u_matmul_axi_slave/crc_reg_reg[10]/D
|
|
(rising edge-triggered cell FDSE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Path Group: sys_clk
|
|
Path Type: Setup (Max at Slow Process Corner)
|
|
Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns)
|
|
Data Path Delay: 16.795ns (logic 4.444ns (26.460%) route 12.351ns (73.540%))
|
|
Logic Levels: 18 (CARRY4=3 LUT2=3 LUT4=1 LUT5=4 LUT6=7)
|
|
Clock Path Skew: -0.145ns (DCD - SCD + CPR)
|
|
Destination Clock Delay (DCD): -2.703ns = ( 17.297 - 20.000 )
|
|
Source Clock Delay (SCD): -3.025ns
|
|
Clock Pessimism Removal (CPR): -0.468ns
|
|
Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Discrete Jitter (DJ): 0.122ns
|
|
Phase Error (PE): 0.000ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock sys_clk rise edge) 0.000 0.000 r
|
|
K21 0.000 0.000 r clk (IN)
|
|
net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1
|
|
K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I
|
|
K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O
|
|
net (fo=1, unplaced) 0.584 2.047 pll_clk.u_clk_pll/inst/clk_in1_clk_pll
|
|
r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1
|
|
PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1)
|
|
-6.768 -4.721 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1
|
|
net (fo=1, unplaced) 0.800 -3.921 pll_clk.u_clk_pll/inst/sys_clk_clk_pll
|
|
r pll_clk.u_clk_pll/inst/clkout2_buf/I
|
|
BUFG (Prop_bufg_I_O) 0.096 -3.825 r pll_clk.u_clk_pll/inst/clkout2_buf/O
|
|
net (fo=10994, unplaced) 0.800 -3.025 u_matmul_axi_slave/mult_inst[0].u_mult/sys_clk
|
|
FDRE r u_matmul_axi_slave/mult_inst[0].u_mult/p_reg[1]/C
|
|
------------------------------------------------------------------- -------------------
|
|
FDRE (Prop_fdre_C_Q) 0.456 -2.569 r u_matmul_axi_slave/mult_inst[0].u_mult/p_reg[1]/Q
|
|
net (fo=2, unplaced) 0.481 -2.088 u_matmul_axi_slave/mult_inst[0].u_mult/mult_p[0]_0[1]
|
|
r u_matmul_axi_slave/mult_inst[0].u_mult/b1_c_reg_r1_0_15_0_5_i_20/I0
|
|
LUT2 (Prop_lut2_I0_O) 0.295 -1.793 r u_matmul_axi_slave/mult_inst[0].u_mult/b1_c_reg_r1_0_15_0_5_i_20/O
|
|
net (fo=1, unplaced) 0.000 -1.793 u_matmul_axi_slave/mult_inst[0].u_mult/b1_c_reg_r1_0_15_0_5_i_20_n_0
|
|
r u_matmul_axi_slave/mult_inst[0].u_mult/b1_c_reg_r1_0_15_0_5_i_8/S[1]
|
|
CARRY4 (Prop_carry4_S[1]_CO[3])
|
|
0.550 -1.243 r u_matmul_axi_slave/mult_inst[0].u_mult/b1_c_reg_r1_0_15_0_5_i_8/CO[3]
|
|
net (fo=1, unplaced) 0.009 -1.234 u_matmul_axi_slave/mult_inst[0].u_mult/b1_c_reg_r1_0_15_0_5_i_8_n_0
|
|
r u_matmul_axi_slave/mult_inst[0].u_mult/b1_c_reg_r1_0_15_0_5_i_13/CI
|
|
CARRY4 (Prop_carry4_CI_O[1])
|
|
0.348 -0.886 r u_matmul_axi_slave/mult_inst[0].u_mult/b1_c_reg_r1_0_15_0_5_i_13/O[1]
|
|
net (fo=2, unplaced) 0.622 -0.264 u_matmul_axi_slave/calc_c_result02_out[5]
|
|
r u_matmul_axi_slave/b1_c_reg_r1_0_15_0_5_i_16/I0
|
|
LUT2 (Prop_lut2_I0_O) 0.306 0.042 r u_matmul_axi_slave/b1_c_reg_r1_0_15_0_5_i_16/O
|
|
net (fo=1, unplaced) 0.000 0.042 u_matmul_axi_slave/b1_c_reg_r1_0_15_0_5_i_16_n_0
|
|
r u_matmul_axi_slave/b1_c_reg_r1_0_15_0_5_i_3/S[1]
|
|
CARRY4 (Prop_carry4_S[1]_O[3])
|
|
0.640 0.682 r u_matmul_axi_slave/b1_c_reg_r1_0_15_0_5_i_3/O[3]
|
|
net (fo=15, unplaced) 0.671 1.353 u_matmul_axi_slave/b1_c_reg_r1_0_15_0_5_i_3_n_4
|
|
r u_matmul_axi_slave/crc_reg[12]_i_91/I2
|
|
LUT6 (Prop_lut6_I2_O) 0.307 1.660 r u_matmul_axi_slave/crc_reg[12]_i_91/O
|
|
net (fo=3, unplaced) 0.920 2.580 u_matmul_axi_slave/crc_reg[12]_i_91_n_0
|
|
r u_matmul_axi_slave/crc_reg[12]_i_72/I3
|
|
LUT6 (Prop_lut6_I3_O) 0.124 2.704 r u_matmul_axi_slave/crc_reg[12]_i_72/O
|
|
net (fo=7, unplaced) 0.484 3.188 u_matmul_axi_slave/crc_reg[12]_i_72_n_0
|
|
r u_matmul_axi_slave/crc_reg[12]_i_64/I1
|
|
LUT6 (Prop_lut6_I1_O) 0.124 3.312 r u_matmul_axi_slave/crc_reg[12]_i_64/O
|
|
net (fo=11, unplaced) 1.010 4.322 u_matmul_axi_slave/crc32_word_next_return4[3]
|
|
r u_matmul_axi_slave/crc_reg[31]_i_30/I1
|
|
LUT6 (Prop_lut6_I1_O) 0.124 4.446 r u_matmul_axi_slave/crc_reg[31]_i_30/O
|
|
net (fo=10, unplaced) 0.945 5.391 u_matmul_axi_slave/crc32_word_next_return1[5]
|
|
r u_matmul_axi_slave/crc_reg[23]_i_18/I1
|
|
LUT5 (Prop_lut5_I1_O) 0.124 5.515 r u_matmul_axi_slave/crc_reg[23]_i_18/O
|
|
net (fo=14, unplaced) 0.953 6.468 u_matmul_axi_slave/crc32_word_next0_return10[7]
|
|
r u_matmul_axi_slave/crc_reg[12]_i_33/I2
|
|
LUT6 (Prop_lut6_I2_O) 0.124 6.592 r u_matmul_axi_slave/crc_reg[12]_i_33/O
|
|
net (fo=11, unplaced) 0.948 7.540 u_matmul_axi_slave/crc32_word_next0_return7[5]
|
|
r u_matmul_axi_slave/crc_reg[23]_i_10/I1
|
|
LUT5 (Prop_lut5_I1_O) 0.124 7.664 r u_matmul_axi_slave/crc_reg[23]_i_10/O
|
|
net (fo=15, unplaced) 0.955 8.619 u_matmul_axi_slave/crc32_word_next0_return4[7]
|
|
r u_matmul_axi_slave/crc_reg[12]_i_32/I1
|
|
LUT4 (Prop_lut4_I1_O) 0.124 8.743 r u_matmul_axi_slave/crc_reg[12]_i_32/O
|
|
net (fo=1, unplaced) 0.902 9.645 u_matmul_axi_slave/crc32_word_next0_return3[21]
|
|
r u_matmul_axi_slave/crc_reg[12]_i_16/I0
|
|
LUT6 (Prop_lut6_I0_O) 0.124 9.769 r u_matmul_axi_slave/crc_reg[12]_i_16/O
|
|
net (fo=2, unplaced) 1.122 10.891 u_matmul_axi_slave/crc_reg[12]_i_16_n_0
|
|
r u_matmul_axi_slave/crc_reg[20]_i_8/I0
|
|
LUT5 (Prop_lut5_I0_O) 0.152 11.043 r u_matmul_axi_slave/crc_reg[20]_i_8/O
|
|
net (fo=6, unplaced) 0.934 11.977 u_matmul_axi_slave/crc32_word_next1_return7[4]
|
|
r u_matmul_axi_slave/crc_reg[20]_i_3/I2
|
|
LUT5 (Prop_lut5_I2_O) 0.150 12.127 r u_matmul_axi_slave/crc_reg[20]_i_3/O
|
|
net (fo=13, unplaced) 0.469 12.596 u_matmul_axi_slave/crc32_word_next1_return4[5]
|
|
r u_matmul_axi_slave/crc_reg[21]_i_2/I0
|
|
LUT2 (Prop_lut2_I0_O) 0.124 12.720 r u_matmul_axi_slave/crc_reg[21]_i_2/O
|
|
net (fo=4, unplaced) 0.926 13.646 u_matmul_axi_slave/crc_reg[21]_i_2_n_0
|
|
r u_matmul_axi_slave/crc_reg[10]_i_1/I2
|
|
LUT6 (Prop_lut6_I2_O) 0.124 13.770 r u_matmul_axi_slave/crc_reg[10]_i_1/O
|
|
net (fo=1, unplaced) 0.000 13.770 u_matmul_axi_slave/crc32_word_next1_return[10]
|
|
FDSE r u_matmul_axi_slave/crc_reg_reg[10]/D
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock sys_clk rise edge) 20.000 20.000 r
|
|
K21 0.000 20.000 r clk (IN)
|
|
net (fo=0) 0.000 20.000 pll_clk.u_clk_pll/inst/clk_in1
|
|
K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I
|
|
K21 IBUF (Prop_ibuf_I_O) 1.393 21.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O
|
|
net (fo=1, unplaced) 0.439 21.832 pll_clk.u_clk_pll/inst/clk_in1_clk_pll
|
|
r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1
|
|
PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1)
|
|
-6.040 15.792 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1
|
|
net (fo=1, unplaced) 0.760 16.552 pll_clk.u_clk_pll/inst/sys_clk_clk_pll
|
|
r pll_clk.u_clk_pll/inst/clkout2_buf/I
|
|
BUFG (Prop_bufg_I_O) 0.091 16.643 r pll_clk.u_clk_pll/inst/clkout2_buf/O
|
|
net (fo=10994, unplaced) 0.655 17.297 u_matmul_axi_slave/sys_clk
|
|
FDSE r u_matmul_axi_slave/crc_reg_reg[10]/C
|
|
clock pessimism -0.468 16.830
|
|
clock uncertainty -0.071 16.759
|
|
FDSE (Setup_fdse_C_D) 0.029 16.788 u_matmul_axi_slave/crc_reg_reg[10]
|
|
-------------------------------------------------------------------
|
|
required time 16.788
|
|
arrival time -13.770
|
|
-------------------------------------------------------------------
|
|
slack 3.018
|
|
|
|
Slack (MET) : 3.018ns (required time - arrival time)
|
|
Source: u_matmul_axi_slave/mult_inst[0].u_mult/p_reg[1]/C
|
|
(rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Destination: u_matmul_axi_slave/crc_reg_reg[11]/D
|
|
(rising edge-triggered cell FDSE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Path Group: sys_clk
|
|
Path Type: Setup (Max at Slow Process Corner)
|
|
Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns)
|
|
Data Path Delay: 16.795ns (logic 4.444ns (26.460%) route 12.351ns (73.540%))
|
|
Logic Levels: 18 (CARRY4=3 LUT2=3 LUT4=1 LUT5=4 LUT6=7)
|
|
Clock Path Skew: -0.145ns (DCD - SCD + CPR)
|
|
Destination Clock Delay (DCD): -2.703ns = ( 17.297 - 20.000 )
|
|
Source Clock Delay (SCD): -3.025ns
|
|
Clock Pessimism Removal (CPR): -0.468ns
|
|
Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Discrete Jitter (DJ): 0.122ns
|
|
Phase Error (PE): 0.000ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock sys_clk rise edge) 0.000 0.000 r
|
|
K21 0.000 0.000 r clk (IN)
|
|
net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1
|
|
K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I
|
|
K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O
|
|
net (fo=1, unplaced) 0.584 2.047 pll_clk.u_clk_pll/inst/clk_in1_clk_pll
|
|
r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1
|
|
PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1)
|
|
-6.768 -4.721 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1
|
|
net (fo=1, unplaced) 0.800 -3.921 pll_clk.u_clk_pll/inst/sys_clk_clk_pll
|
|
r pll_clk.u_clk_pll/inst/clkout2_buf/I
|
|
BUFG (Prop_bufg_I_O) 0.096 -3.825 r pll_clk.u_clk_pll/inst/clkout2_buf/O
|
|
net (fo=10994, unplaced) 0.800 -3.025 u_matmul_axi_slave/mult_inst[0].u_mult/sys_clk
|
|
FDRE r u_matmul_axi_slave/mult_inst[0].u_mult/p_reg[1]/C
|
|
------------------------------------------------------------------- -------------------
|
|
FDRE (Prop_fdre_C_Q) 0.456 -2.569 r u_matmul_axi_slave/mult_inst[0].u_mult/p_reg[1]/Q
|
|
net (fo=2, unplaced) 0.481 -2.088 u_matmul_axi_slave/mult_inst[0].u_mult/mult_p[0]_0[1]
|
|
r u_matmul_axi_slave/mult_inst[0].u_mult/b1_c_reg_r1_0_15_0_5_i_20/I0
|
|
LUT2 (Prop_lut2_I0_O) 0.295 -1.793 r u_matmul_axi_slave/mult_inst[0].u_mult/b1_c_reg_r1_0_15_0_5_i_20/O
|
|
net (fo=1, unplaced) 0.000 -1.793 u_matmul_axi_slave/mult_inst[0].u_mult/b1_c_reg_r1_0_15_0_5_i_20_n_0
|
|
r u_matmul_axi_slave/mult_inst[0].u_mult/b1_c_reg_r1_0_15_0_5_i_8/S[1]
|
|
CARRY4 (Prop_carry4_S[1]_CO[3])
|
|
0.550 -1.243 r u_matmul_axi_slave/mult_inst[0].u_mult/b1_c_reg_r1_0_15_0_5_i_8/CO[3]
|
|
net (fo=1, unplaced) 0.009 -1.234 u_matmul_axi_slave/mult_inst[0].u_mult/b1_c_reg_r1_0_15_0_5_i_8_n_0
|
|
r u_matmul_axi_slave/mult_inst[0].u_mult/b1_c_reg_r1_0_15_0_5_i_13/CI
|
|
CARRY4 (Prop_carry4_CI_O[1])
|
|
0.348 -0.886 r u_matmul_axi_slave/mult_inst[0].u_mult/b1_c_reg_r1_0_15_0_5_i_13/O[1]
|
|
net (fo=2, unplaced) 0.622 -0.264 u_matmul_axi_slave/calc_c_result02_out[5]
|
|
r u_matmul_axi_slave/b1_c_reg_r1_0_15_0_5_i_16/I0
|
|
LUT2 (Prop_lut2_I0_O) 0.306 0.042 r u_matmul_axi_slave/b1_c_reg_r1_0_15_0_5_i_16/O
|
|
net (fo=1, unplaced) 0.000 0.042 u_matmul_axi_slave/b1_c_reg_r1_0_15_0_5_i_16_n_0
|
|
r u_matmul_axi_slave/b1_c_reg_r1_0_15_0_5_i_3/S[1]
|
|
CARRY4 (Prop_carry4_S[1]_O[3])
|
|
0.640 0.682 r u_matmul_axi_slave/b1_c_reg_r1_0_15_0_5_i_3/O[3]
|
|
net (fo=15, unplaced) 0.671 1.353 u_matmul_axi_slave/b1_c_reg_r1_0_15_0_5_i_3_n_4
|
|
r u_matmul_axi_slave/crc_reg[12]_i_91/I2
|
|
LUT6 (Prop_lut6_I2_O) 0.307 1.660 r u_matmul_axi_slave/crc_reg[12]_i_91/O
|
|
net (fo=3, unplaced) 0.920 2.580 u_matmul_axi_slave/crc_reg[12]_i_91_n_0
|
|
r u_matmul_axi_slave/crc_reg[12]_i_72/I3
|
|
LUT6 (Prop_lut6_I3_O) 0.124 2.704 r u_matmul_axi_slave/crc_reg[12]_i_72/O
|
|
net (fo=7, unplaced) 0.484 3.188 u_matmul_axi_slave/crc_reg[12]_i_72_n_0
|
|
r u_matmul_axi_slave/crc_reg[12]_i_64/I1
|
|
LUT6 (Prop_lut6_I1_O) 0.124 3.312 r u_matmul_axi_slave/crc_reg[12]_i_64/O
|
|
net (fo=11, unplaced) 1.010 4.322 u_matmul_axi_slave/crc32_word_next_return4[3]
|
|
r u_matmul_axi_slave/crc_reg[31]_i_30/I1
|
|
LUT6 (Prop_lut6_I1_O) 0.124 4.446 r u_matmul_axi_slave/crc_reg[31]_i_30/O
|
|
net (fo=10, unplaced) 0.945 5.391 u_matmul_axi_slave/crc32_word_next_return1[5]
|
|
r u_matmul_axi_slave/crc_reg[23]_i_18/I1
|
|
LUT5 (Prop_lut5_I1_O) 0.124 5.515 r u_matmul_axi_slave/crc_reg[23]_i_18/O
|
|
net (fo=14, unplaced) 0.953 6.468 u_matmul_axi_slave/crc32_word_next0_return10[7]
|
|
r u_matmul_axi_slave/crc_reg[12]_i_33/I2
|
|
LUT6 (Prop_lut6_I2_O) 0.124 6.592 r u_matmul_axi_slave/crc_reg[12]_i_33/O
|
|
net (fo=11, unplaced) 0.948 7.540 u_matmul_axi_slave/crc32_word_next0_return7[5]
|
|
r u_matmul_axi_slave/crc_reg[23]_i_10/I1
|
|
LUT5 (Prop_lut5_I1_O) 0.124 7.664 r u_matmul_axi_slave/crc_reg[23]_i_10/O
|
|
net (fo=15, unplaced) 0.955 8.619 u_matmul_axi_slave/crc32_word_next0_return4[7]
|
|
r u_matmul_axi_slave/crc_reg[12]_i_32/I1
|
|
LUT4 (Prop_lut4_I1_O) 0.124 8.743 r u_matmul_axi_slave/crc_reg[12]_i_32/O
|
|
net (fo=1, unplaced) 0.902 9.645 u_matmul_axi_slave/crc32_word_next0_return3[21]
|
|
r u_matmul_axi_slave/crc_reg[12]_i_16/I0
|
|
LUT6 (Prop_lut6_I0_O) 0.124 9.769 r u_matmul_axi_slave/crc_reg[12]_i_16/O
|
|
net (fo=2, unplaced) 1.122 10.891 u_matmul_axi_slave/crc_reg[12]_i_16_n_0
|
|
r u_matmul_axi_slave/crc_reg[20]_i_8/I0
|
|
LUT5 (Prop_lut5_I0_O) 0.152 11.043 r u_matmul_axi_slave/crc_reg[20]_i_8/O
|
|
net (fo=6, unplaced) 0.934 11.977 u_matmul_axi_slave/crc32_word_next1_return7[4]
|
|
r u_matmul_axi_slave/crc_reg[20]_i_3/I2
|
|
LUT5 (Prop_lut5_I2_O) 0.150 12.127 r u_matmul_axi_slave/crc_reg[20]_i_3/O
|
|
net (fo=13, unplaced) 0.469 12.596 u_matmul_axi_slave/crc32_word_next1_return4[5]
|
|
r u_matmul_axi_slave/crc_reg[21]_i_2/I0
|
|
LUT2 (Prop_lut2_I0_O) 0.124 12.720 r u_matmul_axi_slave/crc_reg[21]_i_2/O
|
|
net (fo=4, unplaced) 0.926 13.646 u_matmul_axi_slave/crc_reg[21]_i_2_n_0
|
|
r u_matmul_axi_slave/crc_reg[11]_i_1/I1
|
|
LUT6 (Prop_lut6_I1_O) 0.124 13.770 r u_matmul_axi_slave/crc_reg[11]_i_1/O
|
|
net (fo=1, unplaced) 0.000 13.770 u_matmul_axi_slave/crc32_word_next1_return[11]
|
|
FDSE r u_matmul_axi_slave/crc_reg_reg[11]/D
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock sys_clk rise edge) 20.000 20.000 r
|
|
K21 0.000 20.000 r clk (IN)
|
|
net (fo=0) 0.000 20.000 pll_clk.u_clk_pll/inst/clk_in1
|
|
K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I
|
|
K21 IBUF (Prop_ibuf_I_O) 1.393 21.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O
|
|
net (fo=1, unplaced) 0.439 21.832 pll_clk.u_clk_pll/inst/clk_in1_clk_pll
|
|
r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1
|
|
PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1)
|
|
-6.040 15.792 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1
|
|
net (fo=1, unplaced) 0.760 16.552 pll_clk.u_clk_pll/inst/sys_clk_clk_pll
|
|
r pll_clk.u_clk_pll/inst/clkout2_buf/I
|
|
BUFG (Prop_bufg_I_O) 0.091 16.643 r pll_clk.u_clk_pll/inst/clkout2_buf/O
|
|
net (fo=10994, unplaced) 0.655 17.297 u_matmul_axi_slave/sys_clk
|
|
FDSE r u_matmul_axi_slave/crc_reg_reg[11]/C
|
|
clock pessimism -0.468 16.830
|
|
clock uncertainty -0.071 16.759
|
|
FDSE (Setup_fdse_C_D) 0.029 16.788 u_matmul_axi_slave/crc_reg_reg[11]
|
|
-------------------------------------------------------------------
|
|
required time 16.788
|
|
arrival time -13.770
|
|
-------------------------------------------------------------------
|
|
slack 3.018
|
|
|
|
Slack (MET) : 3.018ns (required time - arrival time)
|
|
Source: u_matmul_axi_slave/mult_inst[0].u_mult/p_reg[1]/C
|
|
(rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Destination: u_matmul_axi_slave/crc_reg_reg[9]/D
|
|
(rising edge-triggered cell FDSE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Path Group: sys_clk
|
|
Path Type: Setup (Max at Slow Process Corner)
|
|
Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns)
|
|
Data Path Delay: 16.795ns (logic 4.444ns (26.460%) route 12.351ns (73.540%))
|
|
Logic Levels: 18 (CARRY4=3 LUT2=3 LUT4=1 LUT5=5 LUT6=6)
|
|
Clock Path Skew: -0.145ns (DCD - SCD + CPR)
|
|
Destination Clock Delay (DCD): -2.703ns = ( 17.297 - 20.000 )
|
|
Source Clock Delay (SCD): -3.025ns
|
|
Clock Pessimism Removal (CPR): -0.468ns
|
|
Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Discrete Jitter (DJ): 0.122ns
|
|
Phase Error (PE): 0.000ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock sys_clk rise edge) 0.000 0.000 r
|
|
K21 0.000 0.000 r clk (IN)
|
|
net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1
|
|
K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I
|
|
K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O
|
|
net (fo=1, unplaced) 0.584 2.047 pll_clk.u_clk_pll/inst/clk_in1_clk_pll
|
|
r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1
|
|
PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1)
|
|
-6.768 -4.721 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1
|
|
net (fo=1, unplaced) 0.800 -3.921 pll_clk.u_clk_pll/inst/sys_clk_clk_pll
|
|
r pll_clk.u_clk_pll/inst/clkout2_buf/I
|
|
BUFG (Prop_bufg_I_O) 0.096 -3.825 r pll_clk.u_clk_pll/inst/clkout2_buf/O
|
|
net (fo=10994, unplaced) 0.800 -3.025 u_matmul_axi_slave/mult_inst[0].u_mult/sys_clk
|
|
FDRE r u_matmul_axi_slave/mult_inst[0].u_mult/p_reg[1]/C
|
|
------------------------------------------------------------------- -------------------
|
|
FDRE (Prop_fdre_C_Q) 0.456 -2.569 r u_matmul_axi_slave/mult_inst[0].u_mult/p_reg[1]/Q
|
|
net (fo=2, unplaced) 0.481 -2.088 u_matmul_axi_slave/mult_inst[0].u_mult/mult_p[0]_0[1]
|
|
r u_matmul_axi_slave/mult_inst[0].u_mult/b1_c_reg_r1_0_15_0_5_i_20/I0
|
|
LUT2 (Prop_lut2_I0_O) 0.295 -1.793 r u_matmul_axi_slave/mult_inst[0].u_mult/b1_c_reg_r1_0_15_0_5_i_20/O
|
|
net (fo=1, unplaced) 0.000 -1.793 u_matmul_axi_slave/mult_inst[0].u_mult/b1_c_reg_r1_0_15_0_5_i_20_n_0
|
|
r u_matmul_axi_slave/mult_inst[0].u_mult/b1_c_reg_r1_0_15_0_5_i_8/S[1]
|
|
CARRY4 (Prop_carry4_S[1]_CO[3])
|
|
0.550 -1.243 r u_matmul_axi_slave/mult_inst[0].u_mult/b1_c_reg_r1_0_15_0_5_i_8/CO[3]
|
|
net (fo=1, unplaced) 0.009 -1.234 u_matmul_axi_slave/mult_inst[0].u_mult/b1_c_reg_r1_0_15_0_5_i_8_n_0
|
|
r u_matmul_axi_slave/mult_inst[0].u_mult/b1_c_reg_r1_0_15_0_5_i_13/CI
|
|
CARRY4 (Prop_carry4_CI_O[1])
|
|
0.348 -0.886 r u_matmul_axi_slave/mult_inst[0].u_mult/b1_c_reg_r1_0_15_0_5_i_13/O[1]
|
|
net (fo=2, unplaced) 0.622 -0.264 u_matmul_axi_slave/calc_c_result02_out[5]
|
|
r u_matmul_axi_slave/b1_c_reg_r1_0_15_0_5_i_16/I0
|
|
LUT2 (Prop_lut2_I0_O) 0.306 0.042 r u_matmul_axi_slave/b1_c_reg_r1_0_15_0_5_i_16/O
|
|
net (fo=1, unplaced) 0.000 0.042 u_matmul_axi_slave/b1_c_reg_r1_0_15_0_5_i_16_n_0
|
|
r u_matmul_axi_slave/b1_c_reg_r1_0_15_0_5_i_3/S[1]
|
|
CARRY4 (Prop_carry4_S[1]_O[3])
|
|
0.640 0.682 r u_matmul_axi_slave/b1_c_reg_r1_0_15_0_5_i_3/O[3]
|
|
net (fo=15, unplaced) 0.671 1.353 u_matmul_axi_slave/b1_c_reg_r1_0_15_0_5_i_3_n_4
|
|
r u_matmul_axi_slave/crc_reg[12]_i_91/I2
|
|
LUT6 (Prop_lut6_I2_O) 0.307 1.660 r u_matmul_axi_slave/crc_reg[12]_i_91/O
|
|
net (fo=3, unplaced) 0.920 2.580 u_matmul_axi_slave/crc_reg[12]_i_91_n_0
|
|
r u_matmul_axi_slave/crc_reg[12]_i_72/I3
|
|
LUT6 (Prop_lut6_I3_O) 0.124 2.704 r u_matmul_axi_slave/crc_reg[12]_i_72/O
|
|
net (fo=7, unplaced) 0.484 3.188 u_matmul_axi_slave/crc_reg[12]_i_72_n_0
|
|
r u_matmul_axi_slave/crc_reg[12]_i_64/I1
|
|
LUT6 (Prop_lut6_I1_O) 0.124 3.312 r u_matmul_axi_slave/crc_reg[12]_i_64/O
|
|
net (fo=11, unplaced) 1.010 4.322 u_matmul_axi_slave/crc32_word_next_return4[3]
|
|
r u_matmul_axi_slave/crc_reg[31]_i_30/I1
|
|
LUT6 (Prop_lut6_I1_O) 0.124 4.446 r u_matmul_axi_slave/crc_reg[31]_i_30/O
|
|
net (fo=10, unplaced) 0.945 5.391 u_matmul_axi_slave/crc32_word_next_return1[5]
|
|
r u_matmul_axi_slave/crc_reg[23]_i_18/I1
|
|
LUT5 (Prop_lut5_I1_O) 0.124 5.515 r u_matmul_axi_slave/crc_reg[23]_i_18/O
|
|
net (fo=14, unplaced) 0.953 6.468 u_matmul_axi_slave/crc32_word_next0_return10[7]
|
|
r u_matmul_axi_slave/crc_reg[12]_i_33/I2
|
|
LUT6 (Prop_lut6_I2_O) 0.124 6.592 r u_matmul_axi_slave/crc_reg[12]_i_33/O
|
|
net (fo=11, unplaced) 0.948 7.540 u_matmul_axi_slave/crc32_word_next0_return7[5]
|
|
r u_matmul_axi_slave/crc_reg[23]_i_10/I1
|
|
LUT5 (Prop_lut5_I1_O) 0.124 7.664 r u_matmul_axi_slave/crc_reg[23]_i_10/O
|
|
net (fo=15, unplaced) 0.955 8.619 u_matmul_axi_slave/crc32_word_next0_return4[7]
|
|
r u_matmul_axi_slave/crc_reg[12]_i_32/I1
|
|
LUT4 (Prop_lut4_I1_O) 0.124 8.743 r u_matmul_axi_slave/crc_reg[12]_i_32/O
|
|
net (fo=1, unplaced) 0.902 9.645 u_matmul_axi_slave/crc32_word_next0_return3[21]
|
|
r u_matmul_axi_slave/crc_reg[12]_i_16/I0
|
|
LUT6 (Prop_lut6_I0_O) 0.124 9.769 r u_matmul_axi_slave/crc_reg[12]_i_16/O
|
|
net (fo=2, unplaced) 1.122 10.891 u_matmul_axi_slave/crc_reg[12]_i_16_n_0
|
|
r u_matmul_axi_slave/crc_reg[20]_i_8/I0
|
|
LUT5 (Prop_lut5_I0_O) 0.152 11.043 r u_matmul_axi_slave/crc_reg[20]_i_8/O
|
|
net (fo=6, unplaced) 0.934 11.977 u_matmul_axi_slave/crc32_word_next1_return7[4]
|
|
r u_matmul_axi_slave/crc_reg[20]_i_3/I2
|
|
LUT5 (Prop_lut5_I2_O) 0.150 12.127 r u_matmul_axi_slave/crc_reg[20]_i_3/O
|
|
net (fo=13, unplaced) 0.469 12.596 u_matmul_axi_slave/crc32_word_next1_return4[5]
|
|
r u_matmul_axi_slave/crc_reg[21]_i_2/I0
|
|
LUT2 (Prop_lut2_I0_O) 0.124 12.720 r u_matmul_axi_slave/crc_reg[21]_i_2/O
|
|
net (fo=4, unplaced) 0.926 13.646 u_matmul_axi_slave/crc_reg[21]_i_2_n_0
|
|
r u_matmul_axi_slave/crc_reg[9]_i_1/I1
|
|
LUT5 (Prop_lut5_I1_O) 0.124 13.770 r u_matmul_axi_slave/crc_reg[9]_i_1/O
|
|
net (fo=1, unplaced) 0.000 13.770 u_matmul_axi_slave/crc32_word_next1_return[9]
|
|
FDSE r u_matmul_axi_slave/crc_reg_reg[9]/D
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock sys_clk rise edge) 20.000 20.000 r
|
|
K21 0.000 20.000 r clk (IN)
|
|
net (fo=0) 0.000 20.000 pll_clk.u_clk_pll/inst/clk_in1
|
|
K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I
|
|
K21 IBUF (Prop_ibuf_I_O) 1.393 21.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O
|
|
net (fo=1, unplaced) 0.439 21.832 pll_clk.u_clk_pll/inst/clk_in1_clk_pll
|
|
r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1
|
|
PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1)
|
|
-6.040 15.792 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1
|
|
net (fo=1, unplaced) 0.760 16.552 pll_clk.u_clk_pll/inst/sys_clk_clk_pll
|
|
r pll_clk.u_clk_pll/inst/clkout2_buf/I
|
|
BUFG (Prop_bufg_I_O) 0.091 16.643 r pll_clk.u_clk_pll/inst/clkout2_buf/O
|
|
net (fo=10994, unplaced) 0.655 17.297 u_matmul_axi_slave/sys_clk
|
|
FDSE r u_matmul_axi_slave/crc_reg_reg[9]/C
|
|
clock pessimism -0.468 16.830
|
|
clock uncertainty -0.071 16.759
|
|
FDSE (Setup_fdse_C_D) 0.029 16.788 u_matmul_axi_slave/crc_reg_reg[9]
|
|
-------------------------------------------------------------------
|
|
required time 16.788
|
|
arrival time -13.770
|
|
-------------------------------------------------------------------
|
|
slack 3.018
|
|
|
|
Slack (MET) : 3.125ns (required time - arrival time)
|
|
Source: u_matmul_axi_slave/mult_inst[0].u_mult/p_reg[1]/C
|
|
(rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Destination: u_matmul_axi_slave/crc_reg_reg[14]/D
|
|
(rising edge-triggered cell FDSE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Path Group: sys_clk
|
|
Path Type: Setup (Max at Slow Process Corner)
|
|
Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns)
|
|
Data Path Delay: 16.688ns (logic 4.416ns (26.462%) route 12.272ns (73.538%))
|
|
Logic Levels: 18 (CARRY4=3 LUT2=2 LUT3=1 LUT4=2 LUT5=3 LUT6=7)
|
|
Clock Path Skew: -0.145ns (DCD - SCD + CPR)
|
|
Destination Clock Delay (DCD): -2.703ns = ( 17.297 - 20.000 )
|
|
Source Clock Delay (SCD): -3.025ns
|
|
Clock Pessimism Removal (CPR): -0.468ns
|
|
Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Discrete Jitter (DJ): 0.122ns
|
|
Phase Error (PE): 0.000ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock sys_clk rise edge) 0.000 0.000 r
|
|
K21 0.000 0.000 r clk (IN)
|
|
net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1
|
|
K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I
|
|
K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O
|
|
net (fo=1, unplaced) 0.584 2.047 pll_clk.u_clk_pll/inst/clk_in1_clk_pll
|
|
r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1
|
|
PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1)
|
|
-6.768 -4.721 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1
|
|
net (fo=1, unplaced) 0.800 -3.921 pll_clk.u_clk_pll/inst/sys_clk_clk_pll
|
|
r pll_clk.u_clk_pll/inst/clkout2_buf/I
|
|
BUFG (Prop_bufg_I_O) 0.096 -3.825 r pll_clk.u_clk_pll/inst/clkout2_buf/O
|
|
net (fo=10994, unplaced) 0.800 -3.025 u_matmul_axi_slave/mult_inst[0].u_mult/sys_clk
|
|
FDRE r u_matmul_axi_slave/mult_inst[0].u_mult/p_reg[1]/C
|
|
------------------------------------------------------------------- -------------------
|
|
FDRE (Prop_fdre_C_Q) 0.456 -2.569 r u_matmul_axi_slave/mult_inst[0].u_mult/p_reg[1]/Q
|
|
net (fo=2, unplaced) 0.481 -2.088 u_matmul_axi_slave/mult_inst[0].u_mult/mult_p[0]_0[1]
|
|
r u_matmul_axi_slave/mult_inst[0].u_mult/b1_c_reg_r1_0_15_0_5_i_20/I0
|
|
LUT2 (Prop_lut2_I0_O) 0.295 -1.793 r u_matmul_axi_slave/mult_inst[0].u_mult/b1_c_reg_r1_0_15_0_5_i_20/O
|
|
net (fo=1, unplaced) 0.000 -1.793 u_matmul_axi_slave/mult_inst[0].u_mult/b1_c_reg_r1_0_15_0_5_i_20_n_0
|
|
r u_matmul_axi_slave/mult_inst[0].u_mult/b1_c_reg_r1_0_15_0_5_i_8/S[1]
|
|
CARRY4 (Prop_carry4_S[1]_CO[3])
|
|
0.550 -1.243 r u_matmul_axi_slave/mult_inst[0].u_mult/b1_c_reg_r1_0_15_0_5_i_8/CO[3]
|
|
net (fo=1, unplaced) 0.009 -1.234 u_matmul_axi_slave/mult_inst[0].u_mult/b1_c_reg_r1_0_15_0_5_i_8_n_0
|
|
r u_matmul_axi_slave/mult_inst[0].u_mult/b1_c_reg_r1_0_15_0_5_i_13/CI
|
|
CARRY4 (Prop_carry4_CI_O[1])
|
|
0.348 -0.886 r u_matmul_axi_slave/mult_inst[0].u_mult/b1_c_reg_r1_0_15_0_5_i_13/O[1]
|
|
net (fo=2, unplaced) 0.622 -0.264 u_matmul_axi_slave/calc_c_result02_out[5]
|
|
r u_matmul_axi_slave/b1_c_reg_r1_0_15_0_5_i_16/I0
|
|
LUT2 (Prop_lut2_I0_O) 0.306 0.042 r u_matmul_axi_slave/b1_c_reg_r1_0_15_0_5_i_16/O
|
|
net (fo=1, unplaced) 0.000 0.042 u_matmul_axi_slave/b1_c_reg_r1_0_15_0_5_i_16_n_0
|
|
r u_matmul_axi_slave/b1_c_reg_r1_0_15_0_5_i_3/S[1]
|
|
CARRY4 (Prop_carry4_S[1]_O[3])
|
|
0.640 0.682 r u_matmul_axi_slave/b1_c_reg_r1_0_15_0_5_i_3/O[3]
|
|
net (fo=15, unplaced) 0.671 1.353 u_matmul_axi_slave/b1_c_reg_r1_0_15_0_5_i_3_n_4
|
|
r u_matmul_axi_slave/crc_reg[12]_i_91/I2
|
|
LUT6 (Prop_lut6_I2_O) 0.307 1.660 r u_matmul_axi_slave/crc_reg[12]_i_91/O
|
|
net (fo=3, unplaced) 0.920 2.580 u_matmul_axi_slave/crc_reg[12]_i_91_n_0
|
|
r u_matmul_axi_slave/crc_reg[12]_i_72/I3
|
|
LUT6 (Prop_lut6_I3_O) 0.124 2.704 r u_matmul_axi_slave/crc_reg[12]_i_72/O
|
|
net (fo=7, unplaced) 0.484 3.188 u_matmul_axi_slave/crc_reg[12]_i_72_n_0
|
|
r u_matmul_axi_slave/crc_reg[12]_i_64/I1
|
|
LUT6 (Prop_lut6_I1_O) 0.124 3.312 r u_matmul_axi_slave/crc_reg[12]_i_64/O
|
|
net (fo=11, unplaced) 0.948 4.260 u_matmul_axi_slave/crc32_word_next_return4[3]
|
|
r u_matmul_axi_slave/crc_reg[12]_i_52/I1
|
|
LUT6 (Prop_lut6_I1_O) 0.124 4.384 r u_matmul_axi_slave/crc_reg[12]_i_52/O
|
|
net (fo=11, unplaced) 1.157 5.541 u_matmul_axi_slave/crc32_word_next_return1[1]
|
|
r u_matmul_axi_slave/crc_reg[12]_i_39/I4
|
|
LUT6 (Prop_lut6_I4_O) 0.124 5.665 r u_matmul_axi_slave/crc_reg[12]_i_39/O
|
|
net (fo=10, unplaced) 0.945 6.610 u_matmul_axi_slave/crc32_word_next0_return10[5]
|
|
r u_matmul_axi_slave/crc_reg[12]_i_22/I1
|
|
LUT5 (Prop_lut5_I1_O) 0.124 6.734 r u_matmul_axi_slave/crc_reg[12]_i_22/O
|
|
net (fo=14, unplaced) 0.953 7.687 u_matmul_axi_slave/crc32_word_next0_return7[7]
|
|
r u_matmul_axi_slave/crc_reg[12]_i_55/I1
|
|
LUT4 (Prop_lut4_I1_O) 0.124 7.811 r u_matmul_axi_slave/crc_reg[12]_i_55/O
|
|
net (fo=1, unplaced) 0.902 8.713 u_matmul_axi_slave/crc32_word_next0_return6[21]
|
|
r u_matmul_axi_slave/crc_reg[12]_i_27/I0
|
|
LUT6 (Prop_lut6_I0_O) 0.124 8.837 r u_matmul_axi_slave/crc_reg[12]_i_27/O
|
|
net (fo=1, unplaced) 1.111 9.948 u_matmul_axi_slave/p_0_in11_in[4]
|
|
r u_matmul_axi_slave/crc_reg[12]_i_11/I0
|
|
LUT5 (Prop_lut5_I0_O) 0.124 10.072 r u_matmul_axi_slave/crc_reg[12]_i_11/O
|
|
net (fo=9, unplaced) 0.490 10.562 u_matmul_axi_slave/crc_reg[12]_i_11_n_0
|
|
r u_matmul_axi_slave/crc_reg[30]_i_6/I3
|
|
LUT4 (Prop_lut4_I3_O) 0.124 10.686 r u_matmul_axi_slave/crc_reg[30]_i_6/O
|
|
net (fo=12, unplaced) 0.950 11.636 u_matmul_axi_slave/crc32_word_next1_return7[2]
|
|
r u_matmul_axi_slave/crc_reg[9]_i_2/I2
|
|
LUT5 (Prop_lut5_I2_O) 0.150 11.786 r u_matmul_axi_slave/crc_reg[9]_i_2/O
|
|
net (fo=14, unplaced) 0.953 12.739 u_matmul_axi_slave/crc32_word_next1_return4[3]
|
|
r u_matmul_axi_slave/crc_reg[14]_i_2/I0
|
|
LUT3 (Prop_lut3_I0_O) 0.124 12.863 r u_matmul_axi_slave/crc_reg[14]_i_2/O
|
|
net (fo=2, unplaced) 0.676 13.539 u_matmul_axi_slave/crc_reg[14]_i_2_n_0
|
|
r u_matmul_axi_slave/crc_reg[14]_i_1/I0
|
|
LUT6 (Prop_lut6_I0_O) 0.124 13.663 r u_matmul_axi_slave/crc_reg[14]_i_1/O
|
|
net (fo=1, unplaced) 0.000 13.663 u_matmul_axi_slave/crc32_word_next1_return[14]
|
|
FDSE r u_matmul_axi_slave/crc_reg_reg[14]/D
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock sys_clk rise edge) 20.000 20.000 r
|
|
K21 0.000 20.000 r clk (IN)
|
|
net (fo=0) 0.000 20.000 pll_clk.u_clk_pll/inst/clk_in1
|
|
K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I
|
|
K21 IBUF (Prop_ibuf_I_O) 1.393 21.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O
|
|
net (fo=1, unplaced) 0.439 21.832 pll_clk.u_clk_pll/inst/clk_in1_clk_pll
|
|
r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1
|
|
PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1)
|
|
-6.040 15.792 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1
|
|
net (fo=1, unplaced) 0.760 16.552 pll_clk.u_clk_pll/inst/sys_clk_clk_pll
|
|
r pll_clk.u_clk_pll/inst/clkout2_buf/I
|
|
BUFG (Prop_bufg_I_O) 0.091 16.643 r pll_clk.u_clk_pll/inst/clkout2_buf/O
|
|
net (fo=10994, unplaced) 0.655 17.297 u_matmul_axi_slave/sys_clk
|
|
FDSE r u_matmul_axi_slave/crc_reg_reg[14]/C
|
|
clock pessimism -0.468 16.830
|
|
clock uncertainty -0.071 16.759
|
|
FDSE (Setup_fdse_C_D) 0.029 16.788 u_matmul_axi_slave/crc_reg_reg[14]
|
|
-------------------------------------------------------------------
|
|
required time 16.788
|
|
arrival time -13.663
|
|
-------------------------------------------------------------------
|
|
slack 3.125
|
|
|
|
Slack (MET) : 3.224ns (required time - arrival time)
|
|
Source: u_matmul_axi_slave/mult_inst[0].u_mult/p_reg[1]/C
|
|
(rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Destination: u_matmul_axi_slave/crc_reg_reg[12]/D
|
|
(rising edge-triggered cell FDSE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Path Group: sys_clk
|
|
Path Type: Setup (Max at Slow Process Corner)
|
|
Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns)
|
|
Data Path Delay: 16.589ns (logic 4.418ns (26.632%) route 12.171ns (73.368%))
|
|
Logic Levels: 18 (CARRY4=3 LUT2=2 LUT4=2 LUT5=3 LUT6=8)
|
|
Clock Path Skew: -0.145ns (DCD - SCD + CPR)
|
|
Destination Clock Delay (DCD): -2.703ns = ( 17.297 - 20.000 )
|
|
Source Clock Delay (SCD): -3.025ns
|
|
Clock Pessimism Removal (CPR): -0.468ns
|
|
Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Discrete Jitter (DJ): 0.122ns
|
|
Phase Error (PE): 0.000ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock sys_clk rise edge) 0.000 0.000 r
|
|
K21 0.000 0.000 r clk (IN)
|
|
net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1
|
|
K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I
|
|
K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O
|
|
net (fo=1, unplaced) 0.584 2.047 pll_clk.u_clk_pll/inst/clk_in1_clk_pll
|
|
r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1
|
|
PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1)
|
|
-6.768 -4.721 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1
|
|
net (fo=1, unplaced) 0.800 -3.921 pll_clk.u_clk_pll/inst/sys_clk_clk_pll
|
|
r pll_clk.u_clk_pll/inst/clkout2_buf/I
|
|
BUFG (Prop_bufg_I_O) 0.096 -3.825 r pll_clk.u_clk_pll/inst/clkout2_buf/O
|
|
net (fo=10994, unplaced) 0.800 -3.025 u_matmul_axi_slave/mult_inst[0].u_mult/sys_clk
|
|
FDRE r u_matmul_axi_slave/mult_inst[0].u_mult/p_reg[1]/C
|
|
------------------------------------------------------------------- -------------------
|
|
FDRE (Prop_fdre_C_Q) 0.456 -2.569 r u_matmul_axi_slave/mult_inst[0].u_mult/p_reg[1]/Q
|
|
net (fo=2, unplaced) 0.481 -2.088 u_matmul_axi_slave/mult_inst[0].u_mult/mult_p[0]_0[1]
|
|
r u_matmul_axi_slave/mult_inst[0].u_mult/b1_c_reg_r1_0_15_0_5_i_20/I0
|
|
LUT2 (Prop_lut2_I0_O) 0.295 -1.793 r u_matmul_axi_slave/mult_inst[0].u_mult/b1_c_reg_r1_0_15_0_5_i_20/O
|
|
net (fo=1, unplaced) 0.000 -1.793 u_matmul_axi_slave/mult_inst[0].u_mult/b1_c_reg_r1_0_15_0_5_i_20_n_0
|
|
r u_matmul_axi_slave/mult_inst[0].u_mult/b1_c_reg_r1_0_15_0_5_i_8/S[1]
|
|
CARRY4 (Prop_carry4_S[1]_CO[3])
|
|
0.550 -1.243 r u_matmul_axi_slave/mult_inst[0].u_mult/b1_c_reg_r1_0_15_0_5_i_8/CO[3]
|
|
net (fo=1, unplaced) 0.009 -1.234 u_matmul_axi_slave/mult_inst[0].u_mult/b1_c_reg_r1_0_15_0_5_i_8_n_0
|
|
r u_matmul_axi_slave/mult_inst[0].u_mult/b1_c_reg_r1_0_15_0_5_i_13/CI
|
|
CARRY4 (Prop_carry4_CI_O[1])
|
|
0.348 -0.886 r u_matmul_axi_slave/mult_inst[0].u_mult/b1_c_reg_r1_0_15_0_5_i_13/O[1]
|
|
net (fo=2, unplaced) 0.622 -0.264 u_matmul_axi_slave/calc_c_result02_out[5]
|
|
r u_matmul_axi_slave/b1_c_reg_r1_0_15_0_5_i_16/I0
|
|
LUT2 (Prop_lut2_I0_O) 0.306 0.042 r u_matmul_axi_slave/b1_c_reg_r1_0_15_0_5_i_16/O
|
|
net (fo=1, unplaced) 0.000 0.042 u_matmul_axi_slave/b1_c_reg_r1_0_15_0_5_i_16_n_0
|
|
r u_matmul_axi_slave/b1_c_reg_r1_0_15_0_5_i_3/S[1]
|
|
CARRY4 (Prop_carry4_S[1]_O[3])
|
|
0.640 0.682 r u_matmul_axi_slave/b1_c_reg_r1_0_15_0_5_i_3/O[3]
|
|
net (fo=15, unplaced) 0.671 1.353 u_matmul_axi_slave/b1_c_reg_r1_0_15_0_5_i_3_n_4
|
|
r u_matmul_axi_slave/crc_reg[12]_i_91/I2
|
|
LUT6 (Prop_lut6_I2_O) 0.307 1.660 r u_matmul_axi_slave/crc_reg[12]_i_91/O
|
|
net (fo=3, unplaced) 0.920 2.580 u_matmul_axi_slave/crc_reg[12]_i_91_n_0
|
|
r u_matmul_axi_slave/crc_reg[12]_i_72/I3
|
|
LUT6 (Prop_lut6_I3_O) 0.124 2.704 r u_matmul_axi_slave/crc_reg[12]_i_72/O
|
|
net (fo=7, unplaced) 0.484 3.188 u_matmul_axi_slave/crc_reg[12]_i_72_n_0
|
|
r u_matmul_axi_slave/crc_reg[12]_i_64/I1
|
|
LUT6 (Prop_lut6_I1_O) 0.124 3.312 r u_matmul_axi_slave/crc_reg[12]_i_64/O
|
|
net (fo=11, unplaced) 0.948 4.260 u_matmul_axi_slave/crc32_word_next_return4[3]
|
|
r u_matmul_axi_slave/crc_reg[12]_i_52/I1
|
|
LUT6 (Prop_lut6_I1_O) 0.124 4.384 r u_matmul_axi_slave/crc_reg[12]_i_52/O
|
|
net (fo=11, unplaced) 1.157 5.541 u_matmul_axi_slave/crc32_word_next_return1[1]
|
|
r u_matmul_axi_slave/crc_reg[12]_i_39/I4
|
|
LUT6 (Prop_lut6_I4_O) 0.124 5.665 r u_matmul_axi_slave/crc_reg[12]_i_39/O
|
|
net (fo=10, unplaced) 0.945 6.610 u_matmul_axi_slave/crc32_word_next0_return10[5]
|
|
r u_matmul_axi_slave/crc_reg[12]_i_22/I1
|
|
LUT5 (Prop_lut5_I1_O) 0.124 6.734 r u_matmul_axi_slave/crc_reg[12]_i_22/O
|
|
net (fo=14, unplaced) 0.953 7.687 u_matmul_axi_slave/crc32_word_next0_return7[7]
|
|
r u_matmul_axi_slave/crc_reg[12]_i_55/I1
|
|
LUT4 (Prop_lut4_I1_O) 0.124 7.811 r u_matmul_axi_slave/crc_reg[12]_i_55/O
|
|
net (fo=1, unplaced) 0.902 8.713 u_matmul_axi_slave/crc32_word_next0_return6[21]
|
|
r u_matmul_axi_slave/crc_reg[12]_i_27/I0
|
|
LUT6 (Prop_lut6_I0_O) 0.124 8.837 r u_matmul_axi_slave/crc_reg[12]_i_27/O
|
|
net (fo=1, unplaced) 1.111 9.948 u_matmul_axi_slave/p_0_in11_in[4]
|
|
r u_matmul_axi_slave/crc_reg[12]_i_11/I0
|
|
LUT5 (Prop_lut5_I0_O) 0.124 10.072 r u_matmul_axi_slave/crc_reg[12]_i_11/O
|
|
net (fo=9, unplaced) 0.460 10.532 u_matmul_axi_slave/crc_reg[12]_i_11_n_0
|
|
r u_matmul_axi_slave/crc_reg[28]_i_4/I2
|
|
LUT4 (Prop_lut4_I2_O) 0.124 10.656 r u_matmul_axi_slave/crc_reg[28]_i_4/O
|
|
net (fo=1, unplaced) 0.902 11.558 u_matmul_axi_slave/crc32_word_next1_return9[21]
|
|
r u_matmul_axi_slave/crc_reg[28]_i_3/I0
|
|
LUT6 (Prop_lut6_I0_O) 0.124 11.682 r u_matmul_axi_slave/crc_reg[28]_i_3/O
|
|
net (fo=3, unplaced) 1.129 12.811 u_matmul_axi_slave/crc_reg[28]_i_3_n_0
|
|
r u_matmul_axi_slave/crc_reg[27]_i_3/I0
|
|
LUT5 (Prop_lut5_I0_O) 0.152 12.963 r u_matmul_axi_slave/crc_reg[27]_i_3/O
|
|
net (fo=5, unplaced) 0.477 13.440 u_matmul_axi_slave/crc32_word_next1_return1[4]
|
|
r u_matmul_axi_slave/crc_reg[12]_i_1/I5
|
|
LUT6 (Prop_lut6_I5_O) 0.124 13.564 r u_matmul_axi_slave/crc_reg[12]_i_1/O
|
|
net (fo=1, unplaced) 0.000 13.564 u_matmul_axi_slave/crc32_word_next1_return[12]
|
|
FDSE r u_matmul_axi_slave/crc_reg_reg[12]/D
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock sys_clk rise edge) 20.000 20.000 r
|
|
K21 0.000 20.000 r clk (IN)
|
|
net (fo=0) 0.000 20.000 pll_clk.u_clk_pll/inst/clk_in1
|
|
K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I
|
|
K21 IBUF (Prop_ibuf_I_O) 1.393 21.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O
|
|
net (fo=1, unplaced) 0.439 21.832 pll_clk.u_clk_pll/inst/clk_in1_clk_pll
|
|
r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1
|
|
PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1)
|
|
-6.040 15.792 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1
|
|
net (fo=1, unplaced) 0.760 16.552 pll_clk.u_clk_pll/inst/sys_clk_clk_pll
|
|
r pll_clk.u_clk_pll/inst/clkout2_buf/I
|
|
BUFG (Prop_bufg_I_O) 0.091 16.643 r pll_clk.u_clk_pll/inst/clkout2_buf/O
|
|
net (fo=10994, unplaced) 0.655 17.297 u_matmul_axi_slave/sys_clk
|
|
FDSE r u_matmul_axi_slave/crc_reg_reg[12]/C
|
|
clock pessimism -0.468 16.830
|
|
clock uncertainty -0.071 16.759
|
|
FDSE (Setup_fdse_C_D) 0.029 16.788 u_matmul_axi_slave/crc_reg_reg[12]
|
|
-------------------------------------------------------------------
|
|
required time 16.788
|
|
arrival time -13.564
|
|
-------------------------------------------------------------------
|
|
slack 3.224
|
|
|
|
Slack (MET) : 3.293ns (required time - arrival time)
|
|
Source: u_matmul_axi_slave/mult_inst[0].u_mult/p_reg[1]/C
|
|
(rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Destination: u_matmul_axi_slave/crc_reg_reg[8]/D
|
|
(rising edge-triggered cell FDSE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Path Group: sys_clk
|
|
Path Type: Setup (Max at Slow Process Corner)
|
|
Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns)
|
|
Data Path Delay: 16.520ns (logic 4.418ns (26.743%) route 12.102ns (73.257%))
|
|
Logic Levels: 18 (CARRY4=3 LUT2=2 LUT4=2 LUT5=3 LUT6=8)
|
|
Clock Path Skew: -0.145ns (DCD - SCD + CPR)
|
|
Destination Clock Delay (DCD): -2.703ns = ( 17.297 - 20.000 )
|
|
Source Clock Delay (SCD): -3.025ns
|
|
Clock Pessimism Removal (CPR): -0.468ns
|
|
Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Discrete Jitter (DJ): 0.122ns
|
|
Phase Error (PE): 0.000ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock sys_clk rise edge) 0.000 0.000 r
|
|
K21 0.000 0.000 r clk (IN)
|
|
net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1
|
|
K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I
|
|
K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O
|
|
net (fo=1, unplaced) 0.584 2.047 pll_clk.u_clk_pll/inst/clk_in1_clk_pll
|
|
r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1
|
|
PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1)
|
|
-6.768 -4.721 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1
|
|
net (fo=1, unplaced) 0.800 -3.921 pll_clk.u_clk_pll/inst/sys_clk_clk_pll
|
|
r pll_clk.u_clk_pll/inst/clkout2_buf/I
|
|
BUFG (Prop_bufg_I_O) 0.096 -3.825 r pll_clk.u_clk_pll/inst/clkout2_buf/O
|
|
net (fo=10994, unplaced) 0.800 -3.025 u_matmul_axi_slave/mult_inst[0].u_mult/sys_clk
|
|
FDRE r u_matmul_axi_slave/mult_inst[0].u_mult/p_reg[1]/C
|
|
------------------------------------------------------------------- -------------------
|
|
FDRE (Prop_fdre_C_Q) 0.456 -2.569 r u_matmul_axi_slave/mult_inst[0].u_mult/p_reg[1]/Q
|
|
net (fo=2, unplaced) 0.481 -2.088 u_matmul_axi_slave/mult_inst[0].u_mult/mult_p[0]_0[1]
|
|
r u_matmul_axi_slave/mult_inst[0].u_mult/b1_c_reg_r1_0_15_0_5_i_20/I0
|
|
LUT2 (Prop_lut2_I0_O) 0.295 -1.793 r u_matmul_axi_slave/mult_inst[0].u_mult/b1_c_reg_r1_0_15_0_5_i_20/O
|
|
net (fo=1, unplaced) 0.000 -1.793 u_matmul_axi_slave/mult_inst[0].u_mult/b1_c_reg_r1_0_15_0_5_i_20_n_0
|
|
r u_matmul_axi_slave/mult_inst[0].u_mult/b1_c_reg_r1_0_15_0_5_i_8/S[1]
|
|
CARRY4 (Prop_carry4_S[1]_CO[3])
|
|
0.550 -1.243 r u_matmul_axi_slave/mult_inst[0].u_mult/b1_c_reg_r1_0_15_0_5_i_8/CO[3]
|
|
net (fo=1, unplaced) 0.009 -1.234 u_matmul_axi_slave/mult_inst[0].u_mult/b1_c_reg_r1_0_15_0_5_i_8_n_0
|
|
r u_matmul_axi_slave/mult_inst[0].u_mult/b1_c_reg_r1_0_15_0_5_i_13/CI
|
|
CARRY4 (Prop_carry4_CI_O[1])
|
|
0.348 -0.886 r u_matmul_axi_slave/mult_inst[0].u_mult/b1_c_reg_r1_0_15_0_5_i_13/O[1]
|
|
net (fo=2, unplaced) 0.622 -0.264 u_matmul_axi_slave/calc_c_result02_out[5]
|
|
r u_matmul_axi_slave/b1_c_reg_r1_0_15_0_5_i_16/I0
|
|
LUT2 (Prop_lut2_I0_O) 0.306 0.042 r u_matmul_axi_slave/b1_c_reg_r1_0_15_0_5_i_16/O
|
|
net (fo=1, unplaced) 0.000 0.042 u_matmul_axi_slave/b1_c_reg_r1_0_15_0_5_i_16_n_0
|
|
r u_matmul_axi_slave/b1_c_reg_r1_0_15_0_5_i_3/S[1]
|
|
CARRY4 (Prop_carry4_S[1]_O[3])
|
|
0.640 0.682 r u_matmul_axi_slave/b1_c_reg_r1_0_15_0_5_i_3/O[3]
|
|
net (fo=15, unplaced) 0.671 1.353 u_matmul_axi_slave/b1_c_reg_r1_0_15_0_5_i_3_n_4
|
|
r u_matmul_axi_slave/crc_reg[12]_i_91/I2
|
|
LUT6 (Prop_lut6_I2_O) 0.307 1.660 r u_matmul_axi_slave/crc_reg[12]_i_91/O
|
|
net (fo=3, unplaced) 0.920 2.580 u_matmul_axi_slave/crc_reg[12]_i_91_n_0
|
|
r u_matmul_axi_slave/crc_reg[12]_i_72/I3
|
|
LUT6 (Prop_lut6_I3_O) 0.124 2.704 r u_matmul_axi_slave/crc_reg[12]_i_72/O
|
|
net (fo=7, unplaced) 0.484 3.188 u_matmul_axi_slave/crc_reg[12]_i_72_n_0
|
|
r u_matmul_axi_slave/crc_reg[12]_i_64/I1
|
|
LUT6 (Prop_lut6_I1_O) 0.124 3.312 r u_matmul_axi_slave/crc_reg[12]_i_64/O
|
|
net (fo=11, unplaced) 0.948 4.260 u_matmul_axi_slave/crc32_word_next_return4[3]
|
|
r u_matmul_axi_slave/crc_reg[12]_i_52/I1
|
|
LUT6 (Prop_lut6_I1_O) 0.124 4.384 r u_matmul_axi_slave/crc_reg[12]_i_52/O
|
|
net (fo=11, unplaced) 1.157 5.541 u_matmul_axi_slave/crc32_word_next_return1[1]
|
|
r u_matmul_axi_slave/crc_reg[12]_i_39/I4
|
|
LUT6 (Prop_lut6_I4_O) 0.124 5.665 r u_matmul_axi_slave/crc_reg[12]_i_39/O
|
|
net (fo=10, unplaced) 0.945 6.610 u_matmul_axi_slave/crc32_word_next0_return10[5]
|
|
r u_matmul_axi_slave/crc_reg[12]_i_22/I1
|
|
LUT5 (Prop_lut5_I1_O) 0.124 6.734 r u_matmul_axi_slave/crc_reg[12]_i_22/O
|
|
net (fo=14, unplaced) 0.953 7.687 u_matmul_axi_slave/crc32_word_next0_return7[7]
|
|
r u_matmul_axi_slave/crc_reg[20]_i_16/I2
|
|
LUT6 (Prop_lut6_I2_O) 0.124 7.811 r u_matmul_axi_slave/crc_reg[20]_i_16/O
|
|
net (fo=11, unplaced) 0.948 8.759 u_matmul_axi_slave/crc32_word_next0_return4[5]
|
|
r u_matmul_axi_slave/crc_reg[31]_i_18/I1
|
|
LUT5 (Prop_lut5_I1_O) 0.124 8.883 r u_matmul_axi_slave/crc_reg[31]_i_18/O
|
|
net (fo=16, unplaced) 0.956 9.839 u_matmul_axi_slave/crc32_word_next0_return1[7]
|
|
r u_matmul_axi_slave/crc_reg[20]_i_14/I1
|
|
LUT4 (Prop_lut4_I1_O) 0.124 9.963 r u_matmul_axi_slave/crc_reg[20]_i_14/O
|
|
net (fo=1, unplaced) 0.902 10.865 u_matmul_axi_slave/crc32_word_next0_return0[21]
|
|
r u_matmul_axi_slave/crc_reg[20]_i_6/I0
|
|
LUT6 (Prop_lut6_I0_O) 0.124 10.989 r u_matmul_axi_slave/crc_reg[20]_i_6/O
|
|
net (fo=2, unplaced) 1.122 12.111 u_matmul_axi_slave/p_0_in0_in[4]
|
|
r u_matmul_axi_slave/crc_reg[30]_i_9/I0
|
|
LUT5 (Prop_lut5_I0_O) 0.152 12.263 r u_matmul_axi_slave/crc_reg[30]_i_9/O
|
|
net (fo=7, unplaced) 0.484 12.747 u_matmul_axi_slave/crc32_word_next1_return4[4]
|
|
r u_matmul_axi_slave/crc_reg[30]_i_3/I5
|
|
LUT6 (Prop_lut6_I5_O) 0.124 12.871 r u_matmul_axi_slave/crc_reg[30]_i_3/O
|
|
net (fo=14, unplaced) 0.500 13.371 u_matmul_axi_slave/crc32_word_next1_return1[6]
|
|
r u_matmul_axi_slave/crc_reg[8]_i_1/I3
|
|
LUT4 (Prop_lut4_I3_O) 0.124 13.495 r u_matmul_axi_slave/crc_reg[8]_i_1/O
|
|
net (fo=1, unplaced) 0.000 13.495 u_matmul_axi_slave/crc32_word_next1_return[8]
|
|
FDSE r u_matmul_axi_slave/crc_reg_reg[8]/D
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock sys_clk rise edge) 20.000 20.000 r
|
|
K21 0.000 20.000 r clk (IN)
|
|
net (fo=0) 0.000 20.000 pll_clk.u_clk_pll/inst/clk_in1
|
|
K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I
|
|
K21 IBUF (Prop_ibuf_I_O) 1.393 21.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O
|
|
net (fo=1, unplaced) 0.439 21.832 pll_clk.u_clk_pll/inst/clk_in1_clk_pll
|
|
r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1
|
|
PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1)
|
|
-6.040 15.792 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1
|
|
net (fo=1, unplaced) 0.760 16.552 pll_clk.u_clk_pll/inst/sys_clk_clk_pll
|
|
r pll_clk.u_clk_pll/inst/clkout2_buf/I
|
|
BUFG (Prop_bufg_I_O) 0.091 16.643 r pll_clk.u_clk_pll/inst/clkout2_buf/O
|
|
net (fo=10994, unplaced) 0.655 17.297 u_matmul_axi_slave/sys_clk
|
|
FDSE r u_matmul_axi_slave/crc_reg_reg[8]/C
|
|
clock pessimism -0.468 16.830
|
|
clock uncertainty -0.071 16.759
|
|
FDSE (Setup_fdse_C_D) 0.029 16.788 u_matmul_axi_slave/crc_reg_reg[8]
|
|
-------------------------------------------------------------------
|
|
required time 16.788
|
|
arrival time -13.495
|
|
-------------------------------------------------------------------
|
|
slack 3.293
|
|
|
|
Slack (MET) : 3.392ns (required time - arrival time)
|
|
Source: u_matmul_axi_slave/mult_inst[0].u_mult/p_reg[1]/C
|
|
(rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Destination: u_matmul_axi_slave/crc_reg_reg[31]/D
|
|
(rising edge-triggered cell FDSE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Path Group: sys_clk
|
|
Path Type: Setup (Max at Slow Process Corner)
|
|
Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns)
|
|
Data Path Delay: 16.421ns (logic 4.390ns (26.734%) route 12.031ns (73.266%))
|
|
Logic Levels: 18 (CARRY4=3 LUT2=3 LUT4=1 LUT5=3 LUT6=8)
|
|
Clock Path Skew: -0.145ns (DCD - SCD + CPR)
|
|
Destination Clock Delay (DCD): -2.703ns = ( 17.297 - 20.000 )
|
|
Source Clock Delay (SCD): -3.025ns
|
|
Clock Pessimism Removal (CPR): -0.468ns
|
|
Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Discrete Jitter (DJ): 0.122ns
|
|
Phase Error (PE): 0.000ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock sys_clk rise edge) 0.000 0.000 r
|
|
K21 0.000 0.000 r clk (IN)
|
|
net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1
|
|
K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I
|
|
K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O
|
|
net (fo=1, unplaced) 0.584 2.047 pll_clk.u_clk_pll/inst/clk_in1_clk_pll
|
|
r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1
|
|
PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1)
|
|
-6.768 -4.721 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1
|
|
net (fo=1, unplaced) 0.800 -3.921 pll_clk.u_clk_pll/inst/sys_clk_clk_pll
|
|
r pll_clk.u_clk_pll/inst/clkout2_buf/I
|
|
BUFG (Prop_bufg_I_O) 0.096 -3.825 r pll_clk.u_clk_pll/inst/clkout2_buf/O
|
|
net (fo=10994, unplaced) 0.800 -3.025 u_matmul_axi_slave/mult_inst[0].u_mult/sys_clk
|
|
FDRE r u_matmul_axi_slave/mult_inst[0].u_mult/p_reg[1]/C
|
|
------------------------------------------------------------------- -------------------
|
|
FDRE (Prop_fdre_C_Q) 0.456 -2.569 r u_matmul_axi_slave/mult_inst[0].u_mult/p_reg[1]/Q
|
|
net (fo=2, unplaced) 0.481 -2.088 u_matmul_axi_slave/mult_inst[0].u_mult/mult_p[0]_0[1]
|
|
r u_matmul_axi_slave/mult_inst[0].u_mult/b1_c_reg_r1_0_15_0_5_i_20/I0
|
|
LUT2 (Prop_lut2_I0_O) 0.295 -1.793 r u_matmul_axi_slave/mult_inst[0].u_mult/b1_c_reg_r1_0_15_0_5_i_20/O
|
|
net (fo=1, unplaced) 0.000 -1.793 u_matmul_axi_slave/mult_inst[0].u_mult/b1_c_reg_r1_0_15_0_5_i_20_n_0
|
|
r u_matmul_axi_slave/mult_inst[0].u_mult/b1_c_reg_r1_0_15_0_5_i_8/S[1]
|
|
CARRY4 (Prop_carry4_S[1]_CO[3])
|
|
0.550 -1.243 r u_matmul_axi_slave/mult_inst[0].u_mult/b1_c_reg_r1_0_15_0_5_i_8/CO[3]
|
|
net (fo=1, unplaced) 0.009 -1.234 u_matmul_axi_slave/mult_inst[0].u_mult/b1_c_reg_r1_0_15_0_5_i_8_n_0
|
|
r u_matmul_axi_slave/mult_inst[0].u_mult/b1_c_reg_r1_0_15_0_5_i_13/CI
|
|
CARRY4 (Prop_carry4_CI_O[1])
|
|
0.348 -0.886 r u_matmul_axi_slave/mult_inst[0].u_mult/b1_c_reg_r1_0_15_0_5_i_13/O[1]
|
|
net (fo=2, unplaced) 0.622 -0.264 u_matmul_axi_slave/calc_c_result02_out[5]
|
|
r u_matmul_axi_slave/b1_c_reg_r1_0_15_0_5_i_16/I0
|
|
LUT2 (Prop_lut2_I0_O) 0.306 0.042 r u_matmul_axi_slave/b1_c_reg_r1_0_15_0_5_i_16/O
|
|
net (fo=1, unplaced) 0.000 0.042 u_matmul_axi_slave/b1_c_reg_r1_0_15_0_5_i_16_n_0
|
|
r u_matmul_axi_slave/b1_c_reg_r1_0_15_0_5_i_3/S[1]
|
|
CARRY4 (Prop_carry4_S[1]_O[3])
|
|
0.640 0.682 r u_matmul_axi_slave/b1_c_reg_r1_0_15_0_5_i_3/O[3]
|
|
net (fo=15, unplaced) 0.671 1.353 u_matmul_axi_slave/b1_c_reg_r1_0_15_0_5_i_3_n_4
|
|
r u_matmul_axi_slave/crc_reg[12]_i_91/I2
|
|
LUT6 (Prop_lut6_I2_O) 0.307 1.660 r u_matmul_axi_slave/crc_reg[12]_i_91/O
|
|
net (fo=3, unplaced) 0.920 2.580 u_matmul_axi_slave/crc_reg[12]_i_91_n_0
|
|
r u_matmul_axi_slave/crc_reg[12]_i_72/I3
|
|
LUT6 (Prop_lut6_I3_O) 0.124 2.704 r u_matmul_axi_slave/crc_reg[12]_i_72/O
|
|
net (fo=7, unplaced) 0.484 3.188 u_matmul_axi_slave/crc_reg[12]_i_72_n_0
|
|
r u_matmul_axi_slave/crc_reg[12]_i_64/I1
|
|
LUT6 (Prop_lut6_I1_O) 0.124 3.312 r u_matmul_axi_slave/crc_reg[12]_i_64/O
|
|
net (fo=11, unplaced) 0.948 4.260 u_matmul_axi_slave/crc32_word_next_return4[3]
|
|
r u_matmul_axi_slave/crc_reg[12]_i_52/I1
|
|
LUT6 (Prop_lut6_I1_O) 0.124 4.384 r u_matmul_axi_slave/crc_reg[12]_i_52/O
|
|
net (fo=11, unplaced) 1.157 5.541 u_matmul_axi_slave/crc32_word_next_return1[1]
|
|
r u_matmul_axi_slave/crc_reg[12]_i_39/I4
|
|
LUT6 (Prop_lut6_I4_O) 0.124 5.665 r u_matmul_axi_slave/crc_reg[12]_i_39/O
|
|
net (fo=10, unplaced) 0.945 6.610 u_matmul_axi_slave/crc32_word_next0_return10[5]
|
|
r u_matmul_axi_slave/crc_reg[12]_i_22/I1
|
|
LUT5 (Prop_lut5_I1_O) 0.124 6.734 r u_matmul_axi_slave/crc_reg[12]_i_22/O
|
|
net (fo=14, unplaced) 0.953 7.687 u_matmul_axi_slave/crc32_word_next0_return7[7]
|
|
r u_matmul_axi_slave/crc_reg[12]_i_55/I1
|
|
LUT4 (Prop_lut4_I1_O) 0.124 7.811 r u_matmul_axi_slave/crc_reg[12]_i_55/O
|
|
net (fo=1, unplaced) 0.902 8.713 u_matmul_axi_slave/crc32_word_next0_return6[21]
|
|
r u_matmul_axi_slave/crc_reg[12]_i_27/I0
|
|
LUT6 (Prop_lut6_I0_O) 0.124 8.837 r u_matmul_axi_slave/crc_reg[12]_i_27/O
|
|
net (fo=1, unplaced) 1.111 9.948 u_matmul_axi_slave/p_0_in11_in[4]
|
|
r u_matmul_axi_slave/crc_reg[12]_i_11/I0
|
|
LUT5 (Prop_lut5_I0_O) 0.124 10.072 r u_matmul_axi_slave/crc_reg[12]_i_11/O
|
|
net (fo=9, unplaced) 0.943 11.015 u_matmul_axi_slave/crc_reg[12]_i_11_n_0
|
|
r u_matmul_axi_slave/crc_reg[12]_i_4/I2
|
|
LUT5 (Prop_lut5_I2_O) 0.124 11.139 r u_matmul_axi_slave/crc_reg[12]_i_4/O
|
|
net (fo=11, unplaced) 0.465 11.604 u_matmul_axi_slave/crc32_word_next1_return7[5]
|
|
r u_matmul_axi_slave/crc_reg[20]_i_4/I4
|
|
LUT6 (Prop_lut6_I4_O) 0.124 11.728 r u_matmul_axi_slave/crc_reg[20]_i_4/O
|
|
net (fo=14, unplaced) 0.953 12.681 u_matmul_axi_slave/crc32_word_next1_return4[6]
|
|
r u_matmul_axi_slave/crc_reg[31]_i_5/I3
|
|
LUT6 (Prop_lut6_I3_O) 0.124 12.805 r u_matmul_axi_slave/crc_reg[31]_i_5/O
|
|
net (fo=12, unplaced) 0.467 13.272 u_matmul_axi_slave/crc32_word_next1_return1[7]
|
|
r u_matmul_axi_slave/crc_reg[31]_i_2/I0
|
|
LUT2 (Prop_lut2_I0_O) 0.124 13.396 r u_matmul_axi_slave/crc_reg[31]_i_2/O
|
|
net (fo=1, unplaced) 0.000 13.396 u_matmul_axi_slave/crc32_word_next1_return0[29]
|
|
FDSE r u_matmul_axi_slave/crc_reg_reg[31]/D
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock sys_clk rise edge) 20.000 20.000 r
|
|
K21 0.000 20.000 r clk (IN)
|
|
net (fo=0) 0.000 20.000 pll_clk.u_clk_pll/inst/clk_in1
|
|
K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I
|
|
K21 IBUF (Prop_ibuf_I_O) 1.393 21.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O
|
|
net (fo=1, unplaced) 0.439 21.832 pll_clk.u_clk_pll/inst/clk_in1_clk_pll
|
|
r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1
|
|
PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1)
|
|
-6.040 15.792 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1
|
|
net (fo=1, unplaced) 0.760 16.552 pll_clk.u_clk_pll/inst/sys_clk_clk_pll
|
|
r pll_clk.u_clk_pll/inst/clkout2_buf/I
|
|
BUFG (Prop_bufg_I_O) 0.091 16.643 r pll_clk.u_clk_pll/inst/clkout2_buf/O
|
|
net (fo=10994, unplaced) 0.655 17.297 u_matmul_axi_slave/sys_clk
|
|
FDSE r u_matmul_axi_slave/crc_reg_reg[31]/C
|
|
clock pessimism -0.468 16.830
|
|
clock uncertainty -0.071 16.759
|
|
FDSE (Setup_fdse_C_D) 0.029 16.788 u_matmul_axi_slave/crc_reg_reg[31]
|
|
-------------------------------------------------------------------
|
|
required time 16.788
|
|
arrival time -13.396
|
|
-------------------------------------------------------------------
|
|
slack 3.392
|
|
|
|
Slack (MET) : 3.394ns (required time - arrival time)
|
|
Source: u_matmul_axi_slave/mult_inst[0].u_mult/p_reg[1]/C
|
|
(rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Destination: u_matmul_axi_slave/crc_reg_reg[0]/D
|
|
(rising edge-triggered cell FDSE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Path Group: sys_clk
|
|
Path Type: Setup (Max at Slow Process Corner)
|
|
Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns)
|
|
Data Path Delay: 16.419ns (logic 4.384ns (26.701%) route 12.035ns (73.299%))
|
|
Logic Levels: 18 (CARRY4=3 LUT2=3 LUT3=1 LUT4=1 LUT5=3 LUT6=7)
|
|
Clock Path Skew: -0.145ns (DCD - SCD + CPR)
|
|
Destination Clock Delay (DCD): -2.703ns = ( 17.297 - 20.000 )
|
|
Source Clock Delay (SCD): -3.025ns
|
|
Clock Pessimism Removal (CPR): -0.468ns
|
|
Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Discrete Jitter (DJ): 0.122ns
|
|
Phase Error (PE): 0.000ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock sys_clk rise edge) 0.000 0.000 r
|
|
K21 0.000 0.000 r clk (IN)
|
|
net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1
|
|
K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I
|
|
K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O
|
|
net (fo=1, unplaced) 0.584 2.047 pll_clk.u_clk_pll/inst/clk_in1_clk_pll
|
|
r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1
|
|
PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1)
|
|
-6.768 -4.721 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1
|
|
net (fo=1, unplaced) 0.800 -3.921 pll_clk.u_clk_pll/inst/sys_clk_clk_pll
|
|
r pll_clk.u_clk_pll/inst/clkout2_buf/I
|
|
BUFG (Prop_bufg_I_O) 0.096 -3.825 r pll_clk.u_clk_pll/inst/clkout2_buf/O
|
|
net (fo=10994, unplaced) 0.800 -3.025 u_matmul_axi_slave/mult_inst[0].u_mult/sys_clk
|
|
FDRE r u_matmul_axi_slave/mult_inst[0].u_mult/p_reg[1]/C
|
|
------------------------------------------------------------------- -------------------
|
|
FDRE (Prop_fdre_C_Q) 0.456 -2.569 r u_matmul_axi_slave/mult_inst[0].u_mult/p_reg[1]/Q
|
|
net (fo=2, unplaced) 0.481 -2.088 u_matmul_axi_slave/mult_inst[0].u_mult/mult_p[0]_0[1]
|
|
r u_matmul_axi_slave/mult_inst[0].u_mult/b1_c_reg_r1_0_15_0_5_i_20/I0
|
|
LUT2 (Prop_lut2_I0_O) 0.295 -1.793 r u_matmul_axi_slave/mult_inst[0].u_mult/b1_c_reg_r1_0_15_0_5_i_20/O
|
|
net (fo=1, unplaced) 0.000 -1.793 u_matmul_axi_slave/mult_inst[0].u_mult/b1_c_reg_r1_0_15_0_5_i_20_n_0
|
|
r u_matmul_axi_slave/mult_inst[0].u_mult/b1_c_reg_r1_0_15_0_5_i_8/S[1]
|
|
CARRY4 (Prop_carry4_S[1]_CO[3])
|
|
0.550 -1.243 r u_matmul_axi_slave/mult_inst[0].u_mult/b1_c_reg_r1_0_15_0_5_i_8/CO[3]
|
|
net (fo=1, unplaced) 0.009 -1.234 u_matmul_axi_slave/mult_inst[0].u_mult/b1_c_reg_r1_0_15_0_5_i_8_n_0
|
|
r u_matmul_axi_slave/mult_inst[0].u_mult/b1_c_reg_r1_0_15_0_5_i_13/CI
|
|
CARRY4 (Prop_carry4_CI_O[1])
|
|
0.348 -0.886 r u_matmul_axi_slave/mult_inst[0].u_mult/b1_c_reg_r1_0_15_0_5_i_13/O[1]
|
|
net (fo=2, unplaced) 0.622 -0.264 u_matmul_axi_slave/calc_c_result02_out[5]
|
|
r u_matmul_axi_slave/b1_c_reg_r1_0_15_0_5_i_16/I0
|
|
LUT2 (Prop_lut2_I0_O) 0.306 0.042 r u_matmul_axi_slave/b1_c_reg_r1_0_15_0_5_i_16/O
|
|
net (fo=1, unplaced) 0.000 0.042 u_matmul_axi_slave/b1_c_reg_r1_0_15_0_5_i_16_n_0
|
|
r u_matmul_axi_slave/b1_c_reg_r1_0_15_0_5_i_3/S[1]
|
|
CARRY4 (Prop_carry4_S[1]_O[3])
|
|
0.640 0.682 r u_matmul_axi_slave/b1_c_reg_r1_0_15_0_5_i_3/O[3]
|
|
net (fo=15, unplaced) 0.671 1.353 u_matmul_axi_slave/b1_c_reg_r1_0_15_0_5_i_3_n_4
|
|
r u_matmul_axi_slave/crc_reg[12]_i_91/I2
|
|
LUT6 (Prop_lut6_I2_O) 0.307 1.660 r u_matmul_axi_slave/crc_reg[12]_i_91/O
|
|
net (fo=3, unplaced) 0.920 2.580 u_matmul_axi_slave/crc_reg[12]_i_91_n_0
|
|
r u_matmul_axi_slave/crc_reg[12]_i_72/I3
|
|
LUT6 (Prop_lut6_I3_O) 0.124 2.704 r u_matmul_axi_slave/crc_reg[12]_i_72/O
|
|
net (fo=7, unplaced) 0.484 3.188 u_matmul_axi_slave/crc_reg[12]_i_72_n_0
|
|
r u_matmul_axi_slave/crc_reg[12]_i_64/I1
|
|
LUT6 (Prop_lut6_I1_O) 0.124 3.312 r u_matmul_axi_slave/crc_reg[12]_i_64/O
|
|
net (fo=11, unplaced) 0.948 4.260 u_matmul_axi_slave/crc32_word_next_return4[3]
|
|
r u_matmul_axi_slave/crc_reg[12]_i_52/I1
|
|
LUT6 (Prop_lut6_I1_O) 0.124 4.384 r u_matmul_axi_slave/crc_reg[12]_i_52/O
|
|
net (fo=11, unplaced) 1.157 5.541 u_matmul_axi_slave/crc32_word_next_return1[1]
|
|
r u_matmul_axi_slave/crc_reg[12]_i_39/I4
|
|
LUT6 (Prop_lut6_I4_O) 0.124 5.665 r u_matmul_axi_slave/crc_reg[12]_i_39/O
|
|
net (fo=10, unplaced) 0.945 6.610 u_matmul_axi_slave/crc32_word_next0_return10[5]
|
|
r u_matmul_axi_slave/crc_reg[12]_i_22/I1
|
|
LUT5 (Prop_lut5_I1_O) 0.124 6.734 r u_matmul_axi_slave/crc_reg[12]_i_22/O
|
|
net (fo=14, unplaced) 0.953 7.687 u_matmul_axi_slave/crc32_word_next0_return7[7]
|
|
r u_matmul_axi_slave/crc_reg[12]_i_55/I1
|
|
LUT4 (Prop_lut4_I1_O) 0.124 7.811 r u_matmul_axi_slave/crc_reg[12]_i_55/O
|
|
net (fo=1, unplaced) 0.902 8.713 u_matmul_axi_slave/crc32_word_next0_return6[21]
|
|
r u_matmul_axi_slave/crc_reg[12]_i_27/I0
|
|
LUT6 (Prop_lut6_I0_O) 0.124 8.837 r u_matmul_axi_slave/crc_reg[12]_i_27/O
|
|
net (fo=1, unplaced) 1.111 9.948 u_matmul_axi_slave/p_0_in11_in[4]
|
|
r u_matmul_axi_slave/crc_reg[12]_i_11/I0
|
|
LUT5 (Prop_lut5_I0_O) 0.124 10.072 r u_matmul_axi_slave/crc_reg[12]_i_11/O
|
|
net (fo=9, unplaced) 0.490 10.562 u_matmul_axi_slave/crc_reg[12]_i_11_n_0
|
|
r u_matmul_axi_slave/crc_reg[4]_i_4/I1
|
|
LUT2 (Prop_lut2_I1_O) 0.118 10.680 r u_matmul_axi_slave/crc_reg[4]_i_4/O
|
|
net (fo=5, unplaced) 0.930 11.610 u_matmul_axi_slave/crc_reg[4]_i_4_n_0
|
|
r u_matmul_axi_slave/crc_reg[26]_i_3/I3
|
|
LUT6 (Prop_lut6_I3_O) 0.124 11.734 r u_matmul_axi_slave/crc_reg[26]_i_3/O
|
|
net (fo=2, unplaced) 0.913 12.647 u_matmul_axi_slave/crc_reg[26]_i_3_n_0
|
|
r u_matmul_axi_slave/crc_reg[26]_i_2/I0
|
|
LUT3 (Prop_lut3_I0_O) 0.124 12.771 r u_matmul_axi_slave/crc_reg[26]_i_2/O
|
|
net (fo=13, unplaced) 0.499 13.270 u_matmul_axi_slave/crc32_word_next1_return1[2]
|
|
r u_matmul_axi_slave/crc_reg[0]_i_1/I4
|
|
LUT5 (Prop_lut5_I4_O) 0.124 13.394 r u_matmul_axi_slave/crc_reg[0]_i_1/O
|
|
net (fo=1, unplaced) 0.000 13.394 u_matmul_axi_slave/crc32_word_next1_return[0]
|
|
FDSE r u_matmul_axi_slave/crc_reg_reg[0]/D
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock sys_clk rise edge) 20.000 20.000 r
|
|
K21 0.000 20.000 r clk (IN)
|
|
net (fo=0) 0.000 20.000 pll_clk.u_clk_pll/inst/clk_in1
|
|
K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I
|
|
K21 IBUF (Prop_ibuf_I_O) 1.393 21.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O
|
|
net (fo=1, unplaced) 0.439 21.832 pll_clk.u_clk_pll/inst/clk_in1_clk_pll
|
|
r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1
|
|
PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1)
|
|
-6.040 15.792 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1
|
|
net (fo=1, unplaced) 0.760 16.552 pll_clk.u_clk_pll/inst/sys_clk_clk_pll
|
|
r pll_clk.u_clk_pll/inst/clkout2_buf/I
|
|
BUFG (Prop_bufg_I_O) 0.091 16.643 r pll_clk.u_clk_pll/inst/clkout2_buf/O
|
|
net (fo=10994, unplaced) 0.655 17.297 u_matmul_axi_slave/sys_clk
|
|
FDSE r u_matmul_axi_slave/crc_reg_reg[0]/C
|
|
clock pessimism -0.468 16.830
|
|
clock uncertainty -0.071 16.759
|
|
FDSE (Setup_fdse_C_D) 0.029 16.788 u_matmul_axi_slave/crc_reg_reg[0]
|
|
-------------------------------------------------------------------
|
|
required time 16.788
|
|
arrival time -13.394
|
|
-------------------------------------------------------------------
|
|
slack 3.394
|
|
|
|
Slack (MET) : 3.419ns (required time - arrival time)
|
|
Source: u_matmul_axi_slave/mult_inst[0].u_mult/p_reg[1]/C
|
|
(rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Destination: u_matmul_axi_slave/crc_reg_reg[1]/D
|
|
(rising edge-triggered cell FDSE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Path Group: sys_clk
|
|
Path Type: Setup (Max at Slow Process Corner)
|
|
Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns)
|
|
Data Path Delay: 16.394ns (logic 4.470ns (27.266%) route 11.924ns (72.734%))
|
|
Logic Levels: 18 (CARRY4=3 LUT2=2 LUT4=2 LUT5=5 LUT6=6)
|
|
Clock Path Skew: -0.145ns (DCD - SCD + CPR)
|
|
Destination Clock Delay (DCD): -2.703ns = ( 17.297 - 20.000 )
|
|
Source Clock Delay (SCD): -3.025ns
|
|
Clock Pessimism Removal (CPR): -0.468ns
|
|
Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Discrete Jitter (DJ): 0.122ns
|
|
Phase Error (PE): 0.000ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock sys_clk rise edge) 0.000 0.000 r
|
|
K21 0.000 0.000 r clk (IN)
|
|
net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1
|
|
K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I
|
|
K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O
|
|
net (fo=1, unplaced) 0.584 2.047 pll_clk.u_clk_pll/inst/clk_in1_clk_pll
|
|
r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1
|
|
PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1)
|
|
-6.768 -4.721 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1
|
|
net (fo=1, unplaced) 0.800 -3.921 pll_clk.u_clk_pll/inst/sys_clk_clk_pll
|
|
r pll_clk.u_clk_pll/inst/clkout2_buf/I
|
|
BUFG (Prop_bufg_I_O) 0.096 -3.825 r pll_clk.u_clk_pll/inst/clkout2_buf/O
|
|
net (fo=10994, unplaced) 0.800 -3.025 u_matmul_axi_slave/mult_inst[0].u_mult/sys_clk
|
|
FDRE r u_matmul_axi_slave/mult_inst[0].u_mult/p_reg[1]/C
|
|
------------------------------------------------------------------- -------------------
|
|
FDRE (Prop_fdre_C_Q) 0.456 -2.569 r u_matmul_axi_slave/mult_inst[0].u_mult/p_reg[1]/Q
|
|
net (fo=2, unplaced) 0.481 -2.088 u_matmul_axi_slave/mult_inst[0].u_mult/mult_p[0]_0[1]
|
|
r u_matmul_axi_slave/mult_inst[0].u_mult/b1_c_reg_r1_0_15_0_5_i_20/I0
|
|
LUT2 (Prop_lut2_I0_O) 0.295 -1.793 r u_matmul_axi_slave/mult_inst[0].u_mult/b1_c_reg_r1_0_15_0_5_i_20/O
|
|
net (fo=1, unplaced) 0.000 -1.793 u_matmul_axi_slave/mult_inst[0].u_mult/b1_c_reg_r1_0_15_0_5_i_20_n_0
|
|
r u_matmul_axi_slave/mult_inst[0].u_mult/b1_c_reg_r1_0_15_0_5_i_8/S[1]
|
|
CARRY4 (Prop_carry4_S[1]_CO[3])
|
|
0.550 -1.243 r u_matmul_axi_slave/mult_inst[0].u_mult/b1_c_reg_r1_0_15_0_5_i_8/CO[3]
|
|
net (fo=1, unplaced) 0.009 -1.234 u_matmul_axi_slave/mult_inst[0].u_mult/b1_c_reg_r1_0_15_0_5_i_8_n_0
|
|
r u_matmul_axi_slave/mult_inst[0].u_mult/b1_c_reg_r1_0_15_0_5_i_13/CI
|
|
CARRY4 (Prop_carry4_CI_O[1])
|
|
0.348 -0.886 r u_matmul_axi_slave/mult_inst[0].u_mult/b1_c_reg_r1_0_15_0_5_i_13/O[1]
|
|
net (fo=2, unplaced) 0.622 -0.264 u_matmul_axi_slave/calc_c_result02_out[5]
|
|
r u_matmul_axi_slave/b1_c_reg_r1_0_15_0_5_i_16/I0
|
|
LUT2 (Prop_lut2_I0_O) 0.306 0.042 r u_matmul_axi_slave/b1_c_reg_r1_0_15_0_5_i_16/O
|
|
net (fo=1, unplaced) 0.000 0.042 u_matmul_axi_slave/b1_c_reg_r1_0_15_0_5_i_16_n_0
|
|
r u_matmul_axi_slave/b1_c_reg_r1_0_15_0_5_i_3/S[1]
|
|
CARRY4 (Prop_carry4_S[1]_O[3])
|
|
0.640 0.682 r u_matmul_axi_slave/b1_c_reg_r1_0_15_0_5_i_3/O[3]
|
|
net (fo=15, unplaced) 0.671 1.353 u_matmul_axi_slave/b1_c_reg_r1_0_15_0_5_i_3_n_4
|
|
r u_matmul_axi_slave/crc_reg[12]_i_91/I2
|
|
LUT6 (Prop_lut6_I2_O) 0.307 1.660 r u_matmul_axi_slave/crc_reg[12]_i_91/O
|
|
net (fo=3, unplaced) 0.920 2.580 u_matmul_axi_slave/crc_reg[12]_i_91_n_0
|
|
r u_matmul_axi_slave/crc_reg[12]_i_72/I3
|
|
LUT6 (Prop_lut6_I3_O) 0.124 2.704 r u_matmul_axi_slave/crc_reg[12]_i_72/O
|
|
net (fo=7, unplaced) 0.484 3.188 u_matmul_axi_slave/crc_reg[12]_i_72_n_0
|
|
r u_matmul_axi_slave/crc_reg[12]_i_64/I1
|
|
LUT6 (Prop_lut6_I1_O) 0.124 3.312 r u_matmul_axi_slave/crc_reg[12]_i_64/O
|
|
net (fo=11, unplaced) 1.010 4.322 u_matmul_axi_slave/crc32_word_next_return4[3]
|
|
r u_matmul_axi_slave/crc_reg[31]_i_30/I1
|
|
LUT6 (Prop_lut6_I1_O) 0.124 4.446 r u_matmul_axi_slave/crc_reg[31]_i_30/O
|
|
net (fo=10, unplaced) 0.945 5.391 u_matmul_axi_slave/crc32_word_next_return1[5]
|
|
r u_matmul_axi_slave/crc_reg[23]_i_18/I1
|
|
LUT5 (Prop_lut5_I1_O) 0.124 5.515 r u_matmul_axi_slave/crc_reg[23]_i_18/O
|
|
net (fo=14, unplaced) 0.953 6.468 u_matmul_axi_slave/crc32_word_next0_return10[7]
|
|
r u_matmul_axi_slave/crc_reg[12]_i_33/I2
|
|
LUT6 (Prop_lut6_I2_O) 0.124 6.592 r u_matmul_axi_slave/crc_reg[12]_i_33/O
|
|
net (fo=11, unplaced) 0.948 7.540 u_matmul_axi_slave/crc32_word_next0_return7[5]
|
|
r u_matmul_axi_slave/crc_reg[23]_i_10/I1
|
|
LUT5 (Prop_lut5_I1_O) 0.124 7.664 r u_matmul_axi_slave/crc_reg[23]_i_10/O
|
|
net (fo=15, unplaced) 0.955 8.619 u_matmul_axi_slave/crc32_word_next0_return4[7]
|
|
r u_matmul_axi_slave/crc_reg[12]_i_32/I1
|
|
LUT4 (Prop_lut4_I1_O) 0.124 8.743 r u_matmul_axi_slave/crc_reg[12]_i_32/O
|
|
net (fo=1, unplaced) 0.902 9.645 u_matmul_axi_slave/crc32_word_next0_return3[21]
|
|
r u_matmul_axi_slave/crc_reg[12]_i_16/I0
|
|
LUT6 (Prop_lut6_I0_O) 0.124 9.769 r u_matmul_axi_slave/crc_reg[12]_i_16/O
|
|
net (fo=2, unplaced) 1.122 10.891 u_matmul_axi_slave/crc_reg[12]_i_16_n_0
|
|
r u_matmul_axi_slave/crc_reg[20]_i_8/I0
|
|
LUT5 (Prop_lut5_I0_O) 0.152 11.043 r u_matmul_axi_slave/crc_reg[20]_i_8/O
|
|
net (fo=6, unplaced) 0.934 11.977 u_matmul_axi_slave/crc32_word_next1_return7[4]
|
|
r u_matmul_axi_slave/crc_reg[20]_i_3/I2
|
|
LUT5 (Prop_lut5_I2_O) 0.150 12.127 r u_matmul_axi_slave/crc_reg[20]_i_3/O
|
|
net (fo=13, unplaced) 0.469 12.596 u_matmul_axi_slave/crc32_word_next1_return4[5]
|
|
r u_matmul_axi_slave/crc_reg[27]_i_2/I3
|
|
LUT5 (Prop_lut5_I3_O) 0.150 12.746 r u_matmul_axi_slave/crc_reg[27]_i_2/O
|
|
net (fo=13, unplaced) 0.499 13.245 u_matmul_axi_slave/crc32_word_next1_return1[3]
|
|
r u_matmul_axi_slave/crc_reg[1]_i_1/I3
|
|
LUT4 (Prop_lut4_I3_O) 0.124 13.369 r u_matmul_axi_slave/crc_reg[1]_i_1/O
|
|
net (fo=1, unplaced) 0.000 13.369 u_matmul_axi_slave/crc32_word_next1_return[1]
|
|
FDSE r u_matmul_axi_slave/crc_reg_reg[1]/D
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock sys_clk rise edge) 20.000 20.000 r
|
|
K21 0.000 20.000 r clk (IN)
|
|
net (fo=0) 0.000 20.000 pll_clk.u_clk_pll/inst/clk_in1
|
|
K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I
|
|
K21 IBUF (Prop_ibuf_I_O) 1.393 21.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O
|
|
net (fo=1, unplaced) 0.439 21.832 pll_clk.u_clk_pll/inst/clk_in1_clk_pll
|
|
r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1
|
|
PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1)
|
|
-6.040 15.792 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1
|
|
net (fo=1, unplaced) 0.760 16.552 pll_clk.u_clk_pll/inst/sys_clk_clk_pll
|
|
r pll_clk.u_clk_pll/inst/clkout2_buf/I
|
|
BUFG (Prop_bufg_I_O) 0.091 16.643 r pll_clk.u_clk_pll/inst/clkout2_buf/O
|
|
net (fo=10994, unplaced) 0.655 17.297 u_matmul_axi_slave/sys_clk
|
|
FDSE r u_matmul_axi_slave/crc_reg_reg[1]/C
|
|
clock pessimism -0.468 16.830
|
|
clock uncertainty -0.071 16.759
|
|
FDSE (Setup_fdse_C_D) 0.029 16.788 u_matmul_axi_slave/crc_reg_reg[1]
|
|
-------------------------------------------------------------------
|
|
required time 16.788
|
|
arrival time -13.369
|
|
-------------------------------------------------------------------
|
|
slack 3.419
|
|
|
|
Slack (MET) : 5.211ns (required time - arrival time)
|
|
Source: u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[2]/C
|
|
(rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Destination: ext_ram_data[0]
|
|
(output port clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Path Group: sys_clk
|
|
Path Type: Max at Slow Process Corner
|
|
Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns)
|
|
Data Path Delay: 12.723ns (logic 7.382ns (58.023%) route 5.341ns (41.977%))
|
|
Logic Levels: 15 (CARRY4=6 LUT1=1 LUT3=1 LUT4=1 LUT5=1 LUT6=4 OBUFT=1)
|
|
Output Delay: 0.300ns
|
|
Clock Path Skew: -1.695ns (DCD - SCD + CPR)
|
|
Destination Clock Delay (DCD): -4.208ns = ( 15.792 - 20.000 )
|
|
Source Clock Delay (SCD): -3.025ns
|
|
Clock Pessimism Removal (CPR): -0.513ns
|
|
Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Discrete Jitter (DJ): 0.122ns
|
|
Phase Error (PE): 0.000ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock sys_clk rise edge) 0.000 0.000 r
|
|
K21 0.000 0.000 r clk (IN)
|
|
net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1
|
|
K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I
|
|
K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O
|
|
net (fo=1, unplaced) 0.584 2.047 pll_clk.u_clk_pll/inst/clk_in1_clk_pll
|
|
r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1
|
|
PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1)
|
|
-6.768 -4.721 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1
|
|
net (fo=1, unplaced) 0.800 -3.921 pll_clk.u_clk_pll/inst/sys_clk_clk_pll
|
|
r pll_clk.u_clk_pll/inst/clkout2_buf/I
|
|
BUFG (Prop_bufg_I_O) 0.096 -3.825 r pll_clk.u_clk_pll/inst/clkout2_buf/O
|
|
net (fo=10994, unplaced) 0.800 -3.025 u_axi_ram/u_axi_sram_sp/sys_clk
|
|
FDCE r u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[2]/C
|
|
------------------------------------------------------------------- -------------------
|
|
FDCE (Prop_fdce_C_Q) 0.456 -2.569 f u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[2]/Q
|
|
net (fo=56, unplaced) 0.826 -1.743 u_axi_ram/u_axi_sram_sp/len[2]
|
|
f u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6/I1
|
|
LUT4 (Prop_lut4_I1_O) 0.321 -1.422 r u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6/O
|
|
net (fo=4, unplaced) 0.473 -0.949 u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6_n_0
|
|
r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_20/I1
|
|
LUT5 (Prop_lut5_I1_O) 0.124 -0.825 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_20/O
|
|
net (fo=1, unplaced) 0.449 -0.376 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_20_n_0
|
|
r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_19/I5
|
|
LUT6 (Prop_lut6_I5_O) 0.124 -0.252 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_19/O
|
|
net (fo=1, unplaced) 0.000 -0.252 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_19_n_0
|
|
r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/S[0]
|
|
CARRY4 (Prop_carry4_S[0]_CO[3])
|
|
0.532 0.280 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/CO[3]
|
|
net (fo=1, unplaced) 0.000 0.280 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10_n_0
|
|
r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CI
|
|
CARRY4 (Prop_carry4_CI_CO[3])
|
|
0.114 0.394 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CO[3]
|
|
net (fo=1, unplaced) 0.000 0.394 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9_n_0
|
|
r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/CI
|
|
CARRY4 (Prop_carry4_CI_CO[3])
|
|
0.114 0.508 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/CO[3]
|
|
net (fo=1, unplaced) 0.000 0.508 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11_n_0
|
|
r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_10/CI
|
|
CARRY4 (Prop_carry4_CI_CO[3])
|
|
0.114 0.622 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_10/CO[3]
|
|
net (fo=1, unplaced) 0.000 0.622 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_10_n_0
|
|
r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2_i_9/CI
|
|
CARRY4 (Prop_carry4_CI_O[3])
|
|
0.329 0.951 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2_i_9/O[3]
|
|
net (fo=3, unplaced) 0.826 1.777 u_axi_ram/u_axi_sram_sp/upper_wrap_boundary[29]
|
|
r u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1_i_2/I0
|
|
LUT6 (Prop_lut6_I0_O) 0.307 2.084 r u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1_i_2/O
|
|
net (fo=1, unplaced) 0.000 2.084 u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1_i_2_n_0
|
|
r u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1/S[1]
|
|
CARRY4 (Prop_carry4_S[1]_CO[2])
|
|
0.570 2.654 r u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1/CO[2]
|
|
net (fo=23, unplaced) 0.515 3.169 u_axi_ram/u_axi_sram_sp/req_addr_d10_in
|
|
r u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/I5
|
|
LUT6 (Prop_lut6_I5_O) 0.310 3.479 r u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/O
|
|
net (fo=2, unplaced) 0.460 3.939 u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7_n_0
|
|
r u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/I1
|
|
LUT6 (Prop_lut6_I1_O) 0.124 4.063 r u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/O
|
|
net (fo=80, unplaced) 0.543 4.606 u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/soc_sram_addr[0]
|
|
r u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/ext_ram_data_IOBUF[31]_inst_i_2/I2
|
|
LUT3 (Prop_lut3_I2_O) 0.118 4.724 r u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/ext_ram_data_IOBUF[31]_inst_i_2/O
|
|
net (fo=1, unplaced) 0.449 5.173 u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/u_axi_ram/ext_ram_data1
|
|
r u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/ext_ram_data_IOBUF[31]_inst_i_1/I0
|
|
LUT1 (Prop_lut1_I0_O) 0.124 5.297 f u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/ext_ram_data_IOBUF[31]_inst_i_1/O
|
|
net (fo=32, unplaced) 0.800 6.096 ext_ram_data_IOBUF[0]_inst/T
|
|
AF24 f ext_ram_data_IOBUF[0]_inst/OBUFT/T
|
|
AF24 OBUFT (TriStatE_obuft_T_O)
|
|
3.601 9.698 r ext_ram_data_IOBUF[0]_inst/OBUFT/O
|
|
net (fo=1, unset) 0.000 9.698 ext_ram_data[0]
|
|
AF24 r ext_ram_data[0] (INOUT)
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock sys_clk rise edge) 20.000 20.000 r
|
|
K21 0.000 20.000 r clk (IN)
|
|
net (fo=0) 0.000 20.000 pll_clk.u_clk_pll/inst/clk_in1
|
|
K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I
|
|
K21 IBUF (Prop_ibuf_I_O) 1.393 21.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O
|
|
net (fo=1, unplaced) 0.439 21.832 pll_clk.u_clk_pll/inst/clk_in1_clk_pll
|
|
r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1
|
|
PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1)
|
|
-6.040 15.792 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1
|
|
clock pessimism -0.513 15.279
|
|
clock uncertainty -0.071 15.209
|
|
output delay -0.300 14.909
|
|
-------------------------------------------------------------------
|
|
required time 14.909
|
|
arrival time -9.698
|
|
-------------------------------------------------------------------
|
|
slack 5.211
|
|
|
|
Slack (MET) : 5.212ns (required time - arrival time)
|
|
Source: u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[2]/C
|
|
(rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Destination: ext_ram_data[31]
|
|
(output port clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Path Group: sys_clk
|
|
Path Type: Max at Slow Process Corner
|
|
Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns)
|
|
Data Path Delay: 12.722ns (logic 7.381ns (58.020%) route 5.341ns (41.980%))
|
|
Logic Levels: 15 (CARRY4=6 LUT1=1 LUT3=1 LUT4=1 LUT5=1 LUT6=4 OBUFT=1)
|
|
Output Delay: 0.300ns
|
|
Clock Path Skew: -1.695ns (DCD - SCD + CPR)
|
|
Destination Clock Delay (DCD): -4.208ns = ( 15.792 - 20.000 )
|
|
Source Clock Delay (SCD): -3.025ns
|
|
Clock Pessimism Removal (CPR): -0.513ns
|
|
Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Discrete Jitter (DJ): 0.122ns
|
|
Phase Error (PE): 0.000ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock sys_clk rise edge) 0.000 0.000 r
|
|
K21 0.000 0.000 r clk (IN)
|
|
net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1
|
|
K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I
|
|
K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O
|
|
net (fo=1, unplaced) 0.584 2.047 pll_clk.u_clk_pll/inst/clk_in1_clk_pll
|
|
r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1
|
|
PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1)
|
|
-6.768 -4.721 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1
|
|
net (fo=1, unplaced) 0.800 -3.921 pll_clk.u_clk_pll/inst/sys_clk_clk_pll
|
|
r pll_clk.u_clk_pll/inst/clkout2_buf/I
|
|
BUFG (Prop_bufg_I_O) 0.096 -3.825 r pll_clk.u_clk_pll/inst/clkout2_buf/O
|
|
net (fo=10994, unplaced) 0.800 -3.025 u_axi_ram/u_axi_sram_sp/sys_clk
|
|
FDCE r u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[2]/C
|
|
------------------------------------------------------------------- -------------------
|
|
FDCE (Prop_fdce_C_Q) 0.456 -2.569 f u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[2]/Q
|
|
net (fo=56, unplaced) 0.826 -1.743 u_axi_ram/u_axi_sram_sp/len[2]
|
|
f u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6/I1
|
|
LUT4 (Prop_lut4_I1_O) 0.321 -1.422 r u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6/O
|
|
net (fo=4, unplaced) 0.473 -0.949 u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6_n_0
|
|
r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_20/I1
|
|
LUT5 (Prop_lut5_I1_O) 0.124 -0.825 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_20/O
|
|
net (fo=1, unplaced) 0.449 -0.376 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_20_n_0
|
|
r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_19/I5
|
|
LUT6 (Prop_lut6_I5_O) 0.124 -0.252 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_19/O
|
|
net (fo=1, unplaced) 0.000 -0.252 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_19_n_0
|
|
r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/S[0]
|
|
CARRY4 (Prop_carry4_S[0]_CO[3])
|
|
0.532 0.280 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/CO[3]
|
|
net (fo=1, unplaced) 0.000 0.280 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10_n_0
|
|
r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CI
|
|
CARRY4 (Prop_carry4_CI_CO[3])
|
|
0.114 0.394 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CO[3]
|
|
net (fo=1, unplaced) 0.000 0.394 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9_n_0
|
|
r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/CI
|
|
CARRY4 (Prop_carry4_CI_CO[3])
|
|
0.114 0.508 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/CO[3]
|
|
net (fo=1, unplaced) 0.000 0.508 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11_n_0
|
|
r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_10/CI
|
|
CARRY4 (Prop_carry4_CI_CO[3])
|
|
0.114 0.622 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_10/CO[3]
|
|
net (fo=1, unplaced) 0.000 0.622 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_10_n_0
|
|
r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2_i_9/CI
|
|
CARRY4 (Prop_carry4_CI_O[3])
|
|
0.329 0.951 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2_i_9/O[3]
|
|
net (fo=3, unplaced) 0.826 1.777 u_axi_ram/u_axi_sram_sp/upper_wrap_boundary[29]
|
|
r u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1_i_2/I0
|
|
LUT6 (Prop_lut6_I0_O) 0.307 2.084 r u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1_i_2/O
|
|
net (fo=1, unplaced) 0.000 2.084 u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1_i_2_n_0
|
|
r u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1/S[1]
|
|
CARRY4 (Prop_carry4_S[1]_CO[2])
|
|
0.570 2.654 r u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1/CO[2]
|
|
net (fo=23, unplaced) 0.515 3.169 u_axi_ram/u_axi_sram_sp/req_addr_d10_in
|
|
r u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/I5
|
|
LUT6 (Prop_lut6_I5_O) 0.310 3.479 r u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/O
|
|
net (fo=2, unplaced) 0.460 3.939 u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7_n_0
|
|
r u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/I1
|
|
LUT6 (Prop_lut6_I1_O) 0.124 4.063 r u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/O
|
|
net (fo=80, unplaced) 0.543 4.606 u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/soc_sram_addr[0]
|
|
r u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/ext_ram_data_IOBUF[31]_inst_i_2/I2
|
|
LUT3 (Prop_lut3_I2_O) 0.118 4.724 r u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/ext_ram_data_IOBUF[31]_inst_i_2/O
|
|
net (fo=1, unplaced) 0.449 5.173 u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/u_axi_ram/ext_ram_data1
|
|
r u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/ext_ram_data_IOBUF[31]_inst_i_1/I0
|
|
LUT1 (Prop_lut1_I0_O) 0.124 5.297 f u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/ext_ram_data_IOBUF[31]_inst_i_1/O
|
|
net (fo=32, unplaced) 0.800 6.096 ext_ram_data_IOBUF[31]_inst/T
|
|
AC23 f ext_ram_data_IOBUF[31]_inst/OBUFT/T
|
|
AC23 OBUFT (TriStatE_obuft_T_O)
|
|
3.600 9.697 r ext_ram_data_IOBUF[31]_inst/OBUFT/O
|
|
net (fo=1, unset) 0.000 9.697 ext_ram_data[31]
|
|
AC23 r ext_ram_data[31] (INOUT)
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock sys_clk rise edge) 20.000 20.000 r
|
|
K21 0.000 20.000 r clk (IN)
|
|
net (fo=0) 0.000 20.000 pll_clk.u_clk_pll/inst/clk_in1
|
|
K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I
|
|
K21 IBUF (Prop_ibuf_I_O) 1.393 21.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O
|
|
net (fo=1, unplaced) 0.439 21.832 pll_clk.u_clk_pll/inst/clk_in1_clk_pll
|
|
r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1
|
|
PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1)
|
|
-6.040 15.792 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1
|
|
clock pessimism -0.513 15.279
|
|
clock uncertainty -0.071 15.209
|
|
output delay -0.300 14.909
|
|
-------------------------------------------------------------------
|
|
required time 14.909
|
|
arrival time -9.697
|
|
-------------------------------------------------------------------
|
|
slack 5.212
|
|
|
|
Slack (MET) : 5.216ns (required time - arrival time)
|
|
Source: u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[2]/C
|
|
(rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Destination: ext_ram_data[2]
|
|
(output port clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Path Group: sys_clk
|
|
Path Type: Max at Slow Process Corner
|
|
Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns)
|
|
Data Path Delay: 12.718ns (logic 7.378ns (58.008%) route 5.341ns (41.992%))
|
|
Logic Levels: 15 (CARRY4=6 LUT1=1 LUT3=1 LUT4=1 LUT5=1 LUT6=4 OBUFT=1)
|
|
Output Delay: 0.300ns
|
|
Clock Path Skew: -1.695ns (DCD - SCD + CPR)
|
|
Destination Clock Delay (DCD): -4.208ns = ( 15.792 - 20.000 )
|
|
Source Clock Delay (SCD): -3.025ns
|
|
Clock Pessimism Removal (CPR): -0.513ns
|
|
Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Discrete Jitter (DJ): 0.122ns
|
|
Phase Error (PE): 0.000ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock sys_clk rise edge) 0.000 0.000 r
|
|
K21 0.000 0.000 r clk (IN)
|
|
net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1
|
|
K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I
|
|
K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O
|
|
net (fo=1, unplaced) 0.584 2.047 pll_clk.u_clk_pll/inst/clk_in1_clk_pll
|
|
r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1
|
|
PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1)
|
|
-6.768 -4.721 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1
|
|
net (fo=1, unplaced) 0.800 -3.921 pll_clk.u_clk_pll/inst/sys_clk_clk_pll
|
|
r pll_clk.u_clk_pll/inst/clkout2_buf/I
|
|
BUFG (Prop_bufg_I_O) 0.096 -3.825 r pll_clk.u_clk_pll/inst/clkout2_buf/O
|
|
net (fo=10994, unplaced) 0.800 -3.025 u_axi_ram/u_axi_sram_sp/sys_clk
|
|
FDCE r u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[2]/C
|
|
------------------------------------------------------------------- -------------------
|
|
FDCE (Prop_fdce_C_Q) 0.456 -2.569 f u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[2]/Q
|
|
net (fo=56, unplaced) 0.826 -1.743 u_axi_ram/u_axi_sram_sp/len[2]
|
|
f u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6/I1
|
|
LUT4 (Prop_lut4_I1_O) 0.321 -1.422 r u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6/O
|
|
net (fo=4, unplaced) 0.473 -0.949 u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6_n_0
|
|
r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_20/I1
|
|
LUT5 (Prop_lut5_I1_O) 0.124 -0.825 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_20/O
|
|
net (fo=1, unplaced) 0.449 -0.376 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_20_n_0
|
|
r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_19/I5
|
|
LUT6 (Prop_lut6_I5_O) 0.124 -0.252 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_19/O
|
|
net (fo=1, unplaced) 0.000 -0.252 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_19_n_0
|
|
r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/S[0]
|
|
CARRY4 (Prop_carry4_S[0]_CO[3])
|
|
0.532 0.280 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/CO[3]
|
|
net (fo=1, unplaced) 0.000 0.280 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10_n_0
|
|
r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CI
|
|
CARRY4 (Prop_carry4_CI_CO[3])
|
|
0.114 0.394 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CO[3]
|
|
net (fo=1, unplaced) 0.000 0.394 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9_n_0
|
|
r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/CI
|
|
CARRY4 (Prop_carry4_CI_CO[3])
|
|
0.114 0.508 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/CO[3]
|
|
net (fo=1, unplaced) 0.000 0.508 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11_n_0
|
|
r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_10/CI
|
|
CARRY4 (Prop_carry4_CI_CO[3])
|
|
0.114 0.622 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_10/CO[3]
|
|
net (fo=1, unplaced) 0.000 0.622 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_10_n_0
|
|
r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2_i_9/CI
|
|
CARRY4 (Prop_carry4_CI_O[3])
|
|
0.329 0.951 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2_i_9/O[3]
|
|
net (fo=3, unplaced) 0.826 1.777 u_axi_ram/u_axi_sram_sp/upper_wrap_boundary[29]
|
|
r u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1_i_2/I0
|
|
LUT6 (Prop_lut6_I0_O) 0.307 2.084 r u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1_i_2/O
|
|
net (fo=1, unplaced) 0.000 2.084 u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1_i_2_n_0
|
|
r u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1/S[1]
|
|
CARRY4 (Prop_carry4_S[1]_CO[2])
|
|
0.570 2.654 r u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1/CO[2]
|
|
net (fo=23, unplaced) 0.515 3.169 u_axi_ram/u_axi_sram_sp/req_addr_d10_in
|
|
r u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/I5
|
|
LUT6 (Prop_lut6_I5_O) 0.310 3.479 r u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/O
|
|
net (fo=2, unplaced) 0.460 3.939 u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7_n_0
|
|
r u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/I1
|
|
LUT6 (Prop_lut6_I1_O) 0.124 4.063 r u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/O
|
|
net (fo=80, unplaced) 0.543 4.606 u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/soc_sram_addr[0]
|
|
r u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/ext_ram_data_IOBUF[31]_inst_i_2/I2
|
|
LUT3 (Prop_lut3_I2_O) 0.118 4.724 r u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/ext_ram_data_IOBUF[31]_inst_i_2/O
|
|
net (fo=1, unplaced) 0.449 5.173 u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/u_axi_ram/ext_ram_data1
|
|
r u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/ext_ram_data_IOBUF[31]_inst_i_1/I0
|
|
LUT1 (Prop_lut1_I0_O) 0.124 5.297 f u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/ext_ram_data_IOBUF[31]_inst_i_1/O
|
|
net (fo=32, unplaced) 0.800 6.096 ext_ram_data_IOBUF[2]_inst/T
|
|
AF23 f ext_ram_data_IOBUF[2]_inst/OBUFT/T
|
|
AF23 OBUFT (TriStatE_obuft_T_O)
|
|
3.597 9.693 r ext_ram_data_IOBUF[2]_inst/OBUFT/O
|
|
net (fo=1, unset) 0.000 9.693 ext_ram_data[2]
|
|
AF23 r ext_ram_data[2] (INOUT)
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock sys_clk rise edge) 20.000 20.000 r
|
|
K21 0.000 20.000 r clk (IN)
|
|
net (fo=0) 0.000 20.000 pll_clk.u_clk_pll/inst/clk_in1
|
|
K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I
|
|
K21 IBUF (Prop_ibuf_I_O) 1.393 21.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O
|
|
net (fo=1, unplaced) 0.439 21.832 pll_clk.u_clk_pll/inst/clk_in1_clk_pll
|
|
r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1
|
|
PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1)
|
|
-6.040 15.792 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1
|
|
clock pessimism -0.513 15.279
|
|
clock uncertainty -0.071 15.209
|
|
output delay -0.300 14.909
|
|
-------------------------------------------------------------------
|
|
required time 14.909
|
|
arrival time -9.693
|
|
-------------------------------------------------------------------
|
|
slack 5.216
|
|
|
|
Slack (MET) : 5.217ns (required time - arrival time)
|
|
Source: u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[2]/C
|
|
(rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Destination: base_ram_data[8]
|
|
(output port clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Path Group: sys_clk
|
|
Path Type: Max at Slow Process Corner
|
|
Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns)
|
|
Data Path Delay: 12.717ns (logic 7.376ns (58.003%) route 5.341ns (41.997%))
|
|
Logic Levels: 15 (CARRY4=6 LUT1=1 LUT3=1 LUT4=1 LUT5=1 LUT6=4 OBUFT=1)
|
|
Output Delay: 0.300ns
|
|
Clock Path Skew: -1.695ns (DCD - SCD + CPR)
|
|
Destination Clock Delay (DCD): -4.208ns = ( 15.792 - 20.000 )
|
|
Source Clock Delay (SCD): -3.025ns
|
|
Clock Pessimism Removal (CPR): -0.513ns
|
|
Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Discrete Jitter (DJ): 0.122ns
|
|
Phase Error (PE): 0.000ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock sys_clk rise edge) 0.000 0.000 r
|
|
K21 0.000 0.000 r clk (IN)
|
|
net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1
|
|
K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I
|
|
K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O
|
|
net (fo=1, unplaced) 0.584 2.047 pll_clk.u_clk_pll/inst/clk_in1_clk_pll
|
|
r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1
|
|
PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1)
|
|
-6.768 -4.721 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1
|
|
net (fo=1, unplaced) 0.800 -3.921 pll_clk.u_clk_pll/inst/sys_clk_clk_pll
|
|
r pll_clk.u_clk_pll/inst/clkout2_buf/I
|
|
BUFG (Prop_bufg_I_O) 0.096 -3.825 r pll_clk.u_clk_pll/inst/clkout2_buf/O
|
|
net (fo=10994, unplaced) 0.800 -3.025 u_axi_ram/u_axi_sram_sp/sys_clk
|
|
FDCE r u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[2]/C
|
|
------------------------------------------------------------------- -------------------
|
|
FDCE (Prop_fdce_C_Q) 0.456 -2.569 f u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[2]/Q
|
|
net (fo=56, unplaced) 0.826 -1.743 u_axi_ram/u_axi_sram_sp/len[2]
|
|
f u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6/I1
|
|
LUT4 (Prop_lut4_I1_O) 0.321 -1.422 r u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6/O
|
|
net (fo=4, unplaced) 0.473 -0.949 u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6_n_0
|
|
r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_20/I1
|
|
LUT5 (Prop_lut5_I1_O) 0.124 -0.825 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_20/O
|
|
net (fo=1, unplaced) 0.449 -0.376 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_20_n_0
|
|
r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_19/I5
|
|
LUT6 (Prop_lut6_I5_O) 0.124 -0.252 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_19/O
|
|
net (fo=1, unplaced) 0.000 -0.252 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_19_n_0
|
|
r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/S[0]
|
|
CARRY4 (Prop_carry4_S[0]_CO[3])
|
|
0.532 0.280 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/CO[3]
|
|
net (fo=1, unplaced) 0.000 0.280 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10_n_0
|
|
r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CI
|
|
CARRY4 (Prop_carry4_CI_CO[3])
|
|
0.114 0.394 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CO[3]
|
|
net (fo=1, unplaced) 0.000 0.394 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9_n_0
|
|
r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/CI
|
|
CARRY4 (Prop_carry4_CI_CO[3])
|
|
0.114 0.508 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/CO[3]
|
|
net (fo=1, unplaced) 0.000 0.508 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11_n_0
|
|
r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_10/CI
|
|
CARRY4 (Prop_carry4_CI_CO[3])
|
|
0.114 0.622 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_10/CO[3]
|
|
net (fo=1, unplaced) 0.000 0.622 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_10_n_0
|
|
r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2_i_9/CI
|
|
CARRY4 (Prop_carry4_CI_O[3])
|
|
0.329 0.951 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2_i_9/O[3]
|
|
net (fo=3, unplaced) 0.826 1.777 u_axi_ram/u_axi_sram_sp/upper_wrap_boundary[29]
|
|
r u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1_i_2/I0
|
|
LUT6 (Prop_lut6_I0_O) 0.307 2.084 r u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1_i_2/O
|
|
net (fo=1, unplaced) 0.000 2.084 u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1_i_2_n_0
|
|
r u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1/S[1]
|
|
CARRY4 (Prop_carry4_S[1]_CO[2])
|
|
0.570 2.654 r u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1/CO[2]
|
|
net (fo=23, unplaced) 0.515 3.169 u_axi_ram/u_axi_sram_sp/req_addr_d10_in
|
|
r u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/I5
|
|
LUT6 (Prop_lut6_I5_O) 0.310 3.479 f u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/O
|
|
net (fo=2, unplaced) 0.460 3.939 u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7_n_0
|
|
f u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/I1
|
|
LUT6 (Prop_lut6_I1_O) 0.124 4.063 f u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/O
|
|
net (fo=80, unplaced) 0.543 4.606 u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/soc_sram_addr[0]
|
|
f u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/base_ram_data_IOBUF[31]_inst_i_3/I2
|
|
LUT3 (Prop_lut3_I2_O) 0.124 4.730 r u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/base_ram_data_IOBUF[31]_inst_i_3/O
|
|
net (fo=1, unplaced) 0.449 5.179 u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/u_axi_ram/base_ram_data1
|
|
r u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/base_ram_data_IOBUF[31]_inst_i_2/I0
|
|
LUT1 (Prop_lut1_I0_O) 0.124 5.303 f u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/base_ram_data_IOBUF[31]_inst_i_2/O
|
|
net (fo=32, unplaced) 0.800 6.102 base_ram_data_IOBUF[8]_inst/T
|
|
AA24 f base_ram_data_IOBUF[8]_inst/OBUFT/T
|
|
AA24 OBUFT (TriStatE_obuft_T_O)
|
|
3.589 9.691 r base_ram_data_IOBUF[8]_inst/OBUFT/O
|
|
net (fo=1, unset) 0.000 9.691 base_ram_data[8]
|
|
AA24 r base_ram_data[8] (INOUT)
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock sys_clk rise edge) 20.000 20.000 r
|
|
K21 0.000 20.000 r clk (IN)
|
|
net (fo=0) 0.000 20.000 pll_clk.u_clk_pll/inst/clk_in1
|
|
K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I
|
|
K21 IBUF (Prop_ibuf_I_O) 1.393 21.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O
|
|
net (fo=1, unplaced) 0.439 21.832 pll_clk.u_clk_pll/inst/clk_in1_clk_pll
|
|
r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1
|
|
PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1)
|
|
-6.040 15.792 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1
|
|
clock pessimism -0.513 15.279
|
|
clock uncertainty -0.071 15.209
|
|
output delay -0.300 14.909
|
|
-------------------------------------------------------------------
|
|
required time 14.909
|
|
arrival time -9.691
|
|
-------------------------------------------------------------------
|
|
slack 5.217
|
|
|
|
Slack (MET) : 5.219ns (required time - arrival time)
|
|
Source: u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[2]/C
|
|
(rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Destination: ext_ram_data[3]
|
|
(output port clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Path Group: sys_clk
|
|
Path Type: Max at Slow Process Corner
|
|
Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns)
|
|
Data Path Delay: 12.715ns (logic 7.374ns (57.997%) route 5.341ns (42.003%))
|
|
Logic Levels: 15 (CARRY4=6 LUT1=1 LUT3=1 LUT4=1 LUT5=1 LUT6=4 OBUFT=1)
|
|
Output Delay: 0.300ns
|
|
Clock Path Skew: -1.695ns (DCD - SCD + CPR)
|
|
Destination Clock Delay (DCD): -4.208ns = ( 15.792 - 20.000 )
|
|
Source Clock Delay (SCD): -3.025ns
|
|
Clock Pessimism Removal (CPR): -0.513ns
|
|
Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Discrete Jitter (DJ): 0.122ns
|
|
Phase Error (PE): 0.000ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock sys_clk rise edge) 0.000 0.000 r
|
|
K21 0.000 0.000 r clk (IN)
|
|
net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1
|
|
K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I
|
|
K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O
|
|
net (fo=1, unplaced) 0.584 2.047 pll_clk.u_clk_pll/inst/clk_in1_clk_pll
|
|
r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1
|
|
PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1)
|
|
-6.768 -4.721 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1
|
|
net (fo=1, unplaced) 0.800 -3.921 pll_clk.u_clk_pll/inst/sys_clk_clk_pll
|
|
r pll_clk.u_clk_pll/inst/clkout2_buf/I
|
|
BUFG (Prop_bufg_I_O) 0.096 -3.825 r pll_clk.u_clk_pll/inst/clkout2_buf/O
|
|
net (fo=10994, unplaced) 0.800 -3.025 u_axi_ram/u_axi_sram_sp/sys_clk
|
|
FDCE r u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[2]/C
|
|
------------------------------------------------------------------- -------------------
|
|
FDCE (Prop_fdce_C_Q) 0.456 -2.569 f u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[2]/Q
|
|
net (fo=56, unplaced) 0.826 -1.743 u_axi_ram/u_axi_sram_sp/len[2]
|
|
f u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6/I1
|
|
LUT4 (Prop_lut4_I1_O) 0.321 -1.422 r u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6/O
|
|
net (fo=4, unplaced) 0.473 -0.949 u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6_n_0
|
|
r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_20/I1
|
|
LUT5 (Prop_lut5_I1_O) 0.124 -0.825 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_20/O
|
|
net (fo=1, unplaced) 0.449 -0.376 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_20_n_0
|
|
r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_19/I5
|
|
LUT6 (Prop_lut6_I5_O) 0.124 -0.252 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_19/O
|
|
net (fo=1, unplaced) 0.000 -0.252 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_19_n_0
|
|
r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/S[0]
|
|
CARRY4 (Prop_carry4_S[0]_CO[3])
|
|
0.532 0.280 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/CO[3]
|
|
net (fo=1, unplaced) 0.000 0.280 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10_n_0
|
|
r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CI
|
|
CARRY4 (Prop_carry4_CI_CO[3])
|
|
0.114 0.394 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CO[3]
|
|
net (fo=1, unplaced) 0.000 0.394 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9_n_0
|
|
r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/CI
|
|
CARRY4 (Prop_carry4_CI_CO[3])
|
|
0.114 0.508 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/CO[3]
|
|
net (fo=1, unplaced) 0.000 0.508 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11_n_0
|
|
r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_10/CI
|
|
CARRY4 (Prop_carry4_CI_CO[3])
|
|
0.114 0.622 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_10/CO[3]
|
|
net (fo=1, unplaced) 0.000 0.622 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_10_n_0
|
|
r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2_i_9/CI
|
|
CARRY4 (Prop_carry4_CI_O[3])
|
|
0.329 0.951 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2_i_9/O[3]
|
|
net (fo=3, unplaced) 0.826 1.777 u_axi_ram/u_axi_sram_sp/upper_wrap_boundary[29]
|
|
r u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1_i_2/I0
|
|
LUT6 (Prop_lut6_I0_O) 0.307 2.084 r u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1_i_2/O
|
|
net (fo=1, unplaced) 0.000 2.084 u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1_i_2_n_0
|
|
r u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1/S[1]
|
|
CARRY4 (Prop_carry4_S[1]_CO[2])
|
|
0.570 2.654 r u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1/CO[2]
|
|
net (fo=23, unplaced) 0.515 3.169 u_axi_ram/u_axi_sram_sp/req_addr_d10_in
|
|
r u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/I5
|
|
LUT6 (Prop_lut6_I5_O) 0.310 3.479 r u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/O
|
|
net (fo=2, unplaced) 0.460 3.939 u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7_n_0
|
|
r u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/I1
|
|
LUT6 (Prop_lut6_I1_O) 0.124 4.063 r u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/O
|
|
net (fo=80, unplaced) 0.543 4.606 u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/soc_sram_addr[0]
|
|
r u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/ext_ram_data_IOBUF[31]_inst_i_2/I2
|
|
LUT3 (Prop_lut3_I2_O) 0.118 4.724 r u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/ext_ram_data_IOBUF[31]_inst_i_2/O
|
|
net (fo=1, unplaced) 0.449 5.173 u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/u_axi_ram/ext_ram_data1
|
|
r u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/ext_ram_data_IOBUF[31]_inst_i_1/I0
|
|
LUT1 (Prop_lut1_I0_O) 0.124 5.297 f u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/ext_ram_data_IOBUF[31]_inst_i_1/O
|
|
net (fo=32, unplaced) 0.800 6.096 ext_ram_data_IOBUF[3]_inst/T
|
|
AE22 f ext_ram_data_IOBUF[3]_inst/OBUFT/T
|
|
AE22 OBUFT (TriStatE_obuft_T_O)
|
|
3.593 9.690 r ext_ram_data_IOBUF[3]_inst/OBUFT/O
|
|
net (fo=1, unset) 0.000 9.690 ext_ram_data[3]
|
|
AE22 r ext_ram_data[3] (INOUT)
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock sys_clk rise edge) 20.000 20.000 r
|
|
K21 0.000 20.000 r clk (IN)
|
|
net (fo=0) 0.000 20.000 pll_clk.u_clk_pll/inst/clk_in1
|
|
K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I
|
|
K21 IBUF (Prop_ibuf_I_O) 1.393 21.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O
|
|
net (fo=1, unplaced) 0.439 21.832 pll_clk.u_clk_pll/inst/clk_in1_clk_pll
|
|
r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1
|
|
PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1)
|
|
-6.040 15.792 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1
|
|
clock pessimism -0.513 15.279
|
|
clock uncertainty -0.071 15.209
|
|
output delay -0.300 14.909
|
|
-------------------------------------------------------------------
|
|
required time 14.909
|
|
arrival time -9.690
|
|
-------------------------------------------------------------------
|
|
slack 5.219
|
|
|
|
Slack (MET) : 5.219ns (required time - arrival time)
|
|
Source: u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[2]/C
|
|
(rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Destination: base_ram_data[11]
|
|
(output port clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Path Group: sys_clk
|
|
Path Type: Max at Slow Process Corner
|
|
Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns)
|
|
Data Path Delay: 12.715ns (logic 7.374ns (57.997%) route 5.341ns (42.003%))
|
|
Logic Levels: 15 (CARRY4=6 LUT1=1 LUT3=1 LUT4=1 LUT5=1 LUT6=4 OBUFT=1)
|
|
Output Delay: 0.300ns
|
|
Clock Path Skew: -1.695ns (DCD - SCD + CPR)
|
|
Destination Clock Delay (DCD): -4.208ns = ( 15.792 - 20.000 )
|
|
Source Clock Delay (SCD): -3.025ns
|
|
Clock Pessimism Removal (CPR): -0.513ns
|
|
Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Discrete Jitter (DJ): 0.122ns
|
|
Phase Error (PE): 0.000ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock sys_clk rise edge) 0.000 0.000 r
|
|
K21 0.000 0.000 r clk (IN)
|
|
net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1
|
|
K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I
|
|
K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O
|
|
net (fo=1, unplaced) 0.584 2.047 pll_clk.u_clk_pll/inst/clk_in1_clk_pll
|
|
r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1
|
|
PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1)
|
|
-6.768 -4.721 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1
|
|
net (fo=1, unplaced) 0.800 -3.921 pll_clk.u_clk_pll/inst/sys_clk_clk_pll
|
|
r pll_clk.u_clk_pll/inst/clkout2_buf/I
|
|
BUFG (Prop_bufg_I_O) 0.096 -3.825 r pll_clk.u_clk_pll/inst/clkout2_buf/O
|
|
net (fo=10994, unplaced) 0.800 -3.025 u_axi_ram/u_axi_sram_sp/sys_clk
|
|
FDCE r u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[2]/C
|
|
------------------------------------------------------------------- -------------------
|
|
FDCE (Prop_fdce_C_Q) 0.456 -2.569 f u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[2]/Q
|
|
net (fo=56, unplaced) 0.826 -1.743 u_axi_ram/u_axi_sram_sp/len[2]
|
|
f u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6/I1
|
|
LUT4 (Prop_lut4_I1_O) 0.321 -1.422 r u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6/O
|
|
net (fo=4, unplaced) 0.473 -0.949 u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6_n_0
|
|
r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_20/I1
|
|
LUT5 (Prop_lut5_I1_O) 0.124 -0.825 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_20/O
|
|
net (fo=1, unplaced) 0.449 -0.376 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_20_n_0
|
|
r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_19/I5
|
|
LUT6 (Prop_lut6_I5_O) 0.124 -0.252 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_19/O
|
|
net (fo=1, unplaced) 0.000 -0.252 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_19_n_0
|
|
r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/S[0]
|
|
CARRY4 (Prop_carry4_S[0]_CO[3])
|
|
0.532 0.280 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/CO[3]
|
|
net (fo=1, unplaced) 0.000 0.280 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10_n_0
|
|
r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CI
|
|
CARRY4 (Prop_carry4_CI_CO[3])
|
|
0.114 0.394 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CO[3]
|
|
net (fo=1, unplaced) 0.000 0.394 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9_n_0
|
|
r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/CI
|
|
CARRY4 (Prop_carry4_CI_CO[3])
|
|
0.114 0.508 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/CO[3]
|
|
net (fo=1, unplaced) 0.000 0.508 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11_n_0
|
|
r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_10/CI
|
|
CARRY4 (Prop_carry4_CI_CO[3])
|
|
0.114 0.622 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_10/CO[3]
|
|
net (fo=1, unplaced) 0.000 0.622 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_10_n_0
|
|
r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2_i_9/CI
|
|
CARRY4 (Prop_carry4_CI_O[3])
|
|
0.329 0.951 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2_i_9/O[3]
|
|
net (fo=3, unplaced) 0.826 1.777 u_axi_ram/u_axi_sram_sp/upper_wrap_boundary[29]
|
|
r u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1_i_2/I0
|
|
LUT6 (Prop_lut6_I0_O) 0.307 2.084 r u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1_i_2/O
|
|
net (fo=1, unplaced) 0.000 2.084 u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1_i_2_n_0
|
|
r u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1/S[1]
|
|
CARRY4 (Prop_carry4_S[1]_CO[2])
|
|
0.570 2.654 r u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1/CO[2]
|
|
net (fo=23, unplaced) 0.515 3.169 u_axi_ram/u_axi_sram_sp/req_addr_d10_in
|
|
r u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/I5
|
|
LUT6 (Prop_lut6_I5_O) 0.310 3.479 f u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/O
|
|
net (fo=2, unplaced) 0.460 3.939 u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7_n_0
|
|
f u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/I1
|
|
LUT6 (Prop_lut6_I1_O) 0.124 4.063 f u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/O
|
|
net (fo=80, unplaced) 0.543 4.606 u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/soc_sram_addr[0]
|
|
f u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/base_ram_data_IOBUF[31]_inst_i_3/I2
|
|
LUT3 (Prop_lut3_I2_O) 0.124 4.730 r u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/base_ram_data_IOBUF[31]_inst_i_3/O
|
|
net (fo=1, unplaced) 0.449 5.179 u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/u_axi_ram/base_ram_data1
|
|
r u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/base_ram_data_IOBUF[31]_inst_i_2/I0
|
|
LUT1 (Prop_lut1_I0_O) 0.124 5.303 f u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/base_ram_data_IOBUF[31]_inst_i_2/O
|
|
net (fo=32, unplaced) 0.800 6.102 base_ram_data_IOBUF[11]_inst/T
|
|
W24 f base_ram_data_IOBUF[11]_inst/OBUFT/T
|
|
W24 OBUFT (TriStatE_obuft_T_O)
|
|
3.587 9.690 r base_ram_data_IOBUF[11]_inst/OBUFT/O
|
|
net (fo=1, unset) 0.000 9.690 base_ram_data[11]
|
|
W24 r base_ram_data[11] (INOUT)
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock sys_clk rise edge) 20.000 20.000 r
|
|
K21 0.000 20.000 r clk (IN)
|
|
net (fo=0) 0.000 20.000 pll_clk.u_clk_pll/inst/clk_in1
|
|
K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I
|
|
K21 IBUF (Prop_ibuf_I_O) 1.393 21.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O
|
|
net (fo=1, unplaced) 0.439 21.832 pll_clk.u_clk_pll/inst/clk_in1_clk_pll
|
|
r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1
|
|
PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1)
|
|
-6.040 15.792 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1
|
|
clock pessimism -0.513 15.279
|
|
clock uncertainty -0.071 15.209
|
|
output delay -0.300 14.909
|
|
-------------------------------------------------------------------
|
|
required time 14.909
|
|
arrival time -9.690
|
|
-------------------------------------------------------------------
|
|
slack 5.219
|
|
|
|
Slack (MET) : 5.220ns (required time - arrival time)
|
|
Source: u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[2]/C
|
|
(rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Destination: ext_ram_data[9]
|
|
(output port clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Path Group: sys_clk
|
|
Path Type: Max at Slow Process Corner
|
|
Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns)
|
|
Data Path Delay: 12.714ns (logic 7.373ns (57.992%) route 5.341ns (42.008%))
|
|
Logic Levels: 15 (CARRY4=6 LUT1=1 LUT3=1 LUT4=1 LUT5=1 LUT6=4 OBUFT=1)
|
|
Output Delay: 0.300ns
|
|
Clock Path Skew: -1.695ns (DCD - SCD + CPR)
|
|
Destination Clock Delay (DCD): -4.208ns = ( 15.792 - 20.000 )
|
|
Source Clock Delay (SCD): -3.025ns
|
|
Clock Pessimism Removal (CPR): -0.513ns
|
|
Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Discrete Jitter (DJ): 0.122ns
|
|
Phase Error (PE): 0.000ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock sys_clk rise edge) 0.000 0.000 r
|
|
K21 0.000 0.000 r clk (IN)
|
|
net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1
|
|
K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I
|
|
K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O
|
|
net (fo=1, unplaced) 0.584 2.047 pll_clk.u_clk_pll/inst/clk_in1_clk_pll
|
|
r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1
|
|
PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1)
|
|
-6.768 -4.721 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1
|
|
net (fo=1, unplaced) 0.800 -3.921 pll_clk.u_clk_pll/inst/sys_clk_clk_pll
|
|
r pll_clk.u_clk_pll/inst/clkout2_buf/I
|
|
BUFG (Prop_bufg_I_O) 0.096 -3.825 r pll_clk.u_clk_pll/inst/clkout2_buf/O
|
|
net (fo=10994, unplaced) 0.800 -3.025 u_axi_ram/u_axi_sram_sp/sys_clk
|
|
FDCE r u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[2]/C
|
|
------------------------------------------------------------------- -------------------
|
|
FDCE (Prop_fdce_C_Q) 0.456 -2.569 f u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[2]/Q
|
|
net (fo=56, unplaced) 0.826 -1.743 u_axi_ram/u_axi_sram_sp/len[2]
|
|
f u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6/I1
|
|
LUT4 (Prop_lut4_I1_O) 0.321 -1.422 r u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6/O
|
|
net (fo=4, unplaced) 0.473 -0.949 u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6_n_0
|
|
r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_20/I1
|
|
LUT5 (Prop_lut5_I1_O) 0.124 -0.825 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_20/O
|
|
net (fo=1, unplaced) 0.449 -0.376 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_20_n_0
|
|
r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_19/I5
|
|
LUT6 (Prop_lut6_I5_O) 0.124 -0.252 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_19/O
|
|
net (fo=1, unplaced) 0.000 -0.252 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_19_n_0
|
|
r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/S[0]
|
|
CARRY4 (Prop_carry4_S[0]_CO[3])
|
|
0.532 0.280 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/CO[3]
|
|
net (fo=1, unplaced) 0.000 0.280 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10_n_0
|
|
r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CI
|
|
CARRY4 (Prop_carry4_CI_CO[3])
|
|
0.114 0.394 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CO[3]
|
|
net (fo=1, unplaced) 0.000 0.394 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9_n_0
|
|
r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/CI
|
|
CARRY4 (Prop_carry4_CI_CO[3])
|
|
0.114 0.508 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/CO[3]
|
|
net (fo=1, unplaced) 0.000 0.508 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11_n_0
|
|
r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_10/CI
|
|
CARRY4 (Prop_carry4_CI_CO[3])
|
|
0.114 0.622 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_10/CO[3]
|
|
net (fo=1, unplaced) 0.000 0.622 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_10_n_0
|
|
r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2_i_9/CI
|
|
CARRY4 (Prop_carry4_CI_O[3])
|
|
0.329 0.951 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2_i_9/O[3]
|
|
net (fo=3, unplaced) 0.826 1.777 u_axi_ram/u_axi_sram_sp/upper_wrap_boundary[29]
|
|
r u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1_i_2/I0
|
|
LUT6 (Prop_lut6_I0_O) 0.307 2.084 r u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1_i_2/O
|
|
net (fo=1, unplaced) 0.000 2.084 u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1_i_2_n_0
|
|
r u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1/S[1]
|
|
CARRY4 (Prop_carry4_S[1]_CO[2])
|
|
0.570 2.654 r u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1/CO[2]
|
|
net (fo=23, unplaced) 0.515 3.169 u_axi_ram/u_axi_sram_sp/req_addr_d10_in
|
|
r u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/I5
|
|
LUT6 (Prop_lut6_I5_O) 0.310 3.479 r u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/O
|
|
net (fo=2, unplaced) 0.460 3.939 u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7_n_0
|
|
r u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/I1
|
|
LUT6 (Prop_lut6_I1_O) 0.124 4.063 r u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/O
|
|
net (fo=80, unplaced) 0.543 4.606 u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/soc_sram_addr[0]
|
|
r u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/ext_ram_data_IOBUF[31]_inst_i_2/I2
|
|
LUT3 (Prop_lut3_I2_O) 0.118 4.724 r u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/ext_ram_data_IOBUF[31]_inst_i_2/O
|
|
net (fo=1, unplaced) 0.449 5.173 u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/u_axi_ram/ext_ram_data1
|
|
r u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/ext_ram_data_IOBUF[31]_inst_i_1/I0
|
|
LUT1 (Prop_lut1_I0_O) 0.124 5.297 f u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/ext_ram_data_IOBUF[31]_inst_i_1/O
|
|
net (fo=32, unplaced) 0.800 6.096 ext_ram_data_IOBUF[9]_inst/T
|
|
W25 f ext_ram_data_IOBUF[9]_inst/OBUFT/T
|
|
W25 OBUFT (TriStatE_obuft_T_O)
|
|
3.592 9.688 r ext_ram_data_IOBUF[9]_inst/OBUFT/O
|
|
net (fo=1, unset) 0.000 9.688 ext_ram_data[9]
|
|
W25 r ext_ram_data[9] (INOUT)
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock sys_clk rise edge) 20.000 20.000 r
|
|
K21 0.000 20.000 r clk (IN)
|
|
net (fo=0) 0.000 20.000 pll_clk.u_clk_pll/inst/clk_in1
|
|
K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I
|
|
K21 IBUF (Prop_ibuf_I_O) 1.393 21.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O
|
|
net (fo=1, unplaced) 0.439 21.832 pll_clk.u_clk_pll/inst/clk_in1_clk_pll
|
|
r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1
|
|
PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1)
|
|
-6.040 15.792 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1
|
|
clock pessimism -0.513 15.279
|
|
clock uncertainty -0.071 15.209
|
|
output delay -0.300 14.909
|
|
-------------------------------------------------------------------
|
|
required time 14.909
|
|
arrival time -9.688
|
|
-------------------------------------------------------------------
|
|
slack 5.220
|
|
|
|
Slack (MET) : 5.220ns (required time - arrival time)
|
|
Source: u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[2]/C
|
|
(rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Destination: ext_ram_data[4]
|
|
(output port clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Path Group: sys_clk
|
|
Path Type: Max at Slow Process Corner
|
|
Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns)
|
|
Data Path Delay: 12.714ns (logic 7.373ns (57.992%) route 5.341ns (42.008%))
|
|
Logic Levels: 15 (CARRY4=6 LUT1=1 LUT3=1 LUT4=1 LUT5=1 LUT6=4 OBUFT=1)
|
|
Output Delay: 0.300ns
|
|
Clock Path Skew: -1.695ns (DCD - SCD + CPR)
|
|
Destination Clock Delay (DCD): -4.208ns = ( 15.792 - 20.000 )
|
|
Source Clock Delay (SCD): -3.025ns
|
|
Clock Pessimism Removal (CPR): -0.513ns
|
|
Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Discrete Jitter (DJ): 0.122ns
|
|
Phase Error (PE): 0.000ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock sys_clk rise edge) 0.000 0.000 r
|
|
K21 0.000 0.000 r clk (IN)
|
|
net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1
|
|
K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I
|
|
K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O
|
|
net (fo=1, unplaced) 0.584 2.047 pll_clk.u_clk_pll/inst/clk_in1_clk_pll
|
|
r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1
|
|
PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1)
|
|
-6.768 -4.721 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1
|
|
net (fo=1, unplaced) 0.800 -3.921 pll_clk.u_clk_pll/inst/sys_clk_clk_pll
|
|
r pll_clk.u_clk_pll/inst/clkout2_buf/I
|
|
BUFG (Prop_bufg_I_O) 0.096 -3.825 r pll_clk.u_clk_pll/inst/clkout2_buf/O
|
|
net (fo=10994, unplaced) 0.800 -3.025 u_axi_ram/u_axi_sram_sp/sys_clk
|
|
FDCE r u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[2]/C
|
|
------------------------------------------------------------------- -------------------
|
|
FDCE (Prop_fdce_C_Q) 0.456 -2.569 f u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[2]/Q
|
|
net (fo=56, unplaced) 0.826 -1.743 u_axi_ram/u_axi_sram_sp/len[2]
|
|
f u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6/I1
|
|
LUT4 (Prop_lut4_I1_O) 0.321 -1.422 r u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6/O
|
|
net (fo=4, unplaced) 0.473 -0.949 u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6_n_0
|
|
r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_20/I1
|
|
LUT5 (Prop_lut5_I1_O) 0.124 -0.825 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_20/O
|
|
net (fo=1, unplaced) 0.449 -0.376 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_20_n_0
|
|
r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_19/I5
|
|
LUT6 (Prop_lut6_I5_O) 0.124 -0.252 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_19/O
|
|
net (fo=1, unplaced) 0.000 -0.252 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_19_n_0
|
|
r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/S[0]
|
|
CARRY4 (Prop_carry4_S[0]_CO[3])
|
|
0.532 0.280 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/CO[3]
|
|
net (fo=1, unplaced) 0.000 0.280 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10_n_0
|
|
r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CI
|
|
CARRY4 (Prop_carry4_CI_CO[3])
|
|
0.114 0.394 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CO[3]
|
|
net (fo=1, unplaced) 0.000 0.394 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9_n_0
|
|
r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/CI
|
|
CARRY4 (Prop_carry4_CI_CO[3])
|
|
0.114 0.508 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/CO[3]
|
|
net (fo=1, unplaced) 0.000 0.508 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11_n_0
|
|
r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_10/CI
|
|
CARRY4 (Prop_carry4_CI_CO[3])
|
|
0.114 0.622 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_10/CO[3]
|
|
net (fo=1, unplaced) 0.000 0.622 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_10_n_0
|
|
r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2_i_9/CI
|
|
CARRY4 (Prop_carry4_CI_O[3])
|
|
0.329 0.951 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2_i_9/O[3]
|
|
net (fo=3, unplaced) 0.826 1.777 u_axi_ram/u_axi_sram_sp/upper_wrap_boundary[29]
|
|
r u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1_i_2/I0
|
|
LUT6 (Prop_lut6_I0_O) 0.307 2.084 r u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1_i_2/O
|
|
net (fo=1, unplaced) 0.000 2.084 u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1_i_2_n_0
|
|
r u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1/S[1]
|
|
CARRY4 (Prop_carry4_S[1]_CO[2])
|
|
0.570 2.654 r u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1/CO[2]
|
|
net (fo=23, unplaced) 0.515 3.169 u_axi_ram/u_axi_sram_sp/req_addr_d10_in
|
|
r u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/I5
|
|
LUT6 (Prop_lut6_I5_O) 0.310 3.479 r u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/O
|
|
net (fo=2, unplaced) 0.460 3.939 u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7_n_0
|
|
r u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/I1
|
|
LUT6 (Prop_lut6_I1_O) 0.124 4.063 r u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/O
|
|
net (fo=80, unplaced) 0.543 4.606 u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/soc_sram_addr[0]
|
|
r u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/ext_ram_data_IOBUF[31]_inst_i_2/I2
|
|
LUT3 (Prop_lut3_I2_O) 0.118 4.724 r u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/ext_ram_data_IOBUF[31]_inst_i_2/O
|
|
net (fo=1, unplaced) 0.449 5.173 u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/u_axi_ram/ext_ram_data1
|
|
r u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/ext_ram_data_IOBUF[31]_inst_i_1/I0
|
|
LUT1 (Prop_lut1_I0_O) 0.124 5.297 f u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/ext_ram_data_IOBUF[31]_inst_i_1/O
|
|
net (fo=32, unplaced) 0.800 6.096 ext_ram_data_IOBUF[4]_inst/T
|
|
AF22 f ext_ram_data_IOBUF[4]_inst/OBUFT/T
|
|
AF22 OBUFT (TriStatE_obuft_T_O)
|
|
3.592 9.688 r ext_ram_data_IOBUF[4]_inst/OBUFT/O
|
|
net (fo=1, unset) 0.000 9.688 ext_ram_data[4]
|
|
AF22 r ext_ram_data[4] (INOUT)
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock sys_clk rise edge) 20.000 20.000 r
|
|
K21 0.000 20.000 r clk (IN)
|
|
net (fo=0) 0.000 20.000 pll_clk.u_clk_pll/inst/clk_in1
|
|
K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I
|
|
K21 IBUF (Prop_ibuf_I_O) 1.393 21.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O
|
|
net (fo=1, unplaced) 0.439 21.832 pll_clk.u_clk_pll/inst/clk_in1_clk_pll
|
|
r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1
|
|
PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1)
|
|
-6.040 15.792 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1
|
|
clock pessimism -0.513 15.279
|
|
clock uncertainty -0.071 15.209
|
|
output delay -0.300 14.909
|
|
-------------------------------------------------------------------
|
|
required time 14.909
|
|
arrival time -9.688
|
|
-------------------------------------------------------------------
|
|
slack 5.220
|
|
|
|
Slack (MET) : 5.221ns (required time - arrival time)
|
|
Source: u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[2]/C
|
|
(rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Destination: ext_ram_data[11]
|
|
(output port clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Path Group: sys_clk
|
|
Path Type: Max at Slow Process Corner
|
|
Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns)
|
|
Data Path Delay: 12.713ns (logic 7.373ns (57.991%) route 5.341ns (42.009%))
|
|
Logic Levels: 15 (CARRY4=6 LUT1=1 LUT3=1 LUT4=1 LUT5=1 LUT6=4 OBUFT=1)
|
|
Output Delay: 0.300ns
|
|
Clock Path Skew: -1.695ns (DCD - SCD + CPR)
|
|
Destination Clock Delay (DCD): -4.208ns = ( 15.792 - 20.000 )
|
|
Source Clock Delay (SCD): -3.025ns
|
|
Clock Pessimism Removal (CPR): -0.513ns
|
|
Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Discrete Jitter (DJ): 0.122ns
|
|
Phase Error (PE): 0.000ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock sys_clk rise edge) 0.000 0.000 r
|
|
K21 0.000 0.000 r clk (IN)
|
|
net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1
|
|
K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I
|
|
K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O
|
|
net (fo=1, unplaced) 0.584 2.047 pll_clk.u_clk_pll/inst/clk_in1_clk_pll
|
|
r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1
|
|
PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1)
|
|
-6.768 -4.721 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1
|
|
net (fo=1, unplaced) 0.800 -3.921 pll_clk.u_clk_pll/inst/sys_clk_clk_pll
|
|
r pll_clk.u_clk_pll/inst/clkout2_buf/I
|
|
BUFG (Prop_bufg_I_O) 0.096 -3.825 r pll_clk.u_clk_pll/inst/clkout2_buf/O
|
|
net (fo=10994, unplaced) 0.800 -3.025 u_axi_ram/u_axi_sram_sp/sys_clk
|
|
FDCE r u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[2]/C
|
|
------------------------------------------------------------------- -------------------
|
|
FDCE (Prop_fdce_C_Q) 0.456 -2.569 f u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[2]/Q
|
|
net (fo=56, unplaced) 0.826 -1.743 u_axi_ram/u_axi_sram_sp/len[2]
|
|
f u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6/I1
|
|
LUT4 (Prop_lut4_I1_O) 0.321 -1.422 r u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6/O
|
|
net (fo=4, unplaced) 0.473 -0.949 u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6_n_0
|
|
r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_20/I1
|
|
LUT5 (Prop_lut5_I1_O) 0.124 -0.825 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_20/O
|
|
net (fo=1, unplaced) 0.449 -0.376 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_20_n_0
|
|
r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_19/I5
|
|
LUT6 (Prop_lut6_I5_O) 0.124 -0.252 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_19/O
|
|
net (fo=1, unplaced) 0.000 -0.252 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_19_n_0
|
|
r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/S[0]
|
|
CARRY4 (Prop_carry4_S[0]_CO[3])
|
|
0.532 0.280 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/CO[3]
|
|
net (fo=1, unplaced) 0.000 0.280 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10_n_0
|
|
r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CI
|
|
CARRY4 (Prop_carry4_CI_CO[3])
|
|
0.114 0.394 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CO[3]
|
|
net (fo=1, unplaced) 0.000 0.394 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9_n_0
|
|
r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/CI
|
|
CARRY4 (Prop_carry4_CI_CO[3])
|
|
0.114 0.508 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/CO[3]
|
|
net (fo=1, unplaced) 0.000 0.508 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11_n_0
|
|
r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_10/CI
|
|
CARRY4 (Prop_carry4_CI_CO[3])
|
|
0.114 0.622 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_10/CO[3]
|
|
net (fo=1, unplaced) 0.000 0.622 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_10_n_0
|
|
r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2_i_9/CI
|
|
CARRY4 (Prop_carry4_CI_O[3])
|
|
0.329 0.951 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2_i_9/O[3]
|
|
net (fo=3, unplaced) 0.826 1.777 u_axi_ram/u_axi_sram_sp/upper_wrap_boundary[29]
|
|
r u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1_i_2/I0
|
|
LUT6 (Prop_lut6_I0_O) 0.307 2.084 r u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1_i_2/O
|
|
net (fo=1, unplaced) 0.000 2.084 u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1_i_2_n_0
|
|
r u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1/S[1]
|
|
CARRY4 (Prop_carry4_S[1]_CO[2])
|
|
0.570 2.654 r u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1/CO[2]
|
|
net (fo=23, unplaced) 0.515 3.169 u_axi_ram/u_axi_sram_sp/req_addr_d10_in
|
|
r u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/I5
|
|
LUT6 (Prop_lut6_I5_O) 0.310 3.479 r u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/O
|
|
net (fo=2, unplaced) 0.460 3.939 u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7_n_0
|
|
r u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/I1
|
|
LUT6 (Prop_lut6_I1_O) 0.124 4.063 r u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/O
|
|
net (fo=80, unplaced) 0.543 4.606 u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/soc_sram_addr[0]
|
|
r u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/ext_ram_data_IOBUF[31]_inst_i_2/I2
|
|
LUT3 (Prop_lut3_I2_O) 0.118 4.724 r u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/ext_ram_data_IOBUF[31]_inst_i_2/O
|
|
net (fo=1, unplaced) 0.449 5.173 u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/u_axi_ram/ext_ram_data1
|
|
r u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/ext_ram_data_IOBUF[31]_inst_i_1/I0
|
|
LUT1 (Prop_lut1_I0_O) 0.124 5.297 f u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/ext_ram_data_IOBUF[31]_inst_i_1/O
|
|
net (fo=32, unplaced) 0.800 6.096 ext_ram_data_IOBUF[11]_inst/T
|
|
V24 f ext_ram_data_IOBUF[11]_inst/OBUFT/T
|
|
V24 OBUFT (TriStatE_obuft_T_O)
|
|
3.592 9.688 r ext_ram_data_IOBUF[11]_inst/OBUFT/O
|
|
net (fo=1, unset) 0.000 9.688 ext_ram_data[11]
|
|
V24 r ext_ram_data[11] (INOUT)
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock sys_clk rise edge) 20.000 20.000 r
|
|
K21 0.000 20.000 r clk (IN)
|
|
net (fo=0) 0.000 20.000 pll_clk.u_clk_pll/inst/clk_in1
|
|
K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I
|
|
K21 IBUF (Prop_ibuf_I_O) 1.393 21.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O
|
|
net (fo=1, unplaced) 0.439 21.832 pll_clk.u_clk_pll/inst/clk_in1_clk_pll
|
|
r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1
|
|
PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1)
|
|
-6.040 15.792 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1
|
|
clock pessimism -0.513 15.279
|
|
clock uncertainty -0.071 15.209
|
|
output delay -0.300 14.909
|
|
-------------------------------------------------------------------
|
|
required time 14.909
|
|
arrival time -9.688
|
|
-------------------------------------------------------------------
|
|
slack 5.221
|
|
|
|
Slack (MET) : 5.222ns (required time - arrival time)
|
|
Source: u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[2]/C
|
|
(rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Destination: ext_ram_data[7]
|
|
(output port clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Path Group: sys_clk
|
|
Path Type: Max at Slow Process Corner
|
|
Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns)
|
|
Data Path Delay: 12.712ns (logic 7.371ns (57.987%) route 5.341ns (42.013%))
|
|
Logic Levels: 15 (CARRY4=6 LUT1=1 LUT3=1 LUT4=1 LUT5=1 LUT6=4 OBUFT=1)
|
|
Output Delay: 0.300ns
|
|
Clock Path Skew: -1.695ns (DCD - SCD + CPR)
|
|
Destination Clock Delay (DCD): -4.208ns = ( 15.792 - 20.000 )
|
|
Source Clock Delay (SCD): -3.025ns
|
|
Clock Pessimism Removal (CPR): -0.513ns
|
|
Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Discrete Jitter (DJ): 0.122ns
|
|
Phase Error (PE): 0.000ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock sys_clk rise edge) 0.000 0.000 r
|
|
K21 0.000 0.000 r clk (IN)
|
|
net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1
|
|
K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I
|
|
K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O
|
|
net (fo=1, unplaced) 0.584 2.047 pll_clk.u_clk_pll/inst/clk_in1_clk_pll
|
|
r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1
|
|
PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1)
|
|
-6.768 -4.721 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1
|
|
net (fo=1, unplaced) 0.800 -3.921 pll_clk.u_clk_pll/inst/sys_clk_clk_pll
|
|
r pll_clk.u_clk_pll/inst/clkout2_buf/I
|
|
BUFG (Prop_bufg_I_O) 0.096 -3.825 r pll_clk.u_clk_pll/inst/clkout2_buf/O
|
|
net (fo=10994, unplaced) 0.800 -3.025 u_axi_ram/u_axi_sram_sp/sys_clk
|
|
FDCE r u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[2]/C
|
|
------------------------------------------------------------------- -------------------
|
|
FDCE (Prop_fdce_C_Q) 0.456 -2.569 f u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[2]/Q
|
|
net (fo=56, unplaced) 0.826 -1.743 u_axi_ram/u_axi_sram_sp/len[2]
|
|
f u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6/I1
|
|
LUT4 (Prop_lut4_I1_O) 0.321 -1.422 r u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6/O
|
|
net (fo=4, unplaced) 0.473 -0.949 u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6_n_0
|
|
r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_20/I1
|
|
LUT5 (Prop_lut5_I1_O) 0.124 -0.825 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_20/O
|
|
net (fo=1, unplaced) 0.449 -0.376 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_20_n_0
|
|
r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_19/I5
|
|
LUT6 (Prop_lut6_I5_O) 0.124 -0.252 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_19/O
|
|
net (fo=1, unplaced) 0.000 -0.252 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_19_n_0
|
|
r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/S[0]
|
|
CARRY4 (Prop_carry4_S[0]_CO[3])
|
|
0.532 0.280 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/CO[3]
|
|
net (fo=1, unplaced) 0.000 0.280 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10_n_0
|
|
r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CI
|
|
CARRY4 (Prop_carry4_CI_CO[3])
|
|
0.114 0.394 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CO[3]
|
|
net (fo=1, unplaced) 0.000 0.394 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9_n_0
|
|
r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/CI
|
|
CARRY4 (Prop_carry4_CI_CO[3])
|
|
0.114 0.508 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/CO[3]
|
|
net (fo=1, unplaced) 0.000 0.508 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11_n_0
|
|
r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_10/CI
|
|
CARRY4 (Prop_carry4_CI_CO[3])
|
|
0.114 0.622 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_10/CO[3]
|
|
net (fo=1, unplaced) 0.000 0.622 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_10_n_0
|
|
r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2_i_9/CI
|
|
CARRY4 (Prop_carry4_CI_O[3])
|
|
0.329 0.951 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2_i_9/O[3]
|
|
net (fo=3, unplaced) 0.826 1.777 u_axi_ram/u_axi_sram_sp/upper_wrap_boundary[29]
|
|
r u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1_i_2/I0
|
|
LUT6 (Prop_lut6_I0_O) 0.307 2.084 r u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1_i_2/O
|
|
net (fo=1, unplaced) 0.000 2.084 u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1_i_2_n_0
|
|
r u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1/S[1]
|
|
CARRY4 (Prop_carry4_S[1]_CO[2])
|
|
0.570 2.654 r u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1/CO[2]
|
|
net (fo=23, unplaced) 0.515 3.169 u_axi_ram/u_axi_sram_sp/req_addr_d10_in
|
|
r u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/I5
|
|
LUT6 (Prop_lut6_I5_O) 0.310 3.479 r u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/O
|
|
net (fo=2, unplaced) 0.460 3.939 u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7_n_0
|
|
r u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/I1
|
|
LUT6 (Prop_lut6_I1_O) 0.124 4.063 r u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/O
|
|
net (fo=80, unplaced) 0.543 4.606 u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/soc_sram_addr[0]
|
|
r u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/ext_ram_data_IOBUF[31]_inst_i_2/I2
|
|
LUT3 (Prop_lut3_I2_O) 0.118 4.724 r u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/ext_ram_data_IOBUF[31]_inst_i_2/O
|
|
net (fo=1, unplaced) 0.449 5.173 u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/u_axi_ram/ext_ram_data1
|
|
r u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/ext_ram_data_IOBUF[31]_inst_i_1/I0
|
|
LUT1 (Prop_lut1_I0_O) 0.124 5.297 f u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/ext_ram_data_IOBUF[31]_inst_i_1/O
|
|
net (fo=32, unplaced) 0.800 6.096 ext_ram_data_IOBUF[7]_inst/T
|
|
AF20 f ext_ram_data_IOBUF[7]_inst/OBUFT/T
|
|
AF20 OBUFT (TriStatE_obuft_T_O)
|
|
3.590 9.687 r ext_ram_data_IOBUF[7]_inst/OBUFT/O
|
|
net (fo=1, unset) 0.000 9.687 ext_ram_data[7]
|
|
AF20 r ext_ram_data[7] (INOUT)
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock sys_clk rise edge) 20.000 20.000 r
|
|
K21 0.000 20.000 r clk (IN)
|
|
net (fo=0) 0.000 20.000 pll_clk.u_clk_pll/inst/clk_in1
|
|
K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I
|
|
K21 IBUF (Prop_ibuf_I_O) 1.393 21.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O
|
|
net (fo=1, unplaced) 0.439 21.832 pll_clk.u_clk_pll/inst/clk_in1_clk_pll
|
|
r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1
|
|
PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1)
|
|
-6.040 15.792 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1
|
|
clock pessimism -0.513 15.279
|
|
clock uncertainty -0.071 15.209
|
|
output delay -0.300 14.909
|
|
-------------------------------------------------------------------
|
|
required time 14.909
|
|
arrival time -9.687
|
|
-------------------------------------------------------------------
|
|
slack 5.222
|
|
|
|
Slack (MET) : 5.223ns (required time - arrival time)
|
|
Source: u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[2]/C
|
|
(rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Destination: ext_ram_data[8]
|
|
(output port clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Path Group: sys_clk
|
|
Path Type: Max at Slow Process Corner
|
|
Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns)
|
|
Data Path Delay: 12.711ns (logic 7.370ns (57.983%) route 5.341ns (42.017%))
|
|
Logic Levels: 15 (CARRY4=6 LUT1=1 LUT3=1 LUT4=1 LUT5=1 LUT6=4 OBUFT=1)
|
|
Output Delay: 0.300ns
|
|
Clock Path Skew: -1.695ns (DCD - SCD + CPR)
|
|
Destination Clock Delay (DCD): -4.208ns = ( 15.792 - 20.000 )
|
|
Source Clock Delay (SCD): -3.025ns
|
|
Clock Pessimism Removal (CPR): -0.513ns
|
|
Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Discrete Jitter (DJ): 0.122ns
|
|
Phase Error (PE): 0.000ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock sys_clk rise edge) 0.000 0.000 r
|
|
K21 0.000 0.000 r clk (IN)
|
|
net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1
|
|
K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I
|
|
K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O
|
|
net (fo=1, unplaced) 0.584 2.047 pll_clk.u_clk_pll/inst/clk_in1_clk_pll
|
|
r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1
|
|
PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1)
|
|
-6.768 -4.721 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1
|
|
net (fo=1, unplaced) 0.800 -3.921 pll_clk.u_clk_pll/inst/sys_clk_clk_pll
|
|
r pll_clk.u_clk_pll/inst/clkout2_buf/I
|
|
BUFG (Prop_bufg_I_O) 0.096 -3.825 r pll_clk.u_clk_pll/inst/clkout2_buf/O
|
|
net (fo=10994, unplaced) 0.800 -3.025 u_axi_ram/u_axi_sram_sp/sys_clk
|
|
FDCE r u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[2]/C
|
|
------------------------------------------------------------------- -------------------
|
|
FDCE (Prop_fdce_C_Q) 0.456 -2.569 f u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[2]/Q
|
|
net (fo=56, unplaced) 0.826 -1.743 u_axi_ram/u_axi_sram_sp/len[2]
|
|
f u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6/I1
|
|
LUT4 (Prop_lut4_I1_O) 0.321 -1.422 r u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6/O
|
|
net (fo=4, unplaced) 0.473 -0.949 u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6_n_0
|
|
r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_20/I1
|
|
LUT5 (Prop_lut5_I1_O) 0.124 -0.825 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_20/O
|
|
net (fo=1, unplaced) 0.449 -0.376 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_20_n_0
|
|
r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_19/I5
|
|
LUT6 (Prop_lut6_I5_O) 0.124 -0.252 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_19/O
|
|
net (fo=1, unplaced) 0.000 -0.252 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_19_n_0
|
|
r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/S[0]
|
|
CARRY4 (Prop_carry4_S[0]_CO[3])
|
|
0.532 0.280 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/CO[3]
|
|
net (fo=1, unplaced) 0.000 0.280 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10_n_0
|
|
r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CI
|
|
CARRY4 (Prop_carry4_CI_CO[3])
|
|
0.114 0.394 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CO[3]
|
|
net (fo=1, unplaced) 0.000 0.394 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9_n_0
|
|
r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/CI
|
|
CARRY4 (Prop_carry4_CI_CO[3])
|
|
0.114 0.508 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/CO[3]
|
|
net (fo=1, unplaced) 0.000 0.508 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11_n_0
|
|
r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_10/CI
|
|
CARRY4 (Prop_carry4_CI_CO[3])
|
|
0.114 0.622 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_10/CO[3]
|
|
net (fo=1, unplaced) 0.000 0.622 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_10_n_0
|
|
r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2_i_9/CI
|
|
CARRY4 (Prop_carry4_CI_O[3])
|
|
0.329 0.951 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2_i_9/O[3]
|
|
net (fo=3, unplaced) 0.826 1.777 u_axi_ram/u_axi_sram_sp/upper_wrap_boundary[29]
|
|
r u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1_i_2/I0
|
|
LUT6 (Prop_lut6_I0_O) 0.307 2.084 r u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1_i_2/O
|
|
net (fo=1, unplaced) 0.000 2.084 u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1_i_2_n_0
|
|
r u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1/S[1]
|
|
CARRY4 (Prop_carry4_S[1]_CO[2])
|
|
0.570 2.654 r u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1/CO[2]
|
|
net (fo=23, unplaced) 0.515 3.169 u_axi_ram/u_axi_sram_sp/req_addr_d10_in
|
|
r u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/I5
|
|
LUT6 (Prop_lut6_I5_O) 0.310 3.479 r u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/O
|
|
net (fo=2, unplaced) 0.460 3.939 u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7_n_0
|
|
r u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/I1
|
|
LUT6 (Prop_lut6_I1_O) 0.124 4.063 r u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/O
|
|
net (fo=80, unplaced) 0.543 4.606 u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/soc_sram_addr[0]
|
|
r u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/ext_ram_data_IOBUF[31]_inst_i_2/I2
|
|
LUT3 (Prop_lut3_I2_O) 0.118 4.724 r u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/ext_ram_data_IOBUF[31]_inst_i_2/O
|
|
net (fo=1, unplaced) 0.449 5.173 u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/u_axi_ram/ext_ram_data1
|
|
r u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/ext_ram_data_IOBUF[31]_inst_i_1/I0
|
|
LUT1 (Prop_lut1_I0_O) 0.124 5.297 f u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/ext_ram_data_IOBUF[31]_inst_i_1/O
|
|
net (fo=32, unplaced) 0.800 6.096 ext_ram_data_IOBUF[8]_inst/T
|
|
Y26 f ext_ram_data_IOBUF[8]_inst/OBUFT/T
|
|
Y26 OBUFT (TriStatE_obuft_T_O)
|
|
3.589 9.685 r ext_ram_data_IOBUF[8]_inst/OBUFT/O
|
|
net (fo=1, unset) 0.000 9.685 ext_ram_data[8]
|
|
Y26 r ext_ram_data[8] (INOUT)
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock sys_clk rise edge) 20.000 20.000 r
|
|
K21 0.000 20.000 r clk (IN)
|
|
net (fo=0) 0.000 20.000 pll_clk.u_clk_pll/inst/clk_in1
|
|
K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I
|
|
K21 IBUF (Prop_ibuf_I_O) 1.393 21.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O
|
|
net (fo=1, unplaced) 0.439 21.832 pll_clk.u_clk_pll/inst/clk_in1_clk_pll
|
|
r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1
|
|
PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1)
|
|
-6.040 15.792 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1
|
|
clock pessimism -0.513 15.279
|
|
clock uncertainty -0.071 15.209
|
|
output delay -0.300 14.909
|
|
-------------------------------------------------------------------
|
|
required time 14.909
|
|
arrival time -9.685
|
|
-------------------------------------------------------------------
|
|
slack 5.223
|
|
|
|
Slack (MET) : 5.227ns (required time - arrival time)
|
|
Source: u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[2]/C
|
|
(rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Destination: base_ram_data[2]
|
|
(output port clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Path Group: sys_clk
|
|
Path Type: Max at Slow Process Corner
|
|
Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns)
|
|
Data Path Delay: 12.707ns (logic 7.366ns (57.970%) route 5.341ns (42.030%))
|
|
Logic Levels: 15 (CARRY4=6 LUT1=1 LUT3=1 LUT4=1 LUT5=1 LUT6=4 OBUFT=1)
|
|
Output Delay: 0.300ns
|
|
Clock Path Skew: -1.695ns (DCD - SCD + CPR)
|
|
Destination Clock Delay (DCD): -4.208ns = ( 15.792 - 20.000 )
|
|
Source Clock Delay (SCD): -3.025ns
|
|
Clock Pessimism Removal (CPR): -0.513ns
|
|
Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Discrete Jitter (DJ): 0.122ns
|
|
Phase Error (PE): 0.000ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock sys_clk rise edge) 0.000 0.000 r
|
|
K21 0.000 0.000 r clk (IN)
|
|
net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1
|
|
K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I
|
|
K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O
|
|
net (fo=1, unplaced) 0.584 2.047 pll_clk.u_clk_pll/inst/clk_in1_clk_pll
|
|
r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1
|
|
PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1)
|
|
-6.768 -4.721 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1
|
|
net (fo=1, unplaced) 0.800 -3.921 pll_clk.u_clk_pll/inst/sys_clk_clk_pll
|
|
r pll_clk.u_clk_pll/inst/clkout2_buf/I
|
|
BUFG (Prop_bufg_I_O) 0.096 -3.825 r pll_clk.u_clk_pll/inst/clkout2_buf/O
|
|
net (fo=10994, unplaced) 0.800 -3.025 u_axi_ram/u_axi_sram_sp/sys_clk
|
|
FDCE r u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[2]/C
|
|
------------------------------------------------------------------- -------------------
|
|
FDCE (Prop_fdce_C_Q) 0.456 -2.569 f u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[2]/Q
|
|
net (fo=56, unplaced) 0.826 -1.743 u_axi_ram/u_axi_sram_sp/len[2]
|
|
f u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6/I1
|
|
LUT4 (Prop_lut4_I1_O) 0.321 -1.422 r u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6/O
|
|
net (fo=4, unplaced) 0.473 -0.949 u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6_n_0
|
|
r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_20/I1
|
|
LUT5 (Prop_lut5_I1_O) 0.124 -0.825 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_20/O
|
|
net (fo=1, unplaced) 0.449 -0.376 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_20_n_0
|
|
r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_19/I5
|
|
LUT6 (Prop_lut6_I5_O) 0.124 -0.252 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_19/O
|
|
net (fo=1, unplaced) 0.000 -0.252 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_19_n_0
|
|
r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/S[0]
|
|
CARRY4 (Prop_carry4_S[0]_CO[3])
|
|
0.532 0.280 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/CO[3]
|
|
net (fo=1, unplaced) 0.000 0.280 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10_n_0
|
|
r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CI
|
|
CARRY4 (Prop_carry4_CI_CO[3])
|
|
0.114 0.394 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CO[3]
|
|
net (fo=1, unplaced) 0.000 0.394 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9_n_0
|
|
r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/CI
|
|
CARRY4 (Prop_carry4_CI_CO[3])
|
|
0.114 0.508 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/CO[3]
|
|
net (fo=1, unplaced) 0.000 0.508 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11_n_0
|
|
r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_10/CI
|
|
CARRY4 (Prop_carry4_CI_CO[3])
|
|
0.114 0.622 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_10/CO[3]
|
|
net (fo=1, unplaced) 0.000 0.622 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_10_n_0
|
|
r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2_i_9/CI
|
|
CARRY4 (Prop_carry4_CI_O[3])
|
|
0.329 0.951 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2_i_9/O[3]
|
|
net (fo=3, unplaced) 0.826 1.777 u_axi_ram/u_axi_sram_sp/upper_wrap_boundary[29]
|
|
r u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1_i_2/I0
|
|
LUT6 (Prop_lut6_I0_O) 0.307 2.084 r u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1_i_2/O
|
|
net (fo=1, unplaced) 0.000 2.084 u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1_i_2_n_0
|
|
r u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1/S[1]
|
|
CARRY4 (Prop_carry4_S[1]_CO[2])
|
|
0.570 2.654 r u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1/CO[2]
|
|
net (fo=23, unplaced) 0.515 3.169 u_axi_ram/u_axi_sram_sp/req_addr_d10_in
|
|
r u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/I5
|
|
LUT6 (Prop_lut6_I5_O) 0.310 3.479 f u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/O
|
|
net (fo=2, unplaced) 0.460 3.939 u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7_n_0
|
|
f u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/I1
|
|
LUT6 (Prop_lut6_I1_O) 0.124 4.063 f u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/O
|
|
net (fo=80, unplaced) 0.543 4.606 u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/soc_sram_addr[0]
|
|
f u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/base_ram_data_IOBUF[31]_inst_i_3/I2
|
|
LUT3 (Prop_lut3_I2_O) 0.124 4.730 r u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/base_ram_data_IOBUF[31]_inst_i_3/O
|
|
net (fo=1, unplaced) 0.449 5.179 u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/u_axi_ram/base_ram_data1
|
|
r u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/base_ram_data_IOBUF[31]_inst_i_2/I0
|
|
LUT1 (Prop_lut1_I0_O) 0.124 5.303 f u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/base_ram_data_IOBUF[31]_inst_i_2/O
|
|
net (fo=32, unplaced) 0.800 6.102 base_ram_data_IOBUF[2]_inst/T
|
|
M26 f base_ram_data_IOBUF[2]_inst/OBUFT/T
|
|
M26 OBUFT (TriStatE_obuft_T_O)
|
|
3.579 9.682 r base_ram_data_IOBUF[2]_inst/OBUFT/O
|
|
net (fo=1, unset) 0.000 9.682 base_ram_data[2]
|
|
M26 r base_ram_data[2] (INOUT)
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock sys_clk rise edge) 20.000 20.000 r
|
|
K21 0.000 20.000 r clk (IN)
|
|
net (fo=0) 0.000 20.000 pll_clk.u_clk_pll/inst/clk_in1
|
|
K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I
|
|
K21 IBUF (Prop_ibuf_I_O) 1.393 21.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O
|
|
net (fo=1, unplaced) 0.439 21.832 pll_clk.u_clk_pll/inst/clk_in1_clk_pll
|
|
r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1
|
|
PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1)
|
|
-6.040 15.792 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1
|
|
clock pessimism -0.513 15.279
|
|
clock uncertainty -0.071 15.209
|
|
output delay -0.300 14.909
|
|
-------------------------------------------------------------------
|
|
required time 14.909
|
|
arrival time -9.682
|
|
-------------------------------------------------------------------
|
|
slack 5.227
|
|
|
|
Slack (MET) : 5.229ns (required time - arrival time)
|
|
Source: u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[2]/C
|
|
(rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Destination: ext_ram_data[1]
|
|
(output port clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Path Group: sys_clk
|
|
Path Type: Max at Slow Process Corner
|
|
Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns)
|
|
Data Path Delay: 12.705ns (logic 7.364ns (57.964%) route 5.341ns (42.036%))
|
|
Logic Levels: 15 (CARRY4=6 LUT1=1 LUT3=1 LUT4=1 LUT5=1 LUT6=4 OBUFT=1)
|
|
Output Delay: 0.300ns
|
|
Clock Path Skew: -1.695ns (DCD - SCD + CPR)
|
|
Destination Clock Delay (DCD): -4.208ns = ( 15.792 - 20.000 )
|
|
Source Clock Delay (SCD): -3.025ns
|
|
Clock Pessimism Removal (CPR): -0.513ns
|
|
Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Discrete Jitter (DJ): 0.122ns
|
|
Phase Error (PE): 0.000ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock sys_clk rise edge) 0.000 0.000 r
|
|
K21 0.000 0.000 r clk (IN)
|
|
net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1
|
|
K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I
|
|
K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O
|
|
net (fo=1, unplaced) 0.584 2.047 pll_clk.u_clk_pll/inst/clk_in1_clk_pll
|
|
r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1
|
|
PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1)
|
|
-6.768 -4.721 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1
|
|
net (fo=1, unplaced) 0.800 -3.921 pll_clk.u_clk_pll/inst/sys_clk_clk_pll
|
|
r pll_clk.u_clk_pll/inst/clkout2_buf/I
|
|
BUFG (Prop_bufg_I_O) 0.096 -3.825 r pll_clk.u_clk_pll/inst/clkout2_buf/O
|
|
net (fo=10994, unplaced) 0.800 -3.025 u_axi_ram/u_axi_sram_sp/sys_clk
|
|
FDCE r u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[2]/C
|
|
------------------------------------------------------------------- -------------------
|
|
FDCE (Prop_fdce_C_Q) 0.456 -2.569 f u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[2]/Q
|
|
net (fo=56, unplaced) 0.826 -1.743 u_axi_ram/u_axi_sram_sp/len[2]
|
|
f u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6/I1
|
|
LUT4 (Prop_lut4_I1_O) 0.321 -1.422 r u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6/O
|
|
net (fo=4, unplaced) 0.473 -0.949 u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6_n_0
|
|
r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_20/I1
|
|
LUT5 (Prop_lut5_I1_O) 0.124 -0.825 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_20/O
|
|
net (fo=1, unplaced) 0.449 -0.376 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_20_n_0
|
|
r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_19/I5
|
|
LUT6 (Prop_lut6_I5_O) 0.124 -0.252 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_19/O
|
|
net (fo=1, unplaced) 0.000 -0.252 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_19_n_0
|
|
r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/S[0]
|
|
CARRY4 (Prop_carry4_S[0]_CO[3])
|
|
0.532 0.280 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/CO[3]
|
|
net (fo=1, unplaced) 0.000 0.280 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10_n_0
|
|
r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CI
|
|
CARRY4 (Prop_carry4_CI_CO[3])
|
|
0.114 0.394 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CO[3]
|
|
net (fo=1, unplaced) 0.000 0.394 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9_n_0
|
|
r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/CI
|
|
CARRY4 (Prop_carry4_CI_CO[3])
|
|
0.114 0.508 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/CO[3]
|
|
net (fo=1, unplaced) 0.000 0.508 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11_n_0
|
|
r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_10/CI
|
|
CARRY4 (Prop_carry4_CI_CO[3])
|
|
0.114 0.622 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_10/CO[3]
|
|
net (fo=1, unplaced) 0.000 0.622 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_10_n_0
|
|
r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2_i_9/CI
|
|
CARRY4 (Prop_carry4_CI_O[3])
|
|
0.329 0.951 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2_i_9/O[3]
|
|
net (fo=3, unplaced) 0.826 1.777 u_axi_ram/u_axi_sram_sp/upper_wrap_boundary[29]
|
|
r u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1_i_2/I0
|
|
LUT6 (Prop_lut6_I0_O) 0.307 2.084 r u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1_i_2/O
|
|
net (fo=1, unplaced) 0.000 2.084 u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1_i_2_n_0
|
|
r u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1/S[1]
|
|
CARRY4 (Prop_carry4_S[1]_CO[2])
|
|
0.570 2.654 r u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1/CO[2]
|
|
net (fo=23, unplaced) 0.515 3.169 u_axi_ram/u_axi_sram_sp/req_addr_d10_in
|
|
r u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/I5
|
|
LUT6 (Prop_lut6_I5_O) 0.310 3.479 r u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/O
|
|
net (fo=2, unplaced) 0.460 3.939 u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7_n_0
|
|
r u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/I1
|
|
LUT6 (Prop_lut6_I1_O) 0.124 4.063 r u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/O
|
|
net (fo=80, unplaced) 0.543 4.606 u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/soc_sram_addr[0]
|
|
r u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/ext_ram_data_IOBUF[31]_inst_i_2/I2
|
|
LUT3 (Prop_lut3_I2_O) 0.118 4.724 r u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/ext_ram_data_IOBUF[31]_inst_i_2/O
|
|
net (fo=1, unplaced) 0.449 5.173 u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/u_axi_ram/ext_ram_data1
|
|
r u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/ext_ram_data_IOBUF[31]_inst_i_1/I0
|
|
LUT1 (Prop_lut1_I0_O) 0.124 5.297 f u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/ext_ram_data_IOBUF[31]_inst_i_1/O
|
|
net (fo=32, unplaced) 0.800 6.096 ext_ram_data_IOBUF[1]_inst/T
|
|
AE23 f ext_ram_data_IOBUF[1]_inst/OBUFT/T
|
|
AE23 OBUFT (TriStatE_obuft_T_O)
|
|
3.583 9.680 r ext_ram_data_IOBUF[1]_inst/OBUFT/O
|
|
net (fo=1, unset) 0.000 9.680 ext_ram_data[1]
|
|
AE23 r ext_ram_data[1] (INOUT)
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock sys_clk rise edge) 20.000 20.000 r
|
|
K21 0.000 20.000 r clk (IN)
|
|
net (fo=0) 0.000 20.000 pll_clk.u_clk_pll/inst/clk_in1
|
|
K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I
|
|
K21 IBUF (Prop_ibuf_I_O) 1.393 21.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O
|
|
net (fo=1, unplaced) 0.439 21.832 pll_clk.u_clk_pll/inst/clk_in1_clk_pll
|
|
r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1
|
|
PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1)
|
|
-6.040 15.792 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1
|
|
clock pessimism -0.513 15.279
|
|
clock uncertainty -0.071 15.209
|
|
output delay -0.300 14.909
|
|
-------------------------------------------------------------------
|
|
required time 14.909
|
|
arrival time -9.680
|
|
-------------------------------------------------------------------
|
|
slack 5.229
|
|
|
|
Slack (MET) : 5.230ns (required time - arrival time)
|
|
Source: u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[2]/C
|
|
(rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Destination: ext_ram_data[10]
|
|
(output port clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Path Group: sys_clk
|
|
Path Type: Max at Slow Process Corner
|
|
Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns)
|
|
Data Path Delay: 12.704ns (logic 7.364ns (57.962%) route 5.341ns (42.038%))
|
|
Logic Levels: 15 (CARRY4=6 LUT1=1 LUT3=1 LUT4=1 LUT5=1 LUT6=4 OBUFT=1)
|
|
Output Delay: 0.300ns
|
|
Clock Path Skew: -1.695ns (DCD - SCD + CPR)
|
|
Destination Clock Delay (DCD): -4.208ns = ( 15.792 - 20.000 )
|
|
Source Clock Delay (SCD): -3.025ns
|
|
Clock Pessimism Removal (CPR): -0.513ns
|
|
Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Discrete Jitter (DJ): 0.122ns
|
|
Phase Error (PE): 0.000ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock sys_clk rise edge) 0.000 0.000 r
|
|
K21 0.000 0.000 r clk (IN)
|
|
net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1
|
|
K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I
|
|
K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O
|
|
net (fo=1, unplaced) 0.584 2.047 pll_clk.u_clk_pll/inst/clk_in1_clk_pll
|
|
r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1
|
|
PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1)
|
|
-6.768 -4.721 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1
|
|
net (fo=1, unplaced) 0.800 -3.921 pll_clk.u_clk_pll/inst/sys_clk_clk_pll
|
|
r pll_clk.u_clk_pll/inst/clkout2_buf/I
|
|
BUFG (Prop_bufg_I_O) 0.096 -3.825 r pll_clk.u_clk_pll/inst/clkout2_buf/O
|
|
net (fo=10994, unplaced) 0.800 -3.025 u_axi_ram/u_axi_sram_sp/sys_clk
|
|
FDCE r u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[2]/C
|
|
------------------------------------------------------------------- -------------------
|
|
FDCE (Prop_fdce_C_Q) 0.456 -2.569 f u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[2]/Q
|
|
net (fo=56, unplaced) 0.826 -1.743 u_axi_ram/u_axi_sram_sp/len[2]
|
|
f u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6/I1
|
|
LUT4 (Prop_lut4_I1_O) 0.321 -1.422 r u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6/O
|
|
net (fo=4, unplaced) 0.473 -0.949 u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6_n_0
|
|
r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_20/I1
|
|
LUT5 (Prop_lut5_I1_O) 0.124 -0.825 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_20/O
|
|
net (fo=1, unplaced) 0.449 -0.376 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_20_n_0
|
|
r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_19/I5
|
|
LUT6 (Prop_lut6_I5_O) 0.124 -0.252 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_19/O
|
|
net (fo=1, unplaced) 0.000 -0.252 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_19_n_0
|
|
r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/S[0]
|
|
CARRY4 (Prop_carry4_S[0]_CO[3])
|
|
0.532 0.280 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/CO[3]
|
|
net (fo=1, unplaced) 0.000 0.280 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10_n_0
|
|
r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CI
|
|
CARRY4 (Prop_carry4_CI_CO[3])
|
|
0.114 0.394 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CO[3]
|
|
net (fo=1, unplaced) 0.000 0.394 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9_n_0
|
|
r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/CI
|
|
CARRY4 (Prop_carry4_CI_CO[3])
|
|
0.114 0.508 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/CO[3]
|
|
net (fo=1, unplaced) 0.000 0.508 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11_n_0
|
|
r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_10/CI
|
|
CARRY4 (Prop_carry4_CI_CO[3])
|
|
0.114 0.622 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_10/CO[3]
|
|
net (fo=1, unplaced) 0.000 0.622 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_10_n_0
|
|
r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2_i_9/CI
|
|
CARRY4 (Prop_carry4_CI_O[3])
|
|
0.329 0.951 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2_i_9/O[3]
|
|
net (fo=3, unplaced) 0.826 1.777 u_axi_ram/u_axi_sram_sp/upper_wrap_boundary[29]
|
|
r u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1_i_2/I0
|
|
LUT6 (Prop_lut6_I0_O) 0.307 2.084 r u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1_i_2/O
|
|
net (fo=1, unplaced) 0.000 2.084 u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1_i_2_n_0
|
|
r u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1/S[1]
|
|
CARRY4 (Prop_carry4_S[1]_CO[2])
|
|
0.570 2.654 r u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1/CO[2]
|
|
net (fo=23, unplaced) 0.515 3.169 u_axi_ram/u_axi_sram_sp/req_addr_d10_in
|
|
r u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/I5
|
|
LUT6 (Prop_lut6_I5_O) 0.310 3.479 r u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/O
|
|
net (fo=2, unplaced) 0.460 3.939 u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7_n_0
|
|
r u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/I1
|
|
LUT6 (Prop_lut6_I1_O) 0.124 4.063 r u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/O
|
|
net (fo=80, unplaced) 0.543 4.606 u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/soc_sram_addr[0]
|
|
r u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/ext_ram_data_IOBUF[31]_inst_i_2/I2
|
|
LUT3 (Prop_lut3_I2_O) 0.118 4.724 r u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/ext_ram_data_IOBUF[31]_inst_i_2/O
|
|
net (fo=1, unplaced) 0.449 5.173 u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/u_axi_ram/ext_ram_data1
|
|
r u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/ext_ram_data_IOBUF[31]_inst_i_1/I0
|
|
LUT1 (Prop_lut1_I0_O) 0.124 5.297 f u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/ext_ram_data_IOBUF[31]_inst_i_1/O
|
|
net (fo=32, unplaced) 0.800 6.096 ext_ram_data_IOBUF[10]_inst/T
|
|
W26 f ext_ram_data_IOBUF[10]_inst/OBUFT/T
|
|
W26 OBUFT (TriStatE_obuft_T_O)
|
|
3.583 9.679 r ext_ram_data_IOBUF[10]_inst/OBUFT/O
|
|
net (fo=1, unset) 0.000 9.679 ext_ram_data[10]
|
|
W26 r ext_ram_data[10] (INOUT)
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock sys_clk rise edge) 20.000 20.000 r
|
|
K21 0.000 20.000 r clk (IN)
|
|
net (fo=0) 0.000 20.000 pll_clk.u_clk_pll/inst/clk_in1
|
|
K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I
|
|
K21 IBUF (Prop_ibuf_I_O) 1.393 21.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O
|
|
net (fo=1, unplaced) 0.439 21.832 pll_clk.u_clk_pll/inst/clk_in1_clk_pll
|
|
r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1
|
|
PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1)
|
|
-6.040 15.792 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1
|
|
clock pessimism -0.513 15.279
|
|
clock uncertainty -0.071 15.209
|
|
output delay -0.300 14.909
|
|
-------------------------------------------------------------------
|
|
required time 14.909
|
|
arrival time -9.679
|
|
-------------------------------------------------------------------
|
|
slack 5.230
|
|
|
|
Slack (MET) : 5.233ns (required time - arrival time)
|
|
Source: u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[2]/C
|
|
(rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Destination: ext_ram_data[14]
|
|
(output port clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Path Group: sys_clk
|
|
Path Type: Max at Slow Process Corner
|
|
Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns)
|
|
Data Path Delay: 12.701ns (logic 7.361ns (57.952%) route 5.341ns (42.048%))
|
|
Logic Levels: 15 (CARRY4=6 LUT1=1 LUT3=1 LUT4=1 LUT5=1 LUT6=4 OBUFT=1)
|
|
Output Delay: 0.300ns
|
|
Clock Path Skew: -1.695ns (DCD - SCD + CPR)
|
|
Destination Clock Delay (DCD): -4.208ns = ( 15.792 - 20.000 )
|
|
Source Clock Delay (SCD): -3.025ns
|
|
Clock Pessimism Removal (CPR): -0.513ns
|
|
Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Discrete Jitter (DJ): 0.122ns
|
|
Phase Error (PE): 0.000ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock sys_clk rise edge) 0.000 0.000 r
|
|
K21 0.000 0.000 r clk (IN)
|
|
net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1
|
|
K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I
|
|
K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O
|
|
net (fo=1, unplaced) 0.584 2.047 pll_clk.u_clk_pll/inst/clk_in1_clk_pll
|
|
r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1
|
|
PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1)
|
|
-6.768 -4.721 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1
|
|
net (fo=1, unplaced) 0.800 -3.921 pll_clk.u_clk_pll/inst/sys_clk_clk_pll
|
|
r pll_clk.u_clk_pll/inst/clkout2_buf/I
|
|
BUFG (Prop_bufg_I_O) 0.096 -3.825 r pll_clk.u_clk_pll/inst/clkout2_buf/O
|
|
net (fo=10994, unplaced) 0.800 -3.025 u_axi_ram/u_axi_sram_sp/sys_clk
|
|
FDCE r u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[2]/C
|
|
------------------------------------------------------------------- -------------------
|
|
FDCE (Prop_fdce_C_Q) 0.456 -2.569 f u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[2]/Q
|
|
net (fo=56, unplaced) 0.826 -1.743 u_axi_ram/u_axi_sram_sp/len[2]
|
|
f u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6/I1
|
|
LUT4 (Prop_lut4_I1_O) 0.321 -1.422 r u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6/O
|
|
net (fo=4, unplaced) 0.473 -0.949 u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6_n_0
|
|
r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_20/I1
|
|
LUT5 (Prop_lut5_I1_O) 0.124 -0.825 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_20/O
|
|
net (fo=1, unplaced) 0.449 -0.376 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_20_n_0
|
|
r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_19/I5
|
|
LUT6 (Prop_lut6_I5_O) 0.124 -0.252 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_19/O
|
|
net (fo=1, unplaced) 0.000 -0.252 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_19_n_0
|
|
r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/S[0]
|
|
CARRY4 (Prop_carry4_S[0]_CO[3])
|
|
0.532 0.280 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/CO[3]
|
|
net (fo=1, unplaced) 0.000 0.280 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10_n_0
|
|
r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CI
|
|
CARRY4 (Prop_carry4_CI_CO[3])
|
|
0.114 0.394 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CO[3]
|
|
net (fo=1, unplaced) 0.000 0.394 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9_n_0
|
|
r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/CI
|
|
CARRY4 (Prop_carry4_CI_CO[3])
|
|
0.114 0.508 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/CO[3]
|
|
net (fo=1, unplaced) 0.000 0.508 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11_n_0
|
|
r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_10/CI
|
|
CARRY4 (Prop_carry4_CI_CO[3])
|
|
0.114 0.622 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_10/CO[3]
|
|
net (fo=1, unplaced) 0.000 0.622 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_10_n_0
|
|
r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2_i_9/CI
|
|
CARRY4 (Prop_carry4_CI_O[3])
|
|
0.329 0.951 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2_i_9/O[3]
|
|
net (fo=3, unplaced) 0.826 1.777 u_axi_ram/u_axi_sram_sp/upper_wrap_boundary[29]
|
|
r u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1_i_2/I0
|
|
LUT6 (Prop_lut6_I0_O) 0.307 2.084 r u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1_i_2/O
|
|
net (fo=1, unplaced) 0.000 2.084 u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1_i_2_n_0
|
|
r u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1/S[1]
|
|
CARRY4 (Prop_carry4_S[1]_CO[2])
|
|
0.570 2.654 r u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1/CO[2]
|
|
net (fo=23, unplaced) 0.515 3.169 u_axi_ram/u_axi_sram_sp/req_addr_d10_in
|
|
r u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/I5
|
|
LUT6 (Prop_lut6_I5_O) 0.310 3.479 r u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/O
|
|
net (fo=2, unplaced) 0.460 3.939 u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7_n_0
|
|
r u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/I1
|
|
LUT6 (Prop_lut6_I1_O) 0.124 4.063 r u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/O
|
|
net (fo=80, unplaced) 0.543 4.606 u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/soc_sram_addr[0]
|
|
r u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/ext_ram_data_IOBUF[31]_inst_i_2/I2
|
|
LUT3 (Prop_lut3_I2_O) 0.118 4.724 r u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/ext_ram_data_IOBUF[31]_inst_i_2/O
|
|
net (fo=1, unplaced) 0.449 5.173 u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/u_axi_ram/ext_ram_data1
|
|
r u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/ext_ram_data_IOBUF[31]_inst_i_1/I0
|
|
LUT1 (Prop_lut1_I0_O) 0.124 5.297 f u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/ext_ram_data_IOBUF[31]_inst_i_1/O
|
|
net (fo=32, unplaced) 0.800 6.096 ext_ram_data_IOBUF[14]_inst/T
|
|
U26 f ext_ram_data_IOBUF[14]_inst/OBUFT/T
|
|
U26 OBUFT (TriStatE_obuft_T_O)
|
|
3.580 9.676 r ext_ram_data_IOBUF[14]_inst/OBUFT/O
|
|
net (fo=1, unset) 0.000 9.676 ext_ram_data[14]
|
|
U26 r ext_ram_data[14] (INOUT)
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock sys_clk rise edge) 20.000 20.000 r
|
|
K21 0.000 20.000 r clk (IN)
|
|
net (fo=0) 0.000 20.000 pll_clk.u_clk_pll/inst/clk_in1
|
|
K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I
|
|
K21 IBUF (Prop_ibuf_I_O) 1.393 21.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O
|
|
net (fo=1, unplaced) 0.439 21.832 pll_clk.u_clk_pll/inst/clk_in1_clk_pll
|
|
r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1
|
|
PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1)
|
|
-6.040 15.792 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1
|
|
clock pessimism -0.513 15.279
|
|
clock uncertainty -0.071 15.209
|
|
output delay -0.300 14.909
|
|
-------------------------------------------------------------------
|
|
required time 14.909
|
|
arrival time -9.676
|
|
-------------------------------------------------------------------
|
|
slack 5.233
|
|
|
|
Slack (MET) : 5.233ns (required time - arrival time)
|
|
Source: u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[2]/C
|
|
(rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Destination: ext_ram_data[5]
|
|
(output port clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Path Group: sys_clk
|
|
Path Type: Max at Slow Process Corner
|
|
Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns)
|
|
Data Path Delay: 12.701ns (logic 7.361ns (57.952%) route 5.341ns (42.048%))
|
|
Logic Levels: 15 (CARRY4=6 LUT1=1 LUT3=1 LUT4=1 LUT5=1 LUT6=4 OBUFT=1)
|
|
Output Delay: 0.300ns
|
|
Clock Path Skew: -1.695ns (DCD - SCD + CPR)
|
|
Destination Clock Delay (DCD): -4.208ns = ( 15.792 - 20.000 )
|
|
Source Clock Delay (SCD): -3.025ns
|
|
Clock Pessimism Removal (CPR): -0.513ns
|
|
Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Discrete Jitter (DJ): 0.122ns
|
|
Phase Error (PE): 0.000ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock sys_clk rise edge) 0.000 0.000 r
|
|
K21 0.000 0.000 r clk (IN)
|
|
net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1
|
|
K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I
|
|
K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O
|
|
net (fo=1, unplaced) 0.584 2.047 pll_clk.u_clk_pll/inst/clk_in1_clk_pll
|
|
r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1
|
|
PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1)
|
|
-6.768 -4.721 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1
|
|
net (fo=1, unplaced) 0.800 -3.921 pll_clk.u_clk_pll/inst/sys_clk_clk_pll
|
|
r pll_clk.u_clk_pll/inst/clkout2_buf/I
|
|
BUFG (Prop_bufg_I_O) 0.096 -3.825 r pll_clk.u_clk_pll/inst/clkout2_buf/O
|
|
net (fo=10994, unplaced) 0.800 -3.025 u_axi_ram/u_axi_sram_sp/sys_clk
|
|
FDCE r u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[2]/C
|
|
------------------------------------------------------------------- -------------------
|
|
FDCE (Prop_fdce_C_Q) 0.456 -2.569 f u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[2]/Q
|
|
net (fo=56, unplaced) 0.826 -1.743 u_axi_ram/u_axi_sram_sp/len[2]
|
|
f u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6/I1
|
|
LUT4 (Prop_lut4_I1_O) 0.321 -1.422 r u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6/O
|
|
net (fo=4, unplaced) 0.473 -0.949 u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6_n_0
|
|
r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_20/I1
|
|
LUT5 (Prop_lut5_I1_O) 0.124 -0.825 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_20/O
|
|
net (fo=1, unplaced) 0.449 -0.376 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_20_n_0
|
|
r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_19/I5
|
|
LUT6 (Prop_lut6_I5_O) 0.124 -0.252 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_19/O
|
|
net (fo=1, unplaced) 0.000 -0.252 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_19_n_0
|
|
r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/S[0]
|
|
CARRY4 (Prop_carry4_S[0]_CO[3])
|
|
0.532 0.280 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/CO[3]
|
|
net (fo=1, unplaced) 0.000 0.280 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10_n_0
|
|
r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CI
|
|
CARRY4 (Prop_carry4_CI_CO[3])
|
|
0.114 0.394 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CO[3]
|
|
net (fo=1, unplaced) 0.000 0.394 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9_n_0
|
|
r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/CI
|
|
CARRY4 (Prop_carry4_CI_CO[3])
|
|
0.114 0.508 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/CO[3]
|
|
net (fo=1, unplaced) 0.000 0.508 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11_n_0
|
|
r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_10/CI
|
|
CARRY4 (Prop_carry4_CI_CO[3])
|
|
0.114 0.622 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_10/CO[3]
|
|
net (fo=1, unplaced) 0.000 0.622 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_10_n_0
|
|
r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2_i_9/CI
|
|
CARRY4 (Prop_carry4_CI_O[3])
|
|
0.329 0.951 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2_i_9/O[3]
|
|
net (fo=3, unplaced) 0.826 1.777 u_axi_ram/u_axi_sram_sp/upper_wrap_boundary[29]
|
|
r u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1_i_2/I0
|
|
LUT6 (Prop_lut6_I0_O) 0.307 2.084 r u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1_i_2/O
|
|
net (fo=1, unplaced) 0.000 2.084 u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1_i_2_n_0
|
|
r u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1/S[1]
|
|
CARRY4 (Prop_carry4_S[1]_CO[2])
|
|
0.570 2.654 r u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1/CO[2]
|
|
net (fo=23, unplaced) 0.515 3.169 u_axi_ram/u_axi_sram_sp/req_addr_d10_in
|
|
r u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/I5
|
|
LUT6 (Prop_lut6_I5_O) 0.310 3.479 r u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/O
|
|
net (fo=2, unplaced) 0.460 3.939 u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7_n_0
|
|
r u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/I1
|
|
LUT6 (Prop_lut6_I1_O) 0.124 4.063 r u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/O
|
|
net (fo=80, unplaced) 0.543 4.606 u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/soc_sram_addr[0]
|
|
r u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/ext_ram_data_IOBUF[31]_inst_i_2/I2
|
|
LUT3 (Prop_lut3_I2_O) 0.118 4.724 r u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/ext_ram_data_IOBUF[31]_inst_i_2/O
|
|
net (fo=1, unplaced) 0.449 5.173 u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/u_axi_ram/ext_ram_data1
|
|
r u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/ext_ram_data_IOBUF[31]_inst_i_1/I0
|
|
LUT1 (Prop_lut1_I0_O) 0.124 5.297 f u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/ext_ram_data_IOBUF[31]_inst_i_1/O
|
|
net (fo=32, unplaced) 0.800 6.096 ext_ram_data_IOBUF[5]_inst/T
|
|
AE21 f ext_ram_data_IOBUF[5]_inst/OBUFT/T
|
|
AE21 OBUFT (TriStatE_obuft_T_O)
|
|
3.580 9.676 r ext_ram_data_IOBUF[5]_inst/OBUFT/O
|
|
net (fo=1, unset) 0.000 9.676 ext_ram_data[5]
|
|
AE21 r ext_ram_data[5] (INOUT)
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock sys_clk rise edge) 20.000 20.000 r
|
|
K21 0.000 20.000 r clk (IN)
|
|
net (fo=0) 0.000 20.000 pll_clk.u_clk_pll/inst/clk_in1
|
|
K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I
|
|
K21 IBUF (Prop_ibuf_I_O) 1.393 21.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O
|
|
net (fo=1, unplaced) 0.439 21.832 pll_clk.u_clk_pll/inst/clk_in1_clk_pll
|
|
r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1
|
|
PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1)
|
|
-6.040 15.792 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1
|
|
clock pessimism -0.513 15.279
|
|
clock uncertainty -0.071 15.209
|
|
output delay -0.300 14.909
|
|
-------------------------------------------------------------------
|
|
required time 14.909
|
|
arrival time -9.676
|
|
-------------------------------------------------------------------
|
|
slack 5.233
|
|
|
|
Slack (MET) : 5.233ns (required time - arrival time)
|
|
Source: u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[2]/C
|
|
(rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Destination: base_ram_data[4]
|
|
(output port clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Path Group: sys_clk
|
|
Path Type: Max at Slow Process Corner
|
|
Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns)
|
|
Data Path Delay: 12.701ns (logic 7.360ns (57.951%) route 5.341ns (42.049%))
|
|
Logic Levels: 15 (CARRY4=6 LUT1=1 LUT3=1 LUT4=1 LUT5=1 LUT6=4 OBUFT=1)
|
|
Output Delay: 0.300ns
|
|
Clock Path Skew: -1.695ns (DCD - SCD + CPR)
|
|
Destination Clock Delay (DCD): -4.208ns = ( 15.792 - 20.000 )
|
|
Source Clock Delay (SCD): -3.025ns
|
|
Clock Pessimism Removal (CPR): -0.513ns
|
|
Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Discrete Jitter (DJ): 0.122ns
|
|
Phase Error (PE): 0.000ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock sys_clk rise edge) 0.000 0.000 r
|
|
K21 0.000 0.000 r clk (IN)
|
|
net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1
|
|
K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I
|
|
K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O
|
|
net (fo=1, unplaced) 0.584 2.047 pll_clk.u_clk_pll/inst/clk_in1_clk_pll
|
|
r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1
|
|
PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1)
|
|
-6.768 -4.721 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1
|
|
net (fo=1, unplaced) 0.800 -3.921 pll_clk.u_clk_pll/inst/sys_clk_clk_pll
|
|
r pll_clk.u_clk_pll/inst/clkout2_buf/I
|
|
BUFG (Prop_bufg_I_O) 0.096 -3.825 r pll_clk.u_clk_pll/inst/clkout2_buf/O
|
|
net (fo=10994, unplaced) 0.800 -3.025 u_axi_ram/u_axi_sram_sp/sys_clk
|
|
FDCE r u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[2]/C
|
|
------------------------------------------------------------------- -------------------
|
|
FDCE (Prop_fdce_C_Q) 0.456 -2.569 f u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[2]/Q
|
|
net (fo=56, unplaced) 0.826 -1.743 u_axi_ram/u_axi_sram_sp/len[2]
|
|
f u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6/I1
|
|
LUT4 (Prop_lut4_I1_O) 0.321 -1.422 r u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6/O
|
|
net (fo=4, unplaced) 0.473 -0.949 u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6_n_0
|
|
r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_20/I1
|
|
LUT5 (Prop_lut5_I1_O) 0.124 -0.825 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_20/O
|
|
net (fo=1, unplaced) 0.449 -0.376 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_20_n_0
|
|
r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_19/I5
|
|
LUT6 (Prop_lut6_I5_O) 0.124 -0.252 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_19/O
|
|
net (fo=1, unplaced) 0.000 -0.252 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_19_n_0
|
|
r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/S[0]
|
|
CARRY4 (Prop_carry4_S[0]_CO[3])
|
|
0.532 0.280 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/CO[3]
|
|
net (fo=1, unplaced) 0.000 0.280 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10_n_0
|
|
r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CI
|
|
CARRY4 (Prop_carry4_CI_CO[3])
|
|
0.114 0.394 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CO[3]
|
|
net (fo=1, unplaced) 0.000 0.394 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9_n_0
|
|
r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/CI
|
|
CARRY4 (Prop_carry4_CI_CO[3])
|
|
0.114 0.508 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/CO[3]
|
|
net (fo=1, unplaced) 0.000 0.508 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11_n_0
|
|
r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_10/CI
|
|
CARRY4 (Prop_carry4_CI_CO[3])
|
|
0.114 0.622 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_10/CO[3]
|
|
net (fo=1, unplaced) 0.000 0.622 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_10_n_0
|
|
r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2_i_9/CI
|
|
CARRY4 (Prop_carry4_CI_O[3])
|
|
0.329 0.951 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2_i_9/O[3]
|
|
net (fo=3, unplaced) 0.826 1.777 u_axi_ram/u_axi_sram_sp/upper_wrap_boundary[29]
|
|
r u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1_i_2/I0
|
|
LUT6 (Prop_lut6_I0_O) 0.307 2.084 r u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1_i_2/O
|
|
net (fo=1, unplaced) 0.000 2.084 u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1_i_2_n_0
|
|
r u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1/S[1]
|
|
CARRY4 (Prop_carry4_S[1]_CO[2])
|
|
0.570 2.654 r u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1/CO[2]
|
|
net (fo=23, unplaced) 0.515 3.169 u_axi_ram/u_axi_sram_sp/req_addr_d10_in
|
|
r u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/I5
|
|
LUT6 (Prop_lut6_I5_O) 0.310 3.479 f u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/O
|
|
net (fo=2, unplaced) 0.460 3.939 u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7_n_0
|
|
f u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/I1
|
|
LUT6 (Prop_lut6_I1_O) 0.124 4.063 f u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/O
|
|
net (fo=80, unplaced) 0.543 4.606 u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/soc_sram_addr[0]
|
|
f u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/base_ram_data_IOBUF[31]_inst_i_3/I2
|
|
LUT3 (Prop_lut3_I2_O) 0.124 4.730 r u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/base_ram_data_IOBUF[31]_inst_i_3/O
|
|
net (fo=1, unplaced) 0.449 5.179 u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/u_axi_ram/base_ram_data1
|
|
r u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/base_ram_data_IOBUF[31]_inst_i_2/I0
|
|
LUT1 (Prop_lut1_I0_O) 0.124 5.303 f u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/base_ram_data_IOBUF[31]_inst_i_2/O
|
|
net (fo=32, unplaced) 0.800 6.102 base_ram_data_IOBUF[4]_inst/T
|
|
N26 f base_ram_data_IOBUF[4]_inst/OBUFT/T
|
|
N26 OBUFT (TriStatE_obuft_T_O)
|
|
3.573 9.676 r base_ram_data_IOBUF[4]_inst/OBUFT/O
|
|
net (fo=1, unset) 0.000 9.676 base_ram_data[4]
|
|
N26 r base_ram_data[4] (INOUT)
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock sys_clk rise edge) 20.000 20.000 r
|
|
K21 0.000 20.000 r clk (IN)
|
|
net (fo=0) 0.000 20.000 pll_clk.u_clk_pll/inst/clk_in1
|
|
K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I
|
|
K21 IBUF (Prop_ibuf_I_O) 1.393 21.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O
|
|
net (fo=1, unplaced) 0.439 21.832 pll_clk.u_clk_pll/inst/clk_in1_clk_pll
|
|
r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1
|
|
PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1)
|
|
-6.040 15.792 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1
|
|
clock pessimism -0.513 15.279
|
|
clock uncertainty -0.071 15.209
|
|
output delay -0.300 14.909
|
|
-------------------------------------------------------------------
|
|
required time 14.909
|
|
arrival time -9.676
|
|
-------------------------------------------------------------------
|
|
slack 5.233
|
|
|
|
Slack (MET) : 5.233ns (required time - arrival time)
|
|
Source: u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[2]/C
|
|
(rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Destination: ext_ram_data[13]
|
|
(output port clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Path Group: sys_clk
|
|
Path Type: Max at Slow Process Corner
|
|
Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns)
|
|
Data Path Delay: 12.701ns (logic 7.360ns (57.950%) route 5.341ns (42.050%))
|
|
Logic Levels: 15 (CARRY4=6 LUT1=1 LUT3=1 LUT4=1 LUT5=1 LUT6=4 OBUFT=1)
|
|
Output Delay: 0.300ns
|
|
Clock Path Skew: -1.695ns (DCD - SCD + CPR)
|
|
Destination Clock Delay (DCD): -4.208ns = ( 15.792 - 20.000 )
|
|
Source Clock Delay (SCD): -3.025ns
|
|
Clock Pessimism Removal (CPR): -0.513ns
|
|
Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Discrete Jitter (DJ): 0.122ns
|
|
Phase Error (PE): 0.000ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock sys_clk rise edge) 0.000 0.000 r
|
|
K21 0.000 0.000 r clk (IN)
|
|
net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1
|
|
K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I
|
|
K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O
|
|
net (fo=1, unplaced) 0.584 2.047 pll_clk.u_clk_pll/inst/clk_in1_clk_pll
|
|
r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1
|
|
PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1)
|
|
-6.768 -4.721 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1
|
|
net (fo=1, unplaced) 0.800 -3.921 pll_clk.u_clk_pll/inst/sys_clk_clk_pll
|
|
r pll_clk.u_clk_pll/inst/clkout2_buf/I
|
|
BUFG (Prop_bufg_I_O) 0.096 -3.825 r pll_clk.u_clk_pll/inst/clkout2_buf/O
|
|
net (fo=10994, unplaced) 0.800 -3.025 u_axi_ram/u_axi_sram_sp/sys_clk
|
|
FDCE r u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[2]/C
|
|
------------------------------------------------------------------- -------------------
|
|
FDCE (Prop_fdce_C_Q) 0.456 -2.569 f u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[2]/Q
|
|
net (fo=56, unplaced) 0.826 -1.743 u_axi_ram/u_axi_sram_sp/len[2]
|
|
f u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6/I1
|
|
LUT4 (Prop_lut4_I1_O) 0.321 -1.422 r u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6/O
|
|
net (fo=4, unplaced) 0.473 -0.949 u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6_n_0
|
|
r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_20/I1
|
|
LUT5 (Prop_lut5_I1_O) 0.124 -0.825 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_20/O
|
|
net (fo=1, unplaced) 0.449 -0.376 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_20_n_0
|
|
r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_19/I5
|
|
LUT6 (Prop_lut6_I5_O) 0.124 -0.252 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_19/O
|
|
net (fo=1, unplaced) 0.000 -0.252 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_19_n_0
|
|
r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/S[0]
|
|
CARRY4 (Prop_carry4_S[0]_CO[3])
|
|
0.532 0.280 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/CO[3]
|
|
net (fo=1, unplaced) 0.000 0.280 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10_n_0
|
|
r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CI
|
|
CARRY4 (Prop_carry4_CI_CO[3])
|
|
0.114 0.394 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CO[3]
|
|
net (fo=1, unplaced) 0.000 0.394 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9_n_0
|
|
r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/CI
|
|
CARRY4 (Prop_carry4_CI_CO[3])
|
|
0.114 0.508 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/CO[3]
|
|
net (fo=1, unplaced) 0.000 0.508 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11_n_0
|
|
r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_10/CI
|
|
CARRY4 (Prop_carry4_CI_CO[3])
|
|
0.114 0.622 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_10/CO[3]
|
|
net (fo=1, unplaced) 0.000 0.622 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_10_n_0
|
|
r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2_i_9/CI
|
|
CARRY4 (Prop_carry4_CI_O[3])
|
|
0.329 0.951 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2_i_9/O[3]
|
|
net (fo=3, unplaced) 0.826 1.777 u_axi_ram/u_axi_sram_sp/upper_wrap_boundary[29]
|
|
r u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1_i_2/I0
|
|
LUT6 (Prop_lut6_I0_O) 0.307 2.084 r u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1_i_2/O
|
|
net (fo=1, unplaced) 0.000 2.084 u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1_i_2_n_0
|
|
r u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1/S[1]
|
|
CARRY4 (Prop_carry4_S[1]_CO[2])
|
|
0.570 2.654 r u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1/CO[2]
|
|
net (fo=23, unplaced) 0.515 3.169 u_axi_ram/u_axi_sram_sp/req_addr_d10_in
|
|
r u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/I5
|
|
LUT6 (Prop_lut6_I5_O) 0.310 3.479 r u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/O
|
|
net (fo=2, unplaced) 0.460 3.939 u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7_n_0
|
|
r u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/I1
|
|
LUT6 (Prop_lut6_I1_O) 0.124 4.063 r u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/O
|
|
net (fo=80, unplaced) 0.543 4.606 u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/soc_sram_addr[0]
|
|
r u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/ext_ram_data_IOBUF[31]_inst_i_2/I2
|
|
LUT3 (Prop_lut3_I2_O) 0.118 4.724 r u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/ext_ram_data_IOBUF[31]_inst_i_2/O
|
|
net (fo=1, unplaced) 0.449 5.173 u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/u_axi_ram/ext_ram_data1
|
|
r u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/ext_ram_data_IOBUF[31]_inst_i_1/I0
|
|
LUT1 (Prop_lut1_I0_O) 0.124 5.297 f u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/ext_ram_data_IOBUF[31]_inst_i_1/O
|
|
net (fo=32, unplaced) 0.800 6.096 ext_ram_data_IOBUF[13]_inst/T
|
|
U25 f ext_ram_data_IOBUF[13]_inst/OBUFT/T
|
|
U25 OBUFT (TriStatE_obuft_T_O)
|
|
3.579 9.675 r ext_ram_data_IOBUF[13]_inst/OBUFT/O
|
|
net (fo=1, unset) 0.000 9.675 ext_ram_data[13]
|
|
U25 r ext_ram_data[13] (INOUT)
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock sys_clk rise edge) 20.000 20.000 r
|
|
K21 0.000 20.000 r clk (IN)
|
|
net (fo=0) 0.000 20.000 pll_clk.u_clk_pll/inst/clk_in1
|
|
K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I
|
|
K21 IBUF (Prop_ibuf_I_O) 1.393 21.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O
|
|
net (fo=1, unplaced) 0.439 21.832 pll_clk.u_clk_pll/inst/clk_in1_clk_pll
|
|
r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1
|
|
PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1)
|
|
-6.040 15.792 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1
|
|
clock pessimism -0.513 15.279
|
|
clock uncertainty -0.071 15.209
|
|
output delay -0.300 14.909
|
|
-------------------------------------------------------------------
|
|
required time 14.909
|
|
arrival time -9.675
|
|
-------------------------------------------------------------------
|
|
slack 5.233
|
|
|
|
Slack (MET) : 5.235ns (required time - arrival time)
|
|
Source: u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[2]/C
|
|
(rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Destination: ext_ram_data[6]
|
|
(output port clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Path Group: sys_clk
|
|
Path Type: Max at Slow Process Corner
|
|
Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns)
|
|
Data Path Delay: 12.699ns (logic 7.358ns (57.944%) route 5.341ns (42.056%))
|
|
Logic Levels: 15 (CARRY4=6 LUT1=1 LUT3=1 LUT4=1 LUT5=1 LUT6=4 OBUFT=1)
|
|
Output Delay: 0.300ns
|
|
Clock Path Skew: -1.695ns (DCD - SCD + CPR)
|
|
Destination Clock Delay (DCD): -4.208ns = ( 15.792 - 20.000 )
|
|
Source Clock Delay (SCD): -3.025ns
|
|
Clock Pessimism Removal (CPR): -0.513ns
|
|
Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Discrete Jitter (DJ): 0.122ns
|
|
Phase Error (PE): 0.000ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock sys_clk rise edge) 0.000 0.000 r
|
|
K21 0.000 0.000 r clk (IN)
|
|
net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1
|
|
K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I
|
|
K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O
|
|
net (fo=1, unplaced) 0.584 2.047 pll_clk.u_clk_pll/inst/clk_in1_clk_pll
|
|
r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1
|
|
PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1)
|
|
-6.768 -4.721 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1
|
|
net (fo=1, unplaced) 0.800 -3.921 pll_clk.u_clk_pll/inst/sys_clk_clk_pll
|
|
r pll_clk.u_clk_pll/inst/clkout2_buf/I
|
|
BUFG (Prop_bufg_I_O) 0.096 -3.825 r pll_clk.u_clk_pll/inst/clkout2_buf/O
|
|
net (fo=10994, unplaced) 0.800 -3.025 u_axi_ram/u_axi_sram_sp/sys_clk
|
|
FDCE r u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[2]/C
|
|
------------------------------------------------------------------- -------------------
|
|
FDCE (Prop_fdce_C_Q) 0.456 -2.569 f u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[2]/Q
|
|
net (fo=56, unplaced) 0.826 -1.743 u_axi_ram/u_axi_sram_sp/len[2]
|
|
f u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6/I1
|
|
LUT4 (Prop_lut4_I1_O) 0.321 -1.422 r u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6/O
|
|
net (fo=4, unplaced) 0.473 -0.949 u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6_n_0
|
|
r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_20/I1
|
|
LUT5 (Prop_lut5_I1_O) 0.124 -0.825 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_20/O
|
|
net (fo=1, unplaced) 0.449 -0.376 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_20_n_0
|
|
r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_19/I5
|
|
LUT6 (Prop_lut6_I5_O) 0.124 -0.252 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_19/O
|
|
net (fo=1, unplaced) 0.000 -0.252 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_19_n_0
|
|
r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/S[0]
|
|
CARRY4 (Prop_carry4_S[0]_CO[3])
|
|
0.532 0.280 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/CO[3]
|
|
net (fo=1, unplaced) 0.000 0.280 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10_n_0
|
|
r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CI
|
|
CARRY4 (Prop_carry4_CI_CO[3])
|
|
0.114 0.394 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CO[3]
|
|
net (fo=1, unplaced) 0.000 0.394 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9_n_0
|
|
r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/CI
|
|
CARRY4 (Prop_carry4_CI_CO[3])
|
|
0.114 0.508 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/CO[3]
|
|
net (fo=1, unplaced) 0.000 0.508 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11_n_0
|
|
r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_10/CI
|
|
CARRY4 (Prop_carry4_CI_CO[3])
|
|
0.114 0.622 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_10/CO[3]
|
|
net (fo=1, unplaced) 0.000 0.622 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_10_n_0
|
|
r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2_i_9/CI
|
|
CARRY4 (Prop_carry4_CI_O[3])
|
|
0.329 0.951 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2_i_9/O[3]
|
|
net (fo=3, unplaced) 0.826 1.777 u_axi_ram/u_axi_sram_sp/upper_wrap_boundary[29]
|
|
r u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1_i_2/I0
|
|
LUT6 (Prop_lut6_I0_O) 0.307 2.084 r u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1_i_2/O
|
|
net (fo=1, unplaced) 0.000 2.084 u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1_i_2_n_0
|
|
r u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1/S[1]
|
|
CARRY4 (Prop_carry4_S[1]_CO[2])
|
|
0.570 2.654 r u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1/CO[2]
|
|
net (fo=23, unplaced) 0.515 3.169 u_axi_ram/u_axi_sram_sp/req_addr_d10_in
|
|
r u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/I5
|
|
LUT6 (Prop_lut6_I5_O) 0.310 3.479 r u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/O
|
|
net (fo=2, unplaced) 0.460 3.939 u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7_n_0
|
|
r u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/I1
|
|
LUT6 (Prop_lut6_I1_O) 0.124 4.063 r u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/O
|
|
net (fo=80, unplaced) 0.543 4.606 u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/soc_sram_addr[0]
|
|
r u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/ext_ram_data_IOBUF[31]_inst_i_2/I2
|
|
LUT3 (Prop_lut3_I2_O) 0.118 4.724 r u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/ext_ram_data_IOBUF[31]_inst_i_2/O
|
|
net (fo=1, unplaced) 0.449 5.173 u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/u_axi_ram/ext_ram_data1
|
|
r u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/ext_ram_data_IOBUF[31]_inst_i_1/I0
|
|
LUT1 (Prop_lut1_I0_O) 0.124 5.297 f u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/ext_ram_data_IOBUF[31]_inst_i_1/O
|
|
net (fo=32, unplaced) 0.800 6.096 ext_ram_data_IOBUF[6]_inst/T
|
|
AE20 f ext_ram_data_IOBUF[6]_inst/OBUFT/T
|
|
AE20 OBUFT (TriStatE_obuft_T_O)
|
|
3.577 9.674 r ext_ram_data_IOBUF[6]_inst/OBUFT/O
|
|
net (fo=1, unset) 0.000 9.674 ext_ram_data[6]
|
|
AE20 r ext_ram_data[6] (INOUT)
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock sys_clk rise edge) 20.000 20.000 r
|
|
K21 0.000 20.000 r clk (IN)
|
|
net (fo=0) 0.000 20.000 pll_clk.u_clk_pll/inst/clk_in1
|
|
K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I
|
|
K21 IBUF (Prop_ibuf_I_O) 1.393 21.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O
|
|
net (fo=1, unplaced) 0.439 21.832 pll_clk.u_clk_pll/inst/clk_in1_clk_pll
|
|
r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1
|
|
PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1)
|
|
-6.040 15.792 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1
|
|
clock pessimism -0.513 15.279
|
|
clock uncertainty -0.071 15.209
|
|
output delay -0.300 14.909
|
|
-------------------------------------------------------------------
|
|
required time 14.909
|
|
arrival time -9.674
|
|
-------------------------------------------------------------------
|
|
slack 5.235
|
|
|
|
Slack (MET) : 5.235ns (required time - arrival time)
|
|
Source: u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[2]/C
|
|
(rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Destination: base_ram_data[12]
|
|
(output port clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Path Group: sys_clk
|
|
Path Type: Max at Slow Process Corner
|
|
Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns)
|
|
Data Path Delay: 12.699ns (logic 7.358ns (57.943%) route 5.341ns (42.057%))
|
|
Logic Levels: 15 (CARRY4=6 LUT1=1 LUT3=1 LUT4=1 LUT5=1 LUT6=4 OBUFT=1)
|
|
Output Delay: 0.300ns
|
|
Clock Path Skew: -1.695ns (DCD - SCD + CPR)
|
|
Destination Clock Delay (DCD): -4.208ns = ( 15.792 - 20.000 )
|
|
Source Clock Delay (SCD): -3.025ns
|
|
Clock Pessimism Removal (CPR): -0.513ns
|
|
Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Discrete Jitter (DJ): 0.122ns
|
|
Phase Error (PE): 0.000ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock sys_clk rise edge) 0.000 0.000 r
|
|
K21 0.000 0.000 r clk (IN)
|
|
net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1
|
|
K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I
|
|
K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O
|
|
net (fo=1, unplaced) 0.584 2.047 pll_clk.u_clk_pll/inst/clk_in1_clk_pll
|
|
r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1
|
|
PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1)
|
|
-6.768 -4.721 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1
|
|
net (fo=1, unplaced) 0.800 -3.921 pll_clk.u_clk_pll/inst/sys_clk_clk_pll
|
|
r pll_clk.u_clk_pll/inst/clkout2_buf/I
|
|
BUFG (Prop_bufg_I_O) 0.096 -3.825 r pll_clk.u_clk_pll/inst/clkout2_buf/O
|
|
net (fo=10994, unplaced) 0.800 -3.025 u_axi_ram/u_axi_sram_sp/sys_clk
|
|
FDCE r u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[2]/C
|
|
------------------------------------------------------------------- -------------------
|
|
FDCE (Prop_fdce_C_Q) 0.456 -2.569 f u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[2]/Q
|
|
net (fo=56, unplaced) 0.826 -1.743 u_axi_ram/u_axi_sram_sp/len[2]
|
|
f u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6/I1
|
|
LUT4 (Prop_lut4_I1_O) 0.321 -1.422 r u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6/O
|
|
net (fo=4, unplaced) 0.473 -0.949 u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6_n_0
|
|
r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_20/I1
|
|
LUT5 (Prop_lut5_I1_O) 0.124 -0.825 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_20/O
|
|
net (fo=1, unplaced) 0.449 -0.376 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_20_n_0
|
|
r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_19/I5
|
|
LUT6 (Prop_lut6_I5_O) 0.124 -0.252 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_19/O
|
|
net (fo=1, unplaced) 0.000 -0.252 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_19_n_0
|
|
r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/S[0]
|
|
CARRY4 (Prop_carry4_S[0]_CO[3])
|
|
0.532 0.280 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/CO[3]
|
|
net (fo=1, unplaced) 0.000 0.280 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10_n_0
|
|
r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CI
|
|
CARRY4 (Prop_carry4_CI_CO[3])
|
|
0.114 0.394 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CO[3]
|
|
net (fo=1, unplaced) 0.000 0.394 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9_n_0
|
|
r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/CI
|
|
CARRY4 (Prop_carry4_CI_CO[3])
|
|
0.114 0.508 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/CO[3]
|
|
net (fo=1, unplaced) 0.000 0.508 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11_n_0
|
|
r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_10/CI
|
|
CARRY4 (Prop_carry4_CI_CO[3])
|
|
0.114 0.622 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_10/CO[3]
|
|
net (fo=1, unplaced) 0.000 0.622 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_10_n_0
|
|
r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2_i_9/CI
|
|
CARRY4 (Prop_carry4_CI_O[3])
|
|
0.329 0.951 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2_i_9/O[3]
|
|
net (fo=3, unplaced) 0.826 1.777 u_axi_ram/u_axi_sram_sp/upper_wrap_boundary[29]
|
|
r u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1_i_2/I0
|
|
LUT6 (Prop_lut6_I0_O) 0.307 2.084 r u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1_i_2/O
|
|
net (fo=1, unplaced) 0.000 2.084 u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1_i_2_n_0
|
|
r u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1/S[1]
|
|
CARRY4 (Prop_carry4_S[1]_CO[2])
|
|
0.570 2.654 r u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1/CO[2]
|
|
net (fo=23, unplaced) 0.515 3.169 u_axi_ram/u_axi_sram_sp/req_addr_d10_in
|
|
r u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/I5
|
|
LUT6 (Prop_lut6_I5_O) 0.310 3.479 f u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/O
|
|
net (fo=2, unplaced) 0.460 3.939 u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7_n_0
|
|
f u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/I1
|
|
LUT6 (Prop_lut6_I1_O) 0.124 4.063 f u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/O
|
|
net (fo=80, unplaced) 0.543 4.606 u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/soc_sram_addr[0]
|
|
f u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/base_ram_data_IOBUF[31]_inst_i_3/I2
|
|
LUT3 (Prop_lut3_I2_O) 0.124 4.730 r u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/base_ram_data_IOBUF[31]_inst_i_3/O
|
|
net (fo=1, unplaced) 0.449 5.179 u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/u_axi_ram/base_ram_data1
|
|
r u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/base_ram_data_IOBUF[31]_inst_i_2/I0
|
|
LUT1 (Prop_lut1_I0_O) 0.124 5.303 f u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/base_ram_data_IOBUF[31]_inst_i_2/O
|
|
net (fo=32, unplaced) 0.800 6.102 base_ram_data_IOBUF[12]_inst/T
|
|
W23 f base_ram_data_IOBUF[12]_inst/OBUFT/T
|
|
W23 OBUFT (TriStatE_obuft_T_O)
|
|
3.571 9.673 r base_ram_data_IOBUF[12]_inst/OBUFT/O
|
|
net (fo=1, unset) 0.000 9.673 base_ram_data[12]
|
|
W23 r base_ram_data[12] (INOUT)
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock sys_clk rise edge) 20.000 20.000 r
|
|
K21 0.000 20.000 r clk (IN)
|
|
net (fo=0) 0.000 20.000 pll_clk.u_clk_pll/inst/clk_in1
|
|
K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I
|
|
K21 IBUF (Prop_ibuf_I_O) 1.393 21.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O
|
|
net (fo=1, unplaced) 0.439 21.832 pll_clk.u_clk_pll/inst/clk_in1_clk_pll
|
|
r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1
|
|
PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1)
|
|
-6.040 15.792 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1
|
|
clock pessimism -0.513 15.279
|
|
clock uncertainty -0.071 15.209
|
|
output delay -0.300 14.909
|
|
-------------------------------------------------------------------
|
|
required time 14.909
|
|
arrival time -9.673
|
|
-------------------------------------------------------------------
|
|
slack 5.235
|
|
|
|
Slack (MET) : 5.236ns (required time - arrival time)
|
|
Source: u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[2]/C
|
|
(rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Destination: ext_ram_data[12]
|
|
(output port clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Path Group: sys_clk
|
|
Path Type: Max at Slow Process Corner
|
|
Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns)
|
|
Data Path Delay: 12.698ns (logic 7.358ns (57.941%) route 5.341ns (42.059%))
|
|
Logic Levels: 15 (CARRY4=6 LUT1=1 LUT3=1 LUT4=1 LUT5=1 LUT6=4 OBUFT=1)
|
|
Output Delay: 0.300ns
|
|
Clock Path Skew: -1.695ns (DCD - SCD + CPR)
|
|
Destination Clock Delay (DCD): -4.208ns = ( 15.792 - 20.000 )
|
|
Source Clock Delay (SCD): -3.025ns
|
|
Clock Pessimism Removal (CPR): -0.513ns
|
|
Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Discrete Jitter (DJ): 0.122ns
|
|
Phase Error (PE): 0.000ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock sys_clk rise edge) 0.000 0.000 r
|
|
K21 0.000 0.000 r clk (IN)
|
|
net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1
|
|
K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I
|
|
K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O
|
|
net (fo=1, unplaced) 0.584 2.047 pll_clk.u_clk_pll/inst/clk_in1_clk_pll
|
|
r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1
|
|
PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1)
|
|
-6.768 -4.721 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1
|
|
net (fo=1, unplaced) 0.800 -3.921 pll_clk.u_clk_pll/inst/sys_clk_clk_pll
|
|
r pll_clk.u_clk_pll/inst/clkout2_buf/I
|
|
BUFG (Prop_bufg_I_O) 0.096 -3.825 r pll_clk.u_clk_pll/inst/clkout2_buf/O
|
|
net (fo=10994, unplaced) 0.800 -3.025 u_axi_ram/u_axi_sram_sp/sys_clk
|
|
FDCE r u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[2]/C
|
|
------------------------------------------------------------------- -------------------
|
|
FDCE (Prop_fdce_C_Q) 0.456 -2.569 f u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[2]/Q
|
|
net (fo=56, unplaced) 0.826 -1.743 u_axi_ram/u_axi_sram_sp/len[2]
|
|
f u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6/I1
|
|
LUT4 (Prop_lut4_I1_O) 0.321 -1.422 r u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6/O
|
|
net (fo=4, unplaced) 0.473 -0.949 u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6_n_0
|
|
r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_20/I1
|
|
LUT5 (Prop_lut5_I1_O) 0.124 -0.825 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_20/O
|
|
net (fo=1, unplaced) 0.449 -0.376 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_20_n_0
|
|
r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_19/I5
|
|
LUT6 (Prop_lut6_I5_O) 0.124 -0.252 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_19/O
|
|
net (fo=1, unplaced) 0.000 -0.252 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_19_n_0
|
|
r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/S[0]
|
|
CARRY4 (Prop_carry4_S[0]_CO[3])
|
|
0.532 0.280 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/CO[3]
|
|
net (fo=1, unplaced) 0.000 0.280 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10_n_0
|
|
r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CI
|
|
CARRY4 (Prop_carry4_CI_CO[3])
|
|
0.114 0.394 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CO[3]
|
|
net (fo=1, unplaced) 0.000 0.394 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9_n_0
|
|
r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/CI
|
|
CARRY4 (Prop_carry4_CI_CO[3])
|
|
0.114 0.508 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/CO[3]
|
|
net (fo=1, unplaced) 0.000 0.508 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11_n_0
|
|
r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_10/CI
|
|
CARRY4 (Prop_carry4_CI_CO[3])
|
|
0.114 0.622 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_10/CO[3]
|
|
net (fo=1, unplaced) 0.000 0.622 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_10_n_0
|
|
r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2_i_9/CI
|
|
CARRY4 (Prop_carry4_CI_O[3])
|
|
0.329 0.951 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2_i_9/O[3]
|
|
net (fo=3, unplaced) 0.826 1.777 u_axi_ram/u_axi_sram_sp/upper_wrap_boundary[29]
|
|
r u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1_i_2/I0
|
|
LUT6 (Prop_lut6_I0_O) 0.307 2.084 r u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1_i_2/O
|
|
net (fo=1, unplaced) 0.000 2.084 u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1_i_2_n_0
|
|
r u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1/S[1]
|
|
CARRY4 (Prop_carry4_S[1]_CO[2])
|
|
0.570 2.654 r u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1/CO[2]
|
|
net (fo=23, unplaced) 0.515 3.169 u_axi_ram/u_axi_sram_sp/req_addr_d10_in
|
|
r u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/I5
|
|
LUT6 (Prop_lut6_I5_O) 0.310 3.479 r u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/O
|
|
net (fo=2, unplaced) 0.460 3.939 u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7_n_0
|
|
r u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/I1
|
|
LUT6 (Prop_lut6_I1_O) 0.124 4.063 r u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/O
|
|
net (fo=80, unplaced) 0.543 4.606 u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/soc_sram_addr[0]
|
|
r u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/ext_ram_data_IOBUF[31]_inst_i_2/I2
|
|
LUT3 (Prop_lut3_I2_O) 0.118 4.724 r u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/ext_ram_data_IOBUF[31]_inst_i_2/O
|
|
net (fo=1, unplaced) 0.449 5.173 u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/u_axi_ram/ext_ram_data1
|
|
r u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/ext_ram_data_IOBUF[31]_inst_i_1/I0
|
|
LUT1 (Prop_lut1_I0_O) 0.124 5.297 f u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/ext_ram_data_IOBUF[31]_inst_i_1/O
|
|
net (fo=32, unplaced) 0.800 6.096 ext_ram_data_IOBUF[12]_inst/T
|
|
V26 f ext_ram_data_IOBUF[12]_inst/OBUFT/T
|
|
V26 OBUFT (TriStatE_obuft_T_O)
|
|
3.577 9.673 r ext_ram_data_IOBUF[12]_inst/OBUFT/O
|
|
net (fo=1, unset) 0.000 9.673 ext_ram_data[12]
|
|
V26 r ext_ram_data[12] (INOUT)
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock sys_clk rise edge) 20.000 20.000 r
|
|
K21 0.000 20.000 r clk (IN)
|
|
net (fo=0) 0.000 20.000 pll_clk.u_clk_pll/inst/clk_in1
|
|
K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I
|
|
K21 IBUF (Prop_ibuf_I_O) 1.393 21.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O
|
|
net (fo=1, unplaced) 0.439 21.832 pll_clk.u_clk_pll/inst/clk_in1_clk_pll
|
|
r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1
|
|
PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1)
|
|
-6.040 15.792 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1
|
|
clock pessimism -0.513 15.279
|
|
clock uncertainty -0.071 15.209
|
|
output delay -0.300 14.909
|
|
-------------------------------------------------------------------
|
|
required time 14.909
|
|
arrival time -9.673
|
|
-------------------------------------------------------------------
|
|
slack 5.236
|
|
|
|
Slack (MET) : 5.236ns (required time - arrival time)
|
|
Source: u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[2]/C
|
|
(rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Destination: base_ram_data[13]
|
|
(output port clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Path Group: sys_clk
|
|
Path Type: Max at Slow Process Corner
|
|
Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns)
|
|
Data Path Delay: 12.698ns (logic 7.357ns (57.940%) route 5.341ns (42.060%))
|
|
Logic Levels: 15 (CARRY4=6 LUT1=1 LUT3=1 LUT4=1 LUT5=1 LUT6=4 OBUFT=1)
|
|
Output Delay: 0.300ns
|
|
Clock Path Skew: -1.695ns (DCD - SCD + CPR)
|
|
Destination Clock Delay (DCD): -4.208ns = ( 15.792 - 20.000 )
|
|
Source Clock Delay (SCD): -3.025ns
|
|
Clock Pessimism Removal (CPR): -0.513ns
|
|
Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Discrete Jitter (DJ): 0.122ns
|
|
Phase Error (PE): 0.000ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock sys_clk rise edge) 0.000 0.000 r
|
|
K21 0.000 0.000 r clk (IN)
|
|
net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1
|
|
K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I
|
|
K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O
|
|
net (fo=1, unplaced) 0.584 2.047 pll_clk.u_clk_pll/inst/clk_in1_clk_pll
|
|
r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1
|
|
PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1)
|
|
-6.768 -4.721 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1
|
|
net (fo=1, unplaced) 0.800 -3.921 pll_clk.u_clk_pll/inst/sys_clk_clk_pll
|
|
r pll_clk.u_clk_pll/inst/clkout2_buf/I
|
|
BUFG (Prop_bufg_I_O) 0.096 -3.825 r pll_clk.u_clk_pll/inst/clkout2_buf/O
|
|
net (fo=10994, unplaced) 0.800 -3.025 u_axi_ram/u_axi_sram_sp/sys_clk
|
|
FDCE r u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[2]/C
|
|
------------------------------------------------------------------- -------------------
|
|
FDCE (Prop_fdce_C_Q) 0.456 -2.569 f u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[2]/Q
|
|
net (fo=56, unplaced) 0.826 -1.743 u_axi_ram/u_axi_sram_sp/len[2]
|
|
f u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6/I1
|
|
LUT4 (Prop_lut4_I1_O) 0.321 -1.422 r u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6/O
|
|
net (fo=4, unplaced) 0.473 -0.949 u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6_n_0
|
|
r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_20/I1
|
|
LUT5 (Prop_lut5_I1_O) 0.124 -0.825 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_20/O
|
|
net (fo=1, unplaced) 0.449 -0.376 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_20_n_0
|
|
r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_19/I5
|
|
LUT6 (Prop_lut6_I5_O) 0.124 -0.252 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_19/O
|
|
net (fo=1, unplaced) 0.000 -0.252 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_19_n_0
|
|
r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/S[0]
|
|
CARRY4 (Prop_carry4_S[0]_CO[3])
|
|
0.532 0.280 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/CO[3]
|
|
net (fo=1, unplaced) 0.000 0.280 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10_n_0
|
|
r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CI
|
|
CARRY4 (Prop_carry4_CI_CO[3])
|
|
0.114 0.394 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CO[3]
|
|
net (fo=1, unplaced) 0.000 0.394 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9_n_0
|
|
r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/CI
|
|
CARRY4 (Prop_carry4_CI_CO[3])
|
|
0.114 0.508 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/CO[3]
|
|
net (fo=1, unplaced) 0.000 0.508 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11_n_0
|
|
r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_10/CI
|
|
CARRY4 (Prop_carry4_CI_CO[3])
|
|
0.114 0.622 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_10/CO[3]
|
|
net (fo=1, unplaced) 0.000 0.622 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_10_n_0
|
|
r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2_i_9/CI
|
|
CARRY4 (Prop_carry4_CI_O[3])
|
|
0.329 0.951 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2_i_9/O[3]
|
|
net (fo=3, unplaced) 0.826 1.777 u_axi_ram/u_axi_sram_sp/upper_wrap_boundary[29]
|
|
r u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1_i_2/I0
|
|
LUT6 (Prop_lut6_I0_O) 0.307 2.084 r u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1_i_2/O
|
|
net (fo=1, unplaced) 0.000 2.084 u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1_i_2_n_0
|
|
r u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1/S[1]
|
|
CARRY4 (Prop_carry4_S[1]_CO[2])
|
|
0.570 2.654 r u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1/CO[2]
|
|
net (fo=23, unplaced) 0.515 3.169 u_axi_ram/u_axi_sram_sp/req_addr_d10_in
|
|
r u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/I5
|
|
LUT6 (Prop_lut6_I5_O) 0.310 3.479 f u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/O
|
|
net (fo=2, unplaced) 0.460 3.939 u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7_n_0
|
|
f u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/I1
|
|
LUT6 (Prop_lut6_I1_O) 0.124 4.063 f u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/O
|
|
net (fo=80, unplaced) 0.543 4.606 u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/soc_sram_addr[0]
|
|
f u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/base_ram_data_IOBUF[31]_inst_i_3/I2
|
|
LUT3 (Prop_lut3_I2_O) 0.124 4.730 r u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/base_ram_data_IOBUF[31]_inst_i_3/O
|
|
net (fo=1, unplaced) 0.449 5.179 u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/u_axi_ram/base_ram_data1
|
|
r u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/base_ram_data_IOBUF[31]_inst_i_2/I0
|
|
LUT1 (Prop_lut1_I0_O) 0.124 5.303 f u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/base_ram_data_IOBUF[31]_inst_i_2/O
|
|
net (fo=32, unplaced) 0.800 6.102 base_ram_data_IOBUF[13]_inst/T
|
|
V22 f base_ram_data_IOBUF[13]_inst/OBUFT/T
|
|
V22 OBUFT (TriStatE_obuft_T_O)
|
|
3.570 9.672 r base_ram_data_IOBUF[13]_inst/OBUFT/O
|
|
net (fo=1, unset) 0.000 9.672 base_ram_data[13]
|
|
V22 r base_ram_data[13] (INOUT)
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock sys_clk rise edge) 20.000 20.000 r
|
|
K21 0.000 20.000 r clk (IN)
|
|
net (fo=0) 0.000 20.000 pll_clk.u_clk_pll/inst/clk_in1
|
|
K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I
|
|
K21 IBUF (Prop_ibuf_I_O) 1.393 21.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O
|
|
net (fo=1, unplaced) 0.439 21.832 pll_clk.u_clk_pll/inst/clk_in1_clk_pll
|
|
r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1
|
|
PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1)
|
|
-6.040 15.792 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1
|
|
clock pessimism -0.513 15.279
|
|
clock uncertainty -0.071 15.209
|
|
output delay -0.300 14.909
|
|
-------------------------------------------------------------------
|
|
required time 14.909
|
|
arrival time -9.672
|
|
-------------------------------------------------------------------
|
|
slack 5.236
|
|
|
|
Slack (MET) : 5.237ns (required time - arrival time)
|
|
Source: u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[2]/C
|
|
(rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Destination: base_ram_data[3]
|
|
(output port clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Path Group: sys_clk
|
|
Path Type: Max at Slow Process Corner
|
|
Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns)
|
|
Data Path Delay: 12.697ns (logic 7.357ns (57.938%) route 5.341ns (42.062%))
|
|
Logic Levels: 15 (CARRY4=6 LUT1=1 LUT3=1 LUT4=1 LUT5=1 LUT6=4 OBUFT=1)
|
|
Output Delay: 0.300ns
|
|
Clock Path Skew: -1.695ns (DCD - SCD + CPR)
|
|
Destination Clock Delay (DCD): -4.208ns = ( 15.792 - 20.000 )
|
|
Source Clock Delay (SCD): -3.025ns
|
|
Clock Pessimism Removal (CPR): -0.513ns
|
|
Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Discrete Jitter (DJ): 0.122ns
|
|
Phase Error (PE): 0.000ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock sys_clk rise edge) 0.000 0.000 r
|
|
K21 0.000 0.000 r clk (IN)
|
|
net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1
|
|
K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I
|
|
K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O
|
|
net (fo=1, unplaced) 0.584 2.047 pll_clk.u_clk_pll/inst/clk_in1_clk_pll
|
|
r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1
|
|
PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1)
|
|
-6.768 -4.721 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1
|
|
net (fo=1, unplaced) 0.800 -3.921 pll_clk.u_clk_pll/inst/sys_clk_clk_pll
|
|
r pll_clk.u_clk_pll/inst/clkout2_buf/I
|
|
BUFG (Prop_bufg_I_O) 0.096 -3.825 r pll_clk.u_clk_pll/inst/clkout2_buf/O
|
|
net (fo=10994, unplaced) 0.800 -3.025 u_axi_ram/u_axi_sram_sp/sys_clk
|
|
FDCE r u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[2]/C
|
|
------------------------------------------------------------------- -------------------
|
|
FDCE (Prop_fdce_C_Q) 0.456 -2.569 f u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[2]/Q
|
|
net (fo=56, unplaced) 0.826 -1.743 u_axi_ram/u_axi_sram_sp/len[2]
|
|
f u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6/I1
|
|
LUT4 (Prop_lut4_I1_O) 0.321 -1.422 r u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6/O
|
|
net (fo=4, unplaced) 0.473 -0.949 u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6_n_0
|
|
r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_20/I1
|
|
LUT5 (Prop_lut5_I1_O) 0.124 -0.825 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_20/O
|
|
net (fo=1, unplaced) 0.449 -0.376 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_20_n_0
|
|
r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_19/I5
|
|
LUT6 (Prop_lut6_I5_O) 0.124 -0.252 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_19/O
|
|
net (fo=1, unplaced) 0.000 -0.252 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_19_n_0
|
|
r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/S[0]
|
|
CARRY4 (Prop_carry4_S[0]_CO[3])
|
|
0.532 0.280 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/CO[3]
|
|
net (fo=1, unplaced) 0.000 0.280 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10_n_0
|
|
r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CI
|
|
CARRY4 (Prop_carry4_CI_CO[3])
|
|
0.114 0.394 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CO[3]
|
|
net (fo=1, unplaced) 0.000 0.394 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9_n_0
|
|
r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/CI
|
|
CARRY4 (Prop_carry4_CI_CO[3])
|
|
0.114 0.508 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/CO[3]
|
|
net (fo=1, unplaced) 0.000 0.508 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11_n_0
|
|
r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_10/CI
|
|
CARRY4 (Prop_carry4_CI_CO[3])
|
|
0.114 0.622 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_10/CO[3]
|
|
net (fo=1, unplaced) 0.000 0.622 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_10_n_0
|
|
r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2_i_9/CI
|
|
CARRY4 (Prop_carry4_CI_O[3])
|
|
0.329 0.951 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2_i_9/O[3]
|
|
net (fo=3, unplaced) 0.826 1.777 u_axi_ram/u_axi_sram_sp/upper_wrap_boundary[29]
|
|
r u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1_i_2/I0
|
|
LUT6 (Prop_lut6_I0_O) 0.307 2.084 r u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1_i_2/O
|
|
net (fo=1, unplaced) 0.000 2.084 u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1_i_2_n_0
|
|
r u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1/S[1]
|
|
CARRY4 (Prop_carry4_S[1]_CO[2])
|
|
0.570 2.654 r u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1/CO[2]
|
|
net (fo=23, unplaced) 0.515 3.169 u_axi_ram/u_axi_sram_sp/req_addr_d10_in
|
|
r u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/I5
|
|
LUT6 (Prop_lut6_I5_O) 0.310 3.479 f u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/O
|
|
net (fo=2, unplaced) 0.460 3.939 u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7_n_0
|
|
f u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/I1
|
|
LUT6 (Prop_lut6_I1_O) 0.124 4.063 f u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/O
|
|
net (fo=80, unplaced) 0.543 4.606 u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/soc_sram_addr[0]
|
|
f u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/base_ram_data_IOBUF[31]_inst_i_3/I2
|
|
LUT3 (Prop_lut3_I2_O) 0.124 4.730 r u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/base_ram_data_IOBUF[31]_inst_i_3/O
|
|
net (fo=1, unplaced) 0.449 5.179 u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/u_axi_ram/base_ram_data1
|
|
r u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/base_ram_data_IOBUF[31]_inst_i_2/I0
|
|
LUT1 (Prop_lut1_I0_O) 0.124 5.303 f u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/base_ram_data_IOBUF[31]_inst_i_2/O
|
|
net (fo=32, unplaced) 0.800 6.102 base_ram_data_IOBUF[3]_inst/T
|
|
M25 f base_ram_data_IOBUF[3]_inst/OBUFT/T
|
|
M25 OBUFT (TriStatE_obuft_T_O)
|
|
3.570 9.672 r base_ram_data_IOBUF[3]_inst/OBUFT/O
|
|
net (fo=1, unset) 0.000 9.672 base_ram_data[3]
|
|
M25 r base_ram_data[3] (INOUT)
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock sys_clk rise edge) 20.000 20.000 r
|
|
K21 0.000 20.000 r clk (IN)
|
|
net (fo=0) 0.000 20.000 pll_clk.u_clk_pll/inst/clk_in1
|
|
K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I
|
|
K21 IBUF (Prop_ibuf_I_O) 1.393 21.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O
|
|
net (fo=1, unplaced) 0.439 21.832 pll_clk.u_clk_pll/inst/clk_in1_clk_pll
|
|
r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1
|
|
PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1)
|
|
-6.040 15.792 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1
|
|
clock pessimism -0.513 15.279
|
|
clock uncertainty -0.071 15.209
|
|
output delay -0.300 14.909
|
|
-------------------------------------------------------------------
|
|
required time 14.909
|
|
arrival time -9.672
|
|
-------------------------------------------------------------------
|
|
slack 5.237
|
|
|
|
Slack (MET) : 5.237ns (required time - arrival time)
|
|
Source: u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[2]/C
|
|
(rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Destination: base_ram_data[14]
|
|
(output port clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Path Group: sys_clk
|
|
Path Type: Max at Slow Process Corner
|
|
Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns)
|
|
Data Path Delay: 12.697ns (logic 7.357ns (57.938%) route 5.341ns (42.062%))
|
|
Logic Levels: 15 (CARRY4=6 LUT1=1 LUT3=1 LUT4=1 LUT5=1 LUT6=4 OBUFT=1)
|
|
Output Delay: 0.300ns
|
|
Clock Path Skew: -1.695ns (DCD - SCD + CPR)
|
|
Destination Clock Delay (DCD): -4.208ns = ( 15.792 - 20.000 )
|
|
Source Clock Delay (SCD): -3.025ns
|
|
Clock Pessimism Removal (CPR): -0.513ns
|
|
Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Discrete Jitter (DJ): 0.122ns
|
|
Phase Error (PE): 0.000ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock sys_clk rise edge) 0.000 0.000 r
|
|
K21 0.000 0.000 r clk (IN)
|
|
net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1
|
|
K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I
|
|
K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O
|
|
net (fo=1, unplaced) 0.584 2.047 pll_clk.u_clk_pll/inst/clk_in1_clk_pll
|
|
r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1
|
|
PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1)
|
|
-6.768 -4.721 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1
|
|
net (fo=1, unplaced) 0.800 -3.921 pll_clk.u_clk_pll/inst/sys_clk_clk_pll
|
|
r pll_clk.u_clk_pll/inst/clkout2_buf/I
|
|
BUFG (Prop_bufg_I_O) 0.096 -3.825 r pll_clk.u_clk_pll/inst/clkout2_buf/O
|
|
net (fo=10994, unplaced) 0.800 -3.025 u_axi_ram/u_axi_sram_sp/sys_clk
|
|
FDCE r u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[2]/C
|
|
------------------------------------------------------------------- -------------------
|
|
FDCE (Prop_fdce_C_Q) 0.456 -2.569 f u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[2]/Q
|
|
net (fo=56, unplaced) 0.826 -1.743 u_axi_ram/u_axi_sram_sp/len[2]
|
|
f u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6/I1
|
|
LUT4 (Prop_lut4_I1_O) 0.321 -1.422 r u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6/O
|
|
net (fo=4, unplaced) 0.473 -0.949 u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6_n_0
|
|
r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_20/I1
|
|
LUT5 (Prop_lut5_I1_O) 0.124 -0.825 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_20/O
|
|
net (fo=1, unplaced) 0.449 -0.376 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_20_n_0
|
|
r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_19/I5
|
|
LUT6 (Prop_lut6_I5_O) 0.124 -0.252 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_19/O
|
|
net (fo=1, unplaced) 0.000 -0.252 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_19_n_0
|
|
r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/S[0]
|
|
CARRY4 (Prop_carry4_S[0]_CO[3])
|
|
0.532 0.280 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/CO[3]
|
|
net (fo=1, unplaced) 0.000 0.280 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10_n_0
|
|
r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CI
|
|
CARRY4 (Prop_carry4_CI_CO[3])
|
|
0.114 0.394 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CO[3]
|
|
net (fo=1, unplaced) 0.000 0.394 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9_n_0
|
|
r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/CI
|
|
CARRY4 (Prop_carry4_CI_CO[3])
|
|
0.114 0.508 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/CO[3]
|
|
net (fo=1, unplaced) 0.000 0.508 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11_n_0
|
|
r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_10/CI
|
|
CARRY4 (Prop_carry4_CI_CO[3])
|
|
0.114 0.622 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_10/CO[3]
|
|
net (fo=1, unplaced) 0.000 0.622 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_10_n_0
|
|
r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2_i_9/CI
|
|
CARRY4 (Prop_carry4_CI_O[3])
|
|
0.329 0.951 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2_i_9/O[3]
|
|
net (fo=3, unplaced) 0.826 1.777 u_axi_ram/u_axi_sram_sp/upper_wrap_boundary[29]
|
|
r u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1_i_2/I0
|
|
LUT6 (Prop_lut6_I0_O) 0.307 2.084 r u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1_i_2/O
|
|
net (fo=1, unplaced) 0.000 2.084 u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1_i_2_n_0
|
|
r u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1/S[1]
|
|
CARRY4 (Prop_carry4_S[1]_CO[2])
|
|
0.570 2.654 r u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1/CO[2]
|
|
net (fo=23, unplaced) 0.515 3.169 u_axi_ram/u_axi_sram_sp/req_addr_d10_in
|
|
r u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/I5
|
|
LUT6 (Prop_lut6_I5_O) 0.310 3.479 f u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/O
|
|
net (fo=2, unplaced) 0.460 3.939 u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7_n_0
|
|
f u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/I1
|
|
LUT6 (Prop_lut6_I1_O) 0.124 4.063 f u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/O
|
|
net (fo=80, unplaced) 0.543 4.606 u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/soc_sram_addr[0]
|
|
f u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/base_ram_data_IOBUF[31]_inst_i_3/I2
|
|
LUT3 (Prop_lut3_I2_O) 0.124 4.730 r u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/base_ram_data_IOBUF[31]_inst_i_3/O
|
|
net (fo=1, unplaced) 0.449 5.179 u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/u_axi_ram/base_ram_data1
|
|
r u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/base_ram_data_IOBUF[31]_inst_i_2/I0
|
|
LUT1 (Prop_lut1_I0_O) 0.124 5.303 f u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/base_ram_data_IOBUF[31]_inst_i_2/O
|
|
net (fo=32, unplaced) 0.800 6.102 base_ram_data_IOBUF[14]_inst/T
|
|
V23 f base_ram_data_IOBUF[14]_inst/OBUFT/T
|
|
V23 OBUFT (TriStatE_obuft_T_O)
|
|
3.570 9.672 r base_ram_data_IOBUF[14]_inst/OBUFT/O
|
|
net (fo=1, unset) 0.000 9.672 base_ram_data[14]
|
|
V23 r base_ram_data[14] (INOUT)
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock sys_clk rise edge) 20.000 20.000 r
|
|
K21 0.000 20.000 r clk (IN)
|
|
net (fo=0) 0.000 20.000 pll_clk.u_clk_pll/inst/clk_in1
|
|
K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I
|
|
K21 IBUF (Prop_ibuf_I_O) 1.393 21.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O
|
|
net (fo=1, unplaced) 0.439 21.832 pll_clk.u_clk_pll/inst/clk_in1_clk_pll
|
|
r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1
|
|
PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1)
|
|
-6.040 15.792 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1
|
|
clock pessimism -0.513 15.279
|
|
clock uncertainty -0.071 15.209
|
|
output delay -0.300 14.909
|
|
-------------------------------------------------------------------
|
|
required time 14.909
|
|
arrival time -9.672
|
|
-------------------------------------------------------------------
|
|
slack 5.237
|
|
|
|
Slack (MET) : 5.237ns (required time - arrival time)
|
|
Source: u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[2]/C
|
|
(rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Destination: base_ram_data[9]
|
|
(output port clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Path Group: sys_clk
|
|
Path Type: Max at Slow Process Corner
|
|
Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns)
|
|
Data Path Delay: 12.697ns (logic 7.356ns (57.936%) route 5.341ns (42.064%))
|
|
Logic Levels: 15 (CARRY4=6 LUT1=1 LUT3=1 LUT4=1 LUT5=1 LUT6=4 OBUFT=1)
|
|
Output Delay: 0.300ns
|
|
Clock Path Skew: -1.695ns (DCD - SCD + CPR)
|
|
Destination Clock Delay (DCD): -4.208ns = ( 15.792 - 20.000 )
|
|
Source Clock Delay (SCD): -3.025ns
|
|
Clock Pessimism Removal (CPR): -0.513ns
|
|
Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Discrete Jitter (DJ): 0.122ns
|
|
Phase Error (PE): 0.000ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock sys_clk rise edge) 0.000 0.000 r
|
|
K21 0.000 0.000 r clk (IN)
|
|
net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1
|
|
K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I
|
|
K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O
|
|
net (fo=1, unplaced) 0.584 2.047 pll_clk.u_clk_pll/inst/clk_in1_clk_pll
|
|
r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1
|
|
PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1)
|
|
-6.768 -4.721 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1
|
|
net (fo=1, unplaced) 0.800 -3.921 pll_clk.u_clk_pll/inst/sys_clk_clk_pll
|
|
r pll_clk.u_clk_pll/inst/clkout2_buf/I
|
|
BUFG (Prop_bufg_I_O) 0.096 -3.825 r pll_clk.u_clk_pll/inst/clkout2_buf/O
|
|
net (fo=10994, unplaced) 0.800 -3.025 u_axi_ram/u_axi_sram_sp/sys_clk
|
|
FDCE r u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[2]/C
|
|
------------------------------------------------------------------- -------------------
|
|
FDCE (Prop_fdce_C_Q) 0.456 -2.569 f u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[2]/Q
|
|
net (fo=56, unplaced) 0.826 -1.743 u_axi_ram/u_axi_sram_sp/len[2]
|
|
f u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6/I1
|
|
LUT4 (Prop_lut4_I1_O) 0.321 -1.422 r u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6/O
|
|
net (fo=4, unplaced) 0.473 -0.949 u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6_n_0
|
|
r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_20/I1
|
|
LUT5 (Prop_lut5_I1_O) 0.124 -0.825 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_20/O
|
|
net (fo=1, unplaced) 0.449 -0.376 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_20_n_0
|
|
r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_19/I5
|
|
LUT6 (Prop_lut6_I5_O) 0.124 -0.252 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_19/O
|
|
net (fo=1, unplaced) 0.000 -0.252 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_19_n_0
|
|
r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/S[0]
|
|
CARRY4 (Prop_carry4_S[0]_CO[3])
|
|
0.532 0.280 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/CO[3]
|
|
net (fo=1, unplaced) 0.000 0.280 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10_n_0
|
|
r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CI
|
|
CARRY4 (Prop_carry4_CI_CO[3])
|
|
0.114 0.394 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CO[3]
|
|
net (fo=1, unplaced) 0.000 0.394 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9_n_0
|
|
r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/CI
|
|
CARRY4 (Prop_carry4_CI_CO[3])
|
|
0.114 0.508 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/CO[3]
|
|
net (fo=1, unplaced) 0.000 0.508 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11_n_0
|
|
r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_10/CI
|
|
CARRY4 (Prop_carry4_CI_CO[3])
|
|
0.114 0.622 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_10/CO[3]
|
|
net (fo=1, unplaced) 0.000 0.622 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_10_n_0
|
|
r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2_i_9/CI
|
|
CARRY4 (Prop_carry4_CI_O[3])
|
|
0.329 0.951 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2_i_9/O[3]
|
|
net (fo=3, unplaced) 0.826 1.777 u_axi_ram/u_axi_sram_sp/upper_wrap_boundary[29]
|
|
r u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1_i_2/I0
|
|
LUT6 (Prop_lut6_I0_O) 0.307 2.084 r u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1_i_2/O
|
|
net (fo=1, unplaced) 0.000 2.084 u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1_i_2_n_0
|
|
r u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1/S[1]
|
|
CARRY4 (Prop_carry4_S[1]_CO[2])
|
|
0.570 2.654 r u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1/CO[2]
|
|
net (fo=23, unplaced) 0.515 3.169 u_axi_ram/u_axi_sram_sp/req_addr_d10_in
|
|
r u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/I5
|
|
LUT6 (Prop_lut6_I5_O) 0.310 3.479 f u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/O
|
|
net (fo=2, unplaced) 0.460 3.939 u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7_n_0
|
|
f u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/I1
|
|
LUT6 (Prop_lut6_I1_O) 0.124 4.063 f u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/O
|
|
net (fo=80, unplaced) 0.543 4.606 u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/soc_sram_addr[0]
|
|
f u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/base_ram_data_IOBUF[31]_inst_i_3/I2
|
|
LUT3 (Prop_lut3_I2_O) 0.124 4.730 r u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/base_ram_data_IOBUF[31]_inst_i_3/O
|
|
net (fo=1, unplaced) 0.449 5.179 u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/u_axi_ram/base_ram_data1
|
|
r u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/base_ram_data_IOBUF[31]_inst_i_2/I0
|
|
LUT1 (Prop_lut1_I0_O) 0.124 5.303 f u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/base_ram_data_IOBUF[31]_inst_i_2/O
|
|
net (fo=32, unplaced) 0.800 6.102 base_ram_data_IOBUF[9]_inst/T
|
|
Y23 f base_ram_data_IOBUF[9]_inst/OBUFT/T
|
|
Y23 OBUFT (TriStatE_obuft_T_O)
|
|
3.569 9.671 r base_ram_data_IOBUF[9]_inst/OBUFT/O
|
|
net (fo=1, unset) 0.000 9.671 base_ram_data[9]
|
|
Y23 r base_ram_data[9] (INOUT)
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock sys_clk rise edge) 20.000 20.000 r
|
|
K21 0.000 20.000 r clk (IN)
|
|
net (fo=0) 0.000 20.000 pll_clk.u_clk_pll/inst/clk_in1
|
|
K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I
|
|
K21 IBUF (Prop_ibuf_I_O) 1.393 21.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O
|
|
net (fo=1, unplaced) 0.439 21.832 pll_clk.u_clk_pll/inst/clk_in1_clk_pll
|
|
r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1
|
|
PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1)
|
|
-6.040 15.792 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1
|
|
clock pessimism -0.513 15.279
|
|
clock uncertainty -0.071 15.209
|
|
output delay -0.300 14.909
|
|
-------------------------------------------------------------------
|
|
required time 14.909
|
|
arrival time -9.671
|
|
-------------------------------------------------------------------
|
|
slack 5.237
|
|
|
|
Slack (MET) : 5.239ns (required time - arrival time)
|
|
Source: u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[2]/C
|
|
(rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Destination: base_ram_data[6]
|
|
(output port clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Path Group: sys_clk
|
|
Path Type: Max at Slow Process Corner
|
|
Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns)
|
|
Data Path Delay: 12.695ns (logic 7.354ns (57.930%) route 5.341ns (42.070%))
|
|
Logic Levels: 15 (CARRY4=6 LUT1=1 LUT3=1 LUT4=1 LUT5=1 LUT6=4 OBUFT=1)
|
|
Output Delay: 0.300ns
|
|
Clock Path Skew: -1.695ns (DCD - SCD + CPR)
|
|
Destination Clock Delay (DCD): -4.208ns = ( 15.792 - 20.000 )
|
|
Source Clock Delay (SCD): -3.025ns
|
|
Clock Pessimism Removal (CPR): -0.513ns
|
|
Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Discrete Jitter (DJ): 0.122ns
|
|
Phase Error (PE): 0.000ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock sys_clk rise edge) 0.000 0.000 r
|
|
K21 0.000 0.000 r clk (IN)
|
|
net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1
|
|
K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I
|
|
K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O
|
|
net (fo=1, unplaced) 0.584 2.047 pll_clk.u_clk_pll/inst/clk_in1_clk_pll
|
|
r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1
|
|
PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1)
|
|
-6.768 -4.721 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1
|
|
net (fo=1, unplaced) 0.800 -3.921 pll_clk.u_clk_pll/inst/sys_clk_clk_pll
|
|
r pll_clk.u_clk_pll/inst/clkout2_buf/I
|
|
BUFG (Prop_bufg_I_O) 0.096 -3.825 r pll_clk.u_clk_pll/inst/clkout2_buf/O
|
|
net (fo=10994, unplaced) 0.800 -3.025 u_axi_ram/u_axi_sram_sp/sys_clk
|
|
FDCE r u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[2]/C
|
|
------------------------------------------------------------------- -------------------
|
|
FDCE (Prop_fdce_C_Q) 0.456 -2.569 f u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[2]/Q
|
|
net (fo=56, unplaced) 0.826 -1.743 u_axi_ram/u_axi_sram_sp/len[2]
|
|
f u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6/I1
|
|
LUT4 (Prop_lut4_I1_O) 0.321 -1.422 r u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6/O
|
|
net (fo=4, unplaced) 0.473 -0.949 u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6_n_0
|
|
r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_20/I1
|
|
LUT5 (Prop_lut5_I1_O) 0.124 -0.825 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_20/O
|
|
net (fo=1, unplaced) 0.449 -0.376 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_20_n_0
|
|
r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_19/I5
|
|
LUT6 (Prop_lut6_I5_O) 0.124 -0.252 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_19/O
|
|
net (fo=1, unplaced) 0.000 -0.252 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_19_n_0
|
|
r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/S[0]
|
|
CARRY4 (Prop_carry4_S[0]_CO[3])
|
|
0.532 0.280 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/CO[3]
|
|
net (fo=1, unplaced) 0.000 0.280 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10_n_0
|
|
r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CI
|
|
CARRY4 (Prop_carry4_CI_CO[3])
|
|
0.114 0.394 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CO[3]
|
|
net (fo=1, unplaced) 0.000 0.394 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9_n_0
|
|
r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/CI
|
|
CARRY4 (Prop_carry4_CI_CO[3])
|
|
0.114 0.508 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/CO[3]
|
|
net (fo=1, unplaced) 0.000 0.508 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11_n_0
|
|
r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_10/CI
|
|
CARRY4 (Prop_carry4_CI_CO[3])
|
|
0.114 0.622 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_10/CO[3]
|
|
net (fo=1, unplaced) 0.000 0.622 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_10_n_0
|
|
r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2_i_9/CI
|
|
CARRY4 (Prop_carry4_CI_O[3])
|
|
0.329 0.951 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2_i_9/O[3]
|
|
net (fo=3, unplaced) 0.826 1.777 u_axi_ram/u_axi_sram_sp/upper_wrap_boundary[29]
|
|
r u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1_i_2/I0
|
|
LUT6 (Prop_lut6_I0_O) 0.307 2.084 r u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1_i_2/O
|
|
net (fo=1, unplaced) 0.000 2.084 u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1_i_2_n_0
|
|
r u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1/S[1]
|
|
CARRY4 (Prop_carry4_S[1]_CO[2])
|
|
0.570 2.654 r u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1/CO[2]
|
|
net (fo=23, unplaced) 0.515 3.169 u_axi_ram/u_axi_sram_sp/req_addr_d10_in
|
|
r u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/I5
|
|
LUT6 (Prop_lut6_I5_O) 0.310 3.479 f u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/O
|
|
net (fo=2, unplaced) 0.460 3.939 u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7_n_0
|
|
f u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/I1
|
|
LUT6 (Prop_lut6_I1_O) 0.124 4.063 f u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/O
|
|
net (fo=80, unplaced) 0.543 4.606 u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/soc_sram_addr[0]
|
|
f u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/base_ram_data_IOBUF[31]_inst_i_3/I2
|
|
LUT3 (Prop_lut3_I2_O) 0.124 4.730 r u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/base_ram_data_IOBUF[31]_inst_i_3/O
|
|
net (fo=1, unplaced) 0.449 5.179 u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/u_axi_ram/base_ram_data1
|
|
r u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/base_ram_data_IOBUF[31]_inst_i_2/I0
|
|
LUT1 (Prop_lut1_I0_O) 0.124 5.303 f u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/base_ram_data_IOBUF[31]_inst_i_2/O
|
|
net (fo=32, unplaced) 0.800 6.102 base_ram_data_IOBUF[6]_inst/T
|
|
P26 f base_ram_data_IOBUF[6]_inst/OBUFT/T
|
|
P26 OBUFT (TriStatE_obuft_T_O)
|
|
3.567 9.669 r base_ram_data_IOBUF[6]_inst/OBUFT/O
|
|
net (fo=1, unset) 0.000 9.669 base_ram_data[6]
|
|
P26 r base_ram_data[6] (INOUT)
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock sys_clk rise edge) 20.000 20.000 r
|
|
K21 0.000 20.000 r clk (IN)
|
|
net (fo=0) 0.000 20.000 pll_clk.u_clk_pll/inst/clk_in1
|
|
K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I
|
|
K21 IBUF (Prop_ibuf_I_O) 1.393 21.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O
|
|
net (fo=1, unplaced) 0.439 21.832 pll_clk.u_clk_pll/inst/clk_in1_clk_pll
|
|
r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1
|
|
PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1)
|
|
-6.040 15.792 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1
|
|
clock pessimism -0.513 15.279
|
|
clock uncertainty -0.071 15.209
|
|
output delay -0.300 14.909
|
|
-------------------------------------------------------------------
|
|
required time 14.909
|
|
arrival time -9.669
|
|
-------------------------------------------------------------------
|
|
slack 5.239
|
|
|
|
Slack (MET) : 5.242ns (required time - arrival time)
|
|
Source: u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[2]/C
|
|
(rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Destination: base_ram_data[1]
|
|
(output port clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Path Group: sys_clk
|
|
Path Type: Max at Slow Process Corner
|
|
Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns)
|
|
Data Path Delay: 12.692ns (logic 7.351ns (57.920%) route 5.341ns (42.080%))
|
|
Logic Levels: 15 (CARRY4=6 LUT1=1 LUT3=1 LUT4=1 LUT5=1 LUT6=4 OBUFT=1)
|
|
Output Delay: 0.300ns
|
|
Clock Path Skew: -1.695ns (DCD - SCD + CPR)
|
|
Destination Clock Delay (DCD): -4.208ns = ( 15.792 - 20.000 )
|
|
Source Clock Delay (SCD): -3.025ns
|
|
Clock Pessimism Removal (CPR): -0.513ns
|
|
Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Discrete Jitter (DJ): 0.122ns
|
|
Phase Error (PE): 0.000ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock sys_clk rise edge) 0.000 0.000 r
|
|
K21 0.000 0.000 r clk (IN)
|
|
net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1
|
|
K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I
|
|
K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O
|
|
net (fo=1, unplaced) 0.584 2.047 pll_clk.u_clk_pll/inst/clk_in1_clk_pll
|
|
r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1
|
|
PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1)
|
|
-6.768 -4.721 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1
|
|
net (fo=1, unplaced) 0.800 -3.921 pll_clk.u_clk_pll/inst/sys_clk_clk_pll
|
|
r pll_clk.u_clk_pll/inst/clkout2_buf/I
|
|
BUFG (Prop_bufg_I_O) 0.096 -3.825 r pll_clk.u_clk_pll/inst/clkout2_buf/O
|
|
net (fo=10994, unplaced) 0.800 -3.025 u_axi_ram/u_axi_sram_sp/sys_clk
|
|
FDCE r u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[2]/C
|
|
------------------------------------------------------------------- -------------------
|
|
FDCE (Prop_fdce_C_Q) 0.456 -2.569 f u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[2]/Q
|
|
net (fo=56, unplaced) 0.826 -1.743 u_axi_ram/u_axi_sram_sp/len[2]
|
|
f u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6/I1
|
|
LUT4 (Prop_lut4_I1_O) 0.321 -1.422 r u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6/O
|
|
net (fo=4, unplaced) 0.473 -0.949 u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6_n_0
|
|
r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_20/I1
|
|
LUT5 (Prop_lut5_I1_O) 0.124 -0.825 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_20/O
|
|
net (fo=1, unplaced) 0.449 -0.376 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_20_n_0
|
|
r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_19/I5
|
|
LUT6 (Prop_lut6_I5_O) 0.124 -0.252 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_19/O
|
|
net (fo=1, unplaced) 0.000 -0.252 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_19_n_0
|
|
r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/S[0]
|
|
CARRY4 (Prop_carry4_S[0]_CO[3])
|
|
0.532 0.280 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/CO[3]
|
|
net (fo=1, unplaced) 0.000 0.280 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10_n_0
|
|
r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CI
|
|
CARRY4 (Prop_carry4_CI_CO[3])
|
|
0.114 0.394 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CO[3]
|
|
net (fo=1, unplaced) 0.000 0.394 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9_n_0
|
|
r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/CI
|
|
CARRY4 (Prop_carry4_CI_CO[3])
|
|
0.114 0.508 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/CO[3]
|
|
net (fo=1, unplaced) 0.000 0.508 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11_n_0
|
|
r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_10/CI
|
|
CARRY4 (Prop_carry4_CI_CO[3])
|
|
0.114 0.622 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_10/CO[3]
|
|
net (fo=1, unplaced) 0.000 0.622 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_10_n_0
|
|
r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2_i_9/CI
|
|
CARRY4 (Prop_carry4_CI_O[3])
|
|
0.329 0.951 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2_i_9/O[3]
|
|
net (fo=3, unplaced) 0.826 1.777 u_axi_ram/u_axi_sram_sp/upper_wrap_boundary[29]
|
|
r u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1_i_2/I0
|
|
LUT6 (Prop_lut6_I0_O) 0.307 2.084 r u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1_i_2/O
|
|
net (fo=1, unplaced) 0.000 2.084 u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1_i_2_n_0
|
|
r u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1/S[1]
|
|
CARRY4 (Prop_carry4_S[1]_CO[2])
|
|
0.570 2.654 r u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1/CO[2]
|
|
net (fo=23, unplaced) 0.515 3.169 u_axi_ram/u_axi_sram_sp/req_addr_d10_in
|
|
r u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/I5
|
|
LUT6 (Prop_lut6_I5_O) 0.310 3.479 f u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/O
|
|
net (fo=2, unplaced) 0.460 3.939 u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7_n_0
|
|
f u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/I1
|
|
LUT6 (Prop_lut6_I1_O) 0.124 4.063 f u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/O
|
|
net (fo=80, unplaced) 0.543 4.606 u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/soc_sram_addr[0]
|
|
f u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/base_ram_data_IOBUF[31]_inst_i_3/I2
|
|
LUT3 (Prop_lut3_I2_O) 0.124 4.730 r u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/base_ram_data_IOBUF[31]_inst_i_3/O
|
|
net (fo=1, unplaced) 0.449 5.179 u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/u_axi_ram/base_ram_data1
|
|
r u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/base_ram_data_IOBUF[31]_inst_i_2/I0
|
|
LUT1 (Prop_lut1_I0_O) 0.124 5.303 f u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/base_ram_data_IOBUF[31]_inst_i_2/O
|
|
net (fo=32, unplaced) 0.800 6.102 base_ram_data_IOBUF[1]_inst/T
|
|
L25 f base_ram_data_IOBUF[1]_inst/OBUFT/T
|
|
L25 OBUFT (TriStatE_obuft_T_O)
|
|
3.564 9.666 r base_ram_data_IOBUF[1]_inst/OBUFT/O
|
|
net (fo=1, unset) 0.000 9.666 base_ram_data[1]
|
|
L25 r base_ram_data[1] (INOUT)
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock sys_clk rise edge) 20.000 20.000 r
|
|
K21 0.000 20.000 r clk (IN)
|
|
net (fo=0) 0.000 20.000 pll_clk.u_clk_pll/inst/clk_in1
|
|
K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I
|
|
K21 IBUF (Prop_ibuf_I_O) 1.393 21.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O
|
|
net (fo=1, unplaced) 0.439 21.832 pll_clk.u_clk_pll/inst/clk_in1_clk_pll
|
|
r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1
|
|
PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1)
|
|
-6.040 15.792 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1
|
|
clock pessimism -0.513 15.279
|
|
clock uncertainty -0.071 15.209
|
|
output delay -0.300 14.909
|
|
-------------------------------------------------------------------
|
|
required time 14.909
|
|
arrival time -9.666
|
|
-------------------------------------------------------------------
|
|
slack 5.242
|
|
|
|
Slack (MET) : 5.245ns (required time - arrival time)
|
|
Source: u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[2]/C
|
|
(rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Destination: ext_ram_data[28]
|
|
(output port clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Path Group: sys_clk
|
|
Path Type: Max at Slow Process Corner
|
|
Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns)
|
|
Data Path Delay: 12.689ns (logic 7.349ns (57.912%) route 5.341ns (42.088%))
|
|
Logic Levels: 15 (CARRY4=6 LUT1=1 LUT3=1 LUT4=1 LUT5=1 LUT6=4 OBUFT=1)
|
|
Output Delay: 0.300ns
|
|
Clock Path Skew: -1.695ns (DCD - SCD + CPR)
|
|
Destination Clock Delay (DCD): -4.208ns = ( 15.792 - 20.000 )
|
|
Source Clock Delay (SCD): -3.025ns
|
|
Clock Pessimism Removal (CPR): -0.513ns
|
|
Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Discrete Jitter (DJ): 0.122ns
|
|
Phase Error (PE): 0.000ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock sys_clk rise edge) 0.000 0.000 r
|
|
K21 0.000 0.000 r clk (IN)
|
|
net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1
|
|
K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I
|
|
K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O
|
|
net (fo=1, unplaced) 0.584 2.047 pll_clk.u_clk_pll/inst/clk_in1_clk_pll
|
|
r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1
|
|
PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1)
|
|
-6.768 -4.721 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1
|
|
net (fo=1, unplaced) 0.800 -3.921 pll_clk.u_clk_pll/inst/sys_clk_clk_pll
|
|
r pll_clk.u_clk_pll/inst/clkout2_buf/I
|
|
BUFG (Prop_bufg_I_O) 0.096 -3.825 r pll_clk.u_clk_pll/inst/clkout2_buf/O
|
|
net (fo=10994, unplaced) 0.800 -3.025 u_axi_ram/u_axi_sram_sp/sys_clk
|
|
FDCE r u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[2]/C
|
|
------------------------------------------------------------------- -------------------
|
|
FDCE (Prop_fdce_C_Q) 0.456 -2.569 f u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[2]/Q
|
|
net (fo=56, unplaced) 0.826 -1.743 u_axi_ram/u_axi_sram_sp/len[2]
|
|
f u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6/I1
|
|
LUT4 (Prop_lut4_I1_O) 0.321 -1.422 r u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6/O
|
|
net (fo=4, unplaced) 0.473 -0.949 u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6_n_0
|
|
r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_20/I1
|
|
LUT5 (Prop_lut5_I1_O) 0.124 -0.825 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_20/O
|
|
net (fo=1, unplaced) 0.449 -0.376 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_20_n_0
|
|
r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_19/I5
|
|
LUT6 (Prop_lut6_I5_O) 0.124 -0.252 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_19/O
|
|
net (fo=1, unplaced) 0.000 -0.252 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_19_n_0
|
|
r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/S[0]
|
|
CARRY4 (Prop_carry4_S[0]_CO[3])
|
|
0.532 0.280 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/CO[3]
|
|
net (fo=1, unplaced) 0.000 0.280 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10_n_0
|
|
r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CI
|
|
CARRY4 (Prop_carry4_CI_CO[3])
|
|
0.114 0.394 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CO[3]
|
|
net (fo=1, unplaced) 0.000 0.394 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9_n_0
|
|
r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/CI
|
|
CARRY4 (Prop_carry4_CI_CO[3])
|
|
0.114 0.508 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/CO[3]
|
|
net (fo=1, unplaced) 0.000 0.508 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11_n_0
|
|
r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_10/CI
|
|
CARRY4 (Prop_carry4_CI_CO[3])
|
|
0.114 0.622 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_10/CO[3]
|
|
net (fo=1, unplaced) 0.000 0.622 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_10_n_0
|
|
r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2_i_9/CI
|
|
CARRY4 (Prop_carry4_CI_O[3])
|
|
0.329 0.951 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2_i_9/O[3]
|
|
net (fo=3, unplaced) 0.826 1.777 u_axi_ram/u_axi_sram_sp/upper_wrap_boundary[29]
|
|
r u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1_i_2/I0
|
|
LUT6 (Prop_lut6_I0_O) 0.307 2.084 r u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1_i_2/O
|
|
net (fo=1, unplaced) 0.000 2.084 u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1_i_2_n_0
|
|
r u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1/S[1]
|
|
CARRY4 (Prop_carry4_S[1]_CO[2])
|
|
0.570 2.654 r u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1/CO[2]
|
|
net (fo=23, unplaced) 0.515 3.169 u_axi_ram/u_axi_sram_sp/req_addr_d10_in
|
|
r u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/I5
|
|
LUT6 (Prop_lut6_I5_O) 0.310 3.479 r u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/O
|
|
net (fo=2, unplaced) 0.460 3.939 u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7_n_0
|
|
r u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/I1
|
|
LUT6 (Prop_lut6_I1_O) 0.124 4.063 r u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/O
|
|
net (fo=80, unplaced) 0.543 4.606 u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/soc_sram_addr[0]
|
|
r u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/ext_ram_data_IOBUF[31]_inst_i_2/I2
|
|
LUT3 (Prop_lut3_I2_O) 0.118 4.724 r u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/ext_ram_data_IOBUF[31]_inst_i_2/O
|
|
net (fo=1, unplaced) 0.449 5.173 u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/u_axi_ram/ext_ram_data1
|
|
r u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/ext_ram_data_IOBUF[31]_inst_i_1/I0
|
|
LUT1 (Prop_lut1_I0_O) 0.124 5.297 f u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/ext_ram_data_IOBUF[31]_inst_i_1/O
|
|
net (fo=32, unplaced) 0.800 6.096 ext_ram_data_IOBUF[28]_inst/T
|
|
AD21 f ext_ram_data_IOBUF[28]_inst/OBUFT/T
|
|
AD21 OBUFT (TriStatE_obuft_T_O)
|
|
3.568 9.664 r ext_ram_data_IOBUF[28]_inst/OBUFT/O
|
|
net (fo=1, unset) 0.000 9.664 ext_ram_data[28]
|
|
AD21 r ext_ram_data[28] (INOUT)
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock sys_clk rise edge) 20.000 20.000 r
|
|
K21 0.000 20.000 r clk (IN)
|
|
net (fo=0) 0.000 20.000 pll_clk.u_clk_pll/inst/clk_in1
|
|
K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I
|
|
K21 IBUF (Prop_ibuf_I_O) 1.393 21.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O
|
|
net (fo=1, unplaced) 0.439 21.832 pll_clk.u_clk_pll/inst/clk_in1_clk_pll
|
|
r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1
|
|
PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1)
|
|
-6.040 15.792 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1
|
|
clock pessimism -0.513 15.279
|
|
clock uncertainty -0.071 15.209
|
|
output delay -0.300 14.909
|
|
-------------------------------------------------------------------
|
|
required time 14.909
|
|
arrival time -9.664
|
|
-------------------------------------------------------------------
|
|
slack 5.245
|
|
|
|
Slack (MET) : 5.245ns (required time - arrival time)
|
|
Source: u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[2]/C
|
|
(rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Destination: ext_ram_data[26]
|
|
(output port clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Path Group: sys_clk
|
|
Path Type: Max at Slow Process Corner
|
|
Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns)
|
|
Data Path Delay: 12.689ns (logic 7.348ns (57.911%) route 5.341ns (42.089%))
|
|
Logic Levels: 15 (CARRY4=6 LUT1=1 LUT3=1 LUT4=1 LUT5=1 LUT6=4 OBUFT=1)
|
|
Output Delay: 0.300ns
|
|
Clock Path Skew: -1.695ns (DCD - SCD + CPR)
|
|
Destination Clock Delay (DCD): -4.208ns = ( 15.792 - 20.000 )
|
|
Source Clock Delay (SCD): -3.025ns
|
|
Clock Pessimism Removal (CPR): -0.513ns
|
|
Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Discrete Jitter (DJ): 0.122ns
|
|
Phase Error (PE): 0.000ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock sys_clk rise edge) 0.000 0.000 r
|
|
K21 0.000 0.000 r clk (IN)
|
|
net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1
|
|
K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I
|
|
K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O
|
|
net (fo=1, unplaced) 0.584 2.047 pll_clk.u_clk_pll/inst/clk_in1_clk_pll
|
|
r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1
|
|
PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1)
|
|
-6.768 -4.721 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1
|
|
net (fo=1, unplaced) 0.800 -3.921 pll_clk.u_clk_pll/inst/sys_clk_clk_pll
|
|
r pll_clk.u_clk_pll/inst/clkout2_buf/I
|
|
BUFG (Prop_bufg_I_O) 0.096 -3.825 r pll_clk.u_clk_pll/inst/clkout2_buf/O
|
|
net (fo=10994, unplaced) 0.800 -3.025 u_axi_ram/u_axi_sram_sp/sys_clk
|
|
FDCE r u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[2]/C
|
|
------------------------------------------------------------------- -------------------
|
|
FDCE (Prop_fdce_C_Q) 0.456 -2.569 f u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[2]/Q
|
|
net (fo=56, unplaced) 0.826 -1.743 u_axi_ram/u_axi_sram_sp/len[2]
|
|
f u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6/I1
|
|
LUT4 (Prop_lut4_I1_O) 0.321 -1.422 r u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6/O
|
|
net (fo=4, unplaced) 0.473 -0.949 u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6_n_0
|
|
r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_20/I1
|
|
LUT5 (Prop_lut5_I1_O) 0.124 -0.825 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_20/O
|
|
net (fo=1, unplaced) 0.449 -0.376 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_20_n_0
|
|
r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_19/I5
|
|
LUT6 (Prop_lut6_I5_O) 0.124 -0.252 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_19/O
|
|
net (fo=1, unplaced) 0.000 -0.252 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_19_n_0
|
|
r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/S[0]
|
|
CARRY4 (Prop_carry4_S[0]_CO[3])
|
|
0.532 0.280 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/CO[3]
|
|
net (fo=1, unplaced) 0.000 0.280 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10_n_0
|
|
r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CI
|
|
CARRY4 (Prop_carry4_CI_CO[3])
|
|
0.114 0.394 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CO[3]
|
|
net (fo=1, unplaced) 0.000 0.394 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9_n_0
|
|
r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/CI
|
|
CARRY4 (Prop_carry4_CI_CO[3])
|
|
0.114 0.508 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/CO[3]
|
|
net (fo=1, unplaced) 0.000 0.508 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11_n_0
|
|
r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_10/CI
|
|
CARRY4 (Prop_carry4_CI_CO[3])
|
|
0.114 0.622 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_10/CO[3]
|
|
net (fo=1, unplaced) 0.000 0.622 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_10_n_0
|
|
r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2_i_9/CI
|
|
CARRY4 (Prop_carry4_CI_O[3])
|
|
0.329 0.951 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2_i_9/O[3]
|
|
net (fo=3, unplaced) 0.826 1.777 u_axi_ram/u_axi_sram_sp/upper_wrap_boundary[29]
|
|
r u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1_i_2/I0
|
|
LUT6 (Prop_lut6_I0_O) 0.307 2.084 r u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1_i_2/O
|
|
net (fo=1, unplaced) 0.000 2.084 u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1_i_2_n_0
|
|
r u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1/S[1]
|
|
CARRY4 (Prop_carry4_S[1]_CO[2])
|
|
0.570 2.654 r u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1/CO[2]
|
|
net (fo=23, unplaced) 0.515 3.169 u_axi_ram/u_axi_sram_sp/req_addr_d10_in
|
|
r u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/I5
|
|
LUT6 (Prop_lut6_I5_O) 0.310 3.479 r u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/O
|
|
net (fo=2, unplaced) 0.460 3.939 u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7_n_0
|
|
r u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/I1
|
|
LUT6 (Prop_lut6_I1_O) 0.124 4.063 r u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/O
|
|
net (fo=80, unplaced) 0.543 4.606 u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/soc_sram_addr[0]
|
|
r u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/ext_ram_data_IOBUF[31]_inst_i_2/I2
|
|
LUT3 (Prop_lut3_I2_O) 0.118 4.724 r u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/ext_ram_data_IOBUF[31]_inst_i_2/O
|
|
net (fo=1, unplaced) 0.449 5.173 u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/u_axi_ram/ext_ram_data1
|
|
r u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/ext_ram_data_IOBUF[31]_inst_i_1/I0
|
|
LUT1 (Prop_lut1_I0_O) 0.124 5.297 f u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/ext_ram_data_IOBUF[31]_inst_i_1/O
|
|
net (fo=32, unplaced) 0.800 6.096 ext_ram_data_IOBUF[26]_inst/T
|
|
AD20 f ext_ram_data_IOBUF[26]_inst/OBUFT/T
|
|
AD20 OBUFT (TriStatE_obuft_T_O)
|
|
3.567 9.664 r ext_ram_data_IOBUF[26]_inst/OBUFT/O
|
|
net (fo=1, unset) 0.000 9.664 ext_ram_data[26]
|
|
AD20 r ext_ram_data[26] (INOUT)
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock sys_clk rise edge) 20.000 20.000 r
|
|
K21 0.000 20.000 r clk (IN)
|
|
net (fo=0) 0.000 20.000 pll_clk.u_clk_pll/inst/clk_in1
|
|
K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I
|
|
K21 IBUF (Prop_ibuf_I_O) 1.393 21.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O
|
|
net (fo=1, unplaced) 0.439 21.832 pll_clk.u_clk_pll/inst/clk_in1_clk_pll
|
|
r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1
|
|
PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1)
|
|
-6.040 15.792 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1
|
|
clock pessimism -0.513 15.279
|
|
clock uncertainty -0.071 15.209
|
|
output delay -0.300 14.909
|
|
-------------------------------------------------------------------
|
|
required time 14.909
|
|
arrival time -9.664
|
|
-------------------------------------------------------------------
|
|
slack 5.245
|
|
|
|
Slack (MET) : 5.246ns (required time - arrival time)
|
|
Source: u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[2]/C
|
|
(rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Destination: base_ram_data[0]
|
|
(output port clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Path Group: sys_clk
|
|
Path Type: Max at Slow Process Corner
|
|
Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns)
|
|
Data Path Delay: 12.688ns (logic 7.347ns (57.906%) route 5.341ns (42.094%))
|
|
Logic Levels: 15 (CARRY4=6 LUT1=1 LUT3=1 LUT4=1 LUT5=1 LUT6=4 OBUFT=1)
|
|
Output Delay: 0.300ns
|
|
Clock Path Skew: -1.695ns (DCD - SCD + CPR)
|
|
Destination Clock Delay (DCD): -4.208ns = ( 15.792 - 20.000 )
|
|
Source Clock Delay (SCD): -3.025ns
|
|
Clock Pessimism Removal (CPR): -0.513ns
|
|
Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Discrete Jitter (DJ): 0.122ns
|
|
Phase Error (PE): 0.000ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock sys_clk rise edge) 0.000 0.000 r
|
|
K21 0.000 0.000 r clk (IN)
|
|
net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1
|
|
K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I
|
|
K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O
|
|
net (fo=1, unplaced) 0.584 2.047 pll_clk.u_clk_pll/inst/clk_in1_clk_pll
|
|
r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1
|
|
PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1)
|
|
-6.768 -4.721 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1
|
|
net (fo=1, unplaced) 0.800 -3.921 pll_clk.u_clk_pll/inst/sys_clk_clk_pll
|
|
r pll_clk.u_clk_pll/inst/clkout2_buf/I
|
|
BUFG (Prop_bufg_I_O) 0.096 -3.825 r pll_clk.u_clk_pll/inst/clkout2_buf/O
|
|
net (fo=10994, unplaced) 0.800 -3.025 u_axi_ram/u_axi_sram_sp/sys_clk
|
|
FDCE r u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[2]/C
|
|
------------------------------------------------------------------- -------------------
|
|
FDCE (Prop_fdce_C_Q) 0.456 -2.569 f u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[2]/Q
|
|
net (fo=56, unplaced) 0.826 -1.743 u_axi_ram/u_axi_sram_sp/len[2]
|
|
f u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6/I1
|
|
LUT4 (Prop_lut4_I1_O) 0.321 -1.422 r u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6/O
|
|
net (fo=4, unplaced) 0.473 -0.949 u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6_n_0
|
|
r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_20/I1
|
|
LUT5 (Prop_lut5_I1_O) 0.124 -0.825 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_20/O
|
|
net (fo=1, unplaced) 0.449 -0.376 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_20_n_0
|
|
r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_19/I5
|
|
LUT6 (Prop_lut6_I5_O) 0.124 -0.252 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_19/O
|
|
net (fo=1, unplaced) 0.000 -0.252 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_19_n_0
|
|
r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/S[0]
|
|
CARRY4 (Prop_carry4_S[0]_CO[3])
|
|
0.532 0.280 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/CO[3]
|
|
net (fo=1, unplaced) 0.000 0.280 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10_n_0
|
|
r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CI
|
|
CARRY4 (Prop_carry4_CI_CO[3])
|
|
0.114 0.394 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CO[3]
|
|
net (fo=1, unplaced) 0.000 0.394 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9_n_0
|
|
r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/CI
|
|
CARRY4 (Prop_carry4_CI_CO[3])
|
|
0.114 0.508 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/CO[3]
|
|
net (fo=1, unplaced) 0.000 0.508 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11_n_0
|
|
r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_10/CI
|
|
CARRY4 (Prop_carry4_CI_CO[3])
|
|
0.114 0.622 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_10/CO[3]
|
|
net (fo=1, unplaced) 0.000 0.622 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_10_n_0
|
|
r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2_i_9/CI
|
|
CARRY4 (Prop_carry4_CI_O[3])
|
|
0.329 0.951 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2_i_9/O[3]
|
|
net (fo=3, unplaced) 0.826 1.777 u_axi_ram/u_axi_sram_sp/upper_wrap_boundary[29]
|
|
r u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1_i_2/I0
|
|
LUT6 (Prop_lut6_I0_O) 0.307 2.084 r u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1_i_2/O
|
|
net (fo=1, unplaced) 0.000 2.084 u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1_i_2_n_0
|
|
r u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1/S[1]
|
|
CARRY4 (Prop_carry4_S[1]_CO[2])
|
|
0.570 2.654 r u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1/CO[2]
|
|
net (fo=23, unplaced) 0.515 3.169 u_axi_ram/u_axi_sram_sp/req_addr_d10_in
|
|
r u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/I5
|
|
LUT6 (Prop_lut6_I5_O) 0.310 3.479 f u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/O
|
|
net (fo=2, unplaced) 0.460 3.939 u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7_n_0
|
|
f u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/I1
|
|
LUT6 (Prop_lut6_I1_O) 0.124 4.063 f u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/O
|
|
net (fo=80, unplaced) 0.543 4.606 u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/soc_sram_addr[0]
|
|
f u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/base_ram_data_IOBUF[31]_inst_i_3/I2
|
|
LUT3 (Prop_lut3_I2_O) 0.124 4.730 r u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/base_ram_data_IOBUF[31]_inst_i_3/O
|
|
net (fo=1, unplaced) 0.449 5.179 u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/u_axi_ram/base_ram_data1
|
|
r u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/base_ram_data_IOBUF[31]_inst_i_2/I0
|
|
LUT1 (Prop_lut1_I0_O) 0.124 5.303 f u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/base_ram_data_IOBUF[31]_inst_i_2/O
|
|
net (fo=32, unplaced) 0.800 6.102 base_ram_data_IOBUF[0]_inst/T
|
|
L24 f base_ram_data_IOBUF[0]_inst/OBUFT/T
|
|
L24 OBUFT (TriStatE_obuft_T_O)
|
|
3.560 9.662 r base_ram_data_IOBUF[0]_inst/OBUFT/O
|
|
net (fo=1, unset) 0.000 9.662 base_ram_data[0]
|
|
L24 r base_ram_data[0] (INOUT)
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock sys_clk rise edge) 20.000 20.000 r
|
|
K21 0.000 20.000 r clk (IN)
|
|
net (fo=0) 0.000 20.000 pll_clk.u_clk_pll/inst/clk_in1
|
|
K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I
|
|
K21 IBUF (Prop_ibuf_I_O) 1.393 21.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O
|
|
net (fo=1, unplaced) 0.439 21.832 pll_clk.u_clk_pll/inst/clk_in1_clk_pll
|
|
r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1
|
|
PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1)
|
|
-6.040 15.792 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1
|
|
clock pessimism -0.513 15.279
|
|
clock uncertainty -0.071 15.209
|
|
output delay -0.300 14.909
|
|
-------------------------------------------------------------------
|
|
required time 14.909
|
|
arrival time -9.662
|
|
-------------------------------------------------------------------
|
|
slack 5.246
|
|
|
|
Slack (MET) : 5.247ns (required time - arrival time)
|
|
Source: u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[2]/C
|
|
(rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Destination: base_ram_data[7]
|
|
(output port clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Path Group: sys_clk
|
|
Path Type: Max at Slow Process Corner
|
|
Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns)
|
|
Data Path Delay: 12.687ns (logic 7.347ns (57.905%) route 5.341ns (42.095%))
|
|
Logic Levels: 15 (CARRY4=6 LUT1=1 LUT3=1 LUT4=1 LUT5=1 LUT6=4 OBUFT=1)
|
|
Output Delay: 0.300ns
|
|
Clock Path Skew: -1.695ns (DCD - SCD + CPR)
|
|
Destination Clock Delay (DCD): -4.208ns = ( 15.792 - 20.000 )
|
|
Source Clock Delay (SCD): -3.025ns
|
|
Clock Pessimism Removal (CPR): -0.513ns
|
|
Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Discrete Jitter (DJ): 0.122ns
|
|
Phase Error (PE): 0.000ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock sys_clk rise edge) 0.000 0.000 r
|
|
K21 0.000 0.000 r clk (IN)
|
|
net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1
|
|
K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I
|
|
K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O
|
|
net (fo=1, unplaced) 0.584 2.047 pll_clk.u_clk_pll/inst/clk_in1_clk_pll
|
|
r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1
|
|
PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1)
|
|
-6.768 -4.721 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1
|
|
net (fo=1, unplaced) 0.800 -3.921 pll_clk.u_clk_pll/inst/sys_clk_clk_pll
|
|
r pll_clk.u_clk_pll/inst/clkout2_buf/I
|
|
BUFG (Prop_bufg_I_O) 0.096 -3.825 r pll_clk.u_clk_pll/inst/clkout2_buf/O
|
|
net (fo=10994, unplaced) 0.800 -3.025 u_axi_ram/u_axi_sram_sp/sys_clk
|
|
FDCE r u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[2]/C
|
|
------------------------------------------------------------------- -------------------
|
|
FDCE (Prop_fdce_C_Q) 0.456 -2.569 f u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[2]/Q
|
|
net (fo=56, unplaced) 0.826 -1.743 u_axi_ram/u_axi_sram_sp/len[2]
|
|
f u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6/I1
|
|
LUT4 (Prop_lut4_I1_O) 0.321 -1.422 r u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6/O
|
|
net (fo=4, unplaced) 0.473 -0.949 u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6_n_0
|
|
r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_20/I1
|
|
LUT5 (Prop_lut5_I1_O) 0.124 -0.825 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_20/O
|
|
net (fo=1, unplaced) 0.449 -0.376 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_20_n_0
|
|
r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_19/I5
|
|
LUT6 (Prop_lut6_I5_O) 0.124 -0.252 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_19/O
|
|
net (fo=1, unplaced) 0.000 -0.252 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_19_n_0
|
|
r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/S[0]
|
|
CARRY4 (Prop_carry4_S[0]_CO[3])
|
|
0.532 0.280 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/CO[3]
|
|
net (fo=1, unplaced) 0.000 0.280 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10_n_0
|
|
r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CI
|
|
CARRY4 (Prop_carry4_CI_CO[3])
|
|
0.114 0.394 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CO[3]
|
|
net (fo=1, unplaced) 0.000 0.394 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9_n_0
|
|
r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/CI
|
|
CARRY4 (Prop_carry4_CI_CO[3])
|
|
0.114 0.508 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/CO[3]
|
|
net (fo=1, unplaced) 0.000 0.508 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11_n_0
|
|
r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_10/CI
|
|
CARRY4 (Prop_carry4_CI_CO[3])
|
|
0.114 0.622 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_10/CO[3]
|
|
net (fo=1, unplaced) 0.000 0.622 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_10_n_0
|
|
r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2_i_9/CI
|
|
CARRY4 (Prop_carry4_CI_O[3])
|
|
0.329 0.951 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2_i_9/O[3]
|
|
net (fo=3, unplaced) 0.826 1.777 u_axi_ram/u_axi_sram_sp/upper_wrap_boundary[29]
|
|
r u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1_i_2/I0
|
|
LUT6 (Prop_lut6_I0_O) 0.307 2.084 r u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1_i_2/O
|
|
net (fo=1, unplaced) 0.000 2.084 u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1_i_2_n_0
|
|
r u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1/S[1]
|
|
CARRY4 (Prop_carry4_S[1]_CO[2])
|
|
0.570 2.654 r u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1/CO[2]
|
|
net (fo=23, unplaced) 0.515 3.169 u_axi_ram/u_axi_sram_sp/req_addr_d10_in
|
|
r u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/I5
|
|
LUT6 (Prop_lut6_I5_O) 0.310 3.479 f u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/O
|
|
net (fo=2, unplaced) 0.460 3.939 u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7_n_0
|
|
f u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/I1
|
|
LUT6 (Prop_lut6_I1_O) 0.124 4.063 f u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/O
|
|
net (fo=80, unplaced) 0.543 4.606 u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/soc_sram_addr[0]
|
|
f u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/base_ram_data_IOBUF[31]_inst_i_3/I2
|
|
LUT3 (Prop_lut3_I2_O) 0.124 4.730 r u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/base_ram_data_IOBUF[31]_inst_i_3/O
|
|
net (fo=1, unplaced) 0.449 5.179 u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/u_axi_ram/base_ram_data1
|
|
r u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/base_ram_data_IOBUF[31]_inst_i_2/I0
|
|
LUT1 (Prop_lut1_I0_O) 0.124 5.303 f u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/base_ram_data_IOBUF[31]_inst_i_2/O
|
|
net (fo=32, unplaced) 0.800 6.102 base_ram_data_IOBUF[7]_inst/T
|
|
P25 f base_ram_data_IOBUF[7]_inst/OBUFT/T
|
|
P25 OBUFT (TriStatE_obuft_T_O)
|
|
3.560 9.662 r base_ram_data_IOBUF[7]_inst/OBUFT/O
|
|
net (fo=1, unset) 0.000 9.662 base_ram_data[7]
|
|
P25 r base_ram_data[7] (INOUT)
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock sys_clk rise edge) 20.000 20.000 r
|
|
K21 0.000 20.000 r clk (IN)
|
|
net (fo=0) 0.000 20.000 pll_clk.u_clk_pll/inst/clk_in1
|
|
K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I
|
|
K21 IBUF (Prop_ibuf_I_O) 1.393 21.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O
|
|
net (fo=1, unplaced) 0.439 21.832 pll_clk.u_clk_pll/inst/clk_in1_clk_pll
|
|
r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1
|
|
PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1)
|
|
-6.040 15.792 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1
|
|
clock pessimism -0.513 15.279
|
|
clock uncertainty -0.071 15.209
|
|
output delay -0.300 14.909
|
|
-------------------------------------------------------------------
|
|
required time 14.909
|
|
arrival time -9.662
|
|
-------------------------------------------------------------------
|
|
slack 5.247
|
|
|
|
Slack (MET) : 5.247ns (required time - arrival time)
|
|
Source: u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[2]/C
|
|
(rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Destination: base_ram_data[30]
|
|
(output port clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Path Group: sys_clk
|
|
Path Type: Max at Slow Process Corner
|
|
Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns)
|
|
Data Path Delay: 12.687ns (logic 7.346ns (57.905%) route 5.341ns (42.095%))
|
|
Logic Levels: 15 (CARRY4=6 LUT1=1 LUT3=1 LUT4=1 LUT5=1 LUT6=4 OBUFT=1)
|
|
Output Delay: 0.300ns
|
|
Clock Path Skew: -1.695ns (DCD - SCD + CPR)
|
|
Destination Clock Delay (DCD): -4.208ns = ( 15.792 - 20.000 )
|
|
Source Clock Delay (SCD): -3.025ns
|
|
Clock Pessimism Removal (CPR): -0.513ns
|
|
Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Discrete Jitter (DJ): 0.122ns
|
|
Phase Error (PE): 0.000ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock sys_clk rise edge) 0.000 0.000 r
|
|
K21 0.000 0.000 r clk (IN)
|
|
net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1
|
|
K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I
|
|
K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O
|
|
net (fo=1, unplaced) 0.584 2.047 pll_clk.u_clk_pll/inst/clk_in1_clk_pll
|
|
r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1
|
|
PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1)
|
|
-6.768 -4.721 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1
|
|
net (fo=1, unplaced) 0.800 -3.921 pll_clk.u_clk_pll/inst/sys_clk_clk_pll
|
|
r pll_clk.u_clk_pll/inst/clkout2_buf/I
|
|
BUFG (Prop_bufg_I_O) 0.096 -3.825 r pll_clk.u_clk_pll/inst/clkout2_buf/O
|
|
net (fo=10994, unplaced) 0.800 -3.025 u_axi_ram/u_axi_sram_sp/sys_clk
|
|
FDCE r u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[2]/C
|
|
------------------------------------------------------------------- -------------------
|
|
FDCE (Prop_fdce_C_Q) 0.456 -2.569 f u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[2]/Q
|
|
net (fo=56, unplaced) 0.826 -1.743 u_axi_ram/u_axi_sram_sp/len[2]
|
|
f u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6/I1
|
|
LUT4 (Prop_lut4_I1_O) 0.321 -1.422 r u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6/O
|
|
net (fo=4, unplaced) 0.473 -0.949 u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6_n_0
|
|
r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_20/I1
|
|
LUT5 (Prop_lut5_I1_O) 0.124 -0.825 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_20/O
|
|
net (fo=1, unplaced) 0.449 -0.376 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_20_n_0
|
|
r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_19/I5
|
|
LUT6 (Prop_lut6_I5_O) 0.124 -0.252 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_19/O
|
|
net (fo=1, unplaced) 0.000 -0.252 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_19_n_0
|
|
r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/S[0]
|
|
CARRY4 (Prop_carry4_S[0]_CO[3])
|
|
0.532 0.280 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/CO[3]
|
|
net (fo=1, unplaced) 0.000 0.280 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10_n_0
|
|
r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CI
|
|
CARRY4 (Prop_carry4_CI_CO[3])
|
|
0.114 0.394 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CO[3]
|
|
net (fo=1, unplaced) 0.000 0.394 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9_n_0
|
|
r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/CI
|
|
CARRY4 (Prop_carry4_CI_CO[3])
|
|
0.114 0.508 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/CO[3]
|
|
net (fo=1, unplaced) 0.000 0.508 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11_n_0
|
|
r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_10/CI
|
|
CARRY4 (Prop_carry4_CI_CO[3])
|
|
0.114 0.622 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_10/CO[3]
|
|
net (fo=1, unplaced) 0.000 0.622 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_10_n_0
|
|
r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2_i_9/CI
|
|
CARRY4 (Prop_carry4_CI_O[3])
|
|
0.329 0.951 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2_i_9/O[3]
|
|
net (fo=3, unplaced) 0.826 1.777 u_axi_ram/u_axi_sram_sp/upper_wrap_boundary[29]
|
|
r u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1_i_2/I0
|
|
LUT6 (Prop_lut6_I0_O) 0.307 2.084 r u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1_i_2/O
|
|
net (fo=1, unplaced) 0.000 2.084 u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1_i_2_n_0
|
|
r u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1/S[1]
|
|
CARRY4 (Prop_carry4_S[1]_CO[2])
|
|
0.570 2.654 r u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1/CO[2]
|
|
net (fo=23, unplaced) 0.515 3.169 u_axi_ram/u_axi_sram_sp/req_addr_d10_in
|
|
r u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/I5
|
|
LUT6 (Prop_lut6_I5_O) 0.310 3.479 f u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/O
|
|
net (fo=2, unplaced) 0.460 3.939 u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7_n_0
|
|
f u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/I1
|
|
LUT6 (Prop_lut6_I1_O) 0.124 4.063 f u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/O
|
|
net (fo=80, unplaced) 0.543 4.606 u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/soc_sram_addr[0]
|
|
f u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/base_ram_data_IOBUF[31]_inst_i_3/I2
|
|
LUT3 (Prop_lut3_I2_O) 0.124 4.730 r u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/base_ram_data_IOBUF[31]_inst_i_3/O
|
|
net (fo=1, unplaced) 0.449 5.179 u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/u_axi_ram/base_ram_data1
|
|
r u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/base_ram_data_IOBUF[31]_inst_i_2/I0
|
|
LUT1 (Prop_lut1_I0_O) 0.124 5.303 f u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/base_ram_data_IOBUF[31]_inst_i_2/O
|
|
net (fo=32, unplaced) 0.800 6.102 base_ram_data_IOBUF[30]_inst/T
|
|
M24 f base_ram_data_IOBUF[30]_inst/OBUFT/T
|
|
M24 OBUFT (TriStatE_obuft_T_O)
|
|
3.559 9.662 r base_ram_data_IOBUF[30]_inst/OBUFT/O
|
|
net (fo=1, unset) 0.000 9.662 base_ram_data[30]
|
|
M24 r base_ram_data[30] (INOUT)
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock sys_clk rise edge) 20.000 20.000 r
|
|
K21 0.000 20.000 r clk (IN)
|
|
net (fo=0) 0.000 20.000 pll_clk.u_clk_pll/inst/clk_in1
|
|
K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I
|
|
K21 IBUF (Prop_ibuf_I_O) 1.393 21.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O
|
|
net (fo=1, unplaced) 0.439 21.832 pll_clk.u_clk_pll/inst/clk_in1_clk_pll
|
|
r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1
|
|
PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1)
|
|
-6.040 15.792 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1
|
|
clock pessimism -0.513 15.279
|
|
clock uncertainty -0.071 15.209
|
|
output delay -0.300 14.909
|
|
-------------------------------------------------------------------
|
|
required time 14.909
|
|
arrival time -9.662
|
|
-------------------------------------------------------------------
|
|
slack 5.247
|
|
|
|
Slack (MET) : 5.250ns (required time - arrival time)
|
|
Source: u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[2]/C
|
|
(rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Destination: ext_ram_data[29]
|
|
(output port clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Path Group: sys_clk
|
|
Path Type: Max at Slow Process Corner
|
|
Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns)
|
|
Data Path Delay: 12.684ns (logic 7.344ns (57.895%) route 5.341ns (42.105%))
|
|
Logic Levels: 15 (CARRY4=6 LUT1=1 LUT3=1 LUT4=1 LUT5=1 LUT6=4 OBUFT=1)
|
|
Output Delay: 0.300ns
|
|
Clock Path Skew: -1.695ns (DCD - SCD + CPR)
|
|
Destination Clock Delay (DCD): -4.208ns = ( 15.792 - 20.000 )
|
|
Source Clock Delay (SCD): -3.025ns
|
|
Clock Pessimism Removal (CPR): -0.513ns
|
|
Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Discrete Jitter (DJ): 0.122ns
|
|
Phase Error (PE): 0.000ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock sys_clk rise edge) 0.000 0.000 r
|
|
K21 0.000 0.000 r clk (IN)
|
|
net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1
|
|
K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I
|
|
K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O
|
|
net (fo=1, unplaced) 0.584 2.047 pll_clk.u_clk_pll/inst/clk_in1_clk_pll
|
|
r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1
|
|
PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1)
|
|
-6.768 -4.721 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1
|
|
net (fo=1, unplaced) 0.800 -3.921 pll_clk.u_clk_pll/inst/sys_clk_clk_pll
|
|
r pll_clk.u_clk_pll/inst/clkout2_buf/I
|
|
BUFG (Prop_bufg_I_O) 0.096 -3.825 r pll_clk.u_clk_pll/inst/clkout2_buf/O
|
|
net (fo=10994, unplaced) 0.800 -3.025 u_axi_ram/u_axi_sram_sp/sys_clk
|
|
FDCE r u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[2]/C
|
|
------------------------------------------------------------------- -------------------
|
|
FDCE (Prop_fdce_C_Q) 0.456 -2.569 f u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[2]/Q
|
|
net (fo=56, unplaced) 0.826 -1.743 u_axi_ram/u_axi_sram_sp/len[2]
|
|
f u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6/I1
|
|
LUT4 (Prop_lut4_I1_O) 0.321 -1.422 r u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6/O
|
|
net (fo=4, unplaced) 0.473 -0.949 u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6_n_0
|
|
r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_20/I1
|
|
LUT5 (Prop_lut5_I1_O) 0.124 -0.825 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_20/O
|
|
net (fo=1, unplaced) 0.449 -0.376 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_20_n_0
|
|
r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_19/I5
|
|
LUT6 (Prop_lut6_I5_O) 0.124 -0.252 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_19/O
|
|
net (fo=1, unplaced) 0.000 -0.252 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_19_n_0
|
|
r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/S[0]
|
|
CARRY4 (Prop_carry4_S[0]_CO[3])
|
|
0.532 0.280 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/CO[3]
|
|
net (fo=1, unplaced) 0.000 0.280 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10_n_0
|
|
r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CI
|
|
CARRY4 (Prop_carry4_CI_CO[3])
|
|
0.114 0.394 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CO[3]
|
|
net (fo=1, unplaced) 0.000 0.394 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9_n_0
|
|
r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/CI
|
|
CARRY4 (Prop_carry4_CI_CO[3])
|
|
0.114 0.508 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/CO[3]
|
|
net (fo=1, unplaced) 0.000 0.508 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11_n_0
|
|
r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_10/CI
|
|
CARRY4 (Prop_carry4_CI_CO[3])
|
|
0.114 0.622 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_10/CO[3]
|
|
net (fo=1, unplaced) 0.000 0.622 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_10_n_0
|
|
r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2_i_9/CI
|
|
CARRY4 (Prop_carry4_CI_O[3])
|
|
0.329 0.951 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2_i_9/O[3]
|
|
net (fo=3, unplaced) 0.826 1.777 u_axi_ram/u_axi_sram_sp/upper_wrap_boundary[29]
|
|
r u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1_i_2/I0
|
|
LUT6 (Prop_lut6_I0_O) 0.307 2.084 r u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1_i_2/O
|
|
net (fo=1, unplaced) 0.000 2.084 u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1_i_2_n_0
|
|
r u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1/S[1]
|
|
CARRY4 (Prop_carry4_S[1]_CO[2])
|
|
0.570 2.654 r u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1/CO[2]
|
|
net (fo=23, unplaced) 0.515 3.169 u_axi_ram/u_axi_sram_sp/req_addr_d10_in
|
|
r u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/I5
|
|
LUT6 (Prop_lut6_I5_O) 0.310 3.479 r u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/O
|
|
net (fo=2, unplaced) 0.460 3.939 u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7_n_0
|
|
r u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/I1
|
|
LUT6 (Prop_lut6_I1_O) 0.124 4.063 r u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/O
|
|
net (fo=80, unplaced) 0.543 4.606 u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/soc_sram_addr[0]
|
|
r u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/ext_ram_data_IOBUF[31]_inst_i_2/I2
|
|
LUT3 (Prop_lut3_I2_O) 0.118 4.724 r u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/ext_ram_data_IOBUF[31]_inst_i_2/O
|
|
net (fo=1, unplaced) 0.449 5.173 u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/u_axi_ram/ext_ram_data1
|
|
r u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/ext_ram_data_IOBUF[31]_inst_i_1/I0
|
|
LUT1 (Prop_lut1_I0_O) 0.124 5.297 f u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/ext_ram_data_IOBUF[31]_inst_i_1/O
|
|
net (fo=32, unplaced) 0.800 6.096 ext_ram_data_IOBUF[29]_inst/T
|
|
AC21 f ext_ram_data_IOBUF[29]_inst/OBUFT/T
|
|
AC21 OBUFT (TriStatE_obuft_T_O)
|
|
3.563 9.659 r ext_ram_data_IOBUF[29]_inst/OBUFT/O
|
|
net (fo=1, unset) 0.000 9.659 ext_ram_data[29]
|
|
AC21 r ext_ram_data[29] (INOUT)
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock sys_clk rise edge) 20.000 20.000 r
|
|
K21 0.000 20.000 r clk (IN)
|
|
net (fo=0) 0.000 20.000 pll_clk.u_clk_pll/inst/clk_in1
|
|
K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I
|
|
K21 IBUF (Prop_ibuf_I_O) 1.393 21.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O
|
|
net (fo=1, unplaced) 0.439 21.832 pll_clk.u_clk_pll/inst/clk_in1_clk_pll
|
|
r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1
|
|
PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1)
|
|
-6.040 15.792 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1
|
|
clock pessimism -0.513 15.279
|
|
clock uncertainty -0.071 15.209
|
|
output delay -0.300 14.909
|
|
-------------------------------------------------------------------
|
|
required time 14.909
|
|
arrival time -9.659
|
|
-------------------------------------------------------------------
|
|
slack 5.250
|
|
|
|
Slack (MET) : 5.252ns (required time - arrival time)
|
|
Source: u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[2]/C
|
|
(rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Destination: ext_ram_data[27]
|
|
(output port clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Path Group: sys_clk
|
|
Path Type: Max at Slow Process Corner
|
|
Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns)
|
|
Data Path Delay: 12.682ns (logic 7.342ns (57.888%) route 5.341ns (42.112%))
|
|
Logic Levels: 15 (CARRY4=6 LUT1=1 LUT3=1 LUT4=1 LUT5=1 LUT6=4 OBUFT=1)
|
|
Output Delay: 0.300ns
|
|
Clock Path Skew: -1.695ns (DCD - SCD + CPR)
|
|
Destination Clock Delay (DCD): -4.208ns = ( 15.792 - 20.000 )
|
|
Source Clock Delay (SCD): -3.025ns
|
|
Clock Pessimism Removal (CPR): -0.513ns
|
|
Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Discrete Jitter (DJ): 0.122ns
|
|
Phase Error (PE): 0.000ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock sys_clk rise edge) 0.000 0.000 r
|
|
K21 0.000 0.000 r clk (IN)
|
|
net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1
|
|
K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I
|
|
K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O
|
|
net (fo=1, unplaced) 0.584 2.047 pll_clk.u_clk_pll/inst/clk_in1_clk_pll
|
|
r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1
|
|
PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1)
|
|
-6.768 -4.721 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1
|
|
net (fo=1, unplaced) 0.800 -3.921 pll_clk.u_clk_pll/inst/sys_clk_clk_pll
|
|
r pll_clk.u_clk_pll/inst/clkout2_buf/I
|
|
BUFG (Prop_bufg_I_O) 0.096 -3.825 r pll_clk.u_clk_pll/inst/clkout2_buf/O
|
|
net (fo=10994, unplaced) 0.800 -3.025 u_axi_ram/u_axi_sram_sp/sys_clk
|
|
FDCE r u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[2]/C
|
|
------------------------------------------------------------------- -------------------
|
|
FDCE (Prop_fdce_C_Q) 0.456 -2.569 f u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[2]/Q
|
|
net (fo=56, unplaced) 0.826 -1.743 u_axi_ram/u_axi_sram_sp/len[2]
|
|
f u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6/I1
|
|
LUT4 (Prop_lut4_I1_O) 0.321 -1.422 r u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6/O
|
|
net (fo=4, unplaced) 0.473 -0.949 u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6_n_0
|
|
r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_20/I1
|
|
LUT5 (Prop_lut5_I1_O) 0.124 -0.825 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_20/O
|
|
net (fo=1, unplaced) 0.449 -0.376 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_20_n_0
|
|
r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_19/I5
|
|
LUT6 (Prop_lut6_I5_O) 0.124 -0.252 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_19/O
|
|
net (fo=1, unplaced) 0.000 -0.252 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_19_n_0
|
|
r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/S[0]
|
|
CARRY4 (Prop_carry4_S[0]_CO[3])
|
|
0.532 0.280 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/CO[3]
|
|
net (fo=1, unplaced) 0.000 0.280 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10_n_0
|
|
r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CI
|
|
CARRY4 (Prop_carry4_CI_CO[3])
|
|
0.114 0.394 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CO[3]
|
|
net (fo=1, unplaced) 0.000 0.394 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9_n_0
|
|
r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/CI
|
|
CARRY4 (Prop_carry4_CI_CO[3])
|
|
0.114 0.508 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/CO[3]
|
|
net (fo=1, unplaced) 0.000 0.508 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11_n_0
|
|
r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_10/CI
|
|
CARRY4 (Prop_carry4_CI_CO[3])
|
|
0.114 0.622 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_10/CO[3]
|
|
net (fo=1, unplaced) 0.000 0.622 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_10_n_0
|
|
r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2_i_9/CI
|
|
CARRY4 (Prop_carry4_CI_O[3])
|
|
0.329 0.951 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2_i_9/O[3]
|
|
net (fo=3, unplaced) 0.826 1.777 u_axi_ram/u_axi_sram_sp/upper_wrap_boundary[29]
|
|
r u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1_i_2/I0
|
|
LUT6 (Prop_lut6_I0_O) 0.307 2.084 r u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1_i_2/O
|
|
net (fo=1, unplaced) 0.000 2.084 u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1_i_2_n_0
|
|
r u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1/S[1]
|
|
CARRY4 (Prop_carry4_S[1]_CO[2])
|
|
0.570 2.654 r u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1/CO[2]
|
|
net (fo=23, unplaced) 0.515 3.169 u_axi_ram/u_axi_sram_sp/req_addr_d10_in
|
|
r u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/I5
|
|
LUT6 (Prop_lut6_I5_O) 0.310 3.479 r u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/O
|
|
net (fo=2, unplaced) 0.460 3.939 u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7_n_0
|
|
r u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/I1
|
|
LUT6 (Prop_lut6_I1_O) 0.124 4.063 r u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/O
|
|
net (fo=80, unplaced) 0.543 4.606 u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/soc_sram_addr[0]
|
|
r u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/ext_ram_data_IOBUF[31]_inst_i_2/I2
|
|
LUT3 (Prop_lut3_I2_O) 0.118 4.724 r u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/ext_ram_data_IOBUF[31]_inst_i_2/O
|
|
net (fo=1, unplaced) 0.449 5.173 u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/u_axi_ram/ext_ram_data1
|
|
r u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/ext_ram_data_IOBUF[31]_inst_i_1/I0
|
|
LUT1 (Prop_lut1_I0_O) 0.124 5.297 f u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/ext_ram_data_IOBUF[31]_inst_i_1/O
|
|
net (fo=32, unplaced) 0.800 6.096 ext_ram_data_IOBUF[27]_inst/T
|
|
AB21 f ext_ram_data_IOBUF[27]_inst/OBUFT/T
|
|
AB21 OBUFT (TriStatE_obuft_T_O)
|
|
3.561 9.657 r ext_ram_data_IOBUF[27]_inst/OBUFT/O
|
|
net (fo=1, unset) 0.000 9.657 ext_ram_data[27]
|
|
AB21 r ext_ram_data[27] (INOUT)
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock sys_clk rise edge) 20.000 20.000 r
|
|
K21 0.000 20.000 r clk (IN)
|
|
net (fo=0) 0.000 20.000 pll_clk.u_clk_pll/inst/clk_in1
|
|
K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I
|
|
K21 IBUF (Prop_ibuf_I_O) 1.393 21.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O
|
|
net (fo=1, unplaced) 0.439 21.832 pll_clk.u_clk_pll/inst/clk_in1_clk_pll
|
|
r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1
|
|
PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1)
|
|
-6.040 15.792 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1
|
|
clock pessimism -0.513 15.279
|
|
clock uncertainty -0.071 15.209
|
|
output delay -0.300 14.909
|
|
-------------------------------------------------------------------
|
|
required time 14.909
|
|
arrival time -9.657
|
|
-------------------------------------------------------------------
|
|
slack 5.252
|
|
|
|
Slack (MET) : 5.252ns (required time - arrival time)
|
|
Source: u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[2]/C
|
|
(rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Destination: base_ram_data[5]
|
|
(output port clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Path Group: sys_clk
|
|
Path Type: Max at Slow Process Corner
|
|
Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns)
|
|
Data Path Delay: 12.682ns (logic 7.341ns (57.886%) route 5.341ns (42.114%))
|
|
Logic Levels: 15 (CARRY4=6 LUT1=1 LUT3=1 LUT4=1 LUT5=1 LUT6=4 OBUFT=1)
|
|
Output Delay: 0.300ns
|
|
Clock Path Skew: -1.695ns (DCD - SCD + CPR)
|
|
Destination Clock Delay (DCD): -4.208ns = ( 15.792 - 20.000 )
|
|
Source Clock Delay (SCD): -3.025ns
|
|
Clock Pessimism Removal (CPR): -0.513ns
|
|
Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Discrete Jitter (DJ): 0.122ns
|
|
Phase Error (PE): 0.000ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock sys_clk rise edge) 0.000 0.000 r
|
|
K21 0.000 0.000 r clk (IN)
|
|
net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1
|
|
K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I
|
|
K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O
|
|
net (fo=1, unplaced) 0.584 2.047 pll_clk.u_clk_pll/inst/clk_in1_clk_pll
|
|
r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1
|
|
PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1)
|
|
-6.768 -4.721 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1
|
|
net (fo=1, unplaced) 0.800 -3.921 pll_clk.u_clk_pll/inst/sys_clk_clk_pll
|
|
r pll_clk.u_clk_pll/inst/clkout2_buf/I
|
|
BUFG (Prop_bufg_I_O) 0.096 -3.825 r pll_clk.u_clk_pll/inst/clkout2_buf/O
|
|
net (fo=10994, unplaced) 0.800 -3.025 u_axi_ram/u_axi_sram_sp/sys_clk
|
|
FDCE r u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[2]/C
|
|
------------------------------------------------------------------- -------------------
|
|
FDCE (Prop_fdce_C_Q) 0.456 -2.569 f u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[2]/Q
|
|
net (fo=56, unplaced) 0.826 -1.743 u_axi_ram/u_axi_sram_sp/len[2]
|
|
f u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6/I1
|
|
LUT4 (Prop_lut4_I1_O) 0.321 -1.422 r u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6/O
|
|
net (fo=4, unplaced) 0.473 -0.949 u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6_n_0
|
|
r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_20/I1
|
|
LUT5 (Prop_lut5_I1_O) 0.124 -0.825 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_20/O
|
|
net (fo=1, unplaced) 0.449 -0.376 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_20_n_0
|
|
r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_19/I5
|
|
LUT6 (Prop_lut6_I5_O) 0.124 -0.252 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_19/O
|
|
net (fo=1, unplaced) 0.000 -0.252 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_19_n_0
|
|
r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/S[0]
|
|
CARRY4 (Prop_carry4_S[0]_CO[3])
|
|
0.532 0.280 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/CO[3]
|
|
net (fo=1, unplaced) 0.000 0.280 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10_n_0
|
|
r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CI
|
|
CARRY4 (Prop_carry4_CI_CO[3])
|
|
0.114 0.394 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CO[3]
|
|
net (fo=1, unplaced) 0.000 0.394 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9_n_0
|
|
r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/CI
|
|
CARRY4 (Prop_carry4_CI_CO[3])
|
|
0.114 0.508 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/CO[3]
|
|
net (fo=1, unplaced) 0.000 0.508 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11_n_0
|
|
r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_10/CI
|
|
CARRY4 (Prop_carry4_CI_CO[3])
|
|
0.114 0.622 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_10/CO[3]
|
|
net (fo=1, unplaced) 0.000 0.622 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_10_n_0
|
|
r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2_i_9/CI
|
|
CARRY4 (Prop_carry4_CI_O[3])
|
|
0.329 0.951 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2_i_9/O[3]
|
|
net (fo=3, unplaced) 0.826 1.777 u_axi_ram/u_axi_sram_sp/upper_wrap_boundary[29]
|
|
r u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1_i_2/I0
|
|
LUT6 (Prop_lut6_I0_O) 0.307 2.084 r u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1_i_2/O
|
|
net (fo=1, unplaced) 0.000 2.084 u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1_i_2_n_0
|
|
r u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1/S[1]
|
|
CARRY4 (Prop_carry4_S[1]_CO[2])
|
|
0.570 2.654 r u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1/CO[2]
|
|
net (fo=23, unplaced) 0.515 3.169 u_axi_ram/u_axi_sram_sp/req_addr_d10_in
|
|
r u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/I5
|
|
LUT6 (Prop_lut6_I5_O) 0.310 3.479 f u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/O
|
|
net (fo=2, unplaced) 0.460 3.939 u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7_n_0
|
|
f u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/I1
|
|
LUT6 (Prop_lut6_I1_O) 0.124 4.063 f u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/O
|
|
net (fo=80, unplaced) 0.543 4.606 u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/soc_sram_addr[0]
|
|
f u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/base_ram_data_IOBUF[31]_inst_i_3/I2
|
|
LUT3 (Prop_lut3_I2_O) 0.124 4.730 r u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/base_ram_data_IOBUF[31]_inst_i_3/O
|
|
net (fo=1, unplaced) 0.449 5.179 u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/u_axi_ram/base_ram_data1
|
|
r u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/base_ram_data_IOBUF[31]_inst_i_2/I0
|
|
LUT1 (Prop_lut1_I0_O) 0.124 5.303 f u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/base_ram_data_IOBUF[31]_inst_i_2/O
|
|
net (fo=32, unplaced) 0.800 6.102 base_ram_data_IOBUF[5]_inst/T
|
|
P24 f base_ram_data_IOBUF[5]_inst/OBUFT/T
|
|
P24 OBUFT (TriStatE_obuft_T_O)
|
|
3.554 9.656 r base_ram_data_IOBUF[5]_inst/OBUFT/O
|
|
net (fo=1, unset) 0.000 9.656 base_ram_data[5]
|
|
P24 r base_ram_data[5] (INOUT)
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock sys_clk rise edge) 20.000 20.000 r
|
|
K21 0.000 20.000 r clk (IN)
|
|
net (fo=0) 0.000 20.000 pll_clk.u_clk_pll/inst/clk_in1
|
|
K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I
|
|
K21 IBUF (Prop_ibuf_I_O) 1.393 21.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O
|
|
net (fo=1, unplaced) 0.439 21.832 pll_clk.u_clk_pll/inst/clk_in1_clk_pll
|
|
r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1
|
|
PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1)
|
|
-6.040 15.792 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1
|
|
clock pessimism -0.513 15.279
|
|
clock uncertainty -0.071 15.209
|
|
output delay -0.300 14.909
|
|
-------------------------------------------------------------------
|
|
required time 14.909
|
|
arrival time -9.656
|
|
-------------------------------------------------------------------
|
|
slack 5.252
|
|
|
|
Slack (MET) : 5.253ns (required time - arrival time)
|
|
Source: u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[2]/C
|
|
(rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Destination: ext_ram_data[20]
|
|
(output port clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Path Group: sys_clk
|
|
Path Type: Max at Slow Process Corner
|
|
Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns)
|
|
Data Path Delay: 12.681ns (logic 7.341ns (57.885%) route 5.341ns (42.115%))
|
|
Logic Levels: 15 (CARRY4=6 LUT1=1 LUT3=1 LUT4=1 LUT5=1 LUT6=4 OBUFT=1)
|
|
Output Delay: 0.300ns
|
|
Clock Path Skew: -1.695ns (DCD - SCD + CPR)
|
|
Destination Clock Delay (DCD): -4.208ns = ( 15.792 - 20.000 )
|
|
Source Clock Delay (SCD): -3.025ns
|
|
Clock Pessimism Removal (CPR): -0.513ns
|
|
Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Discrete Jitter (DJ): 0.122ns
|
|
Phase Error (PE): 0.000ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock sys_clk rise edge) 0.000 0.000 r
|
|
K21 0.000 0.000 r clk (IN)
|
|
net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1
|
|
K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I
|
|
K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O
|
|
net (fo=1, unplaced) 0.584 2.047 pll_clk.u_clk_pll/inst/clk_in1_clk_pll
|
|
r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1
|
|
PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1)
|
|
-6.768 -4.721 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1
|
|
net (fo=1, unplaced) 0.800 -3.921 pll_clk.u_clk_pll/inst/sys_clk_clk_pll
|
|
r pll_clk.u_clk_pll/inst/clkout2_buf/I
|
|
BUFG (Prop_bufg_I_O) 0.096 -3.825 r pll_clk.u_clk_pll/inst/clkout2_buf/O
|
|
net (fo=10994, unplaced) 0.800 -3.025 u_axi_ram/u_axi_sram_sp/sys_clk
|
|
FDCE r u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[2]/C
|
|
------------------------------------------------------------------- -------------------
|
|
FDCE (Prop_fdce_C_Q) 0.456 -2.569 f u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[2]/Q
|
|
net (fo=56, unplaced) 0.826 -1.743 u_axi_ram/u_axi_sram_sp/len[2]
|
|
f u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6/I1
|
|
LUT4 (Prop_lut4_I1_O) 0.321 -1.422 r u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6/O
|
|
net (fo=4, unplaced) 0.473 -0.949 u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6_n_0
|
|
r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_20/I1
|
|
LUT5 (Prop_lut5_I1_O) 0.124 -0.825 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_20/O
|
|
net (fo=1, unplaced) 0.449 -0.376 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_20_n_0
|
|
r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_19/I5
|
|
LUT6 (Prop_lut6_I5_O) 0.124 -0.252 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_19/O
|
|
net (fo=1, unplaced) 0.000 -0.252 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_19_n_0
|
|
r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/S[0]
|
|
CARRY4 (Prop_carry4_S[0]_CO[3])
|
|
0.532 0.280 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/CO[3]
|
|
net (fo=1, unplaced) 0.000 0.280 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10_n_0
|
|
r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CI
|
|
CARRY4 (Prop_carry4_CI_CO[3])
|
|
0.114 0.394 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CO[3]
|
|
net (fo=1, unplaced) 0.000 0.394 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9_n_0
|
|
r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/CI
|
|
CARRY4 (Prop_carry4_CI_CO[3])
|
|
0.114 0.508 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/CO[3]
|
|
net (fo=1, unplaced) 0.000 0.508 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11_n_0
|
|
r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_10/CI
|
|
CARRY4 (Prop_carry4_CI_CO[3])
|
|
0.114 0.622 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_10/CO[3]
|
|
net (fo=1, unplaced) 0.000 0.622 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_10_n_0
|
|
r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2_i_9/CI
|
|
CARRY4 (Prop_carry4_CI_O[3])
|
|
0.329 0.951 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2_i_9/O[3]
|
|
net (fo=3, unplaced) 0.826 1.777 u_axi_ram/u_axi_sram_sp/upper_wrap_boundary[29]
|
|
r u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1_i_2/I0
|
|
LUT6 (Prop_lut6_I0_O) 0.307 2.084 r u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1_i_2/O
|
|
net (fo=1, unplaced) 0.000 2.084 u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1_i_2_n_0
|
|
r u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1/S[1]
|
|
CARRY4 (Prop_carry4_S[1]_CO[2])
|
|
0.570 2.654 r u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1/CO[2]
|
|
net (fo=23, unplaced) 0.515 3.169 u_axi_ram/u_axi_sram_sp/req_addr_d10_in
|
|
r u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/I5
|
|
LUT6 (Prop_lut6_I5_O) 0.310 3.479 r u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/O
|
|
net (fo=2, unplaced) 0.460 3.939 u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7_n_0
|
|
r u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/I1
|
|
LUT6 (Prop_lut6_I1_O) 0.124 4.063 r u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/O
|
|
net (fo=80, unplaced) 0.543 4.606 u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/soc_sram_addr[0]
|
|
r u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/ext_ram_data_IOBUF[31]_inst_i_2/I2
|
|
LUT3 (Prop_lut3_I2_O) 0.118 4.724 r u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/ext_ram_data_IOBUF[31]_inst_i_2/O
|
|
net (fo=1, unplaced) 0.449 5.173 u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/u_axi_ram/ext_ram_data1
|
|
r u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/ext_ram_data_IOBUF[31]_inst_i_1/I0
|
|
LUT1 (Prop_lut1_I0_O) 0.124 5.297 f u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/ext_ram_data_IOBUF[31]_inst_i_1/O
|
|
net (fo=32, unplaced) 0.800 6.096 ext_ram_data_IOBUF[20]_inst/T
|
|
AD18 f ext_ram_data_IOBUF[20]_inst/OBUFT/T
|
|
AD18 OBUFT (TriStatE_obuft_T_O)
|
|
3.560 9.656 r ext_ram_data_IOBUF[20]_inst/OBUFT/O
|
|
net (fo=1, unset) 0.000 9.656 ext_ram_data[20]
|
|
AD18 r ext_ram_data[20] (INOUT)
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock sys_clk rise edge) 20.000 20.000 r
|
|
K21 0.000 20.000 r clk (IN)
|
|
net (fo=0) 0.000 20.000 pll_clk.u_clk_pll/inst/clk_in1
|
|
K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I
|
|
K21 IBUF (Prop_ibuf_I_O) 1.393 21.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O
|
|
net (fo=1, unplaced) 0.439 21.832 pll_clk.u_clk_pll/inst/clk_in1_clk_pll
|
|
r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1
|
|
PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1)
|
|
-6.040 15.792 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1
|
|
clock pessimism -0.513 15.279
|
|
clock uncertainty -0.071 15.209
|
|
output delay -0.300 14.909
|
|
-------------------------------------------------------------------
|
|
required time 14.909
|
|
arrival time -9.656
|
|
-------------------------------------------------------------------
|
|
slack 5.253
|
|
|
|
Slack (MET) : 5.254ns (required time - arrival time)
|
|
Source: u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[2]/C
|
|
(rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Destination: ext_ram_data[15]
|
|
(output port clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Path Group: sys_clk
|
|
Path Type: Max at Slow Process Corner
|
|
Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns)
|
|
Data Path Delay: 12.680ns (logic 7.339ns (57.881%) route 5.341ns (42.119%))
|
|
Logic Levels: 15 (CARRY4=6 LUT1=1 LUT3=1 LUT4=1 LUT5=1 LUT6=4 OBUFT=1)
|
|
Output Delay: 0.300ns
|
|
Clock Path Skew: -1.695ns (DCD - SCD + CPR)
|
|
Destination Clock Delay (DCD): -4.208ns = ( 15.792 - 20.000 )
|
|
Source Clock Delay (SCD): -3.025ns
|
|
Clock Pessimism Removal (CPR): -0.513ns
|
|
Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Discrete Jitter (DJ): 0.122ns
|
|
Phase Error (PE): 0.000ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock sys_clk rise edge) 0.000 0.000 r
|
|
K21 0.000 0.000 r clk (IN)
|
|
net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1
|
|
K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I
|
|
K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O
|
|
net (fo=1, unplaced) 0.584 2.047 pll_clk.u_clk_pll/inst/clk_in1_clk_pll
|
|
r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1
|
|
PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1)
|
|
-6.768 -4.721 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1
|
|
net (fo=1, unplaced) 0.800 -3.921 pll_clk.u_clk_pll/inst/sys_clk_clk_pll
|
|
r pll_clk.u_clk_pll/inst/clkout2_buf/I
|
|
BUFG (Prop_bufg_I_O) 0.096 -3.825 r pll_clk.u_clk_pll/inst/clkout2_buf/O
|
|
net (fo=10994, unplaced) 0.800 -3.025 u_axi_ram/u_axi_sram_sp/sys_clk
|
|
FDCE r u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[2]/C
|
|
------------------------------------------------------------------- -------------------
|
|
FDCE (Prop_fdce_C_Q) 0.456 -2.569 f u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[2]/Q
|
|
net (fo=56, unplaced) 0.826 -1.743 u_axi_ram/u_axi_sram_sp/len[2]
|
|
f u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6/I1
|
|
LUT4 (Prop_lut4_I1_O) 0.321 -1.422 r u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6/O
|
|
net (fo=4, unplaced) 0.473 -0.949 u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6_n_0
|
|
r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_20/I1
|
|
LUT5 (Prop_lut5_I1_O) 0.124 -0.825 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_20/O
|
|
net (fo=1, unplaced) 0.449 -0.376 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_20_n_0
|
|
r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_19/I5
|
|
LUT6 (Prop_lut6_I5_O) 0.124 -0.252 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_19/O
|
|
net (fo=1, unplaced) 0.000 -0.252 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_19_n_0
|
|
r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/S[0]
|
|
CARRY4 (Prop_carry4_S[0]_CO[3])
|
|
0.532 0.280 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/CO[3]
|
|
net (fo=1, unplaced) 0.000 0.280 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10_n_0
|
|
r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CI
|
|
CARRY4 (Prop_carry4_CI_CO[3])
|
|
0.114 0.394 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CO[3]
|
|
net (fo=1, unplaced) 0.000 0.394 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9_n_0
|
|
r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/CI
|
|
CARRY4 (Prop_carry4_CI_CO[3])
|
|
0.114 0.508 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/CO[3]
|
|
net (fo=1, unplaced) 0.000 0.508 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11_n_0
|
|
r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_10/CI
|
|
CARRY4 (Prop_carry4_CI_CO[3])
|
|
0.114 0.622 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_10/CO[3]
|
|
net (fo=1, unplaced) 0.000 0.622 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_10_n_0
|
|
r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2_i_9/CI
|
|
CARRY4 (Prop_carry4_CI_O[3])
|
|
0.329 0.951 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2_i_9/O[3]
|
|
net (fo=3, unplaced) 0.826 1.777 u_axi_ram/u_axi_sram_sp/upper_wrap_boundary[29]
|
|
r u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1_i_2/I0
|
|
LUT6 (Prop_lut6_I0_O) 0.307 2.084 r u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1_i_2/O
|
|
net (fo=1, unplaced) 0.000 2.084 u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1_i_2_n_0
|
|
r u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1/S[1]
|
|
CARRY4 (Prop_carry4_S[1]_CO[2])
|
|
0.570 2.654 r u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1/CO[2]
|
|
net (fo=23, unplaced) 0.515 3.169 u_axi_ram/u_axi_sram_sp/req_addr_d10_in
|
|
r u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/I5
|
|
LUT6 (Prop_lut6_I5_O) 0.310 3.479 r u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/O
|
|
net (fo=2, unplaced) 0.460 3.939 u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7_n_0
|
|
r u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/I1
|
|
LUT6 (Prop_lut6_I1_O) 0.124 4.063 r u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/O
|
|
net (fo=80, unplaced) 0.543 4.606 u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/soc_sram_addr[0]
|
|
r u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/ext_ram_data_IOBUF[31]_inst_i_2/I2
|
|
LUT3 (Prop_lut3_I2_O) 0.118 4.724 r u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/ext_ram_data_IOBUF[31]_inst_i_2/O
|
|
net (fo=1, unplaced) 0.449 5.173 u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/u_axi_ram/ext_ram_data1
|
|
r u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/ext_ram_data_IOBUF[31]_inst_i_1/I0
|
|
LUT1 (Prop_lut1_I0_O) 0.124 5.297 f u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/ext_ram_data_IOBUF[31]_inst_i_1/O
|
|
net (fo=32, unplaced) 0.800 6.096 ext_ram_data_IOBUF[15]_inst/T
|
|
U24 f ext_ram_data_IOBUF[15]_inst/OBUFT/T
|
|
U24 OBUFT (TriStatE_obuft_T_O)
|
|
3.558 9.655 r ext_ram_data_IOBUF[15]_inst/OBUFT/O
|
|
net (fo=1, unset) 0.000 9.655 ext_ram_data[15]
|
|
U24 r ext_ram_data[15] (INOUT)
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock sys_clk rise edge) 20.000 20.000 r
|
|
K21 0.000 20.000 r clk (IN)
|
|
net (fo=0) 0.000 20.000 pll_clk.u_clk_pll/inst/clk_in1
|
|
K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I
|
|
K21 IBUF (Prop_ibuf_I_O) 1.393 21.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O
|
|
net (fo=1, unplaced) 0.439 21.832 pll_clk.u_clk_pll/inst/clk_in1_clk_pll
|
|
r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1
|
|
PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1)
|
|
-6.040 15.792 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1
|
|
clock pessimism -0.513 15.279
|
|
clock uncertainty -0.071 15.209
|
|
output delay -0.300 14.909
|
|
-------------------------------------------------------------------
|
|
required time 14.909
|
|
arrival time -9.655
|
|
-------------------------------------------------------------------
|
|
slack 5.254
|
|
|
|
Slack (MET) : 5.254ns (required time - arrival time)
|
|
Source: u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[2]/C
|
|
(rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Destination: base_ram_data[22]
|
|
(output port clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Path Group: sys_clk
|
|
Path Type: Max at Slow Process Corner
|
|
Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns)
|
|
Data Path Delay: 12.680ns (logic 7.339ns (57.880%) route 5.341ns (42.120%))
|
|
Logic Levels: 15 (CARRY4=6 LUT1=1 LUT3=1 LUT4=1 LUT5=1 LUT6=4 OBUFT=1)
|
|
Output Delay: 0.300ns
|
|
Clock Path Skew: -1.695ns (DCD - SCD + CPR)
|
|
Destination Clock Delay (DCD): -4.208ns = ( 15.792 - 20.000 )
|
|
Source Clock Delay (SCD): -3.025ns
|
|
Clock Pessimism Removal (CPR): -0.513ns
|
|
Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Discrete Jitter (DJ): 0.122ns
|
|
Phase Error (PE): 0.000ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock sys_clk rise edge) 0.000 0.000 r
|
|
K21 0.000 0.000 r clk (IN)
|
|
net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1
|
|
K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I
|
|
K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O
|
|
net (fo=1, unplaced) 0.584 2.047 pll_clk.u_clk_pll/inst/clk_in1_clk_pll
|
|
r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1
|
|
PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1)
|
|
-6.768 -4.721 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1
|
|
net (fo=1, unplaced) 0.800 -3.921 pll_clk.u_clk_pll/inst/sys_clk_clk_pll
|
|
r pll_clk.u_clk_pll/inst/clkout2_buf/I
|
|
BUFG (Prop_bufg_I_O) 0.096 -3.825 r pll_clk.u_clk_pll/inst/clkout2_buf/O
|
|
net (fo=10994, unplaced) 0.800 -3.025 u_axi_ram/u_axi_sram_sp/sys_clk
|
|
FDCE r u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[2]/C
|
|
------------------------------------------------------------------- -------------------
|
|
FDCE (Prop_fdce_C_Q) 0.456 -2.569 f u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[2]/Q
|
|
net (fo=56, unplaced) 0.826 -1.743 u_axi_ram/u_axi_sram_sp/len[2]
|
|
f u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6/I1
|
|
LUT4 (Prop_lut4_I1_O) 0.321 -1.422 r u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6/O
|
|
net (fo=4, unplaced) 0.473 -0.949 u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6_n_0
|
|
r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_20/I1
|
|
LUT5 (Prop_lut5_I1_O) 0.124 -0.825 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_20/O
|
|
net (fo=1, unplaced) 0.449 -0.376 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_20_n_0
|
|
r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_19/I5
|
|
LUT6 (Prop_lut6_I5_O) 0.124 -0.252 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_19/O
|
|
net (fo=1, unplaced) 0.000 -0.252 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_19_n_0
|
|
r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/S[0]
|
|
CARRY4 (Prop_carry4_S[0]_CO[3])
|
|
0.532 0.280 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/CO[3]
|
|
net (fo=1, unplaced) 0.000 0.280 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10_n_0
|
|
r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CI
|
|
CARRY4 (Prop_carry4_CI_CO[3])
|
|
0.114 0.394 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CO[3]
|
|
net (fo=1, unplaced) 0.000 0.394 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9_n_0
|
|
r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/CI
|
|
CARRY4 (Prop_carry4_CI_CO[3])
|
|
0.114 0.508 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/CO[3]
|
|
net (fo=1, unplaced) 0.000 0.508 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11_n_0
|
|
r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_10/CI
|
|
CARRY4 (Prop_carry4_CI_CO[3])
|
|
0.114 0.622 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_10/CO[3]
|
|
net (fo=1, unplaced) 0.000 0.622 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_10_n_0
|
|
r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2_i_9/CI
|
|
CARRY4 (Prop_carry4_CI_O[3])
|
|
0.329 0.951 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2_i_9/O[3]
|
|
net (fo=3, unplaced) 0.826 1.777 u_axi_ram/u_axi_sram_sp/upper_wrap_boundary[29]
|
|
r u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1_i_2/I0
|
|
LUT6 (Prop_lut6_I0_O) 0.307 2.084 r u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1_i_2/O
|
|
net (fo=1, unplaced) 0.000 2.084 u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1_i_2_n_0
|
|
r u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1/S[1]
|
|
CARRY4 (Prop_carry4_S[1]_CO[2])
|
|
0.570 2.654 r u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1/CO[2]
|
|
net (fo=23, unplaced) 0.515 3.169 u_axi_ram/u_axi_sram_sp/req_addr_d10_in
|
|
r u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/I5
|
|
LUT6 (Prop_lut6_I5_O) 0.310 3.479 f u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/O
|
|
net (fo=2, unplaced) 0.460 3.939 u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7_n_0
|
|
f u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/I1
|
|
LUT6 (Prop_lut6_I1_O) 0.124 4.063 f u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/O
|
|
net (fo=80, unplaced) 0.543 4.606 u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/soc_sram_addr[0]
|
|
f u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/base_ram_data_IOBUF[31]_inst_i_3/I2
|
|
LUT3 (Prop_lut3_I2_O) 0.124 4.730 r u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/base_ram_data_IOBUF[31]_inst_i_3/O
|
|
net (fo=1, unplaced) 0.449 5.179 u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/u_axi_ram/base_ram_data1
|
|
r u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/base_ram_data_IOBUF[31]_inst_i_2/I0
|
|
LUT1 (Prop_lut1_I0_O) 0.124 5.303 f u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/base_ram_data_IOBUF[31]_inst_i_2/O
|
|
net (fo=32, unplaced) 0.800 6.102 base_ram_data_IOBUF[22]_inst/T
|
|
N24 f base_ram_data_IOBUF[22]_inst/OBUFT/T
|
|
N24 OBUFT (TriStatE_obuft_T_O)
|
|
3.552 9.655 r base_ram_data_IOBUF[22]_inst/OBUFT/O
|
|
net (fo=1, unset) 0.000 9.655 base_ram_data[22]
|
|
N24 r base_ram_data[22] (INOUT)
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock sys_clk rise edge) 20.000 20.000 r
|
|
K21 0.000 20.000 r clk (IN)
|
|
net (fo=0) 0.000 20.000 pll_clk.u_clk_pll/inst/clk_in1
|
|
K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I
|
|
K21 IBUF (Prop_ibuf_I_O) 1.393 21.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O
|
|
net (fo=1, unplaced) 0.439 21.832 pll_clk.u_clk_pll/inst/clk_in1_clk_pll
|
|
r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1
|
|
PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1)
|
|
-6.040 15.792 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1
|
|
clock pessimism -0.513 15.279
|
|
clock uncertainty -0.071 15.209
|
|
output delay -0.300 14.909
|
|
-------------------------------------------------------------------
|
|
required time 14.909
|
|
arrival time -9.655
|
|
-------------------------------------------------------------------
|
|
slack 5.254
|
|
|
|
Slack (MET) : 5.254ns (required time - arrival time)
|
|
Source: u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[2]/C
|
|
(rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Destination: ext_ram_data[24]
|
|
(output port clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Path Group: sys_clk
|
|
Path Type: Max at Slow Process Corner
|
|
Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns)
|
|
Data Path Delay: 12.680ns (logic 7.339ns (57.880%) route 5.341ns (42.120%))
|
|
Logic Levels: 15 (CARRY4=6 LUT1=1 LUT3=1 LUT4=1 LUT5=1 LUT6=4 OBUFT=1)
|
|
Output Delay: 0.300ns
|
|
Clock Path Skew: -1.695ns (DCD - SCD + CPR)
|
|
Destination Clock Delay (DCD): -4.208ns = ( 15.792 - 20.000 )
|
|
Source Clock Delay (SCD): -3.025ns
|
|
Clock Pessimism Removal (CPR): -0.513ns
|
|
Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Discrete Jitter (DJ): 0.122ns
|
|
Phase Error (PE): 0.000ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock sys_clk rise edge) 0.000 0.000 r
|
|
K21 0.000 0.000 r clk (IN)
|
|
net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1
|
|
K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I
|
|
K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O
|
|
net (fo=1, unplaced) 0.584 2.047 pll_clk.u_clk_pll/inst/clk_in1_clk_pll
|
|
r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1
|
|
PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1)
|
|
-6.768 -4.721 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1
|
|
net (fo=1, unplaced) 0.800 -3.921 pll_clk.u_clk_pll/inst/sys_clk_clk_pll
|
|
r pll_clk.u_clk_pll/inst/clkout2_buf/I
|
|
BUFG (Prop_bufg_I_O) 0.096 -3.825 r pll_clk.u_clk_pll/inst/clkout2_buf/O
|
|
net (fo=10994, unplaced) 0.800 -3.025 u_axi_ram/u_axi_sram_sp/sys_clk
|
|
FDCE r u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[2]/C
|
|
------------------------------------------------------------------- -------------------
|
|
FDCE (Prop_fdce_C_Q) 0.456 -2.569 f u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[2]/Q
|
|
net (fo=56, unplaced) 0.826 -1.743 u_axi_ram/u_axi_sram_sp/len[2]
|
|
f u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6/I1
|
|
LUT4 (Prop_lut4_I1_O) 0.321 -1.422 r u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6/O
|
|
net (fo=4, unplaced) 0.473 -0.949 u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6_n_0
|
|
r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_20/I1
|
|
LUT5 (Prop_lut5_I1_O) 0.124 -0.825 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_20/O
|
|
net (fo=1, unplaced) 0.449 -0.376 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_20_n_0
|
|
r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_19/I5
|
|
LUT6 (Prop_lut6_I5_O) 0.124 -0.252 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_19/O
|
|
net (fo=1, unplaced) 0.000 -0.252 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_19_n_0
|
|
r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/S[0]
|
|
CARRY4 (Prop_carry4_S[0]_CO[3])
|
|
0.532 0.280 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/CO[3]
|
|
net (fo=1, unplaced) 0.000 0.280 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10_n_0
|
|
r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CI
|
|
CARRY4 (Prop_carry4_CI_CO[3])
|
|
0.114 0.394 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CO[3]
|
|
net (fo=1, unplaced) 0.000 0.394 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9_n_0
|
|
r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/CI
|
|
CARRY4 (Prop_carry4_CI_CO[3])
|
|
0.114 0.508 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/CO[3]
|
|
net (fo=1, unplaced) 0.000 0.508 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11_n_0
|
|
r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_10/CI
|
|
CARRY4 (Prop_carry4_CI_CO[3])
|
|
0.114 0.622 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_10/CO[3]
|
|
net (fo=1, unplaced) 0.000 0.622 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_10_n_0
|
|
r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2_i_9/CI
|
|
CARRY4 (Prop_carry4_CI_O[3])
|
|
0.329 0.951 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2_i_9/O[3]
|
|
net (fo=3, unplaced) 0.826 1.777 u_axi_ram/u_axi_sram_sp/upper_wrap_boundary[29]
|
|
r u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1_i_2/I0
|
|
LUT6 (Prop_lut6_I0_O) 0.307 2.084 r u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1_i_2/O
|
|
net (fo=1, unplaced) 0.000 2.084 u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1_i_2_n_0
|
|
r u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1/S[1]
|
|
CARRY4 (Prop_carry4_S[1]_CO[2])
|
|
0.570 2.654 r u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1/CO[2]
|
|
net (fo=23, unplaced) 0.515 3.169 u_axi_ram/u_axi_sram_sp/req_addr_d10_in
|
|
r u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/I5
|
|
LUT6 (Prop_lut6_I5_O) 0.310 3.479 r u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/O
|
|
net (fo=2, unplaced) 0.460 3.939 u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7_n_0
|
|
r u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/I1
|
|
LUT6 (Prop_lut6_I1_O) 0.124 4.063 r u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/O
|
|
net (fo=80, unplaced) 0.543 4.606 u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/soc_sram_addr[0]
|
|
r u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/ext_ram_data_IOBUF[31]_inst_i_2/I2
|
|
LUT3 (Prop_lut3_I2_O) 0.118 4.724 r u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/ext_ram_data_IOBUF[31]_inst_i_2/O
|
|
net (fo=1, unplaced) 0.449 5.173 u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/u_axi_ram/ext_ram_data1
|
|
r u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/ext_ram_data_IOBUF[31]_inst_i_1/I0
|
|
LUT1 (Prop_lut1_I0_O) 0.124 5.297 f u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/ext_ram_data_IOBUF[31]_inst_i_1/O
|
|
net (fo=32, unplaced) 0.800 6.096 ext_ram_data_IOBUF[24]_inst/T
|
|
AD17 f ext_ram_data_IOBUF[24]_inst/OBUFT/T
|
|
AD17 OBUFT (TriStatE_obuft_T_O)
|
|
3.558 9.654 r ext_ram_data_IOBUF[24]_inst/OBUFT/O
|
|
net (fo=1, unset) 0.000 9.654 ext_ram_data[24]
|
|
AD17 r ext_ram_data[24] (INOUT)
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock sys_clk rise edge) 20.000 20.000 r
|
|
K21 0.000 20.000 r clk (IN)
|
|
net (fo=0) 0.000 20.000 pll_clk.u_clk_pll/inst/clk_in1
|
|
K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I
|
|
K21 IBUF (Prop_ibuf_I_O) 1.393 21.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O
|
|
net (fo=1, unplaced) 0.439 21.832 pll_clk.u_clk_pll/inst/clk_in1_clk_pll
|
|
r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1
|
|
PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1)
|
|
-6.040 15.792 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1
|
|
clock pessimism -0.513 15.279
|
|
clock uncertainty -0.071 15.209
|
|
output delay -0.300 14.909
|
|
-------------------------------------------------------------------
|
|
required time 14.909
|
|
arrival time -9.654
|
|
-------------------------------------------------------------------
|
|
slack 5.254
|
|
|
|
Slack (MET) : 5.255ns (required time - arrival time)
|
|
Source: u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[2]/C
|
|
(rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Destination: ext_ram_data[19]
|
|
(output port clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Path Group: sys_clk
|
|
Path Type: Max at Slow Process Corner
|
|
Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns)
|
|
Data Path Delay: 12.679ns (logic 7.338ns (57.877%) route 5.341ns (42.123%))
|
|
Logic Levels: 15 (CARRY4=6 LUT1=1 LUT3=1 LUT4=1 LUT5=1 LUT6=4 OBUFT=1)
|
|
Output Delay: 0.300ns
|
|
Clock Path Skew: -1.695ns (DCD - SCD + CPR)
|
|
Destination Clock Delay (DCD): -4.208ns = ( 15.792 - 20.000 )
|
|
Source Clock Delay (SCD): -3.025ns
|
|
Clock Pessimism Removal (CPR): -0.513ns
|
|
Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Discrete Jitter (DJ): 0.122ns
|
|
Phase Error (PE): 0.000ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock sys_clk rise edge) 0.000 0.000 r
|
|
K21 0.000 0.000 r clk (IN)
|
|
net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1
|
|
K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I
|
|
K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O
|
|
net (fo=1, unplaced) 0.584 2.047 pll_clk.u_clk_pll/inst/clk_in1_clk_pll
|
|
r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1
|
|
PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1)
|
|
-6.768 -4.721 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1
|
|
net (fo=1, unplaced) 0.800 -3.921 pll_clk.u_clk_pll/inst/sys_clk_clk_pll
|
|
r pll_clk.u_clk_pll/inst/clkout2_buf/I
|
|
BUFG (Prop_bufg_I_O) 0.096 -3.825 r pll_clk.u_clk_pll/inst/clkout2_buf/O
|
|
net (fo=10994, unplaced) 0.800 -3.025 u_axi_ram/u_axi_sram_sp/sys_clk
|
|
FDCE r u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[2]/C
|
|
------------------------------------------------------------------- -------------------
|
|
FDCE (Prop_fdce_C_Q) 0.456 -2.569 f u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[2]/Q
|
|
net (fo=56, unplaced) 0.826 -1.743 u_axi_ram/u_axi_sram_sp/len[2]
|
|
f u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6/I1
|
|
LUT4 (Prop_lut4_I1_O) 0.321 -1.422 r u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6/O
|
|
net (fo=4, unplaced) 0.473 -0.949 u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6_n_0
|
|
r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_20/I1
|
|
LUT5 (Prop_lut5_I1_O) 0.124 -0.825 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_20/O
|
|
net (fo=1, unplaced) 0.449 -0.376 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_20_n_0
|
|
r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_19/I5
|
|
LUT6 (Prop_lut6_I5_O) 0.124 -0.252 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_19/O
|
|
net (fo=1, unplaced) 0.000 -0.252 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_19_n_0
|
|
r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/S[0]
|
|
CARRY4 (Prop_carry4_S[0]_CO[3])
|
|
0.532 0.280 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/CO[3]
|
|
net (fo=1, unplaced) 0.000 0.280 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10_n_0
|
|
r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CI
|
|
CARRY4 (Prop_carry4_CI_CO[3])
|
|
0.114 0.394 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CO[3]
|
|
net (fo=1, unplaced) 0.000 0.394 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9_n_0
|
|
r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/CI
|
|
CARRY4 (Prop_carry4_CI_CO[3])
|
|
0.114 0.508 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/CO[3]
|
|
net (fo=1, unplaced) 0.000 0.508 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11_n_0
|
|
r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_10/CI
|
|
CARRY4 (Prop_carry4_CI_CO[3])
|
|
0.114 0.622 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_10/CO[3]
|
|
net (fo=1, unplaced) 0.000 0.622 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_10_n_0
|
|
r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2_i_9/CI
|
|
CARRY4 (Prop_carry4_CI_O[3])
|
|
0.329 0.951 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2_i_9/O[3]
|
|
net (fo=3, unplaced) 0.826 1.777 u_axi_ram/u_axi_sram_sp/upper_wrap_boundary[29]
|
|
r u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1_i_2/I0
|
|
LUT6 (Prop_lut6_I0_O) 0.307 2.084 r u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1_i_2/O
|
|
net (fo=1, unplaced) 0.000 2.084 u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1_i_2_n_0
|
|
r u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1/S[1]
|
|
CARRY4 (Prop_carry4_S[1]_CO[2])
|
|
0.570 2.654 r u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1/CO[2]
|
|
net (fo=23, unplaced) 0.515 3.169 u_axi_ram/u_axi_sram_sp/req_addr_d10_in
|
|
r u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/I5
|
|
LUT6 (Prop_lut6_I5_O) 0.310 3.479 r u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/O
|
|
net (fo=2, unplaced) 0.460 3.939 u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7_n_0
|
|
r u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/I1
|
|
LUT6 (Prop_lut6_I1_O) 0.124 4.063 r u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/O
|
|
net (fo=80, unplaced) 0.543 4.606 u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/soc_sram_addr[0]
|
|
r u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/ext_ram_data_IOBUF[31]_inst_i_2/I2
|
|
LUT3 (Prop_lut3_I2_O) 0.118 4.724 r u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/ext_ram_data_IOBUF[31]_inst_i_2/O
|
|
net (fo=1, unplaced) 0.449 5.173 u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/u_axi_ram/ext_ram_data1
|
|
r u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/ext_ram_data_IOBUF[31]_inst_i_1/I0
|
|
LUT1 (Prop_lut1_I0_O) 0.124 5.297 f u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/ext_ram_data_IOBUF[31]_inst_i_1/O
|
|
net (fo=32, unplaced) 0.800 6.096 ext_ram_data_IOBUF[19]_inst/T
|
|
AC18 f ext_ram_data_IOBUF[19]_inst/OBUFT/T
|
|
AC18 OBUFT (TriStatE_obuft_T_O)
|
|
3.557 9.654 r ext_ram_data_IOBUF[19]_inst/OBUFT/O
|
|
net (fo=1, unset) 0.000 9.654 ext_ram_data[19]
|
|
AC18 r ext_ram_data[19] (INOUT)
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock sys_clk rise edge) 20.000 20.000 r
|
|
K21 0.000 20.000 r clk (IN)
|
|
net (fo=0) 0.000 20.000 pll_clk.u_clk_pll/inst/clk_in1
|
|
K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I
|
|
K21 IBUF (Prop_ibuf_I_O) 1.393 21.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O
|
|
net (fo=1, unplaced) 0.439 21.832 pll_clk.u_clk_pll/inst/clk_in1_clk_pll
|
|
r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1
|
|
PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1)
|
|
-6.040 15.792 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1
|
|
clock pessimism -0.513 15.279
|
|
clock uncertainty -0.071 15.209
|
|
output delay -0.300 14.909
|
|
-------------------------------------------------------------------
|
|
required time 14.909
|
|
arrival time -9.654
|
|
-------------------------------------------------------------------
|
|
slack 5.255
|
|
|
|
Slack (MET) : 5.255ns (required time - arrival time)
|
|
Source: u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[2]/C
|
|
(rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Destination: base_ram_data[25]
|
|
(output port clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Path Group: sys_clk
|
|
Path Type: Max at Slow Process Corner
|
|
Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns)
|
|
Data Path Delay: 12.679ns (logic 7.338ns (57.877%) route 5.341ns (42.123%))
|
|
Logic Levels: 15 (CARRY4=6 LUT1=1 LUT3=1 LUT4=1 LUT5=1 LUT6=4 OBUFT=1)
|
|
Output Delay: 0.300ns
|
|
Clock Path Skew: -1.695ns (DCD - SCD + CPR)
|
|
Destination Clock Delay (DCD): -4.208ns = ( 15.792 - 20.000 )
|
|
Source Clock Delay (SCD): -3.025ns
|
|
Clock Pessimism Removal (CPR): -0.513ns
|
|
Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Discrete Jitter (DJ): 0.122ns
|
|
Phase Error (PE): 0.000ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock sys_clk rise edge) 0.000 0.000 r
|
|
K21 0.000 0.000 r clk (IN)
|
|
net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1
|
|
K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I
|
|
K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O
|
|
net (fo=1, unplaced) 0.584 2.047 pll_clk.u_clk_pll/inst/clk_in1_clk_pll
|
|
r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1
|
|
PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1)
|
|
-6.768 -4.721 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1
|
|
net (fo=1, unplaced) 0.800 -3.921 pll_clk.u_clk_pll/inst/sys_clk_clk_pll
|
|
r pll_clk.u_clk_pll/inst/clkout2_buf/I
|
|
BUFG (Prop_bufg_I_O) 0.096 -3.825 r pll_clk.u_clk_pll/inst/clkout2_buf/O
|
|
net (fo=10994, unplaced) 0.800 -3.025 u_axi_ram/u_axi_sram_sp/sys_clk
|
|
FDCE r u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[2]/C
|
|
------------------------------------------------------------------- -------------------
|
|
FDCE (Prop_fdce_C_Q) 0.456 -2.569 f u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[2]/Q
|
|
net (fo=56, unplaced) 0.826 -1.743 u_axi_ram/u_axi_sram_sp/len[2]
|
|
f u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6/I1
|
|
LUT4 (Prop_lut4_I1_O) 0.321 -1.422 r u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6/O
|
|
net (fo=4, unplaced) 0.473 -0.949 u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6_n_0
|
|
r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_20/I1
|
|
LUT5 (Prop_lut5_I1_O) 0.124 -0.825 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_20/O
|
|
net (fo=1, unplaced) 0.449 -0.376 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_20_n_0
|
|
r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_19/I5
|
|
LUT6 (Prop_lut6_I5_O) 0.124 -0.252 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_19/O
|
|
net (fo=1, unplaced) 0.000 -0.252 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_19_n_0
|
|
r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/S[0]
|
|
CARRY4 (Prop_carry4_S[0]_CO[3])
|
|
0.532 0.280 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/CO[3]
|
|
net (fo=1, unplaced) 0.000 0.280 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10_n_0
|
|
r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CI
|
|
CARRY4 (Prop_carry4_CI_CO[3])
|
|
0.114 0.394 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CO[3]
|
|
net (fo=1, unplaced) 0.000 0.394 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9_n_0
|
|
r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/CI
|
|
CARRY4 (Prop_carry4_CI_CO[3])
|
|
0.114 0.508 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/CO[3]
|
|
net (fo=1, unplaced) 0.000 0.508 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11_n_0
|
|
r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_10/CI
|
|
CARRY4 (Prop_carry4_CI_CO[3])
|
|
0.114 0.622 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_10/CO[3]
|
|
net (fo=1, unplaced) 0.000 0.622 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_10_n_0
|
|
r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2_i_9/CI
|
|
CARRY4 (Prop_carry4_CI_O[3])
|
|
0.329 0.951 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2_i_9/O[3]
|
|
net (fo=3, unplaced) 0.826 1.777 u_axi_ram/u_axi_sram_sp/upper_wrap_boundary[29]
|
|
r u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1_i_2/I0
|
|
LUT6 (Prop_lut6_I0_O) 0.307 2.084 r u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1_i_2/O
|
|
net (fo=1, unplaced) 0.000 2.084 u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1_i_2_n_0
|
|
r u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1/S[1]
|
|
CARRY4 (Prop_carry4_S[1]_CO[2])
|
|
0.570 2.654 r u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1/CO[2]
|
|
net (fo=23, unplaced) 0.515 3.169 u_axi_ram/u_axi_sram_sp/req_addr_d10_in
|
|
r u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/I5
|
|
LUT6 (Prop_lut6_I5_O) 0.310 3.479 f u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/O
|
|
net (fo=2, unplaced) 0.460 3.939 u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7_n_0
|
|
f u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/I1
|
|
LUT6 (Prop_lut6_I1_O) 0.124 4.063 f u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/O
|
|
net (fo=80, unplaced) 0.543 4.606 u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/soc_sram_addr[0]
|
|
f u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/base_ram_data_IOBUF[31]_inst_i_3/I2
|
|
LUT3 (Prop_lut3_I2_O) 0.124 4.730 r u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/base_ram_data_IOBUF[31]_inst_i_3/O
|
|
net (fo=1, unplaced) 0.449 5.179 u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/u_axi_ram/base_ram_data1
|
|
r u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/base_ram_data_IOBUF[31]_inst_i_2/I0
|
|
LUT1 (Prop_lut1_I0_O) 0.124 5.303 f u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/base_ram_data_IOBUF[31]_inst_i_2/O
|
|
net (fo=32, unplaced) 0.800 6.102 base_ram_data_IOBUF[25]_inst/T
|
|
R22 f base_ram_data_IOBUF[25]_inst/OBUFT/T
|
|
R22 OBUFT (TriStatE_obuft_T_O)
|
|
3.551 9.653 r base_ram_data_IOBUF[25]_inst/OBUFT/O
|
|
net (fo=1, unset) 0.000 9.653 base_ram_data[25]
|
|
R22 r base_ram_data[25] (INOUT)
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock sys_clk rise edge) 20.000 20.000 r
|
|
K21 0.000 20.000 r clk (IN)
|
|
net (fo=0) 0.000 20.000 pll_clk.u_clk_pll/inst/clk_in1
|
|
K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I
|
|
K21 IBUF (Prop_ibuf_I_O) 1.393 21.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O
|
|
net (fo=1, unplaced) 0.439 21.832 pll_clk.u_clk_pll/inst/clk_in1_clk_pll
|
|
r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1
|
|
PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1)
|
|
-6.040 15.792 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1
|
|
clock pessimism -0.513 15.279
|
|
clock uncertainty -0.071 15.209
|
|
output delay -0.300 14.909
|
|
-------------------------------------------------------------------
|
|
required time 14.909
|
|
arrival time -9.653
|
|
-------------------------------------------------------------------
|
|
slack 5.255
|
|
|
|
Slack (MET) : 5.256ns (required time - arrival time)
|
|
Source: u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[2]/C
|
|
(rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Destination: base_ram_data[24]
|
|
(output port clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Path Group: sys_clk
|
|
Path Type: Max at Slow Process Corner
|
|
Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns)
|
|
Data Path Delay: 12.678ns (logic 7.338ns (57.876%) route 5.341ns (42.124%))
|
|
Logic Levels: 15 (CARRY4=6 LUT1=1 LUT3=1 LUT4=1 LUT5=1 LUT6=4 OBUFT=1)
|
|
Output Delay: 0.300ns
|
|
Clock Path Skew: -1.695ns (DCD - SCD + CPR)
|
|
Destination Clock Delay (DCD): -4.208ns = ( 15.792 - 20.000 )
|
|
Source Clock Delay (SCD): -3.025ns
|
|
Clock Pessimism Removal (CPR): -0.513ns
|
|
Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Discrete Jitter (DJ): 0.122ns
|
|
Phase Error (PE): 0.000ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock sys_clk rise edge) 0.000 0.000 r
|
|
K21 0.000 0.000 r clk (IN)
|
|
net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1
|
|
K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I
|
|
K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O
|
|
net (fo=1, unplaced) 0.584 2.047 pll_clk.u_clk_pll/inst/clk_in1_clk_pll
|
|
r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1
|
|
PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1)
|
|
-6.768 -4.721 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1
|
|
net (fo=1, unplaced) 0.800 -3.921 pll_clk.u_clk_pll/inst/sys_clk_clk_pll
|
|
r pll_clk.u_clk_pll/inst/clkout2_buf/I
|
|
BUFG (Prop_bufg_I_O) 0.096 -3.825 r pll_clk.u_clk_pll/inst/clkout2_buf/O
|
|
net (fo=10994, unplaced) 0.800 -3.025 u_axi_ram/u_axi_sram_sp/sys_clk
|
|
FDCE r u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[2]/C
|
|
------------------------------------------------------------------- -------------------
|
|
FDCE (Prop_fdce_C_Q) 0.456 -2.569 f u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[2]/Q
|
|
net (fo=56, unplaced) 0.826 -1.743 u_axi_ram/u_axi_sram_sp/len[2]
|
|
f u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6/I1
|
|
LUT4 (Prop_lut4_I1_O) 0.321 -1.422 r u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6/O
|
|
net (fo=4, unplaced) 0.473 -0.949 u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6_n_0
|
|
r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_20/I1
|
|
LUT5 (Prop_lut5_I1_O) 0.124 -0.825 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_20/O
|
|
net (fo=1, unplaced) 0.449 -0.376 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_20_n_0
|
|
r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_19/I5
|
|
LUT6 (Prop_lut6_I5_O) 0.124 -0.252 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_19/O
|
|
net (fo=1, unplaced) 0.000 -0.252 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_19_n_0
|
|
r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/S[0]
|
|
CARRY4 (Prop_carry4_S[0]_CO[3])
|
|
0.532 0.280 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/CO[3]
|
|
net (fo=1, unplaced) 0.000 0.280 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10_n_0
|
|
r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CI
|
|
CARRY4 (Prop_carry4_CI_CO[3])
|
|
0.114 0.394 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CO[3]
|
|
net (fo=1, unplaced) 0.000 0.394 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9_n_0
|
|
r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/CI
|
|
CARRY4 (Prop_carry4_CI_CO[3])
|
|
0.114 0.508 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/CO[3]
|
|
net (fo=1, unplaced) 0.000 0.508 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11_n_0
|
|
r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_10/CI
|
|
CARRY4 (Prop_carry4_CI_CO[3])
|
|
0.114 0.622 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_10/CO[3]
|
|
net (fo=1, unplaced) 0.000 0.622 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_10_n_0
|
|
r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2_i_9/CI
|
|
CARRY4 (Prop_carry4_CI_O[3])
|
|
0.329 0.951 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2_i_9/O[3]
|
|
net (fo=3, unplaced) 0.826 1.777 u_axi_ram/u_axi_sram_sp/upper_wrap_boundary[29]
|
|
r u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1_i_2/I0
|
|
LUT6 (Prop_lut6_I0_O) 0.307 2.084 r u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1_i_2/O
|
|
net (fo=1, unplaced) 0.000 2.084 u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1_i_2_n_0
|
|
r u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1/S[1]
|
|
CARRY4 (Prop_carry4_S[1]_CO[2])
|
|
0.570 2.654 r u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1/CO[2]
|
|
net (fo=23, unplaced) 0.515 3.169 u_axi_ram/u_axi_sram_sp/req_addr_d10_in
|
|
r u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/I5
|
|
LUT6 (Prop_lut6_I5_O) 0.310 3.479 f u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/O
|
|
net (fo=2, unplaced) 0.460 3.939 u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7_n_0
|
|
f u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/I1
|
|
LUT6 (Prop_lut6_I1_O) 0.124 4.063 f u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/O
|
|
net (fo=80, unplaced) 0.543 4.606 u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/soc_sram_addr[0]
|
|
f u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/base_ram_data_IOBUF[31]_inst_i_3/I2
|
|
LUT3 (Prop_lut3_I2_O) 0.124 4.730 r u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/base_ram_data_IOBUF[31]_inst_i_3/O
|
|
net (fo=1, unplaced) 0.449 5.179 u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/u_axi_ram/base_ram_data1
|
|
r u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/base_ram_data_IOBUF[31]_inst_i_2/I0
|
|
LUT1 (Prop_lut1_I0_O) 0.124 5.303 f u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/base_ram_data_IOBUF[31]_inst_i_2/O
|
|
net (fo=32, unplaced) 0.800 6.102 base_ram_data_IOBUF[24]_inst/T
|
|
T22 f base_ram_data_IOBUF[24]_inst/OBUFT/T
|
|
T22 OBUFT (TriStatE_obuft_T_O)
|
|
3.551 9.653 r base_ram_data_IOBUF[24]_inst/OBUFT/O
|
|
net (fo=1, unset) 0.000 9.653 base_ram_data[24]
|
|
T22 r base_ram_data[24] (INOUT)
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock sys_clk rise edge) 20.000 20.000 r
|
|
K21 0.000 20.000 r clk (IN)
|
|
net (fo=0) 0.000 20.000 pll_clk.u_clk_pll/inst/clk_in1
|
|
K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I
|
|
K21 IBUF (Prop_ibuf_I_O) 1.393 21.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O
|
|
net (fo=1, unplaced) 0.439 21.832 pll_clk.u_clk_pll/inst/clk_in1_clk_pll
|
|
r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1
|
|
PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1)
|
|
-6.040 15.792 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1
|
|
clock pessimism -0.513 15.279
|
|
clock uncertainty -0.071 15.209
|
|
output delay -0.300 14.909
|
|
-------------------------------------------------------------------
|
|
required time 14.909
|
|
arrival time -9.653
|
|
-------------------------------------------------------------------
|
|
slack 5.256
|
|
|
|
Slack (MET) : 5.256ns (required time - arrival time)
|
|
Source: u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[2]/C
|
|
(rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Destination: base_ram_data[29]
|
|
(output port clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Path Group: sys_clk
|
|
Path Type: Max at Slow Process Corner
|
|
Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns)
|
|
Data Path Delay: 12.678ns (logic 7.338ns (57.876%) route 5.341ns (42.124%))
|
|
Logic Levels: 15 (CARRY4=6 LUT1=1 LUT3=1 LUT4=1 LUT5=1 LUT6=4 OBUFT=1)
|
|
Output Delay: 0.300ns
|
|
Clock Path Skew: -1.695ns (DCD - SCD + CPR)
|
|
Destination Clock Delay (DCD): -4.208ns = ( 15.792 - 20.000 )
|
|
Source Clock Delay (SCD): -3.025ns
|
|
Clock Pessimism Removal (CPR): -0.513ns
|
|
Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Discrete Jitter (DJ): 0.122ns
|
|
Phase Error (PE): 0.000ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock sys_clk rise edge) 0.000 0.000 r
|
|
K21 0.000 0.000 r clk (IN)
|
|
net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1
|
|
K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I
|
|
K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O
|
|
net (fo=1, unplaced) 0.584 2.047 pll_clk.u_clk_pll/inst/clk_in1_clk_pll
|
|
r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1
|
|
PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1)
|
|
-6.768 -4.721 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1
|
|
net (fo=1, unplaced) 0.800 -3.921 pll_clk.u_clk_pll/inst/sys_clk_clk_pll
|
|
r pll_clk.u_clk_pll/inst/clkout2_buf/I
|
|
BUFG (Prop_bufg_I_O) 0.096 -3.825 r pll_clk.u_clk_pll/inst/clkout2_buf/O
|
|
net (fo=10994, unplaced) 0.800 -3.025 u_axi_ram/u_axi_sram_sp/sys_clk
|
|
FDCE r u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[2]/C
|
|
------------------------------------------------------------------- -------------------
|
|
FDCE (Prop_fdce_C_Q) 0.456 -2.569 f u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[2]/Q
|
|
net (fo=56, unplaced) 0.826 -1.743 u_axi_ram/u_axi_sram_sp/len[2]
|
|
f u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6/I1
|
|
LUT4 (Prop_lut4_I1_O) 0.321 -1.422 r u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6/O
|
|
net (fo=4, unplaced) 0.473 -0.949 u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6_n_0
|
|
r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_20/I1
|
|
LUT5 (Prop_lut5_I1_O) 0.124 -0.825 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_20/O
|
|
net (fo=1, unplaced) 0.449 -0.376 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_20_n_0
|
|
r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_19/I5
|
|
LUT6 (Prop_lut6_I5_O) 0.124 -0.252 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_19/O
|
|
net (fo=1, unplaced) 0.000 -0.252 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_19_n_0
|
|
r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/S[0]
|
|
CARRY4 (Prop_carry4_S[0]_CO[3])
|
|
0.532 0.280 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/CO[3]
|
|
net (fo=1, unplaced) 0.000 0.280 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10_n_0
|
|
r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CI
|
|
CARRY4 (Prop_carry4_CI_CO[3])
|
|
0.114 0.394 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CO[3]
|
|
net (fo=1, unplaced) 0.000 0.394 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9_n_0
|
|
r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/CI
|
|
CARRY4 (Prop_carry4_CI_CO[3])
|
|
0.114 0.508 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/CO[3]
|
|
net (fo=1, unplaced) 0.000 0.508 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11_n_0
|
|
r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_10/CI
|
|
CARRY4 (Prop_carry4_CI_CO[3])
|
|
0.114 0.622 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_10/CO[3]
|
|
net (fo=1, unplaced) 0.000 0.622 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_10_n_0
|
|
r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2_i_9/CI
|
|
CARRY4 (Prop_carry4_CI_O[3])
|
|
0.329 0.951 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2_i_9/O[3]
|
|
net (fo=3, unplaced) 0.826 1.777 u_axi_ram/u_axi_sram_sp/upper_wrap_boundary[29]
|
|
r u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1_i_2/I0
|
|
LUT6 (Prop_lut6_I0_O) 0.307 2.084 r u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1_i_2/O
|
|
net (fo=1, unplaced) 0.000 2.084 u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1_i_2_n_0
|
|
r u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1/S[1]
|
|
CARRY4 (Prop_carry4_S[1]_CO[2])
|
|
0.570 2.654 r u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1/CO[2]
|
|
net (fo=23, unplaced) 0.515 3.169 u_axi_ram/u_axi_sram_sp/req_addr_d10_in
|
|
r u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/I5
|
|
LUT6 (Prop_lut6_I5_O) 0.310 3.479 f u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/O
|
|
net (fo=2, unplaced) 0.460 3.939 u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7_n_0
|
|
f u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/I1
|
|
LUT6 (Prop_lut6_I1_O) 0.124 4.063 f u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/O
|
|
net (fo=80, unplaced) 0.543 4.606 u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/soc_sram_addr[0]
|
|
f u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/base_ram_data_IOBUF[31]_inst_i_3/I2
|
|
LUT3 (Prop_lut3_I2_O) 0.124 4.730 r u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/base_ram_data_IOBUF[31]_inst_i_3/O
|
|
net (fo=1, unplaced) 0.449 5.179 u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/u_axi_ram/base_ram_data1
|
|
r u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/base_ram_data_IOBUF[31]_inst_i_2/I0
|
|
LUT1 (Prop_lut1_I0_O) 0.124 5.303 f u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/base_ram_data_IOBUF[31]_inst_i_2/O
|
|
net (fo=32, unplaced) 0.800 6.102 base_ram_data_IOBUF[29]_inst/T
|
|
N23 f base_ram_data_IOBUF[29]_inst/OBUFT/T
|
|
N23 OBUFT (TriStatE_obuft_T_O)
|
|
3.551 9.653 r base_ram_data_IOBUF[29]_inst/OBUFT/O
|
|
net (fo=1, unset) 0.000 9.653 base_ram_data[29]
|
|
N23 r base_ram_data[29] (INOUT)
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock sys_clk rise edge) 20.000 20.000 r
|
|
K21 0.000 20.000 r clk (IN)
|
|
net (fo=0) 0.000 20.000 pll_clk.u_clk_pll/inst/clk_in1
|
|
K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I
|
|
K21 IBUF (Prop_ibuf_I_O) 1.393 21.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O
|
|
net (fo=1, unplaced) 0.439 21.832 pll_clk.u_clk_pll/inst/clk_in1_clk_pll
|
|
r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1
|
|
PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1)
|
|
-6.040 15.792 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1
|
|
clock pessimism -0.513 15.279
|
|
clock uncertainty -0.071 15.209
|
|
output delay -0.300 14.909
|
|
-------------------------------------------------------------------
|
|
required time 14.909
|
|
arrival time -9.653
|
|
-------------------------------------------------------------------
|
|
slack 5.256
|
|
|
|
Slack (MET) : 5.257ns (required time - arrival time)
|
|
Source: u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[2]/C
|
|
(rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Destination: ext_ram_data[17]
|
|
(output port clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Path Group: sys_clk
|
|
Path Type: Max at Slow Process Corner
|
|
Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns)
|
|
Data Path Delay: 12.677ns (logic 7.336ns (57.870%) route 5.341ns (42.130%))
|
|
Logic Levels: 15 (CARRY4=6 LUT1=1 LUT3=1 LUT4=1 LUT5=1 LUT6=4 OBUFT=1)
|
|
Output Delay: 0.300ns
|
|
Clock Path Skew: -1.695ns (DCD - SCD + CPR)
|
|
Destination Clock Delay (DCD): -4.208ns = ( 15.792 - 20.000 )
|
|
Source Clock Delay (SCD): -3.025ns
|
|
Clock Pessimism Removal (CPR): -0.513ns
|
|
Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Discrete Jitter (DJ): 0.122ns
|
|
Phase Error (PE): 0.000ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock sys_clk rise edge) 0.000 0.000 r
|
|
K21 0.000 0.000 r clk (IN)
|
|
net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1
|
|
K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I
|
|
K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O
|
|
net (fo=1, unplaced) 0.584 2.047 pll_clk.u_clk_pll/inst/clk_in1_clk_pll
|
|
r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1
|
|
PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1)
|
|
-6.768 -4.721 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1
|
|
net (fo=1, unplaced) 0.800 -3.921 pll_clk.u_clk_pll/inst/sys_clk_clk_pll
|
|
r pll_clk.u_clk_pll/inst/clkout2_buf/I
|
|
BUFG (Prop_bufg_I_O) 0.096 -3.825 r pll_clk.u_clk_pll/inst/clkout2_buf/O
|
|
net (fo=10994, unplaced) 0.800 -3.025 u_axi_ram/u_axi_sram_sp/sys_clk
|
|
FDCE r u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[2]/C
|
|
------------------------------------------------------------------- -------------------
|
|
FDCE (Prop_fdce_C_Q) 0.456 -2.569 f u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[2]/Q
|
|
net (fo=56, unplaced) 0.826 -1.743 u_axi_ram/u_axi_sram_sp/len[2]
|
|
f u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6/I1
|
|
LUT4 (Prop_lut4_I1_O) 0.321 -1.422 r u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6/O
|
|
net (fo=4, unplaced) 0.473 -0.949 u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6_n_0
|
|
r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_20/I1
|
|
LUT5 (Prop_lut5_I1_O) 0.124 -0.825 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_20/O
|
|
net (fo=1, unplaced) 0.449 -0.376 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_20_n_0
|
|
r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_19/I5
|
|
LUT6 (Prop_lut6_I5_O) 0.124 -0.252 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_19/O
|
|
net (fo=1, unplaced) 0.000 -0.252 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_19_n_0
|
|
r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/S[0]
|
|
CARRY4 (Prop_carry4_S[0]_CO[3])
|
|
0.532 0.280 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/CO[3]
|
|
net (fo=1, unplaced) 0.000 0.280 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10_n_0
|
|
r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CI
|
|
CARRY4 (Prop_carry4_CI_CO[3])
|
|
0.114 0.394 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CO[3]
|
|
net (fo=1, unplaced) 0.000 0.394 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9_n_0
|
|
r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/CI
|
|
CARRY4 (Prop_carry4_CI_CO[3])
|
|
0.114 0.508 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/CO[3]
|
|
net (fo=1, unplaced) 0.000 0.508 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11_n_0
|
|
r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_10/CI
|
|
CARRY4 (Prop_carry4_CI_CO[3])
|
|
0.114 0.622 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_10/CO[3]
|
|
net (fo=1, unplaced) 0.000 0.622 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_10_n_0
|
|
r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2_i_9/CI
|
|
CARRY4 (Prop_carry4_CI_O[3])
|
|
0.329 0.951 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2_i_9/O[3]
|
|
net (fo=3, unplaced) 0.826 1.777 u_axi_ram/u_axi_sram_sp/upper_wrap_boundary[29]
|
|
r u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1_i_2/I0
|
|
LUT6 (Prop_lut6_I0_O) 0.307 2.084 r u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1_i_2/O
|
|
net (fo=1, unplaced) 0.000 2.084 u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1_i_2_n_0
|
|
r u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1/S[1]
|
|
CARRY4 (Prop_carry4_S[1]_CO[2])
|
|
0.570 2.654 r u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1/CO[2]
|
|
net (fo=23, unplaced) 0.515 3.169 u_axi_ram/u_axi_sram_sp/req_addr_d10_in
|
|
r u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/I5
|
|
LUT6 (Prop_lut6_I5_O) 0.310 3.479 r u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/O
|
|
net (fo=2, unplaced) 0.460 3.939 u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7_n_0
|
|
r u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/I1
|
|
LUT6 (Prop_lut6_I1_O) 0.124 4.063 r u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/O
|
|
net (fo=80, unplaced) 0.543 4.606 u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/soc_sram_addr[0]
|
|
r u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/ext_ram_data_IOBUF[31]_inst_i_2/I2
|
|
LUT3 (Prop_lut3_I2_O) 0.118 4.724 r u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/ext_ram_data_IOBUF[31]_inst_i_2/O
|
|
net (fo=1, unplaced) 0.449 5.173 u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/u_axi_ram/ext_ram_data1
|
|
r u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/ext_ram_data_IOBUF[31]_inst_i_1/I0
|
|
LUT1 (Prop_lut1_I0_O) 0.124 5.297 f u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/ext_ram_data_IOBUF[31]_inst_i_1/O
|
|
net (fo=32, unplaced) 0.800 6.096 ext_ram_data_IOBUF[17]_inst/T
|
|
AC19 f ext_ram_data_IOBUF[17]_inst/OBUFT/T
|
|
AC19 OBUFT (TriStatE_obuft_T_O)
|
|
3.555 9.652 r ext_ram_data_IOBUF[17]_inst/OBUFT/O
|
|
net (fo=1, unset) 0.000 9.652 ext_ram_data[17]
|
|
AC19 r ext_ram_data[17] (INOUT)
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock sys_clk rise edge) 20.000 20.000 r
|
|
K21 0.000 20.000 r clk (IN)
|
|
net (fo=0) 0.000 20.000 pll_clk.u_clk_pll/inst/clk_in1
|
|
K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I
|
|
K21 IBUF (Prop_ibuf_I_O) 1.393 21.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O
|
|
net (fo=1, unplaced) 0.439 21.832 pll_clk.u_clk_pll/inst/clk_in1_clk_pll
|
|
r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1
|
|
PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1)
|
|
-6.040 15.792 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1
|
|
clock pessimism -0.513 15.279
|
|
clock uncertainty -0.071 15.209
|
|
output delay -0.300 14.909
|
|
-------------------------------------------------------------------
|
|
required time 14.909
|
|
arrival time -9.652
|
|
-------------------------------------------------------------------
|
|
slack 5.257
|
|
|
|
Slack (MET) : 5.258ns (required time - arrival time)
|
|
Source: u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[2]/C
|
|
(rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Destination: base_ram_data[18]
|
|
(output port clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Path Group: sys_clk
|
|
Path Type: Max at Slow Process Corner
|
|
Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns)
|
|
Data Path Delay: 12.676ns (logic 7.336ns (57.869%) route 5.341ns (42.131%))
|
|
Logic Levels: 15 (CARRY4=6 LUT1=1 LUT3=1 LUT4=1 LUT5=1 LUT6=4 OBUFT=1)
|
|
Output Delay: 0.300ns
|
|
Clock Path Skew: -1.695ns (DCD - SCD + CPR)
|
|
Destination Clock Delay (DCD): -4.208ns = ( 15.792 - 20.000 )
|
|
Source Clock Delay (SCD): -3.025ns
|
|
Clock Pessimism Removal (CPR): -0.513ns
|
|
Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Discrete Jitter (DJ): 0.122ns
|
|
Phase Error (PE): 0.000ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock sys_clk rise edge) 0.000 0.000 r
|
|
K21 0.000 0.000 r clk (IN)
|
|
net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1
|
|
K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I
|
|
K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O
|
|
net (fo=1, unplaced) 0.584 2.047 pll_clk.u_clk_pll/inst/clk_in1_clk_pll
|
|
r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1
|
|
PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1)
|
|
-6.768 -4.721 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1
|
|
net (fo=1, unplaced) 0.800 -3.921 pll_clk.u_clk_pll/inst/sys_clk_clk_pll
|
|
r pll_clk.u_clk_pll/inst/clkout2_buf/I
|
|
BUFG (Prop_bufg_I_O) 0.096 -3.825 r pll_clk.u_clk_pll/inst/clkout2_buf/O
|
|
net (fo=10994, unplaced) 0.800 -3.025 u_axi_ram/u_axi_sram_sp/sys_clk
|
|
FDCE r u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[2]/C
|
|
------------------------------------------------------------------- -------------------
|
|
FDCE (Prop_fdce_C_Q) 0.456 -2.569 f u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[2]/Q
|
|
net (fo=56, unplaced) 0.826 -1.743 u_axi_ram/u_axi_sram_sp/len[2]
|
|
f u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6/I1
|
|
LUT4 (Prop_lut4_I1_O) 0.321 -1.422 r u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6/O
|
|
net (fo=4, unplaced) 0.473 -0.949 u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6_n_0
|
|
r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_20/I1
|
|
LUT5 (Prop_lut5_I1_O) 0.124 -0.825 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_20/O
|
|
net (fo=1, unplaced) 0.449 -0.376 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_20_n_0
|
|
r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_19/I5
|
|
LUT6 (Prop_lut6_I5_O) 0.124 -0.252 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_19/O
|
|
net (fo=1, unplaced) 0.000 -0.252 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_19_n_0
|
|
r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/S[0]
|
|
CARRY4 (Prop_carry4_S[0]_CO[3])
|
|
0.532 0.280 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/CO[3]
|
|
net (fo=1, unplaced) 0.000 0.280 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10_n_0
|
|
r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CI
|
|
CARRY4 (Prop_carry4_CI_CO[3])
|
|
0.114 0.394 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CO[3]
|
|
net (fo=1, unplaced) 0.000 0.394 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9_n_0
|
|
r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/CI
|
|
CARRY4 (Prop_carry4_CI_CO[3])
|
|
0.114 0.508 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/CO[3]
|
|
net (fo=1, unplaced) 0.000 0.508 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11_n_0
|
|
r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_10/CI
|
|
CARRY4 (Prop_carry4_CI_CO[3])
|
|
0.114 0.622 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_10/CO[3]
|
|
net (fo=1, unplaced) 0.000 0.622 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_10_n_0
|
|
r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2_i_9/CI
|
|
CARRY4 (Prop_carry4_CI_O[3])
|
|
0.329 0.951 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2_i_9/O[3]
|
|
net (fo=3, unplaced) 0.826 1.777 u_axi_ram/u_axi_sram_sp/upper_wrap_boundary[29]
|
|
r u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1_i_2/I0
|
|
LUT6 (Prop_lut6_I0_O) 0.307 2.084 r u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1_i_2/O
|
|
net (fo=1, unplaced) 0.000 2.084 u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1_i_2_n_0
|
|
r u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1/S[1]
|
|
CARRY4 (Prop_carry4_S[1]_CO[2])
|
|
0.570 2.654 r u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1/CO[2]
|
|
net (fo=23, unplaced) 0.515 3.169 u_axi_ram/u_axi_sram_sp/req_addr_d10_in
|
|
r u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/I5
|
|
LUT6 (Prop_lut6_I5_O) 0.310 3.479 f u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/O
|
|
net (fo=2, unplaced) 0.460 3.939 u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7_n_0
|
|
f u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/I1
|
|
LUT6 (Prop_lut6_I1_O) 0.124 4.063 f u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/O
|
|
net (fo=80, unplaced) 0.543 4.606 u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/soc_sram_addr[0]
|
|
f u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/base_ram_data_IOBUF[31]_inst_i_3/I2
|
|
LUT3 (Prop_lut3_I2_O) 0.124 4.730 r u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/base_ram_data_IOBUF[31]_inst_i_3/O
|
|
net (fo=1, unplaced) 0.449 5.179 u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/u_axi_ram/base_ram_data1
|
|
r u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/base_ram_data_IOBUF[31]_inst_i_2/I0
|
|
LUT1 (Prop_lut1_I0_O) 0.124 5.303 f u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/base_ram_data_IOBUF[31]_inst_i_2/O
|
|
net (fo=32, unplaced) 0.800 6.102 base_ram_data_IOBUF[18]_inst/T
|
|
P23 f base_ram_data_IOBUF[18]_inst/OBUFT/T
|
|
P23 OBUFT (TriStatE_obuft_T_O)
|
|
3.549 9.651 r base_ram_data_IOBUF[18]_inst/OBUFT/O
|
|
net (fo=1, unset) 0.000 9.651 base_ram_data[18]
|
|
P23 r base_ram_data[18] (INOUT)
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock sys_clk rise edge) 20.000 20.000 r
|
|
K21 0.000 20.000 r clk (IN)
|
|
net (fo=0) 0.000 20.000 pll_clk.u_clk_pll/inst/clk_in1
|
|
K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I
|
|
K21 IBUF (Prop_ibuf_I_O) 1.393 21.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O
|
|
net (fo=1, unplaced) 0.439 21.832 pll_clk.u_clk_pll/inst/clk_in1_clk_pll
|
|
r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1
|
|
PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1)
|
|
-6.040 15.792 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1
|
|
clock pessimism -0.513 15.279
|
|
clock uncertainty -0.071 15.209
|
|
output delay -0.300 14.909
|
|
-------------------------------------------------------------------
|
|
required time 14.909
|
|
arrival time -9.651
|
|
-------------------------------------------------------------------
|
|
slack 5.258
|
|
|
|
Slack (MET) : 5.259ns (required time - arrival time)
|
|
Source: u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[2]/C
|
|
(rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Destination: ext_ram_data[25]
|
|
(output port clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Path Group: sys_clk
|
|
Path Type: Max at Slow Process Corner
|
|
Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns)
|
|
Data Path Delay: 12.675ns (logic 7.334ns (57.865%) route 5.341ns (42.135%))
|
|
Logic Levels: 15 (CARRY4=6 LUT1=1 LUT3=1 LUT4=1 LUT5=1 LUT6=4 OBUFT=1)
|
|
Output Delay: 0.300ns
|
|
Clock Path Skew: -1.695ns (DCD - SCD + CPR)
|
|
Destination Clock Delay (DCD): -4.208ns = ( 15.792 - 20.000 )
|
|
Source Clock Delay (SCD): -3.025ns
|
|
Clock Pessimism Removal (CPR): -0.513ns
|
|
Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Discrete Jitter (DJ): 0.122ns
|
|
Phase Error (PE): 0.000ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock sys_clk rise edge) 0.000 0.000 r
|
|
K21 0.000 0.000 r clk (IN)
|
|
net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1
|
|
K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I
|
|
K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O
|
|
net (fo=1, unplaced) 0.584 2.047 pll_clk.u_clk_pll/inst/clk_in1_clk_pll
|
|
r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1
|
|
PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1)
|
|
-6.768 -4.721 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1
|
|
net (fo=1, unplaced) 0.800 -3.921 pll_clk.u_clk_pll/inst/sys_clk_clk_pll
|
|
r pll_clk.u_clk_pll/inst/clkout2_buf/I
|
|
BUFG (Prop_bufg_I_O) 0.096 -3.825 r pll_clk.u_clk_pll/inst/clkout2_buf/O
|
|
net (fo=10994, unplaced) 0.800 -3.025 u_axi_ram/u_axi_sram_sp/sys_clk
|
|
FDCE r u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[2]/C
|
|
------------------------------------------------------------------- -------------------
|
|
FDCE (Prop_fdce_C_Q) 0.456 -2.569 f u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[2]/Q
|
|
net (fo=56, unplaced) 0.826 -1.743 u_axi_ram/u_axi_sram_sp/len[2]
|
|
f u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6/I1
|
|
LUT4 (Prop_lut4_I1_O) 0.321 -1.422 r u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6/O
|
|
net (fo=4, unplaced) 0.473 -0.949 u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6_n_0
|
|
r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_20/I1
|
|
LUT5 (Prop_lut5_I1_O) 0.124 -0.825 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_20/O
|
|
net (fo=1, unplaced) 0.449 -0.376 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_20_n_0
|
|
r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_19/I5
|
|
LUT6 (Prop_lut6_I5_O) 0.124 -0.252 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_19/O
|
|
net (fo=1, unplaced) 0.000 -0.252 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_19_n_0
|
|
r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/S[0]
|
|
CARRY4 (Prop_carry4_S[0]_CO[3])
|
|
0.532 0.280 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/CO[3]
|
|
net (fo=1, unplaced) 0.000 0.280 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10_n_0
|
|
r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CI
|
|
CARRY4 (Prop_carry4_CI_CO[3])
|
|
0.114 0.394 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CO[3]
|
|
net (fo=1, unplaced) 0.000 0.394 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9_n_0
|
|
r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/CI
|
|
CARRY4 (Prop_carry4_CI_CO[3])
|
|
0.114 0.508 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/CO[3]
|
|
net (fo=1, unplaced) 0.000 0.508 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11_n_0
|
|
r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_10/CI
|
|
CARRY4 (Prop_carry4_CI_CO[3])
|
|
0.114 0.622 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_10/CO[3]
|
|
net (fo=1, unplaced) 0.000 0.622 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_10_n_0
|
|
r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2_i_9/CI
|
|
CARRY4 (Prop_carry4_CI_O[3])
|
|
0.329 0.951 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2_i_9/O[3]
|
|
net (fo=3, unplaced) 0.826 1.777 u_axi_ram/u_axi_sram_sp/upper_wrap_boundary[29]
|
|
r u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1_i_2/I0
|
|
LUT6 (Prop_lut6_I0_O) 0.307 2.084 r u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1_i_2/O
|
|
net (fo=1, unplaced) 0.000 2.084 u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1_i_2_n_0
|
|
r u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1/S[1]
|
|
CARRY4 (Prop_carry4_S[1]_CO[2])
|
|
0.570 2.654 r u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1/CO[2]
|
|
net (fo=23, unplaced) 0.515 3.169 u_axi_ram/u_axi_sram_sp/req_addr_d10_in
|
|
r u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/I5
|
|
LUT6 (Prop_lut6_I5_O) 0.310 3.479 r u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/O
|
|
net (fo=2, unplaced) 0.460 3.939 u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7_n_0
|
|
r u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/I1
|
|
LUT6 (Prop_lut6_I1_O) 0.124 4.063 r u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/O
|
|
net (fo=80, unplaced) 0.543 4.606 u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/soc_sram_addr[0]
|
|
r u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/ext_ram_data_IOBUF[31]_inst_i_2/I2
|
|
LUT3 (Prop_lut3_I2_O) 0.118 4.724 r u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/ext_ram_data_IOBUF[31]_inst_i_2/O
|
|
net (fo=1, unplaced) 0.449 5.173 u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/u_axi_ram/ext_ram_data1
|
|
r u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/ext_ram_data_IOBUF[31]_inst_i_1/I0
|
|
LUT1 (Prop_lut1_I0_O) 0.124 5.297 f u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/ext_ram_data_IOBUF[31]_inst_i_1/O
|
|
net (fo=32, unplaced) 0.800 6.096 ext_ram_data_IOBUF[25]_inst/T
|
|
AC17 f ext_ram_data_IOBUF[25]_inst/OBUFT/T
|
|
AC17 OBUFT (TriStatE_obuft_T_O)
|
|
3.553 9.650 r ext_ram_data_IOBUF[25]_inst/OBUFT/O
|
|
net (fo=1, unset) 0.000 9.650 ext_ram_data[25]
|
|
AC17 r ext_ram_data[25] (INOUT)
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock sys_clk rise edge) 20.000 20.000 r
|
|
K21 0.000 20.000 r clk (IN)
|
|
net (fo=0) 0.000 20.000 pll_clk.u_clk_pll/inst/clk_in1
|
|
K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I
|
|
K21 IBUF (Prop_ibuf_I_O) 1.393 21.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O
|
|
net (fo=1, unplaced) 0.439 21.832 pll_clk.u_clk_pll/inst/clk_in1_clk_pll
|
|
r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1
|
|
PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1)
|
|
-6.040 15.792 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1
|
|
clock pessimism -0.513 15.279
|
|
clock uncertainty -0.071 15.209
|
|
output delay -0.300 14.909
|
|
-------------------------------------------------------------------
|
|
required time 14.909
|
|
arrival time -9.650
|
|
-------------------------------------------------------------------
|
|
slack 5.259
|
|
|
|
Slack (MET) : 5.260ns (required time - arrival time)
|
|
Source: u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[2]/C
|
|
(rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Destination: base_ram_data[31]
|
|
(output port clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Path Group: sys_clk
|
|
Path Type: Max at Slow Process Corner
|
|
Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns)
|
|
Data Path Delay: 12.674ns (logic 7.333ns (57.861%) route 5.341ns (42.139%))
|
|
Logic Levels: 15 (CARRY4=6 LUT1=1 LUT3=1 LUT4=1 LUT5=1 LUT6=4 OBUFT=1)
|
|
Output Delay: 0.300ns
|
|
Clock Path Skew: -1.695ns (DCD - SCD + CPR)
|
|
Destination Clock Delay (DCD): -4.208ns = ( 15.792 - 20.000 )
|
|
Source Clock Delay (SCD): -3.025ns
|
|
Clock Pessimism Removal (CPR): -0.513ns
|
|
Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Discrete Jitter (DJ): 0.122ns
|
|
Phase Error (PE): 0.000ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock sys_clk rise edge) 0.000 0.000 r
|
|
K21 0.000 0.000 r clk (IN)
|
|
net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1
|
|
K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I
|
|
K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O
|
|
net (fo=1, unplaced) 0.584 2.047 pll_clk.u_clk_pll/inst/clk_in1_clk_pll
|
|
r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1
|
|
PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1)
|
|
-6.768 -4.721 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1
|
|
net (fo=1, unplaced) 0.800 -3.921 pll_clk.u_clk_pll/inst/sys_clk_clk_pll
|
|
r pll_clk.u_clk_pll/inst/clkout2_buf/I
|
|
BUFG (Prop_bufg_I_O) 0.096 -3.825 r pll_clk.u_clk_pll/inst/clkout2_buf/O
|
|
net (fo=10994, unplaced) 0.800 -3.025 u_axi_ram/u_axi_sram_sp/sys_clk
|
|
FDCE r u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[2]/C
|
|
------------------------------------------------------------------- -------------------
|
|
FDCE (Prop_fdce_C_Q) 0.456 -2.569 f u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[2]/Q
|
|
net (fo=56, unplaced) 0.826 -1.743 u_axi_ram/u_axi_sram_sp/len[2]
|
|
f u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6/I1
|
|
LUT4 (Prop_lut4_I1_O) 0.321 -1.422 r u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6/O
|
|
net (fo=4, unplaced) 0.473 -0.949 u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6_n_0
|
|
r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_20/I1
|
|
LUT5 (Prop_lut5_I1_O) 0.124 -0.825 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_20/O
|
|
net (fo=1, unplaced) 0.449 -0.376 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_20_n_0
|
|
r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_19/I5
|
|
LUT6 (Prop_lut6_I5_O) 0.124 -0.252 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_19/O
|
|
net (fo=1, unplaced) 0.000 -0.252 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_19_n_0
|
|
r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/S[0]
|
|
CARRY4 (Prop_carry4_S[0]_CO[3])
|
|
0.532 0.280 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/CO[3]
|
|
net (fo=1, unplaced) 0.000 0.280 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10_n_0
|
|
r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CI
|
|
CARRY4 (Prop_carry4_CI_CO[3])
|
|
0.114 0.394 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CO[3]
|
|
net (fo=1, unplaced) 0.000 0.394 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9_n_0
|
|
r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/CI
|
|
CARRY4 (Prop_carry4_CI_CO[3])
|
|
0.114 0.508 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/CO[3]
|
|
net (fo=1, unplaced) 0.000 0.508 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11_n_0
|
|
r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_10/CI
|
|
CARRY4 (Prop_carry4_CI_CO[3])
|
|
0.114 0.622 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_10/CO[3]
|
|
net (fo=1, unplaced) 0.000 0.622 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_10_n_0
|
|
r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2_i_9/CI
|
|
CARRY4 (Prop_carry4_CI_O[3])
|
|
0.329 0.951 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2_i_9/O[3]
|
|
net (fo=3, unplaced) 0.826 1.777 u_axi_ram/u_axi_sram_sp/upper_wrap_boundary[29]
|
|
r u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1_i_2/I0
|
|
LUT6 (Prop_lut6_I0_O) 0.307 2.084 r u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1_i_2/O
|
|
net (fo=1, unplaced) 0.000 2.084 u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1_i_2_n_0
|
|
r u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1/S[1]
|
|
CARRY4 (Prop_carry4_S[1]_CO[2])
|
|
0.570 2.654 r u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1/CO[2]
|
|
net (fo=23, unplaced) 0.515 3.169 u_axi_ram/u_axi_sram_sp/req_addr_d10_in
|
|
r u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/I5
|
|
LUT6 (Prop_lut6_I5_O) 0.310 3.479 f u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/O
|
|
net (fo=2, unplaced) 0.460 3.939 u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7_n_0
|
|
f u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/I1
|
|
LUT6 (Prop_lut6_I1_O) 0.124 4.063 f u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/O
|
|
net (fo=80, unplaced) 0.543 4.606 u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/soc_sram_addr[0]
|
|
f u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/base_ram_data_IOBUF[31]_inst_i_3/I2
|
|
LUT3 (Prop_lut3_I2_O) 0.124 4.730 r u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/base_ram_data_IOBUF[31]_inst_i_3/O
|
|
net (fo=1, unplaced) 0.449 5.179 u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/u_axi_ram/base_ram_data1
|
|
r u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/base_ram_data_IOBUF[31]_inst_i_2/I0
|
|
LUT1 (Prop_lut1_I0_O) 0.124 5.303 f u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/base_ram_data_IOBUF[31]_inst_i_2/O
|
|
net (fo=32, unplaced) 0.800 6.102 base_ram_data_IOBUF[31]_inst/T
|
|
M22 f base_ram_data_IOBUF[31]_inst/OBUFT/T
|
|
M22 OBUFT (TriStatE_obuft_T_O)
|
|
3.546 9.649 r base_ram_data_IOBUF[31]_inst/OBUFT/O
|
|
net (fo=1, unset) 0.000 9.649 base_ram_data[31]
|
|
M22 r base_ram_data[31] (INOUT)
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock sys_clk rise edge) 20.000 20.000 r
|
|
K21 0.000 20.000 r clk (IN)
|
|
net (fo=0) 0.000 20.000 pll_clk.u_clk_pll/inst/clk_in1
|
|
K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I
|
|
K21 IBUF (Prop_ibuf_I_O) 1.393 21.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O
|
|
net (fo=1, unplaced) 0.439 21.832 pll_clk.u_clk_pll/inst/clk_in1_clk_pll
|
|
r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1
|
|
PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1)
|
|
-6.040 15.792 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1
|
|
clock pessimism -0.513 15.279
|
|
clock uncertainty -0.071 15.209
|
|
output delay -0.300 14.909
|
|
-------------------------------------------------------------------
|
|
required time 14.909
|
|
arrival time -9.649
|
|
-------------------------------------------------------------------
|
|
slack 5.260
|
|
|
|
Slack (MET) : 5.260ns (required time - arrival time)
|
|
Source: u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[2]/C
|
|
(rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Destination: base_ram_data[17]
|
|
(output port clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Path Group: sys_clk
|
|
Path Type: Max at Slow Process Corner
|
|
Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns)
|
|
Data Path Delay: 12.674ns (logic 7.333ns (57.859%) route 5.341ns (42.141%))
|
|
Logic Levels: 15 (CARRY4=6 LUT1=1 LUT3=1 LUT4=1 LUT5=1 LUT6=4 OBUFT=1)
|
|
Output Delay: 0.300ns
|
|
Clock Path Skew: -1.695ns (DCD - SCD + CPR)
|
|
Destination Clock Delay (DCD): -4.208ns = ( 15.792 - 20.000 )
|
|
Source Clock Delay (SCD): -3.025ns
|
|
Clock Pessimism Removal (CPR): -0.513ns
|
|
Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Discrete Jitter (DJ): 0.122ns
|
|
Phase Error (PE): 0.000ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock sys_clk rise edge) 0.000 0.000 r
|
|
K21 0.000 0.000 r clk (IN)
|
|
net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1
|
|
K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I
|
|
K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O
|
|
net (fo=1, unplaced) 0.584 2.047 pll_clk.u_clk_pll/inst/clk_in1_clk_pll
|
|
r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1
|
|
PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1)
|
|
-6.768 -4.721 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1
|
|
net (fo=1, unplaced) 0.800 -3.921 pll_clk.u_clk_pll/inst/sys_clk_clk_pll
|
|
r pll_clk.u_clk_pll/inst/clkout2_buf/I
|
|
BUFG (Prop_bufg_I_O) 0.096 -3.825 r pll_clk.u_clk_pll/inst/clkout2_buf/O
|
|
net (fo=10994, unplaced) 0.800 -3.025 u_axi_ram/u_axi_sram_sp/sys_clk
|
|
FDCE r u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[2]/C
|
|
------------------------------------------------------------------- -------------------
|
|
FDCE (Prop_fdce_C_Q) 0.456 -2.569 f u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[2]/Q
|
|
net (fo=56, unplaced) 0.826 -1.743 u_axi_ram/u_axi_sram_sp/len[2]
|
|
f u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6/I1
|
|
LUT4 (Prop_lut4_I1_O) 0.321 -1.422 r u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6/O
|
|
net (fo=4, unplaced) 0.473 -0.949 u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6_n_0
|
|
r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_20/I1
|
|
LUT5 (Prop_lut5_I1_O) 0.124 -0.825 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_20/O
|
|
net (fo=1, unplaced) 0.449 -0.376 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_20_n_0
|
|
r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_19/I5
|
|
LUT6 (Prop_lut6_I5_O) 0.124 -0.252 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_19/O
|
|
net (fo=1, unplaced) 0.000 -0.252 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_19_n_0
|
|
r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/S[0]
|
|
CARRY4 (Prop_carry4_S[0]_CO[3])
|
|
0.532 0.280 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/CO[3]
|
|
net (fo=1, unplaced) 0.000 0.280 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10_n_0
|
|
r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CI
|
|
CARRY4 (Prop_carry4_CI_CO[3])
|
|
0.114 0.394 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CO[3]
|
|
net (fo=1, unplaced) 0.000 0.394 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9_n_0
|
|
r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/CI
|
|
CARRY4 (Prop_carry4_CI_CO[3])
|
|
0.114 0.508 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/CO[3]
|
|
net (fo=1, unplaced) 0.000 0.508 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11_n_0
|
|
r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_10/CI
|
|
CARRY4 (Prop_carry4_CI_CO[3])
|
|
0.114 0.622 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_10/CO[3]
|
|
net (fo=1, unplaced) 0.000 0.622 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_10_n_0
|
|
r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2_i_9/CI
|
|
CARRY4 (Prop_carry4_CI_O[3])
|
|
0.329 0.951 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2_i_9/O[3]
|
|
net (fo=3, unplaced) 0.826 1.777 u_axi_ram/u_axi_sram_sp/upper_wrap_boundary[29]
|
|
r u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1_i_2/I0
|
|
LUT6 (Prop_lut6_I0_O) 0.307 2.084 r u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1_i_2/O
|
|
net (fo=1, unplaced) 0.000 2.084 u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1_i_2_n_0
|
|
r u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1/S[1]
|
|
CARRY4 (Prop_carry4_S[1]_CO[2])
|
|
0.570 2.654 r u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1/CO[2]
|
|
net (fo=23, unplaced) 0.515 3.169 u_axi_ram/u_axi_sram_sp/req_addr_d10_in
|
|
r u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/I5
|
|
LUT6 (Prop_lut6_I5_O) 0.310 3.479 f u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/O
|
|
net (fo=2, unplaced) 0.460 3.939 u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7_n_0
|
|
f u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/I1
|
|
LUT6 (Prop_lut6_I1_O) 0.124 4.063 f u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/O
|
|
net (fo=80, unplaced) 0.543 4.606 u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/soc_sram_addr[0]
|
|
f u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/base_ram_data_IOBUF[31]_inst_i_3/I2
|
|
LUT3 (Prop_lut3_I2_O) 0.124 4.730 r u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/base_ram_data_IOBUF[31]_inst_i_3/O
|
|
net (fo=1, unplaced) 0.449 5.179 u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/u_axi_ram/base_ram_data1
|
|
r u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/base_ram_data_IOBUF[31]_inst_i_2/I0
|
|
LUT1 (Prop_lut1_I0_O) 0.124 5.303 f u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/base_ram_data_IOBUF[31]_inst_i_2/O
|
|
net (fo=32, unplaced) 0.800 6.102 base_ram_data_IOBUF[17]_inst/T
|
|
M21 f base_ram_data_IOBUF[17]_inst/OBUFT/T
|
|
M21 OBUFT (TriStatE_obuft_T_O)
|
|
3.546 9.648 r base_ram_data_IOBUF[17]_inst/OBUFT/O
|
|
net (fo=1, unset) 0.000 9.648 base_ram_data[17]
|
|
M21 r base_ram_data[17] (INOUT)
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock sys_clk rise edge) 20.000 20.000 r
|
|
K21 0.000 20.000 r clk (IN)
|
|
net (fo=0) 0.000 20.000 pll_clk.u_clk_pll/inst/clk_in1
|
|
K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I
|
|
K21 IBUF (Prop_ibuf_I_O) 1.393 21.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O
|
|
net (fo=1, unplaced) 0.439 21.832 pll_clk.u_clk_pll/inst/clk_in1_clk_pll
|
|
r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1
|
|
PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1)
|
|
-6.040 15.792 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1
|
|
clock pessimism -0.513 15.279
|
|
clock uncertainty -0.071 15.209
|
|
output delay -0.300 14.909
|
|
-------------------------------------------------------------------
|
|
required time 14.909
|
|
arrival time -9.648
|
|
-------------------------------------------------------------------
|
|
slack 5.260
|
|
|
|
Slack (MET) : 5.263ns (required time - arrival time)
|
|
Source: u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[2]/C
|
|
(rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Destination: base_ram_data[21]
|
|
(output port clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Path Group: sys_clk
|
|
Path Type: Max at Slow Process Corner
|
|
Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns)
|
|
Data Path Delay: 12.671ns (logic 7.331ns (57.852%) route 5.341ns (42.148%))
|
|
Logic Levels: 15 (CARRY4=6 LUT1=1 LUT3=1 LUT4=1 LUT5=1 LUT6=4 OBUFT=1)
|
|
Output Delay: 0.300ns
|
|
Clock Path Skew: -1.695ns (DCD - SCD + CPR)
|
|
Destination Clock Delay (DCD): -4.208ns = ( 15.792 - 20.000 )
|
|
Source Clock Delay (SCD): -3.025ns
|
|
Clock Pessimism Removal (CPR): -0.513ns
|
|
Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Discrete Jitter (DJ): 0.122ns
|
|
Phase Error (PE): 0.000ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock sys_clk rise edge) 0.000 0.000 r
|
|
K21 0.000 0.000 r clk (IN)
|
|
net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1
|
|
K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I
|
|
K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O
|
|
net (fo=1, unplaced) 0.584 2.047 pll_clk.u_clk_pll/inst/clk_in1_clk_pll
|
|
r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1
|
|
PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1)
|
|
-6.768 -4.721 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1
|
|
net (fo=1, unplaced) 0.800 -3.921 pll_clk.u_clk_pll/inst/sys_clk_clk_pll
|
|
r pll_clk.u_clk_pll/inst/clkout2_buf/I
|
|
BUFG (Prop_bufg_I_O) 0.096 -3.825 r pll_clk.u_clk_pll/inst/clkout2_buf/O
|
|
net (fo=10994, unplaced) 0.800 -3.025 u_axi_ram/u_axi_sram_sp/sys_clk
|
|
FDCE r u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[2]/C
|
|
------------------------------------------------------------------- -------------------
|
|
FDCE (Prop_fdce_C_Q) 0.456 -2.569 f u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[2]/Q
|
|
net (fo=56, unplaced) 0.826 -1.743 u_axi_ram/u_axi_sram_sp/len[2]
|
|
f u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6/I1
|
|
LUT4 (Prop_lut4_I1_O) 0.321 -1.422 r u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6/O
|
|
net (fo=4, unplaced) 0.473 -0.949 u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6_n_0
|
|
r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_20/I1
|
|
LUT5 (Prop_lut5_I1_O) 0.124 -0.825 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_20/O
|
|
net (fo=1, unplaced) 0.449 -0.376 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_20_n_0
|
|
r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_19/I5
|
|
LUT6 (Prop_lut6_I5_O) 0.124 -0.252 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_19/O
|
|
net (fo=1, unplaced) 0.000 -0.252 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_19_n_0
|
|
r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/S[0]
|
|
CARRY4 (Prop_carry4_S[0]_CO[3])
|
|
0.532 0.280 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/CO[3]
|
|
net (fo=1, unplaced) 0.000 0.280 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10_n_0
|
|
r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CI
|
|
CARRY4 (Prop_carry4_CI_CO[3])
|
|
0.114 0.394 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CO[3]
|
|
net (fo=1, unplaced) 0.000 0.394 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9_n_0
|
|
r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/CI
|
|
CARRY4 (Prop_carry4_CI_CO[3])
|
|
0.114 0.508 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/CO[3]
|
|
net (fo=1, unplaced) 0.000 0.508 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11_n_0
|
|
r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_10/CI
|
|
CARRY4 (Prop_carry4_CI_CO[3])
|
|
0.114 0.622 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_10/CO[3]
|
|
net (fo=1, unplaced) 0.000 0.622 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_10_n_0
|
|
r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2_i_9/CI
|
|
CARRY4 (Prop_carry4_CI_O[3])
|
|
0.329 0.951 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2_i_9/O[3]
|
|
net (fo=3, unplaced) 0.826 1.777 u_axi_ram/u_axi_sram_sp/upper_wrap_boundary[29]
|
|
r u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1_i_2/I0
|
|
LUT6 (Prop_lut6_I0_O) 0.307 2.084 r u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1_i_2/O
|
|
net (fo=1, unplaced) 0.000 2.084 u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1_i_2_n_0
|
|
r u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1/S[1]
|
|
CARRY4 (Prop_carry4_S[1]_CO[2])
|
|
0.570 2.654 r u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1/CO[2]
|
|
net (fo=23, unplaced) 0.515 3.169 u_axi_ram/u_axi_sram_sp/req_addr_d10_in
|
|
r u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/I5
|
|
LUT6 (Prop_lut6_I5_O) 0.310 3.479 f u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/O
|
|
net (fo=2, unplaced) 0.460 3.939 u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7_n_0
|
|
f u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/I1
|
|
LUT6 (Prop_lut6_I1_O) 0.124 4.063 f u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/O
|
|
net (fo=80, unplaced) 0.543 4.606 u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/soc_sram_addr[0]
|
|
f u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/base_ram_data_IOBUF[31]_inst_i_3/I2
|
|
LUT3 (Prop_lut3_I2_O) 0.124 4.730 r u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/base_ram_data_IOBUF[31]_inst_i_3/O
|
|
net (fo=1, unplaced) 0.449 5.179 u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/u_axi_ram/base_ram_data1
|
|
r u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/base_ram_data_IOBUF[31]_inst_i_2/I0
|
|
LUT1 (Prop_lut1_I0_O) 0.124 5.303 f u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/base_ram_data_IOBUF[31]_inst_i_2/O
|
|
net (fo=32, unplaced) 0.800 6.102 base_ram_data_IOBUF[21]_inst/T
|
|
M20 f base_ram_data_IOBUF[21]_inst/OBUFT/T
|
|
M20 OBUFT (TriStatE_obuft_T_O)
|
|
3.544 9.646 r base_ram_data_IOBUF[21]_inst/OBUFT/O
|
|
net (fo=1, unset) 0.000 9.646 base_ram_data[21]
|
|
M20 r base_ram_data[21] (INOUT)
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock sys_clk rise edge) 20.000 20.000 r
|
|
K21 0.000 20.000 r clk (IN)
|
|
net (fo=0) 0.000 20.000 pll_clk.u_clk_pll/inst/clk_in1
|
|
K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I
|
|
K21 IBUF (Prop_ibuf_I_O) 1.393 21.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O
|
|
net (fo=1, unplaced) 0.439 21.832 pll_clk.u_clk_pll/inst/clk_in1_clk_pll
|
|
r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1
|
|
PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1)
|
|
-6.040 15.792 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1
|
|
clock pessimism -0.513 15.279
|
|
clock uncertainty -0.071 15.209
|
|
output delay -0.300 14.909
|
|
-------------------------------------------------------------------
|
|
required time 14.909
|
|
arrival time -9.646
|
|
-------------------------------------------------------------------
|
|
slack 5.263
|
|
|
|
Slack (MET) : 5.266ns (required time - arrival time)
|
|
Source: u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[2]/C
|
|
(rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Destination: ext_ram_data[21]
|
|
(output port clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Path Group: sys_clk
|
|
Path Type: Max at Slow Process Corner
|
|
Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns)
|
|
Data Path Delay: 12.668ns (logic 7.327ns (57.840%) route 5.341ns (42.160%))
|
|
Logic Levels: 15 (CARRY4=6 LUT1=1 LUT3=1 LUT4=1 LUT5=1 LUT6=4 OBUFT=1)
|
|
Output Delay: 0.300ns
|
|
Clock Path Skew: -1.695ns (DCD - SCD + CPR)
|
|
Destination Clock Delay (DCD): -4.208ns = ( 15.792 - 20.000 )
|
|
Source Clock Delay (SCD): -3.025ns
|
|
Clock Pessimism Removal (CPR): -0.513ns
|
|
Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Discrete Jitter (DJ): 0.122ns
|
|
Phase Error (PE): 0.000ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock sys_clk rise edge) 0.000 0.000 r
|
|
K21 0.000 0.000 r clk (IN)
|
|
net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1
|
|
K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I
|
|
K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O
|
|
net (fo=1, unplaced) 0.584 2.047 pll_clk.u_clk_pll/inst/clk_in1_clk_pll
|
|
r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1
|
|
PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1)
|
|
-6.768 -4.721 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1
|
|
net (fo=1, unplaced) 0.800 -3.921 pll_clk.u_clk_pll/inst/sys_clk_clk_pll
|
|
r pll_clk.u_clk_pll/inst/clkout2_buf/I
|
|
BUFG (Prop_bufg_I_O) 0.096 -3.825 r pll_clk.u_clk_pll/inst/clkout2_buf/O
|
|
net (fo=10994, unplaced) 0.800 -3.025 u_axi_ram/u_axi_sram_sp/sys_clk
|
|
FDCE r u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[2]/C
|
|
------------------------------------------------------------------- -------------------
|
|
FDCE (Prop_fdce_C_Q) 0.456 -2.569 f u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[2]/Q
|
|
net (fo=56, unplaced) 0.826 -1.743 u_axi_ram/u_axi_sram_sp/len[2]
|
|
f u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6/I1
|
|
LUT4 (Prop_lut4_I1_O) 0.321 -1.422 r u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6/O
|
|
net (fo=4, unplaced) 0.473 -0.949 u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6_n_0
|
|
r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_20/I1
|
|
LUT5 (Prop_lut5_I1_O) 0.124 -0.825 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_20/O
|
|
net (fo=1, unplaced) 0.449 -0.376 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_20_n_0
|
|
r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_19/I5
|
|
LUT6 (Prop_lut6_I5_O) 0.124 -0.252 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_19/O
|
|
net (fo=1, unplaced) 0.000 -0.252 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_19_n_0
|
|
r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/S[0]
|
|
CARRY4 (Prop_carry4_S[0]_CO[3])
|
|
0.532 0.280 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/CO[3]
|
|
net (fo=1, unplaced) 0.000 0.280 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10_n_0
|
|
r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CI
|
|
CARRY4 (Prop_carry4_CI_CO[3])
|
|
0.114 0.394 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CO[3]
|
|
net (fo=1, unplaced) 0.000 0.394 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9_n_0
|
|
r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/CI
|
|
CARRY4 (Prop_carry4_CI_CO[3])
|
|
0.114 0.508 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/CO[3]
|
|
net (fo=1, unplaced) 0.000 0.508 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11_n_0
|
|
r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_10/CI
|
|
CARRY4 (Prop_carry4_CI_CO[3])
|
|
0.114 0.622 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_10/CO[3]
|
|
net (fo=1, unplaced) 0.000 0.622 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_10_n_0
|
|
r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2_i_9/CI
|
|
CARRY4 (Prop_carry4_CI_O[3])
|
|
0.329 0.951 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2_i_9/O[3]
|
|
net (fo=3, unplaced) 0.826 1.777 u_axi_ram/u_axi_sram_sp/upper_wrap_boundary[29]
|
|
r u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1_i_2/I0
|
|
LUT6 (Prop_lut6_I0_O) 0.307 2.084 r u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1_i_2/O
|
|
net (fo=1, unplaced) 0.000 2.084 u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1_i_2_n_0
|
|
r u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1/S[1]
|
|
CARRY4 (Prop_carry4_S[1]_CO[2])
|
|
0.570 2.654 r u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1/CO[2]
|
|
net (fo=23, unplaced) 0.515 3.169 u_axi_ram/u_axi_sram_sp/req_addr_d10_in
|
|
r u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/I5
|
|
LUT6 (Prop_lut6_I5_O) 0.310 3.479 r u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/O
|
|
net (fo=2, unplaced) 0.460 3.939 u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7_n_0
|
|
r u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/I1
|
|
LUT6 (Prop_lut6_I1_O) 0.124 4.063 r u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/O
|
|
net (fo=80, unplaced) 0.543 4.606 u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/soc_sram_addr[0]
|
|
r u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/ext_ram_data_IOBUF[31]_inst_i_2/I2
|
|
LUT3 (Prop_lut3_I2_O) 0.118 4.724 r u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/ext_ram_data_IOBUF[31]_inst_i_2/O
|
|
net (fo=1, unplaced) 0.449 5.173 u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/u_axi_ram/ext_ram_data1
|
|
r u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/ext_ram_data_IOBUF[31]_inst_i_1/I0
|
|
LUT1 (Prop_lut1_I0_O) 0.124 5.297 f u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/ext_ram_data_IOBUF[31]_inst_i_1/O
|
|
net (fo=32, unplaced) 0.800 6.096 ext_ram_data_IOBUF[21]_inst/T
|
|
AC16 f ext_ram_data_IOBUF[21]_inst/OBUFT/T
|
|
AC16 OBUFT (TriStatE_obuft_T_O)
|
|
3.546 9.642 r ext_ram_data_IOBUF[21]_inst/OBUFT/O
|
|
net (fo=1, unset) 0.000 9.642 ext_ram_data[21]
|
|
AC16 r ext_ram_data[21] (INOUT)
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock sys_clk rise edge) 20.000 20.000 r
|
|
K21 0.000 20.000 r clk (IN)
|
|
net (fo=0) 0.000 20.000 pll_clk.u_clk_pll/inst/clk_in1
|
|
K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I
|
|
K21 IBUF (Prop_ibuf_I_O) 1.393 21.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O
|
|
net (fo=1, unplaced) 0.439 21.832 pll_clk.u_clk_pll/inst/clk_in1_clk_pll
|
|
r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1
|
|
PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1)
|
|
-6.040 15.792 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1
|
|
clock pessimism -0.513 15.279
|
|
clock uncertainty -0.071 15.209
|
|
output delay -0.300 14.909
|
|
-------------------------------------------------------------------
|
|
required time 14.909
|
|
arrival time -9.642
|
|
-------------------------------------------------------------------
|
|
slack 5.266
|
|
|
|
Slack (MET) : 5.268ns (required time - arrival time)
|
|
Source: u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[2]/C
|
|
(rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Destination: ext_ram_data[30]
|
|
(output port clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Path Group: sys_clk
|
|
Path Type: Max at Slow Process Corner
|
|
Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns)
|
|
Data Path Delay: 12.666ns (logic 7.325ns (57.834%) route 5.341ns (42.166%))
|
|
Logic Levels: 15 (CARRY4=6 LUT1=1 LUT3=1 LUT4=1 LUT5=1 LUT6=4 OBUFT=1)
|
|
Output Delay: 0.300ns
|
|
Clock Path Skew: -1.695ns (DCD - SCD + CPR)
|
|
Destination Clock Delay (DCD): -4.208ns = ( 15.792 - 20.000 )
|
|
Source Clock Delay (SCD): -3.025ns
|
|
Clock Pessimism Removal (CPR): -0.513ns
|
|
Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Discrete Jitter (DJ): 0.122ns
|
|
Phase Error (PE): 0.000ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock sys_clk rise edge) 0.000 0.000 r
|
|
K21 0.000 0.000 r clk (IN)
|
|
net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1
|
|
K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I
|
|
K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O
|
|
net (fo=1, unplaced) 0.584 2.047 pll_clk.u_clk_pll/inst/clk_in1_clk_pll
|
|
r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1
|
|
PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1)
|
|
-6.768 -4.721 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1
|
|
net (fo=1, unplaced) 0.800 -3.921 pll_clk.u_clk_pll/inst/sys_clk_clk_pll
|
|
r pll_clk.u_clk_pll/inst/clkout2_buf/I
|
|
BUFG (Prop_bufg_I_O) 0.096 -3.825 r pll_clk.u_clk_pll/inst/clkout2_buf/O
|
|
net (fo=10994, unplaced) 0.800 -3.025 u_axi_ram/u_axi_sram_sp/sys_clk
|
|
FDCE r u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[2]/C
|
|
------------------------------------------------------------------- -------------------
|
|
FDCE (Prop_fdce_C_Q) 0.456 -2.569 f u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[2]/Q
|
|
net (fo=56, unplaced) 0.826 -1.743 u_axi_ram/u_axi_sram_sp/len[2]
|
|
f u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6/I1
|
|
LUT4 (Prop_lut4_I1_O) 0.321 -1.422 r u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6/O
|
|
net (fo=4, unplaced) 0.473 -0.949 u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6_n_0
|
|
r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_20/I1
|
|
LUT5 (Prop_lut5_I1_O) 0.124 -0.825 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_20/O
|
|
net (fo=1, unplaced) 0.449 -0.376 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_20_n_0
|
|
r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_19/I5
|
|
LUT6 (Prop_lut6_I5_O) 0.124 -0.252 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_19/O
|
|
net (fo=1, unplaced) 0.000 -0.252 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_19_n_0
|
|
r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/S[0]
|
|
CARRY4 (Prop_carry4_S[0]_CO[3])
|
|
0.532 0.280 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/CO[3]
|
|
net (fo=1, unplaced) 0.000 0.280 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10_n_0
|
|
r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CI
|
|
CARRY4 (Prop_carry4_CI_CO[3])
|
|
0.114 0.394 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CO[3]
|
|
net (fo=1, unplaced) 0.000 0.394 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9_n_0
|
|
r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/CI
|
|
CARRY4 (Prop_carry4_CI_CO[3])
|
|
0.114 0.508 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/CO[3]
|
|
net (fo=1, unplaced) 0.000 0.508 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11_n_0
|
|
r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_10/CI
|
|
CARRY4 (Prop_carry4_CI_CO[3])
|
|
0.114 0.622 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_10/CO[3]
|
|
net (fo=1, unplaced) 0.000 0.622 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_10_n_0
|
|
r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2_i_9/CI
|
|
CARRY4 (Prop_carry4_CI_O[3])
|
|
0.329 0.951 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2_i_9/O[3]
|
|
net (fo=3, unplaced) 0.826 1.777 u_axi_ram/u_axi_sram_sp/upper_wrap_boundary[29]
|
|
r u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1_i_2/I0
|
|
LUT6 (Prop_lut6_I0_O) 0.307 2.084 r u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1_i_2/O
|
|
net (fo=1, unplaced) 0.000 2.084 u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1_i_2_n_0
|
|
r u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1/S[1]
|
|
CARRY4 (Prop_carry4_S[1]_CO[2])
|
|
0.570 2.654 r u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1/CO[2]
|
|
net (fo=23, unplaced) 0.515 3.169 u_axi_ram/u_axi_sram_sp/req_addr_d10_in
|
|
r u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/I5
|
|
LUT6 (Prop_lut6_I5_O) 0.310 3.479 r u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/O
|
|
net (fo=2, unplaced) 0.460 3.939 u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7_n_0
|
|
r u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/I1
|
|
LUT6 (Prop_lut6_I1_O) 0.124 4.063 r u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/O
|
|
net (fo=80, unplaced) 0.543 4.606 u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/soc_sram_addr[0]
|
|
r u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/ext_ram_data_IOBUF[31]_inst_i_2/I2
|
|
LUT3 (Prop_lut3_I2_O) 0.118 4.724 r u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/ext_ram_data_IOBUF[31]_inst_i_2/O
|
|
net (fo=1, unplaced) 0.449 5.173 u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/u_axi_ram/ext_ram_data1
|
|
r u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/ext_ram_data_IOBUF[31]_inst_i_1/I0
|
|
LUT1 (Prop_lut1_I0_O) 0.124 5.297 f u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/ext_ram_data_IOBUF[31]_inst_i_1/O
|
|
net (fo=32, unplaced) 0.800 6.096 ext_ram_data_IOBUF[30]_inst/T
|
|
AA19 f ext_ram_data_IOBUF[30]_inst/OBUFT/T
|
|
AA19 OBUFT (TriStatE_obuft_T_O)
|
|
3.544 9.641 r ext_ram_data_IOBUF[30]_inst/OBUFT/O
|
|
net (fo=1, unset) 0.000 9.641 ext_ram_data[30]
|
|
AA19 r ext_ram_data[30] (INOUT)
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock sys_clk rise edge) 20.000 20.000 r
|
|
K21 0.000 20.000 r clk (IN)
|
|
net (fo=0) 0.000 20.000 pll_clk.u_clk_pll/inst/clk_in1
|
|
K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I
|
|
K21 IBUF (Prop_ibuf_I_O) 1.393 21.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O
|
|
net (fo=1, unplaced) 0.439 21.832 pll_clk.u_clk_pll/inst/clk_in1_clk_pll
|
|
r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1
|
|
PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1)
|
|
-6.040 15.792 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1
|
|
clock pessimism -0.513 15.279
|
|
clock uncertainty -0.071 15.209
|
|
output delay -0.300 14.909
|
|
-------------------------------------------------------------------
|
|
required time 14.909
|
|
arrival time -9.641
|
|
-------------------------------------------------------------------
|
|
slack 5.268
|
|
|
|
Slack (MET) : 5.269ns (required time - arrival time)
|
|
Source: u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[2]/C
|
|
(rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Destination: base_ram_data[10]
|
|
(output port clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Path Group: sys_clk
|
|
Path Type: Max at Slow Process Corner
|
|
Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns)
|
|
Data Path Delay: 12.665ns (logic 7.324ns (57.830%) route 5.341ns (42.170%))
|
|
Logic Levels: 15 (CARRY4=6 LUT1=1 LUT3=1 LUT4=1 LUT5=1 LUT6=4 OBUFT=1)
|
|
Output Delay: 0.300ns
|
|
Clock Path Skew: -1.695ns (DCD - SCD + CPR)
|
|
Destination Clock Delay (DCD): -4.208ns = ( 15.792 - 20.000 )
|
|
Source Clock Delay (SCD): -3.025ns
|
|
Clock Pessimism Removal (CPR): -0.513ns
|
|
Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Discrete Jitter (DJ): 0.122ns
|
|
Phase Error (PE): 0.000ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock sys_clk rise edge) 0.000 0.000 r
|
|
K21 0.000 0.000 r clk (IN)
|
|
net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1
|
|
K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I
|
|
K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O
|
|
net (fo=1, unplaced) 0.584 2.047 pll_clk.u_clk_pll/inst/clk_in1_clk_pll
|
|
r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1
|
|
PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1)
|
|
-6.768 -4.721 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1
|
|
net (fo=1, unplaced) 0.800 -3.921 pll_clk.u_clk_pll/inst/sys_clk_clk_pll
|
|
r pll_clk.u_clk_pll/inst/clkout2_buf/I
|
|
BUFG (Prop_bufg_I_O) 0.096 -3.825 r pll_clk.u_clk_pll/inst/clkout2_buf/O
|
|
net (fo=10994, unplaced) 0.800 -3.025 u_axi_ram/u_axi_sram_sp/sys_clk
|
|
FDCE r u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[2]/C
|
|
------------------------------------------------------------------- -------------------
|
|
FDCE (Prop_fdce_C_Q) 0.456 -2.569 f u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[2]/Q
|
|
net (fo=56, unplaced) 0.826 -1.743 u_axi_ram/u_axi_sram_sp/len[2]
|
|
f u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6/I1
|
|
LUT4 (Prop_lut4_I1_O) 0.321 -1.422 r u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6/O
|
|
net (fo=4, unplaced) 0.473 -0.949 u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6_n_0
|
|
r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_20/I1
|
|
LUT5 (Prop_lut5_I1_O) 0.124 -0.825 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_20/O
|
|
net (fo=1, unplaced) 0.449 -0.376 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_20_n_0
|
|
r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_19/I5
|
|
LUT6 (Prop_lut6_I5_O) 0.124 -0.252 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_19/O
|
|
net (fo=1, unplaced) 0.000 -0.252 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_19_n_0
|
|
r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/S[0]
|
|
CARRY4 (Prop_carry4_S[0]_CO[3])
|
|
0.532 0.280 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/CO[3]
|
|
net (fo=1, unplaced) 0.000 0.280 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10_n_0
|
|
r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CI
|
|
CARRY4 (Prop_carry4_CI_CO[3])
|
|
0.114 0.394 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CO[3]
|
|
net (fo=1, unplaced) 0.000 0.394 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9_n_0
|
|
r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/CI
|
|
CARRY4 (Prop_carry4_CI_CO[3])
|
|
0.114 0.508 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/CO[3]
|
|
net (fo=1, unplaced) 0.000 0.508 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11_n_0
|
|
r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_10/CI
|
|
CARRY4 (Prop_carry4_CI_CO[3])
|
|
0.114 0.622 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_10/CO[3]
|
|
net (fo=1, unplaced) 0.000 0.622 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_10_n_0
|
|
r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2_i_9/CI
|
|
CARRY4 (Prop_carry4_CI_O[3])
|
|
0.329 0.951 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2_i_9/O[3]
|
|
net (fo=3, unplaced) 0.826 1.777 u_axi_ram/u_axi_sram_sp/upper_wrap_boundary[29]
|
|
r u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1_i_2/I0
|
|
LUT6 (Prop_lut6_I0_O) 0.307 2.084 r u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1_i_2/O
|
|
net (fo=1, unplaced) 0.000 2.084 u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1_i_2_n_0
|
|
r u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1/S[1]
|
|
CARRY4 (Prop_carry4_S[1]_CO[2])
|
|
0.570 2.654 r u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1/CO[2]
|
|
net (fo=23, unplaced) 0.515 3.169 u_axi_ram/u_axi_sram_sp/req_addr_d10_in
|
|
r u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/I5
|
|
LUT6 (Prop_lut6_I5_O) 0.310 3.479 f u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/O
|
|
net (fo=2, unplaced) 0.460 3.939 u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7_n_0
|
|
f u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/I1
|
|
LUT6 (Prop_lut6_I1_O) 0.124 4.063 f u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/O
|
|
net (fo=80, unplaced) 0.543 4.606 u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/soc_sram_addr[0]
|
|
f u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/base_ram_data_IOBUF[31]_inst_i_3/I2
|
|
LUT3 (Prop_lut3_I2_O) 0.124 4.730 r u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/base_ram_data_IOBUF[31]_inst_i_3/O
|
|
net (fo=1, unplaced) 0.449 5.179 u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/u_axi_ram/base_ram_data1
|
|
r u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/base_ram_data_IOBUF[31]_inst_i_2/I0
|
|
LUT1 (Prop_lut1_I0_O) 0.124 5.303 f u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/base_ram_data_IOBUF[31]_inst_i_2/O
|
|
net (fo=32, unplaced) 0.800 6.102 base_ram_data_IOBUF[10]_inst/T
|
|
V21 f base_ram_data_IOBUF[10]_inst/OBUFT/T
|
|
V21 OBUFT (TriStatE_obuft_T_O)
|
|
3.537 9.639 r base_ram_data_IOBUF[10]_inst/OBUFT/O
|
|
net (fo=1, unset) 0.000 9.639 base_ram_data[10]
|
|
V21 r base_ram_data[10] (INOUT)
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock sys_clk rise edge) 20.000 20.000 r
|
|
K21 0.000 20.000 r clk (IN)
|
|
net (fo=0) 0.000 20.000 pll_clk.u_clk_pll/inst/clk_in1
|
|
K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I
|
|
K21 IBUF (Prop_ibuf_I_O) 1.393 21.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O
|
|
net (fo=1, unplaced) 0.439 21.832 pll_clk.u_clk_pll/inst/clk_in1_clk_pll
|
|
r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1
|
|
PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1)
|
|
-6.040 15.792 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1
|
|
clock pessimism -0.513 15.279
|
|
clock uncertainty -0.071 15.209
|
|
output delay -0.300 14.909
|
|
-------------------------------------------------------------------
|
|
required time 14.909
|
|
arrival time -9.639
|
|
-------------------------------------------------------------------
|
|
slack 5.269
|
|
|
|
Slack (MET) : 5.269ns (required time - arrival time)
|
|
Source: u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[2]/C
|
|
(rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Destination: ext_ram_data[22]
|
|
(output port clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Path Group: sys_clk
|
|
Path Type: Max at Slow Process Corner
|
|
Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns)
|
|
Data Path Delay: 12.665ns (logic 7.324ns (57.830%) route 5.341ns (42.170%))
|
|
Logic Levels: 15 (CARRY4=6 LUT1=1 LUT3=1 LUT4=1 LUT5=1 LUT6=4 OBUFT=1)
|
|
Output Delay: 0.300ns
|
|
Clock Path Skew: -1.695ns (DCD - SCD + CPR)
|
|
Destination Clock Delay (DCD): -4.208ns = ( 15.792 - 20.000 )
|
|
Source Clock Delay (SCD): -3.025ns
|
|
Clock Pessimism Removal (CPR): -0.513ns
|
|
Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Discrete Jitter (DJ): 0.122ns
|
|
Phase Error (PE): 0.000ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock sys_clk rise edge) 0.000 0.000 r
|
|
K21 0.000 0.000 r clk (IN)
|
|
net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1
|
|
K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I
|
|
K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O
|
|
net (fo=1, unplaced) 0.584 2.047 pll_clk.u_clk_pll/inst/clk_in1_clk_pll
|
|
r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1
|
|
PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1)
|
|
-6.768 -4.721 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1
|
|
net (fo=1, unplaced) 0.800 -3.921 pll_clk.u_clk_pll/inst/sys_clk_clk_pll
|
|
r pll_clk.u_clk_pll/inst/clkout2_buf/I
|
|
BUFG (Prop_bufg_I_O) 0.096 -3.825 r pll_clk.u_clk_pll/inst/clkout2_buf/O
|
|
net (fo=10994, unplaced) 0.800 -3.025 u_axi_ram/u_axi_sram_sp/sys_clk
|
|
FDCE r u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[2]/C
|
|
------------------------------------------------------------------- -------------------
|
|
FDCE (Prop_fdce_C_Q) 0.456 -2.569 f u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[2]/Q
|
|
net (fo=56, unplaced) 0.826 -1.743 u_axi_ram/u_axi_sram_sp/len[2]
|
|
f u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6/I1
|
|
LUT4 (Prop_lut4_I1_O) 0.321 -1.422 r u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6/O
|
|
net (fo=4, unplaced) 0.473 -0.949 u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6_n_0
|
|
r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_20/I1
|
|
LUT5 (Prop_lut5_I1_O) 0.124 -0.825 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_20/O
|
|
net (fo=1, unplaced) 0.449 -0.376 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_20_n_0
|
|
r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_19/I5
|
|
LUT6 (Prop_lut6_I5_O) 0.124 -0.252 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_19/O
|
|
net (fo=1, unplaced) 0.000 -0.252 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_19_n_0
|
|
r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/S[0]
|
|
CARRY4 (Prop_carry4_S[0]_CO[3])
|
|
0.532 0.280 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/CO[3]
|
|
net (fo=1, unplaced) 0.000 0.280 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10_n_0
|
|
r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CI
|
|
CARRY4 (Prop_carry4_CI_CO[3])
|
|
0.114 0.394 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CO[3]
|
|
net (fo=1, unplaced) 0.000 0.394 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9_n_0
|
|
r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/CI
|
|
CARRY4 (Prop_carry4_CI_CO[3])
|
|
0.114 0.508 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/CO[3]
|
|
net (fo=1, unplaced) 0.000 0.508 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11_n_0
|
|
r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_10/CI
|
|
CARRY4 (Prop_carry4_CI_CO[3])
|
|
0.114 0.622 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_10/CO[3]
|
|
net (fo=1, unplaced) 0.000 0.622 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_10_n_0
|
|
r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2_i_9/CI
|
|
CARRY4 (Prop_carry4_CI_O[3])
|
|
0.329 0.951 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2_i_9/O[3]
|
|
net (fo=3, unplaced) 0.826 1.777 u_axi_ram/u_axi_sram_sp/upper_wrap_boundary[29]
|
|
r u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1_i_2/I0
|
|
LUT6 (Prop_lut6_I0_O) 0.307 2.084 r u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1_i_2/O
|
|
net (fo=1, unplaced) 0.000 2.084 u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1_i_2_n_0
|
|
r u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1/S[1]
|
|
CARRY4 (Prop_carry4_S[1]_CO[2])
|
|
0.570 2.654 r u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1/CO[2]
|
|
net (fo=23, unplaced) 0.515 3.169 u_axi_ram/u_axi_sram_sp/req_addr_d10_in
|
|
r u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/I5
|
|
LUT6 (Prop_lut6_I5_O) 0.310 3.479 r u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/O
|
|
net (fo=2, unplaced) 0.460 3.939 u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7_n_0
|
|
r u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/I1
|
|
LUT6 (Prop_lut6_I1_O) 0.124 4.063 r u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/O
|
|
net (fo=80, unplaced) 0.543 4.606 u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/soc_sram_addr[0]
|
|
r u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/ext_ram_data_IOBUF[31]_inst_i_2/I2
|
|
LUT3 (Prop_lut3_I2_O) 0.118 4.724 r u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/ext_ram_data_IOBUF[31]_inst_i_2/O
|
|
net (fo=1, unplaced) 0.449 5.173 u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/u_axi_ram/ext_ram_data1
|
|
r u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/ext_ram_data_IOBUF[31]_inst_i_1/I0
|
|
LUT1 (Prop_lut1_I0_O) 0.124 5.297 f u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/ext_ram_data_IOBUF[31]_inst_i_1/O
|
|
net (fo=32, unplaced) 0.800 6.096 ext_ram_data_IOBUF[22]_inst/T
|
|
Y15 f ext_ram_data_IOBUF[22]_inst/OBUFT/T
|
|
Y15 OBUFT (TriStatE_obuft_T_O)
|
|
3.543 9.639 r ext_ram_data_IOBUF[22]_inst/OBUFT/O
|
|
net (fo=1, unset) 0.000 9.639 ext_ram_data[22]
|
|
Y15 r ext_ram_data[22] (INOUT)
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock sys_clk rise edge) 20.000 20.000 r
|
|
K21 0.000 20.000 r clk (IN)
|
|
net (fo=0) 0.000 20.000 pll_clk.u_clk_pll/inst/clk_in1
|
|
K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I
|
|
K21 IBUF (Prop_ibuf_I_O) 1.393 21.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O
|
|
net (fo=1, unplaced) 0.439 21.832 pll_clk.u_clk_pll/inst/clk_in1_clk_pll
|
|
r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1
|
|
PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1)
|
|
-6.040 15.792 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1
|
|
clock pessimism -0.513 15.279
|
|
clock uncertainty -0.071 15.209
|
|
output delay -0.300 14.909
|
|
-------------------------------------------------------------------
|
|
required time 14.909
|
|
arrival time -9.639
|
|
-------------------------------------------------------------------
|
|
slack 5.269
|
|
|
|
Slack (MET) : 5.270ns (required time - arrival time)
|
|
Source: u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[2]/C
|
|
(rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Destination: ext_ram_data[23]
|
|
(output port clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Path Group: sys_clk
|
|
Path Type: Max at Slow Process Corner
|
|
Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns)
|
|
Data Path Delay: 12.664ns (logic 7.323ns (57.828%) route 5.341ns (42.172%))
|
|
Logic Levels: 15 (CARRY4=6 LUT1=1 LUT3=1 LUT4=1 LUT5=1 LUT6=4 OBUFT=1)
|
|
Output Delay: 0.300ns
|
|
Clock Path Skew: -1.695ns (DCD - SCD + CPR)
|
|
Destination Clock Delay (DCD): -4.208ns = ( 15.792 - 20.000 )
|
|
Source Clock Delay (SCD): -3.025ns
|
|
Clock Pessimism Removal (CPR): -0.513ns
|
|
Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Discrete Jitter (DJ): 0.122ns
|
|
Phase Error (PE): 0.000ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock sys_clk rise edge) 0.000 0.000 r
|
|
K21 0.000 0.000 r clk (IN)
|
|
net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1
|
|
K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I
|
|
K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O
|
|
net (fo=1, unplaced) 0.584 2.047 pll_clk.u_clk_pll/inst/clk_in1_clk_pll
|
|
r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1
|
|
PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1)
|
|
-6.768 -4.721 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1
|
|
net (fo=1, unplaced) 0.800 -3.921 pll_clk.u_clk_pll/inst/sys_clk_clk_pll
|
|
r pll_clk.u_clk_pll/inst/clkout2_buf/I
|
|
BUFG (Prop_bufg_I_O) 0.096 -3.825 r pll_clk.u_clk_pll/inst/clkout2_buf/O
|
|
net (fo=10994, unplaced) 0.800 -3.025 u_axi_ram/u_axi_sram_sp/sys_clk
|
|
FDCE r u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[2]/C
|
|
------------------------------------------------------------------- -------------------
|
|
FDCE (Prop_fdce_C_Q) 0.456 -2.569 f u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[2]/Q
|
|
net (fo=56, unplaced) 0.826 -1.743 u_axi_ram/u_axi_sram_sp/len[2]
|
|
f u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6/I1
|
|
LUT4 (Prop_lut4_I1_O) 0.321 -1.422 r u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6/O
|
|
net (fo=4, unplaced) 0.473 -0.949 u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6_n_0
|
|
r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_20/I1
|
|
LUT5 (Prop_lut5_I1_O) 0.124 -0.825 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_20/O
|
|
net (fo=1, unplaced) 0.449 -0.376 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_20_n_0
|
|
r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_19/I5
|
|
LUT6 (Prop_lut6_I5_O) 0.124 -0.252 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_19/O
|
|
net (fo=1, unplaced) 0.000 -0.252 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_19_n_0
|
|
r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/S[0]
|
|
CARRY4 (Prop_carry4_S[0]_CO[3])
|
|
0.532 0.280 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/CO[3]
|
|
net (fo=1, unplaced) 0.000 0.280 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10_n_0
|
|
r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CI
|
|
CARRY4 (Prop_carry4_CI_CO[3])
|
|
0.114 0.394 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CO[3]
|
|
net (fo=1, unplaced) 0.000 0.394 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9_n_0
|
|
r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/CI
|
|
CARRY4 (Prop_carry4_CI_CO[3])
|
|
0.114 0.508 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/CO[3]
|
|
net (fo=1, unplaced) 0.000 0.508 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11_n_0
|
|
r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_10/CI
|
|
CARRY4 (Prop_carry4_CI_CO[3])
|
|
0.114 0.622 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_10/CO[3]
|
|
net (fo=1, unplaced) 0.000 0.622 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_10_n_0
|
|
r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2_i_9/CI
|
|
CARRY4 (Prop_carry4_CI_O[3])
|
|
0.329 0.951 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2_i_9/O[3]
|
|
net (fo=3, unplaced) 0.826 1.777 u_axi_ram/u_axi_sram_sp/upper_wrap_boundary[29]
|
|
r u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1_i_2/I0
|
|
LUT6 (Prop_lut6_I0_O) 0.307 2.084 r u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1_i_2/O
|
|
net (fo=1, unplaced) 0.000 2.084 u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1_i_2_n_0
|
|
r u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1/S[1]
|
|
CARRY4 (Prop_carry4_S[1]_CO[2])
|
|
0.570 2.654 r u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1/CO[2]
|
|
net (fo=23, unplaced) 0.515 3.169 u_axi_ram/u_axi_sram_sp/req_addr_d10_in
|
|
r u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/I5
|
|
LUT6 (Prop_lut6_I5_O) 0.310 3.479 r u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/O
|
|
net (fo=2, unplaced) 0.460 3.939 u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7_n_0
|
|
r u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/I1
|
|
LUT6 (Prop_lut6_I1_O) 0.124 4.063 r u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/O
|
|
net (fo=80, unplaced) 0.543 4.606 u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/soc_sram_addr[0]
|
|
r u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/ext_ram_data_IOBUF[31]_inst_i_2/I2
|
|
LUT3 (Prop_lut3_I2_O) 0.118 4.724 r u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/ext_ram_data_IOBUF[31]_inst_i_2/O
|
|
net (fo=1, unplaced) 0.449 5.173 u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/u_axi_ram/ext_ram_data1
|
|
r u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/ext_ram_data_IOBUF[31]_inst_i_1/I0
|
|
LUT1 (Prop_lut1_I0_O) 0.124 5.297 f u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/ext_ram_data_IOBUF[31]_inst_i_1/O
|
|
net (fo=32, unplaced) 0.800 6.096 ext_ram_data_IOBUF[23]_inst/T
|
|
AA15 f ext_ram_data_IOBUF[23]_inst/OBUFT/T
|
|
AA15 OBUFT (TriStatE_obuft_T_O)
|
|
3.542 9.639 r ext_ram_data_IOBUF[23]_inst/OBUFT/O
|
|
net (fo=1, unset) 0.000 9.639 ext_ram_data[23]
|
|
AA15 r ext_ram_data[23] (INOUT)
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock sys_clk rise edge) 20.000 20.000 r
|
|
K21 0.000 20.000 r clk (IN)
|
|
net (fo=0) 0.000 20.000 pll_clk.u_clk_pll/inst/clk_in1
|
|
K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I
|
|
K21 IBUF (Prop_ibuf_I_O) 1.393 21.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O
|
|
net (fo=1, unplaced) 0.439 21.832 pll_clk.u_clk_pll/inst/clk_in1_clk_pll
|
|
r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1
|
|
PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1)
|
|
-6.040 15.792 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1
|
|
clock pessimism -0.513 15.279
|
|
clock uncertainty -0.071 15.209
|
|
output delay -0.300 14.909
|
|
-------------------------------------------------------------------
|
|
required time 14.909
|
|
arrival time -9.639
|
|
-------------------------------------------------------------------
|
|
slack 5.270
|
|
|
|
Slack (MET) : 5.270ns (required time - arrival time)
|
|
Source: u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[2]/C
|
|
(rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Destination: base_ram_data[28]
|
|
(output port clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Path Group: sys_clk
|
|
Path Type: Max at Slow Process Corner
|
|
Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns)
|
|
Data Path Delay: 12.664ns (logic 7.323ns (57.826%) route 5.341ns (42.174%))
|
|
Logic Levels: 15 (CARRY4=6 LUT1=1 LUT3=1 LUT4=1 LUT5=1 LUT6=4 OBUFT=1)
|
|
Output Delay: 0.300ns
|
|
Clock Path Skew: -1.695ns (DCD - SCD + CPR)
|
|
Destination Clock Delay (DCD): -4.208ns = ( 15.792 - 20.000 )
|
|
Source Clock Delay (SCD): -3.025ns
|
|
Clock Pessimism Removal (CPR): -0.513ns
|
|
Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Discrete Jitter (DJ): 0.122ns
|
|
Phase Error (PE): 0.000ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock sys_clk rise edge) 0.000 0.000 r
|
|
K21 0.000 0.000 r clk (IN)
|
|
net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1
|
|
K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I
|
|
K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O
|
|
net (fo=1, unplaced) 0.584 2.047 pll_clk.u_clk_pll/inst/clk_in1_clk_pll
|
|
r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1
|
|
PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1)
|
|
-6.768 -4.721 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1
|
|
net (fo=1, unplaced) 0.800 -3.921 pll_clk.u_clk_pll/inst/sys_clk_clk_pll
|
|
r pll_clk.u_clk_pll/inst/clkout2_buf/I
|
|
BUFG (Prop_bufg_I_O) 0.096 -3.825 r pll_clk.u_clk_pll/inst/clkout2_buf/O
|
|
net (fo=10994, unplaced) 0.800 -3.025 u_axi_ram/u_axi_sram_sp/sys_clk
|
|
FDCE r u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[2]/C
|
|
------------------------------------------------------------------- -------------------
|
|
FDCE (Prop_fdce_C_Q) 0.456 -2.569 f u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[2]/Q
|
|
net (fo=56, unplaced) 0.826 -1.743 u_axi_ram/u_axi_sram_sp/len[2]
|
|
f u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6/I1
|
|
LUT4 (Prop_lut4_I1_O) 0.321 -1.422 r u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6/O
|
|
net (fo=4, unplaced) 0.473 -0.949 u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6_n_0
|
|
r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_20/I1
|
|
LUT5 (Prop_lut5_I1_O) 0.124 -0.825 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_20/O
|
|
net (fo=1, unplaced) 0.449 -0.376 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_20_n_0
|
|
r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_19/I5
|
|
LUT6 (Prop_lut6_I5_O) 0.124 -0.252 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_19/O
|
|
net (fo=1, unplaced) 0.000 -0.252 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_19_n_0
|
|
r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/S[0]
|
|
CARRY4 (Prop_carry4_S[0]_CO[3])
|
|
0.532 0.280 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/CO[3]
|
|
net (fo=1, unplaced) 0.000 0.280 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10_n_0
|
|
r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CI
|
|
CARRY4 (Prop_carry4_CI_CO[3])
|
|
0.114 0.394 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CO[3]
|
|
net (fo=1, unplaced) 0.000 0.394 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9_n_0
|
|
r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/CI
|
|
CARRY4 (Prop_carry4_CI_CO[3])
|
|
0.114 0.508 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/CO[3]
|
|
net (fo=1, unplaced) 0.000 0.508 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11_n_0
|
|
r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_10/CI
|
|
CARRY4 (Prop_carry4_CI_CO[3])
|
|
0.114 0.622 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_10/CO[3]
|
|
net (fo=1, unplaced) 0.000 0.622 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_10_n_0
|
|
r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2_i_9/CI
|
|
CARRY4 (Prop_carry4_CI_O[3])
|
|
0.329 0.951 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2_i_9/O[3]
|
|
net (fo=3, unplaced) 0.826 1.777 u_axi_ram/u_axi_sram_sp/upper_wrap_boundary[29]
|
|
r u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1_i_2/I0
|
|
LUT6 (Prop_lut6_I0_O) 0.307 2.084 r u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1_i_2/O
|
|
net (fo=1, unplaced) 0.000 2.084 u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1_i_2_n_0
|
|
r u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1/S[1]
|
|
CARRY4 (Prop_carry4_S[1]_CO[2])
|
|
0.570 2.654 r u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1/CO[2]
|
|
net (fo=23, unplaced) 0.515 3.169 u_axi_ram/u_axi_sram_sp/req_addr_d10_in
|
|
r u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/I5
|
|
LUT6 (Prop_lut6_I5_O) 0.310 3.479 f u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/O
|
|
net (fo=2, unplaced) 0.460 3.939 u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7_n_0
|
|
f u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/I1
|
|
LUT6 (Prop_lut6_I1_O) 0.124 4.063 f u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/O
|
|
net (fo=80, unplaced) 0.543 4.606 u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/soc_sram_addr[0]
|
|
f u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/base_ram_data_IOBUF[31]_inst_i_3/I2
|
|
LUT3 (Prop_lut3_I2_O) 0.124 4.730 r u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/base_ram_data_IOBUF[31]_inst_i_3/O
|
|
net (fo=1, unplaced) 0.449 5.179 u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/u_axi_ram/base_ram_data1
|
|
r u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/base_ram_data_IOBUF[31]_inst_i_2/I0
|
|
LUT1 (Prop_lut1_I0_O) 0.124 5.303 f u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/base_ram_data_IOBUF[31]_inst_i_2/O
|
|
net (fo=32, unplaced) 0.800 6.102 base_ram_data_IOBUF[28]_inst/T
|
|
N22 f base_ram_data_IOBUF[28]_inst/OBUFT/T
|
|
N22 OBUFT (TriStatE_obuft_T_O)
|
|
3.536 9.638 r base_ram_data_IOBUF[28]_inst/OBUFT/O
|
|
net (fo=1, unset) 0.000 9.638 base_ram_data[28]
|
|
N22 r base_ram_data[28] (INOUT)
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock sys_clk rise edge) 20.000 20.000 r
|
|
K21 0.000 20.000 r clk (IN)
|
|
net (fo=0) 0.000 20.000 pll_clk.u_clk_pll/inst/clk_in1
|
|
K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I
|
|
K21 IBUF (Prop_ibuf_I_O) 1.393 21.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O
|
|
net (fo=1, unplaced) 0.439 21.832 pll_clk.u_clk_pll/inst/clk_in1_clk_pll
|
|
r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1
|
|
PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1)
|
|
-6.040 15.792 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1
|
|
clock pessimism -0.513 15.279
|
|
clock uncertainty -0.071 15.209
|
|
output delay -0.300 14.909
|
|
-------------------------------------------------------------------
|
|
required time 14.909
|
|
arrival time -9.638
|
|
-------------------------------------------------------------------
|
|
slack 5.270
|
|
|
|
Slack (MET) : 5.270ns (required time - arrival time)
|
|
Source: u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[2]/C
|
|
(rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Destination: ext_ram_data[18]
|
|
(output port clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Path Group: sys_clk
|
|
Path Type: Max at Slow Process Corner
|
|
Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns)
|
|
Data Path Delay: 12.664ns (logic 7.323ns (57.826%) route 5.341ns (42.174%))
|
|
Logic Levels: 15 (CARRY4=6 LUT1=1 LUT3=1 LUT4=1 LUT5=1 LUT6=4 OBUFT=1)
|
|
Output Delay: 0.300ns
|
|
Clock Path Skew: -1.695ns (DCD - SCD + CPR)
|
|
Destination Clock Delay (DCD): -4.208ns = ( 15.792 - 20.000 )
|
|
Source Clock Delay (SCD): -3.025ns
|
|
Clock Pessimism Removal (CPR): -0.513ns
|
|
Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Discrete Jitter (DJ): 0.122ns
|
|
Phase Error (PE): 0.000ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock sys_clk rise edge) 0.000 0.000 r
|
|
K21 0.000 0.000 r clk (IN)
|
|
net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1
|
|
K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I
|
|
K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O
|
|
net (fo=1, unplaced) 0.584 2.047 pll_clk.u_clk_pll/inst/clk_in1_clk_pll
|
|
r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1
|
|
PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1)
|
|
-6.768 -4.721 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1
|
|
net (fo=1, unplaced) 0.800 -3.921 pll_clk.u_clk_pll/inst/sys_clk_clk_pll
|
|
r pll_clk.u_clk_pll/inst/clkout2_buf/I
|
|
BUFG (Prop_bufg_I_O) 0.096 -3.825 r pll_clk.u_clk_pll/inst/clkout2_buf/O
|
|
net (fo=10994, unplaced) 0.800 -3.025 u_axi_ram/u_axi_sram_sp/sys_clk
|
|
FDCE r u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[2]/C
|
|
------------------------------------------------------------------- -------------------
|
|
FDCE (Prop_fdce_C_Q) 0.456 -2.569 f u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[2]/Q
|
|
net (fo=56, unplaced) 0.826 -1.743 u_axi_ram/u_axi_sram_sp/len[2]
|
|
f u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6/I1
|
|
LUT4 (Prop_lut4_I1_O) 0.321 -1.422 r u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6/O
|
|
net (fo=4, unplaced) 0.473 -0.949 u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6_n_0
|
|
r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_20/I1
|
|
LUT5 (Prop_lut5_I1_O) 0.124 -0.825 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_20/O
|
|
net (fo=1, unplaced) 0.449 -0.376 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_20_n_0
|
|
r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_19/I5
|
|
LUT6 (Prop_lut6_I5_O) 0.124 -0.252 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_19/O
|
|
net (fo=1, unplaced) 0.000 -0.252 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_19_n_0
|
|
r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/S[0]
|
|
CARRY4 (Prop_carry4_S[0]_CO[3])
|
|
0.532 0.280 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/CO[3]
|
|
net (fo=1, unplaced) 0.000 0.280 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10_n_0
|
|
r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CI
|
|
CARRY4 (Prop_carry4_CI_CO[3])
|
|
0.114 0.394 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CO[3]
|
|
net (fo=1, unplaced) 0.000 0.394 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9_n_0
|
|
r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/CI
|
|
CARRY4 (Prop_carry4_CI_CO[3])
|
|
0.114 0.508 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/CO[3]
|
|
net (fo=1, unplaced) 0.000 0.508 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11_n_0
|
|
r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_10/CI
|
|
CARRY4 (Prop_carry4_CI_CO[3])
|
|
0.114 0.622 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_10/CO[3]
|
|
net (fo=1, unplaced) 0.000 0.622 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_10_n_0
|
|
r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2_i_9/CI
|
|
CARRY4 (Prop_carry4_CI_O[3])
|
|
0.329 0.951 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2_i_9/O[3]
|
|
net (fo=3, unplaced) 0.826 1.777 u_axi_ram/u_axi_sram_sp/upper_wrap_boundary[29]
|
|
r u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1_i_2/I0
|
|
LUT6 (Prop_lut6_I0_O) 0.307 2.084 r u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1_i_2/O
|
|
net (fo=1, unplaced) 0.000 2.084 u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1_i_2_n_0
|
|
r u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1/S[1]
|
|
CARRY4 (Prop_carry4_S[1]_CO[2])
|
|
0.570 2.654 r u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1/CO[2]
|
|
net (fo=23, unplaced) 0.515 3.169 u_axi_ram/u_axi_sram_sp/req_addr_d10_in
|
|
r u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/I5
|
|
LUT6 (Prop_lut6_I5_O) 0.310 3.479 r u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/O
|
|
net (fo=2, unplaced) 0.460 3.939 u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7_n_0
|
|
r u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/I1
|
|
LUT6 (Prop_lut6_I1_O) 0.124 4.063 r u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/O
|
|
net (fo=80, unplaced) 0.543 4.606 u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/soc_sram_addr[0]
|
|
r u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/ext_ram_data_IOBUF[31]_inst_i_2/I2
|
|
LUT3 (Prop_lut3_I2_O) 0.118 4.724 r u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/ext_ram_data_IOBUF[31]_inst_i_2/O
|
|
net (fo=1, unplaced) 0.449 5.173 u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/u_axi_ram/ext_ram_data1
|
|
r u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/ext_ram_data_IOBUF[31]_inst_i_1/I0
|
|
LUT1 (Prop_lut1_I0_O) 0.124 5.297 f u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/ext_ram_data_IOBUF[31]_inst_i_1/O
|
|
net (fo=32, unplaced) 0.800 6.096 ext_ram_data_IOBUF[18]_inst/T
|
|
AB17 f ext_ram_data_IOBUF[18]_inst/OBUFT/T
|
|
AB17 OBUFT (TriStatE_obuft_T_O)
|
|
3.542 9.638 r ext_ram_data_IOBUF[18]_inst/OBUFT/O
|
|
net (fo=1, unset) 0.000 9.638 ext_ram_data[18]
|
|
AB17 r ext_ram_data[18] (INOUT)
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock sys_clk rise edge) 20.000 20.000 r
|
|
K21 0.000 20.000 r clk (IN)
|
|
net (fo=0) 0.000 20.000 pll_clk.u_clk_pll/inst/clk_in1
|
|
K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I
|
|
K21 IBUF (Prop_ibuf_I_O) 1.393 21.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O
|
|
net (fo=1, unplaced) 0.439 21.832 pll_clk.u_clk_pll/inst/clk_in1_clk_pll
|
|
r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1
|
|
PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1)
|
|
-6.040 15.792 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1
|
|
clock pessimism -0.513 15.279
|
|
clock uncertainty -0.071 15.209
|
|
output delay -0.300 14.909
|
|
-------------------------------------------------------------------
|
|
required time 14.909
|
|
arrival time -9.638
|
|
-------------------------------------------------------------------
|
|
slack 5.270
|
|
|
|
Slack (MET) : 5.271ns (required time - arrival time)
|
|
Source: u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[2]/C
|
|
(rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Destination: base_ram_data[23]
|
|
(output port clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Path Group: sys_clk
|
|
Path Type: Max at Slow Process Corner
|
|
Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns)
|
|
Data Path Delay: 12.663ns (logic 7.322ns (57.824%) route 5.341ns (42.176%))
|
|
Logic Levels: 15 (CARRY4=6 LUT1=1 LUT3=1 LUT4=1 LUT5=1 LUT6=4 OBUFT=1)
|
|
Output Delay: 0.300ns
|
|
Clock Path Skew: -1.695ns (DCD - SCD + CPR)
|
|
Destination Clock Delay (DCD): -4.208ns = ( 15.792 - 20.000 )
|
|
Source Clock Delay (SCD): -3.025ns
|
|
Clock Pessimism Removal (CPR): -0.513ns
|
|
Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Discrete Jitter (DJ): 0.122ns
|
|
Phase Error (PE): 0.000ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock sys_clk rise edge) 0.000 0.000 r
|
|
K21 0.000 0.000 r clk (IN)
|
|
net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1
|
|
K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I
|
|
K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O
|
|
net (fo=1, unplaced) 0.584 2.047 pll_clk.u_clk_pll/inst/clk_in1_clk_pll
|
|
r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1
|
|
PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1)
|
|
-6.768 -4.721 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1
|
|
net (fo=1, unplaced) 0.800 -3.921 pll_clk.u_clk_pll/inst/sys_clk_clk_pll
|
|
r pll_clk.u_clk_pll/inst/clkout2_buf/I
|
|
BUFG (Prop_bufg_I_O) 0.096 -3.825 r pll_clk.u_clk_pll/inst/clkout2_buf/O
|
|
net (fo=10994, unplaced) 0.800 -3.025 u_axi_ram/u_axi_sram_sp/sys_clk
|
|
FDCE r u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[2]/C
|
|
------------------------------------------------------------------- -------------------
|
|
FDCE (Prop_fdce_C_Q) 0.456 -2.569 f u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[2]/Q
|
|
net (fo=56, unplaced) 0.826 -1.743 u_axi_ram/u_axi_sram_sp/len[2]
|
|
f u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6/I1
|
|
LUT4 (Prop_lut4_I1_O) 0.321 -1.422 r u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6/O
|
|
net (fo=4, unplaced) 0.473 -0.949 u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6_n_0
|
|
r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_20/I1
|
|
LUT5 (Prop_lut5_I1_O) 0.124 -0.825 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_20/O
|
|
net (fo=1, unplaced) 0.449 -0.376 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_20_n_0
|
|
r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_19/I5
|
|
LUT6 (Prop_lut6_I5_O) 0.124 -0.252 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_19/O
|
|
net (fo=1, unplaced) 0.000 -0.252 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_19_n_0
|
|
r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/S[0]
|
|
CARRY4 (Prop_carry4_S[0]_CO[3])
|
|
0.532 0.280 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/CO[3]
|
|
net (fo=1, unplaced) 0.000 0.280 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10_n_0
|
|
r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CI
|
|
CARRY4 (Prop_carry4_CI_CO[3])
|
|
0.114 0.394 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CO[3]
|
|
net (fo=1, unplaced) 0.000 0.394 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9_n_0
|
|
r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/CI
|
|
CARRY4 (Prop_carry4_CI_CO[3])
|
|
0.114 0.508 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/CO[3]
|
|
net (fo=1, unplaced) 0.000 0.508 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11_n_0
|
|
r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_10/CI
|
|
CARRY4 (Prop_carry4_CI_CO[3])
|
|
0.114 0.622 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_10/CO[3]
|
|
net (fo=1, unplaced) 0.000 0.622 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_10_n_0
|
|
r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2_i_9/CI
|
|
CARRY4 (Prop_carry4_CI_O[3])
|
|
0.329 0.951 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2_i_9/O[3]
|
|
net (fo=3, unplaced) 0.826 1.777 u_axi_ram/u_axi_sram_sp/upper_wrap_boundary[29]
|
|
r u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1_i_2/I0
|
|
LUT6 (Prop_lut6_I0_O) 0.307 2.084 r u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1_i_2/O
|
|
net (fo=1, unplaced) 0.000 2.084 u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1_i_2_n_0
|
|
r u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1/S[1]
|
|
CARRY4 (Prop_carry4_S[1]_CO[2])
|
|
0.570 2.654 r u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1/CO[2]
|
|
net (fo=23, unplaced) 0.515 3.169 u_axi_ram/u_axi_sram_sp/req_addr_d10_in
|
|
r u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/I5
|
|
LUT6 (Prop_lut6_I5_O) 0.310 3.479 f u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/O
|
|
net (fo=2, unplaced) 0.460 3.939 u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7_n_0
|
|
f u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/I1
|
|
LUT6 (Prop_lut6_I1_O) 0.124 4.063 f u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/O
|
|
net (fo=80, unplaced) 0.543 4.606 u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/soc_sram_addr[0]
|
|
f u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/base_ram_data_IOBUF[31]_inst_i_3/I2
|
|
LUT3 (Prop_lut3_I2_O) 0.124 4.730 r u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/base_ram_data_IOBUF[31]_inst_i_3/O
|
|
net (fo=1, unplaced) 0.449 5.179 u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/u_axi_ram/base_ram_data1
|
|
r u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/base_ram_data_IOBUF[31]_inst_i_2/I0
|
|
LUT1 (Prop_lut1_I0_O) 0.124 5.303 f u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/base_ram_data_IOBUF[31]_inst_i_2/O
|
|
net (fo=32, unplaced) 0.800 6.102 base_ram_data_IOBUF[23]_inst/T
|
|
N21 f base_ram_data_IOBUF[23]_inst/OBUFT/T
|
|
N21 OBUFT (TriStatE_obuft_T_O)
|
|
3.535 9.638 r base_ram_data_IOBUF[23]_inst/OBUFT/O
|
|
net (fo=1, unset) 0.000 9.638 base_ram_data[23]
|
|
N21 r base_ram_data[23] (INOUT)
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock sys_clk rise edge) 20.000 20.000 r
|
|
K21 0.000 20.000 r clk (IN)
|
|
net (fo=0) 0.000 20.000 pll_clk.u_clk_pll/inst/clk_in1
|
|
K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I
|
|
K21 IBUF (Prop_ibuf_I_O) 1.393 21.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O
|
|
net (fo=1, unplaced) 0.439 21.832 pll_clk.u_clk_pll/inst/clk_in1_clk_pll
|
|
r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1
|
|
PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1)
|
|
-6.040 15.792 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1
|
|
clock pessimism -0.513 15.279
|
|
clock uncertainty -0.071 15.209
|
|
output delay -0.300 14.909
|
|
-------------------------------------------------------------------
|
|
required time 14.909
|
|
arrival time -9.638
|
|
-------------------------------------------------------------------
|
|
slack 5.271
|
|
|
|
Slack (MET) : 5.272ns (required time - arrival time)
|
|
Source: u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[2]/C
|
|
(rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Destination: base_ram_data[15]
|
|
(output port clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Path Group: sys_clk
|
|
Path Type: Max at Slow Process Corner
|
|
Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns)
|
|
Data Path Delay: 12.662ns (logic 7.321ns (57.821%) route 5.341ns (42.179%))
|
|
Logic Levels: 15 (CARRY4=6 LUT1=1 LUT3=1 LUT4=1 LUT5=1 LUT6=4 OBUFT=1)
|
|
Output Delay: 0.300ns
|
|
Clock Path Skew: -1.695ns (DCD - SCD + CPR)
|
|
Destination Clock Delay (DCD): -4.208ns = ( 15.792 - 20.000 )
|
|
Source Clock Delay (SCD): -3.025ns
|
|
Clock Pessimism Removal (CPR): -0.513ns
|
|
Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Discrete Jitter (DJ): 0.122ns
|
|
Phase Error (PE): 0.000ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock sys_clk rise edge) 0.000 0.000 r
|
|
K21 0.000 0.000 r clk (IN)
|
|
net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1
|
|
K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I
|
|
K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O
|
|
net (fo=1, unplaced) 0.584 2.047 pll_clk.u_clk_pll/inst/clk_in1_clk_pll
|
|
r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1
|
|
PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1)
|
|
-6.768 -4.721 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1
|
|
net (fo=1, unplaced) 0.800 -3.921 pll_clk.u_clk_pll/inst/sys_clk_clk_pll
|
|
r pll_clk.u_clk_pll/inst/clkout2_buf/I
|
|
BUFG (Prop_bufg_I_O) 0.096 -3.825 r pll_clk.u_clk_pll/inst/clkout2_buf/O
|
|
net (fo=10994, unplaced) 0.800 -3.025 u_axi_ram/u_axi_sram_sp/sys_clk
|
|
FDCE r u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[2]/C
|
|
------------------------------------------------------------------- -------------------
|
|
FDCE (Prop_fdce_C_Q) 0.456 -2.569 f u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[2]/Q
|
|
net (fo=56, unplaced) 0.826 -1.743 u_axi_ram/u_axi_sram_sp/len[2]
|
|
f u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6/I1
|
|
LUT4 (Prop_lut4_I1_O) 0.321 -1.422 r u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6/O
|
|
net (fo=4, unplaced) 0.473 -0.949 u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6_n_0
|
|
r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_20/I1
|
|
LUT5 (Prop_lut5_I1_O) 0.124 -0.825 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_20/O
|
|
net (fo=1, unplaced) 0.449 -0.376 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_20_n_0
|
|
r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_19/I5
|
|
LUT6 (Prop_lut6_I5_O) 0.124 -0.252 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_19/O
|
|
net (fo=1, unplaced) 0.000 -0.252 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_19_n_0
|
|
r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/S[0]
|
|
CARRY4 (Prop_carry4_S[0]_CO[3])
|
|
0.532 0.280 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/CO[3]
|
|
net (fo=1, unplaced) 0.000 0.280 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10_n_0
|
|
r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CI
|
|
CARRY4 (Prop_carry4_CI_CO[3])
|
|
0.114 0.394 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CO[3]
|
|
net (fo=1, unplaced) 0.000 0.394 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9_n_0
|
|
r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/CI
|
|
CARRY4 (Prop_carry4_CI_CO[3])
|
|
0.114 0.508 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/CO[3]
|
|
net (fo=1, unplaced) 0.000 0.508 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11_n_0
|
|
r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_10/CI
|
|
CARRY4 (Prop_carry4_CI_CO[3])
|
|
0.114 0.622 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_10/CO[3]
|
|
net (fo=1, unplaced) 0.000 0.622 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_10_n_0
|
|
r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2_i_9/CI
|
|
CARRY4 (Prop_carry4_CI_O[3])
|
|
0.329 0.951 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2_i_9/O[3]
|
|
net (fo=3, unplaced) 0.826 1.777 u_axi_ram/u_axi_sram_sp/upper_wrap_boundary[29]
|
|
r u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1_i_2/I0
|
|
LUT6 (Prop_lut6_I0_O) 0.307 2.084 r u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1_i_2/O
|
|
net (fo=1, unplaced) 0.000 2.084 u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1_i_2_n_0
|
|
r u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1/S[1]
|
|
CARRY4 (Prop_carry4_S[1]_CO[2])
|
|
0.570 2.654 r u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1/CO[2]
|
|
net (fo=23, unplaced) 0.515 3.169 u_axi_ram/u_axi_sram_sp/req_addr_d10_in
|
|
r u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/I5
|
|
LUT6 (Prop_lut6_I5_O) 0.310 3.479 f u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/O
|
|
net (fo=2, unplaced) 0.460 3.939 u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7_n_0
|
|
f u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/I1
|
|
LUT6 (Prop_lut6_I1_O) 0.124 4.063 f u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/O
|
|
net (fo=80, unplaced) 0.543 4.606 u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/soc_sram_addr[0]
|
|
f u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/base_ram_data_IOBUF[31]_inst_i_3/I2
|
|
LUT3 (Prop_lut3_I2_O) 0.124 4.730 r u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/base_ram_data_IOBUF[31]_inst_i_3/O
|
|
net (fo=1, unplaced) 0.449 5.179 u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/u_axi_ram/base_ram_data1
|
|
r u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/base_ram_data_IOBUF[31]_inst_i_2/I0
|
|
LUT1 (Prop_lut1_I0_O) 0.124 5.303 f u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/base_ram_data_IOBUF[31]_inst_i_2/O
|
|
net (fo=32, unplaced) 0.800 6.102 base_ram_data_IOBUF[15]_inst/T
|
|
U21 f base_ram_data_IOBUF[15]_inst/OBUFT/T
|
|
U21 OBUFT (TriStatE_obuft_T_O)
|
|
3.534 9.637 r base_ram_data_IOBUF[15]_inst/OBUFT/O
|
|
net (fo=1, unset) 0.000 9.637 base_ram_data[15]
|
|
U21 r base_ram_data[15] (INOUT)
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock sys_clk rise edge) 20.000 20.000 r
|
|
K21 0.000 20.000 r clk (IN)
|
|
net (fo=0) 0.000 20.000 pll_clk.u_clk_pll/inst/clk_in1
|
|
K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I
|
|
K21 IBUF (Prop_ibuf_I_O) 1.393 21.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O
|
|
net (fo=1, unplaced) 0.439 21.832 pll_clk.u_clk_pll/inst/clk_in1_clk_pll
|
|
r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1
|
|
PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1)
|
|
-6.040 15.792 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1
|
|
clock pessimism -0.513 15.279
|
|
clock uncertainty -0.071 15.209
|
|
output delay -0.300 14.909
|
|
-------------------------------------------------------------------
|
|
required time 14.909
|
|
arrival time -9.637
|
|
-------------------------------------------------------------------
|
|
slack 5.272
|
|
|
|
Slack (MET) : 5.273ns (required time - arrival time)
|
|
Source: u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[2]/C
|
|
(rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Destination: base_ram_data[26]
|
|
(output port clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Path Group: sys_clk
|
|
Path Type: Max at Slow Process Corner
|
|
Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns)
|
|
Data Path Delay: 12.661ns (logic 7.320ns (57.816%) route 5.341ns (42.184%))
|
|
Logic Levels: 15 (CARRY4=6 LUT1=1 LUT3=1 LUT4=1 LUT5=1 LUT6=4 OBUFT=1)
|
|
Output Delay: 0.300ns
|
|
Clock Path Skew: -1.695ns (DCD - SCD + CPR)
|
|
Destination Clock Delay (DCD): -4.208ns = ( 15.792 - 20.000 )
|
|
Source Clock Delay (SCD): -3.025ns
|
|
Clock Pessimism Removal (CPR): -0.513ns
|
|
Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Discrete Jitter (DJ): 0.122ns
|
|
Phase Error (PE): 0.000ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock sys_clk rise edge) 0.000 0.000 r
|
|
K21 0.000 0.000 r clk (IN)
|
|
net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1
|
|
K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I
|
|
K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O
|
|
net (fo=1, unplaced) 0.584 2.047 pll_clk.u_clk_pll/inst/clk_in1_clk_pll
|
|
r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1
|
|
PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1)
|
|
-6.768 -4.721 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1
|
|
net (fo=1, unplaced) 0.800 -3.921 pll_clk.u_clk_pll/inst/sys_clk_clk_pll
|
|
r pll_clk.u_clk_pll/inst/clkout2_buf/I
|
|
BUFG (Prop_bufg_I_O) 0.096 -3.825 r pll_clk.u_clk_pll/inst/clkout2_buf/O
|
|
net (fo=10994, unplaced) 0.800 -3.025 u_axi_ram/u_axi_sram_sp/sys_clk
|
|
FDCE r u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[2]/C
|
|
------------------------------------------------------------------- -------------------
|
|
FDCE (Prop_fdce_C_Q) 0.456 -2.569 f u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[2]/Q
|
|
net (fo=56, unplaced) 0.826 -1.743 u_axi_ram/u_axi_sram_sp/len[2]
|
|
f u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6/I1
|
|
LUT4 (Prop_lut4_I1_O) 0.321 -1.422 r u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6/O
|
|
net (fo=4, unplaced) 0.473 -0.949 u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6_n_0
|
|
r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_20/I1
|
|
LUT5 (Prop_lut5_I1_O) 0.124 -0.825 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_20/O
|
|
net (fo=1, unplaced) 0.449 -0.376 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_20_n_0
|
|
r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_19/I5
|
|
LUT6 (Prop_lut6_I5_O) 0.124 -0.252 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_19/O
|
|
net (fo=1, unplaced) 0.000 -0.252 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_19_n_0
|
|
r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/S[0]
|
|
CARRY4 (Prop_carry4_S[0]_CO[3])
|
|
0.532 0.280 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/CO[3]
|
|
net (fo=1, unplaced) 0.000 0.280 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10_n_0
|
|
r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CI
|
|
CARRY4 (Prop_carry4_CI_CO[3])
|
|
0.114 0.394 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CO[3]
|
|
net (fo=1, unplaced) 0.000 0.394 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9_n_0
|
|
r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/CI
|
|
CARRY4 (Prop_carry4_CI_CO[3])
|
|
0.114 0.508 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/CO[3]
|
|
net (fo=1, unplaced) 0.000 0.508 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11_n_0
|
|
r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_10/CI
|
|
CARRY4 (Prop_carry4_CI_CO[3])
|
|
0.114 0.622 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_10/CO[3]
|
|
net (fo=1, unplaced) 0.000 0.622 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_10_n_0
|
|
r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2_i_9/CI
|
|
CARRY4 (Prop_carry4_CI_O[3])
|
|
0.329 0.951 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2_i_9/O[3]
|
|
net (fo=3, unplaced) 0.826 1.777 u_axi_ram/u_axi_sram_sp/upper_wrap_boundary[29]
|
|
r u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1_i_2/I0
|
|
LUT6 (Prop_lut6_I0_O) 0.307 2.084 r u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1_i_2/O
|
|
net (fo=1, unplaced) 0.000 2.084 u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1_i_2_n_0
|
|
r u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1/S[1]
|
|
CARRY4 (Prop_carry4_S[1]_CO[2])
|
|
0.570 2.654 r u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1/CO[2]
|
|
net (fo=23, unplaced) 0.515 3.169 u_axi_ram/u_axi_sram_sp/req_addr_d10_in
|
|
r u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/I5
|
|
LUT6 (Prop_lut6_I5_O) 0.310 3.479 f u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/O
|
|
net (fo=2, unplaced) 0.460 3.939 u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7_n_0
|
|
f u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/I1
|
|
LUT6 (Prop_lut6_I1_O) 0.124 4.063 f u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/O
|
|
net (fo=80, unplaced) 0.543 4.606 u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/soc_sram_addr[0]
|
|
f u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/base_ram_data_IOBUF[31]_inst_i_3/I2
|
|
LUT3 (Prop_lut3_I2_O) 0.124 4.730 r u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/base_ram_data_IOBUF[31]_inst_i_3/O
|
|
net (fo=1, unplaced) 0.449 5.179 u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/u_axi_ram/base_ram_data1
|
|
r u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/base_ram_data_IOBUF[31]_inst_i_2/I0
|
|
LUT1 (Prop_lut1_I0_O) 0.124 5.303 f u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/base_ram_data_IOBUF[31]_inst_i_2/O
|
|
net (fo=32, unplaced) 0.800 6.102 base_ram_data_IOBUF[26]_inst/T
|
|
R21 f base_ram_data_IOBUF[26]_inst/OBUFT/T
|
|
R21 OBUFT (TriStatE_obuft_T_O)
|
|
3.533 9.635 r base_ram_data_IOBUF[26]_inst/OBUFT/O
|
|
net (fo=1, unset) 0.000 9.635 base_ram_data[26]
|
|
R21 r base_ram_data[26] (INOUT)
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock sys_clk rise edge) 20.000 20.000 r
|
|
K21 0.000 20.000 r clk (IN)
|
|
net (fo=0) 0.000 20.000 pll_clk.u_clk_pll/inst/clk_in1
|
|
K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I
|
|
K21 IBUF (Prop_ibuf_I_O) 1.393 21.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O
|
|
net (fo=1, unplaced) 0.439 21.832 pll_clk.u_clk_pll/inst/clk_in1_clk_pll
|
|
r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1
|
|
PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1)
|
|
-6.040 15.792 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1
|
|
clock pessimism -0.513 15.279
|
|
clock uncertainty -0.071 15.209
|
|
output delay -0.300 14.909
|
|
-------------------------------------------------------------------
|
|
required time 14.909
|
|
arrival time -9.635
|
|
-------------------------------------------------------------------
|
|
slack 5.273
|
|
|
|
Slack (MET) : 5.276ns (required time - arrival time)
|
|
Source: u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[2]/C
|
|
(rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Destination: ext_ram_data[16]
|
|
(output port clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Path Group: sys_clk
|
|
Path Type: Max at Slow Process Corner
|
|
Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns)
|
|
Data Path Delay: 12.658ns (logic 7.317ns (57.808%) route 5.341ns (42.192%))
|
|
Logic Levels: 15 (CARRY4=6 LUT1=1 LUT3=1 LUT4=1 LUT5=1 LUT6=4 OBUFT=1)
|
|
Output Delay: 0.300ns
|
|
Clock Path Skew: -1.695ns (DCD - SCD + CPR)
|
|
Destination Clock Delay (DCD): -4.208ns = ( 15.792 - 20.000 )
|
|
Source Clock Delay (SCD): -3.025ns
|
|
Clock Pessimism Removal (CPR): -0.513ns
|
|
Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Discrete Jitter (DJ): 0.122ns
|
|
Phase Error (PE): 0.000ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock sys_clk rise edge) 0.000 0.000 r
|
|
K21 0.000 0.000 r clk (IN)
|
|
net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1
|
|
K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I
|
|
K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O
|
|
net (fo=1, unplaced) 0.584 2.047 pll_clk.u_clk_pll/inst/clk_in1_clk_pll
|
|
r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1
|
|
PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1)
|
|
-6.768 -4.721 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1
|
|
net (fo=1, unplaced) 0.800 -3.921 pll_clk.u_clk_pll/inst/sys_clk_clk_pll
|
|
r pll_clk.u_clk_pll/inst/clkout2_buf/I
|
|
BUFG (Prop_bufg_I_O) 0.096 -3.825 r pll_clk.u_clk_pll/inst/clkout2_buf/O
|
|
net (fo=10994, unplaced) 0.800 -3.025 u_axi_ram/u_axi_sram_sp/sys_clk
|
|
FDCE r u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[2]/C
|
|
------------------------------------------------------------------- -------------------
|
|
FDCE (Prop_fdce_C_Q) 0.456 -2.569 f u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[2]/Q
|
|
net (fo=56, unplaced) 0.826 -1.743 u_axi_ram/u_axi_sram_sp/len[2]
|
|
f u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6/I1
|
|
LUT4 (Prop_lut4_I1_O) 0.321 -1.422 r u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6/O
|
|
net (fo=4, unplaced) 0.473 -0.949 u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6_n_0
|
|
r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_20/I1
|
|
LUT5 (Prop_lut5_I1_O) 0.124 -0.825 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_20/O
|
|
net (fo=1, unplaced) 0.449 -0.376 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_20_n_0
|
|
r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_19/I5
|
|
LUT6 (Prop_lut6_I5_O) 0.124 -0.252 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_19/O
|
|
net (fo=1, unplaced) 0.000 -0.252 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_19_n_0
|
|
r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/S[0]
|
|
CARRY4 (Prop_carry4_S[0]_CO[3])
|
|
0.532 0.280 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/CO[3]
|
|
net (fo=1, unplaced) 0.000 0.280 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10_n_0
|
|
r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CI
|
|
CARRY4 (Prop_carry4_CI_CO[3])
|
|
0.114 0.394 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CO[3]
|
|
net (fo=1, unplaced) 0.000 0.394 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9_n_0
|
|
r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/CI
|
|
CARRY4 (Prop_carry4_CI_CO[3])
|
|
0.114 0.508 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/CO[3]
|
|
net (fo=1, unplaced) 0.000 0.508 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11_n_0
|
|
r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_10/CI
|
|
CARRY4 (Prop_carry4_CI_CO[3])
|
|
0.114 0.622 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_10/CO[3]
|
|
net (fo=1, unplaced) 0.000 0.622 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_10_n_0
|
|
r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2_i_9/CI
|
|
CARRY4 (Prop_carry4_CI_O[3])
|
|
0.329 0.951 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2_i_9/O[3]
|
|
net (fo=3, unplaced) 0.826 1.777 u_axi_ram/u_axi_sram_sp/upper_wrap_boundary[29]
|
|
r u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1_i_2/I0
|
|
LUT6 (Prop_lut6_I0_O) 0.307 2.084 r u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1_i_2/O
|
|
net (fo=1, unplaced) 0.000 2.084 u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1_i_2_n_0
|
|
r u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1/S[1]
|
|
CARRY4 (Prop_carry4_S[1]_CO[2])
|
|
0.570 2.654 r u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1/CO[2]
|
|
net (fo=23, unplaced) 0.515 3.169 u_axi_ram/u_axi_sram_sp/req_addr_d10_in
|
|
r u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/I5
|
|
LUT6 (Prop_lut6_I5_O) 0.310 3.479 r u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/O
|
|
net (fo=2, unplaced) 0.460 3.939 u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7_n_0
|
|
r u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/I1
|
|
LUT6 (Prop_lut6_I1_O) 0.124 4.063 r u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/O
|
|
net (fo=80, unplaced) 0.543 4.606 u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/soc_sram_addr[0]
|
|
r u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/ext_ram_data_IOBUF[31]_inst_i_2/I2
|
|
LUT3 (Prop_lut3_I2_O) 0.118 4.724 r u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/ext_ram_data_IOBUF[31]_inst_i_2/O
|
|
net (fo=1, unplaced) 0.449 5.173 u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/u_axi_ram/ext_ram_data1
|
|
r u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/ext_ram_data_IOBUF[31]_inst_i_1/I0
|
|
LUT1 (Prop_lut1_I0_O) 0.124 5.297 f u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/ext_ram_data_IOBUF[31]_inst_i_1/O
|
|
net (fo=32, unplaced) 0.800 6.096 ext_ram_data_IOBUF[16]_inst/T
|
|
AB16 f ext_ram_data_IOBUF[16]_inst/OBUFT/T
|
|
AB16 OBUFT (TriStatE_obuft_T_O)
|
|
3.536 9.633 r ext_ram_data_IOBUF[16]_inst/OBUFT/O
|
|
net (fo=1, unset) 0.000 9.633 ext_ram_data[16]
|
|
AB16 r ext_ram_data[16] (INOUT)
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock sys_clk rise edge) 20.000 20.000 r
|
|
K21 0.000 20.000 r clk (IN)
|
|
net (fo=0) 0.000 20.000 pll_clk.u_clk_pll/inst/clk_in1
|
|
K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I
|
|
K21 IBUF (Prop_ibuf_I_O) 1.393 21.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O
|
|
net (fo=1, unplaced) 0.439 21.832 pll_clk.u_clk_pll/inst/clk_in1_clk_pll
|
|
r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1
|
|
PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1)
|
|
-6.040 15.792 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1
|
|
clock pessimism -0.513 15.279
|
|
clock uncertainty -0.071 15.209
|
|
output delay -0.300 14.909
|
|
-------------------------------------------------------------------
|
|
required time 14.909
|
|
arrival time -9.633
|
|
-------------------------------------------------------------------
|
|
slack 5.276
|
|
|
|
Slack (MET) : 5.279ns (required time - arrival time)
|
|
Source: u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[2]/C
|
|
(rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Destination: base_ram_data[16]
|
|
(output port clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Path Group: sys_clk
|
|
Path Type: Max at Slow Process Corner
|
|
Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns)
|
|
Data Path Delay: 12.655ns (logic 7.314ns (57.798%) route 5.341ns (42.202%))
|
|
Logic Levels: 15 (CARRY4=6 LUT1=1 LUT3=1 LUT4=1 LUT5=1 LUT6=4 OBUFT=1)
|
|
Output Delay: 0.300ns
|
|
Clock Path Skew: -1.695ns (DCD - SCD + CPR)
|
|
Destination Clock Delay (DCD): -4.208ns = ( 15.792 - 20.000 )
|
|
Source Clock Delay (SCD): -3.025ns
|
|
Clock Pessimism Removal (CPR): -0.513ns
|
|
Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Discrete Jitter (DJ): 0.122ns
|
|
Phase Error (PE): 0.000ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock sys_clk rise edge) 0.000 0.000 r
|
|
K21 0.000 0.000 r clk (IN)
|
|
net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1
|
|
K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I
|
|
K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O
|
|
net (fo=1, unplaced) 0.584 2.047 pll_clk.u_clk_pll/inst/clk_in1_clk_pll
|
|
r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1
|
|
PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1)
|
|
-6.768 -4.721 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1
|
|
net (fo=1, unplaced) 0.800 -3.921 pll_clk.u_clk_pll/inst/sys_clk_clk_pll
|
|
r pll_clk.u_clk_pll/inst/clkout2_buf/I
|
|
BUFG (Prop_bufg_I_O) 0.096 -3.825 r pll_clk.u_clk_pll/inst/clkout2_buf/O
|
|
net (fo=10994, unplaced) 0.800 -3.025 u_axi_ram/u_axi_sram_sp/sys_clk
|
|
FDCE r u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[2]/C
|
|
------------------------------------------------------------------- -------------------
|
|
FDCE (Prop_fdce_C_Q) 0.456 -2.569 f u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[2]/Q
|
|
net (fo=56, unplaced) 0.826 -1.743 u_axi_ram/u_axi_sram_sp/len[2]
|
|
f u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6/I1
|
|
LUT4 (Prop_lut4_I1_O) 0.321 -1.422 r u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6/O
|
|
net (fo=4, unplaced) 0.473 -0.949 u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6_n_0
|
|
r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_20/I1
|
|
LUT5 (Prop_lut5_I1_O) 0.124 -0.825 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_20/O
|
|
net (fo=1, unplaced) 0.449 -0.376 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_20_n_0
|
|
r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_19/I5
|
|
LUT6 (Prop_lut6_I5_O) 0.124 -0.252 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_19/O
|
|
net (fo=1, unplaced) 0.000 -0.252 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_19_n_0
|
|
r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/S[0]
|
|
CARRY4 (Prop_carry4_S[0]_CO[3])
|
|
0.532 0.280 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/CO[3]
|
|
net (fo=1, unplaced) 0.000 0.280 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10_n_0
|
|
r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CI
|
|
CARRY4 (Prop_carry4_CI_CO[3])
|
|
0.114 0.394 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CO[3]
|
|
net (fo=1, unplaced) 0.000 0.394 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9_n_0
|
|
r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/CI
|
|
CARRY4 (Prop_carry4_CI_CO[3])
|
|
0.114 0.508 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/CO[3]
|
|
net (fo=1, unplaced) 0.000 0.508 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11_n_0
|
|
r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_10/CI
|
|
CARRY4 (Prop_carry4_CI_CO[3])
|
|
0.114 0.622 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_10/CO[3]
|
|
net (fo=1, unplaced) 0.000 0.622 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_10_n_0
|
|
r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2_i_9/CI
|
|
CARRY4 (Prop_carry4_CI_O[3])
|
|
0.329 0.951 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2_i_9/O[3]
|
|
net (fo=3, unplaced) 0.826 1.777 u_axi_ram/u_axi_sram_sp/upper_wrap_boundary[29]
|
|
r u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1_i_2/I0
|
|
LUT6 (Prop_lut6_I0_O) 0.307 2.084 r u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1_i_2/O
|
|
net (fo=1, unplaced) 0.000 2.084 u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1_i_2_n_0
|
|
r u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1/S[1]
|
|
CARRY4 (Prop_carry4_S[1]_CO[2])
|
|
0.570 2.654 r u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1/CO[2]
|
|
net (fo=23, unplaced) 0.515 3.169 u_axi_ram/u_axi_sram_sp/req_addr_d10_in
|
|
r u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/I5
|
|
LUT6 (Prop_lut6_I5_O) 0.310 3.479 f u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/O
|
|
net (fo=2, unplaced) 0.460 3.939 u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7_n_0
|
|
f u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/I1
|
|
LUT6 (Prop_lut6_I1_O) 0.124 4.063 f u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/O
|
|
net (fo=80, unplaced) 0.543 4.606 u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/soc_sram_addr[0]
|
|
f u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/base_ram_data_IOBUF[31]_inst_i_3/I2
|
|
LUT3 (Prop_lut3_I2_O) 0.124 4.730 r u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/base_ram_data_IOBUF[31]_inst_i_3/O
|
|
net (fo=1, unplaced) 0.449 5.179 u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/u_axi_ram/base_ram_data1
|
|
r u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/base_ram_data_IOBUF[31]_inst_i_2/I0
|
|
LUT1 (Prop_lut1_I0_O) 0.124 5.303 f u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/base_ram_data_IOBUF[31]_inst_i_2/O
|
|
net (fo=32, unplaced) 0.800 6.102 base_ram_data_IOBUF[16]_inst/T
|
|
P21 f base_ram_data_IOBUF[16]_inst/OBUFT/T
|
|
P21 OBUFT (TriStatE_obuft_T_O)
|
|
3.527 9.630 r base_ram_data_IOBUF[16]_inst/OBUFT/O
|
|
net (fo=1, unset) 0.000 9.630 base_ram_data[16]
|
|
P21 r base_ram_data[16] (INOUT)
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock sys_clk rise edge) 20.000 20.000 r
|
|
K21 0.000 20.000 r clk (IN)
|
|
net (fo=0) 0.000 20.000 pll_clk.u_clk_pll/inst/clk_in1
|
|
K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I
|
|
K21 IBUF (Prop_ibuf_I_O) 1.393 21.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O
|
|
net (fo=1, unplaced) 0.439 21.832 pll_clk.u_clk_pll/inst/clk_in1_clk_pll
|
|
r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1
|
|
PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1)
|
|
-6.040 15.792 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1
|
|
clock pessimism -0.513 15.279
|
|
clock uncertainty -0.071 15.209
|
|
output delay -0.300 14.909
|
|
-------------------------------------------------------------------
|
|
required time 14.909
|
|
arrival time -9.630
|
|
-------------------------------------------------------------------
|
|
slack 5.279
|
|
|
|
Slack (MET) : 5.284ns (required time - arrival time)
|
|
Source: u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[2]/C
|
|
(rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Destination: base_ram_data[27]
|
|
(output port clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Path Group: sys_clk
|
|
Path Type: Max at Slow Process Corner
|
|
Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns)
|
|
Data Path Delay: 12.650ns (logic 7.310ns (57.782%) route 5.341ns (42.218%))
|
|
Logic Levels: 15 (CARRY4=6 LUT1=1 LUT3=1 LUT4=1 LUT5=1 LUT6=4 OBUFT=1)
|
|
Output Delay: 0.300ns
|
|
Clock Path Skew: -1.695ns (DCD - SCD + CPR)
|
|
Destination Clock Delay (DCD): -4.208ns = ( 15.792 - 20.000 )
|
|
Source Clock Delay (SCD): -3.025ns
|
|
Clock Pessimism Removal (CPR): -0.513ns
|
|
Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Discrete Jitter (DJ): 0.122ns
|
|
Phase Error (PE): 0.000ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock sys_clk rise edge) 0.000 0.000 r
|
|
K21 0.000 0.000 r clk (IN)
|
|
net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1
|
|
K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I
|
|
K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O
|
|
net (fo=1, unplaced) 0.584 2.047 pll_clk.u_clk_pll/inst/clk_in1_clk_pll
|
|
r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1
|
|
PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1)
|
|
-6.768 -4.721 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1
|
|
net (fo=1, unplaced) 0.800 -3.921 pll_clk.u_clk_pll/inst/sys_clk_clk_pll
|
|
r pll_clk.u_clk_pll/inst/clkout2_buf/I
|
|
BUFG (Prop_bufg_I_O) 0.096 -3.825 r pll_clk.u_clk_pll/inst/clkout2_buf/O
|
|
net (fo=10994, unplaced) 0.800 -3.025 u_axi_ram/u_axi_sram_sp/sys_clk
|
|
FDCE r u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[2]/C
|
|
------------------------------------------------------------------- -------------------
|
|
FDCE (Prop_fdce_C_Q) 0.456 -2.569 f u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[2]/Q
|
|
net (fo=56, unplaced) 0.826 -1.743 u_axi_ram/u_axi_sram_sp/len[2]
|
|
f u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6/I1
|
|
LUT4 (Prop_lut4_I1_O) 0.321 -1.422 r u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6/O
|
|
net (fo=4, unplaced) 0.473 -0.949 u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6_n_0
|
|
r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_20/I1
|
|
LUT5 (Prop_lut5_I1_O) 0.124 -0.825 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_20/O
|
|
net (fo=1, unplaced) 0.449 -0.376 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_20_n_0
|
|
r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_19/I5
|
|
LUT6 (Prop_lut6_I5_O) 0.124 -0.252 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_19/O
|
|
net (fo=1, unplaced) 0.000 -0.252 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_19_n_0
|
|
r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/S[0]
|
|
CARRY4 (Prop_carry4_S[0]_CO[3])
|
|
0.532 0.280 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/CO[3]
|
|
net (fo=1, unplaced) 0.000 0.280 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10_n_0
|
|
r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CI
|
|
CARRY4 (Prop_carry4_CI_CO[3])
|
|
0.114 0.394 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CO[3]
|
|
net (fo=1, unplaced) 0.000 0.394 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9_n_0
|
|
r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/CI
|
|
CARRY4 (Prop_carry4_CI_CO[3])
|
|
0.114 0.508 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/CO[3]
|
|
net (fo=1, unplaced) 0.000 0.508 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11_n_0
|
|
r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_10/CI
|
|
CARRY4 (Prop_carry4_CI_CO[3])
|
|
0.114 0.622 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_10/CO[3]
|
|
net (fo=1, unplaced) 0.000 0.622 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_10_n_0
|
|
r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2_i_9/CI
|
|
CARRY4 (Prop_carry4_CI_O[3])
|
|
0.329 0.951 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2_i_9/O[3]
|
|
net (fo=3, unplaced) 0.826 1.777 u_axi_ram/u_axi_sram_sp/upper_wrap_boundary[29]
|
|
r u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1_i_2/I0
|
|
LUT6 (Prop_lut6_I0_O) 0.307 2.084 r u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1_i_2/O
|
|
net (fo=1, unplaced) 0.000 2.084 u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1_i_2_n_0
|
|
r u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1/S[1]
|
|
CARRY4 (Prop_carry4_S[1]_CO[2])
|
|
0.570 2.654 r u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1/CO[2]
|
|
net (fo=23, unplaced) 0.515 3.169 u_axi_ram/u_axi_sram_sp/req_addr_d10_in
|
|
r u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/I5
|
|
LUT6 (Prop_lut6_I5_O) 0.310 3.479 f u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/O
|
|
net (fo=2, unplaced) 0.460 3.939 u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7_n_0
|
|
f u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/I1
|
|
LUT6 (Prop_lut6_I1_O) 0.124 4.063 f u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/O
|
|
net (fo=80, unplaced) 0.543 4.606 u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/soc_sram_addr[0]
|
|
f u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/base_ram_data_IOBUF[31]_inst_i_3/I2
|
|
LUT3 (Prop_lut3_I2_O) 0.124 4.730 r u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/base_ram_data_IOBUF[31]_inst_i_3/O
|
|
net (fo=1, unplaced) 0.449 5.179 u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/u_axi_ram/base_ram_data1
|
|
r u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/base_ram_data_IOBUF[31]_inst_i_2/I0
|
|
LUT1 (Prop_lut1_I0_O) 0.124 5.303 f u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/base_ram_data_IOBUF[31]_inst_i_2/O
|
|
net (fo=32, unplaced) 0.800 6.102 base_ram_data_IOBUF[27]_inst/T
|
|
P20 f base_ram_data_IOBUF[27]_inst/OBUFT/T
|
|
P20 OBUFT (TriStatE_obuft_T_O)
|
|
3.523 9.625 r base_ram_data_IOBUF[27]_inst/OBUFT/O
|
|
net (fo=1, unset) 0.000 9.625 base_ram_data[27]
|
|
P20 r base_ram_data[27] (INOUT)
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock sys_clk rise edge) 20.000 20.000 r
|
|
K21 0.000 20.000 r clk (IN)
|
|
net (fo=0) 0.000 20.000 pll_clk.u_clk_pll/inst/clk_in1
|
|
K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I
|
|
K21 IBUF (Prop_ibuf_I_O) 1.393 21.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O
|
|
net (fo=1, unplaced) 0.439 21.832 pll_clk.u_clk_pll/inst/clk_in1_clk_pll
|
|
r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1
|
|
PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1)
|
|
-6.040 15.792 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1
|
|
clock pessimism -0.513 15.279
|
|
clock uncertainty -0.071 15.209
|
|
output delay -0.300 14.909
|
|
-------------------------------------------------------------------
|
|
required time 14.909
|
|
arrival time -9.625
|
|
-------------------------------------------------------------------
|
|
slack 5.284
|
|
|
|
Slack (MET) : 5.289ns (required time - arrival time)
|
|
Source: u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[2]/C
|
|
(rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Destination: base_ram_data[19]
|
|
(output port clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Path Group: sys_clk
|
|
Path Type: Max at Slow Process Corner
|
|
Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns)
|
|
Data Path Delay: 12.645ns (logic 7.305ns (57.765%) route 5.341ns (42.235%))
|
|
Logic Levels: 15 (CARRY4=6 LUT1=1 LUT3=1 LUT4=1 LUT5=1 LUT6=4 OBUFT=1)
|
|
Output Delay: 0.300ns
|
|
Clock Path Skew: -1.695ns (DCD - SCD + CPR)
|
|
Destination Clock Delay (DCD): -4.208ns = ( 15.792 - 20.000 )
|
|
Source Clock Delay (SCD): -3.025ns
|
|
Clock Pessimism Removal (CPR): -0.513ns
|
|
Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Discrete Jitter (DJ): 0.122ns
|
|
Phase Error (PE): 0.000ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock sys_clk rise edge) 0.000 0.000 r
|
|
K21 0.000 0.000 r clk (IN)
|
|
net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1
|
|
K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I
|
|
K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O
|
|
net (fo=1, unplaced) 0.584 2.047 pll_clk.u_clk_pll/inst/clk_in1_clk_pll
|
|
r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1
|
|
PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1)
|
|
-6.768 -4.721 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1
|
|
net (fo=1, unplaced) 0.800 -3.921 pll_clk.u_clk_pll/inst/sys_clk_clk_pll
|
|
r pll_clk.u_clk_pll/inst/clkout2_buf/I
|
|
BUFG (Prop_bufg_I_O) 0.096 -3.825 r pll_clk.u_clk_pll/inst/clkout2_buf/O
|
|
net (fo=10994, unplaced) 0.800 -3.025 u_axi_ram/u_axi_sram_sp/sys_clk
|
|
FDCE r u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[2]/C
|
|
------------------------------------------------------------------- -------------------
|
|
FDCE (Prop_fdce_C_Q) 0.456 -2.569 f u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[2]/Q
|
|
net (fo=56, unplaced) 0.826 -1.743 u_axi_ram/u_axi_sram_sp/len[2]
|
|
f u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6/I1
|
|
LUT4 (Prop_lut4_I1_O) 0.321 -1.422 r u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6/O
|
|
net (fo=4, unplaced) 0.473 -0.949 u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6_n_0
|
|
r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_20/I1
|
|
LUT5 (Prop_lut5_I1_O) 0.124 -0.825 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_20/O
|
|
net (fo=1, unplaced) 0.449 -0.376 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_20_n_0
|
|
r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_19/I5
|
|
LUT6 (Prop_lut6_I5_O) 0.124 -0.252 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_19/O
|
|
net (fo=1, unplaced) 0.000 -0.252 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_19_n_0
|
|
r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/S[0]
|
|
CARRY4 (Prop_carry4_S[0]_CO[3])
|
|
0.532 0.280 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/CO[3]
|
|
net (fo=1, unplaced) 0.000 0.280 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10_n_0
|
|
r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CI
|
|
CARRY4 (Prop_carry4_CI_CO[3])
|
|
0.114 0.394 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CO[3]
|
|
net (fo=1, unplaced) 0.000 0.394 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9_n_0
|
|
r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/CI
|
|
CARRY4 (Prop_carry4_CI_CO[3])
|
|
0.114 0.508 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/CO[3]
|
|
net (fo=1, unplaced) 0.000 0.508 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11_n_0
|
|
r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_10/CI
|
|
CARRY4 (Prop_carry4_CI_CO[3])
|
|
0.114 0.622 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_10/CO[3]
|
|
net (fo=1, unplaced) 0.000 0.622 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_10_n_0
|
|
r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2_i_9/CI
|
|
CARRY4 (Prop_carry4_CI_O[3])
|
|
0.329 0.951 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2_i_9/O[3]
|
|
net (fo=3, unplaced) 0.826 1.777 u_axi_ram/u_axi_sram_sp/upper_wrap_boundary[29]
|
|
r u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1_i_2/I0
|
|
LUT6 (Prop_lut6_I0_O) 0.307 2.084 r u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1_i_2/O
|
|
net (fo=1, unplaced) 0.000 2.084 u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1_i_2_n_0
|
|
r u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1/S[1]
|
|
CARRY4 (Prop_carry4_S[1]_CO[2])
|
|
0.570 2.654 r u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1/CO[2]
|
|
net (fo=23, unplaced) 0.515 3.169 u_axi_ram/u_axi_sram_sp/req_addr_d10_in
|
|
r u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/I5
|
|
LUT6 (Prop_lut6_I5_O) 0.310 3.479 f u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/O
|
|
net (fo=2, unplaced) 0.460 3.939 u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7_n_0
|
|
f u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/I1
|
|
LUT6 (Prop_lut6_I1_O) 0.124 4.063 f u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/O
|
|
net (fo=80, unplaced) 0.543 4.606 u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/soc_sram_addr[0]
|
|
f u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/base_ram_data_IOBUF[31]_inst_i_3/I2
|
|
LUT3 (Prop_lut3_I2_O) 0.124 4.730 r u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/base_ram_data_IOBUF[31]_inst_i_3/O
|
|
net (fo=1, unplaced) 0.449 5.179 u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/u_axi_ram/base_ram_data1
|
|
r u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/base_ram_data_IOBUF[31]_inst_i_2/I0
|
|
LUT1 (Prop_lut1_I0_O) 0.124 5.303 f u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/base_ram_data_IOBUF[31]_inst_i_2/O
|
|
net (fo=32, unplaced) 0.800 6.102 base_ram_data_IOBUF[19]_inst/T
|
|
P19 f base_ram_data_IOBUF[19]_inst/OBUFT/T
|
|
P19 OBUFT (TriStatE_obuft_T_O)
|
|
3.518 9.620 r base_ram_data_IOBUF[19]_inst/OBUFT/O
|
|
net (fo=1, unset) 0.000 9.620 base_ram_data[19]
|
|
P19 r base_ram_data[19] (INOUT)
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock sys_clk rise edge) 20.000 20.000 r
|
|
K21 0.000 20.000 r clk (IN)
|
|
net (fo=0) 0.000 20.000 pll_clk.u_clk_pll/inst/clk_in1
|
|
K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I
|
|
K21 IBUF (Prop_ibuf_I_O) 1.393 21.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O
|
|
net (fo=1, unplaced) 0.439 21.832 pll_clk.u_clk_pll/inst/clk_in1_clk_pll
|
|
r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1
|
|
PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1)
|
|
-6.040 15.792 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1
|
|
clock pessimism -0.513 15.279
|
|
clock uncertainty -0.071 15.209
|
|
output delay -0.300 14.909
|
|
-------------------------------------------------------------------
|
|
required time 14.909
|
|
arrival time -9.620
|
|
-------------------------------------------------------------------
|
|
slack 5.289
|
|
|
|
Slack (MET) : 5.289ns (required time - arrival time)
|
|
Source: u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[2]/C
|
|
(rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Destination: base_ram_data[20]
|
|
(output port clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Path Group: sys_clk
|
|
Path Type: Max at Slow Process Corner
|
|
Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns)
|
|
Data Path Delay: 12.645ns (logic 7.304ns (57.764%) route 5.341ns (42.236%))
|
|
Logic Levels: 15 (CARRY4=6 LUT1=1 LUT3=1 LUT4=1 LUT5=1 LUT6=4 OBUFT=1)
|
|
Output Delay: 0.300ns
|
|
Clock Path Skew: -1.695ns (DCD - SCD + CPR)
|
|
Destination Clock Delay (DCD): -4.208ns = ( 15.792 - 20.000 )
|
|
Source Clock Delay (SCD): -3.025ns
|
|
Clock Pessimism Removal (CPR): -0.513ns
|
|
Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Discrete Jitter (DJ): 0.122ns
|
|
Phase Error (PE): 0.000ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock sys_clk rise edge) 0.000 0.000 r
|
|
K21 0.000 0.000 r clk (IN)
|
|
net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1
|
|
K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I
|
|
K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O
|
|
net (fo=1, unplaced) 0.584 2.047 pll_clk.u_clk_pll/inst/clk_in1_clk_pll
|
|
r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1
|
|
PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1)
|
|
-6.768 -4.721 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1
|
|
net (fo=1, unplaced) 0.800 -3.921 pll_clk.u_clk_pll/inst/sys_clk_clk_pll
|
|
r pll_clk.u_clk_pll/inst/clkout2_buf/I
|
|
BUFG (Prop_bufg_I_O) 0.096 -3.825 r pll_clk.u_clk_pll/inst/clkout2_buf/O
|
|
net (fo=10994, unplaced) 0.800 -3.025 u_axi_ram/u_axi_sram_sp/sys_clk
|
|
FDCE r u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[2]/C
|
|
------------------------------------------------------------------- -------------------
|
|
FDCE (Prop_fdce_C_Q) 0.456 -2.569 f u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[2]/Q
|
|
net (fo=56, unplaced) 0.826 -1.743 u_axi_ram/u_axi_sram_sp/len[2]
|
|
f u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6/I1
|
|
LUT4 (Prop_lut4_I1_O) 0.321 -1.422 r u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6/O
|
|
net (fo=4, unplaced) 0.473 -0.949 u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6_n_0
|
|
r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_20/I1
|
|
LUT5 (Prop_lut5_I1_O) 0.124 -0.825 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_20/O
|
|
net (fo=1, unplaced) 0.449 -0.376 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_20_n_0
|
|
r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_19/I5
|
|
LUT6 (Prop_lut6_I5_O) 0.124 -0.252 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_19/O
|
|
net (fo=1, unplaced) 0.000 -0.252 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_19_n_0
|
|
r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/S[0]
|
|
CARRY4 (Prop_carry4_S[0]_CO[3])
|
|
0.532 0.280 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/CO[3]
|
|
net (fo=1, unplaced) 0.000 0.280 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10_n_0
|
|
r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CI
|
|
CARRY4 (Prop_carry4_CI_CO[3])
|
|
0.114 0.394 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CO[3]
|
|
net (fo=1, unplaced) 0.000 0.394 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9_n_0
|
|
r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/CI
|
|
CARRY4 (Prop_carry4_CI_CO[3])
|
|
0.114 0.508 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/CO[3]
|
|
net (fo=1, unplaced) 0.000 0.508 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11_n_0
|
|
r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_10/CI
|
|
CARRY4 (Prop_carry4_CI_CO[3])
|
|
0.114 0.622 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_10/CO[3]
|
|
net (fo=1, unplaced) 0.000 0.622 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_10_n_0
|
|
r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2_i_9/CI
|
|
CARRY4 (Prop_carry4_CI_O[3])
|
|
0.329 0.951 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2_i_9/O[3]
|
|
net (fo=3, unplaced) 0.826 1.777 u_axi_ram/u_axi_sram_sp/upper_wrap_boundary[29]
|
|
r u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1_i_2/I0
|
|
LUT6 (Prop_lut6_I0_O) 0.307 2.084 r u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1_i_2/O
|
|
net (fo=1, unplaced) 0.000 2.084 u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1_i_2_n_0
|
|
r u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1/S[1]
|
|
CARRY4 (Prop_carry4_S[1]_CO[2])
|
|
0.570 2.654 r u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1/CO[2]
|
|
net (fo=23, unplaced) 0.515 3.169 u_axi_ram/u_axi_sram_sp/req_addr_d10_in
|
|
r u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/I5
|
|
LUT6 (Prop_lut6_I5_O) 0.310 3.479 f u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/O
|
|
net (fo=2, unplaced) 0.460 3.939 u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7_n_0
|
|
f u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/I1
|
|
LUT6 (Prop_lut6_I1_O) 0.124 4.063 f u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/O
|
|
net (fo=80, unplaced) 0.543 4.606 u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/soc_sram_addr[0]
|
|
f u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/base_ram_data_IOBUF[31]_inst_i_3/I2
|
|
LUT3 (Prop_lut3_I2_O) 0.124 4.730 r u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/base_ram_data_IOBUF[31]_inst_i_3/O
|
|
net (fo=1, unplaced) 0.449 5.179 u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/u_axi_ram/base_ram_data1
|
|
r u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/base_ram_data_IOBUF[31]_inst_i_2/I0
|
|
LUT1 (Prop_lut1_I0_O) 0.124 5.303 f u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/base_ram_data_IOBUF[31]_inst_i_2/O
|
|
net (fo=32, unplaced) 0.800 6.102 base_ram_data_IOBUF[20]_inst/T
|
|
N19 f base_ram_data_IOBUF[20]_inst/OBUFT/T
|
|
N19 OBUFT (TriStatE_obuft_T_O)
|
|
3.517 9.620 r base_ram_data_IOBUF[20]_inst/OBUFT/O
|
|
net (fo=1, unset) 0.000 9.620 base_ram_data[20]
|
|
N19 r base_ram_data[20] (INOUT)
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock sys_clk rise edge) 20.000 20.000 r
|
|
K21 0.000 20.000 r clk (IN)
|
|
net (fo=0) 0.000 20.000 pll_clk.u_clk_pll/inst/clk_in1
|
|
K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I
|
|
K21 IBUF (Prop_ibuf_I_O) 1.393 21.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O
|
|
net (fo=1, unplaced) 0.439 21.832 pll_clk.u_clk_pll/inst/clk_in1_clk_pll
|
|
r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1
|
|
PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1)
|
|
-6.040 15.792 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1
|
|
clock pessimism -0.513 15.279
|
|
clock uncertainty -0.071 15.209
|
|
output delay -0.300 14.909
|
|
-------------------------------------------------------------------
|
|
required time 14.909
|
|
arrival time -9.620
|
|
-------------------------------------------------------------------
|
|
slack 5.289
|
|
|
|
Slack (MET) : 5.321ns (required time - arrival time)
|
|
Source: u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[2]/C
|
|
(rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Destination: ext_ram_addr[3]
|
|
(output port clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Path Group: sys_clk
|
|
Path Type: Max at Slow Process Corner
|
|
Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns)
|
|
Data Path Delay: 12.613ns (logic 7.366ns (58.402%) route 5.247ns (41.598%))
|
|
Logic Levels: 15 (CARRY4=6 LUT4=1 LUT5=2 LUT6=5 OBUF=1)
|
|
Output Delay: 0.300ns
|
|
Clock Path Skew: -1.695ns (DCD - SCD + CPR)
|
|
Destination Clock Delay (DCD): -4.208ns = ( 15.792 - 20.000 )
|
|
Source Clock Delay (SCD): -3.025ns
|
|
Clock Pessimism Removal (CPR): -0.513ns
|
|
Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Discrete Jitter (DJ): 0.122ns
|
|
Phase Error (PE): 0.000ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock sys_clk rise edge) 0.000 0.000 r
|
|
K21 0.000 0.000 r clk (IN)
|
|
net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1
|
|
K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I
|
|
K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O
|
|
net (fo=1, unplaced) 0.584 2.047 pll_clk.u_clk_pll/inst/clk_in1_clk_pll
|
|
r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1
|
|
PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1)
|
|
-6.768 -4.721 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1
|
|
net (fo=1, unplaced) 0.800 -3.921 pll_clk.u_clk_pll/inst/sys_clk_clk_pll
|
|
r pll_clk.u_clk_pll/inst/clkout2_buf/I
|
|
BUFG (Prop_bufg_I_O) 0.096 -3.825 r pll_clk.u_clk_pll/inst/clkout2_buf/O
|
|
net (fo=10994, unplaced) 0.800 -3.025 u_axi_ram/u_axi_sram_sp/sys_clk
|
|
FDCE r u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[2]/C
|
|
------------------------------------------------------------------- -------------------
|
|
FDCE (Prop_fdce_C_Q) 0.456 -2.569 f u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[2]/Q
|
|
net (fo=56, unplaced) 0.826 -1.743 u_axi_ram/u_axi_sram_sp/len[2]
|
|
f u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6/I1
|
|
LUT4 (Prop_lut4_I1_O) 0.321 -1.422 r u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6/O
|
|
net (fo=4, unplaced) 0.473 -0.949 u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6_n_0
|
|
r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_20/I1
|
|
LUT5 (Prop_lut5_I1_O) 0.124 -0.825 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_20/O
|
|
net (fo=1, unplaced) 0.449 -0.376 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_20_n_0
|
|
r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_19/I5
|
|
LUT6 (Prop_lut6_I5_O) 0.124 -0.252 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_19/O
|
|
net (fo=1, unplaced) 0.000 -0.252 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_19_n_0
|
|
r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/S[0]
|
|
CARRY4 (Prop_carry4_S[0]_CO[3])
|
|
0.532 0.280 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/CO[3]
|
|
net (fo=1, unplaced) 0.000 0.280 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10_n_0
|
|
r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CI
|
|
CARRY4 (Prop_carry4_CI_CO[3])
|
|
0.114 0.394 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CO[3]
|
|
net (fo=1, unplaced) 0.000 0.394 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9_n_0
|
|
r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/CI
|
|
CARRY4 (Prop_carry4_CI_CO[3])
|
|
0.114 0.508 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/CO[3]
|
|
net (fo=1, unplaced) 0.000 0.508 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11_n_0
|
|
r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_10/CI
|
|
CARRY4 (Prop_carry4_CI_CO[3])
|
|
0.114 0.622 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_10/CO[3]
|
|
net (fo=1, unplaced) 0.000 0.622 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_10_n_0
|
|
r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2_i_9/CI
|
|
CARRY4 (Prop_carry4_CI_O[3])
|
|
0.329 0.951 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2_i_9/O[3]
|
|
net (fo=3, unplaced) 0.826 1.777 u_axi_ram/u_axi_sram_sp/upper_wrap_boundary[29]
|
|
r u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1_i_2/I0
|
|
LUT6 (Prop_lut6_I0_O) 0.307 2.084 r u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1_i_2/O
|
|
net (fo=1, unplaced) 0.000 2.084 u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1_i_2_n_0
|
|
r u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1/S[1]
|
|
CARRY4 (Prop_carry4_S[1]_CO[2])
|
|
0.570 2.654 r u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1/CO[2]
|
|
net (fo=23, unplaced) 0.515 3.169 u_axi_ram/u_axi_sram_sp/req_addr_d10_in
|
|
r u_axi_ram/u_axi_sram_sp/base_ram_addr_OBUF[3]_inst_i_6/I5
|
|
LUT6 (Prop_lut6_I5_O) 0.310 3.479 r u_axi_ram/u_axi_sram_sp/base_ram_addr_OBUF[3]_inst_i_6/O
|
|
net (fo=1, unplaced) 0.449 3.928 u_axi_ram/u_axi_sram_sp/base_ram_addr_OBUF[3]_inst_i_6_n_0
|
|
r u_axi_ram/u_axi_sram_sp/base_ram_addr_OBUF[3]_inst_i_5/I2
|
|
LUT6 (Prop_lut6_I2_O) 0.124 4.052 r u_axi_ram/u_axi_sram_sp/base_ram_addr_OBUF[3]_inst_i_5/O
|
|
net (fo=1, unplaced) 0.449 4.501 u_axi_ram/u_axi_sram_sp/base_ram_addr_OBUF[3]_inst_i_5_n_0
|
|
r u_axi_ram/u_axi_sram_sp/base_ram_addr_OBUF[3]_inst_i_2/I0
|
|
LUT5 (Prop_lut5_I0_O) 0.124 4.625 r u_axi_ram/u_axi_sram_sp/base_ram_addr_OBUF[3]_inst_i_2/O
|
|
net (fo=2, unplaced) 0.460 5.085 u_axi_ram/u_axi_sram_sp/base_ram_addr_OBUF[3]_inst_i_2_n_0
|
|
r u_axi_ram/u_axi_sram_sp/base_ram_addr_OBUF[3]_inst_i_1/I1
|
|
LUT6 (Prop_lut6_I1_O) 0.124 5.209 r u_axi_ram/u_axi_sram_sp/base_ram_addr_OBUF[3]_inst_i_1/O
|
|
net (fo=2, unplaced) 0.800 6.008 ext_ram_addr_OBUF[3]
|
|
AD25 r ext_ram_addr_OBUF[3]_inst/I
|
|
AD25 OBUF (Prop_obuf_I_O) 3.579 9.588 r ext_ram_addr_OBUF[3]_inst/O
|
|
net (fo=0) 0.000 9.588 ext_ram_addr[3]
|
|
AD25 r ext_ram_addr[3] (OUT)
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock sys_clk rise edge) 20.000 20.000 r
|
|
K21 0.000 20.000 r clk (IN)
|
|
net (fo=0) 0.000 20.000 pll_clk.u_clk_pll/inst/clk_in1
|
|
K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I
|
|
K21 IBUF (Prop_ibuf_I_O) 1.393 21.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O
|
|
net (fo=1, unplaced) 0.439 21.832 pll_clk.u_clk_pll/inst/clk_in1_clk_pll
|
|
r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1
|
|
PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1)
|
|
-6.040 15.792 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1
|
|
clock pessimism -0.513 15.279
|
|
clock uncertainty -0.071 15.209
|
|
output delay -0.300 14.909
|
|
-------------------------------------------------------------------
|
|
required time 14.909
|
|
arrival time -9.588
|
|
-------------------------------------------------------------------
|
|
slack 5.321
|
|
|
|
Slack (MET) : 5.395ns (required time - arrival time)
|
|
Source: u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[2]/C
|
|
(rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Destination: base_ram_addr[3]
|
|
(output port clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Path Group: sys_clk
|
|
Path Type: Max at Slow Process Corner
|
|
Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns)
|
|
Data Path Delay: 12.539ns (logic 7.293ns (58.158%) route 5.247ns (41.842%))
|
|
Logic Levels: 15 (CARRY4=6 LUT4=1 LUT5=2 LUT6=5 OBUF=1)
|
|
Output Delay: 0.300ns
|
|
Clock Path Skew: -1.695ns (DCD - SCD + CPR)
|
|
Destination Clock Delay (DCD): -4.208ns = ( 15.792 - 20.000 )
|
|
Source Clock Delay (SCD): -3.025ns
|
|
Clock Pessimism Removal (CPR): -0.513ns
|
|
Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Discrete Jitter (DJ): 0.122ns
|
|
Phase Error (PE): 0.000ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock sys_clk rise edge) 0.000 0.000 r
|
|
K21 0.000 0.000 r clk (IN)
|
|
net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1
|
|
K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I
|
|
K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O
|
|
net (fo=1, unplaced) 0.584 2.047 pll_clk.u_clk_pll/inst/clk_in1_clk_pll
|
|
r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1
|
|
PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1)
|
|
-6.768 -4.721 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1
|
|
net (fo=1, unplaced) 0.800 -3.921 pll_clk.u_clk_pll/inst/sys_clk_clk_pll
|
|
r pll_clk.u_clk_pll/inst/clkout2_buf/I
|
|
BUFG (Prop_bufg_I_O) 0.096 -3.825 r pll_clk.u_clk_pll/inst/clkout2_buf/O
|
|
net (fo=10994, unplaced) 0.800 -3.025 u_axi_ram/u_axi_sram_sp/sys_clk
|
|
FDCE r u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[2]/C
|
|
------------------------------------------------------------------- -------------------
|
|
FDCE (Prop_fdce_C_Q) 0.456 -2.569 f u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[2]/Q
|
|
net (fo=56, unplaced) 0.826 -1.743 u_axi_ram/u_axi_sram_sp/len[2]
|
|
f u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6/I1
|
|
LUT4 (Prop_lut4_I1_O) 0.321 -1.422 r u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6/O
|
|
net (fo=4, unplaced) 0.473 -0.949 u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6_n_0
|
|
r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_20/I1
|
|
LUT5 (Prop_lut5_I1_O) 0.124 -0.825 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_20/O
|
|
net (fo=1, unplaced) 0.449 -0.376 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_20_n_0
|
|
r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_19/I5
|
|
LUT6 (Prop_lut6_I5_O) 0.124 -0.252 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_19/O
|
|
net (fo=1, unplaced) 0.000 -0.252 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_19_n_0
|
|
r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/S[0]
|
|
CARRY4 (Prop_carry4_S[0]_CO[3])
|
|
0.532 0.280 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/CO[3]
|
|
net (fo=1, unplaced) 0.000 0.280 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10_n_0
|
|
r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CI
|
|
CARRY4 (Prop_carry4_CI_CO[3])
|
|
0.114 0.394 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CO[3]
|
|
net (fo=1, unplaced) 0.000 0.394 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9_n_0
|
|
r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/CI
|
|
CARRY4 (Prop_carry4_CI_CO[3])
|
|
0.114 0.508 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/CO[3]
|
|
net (fo=1, unplaced) 0.000 0.508 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11_n_0
|
|
r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_10/CI
|
|
CARRY4 (Prop_carry4_CI_CO[3])
|
|
0.114 0.622 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_10/CO[3]
|
|
net (fo=1, unplaced) 0.000 0.622 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_10_n_0
|
|
r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2_i_9/CI
|
|
CARRY4 (Prop_carry4_CI_O[3])
|
|
0.329 0.951 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2_i_9/O[3]
|
|
net (fo=3, unplaced) 0.826 1.777 u_axi_ram/u_axi_sram_sp/upper_wrap_boundary[29]
|
|
r u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1_i_2/I0
|
|
LUT6 (Prop_lut6_I0_O) 0.307 2.084 r u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1_i_2/O
|
|
net (fo=1, unplaced) 0.000 2.084 u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1_i_2_n_0
|
|
r u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1/S[1]
|
|
CARRY4 (Prop_carry4_S[1]_CO[2])
|
|
0.570 2.654 r u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1/CO[2]
|
|
net (fo=23, unplaced) 0.515 3.169 u_axi_ram/u_axi_sram_sp/req_addr_d10_in
|
|
r u_axi_ram/u_axi_sram_sp/base_ram_addr_OBUF[3]_inst_i_6/I5
|
|
LUT6 (Prop_lut6_I5_O) 0.310 3.479 r u_axi_ram/u_axi_sram_sp/base_ram_addr_OBUF[3]_inst_i_6/O
|
|
net (fo=1, unplaced) 0.449 3.928 u_axi_ram/u_axi_sram_sp/base_ram_addr_OBUF[3]_inst_i_6_n_0
|
|
r u_axi_ram/u_axi_sram_sp/base_ram_addr_OBUF[3]_inst_i_5/I2
|
|
LUT6 (Prop_lut6_I2_O) 0.124 4.052 r u_axi_ram/u_axi_sram_sp/base_ram_addr_OBUF[3]_inst_i_5/O
|
|
net (fo=1, unplaced) 0.449 4.501 u_axi_ram/u_axi_sram_sp/base_ram_addr_OBUF[3]_inst_i_5_n_0
|
|
r u_axi_ram/u_axi_sram_sp/base_ram_addr_OBUF[3]_inst_i_2/I0
|
|
LUT5 (Prop_lut5_I0_O) 0.124 4.625 r u_axi_ram/u_axi_sram_sp/base_ram_addr_OBUF[3]_inst_i_2/O
|
|
net (fo=2, unplaced) 0.460 5.085 u_axi_ram/u_axi_sram_sp/base_ram_addr_OBUF[3]_inst_i_2_n_0
|
|
r u_axi_ram/u_axi_sram_sp/base_ram_addr_OBUF[3]_inst_i_1/I1
|
|
LUT6 (Prop_lut6_I1_O) 0.124 5.209 r u_axi_ram/u_axi_sram_sp/base_ram_addr_OBUF[3]_inst_i_1/O
|
|
net (fo=2, unplaced) 0.800 6.008 ext_ram_addr_OBUF[3]
|
|
V17 r base_ram_addr_OBUF[3]_inst/I
|
|
V17 OBUF (Prop_obuf_I_O) 3.506 9.514 r base_ram_addr_OBUF[3]_inst/O
|
|
net (fo=0) 0.000 9.514 base_ram_addr[3]
|
|
V17 r base_ram_addr[3] (OUT)
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock sys_clk rise edge) 20.000 20.000 r
|
|
K21 0.000 20.000 r clk (IN)
|
|
net (fo=0) 0.000 20.000 pll_clk.u_clk_pll/inst/clk_in1
|
|
K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I
|
|
K21 IBUF (Prop_ibuf_I_O) 1.393 21.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O
|
|
net (fo=1, unplaced) 0.439 21.832 pll_clk.u_clk_pll/inst/clk_in1_clk_pll
|
|
r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1
|
|
PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1)
|
|
-6.040 15.792 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1
|
|
clock pessimism -0.513 15.279
|
|
clock uncertainty -0.071 15.209
|
|
output delay -0.300 14.909
|
|
-------------------------------------------------------------------
|
|
required time 14.909
|
|
arrival time -9.514
|
|
-------------------------------------------------------------------
|
|
slack 5.395
|
|
|
|
Slack (MET) : 5.795ns (required time - arrival time)
|
|
Source: u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[2]/C
|
|
(rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Destination: ext_ram_be_n[2]
|
|
(output port clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Path Group: sys_clk
|
|
Path Type: Max at Slow Process Corner
|
|
Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns)
|
|
Data Path Delay: 12.139ns (logic 7.248ns (59.704%) route 4.892ns (40.296%))
|
|
Logic Levels: 14 (CARRY4=6 LUT4=1 LUT5=1 LUT6=5 OBUF=1)
|
|
Output Delay: 0.300ns
|
|
Clock Path Skew: -1.695ns (DCD - SCD + CPR)
|
|
Destination Clock Delay (DCD): -4.208ns = ( 15.792 - 20.000 )
|
|
Source Clock Delay (SCD): -3.025ns
|
|
Clock Pessimism Removal (CPR): -0.513ns
|
|
Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Discrete Jitter (DJ): 0.122ns
|
|
Phase Error (PE): 0.000ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock sys_clk rise edge) 0.000 0.000 r
|
|
K21 0.000 0.000 r clk (IN)
|
|
net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1
|
|
K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I
|
|
K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O
|
|
net (fo=1, unplaced) 0.584 2.047 pll_clk.u_clk_pll/inst/clk_in1_clk_pll
|
|
r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1
|
|
PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1)
|
|
-6.768 -4.721 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1
|
|
net (fo=1, unplaced) 0.800 -3.921 pll_clk.u_clk_pll/inst/sys_clk_clk_pll
|
|
r pll_clk.u_clk_pll/inst/clkout2_buf/I
|
|
BUFG (Prop_bufg_I_O) 0.096 -3.825 r pll_clk.u_clk_pll/inst/clkout2_buf/O
|
|
net (fo=10994, unplaced) 0.800 -3.025 u_axi_ram/u_axi_sram_sp/sys_clk
|
|
FDCE r u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[2]/C
|
|
------------------------------------------------------------------- -------------------
|
|
FDCE (Prop_fdce_C_Q) 0.456 -2.569 f u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[2]/Q
|
|
net (fo=56, unplaced) 0.826 -1.743 u_axi_ram/u_axi_sram_sp/len[2]
|
|
f u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6/I1
|
|
LUT4 (Prop_lut4_I1_O) 0.321 -1.422 r u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6/O
|
|
net (fo=4, unplaced) 0.473 -0.949 u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6_n_0
|
|
r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_20/I1
|
|
LUT5 (Prop_lut5_I1_O) 0.124 -0.825 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_20/O
|
|
net (fo=1, unplaced) 0.449 -0.376 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_20_n_0
|
|
r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_19/I5
|
|
LUT6 (Prop_lut6_I5_O) 0.124 -0.252 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_19/O
|
|
net (fo=1, unplaced) 0.000 -0.252 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_19_n_0
|
|
r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/S[0]
|
|
CARRY4 (Prop_carry4_S[0]_CO[3])
|
|
0.532 0.280 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/CO[3]
|
|
net (fo=1, unplaced) 0.000 0.280 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10_n_0
|
|
r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CI
|
|
CARRY4 (Prop_carry4_CI_CO[3])
|
|
0.114 0.394 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CO[3]
|
|
net (fo=1, unplaced) 0.000 0.394 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9_n_0
|
|
r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/CI
|
|
CARRY4 (Prop_carry4_CI_CO[3])
|
|
0.114 0.508 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/CO[3]
|
|
net (fo=1, unplaced) 0.000 0.508 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11_n_0
|
|
r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_10/CI
|
|
CARRY4 (Prop_carry4_CI_CO[3])
|
|
0.114 0.622 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_10/CO[3]
|
|
net (fo=1, unplaced) 0.000 0.622 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_10_n_0
|
|
r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2_i_9/CI
|
|
CARRY4 (Prop_carry4_CI_O[3])
|
|
0.329 0.951 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2_i_9/O[3]
|
|
net (fo=3, unplaced) 0.826 1.777 u_axi_ram/u_axi_sram_sp/upper_wrap_boundary[29]
|
|
r u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1_i_2/I0
|
|
LUT6 (Prop_lut6_I0_O) 0.307 2.084 r u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1_i_2/O
|
|
net (fo=1, unplaced) 0.000 2.084 u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1_i_2_n_0
|
|
r u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1/S[1]
|
|
CARRY4 (Prop_carry4_S[1]_CO[2])
|
|
0.570 2.654 r u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1/CO[2]
|
|
net (fo=23, unplaced) 0.515 3.169 u_axi_ram/u_axi_sram_sp/req_addr_d10_in
|
|
r u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/I5
|
|
LUT6 (Prop_lut6_I5_O) 0.310 3.479 f u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/O
|
|
net (fo=2, unplaced) 0.460 3.939 u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7_n_0
|
|
f u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/I1
|
|
LUT6 (Prop_lut6_I1_O) 0.124 4.063 f u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/O
|
|
net (fo=80, unplaced) 0.543 4.606 u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/soc_sram_addr[0]
|
|
f u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/ext_ram_be_n_OBUF[2]_inst_i_1/I5
|
|
LUT6 (Prop_lut6_I5_O) 0.124 4.730 r u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/ext_ram_be_n_OBUF[2]_inst_i_1/O
|
|
net (fo=1, unplaced) 0.800 5.529 ext_ram_be_n_OBUF[2]
|
|
AD24 r ext_ram_be_n_OBUF[2]_inst/I
|
|
AD24 OBUF (Prop_obuf_I_O) 3.585 9.114 r ext_ram_be_n_OBUF[2]_inst/O
|
|
net (fo=0) 0.000 9.114 ext_ram_be_n[2]
|
|
AD24 r ext_ram_be_n[2] (OUT)
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock sys_clk rise edge) 20.000 20.000 r
|
|
K21 0.000 20.000 r clk (IN)
|
|
net (fo=0) 0.000 20.000 pll_clk.u_clk_pll/inst/clk_in1
|
|
K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I
|
|
K21 IBUF (Prop_ibuf_I_O) 1.393 21.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O
|
|
net (fo=1, unplaced) 0.439 21.832 pll_clk.u_clk_pll/inst/clk_in1_clk_pll
|
|
r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1
|
|
PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1)
|
|
-6.040 15.792 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1
|
|
clock pessimism -0.513 15.279
|
|
clock uncertainty -0.071 15.209
|
|
output delay -0.300 14.909
|
|
-------------------------------------------------------------------
|
|
required time 14.909
|
|
arrival time -9.114
|
|
-------------------------------------------------------------------
|
|
slack 5.795
|
|
|
|
Slack (MET) : 5.811ns (required time - arrival time)
|
|
Source: u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[2]/C
|
|
(rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Destination: ext_ram_ce_n
|
|
(output port clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Path Group: sys_clk
|
|
Path Type: Max at Slow Process Corner
|
|
Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns)
|
|
Data Path Delay: 12.123ns (logic 7.231ns (59.648%) route 4.892ns (40.352%))
|
|
Logic Levels: 14 (CARRY4=6 LUT2=1 LUT4=1 LUT5=1 LUT6=4 OBUF=1)
|
|
Output Delay: 0.300ns
|
|
Clock Path Skew: -1.695ns (DCD - SCD + CPR)
|
|
Destination Clock Delay (DCD): -4.208ns = ( 15.792 - 20.000 )
|
|
Source Clock Delay (SCD): -3.025ns
|
|
Clock Pessimism Removal (CPR): -0.513ns
|
|
Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Discrete Jitter (DJ): 0.122ns
|
|
Phase Error (PE): 0.000ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock sys_clk rise edge) 0.000 0.000 r
|
|
K21 0.000 0.000 r clk (IN)
|
|
net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1
|
|
K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I
|
|
K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O
|
|
net (fo=1, unplaced) 0.584 2.047 pll_clk.u_clk_pll/inst/clk_in1_clk_pll
|
|
r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1
|
|
PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1)
|
|
-6.768 -4.721 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1
|
|
net (fo=1, unplaced) 0.800 -3.921 pll_clk.u_clk_pll/inst/sys_clk_clk_pll
|
|
r pll_clk.u_clk_pll/inst/clkout2_buf/I
|
|
BUFG (Prop_bufg_I_O) 0.096 -3.825 r pll_clk.u_clk_pll/inst/clkout2_buf/O
|
|
net (fo=10994, unplaced) 0.800 -3.025 u_axi_ram/u_axi_sram_sp/sys_clk
|
|
FDCE r u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[2]/C
|
|
------------------------------------------------------------------- -------------------
|
|
FDCE (Prop_fdce_C_Q) 0.456 -2.569 f u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[2]/Q
|
|
net (fo=56, unplaced) 0.826 -1.743 u_axi_ram/u_axi_sram_sp/len[2]
|
|
f u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6/I1
|
|
LUT4 (Prop_lut4_I1_O) 0.321 -1.422 r u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6/O
|
|
net (fo=4, unplaced) 0.473 -0.949 u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6_n_0
|
|
r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_20/I1
|
|
LUT5 (Prop_lut5_I1_O) 0.124 -0.825 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_20/O
|
|
net (fo=1, unplaced) 0.449 -0.376 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_20_n_0
|
|
r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_19/I5
|
|
LUT6 (Prop_lut6_I5_O) 0.124 -0.252 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_19/O
|
|
net (fo=1, unplaced) 0.000 -0.252 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_19_n_0
|
|
r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/S[0]
|
|
CARRY4 (Prop_carry4_S[0]_CO[3])
|
|
0.532 0.280 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/CO[3]
|
|
net (fo=1, unplaced) 0.000 0.280 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10_n_0
|
|
r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CI
|
|
CARRY4 (Prop_carry4_CI_CO[3])
|
|
0.114 0.394 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CO[3]
|
|
net (fo=1, unplaced) 0.000 0.394 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9_n_0
|
|
r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/CI
|
|
CARRY4 (Prop_carry4_CI_CO[3])
|
|
0.114 0.508 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/CO[3]
|
|
net (fo=1, unplaced) 0.000 0.508 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11_n_0
|
|
r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_10/CI
|
|
CARRY4 (Prop_carry4_CI_CO[3])
|
|
0.114 0.622 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_10/CO[3]
|
|
net (fo=1, unplaced) 0.000 0.622 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_10_n_0
|
|
r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2_i_9/CI
|
|
CARRY4 (Prop_carry4_CI_O[3])
|
|
0.329 0.951 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2_i_9/O[3]
|
|
net (fo=3, unplaced) 0.826 1.777 u_axi_ram/u_axi_sram_sp/upper_wrap_boundary[29]
|
|
r u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1_i_2/I0
|
|
LUT6 (Prop_lut6_I0_O) 0.307 2.084 r u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1_i_2/O
|
|
net (fo=1, unplaced) 0.000 2.084 u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1_i_2_n_0
|
|
r u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1/S[1]
|
|
CARRY4 (Prop_carry4_S[1]_CO[2])
|
|
0.570 2.654 r u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1/CO[2]
|
|
net (fo=23, unplaced) 0.515 3.169 u_axi_ram/u_axi_sram_sp/req_addr_d10_in
|
|
r u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/I5
|
|
LUT6 (Prop_lut6_I5_O) 0.310 3.479 f u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/O
|
|
net (fo=2, unplaced) 0.460 3.939 u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7_n_0
|
|
f u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/I1
|
|
LUT6 (Prop_lut6_I1_O) 0.124 4.063 f u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/O
|
|
net (fo=80, unplaced) 0.543 4.606 u_axi_ram/u_axi_sram_sp/ax_req_q_burst_reg[0]_0
|
|
f u_axi_ram/u_axi_sram_sp/ext_ram_ce_n_OBUF_inst_i_1/I0
|
|
LUT2 (Prop_lut2_I0_O) 0.118 4.724 r u_axi_ram/u_axi_sram_sp/ext_ram_ce_n_OBUF_inst_i_1/O
|
|
net (fo=1, unplaced) 0.800 5.523 ext_ram_ce_n_OBUF
|
|
AD23 r ext_ram_ce_n_OBUF_inst/I
|
|
AD23 OBUF (Prop_obuf_I_O) 3.574 9.097 r ext_ram_ce_n_OBUF_inst/O
|
|
net (fo=0) 0.000 9.097 ext_ram_ce_n
|
|
AD23 r ext_ram_ce_n (OUT)
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock sys_clk rise edge) 20.000 20.000 r
|
|
K21 0.000 20.000 r clk (IN)
|
|
net (fo=0) 0.000 20.000 pll_clk.u_clk_pll/inst/clk_in1
|
|
K21 r pll_clk.u_clk_pll/inst/clkin1_ibufg/I
|
|
K21 IBUF (Prop_ibuf_I_O) 1.393 21.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O
|
|
net (fo=1, unplaced) 0.439 21.832 pll_clk.u_clk_pll/inst/clk_in1_clk_pll
|
|
r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1
|
|
PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1)
|
|
-6.040 15.792 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1
|
|
clock pessimism -0.513 15.279
|
|
clock uncertainty -0.071 15.209
|
|
output delay -0.300 14.909
|
|
-------------------------------------------------------------------
|
|
required time 14.909
|
|
arrival time -9.097
|
|
-------------------------------------------------------------------
|
|
slack 5.811
|
|
|
|
|
|
|
|
|