453 lines
17 KiB
Verilog
453 lines
17 KiB
Verilog
// ═══════════════════════════════════════════════════════
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// 基础时序乘法器模块 (无 DSP，移位累加，32个周期)
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// ═══════════════════════════════════════════════════════
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module shift_add_mult (
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input clk,
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input rstn,
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input start,
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input [31:0] a,
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input [31:0] b,
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output reg [63:0] p,
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output reg done
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);
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reg [5:0] cnt;
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reg [63:0] a_reg;
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reg [31:0] b_reg;
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reg busy;
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always @(posedge clk) begin
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if (!rstn) begin
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busy <= 1'b0;
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done <= 1'b0;
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p <= 64'b0;
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cnt <= 6'd0;
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a_reg<= 64'b0;
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b_reg<= 32'b0;
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end else begin
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if (start && !busy) begin
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a_reg <= {32'b0, a};
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b_reg <= b;
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p <= 64'b0;
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cnt <= 6'd0;
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busy <= 1'b1;
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done <= 1'b0;
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end else if (busy) begin
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if (cnt == 6'd32) begin
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busy <= 1'b0;
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done <= 1'b1;
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end else begin
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// 如果 b 的当前最低位为 1，则累加 a
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if (b_reg[0]) begin
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p <= p + a_reg;
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end
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a_reg <= a_reg << 1;
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b_reg <= b_reg >> 1;
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cnt <= cnt + 6'd1;
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end
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end else begin
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done <= 1'b0;
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end
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end
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end
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endmodule
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// ═══════════════════════════════════════════════════════
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// 矩阵乘法器顶层模块 (AXI Burst Slave + Ping-Pong)
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// ═══════════════════════════════════════════════════════
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module matmul_axi_slave (
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input clk,
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input resetn,
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// AXI Write Address Channel
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input [4:0] s_axi_awid,
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input [31:0] s_axi_awaddr,
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input [7:0] s_axi_awlen,
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input [2:0] s_axi_awsize,
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input [1:0] s_axi_awburst,
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input s_axi_awvalid,
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output reg s_axi_awready,
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// AXI Write Data Channel
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input [4:0] s_axi_wid,
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input [31:0] s_axi_wdata,
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input [3:0] s_axi_wstrb,
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input s_axi_wlast,
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input s_axi_wvalid,
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output reg s_axi_wready,
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// AXI Write Response Channel
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output [4:0] s_axi_bid,
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output [1:0] s_axi_bresp,
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output reg s_axi_bvalid,
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input s_axi_bready,
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// AXI Read Address Channel
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input [4:0] s_axi_arid,
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input [31:0] s_axi_araddr,
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input [7:0] s_axi_arlen,
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input [2:0] s_axi_arsize,
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input [1:0] s_axi_arburst,
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input s_axi_arvalid,
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output reg s_axi_arready,
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// AXI Read Data Channel
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output reg [4:0] s_axi_rid,
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output reg [31:0] s_axi_rdata,
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output [1:0] s_axi_rresp,
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output reg s_axi_rlast,
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output reg s_axi_rvalid,
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input s_axi_rready
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);
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// ==========================================
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// 内存地址映射 (Memory Map)
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// ==========================================
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localparam ADDR_CTRL = 12'h000;
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localparam ADDR_STATUS = 12'h004;
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// Bank 0 (可完全当作原来的单缓冲使用)
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localparam ADDR_B0_A = 12'h100;
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localparam ADDR_B0_B = 12'h140;
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localparam ADDR_B0_C = 12'h180;
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// Bank 1 (供无等待计算扩展使用)
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localparam ADDR_B1_A = 12'h300;
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localparam ADDR_B1_B = 12'h340;
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localparam ADDR_B1_C = 12'h380;
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// ==========================================
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// 寄存器与数据缓冲
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// ==========================================
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reg req_0, req_1;
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reg busy;
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reg done;
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reg error;
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reg [31:0] b0_a [0:15];
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reg [31:0] b0_b [0:15];
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reg [65:0] b0_c [0:15];
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reg [31:0] b1_a [0:15];
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reg [31:0] b1_b [0:15];
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reg [65:0] b1_c [0:15];
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function [31:0] apply_wstrb;
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input [31:0] old_value;
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input [31:0] new_value;
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input [3:0] strobe;
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begin
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apply_wstrb = old_value;
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if (strobe[0]) apply_wstrb[7:0] = new_value[7:0];
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if (strobe[1]) apply_wstrb[15:8] = new_value[15:8];
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if (strobe[2]) apply_wstrb[23:16] = new_value[23:16];
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if (strobe[3]) apply_wstrb[31:24] = new_value[31:24];
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end
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endfunction
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// ==========================================
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// AXI Write 通道逻辑 (支持 INCR Burst)
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// ==========================================
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localparam W_IDLE = 2'd0;
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localparam W_DATA = 2'd1;
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localparam W_RESP = 2'd2;
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reg [1:0] w_state;
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reg [31:0] w_addr;
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reg [4:0] w_id;
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reg [1:0] w_burst;
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wire [11:0] w_offset = w_addr[11:0];
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assign s_axi_bid = w_id;
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assign s_axi_bresp = 2'b00;
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// 前向声明引擎的状态
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localparam C_IDLE = 2'd0;
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localparam C_CALC = 2'd1;
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localparam C_WAIT_MULT = 2'd2;
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localparam C_ACCUM = 2'd3;
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reg [1:0] state;
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reg cur_bank;
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reg calc_done_pulse;
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always @(posedge clk) begin
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if (!resetn) begin
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w_state <= W_IDLE;
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s_axi_awready <= 1'b1;
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s_axi_wready <= 1'b0;
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s_axi_bvalid <= 1'b0;
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req_0 <= 1'b0;
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req_1 <= 1'b0;
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done <= 1'b0;
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error <= 1'b0;
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end else begin
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// 引擎接管请求后清零
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if (req_0 && state == C_CALC && cur_bank == 1'b0) req_0 <= 1'b0;
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if (req_1 && state == C_CALC && cur_bank == 1'b1) req_1 <= 1'b0;
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// 引擎计算完成，拉高通用 done 标志
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if (calc_done_pulse) begin
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done <= 1'b1;
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end
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case (w_state)
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W_IDLE: begin
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s_axi_awready <= 1'b1;
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if (s_axi_awvalid && s_axi_awready) begin
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s_axi_awready <= 1'b0;
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s_axi_wready <= 1'b1;
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w_addr <= s_axi_awaddr;
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w_id <= s_axi_awid;
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w_burst <= s_axi_awburst;
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w_state <= W_DATA;
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end
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end
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W_DATA: begin
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if (s_axi_wvalid && s_axi_wready) begin
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// ===== 写地址译码与数据装载 =====
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if (w_offset == ADDR_CTRL) begin
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if (s_axi_wdata[0]) req_0 <= 1'b1; // 启动 Bank 0
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if (s_axi_wdata[1]) req_1 <= 1'b1; // 启动 Bank 1
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end
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else if (w_offset == ADDR_STATUS) begin
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if (s_axi_wdata[1]) done <= 1'b0; // 写 1 清零 Done (兼容旧版TB)
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if (s_axi_wdata[2]) error <= 1'b0; // 写 1 清零 Error
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end
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else if (w_offset >= ADDR_B0_A && w_offset < ADDR_B0_B)
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b0_a[(w_offset - ADDR_B0_A) >> 2] <= apply_wstrb(b0_a[(w_offset - ADDR_B0_A) >> 2], s_axi_wdata, s_axi_wstrb);
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else if (w_offset >= ADDR_B0_B && w_offset < ADDR_B0_C)
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b0_b[(w_offset - ADDR_B0_B) >> 2] <= apply_wstrb(b0_b[(w_offset - ADDR_B0_B) >> 2], s_axi_wdata, s_axi_wstrb);
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else if (w_offset >= ADDR_B1_A && w_offset < ADDR_B1_B)
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b1_a[(w_offset - ADDR_B1_A) >> 2] <= apply_wstrb(b1_a[(w_offset - ADDR_B1_A) >> 2], s_axi_wdata, s_axi_wstrb);
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else if (w_offset >= ADDR_B1_B && w_offset < ADDR_B1_C)
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b1_b[(w_offset - ADDR_B1_B) >> 2] <= apply_wstrb(b1_b[(w_offset - ADDR_B1_B) >> 2], s_axi_wdata, s_axi_wstrb);
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else begin
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// 访问无效地址，拉高 error 标志
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error <= 1'b1;
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end
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// ===== Burst 地址累加 =====
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if (w_burst == 2'b01) w_addr <= w_addr + 32'd4;
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if (s_axi_wlast) begin
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s_axi_wready <= 1'b0;
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s_axi_bvalid <= 1'b1;
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w_state <= W_RESP;
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end
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end
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end
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W_RESP: begin
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if (s_axi_bvalid && s_axi_bready) begin
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s_axi_bvalid <= 1'b0;
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s_axi_awready <= 1'b1;
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w_state <= W_IDLE;
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end
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end
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default: w_state <= W_IDLE;
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endcase
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end
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end
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// ==========================================
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// AXI Read 通道逻辑 (支持 INCR Burst)
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// ==========================================
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localparam R_IDLE = 2'd0;
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localparam R_DATA = 2'd1;
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reg [1:0] r_state;
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reg [31:0] r_addr;
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reg [7:0] r_cnt;
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reg [7:0] r_len;
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reg [1:0] r_burst;
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wire [11:0] r_offset = r_addr[11:0];
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assign s_axi_rresp = 2'b00;
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wire [5:0] c0_offset = (r_offset - ADDR_B0_C) >> 2;
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wire [3:0] c0_elem = c0_offset / 3;
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wire [1:0] c0_part = c0_offset % 3;
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wire [65:0] target_c0 = b0_c[c0_elem];
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wire [5:0] c1_offset = (r_offset - ADDR_B1_C) >> 2;
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wire [3:0] c1_elem = c1_offset / 3;
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wire [1:0] c1_part = c1_offset % 3;
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wire [65:0] target_c1 = b1_c[c1_elem];
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always @(posedge clk) begin
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if (!resetn) begin
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r_state <= R_IDLE;
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s_axi_arready <= 1'b1;
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s_axi_rvalid <= 1'b0;
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s_axi_rlast <= 1'b0;
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s_axi_rid <= 5'b0;
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end else begin
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case (r_state)
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R_IDLE: begin
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s_axi_arready <= 1'b1;
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if (s_axi_arvalid && s_axi_arready) begin
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s_axi_arready <= 1'b0;
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r_addr <= s_axi_araddr;
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r_len <= s_axi_arlen;
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r_burst <= s_axi_arburst;
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r_cnt <= 8'd0;
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s_axi_rvalid <= 1'b1;
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s_axi_rlast <= (s_axi_arlen == 8'd0);
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s_axi_rid <= s_axi_arid;
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r_state <= R_DATA;
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end
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end
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R_DATA: begin
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if (s_axi_rvalid && s_axi_rready) begin
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if (r_cnt == r_len) begin
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s_axi_rvalid <= 1'b0;
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s_axi_rlast <= 1'b0;
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s_axi_arready <= 1'b1;
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r_state <= R_IDLE;
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end else begin
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r_cnt <= r_cnt + 8'd1;
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s_axi_rlast <= (r_cnt + 8'd1 == r_len);
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if (r_burst == 2'b01) r_addr <= r_addr + 32'd4;
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end
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end
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end
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default: r_state <= R_IDLE;
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endcase
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end
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end
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// 修复：将 wire 声明提取到 always 块外部
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wire [11:0] current_r_offset = (r_state == R_DATA) ? r_offset : s_axi_araddr[11:0];
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// 组合逻辑准备 Read 数据
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always @(*) begin
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s_axi_rdata = 32'b0;
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if (r_state == R_DATA || (r_state == R_IDLE && s_axi_arvalid)) begin
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if (current_r_offset == ADDR_CTRL)
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s_axi_rdata = {30'b0, req_1, req_0};
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else if (current_r_offset == ADDR_STATUS)
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s_axi_rdata = {29'b0, error, done, busy}; // 完美兼容旧 TB
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else if (current_r_offset >= ADDR_B0_A && current_r_offset < ADDR_B0_B)
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s_axi_rdata = b0_a[(current_r_offset - ADDR_B0_A) >> 2];
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else if (current_r_offset >= ADDR_B0_B && current_r_offset < ADDR_B0_C)
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s_axi_rdata = b0_b[(current_r_offset - ADDR_B0_B) >> 2];
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else if (current_r_offset >= ADDR_B0_C && current_r_offset < (ADDR_B0_C + 12'h0C0)) begin
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if (c0_part == 2'd0) s_axi_rdata = target_c0[31:0];
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else if (c0_part == 2'd1) s_axi_rdata = target_c0[63:32];
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else s_axi_rdata = {30'b0, target_c0[65:64]};
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end
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else if (current_r_offset >= ADDR_B1_A && current_r_offset < ADDR_B1_B)
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s_axi_rdata = b1_a[(current_r_offset - ADDR_B1_A) >> 2];
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else if (current_r_offset >= ADDR_B1_B && current_r_offset < ADDR_B1_C)
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s_axi_rdata = b1_b[(current_r_offset - ADDR_B1_B) >> 2];
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else if (current_r_offset >= ADDR_B1_C && current_r_offset < (ADDR_B1_C + 12'h0C0)) begin
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if (c1_part == 2'd0) s_axi_rdata = target_c1[31:0];
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else if (c1_part == 2'd1) s_axi_rdata = target_c1[63:32];
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else s_axi_rdata = {30'b0, target_c1[65:64]};
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end
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end
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end
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// ==========================================
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// 计算引擎 (Compute FSM)
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// ==========================================
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reg [3:0] calc_idx;
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wire [1:0] row = calc_idx[3:2];
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wire [1:0] col = calc_idx[1:0];
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reg mult_start;
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wire mult_done [0:3];
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wire [63:0] mult_p [0:3];
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reg [31:0] m_in_a [0:3];
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reg [31:0] m_in_b [0:3];
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genvar i;
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generate
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for (i = 0; i < 4; i = i + 1) begin : mult_inst
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shift_add_mult u_mult (
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.clk (clk),
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.rstn (resetn),
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.start (mult_start),
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.a (m_in_a[i]),
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.b (m_in_b[i]),
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.p (mult_p[i]),
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.done (mult_done[i])
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);
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end
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endgenerate
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always @(posedge clk) begin
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if (!resetn) begin
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state <= C_IDLE;
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busy <= 1'b0;
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cur_bank <= 1'b0;
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calc_idx <= 4'd0;
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mult_start <= 1'b0;
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calc_done_pulse <= 1'b0;
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end else begin
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calc_done_pulse <= 1'b0;
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case (state)
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C_IDLE: begin
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calc_idx <= 4'd0;
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if (req_0) begin
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cur_bank <= 1'b0;
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busy <= 1'b1;
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state <= C_CALC;
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end else if (req_1) begin
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cur_bank <= 1'b1;
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busy <= 1'b1;
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state <= C_CALC;
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end else begin
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busy <= 1'b0;
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end
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end
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C_CALC: begin
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if (cur_bank == 1'b0) begin
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m_in_a[0] <= b0_a[{row, 2'd0}]; m_in_b[0] <= b0_b[{2'd0, col}];
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m_in_a[1] <= b0_a[{row, 2'd1}]; m_in_b[1] <= b0_b[{2'd1, col}];
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m_in_a[2] <= b0_a[{row, 2'd2}]; m_in_b[2] <= b0_b[{2'd2, col}];
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m_in_a[3] <= b0_a[{row, 2'd3}]; m_in_b[3] <= b0_b[{2'd3, col}];
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end else begin
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m_in_a[0] <= b1_a[{row, 2'd0}]; m_in_b[0] <= b1_b[{2'd0, col}];
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m_in_a[1] <= b1_a[{row, 2'd1}]; m_in_b[1] <= b1_b[{2'd1, col}];
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m_in_a[2] <= b1_a[{row, 2'd2}]; m_in_b[2] <= b1_b[{2'd2, col}];
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m_in_a[3] <= b1_a[{row, 2'd3}]; m_in_b[3] <= b1_b[{2'd3, col}];
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end
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mult_start <= 1'b1;
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state <= C_WAIT_MULT;
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end
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C_WAIT_MULT: begin
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mult_start <= 1'b0;
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// 4个乘法器同时启动，监控第一个即可
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if (mult_done[0]) begin
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state <= C_ACCUM;
|
||
end
|
||
end
|
||
|
||
C_ACCUM: begin
|
||
if (cur_bank == 1'b0) begin
|
||
b0_c[calc_idx] <= {2'b0, mult_p[0]} + {2'b0, mult_p[1]} +
|
||
{2'b0, mult_p[2]} + {2'b0, mult_p[3]};
|
||
end else begin
|
||
b1_c[calc_idx] <= {2'b0, mult_p[0]} + {2'b0, mult_p[1]} +
|
||
{2'b0, mult_p[2]} + {2'b0, mult_p[3]};
|
||
end
|
||
|
||
if (calc_idx == 4'd15) begin
|
||
calc_done_pulse <= 1'b1;
|
||
busy <= 1'b0;
|
||
state <= C_IDLE;
|
||
end else begin
|
||
calc_idx <= calc_idx + 4'd1;
|
||
state <= C_CALC;
|
||
end
|
||
end
|
||
endcase
|
||
end
|
||
end
|
||
|
||
endmodule |