26093 lines
2.4 MiB
26093 lines
2.4 MiB
Copyright 1986-2019 Xilinx, Inc. All Rights Reserved.
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| Tool Version : Vivado v.2019.2 (lin64) Build 2708876 Wed Nov 6 21:39:14 MST 2019
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| Date : Fri Jul 10 04:14:53 2026
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| Host : fedora running 64-bit unknown
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| Command : report_timing -delay_type max -sort_by group -max_paths 100 -nworst 10 -path_type full -input_pins -file /home/fallensigh/Dev/ciciec2026_loongson_regional/fpga/vivado_reports_nodsp/timing_setup_paths.rpt
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| Design : soc_top
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| Device : 7a200t-fbg676
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| Speed File : -1 PRODUCTION 1.23 2018-06-13
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Timing Report
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Slack (MET) : 0.146ns (required time - arrival time)
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Source: u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[3]/C
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(rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
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Destination: base_ram_be_n[3]
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(output port clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
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Path Group: sys_clk
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Path Type: Max at Slow Process Corner
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Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns)
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Data Path Delay: 15.529ns (logic 6.868ns (44.228%) route 8.661ns (55.772%))
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Logic Levels: 14 (CARRY4=6 LUT4=2 LUT5=1 LUT6=4 OBUF=1)
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Output Delay: 0.300ns
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Clock Path Skew: -3.955ns (DCD - SCD + CPR)
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Destination Clock Delay (DCD): -5.674ns = ( 14.326 - 20.000 )
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Source Clock Delay (SCD): -2.321ns
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Clock Pessimism Removal (CPR): -0.601ns
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Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
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Total System Jitter (TSJ): 0.071ns
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Discrete Jitter (DJ): 0.122ns
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Phase Error (PE): 0.000ns
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Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
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------------------------------------------------------------------- -------------------
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(clock sys_clk rise edge) 0.000 0.000 r
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clock source latency -6.275 -6.275
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propagated clock network latency
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3.955 -2.321
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SLICE_X7Y62 FDCE 0.000 -2.321 r u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[3]/C
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SLICE_X7Y62 FDCE (Prop_fdce_C_Q) 0.456 -1.865 f u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[3]/Q
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net (fo=54, routed) 0.726 -1.139 u_axi_ram/u_axi_sram_sp/len[3]
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SLICE_X7Y61 f u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6/I3
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SLICE_X7Y61 LUT4 (Prop_lut4_I3_O) 0.124 -1.015 r u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6/O
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net (fo=4, routed) 0.946 -0.068 u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6_n_0
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SLICE_X7Y58 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_11/I1
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SLICE_X7Y58 LUT5 (Prop_lut5_I1_O) 0.124 0.056 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_11/O
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net (fo=2, routed) 0.619 0.675 u_axi_ram/u_axi_sram_sp/state_d2[7]
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SLICE_X6Y59 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_15/I5
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SLICE_X6Y59 LUT6 (Prop_lut6_I5_O) 0.124 0.799 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_15/O
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net (fo=1, routed) 0.000 0.799 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_15_n_0
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SLICE_X6Y59 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9/S[3]
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SLICE_X6Y59 CARRY4 (Prop_carry4_S[3]_CO[3])
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0.376 1.175 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9/CO[3]
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net (fo=1, routed) 0.000 1.175 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9_n_0
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SLICE_X6Y60 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/CI
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SLICE_X6Y60 CARRY4 (Prop_carry4_CI_CO[3])
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0.117 1.292 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/CO[3]
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net (fo=1, routed) 0.000 1.292 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10_n_0
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SLICE_X6Y61 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CI
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SLICE_X6Y61 CARRY4 (Prop_carry4_CI_CO[3])
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0.117 1.409 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CO[3]
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net (fo=1, routed) 0.000 1.409 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9_n_0
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SLICE_X6Y62 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/CI
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SLICE_X6Y62 CARRY4 (Prop_carry4_CI_O[2])
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0.239 1.648 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/O[2]
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net (fo=3, routed) 0.929 2.576 u_axi_ram/u_axi_sram_sp/upper_wrap_boundary[20]
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SLICE_X5Y65 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_7/I2
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SLICE_X5Y65 LUT4 (Prop_lut4_I2_O) 0.301 2.877 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_7/O
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net (fo=1, routed) 0.000 2.877 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_7_n_0
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SLICE_X5Y65 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1/S[1]
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SLICE_X5Y65 CARRY4 (Prop_carry4_S[1]_CO[3])
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0.550 3.427 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1/CO[3]
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net (fo=1, routed) 0.000 3.427 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_n_0
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SLICE_X5Y66 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2/CI
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SLICE_X5Y66 CARRY4 (Prop_carry4_CI_CO[2])
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0.228 3.655 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2/CO[2]
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net (fo=22, routed) 0.735 4.390 u_axi_ram/u_axi_sram_sp/req_addr_d1
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SLICE_X5Y68 r u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/I0
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SLICE_X5Y68 LUT6 (Prop_lut6_I0_O) 0.313 4.703 r u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/O
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net (fo=2, routed) 0.550 5.253 u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7_n_0
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SLICE_X4Y68 r u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/I1
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SLICE_X4Y68 LUT6 (Prop_lut6_I1_O) 0.124 5.377 r u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/O
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net (fo=80, routed) 1.092 6.469 u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/soc_sram_addr[0]
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SLICE_X0Y77 r u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/base_ram_be_n_OBUF[3]_inst_i_1/I5
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SLICE_X0Y77 LUT6 (Prop_lut6_I5_O) 0.124 6.593 r u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/base_ram_be_n_OBUF[3]_inst_i_1/O
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net (fo=1, routed) 3.064 9.657 base_ram_be_n_OBUF[3]
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K25 r base_ram_be_n_OBUF[3]_inst/I
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K25 OBUF (Prop_obuf_I_O) 3.551 13.208 r base_ram_be_n_OBUF[3]_inst/O
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net (fo=0) 0.000 13.208 base_ram_be_n[3]
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K25 r base_ram_be_n[3] (OUT)
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------------------------------------------------------------------- -------------------
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(clock sys_clk rise edge) 20.000 20.000 r
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clock source latency -5.674 14.326
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propagated clock network latency
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0.000 14.326
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clock pessimism -0.601 13.725
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clock uncertainty -0.071 13.654
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output delay -0.300 13.354
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-------------------------------------------------------------------
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required time 13.354
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arrival time -13.208
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-------------------------------------------------------------------
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slack 0.146
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Slack (MET) : 0.146ns (required time - arrival time)
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Source: u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[3]/C
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(rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
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Destination: base_ram_be_n[3]
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(output port clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
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Path Group: sys_clk
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Path Type: Max at Slow Process Corner
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Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns)
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Data Path Delay: 15.529ns (logic 6.868ns (44.228%) route 8.661ns (55.772%))
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Logic Levels: 14 (CARRY4=6 LUT4=2 LUT5=1 LUT6=4 OBUF=1)
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Output Delay: 0.300ns
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Clock Path Skew: -3.955ns (DCD - SCD + CPR)
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Destination Clock Delay (DCD): -5.674ns = ( 14.326 - 20.000 )
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Source Clock Delay (SCD): -2.321ns
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Clock Pessimism Removal (CPR): -0.601ns
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Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
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Total System Jitter (TSJ): 0.071ns
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Discrete Jitter (DJ): 0.122ns
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Phase Error (PE): 0.000ns
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Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
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------------------------------------------------------------------- -------------------
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(clock sys_clk rise edge) 0.000 0.000 r
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clock source latency -6.275 -6.275
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propagated clock network latency
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3.955 -2.321
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SLICE_X7Y62 FDCE 0.000 -2.321 r u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[3]/C
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SLICE_X7Y62 FDCE (Prop_fdce_C_Q) 0.456 -1.865 f u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[3]/Q
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net (fo=54, routed) 0.726 -1.139 u_axi_ram/u_axi_sram_sp/len[3]
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SLICE_X7Y61 f u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6/I3
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SLICE_X7Y61 LUT4 (Prop_lut4_I3_O) 0.124 -1.015 r u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6/O
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net (fo=4, routed) 0.946 -0.068 u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6_n_0
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SLICE_X7Y58 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_11/I1
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SLICE_X7Y58 LUT5 (Prop_lut5_I1_O) 0.124 0.056 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_11/O
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net (fo=2, routed) 0.619 0.675 u_axi_ram/u_axi_sram_sp/state_d2[7]
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SLICE_X6Y59 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_15/I5
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SLICE_X6Y59 LUT6 (Prop_lut6_I5_O) 0.124 0.799 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_15/O
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net (fo=1, routed) 0.000 0.799 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_15_n_0
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SLICE_X6Y59 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9/S[3]
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SLICE_X6Y59 CARRY4 (Prop_carry4_S[3]_CO[3])
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0.376 1.175 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9/CO[3]
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net (fo=1, routed) 0.000 1.175 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9_n_0
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SLICE_X6Y60 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/CI
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SLICE_X6Y60 CARRY4 (Prop_carry4_CI_CO[3])
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0.117 1.292 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/CO[3]
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net (fo=1, routed) 0.000 1.292 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10_n_0
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SLICE_X6Y61 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CI
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SLICE_X6Y61 CARRY4 (Prop_carry4_CI_CO[3])
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0.117 1.409 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CO[3]
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net (fo=1, routed) 0.000 1.409 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9_n_0
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SLICE_X6Y62 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/CI
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SLICE_X6Y62 CARRY4 (Prop_carry4_CI_O[2])
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0.239 1.648 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/O[2]
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net (fo=3, routed) 0.929 2.576 u_axi_ram/u_axi_sram_sp/upper_wrap_boundary[20]
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SLICE_X5Y65 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_7/I2
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SLICE_X5Y65 LUT4 (Prop_lut4_I2_O) 0.301 2.877 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_7/O
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net (fo=1, routed) 0.000 2.877 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_7_n_0
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SLICE_X5Y65 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1/S[1]
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SLICE_X5Y65 CARRY4 (Prop_carry4_S[1]_CO[3])
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0.550 3.427 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1/CO[3]
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net (fo=1, routed) 0.000 3.427 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_n_0
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SLICE_X5Y66 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2/CI
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SLICE_X5Y66 CARRY4 (Prop_carry4_CI_CO[2])
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0.228 3.655 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2/CO[2]
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net (fo=22, routed) 0.735 4.390 u_axi_ram/u_axi_sram_sp/req_addr_d1
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SLICE_X5Y68 r u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/I0
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SLICE_X5Y68 LUT6 (Prop_lut6_I0_O) 0.313 4.703 r u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/O
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net (fo=2, routed) 0.550 5.253 u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7_n_0
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SLICE_X4Y68 r u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/I1
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SLICE_X4Y68 LUT6 (Prop_lut6_I1_O) 0.124 5.377 r u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/O
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net (fo=80, routed) 1.092 6.469 u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/soc_sram_addr[0]
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SLICE_X0Y77 r u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/base_ram_be_n_OBUF[3]_inst_i_1/I5
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SLICE_X0Y77 LUT6 (Prop_lut6_I5_O) 0.124 6.593 r u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/base_ram_be_n_OBUF[3]_inst_i_1/O
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net (fo=1, routed) 3.064 9.657 base_ram_be_n_OBUF[3]
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K25 r base_ram_be_n_OBUF[3]_inst/I
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K25 OBUF (Prop_obuf_I_O) 3.551 13.208 r base_ram_be_n_OBUF[3]_inst/O
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net (fo=0) 0.000 13.208 base_ram_be_n[3]
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K25 r base_ram_be_n[3] (OUT)
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------------------------------------------------------------------- -------------------
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(clock sys_clk rise edge) 20.000 20.000 r
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clock source latency -5.674 14.326
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propagated clock network latency
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0.000 14.326
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clock pessimism -0.601 13.725
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clock uncertainty -0.071 13.654
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output delay -0.300 13.354
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-------------------------------------------------------------------
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required time 13.354
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arrival time -13.208
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-------------------------------------------------------------------
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slack 0.146
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Slack (MET) : 0.146ns (required time - arrival time)
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Source: u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[3]/C
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(rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
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Destination: base_ram_be_n[3]
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(output port clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
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Path Group: sys_clk
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Path Type: Max at Slow Process Corner
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Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns)
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Data Path Delay: 15.529ns (logic 6.868ns (44.228%) route 8.661ns (55.772%))
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Logic Levels: 14 (CARRY4=6 LUT4=2 LUT5=1 LUT6=4 OBUF=1)
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Output Delay: 0.300ns
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Clock Path Skew: -3.955ns (DCD - SCD + CPR)
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Destination Clock Delay (DCD): -5.674ns = ( 14.326 - 20.000 )
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Source Clock Delay (SCD): -2.321ns
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Clock Pessimism Removal (CPR): -0.601ns
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Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
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Total System Jitter (TSJ): 0.071ns
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Discrete Jitter (DJ): 0.122ns
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Phase Error (PE): 0.000ns
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Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
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------------------------------------------------------------------- -------------------
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(clock sys_clk rise edge) 0.000 0.000 r
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clock source latency -6.275 -6.275
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propagated clock network latency
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3.955 -2.321
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SLICE_X7Y62 FDCE 0.000 -2.321 r u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[3]/C
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SLICE_X7Y62 FDCE (Prop_fdce_C_Q) 0.456 -1.865 f u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[3]/Q
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net (fo=54, routed) 0.726 -1.139 u_axi_ram/u_axi_sram_sp/len[3]
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SLICE_X7Y61 f u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6/I3
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SLICE_X7Y61 LUT4 (Prop_lut4_I3_O) 0.124 -1.015 r u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6/O
|
|
net (fo=4, routed) 0.946 -0.068 u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6_n_0
|
|
SLICE_X7Y58 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_11/I1
|
|
SLICE_X7Y58 LUT5 (Prop_lut5_I1_O) 0.124 0.056 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_11/O
|
|
net (fo=2, routed) 0.619 0.675 u_axi_ram/u_axi_sram_sp/state_d2[7]
|
|
SLICE_X6Y59 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_15/I5
|
|
SLICE_X6Y59 LUT6 (Prop_lut6_I5_O) 0.124 0.799 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_15/O
|
|
net (fo=1, routed) 0.000 0.799 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_15_n_0
|
|
SLICE_X6Y59 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9/S[3]
|
|
SLICE_X6Y59 CARRY4 (Prop_carry4_S[3]_CO[3])
|
|
0.376 1.175 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9/CO[3]
|
|
net (fo=1, routed) 0.000 1.175 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9_n_0
|
|
SLICE_X6Y60 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/CI
|
|
SLICE_X6Y60 CARRY4 (Prop_carry4_CI_CO[3])
|
|
0.117 1.292 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/CO[3]
|
|
net (fo=1, routed) 0.000 1.292 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10_n_0
|
|
SLICE_X6Y61 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CI
|
|
SLICE_X6Y61 CARRY4 (Prop_carry4_CI_CO[3])
|
|
0.117 1.409 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CO[3]
|
|
net (fo=1, routed) 0.000 1.409 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9_n_0
|
|
SLICE_X6Y62 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/CI
|
|
SLICE_X6Y62 CARRY4 (Prop_carry4_CI_O[2])
|
|
0.239 1.648 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/O[2]
|
|
net (fo=3, routed) 0.929 2.576 u_axi_ram/u_axi_sram_sp/upper_wrap_boundary[20]
|
|
SLICE_X5Y65 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_7/I2
|
|
SLICE_X5Y65 LUT4 (Prop_lut4_I2_O) 0.301 2.877 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_7/O
|
|
net (fo=1, routed) 0.000 2.877 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_7_n_0
|
|
SLICE_X5Y65 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1/S[1]
|
|
SLICE_X5Y65 CARRY4 (Prop_carry4_S[1]_CO[3])
|
|
0.550 3.427 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1/CO[3]
|
|
net (fo=1, routed) 0.000 3.427 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_n_0
|
|
SLICE_X5Y66 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2/CI
|
|
SLICE_X5Y66 CARRY4 (Prop_carry4_CI_CO[2])
|
|
0.228 3.655 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2/CO[2]
|
|
net (fo=22, routed) 0.735 4.390 u_axi_ram/u_axi_sram_sp/req_addr_d1
|
|
SLICE_X5Y68 r u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/I0
|
|
SLICE_X5Y68 LUT6 (Prop_lut6_I0_O) 0.313 4.703 r u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/O
|
|
net (fo=2, routed) 0.550 5.253 u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7_n_0
|
|
SLICE_X4Y68 r u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/I1
|
|
SLICE_X4Y68 LUT6 (Prop_lut6_I1_O) 0.124 5.377 r u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/O
|
|
net (fo=80, routed) 1.092 6.469 u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/soc_sram_addr[0]
|
|
SLICE_X0Y77 r u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/base_ram_be_n_OBUF[3]_inst_i_1/I5
|
|
SLICE_X0Y77 LUT6 (Prop_lut6_I5_O) 0.124 6.593 r u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/base_ram_be_n_OBUF[3]_inst_i_1/O
|
|
net (fo=1, routed) 3.064 9.657 base_ram_be_n_OBUF[3]
|
|
K25 r base_ram_be_n_OBUF[3]_inst/I
|
|
K25 OBUF (Prop_obuf_I_O) 3.551 13.208 r base_ram_be_n_OBUF[3]_inst/O
|
|
net (fo=0) 0.000 13.208 base_ram_be_n[3]
|
|
K25 r base_ram_be_n[3] (OUT)
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock sys_clk rise edge) 20.000 20.000 r
|
|
clock source latency -5.674 14.326
|
|
propagated clock network latency
|
|
0.000 14.326
|
|
clock pessimism -0.601 13.725
|
|
clock uncertainty -0.071 13.654
|
|
output delay -0.300 13.354
|
|
-------------------------------------------------------------------
|
|
required time 13.354
|
|
arrival time -13.208
|
|
-------------------------------------------------------------------
|
|
slack 0.146
|
|
|
|
Slack (MET) : 0.146ns (required time - arrival time)
|
|
Source: u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[3]/C
|
|
(rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Destination: base_ram_be_n[3]
|
|
(output port clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Path Group: sys_clk
|
|
Path Type: Max at Slow Process Corner
|
|
Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns)
|
|
Data Path Delay: 15.529ns (logic 6.868ns (44.228%) route 8.661ns (55.772%))
|
|
Logic Levels: 14 (CARRY4=6 LUT4=2 LUT5=1 LUT6=4 OBUF=1)
|
|
Output Delay: 0.300ns
|
|
Clock Path Skew: -3.955ns (DCD - SCD + CPR)
|
|
Destination Clock Delay (DCD): -5.674ns = ( 14.326 - 20.000 )
|
|
Source Clock Delay (SCD): -2.321ns
|
|
Clock Pessimism Removal (CPR): -0.601ns
|
|
Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Discrete Jitter (DJ): 0.122ns
|
|
Phase Error (PE): 0.000ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock sys_clk rise edge) 0.000 0.000 r
|
|
clock source latency -6.275 -6.275
|
|
propagated clock network latency
|
|
3.955 -2.321
|
|
SLICE_X7Y62 FDCE 0.000 -2.321 r u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[3]/C
|
|
SLICE_X7Y62 FDCE (Prop_fdce_C_Q) 0.456 -1.865 f u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[3]/Q
|
|
net (fo=54, routed) 0.726 -1.139 u_axi_ram/u_axi_sram_sp/len[3]
|
|
SLICE_X7Y61 f u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6/I3
|
|
SLICE_X7Y61 LUT4 (Prop_lut4_I3_O) 0.124 -1.015 r u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6/O
|
|
net (fo=4, routed) 0.946 -0.068 u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6_n_0
|
|
SLICE_X7Y58 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_11/I1
|
|
SLICE_X7Y58 LUT5 (Prop_lut5_I1_O) 0.124 0.056 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_11/O
|
|
net (fo=2, routed) 0.619 0.675 u_axi_ram/u_axi_sram_sp/state_d2[7]
|
|
SLICE_X6Y59 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_15/I5
|
|
SLICE_X6Y59 LUT6 (Prop_lut6_I5_O) 0.124 0.799 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_15/O
|
|
net (fo=1, routed) 0.000 0.799 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_15_n_0
|
|
SLICE_X6Y59 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9/S[3]
|
|
SLICE_X6Y59 CARRY4 (Prop_carry4_S[3]_CO[3])
|
|
0.376 1.175 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9/CO[3]
|
|
net (fo=1, routed) 0.000 1.175 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9_n_0
|
|
SLICE_X6Y60 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/CI
|
|
SLICE_X6Y60 CARRY4 (Prop_carry4_CI_CO[3])
|
|
0.117 1.292 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/CO[3]
|
|
net (fo=1, routed) 0.000 1.292 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10_n_0
|
|
SLICE_X6Y61 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CI
|
|
SLICE_X6Y61 CARRY4 (Prop_carry4_CI_CO[3])
|
|
0.117 1.409 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CO[3]
|
|
net (fo=1, routed) 0.000 1.409 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9_n_0
|
|
SLICE_X6Y62 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/CI
|
|
SLICE_X6Y62 CARRY4 (Prop_carry4_CI_O[2])
|
|
0.239 1.648 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/O[2]
|
|
net (fo=3, routed) 0.929 2.576 u_axi_ram/u_axi_sram_sp/upper_wrap_boundary[20]
|
|
SLICE_X5Y65 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_7/I2
|
|
SLICE_X5Y65 LUT4 (Prop_lut4_I2_O) 0.301 2.877 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_7/O
|
|
net (fo=1, routed) 0.000 2.877 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_7_n_0
|
|
SLICE_X5Y65 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1/S[1]
|
|
SLICE_X5Y65 CARRY4 (Prop_carry4_S[1]_CO[3])
|
|
0.550 3.427 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1/CO[3]
|
|
net (fo=1, routed) 0.000 3.427 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_n_0
|
|
SLICE_X5Y66 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2/CI
|
|
SLICE_X5Y66 CARRY4 (Prop_carry4_CI_CO[2])
|
|
0.228 3.655 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2/CO[2]
|
|
net (fo=22, routed) 0.735 4.390 u_axi_ram/u_axi_sram_sp/req_addr_d1
|
|
SLICE_X5Y68 r u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/I0
|
|
SLICE_X5Y68 LUT6 (Prop_lut6_I0_O) 0.313 4.703 r u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/O
|
|
net (fo=2, routed) 0.550 5.253 u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7_n_0
|
|
SLICE_X4Y68 r u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/I1
|
|
SLICE_X4Y68 LUT6 (Prop_lut6_I1_O) 0.124 5.377 r u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/O
|
|
net (fo=80, routed) 1.092 6.469 u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/soc_sram_addr[0]
|
|
SLICE_X0Y77 r u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/base_ram_be_n_OBUF[3]_inst_i_1/I5
|
|
SLICE_X0Y77 LUT6 (Prop_lut6_I5_O) 0.124 6.593 r u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/base_ram_be_n_OBUF[3]_inst_i_1/O
|
|
net (fo=1, routed) 3.064 9.657 base_ram_be_n_OBUF[3]
|
|
K25 r base_ram_be_n_OBUF[3]_inst/I
|
|
K25 OBUF (Prop_obuf_I_O) 3.551 13.208 r base_ram_be_n_OBUF[3]_inst/O
|
|
net (fo=0) 0.000 13.208 base_ram_be_n[3]
|
|
K25 r base_ram_be_n[3] (OUT)
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock sys_clk rise edge) 20.000 20.000 r
|
|
clock source latency -5.674 14.326
|
|
propagated clock network latency
|
|
0.000 14.326
|
|
clock pessimism -0.601 13.725
|
|
clock uncertainty -0.071 13.654
|
|
output delay -0.300 13.354
|
|
-------------------------------------------------------------------
|
|
required time 13.354
|
|
arrival time -13.208
|
|
-------------------------------------------------------------------
|
|
slack 0.146
|
|
|
|
Slack (MET) : 0.146ns (required time - arrival time)
|
|
Source: u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[3]/C
|
|
(rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Destination: base_ram_be_n[3]
|
|
(output port clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Path Group: sys_clk
|
|
Path Type: Max at Slow Process Corner
|
|
Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns)
|
|
Data Path Delay: 15.529ns (logic 6.868ns (44.228%) route 8.661ns (55.772%))
|
|
Logic Levels: 14 (CARRY4=6 LUT4=2 LUT5=1 LUT6=4 OBUF=1)
|
|
Output Delay: 0.300ns
|
|
Clock Path Skew: -3.955ns (DCD - SCD + CPR)
|
|
Destination Clock Delay (DCD): -5.674ns = ( 14.326 - 20.000 )
|
|
Source Clock Delay (SCD): -2.321ns
|
|
Clock Pessimism Removal (CPR): -0.601ns
|
|
Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Discrete Jitter (DJ): 0.122ns
|
|
Phase Error (PE): 0.000ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock sys_clk rise edge) 0.000 0.000 r
|
|
clock source latency -6.275 -6.275
|
|
propagated clock network latency
|
|
3.955 -2.321
|
|
SLICE_X7Y62 FDCE 0.000 -2.321 r u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[3]/C
|
|
SLICE_X7Y62 FDCE (Prop_fdce_C_Q) 0.456 -1.865 f u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[3]/Q
|
|
net (fo=54, routed) 0.726 -1.139 u_axi_ram/u_axi_sram_sp/len[3]
|
|
SLICE_X7Y61 f u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6/I3
|
|
SLICE_X7Y61 LUT4 (Prop_lut4_I3_O) 0.124 -1.015 r u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6/O
|
|
net (fo=4, routed) 0.946 -0.068 u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6_n_0
|
|
SLICE_X7Y58 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_11/I1
|
|
SLICE_X7Y58 LUT5 (Prop_lut5_I1_O) 0.124 0.056 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_11/O
|
|
net (fo=2, routed) 0.619 0.675 u_axi_ram/u_axi_sram_sp/state_d2[7]
|
|
SLICE_X6Y59 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_15/I5
|
|
SLICE_X6Y59 LUT6 (Prop_lut6_I5_O) 0.124 0.799 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_15/O
|
|
net (fo=1, routed) 0.000 0.799 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_15_n_0
|
|
SLICE_X6Y59 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9/S[3]
|
|
SLICE_X6Y59 CARRY4 (Prop_carry4_S[3]_CO[3])
|
|
0.376 1.175 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9/CO[3]
|
|
net (fo=1, routed) 0.000 1.175 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9_n_0
|
|
SLICE_X6Y60 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/CI
|
|
SLICE_X6Y60 CARRY4 (Prop_carry4_CI_CO[3])
|
|
0.117 1.292 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/CO[3]
|
|
net (fo=1, routed) 0.000 1.292 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10_n_0
|
|
SLICE_X6Y61 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CI
|
|
SLICE_X6Y61 CARRY4 (Prop_carry4_CI_CO[3])
|
|
0.117 1.409 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CO[3]
|
|
net (fo=1, routed) 0.000 1.409 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9_n_0
|
|
SLICE_X6Y62 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/CI
|
|
SLICE_X6Y62 CARRY4 (Prop_carry4_CI_O[2])
|
|
0.239 1.648 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/O[2]
|
|
net (fo=3, routed) 0.929 2.576 u_axi_ram/u_axi_sram_sp/upper_wrap_boundary[20]
|
|
SLICE_X5Y65 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_7/I2
|
|
SLICE_X5Y65 LUT4 (Prop_lut4_I2_O) 0.301 2.877 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_7/O
|
|
net (fo=1, routed) 0.000 2.877 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_7_n_0
|
|
SLICE_X5Y65 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1/S[1]
|
|
SLICE_X5Y65 CARRY4 (Prop_carry4_S[1]_CO[3])
|
|
0.550 3.427 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1/CO[3]
|
|
net (fo=1, routed) 0.000 3.427 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_n_0
|
|
SLICE_X5Y66 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2/CI
|
|
SLICE_X5Y66 CARRY4 (Prop_carry4_CI_CO[2])
|
|
0.228 3.655 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2/CO[2]
|
|
net (fo=22, routed) 0.735 4.390 u_axi_ram/u_axi_sram_sp/req_addr_d1
|
|
SLICE_X5Y68 r u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/I0
|
|
SLICE_X5Y68 LUT6 (Prop_lut6_I0_O) 0.313 4.703 r u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/O
|
|
net (fo=2, routed) 0.550 5.253 u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7_n_0
|
|
SLICE_X4Y68 r u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/I1
|
|
SLICE_X4Y68 LUT6 (Prop_lut6_I1_O) 0.124 5.377 r u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/O
|
|
net (fo=80, routed) 1.092 6.469 u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/soc_sram_addr[0]
|
|
SLICE_X0Y77 r u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/base_ram_be_n_OBUF[3]_inst_i_1/I5
|
|
SLICE_X0Y77 LUT6 (Prop_lut6_I5_O) 0.124 6.593 r u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/base_ram_be_n_OBUF[3]_inst_i_1/O
|
|
net (fo=1, routed) 3.064 9.657 base_ram_be_n_OBUF[3]
|
|
K25 r base_ram_be_n_OBUF[3]_inst/I
|
|
K25 OBUF (Prop_obuf_I_O) 3.551 13.208 r base_ram_be_n_OBUF[3]_inst/O
|
|
net (fo=0) 0.000 13.208 base_ram_be_n[3]
|
|
K25 r base_ram_be_n[3] (OUT)
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock sys_clk rise edge) 20.000 20.000 r
|
|
clock source latency -5.674 14.326
|
|
propagated clock network latency
|
|
0.000 14.326
|
|
clock pessimism -0.601 13.725
|
|
clock uncertainty -0.071 13.654
|
|
output delay -0.300 13.354
|
|
-------------------------------------------------------------------
|
|
required time 13.354
|
|
arrival time -13.208
|
|
-------------------------------------------------------------------
|
|
slack 0.146
|
|
|
|
Slack (MET) : 0.146ns (required time - arrival time)
|
|
Source: u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[3]/C
|
|
(rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Destination: base_ram_be_n[3]
|
|
(output port clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Path Group: sys_clk
|
|
Path Type: Max at Slow Process Corner
|
|
Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns)
|
|
Data Path Delay: 15.529ns (logic 6.868ns (44.228%) route 8.661ns (55.772%))
|
|
Logic Levels: 14 (CARRY4=6 LUT4=2 LUT5=1 LUT6=4 OBUF=1)
|
|
Output Delay: 0.300ns
|
|
Clock Path Skew: -3.955ns (DCD - SCD + CPR)
|
|
Destination Clock Delay (DCD): -5.674ns = ( 14.326 - 20.000 )
|
|
Source Clock Delay (SCD): -2.321ns
|
|
Clock Pessimism Removal (CPR): -0.601ns
|
|
Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Discrete Jitter (DJ): 0.122ns
|
|
Phase Error (PE): 0.000ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock sys_clk rise edge) 0.000 0.000 r
|
|
clock source latency -6.275 -6.275
|
|
propagated clock network latency
|
|
3.955 -2.321
|
|
SLICE_X7Y62 FDCE 0.000 -2.321 r u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[3]/C
|
|
SLICE_X7Y62 FDCE (Prop_fdce_C_Q) 0.456 -1.865 f u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[3]/Q
|
|
net (fo=54, routed) 0.726 -1.139 u_axi_ram/u_axi_sram_sp/len[3]
|
|
SLICE_X7Y61 f u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6/I3
|
|
SLICE_X7Y61 LUT4 (Prop_lut4_I3_O) 0.124 -1.015 r u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6/O
|
|
net (fo=4, routed) 0.946 -0.068 u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6_n_0
|
|
SLICE_X7Y58 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_11/I1
|
|
SLICE_X7Y58 LUT5 (Prop_lut5_I1_O) 0.124 0.056 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_11/O
|
|
net (fo=2, routed) 0.619 0.675 u_axi_ram/u_axi_sram_sp/state_d2[7]
|
|
SLICE_X6Y59 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_15/I5
|
|
SLICE_X6Y59 LUT6 (Prop_lut6_I5_O) 0.124 0.799 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_15/O
|
|
net (fo=1, routed) 0.000 0.799 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_15_n_0
|
|
SLICE_X6Y59 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9/S[3]
|
|
SLICE_X6Y59 CARRY4 (Prop_carry4_S[3]_CO[3])
|
|
0.376 1.175 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9/CO[3]
|
|
net (fo=1, routed) 0.000 1.175 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9_n_0
|
|
SLICE_X6Y60 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/CI
|
|
SLICE_X6Y60 CARRY4 (Prop_carry4_CI_CO[3])
|
|
0.117 1.292 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/CO[3]
|
|
net (fo=1, routed) 0.000 1.292 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10_n_0
|
|
SLICE_X6Y61 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CI
|
|
SLICE_X6Y61 CARRY4 (Prop_carry4_CI_CO[3])
|
|
0.117 1.409 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CO[3]
|
|
net (fo=1, routed) 0.000 1.409 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9_n_0
|
|
SLICE_X6Y62 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/CI
|
|
SLICE_X6Y62 CARRY4 (Prop_carry4_CI_O[2])
|
|
0.239 1.648 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/O[2]
|
|
net (fo=3, routed) 0.929 2.576 u_axi_ram/u_axi_sram_sp/upper_wrap_boundary[20]
|
|
SLICE_X5Y65 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_7/I2
|
|
SLICE_X5Y65 LUT4 (Prop_lut4_I2_O) 0.301 2.877 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_7/O
|
|
net (fo=1, routed) 0.000 2.877 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_7_n_0
|
|
SLICE_X5Y65 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1/S[1]
|
|
SLICE_X5Y65 CARRY4 (Prop_carry4_S[1]_CO[3])
|
|
0.550 3.427 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1/CO[3]
|
|
net (fo=1, routed) 0.000 3.427 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_n_0
|
|
SLICE_X5Y66 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2/CI
|
|
SLICE_X5Y66 CARRY4 (Prop_carry4_CI_CO[2])
|
|
0.228 3.655 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2/CO[2]
|
|
net (fo=22, routed) 0.735 4.390 u_axi_ram/u_axi_sram_sp/req_addr_d1
|
|
SLICE_X5Y68 r u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/I0
|
|
SLICE_X5Y68 LUT6 (Prop_lut6_I0_O) 0.313 4.703 r u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/O
|
|
net (fo=2, routed) 0.550 5.253 u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7_n_0
|
|
SLICE_X4Y68 r u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/I1
|
|
SLICE_X4Y68 LUT6 (Prop_lut6_I1_O) 0.124 5.377 r u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/O
|
|
net (fo=80, routed) 1.092 6.469 u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/soc_sram_addr[0]
|
|
SLICE_X0Y77 r u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/base_ram_be_n_OBUF[3]_inst_i_1/I5
|
|
SLICE_X0Y77 LUT6 (Prop_lut6_I5_O) 0.124 6.593 r u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/base_ram_be_n_OBUF[3]_inst_i_1/O
|
|
net (fo=1, routed) 3.064 9.657 base_ram_be_n_OBUF[3]
|
|
K25 r base_ram_be_n_OBUF[3]_inst/I
|
|
K25 OBUF (Prop_obuf_I_O) 3.551 13.208 r base_ram_be_n_OBUF[3]_inst/O
|
|
net (fo=0) 0.000 13.208 base_ram_be_n[3]
|
|
K25 r base_ram_be_n[3] (OUT)
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock sys_clk rise edge) 20.000 20.000 r
|
|
clock source latency -5.674 14.326
|
|
propagated clock network latency
|
|
0.000 14.326
|
|
clock pessimism -0.601 13.725
|
|
clock uncertainty -0.071 13.654
|
|
output delay -0.300 13.354
|
|
-------------------------------------------------------------------
|
|
required time 13.354
|
|
arrival time -13.208
|
|
-------------------------------------------------------------------
|
|
slack 0.146
|
|
|
|
Slack (MET) : 0.146ns (required time - arrival time)
|
|
Source: u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[3]/C
|
|
(rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Destination: base_ram_be_n[3]
|
|
(output port clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Path Group: sys_clk
|
|
Path Type: Max at Slow Process Corner
|
|
Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns)
|
|
Data Path Delay: 15.529ns (logic 6.868ns (44.228%) route 8.661ns (55.772%))
|
|
Logic Levels: 14 (CARRY4=6 LUT4=2 LUT5=1 LUT6=4 OBUF=1)
|
|
Output Delay: 0.300ns
|
|
Clock Path Skew: -3.955ns (DCD - SCD + CPR)
|
|
Destination Clock Delay (DCD): -5.674ns = ( 14.326 - 20.000 )
|
|
Source Clock Delay (SCD): -2.321ns
|
|
Clock Pessimism Removal (CPR): -0.601ns
|
|
Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Discrete Jitter (DJ): 0.122ns
|
|
Phase Error (PE): 0.000ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock sys_clk rise edge) 0.000 0.000 r
|
|
clock source latency -6.275 -6.275
|
|
propagated clock network latency
|
|
3.955 -2.321
|
|
SLICE_X7Y62 FDCE 0.000 -2.321 r u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[3]/C
|
|
SLICE_X7Y62 FDCE (Prop_fdce_C_Q) 0.456 -1.865 f u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[3]/Q
|
|
net (fo=54, routed) 0.726 -1.139 u_axi_ram/u_axi_sram_sp/len[3]
|
|
SLICE_X7Y61 f u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6/I3
|
|
SLICE_X7Y61 LUT4 (Prop_lut4_I3_O) 0.124 -1.015 r u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6/O
|
|
net (fo=4, routed) 0.946 -0.068 u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6_n_0
|
|
SLICE_X7Y58 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_11/I1
|
|
SLICE_X7Y58 LUT5 (Prop_lut5_I1_O) 0.124 0.056 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_11/O
|
|
net (fo=2, routed) 0.619 0.675 u_axi_ram/u_axi_sram_sp/state_d2[7]
|
|
SLICE_X6Y59 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_15/I5
|
|
SLICE_X6Y59 LUT6 (Prop_lut6_I5_O) 0.124 0.799 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_15/O
|
|
net (fo=1, routed) 0.000 0.799 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_15_n_0
|
|
SLICE_X6Y59 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9/S[3]
|
|
SLICE_X6Y59 CARRY4 (Prop_carry4_S[3]_CO[3])
|
|
0.376 1.175 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9/CO[3]
|
|
net (fo=1, routed) 0.000 1.175 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9_n_0
|
|
SLICE_X6Y60 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/CI
|
|
SLICE_X6Y60 CARRY4 (Prop_carry4_CI_CO[3])
|
|
0.117 1.292 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/CO[3]
|
|
net (fo=1, routed) 0.000 1.292 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10_n_0
|
|
SLICE_X6Y61 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CI
|
|
SLICE_X6Y61 CARRY4 (Prop_carry4_CI_CO[3])
|
|
0.117 1.409 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CO[3]
|
|
net (fo=1, routed) 0.000 1.409 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9_n_0
|
|
SLICE_X6Y62 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/CI
|
|
SLICE_X6Y62 CARRY4 (Prop_carry4_CI_O[2])
|
|
0.239 1.648 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/O[2]
|
|
net (fo=3, routed) 0.929 2.576 u_axi_ram/u_axi_sram_sp/upper_wrap_boundary[20]
|
|
SLICE_X5Y65 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_7/I2
|
|
SLICE_X5Y65 LUT4 (Prop_lut4_I2_O) 0.301 2.877 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_7/O
|
|
net (fo=1, routed) 0.000 2.877 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_7_n_0
|
|
SLICE_X5Y65 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1/S[1]
|
|
SLICE_X5Y65 CARRY4 (Prop_carry4_S[1]_CO[3])
|
|
0.550 3.427 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1/CO[3]
|
|
net (fo=1, routed) 0.000 3.427 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_n_0
|
|
SLICE_X5Y66 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2/CI
|
|
SLICE_X5Y66 CARRY4 (Prop_carry4_CI_CO[2])
|
|
0.228 3.655 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2/CO[2]
|
|
net (fo=22, routed) 0.735 4.390 u_axi_ram/u_axi_sram_sp/req_addr_d1
|
|
SLICE_X5Y68 r u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/I0
|
|
SLICE_X5Y68 LUT6 (Prop_lut6_I0_O) 0.313 4.703 r u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/O
|
|
net (fo=2, routed) 0.550 5.253 u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7_n_0
|
|
SLICE_X4Y68 r u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/I1
|
|
SLICE_X4Y68 LUT6 (Prop_lut6_I1_O) 0.124 5.377 r u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/O
|
|
net (fo=80, routed) 1.092 6.469 u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/soc_sram_addr[0]
|
|
SLICE_X0Y77 r u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/base_ram_be_n_OBUF[3]_inst_i_1/I5
|
|
SLICE_X0Y77 LUT6 (Prop_lut6_I5_O) 0.124 6.593 r u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/base_ram_be_n_OBUF[3]_inst_i_1/O
|
|
net (fo=1, routed) 3.064 9.657 base_ram_be_n_OBUF[3]
|
|
K25 r base_ram_be_n_OBUF[3]_inst/I
|
|
K25 OBUF (Prop_obuf_I_O) 3.551 13.208 r base_ram_be_n_OBUF[3]_inst/O
|
|
net (fo=0) 0.000 13.208 base_ram_be_n[3]
|
|
K25 r base_ram_be_n[3] (OUT)
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock sys_clk rise edge) 20.000 20.000 r
|
|
clock source latency -5.674 14.326
|
|
propagated clock network latency
|
|
0.000 14.326
|
|
clock pessimism -0.601 13.725
|
|
clock uncertainty -0.071 13.654
|
|
output delay -0.300 13.354
|
|
-------------------------------------------------------------------
|
|
required time 13.354
|
|
arrival time -13.208
|
|
-------------------------------------------------------------------
|
|
slack 0.146
|
|
|
|
Slack (MET) : 0.146ns (required time - arrival time)
|
|
Source: u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[3]/C
|
|
(rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Destination: base_ram_be_n[3]
|
|
(output port clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Path Group: sys_clk
|
|
Path Type: Max at Slow Process Corner
|
|
Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns)
|
|
Data Path Delay: 15.529ns (logic 6.868ns (44.228%) route 8.661ns (55.772%))
|
|
Logic Levels: 14 (CARRY4=6 LUT4=2 LUT5=1 LUT6=4 OBUF=1)
|
|
Output Delay: 0.300ns
|
|
Clock Path Skew: -3.955ns (DCD - SCD + CPR)
|
|
Destination Clock Delay (DCD): -5.674ns = ( 14.326 - 20.000 )
|
|
Source Clock Delay (SCD): -2.321ns
|
|
Clock Pessimism Removal (CPR): -0.601ns
|
|
Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Discrete Jitter (DJ): 0.122ns
|
|
Phase Error (PE): 0.000ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock sys_clk rise edge) 0.000 0.000 r
|
|
clock source latency -6.275 -6.275
|
|
propagated clock network latency
|
|
3.955 -2.321
|
|
SLICE_X7Y62 FDCE 0.000 -2.321 r u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[3]/C
|
|
SLICE_X7Y62 FDCE (Prop_fdce_C_Q) 0.456 -1.865 f u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[3]/Q
|
|
net (fo=54, routed) 0.726 -1.139 u_axi_ram/u_axi_sram_sp/len[3]
|
|
SLICE_X7Y61 f u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6/I3
|
|
SLICE_X7Y61 LUT4 (Prop_lut4_I3_O) 0.124 -1.015 r u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6/O
|
|
net (fo=4, routed) 0.946 -0.068 u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6_n_0
|
|
SLICE_X7Y58 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_11/I1
|
|
SLICE_X7Y58 LUT5 (Prop_lut5_I1_O) 0.124 0.056 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_11/O
|
|
net (fo=2, routed) 0.619 0.675 u_axi_ram/u_axi_sram_sp/state_d2[7]
|
|
SLICE_X6Y59 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_15/I5
|
|
SLICE_X6Y59 LUT6 (Prop_lut6_I5_O) 0.124 0.799 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_15/O
|
|
net (fo=1, routed) 0.000 0.799 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_15_n_0
|
|
SLICE_X6Y59 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9/S[3]
|
|
SLICE_X6Y59 CARRY4 (Prop_carry4_S[3]_CO[3])
|
|
0.376 1.175 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9/CO[3]
|
|
net (fo=1, routed) 0.000 1.175 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9_n_0
|
|
SLICE_X6Y60 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/CI
|
|
SLICE_X6Y60 CARRY4 (Prop_carry4_CI_CO[3])
|
|
0.117 1.292 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/CO[3]
|
|
net (fo=1, routed) 0.000 1.292 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10_n_0
|
|
SLICE_X6Y61 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CI
|
|
SLICE_X6Y61 CARRY4 (Prop_carry4_CI_CO[3])
|
|
0.117 1.409 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CO[3]
|
|
net (fo=1, routed) 0.000 1.409 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9_n_0
|
|
SLICE_X6Y62 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/CI
|
|
SLICE_X6Y62 CARRY4 (Prop_carry4_CI_O[2])
|
|
0.239 1.648 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/O[2]
|
|
net (fo=3, routed) 0.929 2.576 u_axi_ram/u_axi_sram_sp/upper_wrap_boundary[20]
|
|
SLICE_X5Y65 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_7/I2
|
|
SLICE_X5Y65 LUT4 (Prop_lut4_I2_O) 0.301 2.877 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_7/O
|
|
net (fo=1, routed) 0.000 2.877 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_7_n_0
|
|
SLICE_X5Y65 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1/S[1]
|
|
SLICE_X5Y65 CARRY4 (Prop_carry4_S[1]_CO[3])
|
|
0.550 3.427 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1/CO[3]
|
|
net (fo=1, routed) 0.000 3.427 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_n_0
|
|
SLICE_X5Y66 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2/CI
|
|
SLICE_X5Y66 CARRY4 (Prop_carry4_CI_CO[2])
|
|
0.228 3.655 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2/CO[2]
|
|
net (fo=22, routed) 0.735 4.390 u_axi_ram/u_axi_sram_sp/req_addr_d1
|
|
SLICE_X5Y68 r u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/I0
|
|
SLICE_X5Y68 LUT6 (Prop_lut6_I0_O) 0.313 4.703 r u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/O
|
|
net (fo=2, routed) 0.550 5.253 u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7_n_0
|
|
SLICE_X4Y68 r u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/I1
|
|
SLICE_X4Y68 LUT6 (Prop_lut6_I1_O) 0.124 5.377 r u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/O
|
|
net (fo=80, routed) 1.092 6.469 u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/soc_sram_addr[0]
|
|
SLICE_X0Y77 r u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/base_ram_be_n_OBUF[3]_inst_i_1/I5
|
|
SLICE_X0Y77 LUT6 (Prop_lut6_I5_O) 0.124 6.593 r u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/base_ram_be_n_OBUF[3]_inst_i_1/O
|
|
net (fo=1, routed) 3.064 9.657 base_ram_be_n_OBUF[3]
|
|
K25 r base_ram_be_n_OBUF[3]_inst/I
|
|
K25 OBUF (Prop_obuf_I_O) 3.551 13.208 r base_ram_be_n_OBUF[3]_inst/O
|
|
net (fo=0) 0.000 13.208 base_ram_be_n[3]
|
|
K25 r base_ram_be_n[3] (OUT)
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock sys_clk rise edge) 20.000 20.000 r
|
|
clock source latency -5.674 14.326
|
|
propagated clock network latency
|
|
0.000 14.326
|
|
clock pessimism -0.601 13.725
|
|
clock uncertainty -0.071 13.654
|
|
output delay -0.300 13.354
|
|
-------------------------------------------------------------------
|
|
required time 13.354
|
|
arrival time -13.208
|
|
-------------------------------------------------------------------
|
|
slack 0.146
|
|
|
|
Slack (MET) : 0.146ns (required time - arrival time)
|
|
Source: u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[3]/C
|
|
(rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Destination: base_ram_be_n[3]
|
|
(output port clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Path Group: sys_clk
|
|
Path Type: Max at Slow Process Corner
|
|
Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns)
|
|
Data Path Delay: 15.529ns (logic 6.868ns (44.228%) route 8.661ns (55.772%))
|
|
Logic Levels: 14 (CARRY4=6 LUT4=2 LUT5=1 LUT6=4 OBUF=1)
|
|
Output Delay: 0.300ns
|
|
Clock Path Skew: -3.955ns (DCD - SCD + CPR)
|
|
Destination Clock Delay (DCD): -5.674ns = ( 14.326 - 20.000 )
|
|
Source Clock Delay (SCD): -2.321ns
|
|
Clock Pessimism Removal (CPR): -0.601ns
|
|
Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Discrete Jitter (DJ): 0.122ns
|
|
Phase Error (PE): 0.000ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock sys_clk rise edge) 0.000 0.000 r
|
|
clock source latency -6.275 -6.275
|
|
propagated clock network latency
|
|
3.955 -2.321
|
|
SLICE_X7Y62 FDCE 0.000 -2.321 r u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[3]/C
|
|
SLICE_X7Y62 FDCE (Prop_fdce_C_Q) 0.456 -1.865 f u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[3]/Q
|
|
net (fo=54, routed) 0.726 -1.139 u_axi_ram/u_axi_sram_sp/len[3]
|
|
SLICE_X7Y61 f u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6/I3
|
|
SLICE_X7Y61 LUT4 (Prop_lut4_I3_O) 0.124 -1.015 r u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6/O
|
|
net (fo=4, routed) 0.946 -0.068 u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6_n_0
|
|
SLICE_X7Y58 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_11/I1
|
|
SLICE_X7Y58 LUT5 (Prop_lut5_I1_O) 0.124 0.056 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_11/O
|
|
net (fo=2, routed) 0.619 0.675 u_axi_ram/u_axi_sram_sp/state_d2[7]
|
|
SLICE_X6Y59 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_15/I5
|
|
SLICE_X6Y59 LUT6 (Prop_lut6_I5_O) 0.124 0.799 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_15/O
|
|
net (fo=1, routed) 0.000 0.799 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_15_n_0
|
|
SLICE_X6Y59 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9/S[3]
|
|
SLICE_X6Y59 CARRY4 (Prop_carry4_S[3]_CO[3])
|
|
0.376 1.175 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9/CO[3]
|
|
net (fo=1, routed) 0.000 1.175 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9_n_0
|
|
SLICE_X6Y60 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/CI
|
|
SLICE_X6Y60 CARRY4 (Prop_carry4_CI_CO[3])
|
|
0.117 1.292 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/CO[3]
|
|
net (fo=1, routed) 0.000 1.292 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10_n_0
|
|
SLICE_X6Y61 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CI
|
|
SLICE_X6Y61 CARRY4 (Prop_carry4_CI_CO[3])
|
|
0.117 1.409 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CO[3]
|
|
net (fo=1, routed) 0.000 1.409 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9_n_0
|
|
SLICE_X6Y62 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/CI
|
|
SLICE_X6Y62 CARRY4 (Prop_carry4_CI_O[2])
|
|
0.239 1.648 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/O[2]
|
|
net (fo=3, routed) 0.929 2.576 u_axi_ram/u_axi_sram_sp/upper_wrap_boundary[20]
|
|
SLICE_X5Y65 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_7/I2
|
|
SLICE_X5Y65 LUT4 (Prop_lut4_I2_O) 0.301 2.877 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_7/O
|
|
net (fo=1, routed) 0.000 2.877 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_7_n_0
|
|
SLICE_X5Y65 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1/S[1]
|
|
SLICE_X5Y65 CARRY4 (Prop_carry4_S[1]_CO[3])
|
|
0.550 3.427 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1/CO[3]
|
|
net (fo=1, routed) 0.000 3.427 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_n_0
|
|
SLICE_X5Y66 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2/CI
|
|
SLICE_X5Y66 CARRY4 (Prop_carry4_CI_CO[2])
|
|
0.228 3.655 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2/CO[2]
|
|
net (fo=22, routed) 0.735 4.390 u_axi_ram/u_axi_sram_sp/req_addr_d1
|
|
SLICE_X5Y68 r u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/I0
|
|
SLICE_X5Y68 LUT6 (Prop_lut6_I0_O) 0.313 4.703 r u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/O
|
|
net (fo=2, routed) 0.550 5.253 u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7_n_0
|
|
SLICE_X4Y68 r u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/I1
|
|
SLICE_X4Y68 LUT6 (Prop_lut6_I1_O) 0.124 5.377 r u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/O
|
|
net (fo=80, routed) 1.092 6.469 u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/soc_sram_addr[0]
|
|
SLICE_X0Y77 r u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/base_ram_be_n_OBUF[3]_inst_i_1/I5
|
|
SLICE_X0Y77 LUT6 (Prop_lut6_I5_O) 0.124 6.593 r u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/base_ram_be_n_OBUF[3]_inst_i_1/O
|
|
net (fo=1, routed) 3.064 9.657 base_ram_be_n_OBUF[3]
|
|
K25 r base_ram_be_n_OBUF[3]_inst/I
|
|
K25 OBUF (Prop_obuf_I_O) 3.551 13.208 r base_ram_be_n_OBUF[3]_inst/O
|
|
net (fo=0) 0.000 13.208 base_ram_be_n[3]
|
|
K25 r base_ram_be_n[3] (OUT)
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock sys_clk rise edge) 20.000 20.000 r
|
|
clock source latency -5.674 14.326
|
|
propagated clock network latency
|
|
0.000 14.326
|
|
clock pessimism -0.601 13.725
|
|
clock uncertainty -0.071 13.654
|
|
output delay -0.300 13.354
|
|
-------------------------------------------------------------------
|
|
required time 13.354
|
|
arrival time -13.208
|
|
-------------------------------------------------------------------
|
|
slack 0.146
|
|
|
|
Slack (MET) : 0.146ns (required time - arrival time)
|
|
Source: u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[3]/C
|
|
(rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Destination: base_ram_be_n[3]
|
|
(output port clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Path Group: sys_clk
|
|
Path Type: Max at Slow Process Corner
|
|
Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns)
|
|
Data Path Delay: 15.529ns (logic 6.868ns (44.228%) route 8.661ns (55.772%))
|
|
Logic Levels: 14 (CARRY4=6 LUT4=2 LUT5=1 LUT6=4 OBUF=1)
|
|
Output Delay: 0.300ns
|
|
Clock Path Skew: -3.955ns (DCD - SCD + CPR)
|
|
Destination Clock Delay (DCD): -5.674ns = ( 14.326 - 20.000 )
|
|
Source Clock Delay (SCD): -2.321ns
|
|
Clock Pessimism Removal (CPR): -0.601ns
|
|
Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Discrete Jitter (DJ): 0.122ns
|
|
Phase Error (PE): 0.000ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock sys_clk rise edge) 0.000 0.000 r
|
|
clock source latency -6.275 -6.275
|
|
propagated clock network latency
|
|
3.955 -2.321
|
|
SLICE_X7Y62 FDCE 0.000 -2.321 r u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[3]/C
|
|
SLICE_X7Y62 FDCE (Prop_fdce_C_Q) 0.456 -1.865 f u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[3]/Q
|
|
net (fo=54, routed) 0.726 -1.139 u_axi_ram/u_axi_sram_sp/len[3]
|
|
SLICE_X7Y61 f u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6/I3
|
|
SLICE_X7Y61 LUT4 (Prop_lut4_I3_O) 0.124 -1.015 r u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6/O
|
|
net (fo=4, routed) 0.946 -0.068 u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6_n_0
|
|
SLICE_X7Y58 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_11/I1
|
|
SLICE_X7Y58 LUT5 (Prop_lut5_I1_O) 0.124 0.056 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_11/O
|
|
net (fo=2, routed) 0.619 0.675 u_axi_ram/u_axi_sram_sp/state_d2[7]
|
|
SLICE_X6Y59 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_15/I5
|
|
SLICE_X6Y59 LUT6 (Prop_lut6_I5_O) 0.124 0.799 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_15/O
|
|
net (fo=1, routed) 0.000 0.799 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_15_n_0
|
|
SLICE_X6Y59 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9/S[3]
|
|
SLICE_X6Y59 CARRY4 (Prop_carry4_S[3]_CO[3])
|
|
0.376 1.175 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9/CO[3]
|
|
net (fo=1, routed) 0.000 1.175 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9_n_0
|
|
SLICE_X6Y60 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/CI
|
|
SLICE_X6Y60 CARRY4 (Prop_carry4_CI_CO[3])
|
|
0.117 1.292 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/CO[3]
|
|
net (fo=1, routed) 0.000 1.292 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10_n_0
|
|
SLICE_X6Y61 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CI
|
|
SLICE_X6Y61 CARRY4 (Prop_carry4_CI_CO[3])
|
|
0.117 1.409 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CO[3]
|
|
net (fo=1, routed) 0.000 1.409 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9_n_0
|
|
SLICE_X6Y62 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/CI
|
|
SLICE_X6Y62 CARRY4 (Prop_carry4_CI_O[2])
|
|
0.239 1.648 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/O[2]
|
|
net (fo=3, routed) 0.929 2.576 u_axi_ram/u_axi_sram_sp/upper_wrap_boundary[20]
|
|
SLICE_X5Y65 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_7/I2
|
|
SLICE_X5Y65 LUT4 (Prop_lut4_I2_O) 0.301 2.877 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_7/O
|
|
net (fo=1, routed) 0.000 2.877 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_7_n_0
|
|
SLICE_X5Y65 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1/S[1]
|
|
SLICE_X5Y65 CARRY4 (Prop_carry4_S[1]_CO[3])
|
|
0.550 3.427 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1/CO[3]
|
|
net (fo=1, routed) 0.000 3.427 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_n_0
|
|
SLICE_X5Y66 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2/CI
|
|
SLICE_X5Y66 CARRY4 (Prop_carry4_CI_CO[2])
|
|
0.228 3.655 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2/CO[2]
|
|
net (fo=22, routed) 0.735 4.390 u_axi_ram/u_axi_sram_sp/req_addr_d1
|
|
SLICE_X5Y68 r u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/I0
|
|
SLICE_X5Y68 LUT6 (Prop_lut6_I0_O) 0.313 4.703 r u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/O
|
|
net (fo=2, routed) 0.550 5.253 u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7_n_0
|
|
SLICE_X4Y68 r u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/I1
|
|
SLICE_X4Y68 LUT6 (Prop_lut6_I1_O) 0.124 5.377 r u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/O
|
|
net (fo=80, routed) 1.092 6.469 u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/soc_sram_addr[0]
|
|
SLICE_X0Y77 r u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/base_ram_be_n_OBUF[3]_inst_i_1/I5
|
|
SLICE_X0Y77 LUT6 (Prop_lut6_I5_O) 0.124 6.593 r u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/base_ram_be_n_OBUF[3]_inst_i_1/O
|
|
net (fo=1, routed) 3.064 9.657 base_ram_be_n_OBUF[3]
|
|
K25 r base_ram_be_n_OBUF[3]_inst/I
|
|
K25 OBUF (Prop_obuf_I_O) 3.551 13.208 r base_ram_be_n_OBUF[3]_inst/O
|
|
net (fo=0) 0.000 13.208 base_ram_be_n[3]
|
|
K25 r base_ram_be_n[3] (OUT)
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock sys_clk rise edge) 20.000 20.000 r
|
|
clock source latency -5.674 14.326
|
|
propagated clock network latency
|
|
0.000 14.326
|
|
clock pessimism -0.601 13.725
|
|
clock uncertainty -0.071 13.654
|
|
output delay -0.300 13.354
|
|
-------------------------------------------------------------------
|
|
required time 13.354
|
|
arrival time -13.208
|
|
-------------------------------------------------------------------
|
|
slack 0.146
|
|
|
|
Slack (MET) : 0.243ns (required time - arrival time)
|
|
Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_wb_inc_reg/C
|
|
(rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_block_r_reg[1066]/D
|
|
(rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Path Group: sys_clk
|
|
Path Type: Setup (Max at Slow Process Corner)
|
|
Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns)
|
|
Data Path Delay: 19.438ns (logic 0.818ns (4.208%) route 18.620ns (95.792%))
|
|
Logic Levels: 2 (LUT4=1 MUXF7=1)
|
|
Clock Path Skew: -0.313ns (DCD - SCD + CPR)
|
|
Destination Clock Delay (DCD): -2.293ns = ( 17.707 - 20.000 )
|
|
Source Clock Delay (SCD): -2.487ns
|
|
Clock Pessimism Removal (CPR): -0.507ns
|
|
Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Discrete Jitter (DJ): 0.122ns
|
|
Phase Error (PE): 0.000ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock sys_clk rise edge) 0.000 0.000 r
|
|
clock source latency -6.275 -6.275
|
|
propagated clock network latency
|
|
3.789 -2.487
|
|
SLICE_X123Y83 FDRE 0.000 -2.487 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_wb_inc_reg/C
|
|
SLICE_X123Y83 FDRE (Prop_fdre_C_Q) 0.456 -2.031 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_wb_inc_reg/Q
|
|
net (fo=1088, routed) 18.620 16.589 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_c_in_bram/dj_block_r_reg[902]_3
|
|
SLICE_X77Y144 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_c_in_bram/dj_block_r[1066]_i_2/I2
|
|
SLICE_X77Y144 LUT4 (Prop_lut4_I2_O) 0.124 16.713 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_c_in_bram/dj_block_r[1066]_i_2/O
|
|
net (fo=1, routed) 0.000 16.713 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_c_in_bram/dj_block_r[1066]_i_2_n_0
|
|
SLICE_X77Y144 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_c_in_bram/dj_block_r_reg[1066]_i_1/I0
|
|
SLICE_X77Y144 MUXF7 (Prop_muxf7_I0_O) 0.238 16.951 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_c_in_bram/dj_block_r_reg[1066]_i_1/O
|
|
net (fo=1, routed) 0.000 16.951 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_c_in_bram_n_51
|
|
SLICE_X77Y144 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_block_r_reg[1066]/D
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock sys_clk rise edge) 20.000 20.000 r
|
|
clock source latency -5.674 14.326
|
|
propagated clock network latency
|
|
3.382 17.707
|
|
clock pessimism -0.507 17.200
|
|
clock uncertainty -0.071 17.130
|
|
SLICE_X77Y144 FDCE (Setup_fdce_C_D) 0.064 17.194 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_block_r_reg[1066]
|
|
-------------------------------------------------------------------
|
|
required time 17.194
|
|
arrival time -16.951
|
|
-------------------------------------------------------------------
|
|
slack 0.243
|
|
|
|
Slack (MET) : 0.243ns (required time - arrival time)
|
|
Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_wb_inc_reg/C
|
|
(rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_block_r_reg[1066]/D
|
|
(rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Path Group: sys_clk
|
|
Path Type: Setup (Max at Slow Process Corner)
|
|
Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns)
|
|
Data Path Delay: 19.438ns (logic 0.818ns (4.208%) route 18.620ns (95.792%))
|
|
Logic Levels: 2 (LUT4=1 MUXF7=1)
|
|
Clock Path Skew: -0.313ns (DCD - SCD + CPR)
|
|
Destination Clock Delay (DCD): -2.293ns = ( 17.707 - 20.000 )
|
|
Source Clock Delay (SCD): -2.487ns
|
|
Clock Pessimism Removal (CPR): -0.507ns
|
|
Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Discrete Jitter (DJ): 0.122ns
|
|
Phase Error (PE): 0.000ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock sys_clk rise edge) 0.000 0.000 r
|
|
clock source latency -6.275 -6.275
|
|
propagated clock network latency
|
|
3.789 -2.487
|
|
SLICE_X123Y83 FDRE 0.000 -2.487 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_wb_inc_reg/C
|
|
SLICE_X123Y83 FDRE (Prop_fdre_C_Q) 0.456 -2.031 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_wb_inc_reg/Q
|
|
net (fo=1088, routed) 18.620 16.589 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_c_in_bram/dj_block_r_reg[902]_3
|
|
SLICE_X77Y144 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_c_in_bram/dj_block_r[1066]_i_2/I2
|
|
SLICE_X77Y144 LUT4 (Prop_lut4_I2_O) 0.124 16.713 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_c_in_bram/dj_block_r[1066]_i_2/O
|
|
net (fo=1, routed) 0.000 16.713 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_c_in_bram/dj_block_r[1066]_i_2_n_0
|
|
SLICE_X77Y144 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_c_in_bram/dj_block_r_reg[1066]_i_1/I0
|
|
SLICE_X77Y144 MUXF7 (Prop_muxf7_I0_O) 0.238 16.951 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_c_in_bram/dj_block_r_reg[1066]_i_1/O
|
|
net (fo=1, routed) 0.000 16.951 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_c_in_bram_n_51
|
|
SLICE_X77Y144 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_block_r_reg[1066]/D
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock sys_clk rise edge) 20.000 20.000 r
|
|
clock source latency -5.674 14.326
|
|
propagated clock network latency
|
|
3.382 17.707
|
|
clock pessimism -0.507 17.200
|
|
clock uncertainty -0.071 17.130
|
|
SLICE_X77Y144 FDCE (Setup_fdce_C_D) 0.064 17.194 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_block_r_reg[1066]
|
|
-------------------------------------------------------------------
|
|
required time 17.194
|
|
arrival time -16.951
|
|
-------------------------------------------------------------------
|
|
slack 0.243
|
|
|
|
Slack (MET) : 0.243ns (required time - arrival time)
|
|
Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_wb_inc_reg/C
|
|
(rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_block_r_reg[1066]/D
|
|
(rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Path Group: sys_clk
|
|
Path Type: Setup (Max at Slow Process Corner)
|
|
Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns)
|
|
Data Path Delay: 19.438ns (logic 0.818ns (4.208%) route 18.620ns (95.792%))
|
|
Logic Levels: 2 (LUT4=1 MUXF7=1)
|
|
Clock Path Skew: -0.313ns (DCD - SCD + CPR)
|
|
Destination Clock Delay (DCD): -2.293ns = ( 17.707 - 20.000 )
|
|
Source Clock Delay (SCD): -2.487ns
|
|
Clock Pessimism Removal (CPR): -0.507ns
|
|
Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Discrete Jitter (DJ): 0.122ns
|
|
Phase Error (PE): 0.000ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock sys_clk rise edge) 0.000 0.000 r
|
|
clock source latency -6.275 -6.275
|
|
propagated clock network latency
|
|
3.789 -2.487
|
|
SLICE_X123Y83 FDRE 0.000 -2.487 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_wb_inc_reg/C
|
|
SLICE_X123Y83 FDRE (Prop_fdre_C_Q) 0.456 -2.031 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_wb_inc_reg/Q
|
|
net (fo=1088, routed) 18.620 16.589 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_c_in_bram/dj_block_r_reg[902]_3
|
|
SLICE_X77Y144 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_c_in_bram/dj_block_r[1066]_i_2/I2
|
|
SLICE_X77Y144 LUT4 (Prop_lut4_I2_O) 0.124 16.713 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_c_in_bram/dj_block_r[1066]_i_2/O
|
|
net (fo=1, routed) 0.000 16.713 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_c_in_bram/dj_block_r[1066]_i_2_n_0
|
|
SLICE_X77Y144 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_c_in_bram/dj_block_r_reg[1066]_i_1/I0
|
|
SLICE_X77Y144 MUXF7 (Prop_muxf7_I0_O) 0.238 16.951 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_c_in_bram/dj_block_r_reg[1066]_i_1/O
|
|
net (fo=1, routed) 0.000 16.951 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_c_in_bram_n_51
|
|
SLICE_X77Y144 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_block_r_reg[1066]/D
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock sys_clk rise edge) 20.000 20.000 r
|
|
clock source latency -5.674 14.326
|
|
propagated clock network latency
|
|
3.382 17.707
|
|
clock pessimism -0.507 17.200
|
|
clock uncertainty -0.071 17.130
|
|
SLICE_X77Y144 FDCE (Setup_fdce_C_D) 0.064 17.194 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_block_r_reg[1066]
|
|
-------------------------------------------------------------------
|
|
required time 17.194
|
|
arrival time -16.951
|
|
-------------------------------------------------------------------
|
|
slack 0.243
|
|
|
|
Slack (MET) : 0.243ns (required time - arrival time)
|
|
Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_wb_inc_reg/C
|
|
(rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_block_r_reg[1066]/D
|
|
(rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Path Group: sys_clk
|
|
Path Type: Setup (Max at Slow Process Corner)
|
|
Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns)
|
|
Data Path Delay: 19.438ns (logic 0.818ns (4.208%) route 18.620ns (95.792%))
|
|
Logic Levels: 2 (LUT4=1 MUXF7=1)
|
|
Clock Path Skew: -0.313ns (DCD - SCD + CPR)
|
|
Destination Clock Delay (DCD): -2.293ns = ( 17.707 - 20.000 )
|
|
Source Clock Delay (SCD): -2.487ns
|
|
Clock Pessimism Removal (CPR): -0.507ns
|
|
Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Discrete Jitter (DJ): 0.122ns
|
|
Phase Error (PE): 0.000ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock sys_clk rise edge) 0.000 0.000 r
|
|
clock source latency -6.275 -6.275
|
|
propagated clock network latency
|
|
3.789 -2.487
|
|
SLICE_X123Y83 FDRE 0.000 -2.487 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_wb_inc_reg/C
|
|
SLICE_X123Y83 FDRE (Prop_fdre_C_Q) 0.456 -2.031 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_wb_inc_reg/Q
|
|
net (fo=1088, routed) 18.620 16.589 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_c_in_bram/dj_block_r_reg[902]_3
|
|
SLICE_X77Y144 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_c_in_bram/dj_block_r[1066]_i_2/I2
|
|
SLICE_X77Y144 LUT4 (Prop_lut4_I2_O) 0.124 16.713 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_c_in_bram/dj_block_r[1066]_i_2/O
|
|
net (fo=1, routed) 0.000 16.713 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_c_in_bram/dj_block_r[1066]_i_2_n_0
|
|
SLICE_X77Y144 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_c_in_bram/dj_block_r_reg[1066]_i_1/I0
|
|
SLICE_X77Y144 MUXF7 (Prop_muxf7_I0_O) 0.238 16.951 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_c_in_bram/dj_block_r_reg[1066]_i_1/O
|
|
net (fo=1, routed) 0.000 16.951 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_c_in_bram_n_51
|
|
SLICE_X77Y144 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_block_r_reg[1066]/D
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock sys_clk rise edge) 20.000 20.000 r
|
|
clock source latency -5.674 14.326
|
|
propagated clock network latency
|
|
3.382 17.707
|
|
clock pessimism -0.507 17.200
|
|
clock uncertainty -0.071 17.130
|
|
SLICE_X77Y144 FDCE (Setup_fdce_C_D) 0.064 17.194 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_block_r_reg[1066]
|
|
-------------------------------------------------------------------
|
|
required time 17.194
|
|
arrival time -16.951
|
|
-------------------------------------------------------------------
|
|
slack 0.243
|
|
|
|
Slack (MET) : 0.272ns (required time - arrival time)
|
|
Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_wb_inc_reg/C
|
|
(rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_block_r_reg[1065]/D
|
|
(rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Path Group: sys_clk
|
|
Path Type: Setup (Max at Slow Process Corner)
|
|
Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns)
|
|
Data Path Delay: 19.409ns (logic 0.792ns (4.081%) route 18.617ns (95.919%))
|
|
Logic Levels: 2 (LUT4=1 MUXF7=1)
|
|
Clock Path Skew: -0.313ns (DCD - SCD + CPR)
|
|
Destination Clock Delay (DCD): -2.293ns = ( 17.707 - 20.000 )
|
|
Source Clock Delay (SCD): -2.487ns
|
|
Clock Pessimism Removal (CPR): -0.507ns
|
|
Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Discrete Jitter (DJ): 0.122ns
|
|
Phase Error (PE): 0.000ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock sys_clk rise edge) 0.000 0.000 r
|
|
clock source latency -6.275 -6.275
|
|
propagated clock network latency
|
|
3.789 -2.487
|
|
SLICE_X123Y83 FDRE 0.000 -2.487 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_wb_inc_reg/C
|
|
SLICE_X123Y83 FDRE (Prop_fdre_C_Q) 0.456 -2.031 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_wb_inc_reg/Q
|
|
net (fo=1088, routed) 18.617 16.586 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_c_in_bram/dj_block_r_reg[902]_3
|
|
SLICE_X77Y144 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_c_in_bram/dj_block_r[1065]_i_2/I2
|
|
SLICE_X77Y144 LUT4 (Prop_lut4_I2_O) 0.124 16.710 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_c_in_bram/dj_block_r[1065]_i_2/O
|
|
net (fo=1, routed) 0.000 16.710 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_c_in_bram/dj_block_r[1065]_i_2_n_0
|
|
SLICE_X77Y144 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_c_in_bram/dj_block_r_reg[1065]_i_1/I0
|
|
SLICE_X77Y144 MUXF7 (Prop_muxf7_I0_O) 0.212 16.922 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_c_in_bram/dj_block_r_reg[1065]_i_1/O
|
|
net (fo=1, routed) 0.000 16.922 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_c_in_bram_n_52
|
|
SLICE_X77Y144 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_block_r_reg[1065]/D
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock sys_clk rise edge) 20.000 20.000 r
|
|
clock source latency -5.674 14.326
|
|
propagated clock network latency
|
|
3.382 17.707
|
|
clock pessimism -0.507 17.200
|
|
clock uncertainty -0.071 17.130
|
|
SLICE_X77Y144 FDCE (Setup_fdce_C_D) 0.064 17.194 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_block_r_reg[1065]
|
|
-------------------------------------------------------------------
|
|
required time 17.194
|
|
arrival time -16.922
|
|
-------------------------------------------------------------------
|
|
slack 0.272
|
|
|
|
Slack (MET) : 0.272ns (required time - arrival time)
|
|
Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_wb_inc_reg/C
|
|
(rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_block_r_reg[1065]/D
|
|
(rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Path Group: sys_clk
|
|
Path Type: Setup (Max at Slow Process Corner)
|
|
Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns)
|
|
Data Path Delay: 19.409ns (logic 0.792ns (4.081%) route 18.617ns (95.919%))
|
|
Logic Levels: 2 (LUT4=1 MUXF7=1)
|
|
Clock Path Skew: -0.313ns (DCD - SCD + CPR)
|
|
Destination Clock Delay (DCD): -2.293ns = ( 17.707 - 20.000 )
|
|
Source Clock Delay (SCD): -2.487ns
|
|
Clock Pessimism Removal (CPR): -0.507ns
|
|
Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Discrete Jitter (DJ): 0.122ns
|
|
Phase Error (PE): 0.000ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock sys_clk rise edge) 0.000 0.000 r
|
|
clock source latency -6.275 -6.275
|
|
propagated clock network latency
|
|
3.789 -2.487
|
|
SLICE_X123Y83 FDRE 0.000 -2.487 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_wb_inc_reg/C
|
|
SLICE_X123Y83 FDRE (Prop_fdre_C_Q) 0.456 -2.031 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_wb_inc_reg/Q
|
|
net (fo=1088, routed) 18.617 16.586 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_c_in_bram/dj_block_r_reg[902]_3
|
|
SLICE_X77Y144 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_c_in_bram/dj_block_r[1065]_i_2/I2
|
|
SLICE_X77Y144 LUT4 (Prop_lut4_I2_O) 0.124 16.710 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_c_in_bram/dj_block_r[1065]_i_2/O
|
|
net (fo=1, routed) 0.000 16.710 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_c_in_bram/dj_block_r[1065]_i_2_n_0
|
|
SLICE_X77Y144 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_c_in_bram/dj_block_r_reg[1065]_i_1/I0
|
|
SLICE_X77Y144 MUXF7 (Prop_muxf7_I0_O) 0.212 16.922 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_c_in_bram/dj_block_r_reg[1065]_i_1/O
|
|
net (fo=1, routed) 0.000 16.922 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_c_in_bram_n_52
|
|
SLICE_X77Y144 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_block_r_reg[1065]/D
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock sys_clk rise edge) 20.000 20.000 r
|
|
clock source latency -5.674 14.326
|
|
propagated clock network latency
|
|
3.382 17.707
|
|
clock pessimism -0.507 17.200
|
|
clock uncertainty -0.071 17.130
|
|
SLICE_X77Y144 FDCE (Setup_fdce_C_D) 0.064 17.194 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_block_r_reg[1065]
|
|
-------------------------------------------------------------------
|
|
required time 17.194
|
|
arrival time -16.922
|
|
-------------------------------------------------------------------
|
|
slack 0.272
|
|
|
|
Slack (MET) : 0.272ns (required time - arrival time)
|
|
Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_wb_inc_reg/C
|
|
(rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_block_r_reg[1065]/D
|
|
(rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Path Group: sys_clk
|
|
Path Type: Setup (Max at Slow Process Corner)
|
|
Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns)
|
|
Data Path Delay: 19.409ns (logic 0.792ns (4.081%) route 18.617ns (95.919%))
|
|
Logic Levels: 2 (LUT4=1 MUXF7=1)
|
|
Clock Path Skew: -0.313ns (DCD - SCD + CPR)
|
|
Destination Clock Delay (DCD): -2.293ns = ( 17.707 - 20.000 )
|
|
Source Clock Delay (SCD): -2.487ns
|
|
Clock Pessimism Removal (CPR): -0.507ns
|
|
Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Discrete Jitter (DJ): 0.122ns
|
|
Phase Error (PE): 0.000ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock sys_clk rise edge) 0.000 0.000 r
|
|
clock source latency -6.275 -6.275
|
|
propagated clock network latency
|
|
3.789 -2.487
|
|
SLICE_X123Y83 FDRE 0.000 -2.487 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_wb_inc_reg/C
|
|
SLICE_X123Y83 FDRE (Prop_fdre_C_Q) 0.456 -2.031 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_wb_inc_reg/Q
|
|
net (fo=1088, routed) 18.617 16.586 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_c_in_bram/dj_block_r_reg[902]_3
|
|
SLICE_X77Y144 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_c_in_bram/dj_block_r[1065]_i_2/I2
|
|
SLICE_X77Y144 LUT4 (Prop_lut4_I2_O) 0.124 16.710 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_c_in_bram/dj_block_r[1065]_i_2/O
|
|
net (fo=1, routed) 0.000 16.710 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_c_in_bram/dj_block_r[1065]_i_2_n_0
|
|
SLICE_X77Y144 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_c_in_bram/dj_block_r_reg[1065]_i_1/I0
|
|
SLICE_X77Y144 MUXF7 (Prop_muxf7_I0_O) 0.212 16.922 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_c_in_bram/dj_block_r_reg[1065]_i_1/O
|
|
net (fo=1, routed) 0.000 16.922 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_c_in_bram_n_52
|
|
SLICE_X77Y144 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_block_r_reg[1065]/D
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock sys_clk rise edge) 20.000 20.000 r
|
|
clock source latency -5.674 14.326
|
|
propagated clock network latency
|
|
3.382 17.707
|
|
clock pessimism -0.507 17.200
|
|
clock uncertainty -0.071 17.130
|
|
SLICE_X77Y144 FDCE (Setup_fdce_C_D) 0.064 17.194 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_block_r_reg[1065]
|
|
-------------------------------------------------------------------
|
|
required time 17.194
|
|
arrival time -16.922
|
|
-------------------------------------------------------------------
|
|
slack 0.272
|
|
|
|
Slack (MET) : 0.272ns (required time - arrival time)
|
|
Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_wb_inc_reg/C
|
|
(rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_block_r_reg[1065]/D
|
|
(rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Path Group: sys_clk
|
|
Path Type: Setup (Max at Slow Process Corner)
|
|
Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns)
|
|
Data Path Delay: 19.409ns (logic 0.792ns (4.081%) route 18.617ns (95.919%))
|
|
Logic Levels: 2 (LUT4=1 MUXF7=1)
|
|
Clock Path Skew: -0.313ns (DCD - SCD + CPR)
|
|
Destination Clock Delay (DCD): -2.293ns = ( 17.707 - 20.000 )
|
|
Source Clock Delay (SCD): -2.487ns
|
|
Clock Pessimism Removal (CPR): -0.507ns
|
|
Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Discrete Jitter (DJ): 0.122ns
|
|
Phase Error (PE): 0.000ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock sys_clk rise edge) 0.000 0.000 r
|
|
clock source latency -6.275 -6.275
|
|
propagated clock network latency
|
|
3.789 -2.487
|
|
SLICE_X123Y83 FDRE 0.000 -2.487 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_wb_inc_reg/C
|
|
SLICE_X123Y83 FDRE (Prop_fdre_C_Q) 0.456 -2.031 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_wb_inc_reg/Q
|
|
net (fo=1088, routed) 18.617 16.586 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_c_in_bram/dj_block_r_reg[902]_3
|
|
SLICE_X77Y144 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_c_in_bram/dj_block_r[1065]_i_2/I2
|
|
SLICE_X77Y144 LUT4 (Prop_lut4_I2_O) 0.124 16.710 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_c_in_bram/dj_block_r[1065]_i_2/O
|
|
net (fo=1, routed) 0.000 16.710 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_c_in_bram/dj_block_r[1065]_i_2_n_0
|
|
SLICE_X77Y144 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_c_in_bram/dj_block_r_reg[1065]_i_1/I0
|
|
SLICE_X77Y144 MUXF7 (Prop_muxf7_I0_O) 0.212 16.922 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_c_in_bram/dj_block_r_reg[1065]_i_1/O
|
|
net (fo=1, routed) 0.000 16.922 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_c_in_bram_n_52
|
|
SLICE_X77Y144 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_block_r_reg[1065]/D
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock sys_clk rise edge) 20.000 20.000 r
|
|
clock source latency -5.674 14.326
|
|
propagated clock network latency
|
|
3.382 17.707
|
|
clock pessimism -0.507 17.200
|
|
clock uncertainty -0.071 17.130
|
|
SLICE_X77Y144 FDCE (Setup_fdce_C_D) 0.064 17.194 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_block_r_reg[1065]
|
|
-------------------------------------------------------------------
|
|
required time 17.194
|
|
arrival time -16.922
|
|
-------------------------------------------------------------------
|
|
slack 0.272
|
|
|
|
Slack (MET) : 0.275ns (required time - arrival time)
|
|
Source: u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[3]/C
|
|
(rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Destination: ext_ram_data[23]
|
|
(output port clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Path Group: sys_clk
|
|
Path Type: Max at Slow Process Corner
|
|
Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns)
|
|
Data Path Delay: 15.399ns (logic 6.859ns (44.544%) route 8.540ns (55.456%))
|
|
Logic Levels: 14 (CARRY4=6 LUT3=1 LUT4=2 LUT5=1 LUT6=3 OBUFT=1)
|
|
Output Delay: 0.300ns
|
|
Clock Path Skew: -3.955ns (DCD - SCD + CPR)
|
|
Destination Clock Delay (DCD): -5.674ns = ( 14.326 - 20.000 )
|
|
Source Clock Delay (SCD): -2.321ns
|
|
Clock Pessimism Removal (CPR): -0.601ns
|
|
Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Discrete Jitter (DJ): 0.122ns
|
|
Phase Error (PE): 0.000ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock sys_clk rise edge) 0.000 0.000 r
|
|
clock source latency -6.275 -6.275
|
|
propagated clock network latency
|
|
3.955 -2.321
|
|
SLICE_X7Y62 FDCE 0.000 -2.321 r u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[3]/C
|
|
SLICE_X7Y62 FDCE (Prop_fdce_C_Q) 0.456 -1.865 f u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[3]/Q
|
|
net (fo=54, routed) 0.726 -1.139 u_axi_ram/u_axi_sram_sp/len[3]
|
|
SLICE_X7Y61 f u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6/I3
|
|
SLICE_X7Y61 LUT4 (Prop_lut4_I3_O) 0.124 -1.015 r u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6/O
|
|
net (fo=4, routed) 0.946 -0.068 u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6_n_0
|
|
SLICE_X7Y58 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_11/I1
|
|
SLICE_X7Y58 LUT5 (Prop_lut5_I1_O) 0.124 0.056 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_11/O
|
|
net (fo=2, routed) 0.619 0.675 u_axi_ram/u_axi_sram_sp/state_d2[7]
|
|
SLICE_X6Y59 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_15/I5
|
|
SLICE_X6Y59 LUT6 (Prop_lut6_I5_O) 0.124 0.799 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_15/O
|
|
net (fo=1, routed) 0.000 0.799 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_15_n_0
|
|
SLICE_X6Y59 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9/S[3]
|
|
SLICE_X6Y59 CARRY4 (Prop_carry4_S[3]_CO[3])
|
|
0.376 1.175 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9/CO[3]
|
|
net (fo=1, routed) 0.000 1.175 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9_n_0
|
|
SLICE_X6Y60 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/CI
|
|
SLICE_X6Y60 CARRY4 (Prop_carry4_CI_CO[3])
|
|
0.117 1.292 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/CO[3]
|
|
net (fo=1, routed) 0.000 1.292 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10_n_0
|
|
SLICE_X6Y61 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CI
|
|
SLICE_X6Y61 CARRY4 (Prop_carry4_CI_CO[3])
|
|
0.117 1.409 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CO[3]
|
|
net (fo=1, routed) 0.000 1.409 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9_n_0
|
|
SLICE_X6Y62 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/CI
|
|
SLICE_X6Y62 CARRY4 (Prop_carry4_CI_O[2])
|
|
0.239 1.648 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/O[2]
|
|
net (fo=3, routed) 0.929 2.576 u_axi_ram/u_axi_sram_sp/upper_wrap_boundary[20]
|
|
SLICE_X5Y65 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_7/I2
|
|
SLICE_X5Y65 LUT4 (Prop_lut4_I2_O) 0.301 2.877 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_7/O
|
|
net (fo=1, routed) 0.000 2.877 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_7_n_0
|
|
SLICE_X5Y65 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1/S[1]
|
|
SLICE_X5Y65 CARRY4 (Prop_carry4_S[1]_CO[3])
|
|
0.550 3.427 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1/CO[3]
|
|
net (fo=1, routed) 0.000 3.427 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_n_0
|
|
SLICE_X5Y66 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2/CI
|
|
SLICE_X5Y66 CARRY4 (Prop_carry4_CI_CO[2])
|
|
0.228 3.655 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2/CO[2]
|
|
net (fo=22, routed) 0.735 4.390 u_axi_ram/u_axi_sram_sp/req_addr_d1
|
|
SLICE_X5Y68 r u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/I0
|
|
SLICE_X5Y68 LUT6 (Prop_lut6_I0_O) 0.313 4.703 r u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/O
|
|
net (fo=2, routed) 0.550 5.253 u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7_n_0
|
|
SLICE_X4Y68 r u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/I1
|
|
SLICE_X4Y68 LUT6 (Prop_lut6_I1_O) 0.124 5.377 r u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/O
|
|
net (fo=80, routed) 0.770 6.147 u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/soc_sram_addr[0]
|
|
SLICE_X1Y63 r u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/ext_ram_data_IOBUF[31]_inst_i_2/I2
|
|
SLICE_X1Y63 LUT3 (Prop_lut3_I2_O) 0.124 6.271 f u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/ext_ram_data_IOBUF[31]_inst_i_2/O
|
|
net (fo=32, routed) 3.265 9.536 ext_ram_data_IOBUF[23]_inst/T
|
|
AA15 f ext_ram_data_IOBUF[23]_inst/OBUFT/T
|
|
AA15 OBUFT (TriStatE_obuft_T_O)
|
|
3.542 13.079 r ext_ram_data_IOBUF[23]_inst/OBUFT/O
|
|
net (fo=1, unset) 0.000 13.079 ext_ram_data[23]
|
|
AA15 r ext_ram_data[23] (INOUT)
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock sys_clk rise edge) 20.000 20.000 r
|
|
clock source latency -5.674 14.326
|
|
propagated clock network latency
|
|
0.000 14.326
|
|
clock pessimism -0.601 13.725
|
|
clock uncertainty -0.071 13.654
|
|
output delay -0.300 13.354
|
|
-------------------------------------------------------------------
|
|
required time 13.354
|
|
arrival time -13.079
|
|
-------------------------------------------------------------------
|
|
slack 0.275
|
|
|
|
Slack (MET) : 0.275ns (required time - arrival time)
|
|
Source: u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[3]/C
|
|
(rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Destination: ext_ram_data[23]
|
|
(output port clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Path Group: sys_clk
|
|
Path Type: Max at Slow Process Corner
|
|
Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns)
|
|
Data Path Delay: 15.399ns (logic 6.859ns (44.544%) route 8.540ns (55.456%))
|
|
Logic Levels: 14 (CARRY4=6 LUT3=1 LUT4=2 LUT5=1 LUT6=3 OBUFT=1)
|
|
Output Delay: 0.300ns
|
|
Clock Path Skew: -3.955ns (DCD - SCD + CPR)
|
|
Destination Clock Delay (DCD): -5.674ns = ( 14.326 - 20.000 )
|
|
Source Clock Delay (SCD): -2.321ns
|
|
Clock Pessimism Removal (CPR): -0.601ns
|
|
Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Discrete Jitter (DJ): 0.122ns
|
|
Phase Error (PE): 0.000ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock sys_clk rise edge) 0.000 0.000 r
|
|
clock source latency -6.275 -6.275
|
|
propagated clock network latency
|
|
3.955 -2.321
|
|
SLICE_X7Y62 FDCE 0.000 -2.321 r u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[3]/C
|
|
SLICE_X7Y62 FDCE (Prop_fdce_C_Q) 0.456 -1.865 f u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[3]/Q
|
|
net (fo=54, routed) 0.726 -1.139 u_axi_ram/u_axi_sram_sp/len[3]
|
|
SLICE_X7Y61 f u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6/I3
|
|
SLICE_X7Y61 LUT4 (Prop_lut4_I3_O) 0.124 -1.015 r u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6/O
|
|
net (fo=4, routed) 0.946 -0.068 u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6_n_0
|
|
SLICE_X7Y58 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_11/I1
|
|
SLICE_X7Y58 LUT5 (Prop_lut5_I1_O) 0.124 0.056 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_11/O
|
|
net (fo=2, routed) 0.619 0.675 u_axi_ram/u_axi_sram_sp/state_d2[7]
|
|
SLICE_X6Y59 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_15/I5
|
|
SLICE_X6Y59 LUT6 (Prop_lut6_I5_O) 0.124 0.799 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_15/O
|
|
net (fo=1, routed) 0.000 0.799 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_15_n_0
|
|
SLICE_X6Y59 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9/S[3]
|
|
SLICE_X6Y59 CARRY4 (Prop_carry4_S[3]_CO[3])
|
|
0.376 1.175 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9/CO[3]
|
|
net (fo=1, routed) 0.000 1.175 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9_n_0
|
|
SLICE_X6Y60 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/CI
|
|
SLICE_X6Y60 CARRY4 (Prop_carry4_CI_CO[3])
|
|
0.117 1.292 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/CO[3]
|
|
net (fo=1, routed) 0.000 1.292 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10_n_0
|
|
SLICE_X6Y61 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CI
|
|
SLICE_X6Y61 CARRY4 (Prop_carry4_CI_CO[3])
|
|
0.117 1.409 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CO[3]
|
|
net (fo=1, routed) 0.000 1.409 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9_n_0
|
|
SLICE_X6Y62 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/CI
|
|
SLICE_X6Y62 CARRY4 (Prop_carry4_CI_O[2])
|
|
0.239 1.648 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/O[2]
|
|
net (fo=3, routed) 0.929 2.576 u_axi_ram/u_axi_sram_sp/upper_wrap_boundary[20]
|
|
SLICE_X5Y65 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_7/I2
|
|
SLICE_X5Y65 LUT4 (Prop_lut4_I2_O) 0.301 2.877 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_7/O
|
|
net (fo=1, routed) 0.000 2.877 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_7_n_0
|
|
SLICE_X5Y65 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1/S[1]
|
|
SLICE_X5Y65 CARRY4 (Prop_carry4_S[1]_CO[3])
|
|
0.550 3.427 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1/CO[3]
|
|
net (fo=1, routed) 0.000 3.427 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_n_0
|
|
SLICE_X5Y66 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2/CI
|
|
SLICE_X5Y66 CARRY4 (Prop_carry4_CI_CO[2])
|
|
0.228 3.655 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2/CO[2]
|
|
net (fo=22, routed) 0.735 4.390 u_axi_ram/u_axi_sram_sp/req_addr_d1
|
|
SLICE_X5Y68 r u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/I0
|
|
SLICE_X5Y68 LUT6 (Prop_lut6_I0_O) 0.313 4.703 r u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/O
|
|
net (fo=2, routed) 0.550 5.253 u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7_n_0
|
|
SLICE_X4Y68 r u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/I1
|
|
SLICE_X4Y68 LUT6 (Prop_lut6_I1_O) 0.124 5.377 r u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/O
|
|
net (fo=80, routed) 0.770 6.147 u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/soc_sram_addr[0]
|
|
SLICE_X1Y63 r u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/ext_ram_data_IOBUF[31]_inst_i_2/I2
|
|
SLICE_X1Y63 LUT3 (Prop_lut3_I2_O) 0.124 6.271 f u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/ext_ram_data_IOBUF[31]_inst_i_2/O
|
|
net (fo=32, routed) 3.265 9.536 ext_ram_data_IOBUF[23]_inst/T
|
|
AA15 f ext_ram_data_IOBUF[23]_inst/OBUFT/T
|
|
AA15 OBUFT (TriStatE_obuft_T_O)
|
|
3.542 13.079 r ext_ram_data_IOBUF[23]_inst/OBUFT/O
|
|
net (fo=1, unset) 0.000 13.079 ext_ram_data[23]
|
|
AA15 r ext_ram_data[23] (INOUT)
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock sys_clk rise edge) 20.000 20.000 r
|
|
clock source latency -5.674 14.326
|
|
propagated clock network latency
|
|
0.000 14.326
|
|
clock pessimism -0.601 13.725
|
|
clock uncertainty -0.071 13.654
|
|
output delay -0.300 13.354
|
|
-------------------------------------------------------------------
|
|
required time 13.354
|
|
arrival time -13.079
|
|
-------------------------------------------------------------------
|
|
slack 0.275
|
|
|
|
Slack (MET) : 0.275ns (required time - arrival time)
|
|
Source: u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[3]/C
|
|
(rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Destination: ext_ram_data[23]
|
|
(output port clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Path Group: sys_clk
|
|
Path Type: Max at Slow Process Corner
|
|
Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns)
|
|
Data Path Delay: 15.399ns (logic 6.859ns (44.544%) route 8.540ns (55.456%))
|
|
Logic Levels: 14 (CARRY4=6 LUT3=1 LUT4=2 LUT5=1 LUT6=3 OBUFT=1)
|
|
Output Delay: 0.300ns
|
|
Clock Path Skew: -3.955ns (DCD - SCD + CPR)
|
|
Destination Clock Delay (DCD): -5.674ns = ( 14.326 - 20.000 )
|
|
Source Clock Delay (SCD): -2.321ns
|
|
Clock Pessimism Removal (CPR): -0.601ns
|
|
Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Discrete Jitter (DJ): 0.122ns
|
|
Phase Error (PE): 0.000ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock sys_clk rise edge) 0.000 0.000 r
|
|
clock source latency -6.275 -6.275
|
|
propagated clock network latency
|
|
3.955 -2.321
|
|
SLICE_X7Y62 FDCE 0.000 -2.321 r u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[3]/C
|
|
SLICE_X7Y62 FDCE (Prop_fdce_C_Q) 0.456 -1.865 f u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[3]/Q
|
|
net (fo=54, routed) 0.726 -1.139 u_axi_ram/u_axi_sram_sp/len[3]
|
|
SLICE_X7Y61 f u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6/I3
|
|
SLICE_X7Y61 LUT4 (Prop_lut4_I3_O) 0.124 -1.015 r u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6/O
|
|
net (fo=4, routed) 0.946 -0.068 u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6_n_0
|
|
SLICE_X7Y58 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_11/I1
|
|
SLICE_X7Y58 LUT5 (Prop_lut5_I1_O) 0.124 0.056 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_11/O
|
|
net (fo=2, routed) 0.619 0.675 u_axi_ram/u_axi_sram_sp/state_d2[7]
|
|
SLICE_X6Y59 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_15/I5
|
|
SLICE_X6Y59 LUT6 (Prop_lut6_I5_O) 0.124 0.799 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_15/O
|
|
net (fo=1, routed) 0.000 0.799 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_15_n_0
|
|
SLICE_X6Y59 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9/S[3]
|
|
SLICE_X6Y59 CARRY4 (Prop_carry4_S[3]_CO[3])
|
|
0.376 1.175 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9/CO[3]
|
|
net (fo=1, routed) 0.000 1.175 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9_n_0
|
|
SLICE_X6Y60 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/CI
|
|
SLICE_X6Y60 CARRY4 (Prop_carry4_CI_CO[3])
|
|
0.117 1.292 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/CO[3]
|
|
net (fo=1, routed) 0.000 1.292 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10_n_0
|
|
SLICE_X6Y61 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CI
|
|
SLICE_X6Y61 CARRY4 (Prop_carry4_CI_CO[3])
|
|
0.117 1.409 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CO[3]
|
|
net (fo=1, routed) 0.000 1.409 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9_n_0
|
|
SLICE_X6Y62 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/CI
|
|
SLICE_X6Y62 CARRY4 (Prop_carry4_CI_O[2])
|
|
0.239 1.648 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/O[2]
|
|
net (fo=3, routed) 0.929 2.576 u_axi_ram/u_axi_sram_sp/upper_wrap_boundary[20]
|
|
SLICE_X5Y65 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_7/I2
|
|
SLICE_X5Y65 LUT4 (Prop_lut4_I2_O) 0.301 2.877 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_7/O
|
|
net (fo=1, routed) 0.000 2.877 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_7_n_0
|
|
SLICE_X5Y65 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1/S[1]
|
|
SLICE_X5Y65 CARRY4 (Prop_carry4_S[1]_CO[3])
|
|
0.550 3.427 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1/CO[3]
|
|
net (fo=1, routed) 0.000 3.427 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_n_0
|
|
SLICE_X5Y66 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2/CI
|
|
SLICE_X5Y66 CARRY4 (Prop_carry4_CI_CO[2])
|
|
0.228 3.655 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2/CO[2]
|
|
net (fo=22, routed) 0.735 4.390 u_axi_ram/u_axi_sram_sp/req_addr_d1
|
|
SLICE_X5Y68 r u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/I0
|
|
SLICE_X5Y68 LUT6 (Prop_lut6_I0_O) 0.313 4.703 r u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/O
|
|
net (fo=2, routed) 0.550 5.253 u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7_n_0
|
|
SLICE_X4Y68 r u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/I1
|
|
SLICE_X4Y68 LUT6 (Prop_lut6_I1_O) 0.124 5.377 r u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/O
|
|
net (fo=80, routed) 0.770 6.147 u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/soc_sram_addr[0]
|
|
SLICE_X1Y63 r u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/ext_ram_data_IOBUF[31]_inst_i_2/I2
|
|
SLICE_X1Y63 LUT3 (Prop_lut3_I2_O) 0.124 6.271 f u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/ext_ram_data_IOBUF[31]_inst_i_2/O
|
|
net (fo=32, routed) 3.265 9.536 ext_ram_data_IOBUF[23]_inst/T
|
|
AA15 f ext_ram_data_IOBUF[23]_inst/OBUFT/T
|
|
AA15 OBUFT (TriStatE_obuft_T_O)
|
|
3.542 13.079 r ext_ram_data_IOBUF[23]_inst/OBUFT/O
|
|
net (fo=1, unset) 0.000 13.079 ext_ram_data[23]
|
|
AA15 r ext_ram_data[23] (INOUT)
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock sys_clk rise edge) 20.000 20.000 r
|
|
clock source latency -5.674 14.326
|
|
propagated clock network latency
|
|
0.000 14.326
|
|
clock pessimism -0.601 13.725
|
|
clock uncertainty -0.071 13.654
|
|
output delay -0.300 13.354
|
|
-------------------------------------------------------------------
|
|
required time 13.354
|
|
arrival time -13.079
|
|
-------------------------------------------------------------------
|
|
slack 0.275
|
|
|
|
Slack (MET) : 0.275ns (required time - arrival time)
|
|
Source: u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[3]/C
|
|
(rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Destination: ext_ram_data[23]
|
|
(output port clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Path Group: sys_clk
|
|
Path Type: Max at Slow Process Corner
|
|
Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns)
|
|
Data Path Delay: 15.399ns (logic 6.859ns (44.544%) route 8.540ns (55.456%))
|
|
Logic Levels: 14 (CARRY4=6 LUT3=1 LUT4=2 LUT5=1 LUT6=3 OBUFT=1)
|
|
Output Delay: 0.300ns
|
|
Clock Path Skew: -3.955ns (DCD - SCD + CPR)
|
|
Destination Clock Delay (DCD): -5.674ns = ( 14.326 - 20.000 )
|
|
Source Clock Delay (SCD): -2.321ns
|
|
Clock Pessimism Removal (CPR): -0.601ns
|
|
Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Discrete Jitter (DJ): 0.122ns
|
|
Phase Error (PE): 0.000ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock sys_clk rise edge) 0.000 0.000 r
|
|
clock source latency -6.275 -6.275
|
|
propagated clock network latency
|
|
3.955 -2.321
|
|
SLICE_X7Y62 FDCE 0.000 -2.321 r u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[3]/C
|
|
SLICE_X7Y62 FDCE (Prop_fdce_C_Q) 0.456 -1.865 f u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[3]/Q
|
|
net (fo=54, routed) 0.726 -1.139 u_axi_ram/u_axi_sram_sp/len[3]
|
|
SLICE_X7Y61 f u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6/I3
|
|
SLICE_X7Y61 LUT4 (Prop_lut4_I3_O) 0.124 -1.015 r u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6/O
|
|
net (fo=4, routed) 0.946 -0.068 u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6_n_0
|
|
SLICE_X7Y58 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_11/I1
|
|
SLICE_X7Y58 LUT5 (Prop_lut5_I1_O) 0.124 0.056 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_11/O
|
|
net (fo=2, routed) 0.619 0.675 u_axi_ram/u_axi_sram_sp/state_d2[7]
|
|
SLICE_X6Y59 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_15/I5
|
|
SLICE_X6Y59 LUT6 (Prop_lut6_I5_O) 0.124 0.799 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_15/O
|
|
net (fo=1, routed) 0.000 0.799 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_15_n_0
|
|
SLICE_X6Y59 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9/S[3]
|
|
SLICE_X6Y59 CARRY4 (Prop_carry4_S[3]_CO[3])
|
|
0.376 1.175 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9/CO[3]
|
|
net (fo=1, routed) 0.000 1.175 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9_n_0
|
|
SLICE_X6Y60 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/CI
|
|
SLICE_X6Y60 CARRY4 (Prop_carry4_CI_CO[3])
|
|
0.117 1.292 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/CO[3]
|
|
net (fo=1, routed) 0.000 1.292 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10_n_0
|
|
SLICE_X6Y61 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CI
|
|
SLICE_X6Y61 CARRY4 (Prop_carry4_CI_CO[3])
|
|
0.117 1.409 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CO[3]
|
|
net (fo=1, routed) 0.000 1.409 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9_n_0
|
|
SLICE_X6Y62 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/CI
|
|
SLICE_X6Y62 CARRY4 (Prop_carry4_CI_O[2])
|
|
0.239 1.648 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/O[2]
|
|
net (fo=3, routed) 0.929 2.576 u_axi_ram/u_axi_sram_sp/upper_wrap_boundary[20]
|
|
SLICE_X5Y65 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_7/I2
|
|
SLICE_X5Y65 LUT4 (Prop_lut4_I2_O) 0.301 2.877 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_7/O
|
|
net (fo=1, routed) 0.000 2.877 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_7_n_0
|
|
SLICE_X5Y65 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1/S[1]
|
|
SLICE_X5Y65 CARRY4 (Prop_carry4_S[1]_CO[3])
|
|
0.550 3.427 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1/CO[3]
|
|
net (fo=1, routed) 0.000 3.427 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_n_0
|
|
SLICE_X5Y66 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2/CI
|
|
SLICE_X5Y66 CARRY4 (Prop_carry4_CI_CO[2])
|
|
0.228 3.655 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2/CO[2]
|
|
net (fo=22, routed) 0.735 4.390 u_axi_ram/u_axi_sram_sp/req_addr_d1
|
|
SLICE_X5Y68 r u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/I0
|
|
SLICE_X5Y68 LUT6 (Prop_lut6_I0_O) 0.313 4.703 r u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/O
|
|
net (fo=2, routed) 0.550 5.253 u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7_n_0
|
|
SLICE_X4Y68 r u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/I1
|
|
SLICE_X4Y68 LUT6 (Prop_lut6_I1_O) 0.124 5.377 r u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/O
|
|
net (fo=80, routed) 0.770 6.147 u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/soc_sram_addr[0]
|
|
SLICE_X1Y63 r u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/ext_ram_data_IOBUF[31]_inst_i_2/I2
|
|
SLICE_X1Y63 LUT3 (Prop_lut3_I2_O) 0.124 6.271 f u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/ext_ram_data_IOBUF[31]_inst_i_2/O
|
|
net (fo=32, routed) 3.265 9.536 ext_ram_data_IOBUF[23]_inst/T
|
|
AA15 f ext_ram_data_IOBUF[23]_inst/OBUFT/T
|
|
AA15 OBUFT (TriStatE_obuft_T_O)
|
|
3.542 13.079 r ext_ram_data_IOBUF[23]_inst/OBUFT/O
|
|
net (fo=1, unset) 0.000 13.079 ext_ram_data[23]
|
|
AA15 r ext_ram_data[23] (INOUT)
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock sys_clk rise edge) 20.000 20.000 r
|
|
clock source latency -5.674 14.326
|
|
propagated clock network latency
|
|
0.000 14.326
|
|
clock pessimism -0.601 13.725
|
|
clock uncertainty -0.071 13.654
|
|
output delay -0.300 13.354
|
|
-------------------------------------------------------------------
|
|
required time 13.354
|
|
arrival time -13.079
|
|
-------------------------------------------------------------------
|
|
slack 0.275
|
|
|
|
Slack (MET) : 0.275ns (required time - arrival time)
|
|
Source: u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[3]/C
|
|
(rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Destination: ext_ram_data[23]
|
|
(output port clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Path Group: sys_clk
|
|
Path Type: Max at Slow Process Corner
|
|
Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns)
|
|
Data Path Delay: 15.399ns (logic 6.859ns (44.544%) route 8.540ns (55.456%))
|
|
Logic Levels: 14 (CARRY4=6 LUT3=1 LUT4=2 LUT5=1 LUT6=3 OBUFT=1)
|
|
Output Delay: 0.300ns
|
|
Clock Path Skew: -3.955ns (DCD - SCD + CPR)
|
|
Destination Clock Delay (DCD): -5.674ns = ( 14.326 - 20.000 )
|
|
Source Clock Delay (SCD): -2.321ns
|
|
Clock Pessimism Removal (CPR): -0.601ns
|
|
Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Discrete Jitter (DJ): 0.122ns
|
|
Phase Error (PE): 0.000ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock sys_clk rise edge) 0.000 0.000 r
|
|
clock source latency -6.275 -6.275
|
|
propagated clock network latency
|
|
3.955 -2.321
|
|
SLICE_X7Y62 FDCE 0.000 -2.321 r u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[3]/C
|
|
SLICE_X7Y62 FDCE (Prop_fdce_C_Q) 0.456 -1.865 f u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[3]/Q
|
|
net (fo=54, routed) 0.726 -1.139 u_axi_ram/u_axi_sram_sp/len[3]
|
|
SLICE_X7Y61 f u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6/I3
|
|
SLICE_X7Y61 LUT4 (Prop_lut4_I3_O) 0.124 -1.015 r u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6/O
|
|
net (fo=4, routed) 0.946 -0.068 u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6_n_0
|
|
SLICE_X7Y58 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_11/I1
|
|
SLICE_X7Y58 LUT5 (Prop_lut5_I1_O) 0.124 0.056 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_11/O
|
|
net (fo=2, routed) 0.619 0.675 u_axi_ram/u_axi_sram_sp/state_d2[7]
|
|
SLICE_X6Y59 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_15/I5
|
|
SLICE_X6Y59 LUT6 (Prop_lut6_I5_O) 0.124 0.799 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_15/O
|
|
net (fo=1, routed) 0.000 0.799 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_15_n_0
|
|
SLICE_X6Y59 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9/S[3]
|
|
SLICE_X6Y59 CARRY4 (Prop_carry4_S[3]_CO[3])
|
|
0.376 1.175 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9/CO[3]
|
|
net (fo=1, routed) 0.000 1.175 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9_n_0
|
|
SLICE_X6Y60 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/CI
|
|
SLICE_X6Y60 CARRY4 (Prop_carry4_CI_CO[3])
|
|
0.117 1.292 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/CO[3]
|
|
net (fo=1, routed) 0.000 1.292 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10_n_0
|
|
SLICE_X6Y61 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CI
|
|
SLICE_X6Y61 CARRY4 (Prop_carry4_CI_CO[3])
|
|
0.117 1.409 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CO[3]
|
|
net (fo=1, routed) 0.000 1.409 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9_n_0
|
|
SLICE_X6Y62 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/CI
|
|
SLICE_X6Y62 CARRY4 (Prop_carry4_CI_O[2])
|
|
0.239 1.648 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/O[2]
|
|
net (fo=3, routed) 0.929 2.576 u_axi_ram/u_axi_sram_sp/upper_wrap_boundary[20]
|
|
SLICE_X5Y65 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_7/I2
|
|
SLICE_X5Y65 LUT4 (Prop_lut4_I2_O) 0.301 2.877 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_7/O
|
|
net (fo=1, routed) 0.000 2.877 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_7_n_0
|
|
SLICE_X5Y65 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1/S[1]
|
|
SLICE_X5Y65 CARRY4 (Prop_carry4_S[1]_CO[3])
|
|
0.550 3.427 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1/CO[3]
|
|
net (fo=1, routed) 0.000 3.427 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_n_0
|
|
SLICE_X5Y66 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2/CI
|
|
SLICE_X5Y66 CARRY4 (Prop_carry4_CI_CO[2])
|
|
0.228 3.655 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2/CO[2]
|
|
net (fo=22, routed) 0.735 4.390 u_axi_ram/u_axi_sram_sp/req_addr_d1
|
|
SLICE_X5Y68 r u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/I0
|
|
SLICE_X5Y68 LUT6 (Prop_lut6_I0_O) 0.313 4.703 r u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/O
|
|
net (fo=2, routed) 0.550 5.253 u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7_n_0
|
|
SLICE_X4Y68 r u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/I1
|
|
SLICE_X4Y68 LUT6 (Prop_lut6_I1_O) 0.124 5.377 r u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/O
|
|
net (fo=80, routed) 0.770 6.147 u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/soc_sram_addr[0]
|
|
SLICE_X1Y63 r u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/ext_ram_data_IOBUF[31]_inst_i_2/I2
|
|
SLICE_X1Y63 LUT3 (Prop_lut3_I2_O) 0.124 6.271 f u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/ext_ram_data_IOBUF[31]_inst_i_2/O
|
|
net (fo=32, routed) 3.265 9.536 ext_ram_data_IOBUF[23]_inst/T
|
|
AA15 f ext_ram_data_IOBUF[23]_inst/OBUFT/T
|
|
AA15 OBUFT (TriStatE_obuft_T_O)
|
|
3.542 13.079 r ext_ram_data_IOBUF[23]_inst/OBUFT/O
|
|
net (fo=1, unset) 0.000 13.079 ext_ram_data[23]
|
|
AA15 r ext_ram_data[23] (INOUT)
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock sys_clk rise edge) 20.000 20.000 r
|
|
clock source latency -5.674 14.326
|
|
propagated clock network latency
|
|
0.000 14.326
|
|
clock pessimism -0.601 13.725
|
|
clock uncertainty -0.071 13.654
|
|
output delay -0.300 13.354
|
|
-------------------------------------------------------------------
|
|
required time 13.354
|
|
arrival time -13.079
|
|
-------------------------------------------------------------------
|
|
slack 0.275
|
|
|
|
Slack (MET) : 0.275ns (required time - arrival time)
|
|
Source: u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[3]/C
|
|
(rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Destination: ext_ram_data[23]
|
|
(output port clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Path Group: sys_clk
|
|
Path Type: Max at Slow Process Corner
|
|
Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns)
|
|
Data Path Delay: 15.399ns (logic 6.859ns (44.544%) route 8.540ns (55.456%))
|
|
Logic Levels: 14 (CARRY4=6 LUT3=1 LUT4=2 LUT5=1 LUT6=3 OBUFT=1)
|
|
Output Delay: 0.300ns
|
|
Clock Path Skew: -3.955ns (DCD - SCD + CPR)
|
|
Destination Clock Delay (DCD): -5.674ns = ( 14.326 - 20.000 )
|
|
Source Clock Delay (SCD): -2.321ns
|
|
Clock Pessimism Removal (CPR): -0.601ns
|
|
Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Discrete Jitter (DJ): 0.122ns
|
|
Phase Error (PE): 0.000ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock sys_clk rise edge) 0.000 0.000 r
|
|
clock source latency -6.275 -6.275
|
|
propagated clock network latency
|
|
3.955 -2.321
|
|
SLICE_X7Y62 FDCE 0.000 -2.321 r u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[3]/C
|
|
SLICE_X7Y62 FDCE (Prop_fdce_C_Q) 0.456 -1.865 f u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[3]/Q
|
|
net (fo=54, routed) 0.726 -1.139 u_axi_ram/u_axi_sram_sp/len[3]
|
|
SLICE_X7Y61 f u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6/I3
|
|
SLICE_X7Y61 LUT4 (Prop_lut4_I3_O) 0.124 -1.015 r u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6/O
|
|
net (fo=4, routed) 0.946 -0.068 u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6_n_0
|
|
SLICE_X7Y58 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_11/I1
|
|
SLICE_X7Y58 LUT5 (Prop_lut5_I1_O) 0.124 0.056 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_11/O
|
|
net (fo=2, routed) 0.619 0.675 u_axi_ram/u_axi_sram_sp/state_d2[7]
|
|
SLICE_X6Y59 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_15/I5
|
|
SLICE_X6Y59 LUT6 (Prop_lut6_I5_O) 0.124 0.799 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_15/O
|
|
net (fo=1, routed) 0.000 0.799 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_15_n_0
|
|
SLICE_X6Y59 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9/S[3]
|
|
SLICE_X6Y59 CARRY4 (Prop_carry4_S[3]_CO[3])
|
|
0.376 1.175 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9/CO[3]
|
|
net (fo=1, routed) 0.000 1.175 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9_n_0
|
|
SLICE_X6Y60 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/CI
|
|
SLICE_X6Y60 CARRY4 (Prop_carry4_CI_CO[3])
|
|
0.117 1.292 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/CO[3]
|
|
net (fo=1, routed) 0.000 1.292 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10_n_0
|
|
SLICE_X6Y61 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CI
|
|
SLICE_X6Y61 CARRY4 (Prop_carry4_CI_CO[3])
|
|
0.117 1.409 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CO[3]
|
|
net (fo=1, routed) 0.000 1.409 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9_n_0
|
|
SLICE_X6Y62 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/CI
|
|
SLICE_X6Y62 CARRY4 (Prop_carry4_CI_O[2])
|
|
0.239 1.648 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/O[2]
|
|
net (fo=3, routed) 0.929 2.576 u_axi_ram/u_axi_sram_sp/upper_wrap_boundary[20]
|
|
SLICE_X5Y65 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_7/I2
|
|
SLICE_X5Y65 LUT4 (Prop_lut4_I2_O) 0.301 2.877 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_7/O
|
|
net (fo=1, routed) 0.000 2.877 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_7_n_0
|
|
SLICE_X5Y65 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1/S[1]
|
|
SLICE_X5Y65 CARRY4 (Prop_carry4_S[1]_CO[3])
|
|
0.550 3.427 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1/CO[3]
|
|
net (fo=1, routed) 0.000 3.427 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_n_0
|
|
SLICE_X5Y66 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2/CI
|
|
SLICE_X5Y66 CARRY4 (Prop_carry4_CI_CO[2])
|
|
0.228 3.655 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2/CO[2]
|
|
net (fo=22, routed) 0.735 4.390 u_axi_ram/u_axi_sram_sp/req_addr_d1
|
|
SLICE_X5Y68 r u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/I0
|
|
SLICE_X5Y68 LUT6 (Prop_lut6_I0_O) 0.313 4.703 r u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/O
|
|
net (fo=2, routed) 0.550 5.253 u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7_n_0
|
|
SLICE_X4Y68 r u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/I1
|
|
SLICE_X4Y68 LUT6 (Prop_lut6_I1_O) 0.124 5.377 r u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/O
|
|
net (fo=80, routed) 0.770 6.147 u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/soc_sram_addr[0]
|
|
SLICE_X1Y63 r u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/ext_ram_data_IOBUF[31]_inst_i_2/I2
|
|
SLICE_X1Y63 LUT3 (Prop_lut3_I2_O) 0.124 6.271 f u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/ext_ram_data_IOBUF[31]_inst_i_2/O
|
|
net (fo=32, routed) 3.265 9.536 ext_ram_data_IOBUF[23]_inst/T
|
|
AA15 f ext_ram_data_IOBUF[23]_inst/OBUFT/T
|
|
AA15 OBUFT (TriStatE_obuft_T_O)
|
|
3.542 13.079 r ext_ram_data_IOBUF[23]_inst/OBUFT/O
|
|
net (fo=1, unset) 0.000 13.079 ext_ram_data[23]
|
|
AA15 r ext_ram_data[23] (INOUT)
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock sys_clk rise edge) 20.000 20.000 r
|
|
clock source latency -5.674 14.326
|
|
propagated clock network latency
|
|
0.000 14.326
|
|
clock pessimism -0.601 13.725
|
|
clock uncertainty -0.071 13.654
|
|
output delay -0.300 13.354
|
|
-------------------------------------------------------------------
|
|
required time 13.354
|
|
arrival time -13.079
|
|
-------------------------------------------------------------------
|
|
slack 0.275
|
|
|
|
Slack (MET) : 0.275ns (required time - arrival time)
|
|
Source: u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[3]/C
|
|
(rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Destination: ext_ram_data[23]
|
|
(output port clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Path Group: sys_clk
|
|
Path Type: Max at Slow Process Corner
|
|
Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns)
|
|
Data Path Delay: 15.399ns (logic 6.859ns (44.544%) route 8.540ns (55.456%))
|
|
Logic Levels: 14 (CARRY4=6 LUT3=1 LUT4=2 LUT5=1 LUT6=3 OBUFT=1)
|
|
Output Delay: 0.300ns
|
|
Clock Path Skew: -3.955ns (DCD - SCD + CPR)
|
|
Destination Clock Delay (DCD): -5.674ns = ( 14.326 - 20.000 )
|
|
Source Clock Delay (SCD): -2.321ns
|
|
Clock Pessimism Removal (CPR): -0.601ns
|
|
Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Discrete Jitter (DJ): 0.122ns
|
|
Phase Error (PE): 0.000ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock sys_clk rise edge) 0.000 0.000 r
|
|
clock source latency -6.275 -6.275
|
|
propagated clock network latency
|
|
3.955 -2.321
|
|
SLICE_X7Y62 FDCE 0.000 -2.321 r u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[3]/C
|
|
SLICE_X7Y62 FDCE (Prop_fdce_C_Q) 0.456 -1.865 f u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[3]/Q
|
|
net (fo=54, routed) 0.726 -1.139 u_axi_ram/u_axi_sram_sp/len[3]
|
|
SLICE_X7Y61 f u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6/I3
|
|
SLICE_X7Y61 LUT4 (Prop_lut4_I3_O) 0.124 -1.015 r u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6/O
|
|
net (fo=4, routed) 0.946 -0.068 u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6_n_0
|
|
SLICE_X7Y58 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_11/I1
|
|
SLICE_X7Y58 LUT5 (Prop_lut5_I1_O) 0.124 0.056 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_11/O
|
|
net (fo=2, routed) 0.619 0.675 u_axi_ram/u_axi_sram_sp/state_d2[7]
|
|
SLICE_X6Y59 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_15/I5
|
|
SLICE_X6Y59 LUT6 (Prop_lut6_I5_O) 0.124 0.799 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_15/O
|
|
net (fo=1, routed) 0.000 0.799 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_15_n_0
|
|
SLICE_X6Y59 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9/S[3]
|
|
SLICE_X6Y59 CARRY4 (Prop_carry4_S[3]_CO[3])
|
|
0.376 1.175 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9/CO[3]
|
|
net (fo=1, routed) 0.000 1.175 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9_n_0
|
|
SLICE_X6Y60 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/CI
|
|
SLICE_X6Y60 CARRY4 (Prop_carry4_CI_CO[3])
|
|
0.117 1.292 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/CO[3]
|
|
net (fo=1, routed) 0.000 1.292 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10_n_0
|
|
SLICE_X6Y61 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CI
|
|
SLICE_X6Y61 CARRY4 (Prop_carry4_CI_CO[3])
|
|
0.117 1.409 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CO[3]
|
|
net (fo=1, routed) 0.000 1.409 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9_n_0
|
|
SLICE_X6Y62 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/CI
|
|
SLICE_X6Y62 CARRY4 (Prop_carry4_CI_O[2])
|
|
0.239 1.648 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/O[2]
|
|
net (fo=3, routed) 0.929 2.576 u_axi_ram/u_axi_sram_sp/upper_wrap_boundary[20]
|
|
SLICE_X5Y65 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_7/I2
|
|
SLICE_X5Y65 LUT4 (Prop_lut4_I2_O) 0.301 2.877 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_7/O
|
|
net (fo=1, routed) 0.000 2.877 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_7_n_0
|
|
SLICE_X5Y65 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1/S[1]
|
|
SLICE_X5Y65 CARRY4 (Prop_carry4_S[1]_CO[3])
|
|
0.550 3.427 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1/CO[3]
|
|
net (fo=1, routed) 0.000 3.427 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_n_0
|
|
SLICE_X5Y66 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2/CI
|
|
SLICE_X5Y66 CARRY4 (Prop_carry4_CI_CO[2])
|
|
0.228 3.655 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2/CO[2]
|
|
net (fo=22, routed) 0.735 4.390 u_axi_ram/u_axi_sram_sp/req_addr_d1
|
|
SLICE_X5Y68 r u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/I0
|
|
SLICE_X5Y68 LUT6 (Prop_lut6_I0_O) 0.313 4.703 r u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/O
|
|
net (fo=2, routed) 0.550 5.253 u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7_n_0
|
|
SLICE_X4Y68 r u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/I1
|
|
SLICE_X4Y68 LUT6 (Prop_lut6_I1_O) 0.124 5.377 r u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/O
|
|
net (fo=80, routed) 0.770 6.147 u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/soc_sram_addr[0]
|
|
SLICE_X1Y63 r u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/ext_ram_data_IOBUF[31]_inst_i_2/I2
|
|
SLICE_X1Y63 LUT3 (Prop_lut3_I2_O) 0.124 6.271 f u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/ext_ram_data_IOBUF[31]_inst_i_2/O
|
|
net (fo=32, routed) 3.265 9.536 ext_ram_data_IOBUF[23]_inst/T
|
|
AA15 f ext_ram_data_IOBUF[23]_inst/OBUFT/T
|
|
AA15 OBUFT (TriStatE_obuft_T_O)
|
|
3.542 13.079 r ext_ram_data_IOBUF[23]_inst/OBUFT/O
|
|
net (fo=1, unset) 0.000 13.079 ext_ram_data[23]
|
|
AA15 r ext_ram_data[23] (INOUT)
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock sys_clk rise edge) 20.000 20.000 r
|
|
clock source latency -5.674 14.326
|
|
propagated clock network latency
|
|
0.000 14.326
|
|
clock pessimism -0.601 13.725
|
|
clock uncertainty -0.071 13.654
|
|
output delay -0.300 13.354
|
|
-------------------------------------------------------------------
|
|
required time 13.354
|
|
arrival time -13.079
|
|
-------------------------------------------------------------------
|
|
slack 0.275
|
|
|
|
Slack (MET) : 0.275ns (required time - arrival time)
|
|
Source: u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[3]/C
|
|
(rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Destination: ext_ram_data[23]
|
|
(output port clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Path Group: sys_clk
|
|
Path Type: Max at Slow Process Corner
|
|
Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns)
|
|
Data Path Delay: 15.399ns (logic 6.859ns (44.544%) route 8.540ns (55.456%))
|
|
Logic Levels: 14 (CARRY4=6 LUT3=1 LUT4=2 LUT5=1 LUT6=3 OBUFT=1)
|
|
Output Delay: 0.300ns
|
|
Clock Path Skew: -3.955ns (DCD - SCD + CPR)
|
|
Destination Clock Delay (DCD): -5.674ns = ( 14.326 - 20.000 )
|
|
Source Clock Delay (SCD): -2.321ns
|
|
Clock Pessimism Removal (CPR): -0.601ns
|
|
Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Discrete Jitter (DJ): 0.122ns
|
|
Phase Error (PE): 0.000ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock sys_clk rise edge) 0.000 0.000 r
|
|
clock source latency -6.275 -6.275
|
|
propagated clock network latency
|
|
3.955 -2.321
|
|
SLICE_X7Y62 FDCE 0.000 -2.321 r u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[3]/C
|
|
SLICE_X7Y62 FDCE (Prop_fdce_C_Q) 0.456 -1.865 f u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[3]/Q
|
|
net (fo=54, routed) 0.726 -1.139 u_axi_ram/u_axi_sram_sp/len[3]
|
|
SLICE_X7Y61 f u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6/I3
|
|
SLICE_X7Y61 LUT4 (Prop_lut4_I3_O) 0.124 -1.015 r u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6/O
|
|
net (fo=4, routed) 0.946 -0.068 u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6_n_0
|
|
SLICE_X7Y58 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_11/I1
|
|
SLICE_X7Y58 LUT5 (Prop_lut5_I1_O) 0.124 0.056 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_11/O
|
|
net (fo=2, routed) 0.619 0.675 u_axi_ram/u_axi_sram_sp/state_d2[7]
|
|
SLICE_X6Y59 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_15/I5
|
|
SLICE_X6Y59 LUT6 (Prop_lut6_I5_O) 0.124 0.799 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_15/O
|
|
net (fo=1, routed) 0.000 0.799 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_15_n_0
|
|
SLICE_X6Y59 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9/S[3]
|
|
SLICE_X6Y59 CARRY4 (Prop_carry4_S[3]_CO[3])
|
|
0.376 1.175 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9/CO[3]
|
|
net (fo=1, routed) 0.000 1.175 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9_n_0
|
|
SLICE_X6Y60 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/CI
|
|
SLICE_X6Y60 CARRY4 (Prop_carry4_CI_CO[3])
|
|
0.117 1.292 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/CO[3]
|
|
net (fo=1, routed) 0.000 1.292 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10_n_0
|
|
SLICE_X6Y61 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CI
|
|
SLICE_X6Y61 CARRY4 (Prop_carry4_CI_CO[3])
|
|
0.117 1.409 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CO[3]
|
|
net (fo=1, routed) 0.000 1.409 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9_n_0
|
|
SLICE_X6Y62 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/CI
|
|
SLICE_X6Y62 CARRY4 (Prop_carry4_CI_O[2])
|
|
0.239 1.648 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/O[2]
|
|
net (fo=3, routed) 0.929 2.576 u_axi_ram/u_axi_sram_sp/upper_wrap_boundary[20]
|
|
SLICE_X5Y65 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_7/I2
|
|
SLICE_X5Y65 LUT4 (Prop_lut4_I2_O) 0.301 2.877 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_7/O
|
|
net (fo=1, routed) 0.000 2.877 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_7_n_0
|
|
SLICE_X5Y65 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1/S[1]
|
|
SLICE_X5Y65 CARRY4 (Prop_carry4_S[1]_CO[3])
|
|
0.550 3.427 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1/CO[3]
|
|
net (fo=1, routed) 0.000 3.427 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_n_0
|
|
SLICE_X5Y66 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2/CI
|
|
SLICE_X5Y66 CARRY4 (Prop_carry4_CI_CO[2])
|
|
0.228 3.655 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2/CO[2]
|
|
net (fo=22, routed) 0.735 4.390 u_axi_ram/u_axi_sram_sp/req_addr_d1
|
|
SLICE_X5Y68 r u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/I0
|
|
SLICE_X5Y68 LUT6 (Prop_lut6_I0_O) 0.313 4.703 r u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/O
|
|
net (fo=2, routed) 0.550 5.253 u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7_n_0
|
|
SLICE_X4Y68 r u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/I1
|
|
SLICE_X4Y68 LUT6 (Prop_lut6_I1_O) 0.124 5.377 r u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/O
|
|
net (fo=80, routed) 0.770 6.147 u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/soc_sram_addr[0]
|
|
SLICE_X1Y63 r u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/ext_ram_data_IOBUF[31]_inst_i_2/I2
|
|
SLICE_X1Y63 LUT3 (Prop_lut3_I2_O) 0.124 6.271 f u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/ext_ram_data_IOBUF[31]_inst_i_2/O
|
|
net (fo=32, routed) 3.265 9.536 ext_ram_data_IOBUF[23]_inst/T
|
|
AA15 f ext_ram_data_IOBUF[23]_inst/OBUFT/T
|
|
AA15 OBUFT (TriStatE_obuft_T_O)
|
|
3.542 13.079 r ext_ram_data_IOBUF[23]_inst/OBUFT/O
|
|
net (fo=1, unset) 0.000 13.079 ext_ram_data[23]
|
|
AA15 r ext_ram_data[23] (INOUT)
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock sys_clk rise edge) 20.000 20.000 r
|
|
clock source latency -5.674 14.326
|
|
propagated clock network latency
|
|
0.000 14.326
|
|
clock pessimism -0.601 13.725
|
|
clock uncertainty -0.071 13.654
|
|
output delay -0.300 13.354
|
|
-------------------------------------------------------------------
|
|
required time 13.354
|
|
arrival time -13.079
|
|
-------------------------------------------------------------------
|
|
slack 0.275
|
|
|
|
Slack (MET) : 0.275ns (required time - arrival time)
|
|
Source: u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[3]/C
|
|
(rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Destination: ext_ram_data[23]
|
|
(output port clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Path Group: sys_clk
|
|
Path Type: Max at Slow Process Corner
|
|
Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns)
|
|
Data Path Delay: 15.399ns (logic 6.859ns (44.544%) route 8.540ns (55.456%))
|
|
Logic Levels: 14 (CARRY4=6 LUT3=1 LUT4=2 LUT5=1 LUT6=3 OBUFT=1)
|
|
Output Delay: 0.300ns
|
|
Clock Path Skew: -3.955ns (DCD - SCD + CPR)
|
|
Destination Clock Delay (DCD): -5.674ns = ( 14.326 - 20.000 )
|
|
Source Clock Delay (SCD): -2.321ns
|
|
Clock Pessimism Removal (CPR): -0.601ns
|
|
Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Discrete Jitter (DJ): 0.122ns
|
|
Phase Error (PE): 0.000ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock sys_clk rise edge) 0.000 0.000 r
|
|
clock source latency -6.275 -6.275
|
|
propagated clock network latency
|
|
3.955 -2.321
|
|
SLICE_X7Y62 FDCE 0.000 -2.321 r u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[3]/C
|
|
SLICE_X7Y62 FDCE (Prop_fdce_C_Q) 0.456 -1.865 f u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[3]/Q
|
|
net (fo=54, routed) 0.726 -1.139 u_axi_ram/u_axi_sram_sp/len[3]
|
|
SLICE_X7Y61 f u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6/I3
|
|
SLICE_X7Y61 LUT4 (Prop_lut4_I3_O) 0.124 -1.015 r u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6/O
|
|
net (fo=4, routed) 0.946 -0.068 u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6_n_0
|
|
SLICE_X7Y58 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_11/I1
|
|
SLICE_X7Y58 LUT5 (Prop_lut5_I1_O) 0.124 0.056 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_11/O
|
|
net (fo=2, routed) 0.619 0.675 u_axi_ram/u_axi_sram_sp/state_d2[7]
|
|
SLICE_X6Y59 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_15/I5
|
|
SLICE_X6Y59 LUT6 (Prop_lut6_I5_O) 0.124 0.799 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_15/O
|
|
net (fo=1, routed) 0.000 0.799 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_15_n_0
|
|
SLICE_X6Y59 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9/S[3]
|
|
SLICE_X6Y59 CARRY4 (Prop_carry4_S[3]_CO[3])
|
|
0.376 1.175 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9/CO[3]
|
|
net (fo=1, routed) 0.000 1.175 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9_n_0
|
|
SLICE_X6Y60 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/CI
|
|
SLICE_X6Y60 CARRY4 (Prop_carry4_CI_CO[3])
|
|
0.117 1.292 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/CO[3]
|
|
net (fo=1, routed) 0.000 1.292 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10_n_0
|
|
SLICE_X6Y61 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CI
|
|
SLICE_X6Y61 CARRY4 (Prop_carry4_CI_CO[3])
|
|
0.117 1.409 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CO[3]
|
|
net (fo=1, routed) 0.000 1.409 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9_n_0
|
|
SLICE_X6Y62 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/CI
|
|
SLICE_X6Y62 CARRY4 (Prop_carry4_CI_O[2])
|
|
0.239 1.648 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/O[2]
|
|
net (fo=3, routed) 0.929 2.576 u_axi_ram/u_axi_sram_sp/upper_wrap_boundary[20]
|
|
SLICE_X5Y65 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_7/I2
|
|
SLICE_X5Y65 LUT4 (Prop_lut4_I2_O) 0.301 2.877 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_7/O
|
|
net (fo=1, routed) 0.000 2.877 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_7_n_0
|
|
SLICE_X5Y65 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1/S[1]
|
|
SLICE_X5Y65 CARRY4 (Prop_carry4_S[1]_CO[3])
|
|
0.550 3.427 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1/CO[3]
|
|
net (fo=1, routed) 0.000 3.427 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_n_0
|
|
SLICE_X5Y66 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2/CI
|
|
SLICE_X5Y66 CARRY4 (Prop_carry4_CI_CO[2])
|
|
0.228 3.655 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2/CO[2]
|
|
net (fo=22, routed) 0.735 4.390 u_axi_ram/u_axi_sram_sp/req_addr_d1
|
|
SLICE_X5Y68 r u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/I0
|
|
SLICE_X5Y68 LUT6 (Prop_lut6_I0_O) 0.313 4.703 r u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/O
|
|
net (fo=2, routed) 0.550 5.253 u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7_n_0
|
|
SLICE_X4Y68 r u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/I1
|
|
SLICE_X4Y68 LUT6 (Prop_lut6_I1_O) 0.124 5.377 r u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/O
|
|
net (fo=80, routed) 0.770 6.147 u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/soc_sram_addr[0]
|
|
SLICE_X1Y63 r u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/ext_ram_data_IOBUF[31]_inst_i_2/I2
|
|
SLICE_X1Y63 LUT3 (Prop_lut3_I2_O) 0.124 6.271 f u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/ext_ram_data_IOBUF[31]_inst_i_2/O
|
|
net (fo=32, routed) 3.265 9.536 ext_ram_data_IOBUF[23]_inst/T
|
|
AA15 f ext_ram_data_IOBUF[23]_inst/OBUFT/T
|
|
AA15 OBUFT (TriStatE_obuft_T_O)
|
|
3.542 13.079 r ext_ram_data_IOBUF[23]_inst/OBUFT/O
|
|
net (fo=1, unset) 0.000 13.079 ext_ram_data[23]
|
|
AA15 r ext_ram_data[23] (INOUT)
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock sys_clk rise edge) 20.000 20.000 r
|
|
clock source latency -5.674 14.326
|
|
propagated clock network latency
|
|
0.000 14.326
|
|
clock pessimism -0.601 13.725
|
|
clock uncertainty -0.071 13.654
|
|
output delay -0.300 13.354
|
|
-------------------------------------------------------------------
|
|
required time 13.354
|
|
arrival time -13.079
|
|
-------------------------------------------------------------------
|
|
slack 0.275
|
|
|
|
Slack (MET) : 0.275ns (required time - arrival time)
|
|
Source: u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[3]/C
|
|
(rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Destination: ext_ram_data[23]
|
|
(output port clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Path Group: sys_clk
|
|
Path Type: Max at Slow Process Corner
|
|
Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns)
|
|
Data Path Delay: 15.399ns (logic 6.859ns (44.544%) route 8.540ns (55.456%))
|
|
Logic Levels: 14 (CARRY4=6 LUT3=1 LUT4=2 LUT5=1 LUT6=3 OBUFT=1)
|
|
Output Delay: 0.300ns
|
|
Clock Path Skew: -3.955ns (DCD - SCD + CPR)
|
|
Destination Clock Delay (DCD): -5.674ns = ( 14.326 - 20.000 )
|
|
Source Clock Delay (SCD): -2.321ns
|
|
Clock Pessimism Removal (CPR): -0.601ns
|
|
Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Discrete Jitter (DJ): 0.122ns
|
|
Phase Error (PE): 0.000ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock sys_clk rise edge) 0.000 0.000 r
|
|
clock source latency -6.275 -6.275
|
|
propagated clock network latency
|
|
3.955 -2.321
|
|
SLICE_X7Y62 FDCE 0.000 -2.321 r u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[3]/C
|
|
SLICE_X7Y62 FDCE (Prop_fdce_C_Q) 0.456 -1.865 f u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[3]/Q
|
|
net (fo=54, routed) 0.726 -1.139 u_axi_ram/u_axi_sram_sp/len[3]
|
|
SLICE_X7Y61 f u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6/I3
|
|
SLICE_X7Y61 LUT4 (Prop_lut4_I3_O) 0.124 -1.015 r u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6/O
|
|
net (fo=4, routed) 0.946 -0.068 u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6_n_0
|
|
SLICE_X7Y58 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_11/I1
|
|
SLICE_X7Y58 LUT5 (Prop_lut5_I1_O) 0.124 0.056 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_11/O
|
|
net (fo=2, routed) 0.619 0.675 u_axi_ram/u_axi_sram_sp/state_d2[7]
|
|
SLICE_X6Y59 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_15/I5
|
|
SLICE_X6Y59 LUT6 (Prop_lut6_I5_O) 0.124 0.799 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_15/O
|
|
net (fo=1, routed) 0.000 0.799 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_15_n_0
|
|
SLICE_X6Y59 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9/S[3]
|
|
SLICE_X6Y59 CARRY4 (Prop_carry4_S[3]_CO[3])
|
|
0.376 1.175 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9/CO[3]
|
|
net (fo=1, routed) 0.000 1.175 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9_n_0
|
|
SLICE_X6Y60 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/CI
|
|
SLICE_X6Y60 CARRY4 (Prop_carry4_CI_CO[3])
|
|
0.117 1.292 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/CO[3]
|
|
net (fo=1, routed) 0.000 1.292 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10_n_0
|
|
SLICE_X6Y61 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CI
|
|
SLICE_X6Y61 CARRY4 (Prop_carry4_CI_CO[3])
|
|
0.117 1.409 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CO[3]
|
|
net (fo=1, routed) 0.000 1.409 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9_n_0
|
|
SLICE_X6Y62 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/CI
|
|
SLICE_X6Y62 CARRY4 (Prop_carry4_CI_O[2])
|
|
0.239 1.648 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/O[2]
|
|
net (fo=3, routed) 0.929 2.576 u_axi_ram/u_axi_sram_sp/upper_wrap_boundary[20]
|
|
SLICE_X5Y65 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_7/I2
|
|
SLICE_X5Y65 LUT4 (Prop_lut4_I2_O) 0.301 2.877 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_7/O
|
|
net (fo=1, routed) 0.000 2.877 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_7_n_0
|
|
SLICE_X5Y65 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1/S[1]
|
|
SLICE_X5Y65 CARRY4 (Prop_carry4_S[1]_CO[3])
|
|
0.550 3.427 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1/CO[3]
|
|
net (fo=1, routed) 0.000 3.427 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_n_0
|
|
SLICE_X5Y66 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2/CI
|
|
SLICE_X5Y66 CARRY4 (Prop_carry4_CI_CO[2])
|
|
0.228 3.655 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2/CO[2]
|
|
net (fo=22, routed) 0.735 4.390 u_axi_ram/u_axi_sram_sp/req_addr_d1
|
|
SLICE_X5Y68 r u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/I0
|
|
SLICE_X5Y68 LUT6 (Prop_lut6_I0_O) 0.313 4.703 r u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/O
|
|
net (fo=2, routed) 0.550 5.253 u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7_n_0
|
|
SLICE_X4Y68 r u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/I1
|
|
SLICE_X4Y68 LUT6 (Prop_lut6_I1_O) 0.124 5.377 r u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/O
|
|
net (fo=80, routed) 0.770 6.147 u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/soc_sram_addr[0]
|
|
SLICE_X1Y63 r u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/ext_ram_data_IOBUF[31]_inst_i_2/I2
|
|
SLICE_X1Y63 LUT3 (Prop_lut3_I2_O) 0.124 6.271 f u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/ext_ram_data_IOBUF[31]_inst_i_2/O
|
|
net (fo=32, routed) 3.265 9.536 ext_ram_data_IOBUF[23]_inst/T
|
|
AA15 f ext_ram_data_IOBUF[23]_inst/OBUFT/T
|
|
AA15 OBUFT (TriStatE_obuft_T_O)
|
|
3.542 13.079 r ext_ram_data_IOBUF[23]_inst/OBUFT/O
|
|
net (fo=1, unset) 0.000 13.079 ext_ram_data[23]
|
|
AA15 r ext_ram_data[23] (INOUT)
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock sys_clk rise edge) 20.000 20.000 r
|
|
clock source latency -5.674 14.326
|
|
propagated clock network latency
|
|
0.000 14.326
|
|
clock pessimism -0.601 13.725
|
|
clock uncertainty -0.071 13.654
|
|
output delay -0.300 13.354
|
|
-------------------------------------------------------------------
|
|
required time 13.354
|
|
arrival time -13.079
|
|
-------------------------------------------------------------------
|
|
slack 0.275
|
|
|
|
Slack (MET) : 0.280ns (required time - arrival time)
|
|
Source: u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[3]/C
|
|
(rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Destination: base_ram_data[1]
|
|
(output port clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Path Group: sys_clk
|
|
Path Type: Max at Slow Process Corner
|
|
Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns)
|
|
Data Path Delay: 15.395ns (logic 6.881ns (44.698%) route 8.514ns (55.302%))
|
|
Logic Levels: 14 (CARRY4=6 LUT3=1 LUT4=2 LUT5=1 LUT6=3 OBUFT=1)
|
|
Output Delay: 0.300ns
|
|
Clock Path Skew: -3.955ns (DCD - SCD + CPR)
|
|
Destination Clock Delay (DCD): -5.674ns = ( 14.326 - 20.000 )
|
|
Source Clock Delay (SCD): -2.321ns
|
|
Clock Pessimism Removal (CPR): -0.601ns
|
|
Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Discrete Jitter (DJ): 0.122ns
|
|
Phase Error (PE): 0.000ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock sys_clk rise edge) 0.000 0.000 r
|
|
clock source latency -6.275 -6.275
|
|
propagated clock network latency
|
|
3.955 -2.321
|
|
SLICE_X7Y62 FDCE 0.000 -2.321 r u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[3]/C
|
|
SLICE_X7Y62 FDCE (Prop_fdce_C_Q) 0.456 -1.865 f u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[3]/Q
|
|
net (fo=54, routed) 0.726 -1.139 u_axi_ram/u_axi_sram_sp/len[3]
|
|
SLICE_X7Y61 f u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6/I3
|
|
SLICE_X7Y61 LUT4 (Prop_lut4_I3_O) 0.124 -1.015 r u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6/O
|
|
net (fo=4, routed) 0.946 -0.068 u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6_n_0
|
|
SLICE_X7Y58 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_11/I1
|
|
SLICE_X7Y58 LUT5 (Prop_lut5_I1_O) 0.124 0.056 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_11/O
|
|
net (fo=2, routed) 0.619 0.675 u_axi_ram/u_axi_sram_sp/state_d2[7]
|
|
SLICE_X6Y59 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_15/I5
|
|
SLICE_X6Y59 LUT6 (Prop_lut6_I5_O) 0.124 0.799 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_15/O
|
|
net (fo=1, routed) 0.000 0.799 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_15_n_0
|
|
SLICE_X6Y59 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9/S[3]
|
|
SLICE_X6Y59 CARRY4 (Prop_carry4_S[3]_CO[3])
|
|
0.376 1.175 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9/CO[3]
|
|
net (fo=1, routed) 0.000 1.175 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9_n_0
|
|
SLICE_X6Y60 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/CI
|
|
SLICE_X6Y60 CARRY4 (Prop_carry4_CI_CO[3])
|
|
0.117 1.292 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/CO[3]
|
|
net (fo=1, routed) 0.000 1.292 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10_n_0
|
|
SLICE_X6Y61 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CI
|
|
SLICE_X6Y61 CARRY4 (Prop_carry4_CI_CO[3])
|
|
0.117 1.409 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CO[3]
|
|
net (fo=1, routed) 0.000 1.409 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9_n_0
|
|
SLICE_X6Y62 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/CI
|
|
SLICE_X6Y62 CARRY4 (Prop_carry4_CI_O[2])
|
|
0.239 1.648 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/O[2]
|
|
net (fo=3, routed) 0.929 2.576 u_axi_ram/u_axi_sram_sp/upper_wrap_boundary[20]
|
|
SLICE_X5Y65 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_7/I2
|
|
SLICE_X5Y65 LUT4 (Prop_lut4_I2_O) 0.301 2.877 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_7/O
|
|
net (fo=1, routed) 0.000 2.877 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_7_n_0
|
|
SLICE_X5Y65 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1/S[1]
|
|
SLICE_X5Y65 CARRY4 (Prop_carry4_S[1]_CO[3])
|
|
0.550 3.427 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1/CO[3]
|
|
net (fo=1, routed) 0.000 3.427 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_n_0
|
|
SLICE_X5Y66 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2/CI
|
|
SLICE_X5Y66 CARRY4 (Prop_carry4_CI_CO[2])
|
|
0.228 3.655 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2/CO[2]
|
|
net (fo=22, routed) 0.735 4.390 u_axi_ram/u_axi_sram_sp/req_addr_d1
|
|
SLICE_X5Y68 r u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/I0
|
|
SLICE_X5Y68 LUT6 (Prop_lut6_I0_O) 0.313 4.703 f u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/O
|
|
net (fo=2, routed) 0.550 5.253 u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7_n_0
|
|
SLICE_X4Y68 f u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/I1
|
|
SLICE_X4Y68 LUT6 (Prop_lut6_I1_O) 0.124 5.377 f u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/O
|
|
net (fo=80, routed) 0.877 6.254 u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/soc_sram_addr[0]
|
|
SLICE_X1Y74 f u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/base_ram_data_IOBUF[31]_inst_i_3/I2
|
|
SLICE_X1Y74 LUT3 (Prop_lut3_I2_O) 0.124 6.378 f u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/base_ram_data_IOBUF[31]_inst_i_3/O
|
|
net (fo=32, routed) 3.132 9.510 base_ram_data_IOBUF[1]_inst/T
|
|
L25 f base_ram_data_IOBUF[1]_inst/OBUFT/T
|
|
L25 OBUFT (TriStatE_obuft_T_O)
|
|
3.564 13.074 r base_ram_data_IOBUF[1]_inst/OBUFT/O
|
|
net (fo=1, unset) 0.000 13.074 base_ram_data[1]
|
|
L25 r base_ram_data[1] (INOUT)
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock sys_clk rise edge) 20.000 20.000 r
|
|
clock source latency -5.674 14.326
|
|
propagated clock network latency
|
|
0.000 14.326
|
|
clock pessimism -0.601 13.725
|
|
clock uncertainty -0.071 13.654
|
|
output delay -0.300 13.354
|
|
-------------------------------------------------------------------
|
|
required time 13.354
|
|
arrival time -13.074
|
|
-------------------------------------------------------------------
|
|
slack 0.280
|
|
|
|
Slack (MET) : 0.280ns (required time - arrival time)
|
|
Source: u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[3]/C
|
|
(rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Destination: base_ram_data[1]
|
|
(output port clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Path Group: sys_clk
|
|
Path Type: Max at Slow Process Corner
|
|
Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns)
|
|
Data Path Delay: 15.395ns (logic 6.881ns (44.698%) route 8.514ns (55.302%))
|
|
Logic Levels: 14 (CARRY4=6 LUT3=1 LUT4=2 LUT5=1 LUT6=3 OBUFT=1)
|
|
Output Delay: 0.300ns
|
|
Clock Path Skew: -3.955ns (DCD - SCD + CPR)
|
|
Destination Clock Delay (DCD): -5.674ns = ( 14.326 - 20.000 )
|
|
Source Clock Delay (SCD): -2.321ns
|
|
Clock Pessimism Removal (CPR): -0.601ns
|
|
Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Discrete Jitter (DJ): 0.122ns
|
|
Phase Error (PE): 0.000ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock sys_clk rise edge) 0.000 0.000 r
|
|
clock source latency -6.275 -6.275
|
|
propagated clock network latency
|
|
3.955 -2.321
|
|
SLICE_X7Y62 FDCE 0.000 -2.321 r u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[3]/C
|
|
SLICE_X7Y62 FDCE (Prop_fdce_C_Q) 0.456 -1.865 f u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[3]/Q
|
|
net (fo=54, routed) 0.726 -1.139 u_axi_ram/u_axi_sram_sp/len[3]
|
|
SLICE_X7Y61 f u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6/I3
|
|
SLICE_X7Y61 LUT4 (Prop_lut4_I3_O) 0.124 -1.015 r u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6/O
|
|
net (fo=4, routed) 0.946 -0.068 u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6_n_0
|
|
SLICE_X7Y58 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_11/I1
|
|
SLICE_X7Y58 LUT5 (Prop_lut5_I1_O) 0.124 0.056 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_11/O
|
|
net (fo=2, routed) 0.619 0.675 u_axi_ram/u_axi_sram_sp/state_d2[7]
|
|
SLICE_X6Y59 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_15/I5
|
|
SLICE_X6Y59 LUT6 (Prop_lut6_I5_O) 0.124 0.799 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_15/O
|
|
net (fo=1, routed) 0.000 0.799 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_15_n_0
|
|
SLICE_X6Y59 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9/S[3]
|
|
SLICE_X6Y59 CARRY4 (Prop_carry4_S[3]_CO[3])
|
|
0.376 1.175 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9/CO[3]
|
|
net (fo=1, routed) 0.000 1.175 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9_n_0
|
|
SLICE_X6Y60 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/CI
|
|
SLICE_X6Y60 CARRY4 (Prop_carry4_CI_CO[3])
|
|
0.117 1.292 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/CO[3]
|
|
net (fo=1, routed) 0.000 1.292 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10_n_0
|
|
SLICE_X6Y61 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CI
|
|
SLICE_X6Y61 CARRY4 (Prop_carry4_CI_CO[3])
|
|
0.117 1.409 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CO[3]
|
|
net (fo=1, routed) 0.000 1.409 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9_n_0
|
|
SLICE_X6Y62 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/CI
|
|
SLICE_X6Y62 CARRY4 (Prop_carry4_CI_O[2])
|
|
0.239 1.648 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/O[2]
|
|
net (fo=3, routed) 0.929 2.576 u_axi_ram/u_axi_sram_sp/upper_wrap_boundary[20]
|
|
SLICE_X5Y65 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_7/I2
|
|
SLICE_X5Y65 LUT4 (Prop_lut4_I2_O) 0.301 2.877 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_7/O
|
|
net (fo=1, routed) 0.000 2.877 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_7_n_0
|
|
SLICE_X5Y65 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1/S[1]
|
|
SLICE_X5Y65 CARRY4 (Prop_carry4_S[1]_CO[3])
|
|
0.550 3.427 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1/CO[3]
|
|
net (fo=1, routed) 0.000 3.427 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_n_0
|
|
SLICE_X5Y66 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2/CI
|
|
SLICE_X5Y66 CARRY4 (Prop_carry4_CI_CO[2])
|
|
0.228 3.655 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2/CO[2]
|
|
net (fo=22, routed) 0.735 4.390 u_axi_ram/u_axi_sram_sp/req_addr_d1
|
|
SLICE_X5Y68 r u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/I0
|
|
SLICE_X5Y68 LUT6 (Prop_lut6_I0_O) 0.313 4.703 f u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/O
|
|
net (fo=2, routed) 0.550 5.253 u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7_n_0
|
|
SLICE_X4Y68 f u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/I1
|
|
SLICE_X4Y68 LUT6 (Prop_lut6_I1_O) 0.124 5.377 f u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/O
|
|
net (fo=80, routed) 0.877 6.254 u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/soc_sram_addr[0]
|
|
SLICE_X1Y74 f u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/base_ram_data_IOBUF[31]_inst_i_3/I2
|
|
SLICE_X1Y74 LUT3 (Prop_lut3_I2_O) 0.124 6.378 f u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/base_ram_data_IOBUF[31]_inst_i_3/O
|
|
net (fo=32, routed) 3.132 9.510 base_ram_data_IOBUF[1]_inst/T
|
|
L25 f base_ram_data_IOBUF[1]_inst/OBUFT/T
|
|
L25 OBUFT (TriStatE_obuft_T_O)
|
|
3.564 13.074 r base_ram_data_IOBUF[1]_inst/OBUFT/O
|
|
net (fo=1, unset) 0.000 13.074 base_ram_data[1]
|
|
L25 r base_ram_data[1] (INOUT)
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock sys_clk rise edge) 20.000 20.000 r
|
|
clock source latency -5.674 14.326
|
|
propagated clock network latency
|
|
0.000 14.326
|
|
clock pessimism -0.601 13.725
|
|
clock uncertainty -0.071 13.654
|
|
output delay -0.300 13.354
|
|
-------------------------------------------------------------------
|
|
required time 13.354
|
|
arrival time -13.074
|
|
-------------------------------------------------------------------
|
|
slack 0.280
|
|
|
|
Slack (MET) : 0.280ns (required time - arrival time)
|
|
Source: u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[3]/C
|
|
(rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Destination: base_ram_data[1]
|
|
(output port clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Path Group: sys_clk
|
|
Path Type: Max at Slow Process Corner
|
|
Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns)
|
|
Data Path Delay: 15.395ns (logic 6.881ns (44.698%) route 8.514ns (55.302%))
|
|
Logic Levels: 14 (CARRY4=6 LUT3=1 LUT4=2 LUT5=1 LUT6=3 OBUFT=1)
|
|
Output Delay: 0.300ns
|
|
Clock Path Skew: -3.955ns (DCD - SCD + CPR)
|
|
Destination Clock Delay (DCD): -5.674ns = ( 14.326 - 20.000 )
|
|
Source Clock Delay (SCD): -2.321ns
|
|
Clock Pessimism Removal (CPR): -0.601ns
|
|
Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Discrete Jitter (DJ): 0.122ns
|
|
Phase Error (PE): 0.000ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock sys_clk rise edge) 0.000 0.000 r
|
|
clock source latency -6.275 -6.275
|
|
propagated clock network latency
|
|
3.955 -2.321
|
|
SLICE_X7Y62 FDCE 0.000 -2.321 r u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[3]/C
|
|
SLICE_X7Y62 FDCE (Prop_fdce_C_Q) 0.456 -1.865 f u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[3]/Q
|
|
net (fo=54, routed) 0.726 -1.139 u_axi_ram/u_axi_sram_sp/len[3]
|
|
SLICE_X7Y61 f u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6/I3
|
|
SLICE_X7Y61 LUT4 (Prop_lut4_I3_O) 0.124 -1.015 r u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6/O
|
|
net (fo=4, routed) 0.946 -0.068 u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6_n_0
|
|
SLICE_X7Y58 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_11/I1
|
|
SLICE_X7Y58 LUT5 (Prop_lut5_I1_O) 0.124 0.056 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_11/O
|
|
net (fo=2, routed) 0.619 0.675 u_axi_ram/u_axi_sram_sp/state_d2[7]
|
|
SLICE_X6Y59 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_15/I5
|
|
SLICE_X6Y59 LUT6 (Prop_lut6_I5_O) 0.124 0.799 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_15/O
|
|
net (fo=1, routed) 0.000 0.799 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_15_n_0
|
|
SLICE_X6Y59 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9/S[3]
|
|
SLICE_X6Y59 CARRY4 (Prop_carry4_S[3]_CO[3])
|
|
0.376 1.175 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9/CO[3]
|
|
net (fo=1, routed) 0.000 1.175 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9_n_0
|
|
SLICE_X6Y60 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/CI
|
|
SLICE_X6Y60 CARRY4 (Prop_carry4_CI_CO[3])
|
|
0.117 1.292 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/CO[3]
|
|
net (fo=1, routed) 0.000 1.292 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10_n_0
|
|
SLICE_X6Y61 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CI
|
|
SLICE_X6Y61 CARRY4 (Prop_carry4_CI_CO[3])
|
|
0.117 1.409 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CO[3]
|
|
net (fo=1, routed) 0.000 1.409 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9_n_0
|
|
SLICE_X6Y62 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/CI
|
|
SLICE_X6Y62 CARRY4 (Prop_carry4_CI_O[2])
|
|
0.239 1.648 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/O[2]
|
|
net (fo=3, routed) 0.929 2.576 u_axi_ram/u_axi_sram_sp/upper_wrap_boundary[20]
|
|
SLICE_X5Y65 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_7/I2
|
|
SLICE_X5Y65 LUT4 (Prop_lut4_I2_O) 0.301 2.877 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_7/O
|
|
net (fo=1, routed) 0.000 2.877 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_7_n_0
|
|
SLICE_X5Y65 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1/S[1]
|
|
SLICE_X5Y65 CARRY4 (Prop_carry4_S[1]_CO[3])
|
|
0.550 3.427 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1/CO[3]
|
|
net (fo=1, routed) 0.000 3.427 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_n_0
|
|
SLICE_X5Y66 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2/CI
|
|
SLICE_X5Y66 CARRY4 (Prop_carry4_CI_CO[2])
|
|
0.228 3.655 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2/CO[2]
|
|
net (fo=22, routed) 0.735 4.390 u_axi_ram/u_axi_sram_sp/req_addr_d1
|
|
SLICE_X5Y68 r u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/I0
|
|
SLICE_X5Y68 LUT6 (Prop_lut6_I0_O) 0.313 4.703 f u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/O
|
|
net (fo=2, routed) 0.550 5.253 u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7_n_0
|
|
SLICE_X4Y68 f u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/I1
|
|
SLICE_X4Y68 LUT6 (Prop_lut6_I1_O) 0.124 5.377 f u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/O
|
|
net (fo=80, routed) 0.877 6.254 u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/soc_sram_addr[0]
|
|
SLICE_X1Y74 f u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/base_ram_data_IOBUF[31]_inst_i_3/I2
|
|
SLICE_X1Y74 LUT3 (Prop_lut3_I2_O) 0.124 6.378 f u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/base_ram_data_IOBUF[31]_inst_i_3/O
|
|
net (fo=32, routed) 3.132 9.510 base_ram_data_IOBUF[1]_inst/T
|
|
L25 f base_ram_data_IOBUF[1]_inst/OBUFT/T
|
|
L25 OBUFT (TriStatE_obuft_T_O)
|
|
3.564 13.074 r base_ram_data_IOBUF[1]_inst/OBUFT/O
|
|
net (fo=1, unset) 0.000 13.074 base_ram_data[1]
|
|
L25 r base_ram_data[1] (INOUT)
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock sys_clk rise edge) 20.000 20.000 r
|
|
clock source latency -5.674 14.326
|
|
propagated clock network latency
|
|
0.000 14.326
|
|
clock pessimism -0.601 13.725
|
|
clock uncertainty -0.071 13.654
|
|
output delay -0.300 13.354
|
|
-------------------------------------------------------------------
|
|
required time 13.354
|
|
arrival time -13.074
|
|
-------------------------------------------------------------------
|
|
slack 0.280
|
|
|
|
Slack (MET) : 0.280ns (required time - arrival time)
|
|
Source: u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[3]/C
|
|
(rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Destination: base_ram_data[1]
|
|
(output port clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Path Group: sys_clk
|
|
Path Type: Max at Slow Process Corner
|
|
Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns)
|
|
Data Path Delay: 15.395ns (logic 6.881ns (44.698%) route 8.514ns (55.302%))
|
|
Logic Levels: 14 (CARRY4=6 LUT3=1 LUT4=2 LUT5=1 LUT6=3 OBUFT=1)
|
|
Output Delay: 0.300ns
|
|
Clock Path Skew: -3.955ns (DCD - SCD + CPR)
|
|
Destination Clock Delay (DCD): -5.674ns = ( 14.326 - 20.000 )
|
|
Source Clock Delay (SCD): -2.321ns
|
|
Clock Pessimism Removal (CPR): -0.601ns
|
|
Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Discrete Jitter (DJ): 0.122ns
|
|
Phase Error (PE): 0.000ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock sys_clk rise edge) 0.000 0.000 r
|
|
clock source latency -6.275 -6.275
|
|
propagated clock network latency
|
|
3.955 -2.321
|
|
SLICE_X7Y62 FDCE 0.000 -2.321 r u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[3]/C
|
|
SLICE_X7Y62 FDCE (Prop_fdce_C_Q) 0.456 -1.865 f u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[3]/Q
|
|
net (fo=54, routed) 0.726 -1.139 u_axi_ram/u_axi_sram_sp/len[3]
|
|
SLICE_X7Y61 f u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6/I3
|
|
SLICE_X7Y61 LUT4 (Prop_lut4_I3_O) 0.124 -1.015 r u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6/O
|
|
net (fo=4, routed) 0.946 -0.068 u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6_n_0
|
|
SLICE_X7Y58 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_11/I1
|
|
SLICE_X7Y58 LUT5 (Prop_lut5_I1_O) 0.124 0.056 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_11/O
|
|
net (fo=2, routed) 0.619 0.675 u_axi_ram/u_axi_sram_sp/state_d2[7]
|
|
SLICE_X6Y59 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_15/I5
|
|
SLICE_X6Y59 LUT6 (Prop_lut6_I5_O) 0.124 0.799 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_15/O
|
|
net (fo=1, routed) 0.000 0.799 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_15_n_0
|
|
SLICE_X6Y59 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9/S[3]
|
|
SLICE_X6Y59 CARRY4 (Prop_carry4_S[3]_CO[3])
|
|
0.376 1.175 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9/CO[3]
|
|
net (fo=1, routed) 0.000 1.175 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9_n_0
|
|
SLICE_X6Y60 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/CI
|
|
SLICE_X6Y60 CARRY4 (Prop_carry4_CI_CO[3])
|
|
0.117 1.292 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/CO[3]
|
|
net (fo=1, routed) 0.000 1.292 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10_n_0
|
|
SLICE_X6Y61 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CI
|
|
SLICE_X6Y61 CARRY4 (Prop_carry4_CI_CO[3])
|
|
0.117 1.409 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CO[3]
|
|
net (fo=1, routed) 0.000 1.409 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9_n_0
|
|
SLICE_X6Y62 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/CI
|
|
SLICE_X6Y62 CARRY4 (Prop_carry4_CI_O[2])
|
|
0.239 1.648 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/O[2]
|
|
net (fo=3, routed) 0.929 2.576 u_axi_ram/u_axi_sram_sp/upper_wrap_boundary[20]
|
|
SLICE_X5Y65 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_7/I2
|
|
SLICE_X5Y65 LUT4 (Prop_lut4_I2_O) 0.301 2.877 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_7/O
|
|
net (fo=1, routed) 0.000 2.877 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_7_n_0
|
|
SLICE_X5Y65 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1/S[1]
|
|
SLICE_X5Y65 CARRY4 (Prop_carry4_S[1]_CO[3])
|
|
0.550 3.427 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1/CO[3]
|
|
net (fo=1, routed) 0.000 3.427 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_n_0
|
|
SLICE_X5Y66 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2/CI
|
|
SLICE_X5Y66 CARRY4 (Prop_carry4_CI_CO[2])
|
|
0.228 3.655 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2/CO[2]
|
|
net (fo=22, routed) 0.735 4.390 u_axi_ram/u_axi_sram_sp/req_addr_d1
|
|
SLICE_X5Y68 r u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/I0
|
|
SLICE_X5Y68 LUT6 (Prop_lut6_I0_O) 0.313 4.703 f u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/O
|
|
net (fo=2, routed) 0.550 5.253 u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7_n_0
|
|
SLICE_X4Y68 f u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/I1
|
|
SLICE_X4Y68 LUT6 (Prop_lut6_I1_O) 0.124 5.377 f u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/O
|
|
net (fo=80, routed) 0.877 6.254 u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/soc_sram_addr[0]
|
|
SLICE_X1Y74 f u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/base_ram_data_IOBUF[31]_inst_i_3/I2
|
|
SLICE_X1Y74 LUT3 (Prop_lut3_I2_O) 0.124 6.378 f u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/base_ram_data_IOBUF[31]_inst_i_3/O
|
|
net (fo=32, routed) 3.132 9.510 base_ram_data_IOBUF[1]_inst/T
|
|
L25 f base_ram_data_IOBUF[1]_inst/OBUFT/T
|
|
L25 OBUFT (TriStatE_obuft_T_O)
|
|
3.564 13.074 r base_ram_data_IOBUF[1]_inst/OBUFT/O
|
|
net (fo=1, unset) 0.000 13.074 base_ram_data[1]
|
|
L25 r base_ram_data[1] (INOUT)
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock sys_clk rise edge) 20.000 20.000 r
|
|
clock source latency -5.674 14.326
|
|
propagated clock network latency
|
|
0.000 14.326
|
|
clock pessimism -0.601 13.725
|
|
clock uncertainty -0.071 13.654
|
|
output delay -0.300 13.354
|
|
-------------------------------------------------------------------
|
|
required time 13.354
|
|
arrival time -13.074
|
|
-------------------------------------------------------------------
|
|
slack 0.280
|
|
|
|
Slack (MET) : 0.280ns (required time - arrival time)
|
|
Source: u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[3]/C
|
|
(rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Destination: base_ram_data[1]
|
|
(output port clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Path Group: sys_clk
|
|
Path Type: Max at Slow Process Corner
|
|
Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns)
|
|
Data Path Delay: 15.395ns (logic 6.881ns (44.698%) route 8.514ns (55.302%))
|
|
Logic Levels: 14 (CARRY4=6 LUT3=1 LUT4=2 LUT5=1 LUT6=3 OBUFT=1)
|
|
Output Delay: 0.300ns
|
|
Clock Path Skew: -3.955ns (DCD - SCD + CPR)
|
|
Destination Clock Delay (DCD): -5.674ns = ( 14.326 - 20.000 )
|
|
Source Clock Delay (SCD): -2.321ns
|
|
Clock Pessimism Removal (CPR): -0.601ns
|
|
Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Discrete Jitter (DJ): 0.122ns
|
|
Phase Error (PE): 0.000ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock sys_clk rise edge) 0.000 0.000 r
|
|
clock source latency -6.275 -6.275
|
|
propagated clock network latency
|
|
3.955 -2.321
|
|
SLICE_X7Y62 FDCE 0.000 -2.321 r u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[3]/C
|
|
SLICE_X7Y62 FDCE (Prop_fdce_C_Q) 0.456 -1.865 f u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[3]/Q
|
|
net (fo=54, routed) 0.726 -1.139 u_axi_ram/u_axi_sram_sp/len[3]
|
|
SLICE_X7Y61 f u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6/I3
|
|
SLICE_X7Y61 LUT4 (Prop_lut4_I3_O) 0.124 -1.015 r u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6/O
|
|
net (fo=4, routed) 0.946 -0.068 u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6_n_0
|
|
SLICE_X7Y58 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_11/I1
|
|
SLICE_X7Y58 LUT5 (Prop_lut5_I1_O) 0.124 0.056 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_11/O
|
|
net (fo=2, routed) 0.619 0.675 u_axi_ram/u_axi_sram_sp/state_d2[7]
|
|
SLICE_X6Y59 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_15/I5
|
|
SLICE_X6Y59 LUT6 (Prop_lut6_I5_O) 0.124 0.799 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_15/O
|
|
net (fo=1, routed) 0.000 0.799 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_15_n_0
|
|
SLICE_X6Y59 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9/S[3]
|
|
SLICE_X6Y59 CARRY4 (Prop_carry4_S[3]_CO[3])
|
|
0.376 1.175 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9/CO[3]
|
|
net (fo=1, routed) 0.000 1.175 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9_n_0
|
|
SLICE_X6Y60 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/CI
|
|
SLICE_X6Y60 CARRY4 (Prop_carry4_CI_CO[3])
|
|
0.117 1.292 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/CO[3]
|
|
net (fo=1, routed) 0.000 1.292 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10_n_0
|
|
SLICE_X6Y61 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CI
|
|
SLICE_X6Y61 CARRY4 (Prop_carry4_CI_CO[3])
|
|
0.117 1.409 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CO[3]
|
|
net (fo=1, routed) 0.000 1.409 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9_n_0
|
|
SLICE_X6Y62 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/CI
|
|
SLICE_X6Y62 CARRY4 (Prop_carry4_CI_O[2])
|
|
0.239 1.648 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/O[2]
|
|
net (fo=3, routed) 0.929 2.576 u_axi_ram/u_axi_sram_sp/upper_wrap_boundary[20]
|
|
SLICE_X5Y65 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_7/I2
|
|
SLICE_X5Y65 LUT4 (Prop_lut4_I2_O) 0.301 2.877 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_7/O
|
|
net (fo=1, routed) 0.000 2.877 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_7_n_0
|
|
SLICE_X5Y65 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1/S[1]
|
|
SLICE_X5Y65 CARRY4 (Prop_carry4_S[1]_CO[3])
|
|
0.550 3.427 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1/CO[3]
|
|
net (fo=1, routed) 0.000 3.427 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_n_0
|
|
SLICE_X5Y66 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2/CI
|
|
SLICE_X5Y66 CARRY4 (Prop_carry4_CI_CO[2])
|
|
0.228 3.655 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2/CO[2]
|
|
net (fo=22, routed) 0.735 4.390 u_axi_ram/u_axi_sram_sp/req_addr_d1
|
|
SLICE_X5Y68 r u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/I0
|
|
SLICE_X5Y68 LUT6 (Prop_lut6_I0_O) 0.313 4.703 f u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/O
|
|
net (fo=2, routed) 0.550 5.253 u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7_n_0
|
|
SLICE_X4Y68 f u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/I1
|
|
SLICE_X4Y68 LUT6 (Prop_lut6_I1_O) 0.124 5.377 f u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/O
|
|
net (fo=80, routed) 0.877 6.254 u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/soc_sram_addr[0]
|
|
SLICE_X1Y74 f u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/base_ram_data_IOBUF[31]_inst_i_3/I2
|
|
SLICE_X1Y74 LUT3 (Prop_lut3_I2_O) 0.124 6.378 f u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/base_ram_data_IOBUF[31]_inst_i_3/O
|
|
net (fo=32, routed) 3.132 9.510 base_ram_data_IOBUF[1]_inst/T
|
|
L25 f base_ram_data_IOBUF[1]_inst/OBUFT/T
|
|
L25 OBUFT (TriStatE_obuft_T_O)
|
|
3.564 13.074 r base_ram_data_IOBUF[1]_inst/OBUFT/O
|
|
net (fo=1, unset) 0.000 13.074 base_ram_data[1]
|
|
L25 r base_ram_data[1] (INOUT)
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock sys_clk rise edge) 20.000 20.000 r
|
|
clock source latency -5.674 14.326
|
|
propagated clock network latency
|
|
0.000 14.326
|
|
clock pessimism -0.601 13.725
|
|
clock uncertainty -0.071 13.654
|
|
output delay -0.300 13.354
|
|
-------------------------------------------------------------------
|
|
required time 13.354
|
|
arrival time -13.074
|
|
-------------------------------------------------------------------
|
|
slack 0.280
|
|
|
|
Slack (MET) : 0.280ns (required time - arrival time)
|
|
Source: u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[3]/C
|
|
(rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Destination: base_ram_data[1]
|
|
(output port clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Path Group: sys_clk
|
|
Path Type: Max at Slow Process Corner
|
|
Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns)
|
|
Data Path Delay: 15.395ns (logic 6.881ns (44.698%) route 8.514ns (55.302%))
|
|
Logic Levels: 14 (CARRY4=6 LUT3=1 LUT4=2 LUT5=1 LUT6=3 OBUFT=1)
|
|
Output Delay: 0.300ns
|
|
Clock Path Skew: -3.955ns (DCD - SCD + CPR)
|
|
Destination Clock Delay (DCD): -5.674ns = ( 14.326 - 20.000 )
|
|
Source Clock Delay (SCD): -2.321ns
|
|
Clock Pessimism Removal (CPR): -0.601ns
|
|
Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Discrete Jitter (DJ): 0.122ns
|
|
Phase Error (PE): 0.000ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock sys_clk rise edge) 0.000 0.000 r
|
|
clock source latency -6.275 -6.275
|
|
propagated clock network latency
|
|
3.955 -2.321
|
|
SLICE_X7Y62 FDCE 0.000 -2.321 r u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[3]/C
|
|
SLICE_X7Y62 FDCE (Prop_fdce_C_Q) 0.456 -1.865 f u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[3]/Q
|
|
net (fo=54, routed) 0.726 -1.139 u_axi_ram/u_axi_sram_sp/len[3]
|
|
SLICE_X7Y61 f u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6/I3
|
|
SLICE_X7Y61 LUT4 (Prop_lut4_I3_O) 0.124 -1.015 r u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6/O
|
|
net (fo=4, routed) 0.946 -0.068 u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6_n_0
|
|
SLICE_X7Y58 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_11/I1
|
|
SLICE_X7Y58 LUT5 (Prop_lut5_I1_O) 0.124 0.056 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_11/O
|
|
net (fo=2, routed) 0.619 0.675 u_axi_ram/u_axi_sram_sp/state_d2[7]
|
|
SLICE_X6Y59 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_15/I5
|
|
SLICE_X6Y59 LUT6 (Prop_lut6_I5_O) 0.124 0.799 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_15/O
|
|
net (fo=1, routed) 0.000 0.799 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_15_n_0
|
|
SLICE_X6Y59 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9/S[3]
|
|
SLICE_X6Y59 CARRY4 (Prop_carry4_S[3]_CO[3])
|
|
0.376 1.175 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9/CO[3]
|
|
net (fo=1, routed) 0.000 1.175 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9_n_0
|
|
SLICE_X6Y60 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/CI
|
|
SLICE_X6Y60 CARRY4 (Prop_carry4_CI_CO[3])
|
|
0.117 1.292 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/CO[3]
|
|
net (fo=1, routed) 0.000 1.292 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10_n_0
|
|
SLICE_X6Y61 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CI
|
|
SLICE_X6Y61 CARRY4 (Prop_carry4_CI_CO[3])
|
|
0.117 1.409 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CO[3]
|
|
net (fo=1, routed) 0.000 1.409 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9_n_0
|
|
SLICE_X6Y62 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/CI
|
|
SLICE_X6Y62 CARRY4 (Prop_carry4_CI_O[2])
|
|
0.239 1.648 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/O[2]
|
|
net (fo=3, routed) 0.929 2.576 u_axi_ram/u_axi_sram_sp/upper_wrap_boundary[20]
|
|
SLICE_X5Y65 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_7/I2
|
|
SLICE_X5Y65 LUT4 (Prop_lut4_I2_O) 0.301 2.877 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_7/O
|
|
net (fo=1, routed) 0.000 2.877 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_7_n_0
|
|
SLICE_X5Y65 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1/S[1]
|
|
SLICE_X5Y65 CARRY4 (Prop_carry4_S[1]_CO[3])
|
|
0.550 3.427 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1/CO[3]
|
|
net (fo=1, routed) 0.000 3.427 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_n_0
|
|
SLICE_X5Y66 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2/CI
|
|
SLICE_X5Y66 CARRY4 (Prop_carry4_CI_CO[2])
|
|
0.228 3.655 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2/CO[2]
|
|
net (fo=22, routed) 0.735 4.390 u_axi_ram/u_axi_sram_sp/req_addr_d1
|
|
SLICE_X5Y68 r u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/I0
|
|
SLICE_X5Y68 LUT6 (Prop_lut6_I0_O) 0.313 4.703 f u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/O
|
|
net (fo=2, routed) 0.550 5.253 u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7_n_0
|
|
SLICE_X4Y68 f u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/I1
|
|
SLICE_X4Y68 LUT6 (Prop_lut6_I1_O) 0.124 5.377 f u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/O
|
|
net (fo=80, routed) 0.877 6.254 u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/soc_sram_addr[0]
|
|
SLICE_X1Y74 f u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/base_ram_data_IOBUF[31]_inst_i_3/I2
|
|
SLICE_X1Y74 LUT3 (Prop_lut3_I2_O) 0.124 6.378 f u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/base_ram_data_IOBUF[31]_inst_i_3/O
|
|
net (fo=32, routed) 3.132 9.510 base_ram_data_IOBUF[1]_inst/T
|
|
L25 f base_ram_data_IOBUF[1]_inst/OBUFT/T
|
|
L25 OBUFT (TriStatE_obuft_T_O)
|
|
3.564 13.074 r base_ram_data_IOBUF[1]_inst/OBUFT/O
|
|
net (fo=1, unset) 0.000 13.074 base_ram_data[1]
|
|
L25 r base_ram_data[1] (INOUT)
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock sys_clk rise edge) 20.000 20.000 r
|
|
clock source latency -5.674 14.326
|
|
propagated clock network latency
|
|
0.000 14.326
|
|
clock pessimism -0.601 13.725
|
|
clock uncertainty -0.071 13.654
|
|
output delay -0.300 13.354
|
|
-------------------------------------------------------------------
|
|
required time 13.354
|
|
arrival time -13.074
|
|
-------------------------------------------------------------------
|
|
slack 0.280
|
|
|
|
Slack (MET) : 0.280ns (required time - arrival time)
|
|
Source: u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[3]/C
|
|
(rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Destination: base_ram_data[1]
|
|
(output port clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Path Group: sys_clk
|
|
Path Type: Max at Slow Process Corner
|
|
Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns)
|
|
Data Path Delay: 15.395ns (logic 6.881ns (44.698%) route 8.514ns (55.302%))
|
|
Logic Levels: 14 (CARRY4=6 LUT3=1 LUT4=2 LUT5=1 LUT6=3 OBUFT=1)
|
|
Output Delay: 0.300ns
|
|
Clock Path Skew: -3.955ns (DCD - SCD + CPR)
|
|
Destination Clock Delay (DCD): -5.674ns = ( 14.326 - 20.000 )
|
|
Source Clock Delay (SCD): -2.321ns
|
|
Clock Pessimism Removal (CPR): -0.601ns
|
|
Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Discrete Jitter (DJ): 0.122ns
|
|
Phase Error (PE): 0.000ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock sys_clk rise edge) 0.000 0.000 r
|
|
clock source latency -6.275 -6.275
|
|
propagated clock network latency
|
|
3.955 -2.321
|
|
SLICE_X7Y62 FDCE 0.000 -2.321 r u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[3]/C
|
|
SLICE_X7Y62 FDCE (Prop_fdce_C_Q) 0.456 -1.865 f u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[3]/Q
|
|
net (fo=54, routed) 0.726 -1.139 u_axi_ram/u_axi_sram_sp/len[3]
|
|
SLICE_X7Y61 f u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6/I3
|
|
SLICE_X7Y61 LUT4 (Prop_lut4_I3_O) 0.124 -1.015 r u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6/O
|
|
net (fo=4, routed) 0.946 -0.068 u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6_n_0
|
|
SLICE_X7Y58 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_11/I1
|
|
SLICE_X7Y58 LUT5 (Prop_lut5_I1_O) 0.124 0.056 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_11/O
|
|
net (fo=2, routed) 0.619 0.675 u_axi_ram/u_axi_sram_sp/state_d2[7]
|
|
SLICE_X6Y59 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_15/I5
|
|
SLICE_X6Y59 LUT6 (Prop_lut6_I5_O) 0.124 0.799 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_15/O
|
|
net (fo=1, routed) 0.000 0.799 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_15_n_0
|
|
SLICE_X6Y59 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9/S[3]
|
|
SLICE_X6Y59 CARRY4 (Prop_carry4_S[3]_CO[3])
|
|
0.376 1.175 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9/CO[3]
|
|
net (fo=1, routed) 0.000 1.175 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9_n_0
|
|
SLICE_X6Y60 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/CI
|
|
SLICE_X6Y60 CARRY4 (Prop_carry4_CI_CO[3])
|
|
0.117 1.292 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/CO[3]
|
|
net (fo=1, routed) 0.000 1.292 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10_n_0
|
|
SLICE_X6Y61 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CI
|
|
SLICE_X6Y61 CARRY4 (Prop_carry4_CI_CO[3])
|
|
0.117 1.409 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CO[3]
|
|
net (fo=1, routed) 0.000 1.409 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9_n_0
|
|
SLICE_X6Y62 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/CI
|
|
SLICE_X6Y62 CARRY4 (Prop_carry4_CI_O[2])
|
|
0.239 1.648 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/O[2]
|
|
net (fo=3, routed) 0.929 2.576 u_axi_ram/u_axi_sram_sp/upper_wrap_boundary[20]
|
|
SLICE_X5Y65 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_7/I2
|
|
SLICE_X5Y65 LUT4 (Prop_lut4_I2_O) 0.301 2.877 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_7/O
|
|
net (fo=1, routed) 0.000 2.877 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_7_n_0
|
|
SLICE_X5Y65 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1/S[1]
|
|
SLICE_X5Y65 CARRY4 (Prop_carry4_S[1]_CO[3])
|
|
0.550 3.427 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1/CO[3]
|
|
net (fo=1, routed) 0.000 3.427 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_n_0
|
|
SLICE_X5Y66 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2/CI
|
|
SLICE_X5Y66 CARRY4 (Prop_carry4_CI_CO[2])
|
|
0.228 3.655 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2/CO[2]
|
|
net (fo=22, routed) 0.735 4.390 u_axi_ram/u_axi_sram_sp/req_addr_d1
|
|
SLICE_X5Y68 r u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/I0
|
|
SLICE_X5Y68 LUT6 (Prop_lut6_I0_O) 0.313 4.703 f u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/O
|
|
net (fo=2, routed) 0.550 5.253 u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7_n_0
|
|
SLICE_X4Y68 f u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/I1
|
|
SLICE_X4Y68 LUT6 (Prop_lut6_I1_O) 0.124 5.377 f u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/O
|
|
net (fo=80, routed) 0.877 6.254 u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/soc_sram_addr[0]
|
|
SLICE_X1Y74 f u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/base_ram_data_IOBUF[31]_inst_i_3/I2
|
|
SLICE_X1Y74 LUT3 (Prop_lut3_I2_O) 0.124 6.378 f u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/base_ram_data_IOBUF[31]_inst_i_3/O
|
|
net (fo=32, routed) 3.132 9.510 base_ram_data_IOBUF[1]_inst/T
|
|
L25 f base_ram_data_IOBUF[1]_inst/OBUFT/T
|
|
L25 OBUFT (TriStatE_obuft_T_O)
|
|
3.564 13.074 r base_ram_data_IOBUF[1]_inst/OBUFT/O
|
|
net (fo=1, unset) 0.000 13.074 base_ram_data[1]
|
|
L25 r base_ram_data[1] (INOUT)
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock sys_clk rise edge) 20.000 20.000 r
|
|
clock source latency -5.674 14.326
|
|
propagated clock network latency
|
|
0.000 14.326
|
|
clock pessimism -0.601 13.725
|
|
clock uncertainty -0.071 13.654
|
|
output delay -0.300 13.354
|
|
-------------------------------------------------------------------
|
|
required time 13.354
|
|
arrival time -13.074
|
|
-------------------------------------------------------------------
|
|
slack 0.280
|
|
|
|
Slack (MET) : 0.280ns (required time - arrival time)
|
|
Source: u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[3]/C
|
|
(rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Destination: base_ram_data[1]
|
|
(output port clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Path Group: sys_clk
|
|
Path Type: Max at Slow Process Corner
|
|
Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns)
|
|
Data Path Delay: 15.395ns (logic 6.881ns (44.698%) route 8.514ns (55.302%))
|
|
Logic Levels: 14 (CARRY4=6 LUT3=1 LUT4=2 LUT5=1 LUT6=3 OBUFT=1)
|
|
Output Delay: 0.300ns
|
|
Clock Path Skew: -3.955ns (DCD - SCD + CPR)
|
|
Destination Clock Delay (DCD): -5.674ns = ( 14.326 - 20.000 )
|
|
Source Clock Delay (SCD): -2.321ns
|
|
Clock Pessimism Removal (CPR): -0.601ns
|
|
Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Discrete Jitter (DJ): 0.122ns
|
|
Phase Error (PE): 0.000ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock sys_clk rise edge) 0.000 0.000 r
|
|
clock source latency -6.275 -6.275
|
|
propagated clock network latency
|
|
3.955 -2.321
|
|
SLICE_X7Y62 FDCE 0.000 -2.321 r u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[3]/C
|
|
SLICE_X7Y62 FDCE (Prop_fdce_C_Q) 0.456 -1.865 f u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[3]/Q
|
|
net (fo=54, routed) 0.726 -1.139 u_axi_ram/u_axi_sram_sp/len[3]
|
|
SLICE_X7Y61 f u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6/I3
|
|
SLICE_X7Y61 LUT4 (Prop_lut4_I3_O) 0.124 -1.015 r u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6/O
|
|
net (fo=4, routed) 0.946 -0.068 u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6_n_0
|
|
SLICE_X7Y58 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_11/I1
|
|
SLICE_X7Y58 LUT5 (Prop_lut5_I1_O) 0.124 0.056 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_11/O
|
|
net (fo=2, routed) 0.619 0.675 u_axi_ram/u_axi_sram_sp/state_d2[7]
|
|
SLICE_X6Y59 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_15/I5
|
|
SLICE_X6Y59 LUT6 (Prop_lut6_I5_O) 0.124 0.799 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_15/O
|
|
net (fo=1, routed) 0.000 0.799 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_15_n_0
|
|
SLICE_X6Y59 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9/S[3]
|
|
SLICE_X6Y59 CARRY4 (Prop_carry4_S[3]_CO[3])
|
|
0.376 1.175 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9/CO[3]
|
|
net (fo=1, routed) 0.000 1.175 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9_n_0
|
|
SLICE_X6Y60 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/CI
|
|
SLICE_X6Y60 CARRY4 (Prop_carry4_CI_CO[3])
|
|
0.117 1.292 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/CO[3]
|
|
net (fo=1, routed) 0.000 1.292 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10_n_0
|
|
SLICE_X6Y61 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CI
|
|
SLICE_X6Y61 CARRY4 (Prop_carry4_CI_CO[3])
|
|
0.117 1.409 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CO[3]
|
|
net (fo=1, routed) 0.000 1.409 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9_n_0
|
|
SLICE_X6Y62 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/CI
|
|
SLICE_X6Y62 CARRY4 (Prop_carry4_CI_O[2])
|
|
0.239 1.648 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/O[2]
|
|
net (fo=3, routed) 0.929 2.576 u_axi_ram/u_axi_sram_sp/upper_wrap_boundary[20]
|
|
SLICE_X5Y65 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_7/I2
|
|
SLICE_X5Y65 LUT4 (Prop_lut4_I2_O) 0.301 2.877 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_7/O
|
|
net (fo=1, routed) 0.000 2.877 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_7_n_0
|
|
SLICE_X5Y65 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1/S[1]
|
|
SLICE_X5Y65 CARRY4 (Prop_carry4_S[1]_CO[3])
|
|
0.550 3.427 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1/CO[3]
|
|
net (fo=1, routed) 0.000 3.427 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_n_0
|
|
SLICE_X5Y66 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2/CI
|
|
SLICE_X5Y66 CARRY4 (Prop_carry4_CI_CO[2])
|
|
0.228 3.655 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2/CO[2]
|
|
net (fo=22, routed) 0.735 4.390 u_axi_ram/u_axi_sram_sp/req_addr_d1
|
|
SLICE_X5Y68 r u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/I0
|
|
SLICE_X5Y68 LUT6 (Prop_lut6_I0_O) 0.313 4.703 f u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/O
|
|
net (fo=2, routed) 0.550 5.253 u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7_n_0
|
|
SLICE_X4Y68 f u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/I1
|
|
SLICE_X4Y68 LUT6 (Prop_lut6_I1_O) 0.124 5.377 f u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/O
|
|
net (fo=80, routed) 0.877 6.254 u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/soc_sram_addr[0]
|
|
SLICE_X1Y74 f u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/base_ram_data_IOBUF[31]_inst_i_3/I2
|
|
SLICE_X1Y74 LUT3 (Prop_lut3_I2_O) 0.124 6.378 f u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/base_ram_data_IOBUF[31]_inst_i_3/O
|
|
net (fo=32, routed) 3.132 9.510 base_ram_data_IOBUF[1]_inst/T
|
|
L25 f base_ram_data_IOBUF[1]_inst/OBUFT/T
|
|
L25 OBUFT (TriStatE_obuft_T_O)
|
|
3.564 13.074 r base_ram_data_IOBUF[1]_inst/OBUFT/O
|
|
net (fo=1, unset) 0.000 13.074 base_ram_data[1]
|
|
L25 r base_ram_data[1] (INOUT)
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock sys_clk rise edge) 20.000 20.000 r
|
|
clock source latency -5.674 14.326
|
|
propagated clock network latency
|
|
0.000 14.326
|
|
clock pessimism -0.601 13.725
|
|
clock uncertainty -0.071 13.654
|
|
output delay -0.300 13.354
|
|
-------------------------------------------------------------------
|
|
required time 13.354
|
|
arrival time -13.074
|
|
-------------------------------------------------------------------
|
|
slack 0.280
|
|
|
|
Slack (MET) : 0.280ns (required time - arrival time)
|
|
Source: u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[3]/C
|
|
(rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Destination: base_ram_data[1]
|
|
(output port clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Path Group: sys_clk
|
|
Path Type: Max at Slow Process Corner
|
|
Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns)
|
|
Data Path Delay: 15.395ns (logic 6.881ns (44.698%) route 8.514ns (55.302%))
|
|
Logic Levels: 14 (CARRY4=6 LUT3=1 LUT4=2 LUT5=1 LUT6=3 OBUFT=1)
|
|
Output Delay: 0.300ns
|
|
Clock Path Skew: -3.955ns (DCD - SCD + CPR)
|
|
Destination Clock Delay (DCD): -5.674ns = ( 14.326 - 20.000 )
|
|
Source Clock Delay (SCD): -2.321ns
|
|
Clock Pessimism Removal (CPR): -0.601ns
|
|
Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Discrete Jitter (DJ): 0.122ns
|
|
Phase Error (PE): 0.000ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock sys_clk rise edge) 0.000 0.000 r
|
|
clock source latency -6.275 -6.275
|
|
propagated clock network latency
|
|
3.955 -2.321
|
|
SLICE_X7Y62 FDCE 0.000 -2.321 r u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[3]/C
|
|
SLICE_X7Y62 FDCE (Prop_fdce_C_Q) 0.456 -1.865 f u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[3]/Q
|
|
net (fo=54, routed) 0.726 -1.139 u_axi_ram/u_axi_sram_sp/len[3]
|
|
SLICE_X7Y61 f u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6/I3
|
|
SLICE_X7Y61 LUT4 (Prop_lut4_I3_O) 0.124 -1.015 r u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6/O
|
|
net (fo=4, routed) 0.946 -0.068 u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6_n_0
|
|
SLICE_X7Y58 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_11/I1
|
|
SLICE_X7Y58 LUT5 (Prop_lut5_I1_O) 0.124 0.056 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_11/O
|
|
net (fo=2, routed) 0.619 0.675 u_axi_ram/u_axi_sram_sp/state_d2[7]
|
|
SLICE_X6Y59 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_15/I5
|
|
SLICE_X6Y59 LUT6 (Prop_lut6_I5_O) 0.124 0.799 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_15/O
|
|
net (fo=1, routed) 0.000 0.799 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_15_n_0
|
|
SLICE_X6Y59 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9/S[3]
|
|
SLICE_X6Y59 CARRY4 (Prop_carry4_S[3]_CO[3])
|
|
0.376 1.175 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9/CO[3]
|
|
net (fo=1, routed) 0.000 1.175 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9_n_0
|
|
SLICE_X6Y60 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/CI
|
|
SLICE_X6Y60 CARRY4 (Prop_carry4_CI_CO[3])
|
|
0.117 1.292 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/CO[3]
|
|
net (fo=1, routed) 0.000 1.292 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10_n_0
|
|
SLICE_X6Y61 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CI
|
|
SLICE_X6Y61 CARRY4 (Prop_carry4_CI_CO[3])
|
|
0.117 1.409 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CO[3]
|
|
net (fo=1, routed) 0.000 1.409 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9_n_0
|
|
SLICE_X6Y62 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/CI
|
|
SLICE_X6Y62 CARRY4 (Prop_carry4_CI_O[2])
|
|
0.239 1.648 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/O[2]
|
|
net (fo=3, routed) 0.929 2.576 u_axi_ram/u_axi_sram_sp/upper_wrap_boundary[20]
|
|
SLICE_X5Y65 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_7/I2
|
|
SLICE_X5Y65 LUT4 (Prop_lut4_I2_O) 0.301 2.877 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_7/O
|
|
net (fo=1, routed) 0.000 2.877 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_7_n_0
|
|
SLICE_X5Y65 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1/S[1]
|
|
SLICE_X5Y65 CARRY4 (Prop_carry4_S[1]_CO[3])
|
|
0.550 3.427 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1/CO[3]
|
|
net (fo=1, routed) 0.000 3.427 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_n_0
|
|
SLICE_X5Y66 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2/CI
|
|
SLICE_X5Y66 CARRY4 (Prop_carry4_CI_CO[2])
|
|
0.228 3.655 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2/CO[2]
|
|
net (fo=22, routed) 0.735 4.390 u_axi_ram/u_axi_sram_sp/req_addr_d1
|
|
SLICE_X5Y68 r u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/I0
|
|
SLICE_X5Y68 LUT6 (Prop_lut6_I0_O) 0.313 4.703 f u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/O
|
|
net (fo=2, routed) 0.550 5.253 u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7_n_0
|
|
SLICE_X4Y68 f u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/I1
|
|
SLICE_X4Y68 LUT6 (Prop_lut6_I1_O) 0.124 5.377 f u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/O
|
|
net (fo=80, routed) 0.877 6.254 u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/soc_sram_addr[0]
|
|
SLICE_X1Y74 f u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/base_ram_data_IOBUF[31]_inst_i_3/I2
|
|
SLICE_X1Y74 LUT3 (Prop_lut3_I2_O) 0.124 6.378 f u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/base_ram_data_IOBUF[31]_inst_i_3/O
|
|
net (fo=32, routed) 3.132 9.510 base_ram_data_IOBUF[1]_inst/T
|
|
L25 f base_ram_data_IOBUF[1]_inst/OBUFT/T
|
|
L25 OBUFT (TriStatE_obuft_T_O)
|
|
3.564 13.074 r base_ram_data_IOBUF[1]_inst/OBUFT/O
|
|
net (fo=1, unset) 0.000 13.074 base_ram_data[1]
|
|
L25 r base_ram_data[1] (INOUT)
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock sys_clk rise edge) 20.000 20.000 r
|
|
clock source latency -5.674 14.326
|
|
propagated clock network latency
|
|
0.000 14.326
|
|
clock pessimism -0.601 13.725
|
|
clock uncertainty -0.071 13.654
|
|
output delay -0.300 13.354
|
|
-------------------------------------------------------------------
|
|
required time 13.354
|
|
arrival time -13.074
|
|
-------------------------------------------------------------------
|
|
slack 0.280
|
|
|
|
Slack (MET) : 0.280ns (required time - arrival time)
|
|
Source: u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[3]/C
|
|
(rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Destination: base_ram_data[1]
|
|
(output port clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Path Group: sys_clk
|
|
Path Type: Max at Slow Process Corner
|
|
Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns)
|
|
Data Path Delay: 15.395ns (logic 6.881ns (44.698%) route 8.514ns (55.302%))
|
|
Logic Levels: 14 (CARRY4=6 LUT3=1 LUT4=2 LUT5=1 LUT6=3 OBUFT=1)
|
|
Output Delay: 0.300ns
|
|
Clock Path Skew: -3.955ns (DCD - SCD + CPR)
|
|
Destination Clock Delay (DCD): -5.674ns = ( 14.326 - 20.000 )
|
|
Source Clock Delay (SCD): -2.321ns
|
|
Clock Pessimism Removal (CPR): -0.601ns
|
|
Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Discrete Jitter (DJ): 0.122ns
|
|
Phase Error (PE): 0.000ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock sys_clk rise edge) 0.000 0.000 r
|
|
clock source latency -6.275 -6.275
|
|
propagated clock network latency
|
|
3.955 -2.321
|
|
SLICE_X7Y62 FDCE 0.000 -2.321 r u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[3]/C
|
|
SLICE_X7Y62 FDCE (Prop_fdce_C_Q) 0.456 -1.865 f u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[3]/Q
|
|
net (fo=54, routed) 0.726 -1.139 u_axi_ram/u_axi_sram_sp/len[3]
|
|
SLICE_X7Y61 f u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6/I3
|
|
SLICE_X7Y61 LUT4 (Prop_lut4_I3_O) 0.124 -1.015 r u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6/O
|
|
net (fo=4, routed) 0.946 -0.068 u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6_n_0
|
|
SLICE_X7Y58 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_11/I1
|
|
SLICE_X7Y58 LUT5 (Prop_lut5_I1_O) 0.124 0.056 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_11/O
|
|
net (fo=2, routed) 0.619 0.675 u_axi_ram/u_axi_sram_sp/state_d2[7]
|
|
SLICE_X6Y59 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_15/I5
|
|
SLICE_X6Y59 LUT6 (Prop_lut6_I5_O) 0.124 0.799 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_15/O
|
|
net (fo=1, routed) 0.000 0.799 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_15_n_0
|
|
SLICE_X6Y59 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9/S[3]
|
|
SLICE_X6Y59 CARRY4 (Prop_carry4_S[3]_CO[3])
|
|
0.376 1.175 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9/CO[3]
|
|
net (fo=1, routed) 0.000 1.175 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9_n_0
|
|
SLICE_X6Y60 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/CI
|
|
SLICE_X6Y60 CARRY4 (Prop_carry4_CI_CO[3])
|
|
0.117 1.292 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/CO[3]
|
|
net (fo=1, routed) 0.000 1.292 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10_n_0
|
|
SLICE_X6Y61 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CI
|
|
SLICE_X6Y61 CARRY4 (Prop_carry4_CI_CO[3])
|
|
0.117 1.409 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CO[3]
|
|
net (fo=1, routed) 0.000 1.409 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9_n_0
|
|
SLICE_X6Y62 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/CI
|
|
SLICE_X6Y62 CARRY4 (Prop_carry4_CI_O[2])
|
|
0.239 1.648 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/O[2]
|
|
net (fo=3, routed) 0.929 2.576 u_axi_ram/u_axi_sram_sp/upper_wrap_boundary[20]
|
|
SLICE_X5Y65 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_7/I2
|
|
SLICE_X5Y65 LUT4 (Prop_lut4_I2_O) 0.301 2.877 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_7/O
|
|
net (fo=1, routed) 0.000 2.877 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_7_n_0
|
|
SLICE_X5Y65 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1/S[1]
|
|
SLICE_X5Y65 CARRY4 (Prop_carry4_S[1]_CO[3])
|
|
0.550 3.427 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1/CO[3]
|
|
net (fo=1, routed) 0.000 3.427 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_n_0
|
|
SLICE_X5Y66 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2/CI
|
|
SLICE_X5Y66 CARRY4 (Prop_carry4_CI_CO[2])
|
|
0.228 3.655 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2/CO[2]
|
|
net (fo=22, routed) 0.735 4.390 u_axi_ram/u_axi_sram_sp/req_addr_d1
|
|
SLICE_X5Y68 r u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/I0
|
|
SLICE_X5Y68 LUT6 (Prop_lut6_I0_O) 0.313 4.703 f u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/O
|
|
net (fo=2, routed) 0.550 5.253 u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7_n_0
|
|
SLICE_X4Y68 f u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/I1
|
|
SLICE_X4Y68 LUT6 (Prop_lut6_I1_O) 0.124 5.377 f u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/O
|
|
net (fo=80, routed) 0.877 6.254 u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/soc_sram_addr[0]
|
|
SLICE_X1Y74 f u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/base_ram_data_IOBUF[31]_inst_i_3/I2
|
|
SLICE_X1Y74 LUT3 (Prop_lut3_I2_O) 0.124 6.378 f u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/base_ram_data_IOBUF[31]_inst_i_3/O
|
|
net (fo=32, routed) 3.132 9.510 base_ram_data_IOBUF[1]_inst/T
|
|
L25 f base_ram_data_IOBUF[1]_inst/OBUFT/T
|
|
L25 OBUFT (TriStatE_obuft_T_O)
|
|
3.564 13.074 r base_ram_data_IOBUF[1]_inst/OBUFT/O
|
|
net (fo=1, unset) 0.000 13.074 base_ram_data[1]
|
|
L25 r base_ram_data[1] (INOUT)
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock sys_clk rise edge) 20.000 20.000 r
|
|
clock source latency -5.674 14.326
|
|
propagated clock network latency
|
|
0.000 14.326
|
|
clock pessimism -0.601 13.725
|
|
clock uncertainty -0.071 13.654
|
|
output delay -0.300 13.354
|
|
-------------------------------------------------------------------
|
|
required time 13.354
|
|
arrival time -13.074
|
|
-------------------------------------------------------------------
|
|
slack 0.280
|
|
|
|
Slack (MET) : 0.281ns (required time - arrival time)
|
|
Source: u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[3]/C
|
|
(rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Destination: ext_ram_data[21]
|
|
(output port clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Path Group: sys_clk
|
|
Path Type: Max at Slow Process Corner
|
|
Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns)
|
|
Data Path Delay: 15.394ns (logic 6.863ns (44.584%) route 8.531ns (55.416%))
|
|
Logic Levels: 14 (CARRY4=6 LUT3=1 LUT4=2 LUT5=1 LUT6=3 OBUFT=1)
|
|
Output Delay: 0.300ns
|
|
Clock Path Skew: -3.955ns (DCD - SCD + CPR)
|
|
Destination Clock Delay (DCD): -5.674ns = ( 14.326 - 20.000 )
|
|
Source Clock Delay (SCD): -2.321ns
|
|
Clock Pessimism Removal (CPR): -0.601ns
|
|
Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Discrete Jitter (DJ): 0.122ns
|
|
Phase Error (PE): 0.000ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock sys_clk rise edge) 0.000 0.000 r
|
|
clock source latency -6.275 -6.275
|
|
propagated clock network latency
|
|
3.955 -2.321
|
|
SLICE_X7Y62 FDCE 0.000 -2.321 r u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[3]/C
|
|
SLICE_X7Y62 FDCE (Prop_fdce_C_Q) 0.456 -1.865 f u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[3]/Q
|
|
net (fo=54, routed) 0.726 -1.139 u_axi_ram/u_axi_sram_sp/len[3]
|
|
SLICE_X7Y61 f u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6/I3
|
|
SLICE_X7Y61 LUT4 (Prop_lut4_I3_O) 0.124 -1.015 r u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6/O
|
|
net (fo=4, routed) 0.946 -0.068 u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6_n_0
|
|
SLICE_X7Y58 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_11/I1
|
|
SLICE_X7Y58 LUT5 (Prop_lut5_I1_O) 0.124 0.056 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_11/O
|
|
net (fo=2, routed) 0.619 0.675 u_axi_ram/u_axi_sram_sp/state_d2[7]
|
|
SLICE_X6Y59 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_15/I5
|
|
SLICE_X6Y59 LUT6 (Prop_lut6_I5_O) 0.124 0.799 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_15/O
|
|
net (fo=1, routed) 0.000 0.799 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_15_n_0
|
|
SLICE_X6Y59 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9/S[3]
|
|
SLICE_X6Y59 CARRY4 (Prop_carry4_S[3]_CO[3])
|
|
0.376 1.175 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9/CO[3]
|
|
net (fo=1, routed) 0.000 1.175 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9_n_0
|
|
SLICE_X6Y60 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/CI
|
|
SLICE_X6Y60 CARRY4 (Prop_carry4_CI_CO[3])
|
|
0.117 1.292 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/CO[3]
|
|
net (fo=1, routed) 0.000 1.292 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10_n_0
|
|
SLICE_X6Y61 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CI
|
|
SLICE_X6Y61 CARRY4 (Prop_carry4_CI_CO[3])
|
|
0.117 1.409 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CO[3]
|
|
net (fo=1, routed) 0.000 1.409 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9_n_0
|
|
SLICE_X6Y62 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/CI
|
|
SLICE_X6Y62 CARRY4 (Prop_carry4_CI_O[2])
|
|
0.239 1.648 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/O[2]
|
|
net (fo=3, routed) 0.929 2.576 u_axi_ram/u_axi_sram_sp/upper_wrap_boundary[20]
|
|
SLICE_X5Y65 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_7/I2
|
|
SLICE_X5Y65 LUT4 (Prop_lut4_I2_O) 0.301 2.877 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_7/O
|
|
net (fo=1, routed) 0.000 2.877 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_7_n_0
|
|
SLICE_X5Y65 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1/S[1]
|
|
SLICE_X5Y65 CARRY4 (Prop_carry4_S[1]_CO[3])
|
|
0.550 3.427 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1/CO[3]
|
|
net (fo=1, routed) 0.000 3.427 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_n_0
|
|
SLICE_X5Y66 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2/CI
|
|
SLICE_X5Y66 CARRY4 (Prop_carry4_CI_CO[2])
|
|
0.228 3.655 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2/CO[2]
|
|
net (fo=22, routed) 0.735 4.390 u_axi_ram/u_axi_sram_sp/req_addr_d1
|
|
SLICE_X5Y68 r u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/I0
|
|
SLICE_X5Y68 LUT6 (Prop_lut6_I0_O) 0.313 4.703 r u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/O
|
|
net (fo=2, routed) 0.550 5.253 u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7_n_0
|
|
SLICE_X4Y68 r u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/I1
|
|
SLICE_X4Y68 LUT6 (Prop_lut6_I1_O) 0.124 5.377 r u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/O
|
|
net (fo=80, routed) 0.770 6.147 u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/soc_sram_addr[0]
|
|
SLICE_X1Y63 r u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/ext_ram_data_IOBUF[31]_inst_i_2/I2
|
|
SLICE_X1Y63 LUT3 (Prop_lut3_I2_O) 0.124 6.271 f u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/ext_ram_data_IOBUF[31]_inst_i_2/O
|
|
net (fo=32, routed) 3.256 9.527 ext_ram_data_IOBUF[21]_inst/T
|
|
AC16 f ext_ram_data_IOBUF[21]_inst/OBUFT/T
|
|
AC16 OBUFT (TriStatE_obuft_T_O)
|
|
3.546 13.073 r ext_ram_data_IOBUF[21]_inst/OBUFT/O
|
|
net (fo=1, unset) 0.000 13.073 ext_ram_data[21]
|
|
AC16 r ext_ram_data[21] (INOUT)
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock sys_clk rise edge) 20.000 20.000 r
|
|
clock source latency -5.674 14.326
|
|
propagated clock network latency
|
|
0.000 14.326
|
|
clock pessimism -0.601 13.725
|
|
clock uncertainty -0.071 13.654
|
|
output delay -0.300 13.354
|
|
-------------------------------------------------------------------
|
|
required time 13.354
|
|
arrival time -13.073
|
|
-------------------------------------------------------------------
|
|
slack 0.281
|
|
|
|
Slack (MET) : 0.281ns (required time - arrival time)
|
|
Source: u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[3]/C
|
|
(rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Destination: ext_ram_data[21]
|
|
(output port clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Path Group: sys_clk
|
|
Path Type: Max at Slow Process Corner
|
|
Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns)
|
|
Data Path Delay: 15.394ns (logic 6.863ns (44.584%) route 8.531ns (55.416%))
|
|
Logic Levels: 14 (CARRY4=6 LUT3=1 LUT4=2 LUT5=1 LUT6=3 OBUFT=1)
|
|
Output Delay: 0.300ns
|
|
Clock Path Skew: -3.955ns (DCD - SCD + CPR)
|
|
Destination Clock Delay (DCD): -5.674ns = ( 14.326 - 20.000 )
|
|
Source Clock Delay (SCD): -2.321ns
|
|
Clock Pessimism Removal (CPR): -0.601ns
|
|
Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Discrete Jitter (DJ): 0.122ns
|
|
Phase Error (PE): 0.000ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock sys_clk rise edge) 0.000 0.000 r
|
|
clock source latency -6.275 -6.275
|
|
propagated clock network latency
|
|
3.955 -2.321
|
|
SLICE_X7Y62 FDCE 0.000 -2.321 r u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[3]/C
|
|
SLICE_X7Y62 FDCE (Prop_fdce_C_Q) 0.456 -1.865 f u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[3]/Q
|
|
net (fo=54, routed) 0.726 -1.139 u_axi_ram/u_axi_sram_sp/len[3]
|
|
SLICE_X7Y61 f u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6/I3
|
|
SLICE_X7Y61 LUT4 (Prop_lut4_I3_O) 0.124 -1.015 r u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6/O
|
|
net (fo=4, routed) 0.946 -0.068 u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6_n_0
|
|
SLICE_X7Y58 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_11/I1
|
|
SLICE_X7Y58 LUT5 (Prop_lut5_I1_O) 0.124 0.056 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_11/O
|
|
net (fo=2, routed) 0.619 0.675 u_axi_ram/u_axi_sram_sp/state_d2[7]
|
|
SLICE_X6Y59 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_15/I5
|
|
SLICE_X6Y59 LUT6 (Prop_lut6_I5_O) 0.124 0.799 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_15/O
|
|
net (fo=1, routed) 0.000 0.799 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_15_n_0
|
|
SLICE_X6Y59 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9/S[3]
|
|
SLICE_X6Y59 CARRY4 (Prop_carry4_S[3]_CO[3])
|
|
0.376 1.175 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9/CO[3]
|
|
net (fo=1, routed) 0.000 1.175 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9_n_0
|
|
SLICE_X6Y60 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/CI
|
|
SLICE_X6Y60 CARRY4 (Prop_carry4_CI_CO[3])
|
|
0.117 1.292 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/CO[3]
|
|
net (fo=1, routed) 0.000 1.292 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10_n_0
|
|
SLICE_X6Y61 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CI
|
|
SLICE_X6Y61 CARRY4 (Prop_carry4_CI_CO[3])
|
|
0.117 1.409 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CO[3]
|
|
net (fo=1, routed) 0.000 1.409 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9_n_0
|
|
SLICE_X6Y62 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/CI
|
|
SLICE_X6Y62 CARRY4 (Prop_carry4_CI_O[2])
|
|
0.239 1.648 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/O[2]
|
|
net (fo=3, routed) 0.929 2.576 u_axi_ram/u_axi_sram_sp/upper_wrap_boundary[20]
|
|
SLICE_X5Y65 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_7/I2
|
|
SLICE_X5Y65 LUT4 (Prop_lut4_I2_O) 0.301 2.877 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_7/O
|
|
net (fo=1, routed) 0.000 2.877 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_7_n_0
|
|
SLICE_X5Y65 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1/S[1]
|
|
SLICE_X5Y65 CARRY4 (Prop_carry4_S[1]_CO[3])
|
|
0.550 3.427 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1/CO[3]
|
|
net (fo=1, routed) 0.000 3.427 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_n_0
|
|
SLICE_X5Y66 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2/CI
|
|
SLICE_X5Y66 CARRY4 (Prop_carry4_CI_CO[2])
|
|
0.228 3.655 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2/CO[2]
|
|
net (fo=22, routed) 0.735 4.390 u_axi_ram/u_axi_sram_sp/req_addr_d1
|
|
SLICE_X5Y68 r u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/I0
|
|
SLICE_X5Y68 LUT6 (Prop_lut6_I0_O) 0.313 4.703 r u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/O
|
|
net (fo=2, routed) 0.550 5.253 u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7_n_0
|
|
SLICE_X4Y68 r u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/I1
|
|
SLICE_X4Y68 LUT6 (Prop_lut6_I1_O) 0.124 5.377 r u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/O
|
|
net (fo=80, routed) 0.770 6.147 u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/soc_sram_addr[0]
|
|
SLICE_X1Y63 r u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/ext_ram_data_IOBUF[31]_inst_i_2/I2
|
|
SLICE_X1Y63 LUT3 (Prop_lut3_I2_O) 0.124 6.271 f u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/ext_ram_data_IOBUF[31]_inst_i_2/O
|
|
net (fo=32, routed) 3.256 9.527 ext_ram_data_IOBUF[21]_inst/T
|
|
AC16 f ext_ram_data_IOBUF[21]_inst/OBUFT/T
|
|
AC16 OBUFT (TriStatE_obuft_T_O)
|
|
3.546 13.073 r ext_ram_data_IOBUF[21]_inst/OBUFT/O
|
|
net (fo=1, unset) 0.000 13.073 ext_ram_data[21]
|
|
AC16 r ext_ram_data[21] (INOUT)
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock sys_clk rise edge) 20.000 20.000 r
|
|
clock source latency -5.674 14.326
|
|
propagated clock network latency
|
|
0.000 14.326
|
|
clock pessimism -0.601 13.725
|
|
clock uncertainty -0.071 13.654
|
|
output delay -0.300 13.354
|
|
-------------------------------------------------------------------
|
|
required time 13.354
|
|
arrival time -13.073
|
|
-------------------------------------------------------------------
|
|
slack 0.281
|
|
|
|
Slack (MET) : 0.281ns (required time - arrival time)
|
|
Source: u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[3]/C
|
|
(rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Destination: ext_ram_data[21]
|
|
(output port clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Path Group: sys_clk
|
|
Path Type: Max at Slow Process Corner
|
|
Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns)
|
|
Data Path Delay: 15.394ns (logic 6.863ns (44.584%) route 8.531ns (55.416%))
|
|
Logic Levels: 14 (CARRY4=6 LUT3=1 LUT4=2 LUT5=1 LUT6=3 OBUFT=1)
|
|
Output Delay: 0.300ns
|
|
Clock Path Skew: -3.955ns (DCD - SCD + CPR)
|
|
Destination Clock Delay (DCD): -5.674ns = ( 14.326 - 20.000 )
|
|
Source Clock Delay (SCD): -2.321ns
|
|
Clock Pessimism Removal (CPR): -0.601ns
|
|
Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Discrete Jitter (DJ): 0.122ns
|
|
Phase Error (PE): 0.000ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock sys_clk rise edge) 0.000 0.000 r
|
|
clock source latency -6.275 -6.275
|
|
propagated clock network latency
|
|
3.955 -2.321
|
|
SLICE_X7Y62 FDCE 0.000 -2.321 r u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[3]/C
|
|
SLICE_X7Y62 FDCE (Prop_fdce_C_Q) 0.456 -1.865 f u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[3]/Q
|
|
net (fo=54, routed) 0.726 -1.139 u_axi_ram/u_axi_sram_sp/len[3]
|
|
SLICE_X7Y61 f u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6/I3
|
|
SLICE_X7Y61 LUT4 (Prop_lut4_I3_O) 0.124 -1.015 r u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6/O
|
|
net (fo=4, routed) 0.946 -0.068 u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6_n_0
|
|
SLICE_X7Y58 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_11/I1
|
|
SLICE_X7Y58 LUT5 (Prop_lut5_I1_O) 0.124 0.056 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_11/O
|
|
net (fo=2, routed) 0.619 0.675 u_axi_ram/u_axi_sram_sp/state_d2[7]
|
|
SLICE_X6Y59 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_15/I5
|
|
SLICE_X6Y59 LUT6 (Prop_lut6_I5_O) 0.124 0.799 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_15/O
|
|
net (fo=1, routed) 0.000 0.799 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_15_n_0
|
|
SLICE_X6Y59 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9/S[3]
|
|
SLICE_X6Y59 CARRY4 (Prop_carry4_S[3]_CO[3])
|
|
0.376 1.175 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9/CO[3]
|
|
net (fo=1, routed) 0.000 1.175 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9_n_0
|
|
SLICE_X6Y60 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/CI
|
|
SLICE_X6Y60 CARRY4 (Prop_carry4_CI_CO[3])
|
|
0.117 1.292 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/CO[3]
|
|
net (fo=1, routed) 0.000 1.292 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10_n_0
|
|
SLICE_X6Y61 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CI
|
|
SLICE_X6Y61 CARRY4 (Prop_carry4_CI_CO[3])
|
|
0.117 1.409 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CO[3]
|
|
net (fo=1, routed) 0.000 1.409 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9_n_0
|
|
SLICE_X6Y62 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/CI
|
|
SLICE_X6Y62 CARRY4 (Prop_carry4_CI_O[2])
|
|
0.239 1.648 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/O[2]
|
|
net (fo=3, routed) 0.929 2.576 u_axi_ram/u_axi_sram_sp/upper_wrap_boundary[20]
|
|
SLICE_X5Y65 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_7/I2
|
|
SLICE_X5Y65 LUT4 (Prop_lut4_I2_O) 0.301 2.877 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_7/O
|
|
net (fo=1, routed) 0.000 2.877 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_7_n_0
|
|
SLICE_X5Y65 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1/S[1]
|
|
SLICE_X5Y65 CARRY4 (Prop_carry4_S[1]_CO[3])
|
|
0.550 3.427 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1/CO[3]
|
|
net (fo=1, routed) 0.000 3.427 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_n_0
|
|
SLICE_X5Y66 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2/CI
|
|
SLICE_X5Y66 CARRY4 (Prop_carry4_CI_CO[2])
|
|
0.228 3.655 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2/CO[2]
|
|
net (fo=22, routed) 0.735 4.390 u_axi_ram/u_axi_sram_sp/req_addr_d1
|
|
SLICE_X5Y68 r u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/I0
|
|
SLICE_X5Y68 LUT6 (Prop_lut6_I0_O) 0.313 4.703 r u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/O
|
|
net (fo=2, routed) 0.550 5.253 u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7_n_0
|
|
SLICE_X4Y68 r u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/I1
|
|
SLICE_X4Y68 LUT6 (Prop_lut6_I1_O) 0.124 5.377 r u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/O
|
|
net (fo=80, routed) 0.770 6.147 u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/soc_sram_addr[0]
|
|
SLICE_X1Y63 r u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/ext_ram_data_IOBUF[31]_inst_i_2/I2
|
|
SLICE_X1Y63 LUT3 (Prop_lut3_I2_O) 0.124 6.271 f u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/ext_ram_data_IOBUF[31]_inst_i_2/O
|
|
net (fo=32, routed) 3.256 9.527 ext_ram_data_IOBUF[21]_inst/T
|
|
AC16 f ext_ram_data_IOBUF[21]_inst/OBUFT/T
|
|
AC16 OBUFT (TriStatE_obuft_T_O)
|
|
3.546 13.073 r ext_ram_data_IOBUF[21]_inst/OBUFT/O
|
|
net (fo=1, unset) 0.000 13.073 ext_ram_data[21]
|
|
AC16 r ext_ram_data[21] (INOUT)
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock sys_clk rise edge) 20.000 20.000 r
|
|
clock source latency -5.674 14.326
|
|
propagated clock network latency
|
|
0.000 14.326
|
|
clock pessimism -0.601 13.725
|
|
clock uncertainty -0.071 13.654
|
|
output delay -0.300 13.354
|
|
-------------------------------------------------------------------
|
|
required time 13.354
|
|
arrival time -13.073
|
|
-------------------------------------------------------------------
|
|
slack 0.281
|
|
|
|
Slack (MET) : 0.281ns (required time - arrival time)
|
|
Source: u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[3]/C
|
|
(rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Destination: ext_ram_data[21]
|
|
(output port clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Path Group: sys_clk
|
|
Path Type: Max at Slow Process Corner
|
|
Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns)
|
|
Data Path Delay: 15.394ns (logic 6.863ns (44.584%) route 8.531ns (55.416%))
|
|
Logic Levels: 14 (CARRY4=6 LUT3=1 LUT4=2 LUT5=1 LUT6=3 OBUFT=1)
|
|
Output Delay: 0.300ns
|
|
Clock Path Skew: -3.955ns (DCD - SCD + CPR)
|
|
Destination Clock Delay (DCD): -5.674ns = ( 14.326 - 20.000 )
|
|
Source Clock Delay (SCD): -2.321ns
|
|
Clock Pessimism Removal (CPR): -0.601ns
|
|
Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Discrete Jitter (DJ): 0.122ns
|
|
Phase Error (PE): 0.000ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock sys_clk rise edge) 0.000 0.000 r
|
|
clock source latency -6.275 -6.275
|
|
propagated clock network latency
|
|
3.955 -2.321
|
|
SLICE_X7Y62 FDCE 0.000 -2.321 r u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[3]/C
|
|
SLICE_X7Y62 FDCE (Prop_fdce_C_Q) 0.456 -1.865 f u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[3]/Q
|
|
net (fo=54, routed) 0.726 -1.139 u_axi_ram/u_axi_sram_sp/len[3]
|
|
SLICE_X7Y61 f u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6/I3
|
|
SLICE_X7Y61 LUT4 (Prop_lut4_I3_O) 0.124 -1.015 r u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6/O
|
|
net (fo=4, routed) 0.946 -0.068 u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6_n_0
|
|
SLICE_X7Y58 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_11/I1
|
|
SLICE_X7Y58 LUT5 (Prop_lut5_I1_O) 0.124 0.056 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_11/O
|
|
net (fo=2, routed) 0.619 0.675 u_axi_ram/u_axi_sram_sp/state_d2[7]
|
|
SLICE_X6Y59 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_15/I5
|
|
SLICE_X6Y59 LUT6 (Prop_lut6_I5_O) 0.124 0.799 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_15/O
|
|
net (fo=1, routed) 0.000 0.799 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_15_n_0
|
|
SLICE_X6Y59 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9/S[3]
|
|
SLICE_X6Y59 CARRY4 (Prop_carry4_S[3]_CO[3])
|
|
0.376 1.175 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9/CO[3]
|
|
net (fo=1, routed) 0.000 1.175 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9_n_0
|
|
SLICE_X6Y60 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/CI
|
|
SLICE_X6Y60 CARRY4 (Prop_carry4_CI_CO[3])
|
|
0.117 1.292 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/CO[3]
|
|
net (fo=1, routed) 0.000 1.292 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10_n_0
|
|
SLICE_X6Y61 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CI
|
|
SLICE_X6Y61 CARRY4 (Prop_carry4_CI_CO[3])
|
|
0.117 1.409 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CO[3]
|
|
net (fo=1, routed) 0.000 1.409 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9_n_0
|
|
SLICE_X6Y62 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/CI
|
|
SLICE_X6Y62 CARRY4 (Prop_carry4_CI_O[2])
|
|
0.239 1.648 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/O[2]
|
|
net (fo=3, routed) 0.929 2.576 u_axi_ram/u_axi_sram_sp/upper_wrap_boundary[20]
|
|
SLICE_X5Y65 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_7/I2
|
|
SLICE_X5Y65 LUT4 (Prop_lut4_I2_O) 0.301 2.877 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_7/O
|
|
net (fo=1, routed) 0.000 2.877 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_7_n_0
|
|
SLICE_X5Y65 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1/S[1]
|
|
SLICE_X5Y65 CARRY4 (Prop_carry4_S[1]_CO[3])
|
|
0.550 3.427 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1/CO[3]
|
|
net (fo=1, routed) 0.000 3.427 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_n_0
|
|
SLICE_X5Y66 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2/CI
|
|
SLICE_X5Y66 CARRY4 (Prop_carry4_CI_CO[2])
|
|
0.228 3.655 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2/CO[2]
|
|
net (fo=22, routed) 0.735 4.390 u_axi_ram/u_axi_sram_sp/req_addr_d1
|
|
SLICE_X5Y68 r u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/I0
|
|
SLICE_X5Y68 LUT6 (Prop_lut6_I0_O) 0.313 4.703 r u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/O
|
|
net (fo=2, routed) 0.550 5.253 u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7_n_0
|
|
SLICE_X4Y68 r u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/I1
|
|
SLICE_X4Y68 LUT6 (Prop_lut6_I1_O) 0.124 5.377 r u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/O
|
|
net (fo=80, routed) 0.770 6.147 u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/soc_sram_addr[0]
|
|
SLICE_X1Y63 r u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/ext_ram_data_IOBUF[31]_inst_i_2/I2
|
|
SLICE_X1Y63 LUT3 (Prop_lut3_I2_O) 0.124 6.271 f u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/ext_ram_data_IOBUF[31]_inst_i_2/O
|
|
net (fo=32, routed) 3.256 9.527 ext_ram_data_IOBUF[21]_inst/T
|
|
AC16 f ext_ram_data_IOBUF[21]_inst/OBUFT/T
|
|
AC16 OBUFT (TriStatE_obuft_T_O)
|
|
3.546 13.073 r ext_ram_data_IOBUF[21]_inst/OBUFT/O
|
|
net (fo=1, unset) 0.000 13.073 ext_ram_data[21]
|
|
AC16 r ext_ram_data[21] (INOUT)
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock sys_clk rise edge) 20.000 20.000 r
|
|
clock source latency -5.674 14.326
|
|
propagated clock network latency
|
|
0.000 14.326
|
|
clock pessimism -0.601 13.725
|
|
clock uncertainty -0.071 13.654
|
|
output delay -0.300 13.354
|
|
-------------------------------------------------------------------
|
|
required time 13.354
|
|
arrival time -13.073
|
|
-------------------------------------------------------------------
|
|
slack 0.281
|
|
|
|
Slack (MET) : 0.281ns (required time - arrival time)
|
|
Source: u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[3]/C
|
|
(rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Destination: ext_ram_data[21]
|
|
(output port clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Path Group: sys_clk
|
|
Path Type: Max at Slow Process Corner
|
|
Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns)
|
|
Data Path Delay: 15.394ns (logic 6.863ns (44.584%) route 8.531ns (55.416%))
|
|
Logic Levels: 14 (CARRY4=6 LUT3=1 LUT4=2 LUT5=1 LUT6=3 OBUFT=1)
|
|
Output Delay: 0.300ns
|
|
Clock Path Skew: -3.955ns (DCD - SCD + CPR)
|
|
Destination Clock Delay (DCD): -5.674ns = ( 14.326 - 20.000 )
|
|
Source Clock Delay (SCD): -2.321ns
|
|
Clock Pessimism Removal (CPR): -0.601ns
|
|
Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Discrete Jitter (DJ): 0.122ns
|
|
Phase Error (PE): 0.000ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock sys_clk rise edge) 0.000 0.000 r
|
|
clock source latency -6.275 -6.275
|
|
propagated clock network latency
|
|
3.955 -2.321
|
|
SLICE_X7Y62 FDCE 0.000 -2.321 r u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[3]/C
|
|
SLICE_X7Y62 FDCE (Prop_fdce_C_Q) 0.456 -1.865 f u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[3]/Q
|
|
net (fo=54, routed) 0.726 -1.139 u_axi_ram/u_axi_sram_sp/len[3]
|
|
SLICE_X7Y61 f u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6/I3
|
|
SLICE_X7Y61 LUT4 (Prop_lut4_I3_O) 0.124 -1.015 r u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6/O
|
|
net (fo=4, routed) 0.946 -0.068 u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6_n_0
|
|
SLICE_X7Y58 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_11/I1
|
|
SLICE_X7Y58 LUT5 (Prop_lut5_I1_O) 0.124 0.056 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_11/O
|
|
net (fo=2, routed) 0.619 0.675 u_axi_ram/u_axi_sram_sp/state_d2[7]
|
|
SLICE_X6Y59 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_15/I5
|
|
SLICE_X6Y59 LUT6 (Prop_lut6_I5_O) 0.124 0.799 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_15/O
|
|
net (fo=1, routed) 0.000 0.799 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_15_n_0
|
|
SLICE_X6Y59 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9/S[3]
|
|
SLICE_X6Y59 CARRY4 (Prop_carry4_S[3]_CO[3])
|
|
0.376 1.175 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9/CO[3]
|
|
net (fo=1, routed) 0.000 1.175 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9_n_0
|
|
SLICE_X6Y60 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/CI
|
|
SLICE_X6Y60 CARRY4 (Prop_carry4_CI_CO[3])
|
|
0.117 1.292 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/CO[3]
|
|
net (fo=1, routed) 0.000 1.292 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10_n_0
|
|
SLICE_X6Y61 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CI
|
|
SLICE_X6Y61 CARRY4 (Prop_carry4_CI_CO[3])
|
|
0.117 1.409 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CO[3]
|
|
net (fo=1, routed) 0.000 1.409 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9_n_0
|
|
SLICE_X6Y62 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/CI
|
|
SLICE_X6Y62 CARRY4 (Prop_carry4_CI_O[2])
|
|
0.239 1.648 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/O[2]
|
|
net (fo=3, routed) 0.929 2.576 u_axi_ram/u_axi_sram_sp/upper_wrap_boundary[20]
|
|
SLICE_X5Y65 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_7/I2
|
|
SLICE_X5Y65 LUT4 (Prop_lut4_I2_O) 0.301 2.877 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_7/O
|
|
net (fo=1, routed) 0.000 2.877 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_7_n_0
|
|
SLICE_X5Y65 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1/S[1]
|
|
SLICE_X5Y65 CARRY4 (Prop_carry4_S[1]_CO[3])
|
|
0.550 3.427 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1/CO[3]
|
|
net (fo=1, routed) 0.000 3.427 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_n_0
|
|
SLICE_X5Y66 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2/CI
|
|
SLICE_X5Y66 CARRY4 (Prop_carry4_CI_CO[2])
|
|
0.228 3.655 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2/CO[2]
|
|
net (fo=22, routed) 0.735 4.390 u_axi_ram/u_axi_sram_sp/req_addr_d1
|
|
SLICE_X5Y68 r u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/I0
|
|
SLICE_X5Y68 LUT6 (Prop_lut6_I0_O) 0.313 4.703 r u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/O
|
|
net (fo=2, routed) 0.550 5.253 u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7_n_0
|
|
SLICE_X4Y68 r u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/I1
|
|
SLICE_X4Y68 LUT6 (Prop_lut6_I1_O) 0.124 5.377 r u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/O
|
|
net (fo=80, routed) 0.770 6.147 u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/soc_sram_addr[0]
|
|
SLICE_X1Y63 r u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/ext_ram_data_IOBUF[31]_inst_i_2/I2
|
|
SLICE_X1Y63 LUT3 (Prop_lut3_I2_O) 0.124 6.271 f u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/ext_ram_data_IOBUF[31]_inst_i_2/O
|
|
net (fo=32, routed) 3.256 9.527 ext_ram_data_IOBUF[21]_inst/T
|
|
AC16 f ext_ram_data_IOBUF[21]_inst/OBUFT/T
|
|
AC16 OBUFT (TriStatE_obuft_T_O)
|
|
3.546 13.073 r ext_ram_data_IOBUF[21]_inst/OBUFT/O
|
|
net (fo=1, unset) 0.000 13.073 ext_ram_data[21]
|
|
AC16 r ext_ram_data[21] (INOUT)
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock sys_clk rise edge) 20.000 20.000 r
|
|
clock source latency -5.674 14.326
|
|
propagated clock network latency
|
|
0.000 14.326
|
|
clock pessimism -0.601 13.725
|
|
clock uncertainty -0.071 13.654
|
|
output delay -0.300 13.354
|
|
-------------------------------------------------------------------
|
|
required time 13.354
|
|
arrival time -13.073
|
|
-------------------------------------------------------------------
|
|
slack 0.281
|
|
|
|
Slack (MET) : 0.281ns (required time - arrival time)
|
|
Source: u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[3]/C
|
|
(rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Destination: ext_ram_data[21]
|
|
(output port clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Path Group: sys_clk
|
|
Path Type: Max at Slow Process Corner
|
|
Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns)
|
|
Data Path Delay: 15.394ns (logic 6.863ns (44.584%) route 8.531ns (55.416%))
|
|
Logic Levels: 14 (CARRY4=6 LUT3=1 LUT4=2 LUT5=1 LUT6=3 OBUFT=1)
|
|
Output Delay: 0.300ns
|
|
Clock Path Skew: -3.955ns (DCD - SCD + CPR)
|
|
Destination Clock Delay (DCD): -5.674ns = ( 14.326 - 20.000 )
|
|
Source Clock Delay (SCD): -2.321ns
|
|
Clock Pessimism Removal (CPR): -0.601ns
|
|
Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Discrete Jitter (DJ): 0.122ns
|
|
Phase Error (PE): 0.000ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock sys_clk rise edge) 0.000 0.000 r
|
|
clock source latency -6.275 -6.275
|
|
propagated clock network latency
|
|
3.955 -2.321
|
|
SLICE_X7Y62 FDCE 0.000 -2.321 r u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[3]/C
|
|
SLICE_X7Y62 FDCE (Prop_fdce_C_Q) 0.456 -1.865 f u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[3]/Q
|
|
net (fo=54, routed) 0.726 -1.139 u_axi_ram/u_axi_sram_sp/len[3]
|
|
SLICE_X7Y61 f u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6/I3
|
|
SLICE_X7Y61 LUT4 (Prop_lut4_I3_O) 0.124 -1.015 r u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6/O
|
|
net (fo=4, routed) 0.946 -0.068 u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6_n_0
|
|
SLICE_X7Y58 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_11/I1
|
|
SLICE_X7Y58 LUT5 (Prop_lut5_I1_O) 0.124 0.056 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_11/O
|
|
net (fo=2, routed) 0.619 0.675 u_axi_ram/u_axi_sram_sp/state_d2[7]
|
|
SLICE_X6Y59 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_15/I5
|
|
SLICE_X6Y59 LUT6 (Prop_lut6_I5_O) 0.124 0.799 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_15/O
|
|
net (fo=1, routed) 0.000 0.799 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_15_n_0
|
|
SLICE_X6Y59 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9/S[3]
|
|
SLICE_X6Y59 CARRY4 (Prop_carry4_S[3]_CO[3])
|
|
0.376 1.175 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9/CO[3]
|
|
net (fo=1, routed) 0.000 1.175 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9_n_0
|
|
SLICE_X6Y60 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/CI
|
|
SLICE_X6Y60 CARRY4 (Prop_carry4_CI_CO[3])
|
|
0.117 1.292 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/CO[3]
|
|
net (fo=1, routed) 0.000 1.292 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10_n_0
|
|
SLICE_X6Y61 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CI
|
|
SLICE_X6Y61 CARRY4 (Prop_carry4_CI_CO[3])
|
|
0.117 1.409 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CO[3]
|
|
net (fo=1, routed) 0.000 1.409 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9_n_0
|
|
SLICE_X6Y62 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/CI
|
|
SLICE_X6Y62 CARRY4 (Prop_carry4_CI_O[2])
|
|
0.239 1.648 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/O[2]
|
|
net (fo=3, routed) 0.929 2.576 u_axi_ram/u_axi_sram_sp/upper_wrap_boundary[20]
|
|
SLICE_X5Y65 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_7/I2
|
|
SLICE_X5Y65 LUT4 (Prop_lut4_I2_O) 0.301 2.877 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_7/O
|
|
net (fo=1, routed) 0.000 2.877 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_7_n_0
|
|
SLICE_X5Y65 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1/S[1]
|
|
SLICE_X5Y65 CARRY4 (Prop_carry4_S[1]_CO[3])
|
|
0.550 3.427 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1/CO[3]
|
|
net (fo=1, routed) 0.000 3.427 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_n_0
|
|
SLICE_X5Y66 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2/CI
|
|
SLICE_X5Y66 CARRY4 (Prop_carry4_CI_CO[2])
|
|
0.228 3.655 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2/CO[2]
|
|
net (fo=22, routed) 0.735 4.390 u_axi_ram/u_axi_sram_sp/req_addr_d1
|
|
SLICE_X5Y68 r u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/I0
|
|
SLICE_X5Y68 LUT6 (Prop_lut6_I0_O) 0.313 4.703 r u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/O
|
|
net (fo=2, routed) 0.550 5.253 u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7_n_0
|
|
SLICE_X4Y68 r u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/I1
|
|
SLICE_X4Y68 LUT6 (Prop_lut6_I1_O) 0.124 5.377 r u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/O
|
|
net (fo=80, routed) 0.770 6.147 u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/soc_sram_addr[0]
|
|
SLICE_X1Y63 r u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/ext_ram_data_IOBUF[31]_inst_i_2/I2
|
|
SLICE_X1Y63 LUT3 (Prop_lut3_I2_O) 0.124 6.271 f u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/ext_ram_data_IOBUF[31]_inst_i_2/O
|
|
net (fo=32, routed) 3.256 9.527 ext_ram_data_IOBUF[21]_inst/T
|
|
AC16 f ext_ram_data_IOBUF[21]_inst/OBUFT/T
|
|
AC16 OBUFT (TriStatE_obuft_T_O)
|
|
3.546 13.073 r ext_ram_data_IOBUF[21]_inst/OBUFT/O
|
|
net (fo=1, unset) 0.000 13.073 ext_ram_data[21]
|
|
AC16 r ext_ram_data[21] (INOUT)
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock sys_clk rise edge) 20.000 20.000 r
|
|
clock source latency -5.674 14.326
|
|
propagated clock network latency
|
|
0.000 14.326
|
|
clock pessimism -0.601 13.725
|
|
clock uncertainty -0.071 13.654
|
|
output delay -0.300 13.354
|
|
-------------------------------------------------------------------
|
|
required time 13.354
|
|
arrival time -13.073
|
|
-------------------------------------------------------------------
|
|
slack 0.281
|
|
|
|
Slack (MET) : 0.281ns (required time - arrival time)
|
|
Source: u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[3]/C
|
|
(rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Destination: ext_ram_data[21]
|
|
(output port clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Path Group: sys_clk
|
|
Path Type: Max at Slow Process Corner
|
|
Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns)
|
|
Data Path Delay: 15.394ns (logic 6.863ns (44.584%) route 8.531ns (55.416%))
|
|
Logic Levels: 14 (CARRY4=6 LUT3=1 LUT4=2 LUT5=1 LUT6=3 OBUFT=1)
|
|
Output Delay: 0.300ns
|
|
Clock Path Skew: -3.955ns (DCD - SCD + CPR)
|
|
Destination Clock Delay (DCD): -5.674ns = ( 14.326 - 20.000 )
|
|
Source Clock Delay (SCD): -2.321ns
|
|
Clock Pessimism Removal (CPR): -0.601ns
|
|
Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Discrete Jitter (DJ): 0.122ns
|
|
Phase Error (PE): 0.000ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock sys_clk rise edge) 0.000 0.000 r
|
|
clock source latency -6.275 -6.275
|
|
propagated clock network latency
|
|
3.955 -2.321
|
|
SLICE_X7Y62 FDCE 0.000 -2.321 r u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[3]/C
|
|
SLICE_X7Y62 FDCE (Prop_fdce_C_Q) 0.456 -1.865 f u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[3]/Q
|
|
net (fo=54, routed) 0.726 -1.139 u_axi_ram/u_axi_sram_sp/len[3]
|
|
SLICE_X7Y61 f u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6/I3
|
|
SLICE_X7Y61 LUT4 (Prop_lut4_I3_O) 0.124 -1.015 r u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6/O
|
|
net (fo=4, routed) 0.946 -0.068 u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6_n_0
|
|
SLICE_X7Y58 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_11/I1
|
|
SLICE_X7Y58 LUT5 (Prop_lut5_I1_O) 0.124 0.056 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_11/O
|
|
net (fo=2, routed) 0.619 0.675 u_axi_ram/u_axi_sram_sp/state_d2[7]
|
|
SLICE_X6Y59 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_15/I5
|
|
SLICE_X6Y59 LUT6 (Prop_lut6_I5_O) 0.124 0.799 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_15/O
|
|
net (fo=1, routed) 0.000 0.799 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_15_n_0
|
|
SLICE_X6Y59 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9/S[3]
|
|
SLICE_X6Y59 CARRY4 (Prop_carry4_S[3]_CO[3])
|
|
0.376 1.175 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9/CO[3]
|
|
net (fo=1, routed) 0.000 1.175 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9_n_0
|
|
SLICE_X6Y60 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/CI
|
|
SLICE_X6Y60 CARRY4 (Prop_carry4_CI_CO[3])
|
|
0.117 1.292 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/CO[3]
|
|
net (fo=1, routed) 0.000 1.292 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10_n_0
|
|
SLICE_X6Y61 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CI
|
|
SLICE_X6Y61 CARRY4 (Prop_carry4_CI_CO[3])
|
|
0.117 1.409 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CO[3]
|
|
net (fo=1, routed) 0.000 1.409 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9_n_0
|
|
SLICE_X6Y62 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/CI
|
|
SLICE_X6Y62 CARRY4 (Prop_carry4_CI_O[2])
|
|
0.239 1.648 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/O[2]
|
|
net (fo=3, routed) 0.929 2.576 u_axi_ram/u_axi_sram_sp/upper_wrap_boundary[20]
|
|
SLICE_X5Y65 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_7/I2
|
|
SLICE_X5Y65 LUT4 (Prop_lut4_I2_O) 0.301 2.877 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_7/O
|
|
net (fo=1, routed) 0.000 2.877 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_7_n_0
|
|
SLICE_X5Y65 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1/S[1]
|
|
SLICE_X5Y65 CARRY4 (Prop_carry4_S[1]_CO[3])
|
|
0.550 3.427 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1/CO[3]
|
|
net (fo=1, routed) 0.000 3.427 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_n_0
|
|
SLICE_X5Y66 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2/CI
|
|
SLICE_X5Y66 CARRY4 (Prop_carry4_CI_CO[2])
|
|
0.228 3.655 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2/CO[2]
|
|
net (fo=22, routed) 0.735 4.390 u_axi_ram/u_axi_sram_sp/req_addr_d1
|
|
SLICE_X5Y68 r u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/I0
|
|
SLICE_X5Y68 LUT6 (Prop_lut6_I0_O) 0.313 4.703 r u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/O
|
|
net (fo=2, routed) 0.550 5.253 u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7_n_0
|
|
SLICE_X4Y68 r u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/I1
|
|
SLICE_X4Y68 LUT6 (Prop_lut6_I1_O) 0.124 5.377 r u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/O
|
|
net (fo=80, routed) 0.770 6.147 u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/soc_sram_addr[0]
|
|
SLICE_X1Y63 r u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/ext_ram_data_IOBUF[31]_inst_i_2/I2
|
|
SLICE_X1Y63 LUT3 (Prop_lut3_I2_O) 0.124 6.271 f u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/ext_ram_data_IOBUF[31]_inst_i_2/O
|
|
net (fo=32, routed) 3.256 9.527 ext_ram_data_IOBUF[21]_inst/T
|
|
AC16 f ext_ram_data_IOBUF[21]_inst/OBUFT/T
|
|
AC16 OBUFT (TriStatE_obuft_T_O)
|
|
3.546 13.073 r ext_ram_data_IOBUF[21]_inst/OBUFT/O
|
|
net (fo=1, unset) 0.000 13.073 ext_ram_data[21]
|
|
AC16 r ext_ram_data[21] (INOUT)
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock sys_clk rise edge) 20.000 20.000 r
|
|
clock source latency -5.674 14.326
|
|
propagated clock network latency
|
|
0.000 14.326
|
|
clock pessimism -0.601 13.725
|
|
clock uncertainty -0.071 13.654
|
|
output delay -0.300 13.354
|
|
-------------------------------------------------------------------
|
|
required time 13.354
|
|
arrival time -13.073
|
|
-------------------------------------------------------------------
|
|
slack 0.281
|
|
|
|
Slack (MET) : 0.281ns (required time - arrival time)
|
|
Source: u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[3]/C
|
|
(rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Destination: ext_ram_data[21]
|
|
(output port clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Path Group: sys_clk
|
|
Path Type: Max at Slow Process Corner
|
|
Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns)
|
|
Data Path Delay: 15.394ns (logic 6.863ns (44.584%) route 8.531ns (55.416%))
|
|
Logic Levels: 14 (CARRY4=6 LUT3=1 LUT4=2 LUT5=1 LUT6=3 OBUFT=1)
|
|
Output Delay: 0.300ns
|
|
Clock Path Skew: -3.955ns (DCD - SCD + CPR)
|
|
Destination Clock Delay (DCD): -5.674ns = ( 14.326 - 20.000 )
|
|
Source Clock Delay (SCD): -2.321ns
|
|
Clock Pessimism Removal (CPR): -0.601ns
|
|
Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Discrete Jitter (DJ): 0.122ns
|
|
Phase Error (PE): 0.000ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock sys_clk rise edge) 0.000 0.000 r
|
|
clock source latency -6.275 -6.275
|
|
propagated clock network latency
|
|
3.955 -2.321
|
|
SLICE_X7Y62 FDCE 0.000 -2.321 r u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[3]/C
|
|
SLICE_X7Y62 FDCE (Prop_fdce_C_Q) 0.456 -1.865 f u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[3]/Q
|
|
net (fo=54, routed) 0.726 -1.139 u_axi_ram/u_axi_sram_sp/len[3]
|
|
SLICE_X7Y61 f u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6/I3
|
|
SLICE_X7Y61 LUT4 (Prop_lut4_I3_O) 0.124 -1.015 r u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6/O
|
|
net (fo=4, routed) 0.946 -0.068 u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6_n_0
|
|
SLICE_X7Y58 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_11/I1
|
|
SLICE_X7Y58 LUT5 (Prop_lut5_I1_O) 0.124 0.056 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_11/O
|
|
net (fo=2, routed) 0.619 0.675 u_axi_ram/u_axi_sram_sp/state_d2[7]
|
|
SLICE_X6Y59 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_15/I5
|
|
SLICE_X6Y59 LUT6 (Prop_lut6_I5_O) 0.124 0.799 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_15/O
|
|
net (fo=1, routed) 0.000 0.799 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_15_n_0
|
|
SLICE_X6Y59 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9/S[3]
|
|
SLICE_X6Y59 CARRY4 (Prop_carry4_S[3]_CO[3])
|
|
0.376 1.175 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9/CO[3]
|
|
net (fo=1, routed) 0.000 1.175 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9_n_0
|
|
SLICE_X6Y60 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/CI
|
|
SLICE_X6Y60 CARRY4 (Prop_carry4_CI_CO[3])
|
|
0.117 1.292 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/CO[3]
|
|
net (fo=1, routed) 0.000 1.292 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10_n_0
|
|
SLICE_X6Y61 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CI
|
|
SLICE_X6Y61 CARRY4 (Prop_carry4_CI_CO[3])
|
|
0.117 1.409 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CO[3]
|
|
net (fo=1, routed) 0.000 1.409 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9_n_0
|
|
SLICE_X6Y62 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/CI
|
|
SLICE_X6Y62 CARRY4 (Prop_carry4_CI_O[2])
|
|
0.239 1.648 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/O[2]
|
|
net (fo=3, routed) 0.929 2.576 u_axi_ram/u_axi_sram_sp/upper_wrap_boundary[20]
|
|
SLICE_X5Y65 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_7/I2
|
|
SLICE_X5Y65 LUT4 (Prop_lut4_I2_O) 0.301 2.877 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_7/O
|
|
net (fo=1, routed) 0.000 2.877 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_7_n_0
|
|
SLICE_X5Y65 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1/S[1]
|
|
SLICE_X5Y65 CARRY4 (Prop_carry4_S[1]_CO[3])
|
|
0.550 3.427 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1/CO[3]
|
|
net (fo=1, routed) 0.000 3.427 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_n_0
|
|
SLICE_X5Y66 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2/CI
|
|
SLICE_X5Y66 CARRY4 (Prop_carry4_CI_CO[2])
|
|
0.228 3.655 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2/CO[2]
|
|
net (fo=22, routed) 0.735 4.390 u_axi_ram/u_axi_sram_sp/req_addr_d1
|
|
SLICE_X5Y68 r u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/I0
|
|
SLICE_X5Y68 LUT6 (Prop_lut6_I0_O) 0.313 4.703 r u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/O
|
|
net (fo=2, routed) 0.550 5.253 u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7_n_0
|
|
SLICE_X4Y68 r u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/I1
|
|
SLICE_X4Y68 LUT6 (Prop_lut6_I1_O) 0.124 5.377 r u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/O
|
|
net (fo=80, routed) 0.770 6.147 u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/soc_sram_addr[0]
|
|
SLICE_X1Y63 r u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/ext_ram_data_IOBUF[31]_inst_i_2/I2
|
|
SLICE_X1Y63 LUT3 (Prop_lut3_I2_O) 0.124 6.271 f u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/ext_ram_data_IOBUF[31]_inst_i_2/O
|
|
net (fo=32, routed) 3.256 9.527 ext_ram_data_IOBUF[21]_inst/T
|
|
AC16 f ext_ram_data_IOBUF[21]_inst/OBUFT/T
|
|
AC16 OBUFT (TriStatE_obuft_T_O)
|
|
3.546 13.073 r ext_ram_data_IOBUF[21]_inst/OBUFT/O
|
|
net (fo=1, unset) 0.000 13.073 ext_ram_data[21]
|
|
AC16 r ext_ram_data[21] (INOUT)
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock sys_clk rise edge) 20.000 20.000 r
|
|
clock source latency -5.674 14.326
|
|
propagated clock network latency
|
|
0.000 14.326
|
|
clock pessimism -0.601 13.725
|
|
clock uncertainty -0.071 13.654
|
|
output delay -0.300 13.354
|
|
-------------------------------------------------------------------
|
|
required time 13.354
|
|
arrival time -13.073
|
|
-------------------------------------------------------------------
|
|
slack 0.281
|
|
|
|
Slack (MET) : 0.281ns (required time - arrival time)
|
|
Source: u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[3]/C
|
|
(rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Destination: ext_ram_data[21]
|
|
(output port clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Path Group: sys_clk
|
|
Path Type: Max at Slow Process Corner
|
|
Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns)
|
|
Data Path Delay: 15.394ns (logic 6.863ns (44.584%) route 8.531ns (55.416%))
|
|
Logic Levels: 14 (CARRY4=6 LUT3=1 LUT4=2 LUT5=1 LUT6=3 OBUFT=1)
|
|
Output Delay: 0.300ns
|
|
Clock Path Skew: -3.955ns (DCD - SCD + CPR)
|
|
Destination Clock Delay (DCD): -5.674ns = ( 14.326 - 20.000 )
|
|
Source Clock Delay (SCD): -2.321ns
|
|
Clock Pessimism Removal (CPR): -0.601ns
|
|
Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Discrete Jitter (DJ): 0.122ns
|
|
Phase Error (PE): 0.000ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock sys_clk rise edge) 0.000 0.000 r
|
|
clock source latency -6.275 -6.275
|
|
propagated clock network latency
|
|
3.955 -2.321
|
|
SLICE_X7Y62 FDCE 0.000 -2.321 r u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[3]/C
|
|
SLICE_X7Y62 FDCE (Prop_fdce_C_Q) 0.456 -1.865 f u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[3]/Q
|
|
net (fo=54, routed) 0.726 -1.139 u_axi_ram/u_axi_sram_sp/len[3]
|
|
SLICE_X7Y61 f u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6/I3
|
|
SLICE_X7Y61 LUT4 (Prop_lut4_I3_O) 0.124 -1.015 r u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6/O
|
|
net (fo=4, routed) 0.946 -0.068 u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6_n_0
|
|
SLICE_X7Y58 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_11/I1
|
|
SLICE_X7Y58 LUT5 (Prop_lut5_I1_O) 0.124 0.056 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_11/O
|
|
net (fo=2, routed) 0.619 0.675 u_axi_ram/u_axi_sram_sp/state_d2[7]
|
|
SLICE_X6Y59 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_15/I5
|
|
SLICE_X6Y59 LUT6 (Prop_lut6_I5_O) 0.124 0.799 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_15/O
|
|
net (fo=1, routed) 0.000 0.799 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_15_n_0
|
|
SLICE_X6Y59 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9/S[3]
|
|
SLICE_X6Y59 CARRY4 (Prop_carry4_S[3]_CO[3])
|
|
0.376 1.175 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9/CO[3]
|
|
net (fo=1, routed) 0.000 1.175 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9_n_0
|
|
SLICE_X6Y60 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/CI
|
|
SLICE_X6Y60 CARRY4 (Prop_carry4_CI_CO[3])
|
|
0.117 1.292 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/CO[3]
|
|
net (fo=1, routed) 0.000 1.292 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10_n_0
|
|
SLICE_X6Y61 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CI
|
|
SLICE_X6Y61 CARRY4 (Prop_carry4_CI_CO[3])
|
|
0.117 1.409 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CO[3]
|
|
net (fo=1, routed) 0.000 1.409 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9_n_0
|
|
SLICE_X6Y62 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/CI
|
|
SLICE_X6Y62 CARRY4 (Prop_carry4_CI_O[2])
|
|
0.239 1.648 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/O[2]
|
|
net (fo=3, routed) 0.929 2.576 u_axi_ram/u_axi_sram_sp/upper_wrap_boundary[20]
|
|
SLICE_X5Y65 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_7/I2
|
|
SLICE_X5Y65 LUT4 (Prop_lut4_I2_O) 0.301 2.877 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_7/O
|
|
net (fo=1, routed) 0.000 2.877 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_7_n_0
|
|
SLICE_X5Y65 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1/S[1]
|
|
SLICE_X5Y65 CARRY4 (Prop_carry4_S[1]_CO[3])
|
|
0.550 3.427 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1/CO[3]
|
|
net (fo=1, routed) 0.000 3.427 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_n_0
|
|
SLICE_X5Y66 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2/CI
|
|
SLICE_X5Y66 CARRY4 (Prop_carry4_CI_CO[2])
|
|
0.228 3.655 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2/CO[2]
|
|
net (fo=22, routed) 0.735 4.390 u_axi_ram/u_axi_sram_sp/req_addr_d1
|
|
SLICE_X5Y68 r u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/I0
|
|
SLICE_X5Y68 LUT6 (Prop_lut6_I0_O) 0.313 4.703 r u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/O
|
|
net (fo=2, routed) 0.550 5.253 u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7_n_0
|
|
SLICE_X4Y68 r u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/I1
|
|
SLICE_X4Y68 LUT6 (Prop_lut6_I1_O) 0.124 5.377 r u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/O
|
|
net (fo=80, routed) 0.770 6.147 u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/soc_sram_addr[0]
|
|
SLICE_X1Y63 r u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/ext_ram_data_IOBUF[31]_inst_i_2/I2
|
|
SLICE_X1Y63 LUT3 (Prop_lut3_I2_O) 0.124 6.271 f u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/ext_ram_data_IOBUF[31]_inst_i_2/O
|
|
net (fo=32, routed) 3.256 9.527 ext_ram_data_IOBUF[21]_inst/T
|
|
AC16 f ext_ram_data_IOBUF[21]_inst/OBUFT/T
|
|
AC16 OBUFT (TriStatE_obuft_T_O)
|
|
3.546 13.073 r ext_ram_data_IOBUF[21]_inst/OBUFT/O
|
|
net (fo=1, unset) 0.000 13.073 ext_ram_data[21]
|
|
AC16 r ext_ram_data[21] (INOUT)
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock sys_clk rise edge) 20.000 20.000 r
|
|
clock source latency -5.674 14.326
|
|
propagated clock network latency
|
|
0.000 14.326
|
|
clock pessimism -0.601 13.725
|
|
clock uncertainty -0.071 13.654
|
|
output delay -0.300 13.354
|
|
-------------------------------------------------------------------
|
|
required time 13.354
|
|
arrival time -13.073
|
|
-------------------------------------------------------------------
|
|
slack 0.281
|
|
|
|
Slack (MET) : 0.281ns (required time - arrival time)
|
|
Source: u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[3]/C
|
|
(rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Destination: ext_ram_data[21]
|
|
(output port clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Path Group: sys_clk
|
|
Path Type: Max at Slow Process Corner
|
|
Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns)
|
|
Data Path Delay: 15.394ns (logic 6.863ns (44.584%) route 8.531ns (55.416%))
|
|
Logic Levels: 14 (CARRY4=6 LUT3=1 LUT4=2 LUT5=1 LUT6=3 OBUFT=1)
|
|
Output Delay: 0.300ns
|
|
Clock Path Skew: -3.955ns (DCD - SCD + CPR)
|
|
Destination Clock Delay (DCD): -5.674ns = ( 14.326 - 20.000 )
|
|
Source Clock Delay (SCD): -2.321ns
|
|
Clock Pessimism Removal (CPR): -0.601ns
|
|
Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Discrete Jitter (DJ): 0.122ns
|
|
Phase Error (PE): 0.000ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock sys_clk rise edge) 0.000 0.000 r
|
|
clock source latency -6.275 -6.275
|
|
propagated clock network latency
|
|
3.955 -2.321
|
|
SLICE_X7Y62 FDCE 0.000 -2.321 r u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[3]/C
|
|
SLICE_X7Y62 FDCE (Prop_fdce_C_Q) 0.456 -1.865 f u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[3]/Q
|
|
net (fo=54, routed) 0.726 -1.139 u_axi_ram/u_axi_sram_sp/len[3]
|
|
SLICE_X7Y61 f u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6/I3
|
|
SLICE_X7Y61 LUT4 (Prop_lut4_I3_O) 0.124 -1.015 r u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6/O
|
|
net (fo=4, routed) 0.946 -0.068 u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6_n_0
|
|
SLICE_X7Y58 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_11/I1
|
|
SLICE_X7Y58 LUT5 (Prop_lut5_I1_O) 0.124 0.056 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_11/O
|
|
net (fo=2, routed) 0.619 0.675 u_axi_ram/u_axi_sram_sp/state_d2[7]
|
|
SLICE_X6Y59 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_15/I5
|
|
SLICE_X6Y59 LUT6 (Prop_lut6_I5_O) 0.124 0.799 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_15/O
|
|
net (fo=1, routed) 0.000 0.799 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_15_n_0
|
|
SLICE_X6Y59 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9/S[3]
|
|
SLICE_X6Y59 CARRY4 (Prop_carry4_S[3]_CO[3])
|
|
0.376 1.175 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9/CO[3]
|
|
net (fo=1, routed) 0.000 1.175 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9_n_0
|
|
SLICE_X6Y60 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/CI
|
|
SLICE_X6Y60 CARRY4 (Prop_carry4_CI_CO[3])
|
|
0.117 1.292 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/CO[3]
|
|
net (fo=1, routed) 0.000 1.292 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10_n_0
|
|
SLICE_X6Y61 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CI
|
|
SLICE_X6Y61 CARRY4 (Prop_carry4_CI_CO[3])
|
|
0.117 1.409 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CO[3]
|
|
net (fo=1, routed) 0.000 1.409 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9_n_0
|
|
SLICE_X6Y62 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/CI
|
|
SLICE_X6Y62 CARRY4 (Prop_carry4_CI_O[2])
|
|
0.239 1.648 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/O[2]
|
|
net (fo=3, routed) 0.929 2.576 u_axi_ram/u_axi_sram_sp/upper_wrap_boundary[20]
|
|
SLICE_X5Y65 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_7/I2
|
|
SLICE_X5Y65 LUT4 (Prop_lut4_I2_O) 0.301 2.877 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_7/O
|
|
net (fo=1, routed) 0.000 2.877 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_7_n_0
|
|
SLICE_X5Y65 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1/S[1]
|
|
SLICE_X5Y65 CARRY4 (Prop_carry4_S[1]_CO[3])
|
|
0.550 3.427 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1/CO[3]
|
|
net (fo=1, routed) 0.000 3.427 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_n_0
|
|
SLICE_X5Y66 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2/CI
|
|
SLICE_X5Y66 CARRY4 (Prop_carry4_CI_CO[2])
|
|
0.228 3.655 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2/CO[2]
|
|
net (fo=22, routed) 0.735 4.390 u_axi_ram/u_axi_sram_sp/req_addr_d1
|
|
SLICE_X5Y68 r u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/I0
|
|
SLICE_X5Y68 LUT6 (Prop_lut6_I0_O) 0.313 4.703 r u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/O
|
|
net (fo=2, routed) 0.550 5.253 u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7_n_0
|
|
SLICE_X4Y68 r u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/I1
|
|
SLICE_X4Y68 LUT6 (Prop_lut6_I1_O) 0.124 5.377 r u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/O
|
|
net (fo=80, routed) 0.770 6.147 u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/soc_sram_addr[0]
|
|
SLICE_X1Y63 r u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/ext_ram_data_IOBUF[31]_inst_i_2/I2
|
|
SLICE_X1Y63 LUT3 (Prop_lut3_I2_O) 0.124 6.271 f u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/ext_ram_data_IOBUF[31]_inst_i_2/O
|
|
net (fo=32, routed) 3.256 9.527 ext_ram_data_IOBUF[21]_inst/T
|
|
AC16 f ext_ram_data_IOBUF[21]_inst/OBUFT/T
|
|
AC16 OBUFT (TriStatE_obuft_T_O)
|
|
3.546 13.073 r ext_ram_data_IOBUF[21]_inst/OBUFT/O
|
|
net (fo=1, unset) 0.000 13.073 ext_ram_data[21]
|
|
AC16 r ext_ram_data[21] (INOUT)
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock sys_clk rise edge) 20.000 20.000 r
|
|
clock source latency -5.674 14.326
|
|
propagated clock network latency
|
|
0.000 14.326
|
|
clock pessimism -0.601 13.725
|
|
clock uncertainty -0.071 13.654
|
|
output delay -0.300 13.354
|
|
-------------------------------------------------------------------
|
|
required time 13.354
|
|
arrival time -13.073
|
|
-------------------------------------------------------------------
|
|
slack 0.281
|
|
|
|
Slack (MET) : 0.287ns (required time - arrival time)
|
|
Source: u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[3]/C
|
|
(rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Destination: base_ram_data[30]
|
|
(output port clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Path Group: sys_clk
|
|
Path Type: Max at Slow Process Corner
|
|
Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns)
|
|
Data Path Delay: 15.388ns (logic 6.876ns (44.688%) route 8.511ns (55.312%))
|
|
Logic Levels: 14 (CARRY4=6 LUT3=1 LUT4=2 LUT5=1 LUT6=3 OBUFT=1)
|
|
Output Delay: 0.300ns
|
|
Clock Path Skew: -3.955ns (DCD - SCD + CPR)
|
|
Destination Clock Delay (DCD): -5.674ns = ( 14.326 - 20.000 )
|
|
Source Clock Delay (SCD): -2.321ns
|
|
Clock Pessimism Removal (CPR): -0.601ns
|
|
Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Discrete Jitter (DJ): 0.122ns
|
|
Phase Error (PE): 0.000ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock sys_clk rise edge) 0.000 0.000 r
|
|
clock source latency -6.275 -6.275
|
|
propagated clock network latency
|
|
3.955 -2.321
|
|
SLICE_X7Y62 FDCE 0.000 -2.321 r u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[3]/C
|
|
SLICE_X7Y62 FDCE (Prop_fdce_C_Q) 0.456 -1.865 f u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[3]/Q
|
|
net (fo=54, routed) 0.726 -1.139 u_axi_ram/u_axi_sram_sp/len[3]
|
|
SLICE_X7Y61 f u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6/I3
|
|
SLICE_X7Y61 LUT4 (Prop_lut4_I3_O) 0.124 -1.015 r u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6/O
|
|
net (fo=4, routed) 0.946 -0.068 u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6_n_0
|
|
SLICE_X7Y58 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_11/I1
|
|
SLICE_X7Y58 LUT5 (Prop_lut5_I1_O) 0.124 0.056 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_11/O
|
|
net (fo=2, routed) 0.619 0.675 u_axi_ram/u_axi_sram_sp/state_d2[7]
|
|
SLICE_X6Y59 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_15/I5
|
|
SLICE_X6Y59 LUT6 (Prop_lut6_I5_O) 0.124 0.799 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_15/O
|
|
net (fo=1, routed) 0.000 0.799 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_15_n_0
|
|
SLICE_X6Y59 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9/S[3]
|
|
SLICE_X6Y59 CARRY4 (Prop_carry4_S[3]_CO[3])
|
|
0.376 1.175 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9/CO[3]
|
|
net (fo=1, routed) 0.000 1.175 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9_n_0
|
|
SLICE_X6Y60 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/CI
|
|
SLICE_X6Y60 CARRY4 (Prop_carry4_CI_CO[3])
|
|
0.117 1.292 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/CO[3]
|
|
net (fo=1, routed) 0.000 1.292 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10_n_0
|
|
SLICE_X6Y61 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CI
|
|
SLICE_X6Y61 CARRY4 (Prop_carry4_CI_CO[3])
|
|
0.117 1.409 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CO[3]
|
|
net (fo=1, routed) 0.000 1.409 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9_n_0
|
|
SLICE_X6Y62 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/CI
|
|
SLICE_X6Y62 CARRY4 (Prop_carry4_CI_O[2])
|
|
0.239 1.648 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/O[2]
|
|
net (fo=3, routed) 0.929 2.576 u_axi_ram/u_axi_sram_sp/upper_wrap_boundary[20]
|
|
SLICE_X5Y65 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_7/I2
|
|
SLICE_X5Y65 LUT4 (Prop_lut4_I2_O) 0.301 2.877 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_7/O
|
|
net (fo=1, routed) 0.000 2.877 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_7_n_0
|
|
SLICE_X5Y65 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1/S[1]
|
|
SLICE_X5Y65 CARRY4 (Prop_carry4_S[1]_CO[3])
|
|
0.550 3.427 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1/CO[3]
|
|
net (fo=1, routed) 0.000 3.427 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_n_0
|
|
SLICE_X5Y66 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2/CI
|
|
SLICE_X5Y66 CARRY4 (Prop_carry4_CI_CO[2])
|
|
0.228 3.655 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2/CO[2]
|
|
net (fo=22, routed) 0.735 4.390 u_axi_ram/u_axi_sram_sp/req_addr_d1
|
|
SLICE_X5Y68 r u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/I0
|
|
SLICE_X5Y68 LUT6 (Prop_lut6_I0_O) 0.313 4.703 f u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/O
|
|
net (fo=2, routed) 0.550 5.253 u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7_n_0
|
|
SLICE_X4Y68 f u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/I1
|
|
SLICE_X4Y68 LUT6 (Prop_lut6_I1_O) 0.124 5.377 f u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/O
|
|
net (fo=80, routed) 0.877 6.254 u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/soc_sram_addr[0]
|
|
SLICE_X1Y74 f u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/base_ram_data_IOBUF[31]_inst_i_3/I2
|
|
SLICE_X1Y74 LUT3 (Prop_lut3_I2_O) 0.124 6.378 f u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/base_ram_data_IOBUF[31]_inst_i_3/O
|
|
net (fo=32, routed) 3.130 9.508 base_ram_data_IOBUF[30]_inst/T
|
|
M24 f base_ram_data_IOBUF[30]_inst/OBUFT/T
|
|
M24 OBUFT (TriStatE_obuft_T_O)
|
|
3.559 13.067 r base_ram_data_IOBUF[30]_inst/OBUFT/O
|
|
net (fo=1, unset) 0.000 13.067 base_ram_data[30]
|
|
M24 r base_ram_data[30] (INOUT)
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock sys_clk rise edge) 20.000 20.000 r
|
|
clock source latency -5.674 14.326
|
|
propagated clock network latency
|
|
0.000 14.326
|
|
clock pessimism -0.601 13.725
|
|
clock uncertainty -0.071 13.654
|
|
output delay -0.300 13.354
|
|
-------------------------------------------------------------------
|
|
required time 13.354
|
|
arrival time -13.067
|
|
-------------------------------------------------------------------
|
|
slack 0.287
|
|
|
|
Slack (MET) : 0.287ns (required time - arrival time)
|
|
Source: u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[3]/C
|
|
(rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Destination: base_ram_data[30]
|
|
(output port clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Path Group: sys_clk
|
|
Path Type: Max at Slow Process Corner
|
|
Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns)
|
|
Data Path Delay: 15.388ns (logic 6.876ns (44.688%) route 8.511ns (55.312%))
|
|
Logic Levels: 14 (CARRY4=6 LUT3=1 LUT4=2 LUT5=1 LUT6=3 OBUFT=1)
|
|
Output Delay: 0.300ns
|
|
Clock Path Skew: -3.955ns (DCD - SCD + CPR)
|
|
Destination Clock Delay (DCD): -5.674ns = ( 14.326 - 20.000 )
|
|
Source Clock Delay (SCD): -2.321ns
|
|
Clock Pessimism Removal (CPR): -0.601ns
|
|
Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Discrete Jitter (DJ): 0.122ns
|
|
Phase Error (PE): 0.000ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock sys_clk rise edge) 0.000 0.000 r
|
|
clock source latency -6.275 -6.275
|
|
propagated clock network latency
|
|
3.955 -2.321
|
|
SLICE_X7Y62 FDCE 0.000 -2.321 r u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[3]/C
|
|
SLICE_X7Y62 FDCE (Prop_fdce_C_Q) 0.456 -1.865 f u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[3]/Q
|
|
net (fo=54, routed) 0.726 -1.139 u_axi_ram/u_axi_sram_sp/len[3]
|
|
SLICE_X7Y61 f u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6/I3
|
|
SLICE_X7Y61 LUT4 (Prop_lut4_I3_O) 0.124 -1.015 r u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6/O
|
|
net (fo=4, routed) 0.946 -0.068 u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6_n_0
|
|
SLICE_X7Y58 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_11/I1
|
|
SLICE_X7Y58 LUT5 (Prop_lut5_I1_O) 0.124 0.056 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_11/O
|
|
net (fo=2, routed) 0.619 0.675 u_axi_ram/u_axi_sram_sp/state_d2[7]
|
|
SLICE_X6Y59 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_15/I5
|
|
SLICE_X6Y59 LUT6 (Prop_lut6_I5_O) 0.124 0.799 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_15/O
|
|
net (fo=1, routed) 0.000 0.799 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_15_n_0
|
|
SLICE_X6Y59 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9/S[3]
|
|
SLICE_X6Y59 CARRY4 (Prop_carry4_S[3]_CO[3])
|
|
0.376 1.175 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9/CO[3]
|
|
net (fo=1, routed) 0.000 1.175 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9_n_0
|
|
SLICE_X6Y60 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/CI
|
|
SLICE_X6Y60 CARRY4 (Prop_carry4_CI_CO[3])
|
|
0.117 1.292 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/CO[3]
|
|
net (fo=1, routed) 0.000 1.292 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10_n_0
|
|
SLICE_X6Y61 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CI
|
|
SLICE_X6Y61 CARRY4 (Prop_carry4_CI_CO[3])
|
|
0.117 1.409 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CO[3]
|
|
net (fo=1, routed) 0.000 1.409 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9_n_0
|
|
SLICE_X6Y62 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/CI
|
|
SLICE_X6Y62 CARRY4 (Prop_carry4_CI_O[2])
|
|
0.239 1.648 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/O[2]
|
|
net (fo=3, routed) 0.929 2.576 u_axi_ram/u_axi_sram_sp/upper_wrap_boundary[20]
|
|
SLICE_X5Y65 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_7/I2
|
|
SLICE_X5Y65 LUT4 (Prop_lut4_I2_O) 0.301 2.877 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_7/O
|
|
net (fo=1, routed) 0.000 2.877 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_7_n_0
|
|
SLICE_X5Y65 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1/S[1]
|
|
SLICE_X5Y65 CARRY4 (Prop_carry4_S[1]_CO[3])
|
|
0.550 3.427 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1/CO[3]
|
|
net (fo=1, routed) 0.000 3.427 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_n_0
|
|
SLICE_X5Y66 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2/CI
|
|
SLICE_X5Y66 CARRY4 (Prop_carry4_CI_CO[2])
|
|
0.228 3.655 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2/CO[2]
|
|
net (fo=22, routed) 0.735 4.390 u_axi_ram/u_axi_sram_sp/req_addr_d1
|
|
SLICE_X5Y68 r u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/I0
|
|
SLICE_X5Y68 LUT6 (Prop_lut6_I0_O) 0.313 4.703 f u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/O
|
|
net (fo=2, routed) 0.550 5.253 u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7_n_0
|
|
SLICE_X4Y68 f u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/I1
|
|
SLICE_X4Y68 LUT6 (Prop_lut6_I1_O) 0.124 5.377 f u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/O
|
|
net (fo=80, routed) 0.877 6.254 u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/soc_sram_addr[0]
|
|
SLICE_X1Y74 f u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/base_ram_data_IOBUF[31]_inst_i_3/I2
|
|
SLICE_X1Y74 LUT3 (Prop_lut3_I2_O) 0.124 6.378 f u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/base_ram_data_IOBUF[31]_inst_i_3/O
|
|
net (fo=32, routed) 3.130 9.508 base_ram_data_IOBUF[30]_inst/T
|
|
M24 f base_ram_data_IOBUF[30]_inst/OBUFT/T
|
|
M24 OBUFT (TriStatE_obuft_T_O)
|
|
3.559 13.067 r base_ram_data_IOBUF[30]_inst/OBUFT/O
|
|
net (fo=1, unset) 0.000 13.067 base_ram_data[30]
|
|
M24 r base_ram_data[30] (INOUT)
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock sys_clk rise edge) 20.000 20.000 r
|
|
clock source latency -5.674 14.326
|
|
propagated clock network latency
|
|
0.000 14.326
|
|
clock pessimism -0.601 13.725
|
|
clock uncertainty -0.071 13.654
|
|
output delay -0.300 13.354
|
|
-------------------------------------------------------------------
|
|
required time 13.354
|
|
arrival time -13.067
|
|
-------------------------------------------------------------------
|
|
slack 0.287
|
|
|
|
Slack (MET) : 0.287ns (required time - arrival time)
|
|
Source: u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[3]/C
|
|
(rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Destination: base_ram_data[30]
|
|
(output port clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Path Group: sys_clk
|
|
Path Type: Max at Slow Process Corner
|
|
Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns)
|
|
Data Path Delay: 15.388ns (logic 6.876ns (44.688%) route 8.511ns (55.312%))
|
|
Logic Levels: 14 (CARRY4=6 LUT3=1 LUT4=2 LUT5=1 LUT6=3 OBUFT=1)
|
|
Output Delay: 0.300ns
|
|
Clock Path Skew: -3.955ns (DCD - SCD + CPR)
|
|
Destination Clock Delay (DCD): -5.674ns = ( 14.326 - 20.000 )
|
|
Source Clock Delay (SCD): -2.321ns
|
|
Clock Pessimism Removal (CPR): -0.601ns
|
|
Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Discrete Jitter (DJ): 0.122ns
|
|
Phase Error (PE): 0.000ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock sys_clk rise edge) 0.000 0.000 r
|
|
clock source latency -6.275 -6.275
|
|
propagated clock network latency
|
|
3.955 -2.321
|
|
SLICE_X7Y62 FDCE 0.000 -2.321 r u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[3]/C
|
|
SLICE_X7Y62 FDCE (Prop_fdce_C_Q) 0.456 -1.865 f u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[3]/Q
|
|
net (fo=54, routed) 0.726 -1.139 u_axi_ram/u_axi_sram_sp/len[3]
|
|
SLICE_X7Y61 f u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6/I3
|
|
SLICE_X7Y61 LUT4 (Prop_lut4_I3_O) 0.124 -1.015 r u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6/O
|
|
net (fo=4, routed) 0.946 -0.068 u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6_n_0
|
|
SLICE_X7Y58 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_11/I1
|
|
SLICE_X7Y58 LUT5 (Prop_lut5_I1_O) 0.124 0.056 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_11/O
|
|
net (fo=2, routed) 0.619 0.675 u_axi_ram/u_axi_sram_sp/state_d2[7]
|
|
SLICE_X6Y59 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_15/I5
|
|
SLICE_X6Y59 LUT6 (Prop_lut6_I5_O) 0.124 0.799 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_15/O
|
|
net (fo=1, routed) 0.000 0.799 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_15_n_0
|
|
SLICE_X6Y59 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9/S[3]
|
|
SLICE_X6Y59 CARRY4 (Prop_carry4_S[3]_CO[3])
|
|
0.376 1.175 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9/CO[3]
|
|
net (fo=1, routed) 0.000 1.175 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9_n_0
|
|
SLICE_X6Y60 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/CI
|
|
SLICE_X6Y60 CARRY4 (Prop_carry4_CI_CO[3])
|
|
0.117 1.292 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/CO[3]
|
|
net (fo=1, routed) 0.000 1.292 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10_n_0
|
|
SLICE_X6Y61 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CI
|
|
SLICE_X6Y61 CARRY4 (Prop_carry4_CI_CO[3])
|
|
0.117 1.409 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CO[3]
|
|
net (fo=1, routed) 0.000 1.409 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9_n_0
|
|
SLICE_X6Y62 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/CI
|
|
SLICE_X6Y62 CARRY4 (Prop_carry4_CI_O[2])
|
|
0.239 1.648 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/O[2]
|
|
net (fo=3, routed) 0.929 2.576 u_axi_ram/u_axi_sram_sp/upper_wrap_boundary[20]
|
|
SLICE_X5Y65 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_7/I2
|
|
SLICE_X5Y65 LUT4 (Prop_lut4_I2_O) 0.301 2.877 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_7/O
|
|
net (fo=1, routed) 0.000 2.877 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_7_n_0
|
|
SLICE_X5Y65 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1/S[1]
|
|
SLICE_X5Y65 CARRY4 (Prop_carry4_S[1]_CO[3])
|
|
0.550 3.427 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1/CO[3]
|
|
net (fo=1, routed) 0.000 3.427 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_n_0
|
|
SLICE_X5Y66 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2/CI
|
|
SLICE_X5Y66 CARRY4 (Prop_carry4_CI_CO[2])
|
|
0.228 3.655 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2/CO[2]
|
|
net (fo=22, routed) 0.735 4.390 u_axi_ram/u_axi_sram_sp/req_addr_d1
|
|
SLICE_X5Y68 r u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/I0
|
|
SLICE_X5Y68 LUT6 (Prop_lut6_I0_O) 0.313 4.703 f u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/O
|
|
net (fo=2, routed) 0.550 5.253 u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7_n_0
|
|
SLICE_X4Y68 f u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/I1
|
|
SLICE_X4Y68 LUT6 (Prop_lut6_I1_O) 0.124 5.377 f u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/O
|
|
net (fo=80, routed) 0.877 6.254 u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/soc_sram_addr[0]
|
|
SLICE_X1Y74 f u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/base_ram_data_IOBUF[31]_inst_i_3/I2
|
|
SLICE_X1Y74 LUT3 (Prop_lut3_I2_O) 0.124 6.378 f u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/base_ram_data_IOBUF[31]_inst_i_3/O
|
|
net (fo=32, routed) 3.130 9.508 base_ram_data_IOBUF[30]_inst/T
|
|
M24 f base_ram_data_IOBUF[30]_inst/OBUFT/T
|
|
M24 OBUFT (TriStatE_obuft_T_O)
|
|
3.559 13.067 r base_ram_data_IOBUF[30]_inst/OBUFT/O
|
|
net (fo=1, unset) 0.000 13.067 base_ram_data[30]
|
|
M24 r base_ram_data[30] (INOUT)
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock sys_clk rise edge) 20.000 20.000 r
|
|
clock source latency -5.674 14.326
|
|
propagated clock network latency
|
|
0.000 14.326
|
|
clock pessimism -0.601 13.725
|
|
clock uncertainty -0.071 13.654
|
|
output delay -0.300 13.354
|
|
-------------------------------------------------------------------
|
|
required time 13.354
|
|
arrival time -13.067
|
|
-------------------------------------------------------------------
|
|
slack 0.287
|
|
|
|
Slack (MET) : 0.287ns (required time - arrival time)
|
|
Source: u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[3]/C
|
|
(rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Destination: base_ram_data[30]
|
|
(output port clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Path Group: sys_clk
|
|
Path Type: Max at Slow Process Corner
|
|
Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns)
|
|
Data Path Delay: 15.388ns (logic 6.876ns (44.688%) route 8.511ns (55.312%))
|
|
Logic Levels: 14 (CARRY4=6 LUT3=1 LUT4=2 LUT5=1 LUT6=3 OBUFT=1)
|
|
Output Delay: 0.300ns
|
|
Clock Path Skew: -3.955ns (DCD - SCD + CPR)
|
|
Destination Clock Delay (DCD): -5.674ns = ( 14.326 - 20.000 )
|
|
Source Clock Delay (SCD): -2.321ns
|
|
Clock Pessimism Removal (CPR): -0.601ns
|
|
Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Discrete Jitter (DJ): 0.122ns
|
|
Phase Error (PE): 0.000ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock sys_clk rise edge) 0.000 0.000 r
|
|
clock source latency -6.275 -6.275
|
|
propagated clock network latency
|
|
3.955 -2.321
|
|
SLICE_X7Y62 FDCE 0.000 -2.321 r u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[3]/C
|
|
SLICE_X7Y62 FDCE (Prop_fdce_C_Q) 0.456 -1.865 f u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[3]/Q
|
|
net (fo=54, routed) 0.726 -1.139 u_axi_ram/u_axi_sram_sp/len[3]
|
|
SLICE_X7Y61 f u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6/I3
|
|
SLICE_X7Y61 LUT4 (Prop_lut4_I3_O) 0.124 -1.015 r u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6/O
|
|
net (fo=4, routed) 0.946 -0.068 u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6_n_0
|
|
SLICE_X7Y58 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_11/I1
|
|
SLICE_X7Y58 LUT5 (Prop_lut5_I1_O) 0.124 0.056 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_11/O
|
|
net (fo=2, routed) 0.619 0.675 u_axi_ram/u_axi_sram_sp/state_d2[7]
|
|
SLICE_X6Y59 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_15/I5
|
|
SLICE_X6Y59 LUT6 (Prop_lut6_I5_O) 0.124 0.799 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_15/O
|
|
net (fo=1, routed) 0.000 0.799 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_15_n_0
|
|
SLICE_X6Y59 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9/S[3]
|
|
SLICE_X6Y59 CARRY4 (Prop_carry4_S[3]_CO[3])
|
|
0.376 1.175 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9/CO[3]
|
|
net (fo=1, routed) 0.000 1.175 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9_n_0
|
|
SLICE_X6Y60 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/CI
|
|
SLICE_X6Y60 CARRY4 (Prop_carry4_CI_CO[3])
|
|
0.117 1.292 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/CO[3]
|
|
net (fo=1, routed) 0.000 1.292 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10_n_0
|
|
SLICE_X6Y61 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CI
|
|
SLICE_X6Y61 CARRY4 (Prop_carry4_CI_CO[3])
|
|
0.117 1.409 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CO[3]
|
|
net (fo=1, routed) 0.000 1.409 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9_n_0
|
|
SLICE_X6Y62 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/CI
|
|
SLICE_X6Y62 CARRY4 (Prop_carry4_CI_O[2])
|
|
0.239 1.648 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/O[2]
|
|
net (fo=3, routed) 0.929 2.576 u_axi_ram/u_axi_sram_sp/upper_wrap_boundary[20]
|
|
SLICE_X5Y65 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_7/I2
|
|
SLICE_X5Y65 LUT4 (Prop_lut4_I2_O) 0.301 2.877 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_7/O
|
|
net (fo=1, routed) 0.000 2.877 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_7_n_0
|
|
SLICE_X5Y65 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1/S[1]
|
|
SLICE_X5Y65 CARRY4 (Prop_carry4_S[1]_CO[3])
|
|
0.550 3.427 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1/CO[3]
|
|
net (fo=1, routed) 0.000 3.427 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_n_0
|
|
SLICE_X5Y66 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2/CI
|
|
SLICE_X5Y66 CARRY4 (Prop_carry4_CI_CO[2])
|
|
0.228 3.655 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2/CO[2]
|
|
net (fo=22, routed) 0.735 4.390 u_axi_ram/u_axi_sram_sp/req_addr_d1
|
|
SLICE_X5Y68 r u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/I0
|
|
SLICE_X5Y68 LUT6 (Prop_lut6_I0_O) 0.313 4.703 f u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/O
|
|
net (fo=2, routed) 0.550 5.253 u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7_n_0
|
|
SLICE_X4Y68 f u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/I1
|
|
SLICE_X4Y68 LUT6 (Prop_lut6_I1_O) 0.124 5.377 f u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/O
|
|
net (fo=80, routed) 0.877 6.254 u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/soc_sram_addr[0]
|
|
SLICE_X1Y74 f u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/base_ram_data_IOBUF[31]_inst_i_3/I2
|
|
SLICE_X1Y74 LUT3 (Prop_lut3_I2_O) 0.124 6.378 f u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/base_ram_data_IOBUF[31]_inst_i_3/O
|
|
net (fo=32, routed) 3.130 9.508 base_ram_data_IOBUF[30]_inst/T
|
|
M24 f base_ram_data_IOBUF[30]_inst/OBUFT/T
|
|
M24 OBUFT (TriStatE_obuft_T_O)
|
|
3.559 13.067 r base_ram_data_IOBUF[30]_inst/OBUFT/O
|
|
net (fo=1, unset) 0.000 13.067 base_ram_data[30]
|
|
M24 r base_ram_data[30] (INOUT)
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock sys_clk rise edge) 20.000 20.000 r
|
|
clock source latency -5.674 14.326
|
|
propagated clock network latency
|
|
0.000 14.326
|
|
clock pessimism -0.601 13.725
|
|
clock uncertainty -0.071 13.654
|
|
output delay -0.300 13.354
|
|
-------------------------------------------------------------------
|
|
required time 13.354
|
|
arrival time -13.067
|
|
-------------------------------------------------------------------
|
|
slack 0.287
|
|
|
|
Slack (MET) : 0.287ns (required time - arrival time)
|
|
Source: u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[3]/C
|
|
(rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Destination: base_ram_data[30]
|
|
(output port clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Path Group: sys_clk
|
|
Path Type: Max at Slow Process Corner
|
|
Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns)
|
|
Data Path Delay: 15.388ns (logic 6.876ns (44.688%) route 8.511ns (55.312%))
|
|
Logic Levels: 14 (CARRY4=6 LUT3=1 LUT4=2 LUT5=1 LUT6=3 OBUFT=1)
|
|
Output Delay: 0.300ns
|
|
Clock Path Skew: -3.955ns (DCD - SCD + CPR)
|
|
Destination Clock Delay (DCD): -5.674ns = ( 14.326 - 20.000 )
|
|
Source Clock Delay (SCD): -2.321ns
|
|
Clock Pessimism Removal (CPR): -0.601ns
|
|
Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Discrete Jitter (DJ): 0.122ns
|
|
Phase Error (PE): 0.000ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock sys_clk rise edge) 0.000 0.000 r
|
|
clock source latency -6.275 -6.275
|
|
propagated clock network latency
|
|
3.955 -2.321
|
|
SLICE_X7Y62 FDCE 0.000 -2.321 r u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[3]/C
|
|
SLICE_X7Y62 FDCE (Prop_fdce_C_Q) 0.456 -1.865 f u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[3]/Q
|
|
net (fo=54, routed) 0.726 -1.139 u_axi_ram/u_axi_sram_sp/len[3]
|
|
SLICE_X7Y61 f u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6/I3
|
|
SLICE_X7Y61 LUT4 (Prop_lut4_I3_O) 0.124 -1.015 r u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6/O
|
|
net (fo=4, routed) 0.946 -0.068 u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6_n_0
|
|
SLICE_X7Y58 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_11/I1
|
|
SLICE_X7Y58 LUT5 (Prop_lut5_I1_O) 0.124 0.056 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_11/O
|
|
net (fo=2, routed) 0.619 0.675 u_axi_ram/u_axi_sram_sp/state_d2[7]
|
|
SLICE_X6Y59 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_15/I5
|
|
SLICE_X6Y59 LUT6 (Prop_lut6_I5_O) 0.124 0.799 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_15/O
|
|
net (fo=1, routed) 0.000 0.799 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_15_n_0
|
|
SLICE_X6Y59 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9/S[3]
|
|
SLICE_X6Y59 CARRY4 (Prop_carry4_S[3]_CO[3])
|
|
0.376 1.175 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9/CO[3]
|
|
net (fo=1, routed) 0.000 1.175 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9_n_0
|
|
SLICE_X6Y60 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/CI
|
|
SLICE_X6Y60 CARRY4 (Prop_carry4_CI_CO[3])
|
|
0.117 1.292 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/CO[3]
|
|
net (fo=1, routed) 0.000 1.292 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10_n_0
|
|
SLICE_X6Y61 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CI
|
|
SLICE_X6Y61 CARRY4 (Prop_carry4_CI_CO[3])
|
|
0.117 1.409 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CO[3]
|
|
net (fo=1, routed) 0.000 1.409 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9_n_0
|
|
SLICE_X6Y62 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/CI
|
|
SLICE_X6Y62 CARRY4 (Prop_carry4_CI_O[2])
|
|
0.239 1.648 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/O[2]
|
|
net (fo=3, routed) 0.929 2.576 u_axi_ram/u_axi_sram_sp/upper_wrap_boundary[20]
|
|
SLICE_X5Y65 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_7/I2
|
|
SLICE_X5Y65 LUT4 (Prop_lut4_I2_O) 0.301 2.877 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_7/O
|
|
net (fo=1, routed) 0.000 2.877 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_7_n_0
|
|
SLICE_X5Y65 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1/S[1]
|
|
SLICE_X5Y65 CARRY4 (Prop_carry4_S[1]_CO[3])
|
|
0.550 3.427 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1/CO[3]
|
|
net (fo=1, routed) 0.000 3.427 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_n_0
|
|
SLICE_X5Y66 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2/CI
|
|
SLICE_X5Y66 CARRY4 (Prop_carry4_CI_CO[2])
|
|
0.228 3.655 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2/CO[2]
|
|
net (fo=22, routed) 0.735 4.390 u_axi_ram/u_axi_sram_sp/req_addr_d1
|
|
SLICE_X5Y68 r u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/I0
|
|
SLICE_X5Y68 LUT6 (Prop_lut6_I0_O) 0.313 4.703 f u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/O
|
|
net (fo=2, routed) 0.550 5.253 u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7_n_0
|
|
SLICE_X4Y68 f u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/I1
|
|
SLICE_X4Y68 LUT6 (Prop_lut6_I1_O) 0.124 5.377 f u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/O
|
|
net (fo=80, routed) 0.877 6.254 u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/soc_sram_addr[0]
|
|
SLICE_X1Y74 f u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/base_ram_data_IOBUF[31]_inst_i_3/I2
|
|
SLICE_X1Y74 LUT3 (Prop_lut3_I2_O) 0.124 6.378 f u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/base_ram_data_IOBUF[31]_inst_i_3/O
|
|
net (fo=32, routed) 3.130 9.508 base_ram_data_IOBUF[30]_inst/T
|
|
M24 f base_ram_data_IOBUF[30]_inst/OBUFT/T
|
|
M24 OBUFT (TriStatE_obuft_T_O)
|
|
3.559 13.067 r base_ram_data_IOBUF[30]_inst/OBUFT/O
|
|
net (fo=1, unset) 0.000 13.067 base_ram_data[30]
|
|
M24 r base_ram_data[30] (INOUT)
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock sys_clk rise edge) 20.000 20.000 r
|
|
clock source latency -5.674 14.326
|
|
propagated clock network latency
|
|
0.000 14.326
|
|
clock pessimism -0.601 13.725
|
|
clock uncertainty -0.071 13.654
|
|
output delay -0.300 13.354
|
|
-------------------------------------------------------------------
|
|
required time 13.354
|
|
arrival time -13.067
|
|
-------------------------------------------------------------------
|
|
slack 0.287
|
|
|
|
Slack (MET) : 0.287ns (required time - arrival time)
|
|
Source: u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[3]/C
|
|
(rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Destination: base_ram_data[30]
|
|
(output port clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Path Group: sys_clk
|
|
Path Type: Max at Slow Process Corner
|
|
Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns)
|
|
Data Path Delay: 15.388ns (logic 6.876ns (44.688%) route 8.511ns (55.312%))
|
|
Logic Levels: 14 (CARRY4=6 LUT3=1 LUT4=2 LUT5=1 LUT6=3 OBUFT=1)
|
|
Output Delay: 0.300ns
|
|
Clock Path Skew: -3.955ns (DCD - SCD + CPR)
|
|
Destination Clock Delay (DCD): -5.674ns = ( 14.326 - 20.000 )
|
|
Source Clock Delay (SCD): -2.321ns
|
|
Clock Pessimism Removal (CPR): -0.601ns
|
|
Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Discrete Jitter (DJ): 0.122ns
|
|
Phase Error (PE): 0.000ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock sys_clk rise edge) 0.000 0.000 r
|
|
clock source latency -6.275 -6.275
|
|
propagated clock network latency
|
|
3.955 -2.321
|
|
SLICE_X7Y62 FDCE 0.000 -2.321 r u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[3]/C
|
|
SLICE_X7Y62 FDCE (Prop_fdce_C_Q) 0.456 -1.865 f u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[3]/Q
|
|
net (fo=54, routed) 0.726 -1.139 u_axi_ram/u_axi_sram_sp/len[3]
|
|
SLICE_X7Y61 f u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6/I3
|
|
SLICE_X7Y61 LUT4 (Prop_lut4_I3_O) 0.124 -1.015 r u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6/O
|
|
net (fo=4, routed) 0.946 -0.068 u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6_n_0
|
|
SLICE_X7Y58 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_11/I1
|
|
SLICE_X7Y58 LUT5 (Prop_lut5_I1_O) 0.124 0.056 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_11/O
|
|
net (fo=2, routed) 0.619 0.675 u_axi_ram/u_axi_sram_sp/state_d2[7]
|
|
SLICE_X6Y59 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_15/I5
|
|
SLICE_X6Y59 LUT6 (Prop_lut6_I5_O) 0.124 0.799 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_15/O
|
|
net (fo=1, routed) 0.000 0.799 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_15_n_0
|
|
SLICE_X6Y59 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9/S[3]
|
|
SLICE_X6Y59 CARRY4 (Prop_carry4_S[3]_CO[3])
|
|
0.376 1.175 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9/CO[3]
|
|
net (fo=1, routed) 0.000 1.175 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9_n_0
|
|
SLICE_X6Y60 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/CI
|
|
SLICE_X6Y60 CARRY4 (Prop_carry4_CI_CO[3])
|
|
0.117 1.292 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/CO[3]
|
|
net (fo=1, routed) 0.000 1.292 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10_n_0
|
|
SLICE_X6Y61 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CI
|
|
SLICE_X6Y61 CARRY4 (Prop_carry4_CI_CO[3])
|
|
0.117 1.409 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CO[3]
|
|
net (fo=1, routed) 0.000 1.409 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9_n_0
|
|
SLICE_X6Y62 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/CI
|
|
SLICE_X6Y62 CARRY4 (Prop_carry4_CI_O[2])
|
|
0.239 1.648 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/O[2]
|
|
net (fo=3, routed) 0.929 2.576 u_axi_ram/u_axi_sram_sp/upper_wrap_boundary[20]
|
|
SLICE_X5Y65 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_7/I2
|
|
SLICE_X5Y65 LUT4 (Prop_lut4_I2_O) 0.301 2.877 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_7/O
|
|
net (fo=1, routed) 0.000 2.877 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_7_n_0
|
|
SLICE_X5Y65 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1/S[1]
|
|
SLICE_X5Y65 CARRY4 (Prop_carry4_S[1]_CO[3])
|
|
0.550 3.427 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1/CO[3]
|
|
net (fo=1, routed) 0.000 3.427 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_n_0
|
|
SLICE_X5Y66 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2/CI
|
|
SLICE_X5Y66 CARRY4 (Prop_carry4_CI_CO[2])
|
|
0.228 3.655 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2/CO[2]
|
|
net (fo=22, routed) 0.735 4.390 u_axi_ram/u_axi_sram_sp/req_addr_d1
|
|
SLICE_X5Y68 r u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/I0
|
|
SLICE_X5Y68 LUT6 (Prop_lut6_I0_O) 0.313 4.703 f u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/O
|
|
net (fo=2, routed) 0.550 5.253 u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7_n_0
|
|
SLICE_X4Y68 f u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/I1
|
|
SLICE_X4Y68 LUT6 (Prop_lut6_I1_O) 0.124 5.377 f u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/O
|
|
net (fo=80, routed) 0.877 6.254 u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/soc_sram_addr[0]
|
|
SLICE_X1Y74 f u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/base_ram_data_IOBUF[31]_inst_i_3/I2
|
|
SLICE_X1Y74 LUT3 (Prop_lut3_I2_O) 0.124 6.378 f u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/base_ram_data_IOBUF[31]_inst_i_3/O
|
|
net (fo=32, routed) 3.130 9.508 base_ram_data_IOBUF[30]_inst/T
|
|
M24 f base_ram_data_IOBUF[30]_inst/OBUFT/T
|
|
M24 OBUFT (TriStatE_obuft_T_O)
|
|
3.559 13.067 r base_ram_data_IOBUF[30]_inst/OBUFT/O
|
|
net (fo=1, unset) 0.000 13.067 base_ram_data[30]
|
|
M24 r base_ram_data[30] (INOUT)
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock sys_clk rise edge) 20.000 20.000 r
|
|
clock source latency -5.674 14.326
|
|
propagated clock network latency
|
|
0.000 14.326
|
|
clock pessimism -0.601 13.725
|
|
clock uncertainty -0.071 13.654
|
|
output delay -0.300 13.354
|
|
-------------------------------------------------------------------
|
|
required time 13.354
|
|
arrival time -13.067
|
|
-------------------------------------------------------------------
|
|
slack 0.287
|
|
|
|
Slack (MET) : 0.287ns (required time - arrival time)
|
|
Source: u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[3]/C
|
|
(rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Destination: base_ram_data[30]
|
|
(output port clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Path Group: sys_clk
|
|
Path Type: Max at Slow Process Corner
|
|
Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns)
|
|
Data Path Delay: 15.388ns (logic 6.876ns (44.688%) route 8.511ns (55.312%))
|
|
Logic Levels: 14 (CARRY4=6 LUT3=1 LUT4=2 LUT5=1 LUT6=3 OBUFT=1)
|
|
Output Delay: 0.300ns
|
|
Clock Path Skew: -3.955ns (DCD - SCD + CPR)
|
|
Destination Clock Delay (DCD): -5.674ns = ( 14.326 - 20.000 )
|
|
Source Clock Delay (SCD): -2.321ns
|
|
Clock Pessimism Removal (CPR): -0.601ns
|
|
Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Discrete Jitter (DJ): 0.122ns
|
|
Phase Error (PE): 0.000ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock sys_clk rise edge) 0.000 0.000 r
|
|
clock source latency -6.275 -6.275
|
|
propagated clock network latency
|
|
3.955 -2.321
|
|
SLICE_X7Y62 FDCE 0.000 -2.321 r u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[3]/C
|
|
SLICE_X7Y62 FDCE (Prop_fdce_C_Q) 0.456 -1.865 f u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[3]/Q
|
|
net (fo=54, routed) 0.726 -1.139 u_axi_ram/u_axi_sram_sp/len[3]
|
|
SLICE_X7Y61 f u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6/I3
|
|
SLICE_X7Y61 LUT4 (Prop_lut4_I3_O) 0.124 -1.015 r u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6/O
|
|
net (fo=4, routed) 0.946 -0.068 u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6_n_0
|
|
SLICE_X7Y58 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_11/I1
|
|
SLICE_X7Y58 LUT5 (Prop_lut5_I1_O) 0.124 0.056 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_11/O
|
|
net (fo=2, routed) 0.619 0.675 u_axi_ram/u_axi_sram_sp/state_d2[7]
|
|
SLICE_X6Y59 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_15/I5
|
|
SLICE_X6Y59 LUT6 (Prop_lut6_I5_O) 0.124 0.799 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_15/O
|
|
net (fo=1, routed) 0.000 0.799 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_15_n_0
|
|
SLICE_X6Y59 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9/S[3]
|
|
SLICE_X6Y59 CARRY4 (Prop_carry4_S[3]_CO[3])
|
|
0.376 1.175 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9/CO[3]
|
|
net (fo=1, routed) 0.000 1.175 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9_n_0
|
|
SLICE_X6Y60 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/CI
|
|
SLICE_X6Y60 CARRY4 (Prop_carry4_CI_CO[3])
|
|
0.117 1.292 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/CO[3]
|
|
net (fo=1, routed) 0.000 1.292 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10_n_0
|
|
SLICE_X6Y61 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CI
|
|
SLICE_X6Y61 CARRY4 (Prop_carry4_CI_CO[3])
|
|
0.117 1.409 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CO[3]
|
|
net (fo=1, routed) 0.000 1.409 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9_n_0
|
|
SLICE_X6Y62 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/CI
|
|
SLICE_X6Y62 CARRY4 (Prop_carry4_CI_O[2])
|
|
0.239 1.648 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/O[2]
|
|
net (fo=3, routed) 0.929 2.576 u_axi_ram/u_axi_sram_sp/upper_wrap_boundary[20]
|
|
SLICE_X5Y65 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_7/I2
|
|
SLICE_X5Y65 LUT4 (Prop_lut4_I2_O) 0.301 2.877 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_7/O
|
|
net (fo=1, routed) 0.000 2.877 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_7_n_0
|
|
SLICE_X5Y65 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1/S[1]
|
|
SLICE_X5Y65 CARRY4 (Prop_carry4_S[1]_CO[3])
|
|
0.550 3.427 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1/CO[3]
|
|
net (fo=1, routed) 0.000 3.427 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_n_0
|
|
SLICE_X5Y66 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2/CI
|
|
SLICE_X5Y66 CARRY4 (Prop_carry4_CI_CO[2])
|
|
0.228 3.655 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2/CO[2]
|
|
net (fo=22, routed) 0.735 4.390 u_axi_ram/u_axi_sram_sp/req_addr_d1
|
|
SLICE_X5Y68 r u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/I0
|
|
SLICE_X5Y68 LUT6 (Prop_lut6_I0_O) 0.313 4.703 f u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/O
|
|
net (fo=2, routed) 0.550 5.253 u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7_n_0
|
|
SLICE_X4Y68 f u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/I1
|
|
SLICE_X4Y68 LUT6 (Prop_lut6_I1_O) 0.124 5.377 f u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/O
|
|
net (fo=80, routed) 0.877 6.254 u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/soc_sram_addr[0]
|
|
SLICE_X1Y74 f u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/base_ram_data_IOBUF[31]_inst_i_3/I2
|
|
SLICE_X1Y74 LUT3 (Prop_lut3_I2_O) 0.124 6.378 f u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/base_ram_data_IOBUF[31]_inst_i_3/O
|
|
net (fo=32, routed) 3.130 9.508 base_ram_data_IOBUF[30]_inst/T
|
|
M24 f base_ram_data_IOBUF[30]_inst/OBUFT/T
|
|
M24 OBUFT (TriStatE_obuft_T_O)
|
|
3.559 13.067 r base_ram_data_IOBUF[30]_inst/OBUFT/O
|
|
net (fo=1, unset) 0.000 13.067 base_ram_data[30]
|
|
M24 r base_ram_data[30] (INOUT)
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock sys_clk rise edge) 20.000 20.000 r
|
|
clock source latency -5.674 14.326
|
|
propagated clock network latency
|
|
0.000 14.326
|
|
clock pessimism -0.601 13.725
|
|
clock uncertainty -0.071 13.654
|
|
output delay -0.300 13.354
|
|
-------------------------------------------------------------------
|
|
required time 13.354
|
|
arrival time -13.067
|
|
-------------------------------------------------------------------
|
|
slack 0.287
|
|
|
|
Slack (MET) : 0.287ns (required time - arrival time)
|
|
Source: u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[3]/C
|
|
(rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Destination: base_ram_data[30]
|
|
(output port clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Path Group: sys_clk
|
|
Path Type: Max at Slow Process Corner
|
|
Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns)
|
|
Data Path Delay: 15.388ns (logic 6.876ns (44.688%) route 8.511ns (55.312%))
|
|
Logic Levels: 14 (CARRY4=6 LUT3=1 LUT4=2 LUT5=1 LUT6=3 OBUFT=1)
|
|
Output Delay: 0.300ns
|
|
Clock Path Skew: -3.955ns (DCD - SCD + CPR)
|
|
Destination Clock Delay (DCD): -5.674ns = ( 14.326 - 20.000 )
|
|
Source Clock Delay (SCD): -2.321ns
|
|
Clock Pessimism Removal (CPR): -0.601ns
|
|
Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Discrete Jitter (DJ): 0.122ns
|
|
Phase Error (PE): 0.000ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock sys_clk rise edge) 0.000 0.000 r
|
|
clock source latency -6.275 -6.275
|
|
propagated clock network latency
|
|
3.955 -2.321
|
|
SLICE_X7Y62 FDCE 0.000 -2.321 r u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[3]/C
|
|
SLICE_X7Y62 FDCE (Prop_fdce_C_Q) 0.456 -1.865 f u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[3]/Q
|
|
net (fo=54, routed) 0.726 -1.139 u_axi_ram/u_axi_sram_sp/len[3]
|
|
SLICE_X7Y61 f u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6/I3
|
|
SLICE_X7Y61 LUT4 (Prop_lut4_I3_O) 0.124 -1.015 r u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6/O
|
|
net (fo=4, routed) 0.946 -0.068 u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6_n_0
|
|
SLICE_X7Y58 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_11/I1
|
|
SLICE_X7Y58 LUT5 (Prop_lut5_I1_O) 0.124 0.056 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_11/O
|
|
net (fo=2, routed) 0.619 0.675 u_axi_ram/u_axi_sram_sp/state_d2[7]
|
|
SLICE_X6Y59 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_15/I5
|
|
SLICE_X6Y59 LUT6 (Prop_lut6_I5_O) 0.124 0.799 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_15/O
|
|
net (fo=1, routed) 0.000 0.799 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_15_n_0
|
|
SLICE_X6Y59 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9/S[3]
|
|
SLICE_X6Y59 CARRY4 (Prop_carry4_S[3]_CO[3])
|
|
0.376 1.175 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9/CO[3]
|
|
net (fo=1, routed) 0.000 1.175 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9_n_0
|
|
SLICE_X6Y60 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/CI
|
|
SLICE_X6Y60 CARRY4 (Prop_carry4_CI_CO[3])
|
|
0.117 1.292 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/CO[3]
|
|
net (fo=1, routed) 0.000 1.292 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10_n_0
|
|
SLICE_X6Y61 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CI
|
|
SLICE_X6Y61 CARRY4 (Prop_carry4_CI_CO[3])
|
|
0.117 1.409 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CO[3]
|
|
net (fo=1, routed) 0.000 1.409 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9_n_0
|
|
SLICE_X6Y62 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/CI
|
|
SLICE_X6Y62 CARRY4 (Prop_carry4_CI_O[2])
|
|
0.239 1.648 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/O[2]
|
|
net (fo=3, routed) 0.929 2.576 u_axi_ram/u_axi_sram_sp/upper_wrap_boundary[20]
|
|
SLICE_X5Y65 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_7/I2
|
|
SLICE_X5Y65 LUT4 (Prop_lut4_I2_O) 0.301 2.877 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_7/O
|
|
net (fo=1, routed) 0.000 2.877 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_7_n_0
|
|
SLICE_X5Y65 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1/S[1]
|
|
SLICE_X5Y65 CARRY4 (Prop_carry4_S[1]_CO[3])
|
|
0.550 3.427 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1/CO[3]
|
|
net (fo=1, routed) 0.000 3.427 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_n_0
|
|
SLICE_X5Y66 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2/CI
|
|
SLICE_X5Y66 CARRY4 (Prop_carry4_CI_CO[2])
|
|
0.228 3.655 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2/CO[2]
|
|
net (fo=22, routed) 0.735 4.390 u_axi_ram/u_axi_sram_sp/req_addr_d1
|
|
SLICE_X5Y68 r u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/I0
|
|
SLICE_X5Y68 LUT6 (Prop_lut6_I0_O) 0.313 4.703 f u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/O
|
|
net (fo=2, routed) 0.550 5.253 u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7_n_0
|
|
SLICE_X4Y68 f u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/I1
|
|
SLICE_X4Y68 LUT6 (Prop_lut6_I1_O) 0.124 5.377 f u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/O
|
|
net (fo=80, routed) 0.877 6.254 u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/soc_sram_addr[0]
|
|
SLICE_X1Y74 f u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/base_ram_data_IOBUF[31]_inst_i_3/I2
|
|
SLICE_X1Y74 LUT3 (Prop_lut3_I2_O) 0.124 6.378 f u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/base_ram_data_IOBUF[31]_inst_i_3/O
|
|
net (fo=32, routed) 3.130 9.508 base_ram_data_IOBUF[30]_inst/T
|
|
M24 f base_ram_data_IOBUF[30]_inst/OBUFT/T
|
|
M24 OBUFT (TriStatE_obuft_T_O)
|
|
3.559 13.067 r base_ram_data_IOBUF[30]_inst/OBUFT/O
|
|
net (fo=1, unset) 0.000 13.067 base_ram_data[30]
|
|
M24 r base_ram_data[30] (INOUT)
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock sys_clk rise edge) 20.000 20.000 r
|
|
clock source latency -5.674 14.326
|
|
propagated clock network latency
|
|
0.000 14.326
|
|
clock pessimism -0.601 13.725
|
|
clock uncertainty -0.071 13.654
|
|
output delay -0.300 13.354
|
|
-------------------------------------------------------------------
|
|
required time 13.354
|
|
arrival time -13.067
|
|
-------------------------------------------------------------------
|
|
slack 0.287
|
|
|
|
Slack (MET) : 0.287ns (required time - arrival time)
|
|
Source: u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[3]/C
|
|
(rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Destination: base_ram_data[30]
|
|
(output port clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Path Group: sys_clk
|
|
Path Type: Max at Slow Process Corner
|
|
Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns)
|
|
Data Path Delay: 15.388ns (logic 6.876ns (44.688%) route 8.511ns (55.312%))
|
|
Logic Levels: 14 (CARRY4=6 LUT3=1 LUT4=2 LUT5=1 LUT6=3 OBUFT=1)
|
|
Output Delay: 0.300ns
|
|
Clock Path Skew: -3.955ns (DCD - SCD + CPR)
|
|
Destination Clock Delay (DCD): -5.674ns = ( 14.326 - 20.000 )
|
|
Source Clock Delay (SCD): -2.321ns
|
|
Clock Pessimism Removal (CPR): -0.601ns
|
|
Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Discrete Jitter (DJ): 0.122ns
|
|
Phase Error (PE): 0.000ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock sys_clk rise edge) 0.000 0.000 r
|
|
clock source latency -6.275 -6.275
|
|
propagated clock network latency
|
|
3.955 -2.321
|
|
SLICE_X7Y62 FDCE 0.000 -2.321 r u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[3]/C
|
|
SLICE_X7Y62 FDCE (Prop_fdce_C_Q) 0.456 -1.865 f u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[3]/Q
|
|
net (fo=54, routed) 0.726 -1.139 u_axi_ram/u_axi_sram_sp/len[3]
|
|
SLICE_X7Y61 f u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6/I3
|
|
SLICE_X7Y61 LUT4 (Prop_lut4_I3_O) 0.124 -1.015 r u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6/O
|
|
net (fo=4, routed) 0.946 -0.068 u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6_n_0
|
|
SLICE_X7Y58 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_11/I1
|
|
SLICE_X7Y58 LUT5 (Prop_lut5_I1_O) 0.124 0.056 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_11/O
|
|
net (fo=2, routed) 0.619 0.675 u_axi_ram/u_axi_sram_sp/state_d2[7]
|
|
SLICE_X6Y59 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_15/I5
|
|
SLICE_X6Y59 LUT6 (Prop_lut6_I5_O) 0.124 0.799 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_15/O
|
|
net (fo=1, routed) 0.000 0.799 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_15_n_0
|
|
SLICE_X6Y59 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9/S[3]
|
|
SLICE_X6Y59 CARRY4 (Prop_carry4_S[3]_CO[3])
|
|
0.376 1.175 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9/CO[3]
|
|
net (fo=1, routed) 0.000 1.175 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9_n_0
|
|
SLICE_X6Y60 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/CI
|
|
SLICE_X6Y60 CARRY4 (Prop_carry4_CI_CO[3])
|
|
0.117 1.292 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/CO[3]
|
|
net (fo=1, routed) 0.000 1.292 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10_n_0
|
|
SLICE_X6Y61 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CI
|
|
SLICE_X6Y61 CARRY4 (Prop_carry4_CI_CO[3])
|
|
0.117 1.409 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CO[3]
|
|
net (fo=1, routed) 0.000 1.409 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9_n_0
|
|
SLICE_X6Y62 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/CI
|
|
SLICE_X6Y62 CARRY4 (Prop_carry4_CI_O[2])
|
|
0.239 1.648 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/O[2]
|
|
net (fo=3, routed) 0.929 2.576 u_axi_ram/u_axi_sram_sp/upper_wrap_boundary[20]
|
|
SLICE_X5Y65 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_7/I2
|
|
SLICE_X5Y65 LUT4 (Prop_lut4_I2_O) 0.301 2.877 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_7/O
|
|
net (fo=1, routed) 0.000 2.877 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_7_n_0
|
|
SLICE_X5Y65 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1/S[1]
|
|
SLICE_X5Y65 CARRY4 (Prop_carry4_S[1]_CO[3])
|
|
0.550 3.427 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1/CO[3]
|
|
net (fo=1, routed) 0.000 3.427 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_n_0
|
|
SLICE_X5Y66 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2/CI
|
|
SLICE_X5Y66 CARRY4 (Prop_carry4_CI_CO[2])
|
|
0.228 3.655 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2/CO[2]
|
|
net (fo=22, routed) 0.735 4.390 u_axi_ram/u_axi_sram_sp/req_addr_d1
|
|
SLICE_X5Y68 r u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/I0
|
|
SLICE_X5Y68 LUT6 (Prop_lut6_I0_O) 0.313 4.703 f u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/O
|
|
net (fo=2, routed) 0.550 5.253 u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7_n_0
|
|
SLICE_X4Y68 f u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/I1
|
|
SLICE_X4Y68 LUT6 (Prop_lut6_I1_O) 0.124 5.377 f u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/O
|
|
net (fo=80, routed) 0.877 6.254 u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/soc_sram_addr[0]
|
|
SLICE_X1Y74 f u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/base_ram_data_IOBUF[31]_inst_i_3/I2
|
|
SLICE_X1Y74 LUT3 (Prop_lut3_I2_O) 0.124 6.378 f u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/base_ram_data_IOBUF[31]_inst_i_3/O
|
|
net (fo=32, routed) 3.130 9.508 base_ram_data_IOBUF[30]_inst/T
|
|
M24 f base_ram_data_IOBUF[30]_inst/OBUFT/T
|
|
M24 OBUFT (TriStatE_obuft_T_O)
|
|
3.559 13.067 r base_ram_data_IOBUF[30]_inst/OBUFT/O
|
|
net (fo=1, unset) 0.000 13.067 base_ram_data[30]
|
|
M24 r base_ram_data[30] (INOUT)
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock sys_clk rise edge) 20.000 20.000 r
|
|
clock source latency -5.674 14.326
|
|
propagated clock network latency
|
|
0.000 14.326
|
|
clock pessimism -0.601 13.725
|
|
clock uncertainty -0.071 13.654
|
|
output delay -0.300 13.354
|
|
-------------------------------------------------------------------
|
|
required time 13.354
|
|
arrival time -13.067
|
|
-------------------------------------------------------------------
|
|
slack 0.287
|
|
|
|
Slack (MET) : 0.287ns (required time - arrival time)
|
|
Source: u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[3]/C
|
|
(rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Destination: base_ram_data[30]
|
|
(output port clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Path Group: sys_clk
|
|
Path Type: Max at Slow Process Corner
|
|
Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns)
|
|
Data Path Delay: 15.388ns (logic 6.876ns (44.688%) route 8.511ns (55.312%))
|
|
Logic Levels: 14 (CARRY4=6 LUT3=1 LUT4=2 LUT5=1 LUT6=3 OBUFT=1)
|
|
Output Delay: 0.300ns
|
|
Clock Path Skew: -3.955ns (DCD - SCD + CPR)
|
|
Destination Clock Delay (DCD): -5.674ns = ( 14.326 - 20.000 )
|
|
Source Clock Delay (SCD): -2.321ns
|
|
Clock Pessimism Removal (CPR): -0.601ns
|
|
Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Discrete Jitter (DJ): 0.122ns
|
|
Phase Error (PE): 0.000ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock sys_clk rise edge) 0.000 0.000 r
|
|
clock source latency -6.275 -6.275
|
|
propagated clock network latency
|
|
3.955 -2.321
|
|
SLICE_X7Y62 FDCE 0.000 -2.321 r u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[3]/C
|
|
SLICE_X7Y62 FDCE (Prop_fdce_C_Q) 0.456 -1.865 f u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[3]/Q
|
|
net (fo=54, routed) 0.726 -1.139 u_axi_ram/u_axi_sram_sp/len[3]
|
|
SLICE_X7Y61 f u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6/I3
|
|
SLICE_X7Y61 LUT4 (Prop_lut4_I3_O) 0.124 -1.015 r u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6/O
|
|
net (fo=4, routed) 0.946 -0.068 u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6_n_0
|
|
SLICE_X7Y58 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_11/I1
|
|
SLICE_X7Y58 LUT5 (Prop_lut5_I1_O) 0.124 0.056 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_11/O
|
|
net (fo=2, routed) 0.619 0.675 u_axi_ram/u_axi_sram_sp/state_d2[7]
|
|
SLICE_X6Y59 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_15/I5
|
|
SLICE_X6Y59 LUT6 (Prop_lut6_I5_O) 0.124 0.799 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_15/O
|
|
net (fo=1, routed) 0.000 0.799 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_15_n_0
|
|
SLICE_X6Y59 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9/S[3]
|
|
SLICE_X6Y59 CARRY4 (Prop_carry4_S[3]_CO[3])
|
|
0.376 1.175 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9/CO[3]
|
|
net (fo=1, routed) 0.000 1.175 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9_n_0
|
|
SLICE_X6Y60 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/CI
|
|
SLICE_X6Y60 CARRY4 (Prop_carry4_CI_CO[3])
|
|
0.117 1.292 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/CO[3]
|
|
net (fo=1, routed) 0.000 1.292 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10_n_0
|
|
SLICE_X6Y61 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CI
|
|
SLICE_X6Y61 CARRY4 (Prop_carry4_CI_CO[3])
|
|
0.117 1.409 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CO[3]
|
|
net (fo=1, routed) 0.000 1.409 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9_n_0
|
|
SLICE_X6Y62 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/CI
|
|
SLICE_X6Y62 CARRY4 (Prop_carry4_CI_O[2])
|
|
0.239 1.648 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/O[2]
|
|
net (fo=3, routed) 0.929 2.576 u_axi_ram/u_axi_sram_sp/upper_wrap_boundary[20]
|
|
SLICE_X5Y65 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_7/I2
|
|
SLICE_X5Y65 LUT4 (Prop_lut4_I2_O) 0.301 2.877 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_7/O
|
|
net (fo=1, routed) 0.000 2.877 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_7_n_0
|
|
SLICE_X5Y65 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1/S[1]
|
|
SLICE_X5Y65 CARRY4 (Prop_carry4_S[1]_CO[3])
|
|
0.550 3.427 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1/CO[3]
|
|
net (fo=1, routed) 0.000 3.427 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_n_0
|
|
SLICE_X5Y66 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2/CI
|
|
SLICE_X5Y66 CARRY4 (Prop_carry4_CI_CO[2])
|
|
0.228 3.655 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2/CO[2]
|
|
net (fo=22, routed) 0.735 4.390 u_axi_ram/u_axi_sram_sp/req_addr_d1
|
|
SLICE_X5Y68 r u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/I0
|
|
SLICE_X5Y68 LUT6 (Prop_lut6_I0_O) 0.313 4.703 f u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/O
|
|
net (fo=2, routed) 0.550 5.253 u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7_n_0
|
|
SLICE_X4Y68 f u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/I1
|
|
SLICE_X4Y68 LUT6 (Prop_lut6_I1_O) 0.124 5.377 f u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/O
|
|
net (fo=80, routed) 0.877 6.254 u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/soc_sram_addr[0]
|
|
SLICE_X1Y74 f u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/base_ram_data_IOBUF[31]_inst_i_3/I2
|
|
SLICE_X1Y74 LUT3 (Prop_lut3_I2_O) 0.124 6.378 f u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/base_ram_data_IOBUF[31]_inst_i_3/O
|
|
net (fo=32, routed) 3.130 9.508 base_ram_data_IOBUF[30]_inst/T
|
|
M24 f base_ram_data_IOBUF[30]_inst/OBUFT/T
|
|
M24 OBUFT (TriStatE_obuft_T_O)
|
|
3.559 13.067 r base_ram_data_IOBUF[30]_inst/OBUFT/O
|
|
net (fo=1, unset) 0.000 13.067 base_ram_data[30]
|
|
M24 r base_ram_data[30] (INOUT)
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock sys_clk rise edge) 20.000 20.000 r
|
|
clock source latency -5.674 14.326
|
|
propagated clock network latency
|
|
0.000 14.326
|
|
clock pessimism -0.601 13.725
|
|
clock uncertainty -0.071 13.654
|
|
output delay -0.300 13.354
|
|
-------------------------------------------------------------------
|
|
required time 13.354
|
|
arrival time -13.067
|
|
-------------------------------------------------------------------
|
|
slack 0.287
|
|
|
|
Slack (MET) : 0.311ns (required time - arrival time)
|
|
Source: u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[3]/C
|
|
(rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Destination: ext_ram_data[24]
|
|
(output port clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Path Group: sys_clk
|
|
Path Type: Max at Slow Process Corner
|
|
Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns)
|
|
Data Path Delay: 15.364ns (logic 6.875ns (44.747%) route 8.489ns (55.253%))
|
|
Logic Levels: 14 (CARRY4=6 LUT3=1 LUT4=2 LUT5=1 LUT6=3 OBUFT=1)
|
|
Output Delay: 0.300ns
|
|
Clock Path Skew: -3.955ns (DCD - SCD + CPR)
|
|
Destination Clock Delay (DCD): -5.674ns = ( 14.326 - 20.000 )
|
|
Source Clock Delay (SCD): -2.321ns
|
|
Clock Pessimism Removal (CPR): -0.601ns
|
|
Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Discrete Jitter (DJ): 0.122ns
|
|
Phase Error (PE): 0.000ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock sys_clk rise edge) 0.000 0.000 r
|
|
clock source latency -6.275 -6.275
|
|
propagated clock network latency
|
|
3.955 -2.321
|
|
SLICE_X7Y62 FDCE 0.000 -2.321 r u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[3]/C
|
|
SLICE_X7Y62 FDCE (Prop_fdce_C_Q) 0.456 -1.865 f u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[3]/Q
|
|
net (fo=54, routed) 0.726 -1.139 u_axi_ram/u_axi_sram_sp/len[3]
|
|
SLICE_X7Y61 f u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6/I3
|
|
SLICE_X7Y61 LUT4 (Prop_lut4_I3_O) 0.124 -1.015 r u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6/O
|
|
net (fo=4, routed) 0.946 -0.068 u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6_n_0
|
|
SLICE_X7Y58 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_11/I1
|
|
SLICE_X7Y58 LUT5 (Prop_lut5_I1_O) 0.124 0.056 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_11/O
|
|
net (fo=2, routed) 0.619 0.675 u_axi_ram/u_axi_sram_sp/state_d2[7]
|
|
SLICE_X6Y59 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_15/I5
|
|
SLICE_X6Y59 LUT6 (Prop_lut6_I5_O) 0.124 0.799 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_15/O
|
|
net (fo=1, routed) 0.000 0.799 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_15_n_0
|
|
SLICE_X6Y59 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9/S[3]
|
|
SLICE_X6Y59 CARRY4 (Prop_carry4_S[3]_CO[3])
|
|
0.376 1.175 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9/CO[3]
|
|
net (fo=1, routed) 0.000 1.175 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9_n_0
|
|
SLICE_X6Y60 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/CI
|
|
SLICE_X6Y60 CARRY4 (Prop_carry4_CI_CO[3])
|
|
0.117 1.292 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/CO[3]
|
|
net (fo=1, routed) 0.000 1.292 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10_n_0
|
|
SLICE_X6Y61 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CI
|
|
SLICE_X6Y61 CARRY4 (Prop_carry4_CI_CO[3])
|
|
0.117 1.409 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CO[3]
|
|
net (fo=1, routed) 0.000 1.409 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9_n_0
|
|
SLICE_X6Y62 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/CI
|
|
SLICE_X6Y62 CARRY4 (Prop_carry4_CI_O[2])
|
|
0.239 1.648 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/O[2]
|
|
net (fo=3, routed) 0.929 2.576 u_axi_ram/u_axi_sram_sp/upper_wrap_boundary[20]
|
|
SLICE_X5Y65 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_7/I2
|
|
SLICE_X5Y65 LUT4 (Prop_lut4_I2_O) 0.301 2.877 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_7/O
|
|
net (fo=1, routed) 0.000 2.877 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_7_n_0
|
|
SLICE_X5Y65 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1/S[1]
|
|
SLICE_X5Y65 CARRY4 (Prop_carry4_S[1]_CO[3])
|
|
0.550 3.427 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1/CO[3]
|
|
net (fo=1, routed) 0.000 3.427 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_n_0
|
|
SLICE_X5Y66 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2/CI
|
|
SLICE_X5Y66 CARRY4 (Prop_carry4_CI_CO[2])
|
|
0.228 3.655 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2/CO[2]
|
|
net (fo=22, routed) 0.735 4.390 u_axi_ram/u_axi_sram_sp/req_addr_d1
|
|
SLICE_X5Y68 r u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/I0
|
|
SLICE_X5Y68 LUT6 (Prop_lut6_I0_O) 0.313 4.703 r u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/O
|
|
net (fo=2, routed) 0.550 5.253 u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7_n_0
|
|
SLICE_X4Y68 r u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/I1
|
|
SLICE_X4Y68 LUT6 (Prop_lut6_I1_O) 0.124 5.377 r u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/O
|
|
net (fo=80, routed) 0.770 6.147 u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/soc_sram_addr[0]
|
|
SLICE_X1Y63 r u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/ext_ram_data_IOBUF[31]_inst_i_2/I2
|
|
SLICE_X1Y63 LUT3 (Prop_lut3_I2_O) 0.124 6.271 f u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/ext_ram_data_IOBUF[31]_inst_i_2/O
|
|
net (fo=32, routed) 3.214 9.485 ext_ram_data_IOBUF[24]_inst/T
|
|
AD17 f ext_ram_data_IOBUF[24]_inst/OBUFT/T
|
|
AD17 OBUFT (TriStatE_obuft_T_O)
|
|
3.558 13.043 r ext_ram_data_IOBUF[24]_inst/OBUFT/O
|
|
net (fo=1, unset) 0.000 13.043 ext_ram_data[24]
|
|
AD17 r ext_ram_data[24] (INOUT)
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock sys_clk rise edge) 20.000 20.000 r
|
|
clock source latency -5.674 14.326
|
|
propagated clock network latency
|
|
0.000 14.326
|
|
clock pessimism -0.601 13.725
|
|
clock uncertainty -0.071 13.654
|
|
output delay -0.300 13.354
|
|
-------------------------------------------------------------------
|
|
required time 13.354
|
|
arrival time -13.043
|
|
-------------------------------------------------------------------
|
|
slack 0.311
|
|
|
|
Slack (MET) : 0.311ns (required time - arrival time)
|
|
Source: u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[3]/C
|
|
(rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Destination: ext_ram_data[24]
|
|
(output port clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Path Group: sys_clk
|
|
Path Type: Max at Slow Process Corner
|
|
Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns)
|
|
Data Path Delay: 15.364ns (logic 6.875ns (44.747%) route 8.489ns (55.253%))
|
|
Logic Levels: 14 (CARRY4=6 LUT3=1 LUT4=2 LUT5=1 LUT6=3 OBUFT=1)
|
|
Output Delay: 0.300ns
|
|
Clock Path Skew: -3.955ns (DCD - SCD + CPR)
|
|
Destination Clock Delay (DCD): -5.674ns = ( 14.326 - 20.000 )
|
|
Source Clock Delay (SCD): -2.321ns
|
|
Clock Pessimism Removal (CPR): -0.601ns
|
|
Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Discrete Jitter (DJ): 0.122ns
|
|
Phase Error (PE): 0.000ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock sys_clk rise edge) 0.000 0.000 r
|
|
clock source latency -6.275 -6.275
|
|
propagated clock network latency
|
|
3.955 -2.321
|
|
SLICE_X7Y62 FDCE 0.000 -2.321 r u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[3]/C
|
|
SLICE_X7Y62 FDCE (Prop_fdce_C_Q) 0.456 -1.865 f u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[3]/Q
|
|
net (fo=54, routed) 0.726 -1.139 u_axi_ram/u_axi_sram_sp/len[3]
|
|
SLICE_X7Y61 f u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6/I3
|
|
SLICE_X7Y61 LUT4 (Prop_lut4_I3_O) 0.124 -1.015 r u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6/O
|
|
net (fo=4, routed) 0.946 -0.068 u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6_n_0
|
|
SLICE_X7Y58 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_11/I1
|
|
SLICE_X7Y58 LUT5 (Prop_lut5_I1_O) 0.124 0.056 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_11/O
|
|
net (fo=2, routed) 0.619 0.675 u_axi_ram/u_axi_sram_sp/state_d2[7]
|
|
SLICE_X6Y59 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_15/I5
|
|
SLICE_X6Y59 LUT6 (Prop_lut6_I5_O) 0.124 0.799 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_15/O
|
|
net (fo=1, routed) 0.000 0.799 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_15_n_0
|
|
SLICE_X6Y59 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9/S[3]
|
|
SLICE_X6Y59 CARRY4 (Prop_carry4_S[3]_CO[3])
|
|
0.376 1.175 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9/CO[3]
|
|
net (fo=1, routed) 0.000 1.175 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9_n_0
|
|
SLICE_X6Y60 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/CI
|
|
SLICE_X6Y60 CARRY4 (Prop_carry4_CI_CO[3])
|
|
0.117 1.292 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/CO[3]
|
|
net (fo=1, routed) 0.000 1.292 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10_n_0
|
|
SLICE_X6Y61 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CI
|
|
SLICE_X6Y61 CARRY4 (Prop_carry4_CI_CO[3])
|
|
0.117 1.409 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CO[3]
|
|
net (fo=1, routed) 0.000 1.409 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9_n_0
|
|
SLICE_X6Y62 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/CI
|
|
SLICE_X6Y62 CARRY4 (Prop_carry4_CI_O[2])
|
|
0.239 1.648 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/O[2]
|
|
net (fo=3, routed) 0.929 2.576 u_axi_ram/u_axi_sram_sp/upper_wrap_boundary[20]
|
|
SLICE_X5Y65 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_7/I2
|
|
SLICE_X5Y65 LUT4 (Prop_lut4_I2_O) 0.301 2.877 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_7/O
|
|
net (fo=1, routed) 0.000 2.877 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_7_n_0
|
|
SLICE_X5Y65 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1/S[1]
|
|
SLICE_X5Y65 CARRY4 (Prop_carry4_S[1]_CO[3])
|
|
0.550 3.427 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1/CO[3]
|
|
net (fo=1, routed) 0.000 3.427 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_n_0
|
|
SLICE_X5Y66 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2/CI
|
|
SLICE_X5Y66 CARRY4 (Prop_carry4_CI_CO[2])
|
|
0.228 3.655 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2/CO[2]
|
|
net (fo=22, routed) 0.735 4.390 u_axi_ram/u_axi_sram_sp/req_addr_d1
|
|
SLICE_X5Y68 r u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/I0
|
|
SLICE_X5Y68 LUT6 (Prop_lut6_I0_O) 0.313 4.703 r u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/O
|
|
net (fo=2, routed) 0.550 5.253 u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7_n_0
|
|
SLICE_X4Y68 r u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/I1
|
|
SLICE_X4Y68 LUT6 (Prop_lut6_I1_O) 0.124 5.377 r u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/O
|
|
net (fo=80, routed) 0.770 6.147 u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/soc_sram_addr[0]
|
|
SLICE_X1Y63 r u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/ext_ram_data_IOBUF[31]_inst_i_2/I2
|
|
SLICE_X1Y63 LUT3 (Prop_lut3_I2_O) 0.124 6.271 f u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/ext_ram_data_IOBUF[31]_inst_i_2/O
|
|
net (fo=32, routed) 3.214 9.485 ext_ram_data_IOBUF[24]_inst/T
|
|
AD17 f ext_ram_data_IOBUF[24]_inst/OBUFT/T
|
|
AD17 OBUFT (TriStatE_obuft_T_O)
|
|
3.558 13.043 r ext_ram_data_IOBUF[24]_inst/OBUFT/O
|
|
net (fo=1, unset) 0.000 13.043 ext_ram_data[24]
|
|
AD17 r ext_ram_data[24] (INOUT)
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock sys_clk rise edge) 20.000 20.000 r
|
|
clock source latency -5.674 14.326
|
|
propagated clock network latency
|
|
0.000 14.326
|
|
clock pessimism -0.601 13.725
|
|
clock uncertainty -0.071 13.654
|
|
output delay -0.300 13.354
|
|
-------------------------------------------------------------------
|
|
required time 13.354
|
|
arrival time -13.043
|
|
-------------------------------------------------------------------
|
|
slack 0.311
|
|
|
|
Slack (MET) : 0.311ns (required time - arrival time)
|
|
Source: u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[3]/C
|
|
(rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Destination: ext_ram_data[24]
|
|
(output port clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Path Group: sys_clk
|
|
Path Type: Max at Slow Process Corner
|
|
Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns)
|
|
Data Path Delay: 15.364ns (logic 6.875ns (44.747%) route 8.489ns (55.253%))
|
|
Logic Levels: 14 (CARRY4=6 LUT3=1 LUT4=2 LUT5=1 LUT6=3 OBUFT=1)
|
|
Output Delay: 0.300ns
|
|
Clock Path Skew: -3.955ns (DCD - SCD + CPR)
|
|
Destination Clock Delay (DCD): -5.674ns = ( 14.326 - 20.000 )
|
|
Source Clock Delay (SCD): -2.321ns
|
|
Clock Pessimism Removal (CPR): -0.601ns
|
|
Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Discrete Jitter (DJ): 0.122ns
|
|
Phase Error (PE): 0.000ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock sys_clk rise edge) 0.000 0.000 r
|
|
clock source latency -6.275 -6.275
|
|
propagated clock network latency
|
|
3.955 -2.321
|
|
SLICE_X7Y62 FDCE 0.000 -2.321 r u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[3]/C
|
|
SLICE_X7Y62 FDCE (Prop_fdce_C_Q) 0.456 -1.865 f u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[3]/Q
|
|
net (fo=54, routed) 0.726 -1.139 u_axi_ram/u_axi_sram_sp/len[3]
|
|
SLICE_X7Y61 f u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6/I3
|
|
SLICE_X7Y61 LUT4 (Prop_lut4_I3_O) 0.124 -1.015 r u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6/O
|
|
net (fo=4, routed) 0.946 -0.068 u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6_n_0
|
|
SLICE_X7Y58 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_11/I1
|
|
SLICE_X7Y58 LUT5 (Prop_lut5_I1_O) 0.124 0.056 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_11/O
|
|
net (fo=2, routed) 0.619 0.675 u_axi_ram/u_axi_sram_sp/state_d2[7]
|
|
SLICE_X6Y59 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_15/I5
|
|
SLICE_X6Y59 LUT6 (Prop_lut6_I5_O) 0.124 0.799 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_15/O
|
|
net (fo=1, routed) 0.000 0.799 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_15_n_0
|
|
SLICE_X6Y59 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9/S[3]
|
|
SLICE_X6Y59 CARRY4 (Prop_carry4_S[3]_CO[3])
|
|
0.376 1.175 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9/CO[3]
|
|
net (fo=1, routed) 0.000 1.175 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9_n_0
|
|
SLICE_X6Y60 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/CI
|
|
SLICE_X6Y60 CARRY4 (Prop_carry4_CI_CO[3])
|
|
0.117 1.292 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/CO[3]
|
|
net (fo=1, routed) 0.000 1.292 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10_n_0
|
|
SLICE_X6Y61 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CI
|
|
SLICE_X6Y61 CARRY4 (Prop_carry4_CI_CO[3])
|
|
0.117 1.409 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CO[3]
|
|
net (fo=1, routed) 0.000 1.409 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9_n_0
|
|
SLICE_X6Y62 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/CI
|
|
SLICE_X6Y62 CARRY4 (Prop_carry4_CI_O[2])
|
|
0.239 1.648 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/O[2]
|
|
net (fo=3, routed) 0.929 2.576 u_axi_ram/u_axi_sram_sp/upper_wrap_boundary[20]
|
|
SLICE_X5Y65 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_7/I2
|
|
SLICE_X5Y65 LUT4 (Prop_lut4_I2_O) 0.301 2.877 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_7/O
|
|
net (fo=1, routed) 0.000 2.877 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_7_n_0
|
|
SLICE_X5Y65 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1/S[1]
|
|
SLICE_X5Y65 CARRY4 (Prop_carry4_S[1]_CO[3])
|
|
0.550 3.427 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1/CO[3]
|
|
net (fo=1, routed) 0.000 3.427 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_n_0
|
|
SLICE_X5Y66 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2/CI
|
|
SLICE_X5Y66 CARRY4 (Prop_carry4_CI_CO[2])
|
|
0.228 3.655 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2/CO[2]
|
|
net (fo=22, routed) 0.735 4.390 u_axi_ram/u_axi_sram_sp/req_addr_d1
|
|
SLICE_X5Y68 r u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/I0
|
|
SLICE_X5Y68 LUT6 (Prop_lut6_I0_O) 0.313 4.703 r u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/O
|
|
net (fo=2, routed) 0.550 5.253 u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7_n_0
|
|
SLICE_X4Y68 r u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/I1
|
|
SLICE_X4Y68 LUT6 (Prop_lut6_I1_O) 0.124 5.377 r u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/O
|
|
net (fo=80, routed) 0.770 6.147 u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/soc_sram_addr[0]
|
|
SLICE_X1Y63 r u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/ext_ram_data_IOBUF[31]_inst_i_2/I2
|
|
SLICE_X1Y63 LUT3 (Prop_lut3_I2_O) 0.124 6.271 f u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/ext_ram_data_IOBUF[31]_inst_i_2/O
|
|
net (fo=32, routed) 3.214 9.485 ext_ram_data_IOBUF[24]_inst/T
|
|
AD17 f ext_ram_data_IOBUF[24]_inst/OBUFT/T
|
|
AD17 OBUFT (TriStatE_obuft_T_O)
|
|
3.558 13.043 r ext_ram_data_IOBUF[24]_inst/OBUFT/O
|
|
net (fo=1, unset) 0.000 13.043 ext_ram_data[24]
|
|
AD17 r ext_ram_data[24] (INOUT)
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock sys_clk rise edge) 20.000 20.000 r
|
|
clock source latency -5.674 14.326
|
|
propagated clock network latency
|
|
0.000 14.326
|
|
clock pessimism -0.601 13.725
|
|
clock uncertainty -0.071 13.654
|
|
output delay -0.300 13.354
|
|
-------------------------------------------------------------------
|
|
required time 13.354
|
|
arrival time -13.043
|
|
-------------------------------------------------------------------
|
|
slack 0.311
|
|
|
|
Slack (MET) : 0.311ns (required time - arrival time)
|
|
Source: u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[3]/C
|
|
(rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Destination: ext_ram_data[24]
|
|
(output port clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Path Group: sys_clk
|
|
Path Type: Max at Slow Process Corner
|
|
Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns)
|
|
Data Path Delay: 15.364ns (logic 6.875ns (44.747%) route 8.489ns (55.253%))
|
|
Logic Levels: 14 (CARRY4=6 LUT3=1 LUT4=2 LUT5=1 LUT6=3 OBUFT=1)
|
|
Output Delay: 0.300ns
|
|
Clock Path Skew: -3.955ns (DCD - SCD + CPR)
|
|
Destination Clock Delay (DCD): -5.674ns = ( 14.326 - 20.000 )
|
|
Source Clock Delay (SCD): -2.321ns
|
|
Clock Pessimism Removal (CPR): -0.601ns
|
|
Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Discrete Jitter (DJ): 0.122ns
|
|
Phase Error (PE): 0.000ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock sys_clk rise edge) 0.000 0.000 r
|
|
clock source latency -6.275 -6.275
|
|
propagated clock network latency
|
|
3.955 -2.321
|
|
SLICE_X7Y62 FDCE 0.000 -2.321 r u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[3]/C
|
|
SLICE_X7Y62 FDCE (Prop_fdce_C_Q) 0.456 -1.865 f u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[3]/Q
|
|
net (fo=54, routed) 0.726 -1.139 u_axi_ram/u_axi_sram_sp/len[3]
|
|
SLICE_X7Y61 f u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6/I3
|
|
SLICE_X7Y61 LUT4 (Prop_lut4_I3_O) 0.124 -1.015 r u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6/O
|
|
net (fo=4, routed) 0.946 -0.068 u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6_n_0
|
|
SLICE_X7Y58 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_11/I1
|
|
SLICE_X7Y58 LUT5 (Prop_lut5_I1_O) 0.124 0.056 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_11/O
|
|
net (fo=2, routed) 0.619 0.675 u_axi_ram/u_axi_sram_sp/state_d2[7]
|
|
SLICE_X6Y59 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_15/I5
|
|
SLICE_X6Y59 LUT6 (Prop_lut6_I5_O) 0.124 0.799 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_15/O
|
|
net (fo=1, routed) 0.000 0.799 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_15_n_0
|
|
SLICE_X6Y59 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9/S[3]
|
|
SLICE_X6Y59 CARRY4 (Prop_carry4_S[3]_CO[3])
|
|
0.376 1.175 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9/CO[3]
|
|
net (fo=1, routed) 0.000 1.175 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9_n_0
|
|
SLICE_X6Y60 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/CI
|
|
SLICE_X6Y60 CARRY4 (Prop_carry4_CI_CO[3])
|
|
0.117 1.292 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/CO[3]
|
|
net (fo=1, routed) 0.000 1.292 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10_n_0
|
|
SLICE_X6Y61 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CI
|
|
SLICE_X6Y61 CARRY4 (Prop_carry4_CI_CO[3])
|
|
0.117 1.409 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CO[3]
|
|
net (fo=1, routed) 0.000 1.409 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9_n_0
|
|
SLICE_X6Y62 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/CI
|
|
SLICE_X6Y62 CARRY4 (Prop_carry4_CI_O[2])
|
|
0.239 1.648 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/O[2]
|
|
net (fo=3, routed) 0.929 2.576 u_axi_ram/u_axi_sram_sp/upper_wrap_boundary[20]
|
|
SLICE_X5Y65 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_7/I2
|
|
SLICE_X5Y65 LUT4 (Prop_lut4_I2_O) 0.301 2.877 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_7/O
|
|
net (fo=1, routed) 0.000 2.877 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_7_n_0
|
|
SLICE_X5Y65 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1/S[1]
|
|
SLICE_X5Y65 CARRY4 (Prop_carry4_S[1]_CO[3])
|
|
0.550 3.427 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1/CO[3]
|
|
net (fo=1, routed) 0.000 3.427 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_n_0
|
|
SLICE_X5Y66 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2/CI
|
|
SLICE_X5Y66 CARRY4 (Prop_carry4_CI_CO[2])
|
|
0.228 3.655 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2/CO[2]
|
|
net (fo=22, routed) 0.735 4.390 u_axi_ram/u_axi_sram_sp/req_addr_d1
|
|
SLICE_X5Y68 r u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/I0
|
|
SLICE_X5Y68 LUT6 (Prop_lut6_I0_O) 0.313 4.703 r u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/O
|
|
net (fo=2, routed) 0.550 5.253 u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7_n_0
|
|
SLICE_X4Y68 r u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/I1
|
|
SLICE_X4Y68 LUT6 (Prop_lut6_I1_O) 0.124 5.377 r u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/O
|
|
net (fo=80, routed) 0.770 6.147 u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/soc_sram_addr[0]
|
|
SLICE_X1Y63 r u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/ext_ram_data_IOBUF[31]_inst_i_2/I2
|
|
SLICE_X1Y63 LUT3 (Prop_lut3_I2_O) 0.124 6.271 f u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/ext_ram_data_IOBUF[31]_inst_i_2/O
|
|
net (fo=32, routed) 3.214 9.485 ext_ram_data_IOBUF[24]_inst/T
|
|
AD17 f ext_ram_data_IOBUF[24]_inst/OBUFT/T
|
|
AD17 OBUFT (TriStatE_obuft_T_O)
|
|
3.558 13.043 r ext_ram_data_IOBUF[24]_inst/OBUFT/O
|
|
net (fo=1, unset) 0.000 13.043 ext_ram_data[24]
|
|
AD17 r ext_ram_data[24] (INOUT)
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock sys_clk rise edge) 20.000 20.000 r
|
|
clock source latency -5.674 14.326
|
|
propagated clock network latency
|
|
0.000 14.326
|
|
clock pessimism -0.601 13.725
|
|
clock uncertainty -0.071 13.654
|
|
output delay -0.300 13.354
|
|
-------------------------------------------------------------------
|
|
required time 13.354
|
|
arrival time -13.043
|
|
-------------------------------------------------------------------
|
|
slack 0.311
|
|
|
|
Slack (MET) : 0.311ns (required time - arrival time)
|
|
Source: u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[3]/C
|
|
(rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Destination: ext_ram_data[24]
|
|
(output port clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Path Group: sys_clk
|
|
Path Type: Max at Slow Process Corner
|
|
Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns)
|
|
Data Path Delay: 15.364ns (logic 6.875ns (44.747%) route 8.489ns (55.253%))
|
|
Logic Levels: 14 (CARRY4=6 LUT3=1 LUT4=2 LUT5=1 LUT6=3 OBUFT=1)
|
|
Output Delay: 0.300ns
|
|
Clock Path Skew: -3.955ns (DCD - SCD + CPR)
|
|
Destination Clock Delay (DCD): -5.674ns = ( 14.326 - 20.000 )
|
|
Source Clock Delay (SCD): -2.321ns
|
|
Clock Pessimism Removal (CPR): -0.601ns
|
|
Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Discrete Jitter (DJ): 0.122ns
|
|
Phase Error (PE): 0.000ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock sys_clk rise edge) 0.000 0.000 r
|
|
clock source latency -6.275 -6.275
|
|
propagated clock network latency
|
|
3.955 -2.321
|
|
SLICE_X7Y62 FDCE 0.000 -2.321 r u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[3]/C
|
|
SLICE_X7Y62 FDCE (Prop_fdce_C_Q) 0.456 -1.865 f u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[3]/Q
|
|
net (fo=54, routed) 0.726 -1.139 u_axi_ram/u_axi_sram_sp/len[3]
|
|
SLICE_X7Y61 f u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6/I3
|
|
SLICE_X7Y61 LUT4 (Prop_lut4_I3_O) 0.124 -1.015 r u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6/O
|
|
net (fo=4, routed) 0.946 -0.068 u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6_n_0
|
|
SLICE_X7Y58 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_11/I1
|
|
SLICE_X7Y58 LUT5 (Prop_lut5_I1_O) 0.124 0.056 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_11/O
|
|
net (fo=2, routed) 0.619 0.675 u_axi_ram/u_axi_sram_sp/state_d2[7]
|
|
SLICE_X6Y59 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_15/I5
|
|
SLICE_X6Y59 LUT6 (Prop_lut6_I5_O) 0.124 0.799 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_15/O
|
|
net (fo=1, routed) 0.000 0.799 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_15_n_0
|
|
SLICE_X6Y59 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9/S[3]
|
|
SLICE_X6Y59 CARRY4 (Prop_carry4_S[3]_CO[3])
|
|
0.376 1.175 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9/CO[3]
|
|
net (fo=1, routed) 0.000 1.175 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9_n_0
|
|
SLICE_X6Y60 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/CI
|
|
SLICE_X6Y60 CARRY4 (Prop_carry4_CI_CO[3])
|
|
0.117 1.292 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/CO[3]
|
|
net (fo=1, routed) 0.000 1.292 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10_n_0
|
|
SLICE_X6Y61 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CI
|
|
SLICE_X6Y61 CARRY4 (Prop_carry4_CI_CO[3])
|
|
0.117 1.409 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CO[3]
|
|
net (fo=1, routed) 0.000 1.409 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9_n_0
|
|
SLICE_X6Y62 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/CI
|
|
SLICE_X6Y62 CARRY4 (Prop_carry4_CI_O[2])
|
|
0.239 1.648 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/O[2]
|
|
net (fo=3, routed) 0.929 2.576 u_axi_ram/u_axi_sram_sp/upper_wrap_boundary[20]
|
|
SLICE_X5Y65 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_7/I2
|
|
SLICE_X5Y65 LUT4 (Prop_lut4_I2_O) 0.301 2.877 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_7/O
|
|
net (fo=1, routed) 0.000 2.877 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_7_n_0
|
|
SLICE_X5Y65 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1/S[1]
|
|
SLICE_X5Y65 CARRY4 (Prop_carry4_S[1]_CO[3])
|
|
0.550 3.427 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1/CO[3]
|
|
net (fo=1, routed) 0.000 3.427 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_n_0
|
|
SLICE_X5Y66 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2/CI
|
|
SLICE_X5Y66 CARRY4 (Prop_carry4_CI_CO[2])
|
|
0.228 3.655 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2/CO[2]
|
|
net (fo=22, routed) 0.735 4.390 u_axi_ram/u_axi_sram_sp/req_addr_d1
|
|
SLICE_X5Y68 r u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/I0
|
|
SLICE_X5Y68 LUT6 (Prop_lut6_I0_O) 0.313 4.703 r u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/O
|
|
net (fo=2, routed) 0.550 5.253 u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7_n_0
|
|
SLICE_X4Y68 r u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/I1
|
|
SLICE_X4Y68 LUT6 (Prop_lut6_I1_O) 0.124 5.377 r u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/O
|
|
net (fo=80, routed) 0.770 6.147 u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/soc_sram_addr[0]
|
|
SLICE_X1Y63 r u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/ext_ram_data_IOBUF[31]_inst_i_2/I2
|
|
SLICE_X1Y63 LUT3 (Prop_lut3_I2_O) 0.124 6.271 f u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/ext_ram_data_IOBUF[31]_inst_i_2/O
|
|
net (fo=32, routed) 3.214 9.485 ext_ram_data_IOBUF[24]_inst/T
|
|
AD17 f ext_ram_data_IOBUF[24]_inst/OBUFT/T
|
|
AD17 OBUFT (TriStatE_obuft_T_O)
|
|
3.558 13.043 r ext_ram_data_IOBUF[24]_inst/OBUFT/O
|
|
net (fo=1, unset) 0.000 13.043 ext_ram_data[24]
|
|
AD17 r ext_ram_data[24] (INOUT)
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock sys_clk rise edge) 20.000 20.000 r
|
|
clock source latency -5.674 14.326
|
|
propagated clock network latency
|
|
0.000 14.326
|
|
clock pessimism -0.601 13.725
|
|
clock uncertainty -0.071 13.654
|
|
output delay -0.300 13.354
|
|
-------------------------------------------------------------------
|
|
required time 13.354
|
|
arrival time -13.043
|
|
-------------------------------------------------------------------
|
|
slack 0.311
|
|
|
|
Slack (MET) : 0.311ns (required time - arrival time)
|
|
Source: u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[3]/C
|
|
(rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Destination: ext_ram_data[24]
|
|
(output port clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Path Group: sys_clk
|
|
Path Type: Max at Slow Process Corner
|
|
Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns)
|
|
Data Path Delay: 15.364ns (logic 6.875ns (44.747%) route 8.489ns (55.253%))
|
|
Logic Levels: 14 (CARRY4=6 LUT3=1 LUT4=2 LUT5=1 LUT6=3 OBUFT=1)
|
|
Output Delay: 0.300ns
|
|
Clock Path Skew: -3.955ns (DCD - SCD + CPR)
|
|
Destination Clock Delay (DCD): -5.674ns = ( 14.326 - 20.000 )
|
|
Source Clock Delay (SCD): -2.321ns
|
|
Clock Pessimism Removal (CPR): -0.601ns
|
|
Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Discrete Jitter (DJ): 0.122ns
|
|
Phase Error (PE): 0.000ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock sys_clk rise edge) 0.000 0.000 r
|
|
clock source latency -6.275 -6.275
|
|
propagated clock network latency
|
|
3.955 -2.321
|
|
SLICE_X7Y62 FDCE 0.000 -2.321 r u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[3]/C
|
|
SLICE_X7Y62 FDCE (Prop_fdce_C_Q) 0.456 -1.865 f u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[3]/Q
|
|
net (fo=54, routed) 0.726 -1.139 u_axi_ram/u_axi_sram_sp/len[3]
|
|
SLICE_X7Y61 f u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6/I3
|
|
SLICE_X7Y61 LUT4 (Prop_lut4_I3_O) 0.124 -1.015 r u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6/O
|
|
net (fo=4, routed) 0.946 -0.068 u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6_n_0
|
|
SLICE_X7Y58 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_11/I1
|
|
SLICE_X7Y58 LUT5 (Prop_lut5_I1_O) 0.124 0.056 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_11/O
|
|
net (fo=2, routed) 0.619 0.675 u_axi_ram/u_axi_sram_sp/state_d2[7]
|
|
SLICE_X6Y59 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_15/I5
|
|
SLICE_X6Y59 LUT6 (Prop_lut6_I5_O) 0.124 0.799 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_15/O
|
|
net (fo=1, routed) 0.000 0.799 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_15_n_0
|
|
SLICE_X6Y59 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9/S[3]
|
|
SLICE_X6Y59 CARRY4 (Prop_carry4_S[3]_CO[3])
|
|
0.376 1.175 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9/CO[3]
|
|
net (fo=1, routed) 0.000 1.175 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9_n_0
|
|
SLICE_X6Y60 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/CI
|
|
SLICE_X6Y60 CARRY4 (Prop_carry4_CI_CO[3])
|
|
0.117 1.292 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/CO[3]
|
|
net (fo=1, routed) 0.000 1.292 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10_n_0
|
|
SLICE_X6Y61 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CI
|
|
SLICE_X6Y61 CARRY4 (Prop_carry4_CI_CO[3])
|
|
0.117 1.409 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CO[3]
|
|
net (fo=1, routed) 0.000 1.409 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9_n_0
|
|
SLICE_X6Y62 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/CI
|
|
SLICE_X6Y62 CARRY4 (Prop_carry4_CI_O[2])
|
|
0.239 1.648 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/O[2]
|
|
net (fo=3, routed) 0.929 2.576 u_axi_ram/u_axi_sram_sp/upper_wrap_boundary[20]
|
|
SLICE_X5Y65 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_7/I2
|
|
SLICE_X5Y65 LUT4 (Prop_lut4_I2_O) 0.301 2.877 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_7/O
|
|
net (fo=1, routed) 0.000 2.877 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_7_n_0
|
|
SLICE_X5Y65 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1/S[1]
|
|
SLICE_X5Y65 CARRY4 (Prop_carry4_S[1]_CO[3])
|
|
0.550 3.427 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1/CO[3]
|
|
net (fo=1, routed) 0.000 3.427 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_n_0
|
|
SLICE_X5Y66 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2/CI
|
|
SLICE_X5Y66 CARRY4 (Prop_carry4_CI_CO[2])
|
|
0.228 3.655 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2/CO[2]
|
|
net (fo=22, routed) 0.735 4.390 u_axi_ram/u_axi_sram_sp/req_addr_d1
|
|
SLICE_X5Y68 r u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/I0
|
|
SLICE_X5Y68 LUT6 (Prop_lut6_I0_O) 0.313 4.703 r u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/O
|
|
net (fo=2, routed) 0.550 5.253 u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7_n_0
|
|
SLICE_X4Y68 r u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/I1
|
|
SLICE_X4Y68 LUT6 (Prop_lut6_I1_O) 0.124 5.377 r u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/O
|
|
net (fo=80, routed) 0.770 6.147 u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/soc_sram_addr[0]
|
|
SLICE_X1Y63 r u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/ext_ram_data_IOBUF[31]_inst_i_2/I2
|
|
SLICE_X1Y63 LUT3 (Prop_lut3_I2_O) 0.124 6.271 f u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/ext_ram_data_IOBUF[31]_inst_i_2/O
|
|
net (fo=32, routed) 3.214 9.485 ext_ram_data_IOBUF[24]_inst/T
|
|
AD17 f ext_ram_data_IOBUF[24]_inst/OBUFT/T
|
|
AD17 OBUFT (TriStatE_obuft_T_O)
|
|
3.558 13.043 r ext_ram_data_IOBUF[24]_inst/OBUFT/O
|
|
net (fo=1, unset) 0.000 13.043 ext_ram_data[24]
|
|
AD17 r ext_ram_data[24] (INOUT)
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock sys_clk rise edge) 20.000 20.000 r
|
|
clock source latency -5.674 14.326
|
|
propagated clock network latency
|
|
0.000 14.326
|
|
clock pessimism -0.601 13.725
|
|
clock uncertainty -0.071 13.654
|
|
output delay -0.300 13.354
|
|
-------------------------------------------------------------------
|
|
required time 13.354
|
|
arrival time -13.043
|
|
-------------------------------------------------------------------
|
|
slack 0.311
|
|
|
|
Slack (MET) : 0.311ns (required time - arrival time)
|
|
Source: u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[3]/C
|
|
(rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Destination: ext_ram_data[24]
|
|
(output port clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Path Group: sys_clk
|
|
Path Type: Max at Slow Process Corner
|
|
Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns)
|
|
Data Path Delay: 15.364ns (logic 6.875ns (44.747%) route 8.489ns (55.253%))
|
|
Logic Levels: 14 (CARRY4=6 LUT3=1 LUT4=2 LUT5=1 LUT6=3 OBUFT=1)
|
|
Output Delay: 0.300ns
|
|
Clock Path Skew: -3.955ns (DCD - SCD + CPR)
|
|
Destination Clock Delay (DCD): -5.674ns = ( 14.326 - 20.000 )
|
|
Source Clock Delay (SCD): -2.321ns
|
|
Clock Pessimism Removal (CPR): -0.601ns
|
|
Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Discrete Jitter (DJ): 0.122ns
|
|
Phase Error (PE): 0.000ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock sys_clk rise edge) 0.000 0.000 r
|
|
clock source latency -6.275 -6.275
|
|
propagated clock network latency
|
|
3.955 -2.321
|
|
SLICE_X7Y62 FDCE 0.000 -2.321 r u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[3]/C
|
|
SLICE_X7Y62 FDCE (Prop_fdce_C_Q) 0.456 -1.865 f u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[3]/Q
|
|
net (fo=54, routed) 0.726 -1.139 u_axi_ram/u_axi_sram_sp/len[3]
|
|
SLICE_X7Y61 f u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6/I3
|
|
SLICE_X7Y61 LUT4 (Prop_lut4_I3_O) 0.124 -1.015 r u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6/O
|
|
net (fo=4, routed) 0.946 -0.068 u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6_n_0
|
|
SLICE_X7Y58 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_11/I1
|
|
SLICE_X7Y58 LUT5 (Prop_lut5_I1_O) 0.124 0.056 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_11/O
|
|
net (fo=2, routed) 0.619 0.675 u_axi_ram/u_axi_sram_sp/state_d2[7]
|
|
SLICE_X6Y59 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_15/I5
|
|
SLICE_X6Y59 LUT6 (Prop_lut6_I5_O) 0.124 0.799 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_15/O
|
|
net (fo=1, routed) 0.000 0.799 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_15_n_0
|
|
SLICE_X6Y59 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9/S[3]
|
|
SLICE_X6Y59 CARRY4 (Prop_carry4_S[3]_CO[3])
|
|
0.376 1.175 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9/CO[3]
|
|
net (fo=1, routed) 0.000 1.175 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9_n_0
|
|
SLICE_X6Y60 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/CI
|
|
SLICE_X6Y60 CARRY4 (Prop_carry4_CI_CO[3])
|
|
0.117 1.292 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/CO[3]
|
|
net (fo=1, routed) 0.000 1.292 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10_n_0
|
|
SLICE_X6Y61 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CI
|
|
SLICE_X6Y61 CARRY4 (Prop_carry4_CI_CO[3])
|
|
0.117 1.409 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CO[3]
|
|
net (fo=1, routed) 0.000 1.409 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9_n_0
|
|
SLICE_X6Y62 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/CI
|
|
SLICE_X6Y62 CARRY4 (Prop_carry4_CI_O[2])
|
|
0.239 1.648 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/O[2]
|
|
net (fo=3, routed) 0.929 2.576 u_axi_ram/u_axi_sram_sp/upper_wrap_boundary[20]
|
|
SLICE_X5Y65 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_7/I2
|
|
SLICE_X5Y65 LUT4 (Prop_lut4_I2_O) 0.301 2.877 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_7/O
|
|
net (fo=1, routed) 0.000 2.877 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_7_n_0
|
|
SLICE_X5Y65 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1/S[1]
|
|
SLICE_X5Y65 CARRY4 (Prop_carry4_S[1]_CO[3])
|
|
0.550 3.427 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1/CO[3]
|
|
net (fo=1, routed) 0.000 3.427 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_n_0
|
|
SLICE_X5Y66 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2/CI
|
|
SLICE_X5Y66 CARRY4 (Prop_carry4_CI_CO[2])
|
|
0.228 3.655 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2/CO[2]
|
|
net (fo=22, routed) 0.735 4.390 u_axi_ram/u_axi_sram_sp/req_addr_d1
|
|
SLICE_X5Y68 r u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/I0
|
|
SLICE_X5Y68 LUT6 (Prop_lut6_I0_O) 0.313 4.703 r u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/O
|
|
net (fo=2, routed) 0.550 5.253 u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7_n_0
|
|
SLICE_X4Y68 r u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/I1
|
|
SLICE_X4Y68 LUT6 (Prop_lut6_I1_O) 0.124 5.377 r u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/O
|
|
net (fo=80, routed) 0.770 6.147 u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/soc_sram_addr[0]
|
|
SLICE_X1Y63 r u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/ext_ram_data_IOBUF[31]_inst_i_2/I2
|
|
SLICE_X1Y63 LUT3 (Prop_lut3_I2_O) 0.124 6.271 f u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/ext_ram_data_IOBUF[31]_inst_i_2/O
|
|
net (fo=32, routed) 3.214 9.485 ext_ram_data_IOBUF[24]_inst/T
|
|
AD17 f ext_ram_data_IOBUF[24]_inst/OBUFT/T
|
|
AD17 OBUFT (TriStatE_obuft_T_O)
|
|
3.558 13.043 r ext_ram_data_IOBUF[24]_inst/OBUFT/O
|
|
net (fo=1, unset) 0.000 13.043 ext_ram_data[24]
|
|
AD17 r ext_ram_data[24] (INOUT)
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock sys_clk rise edge) 20.000 20.000 r
|
|
clock source latency -5.674 14.326
|
|
propagated clock network latency
|
|
0.000 14.326
|
|
clock pessimism -0.601 13.725
|
|
clock uncertainty -0.071 13.654
|
|
output delay -0.300 13.354
|
|
-------------------------------------------------------------------
|
|
required time 13.354
|
|
arrival time -13.043
|
|
-------------------------------------------------------------------
|
|
slack 0.311
|
|
|
|
Slack (MET) : 0.311ns (required time - arrival time)
|
|
Source: u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[3]/C
|
|
(rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Destination: ext_ram_data[24]
|
|
(output port clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Path Group: sys_clk
|
|
Path Type: Max at Slow Process Corner
|
|
Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns)
|
|
Data Path Delay: 15.364ns (logic 6.875ns (44.747%) route 8.489ns (55.253%))
|
|
Logic Levels: 14 (CARRY4=6 LUT3=1 LUT4=2 LUT5=1 LUT6=3 OBUFT=1)
|
|
Output Delay: 0.300ns
|
|
Clock Path Skew: -3.955ns (DCD - SCD + CPR)
|
|
Destination Clock Delay (DCD): -5.674ns = ( 14.326 - 20.000 )
|
|
Source Clock Delay (SCD): -2.321ns
|
|
Clock Pessimism Removal (CPR): -0.601ns
|
|
Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Discrete Jitter (DJ): 0.122ns
|
|
Phase Error (PE): 0.000ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock sys_clk rise edge) 0.000 0.000 r
|
|
clock source latency -6.275 -6.275
|
|
propagated clock network latency
|
|
3.955 -2.321
|
|
SLICE_X7Y62 FDCE 0.000 -2.321 r u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[3]/C
|
|
SLICE_X7Y62 FDCE (Prop_fdce_C_Q) 0.456 -1.865 f u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[3]/Q
|
|
net (fo=54, routed) 0.726 -1.139 u_axi_ram/u_axi_sram_sp/len[3]
|
|
SLICE_X7Y61 f u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6/I3
|
|
SLICE_X7Y61 LUT4 (Prop_lut4_I3_O) 0.124 -1.015 r u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6/O
|
|
net (fo=4, routed) 0.946 -0.068 u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6_n_0
|
|
SLICE_X7Y58 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_11/I1
|
|
SLICE_X7Y58 LUT5 (Prop_lut5_I1_O) 0.124 0.056 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_11/O
|
|
net (fo=2, routed) 0.619 0.675 u_axi_ram/u_axi_sram_sp/state_d2[7]
|
|
SLICE_X6Y59 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_15/I5
|
|
SLICE_X6Y59 LUT6 (Prop_lut6_I5_O) 0.124 0.799 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_15/O
|
|
net (fo=1, routed) 0.000 0.799 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_15_n_0
|
|
SLICE_X6Y59 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9/S[3]
|
|
SLICE_X6Y59 CARRY4 (Prop_carry4_S[3]_CO[3])
|
|
0.376 1.175 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9/CO[3]
|
|
net (fo=1, routed) 0.000 1.175 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9_n_0
|
|
SLICE_X6Y60 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/CI
|
|
SLICE_X6Y60 CARRY4 (Prop_carry4_CI_CO[3])
|
|
0.117 1.292 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/CO[3]
|
|
net (fo=1, routed) 0.000 1.292 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10_n_0
|
|
SLICE_X6Y61 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CI
|
|
SLICE_X6Y61 CARRY4 (Prop_carry4_CI_CO[3])
|
|
0.117 1.409 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CO[3]
|
|
net (fo=1, routed) 0.000 1.409 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9_n_0
|
|
SLICE_X6Y62 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/CI
|
|
SLICE_X6Y62 CARRY4 (Prop_carry4_CI_O[2])
|
|
0.239 1.648 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/O[2]
|
|
net (fo=3, routed) 0.929 2.576 u_axi_ram/u_axi_sram_sp/upper_wrap_boundary[20]
|
|
SLICE_X5Y65 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_7/I2
|
|
SLICE_X5Y65 LUT4 (Prop_lut4_I2_O) 0.301 2.877 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_7/O
|
|
net (fo=1, routed) 0.000 2.877 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_7_n_0
|
|
SLICE_X5Y65 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1/S[1]
|
|
SLICE_X5Y65 CARRY4 (Prop_carry4_S[1]_CO[3])
|
|
0.550 3.427 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1/CO[3]
|
|
net (fo=1, routed) 0.000 3.427 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_n_0
|
|
SLICE_X5Y66 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2/CI
|
|
SLICE_X5Y66 CARRY4 (Prop_carry4_CI_CO[2])
|
|
0.228 3.655 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2/CO[2]
|
|
net (fo=22, routed) 0.735 4.390 u_axi_ram/u_axi_sram_sp/req_addr_d1
|
|
SLICE_X5Y68 r u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/I0
|
|
SLICE_X5Y68 LUT6 (Prop_lut6_I0_O) 0.313 4.703 r u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/O
|
|
net (fo=2, routed) 0.550 5.253 u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7_n_0
|
|
SLICE_X4Y68 r u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/I1
|
|
SLICE_X4Y68 LUT6 (Prop_lut6_I1_O) 0.124 5.377 r u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/O
|
|
net (fo=80, routed) 0.770 6.147 u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/soc_sram_addr[0]
|
|
SLICE_X1Y63 r u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/ext_ram_data_IOBUF[31]_inst_i_2/I2
|
|
SLICE_X1Y63 LUT3 (Prop_lut3_I2_O) 0.124 6.271 f u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/ext_ram_data_IOBUF[31]_inst_i_2/O
|
|
net (fo=32, routed) 3.214 9.485 ext_ram_data_IOBUF[24]_inst/T
|
|
AD17 f ext_ram_data_IOBUF[24]_inst/OBUFT/T
|
|
AD17 OBUFT (TriStatE_obuft_T_O)
|
|
3.558 13.043 r ext_ram_data_IOBUF[24]_inst/OBUFT/O
|
|
net (fo=1, unset) 0.000 13.043 ext_ram_data[24]
|
|
AD17 r ext_ram_data[24] (INOUT)
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock sys_clk rise edge) 20.000 20.000 r
|
|
clock source latency -5.674 14.326
|
|
propagated clock network latency
|
|
0.000 14.326
|
|
clock pessimism -0.601 13.725
|
|
clock uncertainty -0.071 13.654
|
|
output delay -0.300 13.354
|
|
-------------------------------------------------------------------
|
|
required time 13.354
|
|
arrival time -13.043
|
|
-------------------------------------------------------------------
|
|
slack 0.311
|
|
|
|
Slack (MET) : 0.311ns (required time - arrival time)
|
|
Source: u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[3]/C
|
|
(rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Destination: ext_ram_data[24]
|
|
(output port clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Path Group: sys_clk
|
|
Path Type: Max at Slow Process Corner
|
|
Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns)
|
|
Data Path Delay: 15.364ns (logic 6.875ns (44.747%) route 8.489ns (55.253%))
|
|
Logic Levels: 14 (CARRY4=6 LUT3=1 LUT4=2 LUT5=1 LUT6=3 OBUFT=1)
|
|
Output Delay: 0.300ns
|
|
Clock Path Skew: -3.955ns (DCD - SCD + CPR)
|
|
Destination Clock Delay (DCD): -5.674ns = ( 14.326 - 20.000 )
|
|
Source Clock Delay (SCD): -2.321ns
|
|
Clock Pessimism Removal (CPR): -0.601ns
|
|
Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Discrete Jitter (DJ): 0.122ns
|
|
Phase Error (PE): 0.000ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock sys_clk rise edge) 0.000 0.000 r
|
|
clock source latency -6.275 -6.275
|
|
propagated clock network latency
|
|
3.955 -2.321
|
|
SLICE_X7Y62 FDCE 0.000 -2.321 r u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[3]/C
|
|
SLICE_X7Y62 FDCE (Prop_fdce_C_Q) 0.456 -1.865 f u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[3]/Q
|
|
net (fo=54, routed) 0.726 -1.139 u_axi_ram/u_axi_sram_sp/len[3]
|
|
SLICE_X7Y61 f u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6/I3
|
|
SLICE_X7Y61 LUT4 (Prop_lut4_I3_O) 0.124 -1.015 r u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6/O
|
|
net (fo=4, routed) 0.946 -0.068 u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6_n_0
|
|
SLICE_X7Y58 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_11/I1
|
|
SLICE_X7Y58 LUT5 (Prop_lut5_I1_O) 0.124 0.056 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_11/O
|
|
net (fo=2, routed) 0.619 0.675 u_axi_ram/u_axi_sram_sp/state_d2[7]
|
|
SLICE_X6Y59 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_15/I5
|
|
SLICE_X6Y59 LUT6 (Prop_lut6_I5_O) 0.124 0.799 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_15/O
|
|
net (fo=1, routed) 0.000 0.799 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_15_n_0
|
|
SLICE_X6Y59 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9/S[3]
|
|
SLICE_X6Y59 CARRY4 (Prop_carry4_S[3]_CO[3])
|
|
0.376 1.175 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9/CO[3]
|
|
net (fo=1, routed) 0.000 1.175 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9_n_0
|
|
SLICE_X6Y60 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/CI
|
|
SLICE_X6Y60 CARRY4 (Prop_carry4_CI_CO[3])
|
|
0.117 1.292 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/CO[3]
|
|
net (fo=1, routed) 0.000 1.292 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10_n_0
|
|
SLICE_X6Y61 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CI
|
|
SLICE_X6Y61 CARRY4 (Prop_carry4_CI_CO[3])
|
|
0.117 1.409 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CO[3]
|
|
net (fo=1, routed) 0.000 1.409 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9_n_0
|
|
SLICE_X6Y62 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/CI
|
|
SLICE_X6Y62 CARRY4 (Prop_carry4_CI_O[2])
|
|
0.239 1.648 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/O[2]
|
|
net (fo=3, routed) 0.929 2.576 u_axi_ram/u_axi_sram_sp/upper_wrap_boundary[20]
|
|
SLICE_X5Y65 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_7/I2
|
|
SLICE_X5Y65 LUT4 (Prop_lut4_I2_O) 0.301 2.877 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_7/O
|
|
net (fo=1, routed) 0.000 2.877 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_7_n_0
|
|
SLICE_X5Y65 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1/S[1]
|
|
SLICE_X5Y65 CARRY4 (Prop_carry4_S[1]_CO[3])
|
|
0.550 3.427 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1/CO[3]
|
|
net (fo=1, routed) 0.000 3.427 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_n_0
|
|
SLICE_X5Y66 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2/CI
|
|
SLICE_X5Y66 CARRY4 (Prop_carry4_CI_CO[2])
|
|
0.228 3.655 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2/CO[2]
|
|
net (fo=22, routed) 0.735 4.390 u_axi_ram/u_axi_sram_sp/req_addr_d1
|
|
SLICE_X5Y68 r u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/I0
|
|
SLICE_X5Y68 LUT6 (Prop_lut6_I0_O) 0.313 4.703 r u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/O
|
|
net (fo=2, routed) 0.550 5.253 u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7_n_0
|
|
SLICE_X4Y68 r u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/I1
|
|
SLICE_X4Y68 LUT6 (Prop_lut6_I1_O) 0.124 5.377 r u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/O
|
|
net (fo=80, routed) 0.770 6.147 u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/soc_sram_addr[0]
|
|
SLICE_X1Y63 r u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/ext_ram_data_IOBUF[31]_inst_i_2/I2
|
|
SLICE_X1Y63 LUT3 (Prop_lut3_I2_O) 0.124 6.271 f u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/ext_ram_data_IOBUF[31]_inst_i_2/O
|
|
net (fo=32, routed) 3.214 9.485 ext_ram_data_IOBUF[24]_inst/T
|
|
AD17 f ext_ram_data_IOBUF[24]_inst/OBUFT/T
|
|
AD17 OBUFT (TriStatE_obuft_T_O)
|
|
3.558 13.043 r ext_ram_data_IOBUF[24]_inst/OBUFT/O
|
|
net (fo=1, unset) 0.000 13.043 ext_ram_data[24]
|
|
AD17 r ext_ram_data[24] (INOUT)
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock sys_clk rise edge) 20.000 20.000 r
|
|
clock source latency -5.674 14.326
|
|
propagated clock network latency
|
|
0.000 14.326
|
|
clock pessimism -0.601 13.725
|
|
clock uncertainty -0.071 13.654
|
|
output delay -0.300 13.354
|
|
-------------------------------------------------------------------
|
|
required time 13.354
|
|
arrival time -13.043
|
|
-------------------------------------------------------------------
|
|
slack 0.311
|
|
|
|
Slack (MET) : 0.311ns (required time - arrival time)
|
|
Source: u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[3]/C
|
|
(rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Destination: ext_ram_data[24]
|
|
(output port clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Path Group: sys_clk
|
|
Path Type: Max at Slow Process Corner
|
|
Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns)
|
|
Data Path Delay: 15.364ns (logic 6.875ns (44.747%) route 8.489ns (55.253%))
|
|
Logic Levels: 14 (CARRY4=6 LUT3=1 LUT4=2 LUT5=1 LUT6=3 OBUFT=1)
|
|
Output Delay: 0.300ns
|
|
Clock Path Skew: -3.955ns (DCD - SCD + CPR)
|
|
Destination Clock Delay (DCD): -5.674ns = ( 14.326 - 20.000 )
|
|
Source Clock Delay (SCD): -2.321ns
|
|
Clock Pessimism Removal (CPR): -0.601ns
|
|
Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Discrete Jitter (DJ): 0.122ns
|
|
Phase Error (PE): 0.000ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock sys_clk rise edge) 0.000 0.000 r
|
|
clock source latency -6.275 -6.275
|
|
propagated clock network latency
|
|
3.955 -2.321
|
|
SLICE_X7Y62 FDCE 0.000 -2.321 r u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[3]/C
|
|
SLICE_X7Y62 FDCE (Prop_fdce_C_Q) 0.456 -1.865 f u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[3]/Q
|
|
net (fo=54, routed) 0.726 -1.139 u_axi_ram/u_axi_sram_sp/len[3]
|
|
SLICE_X7Y61 f u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6/I3
|
|
SLICE_X7Y61 LUT4 (Prop_lut4_I3_O) 0.124 -1.015 r u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6/O
|
|
net (fo=4, routed) 0.946 -0.068 u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6_n_0
|
|
SLICE_X7Y58 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_11/I1
|
|
SLICE_X7Y58 LUT5 (Prop_lut5_I1_O) 0.124 0.056 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_11/O
|
|
net (fo=2, routed) 0.619 0.675 u_axi_ram/u_axi_sram_sp/state_d2[7]
|
|
SLICE_X6Y59 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_15/I5
|
|
SLICE_X6Y59 LUT6 (Prop_lut6_I5_O) 0.124 0.799 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_15/O
|
|
net (fo=1, routed) 0.000 0.799 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_15_n_0
|
|
SLICE_X6Y59 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9/S[3]
|
|
SLICE_X6Y59 CARRY4 (Prop_carry4_S[3]_CO[3])
|
|
0.376 1.175 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9/CO[3]
|
|
net (fo=1, routed) 0.000 1.175 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9_n_0
|
|
SLICE_X6Y60 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/CI
|
|
SLICE_X6Y60 CARRY4 (Prop_carry4_CI_CO[3])
|
|
0.117 1.292 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/CO[3]
|
|
net (fo=1, routed) 0.000 1.292 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10_n_0
|
|
SLICE_X6Y61 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CI
|
|
SLICE_X6Y61 CARRY4 (Prop_carry4_CI_CO[3])
|
|
0.117 1.409 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CO[3]
|
|
net (fo=1, routed) 0.000 1.409 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9_n_0
|
|
SLICE_X6Y62 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/CI
|
|
SLICE_X6Y62 CARRY4 (Prop_carry4_CI_O[2])
|
|
0.239 1.648 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/O[2]
|
|
net (fo=3, routed) 0.929 2.576 u_axi_ram/u_axi_sram_sp/upper_wrap_boundary[20]
|
|
SLICE_X5Y65 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_7/I2
|
|
SLICE_X5Y65 LUT4 (Prop_lut4_I2_O) 0.301 2.877 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_7/O
|
|
net (fo=1, routed) 0.000 2.877 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_7_n_0
|
|
SLICE_X5Y65 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1/S[1]
|
|
SLICE_X5Y65 CARRY4 (Prop_carry4_S[1]_CO[3])
|
|
0.550 3.427 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1/CO[3]
|
|
net (fo=1, routed) 0.000 3.427 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_n_0
|
|
SLICE_X5Y66 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2/CI
|
|
SLICE_X5Y66 CARRY4 (Prop_carry4_CI_CO[2])
|
|
0.228 3.655 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2/CO[2]
|
|
net (fo=22, routed) 0.735 4.390 u_axi_ram/u_axi_sram_sp/req_addr_d1
|
|
SLICE_X5Y68 r u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/I0
|
|
SLICE_X5Y68 LUT6 (Prop_lut6_I0_O) 0.313 4.703 r u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/O
|
|
net (fo=2, routed) 0.550 5.253 u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7_n_0
|
|
SLICE_X4Y68 r u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/I1
|
|
SLICE_X4Y68 LUT6 (Prop_lut6_I1_O) 0.124 5.377 r u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/O
|
|
net (fo=80, routed) 0.770 6.147 u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/soc_sram_addr[0]
|
|
SLICE_X1Y63 r u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/ext_ram_data_IOBUF[31]_inst_i_2/I2
|
|
SLICE_X1Y63 LUT3 (Prop_lut3_I2_O) 0.124 6.271 f u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/ext_ram_data_IOBUF[31]_inst_i_2/O
|
|
net (fo=32, routed) 3.214 9.485 ext_ram_data_IOBUF[24]_inst/T
|
|
AD17 f ext_ram_data_IOBUF[24]_inst/OBUFT/T
|
|
AD17 OBUFT (TriStatE_obuft_T_O)
|
|
3.558 13.043 r ext_ram_data_IOBUF[24]_inst/OBUFT/O
|
|
net (fo=1, unset) 0.000 13.043 ext_ram_data[24]
|
|
AD17 r ext_ram_data[24] (INOUT)
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock sys_clk rise edge) 20.000 20.000 r
|
|
clock source latency -5.674 14.326
|
|
propagated clock network latency
|
|
0.000 14.326
|
|
clock pessimism -0.601 13.725
|
|
clock uncertainty -0.071 13.654
|
|
output delay -0.300 13.354
|
|
-------------------------------------------------------------------
|
|
required time 13.354
|
|
arrival time -13.043
|
|
-------------------------------------------------------------------
|
|
slack 0.311
|
|
|
|
Slack (MET) : 0.324ns (required time - arrival time)
|
|
Source: u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[3]/C
|
|
(rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Destination: base_ram_be_n[1]
|
|
(output port clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Path Group: sys_clk
|
|
Path Type: Max at Slow Process Corner
|
|
Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns)
|
|
Data Path Delay: 15.350ns (logic 6.848ns (44.608%) route 8.503ns (55.392%))
|
|
Logic Levels: 14 (CARRY4=6 LUT4=2 LUT5=1 LUT6=4 OBUF=1)
|
|
Output Delay: 0.300ns
|
|
Clock Path Skew: -3.955ns (DCD - SCD + CPR)
|
|
Destination Clock Delay (DCD): -5.674ns = ( 14.326 - 20.000 )
|
|
Source Clock Delay (SCD): -2.321ns
|
|
Clock Pessimism Removal (CPR): -0.601ns
|
|
Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Discrete Jitter (DJ): 0.122ns
|
|
Phase Error (PE): 0.000ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock sys_clk rise edge) 0.000 0.000 r
|
|
clock source latency -6.275 -6.275
|
|
propagated clock network latency
|
|
3.955 -2.321
|
|
SLICE_X7Y62 FDCE 0.000 -2.321 r u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[3]/C
|
|
SLICE_X7Y62 FDCE (Prop_fdce_C_Q) 0.456 -1.865 f u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[3]/Q
|
|
net (fo=54, routed) 0.726 -1.139 u_axi_ram/u_axi_sram_sp/len[3]
|
|
SLICE_X7Y61 f u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6/I3
|
|
SLICE_X7Y61 LUT4 (Prop_lut4_I3_O) 0.124 -1.015 r u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6/O
|
|
net (fo=4, routed) 0.946 -0.068 u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6_n_0
|
|
SLICE_X7Y58 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_11/I1
|
|
SLICE_X7Y58 LUT5 (Prop_lut5_I1_O) 0.124 0.056 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_11/O
|
|
net (fo=2, routed) 0.619 0.675 u_axi_ram/u_axi_sram_sp/state_d2[7]
|
|
SLICE_X6Y59 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_15/I5
|
|
SLICE_X6Y59 LUT6 (Prop_lut6_I5_O) 0.124 0.799 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_15/O
|
|
net (fo=1, routed) 0.000 0.799 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_15_n_0
|
|
SLICE_X6Y59 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9/S[3]
|
|
SLICE_X6Y59 CARRY4 (Prop_carry4_S[3]_CO[3])
|
|
0.376 1.175 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9/CO[3]
|
|
net (fo=1, routed) 0.000 1.175 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9_n_0
|
|
SLICE_X6Y60 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/CI
|
|
SLICE_X6Y60 CARRY4 (Prop_carry4_CI_CO[3])
|
|
0.117 1.292 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/CO[3]
|
|
net (fo=1, routed) 0.000 1.292 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10_n_0
|
|
SLICE_X6Y61 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CI
|
|
SLICE_X6Y61 CARRY4 (Prop_carry4_CI_CO[3])
|
|
0.117 1.409 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CO[3]
|
|
net (fo=1, routed) 0.000 1.409 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9_n_0
|
|
SLICE_X6Y62 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/CI
|
|
SLICE_X6Y62 CARRY4 (Prop_carry4_CI_O[2])
|
|
0.239 1.648 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/O[2]
|
|
net (fo=3, routed) 0.929 2.576 u_axi_ram/u_axi_sram_sp/upper_wrap_boundary[20]
|
|
SLICE_X5Y65 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_7/I2
|
|
SLICE_X5Y65 LUT4 (Prop_lut4_I2_O) 0.301 2.877 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_7/O
|
|
net (fo=1, routed) 0.000 2.877 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_7_n_0
|
|
SLICE_X5Y65 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1/S[1]
|
|
SLICE_X5Y65 CARRY4 (Prop_carry4_S[1]_CO[3])
|
|
0.550 3.427 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1/CO[3]
|
|
net (fo=1, routed) 0.000 3.427 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_n_0
|
|
SLICE_X5Y66 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2/CI
|
|
SLICE_X5Y66 CARRY4 (Prop_carry4_CI_CO[2])
|
|
0.228 3.655 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2/CO[2]
|
|
net (fo=22, routed) 0.735 4.390 u_axi_ram/u_axi_sram_sp/req_addr_d1
|
|
SLICE_X5Y68 r u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/I0
|
|
SLICE_X5Y68 LUT6 (Prop_lut6_I0_O) 0.313 4.703 r u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/O
|
|
net (fo=2, routed) 0.550 5.253 u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7_n_0
|
|
SLICE_X4Y68 r u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/I1
|
|
SLICE_X4Y68 LUT6 (Prop_lut6_I1_O) 0.124 5.377 r u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/O
|
|
net (fo=80, routed) 1.095 6.472 u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/soc_sram_addr[0]
|
|
SLICE_X0Y77 r u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/base_ram_be_n_OBUF[1]_inst_i_1/I5
|
|
SLICE_X0Y77 LUT6 (Prop_lut6_I5_O) 0.124 6.596 r u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/base_ram_be_n_OBUF[1]_inst_i_1/O
|
|
net (fo=1, routed) 2.903 9.499 base_ram_be_n_OBUF[1]
|
|
L22 r base_ram_be_n_OBUF[1]_inst/I
|
|
L22 OBUF (Prop_obuf_I_O) 3.531 13.030 r base_ram_be_n_OBUF[1]_inst/O
|
|
net (fo=0) 0.000 13.030 base_ram_be_n[1]
|
|
L22 r base_ram_be_n[1] (OUT)
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock sys_clk rise edge) 20.000 20.000 r
|
|
clock source latency -5.674 14.326
|
|
propagated clock network latency
|
|
0.000 14.326
|
|
clock pessimism -0.601 13.725
|
|
clock uncertainty -0.071 13.654
|
|
output delay -0.300 13.354
|
|
-------------------------------------------------------------------
|
|
required time 13.354
|
|
arrival time -13.030
|
|
-------------------------------------------------------------------
|
|
slack 0.324
|
|
|
|
Slack (MET) : 0.324ns (required time - arrival time)
|
|
Source: u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[3]/C
|
|
(rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Destination: base_ram_be_n[1]
|
|
(output port clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Path Group: sys_clk
|
|
Path Type: Max at Slow Process Corner
|
|
Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns)
|
|
Data Path Delay: 15.350ns (logic 6.848ns (44.608%) route 8.503ns (55.392%))
|
|
Logic Levels: 14 (CARRY4=6 LUT4=2 LUT5=1 LUT6=4 OBUF=1)
|
|
Output Delay: 0.300ns
|
|
Clock Path Skew: -3.955ns (DCD - SCD + CPR)
|
|
Destination Clock Delay (DCD): -5.674ns = ( 14.326 - 20.000 )
|
|
Source Clock Delay (SCD): -2.321ns
|
|
Clock Pessimism Removal (CPR): -0.601ns
|
|
Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Discrete Jitter (DJ): 0.122ns
|
|
Phase Error (PE): 0.000ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock sys_clk rise edge) 0.000 0.000 r
|
|
clock source latency -6.275 -6.275
|
|
propagated clock network latency
|
|
3.955 -2.321
|
|
SLICE_X7Y62 FDCE 0.000 -2.321 r u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[3]/C
|
|
SLICE_X7Y62 FDCE (Prop_fdce_C_Q) 0.456 -1.865 f u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[3]/Q
|
|
net (fo=54, routed) 0.726 -1.139 u_axi_ram/u_axi_sram_sp/len[3]
|
|
SLICE_X7Y61 f u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6/I3
|
|
SLICE_X7Y61 LUT4 (Prop_lut4_I3_O) 0.124 -1.015 r u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6/O
|
|
net (fo=4, routed) 0.946 -0.068 u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6_n_0
|
|
SLICE_X7Y58 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_11/I1
|
|
SLICE_X7Y58 LUT5 (Prop_lut5_I1_O) 0.124 0.056 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_11/O
|
|
net (fo=2, routed) 0.619 0.675 u_axi_ram/u_axi_sram_sp/state_d2[7]
|
|
SLICE_X6Y59 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_15/I5
|
|
SLICE_X6Y59 LUT6 (Prop_lut6_I5_O) 0.124 0.799 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_15/O
|
|
net (fo=1, routed) 0.000 0.799 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_15_n_0
|
|
SLICE_X6Y59 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9/S[3]
|
|
SLICE_X6Y59 CARRY4 (Prop_carry4_S[3]_CO[3])
|
|
0.376 1.175 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9/CO[3]
|
|
net (fo=1, routed) 0.000 1.175 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9_n_0
|
|
SLICE_X6Y60 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/CI
|
|
SLICE_X6Y60 CARRY4 (Prop_carry4_CI_CO[3])
|
|
0.117 1.292 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/CO[3]
|
|
net (fo=1, routed) 0.000 1.292 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10_n_0
|
|
SLICE_X6Y61 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CI
|
|
SLICE_X6Y61 CARRY4 (Prop_carry4_CI_CO[3])
|
|
0.117 1.409 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CO[3]
|
|
net (fo=1, routed) 0.000 1.409 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9_n_0
|
|
SLICE_X6Y62 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/CI
|
|
SLICE_X6Y62 CARRY4 (Prop_carry4_CI_O[2])
|
|
0.239 1.648 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/O[2]
|
|
net (fo=3, routed) 0.929 2.576 u_axi_ram/u_axi_sram_sp/upper_wrap_boundary[20]
|
|
SLICE_X5Y65 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_7/I2
|
|
SLICE_X5Y65 LUT4 (Prop_lut4_I2_O) 0.301 2.877 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_7/O
|
|
net (fo=1, routed) 0.000 2.877 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_7_n_0
|
|
SLICE_X5Y65 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1/S[1]
|
|
SLICE_X5Y65 CARRY4 (Prop_carry4_S[1]_CO[3])
|
|
0.550 3.427 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1/CO[3]
|
|
net (fo=1, routed) 0.000 3.427 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_n_0
|
|
SLICE_X5Y66 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2/CI
|
|
SLICE_X5Y66 CARRY4 (Prop_carry4_CI_CO[2])
|
|
0.228 3.655 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2/CO[2]
|
|
net (fo=22, routed) 0.735 4.390 u_axi_ram/u_axi_sram_sp/req_addr_d1
|
|
SLICE_X5Y68 r u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/I0
|
|
SLICE_X5Y68 LUT6 (Prop_lut6_I0_O) 0.313 4.703 r u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/O
|
|
net (fo=2, routed) 0.550 5.253 u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7_n_0
|
|
SLICE_X4Y68 r u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/I1
|
|
SLICE_X4Y68 LUT6 (Prop_lut6_I1_O) 0.124 5.377 r u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/O
|
|
net (fo=80, routed) 1.095 6.472 u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/soc_sram_addr[0]
|
|
SLICE_X0Y77 r u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/base_ram_be_n_OBUF[1]_inst_i_1/I5
|
|
SLICE_X0Y77 LUT6 (Prop_lut6_I5_O) 0.124 6.596 r u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/base_ram_be_n_OBUF[1]_inst_i_1/O
|
|
net (fo=1, routed) 2.903 9.499 base_ram_be_n_OBUF[1]
|
|
L22 r base_ram_be_n_OBUF[1]_inst/I
|
|
L22 OBUF (Prop_obuf_I_O) 3.531 13.030 r base_ram_be_n_OBUF[1]_inst/O
|
|
net (fo=0) 0.000 13.030 base_ram_be_n[1]
|
|
L22 r base_ram_be_n[1] (OUT)
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock sys_clk rise edge) 20.000 20.000 r
|
|
clock source latency -5.674 14.326
|
|
propagated clock network latency
|
|
0.000 14.326
|
|
clock pessimism -0.601 13.725
|
|
clock uncertainty -0.071 13.654
|
|
output delay -0.300 13.354
|
|
-------------------------------------------------------------------
|
|
required time 13.354
|
|
arrival time -13.030
|
|
-------------------------------------------------------------------
|
|
slack 0.324
|
|
|
|
Slack (MET) : 0.324ns (required time - arrival time)
|
|
Source: u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[3]/C
|
|
(rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Destination: base_ram_be_n[1]
|
|
(output port clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Path Group: sys_clk
|
|
Path Type: Max at Slow Process Corner
|
|
Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns)
|
|
Data Path Delay: 15.350ns (logic 6.848ns (44.608%) route 8.503ns (55.392%))
|
|
Logic Levels: 14 (CARRY4=6 LUT4=2 LUT5=1 LUT6=4 OBUF=1)
|
|
Output Delay: 0.300ns
|
|
Clock Path Skew: -3.955ns (DCD - SCD + CPR)
|
|
Destination Clock Delay (DCD): -5.674ns = ( 14.326 - 20.000 )
|
|
Source Clock Delay (SCD): -2.321ns
|
|
Clock Pessimism Removal (CPR): -0.601ns
|
|
Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Discrete Jitter (DJ): 0.122ns
|
|
Phase Error (PE): 0.000ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock sys_clk rise edge) 0.000 0.000 r
|
|
clock source latency -6.275 -6.275
|
|
propagated clock network latency
|
|
3.955 -2.321
|
|
SLICE_X7Y62 FDCE 0.000 -2.321 r u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[3]/C
|
|
SLICE_X7Y62 FDCE (Prop_fdce_C_Q) 0.456 -1.865 f u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[3]/Q
|
|
net (fo=54, routed) 0.726 -1.139 u_axi_ram/u_axi_sram_sp/len[3]
|
|
SLICE_X7Y61 f u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6/I3
|
|
SLICE_X7Y61 LUT4 (Prop_lut4_I3_O) 0.124 -1.015 r u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6/O
|
|
net (fo=4, routed) 0.946 -0.068 u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6_n_0
|
|
SLICE_X7Y58 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_11/I1
|
|
SLICE_X7Y58 LUT5 (Prop_lut5_I1_O) 0.124 0.056 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_11/O
|
|
net (fo=2, routed) 0.619 0.675 u_axi_ram/u_axi_sram_sp/state_d2[7]
|
|
SLICE_X6Y59 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_15/I5
|
|
SLICE_X6Y59 LUT6 (Prop_lut6_I5_O) 0.124 0.799 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_15/O
|
|
net (fo=1, routed) 0.000 0.799 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_15_n_0
|
|
SLICE_X6Y59 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9/S[3]
|
|
SLICE_X6Y59 CARRY4 (Prop_carry4_S[3]_CO[3])
|
|
0.376 1.175 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9/CO[3]
|
|
net (fo=1, routed) 0.000 1.175 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9_n_0
|
|
SLICE_X6Y60 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/CI
|
|
SLICE_X6Y60 CARRY4 (Prop_carry4_CI_CO[3])
|
|
0.117 1.292 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/CO[3]
|
|
net (fo=1, routed) 0.000 1.292 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10_n_0
|
|
SLICE_X6Y61 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CI
|
|
SLICE_X6Y61 CARRY4 (Prop_carry4_CI_CO[3])
|
|
0.117 1.409 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CO[3]
|
|
net (fo=1, routed) 0.000 1.409 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9_n_0
|
|
SLICE_X6Y62 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/CI
|
|
SLICE_X6Y62 CARRY4 (Prop_carry4_CI_O[2])
|
|
0.239 1.648 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/O[2]
|
|
net (fo=3, routed) 0.929 2.576 u_axi_ram/u_axi_sram_sp/upper_wrap_boundary[20]
|
|
SLICE_X5Y65 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_7/I2
|
|
SLICE_X5Y65 LUT4 (Prop_lut4_I2_O) 0.301 2.877 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_7/O
|
|
net (fo=1, routed) 0.000 2.877 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_7_n_0
|
|
SLICE_X5Y65 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1/S[1]
|
|
SLICE_X5Y65 CARRY4 (Prop_carry4_S[1]_CO[3])
|
|
0.550 3.427 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1/CO[3]
|
|
net (fo=1, routed) 0.000 3.427 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_n_0
|
|
SLICE_X5Y66 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2/CI
|
|
SLICE_X5Y66 CARRY4 (Prop_carry4_CI_CO[2])
|
|
0.228 3.655 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2/CO[2]
|
|
net (fo=22, routed) 0.735 4.390 u_axi_ram/u_axi_sram_sp/req_addr_d1
|
|
SLICE_X5Y68 r u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/I0
|
|
SLICE_X5Y68 LUT6 (Prop_lut6_I0_O) 0.313 4.703 r u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/O
|
|
net (fo=2, routed) 0.550 5.253 u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7_n_0
|
|
SLICE_X4Y68 r u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/I1
|
|
SLICE_X4Y68 LUT6 (Prop_lut6_I1_O) 0.124 5.377 r u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/O
|
|
net (fo=80, routed) 1.095 6.472 u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/soc_sram_addr[0]
|
|
SLICE_X0Y77 r u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/base_ram_be_n_OBUF[1]_inst_i_1/I5
|
|
SLICE_X0Y77 LUT6 (Prop_lut6_I5_O) 0.124 6.596 r u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/base_ram_be_n_OBUF[1]_inst_i_1/O
|
|
net (fo=1, routed) 2.903 9.499 base_ram_be_n_OBUF[1]
|
|
L22 r base_ram_be_n_OBUF[1]_inst/I
|
|
L22 OBUF (Prop_obuf_I_O) 3.531 13.030 r base_ram_be_n_OBUF[1]_inst/O
|
|
net (fo=0) 0.000 13.030 base_ram_be_n[1]
|
|
L22 r base_ram_be_n[1] (OUT)
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock sys_clk rise edge) 20.000 20.000 r
|
|
clock source latency -5.674 14.326
|
|
propagated clock network latency
|
|
0.000 14.326
|
|
clock pessimism -0.601 13.725
|
|
clock uncertainty -0.071 13.654
|
|
output delay -0.300 13.354
|
|
-------------------------------------------------------------------
|
|
required time 13.354
|
|
arrival time -13.030
|
|
-------------------------------------------------------------------
|
|
slack 0.324
|
|
|
|
Slack (MET) : 0.324ns (required time - arrival time)
|
|
Source: u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[3]/C
|
|
(rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Destination: base_ram_be_n[1]
|
|
(output port clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Path Group: sys_clk
|
|
Path Type: Max at Slow Process Corner
|
|
Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns)
|
|
Data Path Delay: 15.350ns (logic 6.848ns (44.608%) route 8.503ns (55.392%))
|
|
Logic Levels: 14 (CARRY4=6 LUT4=2 LUT5=1 LUT6=4 OBUF=1)
|
|
Output Delay: 0.300ns
|
|
Clock Path Skew: -3.955ns (DCD - SCD + CPR)
|
|
Destination Clock Delay (DCD): -5.674ns = ( 14.326 - 20.000 )
|
|
Source Clock Delay (SCD): -2.321ns
|
|
Clock Pessimism Removal (CPR): -0.601ns
|
|
Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Discrete Jitter (DJ): 0.122ns
|
|
Phase Error (PE): 0.000ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock sys_clk rise edge) 0.000 0.000 r
|
|
clock source latency -6.275 -6.275
|
|
propagated clock network latency
|
|
3.955 -2.321
|
|
SLICE_X7Y62 FDCE 0.000 -2.321 r u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[3]/C
|
|
SLICE_X7Y62 FDCE (Prop_fdce_C_Q) 0.456 -1.865 f u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[3]/Q
|
|
net (fo=54, routed) 0.726 -1.139 u_axi_ram/u_axi_sram_sp/len[3]
|
|
SLICE_X7Y61 f u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6/I3
|
|
SLICE_X7Y61 LUT4 (Prop_lut4_I3_O) 0.124 -1.015 r u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6/O
|
|
net (fo=4, routed) 0.946 -0.068 u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6_n_0
|
|
SLICE_X7Y58 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_11/I1
|
|
SLICE_X7Y58 LUT5 (Prop_lut5_I1_O) 0.124 0.056 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_11/O
|
|
net (fo=2, routed) 0.619 0.675 u_axi_ram/u_axi_sram_sp/state_d2[7]
|
|
SLICE_X6Y59 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_15/I5
|
|
SLICE_X6Y59 LUT6 (Prop_lut6_I5_O) 0.124 0.799 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_15/O
|
|
net (fo=1, routed) 0.000 0.799 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_15_n_0
|
|
SLICE_X6Y59 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9/S[3]
|
|
SLICE_X6Y59 CARRY4 (Prop_carry4_S[3]_CO[3])
|
|
0.376 1.175 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9/CO[3]
|
|
net (fo=1, routed) 0.000 1.175 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9_n_0
|
|
SLICE_X6Y60 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/CI
|
|
SLICE_X6Y60 CARRY4 (Prop_carry4_CI_CO[3])
|
|
0.117 1.292 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/CO[3]
|
|
net (fo=1, routed) 0.000 1.292 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10_n_0
|
|
SLICE_X6Y61 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CI
|
|
SLICE_X6Y61 CARRY4 (Prop_carry4_CI_CO[3])
|
|
0.117 1.409 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CO[3]
|
|
net (fo=1, routed) 0.000 1.409 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9_n_0
|
|
SLICE_X6Y62 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/CI
|
|
SLICE_X6Y62 CARRY4 (Prop_carry4_CI_O[2])
|
|
0.239 1.648 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/O[2]
|
|
net (fo=3, routed) 0.929 2.576 u_axi_ram/u_axi_sram_sp/upper_wrap_boundary[20]
|
|
SLICE_X5Y65 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_7/I2
|
|
SLICE_X5Y65 LUT4 (Prop_lut4_I2_O) 0.301 2.877 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_7/O
|
|
net (fo=1, routed) 0.000 2.877 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_7_n_0
|
|
SLICE_X5Y65 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1/S[1]
|
|
SLICE_X5Y65 CARRY4 (Prop_carry4_S[1]_CO[3])
|
|
0.550 3.427 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1/CO[3]
|
|
net (fo=1, routed) 0.000 3.427 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_n_0
|
|
SLICE_X5Y66 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2/CI
|
|
SLICE_X5Y66 CARRY4 (Prop_carry4_CI_CO[2])
|
|
0.228 3.655 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2/CO[2]
|
|
net (fo=22, routed) 0.735 4.390 u_axi_ram/u_axi_sram_sp/req_addr_d1
|
|
SLICE_X5Y68 r u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/I0
|
|
SLICE_X5Y68 LUT6 (Prop_lut6_I0_O) 0.313 4.703 r u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/O
|
|
net (fo=2, routed) 0.550 5.253 u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7_n_0
|
|
SLICE_X4Y68 r u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/I1
|
|
SLICE_X4Y68 LUT6 (Prop_lut6_I1_O) 0.124 5.377 r u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/O
|
|
net (fo=80, routed) 1.095 6.472 u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/soc_sram_addr[0]
|
|
SLICE_X0Y77 r u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/base_ram_be_n_OBUF[1]_inst_i_1/I5
|
|
SLICE_X0Y77 LUT6 (Prop_lut6_I5_O) 0.124 6.596 r u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/base_ram_be_n_OBUF[1]_inst_i_1/O
|
|
net (fo=1, routed) 2.903 9.499 base_ram_be_n_OBUF[1]
|
|
L22 r base_ram_be_n_OBUF[1]_inst/I
|
|
L22 OBUF (Prop_obuf_I_O) 3.531 13.030 r base_ram_be_n_OBUF[1]_inst/O
|
|
net (fo=0) 0.000 13.030 base_ram_be_n[1]
|
|
L22 r base_ram_be_n[1] (OUT)
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock sys_clk rise edge) 20.000 20.000 r
|
|
clock source latency -5.674 14.326
|
|
propagated clock network latency
|
|
0.000 14.326
|
|
clock pessimism -0.601 13.725
|
|
clock uncertainty -0.071 13.654
|
|
output delay -0.300 13.354
|
|
-------------------------------------------------------------------
|
|
required time 13.354
|
|
arrival time -13.030
|
|
-------------------------------------------------------------------
|
|
slack 0.324
|
|
|
|
Slack (MET) : 0.324ns (required time - arrival time)
|
|
Source: u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[3]/C
|
|
(rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Destination: base_ram_be_n[1]
|
|
(output port clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Path Group: sys_clk
|
|
Path Type: Max at Slow Process Corner
|
|
Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns)
|
|
Data Path Delay: 15.350ns (logic 6.848ns (44.608%) route 8.503ns (55.392%))
|
|
Logic Levels: 14 (CARRY4=6 LUT4=2 LUT5=1 LUT6=4 OBUF=1)
|
|
Output Delay: 0.300ns
|
|
Clock Path Skew: -3.955ns (DCD - SCD + CPR)
|
|
Destination Clock Delay (DCD): -5.674ns = ( 14.326 - 20.000 )
|
|
Source Clock Delay (SCD): -2.321ns
|
|
Clock Pessimism Removal (CPR): -0.601ns
|
|
Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Discrete Jitter (DJ): 0.122ns
|
|
Phase Error (PE): 0.000ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock sys_clk rise edge) 0.000 0.000 r
|
|
clock source latency -6.275 -6.275
|
|
propagated clock network latency
|
|
3.955 -2.321
|
|
SLICE_X7Y62 FDCE 0.000 -2.321 r u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[3]/C
|
|
SLICE_X7Y62 FDCE (Prop_fdce_C_Q) 0.456 -1.865 f u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[3]/Q
|
|
net (fo=54, routed) 0.726 -1.139 u_axi_ram/u_axi_sram_sp/len[3]
|
|
SLICE_X7Y61 f u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6/I3
|
|
SLICE_X7Y61 LUT4 (Prop_lut4_I3_O) 0.124 -1.015 r u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6/O
|
|
net (fo=4, routed) 0.946 -0.068 u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6_n_0
|
|
SLICE_X7Y58 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_11/I1
|
|
SLICE_X7Y58 LUT5 (Prop_lut5_I1_O) 0.124 0.056 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_11/O
|
|
net (fo=2, routed) 0.619 0.675 u_axi_ram/u_axi_sram_sp/state_d2[7]
|
|
SLICE_X6Y59 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_15/I5
|
|
SLICE_X6Y59 LUT6 (Prop_lut6_I5_O) 0.124 0.799 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_15/O
|
|
net (fo=1, routed) 0.000 0.799 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_15_n_0
|
|
SLICE_X6Y59 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9/S[3]
|
|
SLICE_X6Y59 CARRY4 (Prop_carry4_S[3]_CO[3])
|
|
0.376 1.175 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9/CO[3]
|
|
net (fo=1, routed) 0.000 1.175 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9_n_0
|
|
SLICE_X6Y60 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/CI
|
|
SLICE_X6Y60 CARRY4 (Prop_carry4_CI_CO[3])
|
|
0.117 1.292 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/CO[3]
|
|
net (fo=1, routed) 0.000 1.292 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10_n_0
|
|
SLICE_X6Y61 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CI
|
|
SLICE_X6Y61 CARRY4 (Prop_carry4_CI_CO[3])
|
|
0.117 1.409 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CO[3]
|
|
net (fo=1, routed) 0.000 1.409 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9_n_0
|
|
SLICE_X6Y62 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/CI
|
|
SLICE_X6Y62 CARRY4 (Prop_carry4_CI_O[2])
|
|
0.239 1.648 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/O[2]
|
|
net (fo=3, routed) 0.929 2.576 u_axi_ram/u_axi_sram_sp/upper_wrap_boundary[20]
|
|
SLICE_X5Y65 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_7/I2
|
|
SLICE_X5Y65 LUT4 (Prop_lut4_I2_O) 0.301 2.877 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_7/O
|
|
net (fo=1, routed) 0.000 2.877 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_7_n_0
|
|
SLICE_X5Y65 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1/S[1]
|
|
SLICE_X5Y65 CARRY4 (Prop_carry4_S[1]_CO[3])
|
|
0.550 3.427 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1/CO[3]
|
|
net (fo=1, routed) 0.000 3.427 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_n_0
|
|
SLICE_X5Y66 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2/CI
|
|
SLICE_X5Y66 CARRY4 (Prop_carry4_CI_CO[2])
|
|
0.228 3.655 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2/CO[2]
|
|
net (fo=22, routed) 0.735 4.390 u_axi_ram/u_axi_sram_sp/req_addr_d1
|
|
SLICE_X5Y68 r u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/I0
|
|
SLICE_X5Y68 LUT6 (Prop_lut6_I0_O) 0.313 4.703 r u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/O
|
|
net (fo=2, routed) 0.550 5.253 u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7_n_0
|
|
SLICE_X4Y68 r u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/I1
|
|
SLICE_X4Y68 LUT6 (Prop_lut6_I1_O) 0.124 5.377 r u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/O
|
|
net (fo=80, routed) 1.095 6.472 u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/soc_sram_addr[0]
|
|
SLICE_X0Y77 r u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/base_ram_be_n_OBUF[1]_inst_i_1/I5
|
|
SLICE_X0Y77 LUT6 (Prop_lut6_I5_O) 0.124 6.596 r u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/base_ram_be_n_OBUF[1]_inst_i_1/O
|
|
net (fo=1, routed) 2.903 9.499 base_ram_be_n_OBUF[1]
|
|
L22 r base_ram_be_n_OBUF[1]_inst/I
|
|
L22 OBUF (Prop_obuf_I_O) 3.531 13.030 r base_ram_be_n_OBUF[1]_inst/O
|
|
net (fo=0) 0.000 13.030 base_ram_be_n[1]
|
|
L22 r base_ram_be_n[1] (OUT)
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock sys_clk rise edge) 20.000 20.000 r
|
|
clock source latency -5.674 14.326
|
|
propagated clock network latency
|
|
0.000 14.326
|
|
clock pessimism -0.601 13.725
|
|
clock uncertainty -0.071 13.654
|
|
output delay -0.300 13.354
|
|
-------------------------------------------------------------------
|
|
required time 13.354
|
|
arrival time -13.030
|
|
-------------------------------------------------------------------
|
|
slack 0.324
|
|
|
|
Slack (MET) : 0.324ns (required time - arrival time)
|
|
Source: u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[3]/C
|
|
(rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Destination: base_ram_be_n[1]
|
|
(output port clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Path Group: sys_clk
|
|
Path Type: Max at Slow Process Corner
|
|
Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns)
|
|
Data Path Delay: 15.350ns (logic 6.848ns (44.608%) route 8.503ns (55.392%))
|
|
Logic Levels: 14 (CARRY4=6 LUT4=2 LUT5=1 LUT6=4 OBUF=1)
|
|
Output Delay: 0.300ns
|
|
Clock Path Skew: -3.955ns (DCD - SCD + CPR)
|
|
Destination Clock Delay (DCD): -5.674ns = ( 14.326 - 20.000 )
|
|
Source Clock Delay (SCD): -2.321ns
|
|
Clock Pessimism Removal (CPR): -0.601ns
|
|
Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Discrete Jitter (DJ): 0.122ns
|
|
Phase Error (PE): 0.000ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock sys_clk rise edge) 0.000 0.000 r
|
|
clock source latency -6.275 -6.275
|
|
propagated clock network latency
|
|
3.955 -2.321
|
|
SLICE_X7Y62 FDCE 0.000 -2.321 r u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[3]/C
|
|
SLICE_X7Y62 FDCE (Prop_fdce_C_Q) 0.456 -1.865 f u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[3]/Q
|
|
net (fo=54, routed) 0.726 -1.139 u_axi_ram/u_axi_sram_sp/len[3]
|
|
SLICE_X7Y61 f u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6/I3
|
|
SLICE_X7Y61 LUT4 (Prop_lut4_I3_O) 0.124 -1.015 r u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6/O
|
|
net (fo=4, routed) 0.946 -0.068 u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6_n_0
|
|
SLICE_X7Y58 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_11/I1
|
|
SLICE_X7Y58 LUT5 (Prop_lut5_I1_O) 0.124 0.056 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_11/O
|
|
net (fo=2, routed) 0.619 0.675 u_axi_ram/u_axi_sram_sp/state_d2[7]
|
|
SLICE_X6Y59 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_15/I5
|
|
SLICE_X6Y59 LUT6 (Prop_lut6_I5_O) 0.124 0.799 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_15/O
|
|
net (fo=1, routed) 0.000 0.799 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_15_n_0
|
|
SLICE_X6Y59 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9/S[3]
|
|
SLICE_X6Y59 CARRY4 (Prop_carry4_S[3]_CO[3])
|
|
0.376 1.175 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9/CO[3]
|
|
net (fo=1, routed) 0.000 1.175 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9_n_0
|
|
SLICE_X6Y60 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/CI
|
|
SLICE_X6Y60 CARRY4 (Prop_carry4_CI_CO[3])
|
|
0.117 1.292 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/CO[3]
|
|
net (fo=1, routed) 0.000 1.292 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10_n_0
|
|
SLICE_X6Y61 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CI
|
|
SLICE_X6Y61 CARRY4 (Prop_carry4_CI_CO[3])
|
|
0.117 1.409 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CO[3]
|
|
net (fo=1, routed) 0.000 1.409 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9_n_0
|
|
SLICE_X6Y62 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/CI
|
|
SLICE_X6Y62 CARRY4 (Prop_carry4_CI_O[2])
|
|
0.239 1.648 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/O[2]
|
|
net (fo=3, routed) 0.929 2.576 u_axi_ram/u_axi_sram_sp/upper_wrap_boundary[20]
|
|
SLICE_X5Y65 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_7/I2
|
|
SLICE_X5Y65 LUT4 (Prop_lut4_I2_O) 0.301 2.877 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_7/O
|
|
net (fo=1, routed) 0.000 2.877 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_7_n_0
|
|
SLICE_X5Y65 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1/S[1]
|
|
SLICE_X5Y65 CARRY4 (Prop_carry4_S[1]_CO[3])
|
|
0.550 3.427 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1/CO[3]
|
|
net (fo=1, routed) 0.000 3.427 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_n_0
|
|
SLICE_X5Y66 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2/CI
|
|
SLICE_X5Y66 CARRY4 (Prop_carry4_CI_CO[2])
|
|
0.228 3.655 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2/CO[2]
|
|
net (fo=22, routed) 0.735 4.390 u_axi_ram/u_axi_sram_sp/req_addr_d1
|
|
SLICE_X5Y68 r u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/I0
|
|
SLICE_X5Y68 LUT6 (Prop_lut6_I0_O) 0.313 4.703 r u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/O
|
|
net (fo=2, routed) 0.550 5.253 u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7_n_0
|
|
SLICE_X4Y68 r u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/I1
|
|
SLICE_X4Y68 LUT6 (Prop_lut6_I1_O) 0.124 5.377 r u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/O
|
|
net (fo=80, routed) 1.095 6.472 u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/soc_sram_addr[0]
|
|
SLICE_X0Y77 r u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/base_ram_be_n_OBUF[1]_inst_i_1/I5
|
|
SLICE_X0Y77 LUT6 (Prop_lut6_I5_O) 0.124 6.596 r u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/base_ram_be_n_OBUF[1]_inst_i_1/O
|
|
net (fo=1, routed) 2.903 9.499 base_ram_be_n_OBUF[1]
|
|
L22 r base_ram_be_n_OBUF[1]_inst/I
|
|
L22 OBUF (Prop_obuf_I_O) 3.531 13.030 r base_ram_be_n_OBUF[1]_inst/O
|
|
net (fo=0) 0.000 13.030 base_ram_be_n[1]
|
|
L22 r base_ram_be_n[1] (OUT)
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock sys_clk rise edge) 20.000 20.000 r
|
|
clock source latency -5.674 14.326
|
|
propagated clock network latency
|
|
0.000 14.326
|
|
clock pessimism -0.601 13.725
|
|
clock uncertainty -0.071 13.654
|
|
output delay -0.300 13.354
|
|
-------------------------------------------------------------------
|
|
required time 13.354
|
|
arrival time -13.030
|
|
-------------------------------------------------------------------
|
|
slack 0.324
|
|
|
|
Slack (MET) : 0.324ns (required time - arrival time)
|
|
Source: u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[3]/C
|
|
(rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Destination: base_ram_be_n[1]
|
|
(output port clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Path Group: sys_clk
|
|
Path Type: Max at Slow Process Corner
|
|
Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns)
|
|
Data Path Delay: 15.350ns (logic 6.848ns (44.608%) route 8.503ns (55.392%))
|
|
Logic Levels: 14 (CARRY4=6 LUT4=2 LUT5=1 LUT6=4 OBUF=1)
|
|
Output Delay: 0.300ns
|
|
Clock Path Skew: -3.955ns (DCD - SCD + CPR)
|
|
Destination Clock Delay (DCD): -5.674ns = ( 14.326 - 20.000 )
|
|
Source Clock Delay (SCD): -2.321ns
|
|
Clock Pessimism Removal (CPR): -0.601ns
|
|
Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Discrete Jitter (DJ): 0.122ns
|
|
Phase Error (PE): 0.000ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock sys_clk rise edge) 0.000 0.000 r
|
|
clock source latency -6.275 -6.275
|
|
propagated clock network latency
|
|
3.955 -2.321
|
|
SLICE_X7Y62 FDCE 0.000 -2.321 r u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[3]/C
|
|
SLICE_X7Y62 FDCE (Prop_fdce_C_Q) 0.456 -1.865 f u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[3]/Q
|
|
net (fo=54, routed) 0.726 -1.139 u_axi_ram/u_axi_sram_sp/len[3]
|
|
SLICE_X7Y61 f u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6/I3
|
|
SLICE_X7Y61 LUT4 (Prop_lut4_I3_O) 0.124 -1.015 r u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6/O
|
|
net (fo=4, routed) 0.946 -0.068 u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6_n_0
|
|
SLICE_X7Y58 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_11/I1
|
|
SLICE_X7Y58 LUT5 (Prop_lut5_I1_O) 0.124 0.056 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_11/O
|
|
net (fo=2, routed) 0.619 0.675 u_axi_ram/u_axi_sram_sp/state_d2[7]
|
|
SLICE_X6Y59 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_15/I5
|
|
SLICE_X6Y59 LUT6 (Prop_lut6_I5_O) 0.124 0.799 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_15/O
|
|
net (fo=1, routed) 0.000 0.799 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_15_n_0
|
|
SLICE_X6Y59 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9/S[3]
|
|
SLICE_X6Y59 CARRY4 (Prop_carry4_S[3]_CO[3])
|
|
0.376 1.175 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9/CO[3]
|
|
net (fo=1, routed) 0.000 1.175 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9_n_0
|
|
SLICE_X6Y60 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/CI
|
|
SLICE_X6Y60 CARRY4 (Prop_carry4_CI_CO[3])
|
|
0.117 1.292 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/CO[3]
|
|
net (fo=1, routed) 0.000 1.292 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10_n_0
|
|
SLICE_X6Y61 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CI
|
|
SLICE_X6Y61 CARRY4 (Prop_carry4_CI_CO[3])
|
|
0.117 1.409 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CO[3]
|
|
net (fo=1, routed) 0.000 1.409 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9_n_0
|
|
SLICE_X6Y62 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/CI
|
|
SLICE_X6Y62 CARRY4 (Prop_carry4_CI_O[2])
|
|
0.239 1.648 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/O[2]
|
|
net (fo=3, routed) 0.929 2.576 u_axi_ram/u_axi_sram_sp/upper_wrap_boundary[20]
|
|
SLICE_X5Y65 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_7/I2
|
|
SLICE_X5Y65 LUT4 (Prop_lut4_I2_O) 0.301 2.877 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_7/O
|
|
net (fo=1, routed) 0.000 2.877 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_7_n_0
|
|
SLICE_X5Y65 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1/S[1]
|
|
SLICE_X5Y65 CARRY4 (Prop_carry4_S[1]_CO[3])
|
|
0.550 3.427 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1/CO[3]
|
|
net (fo=1, routed) 0.000 3.427 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_n_0
|
|
SLICE_X5Y66 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2/CI
|
|
SLICE_X5Y66 CARRY4 (Prop_carry4_CI_CO[2])
|
|
0.228 3.655 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2/CO[2]
|
|
net (fo=22, routed) 0.735 4.390 u_axi_ram/u_axi_sram_sp/req_addr_d1
|
|
SLICE_X5Y68 r u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/I0
|
|
SLICE_X5Y68 LUT6 (Prop_lut6_I0_O) 0.313 4.703 r u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/O
|
|
net (fo=2, routed) 0.550 5.253 u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7_n_0
|
|
SLICE_X4Y68 r u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/I1
|
|
SLICE_X4Y68 LUT6 (Prop_lut6_I1_O) 0.124 5.377 r u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/O
|
|
net (fo=80, routed) 1.095 6.472 u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/soc_sram_addr[0]
|
|
SLICE_X0Y77 r u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/base_ram_be_n_OBUF[1]_inst_i_1/I5
|
|
SLICE_X0Y77 LUT6 (Prop_lut6_I5_O) 0.124 6.596 r u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/base_ram_be_n_OBUF[1]_inst_i_1/O
|
|
net (fo=1, routed) 2.903 9.499 base_ram_be_n_OBUF[1]
|
|
L22 r base_ram_be_n_OBUF[1]_inst/I
|
|
L22 OBUF (Prop_obuf_I_O) 3.531 13.030 r base_ram_be_n_OBUF[1]_inst/O
|
|
net (fo=0) 0.000 13.030 base_ram_be_n[1]
|
|
L22 r base_ram_be_n[1] (OUT)
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock sys_clk rise edge) 20.000 20.000 r
|
|
clock source latency -5.674 14.326
|
|
propagated clock network latency
|
|
0.000 14.326
|
|
clock pessimism -0.601 13.725
|
|
clock uncertainty -0.071 13.654
|
|
output delay -0.300 13.354
|
|
-------------------------------------------------------------------
|
|
required time 13.354
|
|
arrival time -13.030
|
|
-------------------------------------------------------------------
|
|
slack 0.324
|
|
|
|
Slack (MET) : 0.324ns (required time - arrival time)
|
|
Source: u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[3]/C
|
|
(rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Destination: base_ram_be_n[1]
|
|
(output port clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Path Group: sys_clk
|
|
Path Type: Max at Slow Process Corner
|
|
Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns)
|
|
Data Path Delay: 15.350ns (logic 6.848ns (44.608%) route 8.503ns (55.392%))
|
|
Logic Levels: 14 (CARRY4=6 LUT4=2 LUT5=1 LUT6=4 OBUF=1)
|
|
Output Delay: 0.300ns
|
|
Clock Path Skew: -3.955ns (DCD - SCD + CPR)
|
|
Destination Clock Delay (DCD): -5.674ns = ( 14.326 - 20.000 )
|
|
Source Clock Delay (SCD): -2.321ns
|
|
Clock Pessimism Removal (CPR): -0.601ns
|
|
Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Discrete Jitter (DJ): 0.122ns
|
|
Phase Error (PE): 0.000ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock sys_clk rise edge) 0.000 0.000 r
|
|
clock source latency -6.275 -6.275
|
|
propagated clock network latency
|
|
3.955 -2.321
|
|
SLICE_X7Y62 FDCE 0.000 -2.321 r u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[3]/C
|
|
SLICE_X7Y62 FDCE (Prop_fdce_C_Q) 0.456 -1.865 f u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[3]/Q
|
|
net (fo=54, routed) 0.726 -1.139 u_axi_ram/u_axi_sram_sp/len[3]
|
|
SLICE_X7Y61 f u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6/I3
|
|
SLICE_X7Y61 LUT4 (Prop_lut4_I3_O) 0.124 -1.015 r u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6/O
|
|
net (fo=4, routed) 0.946 -0.068 u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6_n_0
|
|
SLICE_X7Y58 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_11/I1
|
|
SLICE_X7Y58 LUT5 (Prop_lut5_I1_O) 0.124 0.056 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_11/O
|
|
net (fo=2, routed) 0.619 0.675 u_axi_ram/u_axi_sram_sp/state_d2[7]
|
|
SLICE_X6Y59 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_15/I5
|
|
SLICE_X6Y59 LUT6 (Prop_lut6_I5_O) 0.124 0.799 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_15/O
|
|
net (fo=1, routed) 0.000 0.799 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_15_n_0
|
|
SLICE_X6Y59 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9/S[3]
|
|
SLICE_X6Y59 CARRY4 (Prop_carry4_S[3]_CO[3])
|
|
0.376 1.175 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9/CO[3]
|
|
net (fo=1, routed) 0.000 1.175 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9_n_0
|
|
SLICE_X6Y60 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/CI
|
|
SLICE_X6Y60 CARRY4 (Prop_carry4_CI_CO[3])
|
|
0.117 1.292 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/CO[3]
|
|
net (fo=1, routed) 0.000 1.292 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10_n_0
|
|
SLICE_X6Y61 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CI
|
|
SLICE_X6Y61 CARRY4 (Prop_carry4_CI_CO[3])
|
|
0.117 1.409 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CO[3]
|
|
net (fo=1, routed) 0.000 1.409 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9_n_0
|
|
SLICE_X6Y62 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/CI
|
|
SLICE_X6Y62 CARRY4 (Prop_carry4_CI_O[2])
|
|
0.239 1.648 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/O[2]
|
|
net (fo=3, routed) 0.929 2.576 u_axi_ram/u_axi_sram_sp/upper_wrap_boundary[20]
|
|
SLICE_X5Y65 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_7/I2
|
|
SLICE_X5Y65 LUT4 (Prop_lut4_I2_O) 0.301 2.877 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_7/O
|
|
net (fo=1, routed) 0.000 2.877 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_7_n_0
|
|
SLICE_X5Y65 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1/S[1]
|
|
SLICE_X5Y65 CARRY4 (Prop_carry4_S[1]_CO[3])
|
|
0.550 3.427 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1/CO[3]
|
|
net (fo=1, routed) 0.000 3.427 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_n_0
|
|
SLICE_X5Y66 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2/CI
|
|
SLICE_X5Y66 CARRY4 (Prop_carry4_CI_CO[2])
|
|
0.228 3.655 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2/CO[2]
|
|
net (fo=22, routed) 0.735 4.390 u_axi_ram/u_axi_sram_sp/req_addr_d1
|
|
SLICE_X5Y68 r u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/I0
|
|
SLICE_X5Y68 LUT6 (Prop_lut6_I0_O) 0.313 4.703 r u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/O
|
|
net (fo=2, routed) 0.550 5.253 u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7_n_0
|
|
SLICE_X4Y68 r u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/I1
|
|
SLICE_X4Y68 LUT6 (Prop_lut6_I1_O) 0.124 5.377 r u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/O
|
|
net (fo=80, routed) 1.095 6.472 u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/soc_sram_addr[0]
|
|
SLICE_X0Y77 r u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/base_ram_be_n_OBUF[1]_inst_i_1/I5
|
|
SLICE_X0Y77 LUT6 (Prop_lut6_I5_O) 0.124 6.596 r u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/base_ram_be_n_OBUF[1]_inst_i_1/O
|
|
net (fo=1, routed) 2.903 9.499 base_ram_be_n_OBUF[1]
|
|
L22 r base_ram_be_n_OBUF[1]_inst/I
|
|
L22 OBUF (Prop_obuf_I_O) 3.531 13.030 r base_ram_be_n_OBUF[1]_inst/O
|
|
net (fo=0) 0.000 13.030 base_ram_be_n[1]
|
|
L22 r base_ram_be_n[1] (OUT)
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock sys_clk rise edge) 20.000 20.000 r
|
|
clock source latency -5.674 14.326
|
|
propagated clock network latency
|
|
0.000 14.326
|
|
clock pessimism -0.601 13.725
|
|
clock uncertainty -0.071 13.654
|
|
output delay -0.300 13.354
|
|
-------------------------------------------------------------------
|
|
required time 13.354
|
|
arrival time -13.030
|
|
-------------------------------------------------------------------
|
|
slack 0.324
|
|
|
|
Slack (MET) : 0.324ns (required time - arrival time)
|
|
Source: u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[3]/C
|
|
(rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Destination: base_ram_be_n[1]
|
|
(output port clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Path Group: sys_clk
|
|
Path Type: Max at Slow Process Corner
|
|
Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns)
|
|
Data Path Delay: 15.350ns (logic 6.848ns (44.608%) route 8.503ns (55.392%))
|
|
Logic Levels: 14 (CARRY4=6 LUT4=2 LUT5=1 LUT6=4 OBUF=1)
|
|
Output Delay: 0.300ns
|
|
Clock Path Skew: -3.955ns (DCD - SCD + CPR)
|
|
Destination Clock Delay (DCD): -5.674ns = ( 14.326 - 20.000 )
|
|
Source Clock Delay (SCD): -2.321ns
|
|
Clock Pessimism Removal (CPR): -0.601ns
|
|
Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Discrete Jitter (DJ): 0.122ns
|
|
Phase Error (PE): 0.000ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock sys_clk rise edge) 0.000 0.000 r
|
|
clock source latency -6.275 -6.275
|
|
propagated clock network latency
|
|
3.955 -2.321
|
|
SLICE_X7Y62 FDCE 0.000 -2.321 r u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[3]/C
|
|
SLICE_X7Y62 FDCE (Prop_fdce_C_Q) 0.456 -1.865 f u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[3]/Q
|
|
net (fo=54, routed) 0.726 -1.139 u_axi_ram/u_axi_sram_sp/len[3]
|
|
SLICE_X7Y61 f u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6/I3
|
|
SLICE_X7Y61 LUT4 (Prop_lut4_I3_O) 0.124 -1.015 r u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6/O
|
|
net (fo=4, routed) 0.946 -0.068 u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6_n_0
|
|
SLICE_X7Y58 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_11/I1
|
|
SLICE_X7Y58 LUT5 (Prop_lut5_I1_O) 0.124 0.056 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_11/O
|
|
net (fo=2, routed) 0.619 0.675 u_axi_ram/u_axi_sram_sp/state_d2[7]
|
|
SLICE_X6Y59 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_15/I5
|
|
SLICE_X6Y59 LUT6 (Prop_lut6_I5_O) 0.124 0.799 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_15/O
|
|
net (fo=1, routed) 0.000 0.799 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_15_n_0
|
|
SLICE_X6Y59 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9/S[3]
|
|
SLICE_X6Y59 CARRY4 (Prop_carry4_S[3]_CO[3])
|
|
0.376 1.175 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9/CO[3]
|
|
net (fo=1, routed) 0.000 1.175 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9_n_0
|
|
SLICE_X6Y60 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/CI
|
|
SLICE_X6Y60 CARRY4 (Prop_carry4_CI_CO[3])
|
|
0.117 1.292 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/CO[3]
|
|
net (fo=1, routed) 0.000 1.292 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10_n_0
|
|
SLICE_X6Y61 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CI
|
|
SLICE_X6Y61 CARRY4 (Prop_carry4_CI_CO[3])
|
|
0.117 1.409 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CO[3]
|
|
net (fo=1, routed) 0.000 1.409 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9_n_0
|
|
SLICE_X6Y62 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/CI
|
|
SLICE_X6Y62 CARRY4 (Prop_carry4_CI_O[2])
|
|
0.239 1.648 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/O[2]
|
|
net (fo=3, routed) 0.929 2.576 u_axi_ram/u_axi_sram_sp/upper_wrap_boundary[20]
|
|
SLICE_X5Y65 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_7/I2
|
|
SLICE_X5Y65 LUT4 (Prop_lut4_I2_O) 0.301 2.877 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_7/O
|
|
net (fo=1, routed) 0.000 2.877 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_7_n_0
|
|
SLICE_X5Y65 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1/S[1]
|
|
SLICE_X5Y65 CARRY4 (Prop_carry4_S[1]_CO[3])
|
|
0.550 3.427 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1/CO[3]
|
|
net (fo=1, routed) 0.000 3.427 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_n_0
|
|
SLICE_X5Y66 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2/CI
|
|
SLICE_X5Y66 CARRY4 (Prop_carry4_CI_CO[2])
|
|
0.228 3.655 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2/CO[2]
|
|
net (fo=22, routed) 0.735 4.390 u_axi_ram/u_axi_sram_sp/req_addr_d1
|
|
SLICE_X5Y68 r u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/I0
|
|
SLICE_X5Y68 LUT6 (Prop_lut6_I0_O) 0.313 4.703 r u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/O
|
|
net (fo=2, routed) 0.550 5.253 u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7_n_0
|
|
SLICE_X4Y68 r u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/I1
|
|
SLICE_X4Y68 LUT6 (Prop_lut6_I1_O) 0.124 5.377 r u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/O
|
|
net (fo=80, routed) 1.095 6.472 u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/soc_sram_addr[0]
|
|
SLICE_X0Y77 r u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/base_ram_be_n_OBUF[1]_inst_i_1/I5
|
|
SLICE_X0Y77 LUT6 (Prop_lut6_I5_O) 0.124 6.596 r u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/base_ram_be_n_OBUF[1]_inst_i_1/O
|
|
net (fo=1, routed) 2.903 9.499 base_ram_be_n_OBUF[1]
|
|
L22 r base_ram_be_n_OBUF[1]_inst/I
|
|
L22 OBUF (Prop_obuf_I_O) 3.531 13.030 r base_ram_be_n_OBUF[1]_inst/O
|
|
net (fo=0) 0.000 13.030 base_ram_be_n[1]
|
|
L22 r base_ram_be_n[1] (OUT)
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock sys_clk rise edge) 20.000 20.000 r
|
|
clock source latency -5.674 14.326
|
|
propagated clock network latency
|
|
0.000 14.326
|
|
clock pessimism -0.601 13.725
|
|
clock uncertainty -0.071 13.654
|
|
output delay -0.300 13.354
|
|
-------------------------------------------------------------------
|
|
required time 13.354
|
|
arrival time -13.030
|
|
-------------------------------------------------------------------
|
|
slack 0.324
|
|
|
|
Slack (MET) : 0.324ns (required time - arrival time)
|
|
Source: u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[3]/C
|
|
(rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Destination: base_ram_be_n[1]
|
|
(output port clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Path Group: sys_clk
|
|
Path Type: Max at Slow Process Corner
|
|
Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns)
|
|
Data Path Delay: 15.350ns (logic 6.848ns (44.608%) route 8.503ns (55.392%))
|
|
Logic Levels: 14 (CARRY4=6 LUT4=2 LUT5=1 LUT6=4 OBUF=1)
|
|
Output Delay: 0.300ns
|
|
Clock Path Skew: -3.955ns (DCD - SCD + CPR)
|
|
Destination Clock Delay (DCD): -5.674ns = ( 14.326 - 20.000 )
|
|
Source Clock Delay (SCD): -2.321ns
|
|
Clock Pessimism Removal (CPR): -0.601ns
|
|
Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Discrete Jitter (DJ): 0.122ns
|
|
Phase Error (PE): 0.000ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock sys_clk rise edge) 0.000 0.000 r
|
|
clock source latency -6.275 -6.275
|
|
propagated clock network latency
|
|
3.955 -2.321
|
|
SLICE_X7Y62 FDCE 0.000 -2.321 r u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[3]/C
|
|
SLICE_X7Y62 FDCE (Prop_fdce_C_Q) 0.456 -1.865 f u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[3]/Q
|
|
net (fo=54, routed) 0.726 -1.139 u_axi_ram/u_axi_sram_sp/len[3]
|
|
SLICE_X7Y61 f u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6/I3
|
|
SLICE_X7Y61 LUT4 (Prop_lut4_I3_O) 0.124 -1.015 r u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6/O
|
|
net (fo=4, routed) 0.946 -0.068 u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6_n_0
|
|
SLICE_X7Y58 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_11/I1
|
|
SLICE_X7Y58 LUT5 (Prop_lut5_I1_O) 0.124 0.056 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_11/O
|
|
net (fo=2, routed) 0.619 0.675 u_axi_ram/u_axi_sram_sp/state_d2[7]
|
|
SLICE_X6Y59 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_15/I5
|
|
SLICE_X6Y59 LUT6 (Prop_lut6_I5_O) 0.124 0.799 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_15/O
|
|
net (fo=1, routed) 0.000 0.799 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_15_n_0
|
|
SLICE_X6Y59 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9/S[3]
|
|
SLICE_X6Y59 CARRY4 (Prop_carry4_S[3]_CO[3])
|
|
0.376 1.175 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9/CO[3]
|
|
net (fo=1, routed) 0.000 1.175 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9_n_0
|
|
SLICE_X6Y60 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/CI
|
|
SLICE_X6Y60 CARRY4 (Prop_carry4_CI_CO[3])
|
|
0.117 1.292 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/CO[3]
|
|
net (fo=1, routed) 0.000 1.292 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10_n_0
|
|
SLICE_X6Y61 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CI
|
|
SLICE_X6Y61 CARRY4 (Prop_carry4_CI_CO[3])
|
|
0.117 1.409 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CO[3]
|
|
net (fo=1, routed) 0.000 1.409 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9_n_0
|
|
SLICE_X6Y62 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/CI
|
|
SLICE_X6Y62 CARRY4 (Prop_carry4_CI_O[2])
|
|
0.239 1.648 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/O[2]
|
|
net (fo=3, routed) 0.929 2.576 u_axi_ram/u_axi_sram_sp/upper_wrap_boundary[20]
|
|
SLICE_X5Y65 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_7/I2
|
|
SLICE_X5Y65 LUT4 (Prop_lut4_I2_O) 0.301 2.877 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_7/O
|
|
net (fo=1, routed) 0.000 2.877 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_7_n_0
|
|
SLICE_X5Y65 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1/S[1]
|
|
SLICE_X5Y65 CARRY4 (Prop_carry4_S[1]_CO[3])
|
|
0.550 3.427 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1/CO[3]
|
|
net (fo=1, routed) 0.000 3.427 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_n_0
|
|
SLICE_X5Y66 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2/CI
|
|
SLICE_X5Y66 CARRY4 (Prop_carry4_CI_CO[2])
|
|
0.228 3.655 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2/CO[2]
|
|
net (fo=22, routed) 0.735 4.390 u_axi_ram/u_axi_sram_sp/req_addr_d1
|
|
SLICE_X5Y68 r u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/I0
|
|
SLICE_X5Y68 LUT6 (Prop_lut6_I0_O) 0.313 4.703 r u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/O
|
|
net (fo=2, routed) 0.550 5.253 u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7_n_0
|
|
SLICE_X4Y68 r u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/I1
|
|
SLICE_X4Y68 LUT6 (Prop_lut6_I1_O) 0.124 5.377 r u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/O
|
|
net (fo=80, routed) 1.095 6.472 u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/soc_sram_addr[0]
|
|
SLICE_X0Y77 r u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/base_ram_be_n_OBUF[1]_inst_i_1/I5
|
|
SLICE_X0Y77 LUT6 (Prop_lut6_I5_O) 0.124 6.596 r u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/base_ram_be_n_OBUF[1]_inst_i_1/O
|
|
net (fo=1, routed) 2.903 9.499 base_ram_be_n_OBUF[1]
|
|
L22 r base_ram_be_n_OBUF[1]_inst/I
|
|
L22 OBUF (Prop_obuf_I_O) 3.531 13.030 r base_ram_be_n_OBUF[1]_inst/O
|
|
net (fo=0) 0.000 13.030 base_ram_be_n[1]
|
|
L22 r base_ram_be_n[1] (OUT)
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock sys_clk rise edge) 20.000 20.000 r
|
|
clock source latency -5.674 14.326
|
|
propagated clock network latency
|
|
0.000 14.326
|
|
clock pessimism -0.601 13.725
|
|
clock uncertainty -0.071 13.654
|
|
output delay -0.300 13.354
|
|
-------------------------------------------------------------------
|
|
required time 13.354
|
|
arrival time -13.030
|
|
-------------------------------------------------------------------
|
|
slack 0.324
|
|
|
|
Slack (MET) : 0.328ns (required time - arrival time)
|
|
Source: u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[3]/C
|
|
(rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Destination: ext_ram_data[16]
|
|
(output port clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Path Group: sys_clk
|
|
Path Type: Max at Slow Process Corner
|
|
Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns)
|
|
Data Path Delay: 15.347ns (logic 6.853ns (44.657%) route 8.493ns (55.343%))
|
|
Logic Levels: 14 (CARRY4=6 LUT3=1 LUT4=2 LUT5=1 LUT6=3 OBUFT=1)
|
|
Output Delay: 0.300ns
|
|
Clock Path Skew: -3.955ns (DCD - SCD + CPR)
|
|
Destination Clock Delay (DCD): -5.674ns = ( 14.326 - 20.000 )
|
|
Source Clock Delay (SCD): -2.321ns
|
|
Clock Pessimism Removal (CPR): -0.601ns
|
|
Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Discrete Jitter (DJ): 0.122ns
|
|
Phase Error (PE): 0.000ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock sys_clk rise edge) 0.000 0.000 r
|
|
clock source latency -6.275 -6.275
|
|
propagated clock network latency
|
|
3.955 -2.321
|
|
SLICE_X7Y62 FDCE 0.000 -2.321 r u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[3]/C
|
|
SLICE_X7Y62 FDCE (Prop_fdce_C_Q) 0.456 -1.865 f u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[3]/Q
|
|
net (fo=54, routed) 0.726 -1.139 u_axi_ram/u_axi_sram_sp/len[3]
|
|
SLICE_X7Y61 f u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6/I3
|
|
SLICE_X7Y61 LUT4 (Prop_lut4_I3_O) 0.124 -1.015 r u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6/O
|
|
net (fo=4, routed) 0.946 -0.068 u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6_n_0
|
|
SLICE_X7Y58 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_11/I1
|
|
SLICE_X7Y58 LUT5 (Prop_lut5_I1_O) 0.124 0.056 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_11/O
|
|
net (fo=2, routed) 0.619 0.675 u_axi_ram/u_axi_sram_sp/state_d2[7]
|
|
SLICE_X6Y59 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_15/I5
|
|
SLICE_X6Y59 LUT6 (Prop_lut6_I5_O) 0.124 0.799 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_15/O
|
|
net (fo=1, routed) 0.000 0.799 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_15_n_0
|
|
SLICE_X6Y59 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9/S[3]
|
|
SLICE_X6Y59 CARRY4 (Prop_carry4_S[3]_CO[3])
|
|
0.376 1.175 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9/CO[3]
|
|
net (fo=1, routed) 0.000 1.175 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9_n_0
|
|
SLICE_X6Y60 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/CI
|
|
SLICE_X6Y60 CARRY4 (Prop_carry4_CI_CO[3])
|
|
0.117 1.292 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/CO[3]
|
|
net (fo=1, routed) 0.000 1.292 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10_n_0
|
|
SLICE_X6Y61 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CI
|
|
SLICE_X6Y61 CARRY4 (Prop_carry4_CI_CO[3])
|
|
0.117 1.409 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CO[3]
|
|
net (fo=1, routed) 0.000 1.409 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9_n_0
|
|
SLICE_X6Y62 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/CI
|
|
SLICE_X6Y62 CARRY4 (Prop_carry4_CI_O[2])
|
|
0.239 1.648 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/O[2]
|
|
net (fo=3, routed) 0.929 2.576 u_axi_ram/u_axi_sram_sp/upper_wrap_boundary[20]
|
|
SLICE_X5Y65 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_7/I2
|
|
SLICE_X5Y65 LUT4 (Prop_lut4_I2_O) 0.301 2.877 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_7/O
|
|
net (fo=1, routed) 0.000 2.877 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_7_n_0
|
|
SLICE_X5Y65 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1/S[1]
|
|
SLICE_X5Y65 CARRY4 (Prop_carry4_S[1]_CO[3])
|
|
0.550 3.427 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1/CO[3]
|
|
net (fo=1, routed) 0.000 3.427 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_n_0
|
|
SLICE_X5Y66 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2/CI
|
|
SLICE_X5Y66 CARRY4 (Prop_carry4_CI_CO[2])
|
|
0.228 3.655 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2/CO[2]
|
|
net (fo=22, routed) 0.735 4.390 u_axi_ram/u_axi_sram_sp/req_addr_d1
|
|
SLICE_X5Y68 r u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/I0
|
|
SLICE_X5Y68 LUT6 (Prop_lut6_I0_O) 0.313 4.703 r u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/O
|
|
net (fo=2, routed) 0.550 5.253 u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7_n_0
|
|
SLICE_X4Y68 r u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/I1
|
|
SLICE_X4Y68 LUT6 (Prop_lut6_I1_O) 0.124 5.377 r u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/O
|
|
net (fo=80, routed) 0.770 6.147 u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/soc_sram_addr[0]
|
|
SLICE_X1Y63 r u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/ext_ram_data_IOBUF[31]_inst_i_2/I2
|
|
SLICE_X1Y63 LUT3 (Prop_lut3_I2_O) 0.124 6.271 f u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/ext_ram_data_IOBUF[31]_inst_i_2/O
|
|
net (fo=32, routed) 3.219 9.490 ext_ram_data_IOBUF[16]_inst/T
|
|
AB16 f ext_ram_data_IOBUF[16]_inst/OBUFT/T
|
|
AB16 OBUFT (TriStatE_obuft_T_O)
|
|
3.536 13.026 r ext_ram_data_IOBUF[16]_inst/OBUFT/O
|
|
net (fo=1, unset) 0.000 13.026 ext_ram_data[16]
|
|
AB16 r ext_ram_data[16] (INOUT)
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock sys_clk rise edge) 20.000 20.000 r
|
|
clock source latency -5.674 14.326
|
|
propagated clock network latency
|
|
0.000 14.326
|
|
clock pessimism -0.601 13.725
|
|
clock uncertainty -0.071 13.654
|
|
output delay -0.300 13.354
|
|
-------------------------------------------------------------------
|
|
required time 13.354
|
|
arrival time -13.026
|
|
-------------------------------------------------------------------
|
|
slack 0.328
|
|
|
|
Slack (MET) : 0.328ns (required time - arrival time)
|
|
Source: u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[3]/C
|
|
(rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Destination: ext_ram_data[16]
|
|
(output port clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Path Group: sys_clk
|
|
Path Type: Max at Slow Process Corner
|
|
Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns)
|
|
Data Path Delay: 15.347ns (logic 6.853ns (44.657%) route 8.493ns (55.343%))
|
|
Logic Levels: 14 (CARRY4=6 LUT3=1 LUT4=2 LUT5=1 LUT6=3 OBUFT=1)
|
|
Output Delay: 0.300ns
|
|
Clock Path Skew: -3.955ns (DCD - SCD + CPR)
|
|
Destination Clock Delay (DCD): -5.674ns = ( 14.326 - 20.000 )
|
|
Source Clock Delay (SCD): -2.321ns
|
|
Clock Pessimism Removal (CPR): -0.601ns
|
|
Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Discrete Jitter (DJ): 0.122ns
|
|
Phase Error (PE): 0.000ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock sys_clk rise edge) 0.000 0.000 r
|
|
clock source latency -6.275 -6.275
|
|
propagated clock network latency
|
|
3.955 -2.321
|
|
SLICE_X7Y62 FDCE 0.000 -2.321 r u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[3]/C
|
|
SLICE_X7Y62 FDCE (Prop_fdce_C_Q) 0.456 -1.865 f u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[3]/Q
|
|
net (fo=54, routed) 0.726 -1.139 u_axi_ram/u_axi_sram_sp/len[3]
|
|
SLICE_X7Y61 f u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6/I3
|
|
SLICE_X7Y61 LUT4 (Prop_lut4_I3_O) 0.124 -1.015 r u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6/O
|
|
net (fo=4, routed) 0.946 -0.068 u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6_n_0
|
|
SLICE_X7Y58 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_11/I1
|
|
SLICE_X7Y58 LUT5 (Prop_lut5_I1_O) 0.124 0.056 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_11/O
|
|
net (fo=2, routed) 0.619 0.675 u_axi_ram/u_axi_sram_sp/state_d2[7]
|
|
SLICE_X6Y59 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_15/I5
|
|
SLICE_X6Y59 LUT6 (Prop_lut6_I5_O) 0.124 0.799 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_15/O
|
|
net (fo=1, routed) 0.000 0.799 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_15_n_0
|
|
SLICE_X6Y59 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9/S[3]
|
|
SLICE_X6Y59 CARRY4 (Prop_carry4_S[3]_CO[3])
|
|
0.376 1.175 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9/CO[3]
|
|
net (fo=1, routed) 0.000 1.175 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9_n_0
|
|
SLICE_X6Y60 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/CI
|
|
SLICE_X6Y60 CARRY4 (Prop_carry4_CI_CO[3])
|
|
0.117 1.292 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/CO[3]
|
|
net (fo=1, routed) 0.000 1.292 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10_n_0
|
|
SLICE_X6Y61 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CI
|
|
SLICE_X6Y61 CARRY4 (Prop_carry4_CI_CO[3])
|
|
0.117 1.409 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CO[3]
|
|
net (fo=1, routed) 0.000 1.409 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9_n_0
|
|
SLICE_X6Y62 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/CI
|
|
SLICE_X6Y62 CARRY4 (Prop_carry4_CI_O[2])
|
|
0.239 1.648 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/O[2]
|
|
net (fo=3, routed) 0.929 2.576 u_axi_ram/u_axi_sram_sp/upper_wrap_boundary[20]
|
|
SLICE_X5Y65 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_7/I2
|
|
SLICE_X5Y65 LUT4 (Prop_lut4_I2_O) 0.301 2.877 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_7/O
|
|
net (fo=1, routed) 0.000 2.877 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_7_n_0
|
|
SLICE_X5Y65 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1/S[1]
|
|
SLICE_X5Y65 CARRY4 (Prop_carry4_S[1]_CO[3])
|
|
0.550 3.427 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1/CO[3]
|
|
net (fo=1, routed) 0.000 3.427 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_n_0
|
|
SLICE_X5Y66 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2/CI
|
|
SLICE_X5Y66 CARRY4 (Prop_carry4_CI_CO[2])
|
|
0.228 3.655 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2/CO[2]
|
|
net (fo=22, routed) 0.735 4.390 u_axi_ram/u_axi_sram_sp/req_addr_d1
|
|
SLICE_X5Y68 r u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/I0
|
|
SLICE_X5Y68 LUT6 (Prop_lut6_I0_O) 0.313 4.703 r u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/O
|
|
net (fo=2, routed) 0.550 5.253 u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7_n_0
|
|
SLICE_X4Y68 r u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/I1
|
|
SLICE_X4Y68 LUT6 (Prop_lut6_I1_O) 0.124 5.377 r u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/O
|
|
net (fo=80, routed) 0.770 6.147 u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/soc_sram_addr[0]
|
|
SLICE_X1Y63 r u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/ext_ram_data_IOBUF[31]_inst_i_2/I2
|
|
SLICE_X1Y63 LUT3 (Prop_lut3_I2_O) 0.124 6.271 f u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/ext_ram_data_IOBUF[31]_inst_i_2/O
|
|
net (fo=32, routed) 3.219 9.490 ext_ram_data_IOBUF[16]_inst/T
|
|
AB16 f ext_ram_data_IOBUF[16]_inst/OBUFT/T
|
|
AB16 OBUFT (TriStatE_obuft_T_O)
|
|
3.536 13.026 r ext_ram_data_IOBUF[16]_inst/OBUFT/O
|
|
net (fo=1, unset) 0.000 13.026 ext_ram_data[16]
|
|
AB16 r ext_ram_data[16] (INOUT)
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock sys_clk rise edge) 20.000 20.000 r
|
|
clock source latency -5.674 14.326
|
|
propagated clock network latency
|
|
0.000 14.326
|
|
clock pessimism -0.601 13.725
|
|
clock uncertainty -0.071 13.654
|
|
output delay -0.300 13.354
|
|
-------------------------------------------------------------------
|
|
required time 13.354
|
|
arrival time -13.026
|
|
-------------------------------------------------------------------
|
|
slack 0.328
|
|
|
|
Slack (MET) : 0.328ns (required time - arrival time)
|
|
Source: u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[3]/C
|
|
(rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Destination: ext_ram_data[16]
|
|
(output port clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Path Group: sys_clk
|
|
Path Type: Max at Slow Process Corner
|
|
Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns)
|
|
Data Path Delay: 15.347ns (logic 6.853ns (44.657%) route 8.493ns (55.343%))
|
|
Logic Levels: 14 (CARRY4=6 LUT3=1 LUT4=2 LUT5=1 LUT6=3 OBUFT=1)
|
|
Output Delay: 0.300ns
|
|
Clock Path Skew: -3.955ns (DCD - SCD + CPR)
|
|
Destination Clock Delay (DCD): -5.674ns = ( 14.326 - 20.000 )
|
|
Source Clock Delay (SCD): -2.321ns
|
|
Clock Pessimism Removal (CPR): -0.601ns
|
|
Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Discrete Jitter (DJ): 0.122ns
|
|
Phase Error (PE): 0.000ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock sys_clk rise edge) 0.000 0.000 r
|
|
clock source latency -6.275 -6.275
|
|
propagated clock network latency
|
|
3.955 -2.321
|
|
SLICE_X7Y62 FDCE 0.000 -2.321 r u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[3]/C
|
|
SLICE_X7Y62 FDCE (Prop_fdce_C_Q) 0.456 -1.865 f u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[3]/Q
|
|
net (fo=54, routed) 0.726 -1.139 u_axi_ram/u_axi_sram_sp/len[3]
|
|
SLICE_X7Y61 f u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6/I3
|
|
SLICE_X7Y61 LUT4 (Prop_lut4_I3_O) 0.124 -1.015 r u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6/O
|
|
net (fo=4, routed) 0.946 -0.068 u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6_n_0
|
|
SLICE_X7Y58 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_11/I1
|
|
SLICE_X7Y58 LUT5 (Prop_lut5_I1_O) 0.124 0.056 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_11/O
|
|
net (fo=2, routed) 0.619 0.675 u_axi_ram/u_axi_sram_sp/state_d2[7]
|
|
SLICE_X6Y59 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_15/I5
|
|
SLICE_X6Y59 LUT6 (Prop_lut6_I5_O) 0.124 0.799 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_15/O
|
|
net (fo=1, routed) 0.000 0.799 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_15_n_0
|
|
SLICE_X6Y59 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9/S[3]
|
|
SLICE_X6Y59 CARRY4 (Prop_carry4_S[3]_CO[3])
|
|
0.376 1.175 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9/CO[3]
|
|
net (fo=1, routed) 0.000 1.175 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9_n_0
|
|
SLICE_X6Y60 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/CI
|
|
SLICE_X6Y60 CARRY4 (Prop_carry4_CI_CO[3])
|
|
0.117 1.292 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/CO[3]
|
|
net (fo=1, routed) 0.000 1.292 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10_n_0
|
|
SLICE_X6Y61 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CI
|
|
SLICE_X6Y61 CARRY4 (Prop_carry4_CI_CO[3])
|
|
0.117 1.409 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CO[3]
|
|
net (fo=1, routed) 0.000 1.409 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9_n_0
|
|
SLICE_X6Y62 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/CI
|
|
SLICE_X6Y62 CARRY4 (Prop_carry4_CI_O[2])
|
|
0.239 1.648 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/O[2]
|
|
net (fo=3, routed) 0.929 2.576 u_axi_ram/u_axi_sram_sp/upper_wrap_boundary[20]
|
|
SLICE_X5Y65 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_7/I2
|
|
SLICE_X5Y65 LUT4 (Prop_lut4_I2_O) 0.301 2.877 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_7/O
|
|
net (fo=1, routed) 0.000 2.877 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_7_n_0
|
|
SLICE_X5Y65 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1/S[1]
|
|
SLICE_X5Y65 CARRY4 (Prop_carry4_S[1]_CO[3])
|
|
0.550 3.427 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1/CO[3]
|
|
net (fo=1, routed) 0.000 3.427 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_n_0
|
|
SLICE_X5Y66 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2/CI
|
|
SLICE_X5Y66 CARRY4 (Prop_carry4_CI_CO[2])
|
|
0.228 3.655 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2/CO[2]
|
|
net (fo=22, routed) 0.735 4.390 u_axi_ram/u_axi_sram_sp/req_addr_d1
|
|
SLICE_X5Y68 r u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/I0
|
|
SLICE_X5Y68 LUT6 (Prop_lut6_I0_O) 0.313 4.703 r u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/O
|
|
net (fo=2, routed) 0.550 5.253 u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7_n_0
|
|
SLICE_X4Y68 r u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/I1
|
|
SLICE_X4Y68 LUT6 (Prop_lut6_I1_O) 0.124 5.377 r u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/O
|
|
net (fo=80, routed) 0.770 6.147 u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/soc_sram_addr[0]
|
|
SLICE_X1Y63 r u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/ext_ram_data_IOBUF[31]_inst_i_2/I2
|
|
SLICE_X1Y63 LUT3 (Prop_lut3_I2_O) 0.124 6.271 f u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/ext_ram_data_IOBUF[31]_inst_i_2/O
|
|
net (fo=32, routed) 3.219 9.490 ext_ram_data_IOBUF[16]_inst/T
|
|
AB16 f ext_ram_data_IOBUF[16]_inst/OBUFT/T
|
|
AB16 OBUFT (TriStatE_obuft_T_O)
|
|
3.536 13.026 r ext_ram_data_IOBUF[16]_inst/OBUFT/O
|
|
net (fo=1, unset) 0.000 13.026 ext_ram_data[16]
|
|
AB16 r ext_ram_data[16] (INOUT)
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock sys_clk rise edge) 20.000 20.000 r
|
|
clock source latency -5.674 14.326
|
|
propagated clock network latency
|
|
0.000 14.326
|
|
clock pessimism -0.601 13.725
|
|
clock uncertainty -0.071 13.654
|
|
output delay -0.300 13.354
|
|
-------------------------------------------------------------------
|
|
required time 13.354
|
|
arrival time -13.026
|
|
-------------------------------------------------------------------
|
|
slack 0.328
|
|
|
|
Slack (MET) : 0.328ns (required time - arrival time)
|
|
Source: u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[3]/C
|
|
(rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Destination: ext_ram_data[16]
|
|
(output port clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Path Group: sys_clk
|
|
Path Type: Max at Slow Process Corner
|
|
Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns)
|
|
Data Path Delay: 15.347ns (logic 6.853ns (44.657%) route 8.493ns (55.343%))
|
|
Logic Levels: 14 (CARRY4=6 LUT3=1 LUT4=2 LUT5=1 LUT6=3 OBUFT=1)
|
|
Output Delay: 0.300ns
|
|
Clock Path Skew: -3.955ns (DCD - SCD + CPR)
|
|
Destination Clock Delay (DCD): -5.674ns = ( 14.326 - 20.000 )
|
|
Source Clock Delay (SCD): -2.321ns
|
|
Clock Pessimism Removal (CPR): -0.601ns
|
|
Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Discrete Jitter (DJ): 0.122ns
|
|
Phase Error (PE): 0.000ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock sys_clk rise edge) 0.000 0.000 r
|
|
clock source latency -6.275 -6.275
|
|
propagated clock network latency
|
|
3.955 -2.321
|
|
SLICE_X7Y62 FDCE 0.000 -2.321 r u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[3]/C
|
|
SLICE_X7Y62 FDCE (Prop_fdce_C_Q) 0.456 -1.865 f u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[3]/Q
|
|
net (fo=54, routed) 0.726 -1.139 u_axi_ram/u_axi_sram_sp/len[3]
|
|
SLICE_X7Y61 f u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6/I3
|
|
SLICE_X7Y61 LUT4 (Prop_lut4_I3_O) 0.124 -1.015 r u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6/O
|
|
net (fo=4, routed) 0.946 -0.068 u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6_n_0
|
|
SLICE_X7Y58 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_11/I1
|
|
SLICE_X7Y58 LUT5 (Prop_lut5_I1_O) 0.124 0.056 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_11/O
|
|
net (fo=2, routed) 0.619 0.675 u_axi_ram/u_axi_sram_sp/state_d2[7]
|
|
SLICE_X6Y59 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_15/I5
|
|
SLICE_X6Y59 LUT6 (Prop_lut6_I5_O) 0.124 0.799 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_15/O
|
|
net (fo=1, routed) 0.000 0.799 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_15_n_0
|
|
SLICE_X6Y59 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9/S[3]
|
|
SLICE_X6Y59 CARRY4 (Prop_carry4_S[3]_CO[3])
|
|
0.376 1.175 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9/CO[3]
|
|
net (fo=1, routed) 0.000 1.175 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9_n_0
|
|
SLICE_X6Y60 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/CI
|
|
SLICE_X6Y60 CARRY4 (Prop_carry4_CI_CO[3])
|
|
0.117 1.292 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/CO[3]
|
|
net (fo=1, routed) 0.000 1.292 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10_n_0
|
|
SLICE_X6Y61 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CI
|
|
SLICE_X6Y61 CARRY4 (Prop_carry4_CI_CO[3])
|
|
0.117 1.409 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CO[3]
|
|
net (fo=1, routed) 0.000 1.409 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9_n_0
|
|
SLICE_X6Y62 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/CI
|
|
SLICE_X6Y62 CARRY4 (Prop_carry4_CI_O[2])
|
|
0.239 1.648 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/O[2]
|
|
net (fo=3, routed) 0.929 2.576 u_axi_ram/u_axi_sram_sp/upper_wrap_boundary[20]
|
|
SLICE_X5Y65 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_7/I2
|
|
SLICE_X5Y65 LUT4 (Prop_lut4_I2_O) 0.301 2.877 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_7/O
|
|
net (fo=1, routed) 0.000 2.877 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_7_n_0
|
|
SLICE_X5Y65 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1/S[1]
|
|
SLICE_X5Y65 CARRY4 (Prop_carry4_S[1]_CO[3])
|
|
0.550 3.427 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1/CO[3]
|
|
net (fo=1, routed) 0.000 3.427 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_n_0
|
|
SLICE_X5Y66 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2/CI
|
|
SLICE_X5Y66 CARRY4 (Prop_carry4_CI_CO[2])
|
|
0.228 3.655 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2/CO[2]
|
|
net (fo=22, routed) 0.735 4.390 u_axi_ram/u_axi_sram_sp/req_addr_d1
|
|
SLICE_X5Y68 r u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/I0
|
|
SLICE_X5Y68 LUT6 (Prop_lut6_I0_O) 0.313 4.703 r u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/O
|
|
net (fo=2, routed) 0.550 5.253 u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7_n_0
|
|
SLICE_X4Y68 r u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/I1
|
|
SLICE_X4Y68 LUT6 (Prop_lut6_I1_O) 0.124 5.377 r u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/O
|
|
net (fo=80, routed) 0.770 6.147 u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/soc_sram_addr[0]
|
|
SLICE_X1Y63 r u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/ext_ram_data_IOBUF[31]_inst_i_2/I2
|
|
SLICE_X1Y63 LUT3 (Prop_lut3_I2_O) 0.124 6.271 f u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/ext_ram_data_IOBUF[31]_inst_i_2/O
|
|
net (fo=32, routed) 3.219 9.490 ext_ram_data_IOBUF[16]_inst/T
|
|
AB16 f ext_ram_data_IOBUF[16]_inst/OBUFT/T
|
|
AB16 OBUFT (TriStatE_obuft_T_O)
|
|
3.536 13.026 r ext_ram_data_IOBUF[16]_inst/OBUFT/O
|
|
net (fo=1, unset) 0.000 13.026 ext_ram_data[16]
|
|
AB16 r ext_ram_data[16] (INOUT)
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock sys_clk rise edge) 20.000 20.000 r
|
|
clock source latency -5.674 14.326
|
|
propagated clock network latency
|
|
0.000 14.326
|
|
clock pessimism -0.601 13.725
|
|
clock uncertainty -0.071 13.654
|
|
output delay -0.300 13.354
|
|
-------------------------------------------------------------------
|
|
required time 13.354
|
|
arrival time -13.026
|
|
-------------------------------------------------------------------
|
|
slack 0.328
|
|
|
|
Slack (MET) : 0.328ns (required time - arrival time)
|
|
Source: u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[3]/C
|
|
(rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Destination: ext_ram_data[16]
|
|
(output port clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Path Group: sys_clk
|
|
Path Type: Max at Slow Process Corner
|
|
Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns)
|
|
Data Path Delay: 15.347ns (logic 6.853ns (44.657%) route 8.493ns (55.343%))
|
|
Logic Levels: 14 (CARRY4=6 LUT3=1 LUT4=2 LUT5=1 LUT6=3 OBUFT=1)
|
|
Output Delay: 0.300ns
|
|
Clock Path Skew: -3.955ns (DCD - SCD + CPR)
|
|
Destination Clock Delay (DCD): -5.674ns = ( 14.326 - 20.000 )
|
|
Source Clock Delay (SCD): -2.321ns
|
|
Clock Pessimism Removal (CPR): -0.601ns
|
|
Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Discrete Jitter (DJ): 0.122ns
|
|
Phase Error (PE): 0.000ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock sys_clk rise edge) 0.000 0.000 r
|
|
clock source latency -6.275 -6.275
|
|
propagated clock network latency
|
|
3.955 -2.321
|
|
SLICE_X7Y62 FDCE 0.000 -2.321 r u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[3]/C
|
|
SLICE_X7Y62 FDCE (Prop_fdce_C_Q) 0.456 -1.865 f u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[3]/Q
|
|
net (fo=54, routed) 0.726 -1.139 u_axi_ram/u_axi_sram_sp/len[3]
|
|
SLICE_X7Y61 f u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6/I3
|
|
SLICE_X7Y61 LUT4 (Prop_lut4_I3_O) 0.124 -1.015 r u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6/O
|
|
net (fo=4, routed) 0.946 -0.068 u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6_n_0
|
|
SLICE_X7Y58 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_11/I1
|
|
SLICE_X7Y58 LUT5 (Prop_lut5_I1_O) 0.124 0.056 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_11/O
|
|
net (fo=2, routed) 0.619 0.675 u_axi_ram/u_axi_sram_sp/state_d2[7]
|
|
SLICE_X6Y59 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_15/I5
|
|
SLICE_X6Y59 LUT6 (Prop_lut6_I5_O) 0.124 0.799 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_15/O
|
|
net (fo=1, routed) 0.000 0.799 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_15_n_0
|
|
SLICE_X6Y59 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9/S[3]
|
|
SLICE_X6Y59 CARRY4 (Prop_carry4_S[3]_CO[3])
|
|
0.376 1.175 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9/CO[3]
|
|
net (fo=1, routed) 0.000 1.175 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9_n_0
|
|
SLICE_X6Y60 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/CI
|
|
SLICE_X6Y60 CARRY4 (Prop_carry4_CI_CO[3])
|
|
0.117 1.292 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/CO[3]
|
|
net (fo=1, routed) 0.000 1.292 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10_n_0
|
|
SLICE_X6Y61 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CI
|
|
SLICE_X6Y61 CARRY4 (Prop_carry4_CI_CO[3])
|
|
0.117 1.409 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CO[3]
|
|
net (fo=1, routed) 0.000 1.409 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9_n_0
|
|
SLICE_X6Y62 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/CI
|
|
SLICE_X6Y62 CARRY4 (Prop_carry4_CI_O[2])
|
|
0.239 1.648 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/O[2]
|
|
net (fo=3, routed) 0.929 2.576 u_axi_ram/u_axi_sram_sp/upper_wrap_boundary[20]
|
|
SLICE_X5Y65 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_7/I2
|
|
SLICE_X5Y65 LUT4 (Prop_lut4_I2_O) 0.301 2.877 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_7/O
|
|
net (fo=1, routed) 0.000 2.877 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_7_n_0
|
|
SLICE_X5Y65 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1/S[1]
|
|
SLICE_X5Y65 CARRY4 (Prop_carry4_S[1]_CO[3])
|
|
0.550 3.427 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1/CO[3]
|
|
net (fo=1, routed) 0.000 3.427 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_n_0
|
|
SLICE_X5Y66 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2/CI
|
|
SLICE_X5Y66 CARRY4 (Prop_carry4_CI_CO[2])
|
|
0.228 3.655 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2/CO[2]
|
|
net (fo=22, routed) 0.735 4.390 u_axi_ram/u_axi_sram_sp/req_addr_d1
|
|
SLICE_X5Y68 r u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/I0
|
|
SLICE_X5Y68 LUT6 (Prop_lut6_I0_O) 0.313 4.703 r u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/O
|
|
net (fo=2, routed) 0.550 5.253 u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7_n_0
|
|
SLICE_X4Y68 r u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/I1
|
|
SLICE_X4Y68 LUT6 (Prop_lut6_I1_O) 0.124 5.377 r u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/O
|
|
net (fo=80, routed) 0.770 6.147 u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/soc_sram_addr[0]
|
|
SLICE_X1Y63 r u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/ext_ram_data_IOBUF[31]_inst_i_2/I2
|
|
SLICE_X1Y63 LUT3 (Prop_lut3_I2_O) 0.124 6.271 f u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/ext_ram_data_IOBUF[31]_inst_i_2/O
|
|
net (fo=32, routed) 3.219 9.490 ext_ram_data_IOBUF[16]_inst/T
|
|
AB16 f ext_ram_data_IOBUF[16]_inst/OBUFT/T
|
|
AB16 OBUFT (TriStatE_obuft_T_O)
|
|
3.536 13.026 r ext_ram_data_IOBUF[16]_inst/OBUFT/O
|
|
net (fo=1, unset) 0.000 13.026 ext_ram_data[16]
|
|
AB16 r ext_ram_data[16] (INOUT)
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock sys_clk rise edge) 20.000 20.000 r
|
|
clock source latency -5.674 14.326
|
|
propagated clock network latency
|
|
0.000 14.326
|
|
clock pessimism -0.601 13.725
|
|
clock uncertainty -0.071 13.654
|
|
output delay -0.300 13.354
|
|
-------------------------------------------------------------------
|
|
required time 13.354
|
|
arrival time -13.026
|
|
-------------------------------------------------------------------
|
|
slack 0.328
|
|
|
|
Slack (MET) : 0.328ns (required time - arrival time)
|
|
Source: u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[3]/C
|
|
(rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Destination: ext_ram_data[16]
|
|
(output port clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Path Group: sys_clk
|
|
Path Type: Max at Slow Process Corner
|
|
Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns)
|
|
Data Path Delay: 15.347ns (logic 6.853ns (44.657%) route 8.493ns (55.343%))
|
|
Logic Levels: 14 (CARRY4=6 LUT3=1 LUT4=2 LUT5=1 LUT6=3 OBUFT=1)
|
|
Output Delay: 0.300ns
|
|
Clock Path Skew: -3.955ns (DCD - SCD + CPR)
|
|
Destination Clock Delay (DCD): -5.674ns = ( 14.326 - 20.000 )
|
|
Source Clock Delay (SCD): -2.321ns
|
|
Clock Pessimism Removal (CPR): -0.601ns
|
|
Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Discrete Jitter (DJ): 0.122ns
|
|
Phase Error (PE): 0.000ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock sys_clk rise edge) 0.000 0.000 r
|
|
clock source latency -6.275 -6.275
|
|
propagated clock network latency
|
|
3.955 -2.321
|
|
SLICE_X7Y62 FDCE 0.000 -2.321 r u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[3]/C
|
|
SLICE_X7Y62 FDCE (Prop_fdce_C_Q) 0.456 -1.865 f u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[3]/Q
|
|
net (fo=54, routed) 0.726 -1.139 u_axi_ram/u_axi_sram_sp/len[3]
|
|
SLICE_X7Y61 f u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6/I3
|
|
SLICE_X7Y61 LUT4 (Prop_lut4_I3_O) 0.124 -1.015 r u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6/O
|
|
net (fo=4, routed) 0.946 -0.068 u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6_n_0
|
|
SLICE_X7Y58 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_11/I1
|
|
SLICE_X7Y58 LUT5 (Prop_lut5_I1_O) 0.124 0.056 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_11/O
|
|
net (fo=2, routed) 0.619 0.675 u_axi_ram/u_axi_sram_sp/state_d2[7]
|
|
SLICE_X6Y59 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_15/I5
|
|
SLICE_X6Y59 LUT6 (Prop_lut6_I5_O) 0.124 0.799 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_15/O
|
|
net (fo=1, routed) 0.000 0.799 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_15_n_0
|
|
SLICE_X6Y59 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9/S[3]
|
|
SLICE_X6Y59 CARRY4 (Prop_carry4_S[3]_CO[3])
|
|
0.376 1.175 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9/CO[3]
|
|
net (fo=1, routed) 0.000 1.175 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9_n_0
|
|
SLICE_X6Y60 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/CI
|
|
SLICE_X6Y60 CARRY4 (Prop_carry4_CI_CO[3])
|
|
0.117 1.292 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/CO[3]
|
|
net (fo=1, routed) 0.000 1.292 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10_n_0
|
|
SLICE_X6Y61 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CI
|
|
SLICE_X6Y61 CARRY4 (Prop_carry4_CI_CO[3])
|
|
0.117 1.409 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CO[3]
|
|
net (fo=1, routed) 0.000 1.409 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9_n_0
|
|
SLICE_X6Y62 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/CI
|
|
SLICE_X6Y62 CARRY4 (Prop_carry4_CI_O[2])
|
|
0.239 1.648 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/O[2]
|
|
net (fo=3, routed) 0.929 2.576 u_axi_ram/u_axi_sram_sp/upper_wrap_boundary[20]
|
|
SLICE_X5Y65 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_7/I2
|
|
SLICE_X5Y65 LUT4 (Prop_lut4_I2_O) 0.301 2.877 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_7/O
|
|
net (fo=1, routed) 0.000 2.877 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_7_n_0
|
|
SLICE_X5Y65 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1/S[1]
|
|
SLICE_X5Y65 CARRY4 (Prop_carry4_S[1]_CO[3])
|
|
0.550 3.427 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1/CO[3]
|
|
net (fo=1, routed) 0.000 3.427 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_n_0
|
|
SLICE_X5Y66 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2/CI
|
|
SLICE_X5Y66 CARRY4 (Prop_carry4_CI_CO[2])
|
|
0.228 3.655 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2/CO[2]
|
|
net (fo=22, routed) 0.735 4.390 u_axi_ram/u_axi_sram_sp/req_addr_d1
|
|
SLICE_X5Y68 r u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/I0
|
|
SLICE_X5Y68 LUT6 (Prop_lut6_I0_O) 0.313 4.703 r u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/O
|
|
net (fo=2, routed) 0.550 5.253 u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7_n_0
|
|
SLICE_X4Y68 r u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/I1
|
|
SLICE_X4Y68 LUT6 (Prop_lut6_I1_O) 0.124 5.377 r u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/O
|
|
net (fo=80, routed) 0.770 6.147 u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/soc_sram_addr[0]
|
|
SLICE_X1Y63 r u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/ext_ram_data_IOBUF[31]_inst_i_2/I2
|
|
SLICE_X1Y63 LUT3 (Prop_lut3_I2_O) 0.124 6.271 f u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/ext_ram_data_IOBUF[31]_inst_i_2/O
|
|
net (fo=32, routed) 3.219 9.490 ext_ram_data_IOBUF[16]_inst/T
|
|
AB16 f ext_ram_data_IOBUF[16]_inst/OBUFT/T
|
|
AB16 OBUFT (TriStatE_obuft_T_O)
|
|
3.536 13.026 r ext_ram_data_IOBUF[16]_inst/OBUFT/O
|
|
net (fo=1, unset) 0.000 13.026 ext_ram_data[16]
|
|
AB16 r ext_ram_data[16] (INOUT)
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock sys_clk rise edge) 20.000 20.000 r
|
|
clock source latency -5.674 14.326
|
|
propagated clock network latency
|
|
0.000 14.326
|
|
clock pessimism -0.601 13.725
|
|
clock uncertainty -0.071 13.654
|
|
output delay -0.300 13.354
|
|
-------------------------------------------------------------------
|
|
required time 13.354
|
|
arrival time -13.026
|
|
-------------------------------------------------------------------
|
|
slack 0.328
|
|
|
|
Slack (MET) : 0.328ns (required time - arrival time)
|
|
Source: u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[3]/C
|
|
(rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Destination: ext_ram_data[16]
|
|
(output port clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Path Group: sys_clk
|
|
Path Type: Max at Slow Process Corner
|
|
Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns)
|
|
Data Path Delay: 15.347ns (logic 6.853ns (44.657%) route 8.493ns (55.343%))
|
|
Logic Levels: 14 (CARRY4=6 LUT3=1 LUT4=2 LUT5=1 LUT6=3 OBUFT=1)
|
|
Output Delay: 0.300ns
|
|
Clock Path Skew: -3.955ns (DCD - SCD + CPR)
|
|
Destination Clock Delay (DCD): -5.674ns = ( 14.326 - 20.000 )
|
|
Source Clock Delay (SCD): -2.321ns
|
|
Clock Pessimism Removal (CPR): -0.601ns
|
|
Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Discrete Jitter (DJ): 0.122ns
|
|
Phase Error (PE): 0.000ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock sys_clk rise edge) 0.000 0.000 r
|
|
clock source latency -6.275 -6.275
|
|
propagated clock network latency
|
|
3.955 -2.321
|
|
SLICE_X7Y62 FDCE 0.000 -2.321 r u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[3]/C
|
|
SLICE_X7Y62 FDCE (Prop_fdce_C_Q) 0.456 -1.865 f u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[3]/Q
|
|
net (fo=54, routed) 0.726 -1.139 u_axi_ram/u_axi_sram_sp/len[3]
|
|
SLICE_X7Y61 f u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6/I3
|
|
SLICE_X7Y61 LUT4 (Prop_lut4_I3_O) 0.124 -1.015 r u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6/O
|
|
net (fo=4, routed) 0.946 -0.068 u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6_n_0
|
|
SLICE_X7Y58 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_11/I1
|
|
SLICE_X7Y58 LUT5 (Prop_lut5_I1_O) 0.124 0.056 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_11/O
|
|
net (fo=2, routed) 0.619 0.675 u_axi_ram/u_axi_sram_sp/state_d2[7]
|
|
SLICE_X6Y59 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_15/I5
|
|
SLICE_X6Y59 LUT6 (Prop_lut6_I5_O) 0.124 0.799 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_15/O
|
|
net (fo=1, routed) 0.000 0.799 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_15_n_0
|
|
SLICE_X6Y59 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9/S[3]
|
|
SLICE_X6Y59 CARRY4 (Prop_carry4_S[3]_CO[3])
|
|
0.376 1.175 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9/CO[3]
|
|
net (fo=1, routed) 0.000 1.175 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9_n_0
|
|
SLICE_X6Y60 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/CI
|
|
SLICE_X6Y60 CARRY4 (Prop_carry4_CI_CO[3])
|
|
0.117 1.292 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/CO[3]
|
|
net (fo=1, routed) 0.000 1.292 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10_n_0
|
|
SLICE_X6Y61 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CI
|
|
SLICE_X6Y61 CARRY4 (Prop_carry4_CI_CO[3])
|
|
0.117 1.409 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CO[3]
|
|
net (fo=1, routed) 0.000 1.409 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9_n_0
|
|
SLICE_X6Y62 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/CI
|
|
SLICE_X6Y62 CARRY4 (Prop_carry4_CI_O[2])
|
|
0.239 1.648 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/O[2]
|
|
net (fo=3, routed) 0.929 2.576 u_axi_ram/u_axi_sram_sp/upper_wrap_boundary[20]
|
|
SLICE_X5Y65 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_7/I2
|
|
SLICE_X5Y65 LUT4 (Prop_lut4_I2_O) 0.301 2.877 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_7/O
|
|
net (fo=1, routed) 0.000 2.877 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_7_n_0
|
|
SLICE_X5Y65 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1/S[1]
|
|
SLICE_X5Y65 CARRY4 (Prop_carry4_S[1]_CO[3])
|
|
0.550 3.427 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1/CO[3]
|
|
net (fo=1, routed) 0.000 3.427 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_n_0
|
|
SLICE_X5Y66 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2/CI
|
|
SLICE_X5Y66 CARRY4 (Prop_carry4_CI_CO[2])
|
|
0.228 3.655 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2/CO[2]
|
|
net (fo=22, routed) 0.735 4.390 u_axi_ram/u_axi_sram_sp/req_addr_d1
|
|
SLICE_X5Y68 r u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/I0
|
|
SLICE_X5Y68 LUT6 (Prop_lut6_I0_O) 0.313 4.703 r u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/O
|
|
net (fo=2, routed) 0.550 5.253 u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7_n_0
|
|
SLICE_X4Y68 r u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/I1
|
|
SLICE_X4Y68 LUT6 (Prop_lut6_I1_O) 0.124 5.377 r u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/O
|
|
net (fo=80, routed) 0.770 6.147 u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/soc_sram_addr[0]
|
|
SLICE_X1Y63 r u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/ext_ram_data_IOBUF[31]_inst_i_2/I2
|
|
SLICE_X1Y63 LUT3 (Prop_lut3_I2_O) 0.124 6.271 f u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/ext_ram_data_IOBUF[31]_inst_i_2/O
|
|
net (fo=32, routed) 3.219 9.490 ext_ram_data_IOBUF[16]_inst/T
|
|
AB16 f ext_ram_data_IOBUF[16]_inst/OBUFT/T
|
|
AB16 OBUFT (TriStatE_obuft_T_O)
|
|
3.536 13.026 r ext_ram_data_IOBUF[16]_inst/OBUFT/O
|
|
net (fo=1, unset) 0.000 13.026 ext_ram_data[16]
|
|
AB16 r ext_ram_data[16] (INOUT)
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock sys_clk rise edge) 20.000 20.000 r
|
|
clock source latency -5.674 14.326
|
|
propagated clock network latency
|
|
0.000 14.326
|
|
clock pessimism -0.601 13.725
|
|
clock uncertainty -0.071 13.654
|
|
output delay -0.300 13.354
|
|
-------------------------------------------------------------------
|
|
required time 13.354
|
|
arrival time -13.026
|
|
-------------------------------------------------------------------
|
|
slack 0.328
|
|
|
|
Slack (MET) : 0.328ns (required time - arrival time)
|
|
Source: u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[3]/C
|
|
(rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Destination: ext_ram_data[16]
|
|
(output port clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Path Group: sys_clk
|
|
Path Type: Max at Slow Process Corner
|
|
Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns)
|
|
Data Path Delay: 15.347ns (logic 6.853ns (44.657%) route 8.493ns (55.343%))
|
|
Logic Levels: 14 (CARRY4=6 LUT3=1 LUT4=2 LUT5=1 LUT6=3 OBUFT=1)
|
|
Output Delay: 0.300ns
|
|
Clock Path Skew: -3.955ns (DCD - SCD + CPR)
|
|
Destination Clock Delay (DCD): -5.674ns = ( 14.326 - 20.000 )
|
|
Source Clock Delay (SCD): -2.321ns
|
|
Clock Pessimism Removal (CPR): -0.601ns
|
|
Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Discrete Jitter (DJ): 0.122ns
|
|
Phase Error (PE): 0.000ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock sys_clk rise edge) 0.000 0.000 r
|
|
clock source latency -6.275 -6.275
|
|
propagated clock network latency
|
|
3.955 -2.321
|
|
SLICE_X7Y62 FDCE 0.000 -2.321 r u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[3]/C
|
|
SLICE_X7Y62 FDCE (Prop_fdce_C_Q) 0.456 -1.865 f u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[3]/Q
|
|
net (fo=54, routed) 0.726 -1.139 u_axi_ram/u_axi_sram_sp/len[3]
|
|
SLICE_X7Y61 f u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6/I3
|
|
SLICE_X7Y61 LUT4 (Prop_lut4_I3_O) 0.124 -1.015 r u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6/O
|
|
net (fo=4, routed) 0.946 -0.068 u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6_n_0
|
|
SLICE_X7Y58 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_11/I1
|
|
SLICE_X7Y58 LUT5 (Prop_lut5_I1_O) 0.124 0.056 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_11/O
|
|
net (fo=2, routed) 0.619 0.675 u_axi_ram/u_axi_sram_sp/state_d2[7]
|
|
SLICE_X6Y59 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_15/I5
|
|
SLICE_X6Y59 LUT6 (Prop_lut6_I5_O) 0.124 0.799 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_15/O
|
|
net (fo=1, routed) 0.000 0.799 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_15_n_0
|
|
SLICE_X6Y59 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9/S[3]
|
|
SLICE_X6Y59 CARRY4 (Prop_carry4_S[3]_CO[3])
|
|
0.376 1.175 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9/CO[3]
|
|
net (fo=1, routed) 0.000 1.175 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9_n_0
|
|
SLICE_X6Y60 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/CI
|
|
SLICE_X6Y60 CARRY4 (Prop_carry4_CI_CO[3])
|
|
0.117 1.292 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/CO[3]
|
|
net (fo=1, routed) 0.000 1.292 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10_n_0
|
|
SLICE_X6Y61 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CI
|
|
SLICE_X6Y61 CARRY4 (Prop_carry4_CI_CO[3])
|
|
0.117 1.409 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CO[3]
|
|
net (fo=1, routed) 0.000 1.409 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9_n_0
|
|
SLICE_X6Y62 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/CI
|
|
SLICE_X6Y62 CARRY4 (Prop_carry4_CI_O[2])
|
|
0.239 1.648 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/O[2]
|
|
net (fo=3, routed) 0.929 2.576 u_axi_ram/u_axi_sram_sp/upper_wrap_boundary[20]
|
|
SLICE_X5Y65 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_7/I2
|
|
SLICE_X5Y65 LUT4 (Prop_lut4_I2_O) 0.301 2.877 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_7/O
|
|
net (fo=1, routed) 0.000 2.877 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_7_n_0
|
|
SLICE_X5Y65 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1/S[1]
|
|
SLICE_X5Y65 CARRY4 (Prop_carry4_S[1]_CO[3])
|
|
0.550 3.427 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1/CO[3]
|
|
net (fo=1, routed) 0.000 3.427 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_n_0
|
|
SLICE_X5Y66 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2/CI
|
|
SLICE_X5Y66 CARRY4 (Prop_carry4_CI_CO[2])
|
|
0.228 3.655 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2/CO[2]
|
|
net (fo=22, routed) 0.735 4.390 u_axi_ram/u_axi_sram_sp/req_addr_d1
|
|
SLICE_X5Y68 r u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/I0
|
|
SLICE_X5Y68 LUT6 (Prop_lut6_I0_O) 0.313 4.703 r u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/O
|
|
net (fo=2, routed) 0.550 5.253 u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7_n_0
|
|
SLICE_X4Y68 r u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/I1
|
|
SLICE_X4Y68 LUT6 (Prop_lut6_I1_O) 0.124 5.377 r u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/O
|
|
net (fo=80, routed) 0.770 6.147 u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/soc_sram_addr[0]
|
|
SLICE_X1Y63 r u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/ext_ram_data_IOBUF[31]_inst_i_2/I2
|
|
SLICE_X1Y63 LUT3 (Prop_lut3_I2_O) 0.124 6.271 f u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/ext_ram_data_IOBUF[31]_inst_i_2/O
|
|
net (fo=32, routed) 3.219 9.490 ext_ram_data_IOBUF[16]_inst/T
|
|
AB16 f ext_ram_data_IOBUF[16]_inst/OBUFT/T
|
|
AB16 OBUFT (TriStatE_obuft_T_O)
|
|
3.536 13.026 r ext_ram_data_IOBUF[16]_inst/OBUFT/O
|
|
net (fo=1, unset) 0.000 13.026 ext_ram_data[16]
|
|
AB16 r ext_ram_data[16] (INOUT)
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock sys_clk rise edge) 20.000 20.000 r
|
|
clock source latency -5.674 14.326
|
|
propagated clock network latency
|
|
0.000 14.326
|
|
clock pessimism -0.601 13.725
|
|
clock uncertainty -0.071 13.654
|
|
output delay -0.300 13.354
|
|
-------------------------------------------------------------------
|
|
required time 13.354
|
|
arrival time -13.026
|
|
-------------------------------------------------------------------
|
|
slack 0.328
|
|
|
|
Slack (MET) : 0.328ns (required time - arrival time)
|
|
Source: u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[3]/C
|
|
(rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Destination: ext_ram_data[16]
|
|
(output port clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Path Group: sys_clk
|
|
Path Type: Max at Slow Process Corner
|
|
Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns)
|
|
Data Path Delay: 15.347ns (logic 6.853ns (44.657%) route 8.493ns (55.343%))
|
|
Logic Levels: 14 (CARRY4=6 LUT3=1 LUT4=2 LUT5=1 LUT6=3 OBUFT=1)
|
|
Output Delay: 0.300ns
|
|
Clock Path Skew: -3.955ns (DCD - SCD + CPR)
|
|
Destination Clock Delay (DCD): -5.674ns = ( 14.326 - 20.000 )
|
|
Source Clock Delay (SCD): -2.321ns
|
|
Clock Pessimism Removal (CPR): -0.601ns
|
|
Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Discrete Jitter (DJ): 0.122ns
|
|
Phase Error (PE): 0.000ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock sys_clk rise edge) 0.000 0.000 r
|
|
clock source latency -6.275 -6.275
|
|
propagated clock network latency
|
|
3.955 -2.321
|
|
SLICE_X7Y62 FDCE 0.000 -2.321 r u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[3]/C
|
|
SLICE_X7Y62 FDCE (Prop_fdce_C_Q) 0.456 -1.865 f u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[3]/Q
|
|
net (fo=54, routed) 0.726 -1.139 u_axi_ram/u_axi_sram_sp/len[3]
|
|
SLICE_X7Y61 f u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6/I3
|
|
SLICE_X7Y61 LUT4 (Prop_lut4_I3_O) 0.124 -1.015 r u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6/O
|
|
net (fo=4, routed) 0.946 -0.068 u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6_n_0
|
|
SLICE_X7Y58 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_11/I1
|
|
SLICE_X7Y58 LUT5 (Prop_lut5_I1_O) 0.124 0.056 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_11/O
|
|
net (fo=2, routed) 0.619 0.675 u_axi_ram/u_axi_sram_sp/state_d2[7]
|
|
SLICE_X6Y59 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_15/I5
|
|
SLICE_X6Y59 LUT6 (Prop_lut6_I5_O) 0.124 0.799 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_15/O
|
|
net (fo=1, routed) 0.000 0.799 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_15_n_0
|
|
SLICE_X6Y59 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9/S[3]
|
|
SLICE_X6Y59 CARRY4 (Prop_carry4_S[3]_CO[3])
|
|
0.376 1.175 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9/CO[3]
|
|
net (fo=1, routed) 0.000 1.175 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9_n_0
|
|
SLICE_X6Y60 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/CI
|
|
SLICE_X6Y60 CARRY4 (Prop_carry4_CI_CO[3])
|
|
0.117 1.292 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/CO[3]
|
|
net (fo=1, routed) 0.000 1.292 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10_n_0
|
|
SLICE_X6Y61 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CI
|
|
SLICE_X6Y61 CARRY4 (Prop_carry4_CI_CO[3])
|
|
0.117 1.409 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CO[3]
|
|
net (fo=1, routed) 0.000 1.409 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9_n_0
|
|
SLICE_X6Y62 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/CI
|
|
SLICE_X6Y62 CARRY4 (Prop_carry4_CI_O[2])
|
|
0.239 1.648 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/O[2]
|
|
net (fo=3, routed) 0.929 2.576 u_axi_ram/u_axi_sram_sp/upper_wrap_boundary[20]
|
|
SLICE_X5Y65 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_7/I2
|
|
SLICE_X5Y65 LUT4 (Prop_lut4_I2_O) 0.301 2.877 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_7/O
|
|
net (fo=1, routed) 0.000 2.877 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_7_n_0
|
|
SLICE_X5Y65 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1/S[1]
|
|
SLICE_X5Y65 CARRY4 (Prop_carry4_S[1]_CO[3])
|
|
0.550 3.427 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1/CO[3]
|
|
net (fo=1, routed) 0.000 3.427 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_n_0
|
|
SLICE_X5Y66 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2/CI
|
|
SLICE_X5Y66 CARRY4 (Prop_carry4_CI_CO[2])
|
|
0.228 3.655 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2/CO[2]
|
|
net (fo=22, routed) 0.735 4.390 u_axi_ram/u_axi_sram_sp/req_addr_d1
|
|
SLICE_X5Y68 r u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/I0
|
|
SLICE_X5Y68 LUT6 (Prop_lut6_I0_O) 0.313 4.703 r u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/O
|
|
net (fo=2, routed) 0.550 5.253 u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7_n_0
|
|
SLICE_X4Y68 r u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/I1
|
|
SLICE_X4Y68 LUT6 (Prop_lut6_I1_O) 0.124 5.377 r u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/O
|
|
net (fo=80, routed) 0.770 6.147 u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/soc_sram_addr[0]
|
|
SLICE_X1Y63 r u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/ext_ram_data_IOBUF[31]_inst_i_2/I2
|
|
SLICE_X1Y63 LUT3 (Prop_lut3_I2_O) 0.124 6.271 f u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/ext_ram_data_IOBUF[31]_inst_i_2/O
|
|
net (fo=32, routed) 3.219 9.490 ext_ram_data_IOBUF[16]_inst/T
|
|
AB16 f ext_ram_data_IOBUF[16]_inst/OBUFT/T
|
|
AB16 OBUFT (TriStatE_obuft_T_O)
|
|
3.536 13.026 r ext_ram_data_IOBUF[16]_inst/OBUFT/O
|
|
net (fo=1, unset) 0.000 13.026 ext_ram_data[16]
|
|
AB16 r ext_ram_data[16] (INOUT)
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock sys_clk rise edge) 20.000 20.000 r
|
|
clock source latency -5.674 14.326
|
|
propagated clock network latency
|
|
0.000 14.326
|
|
clock pessimism -0.601 13.725
|
|
clock uncertainty -0.071 13.654
|
|
output delay -0.300 13.354
|
|
-------------------------------------------------------------------
|
|
required time 13.354
|
|
arrival time -13.026
|
|
-------------------------------------------------------------------
|
|
slack 0.328
|
|
|
|
Slack (MET) : 0.328ns (required time - arrival time)
|
|
Source: u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[3]/C
|
|
(rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Destination: ext_ram_data[16]
|
|
(output port clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Path Group: sys_clk
|
|
Path Type: Max at Slow Process Corner
|
|
Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns)
|
|
Data Path Delay: 15.347ns (logic 6.853ns (44.657%) route 8.493ns (55.343%))
|
|
Logic Levels: 14 (CARRY4=6 LUT3=1 LUT4=2 LUT5=1 LUT6=3 OBUFT=1)
|
|
Output Delay: 0.300ns
|
|
Clock Path Skew: -3.955ns (DCD - SCD + CPR)
|
|
Destination Clock Delay (DCD): -5.674ns = ( 14.326 - 20.000 )
|
|
Source Clock Delay (SCD): -2.321ns
|
|
Clock Pessimism Removal (CPR): -0.601ns
|
|
Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Discrete Jitter (DJ): 0.122ns
|
|
Phase Error (PE): 0.000ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock sys_clk rise edge) 0.000 0.000 r
|
|
clock source latency -6.275 -6.275
|
|
propagated clock network latency
|
|
3.955 -2.321
|
|
SLICE_X7Y62 FDCE 0.000 -2.321 r u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[3]/C
|
|
SLICE_X7Y62 FDCE (Prop_fdce_C_Q) 0.456 -1.865 f u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[3]/Q
|
|
net (fo=54, routed) 0.726 -1.139 u_axi_ram/u_axi_sram_sp/len[3]
|
|
SLICE_X7Y61 f u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6/I3
|
|
SLICE_X7Y61 LUT4 (Prop_lut4_I3_O) 0.124 -1.015 r u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6/O
|
|
net (fo=4, routed) 0.946 -0.068 u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6_n_0
|
|
SLICE_X7Y58 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_11/I1
|
|
SLICE_X7Y58 LUT5 (Prop_lut5_I1_O) 0.124 0.056 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_11/O
|
|
net (fo=2, routed) 0.619 0.675 u_axi_ram/u_axi_sram_sp/state_d2[7]
|
|
SLICE_X6Y59 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_15/I5
|
|
SLICE_X6Y59 LUT6 (Prop_lut6_I5_O) 0.124 0.799 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_15/O
|
|
net (fo=1, routed) 0.000 0.799 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_15_n_0
|
|
SLICE_X6Y59 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9/S[3]
|
|
SLICE_X6Y59 CARRY4 (Prop_carry4_S[3]_CO[3])
|
|
0.376 1.175 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9/CO[3]
|
|
net (fo=1, routed) 0.000 1.175 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9_n_0
|
|
SLICE_X6Y60 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/CI
|
|
SLICE_X6Y60 CARRY4 (Prop_carry4_CI_CO[3])
|
|
0.117 1.292 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/CO[3]
|
|
net (fo=1, routed) 0.000 1.292 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10_n_0
|
|
SLICE_X6Y61 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CI
|
|
SLICE_X6Y61 CARRY4 (Prop_carry4_CI_CO[3])
|
|
0.117 1.409 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CO[3]
|
|
net (fo=1, routed) 0.000 1.409 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9_n_0
|
|
SLICE_X6Y62 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/CI
|
|
SLICE_X6Y62 CARRY4 (Prop_carry4_CI_O[2])
|
|
0.239 1.648 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/O[2]
|
|
net (fo=3, routed) 0.929 2.576 u_axi_ram/u_axi_sram_sp/upper_wrap_boundary[20]
|
|
SLICE_X5Y65 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_7/I2
|
|
SLICE_X5Y65 LUT4 (Prop_lut4_I2_O) 0.301 2.877 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_7/O
|
|
net (fo=1, routed) 0.000 2.877 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_7_n_0
|
|
SLICE_X5Y65 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1/S[1]
|
|
SLICE_X5Y65 CARRY4 (Prop_carry4_S[1]_CO[3])
|
|
0.550 3.427 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1/CO[3]
|
|
net (fo=1, routed) 0.000 3.427 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_n_0
|
|
SLICE_X5Y66 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2/CI
|
|
SLICE_X5Y66 CARRY4 (Prop_carry4_CI_CO[2])
|
|
0.228 3.655 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2/CO[2]
|
|
net (fo=22, routed) 0.735 4.390 u_axi_ram/u_axi_sram_sp/req_addr_d1
|
|
SLICE_X5Y68 r u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/I0
|
|
SLICE_X5Y68 LUT6 (Prop_lut6_I0_O) 0.313 4.703 r u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/O
|
|
net (fo=2, routed) 0.550 5.253 u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7_n_0
|
|
SLICE_X4Y68 r u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/I1
|
|
SLICE_X4Y68 LUT6 (Prop_lut6_I1_O) 0.124 5.377 r u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/O
|
|
net (fo=80, routed) 0.770 6.147 u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/soc_sram_addr[0]
|
|
SLICE_X1Y63 r u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/ext_ram_data_IOBUF[31]_inst_i_2/I2
|
|
SLICE_X1Y63 LUT3 (Prop_lut3_I2_O) 0.124 6.271 f u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/ext_ram_data_IOBUF[31]_inst_i_2/O
|
|
net (fo=32, routed) 3.219 9.490 ext_ram_data_IOBUF[16]_inst/T
|
|
AB16 f ext_ram_data_IOBUF[16]_inst/OBUFT/T
|
|
AB16 OBUFT (TriStatE_obuft_T_O)
|
|
3.536 13.026 r ext_ram_data_IOBUF[16]_inst/OBUFT/O
|
|
net (fo=1, unset) 0.000 13.026 ext_ram_data[16]
|
|
AB16 r ext_ram_data[16] (INOUT)
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock sys_clk rise edge) 20.000 20.000 r
|
|
clock source latency -5.674 14.326
|
|
propagated clock network latency
|
|
0.000 14.326
|
|
clock pessimism -0.601 13.725
|
|
clock uncertainty -0.071 13.654
|
|
output delay -0.300 13.354
|
|
-------------------------------------------------------------------
|
|
required time 13.354
|
|
arrival time -13.026
|
|
-------------------------------------------------------------------
|
|
slack 0.328
|
|
|
|
Slack (MET) : 0.329ns (required time - arrival time)
|
|
Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_wb_inc_reg/C
|
|
(rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_block_r_reg[810]/D
|
|
(rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Path Group: sys_clk
|
|
Path Type: Setup (Max at Slow Process Corner)
|
|
Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns)
|
|
Data Path Delay: 19.400ns (logic 0.789ns (4.067%) route 18.611ns (95.933%))
|
|
Logic Levels: 2 (LUT4=1 MUXF7=1)
|
|
Clock Path Skew: -0.314ns (DCD - SCD + CPR)
|
|
Destination Clock Delay (DCD): -2.294ns = ( 17.706 - 20.000 )
|
|
Source Clock Delay (SCD): -2.487ns
|
|
Clock Pessimism Removal (CPR): -0.507ns
|
|
Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Discrete Jitter (DJ): 0.122ns
|
|
Phase Error (PE): 0.000ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock sys_clk rise edge) 0.000 0.000 r
|
|
clock source latency -6.275 -6.275
|
|
propagated clock network latency
|
|
3.789 -2.487
|
|
SLICE_X123Y83 FDRE 0.000 -2.487 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_wb_inc_reg/C
|
|
SLICE_X123Y83 FDRE (Prop_fdre_C_Q) 0.456 -2.031 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_wb_inc_reg/Q
|
|
net (fo=1088, routed) 18.611 16.580 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_c_in_bram/dj_block_r_reg[902]_3
|
|
SLICE_X76Y142 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_c_in_bram/dj_block_r[810]_i_2/I2
|
|
SLICE_X76Y142 LUT4 (Prop_lut4_I2_O) 0.124 16.704 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_c_in_bram/dj_block_r[810]_i_2/O
|
|
net (fo=1, routed) 0.000 16.704 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_c_in_bram/dj_block_r[810]_i_2_n_0
|
|
SLICE_X76Y142 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_c_in_bram/dj_block_r_reg[810]_i_1/I0
|
|
SLICE_X76Y142 MUXF7 (Prop_muxf7_I0_O) 0.209 16.913 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_c_in_bram/dj_block_r_reg[810]_i_1/O
|
|
net (fo=1, routed) 0.000 16.913 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_c_in_bram_n_307
|
|
SLICE_X76Y142 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_block_r_reg[810]/D
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock sys_clk rise edge) 20.000 20.000 r
|
|
clock source latency -5.674 14.326
|
|
propagated clock network latency
|
|
3.381 17.706
|
|
clock pessimism -0.507 17.199
|
|
clock uncertainty -0.071 17.129
|
|
SLICE_X76Y142 FDCE (Setup_fdce_C_D) 0.113 17.242 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_block_r_reg[810]
|
|
-------------------------------------------------------------------
|
|
required time 17.242
|
|
arrival time -16.913
|
|
-------------------------------------------------------------------
|
|
slack 0.329
|
|
|
|
Slack (MET) : 0.329ns (required time - arrival time)
|
|
Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_wb_inc_reg/C
|
|
(rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_block_r_reg[810]/D
|
|
(rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Path Group: sys_clk
|
|
Path Type: Setup (Max at Slow Process Corner)
|
|
Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns)
|
|
Data Path Delay: 19.400ns (logic 0.789ns (4.067%) route 18.611ns (95.933%))
|
|
Logic Levels: 2 (LUT4=1 MUXF7=1)
|
|
Clock Path Skew: -0.314ns (DCD - SCD + CPR)
|
|
Destination Clock Delay (DCD): -2.294ns = ( 17.706 - 20.000 )
|
|
Source Clock Delay (SCD): -2.487ns
|
|
Clock Pessimism Removal (CPR): -0.507ns
|
|
Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Discrete Jitter (DJ): 0.122ns
|
|
Phase Error (PE): 0.000ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock sys_clk rise edge) 0.000 0.000 r
|
|
clock source latency -6.275 -6.275
|
|
propagated clock network latency
|
|
3.789 -2.487
|
|
SLICE_X123Y83 FDRE 0.000 -2.487 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_wb_inc_reg/C
|
|
SLICE_X123Y83 FDRE (Prop_fdre_C_Q) 0.456 -2.031 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_wb_inc_reg/Q
|
|
net (fo=1088, routed) 18.611 16.580 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_c_in_bram/dj_block_r_reg[902]_3
|
|
SLICE_X76Y142 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_c_in_bram/dj_block_r[810]_i_2/I2
|
|
SLICE_X76Y142 LUT4 (Prop_lut4_I2_O) 0.124 16.704 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_c_in_bram/dj_block_r[810]_i_2/O
|
|
net (fo=1, routed) 0.000 16.704 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_c_in_bram/dj_block_r[810]_i_2_n_0
|
|
SLICE_X76Y142 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_c_in_bram/dj_block_r_reg[810]_i_1/I0
|
|
SLICE_X76Y142 MUXF7 (Prop_muxf7_I0_O) 0.209 16.913 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_c_in_bram/dj_block_r_reg[810]_i_1/O
|
|
net (fo=1, routed) 0.000 16.913 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_c_in_bram_n_307
|
|
SLICE_X76Y142 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_block_r_reg[810]/D
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock sys_clk rise edge) 20.000 20.000 r
|
|
clock source latency -5.674 14.326
|
|
propagated clock network latency
|
|
3.381 17.706
|
|
clock pessimism -0.507 17.199
|
|
clock uncertainty -0.071 17.129
|
|
SLICE_X76Y142 FDCE (Setup_fdce_C_D) 0.113 17.242 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_block_r_reg[810]
|
|
-------------------------------------------------------------------
|
|
required time 17.242
|
|
arrival time -16.913
|
|
-------------------------------------------------------------------
|
|
slack 0.329
|
|
|
|
Slack (MET) : 0.329ns (required time - arrival time)
|
|
Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_wb_inc_reg/C
|
|
(rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_block_r_reg[810]/D
|
|
(rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Path Group: sys_clk
|
|
Path Type: Setup (Max at Slow Process Corner)
|
|
Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns)
|
|
Data Path Delay: 19.400ns (logic 0.789ns (4.067%) route 18.611ns (95.933%))
|
|
Logic Levels: 2 (LUT4=1 MUXF7=1)
|
|
Clock Path Skew: -0.314ns (DCD - SCD + CPR)
|
|
Destination Clock Delay (DCD): -2.294ns = ( 17.706 - 20.000 )
|
|
Source Clock Delay (SCD): -2.487ns
|
|
Clock Pessimism Removal (CPR): -0.507ns
|
|
Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Discrete Jitter (DJ): 0.122ns
|
|
Phase Error (PE): 0.000ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock sys_clk rise edge) 0.000 0.000 r
|
|
clock source latency -6.275 -6.275
|
|
propagated clock network latency
|
|
3.789 -2.487
|
|
SLICE_X123Y83 FDRE 0.000 -2.487 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_wb_inc_reg/C
|
|
SLICE_X123Y83 FDRE (Prop_fdre_C_Q) 0.456 -2.031 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_wb_inc_reg/Q
|
|
net (fo=1088, routed) 18.611 16.580 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_c_in_bram/dj_block_r_reg[902]_3
|
|
SLICE_X76Y142 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_c_in_bram/dj_block_r[810]_i_2/I2
|
|
SLICE_X76Y142 LUT4 (Prop_lut4_I2_O) 0.124 16.704 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_c_in_bram/dj_block_r[810]_i_2/O
|
|
net (fo=1, routed) 0.000 16.704 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_c_in_bram/dj_block_r[810]_i_2_n_0
|
|
SLICE_X76Y142 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_c_in_bram/dj_block_r_reg[810]_i_1/I0
|
|
SLICE_X76Y142 MUXF7 (Prop_muxf7_I0_O) 0.209 16.913 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_c_in_bram/dj_block_r_reg[810]_i_1/O
|
|
net (fo=1, routed) 0.000 16.913 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_c_in_bram_n_307
|
|
SLICE_X76Y142 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_block_r_reg[810]/D
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock sys_clk rise edge) 20.000 20.000 r
|
|
clock source latency -5.674 14.326
|
|
propagated clock network latency
|
|
3.381 17.706
|
|
clock pessimism -0.507 17.199
|
|
clock uncertainty -0.071 17.129
|
|
SLICE_X76Y142 FDCE (Setup_fdce_C_D) 0.113 17.242 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_block_r_reg[810]
|
|
-------------------------------------------------------------------
|
|
required time 17.242
|
|
arrival time -16.913
|
|
-------------------------------------------------------------------
|
|
slack 0.329
|
|
|
|
Slack (MET) : 0.329ns (required time - arrival time)
|
|
Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_wb_inc_reg/C
|
|
(rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_block_r_reg[810]/D
|
|
(rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Path Group: sys_clk
|
|
Path Type: Setup (Max at Slow Process Corner)
|
|
Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns)
|
|
Data Path Delay: 19.400ns (logic 0.789ns (4.067%) route 18.611ns (95.933%))
|
|
Logic Levels: 2 (LUT4=1 MUXF7=1)
|
|
Clock Path Skew: -0.314ns (DCD - SCD + CPR)
|
|
Destination Clock Delay (DCD): -2.294ns = ( 17.706 - 20.000 )
|
|
Source Clock Delay (SCD): -2.487ns
|
|
Clock Pessimism Removal (CPR): -0.507ns
|
|
Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Discrete Jitter (DJ): 0.122ns
|
|
Phase Error (PE): 0.000ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock sys_clk rise edge) 0.000 0.000 r
|
|
clock source latency -6.275 -6.275
|
|
propagated clock network latency
|
|
3.789 -2.487
|
|
SLICE_X123Y83 FDRE 0.000 -2.487 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_wb_inc_reg/C
|
|
SLICE_X123Y83 FDRE (Prop_fdre_C_Q) 0.456 -2.031 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_wb_inc_reg/Q
|
|
net (fo=1088, routed) 18.611 16.580 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_c_in_bram/dj_block_r_reg[902]_3
|
|
SLICE_X76Y142 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_c_in_bram/dj_block_r[810]_i_2/I2
|
|
SLICE_X76Y142 LUT4 (Prop_lut4_I2_O) 0.124 16.704 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_c_in_bram/dj_block_r[810]_i_2/O
|
|
net (fo=1, routed) 0.000 16.704 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_c_in_bram/dj_block_r[810]_i_2_n_0
|
|
SLICE_X76Y142 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_c_in_bram/dj_block_r_reg[810]_i_1/I0
|
|
SLICE_X76Y142 MUXF7 (Prop_muxf7_I0_O) 0.209 16.913 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_c_in_bram/dj_block_r_reg[810]_i_1/O
|
|
net (fo=1, routed) 0.000 16.913 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_c_in_bram_n_307
|
|
SLICE_X76Y142 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_block_r_reg[810]/D
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock sys_clk rise edge) 20.000 20.000 r
|
|
clock source latency -5.674 14.326
|
|
propagated clock network latency
|
|
3.381 17.706
|
|
clock pessimism -0.507 17.199
|
|
clock uncertainty -0.071 17.129
|
|
SLICE_X76Y142 FDCE (Setup_fdce_C_D) 0.113 17.242 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_block_r_reg[810]
|
|
-------------------------------------------------------------------
|
|
required time 17.242
|
|
arrival time -16.913
|
|
-------------------------------------------------------------------
|
|
slack 0.329
|
|
|
|
Slack (MET) : 0.332ns (required time - arrival time)
|
|
Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_wb_inc_reg/C
|
|
(rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_block_r_reg[940]/D
|
|
(rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Path Group: sys_clk
|
|
Path Type: Setup (Max at Slow Process Corner)
|
|
Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns)
|
|
Data Path Delay: 19.340ns (logic 0.818ns (4.230%) route 18.522ns (95.770%))
|
|
Logic Levels: 2 (LUT4=1 MUXF7=1)
|
|
Clock Path Skew: -0.321ns (DCD - SCD + CPR)
|
|
Destination Clock Delay (DCD): -2.301ns = ( 17.699 - 20.000 )
|
|
Source Clock Delay (SCD): -2.487ns
|
|
Clock Pessimism Removal (CPR): -0.507ns
|
|
Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Discrete Jitter (DJ): 0.122ns
|
|
Phase Error (PE): 0.000ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock sys_clk rise edge) 0.000 0.000 r
|
|
clock source latency -6.275 -6.275
|
|
propagated clock network latency
|
|
3.789 -2.487
|
|
SLICE_X123Y83 FDRE 0.000 -2.487 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_wb_inc_reg/C
|
|
SLICE_X123Y83 FDRE (Prop_fdre_C_Q) 0.456 -2.031 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_wb_inc_reg/Q
|
|
net (fo=1088, routed) 18.522 16.492 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_c_in_bram/dj_block_r_reg[902]_3
|
|
SLICE_X79Y145 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_c_in_bram/dj_block_r[940]_i_2/I2
|
|
SLICE_X79Y145 LUT4 (Prop_lut4_I2_O) 0.124 16.616 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_c_in_bram/dj_block_r[940]_i_2/O
|
|
net (fo=1, routed) 0.000 16.616 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_c_in_bram/dj_block_r[940]_i_2_n_0
|
|
SLICE_X79Y145 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_c_in_bram/dj_block_r_reg[940]_i_1/I0
|
|
SLICE_X79Y145 MUXF7 (Prop_muxf7_I0_O) 0.238 16.854 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_c_in_bram/dj_block_r_reg[940]_i_1/O
|
|
net (fo=1, routed) 0.000 16.854 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_c_in_bram_n_177
|
|
SLICE_X79Y145 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_block_r_reg[940]/D
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock sys_clk rise edge) 20.000 20.000 r
|
|
clock source latency -5.674 14.326
|
|
propagated clock network latency
|
|
3.373 17.699
|
|
clock pessimism -0.507 17.192
|
|
clock uncertainty -0.071 17.122
|
|
SLICE_X79Y145 FDCE (Setup_fdce_C_D) 0.064 17.186 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_block_r_reg[940]
|
|
-------------------------------------------------------------------
|
|
required time 17.186
|
|
arrival time -16.854
|
|
-------------------------------------------------------------------
|
|
slack 0.332
|
|
|
|
Slack (MET) : 0.332ns (required time - arrival time)
|
|
Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_wb_inc_reg/C
|
|
(rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_block_r_reg[940]/D
|
|
(rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Path Group: sys_clk
|
|
Path Type: Setup (Max at Slow Process Corner)
|
|
Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns)
|
|
Data Path Delay: 19.340ns (logic 0.818ns (4.230%) route 18.522ns (95.770%))
|
|
Logic Levels: 2 (LUT4=1 MUXF7=1)
|
|
Clock Path Skew: -0.321ns (DCD - SCD + CPR)
|
|
Destination Clock Delay (DCD): -2.301ns = ( 17.699 - 20.000 )
|
|
Source Clock Delay (SCD): -2.487ns
|
|
Clock Pessimism Removal (CPR): -0.507ns
|
|
Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Discrete Jitter (DJ): 0.122ns
|
|
Phase Error (PE): 0.000ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock sys_clk rise edge) 0.000 0.000 r
|
|
clock source latency -6.275 -6.275
|
|
propagated clock network latency
|
|
3.789 -2.487
|
|
SLICE_X123Y83 FDRE 0.000 -2.487 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_wb_inc_reg/C
|
|
SLICE_X123Y83 FDRE (Prop_fdre_C_Q) 0.456 -2.031 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_wb_inc_reg/Q
|
|
net (fo=1088, routed) 18.522 16.492 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_c_in_bram/dj_block_r_reg[902]_3
|
|
SLICE_X79Y145 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_c_in_bram/dj_block_r[940]_i_2/I2
|
|
SLICE_X79Y145 LUT4 (Prop_lut4_I2_O) 0.124 16.616 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_c_in_bram/dj_block_r[940]_i_2/O
|
|
net (fo=1, routed) 0.000 16.616 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_c_in_bram/dj_block_r[940]_i_2_n_0
|
|
SLICE_X79Y145 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_c_in_bram/dj_block_r_reg[940]_i_1/I0
|
|
SLICE_X79Y145 MUXF7 (Prop_muxf7_I0_O) 0.238 16.854 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_c_in_bram/dj_block_r_reg[940]_i_1/O
|
|
net (fo=1, routed) 0.000 16.854 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_c_in_bram_n_177
|
|
SLICE_X79Y145 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_block_r_reg[940]/D
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock sys_clk rise edge) 20.000 20.000 r
|
|
clock source latency -5.674 14.326
|
|
propagated clock network latency
|
|
3.373 17.699
|
|
clock pessimism -0.507 17.192
|
|
clock uncertainty -0.071 17.122
|
|
SLICE_X79Y145 FDCE (Setup_fdce_C_D) 0.064 17.186 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_block_r_reg[940]
|
|
-------------------------------------------------------------------
|
|
required time 17.186
|
|
arrival time -16.854
|
|
-------------------------------------------------------------------
|
|
slack 0.332
|
|
|
|
Slack (MET) : 0.332ns (required time - arrival time)
|
|
Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_wb_inc_reg/C
|
|
(rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_block_r_reg[940]/D
|
|
(rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Path Group: sys_clk
|
|
Path Type: Setup (Max at Slow Process Corner)
|
|
Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns)
|
|
Data Path Delay: 19.340ns (logic 0.818ns (4.230%) route 18.522ns (95.770%))
|
|
Logic Levels: 2 (LUT4=1 MUXF7=1)
|
|
Clock Path Skew: -0.321ns (DCD - SCD + CPR)
|
|
Destination Clock Delay (DCD): -2.301ns = ( 17.699 - 20.000 )
|
|
Source Clock Delay (SCD): -2.487ns
|
|
Clock Pessimism Removal (CPR): -0.507ns
|
|
Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Discrete Jitter (DJ): 0.122ns
|
|
Phase Error (PE): 0.000ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock sys_clk rise edge) 0.000 0.000 r
|
|
clock source latency -6.275 -6.275
|
|
propagated clock network latency
|
|
3.789 -2.487
|
|
SLICE_X123Y83 FDRE 0.000 -2.487 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_wb_inc_reg/C
|
|
SLICE_X123Y83 FDRE (Prop_fdre_C_Q) 0.456 -2.031 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_wb_inc_reg/Q
|
|
net (fo=1088, routed) 18.522 16.492 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_c_in_bram/dj_block_r_reg[902]_3
|
|
SLICE_X79Y145 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_c_in_bram/dj_block_r[940]_i_2/I2
|
|
SLICE_X79Y145 LUT4 (Prop_lut4_I2_O) 0.124 16.616 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_c_in_bram/dj_block_r[940]_i_2/O
|
|
net (fo=1, routed) 0.000 16.616 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_c_in_bram/dj_block_r[940]_i_2_n_0
|
|
SLICE_X79Y145 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_c_in_bram/dj_block_r_reg[940]_i_1/I0
|
|
SLICE_X79Y145 MUXF7 (Prop_muxf7_I0_O) 0.238 16.854 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_c_in_bram/dj_block_r_reg[940]_i_1/O
|
|
net (fo=1, routed) 0.000 16.854 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_c_in_bram_n_177
|
|
SLICE_X79Y145 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_block_r_reg[940]/D
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock sys_clk rise edge) 20.000 20.000 r
|
|
clock source latency -5.674 14.326
|
|
propagated clock network latency
|
|
3.373 17.699
|
|
clock pessimism -0.507 17.192
|
|
clock uncertainty -0.071 17.122
|
|
SLICE_X79Y145 FDCE (Setup_fdce_C_D) 0.064 17.186 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_block_r_reg[940]
|
|
-------------------------------------------------------------------
|
|
required time 17.186
|
|
arrival time -16.854
|
|
-------------------------------------------------------------------
|
|
slack 0.332
|
|
|
|
Slack (MET) : 0.332ns (required time - arrival time)
|
|
Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_wb_inc_reg/C
|
|
(rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_block_r_reg[940]/D
|
|
(rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Path Group: sys_clk
|
|
Path Type: Setup (Max at Slow Process Corner)
|
|
Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns)
|
|
Data Path Delay: 19.340ns (logic 0.818ns (4.230%) route 18.522ns (95.770%))
|
|
Logic Levels: 2 (LUT4=1 MUXF7=1)
|
|
Clock Path Skew: -0.321ns (DCD - SCD + CPR)
|
|
Destination Clock Delay (DCD): -2.301ns = ( 17.699 - 20.000 )
|
|
Source Clock Delay (SCD): -2.487ns
|
|
Clock Pessimism Removal (CPR): -0.507ns
|
|
Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Discrete Jitter (DJ): 0.122ns
|
|
Phase Error (PE): 0.000ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock sys_clk rise edge) 0.000 0.000 r
|
|
clock source latency -6.275 -6.275
|
|
propagated clock network latency
|
|
3.789 -2.487
|
|
SLICE_X123Y83 FDRE 0.000 -2.487 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_wb_inc_reg/C
|
|
SLICE_X123Y83 FDRE (Prop_fdre_C_Q) 0.456 -2.031 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_wb_inc_reg/Q
|
|
net (fo=1088, routed) 18.522 16.492 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_c_in_bram/dj_block_r_reg[902]_3
|
|
SLICE_X79Y145 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_c_in_bram/dj_block_r[940]_i_2/I2
|
|
SLICE_X79Y145 LUT4 (Prop_lut4_I2_O) 0.124 16.616 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_c_in_bram/dj_block_r[940]_i_2/O
|
|
net (fo=1, routed) 0.000 16.616 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_c_in_bram/dj_block_r[940]_i_2_n_0
|
|
SLICE_X79Y145 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_c_in_bram/dj_block_r_reg[940]_i_1/I0
|
|
SLICE_X79Y145 MUXF7 (Prop_muxf7_I0_O) 0.238 16.854 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_c_in_bram/dj_block_r_reg[940]_i_1/O
|
|
net (fo=1, routed) 0.000 16.854 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_c_in_bram_n_177
|
|
SLICE_X79Y145 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_block_r_reg[940]/D
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock sys_clk rise edge) 20.000 20.000 r
|
|
clock source latency -5.674 14.326
|
|
propagated clock network latency
|
|
3.373 17.699
|
|
clock pessimism -0.507 17.192
|
|
clock uncertainty -0.071 17.122
|
|
SLICE_X79Y145 FDCE (Setup_fdce_C_D) 0.064 17.186 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_block_r_reg[940]
|
|
-------------------------------------------------------------------
|
|
required time 17.186
|
|
arrival time -16.854
|
|
-------------------------------------------------------------------
|
|
slack 0.332
|
|
|
|
Slack (MET) : 0.344ns (required time - arrival time)
|
|
Source: u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[3]/C
|
|
(rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Destination: base_ram_data[0]
|
|
(output port clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Path Group: sys_clk
|
|
Path Type: Max at Slow Process Corner
|
|
Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns)
|
|
Data Path Delay: 15.331ns (logic 6.877ns (44.857%) route 8.454ns (55.143%))
|
|
Logic Levels: 14 (CARRY4=6 LUT3=1 LUT4=2 LUT5=1 LUT6=3 OBUFT=1)
|
|
Output Delay: 0.300ns
|
|
Clock Path Skew: -3.955ns (DCD - SCD + CPR)
|
|
Destination Clock Delay (DCD): -5.674ns = ( 14.326 - 20.000 )
|
|
Source Clock Delay (SCD): -2.321ns
|
|
Clock Pessimism Removal (CPR): -0.601ns
|
|
Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Discrete Jitter (DJ): 0.122ns
|
|
Phase Error (PE): 0.000ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock sys_clk rise edge) 0.000 0.000 r
|
|
clock source latency -6.275 -6.275
|
|
propagated clock network latency
|
|
3.955 -2.321
|
|
SLICE_X7Y62 FDCE 0.000 -2.321 r u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[3]/C
|
|
SLICE_X7Y62 FDCE (Prop_fdce_C_Q) 0.456 -1.865 f u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[3]/Q
|
|
net (fo=54, routed) 0.726 -1.139 u_axi_ram/u_axi_sram_sp/len[3]
|
|
SLICE_X7Y61 f u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6/I3
|
|
SLICE_X7Y61 LUT4 (Prop_lut4_I3_O) 0.124 -1.015 r u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6/O
|
|
net (fo=4, routed) 0.946 -0.068 u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6_n_0
|
|
SLICE_X7Y58 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_11/I1
|
|
SLICE_X7Y58 LUT5 (Prop_lut5_I1_O) 0.124 0.056 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_11/O
|
|
net (fo=2, routed) 0.619 0.675 u_axi_ram/u_axi_sram_sp/state_d2[7]
|
|
SLICE_X6Y59 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_15/I5
|
|
SLICE_X6Y59 LUT6 (Prop_lut6_I5_O) 0.124 0.799 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_15/O
|
|
net (fo=1, routed) 0.000 0.799 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_15_n_0
|
|
SLICE_X6Y59 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9/S[3]
|
|
SLICE_X6Y59 CARRY4 (Prop_carry4_S[3]_CO[3])
|
|
0.376 1.175 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9/CO[3]
|
|
net (fo=1, routed) 0.000 1.175 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9_n_0
|
|
SLICE_X6Y60 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/CI
|
|
SLICE_X6Y60 CARRY4 (Prop_carry4_CI_CO[3])
|
|
0.117 1.292 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/CO[3]
|
|
net (fo=1, routed) 0.000 1.292 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10_n_0
|
|
SLICE_X6Y61 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CI
|
|
SLICE_X6Y61 CARRY4 (Prop_carry4_CI_CO[3])
|
|
0.117 1.409 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CO[3]
|
|
net (fo=1, routed) 0.000 1.409 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9_n_0
|
|
SLICE_X6Y62 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/CI
|
|
SLICE_X6Y62 CARRY4 (Prop_carry4_CI_O[2])
|
|
0.239 1.648 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/O[2]
|
|
net (fo=3, routed) 0.929 2.576 u_axi_ram/u_axi_sram_sp/upper_wrap_boundary[20]
|
|
SLICE_X5Y65 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_7/I2
|
|
SLICE_X5Y65 LUT4 (Prop_lut4_I2_O) 0.301 2.877 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_7/O
|
|
net (fo=1, routed) 0.000 2.877 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_7_n_0
|
|
SLICE_X5Y65 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1/S[1]
|
|
SLICE_X5Y65 CARRY4 (Prop_carry4_S[1]_CO[3])
|
|
0.550 3.427 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1/CO[3]
|
|
net (fo=1, routed) 0.000 3.427 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_n_0
|
|
SLICE_X5Y66 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2/CI
|
|
SLICE_X5Y66 CARRY4 (Prop_carry4_CI_CO[2])
|
|
0.228 3.655 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2/CO[2]
|
|
net (fo=22, routed) 0.735 4.390 u_axi_ram/u_axi_sram_sp/req_addr_d1
|
|
SLICE_X5Y68 r u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/I0
|
|
SLICE_X5Y68 LUT6 (Prop_lut6_I0_O) 0.313 4.703 f u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/O
|
|
net (fo=2, routed) 0.550 5.253 u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7_n_0
|
|
SLICE_X4Y68 f u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/I1
|
|
SLICE_X4Y68 LUT6 (Prop_lut6_I1_O) 0.124 5.377 f u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/O
|
|
net (fo=80, routed) 0.877 6.254 u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/soc_sram_addr[0]
|
|
SLICE_X1Y74 f u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/base_ram_data_IOBUF[31]_inst_i_3/I2
|
|
SLICE_X1Y74 LUT3 (Prop_lut3_I2_O) 0.124 6.378 f u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/base_ram_data_IOBUF[31]_inst_i_3/O
|
|
net (fo=32, routed) 3.072 9.450 base_ram_data_IOBUF[0]_inst/T
|
|
L24 f base_ram_data_IOBUF[0]_inst/OBUFT/T
|
|
L24 OBUFT (TriStatE_obuft_T_O)
|
|
3.560 13.010 r base_ram_data_IOBUF[0]_inst/OBUFT/O
|
|
net (fo=1, unset) 0.000 13.010 base_ram_data[0]
|
|
L24 r base_ram_data[0] (INOUT)
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock sys_clk rise edge) 20.000 20.000 r
|
|
clock source latency -5.674 14.326
|
|
propagated clock network latency
|
|
0.000 14.326
|
|
clock pessimism -0.601 13.725
|
|
clock uncertainty -0.071 13.654
|
|
output delay -0.300 13.354
|
|
-------------------------------------------------------------------
|
|
required time 13.354
|
|
arrival time -13.010
|
|
-------------------------------------------------------------------
|
|
slack 0.344
|
|
|
|
Slack (MET) : 0.344ns (required time - arrival time)
|
|
Source: u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[3]/C
|
|
(rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Destination: base_ram_data[0]
|
|
(output port clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Path Group: sys_clk
|
|
Path Type: Max at Slow Process Corner
|
|
Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns)
|
|
Data Path Delay: 15.331ns (logic 6.877ns (44.857%) route 8.454ns (55.143%))
|
|
Logic Levels: 14 (CARRY4=6 LUT3=1 LUT4=2 LUT5=1 LUT6=3 OBUFT=1)
|
|
Output Delay: 0.300ns
|
|
Clock Path Skew: -3.955ns (DCD - SCD + CPR)
|
|
Destination Clock Delay (DCD): -5.674ns = ( 14.326 - 20.000 )
|
|
Source Clock Delay (SCD): -2.321ns
|
|
Clock Pessimism Removal (CPR): -0.601ns
|
|
Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Discrete Jitter (DJ): 0.122ns
|
|
Phase Error (PE): 0.000ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock sys_clk rise edge) 0.000 0.000 r
|
|
clock source latency -6.275 -6.275
|
|
propagated clock network latency
|
|
3.955 -2.321
|
|
SLICE_X7Y62 FDCE 0.000 -2.321 r u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[3]/C
|
|
SLICE_X7Y62 FDCE (Prop_fdce_C_Q) 0.456 -1.865 f u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[3]/Q
|
|
net (fo=54, routed) 0.726 -1.139 u_axi_ram/u_axi_sram_sp/len[3]
|
|
SLICE_X7Y61 f u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6/I3
|
|
SLICE_X7Y61 LUT4 (Prop_lut4_I3_O) 0.124 -1.015 r u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6/O
|
|
net (fo=4, routed) 0.946 -0.068 u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6_n_0
|
|
SLICE_X7Y58 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_11/I1
|
|
SLICE_X7Y58 LUT5 (Prop_lut5_I1_O) 0.124 0.056 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_11/O
|
|
net (fo=2, routed) 0.619 0.675 u_axi_ram/u_axi_sram_sp/state_d2[7]
|
|
SLICE_X6Y59 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_15/I5
|
|
SLICE_X6Y59 LUT6 (Prop_lut6_I5_O) 0.124 0.799 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_15/O
|
|
net (fo=1, routed) 0.000 0.799 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_15_n_0
|
|
SLICE_X6Y59 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9/S[3]
|
|
SLICE_X6Y59 CARRY4 (Prop_carry4_S[3]_CO[3])
|
|
0.376 1.175 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9/CO[3]
|
|
net (fo=1, routed) 0.000 1.175 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9_n_0
|
|
SLICE_X6Y60 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/CI
|
|
SLICE_X6Y60 CARRY4 (Prop_carry4_CI_CO[3])
|
|
0.117 1.292 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/CO[3]
|
|
net (fo=1, routed) 0.000 1.292 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10_n_0
|
|
SLICE_X6Y61 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CI
|
|
SLICE_X6Y61 CARRY4 (Prop_carry4_CI_CO[3])
|
|
0.117 1.409 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CO[3]
|
|
net (fo=1, routed) 0.000 1.409 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9_n_0
|
|
SLICE_X6Y62 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/CI
|
|
SLICE_X6Y62 CARRY4 (Prop_carry4_CI_O[2])
|
|
0.239 1.648 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/O[2]
|
|
net (fo=3, routed) 0.929 2.576 u_axi_ram/u_axi_sram_sp/upper_wrap_boundary[20]
|
|
SLICE_X5Y65 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_7/I2
|
|
SLICE_X5Y65 LUT4 (Prop_lut4_I2_O) 0.301 2.877 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_7/O
|
|
net (fo=1, routed) 0.000 2.877 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_7_n_0
|
|
SLICE_X5Y65 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1/S[1]
|
|
SLICE_X5Y65 CARRY4 (Prop_carry4_S[1]_CO[3])
|
|
0.550 3.427 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1/CO[3]
|
|
net (fo=1, routed) 0.000 3.427 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_n_0
|
|
SLICE_X5Y66 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2/CI
|
|
SLICE_X5Y66 CARRY4 (Prop_carry4_CI_CO[2])
|
|
0.228 3.655 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2/CO[2]
|
|
net (fo=22, routed) 0.735 4.390 u_axi_ram/u_axi_sram_sp/req_addr_d1
|
|
SLICE_X5Y68 r u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/I0
|
|
SLICE_X5Y68 LUT6 (Prop_lut6_I0_O) 0.313 4.703 f u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/O
|
|
net (fo=2, routed) 0.550 5.253 u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7_n_0
|
|
SLICE_X4Y68 f u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/I1
|
|
SLICE_X4Y68 LUT6 (Prop_lut6_I1_O) 0.124 5.377 f u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/O
|
|
net (fo=80, routed) 0.877 6.254 u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/soc_sram_addr[0]
|
|
SLICE_X1Y74 f u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/base_ram_data_IOBUF[31]_inst_i_3/I2
|
|
SLICE_X1Y74 LUT3 (Prop_lut3_I2_O) 0.124 6.378 f u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/base_ram_data_IOBUF[31]_inst_i_3/O
|
|
net (fo=32, routed) 3.072 9.450 base_ram_data_IOBUF[0]_inst/T
|
|
L24 f base_ram_data_IOBUF[0]_inst/OBUFT/T
|
|
L24 OBUFT (TriStatE_obuft_T_O)
|
|
3.560 13.010 r base_ram_data_IOBUF[0]_inst/OBUFT/O
|
|
net (fo=1, unset) 0.000 13.010 base_ram_data[0]
|
|
L24 r base_ram_data[0] (INOUT)
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock sys_clk rise edge) 20.000 20.000 r
|
|
clock source latency -5.674 14.326
|
|
propagated clock network latency
|
|
0.000 14.326
|
|
clock pessimism -0.601 13.725
|
|
clock uncertainty -0.071 13.654
|
|
output delay -0.300 13.354
|
|
-------------------------------------------------------------------
|
|
required time 13.354
|
|
arrival time -13.010
|
|
-------------------------------------------------------------------
|
|
slack 0.344
|
|
|
|
Slack (MET) : 0.344ns (required time - arrival time)
|
|
Source: u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[3]/C
|
|
(rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Destination: base_ram_data[0]
|
|
(output port clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Path Group: sys_clk
|
|
Path Type: Max at Slow Process Corner
|
|
Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns)
|
|
Data Path Delay: 15.331ns (logic 6.877ns (44.857%) route 8.454ns (55.143%))
|
|
Logic Levels: 14 (CARRY4=6 LUT3=1 LUT4=2 LUT5=1 LUT6=3 OBUFT=1)
|
|
Output Delay: 0.300ns
|
|
Clock Path Skew: -3.955ns (DCD - SCD + CPR)
|
|
Destination Clock Delay (DCD): -5.674ns = ( 14.326 - 20.000 )
|
|
Source Clock Delay (SCD): -2.321ns
|
|
Clock Pessimism Removal (CPR): -0.601ns
|
|
Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Discrete Jitter (DJ): 0.122ns
|
|
Phase Error (PE): 0.000ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock sys_clk rise edge) 0.000 0.000 r
|
|
clock source latency -6.275 -6.275
|
|
propagated clock network latency
|
|
3.955 -2.321
|
|
SLICE_X7Y62 FDCE 0.000 -2.321 r u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[3]/C
|
|
SLICE_X7Y62 FDCE (Prop_fdce_C_Q) 0.456 -1.865 f u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[3]/Q
|
|
net (fo=54, routed) 0.726 -1.139 u_axi_ram/u_axi_sram_sp/len[3]
|
|
SLICE_X7Y61 f u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6/I3
|
|
SLICE_X7Y61 LUT4 (Prop_lut4_I3_O) 0.124 -1.015 r u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6/O
|
|
net (fo=4, routed) 0.946 -0.068 u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6_n_0
|
|
SLICE_X7Y58 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_11/I1
|
|
SLICE_X7Y58 LUT5 (Prop_lut5_I1_O) 0.124 0.056 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_11/O
|
|
net (fo=2, routed) 0.619 0.675 u_axi_ram/u_axi_sram_sp/state_d2[7]
|
|
SLICE_X6Y59 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_15/I5
|
|
SLICE_X6Y59 LUT6 (Prop_lut6_I5_O) 0.124 0.799 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_15/O
|
|
net (fo=1, routed) 0.000 0.799 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_15_n_0
|
|
SLICE_X6Y59 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9/S[3]
|
|
SLICE_X6Y59 CARRY4 (Prop_carry4_S[3]_CO[3])
|
|
0.376 1.175 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9/CO[3]
|
|
net (fo=1, routed) 0.000 1.175 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9_n_0
|
|
SLICE_X6Y60 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/CI
|
|
SLICE_X6Y60 CARRY4 (Prop_carry4_CI_CO[3])
|
|
0.117 1.292 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/CO[3]
|
|
net (fo=1, routed) 0.000 1.292 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10_n_0
|
|
SLICE_X6Y61 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CI
|
|
SLICE_X6Y61 CARRY4 (Prop_carry4_CI_CO[3])
|
|
0.117 1.409 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CO[3]
|
|
net (fo=1, routed) 0.000 1.409 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9_n_0
|
|
SLICE_X6Y62 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/CI
|
|
SLICE_X6Y62 CARRY4 (Prop_carry4_CI_O[2])
|
|
0.239 1.648 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/O[2]
|
|
net (fo=3, routed) 0.929 2.576 u_axi_ram/u_axi_sram_sp/upper_wrap_boundary[20]
|
|
SLICE_X5Y65 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_7/I2
|
|
SLICE_X5Y65 LUT4 (Prop_lut4_I2_O) 0.301 2.877 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_7/O
|
|
net (fo=1, routed) 0.000 2.877 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_7_n_0
|
|
SLICE_X5Y65 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1/S[1]
|
|
SLICE_X5Y65 CARRY4 (Prop_carry4_S[1]_CO[3])
|
|
0.550 3.427 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1/CO[3]
|
|
net (fo=1, routed) 0.000 3.427 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_n_0
|
|
SLICE_X5Y66 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2/CI
|
|
SLICE_X5Y66 CARRY4 (Prop_carry4_CI_CO[2])
|
|
0.228 3.655 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2/CO[2]
|
|
net (fo=22, routed) 0.735 4.390 u_axi_ram/u_axi_sram_sp/req_addr_d1
|
|
SLICE_X5Y68 r u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/I0
|
|
SLICE_X5Y68 LUT6 (Prop_lut6_I0_O) 0.313 4.703 f u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/O
|
|
net (fo=2, routed) 0.550 5.253 u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7_n_0
|
|
SLICE_X4Y68 f u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/I1
|
|
SLICE_X4Y68 LUT6 (Prop_lut6_I1_O) 0.124 5.377 f u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/O
|
|
net (fo=80, routed) 0.877 6.254 u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/soc_sram_addr[0]
|
|
SLICE_X1Y74 f u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/base_ram_data_IOBUF[31]_inst_i_3/I2
|
|
SLICE_X1Y74 LUT3 (Prop_lut3_I2_O) 0.124 6.378 f u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/base_ram_data_IOBUF[31]_inst_i_3/O
|
|
net (fo=32, routed) 3.072 9.450 base_ram_data_IOBUF[0]_inst/T
|
|
L24 f base_ram_data_IOBUF[0]_inst/OBUFT/T
|
|
L24 OBUFT (TriStatE_obuft_T_O)
|
|
3.560 13.010 r base_ram_data_IOBUF[0]_inst/OBUFT/O
|
|
net (fo=1, unset) 0.000 13.010 base_ram_data[0]
|
|
L24 r base_ram_data[0] (INOUT)
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock sys_clk rise edge) 20.000 20.000 r
|
|
clock source latency -5.674 14.326
|
|
propagated clock network latency
|
|
0.000 14.326
|
|
clock pessimism -0.601 13.725
|
|
clock uncertainty -0.071 13.654
|
|
output delay -0.300 13.354
|
|
-------------------------------------------------------------------
|
|
required time 13.354
|
|
arrival time -13.010
|
|
-------------------------------------------------------------------
|
|
slack 0.344
|
|
|
|
Slack (MET) : 0.344ns (required time - arrival time)
|
|
Source: u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[3]/C
|
|
(rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Destination: base_ram_data[0]
|
|
(output port clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Path Group: sys_clk
|
|
Path Type: Max at Slow Process Corner
|
|
Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns)
|
|
Data Path Delay: 15.331ns (logic 6.877ns (44.857%) route 8.454ns (55.143%))
|
|
Logic Levels: 14 (CARRY4=6 LUT3=1 LUT4=2 LUT5=1 LUT6=3 OBUFT=1)
|
|
Output Delay: 0.300ns
|
|
Clock Path Skew: -3.955ns (DCD - SCD + CPR)
|
|
Destination Clock Delay (DCD): -5.674ns = ( 14.326 - 20.000 )
|
|
Source Clock Delay (SCD): -2.321ns
|
|
Clock Pessimism Removal (CPR): -0.601ns
|
|
Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Discrete Jitter (DJ): 0.122ns
|
|
Phase Error (PE): 0.000ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock sys_clk rise edge) 0.000 0.000 r
|
|
clock source latency -6.275 -6.275
|
|
propagated clock network latency
|
|
3.955 -2.321
|
|
SLICE_X7Y62 FDCE 0.000 -2.321 r u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[3]/C
|
|
SLICE_X7Y62 FDCE (Prop_fdce_C_Q) 0.456 -1.865 f u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[3]/Q
|
|
net (fo=54, routed) 0.726 -1.139 u_axi_ram/u_axi_sram_sp/len[3]
|
|
SLICE_X7Y61 f u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6/I3
|
|
SLICE_X7Y61 LUT4 (Prop_lut4_I3_O) 0.124 -1.015 r u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6/O
|
|
net (fo=4, routed) 0.946 -0.068 u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6_n_0
|
|
SLICE_X7Y58 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_11/I1
|
|
SLICE_X7Y58 LUT5 (Prop_lut5_I1_O) 0.124 0.056 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_11/O
|
|
net (fo=2, routed) 0.619 0.675 u_axi_ram/u_axi_sram_sp/state_d2[7]
|
|
SLICE_X6Y59 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_15/I5
|
|
SLICE_X6Y59 LUT6 (Prop_lut6_I5_O) 0.124 0.799 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_15/O
|
|
net (fo=1, routed) 0.000 0.799 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_15_n_0
|
|
SLICE_X6Y59 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9/S[3]
|
|
SLICE_X6Y59 CARRY4 (Prop_carry4_S[3]_CO[3])
|
|
0.376 1.175 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9/CO[3]
|
|
net (fo=1, routed) 0.000 1.175 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9_n_0
|
|
SLICE_X6Y60 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/CI
|
|
SLICE_X6Y60 CARRY4 (Prop_carry4_CI_CO[3])
|
|
0.117 1.292 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/CO[3]
|
|
net (fo=1, routed) 0.000 1.292 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10_n_0
|
|
SLICE_X6Y61 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CI
|
|
SLICE_X6Y61 CARRY4 (Prop_carry4_CI_CO[3])
|
|
0.117 1.409 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CO[3]
|
|
net (fo=1, routed) 0.000 1.409 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9_n_0
|
|
SLICE_X6Y62 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/CI
|
|
SLICE_X6Y62 CARRY4 (Prop_carry4_CI_O[2])
|
|
0.239 1.648 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/O[2]
|
|
net (fo=3, routed) 0.929 2.576 u_axi_ram/u_axi_sram_sp/upper_wrap_boundary[20]
|
|
SLICE_X5Y65 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_7/I2
|
|
SLICE_X5Y65 LUT4 (Prop_lut4_I2_O) 0.301 2.877 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_7/O
|
|
net (fo=1, routed) 0.000 2.877 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_7_n_0
|
|
SLICE_X5Y65 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1/S[1]
|
|
SLICE_X5Y65 CARRY4 (Prop_carry4_S[1]_CO[3])
|
|
0.550 3.427 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1/CO[3]
|
|
net (fo=1, routed) 0.000 3.427 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_n_0
|
|
SLICE_X5Y66 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2/CI
|
|
SLICE_X5Y66 CARRY4 (Prop_carry4_CI_CO[2])
|
|
0.228 3.655 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2/CO[2]
|
|
net (fo=22, routed) 0.735 4.390 u_axi_ram/u_axi_sram_sp/req_addr_d1
|
|
SLICE_X5Y68 r u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/I0
|
|
SLICE_X5Y68 LUT6 (Prop_lut6_I0_O) 0.313 4.703 f u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/O
|
|
net (fo=2, routed) 0.550 5.253 u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7_n_0
|
|
SLICE_X4Y68 f u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/I1
|
|
SLICE_X4Y68 LUT6 (Prop_lut6_I1_O) 0.124 5.377 f u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/O
|
|
net (fo=80, routed) 0.877 6.254 u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/soc_sram_addr[0]
|
|
SLICE_X1Y74 f u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/base_ram_data_IOBUF[31]_inst_i_3/I2
|
|
SLICE_X1Y74 LUT3 (Prop_lut3_I2_O) 0.124 6.378 f u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/base_ram_data_IOBUF[31]_inst_i_3/O
|
|
net (fo=32, routed) 3.072 9.450 base_ram_data_IOBUF[0]_inst/T
|
|
L24 f base_ram_data_IOBUF[0]_inst/OBUFT/T
|
|
L24 OBUFT (TriStatE_obuft_T_O)
|
|
3.560 13.010 r base_ram_data_IOBUF[0]_inst/OBUFT/O
|
|
net (fo=1, unset) 0.000 13.010 base_ram_data[0]
|
|
L24 r base_ram_data[0] (INOUT)
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock sys_clk rise edge) 20.000 20.000 r
|
|
clock source latency -5.674 14.326
|
|
propagated clock network latency
|
|
0.000 14.326
|
|
clock pessimism -0.601 13.725
|
|
clock uncertainty -0.071 13.654
|
|
output delay -0.300 13.354
|
|
-------------------------------------------------------------------
|
|
required time 13.354
|
|
arrival time -13.010
|
|
-------------------------------------------------------------------
|
|
slack 0.344
|
|
|
|
Slack (MET) : 1.509ns (required time - arrival time)
|
|
Source: u_cpu/addr_trans/data_vaddr_buffer_reg[14]/C
|
|
(rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns})
|
|
Destination: u_cpu/icache/data_ram_way[0].data_ram_bank[1].u/mem_reg_reg/ADDRARDADDR[7]
|
|
(rising edge-triggered cell RAMB18E1 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns})
|
|
Path Group: cpu_clk
|
|
Path Type: Setup (Max at Slow Process Corner)
|
|
Requirement: 30.323ns (cpu_clk rise@30.323ns - cpu_clk rise@0.000ns)
|
|
Data Path Delay: 28.188ns (logic 5.333ns (18.919%) route 22.855ns (81.081%))
|
|
Logic Levels: 26 (CARRY4=4 LUT3=2 LUT4=1 LUT5=2 LUT6=15 MUXF7=1 MUXF8=1)
|
|
Clock Path Skew: 0.014ns (DCD - SCD + CPR)
|
|
Destination Clock Delay (DCD): -1.792ns = ( 28.530 - 30.323 )
|
|
Source Clock Delay (SCD): -2.225ns
|
|
Clock Pessimism Removal (CPR): -0.418ns
|
|
Clock Uncertainty: 0.074ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Discrete Jitter (DJ): 0.130ns
|
|
Phase Error (PE): 0.000ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock cpu_clk rise edge) 0.000 0.000 r
|
|
clock source latency -6.275 -6.275
|
|
propagated clock network latency
|
|
4.051 -2.225
|
|
SLICE_X35Y35 FDRE 0.000 -2.225 r u_cpu/addr_trans/data_vaddr_buffer_reg[14]/C
|
|
SLICE_X35Y35 FDRE (Prop_fdre_C_Q) 0.456 -1.769 r u_cpu/addr_trans/data_vaddr_buffer_reg[14]/Q
|
|
net (fo=33, routed) 1.442 -0.326 u_cpu/addr_trans/tlb_entry/data_vaddr_buffer[2]
|
|
SLICE_X42Y40 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_226/I5
|
|
SLICE_X42Y40 LUT6 (Prop_lut6_I5_O) 0.124 -0.202 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_226/O
|
|
net (fo=1, routed) 0.000 -0.202 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_226_n_0
|
|
SLICE_X42Y40 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_111/S[0]
|
|
SLICE_X42Y40 CARRY4 (Prop_carry4_S[0]_CO[3])
|
|
0.513 0.311 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_111/CO[3]
|
|
net (fo=1, routed) 0.000 0.311 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_111_n_0
|
|
SLICE_X42Y41 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_32/CI
|
|
SLICE_X42Y41 CARRY4 (Prop_carry4_CI_CO[2])
|
|
0.229 0.540 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_32/CO[2]
|
|
net (fo=1, routed) 1.009 1.549 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_32_n_1
|
|
SLICE_X40Y47 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_9/I1
|
|
SLICE_X40Y47 LUT6 (Prop_lut6_I1_O) 0.310 1.859 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_9/O
|
|
net (fo=2, routed) 0.635 2.494 u_cpu/addr_trans/tlb_entry/match1[28]
|
|
SLICE_X38Y47 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/I2
|
|
SLICE_X38Y47 LUT4 (Prop_lut4_I2_O) 0.124 2.618 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/O
|
|
net (fo=2, routed) 0.667 3.285 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2_n_0
|
|
SLICE_X39Y47 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/I0
|
|
SLICE_X39Y47 LUT5 (Prop_lut5_I0_O) 0.124 3.409 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/O
|
|
net (fo=2, routed) 1.103 4.512 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2_n_0
|
|
SLICE_X38Y50 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/I0
|
|
SLICE_X38Y50 LUT6 (Prop_lut6_I0_O) 0.124 4.636 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/O
|
|
net (fo=89, routed) 1.162 5.797 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus[8]
|
|
SLICE_X42Y51 r u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_38__0/S
|
|
SLICE_X42Y51 MUXF7 (Prop_muxf7_S_O) 0.292 6.089 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_38__0/O
|
|
net (fo=1, routed) 0.000 6.089 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_38__0_n_0
|
|
SLICE_X42Y51 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_16__0/I1
|
|
SLICE_X42Y51 MUXF8 (Prop_muxf8_I1_O) 0.088 6.177 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_16__0/O
|
|
net (fo=1, routed) 0.957 7.134 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_16__0_n_0
|
|
SLICE_X42Y50 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7/I0
|
|
SLICE_X42Y50 LUT6 (Prop_lut6_I0_O) 0.319 7.453 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7/O
|
|
net (fo=1, routed) 0.435 7.888 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7_n_0
|
|
SLICE_X44Y50 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0/I5
|
|
SLICE_X44Y50 LUT6 (Prop_lut6_I5_O) 0.124 8.012 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0/O
|
|
net (fo=10, routed) 0.740 8.753 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0_n_0
|
|
SLICE_X44Y50 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[5]_i_1__0/I3
|
|
SLICE_X44Y50 LUT6 (Prop_lut6_I3_O) 0.124 8.877 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[5]_i_1__0/O
|
|
net (fo=6, routed) 0.845 9.722 u_cpu/u_csr/ms_to_ws_bus[13]
|
|
SLICE_X50Y46 r u_cpu/u_csr/write_buffer_way[1]_i_18/I3
|
|
SLICE_X50Y46 LUT6 (Prop_lut6_I3_O) 0.124 9.846 r u_cpu/u_csr/write_buffer_way[1]_i_18/O
|
|
net (fo=1, routed) 0.000 9.846 u_cpu/u_csr/write_buffer_way[1]_i_18_n_0
|
|
SLICE_X50Y46 r u_cpu/u_csr/write_buffer_way_reg[1]_i_11/S[0]
|
|
SLICE_X50Y46 CARRY4 (Prop_carry4_S[0]_CO[3])
|
|
0.532 10.378 r u_cpu/u_csr/write_buffer_way_reg[1]_i_11/CO[3]
|
|
net (fo=1, routed) 0.000 10.378 u_cpu/u_csr/write_buffer_way_reg[1]_i_11_n_0
|
|
SLICE_X50Y47 r u_cpu/u_csr/write_buffer_way_reg[1]_i_9/CI
|
|
SLICE_X50Y47 CARRY4 (Prop_carry4_CI_CO[1])
|
|
0.157 10.535 f u_cpu/u_csr/write_buffer_way_reg[1]_i_9/CO[1]
|
|
net (fo=2, routed) 0.791 11.326 u_cpu/wb_stage/CO[0]
|
|
SLICE_X46Y39 f u_cpu/wb_stage/write_buffer_way[1]_i_5/I1
|
|
SLICE_X46Y39 LUT6 (Prop_lut6_I1_O) 0.329 11.655 r u_cpu/wb_stage/write_buffer_way[1]_i_5/O
|
|
net (fo=7, routed) 0.762 12.417 u_cpu/addr_trans/tlb_entry/sc_cancel_req
|
|
SLICE_X46Y35 r u_cpu/addr_trans/tlb_entry/main_state[0]_i_3/I1
|
|
SLICE_X46Y35 LUT3 (Prop_lut3_I1_O) 0.124 12.541 r u_cpu/addr_trans/tlb_entry/main_state[0]_i_3/O
|
|
net (fo=3, routed) 0.719 13.260 u_cpu/dcache/main_state_reg[0]_2
|
|
SLICE_X43Y31 r u_cpu/dcache/ds_to_es_bus_r[235]_i_10/I3
|
|
SLICE_X43Y31 LUT6 (Prop_lut6_I3_O) 0.124 13.384 r u_cpu/dcache/ds_to_es_bus_r[235]_i_10/O
|
|
net (fo=3, routed) 0.415 13.799 u_cpu/mem_stage/data_data_ok
|
|
SLICE_X43Y30 r u_cpu/mem_stage/flush_inst_req_buffer[1]_i_15/I0
|
|
SLICE_X43Y30 LUT3 (Prop_lut3_I0_O) 0.124 13.923 r u_cpu/mem_stage/flush_inst_req_buffer[1]_i_15/O
|
|
net (fo=2, routed) 0.833 14.756 u_cpu/mem_stage/es_to_ms_bus_r_reg[70]_1
|
|
SLICE_X48Y30 r u_cpu/mem_stage/flush_inst_req_buffer[1]_i_14/I0
|
|
SLICE_X48Y30 LUT6 (Prop_lut6_I0_O) 0.124 14.880 r u_cpu/mem_stage/flush_inst_req_buffer[1]_i_14/O
|
|
net (fo=1, routed) 0.651 15.532 u_cpu/mem_stage/ms_ready_go
|
|
SLICE_X48Y25 r u_cpu/mem_stage/flush_inst_req_buffer[1]_i_13/I4
|
|
SLICE_X48Y25 LUT6 (Prop_lut6_I4_O) 0.124 15.656 r u_cpu/mem_stage/flush_inst_req_buffer[1]_i_13/O
|
|
net (fo=3, routed) 0.483 16.139 u_cpu/id_stage/flush_inst_req_buffer[31]_i_6
|
|
SLICE_X50Y25 r u_cpu/id_stage/flush_inst_req_buffer[1]_i_9/I1
|
|
SLICE_X50Y25 LUT6 (Prop_lut6_I1_O) 0.124 16.263 r u_cpu/id_stage/flush_inst_req_buffer[1]_i_9/O
|
|
net (fo=32, routed) 0.531 16.794 u_cpu/if_stage/nextpc5
|
|
SLICE_X51Y27 r u_cpu/if_stage/fetch_pc_r[6]_i_4/I2
|
|
SLICE_X51Y27 LUT6 (Prop_lut6_I2_O) 0.124 16.918 r u_cpu/if_stage/fetch_pc_r[6]_i_4/O
|
|
net (fo=1, routed) 3.059 19.977 u_cpu/if_stage/fetch_pc_r[6]_i_4_n_0
|
|
SLICE_X114Y28 r u_cpu/if_stage/fetch_pc_r[6]_i_2/I2
|
|
SLICE_X114Y28 LUT6 (Prop_lut6_I2_O) 0.124 20.101 r u_cpu/if_stage/fetch_pc_r[6]_i_2/O
|
|
net (fo=1, routed) 0.441 20.542 u_cpu/if_stage/fetch_pc_r[6]_i_2_n_0
|
|
SLICE_X114Y25 r u_cpu/if_stage/fetch_pc_r[6]_i_1/I2
|
|
SLICE_X114Y25 LUT6 (Prop_lut6_I2_O) 0.124 20.666 r u_cpu/if_stage/fetch_pc_r[6]_i_1/O
|
|
net (fo=6, routed) 3.249 23.915 u_cpu/icache/tagv_ram_way[1].u/mem_reg_reg_2[2]
|
|
SLICE_X49Y33 r u_cpu/icache/tagv_ram_way[1].u/mem_reg_reg_i_8/I4
|
|
SLICE_X49Y33 LUT5 (Prop_lut5_I4_O) 0.124 24.039 r u_cpu/icache/tagv_ram_way[1].u/mem_reg_reg_i_8/O
|
|
net (fo=16, routed) 1.924 25.963 u_cpu/icache/data_ram_way[0].data_ram_bank[1].u/ADDRBWRADDR[2]
|
|
RAMB18_X1Y3 RAMB18E1 r u_cpu/icache/data_ram_way[0].data_ram_bank[1].u/mem_reg_reg/ADDRARDADDR[7]
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock cpu_clk rise edge) 30.323 30.323 r
|
|
clock source latency -5.674 24.648
|
|
propagated clock network latency
|
|
3.882 28.530
|
|
clock pessimism -0.418 28.112
|
|
clock uncertainty -0.074 28.038
|
|
RAMB18_X1Y3 RAMB18E1 (Setup_ramb18e1_CLKARDCLK_ADDRARDADDR[7])
|
|
-0.566 27.472 u_cpu/icache/data_ram_way[0].data_ram_bank[1].u/mem_reg_reg
|
|
-------------------------------------------------------------------
|
|
required time 27.472
|
|
arrival time -25.963
|
|
-------------------------------------------------------------------
|
|
slack 1.509
|
|
|
|
Slack (MET) : 1.509ns (required time - arrival time)
|
|
Source: u_cpu/addr_trans/data_vaddr_buffer_reg[14]/C
|
|
(rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns})
|
|
Destination: u_cpu/icache/data_ram_way[0].data_ram_bank[1].u/mem_reg_reg/ADDRARDADDR[7]
|
|
(rising edge-triggered cell RAMB18E1 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns})
|
|
Path Group: cpu_clk
|
|
Path Type: Setup (Max at Slow Process Corner)
|
|
Requirement: 30.323ns (cpu_clk rise@30.323ns - cpu_clk rise@0.000ns)
|
|
Data Path Delay: 28.188ns (logic 5.333ns (18.919%) route 22.855ns (81.081%))
|
|
Logic Levels: 26 (CARRY4=4 LUT3=2 LUT4=1 LUT5=2 LUT6=15 MUXF7=1 MUXF8=1)
|
|
Clock Path Skew: 0.014ns (DCD - SCD + CPR)
|
|
Destination Clock Delay (DCD): -1.792ns = ( 28.530 - 30.323 )
|
|
Source Clock Delay (SCD): -2.225ns
|
|
Clock Pessimism Removal (CPR): -0.418ns
|
|
Clock Uncertainty: 0.074ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Discrete Jitter (DJ): 0.130ns
|
|
Phase Error (PE): 0.000ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock cpu_clk rise edge) 0.000 0.000 r
|
|
clock source latency -6.275 -6.275
|
|
propagated clock network latency
|
|
4.051 -2.225
|
|
SLICE_X35Y35 FDRE 0.000 -2.225 r u_cpu/addr_trans/data_vaddr_buffer_reg[14]/C
|
|
SLICE_X35Y35 FDRE (Prop_fdre_C_Q) 0.456 -1.769 r u_cpu/addr_trans/data_vaddr_buffer_reg[14]/Q
|
|
net (fo=33, routed) 1.442 -0.326 u_cpu/addr_trans/tlb_entry/data_vaddr_buffer[2]
|
|
SLICE_X42Y40 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_226/I5
|
|
SLICE_X42Y40 LUT6 (Prop_lut6_I5_O) 0.124 -0.202 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_226/O
|
|
net (fo=1, routed) 0.000 -0.202 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_226_n_0
|
|
SLICE_X42Y40 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_111/S[0]
|
|
SLICE_X42Y40 CARRY4 (Prop_carry4_S[0]_CO[3])
|
|
0.513 0.311 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_111/CO[3]
|
|
net (fo=1, routed) 0.000 0.311 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_111_n_0
|
|
SLICE_X42Y41 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_32/CI
|
|
SLICE_X42Y41 CARRY4 (Prop_carry4_CI_CO[2])
|
|
0.229 0.540 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_32/CO[2]
|
|
net (fo=1, routed) 1.009 1.549 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_32_n_1
|
|
SLICE_X40Y47 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_9/I1
|
|
SLICE_X40Y47 LUT6 (Prop_lut6_I1_O) 0.310 1.859 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_9/O
|
|
net (fo=2, routed) 0.635 2.494 u_cpu/addr_trans/tlb_entry/match1[28]
|
|
SLICE_X38Y47 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/I2
|
|
SLICE_X38Y47 LUT4 (Prop_lut4_I2_O) 0.124 2.618 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/O
|
|
net (fo=2, routed) 0.667 3.285 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2_n_0
|
|
SLICE_X39Y47 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/I0
|
|
SLICE_X39Y47 LUT5 (Prop_lut5_I0_O) 0.124 3.409 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/O
|
|
net (fo=2, routed) 1.103 4.512 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2_n_0
|
|
SLICE_X38Y50 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/I0
|
|
SLICE_X38Y50 LUT6 (Prop_lut6_I0_O) 0.124 4.636 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/O
|
|
net (fo=89, routed) 1.162 5.797 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus[8]
|
|
SLICE_X42Y51 r u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_38__0/S
|
|
SLICE_X42Y51 MUXF7 (Prop_muxf7_S_O) 0.292 6.089 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_38__0/O
|
|
net (fo=1, routed) 0.000 6.089 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_38__0_n_0
|
|
SLICE_X42Y51 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_16__0/I1
|
|
SLICE_X42Y51 MUXF8 (Prop_muxf8_I1_O) 0.088 6.177 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_16__0/O
|
|
net (fo=1, routed) 0.957 7.134 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_16__0_n_0
|
|
SLICE_X42Y50 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7/I0
|
|
SLICE_X42Y50 LUT6 (Prop_lut6_I0_O) 0.319 7.453 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7/O
|
|
net (fo=1, routed) 0.435 7.888 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7_n_0
|
|
SLICE_X44Y50 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0/I5
|
|
SLICE_X44Y50 LUT6 (Prop_lut6_I5_O) 0.124 8.012 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0/O
|
|
net (fo=10, routed) 0.740 8.753 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0_n_0
|
|
SLICE_X44Y50 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[5]_i_1__0/I3
|
|
SLICE_X44Y50 LUT6 (Prop_lut6_I3_O) 0.124 8.877 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[5]_i_1__0/O
|
|
net (fo=6, routed) 0.845 9.722 u_cpu/u_csr/ms_to_ws_bus[13]
|
|
SLICE_X50Y46 f u_cpu/u_csr/write_buffer_way[1]_i_18/I3
|
|
SLICE_X50Y46 LUT6 (Prop_lut6_I3_O) 0.124 9.846 r u_cpu/u_csr/write_buffer_way[1]_i_18/O
|
|
net (fo=1, routed) 0.000 9.846 u_cpu/u_csr/write_buffer_way[1]_i_18_n_0
|
|
SLICE_X50Y46 r u_cpu/u_csr/write_buffer_way_reg[1]_i_11/S[0]
|
|
SLICE_X50Y46 CARRY4 (Prop_carry4_S[0]_CO[3])
|
|
0.532 10.378 r u_cpu/u_csr/write_buffer_way_reg[1]_i_11/CO[3]
|
|
net (fo=1, routed) 0.000 10.378 u_cpu/u_csr/write_buffer_way_reg[1]_i_11_n_0
|
|
SLICE_X50Y47 r u_cpu/u_csr/write_buffer_way_reg[1]_i_9/CI
|
|
SLICE_X50Y47 CARRY4 (Prop_carry4_CI_CO[1])
|
|
0.157 10.535 f u_cpu/u_csr/write_buffer_way_reg[1]_i_9/CO[1]
|
|
net (fo=2, routed) 0.791 11.326 u_cpu/wb_stage/CO[0]
|
|
SLICE_X46Y39 f u_cpu/wb_stage/write_buffer_way[1]_i_5/I1
|
|
SLICE_X46Y39 LUT6 (Prop_lut6_I1_O) 0.329 11.655 r u_cpu/wb_stage/write_buffer_way[1]_i_5/O
|
|
net (fo=7, routed) 0.762 12.417 u_cpu/addr_trans/tlb_entry/sc_cancel_req
|
|
SLICE_X46Y35 r u_cpu/addr_trans/tlb_entry/main_state[0]_i_3/I1
|
|
SLICE_X46Y35 LUT3 (Prop_lut3_I1_O) 0.124 12.541 r u_cpu/addr_trans/tlb_entry/main_state[0]_i_3/O
|
|
net (fo=3, routed) 0.719 13.260 u_cpu/dcache/main_state_reg[0]_2
|
|
SLICE_X43Y31 r u_cpu/dcache/ds_to_es_bus_r[235]_i_10/I3
|
|
SLICE_X43Y31 LUT6 (Prop_lut6_I3_O) 0.124 13.384 r u_cpu/dcache/ds_to_es_bus_r[235]_i_10/O
|
|
net (fo=3, routed) 0.415 13.799 u_cpu/mem_stage/data_data_ok
|
|
SLICE_X43Y30 r u_cpu/mem_stage/flush_inst_req_buffer[1]_i_15/I0
|
|
SLICE_X43Y30 LUT3 (Prop_lut3_I0_O) 0.124 13.923 r u_cpu/mem_stage/flush_inst_req_buffer[1]_i_15/O
|
|
net (fo=2, routed) 0.833 14.756 u_cpu/mem_stage/es_to_ms_bus_r_reg[70]_1
|
|
SLICE_X48Y30 r u_cpu/mem_stage/flush_inst_req_buffer[1]_i_14/I0
|
|
SLICE_X48Y30 LUT6 (Prop_lut6_I0_O) 0.124 14.880 r u_cpu/mem_stage/flush_inst_req_buffer[1]_i_14/O
|
|
net (fo=1, routed) 0.651 15.532 u_cpu/mem_stage/ms_ready_go
|
|
SLICE_X48Y25 r u_cpu/mem_stage/flush_inst_req_buffer[1]_i_13/I4
|
|
SLICE_X48Y25 LUT6 (Prop_lut6_I4_O) 0.124 15.656 r u_cpu/mem_stage/flush_inst_req_buffer[1]_i_13/O
|
|
net (fo=3, routed) 0.483 16.139 u_cpu/id_stage/flush_inst_req_buffer[31]_i_6
|
|
SLICE_X50Y25 r u_cpu/id_stage/flush_inst_req_buffer[1]_i_9/I1
|
|
SLICE_X50Y25 LUT6 (Prop_lut6_I1_O) 0.124 16.263 r u_cpu/id_stage/flush_inst_req_buffer[1]_i_9/O
|
|
net (fo=32, routed) 0.531 16.794 u_cpu/if_stage/nextpc5
|
|
SLICE_X51Y27 r u_cpu/if_stage/fetch_pc_r[6]_i_4/I2
|
|
SLICE_X51Y27 LUT6 (Prop_lut6_I2_O) 0.124 16.918 r u_cpu/if_stage/fetch_pc_r[6]_i_4/O
|
|
net (fo=1, routed) 3.059 19.977 u_cpu/if_stage/fetch_pc_r[6]_i_4_n_0
|
|
SLICE_X114Y28 r u_cpu/if_stage/fetch_pc_r[6]_i_2/I2
|
|
SLICE_X114Y28 LUT6 (Prop_lut6_I2_O) 0.124 20.101 r u_cpu/if_stage/fetch_pc_r[6]_i_2/O
|
|
net (fo=1, routed) 0.441 20.542 u_cpu/if_stage/fetch_pc_r[6]_i_2_n_0
|
|
SLICE_X114Y25 r u_cpu/if_stage/fetch_pc_r[6]_i_1/I2
|
|
SLICE_X114Y25 LUT6 (Prop_lut6_I2_O) 0.124 20.666 r u_cpu/if_stage/fetch_pc_r[6]_i_1/O
|
|
net (fo=6, routed) 3.249 23.915 u_cpu/icache/tagv_ram_way[1].u/mem_reg_reg_2[2]
|
|
SLICE_X49Y33 r u_cpu/icache/tagv_ram_way[1].u/mem_reg_reg_i_8/I4
|
|
SLICE_X49Y33 LUT5 (Prop_lut5_I4_O) 0.124 24.039 r u_cpu/icache/tagv_ram_way[1].u/mem_reg_reg_i_8/O
|
|
net (fo=16, routed) 1.924 25.963 u_cpu/icache/data_ram_way[0].data_ram_bank[1].u/ADDRBWRADDR[2]
|
|
RAMB18_X1Y3 RAMB18E1 r u_cpu/icache/data_ram_way[0].data_ram_bank[1].u/mem_reg_reg/ADDRARDADDR[7]
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock cpu_clk rise edge) 30.323 30.323 r
|
|
clock source latency -5.674 24.648
|
|
propagated clock network latency
|
|
3.882 28.530
|
|
clock pessimism -0.418 28.112
|
|
clock uncertainty -0.074 28.038
|
|
RAMB18_X1Y3 RAMB18E1 (Setup_ramb18e1_CLKARDCLK_ADDRARDADDR[7])
|
|
-0.566 27.472 u_cpu/icache/data_ram_way[0].data_ram_bank[1].u/mem_reg_reg
|
|
-------------------------------------------------------------------
|
|
required time 27.472
|
|
arrival time -25.963
|
|
-------------------------------------------------------------------
|
|
slack 1.509
|
|
|
|
Slack (MET) : 1.509ns (required time - arrival time)
|
|
Source: u_cpu/addr_trans/data_vaddr_buffer_reg[14]/C
|
|
(rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns})
|
|
Destination: u_cpu/icache/data_ram_way[0].data_ram_bank[1].u/mem_reg_reg/ADDRARDADDR[7]
|
|
(rising edge-triggered cell RAMB18E1 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns})
|
|
Path Group: cpu_clk
|
|
Path Type: Setup (Max at Slow Process Corner)
|
|
Requirement: 30.323ns (cpu_clk rise@30.323ns - cpu_clk rise@0.000ns)
|
|
Data Path Delay: 28.188ns (logic 5.333ns (18.919%) route 22.855ns (81.081%))
|
|
Logic Levels: 26 (CARRY4=4 LUT3=2 LUT4=1 LUT5=2 LUT6=15 MUXF7=1 MUXF8=1)
|
|
Clock Path Skew: 0.014ns (DCD - SCD + CPR)
|
|
Destination Clock Delay (DCD): -1.792ns = ( 28.530 - 30.323 )
|
|
Source Clock Delay (SCD): -2.225ns
|
|
Clock Pessimism Removal (CPR): -0.418ns
|
|
Clock Uncertainty: 0.074ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Discrete Jitter (DJ): 0.130ns
|
|
Phase Error (PE): 0.000ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock cpu_clk rise edge) 0.000 0.000 r
|
|
clock source latency -6.275 -6.275
|
|
propagated clock network latency
|
|
4.051 -2.225
|
|
SLICE_X35Y35 FDRE 0.000 -2.225 r u_cpu/addr_trans/data_vaddr_buffer_reg[14]/C
|
|
SLICE_X35Y35 FDRE (Prop_fdre_C_Q) 0.456 -1.769 r u_cpu/addr_trans/data_vaddr_buffer_reg[14]/Q
|
|
net (fo=33, routed) 1.442 -0.326 u_cpu/addr_trans/tlb_entry/data_vaddr_buffer[2]
|
|
SLICE_X42Y40 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_226/I5
|
|
SLICE_X42Y40 LUT6 (Prop_lut6_I5_O) 0.124 -0.202 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_226/O
|
|
net (fo=1, routed) 0.000 -0.202 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_226_n_0
|
|
SLICE_X42Y40 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_111/S[0]
|
|
SLICE_X42Y40 CARRY4 (Prop_carry4_S[0]_CO[3])
|
|
0.513 0.311 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_111/CO[3]
|
|
net (fo=1, routed) 0.000 0.311 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_111_n_0
|
|
SLICE_X42Y41 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_32/CI
|
|
SLICE_X42Y41 CARRY4 (Prop_carry4_CI_CO[2])
|
|
0.229 0.540 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_32/CO[2]
|
|
net (fo=1, routed) 1.009 1.549 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_32_n_1
|
|
SLICE_X40Y47 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_9/I1
|
|
SLICE_X40Y47 LUT6 (Prop_lut6_I1_O) 0.310 1.859 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_9/O
|
|
net (fo=2, routed) 0.635 2.494 u_cpu/addr_trans/tlb_entry/match1[28]
|
|
SLICE_X38Y47 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/I2
|
|
SLICE_X38Y47 LUT4 (Prop_lut4_I2_O) 0.124 2.618 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/O
|
|
net (fo=2, routed) 0.667 3.285 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2_n_0
|
|
SLICE_X39Y47 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/I0
|
|
SLICE_X39Y47 LUT5 (Prop_lut5_I0_O) 0.124 3.409 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/O
|
|
net (fo=2, routed) 1.103 4.512 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2_n_0
|
|
SLICE_X38Y50 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/I0
|
|
SLICE_X38Y50 LUT6 (Prop_lut6_I0_O) 0.124 4.636 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/O
|
|
net (fo=89, routed) 1.162 5.797 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus[8]
|
|
SLICE_X42Y51 r u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_38__0/S
|
|
SLICE_X42Y51 MUXF7 (Prop_muxf7_S_O) 0.292 6.089 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_38__0/O
|
|
net (fo=1, routed) 0.000 6.089 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_38__0_n_0
|
|
SLICE_X42Y51 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_16__0/I1
|
|
SLICE_X42Y51 MUXF8 (Prop_muxf8_I1_O) 0.088 6.177 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_16__0/O
|
|
net (fo=1, routed) 0.957 7.134 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_16__0_n_0
|
|
SLICE_X42Y50 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7/I0
|
|
SLICE_X42Y50 LUT6 (Prop_lut6_I0_O) 0.319 7.453 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7/O
|
|
net (fo=1, routed) 0.435 7.888 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7_n_0
|
|
SLICE_X44Y50 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0/I5
|
|
SLICE_X44Y50 LUT6 (Prop_lut6_I5_O) 0.124 8.012 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0/O
|
|
net (fo=10, routed) 0.740 8.753 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0_n_0
|
|
SLICE_X44Y50 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[5]_i_1__0/I3
|
|
SLICE_X44Y50 LUT6 (Prop_lut6_I3_O) 0.124 8.877 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[5]_i_1__0/O
|
|
net (fo=6, routed) 0.845 9.722 u_cpu/u_csr/ms_to_ws_bus[13]
|
|
SLICE_X50Y46 r u_cpu/u_csr/write_buffer_way[1]_i_18/I3
|
|
SLICE_X50Y46 LUT6 (Prop_lut6_I3_O) 0.124 9.846 f u_cpu/u_csr/write_buffer_way[1]_i_18/O
|
|
net (fo=1, routed) 0.000 9.846 u_cpu/u_csr/write_buffer_way[1]_i_18_n_0
|
|
SLICE_X50Y46 f u_cpu/u_csr/write_buffer_way_reg[1]_i_11/S[0]
|
|
SLICE_X50Y46 CARRY4 (Prop_carry4_S[0]_CO[3])
|
|
0.532 10.378 r u_cpu/u_csr/write_buffer_way_reg[1]_i_11/CO[3]
|
|
net (fo=1, routed) 0.000 10.378 u_cpu/u_csr/write_buffer_way_reg[1]_i_11_n_0
|
|
SLICE_X50Y47 r u_cpu/u_csr/write_buffer_way_reg[1]_i_9/CI
|
|
SLICE_X50Y47 CARRY4 (Prop_carry4_CI_CO[1])
|
|
0.157 10.535 f u_cpu/u_csr/write_buffer_way_reg[1]_i_9/CO[1]
|
|
net (fo=2, routed) 0.791 11.326 u_cpu/wb_stage/CO[0]
|
|
SLICE_X46Y39 f u_cpu/wb_stage/write_buffer_way[1]_i_5/I1
|
|
SLICE_X46Y39 LUT6 (Prop_lut6_I1_O) 0.329 11.655 r u_cpu/wb_stage/write_buffer_way[1]_i_5/O
|
|
net (fo=7, routed) 0.762 12.417 u_cpu/addr_trans/tlb_entry/sc_cancel_req
|
|
SLICE_X46Y35 r u_cpu/addr_trans/tlb_entry/main_state[0]_i_3/I1
|
|
SLICE_X46Y35 LUT3 (Prop_lut3_I1_O) 0.124 12.541 r u_cpu/addr_trans/tlb_entry/main_state[0]_i_3/O
|
|
net (fo=3, routed) 0.719 13.260 u_cpu/dcache/main_state_reg[0]_2
|
|
SLICE_X43Y31 r u_cpu/dcache/ds_to_es_bus_r[235]_i_10/I3
|
|
SLICE_X43Y31 LUT6 (Prop_lut6_I3_O) 0.124 13.384 r u_cpu/dcache/ds_to_es_bus_r[235]_i_10/O
|
|
net (fo=3, routed) 0.415 13.799 u_cpu/mem_stage/data_data_ok
|
|
SLICE_X43Y30 r u_cpu/mem_stage/flush_inst_req_buffer[1]_i_15/I0
|
|
SLICE_X43Y30 LUT3 (Prop_lut3_I0_O) 0.124 13.923 r u_cpu/mem_stage/flush_inst_req_buffer[1]_i_15/O
|
|
net (fo=2, routed) 0.833 14.756 u_cpu/mem_stage/es_to_ms_bus_r_reg[70]_1
|
|
SLICE_X48Y30 r u_cpu/mem_stage/flush_inst_req_buffer[1]_i_14/I0
|
|
SLICE_X48Y30 LUT6 (Prop_lut6_I0_O) 0.124 14.880 r u_cpu/mem_stage/flush_inst_req_buffer[1]_i_14/O
|
|
net (fo=1, routed) 0.651 15.532 u_cpu/mem_stage/ms_ready_go
|
|
SLICE_X48Y25 r u_cpu/mem_stage/flush_inst_req_buffer[1]_i_13/I4
|
|
SLICE_X48Y25 LUT6 (Prop_lut6_I4_O) 0.124 15.656 r u_cpu/mem_stage/flush_inst_req_buffer[1]_i_13/O
|
|
net (fo=3, routed) 0.483 16.139 u_cpu/id_stage/flush_inst_req_buffer[31]_i_6
|
|
SLICE_X50Y25 r u_cpu/id_stage/flush_inst_req_buffer[1]_i_9/I1
|
|
SLICE_X50Y25 LUT6 (Prop_lut6_I1_O) 0.124 16.263 r u_cpu/id_stage/flush_inst_req_buffer[1]_i_9/O
|
|
net (fo=32, routed) 0.531 16.794 u_cpu/if_stage/nextpc5
|
|
SLICE_X51Y27 r u_cpu/if_stage/fetch_pc_r[6]_i_4/I2
|
|
SLICE_X51Y27 LUT6 (Prop_lut6_I2_O) 0.124 16.918 r u_cpu/if_stage/fetch_pc_r[6]_i_4/O
|
|
net (fo=1, routed) 3.059 19.977 u_cpu/if_stage/fetch_pc_r[6]_i_4_n_0
|
|
SLICE_X114Y28 r u_cpu/if_stage/fetch_pc_r[6]_i_2/I2
|
|
SLICE_X114Y28 LUT6 (Prop_lut6_I2_O) 0.124 20.101 r u_cpu/if_stage/fetch_pc_r[6]_i_2/O
|
|
net (fo=1, routed) 0.441 20.542 u_cpu/if_stage/fetch_pc_r[6]_i_2_n_0
|
|
SLICE_X114Y25 r u_cpu/if_stage/fetch_pc_r[6]_i_1/I2
|
|
SLICE_X114Y25 LUT6 (Prop_lut6_I2_O) 0.124 20.666 r u_cpu/if_stage/fetch_pc_r[6]_i_1/O
|
|
net (fo=6, routed) 3.249 23.915 u_cpu/icache/tagv_ram_way[1].u/mem_reg_reg_2[2]
|
|
SLICE_X49Y33 r u_cpu/icache/tagv_ram_way[1].u/mem_reg_reg_i_8/I4
|
|
SLICE_X49Y33 LUT5 (Prop_lut5_I4_O) 0.124 24.039 r u_cpu/icache/tagv_ram_way[1].u/mem_reg_reg_i_8/O
|
|
net (fo=16, routed) 1.924 25.963 u_cpu/icache/data_ram_way[0].data_ram_bank[1].u/ADDRBWRADDR[2]
|
|
RAMB18_X1Y3 RAMB18E1 r u_cpu/icache/data_ram_way[0].data_ram_bank[1].u/mem_reg_reg/ADDRARDADDR[7]
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock cpu_clk rise edge) 30.323 30.323 r
|
|
clock source latency -5.674 24.648
|
|
propagated clock network latency
|
|
3.882 28.530
|
|
clock pessimism -0.418 28.112
|
|
clock uncertainty -0.074 28.038
|
|
RAMB18_X1Y3 RAMB18E1 (Setup_ramb18e1_CLKARDCLK_ADDRARDADDR[7])
|
|
-0.566 27.472 u_cpu/icache/data_ram_way[0].data_ram_bank[1].u/mem_reg_reg
|
|
-------------------------------------------------------------------
|
|
required time 27.472
|
|
arrival time -25.963
|
|
-------------------------------------------------------------------
|
|
slack 1.509
|
|
|
|
Slack (MET) : 1.509ns (required time - arrival time)
|
|
Source: u_cpu/addr_trans/data_vaddr_buffer_reg[14]/C
|
|
(rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns})
|
|
Destination: u_cpu/icache/data_ram_way[0].data_ram_bank[1].u/mem_reg_reg/ADDRARDADDR[7]
|
|
(rising edge-triggered cell RAMB18E1 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns})
|
|
Path Group: cpu_clk
|
|
Path Type: Setup (Max at Slow Process Corner)
|
|
Requirement: 30.323ns (cpu_clk rise@30.323ns - cpu_clk rise@0.000ns)
|
|
Data Path Delay: 28.188ns (logic 5.333ns (18.919%) route 22.855ns (81.081%))
|
|
Logic Levels: 26 (CARRY4=4 LUT3=2 LUT4=1 LUT5=2 LUT6=15 MUXF7=1 MUXF8=1)
|
|
Clock Path Skew: 0.014ns (DCD - SCD + CPR)
|
|
Destination Clock Delay (DCD): -1.792ns = ( 28.530 - 30.323 )
|
|
Source Clock Delay (SCD): -2.225ns
|
|
Clock Pessimism Removal (CPR): -0.418ns
|
|
Clock Uncertainty: 0.074ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Discrete Jitter (DJ): 0.130ns
|
|
Phase Error (PE): 0.000ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock cpu_clk rise edge) 0.000 0.000 r
|
|
clock source latency -6.275 -6.275
|
|
propagated clock network latency
|
|
4.051 -2.225
|
|
SLICE_X35Y35 FDRE 0.000 -2.225 r u_cpu/addr_trans/data_vaddr_buffer_reg[14]/C
|
|
SLICE_X35Y35 FDRE (Prop_fdre_C_Q) 0.456 -1.769 r u_cpu/addr_trans/data_vaddr_buffer_reg[14]/Q
|
|
net (fo=33, routed) 1.442 -0.326 u_cpu/addr_trans/tlb_entry/data_vaddr_buffer[2]
|
|
SLICE_X42Y40 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_226/I5
|
|
SLICE_X42Y40 LUT6 (Prop_lut6_I5_O) 0.124 -0.202 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_226/O
|
|
net (fo=1, routed) 0.000 -0.202 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_226_n_0
|
|
SLICE_X42Y40 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_111/S[0]
|
|
SLICE_X42Y40 CARRY4 (Prop_carry4_S[0]_CO[3])
|
|
0.513 0.311 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_111/CO[3]
|
|
net (fo=1, routed) 0.000 0.311 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_111_n_0
|
|
SLICE_X42Y41 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_32/CI
|
|
SLICE_X42Y41 CARRY4 (Prop_carry4_CI_CO[2])
|
|
0.229 0.540 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_32/CO[2]
|
|
net (fo=1, routed) 1.009 1.549 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_32_n_1
|
|
SLICE_X40Y47 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_9/I1
|
|
SLICE_X40Y47 LUT6 (Prop_lut6_I1_O) 0.310 1.859 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_9/O
|
|
net (fo=2, routed) 0.635 2.494 u_cpu/addr_trans/tlb_entry/match1[28]
|
|
SLICE_X38Y47 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/I2
|
|
SLICE_X38Y47 LUT4 (Prop_lut4_I2_O) 0.124 2.618 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/O
|
|
net (fo=2, routed) 0.667 3.285 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2_n_0
|
|
SLICE_X39Y47 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/I0
|
|
SLICE_X39Y47 LUT5 (Prop_lut5_I0_O) 0.124 3.409 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/O
|
|
net (fo=2, routed) 1.103 4.512 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2_n_0
|
|
SLICE_X38Y50 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/I0
|
|
SLICE_X38Y50 LUT6 (Prop_lut6_I0_O) 0.124 4.636 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/O
|
|
net (fo=89, routed) 1.162 5.797 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus[8]
|
|
SLICE_X42Y51 r u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_38__0/S
|
|
SLICE_X42Y51 MUXF7 (Prop_muxf7_S_O) 0.292 6.089 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_38__0/O
|
|
net (fo=1, routed) 0.000 6.089 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_38__0_n_0
|
|
SLICE_X42Y51 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_16__0/I1
|
|
SLICE_X42Y51 MUXF8 (Prop_muxf8_I1_O) 0.088 6.177 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_16__0/O
|
|
net (fo=1, routed) 0.957 7.134 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_16__0_n_0
|
|
SLICE_X42Y50 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7/I0
|
|
SLICE_X42Y50 LUT6 (Prop_lut6_I0_O) 0.319 7.453 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7/O
|
|
net (fo=1, routed) 0.435 7.888 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7_n_0
|
|
SLICE_X44Y50 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0/I5
|
|
SLICE_X44Y50 LUT6 (Prop_lut6_I5_O) 0.124 8.012 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0/O
|
|
net (fo=10, routed) 0.740 8.753 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0_n_0
|
|
SLICE_X44Y50 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[5]_i_1__0/I3
|
|
SLICE_X44Y50 LUT6 (Prop_lut6_I3_O) 0.124 8.877 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[5]_i_1__0/O
|
|
net (fo=6, routed) 0.845 9.722 u_cpu/u_csr/ms_to_ws_bus[13]
|
|
SLICE_X50Y46 f u_cpu/u_csr/write_buffer_way[1]_i_18/I3
|
|
SLICE_X50Y46 LUT6 (Prop_lut6_I3_O) 0.124 9.846 f u_cpu/u_csr/write_buffer_way[1]_i_18/O
|
|
net (fo=1, routed) 0.000 9.846 u_cpu/u_csr/write_buffer_way[1]_i_18_n_0
|
|
SLICE_X50Y46 f u_cpu/u_csr/write_buffer_way_reg[1]_i_11/S[0]
|
|
SLICE_X50Y46 CARRY4 (Prop_carry4_S[0]_CO[3])
|
|
0.532 10.378 r u_cpu/u_csr/write_buffer_way_reg[1]_i_11/CO[3]
|
|
net (fo=1, routed) 0.000 10.378 u_cpu/u_csr/write_buffer_way_reg[1]_i_11_n_0
|
|
SLICE_X50Y47 r u_cpu/u_csr/write_buffer_way_reg[1]_i_9/CI
|
|
SLICE_X50Y47 CARRY4 (Prop_carry4_CI_CO[1])
|
|
0.157 10.535 f u_cpu/u_csr/write_buffer_way_reg[1]_i_9/CO[1]
|
|
net (fo=2, routed) 0.791 11.326 u_cpu/wb_stage/CO[0]
|
|
SLICE_X46Y39 f u_cpu/wb_stage/write_buffer_way[1]_i_5/I1
|
|
SLICE_X46Y39 LUT6 (Prop_lut6_I1_O) 0.329 11.655 r u_cpu/wb_stage/write_buffer_way[1]_i_5/O
|
|
net (fo=7, routed) 0.762 12.417 u_cpu/addr_trans/tlb_entry/sc_cancel_req
|
|
SLICE_X46Y35 r u_cpu/addr_trans/tlb_entry/main_state[0]_i_3/I1
|
|
SLICE_X46Y35 LUT3 (Prop_lut3_I1_O) 0.124 12.541 r u_cpu/addr_trans/tlb_entry/main_state[0]_i_3/O
|
|
net (fo=3, routed) 0.719 13.260 u_cpu/dcache/main_state_reg[0]_2
|
|
SLICE_X43Y31 r u_cpu/dcache/ds_to_es_bus_r[235]_i_10/I3
|
|
SLICE_X43Y31 LUT6 (Prop_lut6_I3_O) 0.124 13.384 r u_cpu/dcache/ds_to_es_bus_r[235]_i_10/O
|
|
net (fo=3, routed) 0.415 13.799 u_cpu/mem_stage/data_data_ok
|
|
SLICE_X43Y30 r u_cpu/mem_stage/flush_inst_req_buffer[1]_i_15/I0
|
|
SLICE_X43Y30 LUT3 (Prop_lut3_I0_O) 0.124 13.923 r u_cpu/mem_stage/flush_inst_req_buffer[1]_i_15/O
|
|
net (fo=2, routed) 0.833 14.756 u_cpu/mem_stage/es_to_ms_bus_r_reg[70]_1
|
|
SLICE_X48Y30 r u_cpu/mem_stage/flush_inst_req_buffer[1]_i_14/I0
|
|
SLICE_X48Y30 LUT6 (Prop_lut6_I0_O) 0.124 14.880 r u_cpu/mem_stage/flush_inst_req_buffer[1]_i_14/O
|
|
net (fo=1, routed) 0.651 15.532 u_cpu/mem_stage/ms_ready_go
|
|
SLICE_X48Y25 r u_cpu/mem_stage/flush_inst_req_buffer[1]_i_13/I4
|
|
SLICE_X48Y25 LUT6 (Prop_lut6_I4_O) 0.124 15.656 r u_cpu/mem_stage/flush_inst_req_buffer[1]_i_13/O
|
|
net (fo=3, routed) 0.483 16.139 u_cpu/id_stage/flush_inst_req_buffer[31]_i_6
|
|
SLICE_X50Y25 r u_cpu/id_stage/flush_inst_req_buffer[1]_i_9/I1
|
|
SLICE_X50Y25 LUT6 (Prop_lut6_I1_O) 0.124 16.263 r u_cpu/id_stage/flush_inst_req_buffer[1]_i_9/O
|
|
net (fo=32, routed) 0.531 16.794 u_cpu/if_stage/nextpc5
|
|
SLICE_X51Y27 r u_cpu/if_stage/fetch_pc_r[6]_i_4/I2
|
|
SLICE_X51Y27 LUT6 (Prop_lut6_I2_O) 0.124 16.918 r u_cpu/if_stage/fetch_pc_r[6]_i_4/O
|
|
net (fo=1, routed) 3.059 19.977 u_cpu/if_stage/fetch_pc_r[6]_i_4_n_0
|
|
SLICE_X114Y28 r u_cpu/if_stage/fetch_pc_r[6]_i_2/I2
|
|
SLICE_X114Y28 LUT6 (Prop_lut6_I2_O) 0.124 20.101 r u_cpu/if_stage/fetch_pc_r[6]_i_2/O
|
|
net (fo=1, routed) 0.441 20.542 u_cpu/if_stage/fetch_pc_r[6]_i_2_n_0
|
|
SLICE_X114Y25 r u_cpu/if_stage/fetch_pc_r[6]_i_1/I2
|
|
SLICE_X114Y25 LUT6 (Prop_lut6_I2_O) 0.124 20.666 r u_cpu/if_stage/fetch_pc_r[6]_i_1/O
|
|
net (fo=6, routed) 3.249 23.915 u_cpu/icache/tagv_ram_way[1].u/mem_reg_reg_2[2]
|
|
SLICE_X49Y33 r u_cpu/icache/tagv_ram_way[1].u/mem_reg_reg_i_8/I4
|
|
SLICE_X49Y33 LUT5 (Prop_lut5_I4_O) 0.124 24.039 r u_cpu/icache/tagv_ram_way[1].u/mem_reg_reg_i_8/O
|
|
net (fo=16, routed) 1.924 25.963 u_cpu/icache/data_ram_way[0].data_ram_bank[1].u/ADDRBWRADDR[2]
|
|
RAMB18_X1Y3 RAMB18E1 r u_cpu/icache/data_ram_way[0].data_ram_bank[1].u/mem_reg_reg/ADDRARDADDR[7]
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock cpu_clk rise edge) 30.323 30.323 r
|
|
clock source latency -5.674 24.648
|
|
propagated clock network latency
|
|
3.882 28.530
|
|
clock pessimism -0.418 28.112
|
|
clock uncertainty -0.074 28.038
|
|
RAMB18_X1Y3 RAMB18E1 (Setup_ramb18e1_CLKARDCLK_ADDRARDADDR[7])
|
|
-0.566 27.472 u_cpu/icache/data_ram_way[0].data_ram_bank[1].u/mem_reg_reg
|
|
-------------------------------------------------------------------
|
|
required time 27.472
|
|
arrival time -25.963
|
|
-------------------------------------------------------------------
|
|
slack 1.509
|
|
|
|
Slack (MET) : 1.509ns (required time - arrival time)
|
|
Source: u_cpu/addr_trans/data_vaddr_buffer_reg[14]/C
|
|
(rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns})
|
|
Destination: u_cpu/icache/data_ram_way[0].data_ram_bank[1].u/mem_reg_reg/ADDRARDADDR[7]
|
|
(rising edge-triggered cell RAMB18E1 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns})
|
|
Path Group: cpu_clk
|
|
Path Type: Setup (Max at Slow Process Corner)
|
|
Requirement: 30.323ns (cpu_clk rise@30.323ns - cpu_clk rise@0.000ns)
|
|
Data Path Delay: 28.188ns (logic 5.333ns (18.919%) route 22.855ns (81.081%))
|
|
Logic Levels: 26 (CARRY4=4 LUT3=2 LUT4=1 LUT5=2 LUT6=15 MUXF7=1 MUXF8=1)
|
|
Clock Path Skew: 0.014ns (DCD - SCD + CPR)
|
|
Destination Clock Delay (DCD): -1.792ns = ( 28.530 - 30.323 )
|
|
Source Clock Delay (SCD): -2.225ns
|
|
Clock Pessimism Removal (CPR): -0.418ns
|
|
Clock Uncertainty: 0.074ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Discrete Jitter (DJ): 0.130ns
|
|
Phase Error (PE): 0.000ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock cpu_clk rise edge) 0.000 0.000 r
|
|
clock source latency -6.275 -6.275
|
|
propagated clock network latency
|
|
4.051 -2.225
|
|
SLICE_X35Y35 FDRE 0.000 -2.225 r u_cpu/addr_trans/data_vaddr_buffer_reg[14]/C
|
|
SLICE_X35Y35 FDRE (Prop_fdre_C_Q) 0.456 -1.769 r u_cpu/addr_trans/data_vaddr_buffer_reg[14]/Q
|
|
net (fo=33, routed) 1.442 -0.326 u_cpu/addr_trans/tlb_entry/data_vaddr_buffer[2]
|
|
SLICE_X42Y40 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_226/I5
|
|
SLICE_X42Y40 LUT6 (Prop_lut6_I5_O) 0.124 -0.202 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_226/O
|
|
net (fo=1, routed) 0.000 -0.202 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_226_n_0
|
|
SLICE_X42Y40 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_111/S[0]
|
|
SLICE_X42Y40 CARRY4 (Prop_carry4_S[0]_CO[3])
|
|
0.513 0.311 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_111/CO[3]
|
|
net (fo=1, routed) 0.000 0.311 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_111_n_0
|
|
SLICE_X42Y41 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_32/CI
|
|
SLICE_X42Y41 CARRY4 (Prop_carry4_CI_CO[2])
|
|
0.229 0.540 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_32/CO[2]
|
|
net (fo=1, routed) 1.009 1.549 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_32_n_1
|
|
SLICE_X40Y47 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_9/I1
|
|
SLICE_X40Y47 LUT6 (Prop_lut6_I1_O) 0.310 1.859 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_9/O
|
|
net (fo=2, routed) 0.635 2.494 u_cpu/addr_trans/tlb_entry/match1[28]
|
|
SLICE_X38Y47 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/I2
|
|
SLICE_X38Y47 LUT4 (Prop_lut4_I2_O) 0.124 2.618 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/O
|
|
net (fo=2, routed) 0.667 3.285 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2_n_0
|
|
SLICE_X39Y47 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/I0
|
|
SLICE_X39Y47 LUT5 (Prop_lut5_I0_O) 0.124 3.409 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/O
|
|
net (fo=2, routed) 1.103 4.512 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2_n_0
|
|
SLICE_X38Y50 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/I0
|
|
SLICE_X38Y50 LUT6 (Prop_lut6_I0_O) 0.124 4.636 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/O
|
|
net (fo=89, routed) 1.162 5.797 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus[8]
|
|
SLICE_X42Y51 r u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_38__0/S
|
|
SLICE_X42Y51 MUXF7 (Prop_muxf7_S_O) 0.292 6.089 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_38__0/O
|
|
net (fo=1, routed) 0.000 6.089 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_38__0_n_0
|
|
SLICE_X42Y51 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_16__0/I1
|
|
SLICE_X42Y51 MUXF8 (Prop_muxf8_I1_O) 0.088 6.177 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_16__0/O
|
|
net (fo=1, routed) 0.957 7.134 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_16__0_n_0
|
|
SLICE_X42Y50 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7/I0
|
|
SLICE_X42Y50 LUT6 (Prop_lut6_I0_O) 0.319 7.453 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7/O
|
|
net (fo=1, routed) 0.435 7.888 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7_n_0
|
|
SLICE_X44Y50 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0/I5
|
|
SLICE_X44Y50 LUT6 (Prop_lut6_I5_O) 0.124 8.012 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0/O
|
|
net (fo=10, routed) 0.740 8.753 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0_n_0
|
|
SLICE_X44Y50 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[5]_i_1__0/I3
|
|
SLICE_X44Y50 LUT6 (Prop_lut6_I3_O) 0.124 8.877 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[5]_i_1__0/O
|
|
net (fo=6, routed) 0.845 9.722 u_cpu/u_csr/ms_to_ws_bus[13]
|
|
SLICE_X50Y46 r u_cpu/u_csr/write_buffer_way[1]_i_18/I3
|
|
SLICE_X50Y46 LUT6 (Prop_lut6_I3_O) 0.124 9.846 r u_cpu/u_csr/write_buffer_way[1]_i_18/O
|
|
net (fo=1, routed) 0.000 9.846 u_cpu/u_csr/write_buffer_way[1]_i_18_n_0
|
|
SLICE_X50Y46 r u_cpu/u_csr/write_buffer_way_reg[1]_i_11/S[0]
|
|
SLICE_X50Y46 CARRY4 (Prop_carry4_S[0]_CO[3])
|
|
0.532 10.378 f u_cpu/u_csr/write_buffer_way_reg[1]_i_11/CO[3]
|
|
net (fo=1, routed) 0.000 10.378 u_cpu/u_csr/write_buffer_way_reg[1]_i_11_n_0
|
|
SLICE_X50Y47 f u_cpu/u_csr/write_buffer_way_reg[1]_i_9/CI
|
|
SLICE_X50Y47 CARRY4 (Prop_carry4_CI_CO[1])
|
|
0.157 10.535 f u_cpu/u_csr/write_buffer_way_reg[1]_i_9/CO[1]
|
|
net (fo=2, routed) 0.791 11.326 u_cpu/wb_stage/CO[0]
|
|
SLICE_X46Y39 f u_cpu/wb_stage/write_buffer_way[1]_i_5/I1
|
|
SLICE_X46Y39 LUT6 (Prop_lut6_I1_O) 0.329 11.655 r u_cpu/wb_stage/write_buffer_way[1]_i_5/O
|
|
net (fo=7, routed) 0.762 12.417 u_cpu/addr_trans/tlb_entry/sc_cancel_req
|
|
SLICE_X46Y35 r u_cpu/addr_trans/tlb_entry/main_state[0]_i_3/I1
|
|
SLICE_X46Y35 LUT3 (Prop_lut3_I1_O) 0.124 12.541 r u_cpu/addr_trans/tlb_entry/main_state[0]_i_3/O
|
|
net (fo=3, routed) 0.719 13.260 u_cpu/dcache/main_state_reg[0]_2
|
|
SLICE_X43Y31 r u_cpu/dcache/ds_to_es_bus_r[235]_i_10/I3
|
|
SLICE_X43Y31 LUT6 (Prop_lut6_I3_O) 0.124 13.384 r u_cpu/dcache/ds_to_es_bus_r[235]_i_10/O
|
|
net (fo=3, routed) 0.415 13.799 u_cpu/mem_stage/data_data_ok
|
|
SLICE_X43Y30 r u_cpu/mem_stage/flush_inst_req_buffer[1]_i_15/I0
|
|
SLICE_X43Y30 LUT3 (Prop_lut3_I0_O) 0.124 13.923 r u_cpu/mem_stage/flush_inst_req_buffer[1]_i_15/O
|
|
net (fo=2, routed) 0.833 14.756 u_cpu/mem_stage/es_to_ms_bus_r_reg[70]_1
|
|
SLICE_X48Y30 r u_cpu/mem_stage/flush_inst_req_buffer[1]_i_14/I0
|
|
SLICE_X48Y30 LUT6 (Prop_lut6_I0_O) 0.124 14.880 r u_cpu/mem_stage/flush_inst_req_buffer[1]_i_14/O
|
|
net (fo=1, routed) 0.651 15.532 u_cpu/mem_stage/ms_ready_go
|
|
SLICE_X48Y25 r u_cpu/mem_stage/flush_inst_req_buffer[1]_i_13/I4
|
|
SLICE_X48Y25 LUT6 (Prop_lut6_I4_O) 0.124 15.656 r u_cpu/mem_stage/flush_inst_req_buffer[1]_i_13/O
|
|
net (fo=3, routed) 0.483 16.139 u_cpu/id_stage/flush_inst_req_buffer[31]_i_6
|
|
SLICE_X50Y25 r u_cpu/id_stage/flush_inst_req_buffer[1]_i_9/I1
|
|
SLICE_X50Y25 LUT6 (Prop_lut6_I1_O) 0.124 16.263 r u_cpu/id_stage/flush_inst_req_buffer[1]_i_9/O
|
|
net (fo=32, routed) 0.531 16.794 u_cpu/if_stage/nextpc5
|
|
SLICE_X51Y27 r u_cpu/if_stage/fetch_pc_r[6]_i_4/I2
|
|
SLICE_X51Y27 LUT6 (Prop_lut6_I2_O) 0.124 16.918 r u_cpu/if_stage/fetch_pc_r[6]_i_4/O
|
|
net (fo=1, routed) 3.059 19.977 u_cpu/if_stage/fetch_pc_r[6]_i_4_n_0
|
|
SLICE_X114Y28 r u_cpu/if_stage/fetch_pc_r[6]_i_2/I2
|
|
SLICE_X114Y28 LUT6 (Prop_lut6_I2_O) 0.124 20.101 r u_cpu/if_stage/fetch_pc_r[6]_i_2/O
|
|
net (fo=1, routed) 0.441 20.542 u_cpu/if_stage/fetch_pc_r[6]_i_2_n_0
|
|
SLICE_X114Y25 r u_cpu/if_stage/fetch_pc_r[6]_i_1/I2
|
|
SLICE_X114Y25 LUT6 (Prop_lut6_I2_O) 0.124 20.666 r u_cpu/if_stage/fetch_pc_r[6]_i_1/O
|
|
net (fo=6, routed) 3.249 23.915 u_cpu/icache/tagv_ram_way[1].u/mem_reg_reg_2[2]
|
|
SLICE_X49Y33 r u_cpu/icache/tagv_ram_way[1].u/mem_reg_reg_i_8/I4
|
|
SLICE_X49Y33 LUT5 (Prop_lut5_I4_O) 0.124 24.039 r u_cpu/icache/tagv_ram_way[1].u/mem_reg_reg_i_8/O
|
|
net (fo=16, routed) 1.924 25.963 u_cpu/icache/data_ram_way[0].data_ram_bank[1].u/ADDRBWRADDR[2]
|
|
RAMB18_X1Y3 RAMB18E1 r u_cpu/icache/data_ram_way[0].data_ram_bank[1].u/mem_reg_reg/ADDRARDADDR[7]
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock cpu_clk rise edge) 30.323 30.323 r
|
|
clock source latency -5.674 24.648
|
|
propagated clock network latency
|
|
3.882 28.530
|
|
clock pessimism -0.418 28.112
|
|
clock uncertainty -0.074 28.038
|
|
RAMB18_X1Y3 RAMB18E1 (Setup_ramb18e1_CLKARDCLK_ADDRARDADDR[7])
|
|
-0.566 27.472 u_cpu/icache/data_ram_way[0].data_ram_bank[1].u/mem_reg_reg
|
|
-------------------------------------------------------------------
|
|
required time 27.472
|
|
arrival time -25.963
|
|
-------------------------------------------------------------------
|
|
slack 1.509
|
|
|
|
Slack (MET) : 1.509ns (required time - arrival time)
|
|
Source: u_cpu/addr_trans/data_vaddr_buffer_reg[14]/C
|
|
(rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns})
|
|
Destination: u_cpu/icache/data_ram_way[0].data_ram_bank[1].u/mem_reg_reg/ADDRARDADDR[7]
|
|
(rising edge-triggered cell RAMB18E1 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns})
|
|
Path Group: cpu_clk
|
|
Path Type: Setup (Max at Slow Process Corner)
|
|
Requirement: 30.323ns (cpu_clk rise@30.323ns - cpu_clk rise@0.000ns)
|
|
Data Path Delay: 28.188ns (logic 5.333ns (18.919%) route 22.855ns (81.081%))
|
|
Logic Levels: 26 (CARRY4=4 LUT3=2 LUT4=1 LUT5=2 LUT6=15 MUXF7=1 MUXF8=1)
|
|
Clock Path Skew: 0.014ns (DCD - SCD + CPR)
|
|
Destination Clock Delay (DCD): -1.792ns = ( 28.530 - 30.323 )
|
|
Source Clock Delay (SCD): -2.225ns
|
|
Clock Pessimism Removal (CPR): -0.418ns
|
|
Clock Uncertainty: 0.074ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Discrete Jitter (DJ): 0.130ns
|
|
Phase Error (PE): 0.000ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock cpu_clk rise edge) 0.000 0.000 r
|
|
clock source latency -6.275 -6.275
|
|
propagated clock network latency
|
|
4.051 -2.225
|
|
SLICE_X35Y35 FDRE 0.000 -2.225 r u_cpu/addr_trans/data_vaddr_buffer_reg[14]/C
|
|
SLICE_X35Y35 FDRE (Prop_fdre_C_Q) 0.456 -1.769 r u_cpu/addr_trans/data_vaddr_buffer_reg[14]/Q
|
|
net (fo=33, routed) 1.442 -0.326 u_cpu/addr_trans/tlb_entry/data_vaddr_buffer[2]
|
|
SLICE_X42Y40 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_226/I5
|
|
SLICE_X42Y40 LUT6 (Prop_lut6_I5_O) 0.124 -0.202 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_226/O
|
|
net (fo=1, routed) 0.000 -0.202 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_226_n_0
|
|
SLICE_X42Y40 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_111/S[0]
|
|
SLICE_X42Y40 CARRY4 (Prop_carry4_S[0]_CO[3])
|
|
0.513 0.311 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_111/CO[3]
|
|
net (fo=1, routed) 0.000 0.311 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_111_n_0
|
|
SLICE_X42Y41 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_32/CI
|
|
SLICE_X42Y41 CARRY4 (Prop_carry4_CI_CO[2])
|
|
0.229 0.540 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_32/CO[2]
|
|
net (fo=1, routed) 1.009 1.549 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_32_n_1
|
|
SLICE_X40Y47 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_9/I1
|
|
SLICE_X40Y47 LUT6 (Prop_lut6_I1_O) 0.310 1.859 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_9/O
|
|
net (fo=2, routed) 0.635 2.494 u_cpu/addr_trans/tlb_entry/match1[28]
|
|
SLICE_X38Y47 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/I2
|
|
SLICE_X38Y47 LUT4 (Prop_lut4_I2_O) 0.124 2.618 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/O
|
|
net (fo=2, routed) 0.667 3.285 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2_n_0
|
|
SLICE_X39Y47 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/I0
|
|
SLICE_X39Y47 LUT5 (Prop_lut5_I0_O) 0.124 3.409 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/O
|
|
net (fo=2, routed) 1.103 4.512 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2_n_0
|
|
SLICE_X38Y50 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/I0
|
|
SLICE_X38Y50 LUT6 (Prop_lut6_I0_O) 0.124 4.636 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/O
|
|
net (fo=89, routed) 1.162 5.797 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus[8]
|
|
SLICE_X42Y51 r u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_38__0/S
|
|
SLICE_X42Y51 MUXF7 (Prop_muxf7_S_O) 0.292 6.089 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_38__0/O
|
|
net (fo=1, routed) 0.000 6.089 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_38__0_n_0
|
|
SLICE_X42Y51 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_16__0/I1
|
|
SLICE_X42Y51 MUXF8 (Prop_muxf8_I1_O) 0.088 6.177 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_16__0/O
|
|
net (fo=1, routed) 0.957 7.134 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_16__0_n_0
|
|
SLICE_X42Y50 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7/I0
|
|
SLICE_X42Y50 LUT6 (Prop_lut6_I0_O) 0.319 7.453 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7/O
|
|
net (fo=1, routed) 0.435 7.888 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7_n_0
|
|
SLICE_X44Y50 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0/I5
|
|
SLICE_X44Y50 LUT6 (Prop_lut6_I5_O) 0.124 8.012 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0/O
|
|
net (fo=10, routed) 0.740 8.753 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0_n_0
|
|
SLICE_X44Y50 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[5]_i_1__0/I3
|
|
SLICE_X44Y50 LUT6 (Prop_lut6_I3_O) 0.124 8.877 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[5]_i_1__0/O
|
|
net (fo=6, routed) 0.845 9.722 u_cpu/u_csr/ms_to_ws_bus[13]
|
|
SLICE_X50Y46 f u_cpu/u_csr/write_buffer_way[1]_i_18/I3
|
|
SLICE_X50Y46 LUT6 (Prop_lut6_I3_O) 0.124 9.846 r u_cpu/u_csr/write_buffer_way[1]_i_18/O
|
|
net (fo=1, routed) 0.000 9.846 u_cpu/u_csr/write_buffer_way[1]_i_18_n_0
|
|
SLICE_X50Y46 r u_cpu/u_csr/write_buffer_way_reg[1]_i_11/S[0]
|
|
SLICE_X50Y46 CARRY4 (Prop_carry4_S[0]_CO[3])
|
|
0.532 10.378 f u_cpu/u_csr/write_buffer_way_reg[1]_i_11/CO[3]
|
|
net (fo=1, routed) 0.000 10.378 u_cpu/u_csr/write_buffer_way_reg[1]_i_11_n_0
|
|
SLICE_X50Y47 f u_cpu/u_csr/write_buffer_way_reg[1]_i_9/CI
|
|
SLICE_X50Y47 CARRY4 (Prop_carry4_CI_CO[1])
|
|
0.157 10.535 f u_cpu/u_csr/write_buffer_way_reg[1]_i_9/CO[1]
|
|
net (fo=2, routed) 0.791 11.326 u_cpu/wb_stage/CO[0]
|
|
SLICE_X46Y39 f u_cpu/wb_stage/write_buffer_way[1]_i_5/I1
|
|
SLICE_X46Y39 LUT6 (Prop_lut6_I1_O) 0.329 11.655 r u_cpu/wb_stage/write_buffer_way[1]_i_5/O
|
|
net (fo=7, routed) 0.762 12.417 u_cpu/addr_trans/tlb_entry/sc_cancel_req
|
|
SLICE_X46Y35 r u_cpu/addr_trans/tlb_entry/main_state[0]_i_3/I1
|
|
SLICE_X46Y35 LUT3 (Prop_lut3_I1_O) 0.124 12.541 r u_cpu/addr_trans/tlb_entry/main_state[0]_i_3/O
|
|
net (fo=3, routed) 0.719 13.260 u_cpu/dcache/main_state_reg[0]_2
|
|
SLICE_X43Y31 r u_cpu/dcache/ds_to_es_bus_r[235]_i_10/I3
|
|
SLICE_X43Y31 LUT6 (Prop_lut6_I3_O) 0.124 13.384 r u_cpu/dcache/ds_to_es_bus_r[235]_i_10/O
|
|
net (fo=3, routed) 0.415 13.799 u_cpu/mem_stage/data_data_ok
|
|
SLICE_X43Y30 r u_cpu/mem_stage/flush_inst_req_buffer[1]_i_15/I0
|
|
SLICE_X43Y30 LUT3 (Prop_lut3_I0_O) 0.124 13.923 r u_cpu/mem_stage/flush_inst_req_buffer[1]_i_15/O
|
|
net (fo=2, routed) 0.833 14.756 u_cpu/mem_stage/es_to_ms_bus_r_reg[70]_1
|
|
SLICE_X48Y30 r u_cpu/mem_stage/flush_inst_req_buffer[1]_i_14/I0
|
|
SLICE_X48Y30 LUT6 (Prop_lut6_I0_O) 0.124 14.880 r u_cpu/mem_stage/flush_inst_req_buffer[1]_i_14/O
|
|
net (fo=1, routed) 0.651 15.532 u_cpu/mem_stage/ms_ready_go
|
|
SLICE_X48Y25 r u_cpu/mem_stage/flush_inst_req_buffer[1]_i_13/I4
|
|
SLICE_X48Y25 LUT6 (Prop_lut6_I4_O) 0.124 15.656 r u_cpu/mem_stage/flush_inst_req_buffer[1]_i_13/O
|
|
net (fo=3, routed) 0.483 16.139 u_cpu/id_stage/flush_inst_req_buffer[31]_i_6
|
|
SLICE_X50Y25 r u_cpu/id_stage/flush_inst_req_buffer[1]_i_9/I1
|
|
SLICE_X50Y25 LUT6 (Prop_lut6_I1_O) 0.124 16.263 r u_cpu/id_stage/flush_inst_req_buffer[1]_i_9/O
|
|
net (fo=32, routed) 0.531 16.794 u_cpu/if_stage/nextpc5
|
|
SLICE_X51Y27 r u_cpu/if_stage/fetch_pc_r[6]_i_4/I2
|
|
SLICE_X51Y27 LUT6 (Prop_lut6_I2_O) 0.124 16.918 r u_cpu/if_stage/fetch_pc_r[6]_i_4/O
|
|
net (fo=1, routed) 3.059 19.977 u_cpu/if_stage/fetch_pc_r[6]_i_4_n_0
|
|
SLICE_X114Y28 r u_cpu/if_stage/fetch_pc_r[6]_i_2/I2
|
|
SLICE_X114Y28 LUT6 (Prop_lut6_I2_O) 0.124 20.101 r u_cpu/if_stage/fetch_pc_r[6]_i_2/O
|
|
net (fo=1, routed) 0.441 20.542 u_cpu/if_stage/fetch_pc_r[6]_i_2_n_0
|
|
SLICE_X114Y25 r u_cpu/if_stage/fetch_pc_r[6]_i_1/I2
|
|
SLICE_X114Y25 LUT6 (Prop_lut6_I2_O) 0.124 20.666 r u_cpu/if_stage/fetch_pc_r[6]_i_1/O
|
|
net (fo=6, routed) 3.249 23.915 u_cpu/icache/tagv_ram_way[1].u/mem_reg_reg_2[2]
|
|
SLICE_X49Y33 r u_cpu/icache/tagv_ram_way[1].u/mem_reg_reg_i_8/I4
|
|
SLICE_X49Y33 LUT5 (Prop_lut5_I4_O) 0.124 24.039 r u_cpu/icache/tagv_ram_way[1].u/mem_reg_reg_i_8/O
|
|
net (fo=16, routed) 1.924 25.963 u_cpu/icache/data_ram_way[0].data_ram_bank[1].u/ADDRBWRADDR[2]
|
|
RAMB18_X1Y3 RAMB18E1 r u_cpu/icache/data_ram_way[0].data_ram_bank[1].u/mem_reg_reg/ADDRARDADDR[7]
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock cpu_clk rise edge) 30.323 30.323 r
|
|
clock source latency -5.674 24.648
|
|
propagated clock network latency
|
|
3.882 28.530
|
|
clock pessimism -0.418 28.112
|
|
clock uncertainty -0.074 28.038
|
|
RAMB18_X1Y3 RAMB18E1 (Setup_ramb18e1_CLKARDCLK_ADDRARDADDR[7])
|
|
-0.566 27.472 u_cpu/icache/data_ram_way[0].data_ram_bank[1].u/mem_reg_reg
|
|
-------------------------------------------------------------------
|
|
required time 27.472
|
|
arrival time -25.963
|
|
-------------------------------------------------------------------
|
|
slack 1.509
|
|
|
|
Slack (MET) : 1.509ns (required time - arrival time)
|
|
Source: u_cpu/addr_trans/data_vaddr_buffer_reg[14]/C
|
|
(rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns})
|
|
Destination: u_cpu/icache/data_ram_way[0].data_ram_bank[1].u/mem_reg_reg/ADDRARDADDR[7]
|
|
(rising edge-triggered cell RAMB18E1 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns})
|
|
Path Group: cpu_clk
|
|
Path Type: Setup (Max at Slow Process Corner)
|
|
Requirement: 30.323ns (cpu_clk rise@30.323ns - cpu_clk rise@0.000ns)
|
|
Data Path Delay: 28.188ns (logic 5.333ns (18.919%) route 22.855ns (81.081%))
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|
Logic Levels: 26 (CARRY4=4 LUT3=2 LUT4=1 LUT5=2 LUT6=15 MUXF7=1 MUXF8=1)
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|
Clock Path Skew: 0.014ns (DCD - SCD + CPR)
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|
Destination Clock Delay (DCD): -1.792ns = ( 28.530 - 30.323 )
|
|
Source Clock Delay (SCD): -2.225ns
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|
Clock Pessimism Removal (CPR): -0.418ns
|
|
Clock Uncertainty: 0.074ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Discrete Jitter (DJ): 0.130ns
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|
Phase Error (PE): 0.000ns
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|
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|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
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|
------------------------------------------------------------------- -------------------
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|
(clock cpu_clk rise edge) 0.000 0.000 r
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|
clock source latency -6.275 -6.275
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propagated clock network latency
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4.051 -2.225
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SLICE_X35Y35 FDRE 0.000 -2.225 r u_cpu/addr_trans/data_vaddr_buffer_reg[14]/C
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SLICE_X35Y35 FDRE (Prop_fdre_C_Q) 0.456 -1.769 r u_cpu/addr_trans/data_vaddr_buffer_reg[14]/Q
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net (fo=33, routed) 1.442 -0.326 u_cpu/addr_trans/tlb_entry/data_vaddr_buffer[2]
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SLICE_X42Y40 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_226/I5
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SLICE_X42Y40 LUT6 (Prop_lut6_I5_O) 0.124 -0.202 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_226/O
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net (fo=1, routed) 0.000 -0.202 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_226_n_0
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SLICE_X42Y40 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_111/S[0]
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SLICE_X42Y40 CARRY4 (Prop_carry4_S[0]_CO[3])
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0.513 0.311 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_111/CO[3]
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net (fo=1, routed) 0.000 0.311 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_111_n_0
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SLICE_X42Y41 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_32/CI
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SLICE_X42Y41 CARRY4 (Prop_carry4_CI_CO[2])
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0.229 0.540 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_32/CO[2]
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net (fo=1, routed) 1.009 1.549 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_32_n_1
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SLICE_X40Y47 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_9/I1
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SLICE_X40Y47 LUT6 (Prop_lut6_I1_O) 0.310 1.859 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_9/O
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net (fo=2, routed) 0.635 2.494 u_cpu/addr_trans/tlb_entry/match1[28]
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SLICE_X38Y47 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/I2
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SLICE_X38Y47 LUT4 (Prop_lut4_I2_O) 0.124 2.618 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/O
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net (fo=2, routed) 0.667 3.285 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2_n_0
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SLICE_X39Y47 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/I0
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SLICE_X39Y47 LUT5 (Prop_lut5_I0_O) 0.124 3.409 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/O
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|
net (fo=2, routed) 1.103 4.512 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2_n_0
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|
SLICE_X38Y50 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/I0
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SLICE_X38Y50 LUT6 (Prop_lut6_I0_O) 0.124 4.636 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/O
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net (fo=89, routed) 1.162 5.797 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus[8]
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SLICE_X42Y51 r u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_38__0/S
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SLICE_X42Y51 MUXF7 (Prop_muxf7_S_O) 0.292 6.089 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_38__0/O
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net (fo=1, routed) 0.000 6.089 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_38__0_n_0
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SLICE_X42Y51 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_16__0/I1
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SLICE_X42Y51 MUXF8 (Prop_muxf8_I1_O) 0.088 6.177 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_16__0/O
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net (fo=1, routed) 0.957 7.134 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_16__0_n_0
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SLICE_X42Y50 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7/I0
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SLICE_X42Y50 LUT6 (Prop_lut6_I0_O) 0.319 7.453 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7/O
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net (fo=1, routed) 0.435 7.888 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7_n_0
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SLICE_X44Y50 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0/I5
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SLICE_X44Y50 LUT6 (Prop_lut6_I5_O) 0.124 8.012 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0/O
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net (fo=10, routed) 0.740 8.753 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0_n_0
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SLICE_X44Y50 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[5]_i_1__0/I3
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|
SLICE_X44Y50 LUT6 (Prop_lut6_I3_O) 0.124 8.877 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[5]_i_1__0/O
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net (fo=6, routed) 0.845 9.722 u_cpu/u_csr/ms_to_ws_bus[13]
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SLICE_X50Y46 r u_cpu/u_csr/write_buffer_way[1]_i_18/I3
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SLICE_X50Y46 LUT6 (Prop_lut6_I3_O) 0.124 9.846 r u_cpu/u_csr/write_buffer_way[1]_i_18/O
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|
net (fo=1, routed) 0.000 9.846 u_cpu/u_csr/write_buffer_way[1]_i_18_n_0
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SLICE_X50Y46 r u_cpu/u_csr/write_buffer_way_reg[1]_i_11/S[0]
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SLICE_X50Y46 CARRY4 (Prop_carry4_S[0]_CO[3])
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0.532 10.378 r u_cpu/u_csr/write_buffer_way_reg[1]_i_11/CO[3]
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|
net (fo=1, routed) 0.000 10.378 u_cpu/u_csr/write_buffer_way_reg[1]_i_11_n_0
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SLICE_X50Y47 r u_cpu/u_csr/write_buffer_way_reg[1]_i_9/CI
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SLICE_X50Y47 CARRY4 (Prop_carry4_CI_CO[1])
|
|
0.157 10.535 r u_cpu/u_csr/write_buffer_way_reg[1]_i_9/CO[1]
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net (fo=2, routed) 0.791 11.326 u_cpu/wb_stage/CO[0]
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SLICE_X46Y39 r u_cpu/wb_stage/write_buffer_way[1]_i_5/I1
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SLICE_X46Y39 LUT6 (Prop_lut6_I1_O) 0.329 11.655 f u_cpu/wb_stage/write_buffer_way[1]_i_5/O
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net (fo=7, routed) 0.762 12.417 u_cpu/addr_trans/tlb_entry/sc_cancel_req
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SLICE_X46Y35 f u_cpu/addr_trans/tlb_entry/main_state[0]_i_3/I1
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SLICE_X46Y35 LUT3 (Prop_lut3_I1_O) 0.124 12.541 f u_cpu/addr_trans/tlb_entry/main_state[0]_i_3/O
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net (fo=3, routed) 0.719 13.260 u_cpu/dcache/main_state_reg[0]_2
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SLICE_X43Y31 f u_cpu/dcache/ds_to_es_bus_r[235]_i_10/I3
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SLICE_X43Y31 LUT6 (Prop_lut6_I3_O) 0.124 13.384 f u_cpu/dcache/ds_to_es_bus_r[235]_i_10/O
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net (fo=3, routed) 0.415 13.799 u_cpu/mem_stage/data_data_ok
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|
SLICE_X43Y30 f u_cpu/mem_stage/flush_inst_req_buffer[1]_i_15/I0
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SLICE_X43Y30 LUT3 (Prop_lut3_I0_O) 0.124 13.923 f u_cpu/mem_stage/flush_inst_req_buffer[1]_i_15/O
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net (fo=2, routed) 0.833 14.756 u_cpu/mem_stage/es_to_ms_bus_r_reg[70]_1
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SLICE_X48Y30 f u_cpu/mem_stage/flush_inst_req_buffer[1]_i_14/I0
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SLICE_X48Y30 LUT6 (Prop_lut6_I0_O) 0.124 14.880 f u_cpu/mem_stage/flush_inst_req_buffer[1]_i_14/O
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net (fo=1, routed) 0.651 15.532 u_cpu/mem_stage/ms_ready_go
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SLICE_X48Y25 f u_cpu/mem_stage/flush_inst_req_buffer[1]_i_13/I4
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SLICE_X48Y25 LUT6 (Prop_lut6_I4_O) 0.124 15.656 f u_cpu/mem_stage/flush_inst_req_buffer[1]_i_13/O
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net (fo=3, routed) 0.483 16.139 u_cpu/id_stage/flush_inst_req_buffer[31]_i_6
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SLICE_X50Y25 f u_cpu/id_stage/flush_inst_req_buffer[1]_i_9/I1
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|
SLICE_X50Y25 LUT6 (Prop_lut6_I1_O) 0.124 16.263 f u_cpu/id_stage/flush_inst_req_buffer[1]_i_9/O
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net (fo=32, routed) 0.531 16.794 u_cpu/if_stage/nextpc5
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|
SLICE_X51Y27 f u_cpu/if_stage/fetch_pc_r[6]_i_4/I2
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SLICE_X51Y27 LUT6 (Prop_lut6_I2_O) 0.124 16.918 r u_cpu/if_stage/fetch_pc_r[6]_i_4/O
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net (fo=1, routed) 3.059 19.977 u_cpu/if_stage/fetch_pc_r[6]_i_4_n_0
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SLICE_X114Y28 r u_cpu/if_stage/fetch_pc_r[6]_i_2/I2
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SLICE_X114Y28 LUT6 (Prop_lut6_I2_O) 0.124 20.101 r u_cpu/if_stage/fetch_pc_r[6]_i_2/O
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net (fo=1, routed) 0.441 20.542 u_cpu/if_stage/fetch_pc_r[6]_i_2_n_0
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SLICE_X114Y25 r u_cpu/if_stage/fetch_pc_r[6]_i_1/I2
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SLICE_X114Y25 LUT6 (Prop_lut6_I2_O) 0.124 20.666 r u_cpu/if_stage/fetch_pc_r[6]_i_1/O
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net (fo=6, routed) 3.249 23.915 u_cpu/icache/tagv_ram_way[1].u/mem_reg_reg_2[2]
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SLICE_X49Y33 r u_cpu/icache/tagv_ram_way[1].u/mem_reg_reg_i_8/I4
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SLICE_X49Y33 LUT5 (Prop_lut5_I4_O) 0.124 24.039 r u_cpu/icache/tagv_ram_way[1].u/mem_reg_reg_i_8/O
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net (fo=16, routed) 1.924 25.963 u_cpu/icache/data_ram_way[0].data_ram_bank[1].u/ADDRBWRADDR[2]
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RAMB18_X1Y3 RAMB18E1 r u_cpu/icache/data_ram_way[0].data_ram_bank[1].u/mem_reg_reg/ADDRARDADDR[7]
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock cpu_clk rise edge) 30.323 30.323 r
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|
clock source latency -5.674 24.648
|
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propagated clock network latency
|
|
3.882 28.530
|
|
clock pessimism -0.418 28.112
|
|
clock uncertainty -0.074 28.038
|
|
RAMB18_X1Y3 RAMB18E1 (Setup_ramb18e1_CLKARDCLK_ADDRARDADDR[7])
|
|
-0.566 27.472 u_cpu/icache/data_ram_way[0].data_ram_bank[1].u/mem_reg_reg
|
|
-------------------------------------------------------------------
|
|
required time 27.472
|
|
arrival time -25.963
|
|
-------------------------------------------------------------------
|
|
slack 1.509
|
|
|
|
Slack (MET) : 1.509ns (required time - arrival time)
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|
Source: u_cpu/addr_trans/data_vaddr_buffer_reg[14]/C
|
|
(rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns})
|
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Destination: u_cpu/icache/data_ram_way[0].data_ram_bank[1].u/mem_reg_reg/ADDRARDADDR[7]
|
|
(rising edge-triggered cell RAMB18E1 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns})
|
|
Path Group: cpu_clk
|
|
Path Type: Setup (Max at Slow Process Corner)
|
|
Requirement: 30.323ns (cpu_clk rise@30.323ns - cpu_clk rise@0.000ns)
|
|
Data Path Delay: 28.188ns (logic 5.333ns (18.919%) route 22.855ns (81.081%))
|
|
Logic Levels: 26 (CARRY4=4 LUT3=2 LUT4=1 LUT5=2 LUT6=15 MUXF7=1 MUXF8=1)
|
|
Clock Path Skew: 0.014ns (DCD - SCD + CPR)
|
|
Destination Clock Delay (DCD): -1.792ns = ( 28.530 - 30.323 )
|
|
Source Clock Delay (SCD): -2.225ns
|
|
Clock Pessimism Removal (CPR): -0.418ns
|
|
Clock Uncertainty: 0.074ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Discrete Jitter (DJ): 0.130ns
|
|
Phase Error (PE): 0.000ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock cpu_clk rise edge) 0.000 0.000 r
|
|
clock source latency -6.275 -6.275
|
|
propagated clock network latency
|
|
4.051 -2.225
|
|
SLICE_X35Y35 FDRE 0.000 -2.225 r u_cpu/addr_trans/data_vaddr_buffer_reg[14]/C
|
|
SLICE_X35Y35 FDRE (Prop_fdre_C_Q) 0.456 -1.769 r u_cpu/addr_trans/data_vaddr_buffer_reg[14]/Q
|
|
net (fo=33, routed) 1.442 -0.326 u_cpu/addr_trans/tlb_entry/data_vaddr_buffer[2]
|
|
SLICE_X42Y40 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_226/I5
|
|
SLICE_X42Y40 LUT6 (Prop_lut6_I5_O) 0.124 -0.202 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_226/O
|
|
net (fo=1, routed) 0.000 -0.202 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_226_n_0
|
|
SLICE_X42Y40 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_111/S[0]
|
|
SLICE_X42Y40 CARRY4 (Prop_carry4_S[0]_CO[3])
|
|
0.513 0.311 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_111/CO[3]
|
|
net (fo=1, routed) 0.000 0.311 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_111_n_0
|
|
SLICE_X42Y41 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_32/CI
|
|
SLICE_X42Y41 CARRY4 (Prop_carry4_CI_CO[2])
|
|
0.229 0.540 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_32/CO[2]
|
|
net (fo=1, routed) 1.009 1.549 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_32_n_1
|
|
SLICE_X40Y47 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_9/I1
|
|
SLICE_X40Y47 LUT6 (Prop_lut6_I1_O) 0.310 1.859 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_9/O
|
|
net (fo=2, routed) 0.635 2.494 u_cpu/addr_trans/tlb_entry/match1[28]
|
|
SLICE_X38Y47 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/I2
|
|
SLICE_X38Y47 LUT4 (Prop_lut4_I2_O) 0.124 2.618 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/O
|
|
net (fo=2, routed) 0.667 3.285 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2_n_0
|
|
SLICE_X39Y47 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/I0
|
|
SLICE_X39Y47 LUT5 (Prop_lut5_I0_O) 0.124 3.409 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/O
|
|
net (fo=2, routed) 1.103 4.512 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2_n_0
|
|
SLICE_X38Y50 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/I0
|
|
SLICE_X38Y50 LUT6 (Prop_lut6_I0_O) 0.124 4.636 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/O
|
|
net (fo=89, routed) 1.162 5.797 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus[8]
|
|
SLICE_X42Y51 r u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_38__0/S
|
|
SLICE_X42Y51 MUXF7 (Prop_muxf7_S_O) 0.292 6.089 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_38__0/O
|
|
net (fo=1, routed) 0.000 6.089 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_38__0_n_0
|
|
SLICE_X42Y51 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_16__0/I1
|
|
SLICE_X42Y51 MUXF8 (Prop_muxf8_I1_O) 0.088 6.177 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_16__0/O
|
|
net (fo=1, routed) 0.957 7.134 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_16__0_n_0
|
|
SLICE_X42Y50 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7/I0
|
|
SLICE_X42Y50 LUT6 (Prop_lut6_I0_O) 0.319 7.453 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7/O
|
|
net (fo=1, routed) 0.435 7.888 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7_n_0
|
|
SLICE_X44Y50 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0/I5
|
|
SLICE_X44Y50 LUT6 (Prop_lut6_I5_O) 0.124 8.012 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0/O
|
|
net (fo=10, routed) 0.740 8.753 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0_n_0
|
|
SLICE_X44Y50 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[5]_i_1__0/I3
|
|
SLICE_X44Y50 LUT6 (Prop_lut6_I3_O) 0.124 8.877 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[5]_i_1__0/O
|
|
net (fo=6, routed) 0.845 9.722 u_cpu/u_csr/ms_to_ws_bus[13]
|
|
SLICE_X50Y46 f u_cpu/u_csr/write_buffer_way[1]_i_18/I3
|
|
SLICE_X50Y46 LUT6 (Prop_lut6_I3_O) 0.124 9.846 r u_cpu/u_csr/write_buffer_way[1]_i_18/O
|
|
net (fo=1, routed) 0.000 9.846 u_cpu/u_csr/write_buffer_way[1]_i_18_n_0
|
|
SLICE_X50Y46 r u_cpu/u_csr/write_buffer_way_reg[1]_i_11/S[0]
|
|
SLICE_X50Y46 CARRY4 (Prop_carry4_S[0]_CO[3])
|
|
0.532 10.378 r u_cpu/u_csr/write_buffer_way_reg[1]_i_11/CO[3]
|
|
net (fo=1, routed) 0.000 10.378 u_cpu/u_csr/write_buffer_way_reg[1]_i_11_n_0
|
|
SLICE_X50Y47 r u_cpu/u_csr/write_buffer_way_reg[1]_i_9/CI
|
|
SLICE_X50Y47 CARRY4 (Prop_carry4_CI_CO[1])
|
|
0.157 10.535 r u_cpu/u_csr/write_buffer_way_reg[1]_i_9/CO[1]
|
|
net (fo=2, routed) 0.791 11.326 u_cpu/wb_stage/CO[0]
|
|
SLICE_X46Y39 r u_cpu/wb_stage/write_buffer_way[1]_i_5/I1
|
|
SLICE_X46Y39 LUT6 (Prop_lut6_I1_O) 0.329 11.655 f u_cpu/wb_stage/write_buffer_way[1]_i_5/O
|
|
net (fo=7, routed) 0.762 12.417 u_cpu/addr_trans/tlb_entry/sc_cancel_req
|
|
SLICE_X46Y35 f u_cpu/addr_trans/tlb_entry/main_state[0]_i_3/I1
|
|
SLICE_X46Y35 LUT3 (Prop_lut3_I1_O) 0.124 12.541 f u_cpu/addr_trans/tlb_entry/main_state[0]_i_3/O
|
|
net (fo=3, routed) 0.719 13.260 u_cpu/dcache/main_state_reg[0]_2
|
|
SLICE_X43Y31 f u_cpu/dcache/ds_to_es_bus_r[235]_i_10/I3
|
|
SLICE_X43Y31 LUT6 (Prop_lut6_I3_O) 0.124 13.384 f u_cpu/dcache/ds_to_es_bus_r[235]_i_10/O
|
|
net (fo=3, routed) 0.415 13.799 u_cpu/mem_stage/data_data_ok
|
|
SLICE_X43Y30 f u_cpu/mem_stage/flush_inst_req_buffer[1]_i_15/I0
|
|
SLICE_X43Y30 LUT3 (Prop_lut3_I0_O) 0.124 13.923 f u_cpu/mem_stage/flush_inst_req_buffer[1]_i_15/O
|
|
net (fo=2, routed) 0.833 14.756 u_cpu/mem_stage/es_to_ms_bus_r_reg[70]_1
|
|
SLICE_X48Y30 f u_cpu/mem_stage/flush_inst_req_buffer[1]_i_14/I0
|
|
SLICE_X48Y30 LUT6 (Prop_lut6_I0_O) 0.124 14.880 f u_cpu/mem_stage/flush_inst_req_buffer[1]_i_14/O
|
|
net (fo=1, routed) 0.651 15.532 u_cpu/mem_stage/ms_ready_go
|
|
SLICE_X48Y25 f u_cpu/mem_stage/flush_inst_req_buffer[1]_i_13/I4
|
|
SLICE_X48Y25 LUT6 (Prop_lut6_I4_O) 0.124 15.656 f u_cpu/mem_stage/flush_inst_req_buffer[1]_i_13/O
|
|
net (fo=3, routed) 0.483 16.139 u_cpu/id_stage/flush_inst_req_buffer[31]_i_6
|
|
SLICE_X50Y25 f u_cpu/id_stage/flush_inst_req_buffer[1]_i_9/I1
|
|
SLICE_X50Y25 LUT6 (Prop_lut6_I1_O) 0.124 16.263 f u_cpu/id_stage/flush_inst_req_buffer[1]_i_9/O
|
|
net (fo=32, routed) 0.531 16.794 u_cpu/if_stage/nextpc5
|
|
SLICE_X51Y27 f u_cpu/if_stage/fetch_pc_r[6]_i_4/I2
|
|
SLICE_X51Y27 LUT6 (Prop_lut6_I2_O) 0.124 16.918 r u_cpu/if_stage/fetch_pc_r[6]_i_4/O
|
|
net (fo=1, routed) 3.059 19.977 u_cpu/if_stage/fetch_pc_r[6]_i_4_n_0
|
|
SLICE_X114Y28 r u_cpu/if_stage/fetch_pc_r[6]_i_2/I2
|
|
SLICE_X114Y28 LUT6 (Prop_lut6_I2_O) 0.124 20.101 r u_cpu/if_stage/fetch_pc_r[6]_i_2/O
|
|
net (fo=1, routed) 0.441 20.542 u_cpu/if_stage/fetch_pc_r[6]_i_2_n_0
|
|
SLICE_X114Y25 r u_cpu/if_stage/fetch_pc_r[6]_i_1/I2
|
|
SLICE_X114Y25 LUT6 (Prop_lut6_I2_O) 0.124 20.666 r u_cpu/if_stage/fetch_pc_r[6]_i_1/O
|
|
net (fo=6, routed) 3.249 23.915 u_cpu/icache/tagv_ram_way[1].u/mem_reg_reg_2[2]
|
|
SLICE_X49Y33 r u_cpu/icache/tagv_ram_way[1].u/mem_reg_reg_i_8/I4
|
|
SLICE_X49Y33 LUT5 (Prop_lut5_I4_O) 0.124 24.039 r u_cpu/icache/tagv_ram_way[1].u/mem_reg_reg_i_8/O
|
|
net (fo=16, routed) 1.924 25.963 u_cpu/icache/data_ram_way[0].data_ram_bank[1].u/ADDRBWRADDR[2]
|
|
RAMB18_X1Y3 RAMB18E1 r u_cpu/icache/data_ram_way[0].data_ram_bank[1].u/mem_reg_reg/ADDRARDADDR[7]
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock cpu_clk rise edge) 30.323 30.323 r
|
|
clock source latency -5.674 24.648
|
|
propagated clock network latency
|
|
3.882 28.530
|
|
clock pessimism -0.418 28.112
|
|
clock uncertainty -0.074 28.038
|
|
RAMB18_X1Y3 RAMB18E1 (Setup_ramb18e1_CLKARDCLK_ADDRARDADDR[7])
|
|
-0.566 27.472 u_cpu/icache/data_ram_way[0].data_ram_bank[1].u/mem_reg_reg
|
|
-------------------------------------------------------------------
|
|
required time 27.472
|
|
arrival time -25.963
|
|
-------------------------------------------------------------------
|
|
slack 1.509
|
|
|
|
Slack (MET) : 1.509ns (required time - arrival time)
|
|
Source: u_cpu/addr_trans/data_vaddr_buffer_reg[14]/C
|
|
(rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns})
|
|
Destination: u_cpu/icache/data_ram_way[0].data_ram_bank[1].u/mem_reg_reg/ADDRARDADDR[7]
|
|
(rising edge-triggered cell RAMB18E1 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns})
|
|
Path Group: cpu_clk
|
|
Path Type: Setup (Max at Slow Process Corner)
|
|
Requirement: 30.323ns (cpu_clk rise@30.323ns - cpu_clk rise@0.000ns)
|
|
Data Path Delay: 28.188ns (logic 5.333ns (18.919%) route 22.855ns (81.081%))
|
|
Logic Levels: 26 (CARRY4=4 LUT3=2 LUT4=1 LUT5=2 LUT6=15 MUXF7=1 MUXF8=1)
|
|
Clock Path Skew: 0.014ns (DCD - SCD + CPR)
|
|
Destination Clock Delay (DCD): -1.792ns = ( 28.530 - 30.323 )
|
|
Source Clock Delay (SCD): -2.225ns
|
|
Clock Pessimism Removal (CPR): -0.418ns
|
|
Clock Uncertainty: 0.074ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Discrete Jitter (DJ): 0.130ns
|
|
Phase Error (PE): 0.000ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock cpu_clk rise edge) 0.000 0.000 r
|
|
clock source latency -6.275 -6.275
|
|
propagated clock network latency
|
|
4.051 -2.225
|
|
SLICE_X35Y35 FDRE 0.000 -2.225 r u_cpu/addr_trans/data_vaddr_buffer_reg[14]/C
|
|
SLICE_X35Y35 FDRE (Prop_fdre_C_Q) 0.456 -1.769 r u_cpu/addr_trans/data_vaddr_buffer_reg[14]/Q
|
|
net (fo=33, routed) 1.442 -0.326 u_cpu/addr_trans/tlb_entry/data_vaddr_buffer[2]
|
|
SLICE_X42Y40 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_226/I5
|
|
SLICE_X42Y40 LUT6 (Prop_lut6_I5_O) 0.124 -0.202 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_226/O
|
|
net (fo=1, routed) 0.000 -0.202 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_226_n_0
|
|
SLICE_X42Y40 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_111/S[0]
|
|
SLICE_X42Y40 CARRY4 (Prop_carry4_S[0]_CO[3])
|
|
0.513 0.311 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_111/CO[3]
|
|
net (fo=1, routed) 0.000 0.311 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_111_n_0
|
|
SLICE_X42Y41 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_32/CI
|
|
SLICE_X42Y41 CARRY4 (Prop_carry4_CI_CO[2])
|
|
0.229 0.540 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_32/CO[2]
|
|
net (fo=1, routed) 1.009 1.549 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_32_n_1
|
|
SLICE_X40Y47 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_9/I1
|
|
SLICE_X40Y47 LUT6 (Prop_lut6_I1_O) 0.310 1.859 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_9/O
|
|
net (fo=2, routed) 0.635 2.494 u_cpu/addr_trans/tlb_entry/match1[28]
|
|
SLICE_X38Y47 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/I2
|
|
SLICE_X38Y47 LUT4 (Prop_lut4_I2_O) 0.124 2.618 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/O
|
|
net (fo=2, routed) 0.667 3.285 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2_n_0
|
|
SLICE_X39Y47 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/I0
|
|
SLICE_X39Y47 LUT5 (Prop_lut5_I0_O) 0.124 3.409 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/O
|
|
net (fo=2, routed) 1.103 4.512 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2_n_0
|
|
SLICE_X38Y50 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/I0
|
|
SLICE_X38Y50 LUT6 (Prop_lut6_I0_O) 0.124 4.636 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/O
|
|
net (fo=89, routed) 1.162 5.797 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus[8]
|
|
SLICE_X42Y51 r u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_38__0/S
|
|
SLICE_X42Y51 MUXF7 (Prop_muxf7_S_O) 0.292 6.089 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_38__0/O
|
|
net (fo=1, routed) 0.000 6.089 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_38__0_n_0
|
|
SLICE_X42Y51 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_16__0/I1
|
|
SLICE_X42Y51 MUXF8 (Prop_muxf8_I1_O) 0.088 6.177 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_16__0/O
|
|
net (fo=1, routed) 0.957 7.134 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_16__0_n_0
|
|
SLICE_X42Y50 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7/I0
|
|
SLICE_X42Y50 LUT6 (Prop_lut6_I0_O) 0.319 7.453 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7/O
|
|
net (fo=1, routed) 0.435 7.888 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7_n_0
|
|
SLICE_X44Y50 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0/I5
|
|
SLICE_X44Y50 LUT6 (Prop_lut6_I5_O) 0.124 8.012 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0/O
|
|
net (fo=10, routed) 0.740 8.753 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0_n_0
|
|
SLICE_X44Y50 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[5]_i_1__0/I3
|
|
SLICE_X44Y50 LUT6 (Prop_lut6_I3_O) 0.124 8.877 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[5]_i_1__0/O
|
|
net (fo=6, routed) 0.845 9.722 u_cpu/u_csr/ms_to_ws_bus[13]
|
|
SLICE_X50Y46 r u_cpu/u_csr/write_buffer_way[1]_i_18/I3
|
|
SLICE_X50Y46 LUT6 (Prop_lut6_I3_O) 0.124 9.846 f u_cpu/u_csr/write_buffer_way[1]_i_18/O
|
|
net (fo=1, routed) 0.000 9.846 u_cpu/u_csr/write_buffer_way[1]_i_18_n_0
|
|
SLICE_X50Y46 f u_cpu/u_csr/write_buffer_way_reg[1]_i_11/S[0]
|
|
SLICE_X50Y46 CARRY4 (Prop_carry4_S[0]_CO[3])
|
|
0.532 10.378 r u_cpu/u_csr/write_buffer_way_reg[1]_i_11/CO[3]
|
|
net (fo=1, routed) 0.000 10.378 u_cpu/u_csr/write_buffer_way_reg[1]_i_11_n_0
|
|
SLICE_X50Y47 r u_cpu/u_csr/write_buffer_way_reg[1]_i_9/CI
|
|
SLICE_X50Y47 CARRY4 (Prop_carry4_CI_CO[1])
|
|
0.157 10.535 r u_cpu/u_csr/write_buffer_way_reg[1]_i_9/CO[1]
|
|
net (fo=2, routed) 0.791 11.326 u_cpu/wb_stage/CO[0]
|
|
SLICE_X46Y39 r u_cpu/wb_stage/write_buffer_way[1]_i_5/I1
|
|
SLICE_X46Y39 LUT6 (Prop_lut6_I1_O) 0.329 11.655 f u_cpu/wb_stage/write_buffer_way[1]_i_5/O
|
|
net (fo=7, routed) 0.762 12.417 u_cpu/addr_trans/tlb_entry/sc_cancel_req
|
|
SLICE_X46Y35 f u_cpu/addr_trans/tlb_entry/main_state[0]_i_3/I1
|
|
SLICE_X46Y35 LUT3 (Prop_lut3_I1_O) 0.124 12.541 f u_cpu/addr_trans/tlb_entry/main_state[0]_i_3/O
|
|
net (fo=3, routed) 0.719 13.260 u_cpu/dcache/main_state_reg[0]_2
|
|
SLICE_X43Y31 f u_cpu/dcache/ds_to_es_bus_r[235]_i_10/I3
|
|
SLICE_X43Y31 LUT6 (Prop_lut6_I3_O) 0.124 13.384 f u_cpu/dcache/ds_to_es_bus_r[235]_i_10/O
|
|
net (fo=3, routed) 0.415 13.799 u_cpu/mem_stage/data_data_ok
|
|
SLICE_X43Y30 f u_cpu/mem_stage/flush_inst_req_buffer[1]_i_15/I0
|
|
SLICE_X43Y30 LUT3 (Prop_lut3_I0_O) 0.124 13.923 f u_cpu/mem_stage/flush_inst_req_buffer[1]_i_15/O
|
|
net (fo=2, routed) 0.833 14.756 u_cpu/mem_stage/es_to_ms_bus_r_reg[70]_1
|
|
SLICE_X48Y30 f u_cpu/mem_stage/flush_inst_req_buffer[1]_i_14/I0
|
|
SLICE_X48Y30 LUT6 (Prop_lut6_I0_O) 0.124 14.880 f u_cpu/mem_stage/flush_inst_req_buffer[1]_i_14/O
|
|
net (fo=1, routed) 0.651 15.532 u_cpu/mem_stage/ms_ready_go
|
|
SLICE_X48Y25 f u_cpu/mem_stage/flush_inst_req_buffer[1]_i_13/I4
|
|
SLICE_X48Y25 LUT6 (Prop_lut6_I4_O) 0.124 15.656 f u_cpu/mem_stage/flush_inst_req_buffer[1]_i_13/O
|
|
net (fo=3, routed) 0.483 16.139 u_cpu/id_stage/flush_inst_req_buffer[31]_i_6
|
|
SLICE_X50Y25 f u_cpu/id_stage/flush_inst_req_buffer[1]_i_9/I1
|
|
SLICE_X50Y25 LUT6 (Prop_lut6_I1_O) 0.124 16.263 f u_cpu/id_stage/flush_inst_req_buffer[1]_i_9/O
|
|
net (fo=32, routed) 0.531 16.794 u_cpu/if_stage/nextpc5
|
|
SLICE_X51Y27 f u_cpu/if_stage/fetch_pc_r[6]_i_4/I2
|
|
SLICE_X51Y27 LUT6 (Prop_lut6_I2_O) 0.124 16.918 r u_cpu/if_stage/fetch_pc_r[6]_i_4/O
|
|
net (fo=1, routed) 3.059 19.977 u_cpu/if_stage/fetch_pc_r[6]_i_4_n_0
|
|
SLICE_X114Y28 r u_cpu/if_stage/fetch_pc_r[6]_i_2/I2
|
|
SLICE_X114Y28 LUT6 (Prop_lut6_I2_O) 0.124 20.101 r u_cpu/if_stage/fetch_pc_r[6]_i_2/O
|
|
net (fo=1, routed) 0.441 20.542 u_cpu/if_stage/fetch_pc_r[6]_i_2_n_0
|
|
SLICE_X114Y25 r u_cpu/if_stage/fetch_pc_r[6]_i_1/I2
|
|
SLICE_X114Y25 LUT6 (Prop_lut6_I2_O) 0.124 20.666 r u_cpu/if_stage/fetch_pc_r[6]_i_1/O
|
|
net (fo=6, routed) 3.249 23.915 u_cpu/icache/tagv_ram_way[1].u/mem_reg_reg_2[2]
|
|
SLICE_X49Y33 r u_cpu/icache/tagv_ram_way[1].u/mem_reg_reg_i_8/I4
|
|
SLICE_X49Y33 LUT5 (Prop_lut5_I4_O) 0.124 24.039 r u_cpu/icache/tagv_ram_way[1].u/mem_reg_reg_i_8/O
|
|
net (fo=16, routed) 1.924 25.963 u_cpu/icache/data_ram_way[0].data_ram_bank[1].u/ADDRBWRADDR[2]
|
|
RAMB18_X1Y3 RAMB18E1 r u_cpu/icache/data_ram_way[0].data_ram_bank[1].u/mem_reg_reg/ADDRARDADDR[7]
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock cpu_clk rise edge) 30.323 30.323 r
|
|
clock source latency -5.674 24.648
|
|
propagated clock network latency
|
|
3.882 28.530
|
|
clock pessimism -0.418 28.112
|
|
clock uncertainty -0.074 28.038
|
|
RAMB18_X1Y3 RAMB18E1 (Setup_ramb18e1_CLKARDCLK_ADDRARDADDR[7])
|
|
-0.566 27.472 u_cpu/icache/data_ram_way[0].data_ram_bank[1].u/mem_reg_reg
|
|
-------------------------------------------------------------------
|
|
required time 27.472
|
|
arrival time -25.963
|
|
-------------------------------------------------------------------
|
|
slack 1.509
|
|
|
|
Slack (MET) : 1.509ns (required time - arrival time)
|
|
Source: u_cpu/addr_trans/data_vaddr_buffer_reg[14]/C
|
|
(rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns})
|
|
Destination: u_cpu/icache/data_ram_way[0].data_ram_bank[1].u/mem_reg_reg/ADDRARDADDR[7]
|
|
(rising edge-triggered cell RAMB18E1 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns})
|
|
Path Group: cpu_clk
|
|
Path Type: Setup (Max at Slow Process Corner)
|
|
Requirement: 30.323ns (cpu_clk rise@30.323ns - cpu_clk rise@0.000ns)
|
|
Data Path Delay: 28.188ns (logic 5.333ns (18.919%) route 22.855ns (81.081%))
|
|
Logic Levels: 26 (CARRY4=4 LUT3=2 LUT4=1 LUT5=2 LUT6=15 MUXF7=1 MUXF8=1)
|
|
Clock Path Skew: 0.014ns (DCD - SCD + CPR)
|
|
Destination Clock Delay (DCD): -1.792ns = ( 28.530 - 30.323 )
|
|
Source Clock Delay (SCD): -2.225ns
|
|
Clock Pessimism Removal (CPR): -0.418ns
|
|
Clock Uncertainty: 0.074ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Discrete Jitter (DJ): 0.130ns
|
|
Phase Error (PE): 0.000ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock cpu_clk rise edge) 0.000 0.000 r
|
|
clock source latency -6.275 -6.275
|
|
propagated clock network latency
|
|
4.051 -2.225
|
|
SLICE_X35Y35 FDRE 0.000 -2.225 r u_cpu/addr_trans/data_vaddr_buffer_reg[14]/C
|
|
SLICE_X35Y35 FDRE (Prop_fdre_C_Q) 0.456 -1.769 r u_cpu/addr_trans/data_vaddr_buffer_reg[14]/Q
|
|
net (fo=33, routed) 1.442 -0.326 u_cpu/addr_trans/tlb_entry/data_vaddr_buffer[2]
|
|
SLICE_X42Y40 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_226/I5
|
|
SLICE_X42Y40 LUT6 (Prop_lut6_I5_O) 0.124 -0.202 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_226/O
|
|
net (fo=1, routed) 0.000 -0.202 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_226_n_0
|
|
SLICE_X42Y40 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_111/S[0]
|
|
SLICE_X42Y40 CARRY4 (Prop_carry4_S[0]_CO[3])
|
|
0.513 0.311 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_111/CO[3]
|
|
net (fo=1, routed) 0.000 0.311 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_111_n_0
|
|
SLICE_X42Y41 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_32/CI
|
|
SLICE_X42Y41 CARRY4 (Prop_carry4_CI_CO[2])
|
|
0.229 0.540 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_32/CO[2]
|
|
net (fo=1, routed) 1.009 1.549 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_32_n_1
|
|
SLICE_X40Y47 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_9/I1
|
|
SLICE_X40Y47 LUT6 (Prop_lut6_I1_O) 0.310 1.859 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_9/O
|
|
net (fo=2, routed) 0.635 2.494 u_cpu/addr_trans/tlb_entry/match1[28]
|
|
SLICE_X38Y47 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/I2
|
|
SLICE_X38Y47 LUT4 (Prop_lut4_I2_O) 0.124 2.618 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/O
|
|
net (fo=2, routed) 0.667 3.285 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2_n_0
|
|
SLICE_X39Y47 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/I0
|
|
SLICE_X39Y47 LUT5 (Prop_lut5_I0_O) 0.124 3.409 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/O
|
|
net (fo=2, routed) 1.103 4.512 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2_n_0
|
|
SLICE_X38Y50 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/I0
|
|
SLICE_X38Y50 LUT6 (Prop_lut6_I0_O) 0.124 4.636 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/O
|
|
net (fo=89, routed) 1.162 5.797 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus[8]
|
|
SLICE_X42Y51 r u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_38__0/S
|
|
SLICE_X42Y51 MUXF7 (Prop_muxf7_S_O) 0.292 6.089 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_38__0/O
|
|
net (fo=1, routed) 0.000 6.089 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_38__0_n_0
|
|
SLICE_X42Y51 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_16__0/I1
|
|
SLICE_X42Y51 MUXF8 (Prop_muxf8_I1_O) 0.088 6.177 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_16__0/O
|
|
net (fo=1, routed) 0.957 7.134 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_16__0_n_0
|
|
SLICE_X42Y50 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7/I0
|
|
SLICE_X42Y50 LUT6 (Prop_lut6_I0_O) 0.319 7.453 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7/O
|
|
net (fo=1, routed) 0.435 7.888 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7_n_0
|
|
SLICE_X44Y50 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0/I5
|
|
SLICE_X44Y50 LUT6 (Prop_lut6_I5_O) 0.124 8.012 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0/O
|
|
net (fo=10, routed) 0.740 8.753 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0_n_0
|
|
SLICE_X44Y50 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[5]_i_1__0/I3
|
|
SLICE_X44Y50 LUT6 (Prop_lut6_I3_O) 0.124 8.877 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[5]_i_1__0/O
|
|
net (fo=6, routed) 0.845 9.722 u_cpu/u_csr/ms_to_ws_bus[13]
|
|
SLICE_X50Y46 f u_cpu/u_csr/write_buffer_way[1]_i_18/I3
|
|
SLICE_X50Y46 LUT6 (Prop_lut6_I3_O) 0.124 9.846 f u_cpu/u_csr/write_buffer_way[1]_i_18/O
|
|
net (fo=1, routed) 0.000 9.846 u_cpu/u_csr/write_buffer_way[1]_i_18_n_0
|
|
SLICE_X50Y46 f u_cpu/u_csr/write_buffer_way_reg[1]_i_11/S[0]
|
|
SLICE_X50Y46 CARRY4 (Prop_carry4_S[0]_CO[3])
|
|
0.532 10.378 r u_cpu/u_csr/write_buffer_way_reg[1]_i_11/CO[3]
|
|
net (fo=1, routed) 0.000 10.378 u_cpu/u_csr/write_buffer_way_reg[1]_i_11_n_0
|
|
SLICE_X50Y47 r u_cpu/u_csr/write_buffer_way_reg[1]_i_9/CI
|
|
SLICE_X50Y47 CARRY4 (Prop_carry4_CI_CO[1])
|
|
0.157 10.535 r u_cpu/u_csr/write_buffer_way_reg[1]_i_9/CO[1]
|
|
net (fo=2, routed) 0.791 11.326 u_cpu/wb_stage/CO[0]
|
|
SLICE_X46Y39 r u_cpu/wb_stage/write_buffer_way[1]_i_5/I1
|
|
SLICE_X46Y39 LUT6 (Prop_lut6_I1_O) 0.329 11.655 f u_cpu/wb_stage/write_buffer_way[1]_i_5/O
|
|
net (fo=7, routed) 0.762 12.417 u_cpu/addr_trans/tlb_entry/sc_cancel_req
|
|
SLICE_X46Y35 f u_cpu/addr_trans/tlb_entry/main_state[0]_i_3/I1
|
|
SLICE_X46Y35 LUT3 (Prop_lut3_I1_O) 0.124 12.541 f u_cpu/addr_trans/tlb_entry/main_state[0]_i_3/O
|
|
net (fo=3, routed) 0.719 13.260 u_cpu/dcache/main_state_reg[0]_2
|
|
SLICE_X43Y31 f u_cpu/dcache/ds_to_es_bus_r[235]_i_10/I3
|
|
SLICE_X43Y31 LUT6 (Prop_lut6_I3_O) 0.124 13.384 f u_cpu/dcache/ds_to_es_bus_r[235]_i_10/O
|
|
net (fo=3, routed) 0.415 13.799 u_cpu/mem_stage/data_data_ok
|
|
SLICE_X43Y30 f u_cpu/mem_stage/flush_inst_req_buffer[1]_i_15/I0
|
|
SLICE_X43Y30 LUT3 (Prop_lut3_I0_O) 0.124 13.923 f u_cpu/mem_stage/flush_inst_req_buffer[1]_i_15/O
|
|
net (fo=2, routed) 0.833 14.756 u_cpu/mem_stage/es_to_ms_bus_r_reg[70]_1
|
|
SLICE_X48Y30 f u_cpu/mem_stage/flush_inst_req_buffer[1]_i_14/I0
|
|
SLICE_X48Y30 LUT6 (Prop_lut6_I0_O) 0.124 14.880 f u_cpu/mem_stage/flush_inst_req_buffer[1]_i_14/O
|
|
net (fo=1, routed) 0.651 15.532 u_cpu/mem_stage/ms_ready_go
|
|
SLICE_X48Y25 f u_cpu/mem_stage/flush_inst_req_buffer[1]_i_13/I4
|
|
SLICE_X48Y25 LUT6 (Prop_lut6_I4_O) 0.124 15.656 f u_cpu/mem_stage/flush_inst_req_buffer[1]_i_13/O
|
|
net (fo=3, routed) 0.483 16.139 u_cpu/id_stage/flush_inst_req_buffer[31]_i_6
|
|
SLICE_X50Y25 f u_cpu/id_stage/flush_inst_req_buffer[1]_i_9/I1
|
|
SLICE_X50Y25 LUT6 (Prop_lut6_I1_O) 0.124 16.263 f u_cpu/id_stage/flush_inst_req_buffer[1]_i_9/O
|
|
net (fo=32, routed) 0.531 16.794 u_cpu/if_stage/nextpc5
|
|
SLICE_X51Y27 f u_cpu/if_stage/fetch_pc_r[6]_i_4/I2
|
|
SLICE_X51Y27 LUT6 (Prop_lut6_I2_O) 0.124 16.918 r u_cpu/if_stage/fetch_pc_r[6]_i_4/O
|
|
net (fo=1, routed) 3.059 19.977 u_cpu/if_stage/fetch_pc_r[6]_i_4_n_0
|
|
SLICE_X114Y28 r u_cpu/if_stage/fetch_pc_r[6]_i_2/I2
|
|
SLICE_X114Y28 LUT6 (Prop_lut6_I2_O) 0.124 20.101 r u_cpu/if_stage/fetch_pc_r[6]_i_2/O
|
|
net (fo=1, routed) 0.441 20.542 u_cpu/if_stage/fetch_pc_r[6]_i_2_n_0
|
|
SLICE_X114Y25 r u_cpu/if_stage/fetch_pc_r[6]_i_1/I2
|
|
SLICE_X114Y25 LUT6 (Prop_lut6_I2_O) 0.124 20.666 r u_cpu/if_stage/fetch_pc_r[6]_i_1/O
|
|
net (fo=6, routed) 3.249 23.915 u_cpu/icache/tagv_ram_way[1].u/mem_reg_reg_2[2]
|
|
SLICE_X49Y33 r u_cpu/icache/tagv_ram_way[1].u/mem_reg_reg_i_8/I4
|
|
SLICE_X49Y33 LUT5 (Prop_lut5_I4_O) 0.124 24.039 r u_cpu/icache/tagv_ram_way[1].u/mem_reg_reg_i_8/O
|
|
net (fo=16, routed) 1.924 25.963 u_cpu/icache/data_ram_way[0].data_ram_bank[1].u/ADDRBWRADDR[2]
|
|
RAMB18_X1Y3 RAMB18E1 r u_cpu/icache/data_ram_way[0].data_ram_bank[1].u/mem_reg_reg/ADDRARDADDR[7]
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock cpu_clk rise edge) 30.323 30.323 r
|
|
clock source latency -5.674 24.648
|
|
propagated clock network latency
|
|
3.882 28.530
|
|
clock pessimism -0.418 28.112
|
|
clock uncertainty -0.074 28.038
|
|
RAMB18_X1Y3 RAMB18E1 (Setup_ramb18e1_CLKARDCLK_ADDRARDADDR[7])
|
|
-0.566 27.472 u_cpu/icache/data_ram_way[0].data_ram_bank[1].u/mem_reg_reg
|
|
-------------------------------------------------------------------
|
|
required time 27.472
|
|
arrival time -25.963
|
|
-------------------------------------------------------------------
|
|
slack 1.509
|
|
|
|
Slack (MET) : 1.512ns (required time - arrival time)
|
|
Source: u_cpu/addr_trans/data_vaddr_buffer_reg[14]/C
|
|
(rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns})
|
|
Destination: u_cpu/icache/data_ram_way[0].data_ram_bank[1].u/mem_reg_reg/ADDRBWRADDR[7]
|
|
(rising edge-triggered cell RAMB18E1 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns})
|
|
Path Group: cpu_clk
|
|
Path Type: Setup (Max at Slow Process Corner)
|
|
Requirement: 30.323ns (cpu_clk rise@30.323ns - cpu_clk rise@0.000ns)
|
|
Data Path Delay: 28.186ns (logic 5.333ns (18.920%) route 22.853ns (81.079%))
|
|
Logic Levels: 26 (CARRY4=4 LUT3=2 LUT4=1 LUT5=2 LUT6=15 MUXF7=1 MUXF8=1)
|
|
Clock Path Skew: 0.015ns (DCD - SCD + CPR)
|
|
Destination Clock Delay (DCD): -1.791ns = ( 28.531 - 30.323 )
|
|
Source Clock Delay (SCD): -2.225ns
|
|
Clock Pessimism Removal (CPR): -0.418ns
|
|
Clock Uncertainty: 0.074ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Discrete Jitter (DJ): 0.130ns
|
|
Phase Error (PE): 0.000ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock cpu_clk rise edge) 0.000 0.000 r
|
|
clock source latency -6.275 -6.275
|
|
propagated clock network latency
|
|
4.051 -2.225
|
|
SLICE_X35Y35 FDRE 0.000 -2.225 r u_cpu/addr_trans/data_vaddr_buffer_reg[14]/C
|
|
SLICE_X35Y35 FDRE (Prop_fdre_C_Q) 0.456 -1.769 r u_cpu/addr_trans/data_vaddr_buffer_reg[14]/Q
|
|
net (fo=33, routed) 1.442 -0.326 u_cpu/addr_trans/tlb_entry/data_vaddr_buffer[2]
|
|
SLICE_X42Y40 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_226/I5
|
|
SLICE_X42Y40 LUT6 (Prop_lut6_I5_O) 0.124 -0.202 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_226/O
|
|
net (fo=1, routed) 0.000 -0.202 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_226_n_0
|
|
SLICE_X42Y40 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_111/S[0]
|
|
SLICE_X42Y40 CARRY4 (Prop_carry4_S[0]_CO[3])
|
|
0.513 0.311 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_111/CO[3]
|
|
net (fo=1, routed) 0.000 0.311 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_111_n_0
|
|
SLICE_X42Y41 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_32/CI
|
|
SLICE_X42Y41 CARRY4 (Prop_carry4_CI_CO[2])
|
|
0.229 0.540 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_32/CO[2]
|
|
net (fo=1, routed) 1.009 1.549 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_32_n_1
|
|
SLICE_X40Y47 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_9/I1
|
|
SLICE_X40Y47 LUT6 (Prop_lut6_I1_O) 0.310 1.859 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_9/O
|
|
net (fo=2, routed) 0.635 2.494 u_cpu/addr_trans/tlb_entry/match1[28]
|
|
SLICE_X38Y47 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/I2
|
|
SLICE_X38Y47 LUT4 (Prop_lut4_I2_O) 0.124 2.618 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/O
|
|
net (fo=2, routed) 0.667 3.285 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2_n_0
|
|
SLICE_X39Y47 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/I0
|
|
SLICE_X39Y47 LUT5 (Prop_lut5_I0_O) 0.124 3.409 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/O
|
|
net (fo=2, routed) 1.103 4.512 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2_n_0
|
|
SLICE_X38Y50 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/I0
|
|
SLICE_X38Y50 LUT6 (Prop_lut6_I0_O) 0.124 4.636 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/O
|
|
net (fo=89, routed) 1.162 5.797 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus[8]
|
|
SLICE_X42Y51 r u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_38__0/S
|
|
SLICE_X42Y51 MUXF7 (Prop_muxf7_S_O) 0.292 6.089 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_38__0/O
|
|
net (fo=1, routed) 0.000 6.089 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_38__0_n_0
|
|
SLICE_X42Y51 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_16__0/I1
|
|
SLICE_X42Y51 MUXF8 (Prop_muxf8_I1_O) 0.088 6.177 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_16__0/O
|
|
net (fo=1, routed) 0.957 7.134 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_16__0_n_0
|
|
SLICE_X42Y50 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7/I0
|
|
SLICE_X42Y50 LUT6 (Prop_lut6_I0_O) 0.319 7.453 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7/O
|
|
net (fo=1, routed) 0.435 7.888 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7_n_0
|
|
SLICE_X44Y50 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0/I5
|
|
SLICE_X44Y50 LUT6 (Prop_lut6_I5_O) 0.124 8.012 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0/O
|
|
net (fo=10, routed) 0.740 8.753 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0_n_0
|
|
SLICE_X44Y50 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[5]_i_1__0/I3
|
|
SLICE_X44Y50 LUT6 (Prop_lut6_I3_O) 0.124 8.877 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[5]_i_1__0/O
|
|
net (fo=6, routed) 0.845 9.722 u_cpu/u_csr/ms_to_ws_bus[13]
|
|
SLICE_X50Y46 r u_cpu/u_csr/write_buffer_way[1]_i_18/I3
|
|
SLICE_X50Y46 LUT6 (Prop_lut6_I3_O) 0.124 9.846 r u_cpu/u_csr/write_buffer_way[1]_i_18/O
|
|
net (fo=1, routed) 0.000 9.846 u_cpu/u_csr/write_buffer_way[1]_i_18_n_0
|
|
SLICE_X50Y46 r u_cpu/u_csr/write_buffer_way_reg[1]_i_11/S[0]
|
|
SLICE_X50Y46 CARRY4 (Prop_carry4_S[0]_CO[3])
|
|
0.532 10.378 r u_cpu/u_csr/write_buffer_way_reg[1]_i_11/CO[3]
|
|
net (fo=1, routed) 0.000 10.378 u_cpu/u_csr/write_buffer_way_reg[1]_i_11_n_0
|
|
SLICE_X50Y47 r u_cpu/u_csr/write_buffer_way_reg[1]_i_9/CI
|
|
SLICE_X50Y47 CARRY4 (Prop_carry4_CI_CO[1])
|
|
0.157 10.535 f u_cpu/u_csr/write_buffer_way_reg[1]_i_9/CO[1]
|
|
net (fo=2, routed) 0.791 11.326 u_cpu/wb_stage/CO[0]
|
|
SLICE_X46Y39 f u_cpu/wb_stage/write_buffer_way[1]_i_5/I1
|
|
SLICE_X46Y39 LUT6 (Prop_lut6_I1_O) 0.329 11.655 r u_cpu/wb_stage/write_buffer_way[1]_i_5/O
|
|
net (fo=7, routed) 0.762 12.417 u_cpu/addr_trans/tlb_entry/sc_cancel_req
|
|
SLICE_X46Y35 r u_cpu/addr_trans/tlb_entry/main_state[0]_i_3/I1
|
|
SLICE_X46Y35 LUT3 (Prop_lut3_I1_O) 0.124 12.541 r u_cpu/addr_trans/tlb_entry/main_state[0]_i_3/O
|
|
net (fo=3, routed) 0.719 13.260 u_cpu/dcache/main_state_reg[0]_2
|
|
SLICE_X43Y31 r u_cpu/dcache/ds_to_es_bus_r[235]_i_10/I3
|
|
SLICE_X43Y31 LUT6 (Prop_lut6_I3_O) 0.124 13.384 r u_cpu/dcache/ds_to_es_bus_r[235]_i_10/O
|
|
net (fo=3, routed) 0.415 13.799 u_cpu/mem_stage/data_data_ok
|
|
SLICE_X43Y30 r u_cpu/mem_stage/flush_inst_req_buffer[1]_i_15/I0
|
|
SLICE_X43Y30 LUT3 (Prop_lut3_I0_O) 0.124 13.923 r u_cpu/mem_stage/flush_inst_req_buffer[1]_i_15/O
|
|
net (fo=2, routed) 0.833 14.756 u_cpu/mem_stage/es_to_ms_bus_r_reg[70]_1
|
|
SLICE_X48Y30 r u_cpu/mem_stage/flush_inst_req_buffer[1]_i_14/I0
|
|
SLICE_X48Y30 LUT6 (Prop_lut6_I0_O) 0.124 14.880 r u_cpu/mem_stage/flush_inst_req_buffer[1]_i_14/O
|
|
net (fo=1, routed) 0.651 15.532 u_cpu/mem_stage/ms_ready_go
|
|
SLICE_X48Y25 r u_cpu/mem_stage/flush_inst_req_buffer[1]_i_13/I4
|
|
SLICE_X48Y25 LUT6 (Prop_lut6_I4_O) 0.124 15.656 r u_cpu/mem_stage/flush_inst_req_buffer[1]_i_13/O
|
|
net (fo=3, routed) 0.483 16.139 u_cpu/id_stage/flush_inst_req_buffer[31]_i_6
|
|
SLICE_X50Y25 r u_cpu/id_stage/flush_inst_req_buffer[1]_i_9/I1
|
|
SLICE_X50Y25 LUT6 (Prop_lut6_I1_O) 0.124 16.263 r u_cpu/id_stage/flush_inst_req_buffer[1]_i_9/O
|
|
net (fo=32, routed) 0.531 16.794 u_cpu/if_stage/nextpc5
|
|
SLICE_X51Y27 r u_cpu/if_stage/fetch_pc_r[6]_i_4/I2
|
|
SLICE_X51Y27 LUT6 (Prop_lut6_I2_O) 0.124 16.918 r u_cpu/if_stage/fetch_pc_r[6]_i_4/O
|
|
net (fo=1, routed) 3.059 19.977 u_cpu/if_stage/fetch_pc_r[6]_i_4_n_0
|
|
SLICE_X114Y28 r u_cpu/if_stage/fetch_pc_r[6]_i_2/I2
|
|
SLICE_X114Y28 LUT6 (Prop_lut6_I2_O) 0.124 20.101 r u_cpu/if_stage/fetch_pc_r[6]_i_2/O
|
|
net (fo=1, routed) 0.441 20.542 u_cpu/if_stage/fetch_pc_r[6]_i_2_n_0
|
|
SLICE_X114Y25 r u_cpu/if_stage/fetch_pc_r[6]_i_1/I2
|
|
SLICE_X114Y25 LUT6 (Prop_lut6_I2_O) 0.124 20.666 r u_cpu/if_stage/fetch_pc_r[6]_i_1/O
|
|
net (fo=6, routed) 3.249 23.915 u_cpu/icache/tagv_ram_way[1].u/mem_reg_reg_2[2]
|
|
SLICE_X49Y33 r u_cpu/icache/tagv_ram_way[1].u/mem_reg_reg_i_8/I4
|
|
SLICE_X49Y33 LUT5 (Prop_lut5_I4_O) 0.124 24.039 r u_cpu/icache/tagv_ram_way[1].u/mem_reg_reg_i_8/O
|
|
net (fo=16, routed) 1.922 25.962 u_cpu/icache/data_ram_way[0].data_ram_bank[1].u/ADDRBWRADDR[2]
|
|
RAMB18_X1Y3 RAMB18E1 r u_cpu/icache/data_ram_way[0].data_ram_bank[1].u/mem_reg_reg/ADDRBWRADDR[7]
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock cpu_clk rise edge) 30.323 30.323 r
|
|
clock source latency -5.674 24.648
|
|
propagated clock network latency
|
|
3.883 28.531
|
|
clock pessimism -0.418 28.113
|
|
clock uncertainty -0.074 28.039
|
|
RAMB18_X1Y3 RAMB18E1 (Setup_ramb18e1_CLKBWRCLK_ADDRBWRADDR[7])
|
|
-0.566 27.473 u_cpu/icache/data_ram_way[0].data_ram_bank[1].u/mem_reg_reg
|
|
-------------------------------------------------------------------
|
|
required time 27.473
|
|
arrival time -25.962
|
|
-------------------------------------------------------------------
|
|
slack 1.512
|
|
|
|
Slack (MET) : 1.512ns (required time - arrival time)
|
|
Source: u_cpu/addr_trans/data_vaddr_buffer_reg[14]/C
|
|
(rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns})
|
|
Destination: u_cpu/icache/data_ram_way[0].data_ram_bank[1].u/mem_reg_reg/ADDRBWRADDR[7]
|
|
(rising edge-triggered cell RAMB18E1 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns})
|
|
Path Group: cpu_clk
|
|
Path Type: Setup (Max at Slow Process Corner)
|
|
Requirement: 30.323ns (cpu_clk rise@30.323ns - cpu_clk rise@0.000ns)
|
|
Data Path Delay: 28.186ns (logic 5.333ns (18.920%) route 22.853ns (81.079%))
|
|
Logic Levels: 26 (CARRY4=4 LUT3=2 LUT4=1 LUT5=2 LUT6=15 MUXF7=1 MUXF8=1)
|
|
Clock Path Skew: 0.015ns (DCD - SCD + CPR)
|
|
Destination Clock Delay (DCD): -1.791ns = ( 28.531 - 30.323 )
|
|
Source Clock Delay (SCD): -2.225ns
|
|
Clock Pessimism Removal (CPR): -0.418ns
|
|
Clock Uncertainty: 0.074ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Discrete Jitter (DJ): 0.130ns
|
|
Phase Error (PE): 0.000ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock cpu_clk rise edge) 0.000 0.000 r
|
|
clock source latency -6.275 -6.275
|
|
propagated clock network latency
|
|
4.051 -2.225
|
|
SLICE_X35Y35 FDRE 0.000 -2.225 r u_cpu/addr_trans/data_vaddr_buffer_reg[14]/C
|
|
SLICE_X35Y35 FDRE (Prop_fdre_C_Q) 0.456 -1.769 r u_cpu/addr_trans/data_vaddr_buffer_reg[14]/Q
|
|
net (fo=33, routed) 1.442 -0.326 u_cpu/addr_trans/tlb_entry/data_vaddr_buffer[2]
|
|
SLICE_X42Y40 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_226/I5
|
|
SLICE_X42Y40 LUT6 (Prop_lut6_I5_O) 0.124 -0.202 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_226/O
|
|
net (fo=1, routed) 0.000 -0.202 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_226_n_0
|
|
SLICE_X42Y40 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_111/S[0]
|
|
SLICE_X42Y40 CARRY4 (Prop_carry4_S[0]_CO[3])
|
|
0.513 0.311 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_111/CO[3]
|
|
net (fo=1, routed) 0.000 0.311 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_111_n_0
|
|
SLICE_X42Y41 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_32/CI
|
|
SLICE_X42Y41 CARRY4 (Prop_carry4_CI_CO[2])
|
|
0.229 0.540 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_32/CO[2]
|
|
net (fo=1, routed) 1.009 1.549 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_32_n_1
|
|
SLICE_X40Y47 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_9/I1
|
|
SLICE_X40Y47 LUT6 (Prop_lut6_I1_O) 0.310 1.859 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_9/O
|
|
net (fo=2, routed) 0.635 2.494 u_cpu/addr_trans/tlb_entry/match1[28]
|
|
SLICE_X38Y47 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/I2
|
|
SLICE_X38Y47 LUT4 (Prop_lut4_I2_O) 0.124 2.618 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/O
|
|
net (fo=2, routed) 0.667 3.285 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2_n_0
|
|
SLICE_X39Y47 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/I0
|
|
SLICE_X39Y47 LUT5 (Prop_lut5_I0_O) 0.124 3.409 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/O
|
|
net (fo=2, routed) 1.103 4.512 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2_n_0
|
|
SLICE_X38Y50 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/I0
|
|
SLICE_X38Y50 LUT6 (Prop_lut6_I0_O) 0.124 4.636 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/O
|
|
net (fo=89, routed) 1.162 5.797 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus[8]
|
|
SLICE_X42Y51 r u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_38__0/S
|
|
SLICE_X42Y51 MUXF7 (Prop_muxf7_S_O) 0.292 6.089 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_38__0/O
|
|
net (fo=1, routed) 0.000 6.089 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_38__0_n_0
|
|
SLICE_X42Y51 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_16__0/I1
|
|
SLICE_X42Y51 MUXF8 (Prop_muxf8_I1_O) 0.088 6.177 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_16__0/O
|
|
net (fo=1, routed) 0.957 7.134 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_16__0_n_0
|
|
SLICE_X42Y50 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7/I0
|
|
SLICE_X42Y50 LUT6 (Prop_lut6_I0_O) 0.319 7.453 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7/O
|
|
net (fo=1, routed) 0.435 7.888 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7_n_0
|
|
SLICE_X44Y50 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0/I5
|
|
SLICE_X44Y50 LUT6 (Prop_lut6_I5_O) 0.124 8.012 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0/O
|
|
net (fo=10, routed) 0.740 8.753 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0_n_0
|
|
SLICE_X44Y50 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[5]_i_1__0/I3
|
|
SLICE_X44Y50 LUT6 (Prop_lut6_I3_O) 0.124 8.877 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[5]_i_1__0/O
|
|
net (fo=6, routed) 0.845 9.722 u_cpu/u_csr/ms_to_ws_bus[13]
|
|
SLICE_X50Y46 f u_cpu/u_csr/write_buffer_way[1]_i_18/I3
|
|
SLICE_X50Y46 LUT6 (Prop_lut6_I3_O) 0.124 9.846 r u_cpu/u_csr/write_buffer_way[1]_i_18/O
|
|
net (fo=1, routed) 0.000 9.846 u_cpu/u_csr/write_buffer_way[1]_i_18_n_0
|
|
SLICE_X50Y46 r u_cpu/u_csr/write_buffer_way_reg[1]_i_11/S[0]
|
|
SLICE_X50Y46 CARRY4 (Prop_carry4_S[0]_CO[3])
|
|
0.532 10.378 r u_cpu/u_csr/write_buffer_way_reg[1]_i_11/CO[3]
|
|
net (fo=1, routed) 0.000 10.378 u_cpu/u_csr/write_buffer_way_reg[1]_i_11_n_0
|
|
SLICE_X50Y47 r u_cpu/u_csr/write_buffer_way_reg[1]_i_9/CI
|
|
SLICE_X50Y47 CARRY4 (Prop_carry4_CI_CO[1])
|
|
0.157 10.535 f u_cpu/u_csr/write_buffer_way_reg[1]_i_9/CO[1]
|
|
net (fo=2, routed) 0.791 11.326 u_cpu/wb_stage/CO[0]
|
|
SLICE_X46Y39 f u_cpu/wb_stage/write_buffer_way[1]_i_5/I1
|
|
SLICE_X46Y39 LUT6 (Prop_lut6_I1_O) 0.329 11.655 r u_cpu/wb_stage/write_buffer_way[1]_i_5/O
|
|
net (fo=7, routed) 0.762 12.417 u_cpu/addr_trans/tlb_entry/sc_cancel_req
|
|
SLICE_X46Y35 r u_cpu/addr_trans/tlb_entry/main_state[0]_i_3/I1
|
|
SLICE_X46Y35 LUT3 (Prop_lut3_I1_O) 0.124 12.541 r u_cpu/addr_trans/tlb_entry/main_state[0]_i_3/O
|
|
net (fo=3, routed) 0.719 13.260 u_cpu/dcache/main_state_reg[0]_2
|
|
SLICE_X43Y31 r u_cpu/dcache/ds_to_es_bus_r[235]_i_10/I3
|
|
SLICE_X43Y31 LUT6 (Prop_lut6_I3_O) 0.124 13.384 r u_cpu/dcache/ds_to_es_bus_r[235]_i_10/O
|
|
net (fo=3, routed) 0.415 13.799 u_cpu/mem_stage/data_data_ok
|
|
SLICE_X43Y30 r u_cpu/mem_stage/flush_inst_req_buffer[1]_i_15/I0
|
|
SLICE_X43Y30 LUT3 (Prop_lut3_I0_O) 0.124 13.923 r u_cpu/mem_stage/flush_inst_req_buffer[1]_i_15/O
|
|
net (fo=2, routed) 0.833 14.756 u_cpu/mem_stage/es_to_ms_bus_r_reg[70]_1
|
|
SLICE_X48Y30 r u_cpu/mem_stage/flush_inst_req_buffer[1]_i_14/I0
|
|
SLICE_X48Y30 LUT6 (Prop_lut6_I0_O) 0.124 14.880 r u_cpu/mem_stage/flush_inst_req_buffer[1]_i_14/O
|
|
net (fo=1, routed) 0.651 15.532 u_cpu/mem_stage/ms_ready_go
|
|
SLICE_X48Y25 r u_cpu/mem_stage/flush_inst_req_buffer[1]_i_13/I4
|
|
SLICE_X48Y25 LUT6 (Prop_lut6_I4_O) 0.124 15.656 r u_cpu/mem_stage/flush_inst_req_buffer[1]_i_13/O
|
|
net (fo=3, routed) 0.483 16.139 u_cpu/id_stage/flush_inst_req_buffer[31]_i_6
|
|
SLICE_X50Y25 r u_cpu/id_stage/flush_inst_req_buffer[1]_i_9/I1
|
|
SLICE_X50Y25 LUT6 (Prop_lut6_I1_O) 0.124 16.263 r u_cpu/id_stage/flush_inst_req_buffer[1]_i_9/O
|
|
net (fo=32, routed) 0.531 16.794 u_cpu/if_stage/nextpc5
|
|
SLICE_X51Y27 r u_cpu/if_stage/fetch_pc_r[6]_i_4/I2
|
|
SLICE_X51Y27 LUT6 (Prop_lut6_I2_O) 0.124 16.918 r u_cpu/if_stage/fetch_pc_r[6]_i_4/O
|
|
net (fo=1, routed) 3.059 19.977 u_cpu/if_stage/fetch_pc_r[6]_i_4_n_0
|
|
SLICE_X114Y28 r u_cpu/if_stage/fetch_pc_r[6]_i_2/I2
|
|
SLICE_X114Y28 LUT6 (Prop_lut6_I2_O) 0.124 20.101 r u_cpu/if_stage/fetch_pc_r[6]_i_2/O
|
|
net (fo=1, routed) 0.441 20.542 u_cpu/if_stage/fetch_pc_r[6]_i_2_n_0
|
|
SLICE_X114Y25 r u_cpu/if_stage/fetch_pc_r[6]_i_1/I2
|
|
SLICE_X114Y25 LUT6 (Prop_lut6_I2_O) 0.124 20.666 r u_cpu/if_stage/fetch_pc_r[6]_i_1/O
|
|
net (fo=6, routed) 3.249 23.915 u_cpu/icache/tagv_ram_way[1].u/mem_reg_reg_2[2]
|
|
SLICE_X49Y33 r u_cpu/icache/tagv_ram_way[1].u/mem_reg_reg_i_8/I4
|
|
SLICE_X49Y33 LUT5 (Prop_lut5_I4_O) 0.124 24.039 r u_cpu/icache/tagv_ram_way[1].u/mem_reg_reg_i_8/O
|
|
net (fo=16, routed) 1.922 25.962 u_cpu/icache/data_ram_way[0].data_ram_bank[1].u/ADDRBWRADDR[2]
|
|
RAMB18_X1Y3 RAMB18E1 r u_cpu/icache/data_ram_way[0].data_ram_bank[1].u/mem_reg_reg/ADDRBWRADDR[7]
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock cpu_clk rise edge) 30.323 30.323 r
|
|
clock source latency -5.674 24.648
|
|
propagated clock network latency
|
|
3.883 28.531
|
|
clock pessimism -0.418 28.113
|
|
clock uncertainty -0.074 28.039
|
|
RAMB18_X1Y3 RAMB18E1 (Setup_ramb18e1_CLKBWRCLK_ADDRBWRADDR[7])
|
|
-0.566 27.473 u_cpu/icache/data_ram_way[0].data_ram_bank[1].u/mem_reg_reg
|
|
-------------------------------------------------------------------
|
|
required time 27.473
|
|
arrival time -25.962
|
|
-------------------------------------------------------------------
|
|
slack 1.512
|
|
|
|
Slack (MET) : 1.512ns (required time - arrival time)
|
|
Source: u_cpu/addr_trans/data_vaddr_buffer_reg[14]/C
|
|
(rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns})
|
|
Destination: u_cpu/icache/data_ram_way[0].data_ram_bank[1].u/mem_reg_reg/ADDRBWRADDR[7]
|
|
(rising edge-triggered cell RAMB18E1 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns})
|
|
Path Group: cpu_clk
|
|
Path Type: Setup (Max at Slow Process Corner)
|
|
Requirement: 30.323ns (cpu_clk rise@30.323ns - cpu_clk rise@0.000ns)
|
|
Data Path Delay: 28.186ns (logic 5.333ns (18.920%) route 22.853ns (81.079%))
|
|
Logic Levels: 26 (CARRY4=4 LUT3=2 LUT4=1 LUT5=2 LUT6=15 MUXF7=1 MUXF8=1)
|
|
Clock Path Skew: 0.015ns (DCD - SCD + CPR)
|
|
Destination Clock Delay (DCD): -1.791ns = ( 28.531 - 30.323 )
|
|
Source Clock Delay (SCD): -2.225ns
|
|
Clock Pessimism Removal (CPR): -0.418ns
|
|
Clock Uncertainty: 0.074ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Discrete Jitter (DJ): 0.130ns
|
|
Phase Error (PE): 0.000ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock cpu_clk rise edge) 0.000 0.000 r
|
|
clock source latency -6.275 -6.275
|
|
propagated clock network latency
|
|
4.051 -2.225
|
|
SLICE_X35Y35 FDRE 0.000 -2.225 r u_cpu/addr_trans/data_vaddr_buffer_reg[14]/C
|
|
SLICE_X35Y35 FDRE (Prop_fdre_C_Q) 0.456 -1.769 r u_cpu/addr_trans/data_vaddr_buffer_reg[14]/Q
|
|
net (fo=33, routed) 1.442 -0.326 u_cpu/addr_trans/tlb_entry/data_vaddr_buffer[2]
|
|
SLICE_X42Y40 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_226/I5
|
|
SLICE_X42Y40 LUT6 (Prop_lut6_I5_O) 0.124 -0.202 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_226/O
|
|
net (fo=1, routed) 0.000 -0.202 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_226_n_0
|
|
SLICE_X42Y40 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_111/S[0]
|
|
SLICE_X42Y40 CARRY4 (Prop_carry4_S[0]_CO[3])
|
|
0.513 0.311 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_111/CO[3]
|
|
net (fo=1, routed) 0.000 0.311 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_111_n_0
|
|
SLICE_X42Y41 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_32/CI
|
|
SLICE_X42Y41 CARRY4 (Prop_carry4_CI_CO[2])
|
|
0.229 0.540 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_32/CO[2]
|
|
net (fo=1, routed) 1.009 1.549 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_32_n_1
|
|
SLICE_X40Y47 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_9/I1
|
|
SLICE_X40Y47 LUT6 (Prop_lut6_I1_O) 0.310 1.859 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_9/O
|
|
net (fo=2, routed) 0.635 2.494 u_cpu/addr_trans/tlb_entry/match1[28]
|
|
SLICE_X38Y47 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/I2
|
|
SLICE_X38Y47 LUT4 (Prop_lut4_I2_O) 0.124 2.618 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/O
|
|
net (fo=2, routed) 0.667 3.285 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2_n_0
|
|
SLICE_X39Y47 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/I0
|
|
SLICE_X39Y47 LUT5 (Prop_lut5_I0_O) 0.124 3.409 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/O
|
|
net (fo=2, routed) 1.103 4.512 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2_n_0
|
|
SLICE_X38Y50 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/I0
|
|
SLICE_X38Y50 LUT6 (Prop_lut6_I0_O) 0.124 4.636 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/O
|
|
net (fo=89, routed) 1.162 5.797 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus[8]
|
|
SLICE_X42Y51 r u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_38__0/S
|
|
SLICE_X42Y51 MUXF7 (Prop_muxf7_S_O) 0.292 6.089 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_38__0/O
|
|
net (fo=1, routed) 0.000 6.089 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_38__0_n_0
|
|
SLICE_X42Y51 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_16__0/I1
|
|
SLICE_X42Y51 MUXF8 (Prop_muxf8_I1_O) 0.088 6.177 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_16__0/O
|
|
net (fo=1, routed) 0.957 7.134 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_16__0_n_0
|
|
SLICE_X42Y50 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7/I0
|
|
SLICE_X42Y50 LUT6 (Prop_lut6_I0_O) 0.319 7.453 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7/O
|
|
net (fo=1, routed) 0.435 7.888 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7_n_0
|
|
SLICE_X44Y50 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0/I5
|
|
SLICE_X44Y50 LUT6 (Prop_lut6_I5_O) 0.124 8.012 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0/O
|
|
net (fo=10, routed) 0.740 8.753 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0_n_0
|
|
SLICE_X44Y50 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[5]_i_1__0/I3
|
|
SLICE_X44Y50 LUT6 (Prop_lut6_I3_O) 0.124 8.877 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[5]_i_1__0/O
|
|
net (fo=6, routed) 0.845 9.722 u_cpu/u_csr/ms_to_ws_bus[13]
|
|
SLICE_X50Y46 r u_cpu/u_csr/write_buffer_way[1]_i_18/I3
|
|
SLICE_X50Y46 LUT6 (Prop_lut6_I3_O) 0.124 9.846 f u_cpu/u_csr/write_buffer_way[1]_i_18/O
|
|
net (fo=1, routed) 0.000 9.846 u_cpu/u_csr/write_buffer_way[1]_i_18_n_0
|
|
SLICE_X50Y46 f u_cpu/u_csr/write_buffer_way_reg[1]_i_11/S[0]
|
|
SLICE_X50Y46 CARRY4 (Prop_carry4_S[0]_CO[3])
|
|
0.532 10.378 r u_cpu/u_csr/write_buffer_way_reg[1]_i_11/CO[3]
|
|
net (fo=1, routed) 0.000 10.378 u_cpu/u_csr/write_buffer_way_reg[1]_i_11_n_0
|
|
SLICE_X50Y47 r u_cpu/u_csr/write_buffer_way_reg[1]_i_9/CI
|
|
SLICE_X50Y47 CARRY4 (Prop_carry4_CI_CO[1])
|
|
0.157 10.535 f u_cpu/u_csr/write_buffer_way_reg[1]_i_9/CO[1]
|
|
net (fo=2, routed) 0.791 11.326 u_cpu/wb_stage/CO[0]
|
|
SLICE_X46Y39 f u_cpu/wb_stage/write_buffer_way[1]_i_5/I1
|
|
SLICE_X46Y39 LUT6 (Prop_lut6_I1_O) 0.329 11.655 r u_cpu/wb_stage/write_buffer_way[1]_i_5/O
|
|
net (fo=7, routed) 0.762 12.417 u_cpu/addr_trans/tlb_entry/sc_cancel_req
|
|
SLICE_X46Y35 r u_cpu/addr_trans/tlb_entry/main_state[0]_i_3/I1
|
|
SLICE_X46Y35 LUT3 (Prop_lut3_I1_O) 0.124 12.541 r u_cpu/addr_trans/tlb_entry/main_state[0]_i_3/O
|
|
net (fo=3, routed) 0.719 13.260 u_cpu/dcache/main_state_reg[0]_2
|
|
SLICE_X43Y31 r u_cpu/dcache/ds_to_es_bus_r[235]_i_10/I3
|
|
SLICE_X43Y31 LUT6 (Prop_lut6_I3_O) 0.124 13.384 r u_cpu/dcache/ds_to_es_bus_r[235]_i_10/O
|
|
net (fo=3, routed) 0.415 13.799 u_cpu/mem_stage/data_data_ok
|
|
SLICE_X43Y30 r u_cpu/mem_stage/flush_inst_req_buffer[1]_i_15/I0
|
|
SLICE_X43Y30 LUT3 (Prop_lut3_I0_O) 0.124 13.923 r u_cpu/mem_stage/flush_inst_req_buffer[1]_i_15/O
|
|
net (fo=2, routed) 0.833 14.756 u_cpu/mem_stage/es_to_ms_bus_r_reg[70]_1
|
|
SLICE_X48Y30 r u_cpu/mem_stage/flush_inst_req_buffer[1]_i_14/I0
|
|
SLICE_X48Y30 LUT6 (Prop_lut6_I0_O) 0.124 14.880 r u_cpu/mem_stage/flush_inst_req_buffer[1]_i_14/O
|
|
net (fo=1, routed) 0.651 15.532 u_cpu/mem_stage/ms_ready_go
|
|
SLICE_X48Y25 r u_cpu/mem_stage/flush_inst_req_buffer[1]_i_13/I4
|
|
SLICE_X48Y25 LUT6 (Prop_lut6_I4_O) 0.124 15.656 r u_cpu/mem_stage/flush_inst_req_buffer[1]_i_13/O
|
|
net (fo=3, routed) 0.483 16.139 u_cpu/id_stage/flush_inst_req_buffer[31]_i_6
|
|
SLICE_X50Y25 r u_cpu/id_stage/flush_inst_req_buffer[1]_i_9/I1
|
|
SLICE_X50Y25 LUT6 (Prop_lut6_I1_O) 0.124 16.263 r u_cpu/id_stage/flush_inst_req_buffer[1]_i_9/O
|
|
net (fo=32, routed) 0.531 16.794 u_cpu/if_stage/nextpc5
|
|
SLICE_X51Y27 r u_cpu/if_stage/fetch_pc_r[6]_i_4/I2
|
|
SLICE_X51Y27 LUT6 (Prop_lut6_I2_O) 0.124 16.918 r u_cpu/if_stage/fetch_pc_r[6]_i_4/O
|
|
net (fo=1, routed) 3.059 19.977 u_cpu/if_stage/fetch_pc_r[6]_i_4_n_0
|
|
SLICE_X114Y28 r u_cpu/if_stage/fetch_pc_r[6]_i_2/I2
|
|
SLICE_X114Y28 LUT6 (Prop_lut6_I2_O) 0.124 20.101 r u_cpu/if_stage/fetch_pc_r[6]_i_2/O
|
|
net (fo=1, routed) 0.441 20.542 u_cpu/if_stage/fetch_pc_r[6]_i_2_n_0
|
|
SLICE_X114Y25 r u_cpu/if_stage/fetch_pc_r[6]_i_1/I2
|
|
SLICE_X114Y25 LUT6 (Prop_lut6_I2_O) 0.124 20.666 r u_cpu/if_stage/fetch_pc_r[6]_i_1/O
|
|
net (fo=6, routed) 3.249 23.915 u_cpu/icache/tagv_ram_way[1].u/mem_reg_reg_2[2]
|
|
SLICE_X49Y33 r u_cpu/icache/tagv_ram_way[1].u/mem_reg_reg_i_8/I4
|
|
SLICE_X49Y33 LUT5 (Prop_lut5_I4_O) 0.124 24.039 r u_cpu/icache/tagv_ram_way[1].u/mem_reg_reg_i_8/O
|
|
net (fo=16, routed) 1.922 25.962 u_cpu/icache/data_ram_way[0].data_ram_bank[1].u/ADDRBWRADDR[2]
|
|
RAMB18_X1Y3 RAMB18E1 r u_cpu/icache/data_ram_way[0].data_ram_bank[1].u/mem_reg_reg/ADDRBWRADDR[7]
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock cpu_clk rise edge) 30.323 30.323 r
|
|
clock source latency -5.674 24.648
|
|
propagated clock network latency
|
|
3.883 28.531
|
|
clock pessimism -0.418 28.113
|
|
clock uncertainty -0.074 28.039
|
|
RAMB18_X1Y3 RAMB18E1 (Setup_ramb18e1_CLKBWRCLK_ADDRBWRADDR[7])
|
|
-0.566 27.473 u_cpu/icache/data_ram_way[0].data_ram_bank[1].u/mem_reg_reg
|
|
-------------------------------------------------------------------
|
|
required time 27.473
|
|
arrival time -25.962
|
|
-------------------------------------------------------------------
|
|
slack 1.512
|
|
|
|
Slack (MET) : 1.512ns (required time - arrival time)
|
|
Source: u_cpu/addr_trans/data_vaddr_buffer_reg[14]/C
|
|
(rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns})
|
|
Destination: u_cpu/icache/data_ram_way[0].data_ram_bank[1].u/mem_reg_reg/ADDRBWRADDR[7]
|
|
(rising edge-triggered cell RAMB18E1 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns})
|
|
Path Group: cpu_clk
|
|
Path Type: Setup (Max at Slow Process Corner)
|
|
Requirement: 30.323ns (cpu_clk rise@30.323ns - cpu_clk rise@0.000ns)
|
|
Data Path Delay: 28.186ns (logic 5.333ns (18.920%) route 22.853ns (81.079%))
|
|
Logic Levels: 26 (CARRY4=4 LUT3=2 LUT4=1 LUT5=2 LUT6=15 MUXF7=1 MUXF8=1)
|
|
Clock Path Skew: 0.015ns (DCD - SCD + CPR)
|
|
Destination Clock Delay (DCD): -1.791ns = ( 28.531 - 30.323 )
|
|
Source Clock Delay (SCD): -2.225ns
|
|
Clock Pessimism Removal (CPR): -0.418ns
|
|
Clock Uncertainty: 0.074ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Discrete Jitter (DJ): 0.130ns
|
|
Phase Error (PE): 0.000ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock cpu_clk rise edge) 0.000 0.000 r
|
|
clock source latency -6.275 -6.275
|
|
propagated clock network latency
|
|
4.051 -2.225
|
|
SLICE_X35Y35 FDRE 0.000 -2.225 r u_cpu/addr_trans/data_vaddr_buffer_reg[14]/C
|
|
SLICE_X35Y35 FDRE (Prop_fdre_C_Q) 0.456 -1.769 r u_cpu/addr_trans/data_vaddr_buffer_reg[14]/Q
|
|
net (fo=33, routed) 1.442 -0.326 u_cpu/addr_trans/tlb_entry/data_vaddr_buffer[2]
|
|
SLICE_X42Y40 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_226/I5
|
|
SLICE_X42Y40 LUT6 (Prop_lut6_I5_O) 0.124 -0.202 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_226/O
|
|
net (fo=1, routed) 0.000 -0.202 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_226_n_0
|
|
SLICE_X42Y40 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_111/S[0]
|
|
SLICE_X42Y40 CARRY4 (Prop_carry4_S[0]_CO[3])
|
|
0.513 0.311 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_111/CO[3]
|
|
net (fo=1, routed) 0.000 0.311 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_111_n_0
|
|
SLICE_X42Y41 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_32/CI
|
|
SLICE_X42Y41 CARRY4 (Prop_carry4_CI_CO[2])
|
|
0.229 0.540 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_32/CO[2]
|
|
net (fo=1, routed) 1.009 1.549 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_32_n_1
|
|
SLICE_X40Y47 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_9/I1
|
|
SLICE_X40Y47 LUT6 (Prop_lut6_I1_O) 0.310 1.859 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_9/O
|
|
net (fo=2, routed) 0.635 2.494 u_cpu/addr_trans/tlb_entry/match1[28]
|
|
SLICE_X38Y47 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/I2
|
|
SLICE_X38Y47 LUT4 (Prop_lut4_I2_O) 0.124 2.618 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/O
|
|
net (fo=2, routed) 0.667 3.285 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2_n_0
|
|
SLICE_X39Y47 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/I0
|
|
SLICE_X39Y47 LUT5 (Prop_lut5_I0_O) 0.124 3.409 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/O
|
|
net (fo=2, routed) 1.103 4.512 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2_n_0
|
|
SLICE_X38Y50 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/I0
|
|
SLICE_X38Y50 LUT6 (Prop_lut6_I0_O) 0.124 4.636 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/O
|
|
net (fo=89, routed) 1.162 5.797 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus[8]
|
|
SLICE_X42Y51 r u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_38__0/S
|
|
SLICE_X42Y51 MUXF7 (Prop_muxf7_S_O) 0.292 6.089 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_38__0/O
|
|
net (fo=1, routed) 0.000 6.089 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_38__0_n_0
|
|
SLICE_X42Y51 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_16__0/I1
|
|
SLICE_X42Y51 MUXF8 (Prop_muxf8_I1_O) 0.088 6.177 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_16__0/O
|
|
net (fo=1, routed) 0.957 7.134 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_16__0_n_0
|
|
SLICE_X42Y50 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7/I0
|
|
SLICE_X42Y50 LUT6 (Prop_lut6_I0_O) 0.319 7.453 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7/O
|
|
net (fo=1, routed) 0.435 7.888 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7_n_0
|
|
SLICE_X44Y50 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0/I5
|
|
SLICE_X44Y50 LUT6 (Prop_lut6_I5_O) 0.124 8.012 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0/O
|
|
net (fo=10, routed) 0.740 8.753 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0_n_0
|
|
SLICE_X44Y50 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[5]_i_1__0/I3
|
|
SLICE_X44Y50 LUT6 (Prop_lut6_I3_O) 0.124 8.877 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[5]_i_1__0/O
|
|
net (fo=6, routed) 0.845 9.722 u_cpu/u_csr/ms_to_ws_bus[13]
|
|
SLICE_X50Y46 f u_cpu/u_csr/write_buffer_way[1]_i_18/I3
|
|
SLICE_X50Y46 LUT6 (Prop_lut6_I3_O) 0.124 9.846 f u_cpu/u_csr/write_buffer_way[1]_i_18/O
|
|
net (fo=1, routed) 0.000 9.846 u_cpu/u_csr/write_buffer_way[1]_i_18_n_0
|
|
SLICE_X50Y46 f u_cpu/u_csr/write_buffer_way_reg[1]_i_11/S[0]
|
|
SLICE_X50Y46 CARRY4 (Prop_carry4_S[0]_CO[3])
|
|
0.532 10.378 r u_cpu/u_csr/write_buffer_way_reg[1]_i_11/CO[3]
|
|
net (fo=1, routed) 0.000 10.378 u_cpu/u_csr/write_buffer_way_reg[1]_i_11_n_0
|
|
SLICE_X50Y47 r u_cpu/u_csr/write_buffer_way_reg[1]_i_9/CI
|
|
SLICE_X50Y47 CARRY4 (Prop_carry4_CI_CO[1])
|
|
0.157 10.535 f u_cpu/u_csr/write_buffer_way_reg[1]_i_9/CO[1]
|
|
net (fo=2, routed) 0.791 11.326 u_cpu/wb_stage/CO[0]
|
|
SLICE_X46Y39 f u_cpu/wb_stage/write_buffer_way[1]_i_5/I1
|
|
SLICE_X46Y39 LUT6 (Prop_lut6_I1_O) 0.329 11.655 r u_cpu/wb_stage/write_buffer_way[1]_i_5/O
|
|
net (fo=7, routed) 0.762 12.417 u_cpu/addr_trans/tlb_entry/sc_cancel_req
|
|
SLICE_X46Y35 r u_cpu/addr_trans/tlb_entry/main_state[0]_i_3/I1
|
|
SLICE_X46Y35 LUT3 (Prop_lut3_I1_O) 0.124 12.541 r u_cpu/addr_trans/tlb_entry/main_state[0]_i_3/O
|
|
net (fo=3, routed) 0.719 13.260 u_cpu/dcache/main_state_reg[0]_2
|
|
SLICE_X43Y31 r u_cpu/dcache/ds_to_es_bus_r[235]_i_10/I3
|
|
SLICE_X43Y31 LUT6 (Prop_lut6_I3_O) 0.124 13.384 r u_cpu/dcache/ds_to_es_bus_r[235]_i_10/O
|
|
net (fo=3, routed) 0.415 13.799 u_cpu/mem_stage/data_data_ok
|
|
SLICE_X43Y30 r u_cpu/mem_stage/flush_inst_req_buffer[1]_i_15/I0
|
|
SLICE_X43Y30 LUT3 (Prop_lut3_I0_O) 0.124 13.923 r u_cpu/mem_stage/flush_inst_req_buffer[1]_i_15/O
|
|
net (fo=2, routed) 0.833 14.756 u_cpu/mem_stage/es_to_ms_bus_r_reg[70]_1
|
|
SLICE_X48Y30 r u_cpu/mem_stage/flush_inst_req_buffer[1]_i_14/I0
|
|
SLICE_X48Y30 LUT6 (Prop_lut6_I0_O) 0.124 14.880 r u_cpu/mem_stage/flush_inst_req_buffer[1]_i_14/O
|
|
net (fo=1, routed) 0.651 15.532 u_cpu/mem_stage/ms_ready_go
|
|
SLICE_X48Y25 r u_cpu/mem_stage/flush_inst_req_buffer[1]_i_13/I4
|
|
SLICE_X48Y25 LUT6 (Prop_lut6_I4_O) 0.124 15.656 r u_cpu/mem_stage/flush_inst_req_buffer[1]_i_13/O
|
|
net (fo=3, routed) 0.483 16.139 u_cpu/id_stage/flush_inst_req_buffer[31]_i_6
|
|
SLICE_X50Y25 r u_cpu/id_stage/flush_inst_req_buffer[1]_i_9/I1
|
|
SLICE_X50Y25 LUT6 (Prop_lut6_I1_O) 0.124 16.263 r u_cpu/id_stage/flush_inst_req_buffer[1]_i_9/O
|
|
net (fo=32, routed) 0.531 16.794 u_cpu/if_stage/nextpc5
|
|
SLICE_X51Y27 r u_cpu/if_stage/fetch_pc_r[6]_i_4/I2
|
|
SLICE_X51Y27 LUT6 (Prop_lut6_I2_O) 0.124 16.918 r u_cpu/if_stage/fetch_pc_r[6]_i_4/O
|
|
net (fo=1, routed) 3.059 19.977 u_cpu/if_stage/fetch_pc_r[6]_i_4_n_0
|
|
SLICE_X114Y28 r u_cpu/if_stage/fetch_pc_r[6]_i_2/I2
|
|
SLICE_X114Y28 LUT6 (Prop_lut6_I2_O) 0.124 20.101 r u_cpu/if_stage/fetch_pc_r[6]_i_2/O
|
|
net (fo=1, routed) 0.441 20.542 u_cpu/if_stage/fetch_pc_r[6]_i_2_n_0
|
|
SLICE_X114Y25 r u_cpu/if_stage/fetch_pc_r[6]_i_1/I2
|
|
SLICE_X114Y25 LUT6 (Prop_lut6_I2_O) 0.124 20.666 r u_cpu/if_stage/fetch_pc_r[6]_i_1/O
|
|
net (fo=6, routed) 3.249 23.915 u_cpu/icache/tagv_ram_way[1].u/mem_reg_reg_2[2]
|
|
SLICE_X49Y33 r u_cpu/icache/tagv_ram_way[1].u/mem_reg_reg_i_8/I4
|
|
SLICE_X49Y33 LUT5 (Prop_lut5_I4_O) 0.124 24.039 r u_cpu/icache/tagv_ram_way[1].u/mem_reg_reg_i_8/O
|
|
net (fo=16, routed) 1.922 25.962 u_cpu/icache/data_ram_way[0].data_ram_bank[1].u/ADDRBWRADDR[2]
|
|
RAMB18_X1Y3 RAMB18E1 r u_cpu/icache/data_ram_way[0].data_ram_bank[1].u/mem_reg_reg/ADDRBWRADDR[7]
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock cpu_clk rise edge) 30.323 30.323 r
|
|
clock source latency -5.674 24.648
|
|
propagated clock network latency
|
|
3.883 28.531
|
|
clock pessimism -0.418 28.113
|
|
clock uncertainty -0.074 28.039
|
|
RAMB18_X1Y3 RAMB18E1 (Setup_ramb18e1_CLKBWRCLK_ADDRBWRADDR[7])
|
|
-0.566 27.473 u_cpu/icache/data_ram_way[0].data_ram_bank[1].u/mem_reg_reg
|
|
-------------------------------------------------------------------
|
|
required time 27.473
|
|
arrival time -25.962
|
|
-------------------------------------------------------------------
|
|
slack 1.512
|
|
|
|
Slack (MET) : 1.512ns (required time - arrival time)
|
|
Source: u_cpu/addr_trans/data_vaddr_buffer_reg[14]/C
|
|
(rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns})
|
|
Destination: u_cpu/icache/data_ram_way[0].data_ram_bank[1].u/mem_reg_reg/ADDRBWRADDR[7]
|
|
(rising edge-triggered cell RAMB18E1 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns})
|
|
Path Group: cpu_clk
|
|
Path Type: Setup (Max at Slow Process Corner)
|
|
Requirement: 30.323ns (cpu_clk rise@30.323ns - cpu_clk rise@0.000ns)
|
|
Data Path Delay: 28.186ns (logic 5.333ns (18.920%) route 22.853ns (81.079%))
|
|
Logic Levels: 26 (CARRY4=4 LUT3=2 LUT4=1 LUT5=2 LUT6=15 MUXF7=1 MUXF8=1)
|
|
Clock Path Skew: 0.015ns (DCD - SCD + CPR)
|
|
Destination Clock Delay (DCD): -1.791ns = ( 28.531 - 30.323 )
|
|
Source Clock Delay (SCD): -2.225ns
|
|
Clock Pessimism Removal (CPR): -0.418ns
|
|
Clock Uncertainty: 0.074ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Discrete Jitter (DJ): 0.130ns
|
|
Phase Error (PE): 0.000ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock cpu_clk rise edge) 0.000 0.000 r
|
|
clock source latency -6.275 -6.275
|
|
propagated clock network latency
|
|
4.051 -2.225
|
|
SLICE_X35Y35 FDRE 0.000 -2.225 r u_cpu/addr_trans/data_vaddr_buffer_reg[14]/C
|
|
SLICE_X35Y35 FDRE (Prop_fdre_C_Q) 0.456 -1.769 r u_cpu/addr_trans/data_vaddr_buffer_reg[14]/Q
|
|
net (fo=33, routed) 1.442 -0.326 u_cpu/addr_trans/tlb_entry/data_vaddr_buffer[2]
|
|
SLICE_X42Y40 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_226/I5
|
|
SLICE_X42Y40 LUT6 (Prop_lut6_I5_O) 0.124 -0.202 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_226/O
|
|
net (fo=1, routed) 0.000 -0.202 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_226_n_0
|
|
SLICE_X42Y40 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_111/S[0]
|
|
SLICE_X42Y40 CARRY4 (Prop_carry4_S[0]_CO[3])
|
|
0.513 0.311 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_111/CO[3]
|
|
net (fo=1, routed) 0.000 0.311 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_111_n_0
|
|
SLICE_X42Y41 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_32/CI
|
|
SLICE_X42Y41 CARRY4 (Prop_carry4_CI_CO[2])
|
|
0.229 0.540 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_32/CO[2]
|
|
net (fo=1, routed) 1.009 1.549 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_32_n_1
|
|
SLICE_X40Y47 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_9/I1
|
|
SLICE_X40Y47 LUT6 (Prop_lut6_I1_O) 0.310 1.859 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_9/O
|
|
net (fo=2, routed) 0.635 2.494 u_cpu/addr_trans/tlb_entry/match1[28]
|
|
SLICE_X38Y47 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/I2
|
|
SLICE_X38Y47 LUT4 (Prop_lut4_I2_O) 0.124 2.618 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/O
|
|
net (fo=2, routed) 0.667 3.285 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2_n_0
|
|
SLICE_X39Y47 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/I0
|
|
SLICE_X39Y47 LUT5 (Prop_lut5_I0_O) 0.124 3.409 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/O
|
|
net (fo=2, routed) 1.103 4.512 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2_n_0
|
|
SLICE_X38Y50 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/I0
|
|
SLICE_X38Y50 LUT6 (Prop_lut6_I0_O) 0.124 4.636 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/O
|
|
net (fo=89, routed) 1.162 5.797 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus[8]
|
|
SLICE_X42Y51 r u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_38__0/S
|
|
SLICE_X42Y51 MUXF7 (Prop_muxf7_S_O) 0.292 6.089 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_38__0/O
|
|
net (fo=1, routed) 0.000 6.089 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_38__0_n_0
|
|
SLICE_X42Y51 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_16__0/I1
|
|
SLICE_X42Y51 MUXF8 (Prop_muxf8_I1_O) 0.088 6.177 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_16__0/O
|
|
net (fo=1, routed) 0.957 7.134 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_16__0_n_0
|
|
SLICE_X42Y50 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7/I0
|
|
SLICE_X42Y50 LUT6 (Prop_lut6_I0_O) 0.319 7.453 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7/O
|
|
net (fo=1, routed) 0.435 7.888 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7_n_0
|
|
SLICE_X44Y50 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0/I5
|
|
SLICE_X44Y50 LUT6 (Prop_lut6_I5_O) 0.124 8.012 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0/O
|
|
net (fo=10, routed) 0.740 8.753 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0_n_0
|
|
SLICE_X44Y50 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[5]_i_1__0/I3
|
|
SLICE_X44Y50 LUT6 (Prop_lut6_I3_O) 0.124 8.877 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[5]_i_1__0/O
|
|
net (fo=6, routed) 0.845 9.722 u_cpu/u_csr/ms_to_ws_bus[13]
|
|
SLICE_X50Y46 r u_cpu/u_csr/write_buffer_way[1]_i_18/I3
|
|
SLICE_X50Y46 LUT6 (Prop_lut6_I3_O) 0.124 9.846 r u_cpu/u_csr/write_buffer_way[1]_i_18/O
|
|
net (fo=1, routed) 0.000 9.846 u_cpu/u_csr/write_buffer_way[1]_i_18_n_0
|
|
SLICE_X50Y46 r u_cpu/u_csr/write_buffer_way_reg[1]_i_11/S[0]
|
|
SLICE_X50Y46 CARRY4 (Prop_carry4_S[0]_CO[3])
|
|
0.532 10.378 f u_cpu/u_csr/write_buffer_way_reg[1]_i_11/CO[3]
|
|
net (fo=1, routed) 0.000 10.378 u_cpu/u_csr/write_buffer_way_reg[1]_i_11_n_0
|
|
SLICE_X50Y47 f u_cpu/u_csr/write_buffer_way_reg[1]_i_9/CI
|
|
SLICE_X50Y47 CARRY4 (Prop_carry4_CI_CO[1])
|
|
0.157 10.535 f u_cpu/u_csr/write_buffer_way_reg[1]_i_9/CO[1]
|
|
net (fo=2, routed) 0.791 11.326 u_cpu/wb_stage/CO[0]
|
|
SLICE_X46Y39 f u_cpu/wb_stage/write_buffer_way[1]_i_5/I1
|
|
SLICE_X46Y39 LUT6 (Prop_lut6_I1_O) 0.329 11.655 r u_cpu/wb_stage/write_buffer_way[1]_i_5/O
|
|
net (fo=7, routed) 0.762 12.417 u_cpu/addr_trans/tlb_entry/sc_cancel_req
|
|
SLICE_X46Y35 r u_cpu/addr_trans/tlb_entry/main_state[0]_i_3/I1
|
|
SLICE_X46Y35 LUT3 (Prop_lut3_I1_O) 0.124 12.541 r u_cpu/addr_trans/tlb_entry/main_state[0]_i_3/O
|
|
net (fo=3, routed) 0.719 13.260 u_cpu/dcache/main_state_reg[0]_2
|
|
SLICE_X43Y31 r u_cpu/dcache/ds_to_es_bus_r[235]_i_10/I3
|
|
SLICE_X43Y31 LUT6 (Prop_lut6_I3_O) 0.124 13.384 r u_cpu/dcache/ds_to_es_bus_r[235]_i_10/O
|
|
net (fo=3, routed) 0.415 13.799 u_cpu/mem_stage/data_data_ok
|
|
SLICE_X43Y30 r u_cpu/mem_stage/flush_inst_req_buffer[1]_i_15/I0
|
|
SLICE_X43Y30 LUT3 (Prop_lut3_I0_O) 0.124 13.923 r u_cpu/mem_stage/flush_inst_req_buffer[1]_i_15/O
|
|
net (fo=2, routed) 0.833 14.756 u_cpu/mem_stage/es_to_ms_bus_r_reg[70]_1
|
|
SLICE_X48Y30 r u_cpu/mem_stage/flush_inst_req_buffer[1]_i_14/I0
|
|
SLICE_X48Y30 LUT6 (Prop_lut6_I0_O) 0.124 14.880 r u_cpu/mem_stage/flush_inst_req_buffer[1]_i_14/O
|
|
net (fo=1, routed) 0.651 15.532 u_cpu/mem_stage/ms_ready_go
|
|
SLICE_X48Y25 r u_cpu/mem_stage/flush_inst_req_buffer[1]_i_13/I4
|
|
SLICE_X48Y25 LUT6 (Prop_lut6_I4_O) 0.124 15.656 r u_cpu/mem_stage/flush_inst_req_buffer[1]_i_13/O
|
|
net (fo=3, routed) 0.483 16.139 u_cpu/id_stage/flush_inst_req_buffer[31]_i_6
|
|
SLICE_X50Y25 r u_cpu/id_stage/flush_inst_req_buffer[1]_i_9/I1
|
|
SLICE_X50Y25 LUT6 (Prop_lut6_I1_O) 0.124 16.263 r u_cpu/id_stage/flush_inst_req_buffer[1]_i_9/O
|
|
net (fo=32, routed) 0.531 16.794 u_cpu/if_stage/nextpc5
|
|
SLICE_X51Y27 r u_cpu/if_stage/fetch_pc_r[6]_i_4/I2
|
|
SLICE_X51Y27 LUT6 (Prop_lut6_I2_O) 0.124 16.918 r u_cpu/if_stage/fetch_pc_r[6]_i_4/O
|
|
net (fo=1, routed) 3.059 19.977 u_cpu/if_stage/fetch_pc_r[6]_i_4_n_0
|
|
SLICE_X114Y28 r u_cpu/if_stage/fetch_pc_r[6]_i_2/I2
|
|
SLICE_X114Y28 LUT6 (Prop_lut6_I2_O) 0.124 20.101 r u_cpu/if_stage/fetch_pc_r[6]_i_2/O
|
|
net (fo=1, routed) 0.441 20.542 u_cpu/if_stage/fetch_pc_r[6]_i_2_n_0
|
|
SLICE_X114Y25 r u_cpu/if_stage/fetch_pc_r[6]_i_1/I2
|
|
SLICE_X114Y25 LUT6 (Prop_lut6_I2_O) 0.124 20.666 r u_cpu/if_stage/fetch_pc_r[6]_i_1/O
|
|
net (fo=6, routed) 3.249 23.915 u_cpu/icache/tagv_ram_way[1].u/mem_reg_reg_2[2]
|
|
SLICE_X49Y33 r u_cpu/icache/tagv_ram_way[1].u/mem_reg_reg_i_8/I4
|
|
SLICE_X49Y33 LUT5 (Prop_lut5_I4_O) 0.124 24.039 r u_cpu/icache/tagv_ram_way[1].u/mem_reg_reg_i_8/O
|
|
net (fo=16, routed) 1.922 25.962 u_cpu/icache/data_ram_way[0].data_ram_bank[1].u/ADDRBWRADDR[2]
|
|
RAMB18_X1Y3 RAMB18E1 r u_cpu/icache/data_ram_way[0].data_ram_bank[1].u/mem_reg_reg/ADDRBWRADDR[7]
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock cpu_clk rise edge) 30.323 30.323 r
|
|
clock source latency -5.674 24.648
|
|
propagated clock network latency
|
|
3.883 28.531
|
|
clock pessimism -0.418 28.113
|
|
clock uncertainty -0.074 28.039
|
|
RAMB18_X1Y3 RAMB18E1 (Setup_ramb18e1_CLKBWRCLK_ADDRBWRADDR[7])
|
|
-0.566 27.473 u_cpu/icache/data_ram_way[0].data_ram_bank[1].u/mem_reg_reg
|
|
-------------------------------------------------------------------
|
|
required time 27.473
|
|
arrival time -25.962
|
|
-------------------------------------------------------------------
|
|
slack 1.512
|
|
|
|
Slack (MET) : 1.512ns (required time - arrival time)
|
|
Source: u_cpu/addr_trans/data_vaddr_buffer_reg[14]/C
|
|
(rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns})
|
|
Destination: u_cpu/icache/data_ram_way[0].data_ram_bank[1].u/mem_reg_reg/ADDRBWRADDR[7]
|
|
(rising edge-triggered cell RAMB18E1 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns})
|
|
Path Group: cpu_clk
|
|
Path Type: Setup (Max at Slow Process Corner)
|
|
Requirement: 30.323ns (cpu_clk rise@30.323ns - cpu_clk rise@0.000ns)
|
|
Data Path Delay: 28.186ns (logic 5.333ns (18.920%) route 22.853ns (81.079%))
|
|
Logic Levels: 26 (CARRY4=4 LUT3=2 LUT4=1 LUT5=2 LUT6=15 MUXF7=1 MUXF8=1)
|
|
Clock Path Skew: 0.015ns (DCD - SCD + CPR)
|
|
Destination Clock Delay (DCD): -1.791ns = ( 28.531 - 30.323 )
|
|
Source Clock Delay (SCD): -2.225ns
|
|
Clock Pessimism Removal (CPR): -0.418ns
|
|
Clock Uncertainty: 0.074ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Discrete Jitter (DJ): 0.130ns
|
|
Phase Error (PE): 0.000ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock cpu_clk rise edge) 0.000 0.000 r
|
|
clock source latency -6.275 -6.275
|
|
propagated clock network latency
|
|
4.051 -2.225
|
|
SLICE_X35Y35 FDRE 0.000 -2.225 r u_cpu/addr_trans/data_vaddr_buffer_reg[14]/C
|
|
SLICE_X35Y35 FDRE (Prop_fdre_C_Q) 0.456 -1.769 r u_cpu/addr_trans/data_vaddr_buffer_reg[14]/Q
|
|
net (fo=33, routed) 1.442 -0.326 u_cpu/addr_trans/tlb_entry/data_vaddr_buffer[2]
|
|
SLICE_X42Y40 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_226/I5
|
|
SLICE_X42Y40 LUT6 (Prop_lut6_I5_O) 0.124 -0.202 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_226/O
|
|
net (fo=1, routed) 0.000 -0.202 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_226_n_0
|
|
SLICE_X42Y40 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_111/S[0]
|
|
SLICE_X42Y40 CARRY4 (Prop_carry4_S[0]_CO[3])
|
|
0.513 0.311 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_111/CO[3]
|
|
net (fo=1, routed) 0.000 0.311 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_111_n_0
|
|
SLICE_X42Y41 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_32/CI
|
|
SLICE_X42Y41 CARRY4 (Prop_carry4_CI_CO[2])
|
|
0.229 0.540 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_32/CO[2]
|
|
net (fo=1, routed) 1.009 1.549 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_32_n_1
|
|
SLICE_X40Y47 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_9/I1
|
|
SLICE_X40Y47 LUT6 (Prop_lut6_I1_O) 0.310 1.859 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_9/O
|
|
net (fo=2, routed) 0.635 2.494 u_cpu/addr_trans/tlb_entry/match1[28]
|
|
SLICE_X38Y47 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/I2
|
|
SLICE_X38Y47 LUT4 (Prop_lut4_I2_O) 0.124 2.618 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/O
|
|
net (fo=2, routed) 0.667 3.285 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2_n_0
|
|
SLICE_X39Y47 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/I0
|
|
SLICE_X39Y47 LUT5 (Prop_lut5_I0_O) 0.124 3.409 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/O
|
|
net (fo=2, routed) 1.103 4.512 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2_n_0
|
|
SLICE_X38Y50 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/I0
|
|
SLICE_X38Y50 LUT6 (Prop_lut6_I0_O) 0.124 4.636 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/O
|
|
net (fo=89, routed) 1.162 5.797 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus[8]
|
|
SLICE_X42Y51 r u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_38__0/S
|
|
SLICE_X42Y51 MUXF7 (Prop_muxf7_S_O) 0.292 6.089 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_38__0/O
|
|
net (fo=1, routed) 0.000 6.089 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_38__0_n_0
|
|
SLICE_X42Y51 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_16__0/I1
|
|
SLICE_X42Y51 MUXF8 (Prop_muxf8_I1_O) 0.088 6.177 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_16__0/O
|
|
net (fo=1, routed) 0.957 7.134 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_16__0_n_0
|
|
SLICE_X42Y50 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7/I0
|
|
SLICE_X42Y50 LUT6 (Prop_lut6_I0_O) 0.319 7.453 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7/O
|
|
net (fo=1, routed) 0.435 7.888 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7_n_0
|
|
SLICE_X44Y50 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0/I5
|
|
SLICE_X44Y50 LUT6 (Prop_lut6_I5_O) 0.124 8.012 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0/O
|
|
net (fo=10, routed) 0.740 8.753 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0_n_0
|
|
SLICE_X44Y50 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[5]_i_1__0/I3
|
|
SLICE_X44Y50 LUT6 (Prop_lut6_I3_O) 0.124 8.877 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[5]_i_1__0/O
|
|
net (fo=6, routed) 0.845 9.722 u_cpu/u_csr/ms_to_ws_bus[13]
|
|
SLICE_X50Y46 f u_cpu/u_csr/write_buffer_way[1]_i_18/I3
|
|
SLICE_X50Y46 LUT6 (Prop_lut6_I3_O) 0.124 9.846 r u_cpu/u_csr/write_buffer_way[1]_i_18/O
|
|
net (fo=1, routed) 0.000 9.846 u_cpu/u_csr/write_buffer_way[1]_i_18_n_0
|
|
SLICE_X50Y46 r u_cpu/u_csr/write_buffer_way_reg[1]_i_11/S[0]
|
|
SLICE_X50Y46 CARRY4 (Prop_carry4_S[0]_CO[3])
|
|
0.532 10.378 f u_cpu/u_csr/write_buffer_way_reg[1]_i_11/CO[3]
|
|
net (fo=1, routed) 0.000 10.378 u_cpu/u_csr/write_buffer_way_reg[1]_i_11_n_0
|
|
SLICE_X50Y47 f u_cpu/u_csr/write_buffer_way_reg[1]_i_9/CI
|
|
SLICE_X50Y47 CARRY4 (Prop_carry4_CI_CO[1])
|
|
0.157 10.535 f u_cpu/u_csr/write_buffer_way_reg[1]_i_9/CO[1]
|
|
net (fo=2, routed) 0.791 11.326 u_cpu/wb_stage/CO[0]
|
|
SLICE_X46Y39 f u_cpu/wb_stage/write_buffer_way[1]_i_5/I1
|
|
SLICE_X46Y39 LUT6 (Prop_lut6_I1_O) 0.329 11.655 r u_cpu/wb_stage/write_buffer_way[1]_i_5/O
|
|
net (fo=7, routed) 0.762 12.417 u_cpu/addr_trans/tlb_entry/sc_cancel_req
|
|
SLICE_X46Y35 r u_cpu/addr_trans/tlb_entry/main_state[0]_i_3/I1
|
|
SLICE_X46Y35 LUT3 (Prop_lut3_I1_O) 0.124 12.541 r u_cpu/addr_trans/tlb_entry/main_state[0]_i_3/O
|
|
net (fo=3, routed) 0.719 13.260 u_cpu/dcache/main_state_reg[0]_2
|
|
SLICE_X43Y31 r u_cpu/dcache/ds_to_es_bus_r[235]_i_10/I3
|
|
SLICE_X43Y31 LUT6 (Prop_lut6_I3_O) 0.124 13.384 r u_cpu/dcache/ds_to_es_bus_r[235]_i_10/O
|
|
net (fo=3, routed) 0.415 13.799 u_cpu/mem_stage/data_data_ok
|
|
SLICE_X43Y30 r u_cpu/mem_stage/flush_inst_req_buffer[1]_i_15/I0
|
|
SLICE_X43Y30 LUT3 (Prop_lut3_I0_O) 0.124 13.923 r u_cpu/mem_stage/flush_inst_req_buffer[1]_i_15/O
|
|
net (fo=2, routed) 0.833 14.756 u_cpu/mem_stage/es_to_ms_bus_r_reg[70]_1
|
|
SLICE_X48Y30 r u_cpu/mem_stage/flush_inst_req_buffer[1]_i_14/I0
|
|
SLICE_X48Y30 LUT6 (Prop_lut6_I0_O) 0.124 14.880 r u_cpu/mem_stage/flush_inst_req_buffer[1]_i_14/O
|
|
net (fo=1, routed) 0.651 15.532 u_cpu/mem_stage/ms_ready_go
|
|
SLICE_X48Y25 r u_cpu/mem_stage/flush_inst_req_buffer[1]_i_13/I4
|
|
SLICE_X48Y25 LUT6 (Prop_lut6_I4_O) 0.124 15.656 r u_cpu/mem_stage/flush_inst_req_buffer[1]_i_13/O
|
|
net (fo=3, routed) 0.483 16.139 u_cpu/id_stage/flush_inst_req_buffer[31]_i_6
|
|
SLICE_X50Y25 r u_cpu/id_stage/flush_inst_req_buffer[1]_i_9/I1
|
|
SLICE_X50Y25 LUT6 (Prop_lut6_I1_O) 0.124 16.263 r u_cpu/id_stage/flush_inst_req_buffer[1]_i_9/O
|
|
net (fo=32, routed) 0.531 16.794 u_cpu/if_stage/nextpc5
|
|
SLICE_X51Y27 r u_cpu/if_stage/fetch_pc_r[6]_i_4/I2
|
|
SLICE_X51Y27 LUT6 (Prop_lut6_I2_O) 0.124 16.918 r u_cpu/if_stage/fetch_pc_r[6]_i_4/O
|
|
net (fo=1, routed) 3.059 19.977 u_cpu/if_stage/fetch_pc_r[6]_i_4_n_0
|
|
SLICE_X114Y28 r u_cpu/if_stage/fetch_pc_r[6]_i_2/I2
|
|
SLICE_X114Y28 LUT6 (Prop_lut6_I2_O) 0.124 20.101 r u_cpu/if_stage/fetch_pc_r[6]_i_2/O
|
|
net (fo=1, routed) 0.441 20.542 u_cpu/if_stage/fetch_pc_r[6]_i_2_n_0
|
|
SLICE_X114Y25 r u_cpu/if_stage/fetch_pc_r[6]_i_1/I2
|
|
SLICE_X114Y25 LUT6 (Prop_lut6_I2_O) 0.124 20.666 r u_cpu/if_stage/fetch_pc_r[6]_i_1/O
|
|
net (fo=6, routed) 3.249 23.915 u_cpu/icache/tagv_ram_way[1].u/mem_reg_reg_2[2]
|
|
SLICE_X49Y33 r u_cpu/icache/tagv_ram_way[1].u/mem_reg_reg_i_8/I4
|
|
SLICE_X49Y33 LUT5 (Prop_lut5_I4_O) 0.124 24.039 r u_cpu/icache/tagv_ram_way[1].u/mem_reg_reg_i_8/O
|
|
net (fo=16, routed) 1.922 25.962 u_cpu/icache/data_ram_way[0].data_ram_bank[1].u/ADDRBWRADDR[2]
|
|
RAMB18_X1Y3 RAMB18E1 r u_cpu/icache/data_ram_way[0].data_ram_bank[1].u/mem_reg_reg/ADDRBWRADDR[7]
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock cpu_clk rise edge) 30.323 30.323 r
|
|
clock source latency -5.674 24.648
|
|
propagated clock network latency
|
|
3.883 28.531
|
|
clock pessimism -0.418 28.113
|
|
clock uncertainty -0.074 28.039
|
|
RAMB18_X1Y3 RAMB18E1 (Setup_ramb18e1_CLKBWRCLK_ADDRBWRADDR[7])
|
|
-0.566 27.473 u_cpu/icache/data_ram_way[0].data_ram_bank[1].u/mem_reg_reg
|
|
-------------------------------------------------------------------
|
|
required time 27.473
|
|
arrival time -25.962
|
|
-------------------------------------------------------------------
|
|
slack 1.512
|
|
|
|
Slack (MET) : 1.512ns (required time - arrival time)
|
|
Source: u_cpu/addr_trans/data_vaddr_buffer_reg[14]/C
|
|
(rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns})
|
|
Destination: u_cpu/icache/data_ram_way[0].data_ram_bank[1].u/mem_reg_reg/ADDRBWRADDR[7]
|
|
(rising edge-triggered cell RAMB18E1 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns})
|
|
Path Group: cpu_clk
|
|
Path Type: Setup (Max at Slow Process Corner)
|
|
Requirement: 30.323ns (cpu_clk rise@30.323ns - cpu_clk rise@0.000ns)
|
|
Data Path Delay: 28.186ns (logic 5.333ns (18.920%) route 22.853ns (81.079%))
|
|
Logic Levels: 26 (CARRY4=4 LUT3=2 LUT4=1 LUT5=2 LUT6=15 MUXF7=1 MUXF8=1)
|
|
Clock Path Skew: 0.015ns (DCD - SCD + CPR)
|
|
Destination Clock Delay (DCD): -1.791ns = ( 28.531 - 30.323 )
|
|
Source Clock Delay (SCD): -2.225ns
|
|
Clock Pessimism Removal (CPR): -0.418ns
|
|
Clock Uncertainty: 0.074ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Discrete Jitter (DJ): 0.130ns
|
|
Phase Error (PE): 0.000ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock cpu_clk rise edge) 0.000 0.000 r
|
|
clock source latency -6.275 -6.275
|
|
propagated clock network latency
|
|
4.051 -2.225
|
|
SLICE_X35Y35 FDRE 0.000 -2.225 r u_cpu/addr_trans/data_vaddr_buffer_reg[14]/C
|
|
SLICE_X35Y35 FDRE (Prop_fdre_C_Q) 0.456 -1.769 r u_cpu/addr_trans/data_vaddr_buffer_reg[14]/Q
|
|
net (fo=33, routed) 1.442 -0.326 u_cpu/addr_trans/tlb_entry/data_vaddr_buffer[2]
|
|
SLICE_X42Y40 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_226/I5
|
|
SLICE_X42Y40 LUT6 (Prop_lut6_I5_O) 0.124 -0.202 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_226/O
|
|
net (fo=1, routed) 0.000 -0.202 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_226_n_0
|
|
SLICE_X42Y40 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_111/S[0]
|
|
SLICE_X42Y40 CARRY4 (Prop_carry4_S[0]_CO[3])
|
|
0.513 0.311 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_111/CO[3]
|
|
net (fo=1, routed) 0.000 0.311 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_111_n_0
|
|
SLICE_X42Y41 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_32/CI
|
|
SLICE_X42Y41 CARRY4 (Prop_carry4_CI_CO[2])
|
|
0.229 0.540 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_32/CO[2]
|
|
net (fo=1, routed) 1.009 1.549 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_32_n_1
|
|
SLICE_X40Y47 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_9/I1
|
|
SLICE_X40Y47 LUT6 (Prop_lut6_I1_O) 0.310 1.859 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_9/O
|
|
net (fo=2, routed) 0.635 2.494 u_cpu/addr_trans/tlb_entry/match1[28]
|
|
SLICE_X38Y47 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/I2
|
|
SLICE_X38Y47 LUT4 (Prop_lut4_I2_O) 0.124 2.618 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/O
|
|
net (fo=2, routed) 0.667 3.285 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2_n_0
|
|
SLICE_X39Y47 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/I0
|
|
SLICE_X39Y47 LUT5 (Prop_lut5_I0_O) 0.124 3.409 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/O
|
|
net (fo=2, routed) 1.103 4.512 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2_n_0
|
|
SLICE_X38Y50 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/I0
|
|
SLICE_X38Y50 LUT6 (Prop_lut6_I0_O) 0.124 4.636 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/O
|
|
net (fo=89, routed) 1.162 5.797 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus[8]
|
|
SLICE_X42Y51 r u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_38__0/S
|
|
SLICE_X42Y51 MUXF7 (Prop_muxf7_S_O) 0.292 6.089 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_38__0/O
|
|
net (fo=1, routed) 0.000 6.089 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_38__0_n_0
|
|
SLICE_X42Y51 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_16__0/I1
|
|
SLICE_X42Y51 MUXF8 (Prop_muxf8_I1_O) 0.088 6.177 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_16__0/O
|
|
net (fo=1, routed) 0.957 7.134 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_16__0_n_0
|
|
SLICE_X42Y50 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7/I0
|
|
SLICE_X42Y50 LUT6 (Prop_lut6_I0_O) 0.319 7.453 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7/O
|
|
net (fo=1, routed) 0.435 7.888 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7_n_0
|
|
SLICE_X44Y50 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0/I5
|
|
SLICE_X44Y50 LUT6 (Prop_lut6_I5_O) 0.124 8.012 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0/O
|
|
net (fo=10, routed) 0.740 8.753 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0_n_0
|
|
SLICE_X44Y50 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[5]_i_1__0/I3
|
|
SLICE_X44Y50 LUT6 (Prop_lut6_I3_O) 0.124 8.877 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[5]_i_1__0/O
|
|
net (fo=6, routed) 0.845 9.722 u_cpu/u_csr/ms_to_ws_bus[13]
|
|
SLICE_X50Y46 r u_cpu/u_csr/write_buffer_way[1]_i_18/I3
|
|
SLICE_X50Y46 LUT6 (Prop_lut6_I3_O) 0.124 9.846 r u_cpu/u_csr/write_buffer_way[1]_i_18/O
|
|
net (fo=1, routed) 0.000 9.846 u_cpu/u_csr/write_buffer_way[1]_i_18_n_0
|
|
SLICE_X50Y46 r u_cpu/u_csr/write_buffer_way_reg[1]_i_11/S[0]
|
|
SLICE_X50Y46 CARRY4 (Prop_carry4_S[0]_CO[3])
|
|
0.532 10.378 r u_cpu/u_csr/write_buffer_way_reg[1]_i_11/CO[3]
|
|
net (fo=1, routed) 0.000 10.378 u_cpu/u_csr/write_buffer_way_reg[1]_i_11_n_0
|
|
SLICE_X50Y47 r u_cpu/u_csr/write_buffer_way_reg[1]_i_9/CI
|
|
SLICE_X50Y47 CARRY4 (Prop_carry4_CI_CO[1])
|
|
0.157 10.535 r u_cpu/u_csr/write_buffer_way_reg[1]_i_9/CO[1]
|
|
net (fo=2, routed) 0.791 11.326 u_cpu/wb_stage/CO[0]
|
|
SLICE_X46Y39 r u_cpu/wb_stage/write_buffer_way[1]_i_5/I1
|
|
SLICE_X46Y39 LUT6 (Prop_lut6_I1_O) 0.329 11.655 f u_cpu/wb_stage/write_buffer_way[1]_i_5/O
|
|
net (fo=7, routed) 0.762 12.417 u_cpu/addr_trans/tlb_entry/sc_cancel_req
|
|
SLICE_X46Y35 f u_cpu/addr_trans/tlb_entry/main_state[0]_i_3/I1
|
|
SLICE_X46Y35 LUT3 (Prop_lut3_I1_O) 0.124 12.541 f u_cpu/addr_trans/tlb_entry/main_state[0]_i_3/O
|
|
net (fo=3, routed) 0.719 13.260 u_cpu/dcache/main_state_reg[0]_2
|
|
SLICE_X43Y31 f u_cpu/dcache/ds_to_es_bus_r[235]_i_10/I3
|
|
SLICE_X43Y31 LUT6 (Prop_lut6_I3_O) 0.124 13.384 f u_cpu/dcache/ds_to_es_bus_r[235]_i_10/O
|
|
net (fo=3, routed) 0.415 13.799 u_cpu/mem_stage/data_data_ok
|
|
SLICE_X43Y30 f u_cpu/mem_stage/flush_inst_req_buffer[1]_i_15/I0
|
|
SLICE_X43Y30 LUT3 (Prop_lut3_I0_O) 0.124 13.923 f u_cpu/mem_stage/flush_inst_req_buffer[1]_i_15/O
|
|
net (fo=2, routed) 0.833 14.756 u_cpu/mem_stage/es_to_ms_bus_r_reg[70]_1
|
|
SLICE_X48Y30 f u_cpu/mem_stage/flush_inst_req_buffer[1]_i_14/I0
|
|
SLICE_X48Y30 LUT6 (Prop_lut6_I0_O) 0.124 14.880 f u_cpu/mem_stage/flush_inst_req_buffer[1]_i_14/O
|
|
net (fo=1, routed) 0.651 15.532 u_cpu/mem_stage/ms_ready_go
|
|
SLICE_X48Y25 f u_cpu/mem_stage/flush_inst_req_buffer[1]_i_13/I4
|
|
SLICE_X48Y25 LUT6 (Prop_lut6_I4_O) 0.124 15.656 f u_cpu/mem_stage/flush_inst_req_buffer[1]_i_13/O
|
|
net (fo=3, routed) 0.483 16.139 u_cpu/id_stage/flush_inst_req_buffer[31]_i_6
|
|
SLICE_X50Y25 f u_cpu/id_stage/flush_inst_req_buffer[1]_i_9/I1
|
|
SLICE_X50Y25 LUT6 (Prop_lut6_I1_O) 0.124 16.263 f u_cpu/id_stage/flush_inst_req_buffer[1]_i_9/O
|
|
net (fo=32, routed) 0.531 16.794 u_cpu/if_stage/nextpc5
|
|
SLICE_X51Y27 f u_cpu/if_stage/fetch_pc_r[6]_i_4/I2
|
|
SLICE_X51Y27 LUT6 (Prop_lut6_I2_O) 0.124 16.918 r u_cpu/if_stage/fetch_pc_r[6]_i_4/O
|
|
net (fo=1, routed) 3.059 19.977 u_cpu/if_stage/fetch_pc_r[6]_i_4_n_0
|
|
SLICE_X114Y28 r u_cpu/if_stage/fetch_pc_r[6]_i_2/I2
|
|
SLICE_X114Y28 LUT6 (Prop_lut6_I2_O) 0.124 20.101 r u_cpu/if_stage/fetch_pc_r[6]_i_2/O
|
|
net (fo=1, routed) 0.441 20.542 u_cpu/if_stage/fetch_pc_r[6]_i_2_n_0
|
|
SLICE_X114Y25 r u_cpu/if_stage/fetch_pc_r[6]_i_1/I2
|
|
SLICE_X114Y25 LUT6 (Prop_lut6_I2_O) 0.124 20.666 r u_cpu/if_stage/fetch_pc_r[6]_i_1/O
|
|
net (fo=6, routed) 3.249 23.915 u_cpu/icache/tagv_ram_way[1].u/mem_reg_reg_2[2]
|
|
SLICE_X49Y33 r u_cpu/icache/tagv_ram_way[1].u/mem_reg_reg_i_8/I4
|
|
SLICE_X49Y33 LUT5 (Prop_lut5_I4_O) 0.124 24.039 r u_cpu/icache/tagv_ram_way[1].u/mem_reg_reg_i_8/O
|
|
net (fo=16, routed) 1.922 25.962 u_cpu/icache/data_ram_way[0].data_ram_bank[1].u/ADDRBWRADDR[2]
|
|
RAMB18_X1Y3 RAMB18E1 r u_cpu/icache/data_ram_way[0].data_ram_bank[1].u/mem_reg_reg/ADDRBWRADDR[7]
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock cpu_clk rise edge) 30.323 30.323 r
|
|
clock source latency -5.674 24.648
|
|
propagated clock network latency
|
|
3.883 28.531
|
|
clock pessimism -0.418 28.113
|
|
clock uncertainty -0.074 28.039
|
|
RAMB18_X1Y3 RAMB18E1 (Setup_ramb18e1_CLKBWRCLK_ADDRBWRADDR[7])
|
|
-0.566 27.473 u_cpu/icache/data_ram_way[0].data_ram_bank[1].u/mem_reg_reg
|
|
-------------------------------------------------------------------
|
|
required time 27.473
|
|
arrival time -25.962
|
|
-------------------------------------------------------------------
|
|
slack 1.512
|
|
|
|
Slack (MET) : 1.512ns (required time - arrival time)
|
|
Source: u_cpu/addr_trans/data_vaddr_buffer_reg[14]/C
|
|
(rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns})
|
|
Destination: u_cpu/icache/data_ram_way[0].data_ram_bank[1].u/mem_reg_reg/ADDRBWRADDR[7]
|
|
(rising edge-triggered cell RAMB18E1 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns})
|
|
Path Group: cpu_clk
|
|
Path Type: Setup (Max at Slow Process Corner)
|
|
Requirement: 30.323ns (cpu_clk rise@30.323ns - cpu_clk rise@0.000ns)
|
|
Data Path Delay: 28.186ns (logic 5.333ns (18.920%) route 22.853ns (81.079%))
|
|
Logic Levels: 26 (CARRY4=4 LUT3=2 LUT4=1 LUT5=2 LUT6=15 MUXF7=1 MUXF8=1)
|
|
Clock Path Skew: 0.015ns (DCD - SCD + CPR)
|
|
Destination Clock Delay (DCD): -1.791ns = ( 28.531 - 30.323 )
|
|
Source Clock Delay (SCD): -2.225ns
|
|
Clock Pessimism Removal (CPR): -0.418ns
|
|
Clock Uncertainty: 0.074ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Discrete Jitter (DJ): 0.130ns
|
|
Phase Error (PE): 0.000ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock cpu_clk rise edge) 0.000 0.000 r
|
|
clock source latency -6.275 -6.275
|
|
propagated clock network latency
|
|
4.051 -2.225
|
|
SLICE_X35Y35 FDRE 0.000 -2.225 r u_cpu/addr_trans/data_vaddr_buffer_reg[14]/C
|
|
SLICE_X35Y35 FDRE (Prop_fdre_C_Q) 0.456 -1.769 r u_cpu/addr_trans/data_vaddr_buffer_reg[14]/Q
|
|
net (fo=33, routed) 1.442 -0.326 u_cpu/addr_trans/tlb_entry/data_vaddr_buffer[2]
|
|
SLICE_X42Y40 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_226/I5
|
|
SLICE_X42Y40 LUT6 (Prop_lut6_I5_O) 0.124 -0.202 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_226/O
|
|
net (fo=1, routed) 0.000 -0.202 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_226_n_0
|
|
SLICE_X42Y40 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_111/S[0]
|
|
SLICE_X42Y40 CARRY4 (Prop_carry4_S[0]_CO[3])
|
|
0.513 0.311 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_111/CO[3]
|
|
net (fo=1, routed) 0.000 0.311 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_111_n_0
|
|
SLICE_X42Y41 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_32/CI
|
|
SLICE_X42Y41 CARRY4 (Prop_carry4_CI_CO[2])
|
|
0.229 0.540 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_32/CO[2]
|
|
net (fo=1, routed) 1.009 1.549 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_32_n_1
|
|
SLICE_X40Y47 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_9/I1
|
|
SLICE_X40Y47 LUT6 (Prop_lut6_I1_O) 0.310 1.859 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_9/O
|
|
net (fo=2, routed) 0.635 2.494 u_cpu/addr_trans/tlb_entry/match1[28]
|
|
SLICE_X38Y47 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/I2
|
|
SLICE_X38Y47 LUT4 (Prop_lut4_I2_O) 0.124 2.618 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/O
|
|
net (fo=2, routed) 0.667 3.285 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2_n_0
|
|
SLICE_X39Y47 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/I0
|
|
SLICE_X39Y47 LUT5 (Prop_lut5_I0_O) 0.124 3.409 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/O
|
|
net (fo=2, routed) 1.103 4.512 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2_n_0
|
|
SLICE_X38Y50 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/I0
|
|
SLICE_X38Y50 LUT6 (Prop_lut6_I0_O) 0.124 4.636 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/O
|
|
net (fo=89, routed) 1.162 5.797 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus[8]
|
|
SLICE_X42Y51 r u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_38__0/S
|
|
SLICE_X42Y51 MUXF7 (Prop_muxf7_S_O) 0.292 6.089 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_38__0/O
|
|
net (fo=1, routed) 0.000 6.089 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_38__0_n_0
|
|
SLICE_X42Y51 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_16__0/I1
|
|
SLICE_X42Y51 MUXF8 (Prop_muxf8_I1_O) 0.088 6.177 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_16__0/O
|
|
net (fo=1, routed) 0.957 7.134 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_16__0_n_0
|
|
SLICE_X42Y50 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7/I0
|
|
SLICE_X42Y50 LUT6 (Prop_lut6_I0_O) 0.319 7.453 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7/O
|
|
net (fo=1, routed) 0.435 7.888 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7_n_0
|
|
SLICE_X44Y50 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0/I5
|
|
SLICE_X44Y50 LUT6 (Prop_lut6_I5_O) 0.124 8.012 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0/O
|
|
net (fo=10, routed) 0.740 8.753 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0_n_0
|
|
SLICE_X44Y50 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[5]_i_1__0/I3
|
|
SLICE_X44Y50 LUT6 (Prop_lut6_I3_O) 0.124 8.877 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[5]_i_1__0/O
|
|
net (fo=6, routed) 0.845 9.722 u_cpu/u_csr/ms_to_ws_bus[13]
|
|
SLICE_X50Y46 f u_cpu/u_csr/write_buffer_way[1]_i_18/I3
|
|
SLICE_X50Y46 LUT6 (Prop_lut6_I3_O) 0.124 9.846 r u_cpu/u_csr/write_buffer_way[1]_i_18/O
|
|
net (fo=1, routed) 0.000 9.846 u_cpu/u_csr/write_buffer_way[1]_i_18_n_0
|
|
SLICE_X50Y46 r u_cpu/u_csr/write_buffer_way_reg[1]_i_11/S[0]
|
|
SLICE_X50Y46 CARRY4 (Prop_carry4_S[0]_CO[3])
|
|
0.532 10.378 r u_cpu/u_csr/write_buffer_way_reg[1]_i_11/CO[3]
|
|
net (fo=1, routed) 0.000 10.378 u_cpu/u_csr/write_buffer_way_reg[1]_i_11_n_0
|
|
SLICE_X50Y47 r u_cpu/u_csr/write_buffer_way_reg[1]_i_9/CI
|
|
SLICE_X50Y47 CARRY4 (Prop_carry4_CI_CO[1])
|
|
0.157 10.535 r u_cpu/u_csr/write_buffer_way_reg[1]_i_9/CO[1]
|
|
net (fo=2, routed) 0.791 11.326 u_cpu/wb_stage/CO[0]
|
|
SLICE_X46Y39 r u_cpu/wb_stage/write_buffer_way[1]_i_5/I1
|
|
SLICE_X46Y39 LUT6 (Prop_lut6_I1_O) 0.329 11.655 f u_cpu/wb_stage/write_buffer_way[1]_i_5/O
|
|
net (fo=7, routed) 0.762 12.417 u_cpu/addr_trans/tlb_entry/sc_cancel_req
|
|
SLICE_X46Y35 f u_cpu/addr_trans/tlb_entry/main_state[0]_i_3/I1
|
|
SLICE_X46Y35 LUT3 (Prop_lut3_I1_O) 0.124 12.541 f u_cpu/addr_trans/tlb_entry/main_state[0]_i_3/O
|
|
net (fo=3, routed) 0.719 13.260 u_cpu/dcache/main_state_reg[0]_2
|
|
SLICE_X43Y31 f u_cpu/dcache/ds_to_es_bus_r[235]_i_10/I3
|
|
SLICE_X43Y31 LUT6 (Prop_lut6_I3_O) 0.124 13.384 f u_cpu/dcache/ds_to_es_bus_r[235]_i_10/O
|
|
net (fo=3, routed) 0.415 13.799 u_cpu/mem_stage/data_data_ok
|
|
SLICE_X43Y30 f u_cpu/mem_stage/flush_inst_req_buffer[1]_i_15/I0
|
|
SLICE_X43Y30 LUT3 (Prop_lut3_I0_O) 0.124 13.923 f u_cpu/mem_stage/flush_inst_req_buffer[1]_i_15/O
|
|
net (fo=2, routed) 0.833 14.756 u_cpu/mem_stage/es_to_ms_bus_r_reg[70]_1
|
|
SLICE_X48Y30 f u_cpu/mem_stage/flush_inst_req_buffer[1]_i_14/I0
|
|
SLICE_X48Y30 LUT6 (Prop_lut6_I0_O) 0.124 14.880 f u_cpu/mem_stage/flush_inst_req_buffer[1]_i_14/O
|
|
net (fo=1, routed) 0.651 15.532 u_cpu/mem_stage/ms_ready_go
|
|
SLICE_X48Y25 f u_cpu/mem_stage/flush_inst_req_buffer[1]_i_13/I4
|
|
SLICE_X48Y25 LUT6 (Prop_lut6_I4_O) 0.124 15.656 f u_cpu/mem_stage/flush_inst_req_buffer[1]_i_13/O
|
|
net (fo=3, routed) 0.483 16.139 u_cpu/id_stage/flush_inst_req_buffer[31]_i_6
|
|
SLICE_X50Y25 f u_cpu/id_stage/flush_inst_req_buffer[1]_i_9/I1
|
|
SLICE_X50Y25 LUT6 (Prop_lut6_I1_O) 0.124 16.263 f u_cpu/id_stage/flush_inst_req_buffer[1]_i_9/O
|
|
net (fo=32, routed) 0.531 16.794 u_cpu/if_stage/nextpc5
|
|
SLICE_X51Y27 f u_cpu/if_stage/fetch_pc_r[6]_i_4/I2
|
|
SLICE_X51Y27 LUT6 (Prop_lut6_I2_O) 0.124 16.918 r u_cpu/if_stage/fetch_pc_r[6]_i_4/O
|
|
net (fo=1, routed) 3.059 19.977 u_cpu/if_stage/fetch_pc_r[6]_i_4_n_0
|
|
SLICE_X114Y28 r u_cpu/if_stage/fetch_pc_r[6]_i_2/I2
|
|
SLICE_X114Y28 LUT6 (Prop_lut6_I2_O) 0.124 20.101 r u_cpu/if_stage/fetch_pc_r[6]_i_2/O
|
|
net (fo=1, routed) 0.441 20.542 u_cpu/if_stage/fetch_pc_r[6]_i_2_n_0
|
|
SLICE_X114Y25 r u_cpu/if_stage/fetch_pc_r[6]_i_1/I2
|
|
SLICE_X114Y25 LUT6 (Prop_lut6_I2_O) 0.124 20.666 r u_cpu/if_stage/fetch_pc_r[6]_i_1/O
|
|
net (fo=6, routed) 3.249 23.915 u_cpu/icache/tagv_ram_way[1].u/mem_reg_reg_2[2]
|
|
SLICE_X49Y33 r u_cpu/icache/tagv_ram_way[1].u/mem_reg_reg_i_8/I4
|
|
SLICE_X49Y33 LUT5 (Prop_lut5_I4_O) 0.124 24.039 r u_cpu/icache/tagv_ram_way[1].u/mem_reg_reg_i_8/O
|
|
net (fo=16, routed) 1.922 25.962 u_cpu/icache/data_ram_way[0].data_ram_bank[1].u/ADDRBWRADDR[2]
|
|
RAMB18_X1Y3 RAMB18E1 r u_cpu/icache/data_ram_way[0].data_ram_bank[1].u/mem_reg_reg/ADDRBWRADDR[7]
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock cpu_clk rise edge) 30.323 30.323 r
|
|
clock source latency -5.674 24.648
|
|
propagated clock network latency
|
|
3.883 28.531
|
|
clock pessimism -0.418 28.113
|
|
clock uncertainty -0.074 28.039
|
|
RAMB18_X1Y3 RAMB18E1 (Setup_ramb18e1_CLKBWRCLK_ADDRBWRADDR[7])
|
|
-0.566 27.473 u_cpu/icache/data_ram_way[0].data_ram_bank[1].u/mem_reg_reg
|
|
-------------------------------------------------------------------
|
|
required time 27.473
|
|
arrival time -25.962
|
|
-------------------------------------------------------------------
|
|
slack 1.512
|
|
|
|
Slack (MET) : 1.512ns (required time - arrival time)
|
|
Source: u_cpu/addr_trans/data_vaddr_buffer_reg[14]/C
|
|
(rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns})
|
|
Destination: u_cpu/icache/data_ram_way[0].data_ram_bank[1].u/mem_reg_reg/ADDRBWRADDR[7]
|
|
(rising edge-triggered cell RAMB18E1 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns})
|
|
Path Group: cpu_clk
|
|
Path Type: Setup (Max at Slow Process Corner)
|
|
Requirement: 30.323ns (cpu_clk rise@30.323ns - cpu_clk rise@0.000ns)
|
|
Data Path Delay: 28.186ns (logic 5.333ns (18.920%) route 22.853ns (81.079%))
|
|
Logic Levels: 26 (CARRY4=4 LUT3=2 LUT4=1 LUT5=2 LUT6=15 MUXF7=1 MUXF8=1)
|
|
Clock Path Skew: 0.015ns (DCD - SCD + CPR)
|
|
Destination Clock Delay (DCD): -1.791ns = ( 28.531 - 30.323 )
|
|
Source Clock Delay (SCD): -2.225ns
|
|
Clock Pessimism Removal (CPR): -0.418ns
|
|
Clock Uncertainty: 0.074ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Discrete Jitter (DJ): 0.130ns
|
|
Phase Error (PE): 0.000ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock cpu_clk rise edge) 0.000 0.000 r
|
|
clock source latency -6.275 -6.275
|
|
propagated clock network latency
|
|
4.051 -2.225
|
|
SLICE_X35Y35 FDRE 0.000 -2.225 r u_cpu/addr_trans/data_vaddr_buffer_reg[14]/C
|
|
SLICE_X35Y35 FDRE (Prop_fdre_C_Q) 0.456 -1.769 r u_cpu/addr_trans/data_vaddr_buffer_reg[14]/Q
|
|
net (fo=33, routed) 1.442 -0.326 u_cpu/addr_trans/tlb_entry/data_vaddr_buffer[2]
|
|
SLICE_X42Y40 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_226/I5
|
|
SLICE_X42Y40 LUT6 (Prop_lut6_I5_O) 0.124 -0.202 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_226/O
|
|
net (fo=1, routed) 0.000 -0.202 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_226_n_0
|
|
SLICE_X42Y40 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_111/S[0]
|
|
SLICE_X42Y40 CARRY4 (Prop_carry4_S[0]_CO[3])
|
|
0.513 0.311 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_111/CO[3]
|
|
net (fo=1, routed) 0.000 0.311 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_111_n_0
|
|
SLICE_X42Y41 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_32/CI
|
|
SLICE_X42Y41 CARRY4 (Prop_carry4_CI_CO[2])
|
|
0.229 0.540 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_32/CO[2]
|
|
net (fo=1, routed) 1.009 1.549 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_32_n_1
|
|
SLICE_X40Y47 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_9/I1
|
|
SLICE_X40Y47 LUT6 (Prop_lut6_I1_O) 0.310 1.859 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_9/O
|
|
net (fo=2, routed) 0.635 2.494 u_cpu/addr_trans/tlb_entry/match1[28]
|
|
SLICE_X38Y47 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/I2
|
|
SLICE_X38Y47 LUT4 (Prop_lut4_I2_O) 0.124 2.618 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/O
|
|
net (fo=2, routed) 0.667 3.285 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2_n_0
|
|
SLICE_X39Y47 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/I0
|
|
SLICE_X39Y47 LUT5 (Prop_lut5_I0_O) 0.124 3.409 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/O
|
|
net (fo=2, routed) 1.103 4.512 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2_n_0
|
|
SLICE_X38Y50 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/I0
|
|
SLICE_X38Y50 LUT6 (Prop_lut6_I0_O) 0.124 4.636 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/O
|
|
net (fo=89, routed) 1.162 5.797 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus[8]
|
|
SLICE_X42Y51 r u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_38__0/S
|
|
SLICE_X42Y51 MUXF7 (Prop_muxf7_S_O) 0.292 6.089 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_38__0/O
|
|
net (fo=1, routed) 0.000 6.089 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_38__0_n_0
|
|
SLICE_X42Y51 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_16__0/I1
|
|
SLICE_X42Y51 MUXF8 (Prop_muxf8_I1_O) 0.088 6.177 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_16__0/O
|
|
net (fo=1, routed) 0.957 7.134 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_16__0_n_0
|
|
SLICE_X42Y50 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7/I0
|
|
SLICE_X42Y50 LUT6 (Prop_lut6_I0_O) 0.319 7.453 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7/O
|
|
net (fo=1, routed) 0.435 7.888 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7_n_0
|
|
SLICE_X44Y50 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0/I5
|
|
SLICE_X44Y50 LUT6 (Prop_lut6_I5_O) 0.124 8.012 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0/O
|
|
net (fo=10, routed) 0.740 8.753 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0_n_0
|
|
SLICE_X44Y50 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[5]_i_1__0/I3
|
|
SLICE_X44Y50 LUT6 (Prop_lut6_I3_O) 0.124 8.877 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[5]_i_1__0/O
|
|
net (fo=6, routed) 0.845 9.722 u_cpu/u_csr/ms_to_ws_bus[13]
|
|
SLICE_X50Y46 r u_cpu/u_csr/write_buffer_way[1]_i_18/I3
|
|
SLICE_X50Y46 LUT6 (Prop_lut6_I3_O) 0.124 9.846 f u_cpu/u_csr/write_buffer_way[1]_i_18/O
|
|
net (fo=1, routed) 0.000 9.846 u_cpu/u_csr/write_buffer_way[1]_i_18_n_0
|
|
SLICE_X50Y46 f u_cpu/u_csr/write_buffer_way_reg[1]_i_11/S[0]
|
|
SLICE_X50Y46 CARRY4 (Prop_carry4_S[0]_CO[3])
|
|
0.532 10.378 r u_cpu/u_csr/write_buffer_way_reg[1]_i_11/CO[3]
|
|
net (fo=1, routed) 0.000 10.378 u_cpu/u_csr/write_buffer_way_reg[1]_i_11_n_0
|
|
SLICE_X50Y47 r u_cpu/u_csr/write_buffer_way_reg[1]_i_9/CI
|
|
SLICE_X50Y47 CARRY4 (Prop_carry4_CI_CO[1])
|
|
0.157 10.535 r u_cpu/u_csr/write_buffer_way_reg[1]_i_9/CO[1]
|
|
net (fo=2, routed) 0.791 11.326 u_cpu/wb_stage/CO[0]
|
|
SLICE_X46Y39 r u_cpu/wb_stage/write_buffer_way[1]_i_5/I1
|
|
SLICE_X46Y39 LUT6 (Prop_lut6_I1_O) 0.329 11.655 f u_cpu/wb_stage/write_buffer_way[1]_i_5/O
|
|
net (fo=7, routed) 0.762 12.417 u_cpu/addr_trans/tlb_entry/sc_cancel_req
|
|
SLICE_X46Y35 f u_cpu/addr_trans/tlb_entry/main_state[0]_i_3/I1
|
|
SLICE_X46Y35 LUT3 (Prop_lut3_I1_O) 0.124 12.541 f u_cpu/addr_trans/tlb_entry/main_state[0]_i_3/O
|
|
net (fo=3, routed) 0.719 13.260 u_cpu/dcache/main_state_reg[0]_2
|
|
SLICE_X43Y31 f u_cpu/dcache/ds_to_es_bus_r[235]_i_10/I3
|
|
SLICE_X43Y31 LUT6 (Prop_lut6_I3_O) 0.124 13.384 f u_cpu/dcache/ds_to_es_bus_r[235]_i_10/O
|
|
net (fo=3, routed) 0.415 13.799 u_cpu/mem_stage/data_data_ok
|
|
SLICE_X43Y30 f u_cpu/mem_stage/flush_inst_req_buffer[1]_i_15/I0
|
|
SLICE_X43Y30 LUT3 (Prop_lut3_I0_O) 0.124 13.923 f u_cpu/mem_stage/flush_inst_req_buffer[1]_i_15/O
|
|
net (fo=2, routed) 0.833 14.756 u_cpu/mem_stage/es_to_ms_bus_r_reg[70]_1
|
|
SLICE_X48Y30 f u_cpu/mem_stage/flush_inst_req_buffer[1]_i_14/I0
|
|
SLICE_X48Y30 LUT6 (Prop_lut6_I0_O) 0.124 14.880 f u_cpu/mem_stage/flush_inst_req_buffer[1]_i_14/O
|
|
net (fo=1, routed) 0.651 15.532 u_cpu/mem_stage/ms_ready_go
|
|
SLICE_X48Y25 f u_cpu/mem_stage/flush_inst_req_buffer[1]_i_13/I4
|
|
SLICE_X48Y25 LUT6 (Prop_lut6_I4_O) 0.124 15.656 f u_cpu/mem_stage/flush_inst_req_buffer[1]_i_13/O
|
|
net (fo=3, routed) 0.483 16.139 u_cpu/id_stage/flush_inst_req_buffer[31]_i_6
|
|
SLICE_X50Y25 f u_cpu/id_stage/flush_inst_req_buffer[1]_i_9/I1
|
|
SLICE_X50Y25 LUT6 (Prop_lut6_I1_O) 0.124 16.263 f u_cpu/id_stage/flush_inst_req_buffer[1]_i_9/O
|
|
net (fo=32, routed) 0.531 16.794 u_cpu/if_stage/nextpc5
|
|
SLICE_X51Y27 f u_cpu/if_stage/fetch_pc_r[6]_i_4/I2
|
|
SLICE_X51Y27 LUT6 (Prop_lut6_I2_O) 0.124 16.918 r u_cpu/if_stage/fetch_pc_r[6]_i_4/O
|
|
net (fo=1, routed) 3.059 19.977 u_cpu/if_stage/fetch_pc_r[6]_i_4_n_0
|
|
SLICE_X114Y28 r u_cpu/if_stage/fetch_pc_r[6]_i_2/I2
|
|
SLICE_X114Y28 LUT6 (Prop_lut6_I2_O) 0.124 20.101 r u_cpu/if_stage/fetch_pc_r[6]_i_2/O
|
|
net (fo=1, routed) 0.441 20.542 u_cpu/if_stage/fetch_pc_r[6]_i_2_n_0
|
|
SLICE_X114Y25 r u_cpu/if_stage/fetch_pc_r[6]_i_1/I2
|
|
SLICE_X114Y25 LUT6 (Prop_lut6_I2_O) 0.124 20.666 r u_cpu/if_stage/fetch_pc_r[6]_i_1/O
|
|
net (fo=6, routed) 3.249 23.915 u_cpu/icache/tagv_ram_way[1].u/mem_reg_reg_2[2]
|
|
SLICE_X49Y33 r u_cpu/icache/tagv_ram_way[1].u/mem_reg_reg_i_8/I4
|
|
SLICE_X49Y33 LUT5 (Prop_lut5_I4_O) 0.124 24.039 r u_cpu/icache/tagv_ram_way[1].u/mem_reg_reg_i_8/O
|
|
net (fo=16, routed) 1.922 25.962 u_cpu/icache/data_ram_way[0].data_ram_bank[1].u/ADDRBWRADDR[2]
|
|
RAMB18_X1Y3 RAMB18E1 r u_cpu/icache/data_ram_way[0].data_ram_bank[1].u/mem_reg_reg/ADDRBWRADDR[7]
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock cpu_clk rise edge) 30.323 30.323 r
|
|
clock source latency -5.674 24.648
|
|
propagated clock network latency
|
|
3.883 28.531
|
|
clock pessimism -0.418 28.113
|
|
clock uncertainty -0.074 28.039
|
|
RAMB18_X1Y3 RAMB18E1 (Setup_ramb18e1_CLKBWRCLK_ADDRBWRADDR[7])
|
|
-0.566 27.473 u_cpu/icache/data_ram_way[0].data_ram_bank[1].u/mem_reg_reg
|
|
-------------------------------------------------------------------
|
|
required time 27.473
|
|
arrival time -25.962
|
|
-------------------------------------------------------------------
|
|
slack 1.512
|
|
|
|
Slack (MET) : 1.512ns (required time - arrival time)
|
|
Source: u_cpu/addr_trans/data_vaddr_buffer_reg[14]/C
|
|
(rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns})
|
|
Destination: u_cpu/icache/data_ram_way[0].data_ram_bank[1].u/mem_reg_reg/ADDRBWRADDR[7]
|
|
(rising edge-triggered cell RAMB18E1 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns})
|
|
Path Group: cpu_clk
|
|
Path Type: Setup (Max at Slow Process Corner)
|
|
Requirement: 30.323ns (cpu_clk rise@30.323ns - cpu_clk rise@0.000ns)
|
|
Data Path Delay: 28.186ns (logic 5.333ns (18.920%) route 22.853ns (81.079%))
|
|
Logic Levels: 26 (CARRY4=4 LUT3=2 LUT4=1 LUT5=2 LUT6=15 MUXF7=1 MUXF8=1)
|
|
Clock Path Skew: 0.015ns (DCD - SCD + CPR)
|
|
Destination Clock Delay (DCD): -1.791ns = ( 28.531 - 30.323 )
|
|
Source Clock Delay (SCD): -2.225ns
|
|
Clock Pessimism Removal (CPR): -0.418ns
|
|
Clock Uncertainty: 0.074ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Discrete Jitter (DJ): 0.130ns
|
|
Phase Error (PE): 0.000ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock cpu_clk rise edge) 0.000 0.000 r
|
|
clock source latency -6.275 -6.275
|
|
propagated clock network latency
|
|
4.051 -2.225
|
|
SLICE_X35Y35 FDRE 0.000 -2.225 r u_cpu/addr_trans/data_vaddr_buffer_reg[14]/C
|
|
SLICE_X35Y35 FDRE (Prop_fdre_C_Q) 0.456 -1.769 r u_cpu/addr_trans/data_vaddr_buffer_reg[14]/Q
|
|
net (fo=33, routed) 1.442 -0.326 u_cpu/addr_trans/tlb_entry/data_vaddr_buffer[2]
|
|
SLICE_X42Y40 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_226/I5
|
|
SLICE_X42Y40 LUT6 (Prop_lut6_I5_O) 0.124 -0.202 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_226/O
|
|
net (fo=1, routed) 0.000 -0.202 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_226_n_0
|
|
SLICE_X42Y40 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_111/S[0]
|
|
SLICE_X42Y40 CARRY4 (Prop_carry4_S[0]_CO[3])
|
|
0.513 0.311 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_111/CO[3]
|
|
net (fo=1, routed) 0.000 0.311 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_111_n_0
|
|
SLICE_X42Y41 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_32/CI
|
|
SLICE_X42Y41 CARRY4 (Prop_carry4_CI_CO[2])
|
|
0.229 0.540 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_32/CO[2]
|
|
net (fo=1, routed) 1.009 1.549 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_32_n_1
|
|
SLICE_X40Y47 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_9/I1
|
|
SLICE_X40Y47 LUT6 (Prop_lut6_I1_O) 0.310 1.859 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_9/O
|
|
net (fo=2, routed) 0.635 2.494 u_cpu/addr_trans/tlb_entry/match1[28]
|
|
SLICE_X38Y47 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/I2
|
|
SLICE_X38Y47 LUT4 (Prop_lut4_I2_O) 0.124 2.618 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/O
|
|
net (fo=2, routed) 0.667 3.285 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2_n_0
|
|
SLICE_X39Y47 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/I0
|
|
SLICE_X39Y47 LUT5 (Prop_lut5_I0_O) 0.124 3.409 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/O
|
|
net (fo=2, routed) 1.103 4.512 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2_n_0
|
|
SLICE_X38Y50 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/I0
|
|
SLICE_X38Y50 LUT6 (Prop_lut6_I0_O) 0.124 4.636 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/O
|
|
net (fo=89, routed) 1.162 5.797 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus[8]
|
|
SLICE_X42Y51 r u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_38__0/S
|
|
SLICE_X42Y51 MUXF7 (Prop_muxf7_S_O) 0.292 6.089 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_38__0/O
|
|
net (fo=1, routed) 0.000 6.089 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_38__0_n_0
|
|
SLICE_X42Y51 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_16__0/I1
|
|
SLICE_X42Y51 MUXF8 (Prop_muxf8_I1_O) 0.088 6.177 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_16__0/O
|
|
net (fo=1, routed) 0.957 7.134 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_16__0_n_0
|
|
SLICE_X42Y50 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7/I0
|
|
SLICE_X42Y50 LUT6 (Prop_lut6_I0_O) 0.319 7.453 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7/O
|
|
net (fo=1, routed) 0.435 7.888 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7_n_0
|
|
SLICE_X44Y50 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0/I5
|
|
SLICE_X44Y50 LUT6 (Prop_lut6_I5_O) 0.124 8.012 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0/O
|
|
net (fo=10, routed) 0.740 8.753 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0_n_0
|
|
SLICE_X44Y50 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[5]_i_1__0/I3
|
|
SLICE_X44Y50 LUT6 (Prop_lut6_I3_O) 0.124 8.877 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[5]_i_1__0/O
|
|
net (fo=6, routed) 0.845 9.722 u_cpu/u_csr/ms_to_ws_bus[13]
|
|
SLICE_X50Y46 f u_cpu/u_csr/write_buffer_way[1]_i_18/I3
|
|
SLICE_X50Y46 LUT6 (Prop_lut6_I3_O) 0.124 9.846 f u_cpu/u_csr/write_buffer_way[1]_i_18/O
|
|
net (fo=1, routed) 0.000 9.846 u_cpu/u_csr/write_buffer_way[1]_i_18_n_0
|
|
SLICE_X50Y46 f u_cpu/u_csr/write_buffer_way_reg[1]_i_11/S[0]
|
|
SLICE_X50Y46 CARRY4 (Prop_carry4_S[0]_CO[3])
|
|
0.532 10.378 r u_cpu/u_csr/write_buffer_way_reg[1]_i_11/CO[3]
|
|
net (fo=1, routed) 0.000 10.378 u_cpu/u_csr/write_buffer_way_reg[1]_i_11_n_0
|
|
SLICE_X50Y47 r u_cpu/u_csr/write_buffer_way_reg[1]_i_9/CI
|
|
SLICE_X50Y47 CARRY4 (Prop_carry4_CI_CO[1])
|
|
0.157 10.535 r u_cpu/u_csr/write_buffer_way_reg[1]_i_9/CO[1]
|
|
net (fo=2, routed) 0.791 11.326 u_cpu/wb_stage/CO[0]
|
|
SLICE_X46Y39 r u_cpu/wb_stage/write_buffer_way[1]_i_5/I1
|
|
SLICE_X46Y39 LUT6 (Prop_lut6_I1_O) 0.329 11.655 f u_cpu/wb_stage/write_buffer_way[1]_i_5/O
|
|
net (fo=7, routed) 0.762 12.417 u_cpu/addr_trans/tlb_entry/sc_cancel_req
|
|
SLICE_X46Y35 f u_cpu/addr_trans/tlb_entry/main_state[0]_i_3/I1
|
|
SLICE_X46Y35 LUT3 (Prop_lut3_I1_O) 0.124 12.541 f u_cpu/addr_trans/tlb_entry/main_state[0]_i_3/O
|
|
net (fo=3, routed) 0.719 13.260 u_cpu/dcache/main_state_reg[0]_2
|
|
SLICE_X43Y31 f u_cpu/dcache/ds_to_es_bus_r[235]_i_10/I3
|
|
SLICE_X43Y31 LUT6 (Prop_lut6_I3_O) 0.124 13.384 f u_cpu/dcache/ds_to_es_bus_r[235]_i_10/O
|
|
net (fo=3, routed) 0.415 13.799 u_cpu/mem_stage/data_data_ok
|
|
SLICE_X43Y30 f u_cpu/mem_stage/flush_inst_req_buffer[1]_i_15/I0
|
|
SLICE_X43Y30 LUT3 (Prop_lut3_I0_O) 0.124 13.923 f u_cpu/mem_stage/flush_inst_req_buffer[1]_i_15/O
|
|
net (fo=2, routed) 0.833 14.756 u_cpu/mem_stage/es_to_ms_bus_r_reg[70]_1
|
|
SLICE_X48Y30 f u_cpu/mem_stage/flush_inst_req_buffer[1]_i_14/I0
|
|
SLICE_X48Y30 LUT6 (Prop_lut6_I0_O) 0.124 14.880 f u_cpu/mem_stage/flush_inst_req_buffer[1]_i_14/O
|
|
net (fo=1, routed) 0.651 15.532 u_cpu/mem_stage/ms_ready_go
|
|
SLICE_X48Y25 f u_cpu/mem_stage/flush_inst_req_buffer[1]_i_13/I4
|
|
SLICE_X48Y25 LUT6 (Prop_lut6_I4_O) 0.124 15.656 f u_cpu/mem_stage/flush_inst_req_buffer[1]_i_13/O
|
|
net (fo=3, routed) 0.483 16.139 u_cpu/id_stage/flush_inst_req_buffer[31]_i_6
|
|
SLICE_X50Y25 f u_cpu/id_stage/flush_inst_req_buffer[1]_i_9/I1
|
|
SLICE_X50Y25 LUT6 (Prop_lut6_I1_O) 0.124 16.263 f u_cpu/id_stage/flush_inst_req_buffer[1]_i_9/O
|
|
net (fo=32, routed) 0.531 16.794 u_cpu/if_stage/nextpc5
|
|
SLICE_X51Y27 f u_cpu/if_stage/fetch_pc_r[6]_i_4/I2
|
|
SLICE_X51Y27 LUT6 (Prop_lut6_I2_O) 0.124 16.918 r u_cpu/if_stage/fetch_pc_r[6]_i_4/O
|
|
net (fo=1, routed) 3.059 19.977 u_cpu/if_stage/fetch_pc_r[6]_i_4_n_0
|
|
SLICE_X114Y28 r u_cpu/if_stage/fetch_pc_r[6]_i_2/I2
|
|
SLICE_X114Y28 LUT6 (Prop_lut6_I2_O) 0.124 20.101 r u_cpu/if_stage/fetch_pc_r[6]_i_2/O
|
|
net (fo=1, routed) 0.441 20.542 u_cpu/if_stage/fetch_pc_r[6]_i_2_n_0
|
|
SLICE_X114Y25 r u_cpu/if_stage/fetch_pc_r[6]_i_1/I2
|
|
SLICE_X114Y25 LUT6 (Prop_lut6_I2_O) 0.124 20.666 r u_cpu/if_stage/fetch_pc_r[6]_i_1/O
|
|
net (fo=6, routed) 3.249 23.915 u_cpu/icache/tagv_ram_way[1].u/mem_reg_reg_2[2]
|
|
SLICE_X49Y33 r u_cpu/icache/tagv_ram_way[1].u/mem_reg_reg_i_8/I4
|
|
SLICE_X49Y33 LUT5 (Prop_lut5_I4_O) 0.124 24.039 r u_cpu/icache/tagv_ram_way[1].u/mem_reg_reg_i_8/O
|
|
net (fo=16, routed) 1.922 25.962 u_cpu/icache/data_ram_way[0].data_ram_bank[1].u/ADDRBWRADDR[2]
|
|
RAMB18_X1Y3 RAMB18E1 r u_cpu/icache/data_ram_way[0].data_ram_bank[1].u/mem_reg_reg/ADDRBWRADDR[7]
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock cpu_clk rise edge) 30.323 30.323 r
|
|
clock source latency -5.674 24.648
|
|
propagated clock network latency
|
|
3.883 28.531
|
|
clock pessimism -0.418 28.113
|
|
clock uncertainty -0.074 28.039
|
|
RAMB18_X1Y3 RAMB18E1 (Setup_ramb18e1_CLKBWRCLK_ADDRBWRADDR[7])
|
|
-0.566 27.473 u_cpu/icache/data_ram_way[0].data_ram_bank[1].u/mem_reg_reg
|
|
-------------------------------------------------------------------
|
|
required time 27.473
|
|
arrival time -25.962
|
|
-------------------------------------------------------------------
|
|
slack 1.512
|
|
|
|
Slack (MET) : 1.855ns (required time - arrival time)
|
|
Source: u_cpu/addr_trans/data_vaddr_buffer_reg[14]/C
|
|
(rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns})
|
|
Destination: u_cpu/icache/data_ram_way[0].data_ram_bank[2].u/mem_reg_reg/ADDRARDADDR[7]
|
|
(rising edge-triggered cell RAMB18E1 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns})
|
|
Path Group: cpu_clk
|
|
Path Type: Setup (Max at Slow Process Corner)
|
|
Requirement: 30.323ns (cpu_clk rise@30.323ns - cpu_clk rise@0.000ns)
|
|
Data Path Delay: 27.741ns (logic 5.333ns (19.224%) route 22.408ns (80.776%))
|
|
Logic Levels: 26 (CARRY4=4 LUT3=2 LUT4=1 LUT5=2 LUT6=15 MUXF7=1 MUXF8=1)
|
|
Clock Path Skew: -0.087ns (DCD - SCD + CPR)
|
|
Destination Clock Delay (DCD): -1.893ns = ( 28.429 - 30.323 )
|
|
Source Clock Delay (SCD): -2.225ns
|
|
Clock Pessimism Removal (CPR): -0.418ns
|
|
Clock Uncertainty: 0.074ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Discrete Jitter (DJ): 0.130ns
|
|
Phase Error (PE): 0.000ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock cpu_clk rise edge) 0.000 0.000 r
|
|
clock source latency -6.275 -6.275
|
|
propagated clock network latency
|
|
4.051 -2.225
|
|
SLICE_X35Y35 FDRE 0.000 -2.225 r u_cpu/addr_trans/data_vaddr_buffer_reg[14]/C
|
|
SLICE_X35Y35 FDRE (Prop_fdre_C_Q) 0.456 -1.769 r u_cpu/addr_trans/data_vaddr_buffer_reg[14]/Q
|
|
net (fo=33, routed) 1.442 -0.326 u_cpu/addr_trans/tlb_entry/data_vaddr_buffer[2]
|
|
SLICE_X42Y40 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_226/I5
|
|
SLICE_X42Y40 LUT6 (Prop_lut6_I5_O) 0.124 -0.202 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_226/O
|
|
net (fo=1, routed) 0.000 -0.202 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_226_n_0
|
|
SLICE_X42Y40 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_111/S[0]
|
|
SLICE_X42Y40 CARRY4 (Prop_carry4_S[0]_CO[3])
|
|
0.513 0.311 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_111/CO[3]
|
|
net (fo=1, routed) 0.000 0.311 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_111_n_0
|
|
SLICE_X42Y41 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_32/CI
|
|
SLICE_X42Y41 CARRY4 (Prop_carry4_CI_CO[2])
|
|
0.229 0.540 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_32/CO[2]
|
|
net (fo=1, routed) 1.009 1.549 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_32_n_1
|
|
SLICE_X40Y47 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_9/I1
|
|
SLICE_X40Y47 LUT6 (Prop_lut6_I1_O) 0.310 1.859 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_9/O
|
|
net (fo=2, routed) 0.635 2.494 u_cpu/addr_trans/tlb_entry/match1[28]
|
|
SLICE_X38Y47 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/I2
|
|
SLICE_X38Y47 LUT4 (Prop_lut4_I2_O) 0.124 2.618 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/O
|
|
net (fo=2, routed) 0.667 3.285 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2_n_0
|
|
SLICE_X39Y47 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/I0
|
|
SLICE_X39Y47 LUT5 (Prop_lut5_I0_O) 0.124 3.409 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/O
|
|
net (fo=2, routed) 1.103 4.512 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2_n_0
|
|
SLICE_X38Y50 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/I0
|
|
SLICE_X38Y50 LUT6 (Prop_lut6_I0_O) 0.124 4.636 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/O
|
|
net (fo=89, routed) 1.162 5.797 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus[8]
|
|
SLICE_X42Y51 r u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_38__0/S
|
|
SLICE_X42Y51 MUXF7 (Prop_muxf7_S_O) 0.292 6.089 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_38__0/O
|
|
net (fo=1, routed) 0.000 6.089 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_38__0_n_0
|
|
SLICE_X42Y51 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_16__0/I1
|
|
SLICE_X42Y51 MUXF8 (Prop_muxf8_I1_O) 0.088 6.177 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_16__0/O
|
|
net (fo=1, routed) 0.957 7.134 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_16__0_n_0
|
|
SLICE_X42Y50 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7/I0
|
|
SLICE_X42Y50 LUT6 (Prop_lut6_I0_O) 0.319 7.453 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7/O
|
|
net (fo=1, routed) 0.435 7.888 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7_n_0
|
|
SLICE_X44Y50 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0/I5
|
|
SLICE_X44Y50 LUT6 (Prop_lut6_I5_O) 0.124 8.012 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0/O
|
|
net (fo=10, routed) 0.740 8.753 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0_n_0
|
|
SLICE_X44Y50 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[5]_i_1__0/I3
|
|
SLICE_X44Y50 LUT6 (Prop_lut6_I3_O) 0.124 8.877 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[5]_i_1__0/O
|
|
net (fo=6, routed) 0.845 9.722 u_cpu/u_csr/ms_to_ws_bus[13]
|
|
SLICE_X50Y46 r u_cpu/u_csr/write_buffer_way[1]_i_18/I3
|
|
SLICE_X50Y46 LUT6 (Prop_lut6_I3_O) 0.124 9.846 r u_cpu/u_csr/write_buffer_way[1]_i_18/O
|
|
net (fo=1, routed) 0.000 9.846 u_cpu/u_csr/write_buffer_way[1]_i_18_n_0
|
|
SLICE_X50Y46 r u_cpu/u_csr/write_buffer_way_reg[1]_i_11/S[0]
|
|
SLICE_X50Y46 CARRY4 (Prop_carry4_S[0]_CO[3])
|
|
0.532 10.378 r u_cpu/u_csr/write_buffer_way_reg[1]_i_11/CO[3]
|
|
net (fo=1, routed) 0.000 10.378 u_cpu/u_csr/write_buffer_way_reg[1]_i_11_n_0
|
|
SLICE_X50Y47 r u_cpu/u_csr/write_buffer_way_reg[1]_i_9/CI
|
|
SLICE_X50Y47 CARRY4 (Prop_carry4_CI_CO[1])
|
|
0.157 10.535 f u_cpu/u_csr/write_buffer_way_reg[1]_i_9/CO[1]
|
|
net (fo=2, routed) 0.791 11.326 u_cpu/wb_stage/CO[0]
|
|
SLICE_X46Y39 f u_cpu/wb_stage/write_buffer_way[1]_i_5/I1
|
|
SLICE_X46Y39 LUT6 (Prop_lut6_I1_O) 0.329 11.655 r u_cpu/wb_stage/write_buffer_way[1]_i_5/O
|
|
net (fo=7, routed) 0.762 12.417 u_cpu/addr_trans/tlb_entry/sc_cancel_req
|
|
SLICE_X46Y35 r u_cpu/addr_trans/tlb_entry/main_state[0]_i_3/I1
|
|
SLICE_X46Y35 LUT3 (Prop_lut3_I1_O) 0.124 12.541 r u_cpu/addr_trans/tlb_entry/main_state[0]_i_3/O
|
|
net (fo=3, routed) 0.719 13.260 u_cpu/dcache/main_state_reg[0]_2
|
|
SLICE_X43Y31 r u_cpu/dcache/ds_to_es_bus_r[235]_i_10/I3
|
|
SLICE_X43Y31 LUT6 (Prop_lut6_I3_O) 0.124 13.384 r u_cpu/dcache/ds_to_es_bus_r[235]_i_10/O
|
|
net (fo=3, routed) 0.415 13.799 u_cpu/mem_stage/data_data_ok
|
|
SLICE_X43Y30 r u_cpu/mem_stage/flush_inst_req_buffer[1]_i_15/I0
|
|
SLICE_X43Y30 LUT3 (Prop_lut3_I0_O) 0.124 13.923 r u_cpu/mem_stage/flush_inst_req_buffer[1]_i_15/O
|
|
net (fo=2, routed) 0.833 14.756 u_cpu/mem_stage/es_to_ms_bus_r_reg[70]_1
|
|
SLICE_X48Y30 r u_cpu/mem_stage/flush_inst_req_buffer[1]_i_14/I0
|
|
SLICE_X48Y30 LUT6 (Prop_lut6_I0_O) 0.124 14.880 r u_cpu/mem_stage/flush_inst_req_buffer[1]_i_14/O
|
|
net (fo=1, routed) 0.651 15.532 u_cpu/mem_stage/ms_ready_go
|
|
SLICE_X48Y25 r u_cpu/mem_stage/flush_inst_req_buffer[1]_i_13/I4
|
|
SLICE_X48Y25 LUT6 (Prop_lut6_I4_O) 0.124 15.656 r u_cpu/mem_stage/flush_inst_req_buffer[1]_i_13/O
|
|
net (fo=3, routed) 0.483 16.139 u_cpu/id_stage/flush_inst_req_buffer[31]_i_6
|
|
SLICE_X50Y25 r u_cpu/id_stage/flush_inst_req_buffer[1]_i_9/I1
|
|
SLICE_X50Y25 LUT6 (Prop_lut6_I1_O) 0.124 16.263 r u_cpu/id_stage/flush_inst_req_buffer[1]_i_9/O
|
|
net (fo=32, routed) 0.531 16.794 u_cpu/if_stage/nextpc5
|
|
SLICE_X51Y27 r u_cpu/if_stage/fetch_pc_r[6]_i_4/I2
|
|
SLICE_X51Y27 LUT6 (Prop_lut6_I2_O) 0.124 16.918 r u_cpu/if_stage/fetch_pc_r[6]_i_4/O
|
|
net (fo=1, routed) 3.059 19.977 u_cpu/if_stage/fetch_pc_r[6]_i_4_n_0
|
|
SLICE_X114Y28 r u_cpu/if_stage/fetch_pc_r[6]_i_2/I2
|
|
SLICE_X114Y28 LUT6 (Prop_lut6_I2_O) 0.124 20.101 r u_cpu/if_stage/fetch_pc_r[6]_i_2/O
|
|
net (fo=1, routed) 0.441 20.542 u_cpu/if_stage/fetch_pc_r[6]_i_2_n_0
|
|
SLICE_X114Y25 r u_cpu/if_stage/fetch_pc_r[6]_i_1/I2
|
|
SLICE_X114Y25 LUT6 (Prop_lut6_I2_O) 0.124 20.666 r u_cpu/if_stage/fetch_pc_r[6]_i_1/O
|
|
net (fo=6, routed) 3.249 23.915 u_cpu/icache/tagv_ram_way[1].u/mem_reg_reg_2[2]
|
|
SLICE_X49Y33 r u_cpu/icache/tagv_ram_way[1].u/mem_reg_reg_i_8/I4
|
|
SLICE_X49Y33 LUT5 (Prop_lut5_I4_O) 0.124 24.039 r u_cpu/icache/tagv_ram_way[1].u/mem_reg_reg_i_8/O
|
|
net (fo=16, routed) 1.477 25.516 u_cpu/icache/data_ram_way[0].data_ram_bank[2].u/ADDRBWRADDR[2]
|
|
RAMB18_X2Y2 RAMB18E1 r u_cpu/icache/data_ram_way[0].data_ram_bank[2].u/mem_reg_reg/ADDRARDADDR[7]
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock cpu_clk rise edge) 30.323 30.323 r
|
|
clock source latency -5.674 24.648
|
|
propagated clock network latency
|
|
3.781 28.429
|
|
clock pessimism -0.418 28.011
|
|
clock uncertainty -0.074 27.937
|
|
RAMB18_X2Y2 RAMB18E1 (Setup_ramb18e1_CLKARDCLK_ADDRARDADDR[7])
|
|
-0.566 27.371 u_cpu/icache/data_ram_way[0].data_ram_bank[2].u/mem_reg_reg
|
|
-------------------------------------------------------------------
|
|
required time 27.371
|
|
arrival time -25.516
|
|
-------------------------------------------------------------------
|
|
slack 1.855
|
|
|
|
Slack (MET) : 1.855ns (required time - arrival time)
|
|
Source: u_cpu/addr_trans/data_vaddr_buffer_reg[14]/C
|
|
(rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns})
|
|
Destination: u_cpu/icache/data_ram_way[0].data_ram_bank[2].u/mem_reg_reg/ADDRARDADDR[7]
|
|
(rising edge-triggered cell RAMB18E1 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns})
|
|
Path Group: cpu_clk
|
|
Path Type: Setup (Max at Slow Process Corner)
|
|
Requirement: 30.323ns (cpu_clk rise@30.323ns - cpu_clk rise@0.000ns)
|
|
Data Path Delay: 27.741ns (logic 5.333ns (19.224%) route 22.408ns (80.776%))
|
|
Logic Levels: 26 (CARRY4=4 LUT3=2 LUT4=1 LUT5=2 LUT6=15 MUXF7=1 MUXF8=1)
|
|
Clock Path Skew: -0.087ns (DCD - SCD + CPR)
|
|
Destination Clock Delay (DCD): -1.893ns = ( 28.429 - 30.323 )
|
|
Source Clock Delay (SCD): -2.225ns
|
|
Clock Pessimism Removal (CPR): -0.418ns
|
|
Clock Uncertainty: 0.074ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Discrete Jitter (DJ): 0.130ns
|
|
Phase Error (PE): 0.000ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock cpu_clk rise edge) 0.000 0.000 r
|
|
clock source latency -6.275 -6.275
|
|
propagated clock network latency
|
|
4.051 -2.225
|
|
SLICE_X35Y35 FDRE 0.000 -2.225 r u_cpu/addr_trans/data_vaddr_buffer_reg[14]/C
|
|
SLICE_X35Y35 FDRE (Prop_fdre_C_Q) 0.456 -1.769 r u_cpu/addr_trans/data_vaddr_buffer_reg[14]/Q
|
|
net (fo=33, routed) 1.442 -0.326 u_cpu/addr_trans/tlb_entry/data_vaddr_buffer[2]
|
|
SLICE_X42Y40 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_226/I5
|
|
SLICE_X42Y40 LUT6 (Prop_lut6_I5_O) 0.124 -0.202 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_226/O
|
|
net (fo=1, routed) 0.000 -0.202 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_226_n_0
|
|
SLICE_X42Y40 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_111/S[0]
|
|
SLICE_X42Y40 CARRY4 (Prop_carry4_S[0]_CO[3])
|
|
0.513 0.311 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_111/CO[3]
|
|
net (fo=1, routed) 0.000 0.311 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_111_n_0
|
|
SLICE_X42Y41 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_32/CI
|
|
SLICE_X42Y41 CARRY4 (Prop_carry4_CI_CO[2])
|
|
0.229 0.540 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_32/CO[2]
|
|
net (fo=1, routed) 1.009 1.549 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_32_n_1
|
|
SLICE_X40Y47 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_9/I1
|
|
SLICE_X40Y47 LUT6 (Prop_lut6_I1_O) 0.310 1.859 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_9/O
|
|
net (fo=2, routed) 0.635 2.494 u_cpu/addr_trans/tlb_entry/match1[28]
|
|
SLICE_X38Y47 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/I2
|
|
SLICE_X38Y47 LUT4 (Prop_lut4_I2_O) 0.124 2.618 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/O
|
|
net (fo=2, routed) 0.667 3.285 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2_n_0
|
|
SLICE_X39Y47 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/I0
|
|
SLICE_X39Y47 LUT5 (Prop_lut5_I0_O) 0.124 3.409 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/O
|
|
net (fo=2, routed) 1.103 4.512 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2_n_0
|
|
SLICE_X38Y50 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/I0
|
|
SLICE_X38Y50 LUT6 (Prop_lut6_I0_O) 0.124 4.636 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/O
|
|
net (fo=89, routed) 1.162 5.797 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus[8]
|
|
SLICE_X42Y51 r u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_38__0/S
|
|
SLICE_X42Y51 MUXF7 (Prop_muxf7_S_O) 0.292 6.089 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_38__0/O
|
|
net (fo=1, routed) 0.000 6.089 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_38__0_n_0
|
|
SLICE_X42Y51 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_16__0/I1
|
|
SLICE_X42Y51 MUXF8 (Prop_muxf8_I1_O) 0.088 6.177 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_16__0/O
|
|
net (fo=1, routed) 0.957 7.134 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_16__0_n_0
|
|
SLICE_X42Y50 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7/I0
|
|
SLICE_X42Y50 LUT6 (Prop_lut6_I0_O) 0.319 7.453 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7/O
|
|
net (fo=1, routed) 0.435 7.888 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7_n_0
|
|
SLICE_X44Y50 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0/I5
|
|
SLICE_X44Y50 LUT6 (Prop_lut6_I5_O) 0.124 8.012 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0/O
|
|
net (fo=10, routed) 0.740 8.753 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0_n_0
|
|
SLICE_X44Y50 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[5]_i_1__0/I3
|
|
SLICE_X44Y50 LUT6 (Prop_lut6_I3_O) 0.124 8.877 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[5]_i_1__0/O
|
|
net (fo=6, routed) 0.845 9.722 u_cpu/u_csr/ms_to_ws_bus[13]
|
|
SLICE_X50Y46 f u_cpu/u_csr/write_buffer_way[1]_i_18/I3
|
|
SLICE_X50Y46 LUT6 (Prop_lut6_I3_O) 0.124 9.846 r u_cpu/u_csr/write_buffer_way[1]_i_18/O
|
|
net (fo=1, routed) 0.000 9.846 u_cpu/u_csr/write_buffer_way[1]_i_18_n_0
|
|
SLICE_X50Y46 r u_cpu/u_csr/write_buffer_way_reg[1]_i_11/S[0]
|
|
SLICE_X50Y46 CARRY4 (Prop_carry4_S[0]_CO[3])
|
|
0.532 10.378 r u_cpu/u_csr/write_buffer_way_reg[1]_i_11/CO[3]
|
|
net (fo=1, routed) 0.000 10.378 u_cpu/u_csr/write_buffer_way_reg[1]_i_11_n_0
|
|
SLICE_X50Y47 r u_cpu/u_csr/write_buffer_way_reg[1]_i_9/CI
|
|
SLICE_X50Y47 CARRY4 (Prop_carry4_CI_CO[1])
|
|
0.157 10.535 f u_cpu/u_csr/write_buffer_way_reg[1]_i_9/CO[1]
|
|
net (fo=2, routed) 0.791 11.326 u_cpu/wb_stage/CO[0]
|
|
SLICE_X46Y39 f u_cpu/wb_stage/write_buffer_way[1]_i_5/I1
|
|
SLICE_X46Y39 LUT6 (Prop_lut6_I1_O) 0.329 11.655 r u_cpu/wb_stage/write_buffer_way[1]_i_5/O
|
|
net (fo=7, routed) 0.762 12.417 u_cpu/addr_trans/tlb_entry/sc_cancel_req
|
|
SLICE_X46Y35 r u_cpu/addr_trans/tlb_entry/main_state[0]_i_3/I1
|
|
SLICE_X46Y35 LUT3 (Prop_lut3_I1_O) 0.124 12.541 r u_cpu/addr_trans/tlb_entry/main_state[0]_i_3/O
|
|
net (fo=3, routed) 0.719 13.260 u_cpu/dcache/main_state_reg[0]_2
|
|
SLICE_X43Y31 r u_cpu/dcache/ds_to_es_bus_r[235]_i_10/I3
|
|
SLICE_X43Y31 LUT6 (Prop_lut6_I3_O) 0.124 13.384 r u_cpu/dcache/ds_to_es_bus_r[235]_i_10/O
|
|
net (fo=3, routed) 0.415 13.799 u_cpu/mem_stage/data_data_ok
|
|
SLICE_X43Y30 r u_cpu/mem_stage/flush_inst_req_buffer[1]_i_15/I0
|
|
SLICE_X43Y30 LUT3 (Prop_lut3_I0_O) 0.124 13.923 r u_cpu/mem_stage/flush_inst_req_buffer[1]_i_15/O
|
|
net (fo=2, routed) 0.833 14.756 u_cpu/mem_stage/es_to_ms_bus_r_reg[70]_1
|
|
SLICE_X48Y30 r u_cpu/mem_stage/flush_inst_req_buffer[1]_i_14/I0
|
|
SLICE_X48Y30 LUT6 (Prop_lut6_I0_O) 0.124 14.880 r u_cpu/mem_stage/flush_inst_req_buffer[1]_i_14/O
|
|
net (fo=1, routed) 0.651 15.532 u_cpu/mem_stage/ms_ready_go
|
|
SLICE_X48Y25 r u_cpu/mem_stage/flush_inst_req_buffer[1]_i_13/I4
|
|
SLICE_X48Y25 LUT6 (Prop_lut6_I4_O) 0.124 15.656 r u_cpu/mem_stage/flush_inst_req_buffer[1]_i_13/O
|
|
net (fo=3, routed) 0.483 16.139 u_cpu/id_stage/flush_inst_req_buffer[31]_i_6
|
|
SLICE_X50Y25 r u_cpu/id_stage/flush_inst_req_buffer[1]_i_9/I1
|
|
SLICE_X50Y25 LUT6 (Prop_lut6_I1_O) 0.124 16.263 r u_cpu/id_stage/flush_inst_req_buffer[1]_i_9/O
|
|
net (fo=32, routed) 0.531 16.794 u_cpu/if_stage/nextpc5
|
|
SLICE_X51Y27 r u_cpu/if_stage/fetch_pc_r[6]_i_4/I2
|
|
SLICE_X51Y27 LUT6 (Prop_lut6_I2_O) 0.124 16.918 r u_cpu/if_stage/fetch_pc_r[6]_i_4/O
|
|
net (fo=1, routed) 3.059 19.977 u_cpu/if_stage/fetch_pc_r[6]_i_4_n_0
|
|
SLICE_X114Y28 r u_cpu/if_stage/fetch_pc_r[6]_i_2/I2
|
|
SLICE_X114Y28 LUT6 (Prop_lut6_I2_O) 0.124 20.101 r u_cpu/if_stage/fetch_pc_r[6]_i_2/O
|
|
net (fo=1, routed) 0.441 20.542 u_cpu/if_stage/fetch_pc_r[6]_i_2_n_0
|
|
SLICE_X114Y25 r u_cpu/if_stage/fetch_pc_r[6]_i_1/I2
|
|
SLICE_X114Y25 LUT6 (Prop_lut6_I2_O) 0.124 20.666 r u_cpu/if_stage/fetch_pc_r[6]_i_1/O
|
|
net (fo=6, routed) 3.249 23.915 u_cpu/icache/tagv_ram_way[1].u/mem_reg_reg_2[2]
|
|
SLICE_X49Y33 r u_cpu/icache/tagv_ram_way[1].u/mem_reg_reg_i_8/I4
|
|
SLICE_X49Y33 LUT5 (Prop_lut5_I4_O) 0.124 24.039 r u_cpu/icache/tagv_ram_way[1].u/mem_reg_reg_i_8/O
|
|
net (fo=16, routed) 1.477 25.516 u_cpu/icache/data_ram_way[0].data_ram_bank[2].u/ADDRBWRADDR[2]
|
|
RAMB18_X2Y2 RAMB18E1 r u_cpu/icache/data_ram_way[0].data_ram_bank[2].u/mem_reg_reg/ADDRARDADDR[7]
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock cpu_clk rise edge) 30.323 30.323 r
|
|
clock source latency -5.674 24.648
|
|
propagated clock network latency
|
|
3.781 28.429
|
|
clock pessimism -0.418 28.011
|
|
clock uncertainty -0.074 27.937
|
|
RAMB18_X2Y2 RAMB18E1 (Setup_ramb18e1_CLKARDCLK_ADDRARDADDR[7])
|
|
-0.566 27.371 u_cpu/icache/data_ram_way[0].data_ram_bank[2].u/mem_reg_reg
|
|
-------------------------------------------------------------------
|
|
required time 27.371
|
|
arrival time -25.516
|
|
-------------------------------------------------------------------
|
|
slack 1.855
|
|
|
|
Slack (MET) : 1.855ns (required time - arrival time)
|
|
Source: u_cpu/addr_trans/data_vaddr_buffer_reg[14]/C
|
|
(rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns})
|
|
Destination: u_cpu/icache/data_ram_way[0].data_ram_bank[2].u/mem_reg_reg/ADDRARDADDR[7]
|
|
(rising edge-triggered cell RAMB18E1 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns})
|
|
Path Group: cpu_clk
|
|
Path Type: Setup (Max at Slow Process Corner)
|
|
Requirement: 30.323ns (cpu_clk rise@30.323ns - cpu_clk rise@0.000ns)
|
|
Data Path Delay: 27.741ns (logic 5.333ns (19.224%) route 22.408ns (80.776%))
|
|
Logic Levels: 26 (CARRY4=4 LUT3=2 LUT4=1 LUT5=2 LUT6=15 MUXF7=1 MUXF8=1)
|
|
Clock Path Skew: -0.087ns (DCD - SCD + CPR)
|
|
Destination Clock Delay (DCD): -1.893ns = ( 28.429 - 30.323 )
|
|
Source Clock Delay (SCD): -2.225ns
|
|
Clock Pessimism Removal (CPR): -0.418ns
|
|
Clock Uncertainty: 0.074ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Discrete Jitter (DJ): 0.130ns
|
|
Phase Error (PE): 0.000ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock cpu_clk rise edge) 0.000 0.000 r
|
|
clock source latency -6.275 -6.275
|
|
propagated clock network latency
|
|
4.051 -2.225
|
|
SLICE_X35Y35 FDRE 0.000 -2.225 r u_cpu/addr_trans/data_vaddr_buffer_reg[14]/C
|
|
SLICE_X35Y35 FDRE (Prop_fdre_C_Q) 0.456 -1.769 r u_cpu/addr_trans/data_vaddr_buffer_reg[14]/Q
|
|
net (fo=33, routed) 1.442 -0.326 u_cpu/addr_trans/tlb_entry/data_vaddr_buffer[2]
|
|
SLICE_X42Y40 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_226/I5
|
|
SLICE_X42Y40 LUT6 (Prop_lut6_I5_O) 0.124 -0.202 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_226/O
|
|
net (fo=1, routed) 0.000 -0.202 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_226_n_0
|
|
SLICE_X42Y40 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_111/S[0]
|
|
SLICE_X42Y40 CARRY4 (Prop_carry4_S[0]_CO[3])
|
|
0.513 0.311 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_111/CO[3]
|
|
net (fo=1, routed) 0.000 0.311 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_111_n_0
|
|
SLICE_X42Y41 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_32/CI
|
|
SLICE_X42Y41 CARRY4 (Prop_carry4_CI_CO[2])
|
|
0.229 0.540 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_32/CO[2]
|
|
net (fo=1, routed) 1.009 1.549 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_32_n_1
|
|
SLICE_X40Y47 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_9/I1
|
|
SLICE_X40Y47 LUT6 (Prop_lut6_I1_O) 0.310 1.859 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_9/O
|
|
net (fo=2, routed) 0.635 2.494 u_cpu/addr_trans/tlb_entry/match1[28]
|
|
SLICE_X38Y47 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/I2
|
|
SLICE_X38Y47 LUT4 (Prop_lut4_I2_O) 0.124 2.618 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/O
|
|
net (fo=2, routed) 0.667 3.285 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2_n_0
|
|
SLICE_X39Y47 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/I0
|
|
SLICE_X39Y47 LUT5 (Prop_lut5_I0_O) 0.124 3.409 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/O
|
|
net (fo=2, routed) 1.103 4.512 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2_n_0
|
|
SLICE_X38Y50 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/I0
|
|
SLICE_X38Y50 LUT6 (Prop_lut6_I0_O) 0.124 4.636 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/O
|
|
net (fo=89, routed) 1.162 5.797 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus[8]
|
|
SLICE_X42Y51 r u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_38__0/S
|
|
SLICE_X42Y51 MUXF7 (Prop_muxf7_S_O) 0.292 6.089 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_38__0/O
|
|
net (fo=1, routed) 0.000 6.089 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_38__0_n_0
|
|
SLICE_X42Y51 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_16__0/I1
|
|
SLICE_X42Y51 MUXF8 (Prop_muxf8_I1_O) 0.088 6.177 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_16__0/O
|
|
net (fo=1, routed) 0.957 7.134 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_16__0_n_0
|
|
SLICE_X42Y50 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7/I0
|
|
SLICE_X42Y50 LUT6 (Prop_lut6_I0_O) 0.319 7.453 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7/O
|
|
net (fo=1, routed) 0.435 7.888 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7_n_0
|
|
SLICE_X44Y50 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0/I5
|
|
SLICE_X44Y50 LUT6 (Prop_lut6_I5_O) 0.124 8.012 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0/O
|
|
net (fo=10, routed) 0.740 8.753 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0_n_0
|
|
SLICE_X44Y50 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[5]_i_1__0/I3
|
|
SLICE_X44Y50 LUT6 (Prop_lut6_I3_O) 0.124 8.877 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[5]_i_1__0/O
|
|
net (fo=6, routed) 0.845 9.722 u_cpu/u_csr/ms_to_ws_bus[13]
|
|
SLICE_X50Y46 r u_cpu/u_csr/write_buffer_way[1]_i_18/I3
|
|
SLICE_X50Y46 LUT6 (Prop_lut6_I3_O) 0.124 9.846 f u_cpu/u_csr/write_buffer_way[1]_i_18/O
|
|
net (fo=1, routed) 0.000 9.846 u_cpu/u_csr/write_buffer_way[1]_i_18_n_0
|
|
SLICE_X50Y46 f u_cpu/u_csr/write_buffer_way_reg[1]_i_11/S[0]
|
|
SLICE_X50Y46 CARRY4 (Prop_carry4_S[0]_CO[3])
|
|
0.532 10.378 r u_cpu/u_csr/write_buffer_way_reg[1]_i_11/CO[3]
|
|
net (fo=1, routed) 0.000 10.378 u_cpu/u_csr/write_buffer_way_reg[1]_i_11_n_0
|
|
SLICE_X50Y47 r u_cpu/u_csr/write_buffer_way_reg[1]_i_9/CI
|
|
SLICE_X50Y47 CARRY4 (Prop_carry4_CI_CO[1])
|
|
0.157 10.535 f u_cpu/u_csr/write_buffer_way_reg[1]_i_9/CO[1]
|
|
net (fo=2, routed) 0.791 11.326 u_cpu/wb_stage/CO[0]
|
|
SLICE_X46Y39 f u_cpu/wb_stage/write_buffer_way[1]_i_5/I1
|
|
SLICE_X46Y39 LUT6 (Prop_lut6_I1_O) 0.329 11.655 r u_cpu/wb_stage/write_buffer_way[1]_i_5/O
|
|
net (fo=7, routed) 0.762 12.417 u_cpu/addr_trans/tlb_entry/sc_cancel_req
|
|
SLICE_X46Y35 r u_cpu/addr_trans/tlb_entry/main_state[0]_i_3/I1
|
|
SLICE_X46Y35 LUT3 (Prop_lut3_I1_O) 0.124 12.541 r u_cpu/addr_trans/tlb_entry/main_state[0]_i_3/O
|
|
net (fo=3, routed) 0.719 13.260 u_cpu/dcache/main_state_reg[0]_2
|
|
SLICE_X43Y31 r u_cpu/dcache/ds_to_es_bus_r[235]_i_10/I3
|
|
SLICE_X43Y31 LUT6 (Prop_lut6_I3_O) 0.124 13.384 r u_cpu/dcache/ds_to_es_bus_r[235]_i_10/O
|
|
net (fo=3, routed) 0.415 13.799 u_cpu/mem_stage/data_data_ok
|
|
SLICE_X43Y30 r u_cpu/mem_stage/flush_inst_req_buffer[1]_i_15/I0
|
|
SLICE_X43Y30 LUT3 (Prop_lut3_I0_O) 0.124 13.923 r u_cpu/mem_stage/flush_inst_req_buffer[1]_i_15/O
|
|
net (fo=2, routed) 0.833 14.756 u_cpu/mem_stage/es_to_ms_bus_r_reg[70]_1
|
|
SLICE_X48Y30 r u_cpu/mem_stage/flush_inst_req_buffer[1]_i_14/I0
|
|
SLICE_X48Y30 LUT6 (Prop_lut6_I0_O) 0.124 14.880 r u_cpu/mem_stage/flush_inst_req_buffer[1]_i_14/O
|
|
net (fo=1, routed) 0.651 15.532 u_cpu/mem_stage/ms_ready_go
|
|
SLICE_X48Y25 r u_cpu/mem_stage/flush_inst_req_buffer[1]_i_13/I4
|
|
SLICE_X48Y25 LUT6 (Prop_lut6_I4_O) 0.124 15.656 r u_cpu/mem_stage/flush_inst_req_buffer[1]_i_13/O
|
|
net (fo=3, routed) 0.483 16.139 u_cpu/id_stage/flush_inst_req_buffer[31]_i_6
|
|
SLICE_X50Y25 r u_cpu/id_stage/flush_inst_req_buffer[1]_i_9/I1
|
|
SLICE_X50Y25 LUT6 (Prop_lut6_I1_O) 0.124 16.263 r u_cpu/id_stage/flush_inst_req_buffer[1]_i_9/O
|
|
net (fo=32, routed) 0.531 16.794 u_cpu/if_stage/nextpc5
|
|
SLICE_X51Y27 r u_cpu/if_stage/fetch_pc_r[6]_i_4/I2
|
|
SLICE_X51Y27 LUT6 (Prop_lut6_I2_O) 0.124 16.918 r u_cpu/if_stage/fetch_pc_r[6]_i_4/O
|
|
net (fo=1, routed) 3.059 19.977 u_cpu/if_stage/fetch_pc_r[6]_i_4_n_0
|
|
SLICE_X114Y28 r u_cpu/if_stage/fetch_pc_r[6]_i_2/I2
|
|
SLICE_X114Y28 LUT6 (Prop_lut6_I2_O) 0.124 20.101 r u_cpu/if_stage/fetch_pc_r[6]_i_2/O
|
|
net (fo=1, routed) 0.441 20.542 u_cpu/if_stage/fetch_pc_r[6]_i_2_n_0
|
|
SLICE_X114Y25 r u_cpu/if_stage/fetch_pc_r[6]_i_1/I2
|
|
SLICE_X114Y25 LUT6 (Prop_lut6_I2_O) 0.124 20.666 r u_cpu/if_stage/fetch_pc_r[6]_i_1/O
|
|
net (fo=6, routed) 3.249 23.915 u_cpu/icache/tagv_ram_way[1].u/mem_reg_reg_2[2]
|
|
SLICE_X49Y33 r u_cpu/icache/tagv_ram_way[1].u/mem_reg_reg_i_8/I4
|
|
SLICE_X49Y33 LUT5 (Prop_lut5_I4_O) 0.124 24.039 r u_cpu/icache/tagv_ram_way[1].u/mem_reg_reg_i_8/O
|
|
net (fo=16, routed) 1.477 25.516 u_cpu/icache/data_ram_way[0].data_ram_bank[2].u/ADDRBWRADDR[2]
|
|
RAMB18_X2Y2 RAMB18E1 r u_cpu/icache/data_ram_way[0].data_ram_bank[2].u/mem_reg_reg/ADDRARDADDR[7]
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock cpu_clk rise edge) 30.323 30.323 r
|
|
clock source latency -5.674 24.648
|
|
propagated clock network latency
|
|
3.781 28.429
|
|
clock pessimism -0.418 28.011
|
|
clock uncertainty -0.074 27.937
|
|
RAMB18_X2Y2 RAMB18E1 (Setup_ramb18e1_CLKARDCLK_ADDRARDADDR[7])
|
|
-0.566 27.371 u_cpu/icache/data_ram_way[0].data_ram_bank[2].u/mem_reg_reg
|
|
-------------------------------------------------------------------
|
|
required time 27.371
|
|
arrival time -25.516
|
|
-------------------------------------------------------------------
|
|
slack 1.855
|
|
|
|
Slack (MET) : 1.855ns (required time - arrival time)
|
|
Source: u_cpu/addr_trans/data_vaddr_buffer_reg[14]/C
|
|
(rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns})
|
|
Destination: u_cpu/icache/data_ram_way[0].data_ram_bank[2].u/mem_reg_reg/ADDRARDADDR[7]
|
|
(rising edge-triggered cell RAMB18E1 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns})
|
|
Path Group: cpu_clk
|
|
Path Type: Setup (Max at Slow Process Corner)
|
|
Requirement: 30.323ns (cpu_clk rise@30.323ns - cpu_clk rise@0.000ns)
|
|
Data Path Delay: 27.741ns (logic 5.333ns (19.224%) route 22.408ns (80.776%))
|
|
Logic Levels: 26 (CARRY4=4 LUT3=2 LUT4=1 LUT5=2 LUT6=15 MUXF7=1 MUXF8=1)
|
|
Clock Path Skew: -0.087ns (DCD - SCD + CPR)
|
|
Destination Clock Delay (DCD): -1.893ns = ( 28.429 - 30.323 )
|
|
Source Clock Delay (SCD): -2.225ns
|
|
Clock Pessimism Removal (CPR): -0.418ns
|
|
Clock Uncertainty: 0.074ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Discrete Jitter (DJ): 0.130ns
|
|
Phase Error (PE): 0.000ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock cpu_clk rise edge) 0.000 0.000 r
|
|
clock source latency -6.275 -6.275
|
|
propagated clock network latency
|
|
4.051 -2.225
|
|
SLICE_X35Y35 FDRE 0.000 -2.225 r u_cpu/addr_trans/data_vaddr_buffer_reg[14]/C
|
|
SLICE_X35Y35 FDRE (Prop_fdre_C_Q) 0.456 -1.769 r u_cpu/addr_trans/data_vaddr_buffer_reg[14]/Q
|
|
net (fo=33, routed) 1.442 -0.326 u_cpu/addr_trans/tlb_entry/data_vaddr_buffer[2]
|
|
SLICE_X42Y40 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_226/I5
|
|
SLICE_X42Y40 LUT6 (Prop_lut6_I5_O) 0.124 -0.202 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_226/O
|
|
net (fo=1, routed) 0.000 -0.202 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_226_n_0
|
|
SLICE_X42Y40 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_111/S[0]
|
|
SLICE_X42Y40 CARRY4 (Prop_carry4_S[0]_CO[3])
|
|
0.513 0.311 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_111/CO[3]
|
|
net (fo=1, routed) 0.000 0.311 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_111_n_0
|
|
SLICE_X42Y41 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_32/CI
|
|
SLICE_X42Y41 CARRY4 (Prop_carry4_CI_CO[2])
|
|
0.229 0.540 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_32/CO[2]
|
|
net (fo=1, routed) 1.009 1.549 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_32_n_1
|
|
SLICE_X40Y47 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_9/I1
|
|
SLICE_X40Y47 LUT6 (Prop_lut6_I1_O) 0.310 1.859 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_9/O
|
|
net (fo=2, routed) 0.635 2.494 u_cpu/addr_trans/tlb_entry/match1[28]
|
|
SLICE_X38Y47 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/I2
|
|
SLICE_X38Y47 LUT4 (Prop_lut4_I2_O) 0.124 2.618 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/O
|
|
net (fo=2, routed) 0.667 3.285 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2_n_0
|
|
SLICE_X39Y47 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/I0
|
|
SLICE_X39Y47 LUT5 (Prop_lut5_I0_O) 0.124 3.409 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/O
|
|
net (fo=2, routed) 1.103 4.512 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2_n_0
|
|
SLICE_X38Y50 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/I0
|
|
SLICE_X38Y50 LUT6 (Prop_lut6_I0_O) 0.124 4.636 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/O
|
|
net (fo=89, routed) 1.162 5.797 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus[8]
|
|
SLICE_X42Y51 r u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_38__0/S
|
|
SLICE_X42Y51 MUXF7 (Prop_muxf7_S_O) 0.292 6.089 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_38__0/O
|
|
net (fo=1, routed) 0.000 6.089 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_38__0_n_0
|
|
SLICE_X42Y51 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_16__0/I1
|
|
SLICE_X42Y51 MUXF8 (Prop_muxf8_I1_O) 0.088 6.177 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_16__0/O
|
|
net (fo=1, routed) 0.957 7.134 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_16__0_n_0
|
|
SLICE_X42Y50 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7/I0
|
|
SLICE_X42Y50 LUT6 (Prop_lut6_I0_O) 0.319 7.453 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7/O
|
|
net (fo=1, routed) 0.435 7.888 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7_n_0
|
|
SLICE_X44Y50 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0/I5
|
|
SLICE_X44Y50 LUT6 (Prop_lut6_I5_O) 0.124 8.012 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0/O
|
|
net (fo=10, routed) 0.740 8.753 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0_n_0
|
|
SLICE_X44Y50 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[5]_i_1__0/I3
|
|
SLICE_X44Y50 LUT6 (Prop_lut6_I3_O) 0.124 8.877 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[5]_i_1__0/O
|
|
net (fo=6, routed) 0.845 9.722 u_cpu/u_csr/ms_to_ws_bus[13]
|
|
SLICE_X50Y46 f u_cpu/u_csr/write_buffer_way[1]_i_18/I3
|
|
SLICE_X50Y46 LUT6 (Prop_lut6_I3_O) 0.124 9.846 f u_cpu/u_csr/write_buffer_way[1]_i_18/O
|
|
net (fo=1, routed) 0.000 9.846 u_cpu/u_csr/write_buffer_way[1]_i_18_n_0
|
|
SLICE_X50Y46 f u_cpu/u_csr/write_buffer_way_reg[1]_i_11/S[0]
|
|
SLICE_X50Y46 CARRY4 (Prop_carry4_S[0]_CO[3])
|
|
0.532 10.378 r u_cpu/u_csr/write_buffer_way_reg[1]_i_11/CO[3]
|
|
net (fo=1, routed) 0.000 10.378 u_cpu/u_csr/write_buffer_way_reg[1]_i_11_n_0
|
|
SLICE_X50Y47 r u_cpu/u_csr/write_buffer_way_reg[1]_i_9/CI
|
|
SLICE_X50Y47 CARRY4 (Prop_carry4_CI_CO[1])
|
|
0.157 10.535 f u_cpu/u_csr/write_buffer_way_reg[1]_i_9/CO[1]
|
|
net (fo=2, routed) 0.791 11.326 u_cpu/wb_stage/CO[0]
|
|
SLICE_X46Y39 f u_cpu/wb_stage/write_buffer_way[1]_i_5/I1
|
|
SLICE_X46Y39 LUT6 (Prop_lut6_I1_O) 0.329 11.655 r u_cpu/wb_stage/write_buffer_way[1]_i_5/O
|
|
net (fo=7, routed) 0.762 12.417 u_cpu/addr_trans/tlb_entry/sc_cancel_req
|
|
SLICE_X46Y35 r u_cpu/addr_trans/tlb_entry/main_state[0]_i_3/I1
|
|
SLICE_X46Y35 LUT3 (Prop_lut3_I1_O) 0.124 12.541 r u_cpu/addr_trans/tlb_entry/main_state[0]_i_3/O
|
|
net (fo=3, routed) 0.719 13.260 u_cpu/dcache/main_state_reg[0]_2
|
|
SLICE_X43Y31 r u_cpu/dcache/ds_to_es_bus_r[235]_i_10/I3
|
|
SLICE_X43Y31 LUT6 (Prop_lut6_I3_O) 0.124 13.384 r u_cpu/dcache/ds_to_es_bus_r[235]_i_10/O
|
|
net (fo=3, routed) 0.415 13.799 u_cpu/mem_stage/data_data_ok
|
|
SLICE_X43Y30 r u_cpu/mem_stage/flush_inst_req_buffer[1]_i_15/I0
|
|
SLICE_X43Y30 LUT3 (Prop_lut3_I0_O) 0.124 13.923 r u_cpu/mem_stage/flush_inst_req_buffer[1]_i_15/O
|
|
net (fo=2, routed) 0.833 14.756 u_cpu/mem_stage/es_to_ms_bus_r_reg[70]_1
|
|
SLICE_X48Y30 r u_cpu/mem_stage/flush_inst_req_buffer[1]_i_14/I0
|
|
SLICE_X48Y30 LUT6 (Prop_lut6_I0_O) 0.124 14.880 r u_cpu/mem_stage/flush_inst_req_buffer[1]_i_14/O
|
|
net (fo=1, routed) 0.651 15.532 u_cpu/mem_stage/ms_ready_go
|
|
SLICE_X48Y25 r u_cpu/mem_stage/flush_inst_req_buffer[1]_i_13/I4
|
|
SLICE_X48Y25 LUT6 (Prop_lut6_I4_O) 0.124 15.656 r u_cpu/mem_stage/flush_inst_req_buffer[1]_i_13/O
|
|
net (fo=3, routed) 0.483 16.139 u_cpu/id_stage/flush_inst_req_buffer[31]_i_6
|
|
SLICE_X50Y25 r u_cpu/id_stage/flush_inst_req_buffer[1]_i_9/I1
|
|
SLICE_X50Y25 LUT6 (Prop_lut6_I1_O) 0.124 16.263 r u_cpu/id_stage/flush_inst_req_buffer[1]_i_9/O
|
|
net (fo=32, routed) 0.531 16.794 u_cpu/if_stage/nextpc5
|
|
SLICE_X51Y27 r u_cpu/if_stage/fetch_pc_r[6]_i_4/I2
|
|
SLICE_X51Y27 LUT6 (Prop_lut6_I2_O) 0.124 16.918 r u_cpu/if_stage/fetch_pc_r[6]_i_4/O
|
|
net (fo=1, routed) 3.059 19.977 u_cpu/if_stage/fetch_pc_r[6]_i_4_n_0
|
|
SLICE_X114Y28 r u_cpu/if_stage/fetch_pc_r[6]_i_2/I2
|
|
SLICE_X114Y28 LUT6 (Prop_lut6_I2_O) 0.124 20.101 r u_cpu/if_stage/fetch_pc_r[6]_i_2/O
|
|
net (fo=1, routed) 0.441 20.542 u_cpu/if_stage/fetch_pc_r[6]_i_2_n_0
|
|
SLICE_X114Y25 r u_cpu/if_stage/fetch_pc_r[6]_i_1/I2
|
|
SLICE_X114Y25 LUT6 (Prop_lut6_I2_O) 0.124 20.666 r u_cpu/if_stage/fetch_pc_r[6]_i_1/O
|
|
net (fo=6, routed) 3.249 23.915 u_cpu/icache/tagv_ram_way[1].u/mem_reg_reg_2[2]
|
|
SLICE_X49Y33 r u_cpu/icache/tagv_ram_way[1].u/mem_reg_reg_i_8/I4
|
|
SLICE_X49Y33 LUT5 (Prop_lut5_I4_O) 0.124 24.039 r u_cpu/icache/tagv_ram_way[1].u/mem_reg_reg_i_8/O
|
|
net (fo=16, routed) 1.477 25.516 u_cpu/icache/data_ram_way[0].data_ram_bank[2].u/ADDRBWRADDR[2]
|
|
RAMB18_X2Y2 RAMB18E1 r u_cpu/icache/data_ram_way[0].data_ram_bank[2].u/mem_reg_reg/ADDRARDADDR[7]
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock cpu_clk rise edge) 30.323 30.323 r
|
|
clock source latency -5.674 24.648
|
|
propagated clock network latency
|
|
3.781 28.429
|
|
clock pessimism -0.418 28.011
|
|
clock uncertainty -0.074 27.937
|
|
RAMB18_X2Y2 RAMB18E1 (Setup_ramb18e1_CLKARDCLK_ADDRARDADDR[7])
|
|
-0.566 27.371 u_cpu/icache/data_ram_way[0].data_ram_bank[2].u/mem_reg_reg
|
|
-------------------------------------------------------------------
|
|
required time 27.371
|
|
arrival time -25.516
|
|
-------------------------------------------------------------------
|
|
slack 1.855
|
|
|
|
Slack (MET) : 1.855ns (required time - arrival time)
|
|
Source: u_cpu/addr_trans/data_vaddr_buffer_reg[14]/C
|
|
(rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns})
|
|
Destination: u_cpu/icache/data_ram_way[0].data_ram_bank[2].u/mem_reg_reg/ADDRARDADDR[7]
|
|
(rising edge-triggered cell RAMB18E1 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns})
|
|
Path Group: cpu_clk
|
|
Path Type: Setup (Max at Slow Process Corner)
|
|
Requirement: 30.323ns (cpu_clk rise@30.323ns - cpu_clk rise@0.000ns)
|
|
Data Path Delay: 27.741ns (logic 5.333ns (19.224%) route 22.408ns (80.776%))
|
|
Logic Levels: 26 (CARRY4=4 LUT3=2 LUT4=1 LUT5=2 LUT6=15 MUXF7=1 MUXF8=1)
|
|
Clock Path Skew: -0.087ns (DCD - SCD + CPR)
|
|
Destination Clock Delay (DCD): -1.893ns = ( 28.429 - 30.323 )
|
|
Source Clock Delay (SCD): -2.225ns
|
|
Clock Pessimism Removal (CPR): -0.418ns
|
|
Clock Uncertainty: 0.074ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Discrete Jitter (DJ): 0.130ns
|
|
Phase Error (PE): 0.000ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock cpu_clk rise edge) 0.000 0.000 r
|
|
clock source latency -6.275 -6.275
|
|
propagated clock network latency
|
|
4.051 -2.225
|
|
SLICE_X35Y35 FDRE 0.000 -2.225 r u_cpu/addr_trans/data_vaddr_buffer_reg[14]/C
|
|
SLICE_X35Y35 FDRE (Prop_fdre_C_Q) 0.456 -1.769 r u_cpu/addr_trans/data_vaddr_buffer_reg[14]/Q
|
|
net (fo=33, routed) 1.442 -0.326 u_cpu/addr_trans/tlb_entry/data_vaddr_buffer[2]
|
|
SLICE_X42Y40 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_226/I5
|
|
SLICE_X42Y40 LUT6 (Prop_lut6_I5_O) 0.124 -0.202 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_226/O
|
|
net (fo=1, routed) 0.000 -0.202 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_226_n_0
|
|
SLICE_X42Y40 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_111/S[0]
|
|
SLICE_X42Y40 CARRY4 (Prop_carry4_S[0]_CO[3])
|
|
0.513 0.311 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_111/CO[3]
|
|
net (fo=1, routed) 0.000 0.311 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_111_n_0
|
|
SLICE_X42Y41 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_32/CI
|
|
SLICE_X42Y41 CARRY4 (Prop_carry4_CI_CO[2])
|
|
0.229 0.540 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_32/CO[2]
|
|
net (fo=1, routed) 1.009 1.549 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_32_n_1
|
|
SLICE_X40Y47 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_9/I1
|
|
SLICE_X40Y47 LUT6 (Prop_lut6_I1_O) 0.310 1.859 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_9/O
|
|
net (fo=2, routed) 0.635 2.494 u_cpu/addr_trans/tlb_entry/match1[28]
|
|
SLICE_X38Y47 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/I2
|
|
SLICE_X38Y47 LUT4 (Prop_lut4_I2_O) 0.124 2.618 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/O
|
|
net (fo=2, routed) 0.667 3.285 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2_n_0
|
|
SLICE_X39Y47 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/I0
|
|
SLICE_X39Y47 LUT5 (Prop_lut5_I0_O) 0.124 3.409 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/O
|
|
net (fo=2, routed) 1.103 4.512 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2_n_0
|
|
SLICE_X38Y50 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/I0
|
|
SLICE_X38Y50 LUT6 (Prop_lut6_I0_O) 0.124 4.636 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/O
|
|
net (fo=89, routed) 1.162 5.797 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus[8]
|
|
SLICE_X42Y51 r u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_38__0/S
|
|
SLICE_X42Y51 MUXF7 (Prop_muxf7_S_O) 0.292 6.089 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_38__0/O
|
|
net (fo=1, routed) 0.000 6.089 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_38__0_n_0
|
|
SLICE_X42Y51 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_16__0/I1
|
|
SLICE_X42Y51 MUXF8 (Prop_muxf8_I1_O) 0.088 6.177 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_16__0/O
|
|
net (fo=1, routed) 0.957 7.134 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_16__0_n_0
|
|
SLICE_X42Y50 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7/I0
|
|
SLICE_X42Y50 LUT6 (Prop_lut6_I0_O) 0.319 7.453 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7/O
|
|
net (fo=1, routed) 0.435 7.888 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7_n_0
|
|
SLICE_X44Y50 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0/I5
|
|
SLICE_X44Y50 LUT6 (Prop_lut6_I5_O) 0.124 8.012 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0/O
|
|
net (fo=10, routed) 0.740 8.753 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0_n_0
|
|
SLICE_X44Y50 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[5]_i_1__0/I3
|
|
SLICE_X44Y50 LUT6 (Prop_lut6_I3_O) 0.124 8.877 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[5]_i_1__0/O
|
|
net (fo=6, routed) 0.845 9.722 u_cpu/u_csr/ms_to_ws_bus[13]
|
|
SLICE_X50Y46 r u_cpu/u_csr/write_buffer_way[1]_i_18/I3
|
|
SLICE_X50Y46 LUT6 (Prop_lut6_I3_O) 0.124 9.846 r u_cpu/u_csr/write_buffer_way[1]_i_18/O
|
|
net (fo=1, routed) 0.000 9.846 u_cpu/u_csr/write_buffer_way[1]_i_18_n_0
|
|
SLICE_X50Y46 r u_cpu/u_csr/write_buffer_way_reg[1]_i_11/S[0]
|
|
SLICE_X50Y46 CARRY4 (Prop_carry4_S[0]_CO[3])
|
|
0.532 10.378 f u_cpu/u_csr/write_buffer_way_reg[1]_i_11/CO[3]
|
|
net (fo=1, routed) 0.000 10.378 u_cpu/u_csr/write_buffer_way_reg[1]_i_11_n_0
|
|
SLICE_X50Y47 f u_cpu/u_csr/write_buffer_way_reg[1]_i_9/CI
|
|
SLICE_X50Y47 CARRY4 (Prop_carry4_CI_CO[1])
|
|
0.157 10.535 f u_cpu/u_csr/write_buffer_way_reg[1]_i_9/CO[1]
|
|
net (fo=2, routed) 0.791 11.326 u_cpu/wb_stage/CO[0]
|
|
SLICE_X46Y39 f u_cpu/wb_stage/write_buffer_way[1]_i_5/I1
|
|
SLICE_X46Y39 LUT6 (Prop_lut6_I1_O) 0.329 11.655 r u_cpu/wb_stage/write_buffer_way[1]_i_5/O
|
|
net (fo=7, routed) 0.762 12.417 u_cpu/addr_trans/tlb_entry/sc_cancel_req
|
|
SLICE_X46Y35 r u_cpu/addr_trans/tlb_entry/main_state[0]_i_3/I1
|
|
SLICE_X46Y35 LUT3 (Prop_lut3_I1_O) 0.124 12.541 r u_cpu/addr_trans/tlb_entry/main_state[0]_i_3/O
|
|
net (fo=3, routed) 0.719 13.260 u_cpu/dcache/main_state_reg[0]_2
|
|
SLICE_X43Y31 r u_cpu/dcache/ds_to_es_bus_r[235]_i_10/I3
|
|
SLICE_X43Y31 LUT6 (Prop_lut6_I3_O) 0.124 13.384 r u_cpu/dcache/ds_to_es_bus_r[235]_i_10/O
|
|
net (fo=3, routed) 0.415 13.799 u_cpu/mem_stage/data_data_ok
|
|
SLICE_X43Y30 r u_cpu/mem_stage/flush_inst_req_buffer[1]_i_15/I0
|
|
SLICE_X43Y30 LUT3 (Prop_lut3_I0_O) 0.124 13.923 r u_cpu/mem_stage/flush_inst_req_buffer[1]_i_15/O
|
|
net (fo=2, routed) 0.833 14.756 u_cpu/mem_stage/es_to_ms_bus_r_reg[70]_1
|
|
SLICE_X48Y30 r u_cpu/mem_stage/flush_inst_req_buffer[1]_i_14/I0
|
|
SLICE_X48Y30 LUT6 (Prop_lut6_I0_O) 0.124 14.880 r u_cpu/mem_stage/flush_inst_req_buffer[1]_i_14/O
|
|
net (fo=1, routed) 0.651 15.532 u_cpu/mem_stage/ms_ready_go
|
|
SLICE_X48Y25 r u_cpu/mem_stage/flush_inst_req_buffer[1]_i_13/I4
|
|
SLICE_X48Y25 LUT6 (Prop_lut6_I4_O) 0.124 15.656 r u_cpu/mem_stage/flush_inst_req_buffer[1]_i_13/O
|
|
net (fo=3, routed) 0.483 16.139 u_cpu/id_stage/flush_inst_req_buffer[31]_i_6
|
|
SLICE_X50Y25 r u_cpu/id_stage/flush_inst_req_buffer[1]_i_9/I1
|
|
SLICE_X50Y25 LUT6 (Prop_lut6_I1_O) 0.124 16.263 r u_cpu/id_stage/flush_inst_req_buffer[1]_i_9/O
|
|
net (fo=32, routed) 0.531 16.794 u_cpu/if_stage/nextpc5
|
|
SLICE_X51Y27 r u_cpu/if_stage/fetch_pc_r[6]_i_4/I2
|
|
SLICE_X51Y27 LUT6 (Prop_lut6_I2_O) 0.124 16.918 r u_cpu/if_stage/fetch_pc_r[6]_i_4/O
|
|
net (fo=1, routed) 3.059 19.977 u_cpu/if_stage/fetch_pc_r[6]_i_4_n_0
|
|
SLICE_X114Y28 r u_cpu/if_stage/fetch_pc_r[6]_i_2/I2
|
|
SLICE_X114Y28 LUT6 (Prop_lut6_I2_O) 0.124 20.101 r u_cpu/if_stage/fetch_pc_r[6]_i_2/O
|
|
net (fo=1, routed) 0.441 20.542 u_cpu/if_stage/fetch_pc_r[6]_i_2_n_0
|
|
SLICE_X114Y25 r u_cpu/if_stage/fetch_pc_r[6]_i_1/I2
|
|
SLICE_X114Y25 LUT6 (Prop_lut6_I2_O) 0.124 20.666 r u_cpu/if_stage/fetch_pc_r[6]_i_1/O
|
|
net (fo=6, routed) 3.249 23.915 u_cpu/icache/tagv_ram_way[1].u/mem_reg_reg_2[2]
|
|
SLICE_X49Y33 r u_cpu/icache/tagv_ram_way[1].u/mem_reg_reg_i_8/I4
|
|
SLICE_X49Y33 LUT5 (Prop_lut5_I4_O) 0.124 24.039 r u_cpu/icache/tagv_ram_way[1].u/mem_reg_reg_i_8/O
|
|
net (fo=16, routed) 1.477 25.516 u_cpu/icache/data_ram_way[0].data_ram_bank[2].u/ADDRBWRADDR[2]
|
|
RAMB18_X2Y2 RAMB18E1 r u_cpu/icache/data_ram_way[0].data_ram_bank[2].u/mem_reg_reg/ADDRARDADDR[7]
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock cpu_clk rise edge) 30.323 30.323 r
|
|
clock source latency -5.674 24.648
|
|
propagated clock network latency
|
|
3.781 28.429
|
|
clock pessimism -0.418 28.011
|
|
clock uncertainty -0.074 27.937
|
|
RAMB18_X2Y2 RAMB18E1 (Setup_ramb18e1_CLKARDCLK_ADDRARDADDR[7])
|
|
-0.566 27.371 u_cpu/icache/data_ram_way[0].data_ram_bank[2].u/mem_reg_reg
|
|
-------------------------------------------------------------------
|
|
required time 27.371
|
|
arrival time -25.516
|
|
-------------------------------------------------------------------
|
|
slack 1.855
|
|
|
|
Slack (MET) : 1.855ns (required time - arrival time)
|
|
Source: u_cpu/addr_trans/data_vaddr_buffer_reg[14]/C
|
|
(rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns})
|
|
Destination: u_cpu/icache/data_ram_way[0].data_ram_bank[2].u/mem_reg_reg/ADDRARDADDR[7]
|
|
(rising edge-triggered cell RAMB18E1 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns})
|
|
Path Group: cpu_clk
|
|
Path Type: Setup (Max at Slow Process Corner)
|
|
Requirement: 30.323ns (cpu_clk rise@30.323ns - cpu_clk rise@0.000ns)
|
|
Data Path Delay: 27.741ns (logic 5.333ns (19.224%) route 22.408ns (80.776%))
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|
Logic Levels: 26 (CARRY4=4 LUT3=2 LUT4=1 LUT5=2 LUT6=15 MUXF7=1 MUXF8=1)
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|
Clock Path Skew: -0.087ns (DCD - SCD + CPR)
|
|
Destination Clock Delay (DCD): -1.893ns = ( 28.429 - 30.323 )
|
|
Source Clock Delay (SCD): -2.225ns
|
|
Clock Pessimism Removal (CPR): -0.418ns
|
|
Clock Uncertainty: 0.074ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Discrete Jitter (DJ): 0.130ns
|
|
Phase Error (PE): 0.000ns
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|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
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|
------------------------------------------------------------------- -------------------
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|
(clock cpu_clk rise edge) 0.000 0.000 r
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|
clock source latency -6.275 -6.275
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|
propagated clock network latency
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|
4.051 -2.225
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SLICE_X35Y35 FDRE 0.000 -2.225 r u_cpu/addr_trans/data_vaddr_buffer_reg[14]/C
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SLICE_X35Y35 FDRE (Prop_fdre_C_Q) 0.456 -1.769 r u_cpu/addr_trans/data_vaddr_buffer_reg[14]/Q
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|
net (fo=33, routed) 1.442 -0.326 u_cpu/addr_trans/tlb_entry/data_vaddr_buffer[2]
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SLICE_X42Y40 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_226/I5
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SLICE_X42Y40 LUT6 (Prop_lut6_I5_O) 0.124 -0.202 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_226/O
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net (fo=1, routed) 0.000 -0.202 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_226_n_0
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SLICE_X42Y40 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_111/S[0]
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SLICE_X42Y40 CARRY4 (Prop_carry4_S[0]_CO[3])
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0.513 0.311 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_111/CO[3]
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net (fo=1, routed) 0.000 0.311 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_111_n_0
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SLICE_X42Y41 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_32/CI
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SLICE_X42Y41 CARRY4 (Prop_carry4_CI_CO[2])
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0.229 0.540 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_32/CO[2]
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net (fo=1, routed) 1.009 1.549 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_32_n_1
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SLICE_X40Y47 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_9/I1
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SLICE_X40Y47 LUT6 (Prop_lut6_I1_O) 0.310 1.859 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_9/O
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net (fo=2, routed) 0.635 2.494 u_cpu/addr_trans/tlb_entry/match1[28]
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SLICE_X38Y47 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/I2
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SLICE_X38Y47 LUT4 (Prop_lut4_I2_O) 0.124 2.618 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/O
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net (fo=2, routed) 0.667 3.285 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2_n_0
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SLICE_X39Y47 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/I0
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SLICE_X39Y47 LUT5 (Prop_lut5_I0_O) 0.124 3.409 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/O
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|
net (fo=2, routed) 1.103 4.512 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2_n_0
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|
SLICE_X38Y50 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/I0
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|
SLICE_X38Y50 LUT6 (Prop_lut6_I0_O) 0.124 4.636 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/O
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|
net (fo=89, routed) 1.162 5.797 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus[8]
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|
SLICE_X42Y51 r u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_38__0/S
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|
SLICE_X42Y51 MUXF7 (Prop_muxf7_S_O) 0.292 6.089 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_38__0/O
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net (fo=1, routed) 0.000 6.089 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_38__0_n_0
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SLICE_X42Y51 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_16__0/I1
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SLICE_X42Y51 MUXF8 (Prop_muxf8_I1_O) 0.088 6.177 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_16__0/O
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net (fo=1, routed) 0.957 7.134 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_16__0_n_0
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|
SLICE_X42Y50 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7/I0
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SLICE_X42Y50 LUT6 (Prop_lut6_I0_O) 0.319 7.453 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7/O
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net (fo=1, routed) 0.435 7.888 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7_n_0
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|
SLICE_X44Y50 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0/I5
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|
SLICE_X44Y50 LUT6 (Prop_lut6_I5_O) 0.124 8.012 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0/O
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net (fo=10, routed) 0.740 8.753 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0_n_0
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|
SLICE_X44Y50 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[5]_i_1__0/I3
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|
SLICE_X44Y50 LUT6 (Prop_lut6_I3_O) 0.124 8.877 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[5]_i_1__0/O
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|
net (fo=6, routed) 0.845 9.722 u_cpu/u_csr/ms_to_ws_bus[13]
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|
SLICE_X50Y46 f u_cpu/u_csr/write_buffer_way[1]_i_18/I3
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SLICE_X50Y46 LUT6 (Prop_lut6_I3_O) 0.124 9.846 r u_cpu/u_csr/write_buffer_way[1]_i_18/O
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|
net (fo=1, routed) 0.000 9.846 u_cpu/u_csr/write_buffer_way[1]_i_18_n_0
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SLICE_X50Y46 r u_cpu/u_csr/write_buffer_way_reg[1]_i_11/S[0]
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SLICE_X50Y46 CARRY4 (Prop_carry4_S[0]_CO[3])
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0.532 10.378 f u_cpu/u_csr/write_buffer_way_reg[1]_i_11/CO[3]
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|
net (fo=1, routed) 0.000 10.378 u_cpu/u_csr/write_buffer_way_reg[1]_i_11_n_0
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|
SLICE_X50Y47 f u_cpu/u_csr/write_buffer_way_reg[1]_i_9/CI
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|
SLICE_X50Y47 CARRY4 (Prop_carry4_CI_CO[1])
|
|
0.157 10.535 f u_cpu/u_csr/write_buffer_way_reg[1]_i_9/CO[1]
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net (fo=2, routed) 0.791 11.326 u_cpu/wb_stage/CO[0]
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|
SLICE_X46Y39 f u_cpu/wb_stage/write_buffer_way[1]_i_5/I1
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SLICE_X46Y39 LUT6 (Prop_lut6_I1_O) 0.329 11.655 r u_cpu/wb_stage/write_buffer_way[1]_i_5/O
|
|
net (fo=7, routed) 0.762 12.417 u_cpu/addr_trans/tlb_entry/sc_cancel_req
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SLICE_X46Y35 r u_cpu/addr_trans/tlb_entry/main_state[0]_i_3/I1
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|
SLICE_X46Y35 LUT3 (Prop_lut3_I1_O) 0.124 12.541 r u_cpu/addr_trans/tlb_entry/main_state[0]_i_3/O
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|
net (fo=3, routed) 0.719 13.260 u_cpu/dcache/main_state_reg[0]_2
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|
SLICE_X43Y31 r u_cpu/dcache/ds_to_es_bus_r[235]_i_10/I3
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|
SLICE_X43Y31 LUT6 (Prop_lut6_I3_O) 0.124 13.384 r u_cpu/dcache/ds_to_es_bus_r[235]_i_10/O
|
|
net (fo=3, routed) 0.415 13.799 u_cpu/mem_stage/data_data_ok
|
|
SLICE_X43Y30 r u_cpu/mem_stage/flush_inst_req_buffer[1]_i_15/I0
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|
SLICE_X43Y30 LUT3 (Prop_lut3_I0_O) 0.124 13.923 r u_cpu/mem_stage/flush_inst_req_buffer[1]_i_15/O
|
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net (fo=2, routed) 0.833 14.756 u_cpu/mem_stage/es_to_ms_bus_r_reg[70]_1
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SLICE_X48Y30 r u_cpu/mem_stage/flush_inst_req_buffer[1]_i_14/I0
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SLICE_X48Y30 LUT6 (Prop_lut6_I0_O) 0.124 14.880 r u_cpu/mem_stage/flush_inst_req_buffer[1]_i_14/O
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net (fo=1, routed) 0.651 15.532 u_cpu/mem_stage/ms_ready_go
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|
SLICE_X48Y25 r u_cpu/mem_stage/flush_inst_req_buffer[1]_i_13/I4
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SLICE_X48Y25 LUT6 (Prop_lut6_I4_O) 0.124 15.656 r u_cpu/mem_stage/flush_inst_req_buffer[1]_i_13/O
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net (fo=3, routed) 0.483 16.139 u_cpu/id_stage/flush_inst_req_buffer[31]_i_6
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|
SLICE_X50Y25 r u_cpu/id_stage/flush_inst_req_buffer[1]_i_9/I1
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|
SLICE_X50Y25 LUT6 (Prop_lut6_I1_O) 0.124 16.263 r u_cpu/id_stage/flush_inst_req_buffer[1]_i_9/O
|
|
net (fo=32, routed) 0.531 16.794 u_cpu/if_stage/nextpc5
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|
SLICE_X51Y27 r u_cpu/if_stage/fetch_pc_r[6]_i_4/I2
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SLICE_X51Y27 LUT6 (Prop_lut6_I2_O) 0.124 16.918 r u_cpu/if_stage/fetch_pc_r[6]_i_4/O
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net (fo=1, routed) 3.059 19.977 u_cpu/if_stage/fetch_pc_r[6]_i_4_n_0
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SLICE_X114Y28 r u_cpu/if_stage/fetch_pc_r[6]_i_2/I2
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SLICE_X114Y28 LUT6 (Prop_lut6_I2_O) 0.124 20.101 r u_cpu/if_stage/fetch_pc_r[6]_i_2/O
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net (fo=1, routed) 0.441 20.542 u_cpu/if_stage/fetch_pc_r[6]_i_2_n_0
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SLICE_X114Y25 r u_cpu/if_stage/fetch_pc_r[6]_i_1/I2
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SLICE_X114Y25 LUT6 (Prop_lut6_I2_O) 0.124 20.666 r u_cpu/if_stage/fetch_pc_r[6]_i_1/O
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net (fo=6, routed) 3.249 23.915 u_cpu/icache/tagv_ram_way[1].u/mem_reg_reg_2[2]
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SLICE_X49Y33 r u_cpu/icache/tagv_ram_way[1].u/mem_reg_reg_i_8/I4
|
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SLICE_X49Y33 LUT5 (Prop_lut5_I4_O) 0.124 24.039 r u_cpu/icache/tagv_ram_way[1].u/mem_reg_reg_i_8/O
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net (fo=16, routed) 1.477 25.516 u_cpu/icache/data_ram_way[0].data_ram_bank[2].u/ADDRBWRADDR[2]
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RAMB18_X2Y2 RAMB18E1 r u_cpu/icache/data_ram_way[0].data_ram_bank[2].u/mem_reg_reg/ADDRARDADDR[7]
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock cpu_clk rise edge) 30.323 30.323 r
|
|
clock source latency -5.674 24.648
|
|
propagated clock network latency
|
|
3.781 28.429
|
|
clock pessimism -0.418 28.011
|
|
clock uncertainty -0.074 27.937
|
|
RAMB18_X2Y2 RAMB18E1 (Setup_ramb18e1_CLKARDCLK_ADDRARDADDR[7])
|
|
-0.566 27.371 u_cpu/icache/data_ram_way[0].data_ram_bank[2].u/mem_reg_reg
|
|
-------------------------------------------------------------------
|
|
required time 27.371
|
|
arrival time -25.516
|
|
-------------------------------------------------------------------
|
|
slack 1.855
|
|
|
|
Slack (MET) : 1.855ns (required time - arrival time)
|
|
Source: u_cpu/addr_trans/data_vaddr_buffer_reg[14]/C
|
|
(rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns})
|
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Destination: u_cpu/icache/data_ram_way[0].data_ram_bank[2].u/mem_reg_reg/ADDRARDADDR[7]
|
|
(rising edge-triggered cell RAMB18E1 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns})
|
|
Path Group: cpu_clk
|
|
Path Type: Setup (Max at Slow Process Corner)
|
|
Requirement: 30.323ns (cpu_clk rise@30.323ns - cpu_clk rise@0.000ns)
|
|
Data Path Delay: 27.741ns (logic 5.333ns (19.224%) route 22.408ns (80.776%))
|
|
Logic Levels: 26 (CARRY4=4 LUT3=2 LUT4=1 LUT5=2 LUT6=15 MUXF7=1 MUXF8=1)
|
|
Clock Path Skew: -0.087ns (DCD - SCD + CPR)
|
|
Destination Clock Delay (DCD): -1.893ns = ( 28.429 - 30.323 )
|
|
Source Clock Delay (SCD): -2.225ns
|
|
Clock Pessimism Removal (CPR): -0.418ns
|
|
Clock Uncertainty: 0.074ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Discrete Jitter (DJ): 0.130ns
|
|
Phase Error (PE): 0.000ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock cpu_clk rise edge) 0.000 0.000 r
|
|
clock source latency -6.275 -6.275
|
|
propagated clock network latency
|
|
4.051 -2.225
|
|
SLICE_X35Y35 FDRE 0.000 -2.225 r u_cpu/addr_trans/data_vaddr_buffer_reg[14]/C
|
|
SLICE_X35Y35 FDRE (Prop_fdre_C_Q) 0.456 -1.769 r u_cpu/addr_trans/data_vaddr_buffer_reg[14]/Q
|
|
net (fo=33, routed) 1.442 -0.326 u_cpu/addr_trans/tlb_entry/data_vaddr_buffer[2]
|
|
SLICE_X42Y40 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_226/I5
|
|
SLICE_X42Y40 LUT6 (Prop_lut6_I5_O) 0.124 -0.202 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_226/O
|
|
net (fo=1, routed) 0.000 -0.202 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_226_n_0
|
|
SLICE_X42Y40 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_111/S[0]
|
|
SLICE_X42Y40 CARRY4 (Prop_carry4_S[0]_CO[3])
|
|
0.513 0.311 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_111/CO[3]
|
|
net (fo=1, routed) 0.000 0.311 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_111_n_0
|
|
SLICE_X42Y41 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_32/CI
|
|
SLICE_X42Y41 CARRY4 (Prop_carry4_CI_CO[2])
|
|
0.229 0.540 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_32/CO[2]
|
|
net (fo=1, routed) 1.009 1.549 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_32_n_1
|
|
SLICE_X40Y47 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_9/I1
|
|
SLICE_X40Y47 LUT6 (Prop_lut6_I1_O) 0.310 1.859 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_9/O
|
|
net (fo=2, routed) 0.635 2.494 u_cpu/addr_trans/tlb_entry/match1[28]
|
|
SLICE_X38Y47 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/I2
|
|
SLICE_X38Y47 LUT4 (Prop_lut4_I2_O) 0.124 2.618 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/O
|
|
net (fo=2, routed) 0.667 3.285 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2_n_0
|
|
SLICE_X39Y47 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/I0
|
|
SLICE_X39Y47 LUT5 (Prop_lut5_I0_O) 0.124 3.409 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/O
|
|
net (fo=2, routed) 1.103 4.512 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2_n_0
|
|
SLICE_X38Y50 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/I0
|
|
SLICE_X38Y50 LUT6 (Prop_lut6_I0_O) 0.124 4.636 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/O
|
|
net (fo=89, routed) 1.162 5.797 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus[8]
|
|
SLICE_X42Y51 r u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_38__0/S
|
|
SLICE_X42Y51 MUXF7 (Prop_muxf7_S_O) 0.292 6.089 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_38__0/O
|
|
net (fo=1, routed) 0.000 6.089 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_38__0_n_0
|
|
SLICE_X42Y51 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_16__0/I1
|
|
SLICE_X42Y51 MUXF8 (Prop_muxf8_I1_O) 0.088 6.177 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_16__0/O
|
|
net (fo=1, routed) 0.957 7.134 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_16__0_n_0
|
|
SLICE_X42Y50 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7/I0
|
|
SLICE_X42Y50 LUT6 (Prop_lut6_I0_O) 0.319 7.453 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7/O
|
|
net (fo=1, routed) 0.435 7.888 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7_n_0
|
|
SLICE_X44Y50 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0/I5
|
|
SLICE_X44Y50 LUT6 (Prop_lut6_I5_O) 0.124 8.012 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0/O
|
|
net (fo=10, routed) 0.740 8.753 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0_n_0
|
|
SLICE_X44Y50 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[5]_i_1__0/I3
|
|
SLICE_X44Y50 LUT6 (Prop_lut6_I3_O) 0.124 8.877 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[5]_i_1__0/O
|
|
net (fo=6, routed) 0.845 9.722 u_cpu/u_csr/ms_to_ws_bus[13]
|
|
SLICE_X50Y46 r u_cpu/u_csr/write_buffer_way[1]_i_18/I3
|
|
SLICE_X50Y46 LUT6 (Prop_lut6_I3_O) 0.124 9.846 r u_cpu/u_csr/write_buffer_way[1]_i_18/O
|
|
net (fo=1, routed) 0.000 9.846 u_cpu/u_csr/write_buffer_way[1]_i_18_n_0
|
|
SLICE_X50Y46 r u_cpu/u_csr/write_buffer_way_reg[1]_i_11/S[0]
|
|
SLICE_X50Y46 CARRY4 (Prop_carry4_S[0]_CO[3])
|
|
0.532 10.378 r u_cpu/u_csr/write_buffer_way_reg[1]_i_11/CO[3]
|
|
net (fo=1, routed) 0.000 10.378 u_cpu/u_csr/write_buffer_way_reg[1]_i_11_n_0
|
|
SLICE_X50Y47 r u_cpu/u_csr/write_buffer_way_reg[1]_i_9/CI
|
|
SLICE_X50Y47 CARRY4 (Prop_carry4_CI_CO[1])
|
|
0.157 10.535 r u_cpu/u_csr/write_buffer_way_reg[1]_i_9/CO[1]
|
|
net (fo=2, routed) 0.791 11.326 u_cpu/wb_stage/CO[0]
|
|
SLICE_X46Y39 r u_cpu/wb_stage/write_buffer_way[1]_i_5/I1
|
|
SLICE_X46Y39 LUT6 (Prop_lut6_I1_O) 0.329 11.655 f u_cpu/wb_stage/write_buffer_way[1]_i_5/O
|
|
net (fo=7, routed) 0.762 12.417 u_cpu/addr_trans/tlb_entry/sc_cancel_req
|
|
SLICE_X46Y35 f u_cpu/addr_trans/tlb_entry/main_state[0]_i_3/I1
|
|
SLICE_X46Y35 LUT3 (Prop_lut3_I1_O) 0.124 12.541 f u_cpu/addr_trans/tlb_entry/main_state[0]_i_3/O
|
|
net (fo=3, routed) 0.719 13.260 u_cpu/dcache/main_state_reg[0]_2
|
|
SLICE_X43Y31 f u_cpu/dcache/ds_to_es_bus_r[235]_i_10/I3
|
|
SLICE_X43Y31 LUT6 (Prop_lut6_I3_O) 0.124 13.384 f u_cpu/dcache/ds_to_es_bus_r[235]_i_10/O
|
|
net (fo=3, routed) 0.415 13.799 u_cpu/mem_stage/data_data_ok
|
|
SLICE_X43Y30 f u_cpu/mem_stage/flush_inst_req_buffer[1]_i_15/I0
|
|
SLICE_X43Y30 LUT3 (Prop_lut3_I0_O) 0.124 13.923 f u_cpu/mem_stage/flush_inst_req_buffer[1]_i_15/O
|
|
net (fo=2, routed) 0.833 14.756 u_cpu/mem_stage/es_to_ms_bus_r_reg[70]_1
|
|
SLICE_X48Y30 f u_cpu/mem_stage/flush_inst_req_buffer[1]_i_14/I0
|
|
SLICE_X48Y30 LUT6 (Prop_lut6_I0_O) 0.124 14.880 f u_cpu/mem_stage/flush_inst_req_buffer[1]_i_14/O
|
|
net (fo=1, routed) 0.651 15.532 u_cpu/mem_stage/ms_ready_go
|
|
SLICE_X48Y25 f u_cpu/mem_stage/flush_inst_req_buffer[1]_i_13/I4
|
|
SLICE_X48Y25 LUT6 (Prop_lut6_I4_O) 0.124 15.656 f u_cpu/mem_stage/flush_inst_req_buffer[1]_i_13/O
|
|
net (fo=3, routed) 0.483 16.139 u_cpu/id_stage/flush_inst_req_buffer[31]_i_6
|
|
SLICE_X50Y25 f u_cpu/id_stage/flush_inst_req_buffer[1]_i_9/I1
|
|
SLICE_X50Y25 LUT6 (Prop_lut6_I1_O) 0.124 16.263 f u_cpu/id_stage/flush_inst_req_buffer[1]_i_9/O
|
|
net (fo=32, routed) 0.531 16.794 u_cpu/if_stage/nextpc5
|
|
SLICE_X51Y27 f u_cpu/if_stage/fetch_pc_r[6]_i_4/I2
|
|
SLICE_X51Y27 LUT6 (Prop_lut6_I2_O) 0.124 16.918 r u_cpu/if_stage/fetch_pc_r[6]_i_4/O
|
|
net (fo=1, routed) 3.059 19.977 u_cpu/if_stage/fetch_pc_r[6]_i_4_n_0
|
|
SLICE_X114Y28 r u_cpu/if_stage/fetch_pc_r[6]_i_2/I2
|
|
SLICE_X114Y28 LUT6 (Prop_lut6_I2_O) 0.124 20.101 r u_cpu/if_stage/fetch_pc_r[6]_i_2/O
|
|
net (fo=1, routed) 0.441 20.542 u_cpu/if_stage/fetch_pc_r[6]_i_2_n_0
|
|
SLICE_X114Y25 r u_cpu/if_stage/fetch_pc_r[6]_i_1/I2
|
|
SLICE_X114Y25 LUT6 (Prop_lut6_I2_O) 0.124 20.666 r u_cpu/if_stage/fetch_pc_r[6]_i_1/O
|
|
net (fo=6, routed) 3.249 23.915 u_cpu/icache/tagv_ram_way[1].u/mem_reg_reg_2[2]
|
|
SLICE_X49Y33 r u_cpu/icache/tagv_ram_way[1].u/mem_reg_reg_i_8/I4
|
|
SLICE_X49Y33 LUT5 (Prop_lut5_I4_O) 0.124 24.039 r u_cpu/icache/tagv_ram_way[1].u/mem_reg_reg_i_8/O
|
|
net (fo=16, routed) 1.477 25.516 u_cpu/icache/data_ram_way[0].data_ram_bank[2].u/ADDRBWRADDR[2]
|
|
RAMB18_X2Y2 RAMB18E1 r u_cpu/icache/data_ram_way[0].data_ram_bank[2].u/mem_reg_reg/ADDRARDADDR[7]
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock cpu_clk rise edge) 30.323 30.323 r
|
|
clock source latency -5.674 24.648
|
|
propagated clock network latency
|
|
3.781 28.429
|
|
clock pessimism -0.418 28.011
|
|
clock uncertainty -0.074 27.937
|
|
RAMB18_X2Y2 RAMB18E1 (Setup_ramb18e1_CLKARDCLK_ADDRARDADDR[7])
|
|
-0.566 27.371 u_cpu/icache/data_ram_way[0].data_ram_bank[2].u/mem_reg_reg
|
|
-------------------------------------------------------------------
|
|
required time 27.371
|
|
arrival time -25.516
|
|
-------------------------------------------------------------------
|
|
slack 1.855
|
|
|
|
Slack (MET) : 1.855ns (required time - arrival time)
|
|
Source: u_cpu/addr_trans/data_vaddr_buffer_reg[14]/C
|
|
(rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns})
|
|
Destination: u_cpu/icache/data_ram_way[0].data_ram_bank[2].u/mem_reg_reg/ADDRARDADDR[7]
|
|
(rising edge-triggered cell RAMB18E1 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns})
|
|
Path Group: cpu_clk
|
|
Path Type: Setup (Max at Slow Process Corner)
|
|
Requirement: 30.323ns (cpu_clk rise@30.323ns - cpu_clk rise@0.000ns)
|
|
Data Path Delay: 27.741ns (logic 5.333ns (19.224%) route 22.408ns (80.776%))
|
|
Logic Levels: 26 (CARRY4=4 LUT3=2 LUT4=1 LUT5=2 LUT6=15 MUXF7=1 MUXF8=1)
|
|
Clock Path Skew: -0.087ns (DCD - SCD + CPR)
|
|
Destination Clock Delay (DCD): -1.893ns = ( 28.429 - 30.323 )
|
|
Source Clock Delay (SCD): -2.225ns
|
|
Clock Pessimism Removal (CPR): -0.418ns
|
|
Clock Uncertainty: 0.074ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Discrete Jitter (DJ): 0.130ns
|
|
Phase Error (PE): 0.000ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock cpu_clk rise edge) 0.000 0.000 r
|
|
clock source latency -6.275 -6.275
|
|
propagated clock network latency
|
|
4.051 -2.225
|
|
SLICE_X35Y35 FDRE 0.000 -2.225 r u_cpu/addr_trans/data_vaddr_buffer_reg[14]/C
|
|
SLICE_X35Y35 FDRE (Prop_fdre_C_Q) 0.456 -1.769 r u_cpu/addr_trans/data_vaddr_buffer_reg[14]/Q
|
|
net (fo=33, routed) 1.442 -0.326 u_cpu/addr_trans/tlb_entry/data_vaddr_buffer[2]
|
|
SLICE_X42Y40 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_226/I5
|
|
SLICE_X42Y40 LUT6 (Prop_lut6_I5_O) 0.124 -0.202 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_226/O
|
|
net (fo=1, routed) 0.000 -0.202 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_226_n_0
|
|
SLICE_X42Y40 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_111/S[0]
|
|
SLICE_X42Y40 CARRY4 (Prop_carry4_S[0]_CO[3])
|
|
0.513 0.311 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_111/CO[3]
|
|
net (fo=1, routed) 0.000 0.311 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_111_n_0
|
|
SLICE_X42Y41 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_32/CI
|
|
SLICE_X42Y41 CARRY4 (Prop_carry4_CI_CO[2])
|
|
0.229 0.540 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_32/CO[2]
|
|
net (fo=1, routed) 1.009 1.549 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_32_n_1
|
|
SLICE_X40Y47 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_9/I1
|
|
SLICE_X40Y47 LUT6 (Prop_lut6_I1_O) 0.310 1.859 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_9/O
|
|
net (fo=2, routed) 0.635 2.494 u_cpu/addr_trans/tlb_entry/match1[28]
|
|
SLICE_X38Y47 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/I2
|
|
SLICE_X38Y47 LUT4 (Prop_lut4_I2_O) 0.124 2.618 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/O
|
|
net (fo=2, routed) 0.667 3.285 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2_n_0
|
|
SLICE_X39Y47 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/I0
|
|
SLICE_X39Y47 LUT5 (Prop_lut5_I0_O) 0.124 3.409 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/O
|
|
net (fo=2, routed) 1.103 4.512 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2_n_0
|
|
SLICE_X38Y50 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/I0
|
|
SLICE_X38Y50 LUT6 (Prop_lut6_I0_O) 0.124 4.636 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/O
|
|
net (fo=89, routed) 1.162 5.797 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus[8]
|
|
SLICE_X42Y51 r u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_38__0/S
|
|
SLICE_X42Y51 MUXF7 (Prop_muxf7_S_O) 0.292 6.089 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_38__0/O
|
|
net (fo=1, routed) 0.000 6.089 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_38__0_n_0
|
|
SLICE_X42Y51 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_16__0/I1
|
|
SLICE_X42Y51 MUXF8 (Prop_muxf8_I1_O) 0.088 6.177 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_16__0/O
|
|
net (fo=1, routed) 0.957 7.134 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_16__0_n_0
|
|
SLICE_X42Y50 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7/I0
|
|
SLICE_X42Y50 LUT6 (Prop_lut6_I0_O) 0.319 7.453 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7/O
|
|
net (fo=1, routed) 0.435 7.888 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7_n_0
|
|
SLICE_X44Y50 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0/I5
|
|
SLICE_X44Y50 LUT6 (Prop_lut6_I5_O) 0.124 8.012 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0/O
|
|
net (fo=10, routed) 0.740 8.753 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0_n_0
|
|
SLICE_X44Y50 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[5]_i_1__0/I3
|
|
SLICE_X44Y50 LUT6 (Prop_lut6_I3_O) 0.124 8.877 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[5]_i_1__0/O
|
|
net (fo=6, routed) 0.845 9.722 u_cpu/u_csr/ms_to_ws_bus[13]
|
|
SLICE_X50Y46 f u_cpu/u_csr/write_buffer_way[1]_i_18/I3
|
|
SLICE_X50Y46 LUT6 (Prop_lut6_I3_O) 0.124 9.846 r u_cpu/u_csr/write_buffer_way[1]_i_18/O
|
|
net (fo=1, routed) 0.000 9.846 u_cpu/u_csr/write_buffer_way[1]_i_18_n_0
|
|
SLICE_X50Y46 r u_cpu/u_csr/write_buffer_way_reg[1]_i_11/S[0]
|
|
SLICE_X50Y46 CARRY4 (Prop_carry4_S[0]_CO[3])
|
|
0.532 10.378 r u_cpu/u_csr/write_buffer_way_reg[1]_i_11/CO[3]
|
|
net (fo=1, routed) 0.000 10.378 u_cpu/u_csr/write_buffer_way_reg[1]_i_11_n_0
|
|
SLICE_X50Y47 r u_cpu/u_csr/write_buffer_way_reg[1]_i_9/CI
|
|
SLICE_X50Y47 CARRY4 (Prop_carry4_CI_CO[1])
|
|
0.157 10.535 r u_cpu/u_csr/write_buffer_way_reg[1]_i_9/CO[1]
|
|
net (fo=2, routed) 0.791 11.326 u_cpu/wb_stage/CO[0]
|
|
SLICE_X46Y39 r u_cpu/wb_stage/write_buffer_way[1]_i_5/I1
|
|
SLICE_X46Y39 LUT6 (Prop_lut6_I1_O) 0.329 11.655 f u_cpu/wb_stage/write_buffer_way[1]_i_5/O
|
|
net (fo=7, routed) 0.762 12.417 u_cpu/addr_trans/tlb_entry/sc_cancel_req
|
|
SLICE_X46Y35 f u_cpu/addr_trans/tlb_entry/main_state[0]_i_3/I1
|
|
SLICE_X46Y35 LUT3 (Prop_lut3_I1_O) 0.124 12.541 f u_cpu/addr_trans/tlb_entry/main_state[0]_i_3/O
|
|
net (fo=3, routed) 0.719 13.260 u_cpu/dcache/main_state_reg[0]_2
|
|
SLICE_X43Y31 f u_cpu/dcache/ds_to_es_bus_r[235]_i_10/I3
|
|
SLICE_X43Y31 LUT6 (Prop_lut6_I3_O) 0.124 13.384 f u_cpu/dcache/ds_to_es_bus_r[235]_i_10/O
|
|
net (fo=3, routed) 0.415 13.799 u_cpu/mem_stage/data_data_ok
|
|
SLICE_X43Y30 f u_cpu/mem_stage/flush_inst_req_buffer[1]_i_15/I0
|
|
SLICE_X43Y30 LUT3 (Prop_lut3_I0_O) 0.124 13.923 f u_cpu/mem_stage/flush_inst_req_buffer[1]_i_15/O
|
|
net (fo=2, routed) 0.833 14.756 u_cpu/mem_stage/es_to_ms_bus_r_reg[70]_1
|
|
SLICE_X48Y30 f u_cpu/mem_stage/flush_inst_req_buffer[1]_i_14/I0
|
|
SLICE_X48Y30 LUT6 (Prop_lut6_I0_O) 0.124 14.880 f u_cpu/mem_stage/flush_inst_req_buffer[1]_i_14/O
|
|
net (fo=1, routed) 0.651 15.532 u_cpu/mem_stage/ms_ready_go
|
|
SLICE_X48Y25 f u_cpu/mem_stage/flush_inst_req_buffer[1]_i_13/I4
|
|
SLICE_X48Y25 LUT6 (Prop_lut6_I4_O) 0.124 15.656 f u_cpu/mem_stage/flush_inst_req_buffer[1]_i_13/O
|
|
net (fo=3, routed) 0.483 16.139 u_cpu/id_stage/flush_inst_req_buffer[31]_i_6
|
|
SLICE_X50Y25 f u_cpu/id_stage/flush_inst_req_buffer[1]_i_9/I1
|
|
SLICE_X50Y25 LUT6 (Prop_lut6_I1_O) 0.124 16.263 f u_cpu/id_stage/flush_inst_req_buffer[1]_i_9/O
|
|
net (fo=32, routed) 0.531 16.794 u_cpu/if_stage/nextpc5
|
|
SLICE_X51Y27 f u_cpu/if_stage/fetch_pc_r[6]_i_4/I2
|
|
SLICE_X51Y27 LUT6 (Prop_lut6_I2_O) 0.124 16.918 r u_cpu/if_stage/fetch_pc_r[6]_i_4/O
|
|
net (fo=1, routed) 3.059 19.977 u_cpu/if_stage/fetch_pc_r[6]_i_4_n_0
|
|
SLICE_X114Y28 r u_cpu/if_stage/fetch_pc_r[6]_i_2/I2
|
|
SLICE_X114Y28 LUT6 (Prop_lut6_I2_O) 0.124 20.101 r u_cpu/if_stage/fetch_pc_r[6]_i_2/O
|
|
net (fo=1, routed) 0.441 20.542 u_cpu/if_stage/fetch_pc_r[6]_i_2_n_0
|
|
SLICE_X114Y25 r u_cpu/if_stage/fetch_pc_r[6]_i_1/I2
|
|
SLICE_X114Y25 LUT6 (Prop_lut6_I2_O) 0.124 20.666 r u_cpu/if_stage/fetch_pc_r[6]_i_1/O
|
|
net (fo=6, routed) 3.249 23.915 u_cpu/icache/tagv_ram_way[1].u/mem_reg_reg_2[2]
|
|
SLICE_X49Y33 r u_cpu/icache/tagv_ram_way[1].u/mem_reg_reg_i_8/I4
|
|
SLICE_X49Y33 LUT5 (Prop_lut5_I4_O) 0.124 24.039 r u_cpu/icache/tagv_ram_way[1].u/mem_reg_reg_i_8/O
|
|
net (fo=16, routed) 1.477 25.516 u_cpu/icache/data_ram_way[0].data_ram_bank[2].u/ADDRBWRADDR[2]
|
|
RAMB18_X2Y2 RAMB18E1 r u_cpu/icache/data_ram_way[0].data_ram_bank[2].u/mem_reg_reg/ADDRARDADDR[7]
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock cpu_clk rise edge) 30.323 30.323 r
|
|
clock source latency -5.674 24.648
|
|
propagated clock network latency
|
|
3.781 28.429
|
|
clock pessimism -0.418 28.011
|
|
clock uncertainty -0.074 27.937
|
|
RAMB18_X2Y2 RAMB18E1 (Setup_ramb18e1_CLKARDCLK_ADDRARDADDR[7])
|
|
-0.566 27.371 u_cpu/icache/data_ram_way[0].data_ram_bank[2].u/mem_reg_reg
|
|
-------------------------------------------------------------------
|
|
required time 27.371
|
|
arrival time -25.516
|
|
-------------------------------------------------------------------
|
|
slack 1.855
|
|
|
|
Slack (MET) : 1.855ns (required time - arrival time)
|
|
Source: u_cpu/addr_trans/data_vaddr_buffer_reg[14]/C
|
|
(rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns})
|
|
Destination: u_cpu/icache/data_ram_way[0].data_ram_bank[2].u/mem_reg_reg/ADDRARDADDR[7]
|
|
(rising edge-triggered cell RAMB18E1 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns})
|
|
Path Group: cpu_clk
|
|
Path Type: Setup (Max at Slow Process Corner)
|
|
Requirement: 30.323ns (cpu_clk rise@30.323ns - cpu_clk rise@0.000ns)
|
|
Data Path Delay: 27.741ns (logic 5.333ns (19.224%) route 22.408ns (80.776%))
|
|
Logic Levels: 26 (CARRY4=4 LUT3=2 LUT4=1 LUT5=2 LUT6=15 MUXF7=1 MUXF8=1)
|
|
Clock Path Skew: -0.087ns (DCD - SCD + CPR)
|
|
Destination Clock Delay (DCD): -1.893ns = ( 28.429 - 30.323 )
|
|
Source Clock Delay (SCD): -2.225ns
|
|
Clock Pessimism Removal (CPR): -0.418ns
|
|
Clock Uncertainty: 0.074ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Discrete Jitter (DJ): 0.130ns
|
|
Phase Error (PE): 0.000ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock cpu_clk rise edge) 0.000 0.000 r
|
|
clock source latency -6.275 -6.275
|
|
propagated clock network latency
|
|
4.051 -2.225
|
|
SLICE_X35Y35 FDRE 0.000 -2.225 r u_cpu/addr_trans/data_vaddr_buffer_reg[14]/C
|
|
SLICE_X35Y35 FDRE (Prop_fdre_C_Q) 0.456 -1.769 r u_cpu/addr_trans/data_vaddr_buffer_reg[14]/Q
|
|
net (fo=33, routed) 1.442 -0.326 u_cpu/addr_trans/tlb_entry/data_vaddr_buffer[2]
|
|
SLICE_X42Y40 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_226/I5
|
|
SLICE_X42Y40 LUT6 (Prop_lut6_I5_O) 0.124 -0.202 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_226/O
|
|
net (fo=1, routed) 0.000 -0.202 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_226_n_0
|
|
SLICE_X42Y40 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_111/S[0]
|
|
SLICE_X42Y40 CARRY4 (Prop_carry4_S[0]_CO[3])
|
|
0.513 0.311 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_111/CO[3]
|
|
net (fo=1, routed) 0.000 0.311 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_111_n_0
|
|
SLICE_X42Y41 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_32/CI
|
|
SLICE_X42Y41 CARRY4 (Prop_carry4_CI_CO[2])
|
|
0.229 0.540 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_32/CO[2]
|
|
net (fo=1, routed) 1.009 1.549 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_32_n_1
|
|
SLICE_X40Y47 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_9/I1
|
|
SLICE_X40Y47 LUT6 (Prop_lut6_I1_O) 0.310 1.859 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_9/O
|
|
net (fo=2, routed) 0.635 2.494 u_cpu/addr_trans/tlb_entry/match1[28]
|
|
SLICE_X38Y47 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/I2
|
|
SLICE_X38Y47 LUT4 (Prop_lut4_I2_O) 0.124 2.618 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/O
|
|
net (fo=2, routed) 0.667 3.285 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2_n_0
|
|
SLICE_X39Y47 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/I0
|
|
SLICE_X39Y47 LUT5 (Prop_lut5_I0_O) 0.124 3.409 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/O
|
|
net (fo=2, routed) 1.103 4.512 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2_n_0
|
|
SLICE_X38Y50 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/I0
|
|
SLICE_X38Y50 LUT6 (Prop_lut6_I0_O) 0.124 4.636 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/O
|
|
net (fo=89, routed) 1.162 5.797 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus[8]
|
|
SLICE_X42Y51 r u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_38__0/S
|
|
SLICE_X42Y51 MUXF7 (Prop_muxf7_S_O) 0.292 6.089 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_38__0/O
|
|
net (fo=1, routed) 0.000 6.089 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_38__0_n_0
|
|
SLICE_X42Y51 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_16__0/I1
|
|
SLICE_X42Y51 MUXF8 (Prop_muxf8_I1_O) 0.088 6.177 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_16__0/O
|
|
net (fo=1, routed) 0.957 7.134 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_16__0_n_0
|
|
SLICE_X42Y50 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7/I0
|
|
SLICE_X42Y50 LUT6 (Prop_lut6_I0_O) 0.319 7.453 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7/O
|
|
net (fo=1, routed) 0.435 7.888 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7_n_0
|
|
SLICE_X44Y50 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0/I5
|
|
SLICE_X44Y50 LUT6 (Prop_lut6_I5_O) 0.124 8.012 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0/O
|
|
net (fo=10, routed) 0.740 8.753 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0_n_0
|
|
SLICE_X44Y50 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[5]_i_1__0/I3
|
|
SLICE_X44Y50 LUT6 (Prop_lut6_I3_O) 0.124 8.877 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[5]_i_1__0/O
|
|
net (fo=6, routed) 0.845 9.722 u_cpu/u_csr/ms_to_ws_bus[13]
|
|
SLICE_X50Y46 r u_cpu/u_csr/write_buffer_way[1]_i_18/I3
|
|
SLICE_X50Y46 LUT6 (Prop_lut6_I3_O) 0.124 9.846 f u_cpu/u_csr/write_buffer_way[1]_i_18/O
|
|
net (fo=1, routed) 0.000 9.846 u_cpu/u_csr/write_buffer_way[1]_i_18_n_0
|
|
SLICE_X50Y46 f u_cpu/u_csr/write_buffer_way_reg[1]_i_11/S[0]
|
|
SLICE_X50Y46 CARRY4 (Prop_carry4_S[0]_CO[3])
|
|
0.532 10.378 r u_cpu/u_csr/write_buffer_way_reg[1]_i_11/CO[3]
|
|
net (fo=1, routed) 0.000 10.378 u_cpu/u_csr/write_buffer_way_reg[1]_i_11_n_0
|
|
SLICE_X50Y47 r u_cpu/u_csr/write_buffer_way_reg[1]_i_9/CI
|
|
SLICE_X50Y47 CARRY4 (Prop_carry4_CI_CO[1])
|
|
0.157 10.535 r u_cpu/u_csr/write_buffer_way_reg[1]_i_9/CO[1]
|
|
net (fo=2, routed) 0.791 11.326 u_cpu/wb_stage/CO[0]
|
|
SLICE_X46Y39 r u_cpu/wb_stage/write_buffer_way[1]_i_5/I1
|
|
SLICE_X46Y39 LUT6 (Prop_lut6_I1_O) 0.329 11.655 f u_cpu/wb_stage/write_buffer_way[1]_i_5/O
|
|
net (fo=7, routed) 0.762 12.417 u_cpu/addr_trans/tlb_entry/sc_cancel_req
|
|
SLICE_X46Y35 f u_cpu/addr_trans/tlb_entry/main_state[0]_i_3/I1
|
|
SLICE_X46Y35 LUT3 (Prop_lut3_I1_O) 0.124 12.541 f u_cpu/addr_trans/tlb_entry/main_state[0]_i_3/O
|
|
net (fo=3, routed) 0.719 13.260 u_cpu/dcache/main_state_reg[0]_2
|
|
SLICE_X43Y31 f u_cpu/dcache/ds_to_es_bus_r[235]_i_10/I3
|
|
SLICE_X43Y31 LUT6 (Prop_lut6_I3_O) 0.124 13.384 f u_cpu/dcache/ds_to_es_bus_r[235]_i_10/O
|
|
net (fo=3, routed) 0.415 13.799 u_cpu/mem_stage/data_data_ok
|
|
SLICE_X43Y30 f u_cpu/mem_stage/flush_inst_req_buffer[1]_i_15/I0
|
|
SLICE_X43Y30 LUT3 (Prop_lut3_I0_O) 0.124 13.923 f u_cpu/mem_stage/flush_inst_req_buffer[1]_i_15/O
|
|
net (fo=2, routed) 0.833 14.756 u_cpu/mem_stage/es_to_ms_bus_r_reg[70]_1
|
|
SLICE_X48Y30 f u_cpu/mem_stage/flush_inst_req_buffer[1]_i_14/I0
|
|
SLICE_X48Y30 LUT6 (Prop_lut6_I0_O) 0.124 14.880 f u_cpu/mem_stage/flush_inst_req_buffer[1]_i_14/O
|
|
net (fo=1, routed) 0.651 15.532 u_cpu/mem_stage/ms_ready_go
|
|
SLICE_X48Y25 f u_cpu/mem_stage/flush_inst_req_buffer[1]_i_13/I4
|
|
SLICE_X48Y25 LUT6 (Prop_lut6_I4_O) 0.124 15.656 f u_cpu/mem_stage/flush_inst_req_buffer[1]_i_13/O
|
|
net (fo=3, routed) 0.483 16.139 u_cpu/id_stage/flush_inst_req_buffer[31]_i_6
|
|
SLICE_X50Y25 f u_cpu/id_stage/flush_inst_req_buffer[1]_i_9/I1
|
|
SLICE_X50Y25 LUT6 (Prop_lut6_I1_O) 0.124 16.263 f u_cpu/id_stage/flush_inst_req_buffer[1]_i_9/O
|
|
net (fo=32, routed) 0.531 16.794 u_cpu/if_stage/nextpc5
|
|
SLICE_X51Y27 f u_cpu/if_stage/fetch_pc_r[6]_i_4/I2
|
|
SLICE_X51Y27 LUT6 (Prop_lut6_I2_O) 0.124 16.918 r u_cpu/if_stage/fetch_pc_r[6]_i_4/O
|
|
net (fo=1, routed) 3.059 19.977 u_cpu/if_stage/fetch_pc_r[6]_i_4_n_0
|
|
SLICE_X114Y28 r u_cpu/if_stage/fetch_pc_r[6]_i_2/I2
|
|
SLICE_X114Y28 LUT6 (Prop_lut6_I2_O) 0.124 20.101 r u_cpu/if_stage/fetch_pc_r[6]_i_2/O
|
|
net (fo=1, routed) 0.441 20.542 u_cpu/if_stage/fetch_pc_r[6]_i_2_n_0
|
|
SLICE_X114Y25 r u_cpu/if_stage/fetch_pc_r[6]_i_1/I2
|
|
SLICE_X114Y25 LUT6 (Prop_lut6_I2_O) 0.124 20.666 r u_cpu/if_stage/fetch_pc_r[6]_i_1/O
|
|
net (fo=6, routed) 3.249 23.915 u_cpu/icache/tagv_ram_way[1].u/mem_reg_reg_2[2]
|
|
SLICE_X49Y33 r u_cpu/icache/tagv_ram_way[1].u/mem_reg_reg_i_8/I4
|
|
SLICE_X49Y33 LUT5 (Prop_lut5_I4_O) 0.124 24.039 r u_cpu/icache/tagv_ram_way[1].u/mem_reg_reg_i_8/O
|
|
net (fo=16, routed) 1.477 25.516 u_cpu/icache/data_ram_way[0].data_ram_bank[2].u/ADDRBWRADDR[2]
|
|
RAMB18_X2Y2 RAMB18E1 r u_cpu/icache/data_ram_way[0].data_ram_bank[2].u/mem_reg_reg/ADDRARDADDR[7]
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock cpu_clk rise edge) 30.323 30.323 r
|
|
clock source latency -5.674 24.648
|
|
propagated clock network latency
|
|
3.781 28.429
|
|
clock pessimism -0.418 28.011
|
|
clock uncertainty -0.074 27.937
|
|
RAMB18_X2Y2 RAMB18E1 (Setup_ramb18e1_CLKARDCLK_ADDRARDADDR[7])
|
|
-0.566 27.371 u_cpu/icache/data_ram_way[0].data_ram_bank[2].u/mem_reg_reg
|
|
-------------------------------------------------------------------
|
|
required time 27.371
|
|
arrival time -25.516
|
|
-------------------------------------------------------------------
|
|
slack 1.855
|
|
|
|
Slack (MET) : 1.855ns (required time - arrival time)
|
|
Source: u_cpu/addr_trans/data_vaddr_buffer_reg[14]/C
|
|
(rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns})
|
|
Destination: u_cpu/icache/data_ram_way[0].data_ram_bank[2].u/mem_reg_reg/ADDRARDADDR[7]
|
|
(rising edge-triggered cell RAMB18E1 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns})
|
|
Path Group: cpu_clk
|
|
Path Type: Setup (Max at Slow Process Corner)
|
|
Requirement: 30.323ns (cpu_clk rise@30.323ns - cpu_clk rise@0.000ns)
|
|
Data Path Delay: 27.741ns (logic 5.333ns (19.224%) route 22.408ns (80.776%))
|
|
Logic Levels: 26 (CARRY4=4 LUT3=2 LUT4=1 LUT5=2 LUT6=15 MUXF7=1 MUXF8=1)
|
|
Clock Path Skew: -0.087ns (DCD - SCD + CPR)
|
|
Destination Clock Delay (DCD): -1.893ns = ( 28.429 - 30.323 )
|
|
Source Clock Delay (SCD): -2.225ns
|
|
Clock Pessimism Removal (CPR): -0.418ns
|
|
Clock Uncertainty: 0.074ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Discrete Jitter (DJ): 0.130ns
|
|
Phase Error (PE): 0.000ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock cpu_clk rise edge) 0.000 0.000 r
|
|
clock source latency -6.275 -6.275
|
|
propagated clock network latency
|
|
4.051 -2.225
|
|
SLICE_X35Y35 FDRE 0.000 -2.225 r u_cpu/addr_trans/data_vaddr_buffer_reg[14]/C
|
|
SLICE_X35Y35 FDRE (Prop_fdre_C_Q) 0.456 -1.769 r u_cpu/addr_trans/data_vaddr_buffer_reg[14]/Q
|
|
net (fo=33, routed) 1.442 -0.326 u_cpu/addr_trans/tlb_entry/data_vaddr_buffer[2]
|
|
SLICE_X42Y40 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_226/I5
|
|
SLICE_X42Y40 LUT6 (Prop_lut6_I5_O) 0.124 -0.202 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_226/O
|
|
net (fo=1, routed) 0.000 -0.202 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_226_n_0
|
|
SLICE_X42Y40 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_111/S[0]
|
|
SLICE_X42Y40 CARRY4 (Prop_carry4_S[0]_CO[3])
|
|
0.513 0.311 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_111/CO[3]
|
|
net (fo=1, routed) 0.000 0.311 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_111_n_0
|
|
SLICE_X42Y41 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_32/CI
|
|
SLICE_X42Y41 CARRY4 (Prop_carry4_CI_CO[2])
|
|
0.229 0.540 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_32/CO[2]
|
|
net (fo=1, routed) 1.009 1.549 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_32_n_1
|
|
SLICE_X40Y47 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_9/I1
|
|
SLICE_X40Y47 LUT6 (Prop_lut6_I1_O) 0.310 1.859 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_9/O
|
|
net (fo=2, routed) 0.635 2.494 u_cpu/addr_trans/tlb_entry/match1[28]
|
|
SLICE_X38Y47 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/I2
|
|
SLICE_X38Y47 LUT4 (Prop_lut4_I2_O) 0.124 2.618 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/O
|
|
net (fo=2, routed) 0.667 3.285 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2_n_0
|
|
SLICE_X39Y47 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/I0
|
|
SLICE_X39Y47 LUT5 (Prop_lut5_I0_O) 0.124 3.409 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/O
|
|
net (fo=2, routed) 1.103 4.512 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2_n_0
|
|
SLICE_X38Y50 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/I0
|
|
SLICE_X38Y50 LUT6 (Prop_lut6_I0_O) 0.124 4.636 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/O
|
|
net (fo=89, routed) 1.162 5.797 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus[8]
|
|
SLICE_X42Y51 r u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_38__0/S
|
|
SLICE_X42Y51 MUXF7 (Prop_muxf7_S_O) 0.292 6.089 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_38__0/O
|
|
net (fo=1, routed) 0.000 6.089 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_38__0_n_0
|
|
SLICE_X42Y51 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_16__0/I1
|
|
SLICE_X42Y51 MUXF8 (Prop_muxf8_I1_O) 0.088 6.177 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_16__0/O
|
|
net (fo=1, routed) 0.957 7.134 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_16__0_n_0
|
|
SLICE_X42Y50 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7/I0
|
|
SLICE_X42Y50 LUT6 (Prop_lut6_I0_O) 0.319 7.453 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7/O
|
|
net (fo=1, routed) 0.435 7.888 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7_n_0
|
|
SLICE_X44Y50 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0/I5
|
|
SLICE_X44Y50 LUT6 (Prop_lut6_I5_O) 0.124 8.012 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0/O
|
|
net (fo=10, routed) 0.740 8.753 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0_n_0
|
|
SLICE_X44Y50 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[5]_i_1__0/I3
|
|
SLICE_X44Y50 LUT6 (Prop_lut6_I3_O) 0.124 8.877 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[5]_i_1__0/O
|
|
net (fo=6, routed) 0.845 9.722 u_cpu/u_csr/ms_to_ws_bus[13]
|
|
SLICE_X50Y46 f u_cpu/u_csr/write_buffer_way[1]_i_18/I3
|
|
SLICE_X50Y46 LUT6 (Prop_lut6_I3_O) 0.124 9.846 f u_cpu/u_csr/write_buffer_way[1]_i_18/O
|
|
net (fo=1, routed) 0.000 9.846 u_cpu/u_csr/write_buffer_way[1]_i_18_n_0
|
|
SLICE_X50Y46 f u_cpu/u_csr/write_buffer_way_reg[1]_i_11/S[0]
|
|
SLICE_X50Y46 CARRY4 (Prop_carry4_S[0]_CO[3])
|
|
0.532 10.378 r u_cpu/u_csr/write_buffer_way_reg[1]_i_11/CO[3]
|
|
net (fo=1, routed) 0.000 10.378 u_cpu/u_csr/write_buffer_way_reg[1]_i_11_n_0
|
|
SLICE_X50Y47 r u_cpu/u_csr/write_buffer_way_reg[1]_i_9/CI
|
|
SLICE_X50Y47 CARRY4 (Prop_carry4_CI_CO[1])
|
|
0.157 10.535 r u_cpu/u_csr/write_buffer_way_reg[1]_i_9/CO[1]
|
|
net (fo=2, routed) 0.791 11.326 u_cpu/wb_stage/CO[0]
|
|
SLICE_X46Y39 r u_cpu/wb_stage/write_buffer_way[1]_i_5/I1
|
|
SLICE_X46Y39 LUT6 (Prop_lut6_I1_O) 0.329 11.655 f u_cpu/wb_stage/write_buffer_way[1]_i_5/O
|
|
net (fo=7, routed) 0.762 12.417 u_cpu/addr_trans/tlb_entry/sc_cancel_req
|
|
SLICE_X46Y35 f u_cpu/addr_trans/tlb_entry/main_state[0]_i_3/I1
|
|
SLICE_X46Y35 LUT3 (Prop_lut3_I1_O) 0.124 12.541 f u_cpu/addr_trans/tlb_entry/main_state[0]_i_3/O
|
|
net (fo=3, routed) 0.719 13.260 u_cpu/dcache/main_state_reg[0]_2
|
|
SLICE_X43Y31 f u_cpu/dcache/ds_to_es_bus_r[235]_i_10/I3
|
|
SLICE_X43Y31 LUT6 (Prop_lut6_I3_O) 0.124 13.384 f u_cpu/dcache/ds_to_es_bus_r[235]_i_10/O
|
|
net (fo=3, routed) 0.415 13.799 u_cpu/mem_stage/data_data_ok
|
|
SLICE_X43Y30 f u_cpu/mem_stage/flush_inst_req_buffer[1]_i_15/I0
|
|
SLICE_X43Y30 LUT3 (Prop_lut3_I0_O) 0.124 13.923 f u_cpu/mem_stage/flush_inst_req_buffer[1]_i_15/O
|
|
net (fo=2, routed) 0.833 14.756 u_cpu/mem_stage/es_to_ms_bus_r_reg[70]_1
|
|
SLICE_X48Y30 f u_cpu/mem_stage/flush_inst_req_buffer[1]_i_14/I0
|
|
SLICE_X48Y30 LUT6 (Prop_lut6_I0_O) 0.124 14.880 f u_cpu/mem_stage/flush_inst_req_buffer[1]_i_14/O
|
|
net (fo=1, routed) 0.651 15.532 u_cpu/mem_stage/ms_ready_go
|
|
SLICE_X48Y25 f u_cpu/mem_stage/flush_inst_req_buffer[1]_i_13/I4
|
|
SLICE_X48Y25 LUT6 (Prop_lut6_I4_O) 0.124 15.656 f u_cpu/mem_stage/flush_inst_req_buffer[1]_i_13/O
|
|
net (fo=3, routed) 0.483 16.139 u_cpu/id_stage/flush_inst_req_buffer[31]_i_6
|
|
SLICE_X50Y25 f u_cpu/id_stage/flush_inst_req_buffer[1]_i_9/I1
|
|
SLICE_X50Y25 LUT6 (Prop_lut6_I1_O) 0.124 16.263 f u_cpu/id_stage/flush_inst_req_buffer[1]_i_9/O
|
|
net (fo=32, routed) 0.531 16.794 u_cpu/if_stage/nextpc5
|
|
SLICE_X51Y27 f u_cpu/if_stage/fetch_pc_r[6]_i_4/I2
|
|
SLICE_X51Y27 LUT6 (Prop_lut6_I2_O) 0.124 16.918 r u_cpu/if_stage/fetch_pc_r[6]_i_4/O
|
|
net (fo=1, routed) 3.059 19.977 u_cpu/if_stage/fetch_pc_r[6]_i_4_n_0
|
|
SLICE_X114Y28 r u_cpu/if_stage/fetch_pc_r[6]_i_2/I2
|
|
SLICE_X114Y28 LUT6 (Prop_lut6_I2_O) 0.124 20.101 r u_cpu/if_stage/fetch_pc_r[6]_i_2/O
|
|
net (fo=1, routed) 0.441 20.542 u_cpu/if_stage/fetch_pc_r[6]_i_2_n_0
|
|
SLICE_X114Y25 r u_cpu/if_stage/fetch_pc_r[6]_i_1/I2
|
|
SLICE_X114Y25 LUT6 (Prop_lut6_I2_O) 0.124 20.666 r u_cpu/if_stage/fetch_pc_r[6]_i_1/O
|
|
net (fo=6, routed) 3.249 23.915 u_cpu/icache/tagv_ram_way[1].u/mem_reg_reg_2[2]
|
|
SLICE_X49Y33 r u_cpu/icache/tagv_ram_way[1].u/mem_reg_reg_i_8/I4
|
|
SLICE_X49Y33 LUT5 (Prop_lut5_I4_O) 0.124 24.039 r u_cpu/icache/tagv_ram_way[1].u/mem_reg_reg_i_8/O
|
|
net (fo=16, routed) 1.477 25.516 u_cpu/icache/data_ram_way[0].data_ram_bank[2].u/ADDRBWRADDR[2]
|
|
RAMB18_X2Y2 RAMB18E1 r u_cpu/icache/data_ram_way[0].data_ram_bank[2].u/mem_reg_reg/ADDRARDADDR[7]
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock cpu_clk rise edge) 30.323 30.323 r
|
|
clock source latency -5.674 24.648
|
|
propagated clock network latency
|
|
3.781 28.429
|
|
clock pessimism -0.418 28.011
|
|
clock uncertainty -0.074 27.937
|
|
RAMB18_X2Y2 RAMB18E1 (Setup_ramb18e1_CLKARDCLK_ADDRARDADDR[7])
|
|
-0.566 27.371 u_cpu/icache/data_ram_way[0].data_ram_bank[2].u/mem_reg_reg
|
|
-------------------------------------------------------------------
|
|
required time 27.371
|
|
arrival time -25.516
|
|
-------------------------------------------------------------------
|
|
slack 1.855
|
|
|
|
Slack (MET) : 1.855ns (required time - arrival time)
|
|
Source: u_cpu/addr_trans/data_vaddr_buffer_reg[14]/C
|
|
(rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns})
|
|
Destination: u_cpu/icache/data_ram_way[0].data_ram_bank[3].u/mem_reg_reg/ADDRARDADDR[7]
|
|
(rising edge-triggered cell RAMB18E1 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns})
|
|
Path Group: cpu_clk
|
|
Path Type: Setup (Max at Slow Process Corner)
|
|
Requirement: 30.323ns (cpu_clk rise@30.323ns - cpu_clk rise@0.000ns)
|
|
Data Path Delay: 27.741ns (logic 5.333ns (19.224%) route 22.408ns (80.776%))
|
|
Logic Levels: 26 (CARRY4=4 LUT3=2 LUT4=1 LUT5=2 LUT6=15 MUXF7=1 MUXF8=1)
|
|
Clock Path Skew: -0.087ns (DCD - SCD + CPR)
|
|
Destination Clock Delay (DCD): -1.893ns = ( 28.429 - 30.323 )
|
|
Source Clock Delay (SCD): -2.225ns
|
|
Clock Pessimism Removal (CPR): -0.418ns
|
|
Clock Uncertainty: 0.074ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Discrete Jitter (DJ): 0.130ns
|
|
Phase Error (PE): 0.000ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock cpu_clk rise edge) 0.000 0.000 r
|
|
clock source latency -6.275 -6.275
|
|
propagated clock network latency
|
|
4.051 -2.225
|
|
SLICE_X35Y35 FDRE 0.000 -2.225 r u_cpu/addr_trans/data_vaddr_buffer_reg[14]/C
|
|
SLICE_X35Y35 FDRE (Prop_fdre_C_Q) 0.456 -1.769 r u_cpu/addr_trans/data_vaddr_buffer_reg[14]/Q
|
|
net (fo=33, routed) 1.442 -0.326 u_cpu/addr_trans/tlb_entry/data_vaddr_buffer[2]
|
|
SLICE_X42Y40 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_226/I5
|
|
SLICE_X42Y40 LUT6 (Prop_lut6_I5_O) 0.124 -0.202 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_226/O
|
|
net (fo=1, routed) 0.000 -0.202 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_226_n_0
|
|
SLICE_X42Y40 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_111/S[0]
|
|
SLICE_X42Y40 CARRY4 (Prop_carry4_S[0]_CO[3])
|
|
0.513 0.311 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_111/CO[3]
|
|
net (fo=1, routed) 0.000 0.311 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_111_n_0
|
|
SLICE_X42Y41 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_32/CI
|
|
SLICE_X42Y41 CARRY4 (Prop_carry4_CI_CO[2])
|
|
0.229 0.540 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_32/CO[2]
|
|
net (fo=1, routed) 1.009 1.549 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_32_n_1
|
|
SLICE_X40Y47 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_9/I1
|
|
SLICE_X40Y47 LUT6 (Prop_lut6_I1_O) 0.310 1.859 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_9/O
|
|
net (fo=2, routed) 0.635 2.494 u_cpu/addr_trans/tlb_entry/match1[28]
|
|
SLICE_X38Y47 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/I2
|
|
SLICE_X38Y47 LUT4 (Prop_lut4_I2_O) 0.124 2.618 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/O
|
|
net (fo=2, routed) 0.667 3.285 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2_n_0
|
|
SLICE_X39Y47 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/I0
|
|
SLICE_X39Y47 LUT5 (Prop_lut5_I0_O) 0.124 3.409 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/O
|
|
net (fo=2, routed) 1.103 4.512 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2_n_0
|
|
SLICE_X38Y50 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/I0
|
|
SLICE_X38Y50 LUT6 (Prop_lut6_I0_O) 0.124 4.636 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/O
|
|
net (fo=89, routed) 1.162 5.797 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus[8]
|
|
SLICE_X42Y51 r u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_38__0/S
|
|
SLICE_X42Y51 MUXF7 (Prop_muxf7_S_O) 0.292 6.089 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_38__0/O
|
|
net (fo=1, routed) 0.000 6.089 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_38__0_n_0
|
|
SLICE_X42Y51 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_16__0/I1
|
|
SLICE_X42Y51 MUXF8 (Prop_muxf8_I1_O) 0.088 6.177 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_16__0/O
|
|
net (fo=1, routed) 0.957 7.134 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_16__0_n_0
|
|
SLICE_X42Y50 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7/I0
|
|
SLICE_X42Y50 LUT6 (Prop_lut6_I0_O) 0.319 7.453 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7/O
|
|
net (fo=1, routed) 0.435 7.888 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7_n_0
|
|
SLICE_X44Y50 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0/I5
|
|
SLICE_X44Y50 LUT6 (Prop_lut6_I5_O) 0.124 8.012 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0/O
|
|
net (fo=10, routed) 0.740 8.753 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0_n_0
|
|
SLICE_X44Y50 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[5]_i_1__0/I3
|
|
SLICE_X44Y50 LUT6 (Prop_lut6_I3_O) 0.124 8.877 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[5]_i_1__0/O
|
|
net (fo=6, routed) 0.845 9.722 u_cpu/u_csr/ms_to_ws_bus[13]
|
|
SLICE_X50Y46 r u_cpu/u_csr/write_buffer_way[1]_i_18/I3
|
|
SLICE_X50Y46 LUT6 (Prop_lut6_I3_O) 0.124 9.846 r u_cpu/u_csr/write_buffer_way[1]_i_18/O
|
|
net (fo=1, routed) 0.000 9.846 u_cpu/u_csr/write_buffer_way[1]_i_18_n_0
|
|
SLICE_X50Y46 r u_cpu/u_csr/write_buffer_way_reg[1]_i_11/S[0]
|
|
SLICE_X50Y46 CARRY4 (Prop_carry4_S[0]_CO[3])
|
|
0.532 10.378 r u_cpu/u_csr/write_buffer_way_reg[1]_i_11/CO[3]
|
|
net (fo=1, routed) 0.000 10.378 u_cpu/u_csr/write_buffer_way_reg[1]_i_11_n_0
|
|
SLICE_X50Y47 r u_cpu/u_csr/write_buffer_way_reg[1]_i_9/CI
|
|
SLICE_X50Y47 CARRY4 (Prop_carry4_CI_CO[1])
|
|
0.157 10.535 f u_cpu/u_csr/write_buffer_way_reg[1]_i_9/CO[1]
|
|
net (fo=2, routed) 0.791 11.326 u_cpu/wb_stage/CO[0]
|
|
SLICE_X46Y39 f u_cpu/wb_stage/write_buffer_way[1]_i_5/I1
|
|
SLICE_X46Y39 LUT6 (Prop_lut6_I1_O) 0.329 11.655 r u_cpu/wb_stage/write_buffer_way[1]_i_5/O
|
|
net (fo=7, routed) 0.762 12.417 u_cpu/addr_trans/tlb_entry/sc_cancel_req
|
|
SLICE_X46Y35 r u_cpu/addr_trans/tlb_entry/main_state[0]_i_3/I1
|
|
SLICE_X46Y35 LUT3 (Prop_lut3_I1_O) 0.124 12.541 r u_cpu/addr_trans/tlb_entry/main_state[0]_i_3/O
|
|
net (fo=3, routed) 0.719 13.260 u_cpu/dcache/main_state_reg[0]_2
|
|
SLICE_X43Y31 r u_cpu/dcache/ds_to_es_bus_r[235]_i_10/I3
|
|
SLICE_X43Y31 LUT6 (Prop_lut6_I3_O) 0.124 13.384 r u_cpu/dcache/ds_to_es_bus_r[235]_i_10/O
|
|
net (fo=3, routed) 0.415 13.799 u_cpu/mem_stage/data_data_ok
|
|
SLICE_X43Y30 r u_cpu/mem_stage/flush_inst_req_buffer[1]_i_15/I0
|
|
SLICE_X43Y30 LUT3 (Prop_lut3_I0_O) 0.124 13.923 r u_cpu/mem_stage/flush_inst_req_buffer[1]_i_15/O
|
|
net (fo=2, routed) 0.833 14.756 u_cpu/mem_stage/es_to_ms_bus_r_reg[70]_1
|
|
SLICE_X48Y30 r u_cpu/mem_stage/flush_inst_req_buffer[1]_i_14/I0
|
|
SLICE_X48Y30 LUT6 (Prop_lut6_I0_O) 0.124 14.880 r u_cpu/mem_stage/flush_inst_req_buffer[1]_i_14/O
|
|
net (fo=1, routed) 0.651 15.532 u_cpu/mem_stage/ms_ready_go
|
|
SLICE_X48Y25 r u_cpu/mem_stage/flush_inst_req_buffer[1]_i_13/I4
|
|
SLICE_X48Y25 LUT6 (Prop_lut6_I4_O) 0.124 15.656 r u_cpu/mem_stage/flush_inst_req_buffer[1]_i_13/O
|
|
net (fo=3, routed) 0.483 16.139 u_cpu/id_stage/flush_inst_req_buffer[31]_i_6
|
|
SLICE_X50Y25 r u_cpu/id_stage/flush_inst_req_buffer[1]_i_9/I1
|
|
SLICE_X50Y25 LUT6 (Prop_lut6_I1_O) 0.124 16.263 r u_cpu/id_stage/flush_inst_req_buffer[1]_i_9/O
|
|
net (fo=32, routed) 0.531 16.794 u_cpu/if_stage/nextpc5
|
|
SLICE_X51Y27 r u_cpu/if_stage/fetch_pc_r[6]_i_4/I2
|
|
SLICE_X51Y27 LUT6 (Prop_lut6_I2_O) 0.124 16.918 r u_cpu/if_stage/fetch_pc_r[6]_i_4/O
|
|
net (fo=1, routed) 3.059 19.977 u_cpu/if_stage/fetch_pc_r[6]_i_4_n_0
|
|
SLICE_X114Y28 r u_cpu/if_stage/fetch_pc_r[6]_i_2/I2
|
|
SLICE_X114Y28 LUT6 (Prop_lut6_I2_O) 0.124 20.101 r u_cpu/if_stage/fetch_pc_r[6]_i_2/O
|
|
net (fo=1, routed) 0.441 20.542 u_cpu/if_stage/fetch_pc_r[6]_i_2_n_0
|
|
SLICE_X114Y25 r u_cpu/if_stage/fetch_pc_r[6]_i_1/I2
|
|
SLICE_X114Y25 LUT6 (Prop_lut6_I2_O) 0.124 20.666 r u_cpu/if_stage/fetch_pc_r[6]_i_1/O
|
|
net (fo=6, routed) 3.249 23.915 u_cpu/icache/tagv_ram_way[1].u/mem_reg_reg_2[2]
|
|
SLICE_X49Y33 r u_cpu/icache/tagv_ram_way[1].u/mem_reg_reg_i_8/I4
|
|
SLICE_X49Y33 LUT5 (Prop_lut5_I4_O) 0.124 24.039 r u_cpu/icache/tagv_ram_way[1].u/mem_reg_reg_i_8/O
|
|
net (fo=16, routed) 1.477 25.516 u_cpu/icache/data_ram_way[0].data_ram_bank[3].u/ADDRBWRADDR[2]
|
|
RAMB18_X2Y3 RAMB18E1 r u_cpu/icache/data_ram_way[0].data_ram_bank[3].u/mem_reg_reg/ADDRARDADDR[7]
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock cpu_clk rise edge) 30.323 30.323 r
|
|
clock source latency -5.674 24.648
|
|
propagated clock network latency
|
|
3.781 28.429
|
|
clock pessimism -0.418 28.011
|
|
clock uncertainty -0.074 27.937
|
|
RAMB18_X2Y3 RAMB18E1 (Setup_ramb18e1_CLKARDCLK_ADDRARDADDR[7])
|
|
-0.566 27.371 u_cpu/icache/data_ram_way[0].data_ram_bank[3].u/mem_reg_reg
|
|
-------------------------------------------------------------------
|
|
required time 27.371
|
|
arrival time -25.516
|
|
-------------------------------------------------------------------
|
|
slack 1.855
|
|
|
|
Slack (MET) : 1.855ns (required time - arrival time)
|
|
Source: u_cpu/addr_trans/data_vaddr_buffer_reg[14]/C
|
|
(rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns})
|
|
Destination: u_cpu/icache/data_ram_way[0].data_ram_bank[3].u/mem_reg_reg/ADDRARDADDR[7]
|
|
(rising edge-triggered cell RAMB18E1 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns})
|
|
Path Group: cpu_clk
|
|
Path Type: Setup (Max at Slow Process Corner)
|
|
Requirement: 30.323ns (cpu_clk rise@30.323ns - cpu_clk rise@0.000ns)
|
|
Data Path Delay: 27.741ns (logic 5.333ns (19.224%) route 22.408ns (80.776%))
|
|
Logic Levels: 26 (CARRY4=4 LUT3=2 LUT4=1 LUT5=2 LUT6=15 MUXF7=1 MUXF8=1)
|
|
Clock Path Skew: -0.087ns (DCD - SCD + CPR)
|
|
Destination Clock Delay (DCD): -1.893ns = ( 28.429 - 30.323 )
|
|
Source Clock Delay (SCD): -2.225ns
|
|
Clock Pessimism Removal (CPR): -0.418ns
|
|
Clock Uncertainty: 0.074ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Discrete Jitter (DJ): 0.130ns
|
|
Phase Error (PE): 0.000ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock cpu_clk rise edge) 0.000 0.000 r
|
|
clock source latency -6.275 -6.275
|
|
propagated clock network latency
|
|
4.051 -2.225
|
|
SLICE_X35Y35 FDRE 0.000 -2.225 r u_cpu/addr_trans/data_vaddr_buffer_reg[14]/C
|
|
SLICE_X35Y35 FDRE (Prop_fdre_C_Q) 0.456 -1.769 r u_cpu/addr_trans/data_vaddr_buffer_reg[14]/Q
|
|
net (fo=33, routed) 1.442 -0.326 u_cpu/addr_trans/tlb_entry/data_vaddr_buffer[2]
|
|
SLICE_X42Y40 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_226/I5
|
|
SLICE_X42Y40 LUT6 (Prop_lut6_I5_O) 0.124 -0.202 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_226/O
|
|
net (fo=1, routed) 0.000 -0.202 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_226_n_0
|
|
SLICE_X42Y40 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_111/S[0]
|
|
SLICE_X42Y40 CARRY4 (Prop_carry4_S[0]_CO[3])
|
|
0.513 0.311 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_111/CO[3]
|
|
net (fo=1, routed) 0.000 0.311 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_111_n_0
|
|
SLICE_X42Y41 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_32/CI
|
|
SLICE_X42Y41 CARRY4 (Prop_carry4_CI_CO[2])
|
|
0.229 0.540 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_32/CO[2]
|
|
net (fo=1, routed) 1.009 1.549 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_32_n_1
|
|
SLICE_X40Y47 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_9/I1
|
|
SLICE_X40Y47 LUT6 (Prop_lut6_I1_O) 0.310 1.859 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_9/O
|
|
net (fo=2, routed) 0.635 2.494 u_cpu/addr_trans/tlb_entry/match1[28]
|
|
SLICE_X38Y47 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/I2
|
|
SLICE_X38Y47 LUT4 (Prop_lut4_I2_O) 0.124 2.618 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/O
|
|
net (fo=2, routed) 0.667 3.285 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2_n_0
|
|
SLICE_X39Y47 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/I0
|
|
SLICE_X39Y47 LUT5 (Prop_lut5_I0_O) 0.124 3.409 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/O
|
|
net (fo=2, routed) 1.103 4.512 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2_n_0
|
|
SLICE_X38Y50 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/I0
|
|
SLICE_X38Y50 LUT6 (Prop_lut6_I0_O) 0.124 4.636 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/O
|
|
net (fo=89, routed) 1.162 5.797 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus[8]
|
|
SLICE_X42Y51 r u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_38__0/S
|
|
SLICE_X42Y51 MUXF7 (Prop_muxf7_S_O) 0.292 6.089 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_38__0/O
|
|
net (fo=1, routed) 0.000 6.089 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_38__0_n_0
|
|
SLICE_X42Y51 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_16__0/I1
|
|
SLICE_X42Y51 MUXF8 (Prop_muxf8_I1_O) 0.088 6.177 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_16__0/O
|
|
net (fo=1, routed) 0.957 7.134 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_16__0_n_0
|
|
SLICE_X42Y50 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7/I0
|
|
SLICE_X42Y50 LUT6 (Prop_lut6_I0_O) 0.319 7.453 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7/O
|
|
net (fo=1, routed) 0.435 7.888 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7_n_0
|
|
SLICE_X44Y50 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0/I5
|
|
SLICE_X44Y50 LUT6 (Prop_lut6_I5_O) 0.124 8.012 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0/O
|
|
net (fo=10, routed) 0.740 8.753 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0_n_0
|
|
SLICE_X44Y50 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[5]_i_1__0/I3
|
|
SLICE_X44Y50 LUT6 (Prop_lut6_I3_O) 0.124 8.877 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[5]_i_1__0/O
|
|
net (fo=6, routed) 0.845 9.722 u_cpu/u_csr/ms_to_ws_bus[13]
|
|
SLICE_X50Y46 f u_cpu/u_csr/write_buffer_way[1]_i_18/I3
|
|
SLICE_X50Y46 LUT6 (Prop_lut6_I3_O) 0.124 9.846 r u_cpu/u_csr/write_buffer_way[1]_i_18/O
|
|
net (fo=1, routed) 0.000 9.846 u_cpu/u_csr/write_buffer_way[1]_i_18_n_0
|
|
SLICE_X50Y46 r u_cpu/u_csr/write_buffer_way_reg[1]_i_11/S[0]
|
|
SLICE_X50Y46 CARRY4 (Prop_carry4_S[0]_CO[3])
|
|
0.532 10.378 r u_cpu/u_csr/write_buffer_way_reg[1]_i_11/CO[3]
|
|
net (fo=1, routed) 0.000 10.378 u_cpu/u_csr/write_buffer_way_reg[1]_i_11_n_0
|
|
SLICE_X50Y47 r u_cpu/u_csr/write_buffer_way_reg[1]_i_9/CI
|
|
SLICE_X50Y47 CARRY4 (Prop_carry4_CI_CO[1])
|
|
0.157 10.535 f u_cpu/u_csr/write_buffer_way_reg[1]_i_9/CO[1]
|
|
net (fo=2, routed) 0.791 11.326 u_cpu/wb_stage/CO[0]
|
|
SLICE_X46Y39 f u_cpu/wb_stage/write_buffer_way[1]_i_5/I1
|
|
SLICE_X46Y39 LUT6 (Prop_lut6_I1_O) 0.329 11.655 r u_cpu/wb_stage/write_buffer_way[1]_i_5/O
|
|
net (fo=7, routed) 0.762 12.417 u_cpu/addr_trans/tlb_entry/sc_cancel_req
|
|
SLICE_X46Y35 r u_cpu/addr_trans/tlb_entry/main_state[0]_i_3/I1
|
|
SLICE_X46Y35 LUT3 (Prop_lut3_I1_O) 0.124 12.541 r u_cpu/addr_trans/tlb_entry/main_state[0]_i_3/O
|
|
net (fo=3, routed) 0.719 13.260 u_cpu/dcache/main_state_reg[0]_2
|
|
SLICE_X43Y31 r u_cpu/dcache/ds_to_es_bus_r[235]_i_10/I3
|
|
SLICE_X43Y31 LUT6 (Prop_lut6_I3_O) 0.124 13.384 r u_cpu/dcache/ds_to_es_bus_r[235]_i_10/O
|
|
net (fo=3, routed) 0.415 13.799 u_cpu/mem_stage/data_data_ok
|
|
SLICE_X43Y30 r u_cpu/mem_stage/flush_inst_req_buffer[1]_i_15/I0
|
|
SLICE_X43Y30 LUT3 (Prop_lut3_I0_O) 0.124 13.923 r u_cpu/mem_stage/flush_inst_req_buffer[1]_i_15/O
|
|
net (fo=2, routed) 0.833 14.756 u_cpu/mem_stage/es_to_ms_bus_r_reg[70]_1
|
|
SLICE_X48Y30 r u_cpu/mem_stage/flush_inst_req_buffer[1]_i_14/I0
|
|
SLICE_X48Y30 LUT6 (Prop_lut6_I0_O) 0.124 14.880 r u_cpu/mem_stage/flush_inst_req_buffer[1]_i_14/O
|
|
net (fo=1, routed) 0.651 15.532 u_cpu/mem_stage/ms_ready_go
|
|
SLICE_X48Y25 r u_cpu/mem_stage/flush_inst_req_buffer[1]_i_13/I4
|
|
SLICE_X48Y25 LUT6 (Prop_lut6_I4_O) 0.124 15.656 r u_cpu/mem_stage/flush_inst_req_buffer[1]_i_13/O
|
|
net (fo=3, routed) 0.483 16.139 u_cpu/id_stage/flush_inst_req_buffer[31]_i_6
|
|
SLICE_X50Y25 r u_cpu/id_stage/flush_inst_req_buffer[1]_i_9/I1
|
|
SLICE_X50Y25 LUT6 (Prop_lut6_I1_O) 0.124 16.263 r u_cpu/id_stage/flush_inst_req_buffer[1]_i_9/O
|
|
net (fo=32, routed) 0.531 16.794 u_cpu/if_stage/nextpc5
|
|
SLICE_X51Y27 r u_cpu/if_stage/fetch_pc_r[6]_i_4/I2
|
|
SLICE_X51Y27 LUT6 (Prop_lut6_I2_O) 0.124 16.918 r u_cpu/if_stage/fetch_pc_r[6]_i_4/O
|
|
net (fo=1, routed) 3.059 19.977 u_cpu/if_stage/fetch_pc_r[6]_i_4_n_0
|
|
SLICE_X114Y28 r u_cpu/if_stage/fetch_pc_r[6]_i_2/I2
|
|
SLICE_X114Y28 LUT6 (Prop_lut6_I2_O) 0.124 20.101 r u_cpu/if_stage/fetch_pc_r[6]_i_2/O
|
|
net (fo=1, routed) 0.441 20.542 u_cpu/if_stage/fetch_pc_r[6]_i_2_n_0
|
|
SLICE_X114Y25 r u_cpu/if_stage/fetch_pc_r[6]_i_1/I2
|
|
SLICE_X114Y25 LUT6 (Prop_lut6_I2_O) 0.124 20.666 r u_cpu/if_stage/fetch_pc_r[6]_i_1/O
|
|
net (fo=6, routed) 3.249 23.915 u_cpu/icache/tagv_ram_way[1].u/mem_reg_reg_2[2]
|
|
SLICE_X49Y33 r u_cpu/icache/tagv_ram_way[1].u/mem_reg_reg_i_8/I4
|
|
SLICE_X49Y33 LUT5 (Prop_lut5_I4_O) 0.124 24.039 r u_cpu/icache/tagv_ram_way[1].u/mem_reg_reg_i_8/O
|
|
net (fo=16, routed) 1.477 25.516 u_cpu/icache/data_ram_way[0].data_ram_bank[3].u/ADDRBWRADDR[2]
|
|
RAMB18_X2Y3 RAMB18E1 r u_cpu/icache/data_ram_way[0].data_ram_bank[3].u/mem_reg_reg/ADDRARDADDR[7]
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock cpu_clk rise edge) 30.323 30.323 r
|
|
clock source latency -5.674 24.648
|
|
propagated clock network latency
|
|
3.781 28.429
|
|
clock pessimism -0.418 28.011
|
|
clock uncertainty -0.074 27.937
|
|
RAMB18_X2Y3 RAMB18E1 (Setup_ramb18e1_CLKARDCLK_ADDRARDADDR[7])
|
|
-0.566 27.371 u_cpu/icache/data_ram_way[0].data_ram_bank[3].u/mem_reg_reg
|
|
-------------------------------------------------------------------
|
|
required time 27.371
|
|
arrival time -25.516
|
|
-------------------------------------------------------------------
|
|
slack 1.855
|
|
|
|
Slack (MET) : 1.855ns (required time - arrival time)
|
|
Source: u_cpu/addr_trans/data_vaddr_buffer_reg[14]/C
|
|
(rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns})
|
|
Destination: u_cpu/icache/data_ram_way[0].data_ram_bank[3].u/mem_reg_reg/ADDRARDADDR[7]
|
|
(rising edge-triggered cell RAMB18E1 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns})
|
|
Path Group: cpu_clk
|
|
Path Type: Setup (Max at Slow Process Corner)
|
|
Requirement: 30.323ns (cpu_clk rise@30.323ns - cpu_clk rise@0.000ns)
|
|
Data Path Delay: 27.741ns (logic 5.333ns (19.224%) route 22.408ns (80.776%))
|
|
Logic Levels: 26 (CARRY4=4 LUT3=2 LUT4=1 LUT5=2 LUT6=15 MUXF7=1 MUXF8=1)
|
|
Clock Path Skew: -0.087ns (DCD - SCD + CPR)
|
|
Destination Clock Delay (DCD): -1.893ns = ( 28.429 - 30.323 )
|
|
Source Clock Delay (SCD): -2.225ns
|
|
Clock Pessimism Removal (CPR): -0.418ns
|
|
Clock Uncertainty: 0.074ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Discrete Jitter (DJ): 0.130ns
|
|
Phase Error (PE): 0.000ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock cpu_clk rise edge) 0.000 0.000 r
|
|
clock source latency -6.275 -6.275
|
|
propagated clock network latency
|
|
4.051 -2.225
|
|
SLICE_X35Y35 FDRE 0.000 -2.225 r u_cpu/addr_trans/data_vaddr_buffer_reg[14]/C
|
|
SLICE_X35Y35 FDRE (Prop_fdre_C_Q) 0.456 -1.769 r u_cpu/addr_trans/data_vaddr_buffer_reg[14]/Q
|
|
net (fo=33, routed) 1.442 -0.326 u_cpu/addr_trans/tlb_entry/data_vaddr_buffer[2]
|
|
SLICE_X42Y40 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_226/I5
|
|
SLICE_X42Y40 LUT6 (Prop_lut6_I5_O) 0.124 -0.202 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_226/O
|
|
net (fo=1, routed) 0.000 -0.202 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_226_n_0
|
|
SLICE_X42Y40 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_111/S[0]
|
|
SLICE_X42Y40 CARRY4 (Prop_carry4_S[0]_CO[3])
|
|
0.513 0.311 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_111/CO[3]
|
|
net (fo=1, routed) 0.000 0.311 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_111_n_0
|
|
SLICE_X42Y41 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_32/CI
|
|
SLICE_X42Y41 CARRY4 (Prop_carry4_CI_CO[2])
|
|
0.229 0.540 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_32/CO[2]
|
|
net (fo=1, routed) 1.009 1.549 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_32_n_1
|
|
SLICE_X40Y47 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_9/I1
|
|
SLICE_X40Y47 LUT6 (Prop_lut6_I1_O) 0.310 1.859 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_9/O
|
|
net (fo=2, routed) 0.635 2.494 u_cpu/addr_trans/tlb_entry/match1[28]
|
|
SLICE_X38Y47 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/I2
|
|
SLICE_X38Y47 LUT4 (Prop_lut4_I2_O) 0.124 2.618 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/O
|
|
net (fo=2, routed) 0.667 3.285 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2_n_0
|
|
SLICE_X39Y47 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/I0
|
|
SLICE_X39Y47 LUT5 (Prop_lut5_I0_O) 0.124 3.409 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/O
|
|
net (fo=2, routed) 1.103 4.512 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2_n_0
|
|
SLICE_X38Y50 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/I0
|
|
SLICE_X38Y50 LUT6 (Prop_lut6_I0_O) 0.124 4.636 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/O
|
|
net (fo=89, routed) 1.162 5.797 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus[8]
|
|
SLICE_X42Y51 r u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_38__0/S
|
|
SLICE_X42Y51 MUXF7 (Prop_muxf7_S_O) 0.292 6.089 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_38__0/O
|
|
net (fo=1, routed) 0.000 6.089 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_38__0_n_0
|
|
SLICE_X42Y51 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_16__0/I1
|
|
SLICE_X42Y51 MUXF8 (Prop_muxf8_I1_O) 0.088 6.177 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_16__0/O
|
|
net (fo=1, routed) 0.957 7.134 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_16__0_n_0
|
|
SLICE_X42Y50 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7/I0
|
|
SLICE_X42Y50 LUT6 (Prop_lut6_I0_O) 0.319 7.453 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7/O
|
|
net (fo=1, routed) 0.435 7.888 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7_n_0
|
|
SLICE_X44Y50 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0/I5
|
|
SLICE_X44Y50 LUT6 (Prop_lut6_I5_O) 0.124 8.012 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0/O
|
|
net (fo=10, routed) 0.740 8.753 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0_n_0
|
|
SLICE_X44Y50 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[5]_i_1__0/I3
|
|
SLICE_X44Y50 LUT6 (Prop_lut6_I3_O) 0.124 8.877 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[5]_i_1__0/O
|
|
net (fo=6, routed) 0.845 9.722 u_cpu/u_csr/ms_to_ws_bus[13]
|
|
SLICE_X50Y46 r u_cpu/u_csr/write_buffer_way[1]_i_18/I3
|
|
SLICE_X50Y46 LUT6 (Prop_lut6_I3_O) 0.124 9.846 f u_cpu/u_csr/write_buffer_way[1]_i_18/O
|
|
net (fo=1, routed) 0.000 9.846 u_cpu/u_csr/write_buffer_way[1]_i_18_n_0
|
|
SLICE_X50Y46 f u_cpu/u_csr/write_buffer_way_reg[1]_i_11/S[0]
|
|
SLICE_X50Y46 CARRY4 (Prop_carry4_S[0]_CO[3])
|
|
0.532 10.378 r u_cpu/u_csr/write_buffer_way_reg[1]_i_11/CO[3]
|
|
net (fo=1, routed) 0.000 10.378 u_cpu/u_csr/write_buffer_way_reg[1]_i_11_n_0
|
|
SLICE_X50Y47 r u_cpu/u_csr/write_buffer_way_reg[1]_i_9/CI
|
|
SLICE_X50Y47 CARRY4 (Prop_carry4_CI_CO[1])
|
|
0.157 10.535 f u_cpu/u_csr/write_buffer_way_reg[1]_i_9/CO[1]
|
|
net (fo=2, routed) 0.791 11.326 u_cpu/wb_stage/CO[0]
|
|
SLICE_X46Y39 f u_cpu/wb_stage/write_buffer_way[1]_i_5/I1
|
|
SLICE_X46Y39 LUT6 (Prop_lut6_I1_O) 0.329 11.655 r u_cpu/wb_stage/write_buffer_way[1]_i_5/O
|
|
net (fo=7, routed) 0.762 12.417 u_cpu/addr_trans/tlb_entry/sc_cancel_req
|
|
SLICE_X46Y35 r u_cpu/addr_trans/tlb_entry/main_state[0]_i_3/I1
|
|
SLICE_X46Y35 LUT3 (Prop_lut3_I1_O) 0.124 12.541 r u_cpu/addr_trans/tlb_entry/main_state[0]_i_3/O
|
|
net (fo=3, routed) 0.719 13.260 u_cpu/dcache/main_state_reg[0]_2
|
|
SLICE_X43Y31 r u_cpu/dcache/ds_to_es_bus_r[235]_i_10/I3
|
|
SLICE_X43Y31 LUT6 (Prop_lut6_I3_O) 0.124 13.384 r u_cpu/dcache/ds_to_es_bus_r[235]_i_10/O
|
|
net (fo=3, routed) 0.415 13.799 u_cpu/mem_stage/data_data_ok
|
|
SLICE_X43Y30 r u_cpu/mem_stage/flush_inst_req_buffer[1]_i_15/I0
|
|
SLICE_X43Y30 LUT3 (Prop_lut3_I0_O) 0.124 13.923 r u_cpu/mem_stage/flush_inst_req_buffer[1]_i_15/O
|
|
net (fo=2, routed) 0.833 14.756 u_cpu/mem_stage/es_to_ms_bus_r_reg[70]_1
|
|
SLICE_X48Y30 r u_cpu/mem_stage/flush_inst_req_buffer[1]_i_14/I0
|
|
SLICE_X48Y30 LUT6 (Prop_lut6_I0_O) 0.124 14.880 r u_cpu/mem_stage/flush_inst_req_buffer[1]_i_14/O
|
|
net (fo=1, routed) 0.651 15.532 u_cpu/mem_stage/ms_ready_go
|
|
SLICE_X48Y25 r u_cpu/mem_stage/flush_inst_req_buffer[1]_i_13/I4
|
|
SLICE_X48Y25 LUT6 (Prop_lut6_I4_O) 0.124 15.656 r u_cpu/mem_stage/flush_inst_req_buffer[1]_i_13/O
|
|
net (fo=3, routed) 0.483 16.139 u_cpu/id_stage/flush_inst_req_buffer[31]_i_6
|
|
SLICE_X50Y25 r u_cpu/id_stage/flush_inst_req_buffer[1]_i_9/I1
|
|
SLICE_X50Y25 LUT6 (Prop_lut6_I1_O) 0.124 16.263 r u_cpu/id_stage/flush_inst_req_buffer[1]_i_9/O
|
|
net (fo=32, routed) 0.531 16.794 u_cpu/if_stage/nextpc5
|
|
SLICE_X51Y27 r u_cpu/if_stage/fetch_pc_r[6]_i_4/I2
|
|
SLICE_X51Y27 LUT6 (Prop_lut6_I2_O) 0.124 16.918 r u_cpu/if_stage/fetch_pc_r[6]_i_4/O
|
|
net (fo=1, routed) 3.059 19.977 u_cpu/if_stage/fetch_pc_r[6]_i_4_n_0
|
|
SLICE_X114Y28 r u_cpu/if_stage/fetch_pc_r[6]_i_2/I2
|
|
SLICE_X114Y28 LUT6 (Prop_lut6_I2_O) 0.124 20.101 r u_cpu/if_stage/fetch_pc_r[6]_i_2/O
|
|
net (fo=1, routed) 0.441 20.542 u_cpu/if_stage/fetch_pc_r[6]_i_2_n_0
|
|
SLICE_X114Y25 r u_cpu/if_stage/fetch_pc_r[6]_i_1/I2
|
|
SLICE_X114Y25 LUT6 (Prop_lut6_I2_O) 0.124 20.666 r u_cpu/if_stage/fetch_pc_r[6]_i_1/O
|
|
net (fo=6, routed) 3.249 23.915 u_cpu/icache/tagv_ram_way[1].u/mem_reg_reg_2[2]
|
|
SLICE_X49Y33 r u_cpu/icache/tagv_ram_way[1].u/mem_reg_reg_i_8/I4
|
|
SLICE_X49Y33 LUT5 (Prop_lut5_I4_O) 0.124 24.039 r u_cpu/icache/tagv_ram_way[1].u/mem_reg_reg_i_8/O
|
|
net (fo=16, routed) 1.477 25.516 u_cpu/icache/data_ram_way[0].data_ram_bank[3].u/ADDRBWRADDR[2]
|
|
RAMB18_X2Y3 RAMB18E1 r u_cpu/icache/data_ram_way[0].data_ram_bank[3].u/mem_reg_reg/ADDRARDADDR[7]
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock cpu_clk rise edge) 30.323 30.323 r
|
|
clock source latency -5.674 24.648
|
|
propagated clock network latency
|
|
3.781 28.429
|
|
clock pessimism -0.418 28.011
|
|
clock uncertainty -0.074 27.937
|
|
RAMB18_X2Y3 RAMB18E1 (Setup_ramb18e1_CLKARDCLK_ADDRARDADDR[7])
|
|
-0.566 27.371 u_cpu/icache/data_ram_way[0].data_ram_bank[3].u/mem_reg_reg
|
|
-------------------------------------------------------------------
|
|
required time 27.371
|
|
arrival time -25.516
|
|
-------------------------------------------------------------------
|
|
slack 1.855
|
|
|
|
Slack (MET) : 1.855ns (required time - arrival time)
|
|
Source: u_cpu/addr_trans/data_vaddr_buffer_reg[14]/C
|
|
(rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns})
|
|
Destination: u_cpu/icache/data_ram_way[0].data_ram_bank[3].u/mem_reg_reg/ADDRARDADDR[7]
|
|
(rising edge-triggered cell RAMB18E1 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns})
|
|
Path Group: cpu_clk
|
|
Path Type: Setup (Max at Slow Process Corner)
|
|
Requirement: 30.323ns (cpu_clk rise@30.323ns - cpu_clk rise@0.000ns)
|
|
Data Path Delay: 27.741ns (logic 5.333ns (19.224%) route 22.408ns (80.776%))
|
|
Logic Levels: 26 (CARRY4=4 LUT3=2 LUT4=1 LUT5=2 LUT6=15 MUXF7=1 MUXF8=1)
|
|
Clock Path Skew: -0.087ns (DCD - SCD + CPR)
|
|
Destination Clock Delay (DCD): -1.893ns = ( 28.429 - 30.323 )
|
|
Source Clock Delay (SCD): -2.225ns
|
|
Clock Pessimism Removal (CPR): -0.418ns
|
|
Clock Uncertainty: 0.074ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Discrete Jitter (DJ): 0.130ns
|
|
Phase Error (PE): 0.000ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock cpu_clk rise edge) 0.000 0.000 r
|
|
clock source latency -6.275 -6.275
|
|
propagated clock network latency
|
|
4.051 -2.225
|
|
SLICE_X35Y35 FDRE 0.000 -2.225 r u_cpu/addr_trans/data_vaddr_buffer_reg[14]/C
|
|
SLICE_X35Y35 FDRE (Prop_fdre_C_Q) 0.456 -1.769 r u_cpu/addr_trans/data_vaddr_buffer_reg[14]/Q
|
|
net (fo=33, routed) 1.442 -0.326 u_cpu/addr_trans/tlb_entry/data_vaddr_buffer[2]
|
|
SLICE_X42Y40 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_226/I5
|
|
SLICE_X42Y40 LUT6 (Prop_lut6_I5_O) 0.124 -0.202 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_226/O
|
|
net (fo=1, routed) 0.000 -0.202 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_226_n_0
|
|
SLICE_X42Y40 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_111/S[0]
|
|
SLICE_X42Y40 CARRY4 (Prop_carry4_S[0]_CO[3])
|
|
0.513 0.311 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_111/CO[3]
|
|
net (fo=1, routed) 0.000 0.311 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_111_n_0
|
|
SLICE_X42Y41 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_32/CI
|
|
SLICE_X42Y41 CARRY4 (Prop_carry4_CI_CO[2])
|
|
0.229 0.540 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_32/CO[2]
|
|
net (fo=1, routed) 1.009 1.549 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_32_n_1
|
|
SLICE_X40Y47 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_9/I1
|
|
SLICE_X40Y47 LUT6 (Prop_lut6_I1_O) 0.310 1.859 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_9/O
|
|
net (fo=2, routed) 0.635 2.494 u_cpu/addr_trans/tlb_entry/match1[28]
|
|
SLICE_X38Y47 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/I2
|
|
SLICE_X38Y47 LUT4 (Prop_lut4_I2_O) 0.124 2.618 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/O
|
|
net (fo=2, routed) 0.667 3.285 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2_n_0
|
|
SLICE_X39Y47 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/I0
|
|
SLICE_X39Y47 LUT5 (Prop_lut5_I0_O) 0.124 3.409 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/O
|
|
net (fo=2, routed) 1.103 4.512 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2_n_0
|
|
SLICE_X38Y50 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/I0
|
|
SLICE_X38Y50 LUT6 (Prop_lut6_I0_O) 0.124 4.636 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/O
|
|
net (fo=89, routed) 1.162 5.797 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus[8]
|
|
SLICE_X42Y51 r u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_38__0/S
|
|
SLICE_X42Y51 MUXF7 (Prop_muxf7_S_O) 0.292 6.089 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_38__0/O
|
|
net (fo=1, routed) 0.000 6.089 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_38__0_n_0
|
|
SLICE_X42Y51 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_16__0/I1
|
|
SLICE_X42Y51 MUXF8 (Prop_muxf8_I1_O) 0.088 6.177 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_16__0/O
|
|
net (fo=1, routed) 0.957 7.134 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_16__0_n_0
|
|
SLICE_X42Y50 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7/I0
|
|
SLICE_X42Y50 LUT6 (Prop_lut6_I0_O) 0.319 7.453 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7/O
|
|
net (fo=1, routed) 0.435 7.888 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7_n_0
|
|
SLICE_X44Y50 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0/I5
|
|
SLICE_X44Y50 LUT6 (Prop_lut6_I5_O) 0.124 8.012 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0/O
|
|
net (fo=10, routed) 0.740 8.753 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0_n_0
|
|
SLICE_X44Y50 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[5]_i_1__0/I3
|
|
SLICE_X44Y50 LUT6 (Prop_lut6_I3_O) 0.124 8.877 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[5]_i_1__0/O
|
|
net (fo=6, routed) 0.845 9.722 u_cpu/u_csr/ms_to_ws_bus[13]
|
|
SLICE_X50Y46 f u_cpu/u_csr/write_buffer_way[1]_i_18/I3
|
|
SLICE_X50Y46 LUT6 (Prop_lut6_I3_O) 0.124 9.846 f u_cpu/u_csr/write_buffer_way[1]_i_18/O
|
|
net (fo=1, routed) 0.000 9.846 u_cpu/u_csr/write_buffer_way[1]_i_18_n_0
|
|
SLICE_X50Y46 f u_cpu/u_csr/write_buffer_way_reg[1]_i_11/S[0]
|
|
SLICE_X50Y46 CARRY4 (Prop_carry4_S[0]_CO[3])
|
|
0.532 10.378 r u_cpu/u_csr/write_buffer_way_reg[1]_i_11/CO[3]
|
|
net (fo=1, routed) 0.000 10.378 u_cpu/u_csr/write_buffer_way_reg[1]_i_11_n_0
|
|
SLICE_X50Y47 r u_cpu/u_csr/write_buffer_way_reg[1]_i_9/CI
|
|
SLICE_X50Y47 CARRY4 (Prop_carry4_CI_CO[1])
|
|
0.157 10.535 f u_cpu/u_csr/write_buffer_way_reg[1]_i_9/CO[1]
|
|
net (fo=2, routed) 0.791 11.326 u_cpu/wb_stage/CO[0]
|
|
SLICE_X46Y39 f u_cpu/wb_stage/write_buffer_way[1]_i_5/I1
|
|
SLICE_X46Y39 LUT6 (Prop_lut6_I1_O) 0.329 11.655 r u_cpu/wb_stage/write_buffer_way[1]_i_5/O
|
|
net (fo=7, routed) 0.762 12.417 u_cpu/addr_trans/tlb_entry/sc_cancel_req
|
|
SLICE_X46Y35 r u_cpu/addr_trans/tlb_entry/main_state[0]_i_3/I1
|
|
SLICE_X46Y35 LUT3 (Prop_lut3_I1_O) 0.124 12.541 r u_cpu/addr_trans/tlb_entry/main_state[0]_i_3/O
|
|
net (fo=3, routed) 0.719 13.260 u_cpu/dcache/main_state_reg[0]_2
|
|
SLICE_X43Y31 r u_cpu/dcache/ds_to_es_bus_r[235]_i_10/I3
|
|
SLICE_X43Y31 LUT6 (Prop_lut6_I3_O) 0.124 13.384 r u_cpu/dcache/ds_to_es_bus_r[235]_i_10/O
|
|
net (fo=3, routed) 0.415 13.799 u_cpu/mem_stage/data_data_ok
|
|
SLICE_X43Y30 r u_cpu/mem_stage/flush_inst_req_buffer[1]_i_15/I0
|
|
SLICE_X43Y30 LUT3 (Prop_lut3_I0_O) 0.124 13.923 r u_cpu/mem_stage/flush_inst_req_buffer[1]_i_15/O
|
|
net (fo=2, routed) 0.833 14.756 u_cpu/mem_stage/es_to_ms_bus_r_reg[70]_1
|
|
SLICE_X48Y30 r u_cpu/mem_stage/flush_inst_req_buffer[1]_i_14/I0
|
|
SLICE_X48Y30 LUT6 (Prop_lut6_I0_O) 0.124 14.880 r u_cpu/mem_stage/flush_inst_req_buffer[1]_i_14/O
|
|
net (fo=1, routed) 0.651 15.532 u_cpu/mem_stage/ms_ready_go
|
|
SLICE_X48Y25 r u_cpu/mem_stage/flush_inst_req_buffer[1]_i_13/I4
|
|
SLICE_X48Y25 LUT6 (Prop_lut6_I4_O) 0.124 15.656 r u_cpu/mem_stage/flush_inst_req_buffer[1]_i_13/O
|
|
net (fo=3, routed) 0.483 16.139 u_cpu/id_stage/flush_inst_req_buffer[31]_i_6
|
|
SLICE_X50Y25 r u_cpu/id_stage/flush_inst_req_buffer[1]_i_9/I1
|
|
SLICE_X50Y25 LUT6 (Prop_lut6_I1_O) 0.124 16.263 r u_cpu/id_stage/flush_inst_req_buffer[1]_i_9/O
|
|
net (fo=32, routed) 0.531 16.794 u_cpu/if_stage/nextpc5
|
|
SLICE_X51Y27 r u_cpu/if_stage/fetch_pc_r[6]_i_4/I2
|
|
SLICE_X51Y27 LUT6 (Prop_lut6_I2_O) 0.124 16.918 r u_cpu/if_stage/fetch_pc_r[6]_i_4/O
|
|
net (fo=1, routed) 3.059 19.977 u_cpu/if_stage/fetch_pc_r[6]_i_4_n_0
|
|
SLICE_X114Y28 r u_cpu/if_stage/fetch_pc_r[6]_i_2/I2
|
|
SLICE_X114Y28 LUT6 (Prop_lut6_I2_O) 0.124 20.101 r u_cpu/if_stage/fetch_pc_r[6]_i_2/O
|
|
net (fo=1, routed) 0.441 20.542 u_cpu/if_stage/fetch_pc_r[6]_i_2_n_0
|
|
SLICE_X114Y25 r u_cpu/if_stage/fetch_pc_r[6]_i_1/I2
|
|
SLICE_X114Y25 LUT6 (Prop_lut6_I2_O) 0.124 20.666 r u_cpu/if_stage/fetch_pc_r[6]_i_1/O
|
|
net (fo=6, routed) 3.249 23.915 u_cpu/icache/tagv_ram_way[1].u/mem_reg_reg_2[2]
|
|
SLICE_X49Y33 r u_cpu/icache/tagv_ram_way[1].u/mem_reg_reg_i_8/I4
|
|
SLICE_X49Y33 LUT5 (Prop_lut5_I4_O) 0.124 24.039 r u_cpu/icache/tagv_ram_way[1].u/mem_reg_reg_i_8/O
|
|
net (fo=16, routed) 1.477 25.516 u_cpu/icache/data_ram_way[0].data_ram_bank[3].u/ADDRBWRADDR[2]
|
|
RAMB18_X2Y3 RAMB18E1 r u_cpu/icache/data_ram_way[0].data_ram_bank[3].u/mem_reg_reg/ADDRARDADDR[7]
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock cpu_clk rise edge) 30.323 30.323 r
|
|
clock source latency -5.674 24.648
|
|
propagated clock network latency
|
|
3.781 28.429
|
|
clock pessimism -0.418 28.011
|
|
clock uncertainty -0.074 27.937
|
|
RAMB18_X2Y3 RAMB18E1 (Setup_ramb18e1_CLKARDCLK_ADDRARDADDR[7])
|
|
-0.566 27.371 u_cpu/icache/data_ram_way[0].data_ram_bank[3].u/mem_reg_reg
|
|
-------------------------------------------------------------------
|
|
required time 27.371
|
|
arrival time -25.516
|
|
-------------------------------------------------------------------
|
|
slack 1.855
|
|
|
|
Slack (MET) : 1.855ns (required time - arrival time)
|
|
Source: u_cpu/addr_trans/data_vaddr_buffer_reg[14]/C
|
|
(rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns})
|
|
Destination: u_cpu/icache/data_ram_way[0].data_ram_bank[3].u/mem_reg_reg/ADDRARDADDR[7]
|
|
(rising edge-triggered cell RAMB18E1 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns})
|
|
Path Group: cpu_clk
|
|
Path Type: Setup (Max at Slow Process Corner)
|
|
Requirement: 30.323ns (cpu_clk rise@30.323ns - cpu_clk rise@0.000ns)
|
|
Data Path Delay: 27.741ns (logic 5.333ns (19.224%) route 22.408ns (80.776%))
|
|
Logic Levels: 26 (CARRY4=4 LUT3=2 LUT4=1 LUT5=2 LUT6=15 MUXF7=1 MUXF8=1)
|
|
Clock Path Skew: -0.087ns (DCD - SCD + CPR)
|
|
Destination Clock Delay (DCD): -1.893ns = ( 28.429 - 30.323 )
|
|
Source Clock Delay (SCD): -2.225ns
|
|
Clock Pessimism Removal (CPR): -0.418ns
|
|
Clock Uncertainty: 0.074ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Discrete Jitter (DJ): 0.130ns
|
|
Phase Error (PE): 0.000ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock cpu_clk rise edge) 0.000 0.000 r
|
|
clock source latency -6.275 -6.275
|
|
propagated clock network latency
|
|
4.051 -2.225
|
|
SLICE_X35Y35 FDRE 0.000 -2.225 r u_cpu/addr_trans/data_vaddr_buffer_reg[14]/C
|
|
SLICE_X35Y35 FDRE (Prop_fdre_C_Q) 0.456 -1.769 r u_cpu/addr_trans/data_vaddr_buffer_reg[14]/Q
|
|
net (fo=33, routed) 1.442 -0.326 u_cpu/addr_trans/tlb_entry/data_vaddr_buffer[2]
|
|
SLICE_X42Y40 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_226/I5
|
|
SLICE_X42Y40 LUT6 (Prop_lut6_I5_O) 0.124 -0.202 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_226/O
|
|
net (fo=1, routed) 0.000 -0.202 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_226_n_0
|
|
SLICE_X42Y40 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_111/S[0]
|
|
SLICE_X42Y40 CARRY4 (Prop_carry4_S[0]_CO[3])
|
|
0.513 0.311 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_111/CO[3]
|
|
net (fo=1, routed) 0.000 0.311 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_111_n_0
|
|
SLICE_X42Y41 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_32/CI
|
|
SLICE_X42Y41 CARRY4 (Prop_carry4_CI_CO[2])
|
|
0.229 0.540 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_32/CO[2]
|
|
net (fo=1, routed) 1.009 1.549 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_32_n_1
|
|
SLICE_X40Y47 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_9/I1
|
|
SLICE_X40Y47 LUT6 (Prop_lut6_I1_O) 0.310 1.859 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_9/O
|
|
net (fo=2, routed) 0.635 2.494 u_cpu/addr_trans/tlb_entry/match1[28]
|
|
SLICE_X38Y47 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/I2
|
|
SLICE_X38Y47 LUT4 (Prop_lut4_I2_O) 0.124 2.618 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/O
|
|
net (fo=2, routed) 0.667 3.285 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2_n_0
|
|
SLICE_X39Y47 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/I0
|
|
SLICE_X39Y47 LUT5 (Prop_lut5_I0_O) 0.124 3.409 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/O
|
|
net (fo=2, routed) 1.103 4.512 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2_n_0
|
|
SLICE_X38Y50 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/I0
|
|
SLICE_X38Y50 LUT6 (Prop_lut6_I0_O) 0.124 4.636 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/O
|
|
net (fo=89, routed) 1.162 5.797 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus[8]
|
|
SLICE_X42Y51 r u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_38__0/S
|
|
SLICE_X42Y51 MUXF7 (Prop_muxf7_S_O) 0.292 6.089 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_38__0/O
|
|
net (fo=1, routed) 0.000 6.089 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_38__0_n_0
|
|
SLICE_X42Y51 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_16__0/I1
|
|
SLICE_X42Y51 MUXF8 (Prop_muxf8_I1_O) 0.088 6.177 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_16__0/O
|
|
net (fo=1, routed) 0.957 7.134 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_16__0_n_0
|
|
SLICE_X42Y50 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7/I0
|
|
SLICE_X42Y50 LUT6 (Prop_lut6_I0_O) 0.319 7.453 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7/O
|
|
net (fo=1, routed) 0.435 7.888 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7_n_0
|
|
SLICE_X44Y50 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0/I5
|
|
SLICE_X44Y50 LUT6 (Prop_lut6_I5_O) 0.124 8.012 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0/O
|
|
net (fo=10, routed) 0.740 8.753 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0_n_0
|
|
SLICE_X44Y50 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[5]_i_1__0/I3
|
|
SLICE_X44Y50 LUT6 (Prop_lut6_I3_O) 0.124 8.877 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[5]_i_1__0/O
|
|
net (fo=6, routed) 0.845 9.722 u_cpu/u_csr/ms_to_ws_bus[13]
|
|
SLICE_X50Y46 r u_cpu/u_csr/write_buffer_way[1]_i_18/I3
|
|
SLICE_X50Y46 LUT6 (Prop_lut6_I3_O) 0.124 9.846 r u_cpu/u_csr/write_buffer_way[1]_i_18/O
|
|
net (fo=1, routed) 0.000 9.846 u_cpu/u_csr/write_buffer_way[1]_i_18_n_0
|
|
SLICE_X50Y46 r u_cpu/u_csr/write_buffer_way_reg[1]_i_11/S[0]
|
|
SLICE_X50Y46 CARRY4 (Prop_carry4_S[0]_CO[3])
|
|
0.532 10.378 r u_cpu/u_csr/write_buffer_way_reg[1]_i_11/CO[3]
|
|
net (fo=1, routed) 0.000 10.378 u_cpu/u_csr/write_buffer_way_reg[1]_i_11_n_0
|
|
SLICE_X50Y47 r u_cpu/u_csr/write_buffer_way_reg[1]_i_9/CI
|
|
SLICE_X50Y47 CARRY4 (Prop_carry4_CI_CO[1])
|
|
0.157 10.535 r u_cpu/u_csr/write_buffer_way_reg[1]_i_9/CO[1]
|
|
net (fo=2, routed) 0.791 11.326 u_cpu/wb_stage/CO[0]
|
|
SLICE_X46Y39 r u_cpu/wb_stage/write_buffer_way[1]_i_5/I1
|
|
SLICE_X46Y39 LUT6 (Prop_lut6_I1_O) 0.329 11.655 f u_cpu/wb_stage/write_buffer_way[1]_i_5/O
|
|
net (fo=7, routed) 0.762 12.417 u_cpu/addr_trans/tlb_entry/sc_cancel_req
|
|
SLICE_X46Y35 f u_cpu/addr_trans/tlb_entry/main_state[0]_i_3/I1
|
|
SLICE_X46Y35 LUT3 (Prop_lut3_I1_O) 0.124 12.541 f u_cpu/addr_trans/tlb_entry/main_state[0]_i_3/O
|
|
net (fo=3, routed) 0.719 13.260 u_cpu/dcache/main_state_reg[0]_2
|
|
SLICE_X43Y31 f u_cpu/dcache/ds_to_es_bus_r[235]_i_10/I3
|
|
SLICE_X43Y31 LUT6 (Prop_lut6_I3_O) 0.124 13.384 f u_cpu/dcache/ds_to_es_bus_r[235]_i_10/O
|
|
net (fo=3, routed) 0.415 13.799 u_cpu/mem_stage/data_data_ok
|
|
SLICE_X43Y30 f u_cpu/mem_stage/flush_inst_req_buffer[1]_i_15/I0
|
|
SLICE_X43Y30 LUT3 (Prop_lut3_I0_O) 0.124 13.923 f u_cpu/mem_stage/flush_inst_req_buffer[1]_i_15/O
|
|
net (fo=2, routed) 0.833 14.756 u_cpu/mem_stage/es_to_ms_bus_r_reg[70]_1
|
|
SLICE_X48Y30 f u_cpu/mem_stage/flush_inst_req_buffer[1]_i_14/I0
|
|
SLICE_X48Y30 LUT6 (Prop_lut6_I0_O) 0.124 14.880 f u_cpu/mem_stage/flush_inst_req_buffer[1]_i_14/O
|
|
net (fo=1, routed) 0.651 15.532 u_cpu/mem_stage/ms_ready_go
|
|
SLICE_X48Y25 f u_cpu/mem_stage/flush_inst_req_buffer[1]_i_13/I4
|
|
SLICE_X48Y25 LUT6 (Prop_lut6_I4_O) 0.124 15.656 f u_cpu/mem_stage/flush_inst_req_buffer[1]_i_13/O
|
|
net (fo=3, routed) 0.483 16.139 u_cpu/id_stage/flush_inst_req_buffer[31]_i_6
|
|
SLICE_X50Y25 f u_cpu/id_stage/flush_inst_req_buffer[1]_i_9/I1
|
|
SLICE_X50Y25 LUT6 (Prop_lut6_I1_O) 0.124 16.263 f u_cpu/id_stage/flush_inst_req_buffer[1]_i_9/O
|
|
net (fo=32, routed) 0.531 16.794 u_cpu/if_stage/nextpc5
|
|
SLICE_X51Y27 f u_cpu/if_stage/fetch_pc_r[6]_i_4/I2
|
|
SLICE_X51Y27 LUT6 (Prop_lut6_I2_O) 0.124 16.918 r u_cpu/if_stage/fetch_pc_r[6]_i_4/O
|
|
net (fo=1, routed) 3.059 19.977 u_cpu/if_stage/fetch_pc_r[6]_i_4_n_0
|
|
SLICE_X114Y28 r u_cpu/if_stage/fetch_pc_r[6]_i_2/I2
|
|
SLICE_X114Y28 LUT6 (Prop_lut6_I2_O) 0.124 20.101 r u_cpu/if_stage/fetch_pc_r[6]_i_2/O
|
|
net (fo=1, routed) 0.441 20.542 u_cpu/if_stage/fetch_pc_r[6]_i_2_n_0
|
|
SLICE_X114Y25 r u_cpu/if_stage/fetch_pc_r[6]_i_1/I2
|
|
SLICE_X114Y25 LUT6 (Prop_lut6_I2_O) 0.124 20.666 r u_cpu/if_stage/fetch_pc_r[6]_i_1/O
|
|
net (fo=6, routed) 3.249 23.915 u_cpu/icache/tagv_ram_way[1].u/mem_reg_reg_2[2]
|
|
SLICE_X49Y33 r u_cpu/icache/tagv_ram_way[1].u/mem_reg_reg_i_8/I4
|
|
SLICE_X49Y33 LUT5 (Prop_lut5_I4_O) 0.124 24.039 r u_cpu/icache/tagv_ram_way[1].u/mem_reg_reg_i_8/O
|
|
net (fo=16, routed) 1.477 25.516 u_cpu/icache/data_ram_way[0].data_ram_bank[3].u/ADDRBWRADDR[2]
|
|
RAMB18_X2Y3 RAMB18E1 r u_cpu/icache/data_ram_way[0].data_ram_bank[3].u/mem_reg_reg/ADDRARDADDR[7]
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock cpu_clk rise edge) 30.323 30.323 r
|
|
clock source latency -5.674 24.648
|
|
propagated clock network latency
|
|
3.781 28.429
|
|
clock pessimism -0.418 28.011
|
|
clock uncertainty -0.074 27.937
|
|
RAMB18_X2Y3 RAMB18E1 (Setup_ramb18e1_CLKARDCLK_ADDRARDADDR[7])
|
|
-0.566 27.371 u_cpu/icache/data_ram_way[0].data_ram_bank[3].u/mem_reg_reg
|
|
-------------------------------------------------------------------
|
|
required time 27.371
|
|
arrival time -25.516
|
|
-------------------------------------------------------------------
|
|
slack 1.855
|
|
|
|
Slack (MET) : 1.855ns (required time - arrival time)
|
|
Source: u_cpu/addr_trans/data_vaddr_buffer_reg[14]/C
|
|
(rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns})
|
|
Destination: u_cpu/icache/data_ram_way[0].data_ram_bank[3].u/mem_reg_reg/ADDRARDADDR[7]
|
|
(rising edge-triggered cell RAMB18E1 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns})
|
|
Path Group: cpu_clk
|
|
Path Type: Setup (Max at Slow Process Corner)
|
|
Requirement: 30.323ns (cpu_clk rise@30.323ns - cpu_clk rise@0.000ns)
|
|
Data Path Delay: 27.741ns (logic 5.333ns (19.224%) route 22.408ns (80.776%))
|
|
Logic Levels: 26 (CARRY4=4 LUT3=2 LUT4=1 LUT5=2 LUT6=15 MUXF7=1 MUXF8=1)
|
|
Clock Path Skew: -0.087ns (DCD - SCD + CPR)
|
|
Destination Clock Delay (DCD): -1.893ns = ( 28.429 - 30.323 )
|
|
Source Clock Delay (SCD): -2.225ns
|
|
Clock Pessimism Removal (CPR): -0.418ns
|
|
Clock Uncertainty: 0.074ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Discrete Jitter (DJ): 0.130ns
|
|
Phase Error (PE): 0.000ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock cpu_clk rise edge) 0.000 0.000 r
|
|
clock source latency -6.275 -6.275
|
|
propagated clock network latency
|
|
4.051 -2.225
|
|
SLICE_X35Y35 FDRE 0.000 -2.225 r u_cpu/addr_trans/data_vaddr_buffer_reg[14]/C
|
|
SLICE_X35Y35 FDRE (Prop_fdre_C_Q) 0.456 -1.769 r u_cpu/addr_trans/data_vaddr_buffer_reg[14]/Q
|
|
net (fo=33, routed) 1.442 -0.326 u_cpu/addr_trans/tlb_entry/data_vaddr_buffer[2]
|
|
SLICE_X42Y40 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_226/I5
|
|
SLICE_X42Y40 LUT6 (Prop_lut6_I5_O) 0.124 -0.202 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_226/O
|
|
net (fo=1, routed) 0.000 -0.202 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_226_n_0
|
|
SLICE_X42Y40 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_111/S[0]
|
|
SLICE_X42Y40 CARRY4 (Prop_carry4_S[0]_CO[3])
|
|
0.513 0.311 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_111/CO[3]
|
|
net (fo=1, routed) 0.000 0.311 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_111_n_0
|
|
SLICE_X42Y41 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_32/CI
|
|
SLICE_X42Y41 CARRY4 (Prop_carry4_CI_CO[2])
|
|
0.229 0.540 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_32/CO[2]
|
|
net (fo=1, routed) 1.009 1.549 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_32_n_1
|
|
SLICE_X40Y47 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_9/I1
|
|
SLICE_X40Y47 LUT6 (Prop_lut6_I1_O) 0.310 1.859 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_9/O
|
|
net (fo=2, routed) 0.635 2.494 u_cpu/addr_trans/tlb_entry/match1[28]
|
|
SLICE_X38Y47 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/I2
|
|
SLICE_X38Y47 LUT4 (Prop_lut4_I2_O) 0.124 2.618 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/O
|
|
net (fo=2, routed) 0.667 3.285 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2_n_0
|
|
SLICE_X39Y47 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/I0
|
|
SLICE_X39Y47 LUT5 (Prop_lut5_I0_O) 0.124 3.409 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/O
|
|
net (fo=2, routed) 1.103 4.512 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2_n_0
|
|
SLICE_X38Y50 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/I0
|
|
SLICE_X38Y50 LUT6 (Prop_lut6_I0_O) 0.124 4.636 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/O
|
|
net (fo=89, routed) 1.162 5.797 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus[8]
|
|
SLICE_X42Y51 r u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_38__0/S
|
|
SLICE_X42Y51 MUXF7 (Prop_muxf7_S_O) 0.292 6.089 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_38__0/O
|
|
net (fo=1, routed) 0.000 6.089 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_38__0_n_0
|
|
SLICE_X42Y51 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_16__0/I1
|
|
SLICE_X42Y51 MUXF8 (Prop_muxf8_I1_O) 0.088 6.177 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_16__0/O
|
|
net (fo=1, routed) 0.957 7.134 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_16__0_n_0
|
|
SLICE_X42Y50 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7/I0
|
|
SLICE_X42Y50 LUT6 (Prop_lut6_I0_O) 0.319 7.453 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7/O
|
|
net (fo=1, routed) 0.435 7.888 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7_n_0
|
|
SLICE_X44Y50 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0/I5
|
|
SLICE_X44Y50 LUT6 (Prop_lut6_I5_O) 0.124 8.012 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0/O
|
|
net (fo=10, routed) 0.740 8.753 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0_n_0
|
|
SLICE_X44Y50 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[5]_i_1__0/I3
|
|
SLICE_X44Y50 LUT6 (Prop_lut6_I3_O) 0.124 8.877 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[5]_i_1__0/O
|
|
net (fo=6, routed) 0.845 9.722 u_cpu/u_csr/ms_to_ws_bus[13]
|
|
SLICE_X50Y46 f u_cpu/u_csr/write_buffer_way[1]_i_18/I3
|
|
SLICE_X50Y46 LUT6 (Prop_lut6_I3_O) 0.124 9.846 r u_cpu/u_csr/write_buffer_way[1]_i_18/O
|
|
net (fo=1, routed) 0.000 9.846 u_cpu/u_csr/write_buffer_way[1]_i_18_n_0
|
|
SLICE_X50Y46 r u_cpu/u_csr/write_buffer_way_reg[1]_i_11/S[0]
|
|
SLICE_X50Y46 CARRY4 (Prop_carry4_S[0]_CO[3])
|
|
0.532 10.378 r u_cpu/u_csr/write_buffer_way_reg[1]_i_11/CO[3]
|
|
net (fo=1, routed) 0.000 10.378 u_cpu/u_csr/write_buffer_way_reg[1]_i_11_n_0
|
|
SLICE_X50Y47 r u_cpu/u_csr/write_buffer_way_reg[1]_i_9/CI
|
|
SLICE_X50Y47 CARRY4 (Prop_carry4_CI_CO[1])
|
|
0.157 10.535 r u_cpu/u_csr/write_buffer_way_reg[1]_i_9/CO[1]
|
|
net (fo=2, routed) 0.791 11.326 u_cpu/wb_stage/CO[0]
|
|
SLICE_X46Y39 r u_cpu/wb_stage/write_buffer_way[1]_i_5/I1
|
|
SLICE_X46Y39 LUT6 (Prop_lut6_I1_O) 0.329 11.655 f u_cpu/wb_stage/write_buffer_way[1]_i_5/O
|
|
net (fo=7, routed) 0.762 12.417 u_cpu/addr_trans/tlb_entry/sc_cancel_req
|
|
SLICE_X46Y35 f u_cpu/addr_trans/tlb_entry/main_state[0]_i_3/I1
|
|
SLICE_X46Y35 LUT3 (Prop_lut3_I1_O) 0.124 12.541 f u_cpu/addr_trans/tlb_entry/main_state[0]_i_3/O
|
|
net (fo=3, routed) 0.719 13.260 u_cpu/dcache/main_state_reg[0]_2
|
|
SLICE_X43Y31 f u_cpu/dcache/ds_to_es_bus_r[235]_i_10/I3
|
|
SLICE_X43Y31 LUT6 (Prop_lut6_I3_O) 0.124 13.384 f u_cpu/dcache/ds_to_es_bus_r[235]_i_10/O
|
|
net (fo=3, routed) 0.415 13.799 u_cpu/mem_stage/data_data_ok
|
|
SLICE_X43Y30 f u_cpu/mem_stage/flush_inst_req_buffer[1]_i_15/I0
|
|
SLICE_X43Y30 LUT3 (Prop_lut3_I0_O) 0.124 13.923 f u_cpu/mem_stage/flush_inst_req_buffer[1]_i_15/O
|
|
net (fo=2, routed) 0.833 14.756 u_cpu/mem_stage/es_to_ms_bus_r_reg[70]_1
|
|
SLICE_X48Y30 f u_cpu/mem_stage/flush_inst_req_buffer[1]_i_14/I0
|
|
SLICE_X48Y30 LUT6 (Prop_lut6_I0_O) 0.124 14.880 f u_cpu/mem_stage/flush_inst_req_buffer[1]_i_14/O
|
|
net (fo=1, routed) 0.651 15.532 u_cpu/mem_stage/ms_ready_go
|
|
SLICE_X48Y25 f u_cpu/mem_stage/flush_inst_req_buffer[1]_i_13/I4
|
|
SLICE_X48Y25 LUT6 (Prop_lut6_I4_O) 0.124 15.656 f u_cpu/mem_stage/flush_inst_req_buffer[1]_i_13/O
|
|
net (fo=3, routed) 0.483 16.139 u_cpu/id_stage/flush_inst_req_buffer[31]_i_6
|
|
SLICE_X50Y25 f u_cpu/id_stage/flush_inst_req_buffer[1]_i_9/I1
|
|
SLICE_X50Y25 LUT6 (Prop_lut6_I1_O) 0.124 16.263 f u_cpu/id_stage/flush_inst_req_buffer[1]_i_9/O
|
|
net (fo=32, routed) 0.531 16.794 u_cpu/if_stage/nextpc5
|
|
SLICE_X51Y27 f u_cpu/if_stage/fetch_pc_r[6]_i_4/I2
|
|
SLICE_X51Y27 LUT6 (Prop_lut6_I2_O) 0.124 16.918 r u_cpu/if_stage/fetch_pc_r[6]_i_4/O
|
|
net (fo=1, routed) 3.059 19.977 u_cpu/if_stage/fetch_pc_r[6]_i_4_n_0
|
|
SLICE_X114Y28 r u_cpu/if_stage/fetch_pc_r[6]_i_2/I2
|
|
SLICE_X114Y28 LUT6 (Prop_lut6_I2_O) 0.124 20.101 r u_cpu/if_stage/fetch_pc_r[6]_i_2/O
|
|
net (fo=1, routed) 0.441 20.542 u_cpu/if_stage/fetch_pc_r[6]_i_2_n_0
|
|
SLICE_X114Y25 r u_cpu/if_stage/fetch_pc_r[6]_i_1/I2
|
|
SLICE_X114Y25 LUT6 (Prop_lut6_I2_O) 0.124 20.666 r u_cpu/if_stage/fetch_pc_r[6]_i_1/O
|
|
net (fo=6, routed) 3.249 23.915 u_cpu/icache/tagv_ram_way[1].u/mem_reg_reg_2[2]
|
|
SLICE_X49Y33 r u_cpu/icache/tagv_ram_way[1].u/mem_reg_reg_i_8/I4
|
|
SLICE_X49Y33 LUT5 (Prop_lut5_I4_O) 0.124 24.039 r u_cpu/icache/tagv_ram_way[1].u/mem_reg_reg_i_8/O
|
|
net (fo=16, routed) 1.477 25.516 u_cpu/icache/data_ram_way[0].data_ram_bank[3].u/ADDRBWRADDR[2]
|
|
RAMB18_X2Y3 RAMB18E1 r u_cpu/icache/data_ram_way[0].data_ram_bank[3].u/mem_reg_reg/ADDRARDADDR[7]
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock cpu_clk rise edge) 30.323 30.323 r
|
|
clock source latency -5.674 24.648
|
|
propagated clock network latency
|
|
3.781 28.429
|
|
clock pessimism -0.418 28.011
|
|
clock uncertainty -0.074 27.937
|
|
RAMB18_X2Y3 RAMB18E1 (Setup_ramb18e1_CLKARDCLK_ADDRARDADDR[7])
|
|
-0.566 27.371 u_cpu/icache/data_ram_way[0].data_ram_bank[3].u/mem_reg_reg
|
|
-------------------------------------------------------------------
|
|
required time 27.371
|
|
arrival time -25.516
|
|
-------------------------------------------------------------------
|
|
slack 1.855
|
|
|
|
Slack (MET) : 1.855ns (required time - arrival time)
|
|
Source: u_cpu/addr_trans/data_vaddr_buffer_reg[14]/C
|
|
(rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns})
|
|
Destination: u_cpu/icache/data_ram_way[0].data_ram_bank[3].u/mem_reg_reg/ADDRARDADDR[7]
|
|
(rising edge-triggered cell RAMB18E1 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns})
|
|
Path Group: cpu_clk
|
|
Path Type: Setup (Max at Slow Process Corner)
|
|
Requirement: 30.323ns (cpu_clk rise@30.323ns - cpu_clk rise@0.000ns)
|
|
Data Path Delay: 27.741ns (logic 5.333ns (19.224%) route 22.408ns (80.776%))
|
|
Logic Levels: 26 (CARRY4=4 LUT3=2 LUT4=1 LUT5=2 LUT6=15 MUXF7=1 MUXF8=1)
|
|
Clock Path Skew: -0.087ns (DCD - SCD + CPR)
|
|
Destination Clock Delay (DCD): -1.893ns = ( 28.429 - 30.323 )
|
|
Source Clock Delay (SCD): -2.225ns
|
|
Clock Pessimism Removal (CPR): -0.418ns
|
|
Clock Uncertainty: 0.074ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Discrete Jitter (DJ): 0.130ns
|
|
Phase Error (PE): 0.000ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock cpu_clk rise edge) 0.000 0.000 r
|
|
clock source latency -6.275 -6.275
|
|
propagated clock network latency
|
|
4.051 -2.225
|
|
SLICE_X35Y35 FDRE 0.000 -2.225 r u_cpu/addr_trans/data_vaddr_buffer_reg[14]/C
|
|
SLICE_X35Y35 FDRE (Prop_fdre_C_Q) 0.456 -1.769 r u_cpu/addr_trans/data_vaddr_buffer_reg[14]/Q
|
|
net (fo=33, routed) 1.442 -0.326 u_cpu/addr_trans/tlb_entry/data_vaddr_buffer[2]
|
|
SLICE_X42Y40 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_226/I5
|
|
SLICE_X42Y40 LUT6 (Prop_lut6_I5_O) 0.124 -0.202 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_226/O
|
|
net (fo=1, routed) 0.000 -0.202 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_226_n_0
|
|
SLICE_X42Y40 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_111/S[0]
|
|
SLICE_X42Y40 CARRY4 (Prop_carry4_S[0]_CO[3])
|
|
0.513 0.311 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_111/CO[3]
|
|
net (fo=1, routed) 0.000 0.311 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_111_n_0
|
|
SLICE_X42Y41 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_32/CI
|
|
SLICE_X42Y41 CARRY4 (Prop_carry4_CI_CO[2])
|
|
0.229 0.540 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_32/CO[2]
|
|
net (fo=1, routed) 1.009 1.549 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_32_n_1
|
|
SLICE_X40Y47 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_9/I1
|
|
SLICE_X40Y47 LUT6 (Prop_lut6_I1_O) 0.310 1.859 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_9/O
|
|
net (fo=2, routed) 0.635 2.494 u_cpu/addr_trans/tlb_entry/match1[28]
|
|
SLICE_X38Y47 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/I2
|
|
SLICE_X38Y47 LUT4 (Prop_lut4_I2_O) 0.124 2.618 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/O
|
|
net (fo=2, routed) 0.667 3.285 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2_n_0
|
|
SLICE_X39Y47 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/I0
|
|
SLICE_X39Y47 LUT5 (Prop_lut5_I0_O) 0.124 3.409 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/O
|
|
net (fo=2, routed) 1.103 4.512 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2_n_0
|
|
SLICE_X38Y50 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/I0
|
|
SLICE_X38Y50 LUT6 (Prop_lut6_I0_O) 0.124 4.636 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/O
|
|
net (fo=89, routed) 1.162 5.797 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus[8]
|
|
SLICE_X42Y51 r u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_38__0/S
|
|
SLICE_X42Y51 MUXF7 (Prop_muxf7_S_O) 0.292 6.089 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_38__0/O
|
|
net (fo=1, routed) 0.000 6.089 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_38__0_n_0
|
|
SLICE_X42Y51 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_16__0/I1
|
|
SLICE_X42Y51 MUXF8 (Prop_muxf8_I1_O) 0.088 6.177 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_16__0/O
|
|
net (fo=1, routed) 0.957 7.134 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_16__0_n_0
|
|
SLICE_X42Y50 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7/I0
|
|
SLICE_X42Y50 LUT6 (Prop_lut6_I0_O) 0.319 7.453 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7/O
|
|
net (fo=1, routed) 0.435 7.888 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7_n_0
|
|
SLICE_X44Y50 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0/I5
|
|
SLICE_X44Y50 LUT6 (Prop_lut6_I5_O) 0.124 8.012 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0/O
|
|
net (fo=10, routed) 0.740 8.753 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0_n_0
|
|
SLICE_X44Y50 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[5]_i_1__0/I3
|
|
SLICE_X44Y50 LUT6 (Prop_lut6_I3_O) 0.124 8.877 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[5]_i_1__0/O
|
|
net (fo=6, routed) 0.845 9.722 u_cpu/u_csr/ms_to_ws_bus[13]
|
|
SLICE_X50Y46 r u_cpu/u_csr/write_buffer_way[1]_i_18/I3
|
|
SLICE_X50Y46 LUT6 (Prop_lut6_I3_O) 0.124 9.846 f u_cpu/u_csr/write_buffer_way[1]_i_18/O
|
|
net (fo=1, routed) 0.000 9.846 u_cpu/u_csr/write_buffer_way[1]_i_18_n_0
|
|
SLICE_X50Y46 f u_cpu/u_csr/write_buffer_way_reg[1]_i_11/S[0]
|
|
SLICE_X50Y46 CARRY4 (Prop_carry4_S[0]_CO[3])
|
|
0.532 10.378 r u_cpu/u_csr/write_buffer_way_reg[1]_i_11/CO[3]
|
|
net (fo=1, routed) 0.000 10.378 u_cpu/u_csr/write_buffer_way_reg[1]_i_11_n_0
|
|
SLICE_X50Y47 r u_cpu/u_csr/write_buffer_way_reg[1]_i_9/CI
|
|
SLICE_X50Y47 CARRY4 (Prop_carry4_CI_CO[1])
|
|
0.157 10.535 r u_cpu/u_csr/write_buffer_way_reg[1]_i_9/CO[1]
|
|
net (fo=2, routed) 0.791 11.326 u_cpu/wb_stage/CO[0]
|
|
SLICE_X46Y39 r u_cpu/wb_stage/write_buffer_way[1]_i_5/I1
|
|
SLICE_X46Y39 LUT6 (Prop_lut6_I1_O) 0.329 11.655 f u_cpu/wb_stage/write_buffer_way[1]_i_5/O
|
|
net (fo=7, routed) 0.762 12.417 u_cpu/addr_trans/tlb_entry/sc_cancel_req
|
|
SLICE_X46Y35 f u_cpu/addr_trans/tlb_entry/main_state[0]_i_3/I1
|
|
SLICE_X46Y35 LUT3 (Prop_lut3_I1_O) 0.124 12.541 f u_cpu/addr_trans/tlb_entry/main_state[0]_i_3/O
|
|
net (fo=3, routed) 0.719 13.260 u_cpu/dcache/main_state_reg[0]_2
|
|
SLICE_X43Y31 f u_cpu/dcache/ds_to_es_bus_r[235]_i_10/I3
|
|
SLICE_X43Y31 LUT6 (Prop_lut6_I3_O) 0.124 13.384 f u_cpu/dcache/ds_to_es_bus_r[235]_i_10/O
|
|
net (fo=3, routed) 0.415 13.799 u_cpu/mem_stage/data_data_ok
|
|
SLICE_X43Y30 f u_cpu/mem_stage/flush_inst_req_buffer[1]_i_15/I0
|
|
SLICE_X43Y30 LUT3 (Prop_lut3_I0_O) 0.124 13.923 f u_cpu/mem_stage/flush_inst_req_buffer[1]_i_15/O
|
|
net (fo=2, routed) 0.833 14.756 u_cpu/mem_stage/es_to_ms_bus_r_reg[70]_1
|
|
SLICE_X48Y30 f u_cpu/mem_stage/flush_inst_req_buffer[1]_i_14/I0
|
|
SLICE_X48Y30 LUT6 (Prop_lut6_I0_O) 0.124 14.880 f u_cpu/mem_stage/flush_inst_req_buffer[1]_i_14/O
|
|
net (fo=1, routed) 0.651 15.532 u_cpu/mem_stage/ms_ready_go
|
|
SLICE_X48Y25 f u_cpu/mem_stage/flush_inst_req_buffer[1]_i_13/I4
|
|
SLICE_X48Y25 LUT6 (Prop_lut6_I4_O) 0.124 15.656 f u_cpu/mem_stage/flush_inst_req_buffer[1]_i_13/O
|
|
net (fo=3, routed) 0.483 16.139 u_cpu/id_stage/flush_inst_req_buffer[31]_i_6
|
|
SLICE_X50Y25 f u_cpu/id_stage/flush_inst_req_buffer[1]_i_9/I1
|
|
SLICE_X50Y25 LUT6 (Prop_lut6_I1_O) 0.124 16.263 f u_cpu/id_stage/flush_inst_req_buffer[1]_i_9/O
|
|
net (fo=32, routed) 0.531 16.794 u_cpu/if_stage/nextpc5
|
|
SLICE_X51Y27 f u_cpu/if_stage/fetch_pc_r[6]_i_4/I2
|
|
SLICE_X51Y27 LUT6 (Prop_lut6_I2_O) 0.124 16.918 r u_cpu/if_stage/fetch_pc_r[6]_i_4/O
|
|
net (fo=1, routed) 3.059 19.977 u_cpu/if_stage/fetch_pc_r[6]_i_4_n_0
|
|
SLICE_X114Y28 r u_cpu/if_stage/fetch_pc_r[6]_i_2/I2
|
|
SLICE_X114Y28 LUT6 (Prop_lut6_I2_O) 0.124 20.101 r u_cpu/if_stage/fetch_pc_r[6]_i_2/O
|
|
net (fo=1, routed) 0.441 20.542 u_cpu/if_stage/fetch_pc_r[6]_i_2_n_0
|
|
SLICE_X114Y25 r u_cpu/if_stage/fetch_pc_r[6]_i_1/I2
|
|
SLICE_X114Y25 LUT6 (Prop_lut6_I2_O) 0.124 20.666 r u_cpu/if_stage/fetch_pc_r[6]_i_1/O
|
|
net (fo=6, routed) 3.249 23.915 u_cpu/icache/tagv_ram_way[1].u/mem_reg_reg_2[2]
|
|
SLICE_X49Y33 r u_cpu/icache/tagv_ram_way[1].u/mem_reg_reg_i_8/I4
|
|
SLICE_X49Y33 LUT5 (Prop_lut5_I4_O) 0.124 24.039 r u_cpu/icache/tagv_ram_way[1].u/mem_reg_reg_i_8/O
|
|
net (fo=16, routed) 1.477 25.516 u_cpu/icache/data_ram_way[0].data_ram_bank[3].u/ADDRBWRADDR[2]
|
|
RAMB18_X2Y3 RAMB18E1 r u_cpu/icache/data_ram_way[0].data_ram_bank[3].u/mem_reg_reg/ADDRARDADDR[7]
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock cpu_clk rise edge) 30.323 30.323 r
|
|
clock source latency -5.674 24.648
|
|
propagated clock network latency
|
|
3.781 28.429
|
|
clock pessimism -0.418 28.011
|
|
clock uncertainty -0.074 27.937
|
|
RAMB18_X2Y3 RAMB18E1 (Setup_ramb18e1_CLKARDCLK_ADDRARDADDR[7])
|
|
-0.566 27.371 u_cpu/icache/data_ram_way[0].data_ram_bank[3].u/mem_reg_reg
|
|
-------------------------------------------------------------------
|
|
required time 27.371
|
|
arrival time -25.516
|
|
-------------------------------------------------------------------
|
|
slack 1.855
|
|
|
|
Slack (MET) : 1.855ns (required time - arrival time)
|
|
Source: u_cpu/addr_trans/data_vaddr_buffer_reg[14]/C
|
|
(rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns})
|
|
Destination: u_cpu/icache/data_ram_way[0].data_ram_bank[3].u/mem_reg_reg/ADDRARDADDR[7]
|
|
(rising edge-triggered cell RAMB18E1 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns})
|
|
Path Group: cpu_clk
|
|
Path Type: Setup (Max at Slow Process Corner)
|
|
Requirement: 30.323ns (cpu_clk rise@30.323ns - cpu_clk rise@0.000ns)
|
|
Data Path Delay: 27.741ns (logic 5.333ns (19.224%) route 22.408ns (80.776%))
|
|
Logic Levels: 26 (CARRY4=4 LUT3=2 LUT4=1 LUT5=2 LUT6=15 MUXF7=1 MUXF8=1)
|
|
Clock Path Skew: -0.087ns (DCD - SCD + CPR)
|
|
Destination Clock Delay (DCD): -1.893ns = ( 28.429 - 30.323 )
|
|
Source Clock Delay (SCD): -2.225ns
|
|
Clock Pessimism Removal (CPR): -0.418ns
|
|
Clock Uncertainty: 0.074ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Discrete Jitter (DJ): 0.130ns
|
|
Phase Error (PE): 0.000ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock cpu_clk rise edge) 0.000 0.000 r
|
|
clock source latency -6.275 -6.275
|
|
propagated clock network latency
|
|
4.051 -2.225
|
|
SLICE_X35Y35 FDRE 0.000 -2.225 r u_cpu/addr_trans/data_vaddr_buffer_reg[14]/C
|
|
SLICE_X35Y35 FDRE (Prop_fdre_C_Q) 0.456 -1.769 r u_cpu/addr_trans/data_vaddr_buffer_reg[14]/Q
|
|
net (fo=33, routed) 1.442 -0.326 u_cpu/addr_trans/tlb_entry/data_vaddr_buffer[2]
|
|
SLICE_X42Y40 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_226/I5
|
|
SLICE_X42Y40 LUT6 (Prop_lut6_I5_O) 0.124 -0.202 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_226/O
|
|
net (fo=1, routed) 0.000 -0.202 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_226_n_0
|
|
SLICE_X42Y40 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_111/S[0]
|
|
SLICE_X42Y40 CARRY4 (Prop_carry4_S[0]_CO[3])
|
|
0.513 0.311 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_111/CO[3]
|
|
net (fo=1, routed) 0.000 0.311 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_111_n_0
|
|
SLICE_X42Y41 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_32/CI
|
|
SLICE_X42Y41 CARRY4 (Prop_carry4_CI_CO[2])
|
|
0.229 0.540 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_32/CO[2]
|
|
net (fo=1, routed) 1.009 1.549 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_32_n_1
|
|
SLICE_X40Y47 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_9/I1
|
|
SLICE_X40Y47 LUT6 (Prop_lut6_I1_O) 0.310 1.859 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_9/O
|
|
net (fo=2, routed) 0.635 2.494 u_cpu/addr_trans/tlb_entry/match1[28]
|
|
SLICE_X38Y47 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/I2
|
|
SLICE_X38Y47 LUT4 (Prop_lut4_I2_O) 0.124 2.618 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/O
|
|
net (fo=2, routed) 0.667 3.285 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2_n_0
|
|
SLICE_X39Y47 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/I0
|
|
SLICE_X39Y47 LUT5 (Prop_lut5_I0_O) 0.124 3.409 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/O
|
|
net (fo=2, routed) 1.103 4.512 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2_n_0
|
|
SLICE_X38Y50 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/I0
|
|
SLICE_X38Y50 LUT6 (Prop_lut6_I0_O) 0.124 4.636 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/O
|
|
net (fo=89, routed) 1.162 5.797 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus[8]
|
|
SLICE_X42Y51 r u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_38__0/S
|
|
SLICE_X42Y51 MUXF7 (Prop_muxf7_S_O) 0.292 6.089 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_38__0/O
|
|
net (fo=1, routed) 0.000 6.089 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_38__0_n_0
|
|
SLICE_X42Y51 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_16__0/I1
|
|
SLICE_X42Y51 MUXF8 (Prop_muxf8_I1_O) 0.088 6.177 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_16__0/O
|
|
net (fo=1, routed) 0.957 7.134 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_16__0_n_0
|
|
SLICE_X42Y50 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7/I0
|
|
SLICE_X42Y50 LUT6 (Prop_lut6_I0_O) 0.319 7.453 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7/O
|
|
net (fo=1, routed) 0.435 7.888 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7_n_0
|
|
SLICE_X44Y50 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0/I5
|
|
SLICE_X44Y50 LUT6 (Prop_lut6_I5_O) 0.124 8.012 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0/O
|
|
net (fo=10, routed) 0.740 8.753 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0_n_0
|
|
SLICE_X44Y50 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[5]_i_1__0/I3
|
|
SLICE_X44Y50 LUT6 (Prop_lut6_I3_O) 0.124 8.877 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[5]_i_1__0/O
|
|
net (fo=6, routed) 0.845 9.722 u_cpu/u_csr/ms_to_ws_bus[13]
|
|
SLICE_X50Y46 f u_cpu/u_csr/write_buffer_way[1]_i_18/I3
|
|
SLICE_X50Y46 LUT6 (Prop_lut6_I3_O) 0.124 9.846 f u_cpu/u_csr/write_buffer_way[1]_i_18/O
|
|
net (fo=1, routed) 0.000 9.846 u_cpu/u_csr/write_buffer_way[1]_i_18_n_0
|
|
SLICE_X50Y46 f u_cpu/u_csr/write_buffer_way_reg[1]_i_11/S[0]
|
|
SLICE_X50Y46 CARRY4 (Prop_carry4_S[0]_CO[3])
|
|
0.532 10.378 r u_cpu/u_csr/write_buffer_way_reg[1]_i_11/CO[3]
|
|
net (fo=1, routed) 0.000 10.378 u_cpu/u_csr/write_buffer_way_reg[1]_i_11_n_0
|
|
SLICE_X50Y47 r u_cpu/u_csr/write_buffer_way_reg[1]_i_9/CI
|
|
SLICE_X50Y47 CARRY4 (Prop_carry4_CI_CO[1])
|
|
0.157 10.535 r u_cpu/u_csr/write_buffer_way_reg[1]_i_9/CO[1]
|
|
net (fo=2, routed) 0.791 11.326 u_cpu/wb_stage/CO[0]
|
|
SLICE_X46Y39 r u_cpu/wb_stage/write_buffer_way[1]_i_5/I1
|
|
SLICE_X46Y39 LUT6 (Prop_lut6_I1_O) 0.329 11.655 f u_cpu/wb_stage/write_buffer_way[1]_i_5/O
|
|
net (fo=7, routed) 0.762 12.417 u_cpu/addr_trans/tlb_entry/sc_cancel_req
|
|
SLICE_X46Y35 f u_cpu/addr_trans/tlb_entry/main_state[0]_i_3/I1
|
|
SLICE_X46Y35 LUT3 (Prop_lut3_I1_O) 0.124 12.541 f u_cpu/addr_trans/tlb_entry/main_state[0]_i_3/O
|
|
net (fo=3, routed) 0.719 13.260 u_cpu/dcache/main_state_reg[0]_2
|
|
SLICE_X43Y31 f u_cpu/dcache/ds_to_es_bus_r[235]_i_10/I3
|
|
SLICE_X43Y31 LUT6 (Prop_lut6_I3_O) 0.124 13.384 f u_cpu/dcache/ds_to_es_bus_r[235]_i_10/O
|
|
net (fo=3, routed) 0.415 13.799 u_cpu/mem_stage/data_data_ok
|
|
SLICE_X43Y30 f u_cpu/mem_stage/flush_inst_req_buffer[1]_i_15/I0
|
|
SLICE_X43Y30 LUT3 (Prop_lut3_I0_O) 0.124 13.923 f u_cpu/mem_stage/flush_inst_req_buffer[1]_i_15/O
|
|
net (fo=2, routed) 0.833 14.756 u_cpu/mem_stage/es_to_ms_bus_r_reg[70]_1
|
|
SLICE_X48Y30 f u_cpu/mem_stage/flush_inst_req_buffer[1]_i_14/I0
|
|
SLICE_X48Y30 LUT6 (Prop_lut6_I0_O) 0.124 14.880 f u_cpu/mem_stage/flush_inst_req_buffer[1]_i_14/O
|
|
net (fo=1, routed) 0.651 15.532 u_cpu/mem_stage/ms_ready_go
|
|
SLICE_X48Y25 f u_cpu/mem_stage/flush_inst_req_buffer[1]_i_13/I4
|
|
SLICE_X48Y25 LUT6 (Prop_lut6_I4_O) 0.124 15.656 f u_cpu/mem_stage/flush_inst_req_buffer[1]_i_13/O
|
|
net (fo=3, routed) 0.483 16.139 u_cpu/id_stage/flush_inst_req_buffer[31]_i_6
|
|
SLICE_X50Y25 f u_cpu/id_stage/flush_inst_req_buffer[1]_i_9/I1
|
|
SLICE_X50Y25 LUT6 (Prop_lut6_I1_O) 0.124 16.263 f u_cpu/id_stage/flush_inst_req_buffer[1]_i_9/O
|
|
net (fo=32, routed) 0.531 16.794 u_cpu/if_stage/nextpc5
|
|
SLICE_X51Y27 f u_cpu/if_stage/fetch_pc_r[6]_i_4/I2
|
|
SLICE_X51Y27 LUT6 (Prop_lut6_I2_O) 0.124 16.918 r u_cpu/if_stage/fetch_pc_r[6]_i_4/O
|
|
net (fo=1, routed) 3.059 19.977 u_cpu/if_stage/fetch_pc_r[6]_i_4_n_0
|
|
SLICE_X114Y28 r u_cpu/if_stage/fetch_pc_r[6]_i_2/I2
|
|
SLICE_X114Y28 LUT6 (Prop_lut6_I2_O) 0.124 20.101 r u_cpu/if_stage/fetch_pc_r[6]_i_2/O
|
|
net (fo=1, routed) 0.441 20.542 u_cpu/if_stage/fetch_pc_r[6]_i_2_n_0
|
|
SLICE_X114Y25 r u_cpu/if_stage/fetch_pc_r[6]_i_1/I2
|
|
SLICE_X114Y25 LUT6 (Prop_lut6_I2_O) 0.124 20.666 r u_cpu/if_stage/fetch_pc_r[6]_i_1/O
|
|
net (fo=6, routed) 3.249 23.915 u_cpu/icache/tagv_ram_way[1].u/mem_reg_reg_2[2]
|
|
SLICE_X49Y33 r u_cpu/icache/tagv_ram_way[1].u/mem_reg_reg_i_8/I4
|
|
SLICE_X49Y33 LUT5 (Prop_lut5_I4_O) 0.124 24.039 r u_cpu/icache/tagv_ram_way[1].u/mem_reg_reg_i_8/O
|
|
net (fo=16, routed) 1.477 25.516 u_cpu/icache/data_ram_way[0].data_ram_bank[3].u/ADDRBWRADDR[2]
|
|
RAMB18_X2Y3 RAMB18E1 r u_cpu/icache/data_ram_way[0].data_ram_bank[3].u/mem_reg_reg/ADDRARDADDR[7]
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock cpu_clk rise edge) 30.323 30.323 r
|
|
clock source latency -5.674 24.648
|
|
propagated clock network latency
|
|
3.781 28.429
|
|
clock pessimism -0.418 28.011
|
|
clock uncertainty -0.074 27.937
|
|
RAMB18_X2Y3 RAMB18E1 (Setup_ramb18e1_CLKARDCLK_ADDRARDADDR[7])
|
|
-0.566 27.371 u_cpu/icache/data_ram_way[0].data_ram_bank[3].u/mem_reg_reg
|
|
-------------------------------------------------------------------
|
|
required time 27.371
|
|
arrival time -25.516
|
|
-------------------------------------------------------------------
|
|
slack 1.855
|
|
|
|
Slack (MET) : 1.855ns (required time - arrival time)
|
|
Source: u_cpu/addr_trans/data_vaddr_buffer_reg[14]/C
|
|
(rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns})
|
|
Destination: u_cpu/icache/data_ram_way[0].data_ram_bank[3].u/mem_reg_reg/ADDRARDADDR[7]
|
|
(rising edge-triggered cell RAMB18E1 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns})
|
|
Path Group: cpu_clk
|
|
Path Type: Setup (Max at Slow Process Corner)
|
|
Requirement: 30.323ns (cpu_clk rise@30.323ns - cpu_clk rise@0.000ns)
|
|
Data Path Delay: 27.741ns (logic 5.333ns (19.224%) route 22.408ns (80.776%))
|
|
Logic Levels: 26 (CARRY4=4 LUT3=2 LUT4=1 LUT5=2 LUT6=15 MUXF7=1 MUXF8=1)
|
|
Clock Path Skew: -0.087ns (DCD - SCD + CPR)
|
|
Destination Clock Delay (DCD): -1.893ns = ( 28.429 - 30.323 )
|
|
Source Clock Delay (SCD): -2.225ns
|
|
Clock Pessimism Removal (CPR): -0.418ns
|
|
Clock Uncertainty: 0.074ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Discrete Jitter (DJ): 0.130ns
|
|
Phase Error (PE): 0.000ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock cpu_clk rise edge) 0.000 0.000 r
|
|
clock source latency -6.275 -6.275
|
|
propagated clock network latency
|
|
4.051 -2.225
|
|
SLICE_X35Y35 FDRE 0.000 -2.225 r u_cpu/addr_trans/data_vaddr_buffer_reg[14]/C
|
|
SLICE_X35Y35 FDRE (Prop_fdre_C_Q) 0.456 -1.769 r u_cpu/addr_trans/data_vaddr_buffer_reg[14]/Q
|
|
net (fo=33, routed) 1.442 -0.326 u_cpu/addr_trans/tlb_entry/data_vaddr_buffer[2]
|
|
SLICE_X42Y40 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_226/I5
|
|
SLICE_X42Y40 LUT6 (Prop_lut6_I5_O) 0.124 -0.202 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_226/O
|
|
net (fo=1, routed) 0.000 -0.202 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_226_n_0
|
|
SLICE_X42Y40 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_111/S[0]
|
|
SLICE_X42Y40 CARRY4 (Prop_carry4_S[0]_CO[3])
|
|
0.513 0.311 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_111/CO[3]
|
|
net (fo=1, routed) 0.000 0.311 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_111_n_0
|
|
SLICE_X42Y41 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_32/CI
|
|
SLICE_X42Y41 CARRY4 (Prop_carry4_CI_CO[2])
|
|
0.229 0.540 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_32/CO[2]
|
|
net (fo=1, routed) 1.009 1.549 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_32_n_1
|
|
SLICE_X40Y47 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_9/I1
|
|
SLICE_X40Y47 LUT6 (Prop_lut6_I1_O) 0.310 1.859 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_9/O
|
|
net (fo=2, routed) 0.635 2.494 u_cpu/addr_trans/tlb_entry/match1[28]
|
|
SLICE_X38Y47 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/I2
|
|
SLICE_X38Y47 LUT4 (Prop_lut4_I2_O) 0.124 2.618 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/O
|
|
net (fo=2, routed) 0.667 3.285 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2_n_0
|
|
SLICE_X39Y47 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/I0
|
|
SLICE_X39Y47 LUT5 (Prop_lut5_I0_O) 0.124 3.409 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/O
|
|
net (fo=2, routed) 1.103 4.512 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2_n_0
|
|
SLICE_X38Y50 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/I0
|
|
SLICE_X38Y50 LUT6 (Prop_lut6_I0_O) 0.124 4.636 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/O
|
|
net (fo=89, routed) 1.162 5.797 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus[8]
|
|
SLICE_X42Y51 r u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_38__0/S
|
|
SLICE_X42Y51 MUXF7 (Prop_muxf7_S_O) 0.292 6.089 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_38__0/O
|
|
net (fo=1, routed) 0.000 6.089 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_38__0_n_0
|
|
SLICE_X42Y51 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_16__0/I1
|
|
SLICE_X42Y51 MUXF8 (Prop_muxf8_I1_O) 0.088 6.177 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_16__0/O
|
|
net (fo=1, routed) 0.957 7.134 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_16__0_n_0
|
|
SLICE_X42Y50 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7/I0
|
|
SLICE_X42Y50 LUT6 (Prop_lut6_I0_O) 0.319 7.453 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7/O
|
|
net (fo=1, routed) 0.435 7.888 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7_n_0
|
|
SLICE_X44Y50 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0/I5
|
|
SLICE_X44Y50 LUT6 (Prop_lut6_I5_O) 0.124 8.012 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0/O
|
|
net (fo=10, routed) 0.740 8.753 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0_n_0
|
|
SLICE_X44Y50 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[5]_i_1__0/I3
|
|
SLICE_X44Y50 LUT6 (Prop_lut6_I3_O) 0.124 8.877 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[5]_i_1__0/O
|
|
net (fo=6, routed) 0.845 9.722 u_cpu/u_csr/ms_to_ws_bus[13]
|
|
SLICE_X50Y46 r u_cpu/u_csr/write_buffer_way[1]_i_18/I3
|
|
SLICE_X50Y46 LUT6 (Prop_lut6_I3_O) 0.124 9.846 r u_cpu/u_csr/write_buffer_way[1]_i_18/O
|
|
net (fo=1, routed) 0.000 9.846 u_cpu/u_csr/write_buffer_way[1]_i_18_n_0
|
|
SLICE_X50Y46 r u_cpu/u_csr/write_buffer_way_reg[1]_i_11/S[0]
|
|
SLICE_X50Y46 CARRY4 (Prop_carry4_S[0]_CO[3])
|
|
0.532 10.378 f u_cpu/u_csr/write_buffer_way_reg[1]_i_11/CO[3]
|
|
net (fo=1, routed) 0.000 10.378 u_cpu/u_csr/write_buffer_way_reg[1]_i_11_n_0
|
|
SLICE_X50Y47 f u_cpu/u_csr/write_buffer_way_reg[1]_i_9/CI
|
|
SLICE_X50Y47 CARRY4 (Prop_carry4_CI_CO[1])
|
|
0.157 10.535 r u_cpu/u_csr/write_buffer_way_reg[1]_i_9/CO[1]
|
|
net (fo=2, routed) 0.791 11.326 u_cpu/wb_stage/CO[0]
|
|
SLICE_X46Y39 r u_cpu/wb_stage/write_buffer_way[1]_i_5/I1
|
|
SLICE_X46Y39 LUT6 (Prop_lut6_I1_O) 0.329 11.655 f u_cpu/wb_stage/write_buffer_way[1]_i_5/O
|
|
net (fo=7, routed) 0.762 12.417 u_cpu/addr_trans/tlb_entry/sc_cancel_req
|
|
SLICE_X46Y35 f u_cpu/addr_trans/tlb_entry/main_state[0]_i_3/I1
|
|
SLICE_X46Y35 LUT3 (Prop_lut3_I1_O) 0.124 12.541 f u_cpu/addr_trans/tlb_entry/main_state[0]_i_3/O
|
|
net (fo=3, routed) 0.719 13.260 u_cpu/dcache/main_state_reg[0]_2
|
|
SLICE_X43Y31 f u_cpu/dcache/ds_to_es_bus_r[235]_i_10/I3
|
|
SLICE_X43Y31 LUT6 (Prop_lut6_I3_O) 0.124 13.384 f u_cpu/dcache/ds_to_es_bus_r[235]_i_10/O
|
|
net (fo=3, routed) 0.415 13.799 u_cpu/mem_stage/data_data_ok
|
|
SLICE_X43Y30 f u_cpu/mem_stage/flush_inst_req_buffer[1]_i_15/I0
|
|
SLICE_X43Y30 LUT3 (Prop_lut3_I0_O) 0.124 13.923 f u_cpu/mem_stage/flush_inst_req_buffer[1]_i_15/O
|
|
net (fo=2, routed) 0.833 14.756 u_cpu/mem_stage/es_to_ms_bus_r_reg[70]_1
|
|
SLICE_X48Y30 f u_cpu/mem_stage/flush_inst_req_buffer[1]_i_14/I0
|
|
SLICE_X48Y30 LUT6 (Prop_lut6_I0_O) 0.124 14.880 f u_cpu/mem_stage/flush_inst_req_buffer[1]_i_14/O
|
|
net (fo=1, routed) 0.651 15.532 u_cpu/mem_stage/ms_ready_go
|
|
SLICE_X48Y25 f u_cpu/mem_stage/flush_inst_req_buffer[1]_i_13/I4
|
|
SLICE_X48Y25 LUT6 (Prop_lut6_I4_O) 0.124 15.656 f u_cpu/mem_stage/flush_inst_req_buffer[1]_i_13/O
|
|
net (fo=3, routed) 0.483 16.139 u_cpu/id_stage/flush_inst_req_buffer[31]_i_6
|
|
SLICE_X50Y25 f u_cpu/id_stage/flush_inst_req_buffer[1]_i_9/I1
|
|
SLICE_X50Y25 LUT6 (Prop_lut6_I1_O) 0.124 16.263 f u_cpu/id_stage/flush_inst_req_buffer[1]_i_9/O
|
|
net (fo=32, routed) 0.531 16.794 u_cpu/if_stage/nextpc5
|
|
SLICE_X51Y27 f u_cpu/if_stage/fetch_pc_r[6]_i_4/I2
|
|
SLICE_X51Y27 LUT6 (Prop_lut6_I2_O) 0.124 16.918 r u_cpu/if_stage/fetch_pc_r[6]_i_4/O
|
|
net (fo=1, routed) 3.059 19.977 u_cpu/if_stage/fetch_pc_r[6]_i_4_n_0
|
|
SLICE_X114Y28 r u_cpu/if_stage/fetch_pc_r[6]_i_2/I2
|
|
SLICE_X114Y28 LUT6 (Prop_lut6_I2_O) 0.124 20.101 r u_cpu/if_stage/fetch_pc_r[6]_i_2/O
|
|
net (fo=1, routed) 0.441 20.542 u_cpu/if_stage/fetch_pc_r[6]_i_2_n_0
|
|
SLICE_X114Y25 r u_cpu/if_stage/fetch_pc_r[6]_i_1/I2
|
|
SLICE_X114Y25 LUT6 (Prop_lut6_I2_O) 0.124 20.666 r u_cpu/if_stage/fetch_pc_r[6]_i_1/O
|
|
net (fo=6, routed) 3.249 23.915 u_cpu/icache/tagv_ram_way[1].u/mem_reg_reg_2[2]
|
|
SLICE_X49Y33 r u_cpu/icache/tagv_ram_way[1].u/mem_reg_reg_i_8/I4
|
|
SLICE_X49Y33 LUT5 (Prop_lut5_I4_O) 0.124 24.039 r u_cpu/icache/tagv_ram_way[1].u/mem_reg_reg_i_8/O
|
|
net (fo=16, routed) 1.477 25.516 u_cpu/icache/data_ram_way[0].data_ram_bank[3].u/ADDRBWRADDR[2]
|
|
RAMB18_X2Y3 RAMB18E1 r u_cpu/icache/data_ram_way[0].data_ram_bank[3].u/mem_reg_reg/ADDRARDADDR[7]
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock cpu_clk rise edge) 30.323 30.323 r
|
|
clock source latency -5.674 24.648
|
|
propagated clock network latency
|
|
3.781 28.429
|
|
clock pessimism -0.418 28.011
|
|
clock uncertainty -0.074 27.937
|
|
RAMB18_X2Y3 RAMB18E1 (Setup_ramb18e1_CLKARDCLK_ADDRARDADDR[7])
|
|
-0.566 27.371 u_cpu/icache/data_ram_way[0].data_ram_bank[3].u/mem_reg_reg
|
|
-------------------------------------------------------------------
|
|
required time 27.371
|
|
arrival time -25.516
|
|
-------------------------------------------------------------------
|
|
slack 1.855
|
|
|
|
Slack (MET) : 1.855ns (required time - arrival time)
|
|
Source: u_cpu/addr_trans/data_vaddr_buffer_reg[14]/C
|
|
(rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns})
|
|
Destination: u_cpu/icache/data_ram_way[0].data_ram_bank[3].u/mem_reg_reg/ADDRARDADDR[7]
|
|
(rising edge-triggered cell RAMB18E1 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns})
|
|
Path Group: cpu_clk
|
|
Path Type: Setup (Max at Slow Process Corner)
|
|
Requirement: 30.323ns (cpu_clk rise@30.323ns - cpu_clk rise@0.000ns)
|
|
Data Path Delay: 27.741ns (logic 5.333ns (19.224%) route 22.408ns (80.776%))
|
|
Logic Levels: 26 (CARRY4=4 LUT3=2 LUT4=1 LUT5=2 LUT6=15 MUXF7=1 MUXF8=1)
|
|
Clock Path Skew: -0.087ns (DCD - SCD + CPR)
|
|
Destination Clock Delay (DCD): -1.893ns = ( 28.429 - 30.323 )
|
|
Source Clock Delay (SCD): -2.225ns
|
|
Clock Pessimism Removal (CPR): -0.418ns
|
|
Clock Uncertainty: 0.074ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Discrete Jitter (DJ): 0.130ns
|
|
Phase Error (PE): 0.000ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock cpu_clk rise edge) 0.000 0.000 r
|
|
clock source latency -6.275 -6.275
|
|
propagated clock network latency
|
|
4.051 -2.225
|
|
SLICE_X35Y35 FDRE 0.000 -2.225 r u_cpu/addr_trans/data_vaddr_buffer_reg[14]/C
|
|
SLICE_X35Y35 FDRE (Prop_fdre_C_Q) 0.456 -1.769 r u_cpu/addr_trans/data_vaddr_buffer_reg[14]/Q
|
|
net (fo=33, routed) 1.442 -0.326 u_cpu/addr_trans/tlb_entry/data_vaddr_buffer[2]
|
|
SLICE_X42Y40 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_226/I5
|
|
SLICE_X42Y40 LUT6 (Prop_lut6_I5_O) 0.124 -0.202 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_226/O
|
|
net (fo=1, routed) 0.000 -0.202 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_226_n_0
|
|
SLICE_X42Y40 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_111/S[0]
|
|
SLICE_X42Y40 CARRY4 (Prop_carry4_S[0]_CO[3])
|
|
0.513 0.311 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_111/CO[3]
|
|
net (fo=1, routed) 0.000 0.311 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_111_n_0
|
|
SLICE_X42Y41 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_32/CI
|
|
SLICE_X42Y41 CARRY4 (Prop_carry4_CI_CO[2])
|
|
0.229 0.540 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_32/CO[2]
|
|
net (fo=1, routed) 1.009 1.549 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_32_n_1
|
|
SLICE_X40Y47 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_9/I1
|
|
SLICE_X40Y47 LUT6 (Prop_lut6_I1_O) 0.310 1.859 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_9/O
|
|
net (fo=2, routed) 0.635 2.494 u_cpu/addr_trans/tlb_entry/match1[28]
|
|
SLICE_X38Y47 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/I2
|
|
SLICE_X38Y47 LUT4 (Prop_lut4_I2_O) 0.124 2.618 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/O
|
|
net (fo=2, routed) 0.667 3.285 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2_n_0
|
|
SLICE_X39Y47 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/I0
|
|
SLICE_X39Y47 LUT5 (Prop_lut5_I0_O) 0.124 3.409 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/O
|
|
net (fo=2, routed) 1.103 4.512 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2_n_0
|
|
SLICE_X38Y50 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/I0
|
|
SLICE_X38Y50 LUT6 (Prop_lut6_I0_O) 0.124 4.636 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/O
|
|
net (fo=89, routed) 1.162 5.797 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus[8]
|
|
SLICE_X42Y51 r u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_38__0/S
|
|
SLICE_X42Y51 MUXF7 (Prop_muxf7_S_O) 0.292 6.089 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_38__0/O
|
|
net (fo=1, routed) 0.000 6.089 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_38__0_n_0
|
|
SLICE_X42Y51 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_16__0/I1
|
|
SLICE_X42Y51 MUXF8 (Prop_muxf8_I1_O) 0.088 6.177 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_16__0/O
|
|
net (fo=1, routed) 0.957 7.134 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_16__0_n_0
|
|
SLICE_X42Y50 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7/I0
|
|
SLICE_X42Y50 LUT6 (Prop_lut6_I0_O) 0.319 7.453 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7/O
|
|
net (fo=1, routed) 0.435 7.888 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7_n_0
|
|
SLICE_X44Y50 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0/I5
|
|
SLICE_X44Y50 LUT6 (Prop_lut6_I5_O) 0.124 8.012 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0/O
|
|
net (fo=10, routed) 0.740 8.753 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0_n_0
|
|
SLICE_X44Y50 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[5]_i_1__0/I3
|
|
SLICE_X44Y50 LUT6 (Prop_lut6_I3_O) 0.124 8.877 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[5]_i_1__0/O
|
|
net (fo=6, routed) 0.845 9.722 u_cpu/u_csr/ms_to_ws_bus[13]
|
|
SLICE_X50Y46 f u_cpu/u_csr/write_buffer_way[1]_i_18/I3
|
|
SLICE_X50Y46 LUT6 (Prop_lut6_I3_O) 0.124 9.846 r u_cpu/u_csr/write_buffer_way[1]_i_18/O
|
|
net (fo=1, routed) 0.000 9.846 u_cpu/u_csr/write_buffer_way[1]_i_18_n_0
|
|
SLICE_X50Y46 r u_cpu/u_csr/write_buffer_way_reg[1]_i_11/S[0]
|
|
SLICE_X50Y46 CARRY4 (Prop_carry4_S[0]_CO[3])
|
|
0.532 10.378 f u_cpu/u_csr/write_buffer_way_reg[1]_i_11/CO[3]
|
|
net (fo=1, routed) 0.000 10.378 u_cpu/u_csr/write_buffer_way_reg[1]_i_11_n_0
|
|
SLICE_X50Y47 f u_cpu/u_csr/write_buffer_way_reg[1]_i_9/CI
|
|
SLICE_X50Y47 CARRY4 (Prop_carry4_CI_CO[1])
|
|
0.157 10.535 r u_cpu/u_csr/write_buffer_way_reg[1]_i_9/CO[1]
|
|
net (fo=2, routed) 0.791 11.326 u_cpu/wb_stage/CO[0]
|
|
SLICE_X46Y39 r u_cpu/wb_stage/write_buffer_way[1]_i_5/I1
|
|
SLICE_X46Y39 LUT6 (Prop_lut6_I1_O) 0.329 11.655 f u_cpu/wb_stage/write_buffer_way[1]_i_5/O
|
|
net (fo=7, routed) 0.762 12.417 u_cpu/addr_trans/tlb_entry/sc_cancel_req
|
|
SLICE_X46Y35 f u_cpu/addr_trans/tlb_entry/main_state[0]_i_3/I1
|
|
SLICE_X46Y35 LUT3 (Prop_lut3_I1_O) 0.124 12.541 f u_cpu/addr_trans/tlb_entry/main_state[0]_i_3/O
|
|
net (fo=3, routed) 0.719 13.260 u_cpu/dcache/main_state_reg[0]_2
|
|
SLICE_X43Y31 f u_cpu/dcache/ds_to_es_bus_r[235]_i_10/I3
|
|
SLICE_X43Y31 LUT6 (Prop_lut6_I3_O) 0.124 13.384 f u_cpu/dcache/ds_to_es_bus_r[235]_i_10/O
|
|
net (fo=3, routed) 0.415 13.799 u_cpu/mem_stage/data_data_ok
|
|
SLICE_X43Y30 f u_cpu/mem_stage/flush_inst_req_buffer[1]_i_15/I0
|
|
SLICE_X43Y30 LUT3 (Prop_lut3_I0_O) 0.124 13.923 f u_cpu/mem_stage/flush_inst_req_buffer[1]_i_15/O
|
|
net (fo=2, routed) 0.833 14.756 u_cpu/mem_stage/es_to_ms_bus_r_reg[70]_1
|
|
SLICE_X48Y30 f u_cpu/mem_stage/flush_inst_req_buffer[1]_i_14/I0
|
|
SLICE_X48Y30 LUT6 (Prop_lut6_I0_O) 0.124 14.880 f u_cpu/mem_stage/flush_inst_req_buffer[1]_i_14/O
|
|
net (fo=1, routed) 0.651 15.532 u_cpu/mem_stage/ms_ready_go
|
|
SLICE_X48Y25 f u_cpu/mem_stage/flush_inst_req_buffer[1]_i_13/I4
|
|
SLICE_X48Y25 LUT6 (Prop_lut6_I4_O) 0.124 15.656 f u_cpu/mem_stage/flush_inst_req_buffer[1]_i_13/O
|
|
net (fo=3, routed) 0.483 16.139 u_cpu/id_stage/flush_inst_req_buffer[31]_i_6
|
|
SLICE_X50Y25 f u_cpu/id_stage/flush_inst_req_buffer[1]_i_9/I1
|
|
SLICE_X50Y25 LUT6 (Prop_lut6_I1_O) 0.124 16.263 f u_cpu/id_stage/flush_inst_req_buffer[1]_i_9/O
|
|
net (fo=32, routed) 0.531 16.794 u_cpu/if_stage/nextpc5
|
|
SLICE_X51Y27 f u_cpu/if_stage/fetch_pc_r[6]_i_4/I2
|
|
SLICE_X51Y27 LUT6 (Prop_lut6_I2_O) 0.124 16.918 r u_cpu/if_stage/fetch_pc_r[6]_i_4/O
|
|
net (fo=1, routed) 3.059 19.977 u_cpu/if_stage/fetch_pc_r[6]_i_4_n_0
|
|
SLICE_X114Y28 r u_cpu/if_stage/fetch_pc_r[6]_i_2/I2
|
|
SLICE_X114Y28 LUT6 (Prop_lut6_I2_O) 0.124 20.101 r u_cpu/if_stage/fetch_pc_r[6]_i_2/O
|
|
net (fo=1, routed) 0.441 20.542 u_cpu/if_stage/fetch_pc_r[6]_i_2_n_0
|
|
SLICE_X114Y25 r u_cpu/if_stage/fetch_pc_r[6]_i_1/I2
|
|
SLICE_X114Y25 LUT6 (Prop_lut6_I2_O) 0.124 20.666 r u_cpu/if_stage/fetch_pc_r[6]_i_1/O
|
|
net (fo=6, routed) 3.249 23.915 u_cpu/icache/tagv_ram_way[1].u/mem_reg_reg_2[2]
|
|
SLICE_X49Y33 r u_cpu/icache/tagv_ram_way[1].u/mem_reg_reg_i_8/I4
|
|
SLICE_X49Y33 LUT5 (Prop_lut5_I4_O) 0.124 24.039 r u_cpu/icache/tagv_ram_way[1].u/mem_reg_reg_i_8/O
|
|
net (fo=16, routed) 1.477 25.516 u_cpu/icache/data_ram_way[0].data_ram_bank[3].u/ADDRBWRADDR[2]
|
|
RAMB18_X2Y3 RAMB18E1 r u_cpu/icache/data_ram_way[0].data_ram_bank[3].u/mem_reg_reg/ADDRARDADDR[7]
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock cpu_clk rise edge) 30.323 30.323 r
|
|
clock source latency -5.674 24.648
|
|
propagated clock network latency
|
|
3.781 28.429
|
|
clock pessimism -0.418 28.011
|
|
clock uncertainty -0.074 27.937
|
|
RAMB18_X2Y3 RAMB18E1 (Setup_ramb18e1_CLKARDCLK_ADDRARDADDR[7])
|
|
-0.566 27.371 u_cpu/icache/data_ram_way[0].data_ram_bank[3].u/mem_reg_reg
|
|
-------------------------------------------------------------------
|
|
required time 27.371
|
|
arrival time -25.516
|
|
-------------------------------------------------------------------
|
|
slack 1.855
|
|
|
|
Slack (MET) : 1.856ns (required time - arrival time)
|
|
Source: u_cpu/addr_trans/data_vaddr_buffer_reg[14]/C
|
|
(rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns})
|
|
Destination: u_cpu/icache/data_ram_way[0].data_ram_bank[2].u/mem_reg_reg/ADDRBWRADDR[7]
|
|
(rising edge-triggered cell RAMB18E1 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns})
|
|
Path Group: cpu_clk
|
|
Path Type: Setup (Max at Slow Process Corner)
|
|
Requirement: 30.323ns (cpu_clk rise@30.323ns - cpu_clk rise@0.000ns)
|
|
Data Path Delay: 27.741ns (logic 5.333ns (19.224%) route 22.408ns (80.776%))
|
|
Logic Levels: 26 (CARRY4=4 LUT3=2 LUT4=1 LUT5=2 LUT6=15 MUXF7=1 MUXF8=1)
|
|
Clock Path Skew: -0.086ns (DCD - SCD + CPR)
|
|
Destination Clock Delay (DCD): -1.892ns = ( 28.430 - 30.323 )
|
|
Source Clock Delay (SCD): -2.225ns
|
|
Clock Pessimism Removal (CPR): -0.418ns
|
|
Clock Uncertainty: 0.074ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Discrete Jitter (DJ): 0.130ns
|
|
Phase Error (PE): 0.000ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock cpu_clk rise edge) 0.000 0.000 r
|
|
clock source latency -6.275 -6.275
|
|
propagated clock network latency
|
|
4.051 -2.225
|
|
SLICE_X35Y35 FDRE 0.000 -2.225 r u_cpu/addr_trans/data_vaddr_buffer_reg[14]/C
|
|
SLICE_X35Y35 FDRE (Prop_fdre_C_Q) 0.456 -1.769 r u_cpu/addr_trans/data_vaddr_buffer_reg[14]/Q
|
|
net (fo=33, routed) 1.442 -0.326 u_cpu/addr_trans/tlb_entry/data_vaddr_buffer[2]
|
|
SLICE_X42Y40 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_226/I5
|
|
SLICE_X42Y40 LUT6 (Prop_lut6_I5_O) 0.124 -0.202 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_226/O
|
|
net (fo=1, routed) 0.000 -0.202 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_226_n_0
|
|
SLICE_X42Y40 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_111/S[0]
|
|
SLICE_X42Y40 CARRY4 (Prop_carry4_S[0]_CO[3])
|
|
0.513 0.311 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_111/CO[3]
|
|
net (fo=1, routed) 0.000 0.311 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_111_n_0
|
|
SLICE_X42Y41 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_32/CI
|
|
SLICE_X42Y41 CARRY4 (Prop_carry4_CI_CO[2])
|
|
0.229 0.540 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_32/CO[2]
|
|
net (fo=1, routed) 1.009 1.549 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_32_n_1
|
|
SLICE_X40Y47 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_9/I1
|
|
SLICE_X40Y47 LUT6 (Prop_lut6_I1_O) 0.310 1.859 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_9/O
|
|
net (fo=2, routed) 0.635 2.494 u_cpu/addr_trans/tlb_entry/match1[28]
|
|
SLICE_X38Y47 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/I2
|
|
SLICE_X38Y47 LUT4 (Prop_lut4_I2_O) 0.124 2.618 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/O
|
|
net (fo=2, routed) 0.667 3.285 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2_n_0
|
|
SLICE_X39Y47 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/I0
|
|
SLICE_X39Y47 LUT5 (Prop_lut5_I0_O) 0.124 3.409 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/O
|
|
net (fo=2, routed) 1.103 4.512 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2_n_0
|
|
SLICE_X38Y50 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/I0
|
|
SLICE_X38Y50 LUT6 (Prop_lut6_I0_O) 0.124 4.636 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/O
|
|
net (fo=89, routed) 1.162 5.797 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus[8]
|
|
SLICE_X42Y51 r u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_38__0/S
|
|
SLICE_X42Y51 MUXF7 (Prop_muxf7_S_O) 0.292 6.089 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_38__0/O
|
|
net (fo=1, routed) 0.000 6.089 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_38__0_n_0
|
|
SLICE_X42Y51 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_16__0/I1
|
|
SLICE_X42Y51 MUXF8 (Prop_muxf8_I1_O) 0.088 6.177 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_16__0/O
|
|
net (fo=1, routed) 0.957 7.134 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_16__0_n_0
|
|
SLICE_X42Y50 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7/I0
|
|
SLICE_X42Y50 LUT6 (Prop_lut6_I0_O) 0.319 7.453 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7/O
|
|
net (fo=1, routed) 0.435 7.888 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7_n_0
|
|
SLICE_X44Y50 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0/I5
|
|
SLICE_X44Y50 LUT6 (Prop_lut6_I5_O) 0.124 8.012 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0/O
|
|
net (fo=10, routed) 0.740 8.753 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0_n_0
|
|
SLICE_X44Y50 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[5]_i_1__0/I3
|
|
SLICE_X44Y50 LUT6 (Prop_lut6_I3_O) 0.124 8.877 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[5]_i_1__0/O
|
|
net (fo=6, routed) 0.845 9.722 u_cpu/u_csr/ms_to_ws_bus[13]
|
|
SLICE_X50Y46 r u_cpu/u_csr/write_buffer_way[1]_i_18/I3
|
|
SLICE_X50Y46 LUT6 (Prop_lut6_I3_O) 0.124 9.846 r u_cpu/u_csr/write_buffer_way[1]_i_18/O
|
|
net (fo=1, routed) 0.000 9.846 u_cpu/u_csr/write_buffer_way[1]_i_18_n_0
|
|
SLICE_X50Y46 r u_cpu/u_csr/write_buffer_way_reg[1]_i_11/S[0]
|
|
SLICE_X50Y46 CARRY4 (Prop_carry4_S[0]_CO[3])
|
|
0.532 10.378 r u_cpu/u_csr/write_buffer_way_reg[1]_i_11/CO[3]
|
|
net (fo=1, routed) 0.000 10.378 u_cpu/u_csr/write_buffer_way_reg[1]_i_11_n_0
|
|
SLICE_X50Y47 r u_cpu/u_csr/write_buffer_way_reg[1]_i_9/CI
|
|
SLICE_X50Y47 CARRY4 (Prop_carry4_CI_CO[1])
|
|
0.157 10.535 f u_cpu/u_csr/write_buffer_way_reg[1]_i_9/CO[1]
|
|
net (fo=2, routed) 0.791 11.326 u_cpu/wb_stage/CO[0]
|
|
SLICE_X46Y39 f u_cpu/wb_stage/write_buffer_way[1]_i_5/I1
|
|
SLICE_X46Y39 LUT6 (Prop_lut6_I1_O) 0.329 11.655 r u_cpu/wb_stage/write_buffer_way[1]_i_5/O
|
|
net (fo=7, routed) 0.762 12.417 u_cpu/addr_trans/tlb_entry/sc_cancel_req
|
|
SLICE_X46Y35 r u_cpu/addr_trans/tlb_entry/main_state[0]_i_3/I1
|
|
SLICE_X46Y35 LUT3 (Prop_lut3_I1_O) 0.124 12.541 r u_cpu/addr_trans/tlb_entry/main_state[0]_i_3/O
|
|
net (fo=3, routed) 0.719 13.260 u_cpu/dcache/main_state_reg[0]_2
|
|
SLICE_X43Y31 r u_cpu/dcache/ds_to_es_bus_r[235]_i_10/I3
|
|
SLICE_X43Y31 LUT6 (Prop_lut6_I3_O) 0.124 13.384 r u_cpu/dcache/ds_to_es_bus_r[235]_i_10/O
|
|
net (fo=3, routed) 0.415 13.799 u_cpu/mem_stage/data_data_ok
|
|
SLICE_X43Y30 r u_cpu/mem_stage/flush_inst_req_buffer[1]_i_15/I0
|
|
SLICE_X43Y30 LUT3 (Prop_lut3_I0_O) 0.124 13.923 r u_cpu/mem_stage/flush_inst_req_buffer[1]_i_15/O
|
|
net (fo=2, routed) 0.833 14.756 u_cpu/mem_stage/es_to_ms_bus_r_reg[70]_1
|
|
SLICE_X48Y30 r u_cpu/mem_stage/flush_inst_req_buffer[1]_i_14/I0
|
|
SLICE_X48Y30 LUT6 (Prop_lut6_I0_O) 0.124 14.880 r u_cpu/mem_stage/flush_inst_req_buffer[1]_i_14/O
|
|
net (fo=1, routed) 0.651 15.532 u_cpu/mem_stage/ms_ready_go
|
|
SLICE_X48Y25 r u_cpu/mem_stage/flush_inst_req_buffer[1]_i_13/I4
|
|
SLICE_X48Y25 LUT6 (Prop_lut6_I4_O) 0.124 15.656 r u_cpu/mem_stage/flush_inst_req_buffer[1]_i_13/O
|
|
net (fo=3, routed) 0.483 16.139 u_cpu/id_stage/flush_inst_req_buffer[31]_i_6
|
|
SLICE_X50Y25 r u_cpu/id_stage/flush_inst_req_buffer[1]_i_9/I1
|
|
SLICE_X50Y25 LUT6 (Prop_lut6_I1_O) 0.124 16.263 r u_cpu/id_stage/flush_inst_req_buffer[1]_i_9/O
|
|
net (fo=32, routed) 0.531 16.794 u_cpu/if_stage/nextpc5
|
|
SLICE_X51Y27 r u_cpu/if_stage/fetch_pc_r[6]_i_4/I2
|
|
SLICE_X51Y27 LUT6 (Prop_lut6_I2_O) 0.124 16.918 r u_cpu/if_stage/fetch_pc_r[6]_i_4/O
|
|
net (fo=1, routed) 3.059 19.977 u_cpu/if_stage/fetch_pc_r[6]_i_4_n_0
|
|
SLICE_X114Y28 r u_cpu/if_stage/fetch_pc_r[6]_i_2/I2
|
|
SLICE_X114Y28 LUT6 (Prop_lut6_I2_O) 0.124 20.101 r u_cpu/if_stage/fetch_pc_r[6]_i_2/O
|
|
net (fo=1, routed) 0.441 20.542 u_cpu/if_stage/fetch_pc_r[6]_i_2_n_0
|
|
SLICE_X114Y25 r u_cpu/if_stage/fetch_pc_r[6]_i_1/I2
|
|
SLICE_X114Y25 LUT6 (Prop_lut6_I2_O) 0.124 20.666 r u_cpu/if_stage/fetch_pc_r[6]_i_1/O
|
|
net (fo=6, routed) 3.249 23.915 u_cpu/icache/tagv_ram_way[1].u/mem_reg_reg_2[2]
|
|
SLICE_X49Y33 r u_cpu/icache/tagv_ram_way[1].u/mem_reg_reg_i_8/I4
|
|
SLICE_X49Y33 LUT5 (Prop_lut5_I4_O) 0.124 24.039 r u_cpu/icache/tagv_ram_way[1].u/mem_reg_reg_i_8/O
|
|
net (fo=16, routed) 1.477 25.516 u_cpu/icache/data_ram_way[0].data_ram_bank[2].u/ADDRBWRADDR[2]
|
|
RAMB18_X2Y2 RAMB18E1 r u_cpu/icache/data_ram_way[0].data_ram_bank[2].u/mem_reg_reg/ADDRBWRADDR[7]
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock cpu_clk rise edge) 30.323 30.323 r
|
|
clock source latency -5.674 24.648
|
|
propagated clock network latency
|
|
3.782 28.430
|
|
clock pessimism -0.418 28.012
|
|
clock uncertainty -0.074 27.938
|
|
RAMB18_X2Y2 RAMB18E1 (Setup_ramb18e1_CLKBWRCLK_ADDRBWRADDR[7])
|
|
-0.566 27.372 u_cpu/icache/data_ram_way[0].data_ram_bank[2].u/mem_reg_reg
|
|
-------------------------------------------------------------------
|
|
required time 27.372
|
|
arrival time -25.516
|
|
-------------------------------------------------------------------
|
|
slack 1.856
|
|
|
|
Slack (MET) : 1.856ns (required time - arrival time)
|
|
Source: u_cpu/addr_trans/data_vaddr_buffer_reg[14]/C
|
|
(rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns})
|
|
Destination: u_cpu/icache/data_ram_way[0].data_ram_bank[2].u/mem_reg_reg/ADDRBWRADDR[7]
|
|
(rising edge-triggered cell RAMB18E1 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns})
|
|
Path Group: cpu_clk
|
|
Path Type: Setup (Max at Slow Process Corner)
|
|
Requirement: 30.323ns (cpu_clk rise@30.323ns - cpu_clk rise@0.000ns)
|
|
Data Path Delay: 27.741ns (logic 5.333ns (19.224%) route 22.408ns (80.776%))
|
|
Logic Levels: 26 (CARRY4=4 LUT3=2 LUT4=1 LUT5=2 LUT6=15 MUXF7=1 MUXF8=1)
|
|
Clock Path Skew: -0.086ns (DCD - SCD + CPR)
|
|
Destination Clock Delay (DCD): -1.892ns = ( 28.430 - 30.323 )
|
|
Source Clock Delay (SCD): -2.225ns
|
|
Clock Pessimism Removal (CPR): -0.418ns
|
|
Clock Uncertainty: 0.074ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Discrete Jitter (DJ): 0.130ns
|
|
Phase Error (PE): 0.000ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock cpu_clk rise edge) 0.000 0.000 r
|
|
clock source latency -6.275 -6.275
|
|
propagated clock network latency
|
|
4.051 -2.225
|
|
SLICE_X35Y35 FDRE 0.000 -2.225 r u_cpu/addr_trans/data_vaddr_buffer_reg[14]/C
|
|
SLICE_X35Y35 FDRE (Prop_fdre_C_Q) 0.456 -1.769 r u_cpu/addr_trans/data_vaddr_buffer_reg[14]/Q
|
|
net (fo=33, routed) 1.442 -0.326 u_cpu/addr_trans/tlb_entry/data_vaddr_buffer[2]
|
|
SLICE_X42Y40 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_226/I5
|
|
SLICE_X42Y40 LUT6 (Prop_lut6_I5_O) 0.124 -0.202 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_226/O
|
|
net (fo=1, routed) 0.000 -0.202 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_226_n_0
|
|
SLICE_X42Y40 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_111/S[0]
|
|
SLICE_X42Y40 CARRY4 (Prop_carry4_S[0]_CO[3])
|
|
0.513 0.311 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_111/CO[3]
|
|
net (fo=1, routed) 0.000 0.311 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_111_n_0
|
|
SLICE_X42Y41 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_32/CI
|
|
SLICE_X42Y41 CARRY4 (Prop_carry4_CI_CO[2])
|
|
0.229 0.540 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_32/CO[2]
|
|
net (fo=1, routed) 1.009 1.549 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_32_n_1
|
|
SLICE_X40Y47 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_9/I1
|
|
SLICE_X40Y47 LUT6 (Prop_lut6_I1_O) 0.310 1.859 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_9/O
|
|
net (fo=2, routed) 0.635 2.494 u_cpu/addr_trans/tlb_entry/match1[28]
|
|
SLICE_X38Y47 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/I2
|
|
SLICE_X38Y47 LUT4 (Prop_lut4_I2_O) 0.124 2.618 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/O
|
|
net (fo=2, routed) 0.667 3.285 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2_n_0
|
|
SLICE_X39Y47 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/I0
|
|
SLICE_X39Y47 LUT5 (Prop_lut5_I0_O) 0.124 3.409 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/O
|
|
net (fo=2, routed) 1.103 4.512 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2_n_0
|
|
SLICE_X38Y50 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/I0
|
|
SLICE_X38Y50 LUT6 (Prop_lut6_I0_O) 0.124 4.636 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/O
|
|
net (fo=89, routed) 1.162 5.797 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus[8]
|
|
SLICE_X42Y51 r u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_38__0/S
|
|
SLICE_X42Y51 MUXF7 (Prop_muxf7_S_O) 0.292 6.089 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_38__0/O
|
|
net (fo=1, routed) 0.000 6.089 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_38__0_n_0
|
|
SLICE_X42Y51 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_16__0/I1
|
|
SLICE_X42Y51 MUXF8 (Prop_muxf8_I1_O) 0.088 6.177 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_16__0/O
|
|
net (fo=1, routed) 0.957 7.134 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_16__0_n_0
|
|
SLICE_X42Y50 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7/I0
|
|
SLICE_X42Y50 LUT6 (Prop_lut6_I0_O) 0.319 7.453 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7/O
|
|
net (fo=1, routed) 0.435 7.888 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7_n_0
|
|
SLICE_X44Y50 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0/I5
|
|
SLICE_X44Y50 LUT6 (Prop_lut6_I5_O) 0.124 8.012 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0/O
|
|
net (fo=10, routed) 0.740 8.753 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0_n_0
|
|
SLICE_X44Y50 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[5]_i_1__0/I3
|
|
SLICE_X44Y50 LUT6 (Prop_lut6_I3_O) 0.124 8.877 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[5]_i_1__0/O
|
|
net (fo=6, routed) 0.845 9.722 u_cpu/u_csr/ms_to_ws_bus[13]
|
|
SLICE_X50Y46 f u_cpu/u_csr/write_buffer_way[1]_i_18/I3
|
|
SLICE_X50Y46 LUT6 (Prop_lut6_I3_O) 0.124 9.846 r u_cpu/u_csr/write_buffer_way[1]_i_18/O
|
|
net (fo=1, routed) 0.000 9.846 u_cpu/u_csr/write_buffer_way[1]_i_18_n_0
|
|
SLICE_X50Y46 r u_cpu/u_csr/write_buffer_way_reg[1]_i_11/S[0]
|
|
SLICE_X50Y46 CARRY4 (Prop_carry4_S[0]_CO[3])
|
|
0.532 10.378 r u_cpu/u_csr/write_buffer_way_reg[1]_i_11/CO[3]
|
|
net (fo=1, routed) 0.000 10.378 u_cpu/u_csr/write_buffer_way_reg[1]_i_11_n_0
|
|
SLICE_X50Y47 r u_cpu/u_csr/write_buffer_way_reg[1]_i_9/CI
|
|
SLICE_X50Y47 CARRY4 (Prop_carry4_CI_CO[1])
|
|
0.157 10.535 f u_cpu/u_csr/write_buffer_way_reg[1]_i_9/CO[1]
|
|
net (fo=2, routed) 0.791 11.326 u_cpu/wb_stage/CO[0]
|
|
SLICE_X46Y39 f u_cpu/wb_stage/write_buffer_way[1]_i_5/I1
|
|
SLICE_X46Y39 LUT6 (Prop_lut6_I1_O) 0.329 11.655 r u_cpu/wb_stage/write_buffer_way[1]_i_5/O
|
|
net (fo=7, routed) 0.762 12.417 u_cpu/addr_trans/tlb_entry/sc_cancel_req
|
|
SLICE_X46Y35 r u_cpu/addr_trans/tlb_entry/main_state[0]_i_3/I1
|
|
SLICE_X46Y35 LUT3 (Prop_lut3_I1_O) 0.124 12.541 r u_cpu/addr_trans/tlb_entry/main_state[0]_i_3/O
|
|
net (fo=3, routed) 0.719 13.260 u_cpu/dcache/main_state_reg[0]_2
|
|
SLICE_X43Y31 r u_cpu/dcache/ds_to_es_bus_r[235]_i_10/I3
|
|
SLICE_X43Y31 LUT6 (Prop_lut6_I3_O) 0.124 13.384 r u_cpu/dcache/ds_to_es_bus_r[235]_i_10/O
|
|
net (fo=3, routed) 0.415 13.799 u_cpu/mem_stage/data_data_ok
|
|
SLICE_X43Y30 r u_cpu/mem_stage/flush_inst_req_buffer[1]_i_15/I0
|
|
SLICE_X43Y30 LUT3 (Prop_lut3_I0_O) 0.124 13.923 r u_cpu/mem_stage/flush_inst_req_buffer[1]_i_15/O
|
|
net (fo=2, routed) 0.833 14.756 u_cpu/mem_stage/es_to_ms_bus_r_reg[70]_1
|
|
SLICE_X48Y30 r u_cpu/mem_stage/flush_inst_req_buffer[1]_i_14/I0
|
|
SLICE_X48Y30 LUT6 (Prop_lut6_I0_O) 0.124 14.880 r u_cpu/mem_stage/flush_inst_req_buffer[1]_i_14/O
|
|
net (fo=1, routed) 0.651 15.532 u_cpu/mem_stage/ms_ready_go
|
|
SLICE_X48Y25 r u_cpu/mem_stage/flush_inst_req_buffer[1]_i_13/I4
|
|
SLICE_X48Y25 LUT6 (Prop_lut6_I4_O) 0.124 15.656 r u_cpu/mem_stage/flush_inst_req_buffer[1]_i_13/O
|
|
net (fo=3, routed) 0.483 16.139 u_cpu/id_stage/flush_inst_req_buffer[31]_i_6
|
|
SLICE_X50Y25 r u_cpu/id_stage/flush_inst_req_buffer[1]_i_9/I1
|
|
SLICE_X50Y25 LUT6 (Prop_lut6_I1_O) 0.124 16.263 r u_cpu/id_stage/flush_inst_req_buffer[1]_i_9/O
|
|
net (fo=32, routed) 0.531 16.794 u_cpu/if_stage/nextpc5
|
|
SLICE_X51Y27 r u_cpu/if_stage/fetch_pc_r[6]_i_4/I2
|
|
SLICE_X51Y27 LUT6 (Prop_lut6_I2_O) 0.124 16.918 r u_cpu/if_stage/fetch_pc_r[6]_i_4/O
|
|
net (fo=1, routed) 3.059 19.977 u_cpu/if_stage/fetch_pc_r[6]_i_4_n_0
|
|
SLICE_X114Y28 r u_cpu/if_stage/fetch_pc_r[6]_i_2/I2
|
|
SLICE_X114Y28 LUT6 (Prop_lut6_I2_O) 0.124 20.101 r u_cpu/if_stage/fetch_pc_r[6]_i_2/O
|
|
net (fo=1, routed) 0.441 20.542 u_cpu/if_stage/fetch_pc_r[6]_i_2_n_0
|
|
SLICE_X114Y25 r u_cpu/if_stage/fetch_pc_r[6]_i_1/I2
|
|
SLICE_X114Y25 LUT6 (Prop_lut6_I2_O) 0.124 20.666 r u_cpu/if_stage/fetch_pc_r[6]_i_1/O
|
|
net (fo=6, routed) 3.249 23.915 u_cpu/icache/tagv_ram_way[1].u/mem_reg_reg_2[2]
|
|
SLICE_X49Y33 r u_cpu/icache/tagv_ram_way[1].u/mem_reg_reg_i_8/I4
|
|
SLICE_X49Y33 LUT5 (Prop_lut5_I4_O) 0.124 24.039 r u_cpu/icache/tagv_ram_way[1].u/mem_reg_reg_i_8/O
|
|
net (fo=16, routed) 1.477 25.516 u_cpu/icache/data_ram_way[0].data_ram_bank[2].u/ADDRBWRADDR[2]
|
|
RAMB18_X2Y2 RAMB18E1 r u_cpu/icache/data_ram_way[0].data_ram_bank[2].u/mem_reg_reg/ADDRBWRADDR[7]
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock cpu_clk rise edge) 30.323 30.323 r
|
|
clock source latency -5.674 24.648
|
|
propagated clock network latency
|
|
3.782 28.430
|
|
clock pessimism -0.418 28.012
|
|
clock uncertainty -0.074 27.938
|
|
RAMB18_X2Y2 RAMB18E1 (Setup_ramb18e1_CLKBWRCLK_ADDRBWRADDR[7])
|
|
-0.566 27.372 u_cpu/icache/data_ram_way[0].data_ram_bank[2].u/mem_reg_reg
|
|
-------------------------------------------------------------------
|
|
required time 27.372
|
|
arrival time -25.516
|
|
-------------------------------------------------------------------
|
|
slack 1.856
|
|
|
|
Slack (MET) : 1.856ns (required time - arrival time)
|
|
Source: u_cpu/addr_trans/data_vaddr_buffer_reg[14]/C
|
|
(rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns})
|
|
Destination: u_cpu/icache/data_ram_way[0].data_ram_bank[2].u/mem_reg_reg/ADDRBWRADDR[7]
|
|
(rising edge-triggered cell RAMB18E1 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns})
|
|
Path Group: cpu_clk
|
|
Path Type: Setup (Max at Slow Process Corner)
|
|
Requirement: 30.323ns (cpu_clk rise@30.323ns - cpu_clk rise@0.000ns)
|
|
Data Path Delay: 27.741ns (logic 5.333ns (19.224%) route 22.408ns (80.776%))
|
|
Logic Levels: 26 (CARRY4=4 LUT3=2 LUT4=1 LUT5=2 LUT6=15 MUXF7=1 MUXF8=1)
|
|
Clock Path Skew: -0.086ns (DCD - SCD + CPR)
|
|
Destination Clock Delay (DCD): -1.892ns = ( 28.430 - 30.323 )
|
|
Source Clock Delay (SCD): -2.225ns
|
|
Clock Pessimism Removal (CPR): -0.418ns
|
|
Clock Uncertainty: 0.074ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Discrete Jitter (DJ): 0.130ns
|
|
Phase Error (PE): 0.000ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock cpu_clk rise edge) 0.000 0.000 r
|
|
clock source latency -6.275 -6.275
|
|
propagated clock network latency
|
|
4.051 -2.225
|
|
SLICE_X35Y35 FDRE 0.000 -2.225 r u_cpu/addr_trans/data_vaddr_buffer_reg[14]/C
|
|
SLICE_X35Y35 FDRE (Prop_fdre_C_Q) 0.456 -1.769 r u_cpu/addr_trans/data_vaddr_buffer_reg[14]/Q
|
|
net (fo=33, routed) 1.442 -0.326 u_cpu/addr_trans/tlb_entry/data_vaddr_buffer[2]
|
|
SLICE_X42Y40 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_226/I5
|
|
SLICE_X42Y40 LUT6 (Prop_lut6_I5_O) 0.124 -0.202 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_226/O
|
|
net (fo=1, routed) 0.000 -0.202 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_226_n_0
|
|
SLICE_X42Y40 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_111/S[0]
|
|
SLICE_X42Y40 CARRY4 (Prop_carry4_S[0]_CO[3])
|
|
0.513 0.311 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_111/CO[3]
|
|
net (fo=1, routed) 0.000 0.311 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_111_n_0
|
|
SLICE_X42Y41 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_32/CI
|
|
SLICE_X42Y41 CARRY4 (Prop_carry4_CI_CO[2])
|
|
0.229 0.540 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_32/CO[2]
|
|
net (fo=1, routed) 1.009 1.549 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_32_n_1
|
|
SLICE_X40Y47 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_9/I1
|
|
SLICE_X40Y47 LUT6 (Prop_lut6_I1_O) 0.310 1.859 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_9/O
|
|
net (fo=2, routed) 0.635 2.494 u_cpu/addr_trans/tlb_entry/match1[28]
|
|
SLICE_X38Y47 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/I2
|
|
SLICE_X38Y47 LUT4 (Prop_lut4_I2_O) 0.124 2.618 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/O
|
|
net (fo=2, routed) 0.667 3.285 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2_n_0
|
|
SLICE_X39Y47 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/I0
|
|
SLICE_X39Y47 LUT5 (Prop_lut5_I0_O) 0.124 3.409 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/O
|
|
net (fo=2, routed) 1.103 4.512 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2_n_0
|
|
SLICE_X38Y50 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/I0
|
|
SLICE_X38Y50 LUT6 (Prop_lut6_I0_O) 0.124 4.636 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/O
|
|
net (fo=89, routed) 1.162 5.797 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus[8]
|
|
SLICE_X42Y51 r u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_38__0/S
|
|
SLICE_X42Y51 MUXF7 (Prop_muxf7_S_O) 0.292 6.089 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_38__0/O
|
|
net (fo=1, routed) 0.000 6.089 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_38__0_n_0
|
|
SLICE_X42Y51 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_16__0/I1
|
|
SLICE_X42Y51 MUXF8 (Prop_muxf8_I1_O) 0.088 6.177 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_16__0/O
|
|
net (fo=1, routed) 0.957 7.134 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_16__0_n_0
|
|
SLICE_X42Y50 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7/I0
|
|
SLICE_X42Y50 LUT6 (Prop_lut6_I0_O) 0.319 7.453 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7/O
|
|
net (fo=1, routed) 0.435 7.888 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7_n_0
|
|
SLICE_X44Y50 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0/I5
|
|
SLICE_X44Y50 LUT6 (Prop_lut6_I5_O) 0.124 8.012 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0/O
|
|
net (fo=10, routed) 0.740 8.753 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0_n_0
|
|
SLICE_X44Y50 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[5]_i_1__0/I3
|
|
SLICE_X44Y50 LUT6 (Prop_lut6_I3_O) 0.124 8.877 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[5]_i_1__0/O
|
|
net (fo=6, routed) 0.845 9.722 u_cpu/u_csr/ms_to_ws_bus[13]
|
|
SLICE_X50Y46 r u_cpu/u_csr/write_buffer_way[1]_i_18/I3
|
|
SLICE_X50Y46 LUT6 (Prop_lut6_I3_O) 0.124 9.846 f u_cpu/u_csr/write_buffer_way[1]_i_18/O
|
|
net (fo=1, routed) 0.000 9.846 u_cpu/u_csr/write_buffer_way[1]_i_18_n_0
|
|
SLICE_X50Y46 f u_cpu/u_csr/write_buffer_way_reg[1]_i_11/S[0]
|
|
SLICE_X50Y46 CARRY4 (Prop_carry4_S[0]_CO[3])
|
|
0.532 10.378 r u_cpu/u_csr/write_buffer_way_reg[1]_i_11/CO[3]
|
|
net (fo=1, routed) 0.000 10.378 u_cpu/u_csr/write_buffer_way_reg[1]_i_11_n_0
|
|
SLICE_X50Y47 r u_cpu/u_csr/write_buffer_way_reg[1]_i_9/CI
|
|
SLICE_X50Y47 CARRY4 (Prop_carry4_CI_CO[1])
|
|
0.157 10.535 f u_cpu/u_csr/write_buffer_way_reg[1]_i_9/CO[1]
|
|
net (fo=2, routed) 0.791 11.326 u_cpu/wb_stage/CO[0]
|
|
SLICE_X46Y39 f u_cpu/wb_stage/write_buffer_way[1]_i_5/I1
|
|
SLICE_X46Y39 LUT6 (Prop_lut6_I1_O) 0.329 11.655 r u_cpu/wb_stage/write_buffer_way[1]_i_5/O
|
|
net (fo=7, routed) 0.762 12.417 u_cpu/addr_trans/tlb_entry/sc_cancel_req
|
|
SLICE_X46Y35 r u_cpu/addr_trans/tlb_entry/main_state[0]_i_3/I1
|
|
SLICE_X46Y35 LUT3 (Prop_lut3_I1_O) 0.124 12.541 r u_cpu/addr_trans/tlb_entry/main_state[0]_i_3/O
|
|
net (fo=3, routed) 0.719 13.260 u_cpu/dcache/main_state_reg[0]_2
|
|
SLICE_X43Y31 r u_cpu/dcache/ds_to_es_bus_r[235]_i_10/I3
|
|
SLICE_X43Y31 LUT6 (Prop_lut6_I3_O) 0.124 13.384 r u_cpu/dcache/ds_to_es_bus_r[235]_i_10/O
|
|
net (fo=3, routed) 0.415 13.799 u_cpu/mem_stage/data_data_ok
|
|
SLICE_X43Y30 r u_cpu/mem_stage/flush_inst_req_buffer[1]_i_15/I0
|
|
SLICE_X43Y30 LUT3 (Prop_lut3_I0_O) 0.124 13.923 r u_cpu/mem_stage/flush_inst_req_buffer[1]_i_15/O
|
|
net (fo=2, routed) 0.833 14.756 u_cpu/mem_stage/es_to_ms_bus_r_reg[70]_1
|
|
SLICE_X48Y30 r u_cpu/mem_stage/flush_inst_req_buffer[1]_i_14/I0
|
|
SLICE_X48Y30 LUT6 (Prop_lut6_I0_O) 0.124 14.880 r u_cpu/mem_stage/flush_inst_req_buffer[1]_i_14/O
|
|
net (fo=1, routed) 0.651 15.532 u_cpu/mem_stage/ms_ready_go
|
|
SLICE_X48Y25 r u_cpu/mem_stage/flush_inst_req_buffer[1]_i_13/I4
|
|
SLICE_X48Y25 LUT6 (Prop_lut6_I4_O) 0.124 15.656 r u_cpu/mem_stage/flush_inst_req_buffer[1]_i_13/O
|
|
net (fo=3, routed) 0.483 16.139 u_cpu/id_stage/flush_inst_req_buffer[31]_i_6
|
|
SLICE_X50Y25 r u_cpu/id_stage/flush_inst_req_buffer[1]_i_9/I1
|
|
SLICE_X50Y25 LUT6 (Prop_lut6_I1_O) 0.124 16.263 r u_cpu/id_stage/flush_inst_req_buffer[1]_i_9/O
|
|
net (fo=32, routed) 0.531 16.794 u_cpu/if_stage/nextpc5
|
|
SLICE_X51Y27 r u_cpu/if_stage/fetch_pc_r[6]_i_4/I2
|
|
SLICE_X51Y27 LUT6 (Prop_lut6_I2_O) 0.124 16.918 r u_cpu/if_stage/fetch_pc_r[6]_i_4/O
|
|
net (fo=1, routed) 3.059 19.977 u_cpu/if_stage/fetch_pc_r[6]_i_4_n_0
|
|
SLICE_X114Y28 r u_cpu/if_stage/fetch_pc_r[6]_i_2/I2
|
|
SLICE_X114Y28 LUT6 (Prop_lut6_I2_O) 0.124 20.101 r u_cpu/if_stage/fetch_pc_r[6]_i_2/O
|
|
net (fo=1, routed) 0.441 20.542 u_cpu/if_stage/fetch_pc_r[6]_i_2_n_0
|
|
SLICE_X114Y25 r u_cpu/if_stage/fetch_pc_r[6]_i_1/I2
|
|
SLICE_X114Y25 LUT6 (Prop_lut6_I2_O) 0.124 20.666 r u_cpu/if_stage/fetch_pc_r[6]_i_1/O
|
|
net (fo=6, routed) 3.249 23.915 u_cpu/icache/tagv_ram_way[1].u/mem_reg_reg_2[2]
|
|
SLICE_X49Y33 r u_cpu/icache/tagv_ram_way[1].u/mem_reg_reg_i_8/I4
|
|
SLICE_X49Y33 LUT5 (Prop_lut5_I4_O) 0.124 24.039 r u_cpu/icache/tagv_ram_way[1].u/mem_reg_reg_i_8/O
|
|
net (fo=16, routed) 1.477 25.516 u_cpu/icache/data_ram_way[0].data_ram_bank[2].u/ADDRBWRADDR[2]
|
|
RAMB18_X2Y2 RAMB18E1 r u_cpu/icache/data_ram_way[0].data_ram_bank[2].u/mem_reg_reg/ADDRBWRADDR[7]
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock cpu_clk rise edge) 30.323 30.323 r
|
|
clock source latency -5.674 24.648
|
|
propagated clock network latency
|
|
3.782 28.430
|
|
clock pessimism -0.418 28.012
|
|
clock uncertainty -0.074 27.938
|
|
RAMB18_X2Y2 RAMB18E1 (Setup_ramb18e1_CLKBWRCLK_ADDRBWRADDR[7])
|
|
-0.566 27.372 u_cpu/icache/data_ram_way[0].data_ram_bank[2].u/mem_reg_reg
|
|
-------------------------------------------------------------------
|
|
required time 27.372
|
|
arrival time -25.516
|
|
-------------------------------------------------------------------
|
|
slack 1.856
|
|
|
|
Slack (MET) : 1.856ns (required time - arrival time)
|
|
Source: u_cpu/addr_trans/data_vaddr_buffer_reg[14]/C
|
|
(rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns})
|
|
Destination: u_cpu/icache/data_ram_way[0].data_ram_bank[2].u/mem_reg_reg/ADDRBWRADDR[7]
|
|
(rising edge-triggered cell RAMB18E1 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns})
|
|
Path Group: cpu_clk
|
|
Path Type: Setup (Max at Slow Process Corner)
|
|
Requirement: 30.323ns (cpu_clk rise@30.323ns - cpu_clk rise@0.000ns)
|
|
Data Path Delay: 27.741ns (logic 5.333ns (19.224%) route 22.408ns (80.776%))
|
|
Logic Levels: 26 (CARRY4=4 LUT3=2 LUT4=1 LUT5=2 LUT6=15 MUXF7=1 MUXF8=1)
|
|
Clock Path Skew: -0.086ns (DCD - SCD + CPR)
|
|
Destination Clock Delay (DCD): -1.892ns = ( 28.430 - 30.323 )
|
|
Source Clock Delay (SCD): -2.225ns
|
|
Clock Pessimism Removal (CPR): -0.418ns
|
|
Clock Uncertainty: 0.074ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Discrete Jitter (DJ): 0.130ns
|
|
Phase Error (PE): 0.000ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock cpu_clk rise edge) 0.000 0.000 r
|
|
clock source latency -6.275 -6.275
|
|
propagated clock network latency
|
|
4.051 -2.225
|
|
SLICE_X35Y35 FDRE 0.000 -2.225 r u_cpu/addr_trans/data_vaddr_buffer_reg[14]/C
|
|
SLICE_X35Y35 FDRE (Prop_fdre_C_Q) 0.456 -1.769 r u_cpu/addr_trans/data_vaddr_buffer_reg[14]/Q
|
|
net (fo=33, routed) 1.442 -0.326 u_cpu/addr_trans/tlb_entry/data_vaddr_buffer[2]
|
|
SLICE_X42Y40 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_226/I5
|
|
SLICE_X42Y40 LUT6 (Prop_lut6_I5_O) 0.124 -0.202 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_226/O
|
|
net (fo=1, routed) 0.000 -0.202 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_226_n_0
|
|
SLICE_X42Y40 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_111/S[0]
|
|
SLICE_X42Y40 CARRY4 (Prop_carry4_S[0]_CO[3])
|
|
0.513 0.311 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_111/CO[3]
|
|
net (fo=1, routed) 0.000 0.311 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_111_n_0
|
|
SLICE_X42Y41 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_32/CI
|
|
SLICE_X42Y41 CARRY4 (Prop_carry4_CI_CO[2])
|
|
0.229 0.540 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_32/CO[2]
|
|
net (fo=1, routed) 1.009 1.549 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_32_n_1
|
|
SLICE_X40Y47 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_9/I1
|
|
SLICE_X40Y47 LUT6 (Prop_lut6_I1_O) 0.310 1.859 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_9/O
|
|
net (fo=2, routed) 0.635 2.494 u_cpu/addr_trans/tlb_entry/match1[28]
|
|
SLICE_X38Y47 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/I2
|
|
SLICE_X38Y47 LUT4 (Prop_lut4_I2_O) 0.124 2.618 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/O
|
|
net (fo=2, routed) 0.667 3.285 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2_n_0
|
|
SLICE_X39Y47 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/I0
|
|
SLICE_X39Y47 LUT5 (Prop_lut5_I0_O) 0.124 3.409 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/O
|
|
net (fo=2, routed) 1.103 4.512 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2_n_0
|
|
SLICE_X38Y50 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/I0
|
|
SLICE_X38Y50 LUT6 (Prop_lut6_I0_O) 0.124 4.636 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/O
|
|
net (fo=89, routed) 1.162 5.797 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus[8]
|
|
SLICE_X42Y51 r u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_38__0/S
|
|
SLICE_X42Y51 MUXF7 (Prop_muxf7_S_O) 0.292 6.089 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_38__0/O
|
|
net (fo=1, routed) 0.000 6.089 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_38__0_n_0
|
|
SLICE_X42Y51 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_16__0/I1
|
|
SLICE_X42Y51 MUXF8 (Prop_muxf8_I1_O) 0.088 6.177 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_16__0/O
|
|
net (fo=1, routed) 0.957 7.134 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_16__0_n_0
|
|
SLICE_X42Y50 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7/I0
|
|
SLICE_X42Y50 LUT6 (Prop_lut6_I0_O) 0.319 7.453 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7/O
|
|
net (fo=1, routed) 0.435 7.888 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7_n_0
|
|
SLICE_X44Y50 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0/I5
|
|
SLICE_X44Y50 LUT6 (Prop_lut6_I5_O) 0.124 8.012 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0/O
|
|
net (fo=10, routed) 0.740 8.753 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0_n_0
|
|
SLICE_X44Y50 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[5]_i_1__0/I3
|
|
SLICE_X44Y50 LUT6 (Prop_lut6_I3_O) 0.124 8.877 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[5]_i_1__0/O
|
|
net (fo=6, routed) 0.845 9.722 u_cpu/u_csr/ms_to_ws_bus[13]
|
|
SLICE_X50Y46 f u_cpu/u_csr/write_buffer_way[1]_i_18/I3
|
|
SLICE_X50Y46 LUT6 (Prop_lut6_I3_O) 0.124 9.846 f u_cpu/u_csr/write_buffer_way[1]_i_18/O
|
|
net (fo=1, routed) 0.000 9.846 u_cpu/u_csr/write_buffer_way[1]_i_18_n_0
|
|
SLICE_X50Y46 f u_cpu/u_csr/write_buffer_way_reg[1]_i_11/S[0]
|
|
SLICE_X50Y46 CARRY4 (Prop_carry4_S[0]_CO[3])
|
|
0.532 10.378 r u_cpu/u_csr/write_buffer_way_reg[1]_i_11/CO[3]
|
|
net (fo=1, routed) 0.000 10.378 u_cpu/u_csr/write_buffer_way_reg[1]_i_11_n_0
|
|
SLICE_X50Y47 r u_cpu/u_csr/write_buffer_way_reg[1]_i_9/CI
|
|
SLICE_X50Y47 CARRY4 (Prop_carry4_CI_CO[1])
|
|
0.157 10.535 f u_cpu/u_csr/write_buffer_way_reg[1]_i_9/CO[1]
|
|
net (fo=2, routed) 0.791 11.326 u_cpu/wb_stage/CO[0]
|
|
SLICE_X46Y39 f u_cpu/wb_stage/write_buffer_way[1]_i_5/I1
|
|
SLICE_X46Y39 LUT6 (Prop_lut6_I1_O) 0.329 11.655 r u_cpu/wb_stage/write_buffer_way[1]_i_5/O
|
|
net (fo=7, routed) 0.762 12.417 u_cpu/addr_trans/tlb_entry/sc_cancel_req
|
|
SLICE_X46Y35 r u_cpu/addr_trans/tlb_entry/main_state[0]_i_3/I1
|
|
SLICE_X46Y35 LUT3 (Prop_lut3_I1_O) 0.124 12.541 r u_cpu/addr_trans/tlb_entry/main_state[0]_i_3/O
|
|
net (fo=3, routed) 0.719 13.260 u_cpu/dcache/main_state_reg[0]_2
|
|
SLICE_X43Y31 r u_cpu/dcache/ds_to_es_bus_r[235]_i_10/I3
|
|
SLICE_X43Y31 LUT6 (Prop_lut6_I3_O) 0.124 13.384 r u_cpu/dcache/ds_to_es_bus_r[235]_i_10/O
|
|
net (fo=3, routed) 0.415 13.799 u_cpu/mem_stage/data_data_ok
|
|
SLICE_X43Y30 r u_cpu/mem_stage/flush_inst_req_buffer[1]_i_15/I0
|
|
SLICE_X43Y30 LUT3 (Prop_lut3_I0_O) 0.124 13.923 r u_cpu/mem_stage/flush_inst_req_buffer[1]_i_15/O
|
|
net (fo=2, routed) 0.833 14.756 u_cpu/mem_stage/es_to_ms_bus_r_reg[70]_1
|
|
SLICE_X48Y30 r u_cpu/mem_stage/flush_inst_req_buffer[1]_i_14/I0
|
|
SLICE_X48Y30 LUT6 (Prop_lut6_I0_O) 0.124 14.880 r u_cpu/mem_stage/flush_inst_req_buffer[1]_i_14/O
|
|
net (fo=1, routed) 0.651 15.532 u_cpu/mem_stage/ms_ready_go
|
|
SLICE_X48Y25 r u_cpu/mem_stage/flush_inst_req_buffer[1]_i_13/I4
|
|
SLICE_X48Y25 LUT6 (Prop_lut6_I4_O) 0.124 15.656 r u_cpu/mem_stage/flush_inst_req_buffer[1]_i_13/O
|
|
net (fo=3, routed) 0.483 16.139 u_cpu/id_stage/flush_inst_req_buffer[31]_i_6
|
|
SLICE_X50Y25 r u_cpu/id_stage/flush_inst_req_buffer[1]_i_9/I1
|
|
SLICE_X50Y25 LUT6 (Prop_lut6_I1_O) 0.124 16.263 r u_cpu/id_stage/flush_inst_req_buffer[1]_i_9/O
|
|
net (fo=32, routed) 0.531 16.794 u_cpu/if_stage/nextpc5
|
|
SLICE_X51Y27 r u_cpu/if_stage/fetch_pc_r[6]_i_4/I2
|
|
SLICE_X51Y27 LUT6 (Prop_lut6_I2_O) 0.124 16.918 r u_cpu/if_stage/fetch_pc_r[6]_i_4/O
|
|
net (fo=1, routed) 3.059 19.977 u_cpu/if_stage/fetch_pc_r[6]_i_4_n_0
|
|
SLICE_X114Y28 r u_cpu/if_stage/fetch_pc_r[6]_i_2/I2
|
|
SLICE_X114Y28 LUT6 (Prop_lut6_I2_O) 0.124 20.101 r u_cpu/if_stage/fetch_pc_r[6]_i_2/O
|
|
net (fo=1, routed) 0.441 20.542 u_cpu/if_stage/fetch_pc_r[6]_i_2_n_0
|
|
SLICE_X114Y25 r u_cpu/if_stage/fetch_pc_r[6]_i_1/I2
|
|
SLICE_X114Y25 LUT6 (Prop_lut6_I2_O) 0.124 20.666 r u_cpu/if_stage/fetch_pc_r[6]_i_1/O
|
|
net (fo=6, routed) 3.249 23.915 u_cpu/icache/tagv_ram_way[1].u/mem_reg_reg_2[2]
|
|
SLICE_X49Y33 r u_cpu/icache/tagv_ram_way[1].u/mem_reg_reg_i_8/I4
|
|
SLICE_X49Y33 LUT5 (Prop_lut5_I4_O) 0.124 24.039 r u_cpu/icache/tagv_ram_way[1].u/mem_reg_reg_i_8/O
|
|
net (fo=16, routed) 1.477 25.516 u_cpu/icache/data_ram_way[0].data_ram_bank[2].u/ADDRBWRADDR[2]
|
|
RAMB18_X2Y2 RAMB18E1 r u_cpu/icache/data_ram_way[0].data_ram_bank[2].u/mem_reg_reg/ADDRBWRADDR[7]
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock cpu_clk rise edge) 30.323 30.323 r
|
|
clock source latency -5.674 24.648
|
|
propagated clock network latency
|
|
3.782 28.430
|
|
clock pessimism -0.418 28.012
|
|
clock uncertainty -0.074 27.938
|
|
RAMB18_X2Y2 RAMB18E1 (Setup_ramb18e1_CLKBWRCLK_ADDRBWRADDR[7])
|
|
-0.566 27.372 u_cpu/icache/data_ram_way[0].data_ram_bank[2].u/mem_reg_reg
|
|
-------------------------------------------------------------------
|
|
required time 27.372
|
|
arrival time -25.516
|
|
-------------------------------------------------------------------
|
|
slack 1.856
|
|
|
|
Slack (MET) : 1.856ns (required time - arrival time)
|
|
Source: u_cpu/addr_trans/data_vaddr_buffer_reg[14]/C
|
|
(rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns})
|
|
Destination: u_cpu/icache/data_ram_way[0].data_ram_bank[2].u/mem_reg_reg/ADDRBWRADDR[7]
|
|
(rising edge-triggered cell RAMB18E1 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns})
|
|
Path Group: cpu_clk
|
|
Path Type: Setup (Max at Slow Process Corner)
|
|
Requirement: 30.323ns (cpu_clk rise@30.323ns - cpu_clk rise@0.000ns)
|
|
Data Path Delay: 27.741ns (logic 5.333ns (19.224%) route 22.408ns (80.776%))
|
|
Logic Levels: 26 (CARRY4=4 LUT3=2 LUT4=1 LUT5=2 LUT6=15 MUXF7=1 MUXF8=1)
|
|
Clock Path Skew: -0.086ns (DCD - SCD + CPR)
|
|
Destination Clock Delay (DCD): -1.892ns = ( 28.430 - 30.323 )
|
|
Source Clock Delay (SCD): -2.225ns
|
|
Clock Pessimism Removal (CPR): -0.418ns
|
|
Clock Uncertainty: 0.074ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Discrete Jitter (DJ): 0.130ns
|
|
Phase Error (PE): 0.000ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock cpu_clk rise edge) 0.000 0.000 r
|
|
clock source latency -6.275 -6.275
|
|
propagated clock network latency
|
|
4.051 -2.225
|
|
SLICE_X35Y35 FDRE 0.000 -2.225 r u_cpu/addr_trans/data_vaddr_buffer_reg[14]/C
|
|
SLICE_X35Y35 FDRE (Prop_fdre_C_Q) 0.456 -1.769 r u_cpu/addr_trans/data_vaddr_buffer_reg[14]/Q
|
|
net (fo=33, routed) 1.442 -0.326 u_cpu/addr_trans/tlb_entry/data_vaddr_buffer[2]
|
|
SLICE_X42Y40 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_226/I5
|
|
SLICE_X42Y40 LUT6 (Prop_lut6_I5_O) 0.124 -0.202 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_226/O
|
|
net (fo=1, routed) 0.000 -0.202 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_226_n_0
|
|
SLICE_X42Y40 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_111/S[0]
|
|
SLICE_X42Y40 CARRY4 (Prop_carry4_S[0]_CO[3])
|
|
0.513 0.311 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_111/CO[3]
|
|
net (fo=1, routed) 0.000 0.311 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_111_n_0
|
|
SLICE_X42Y41 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_32/CI
|
|
SLICE_X42Y41 CARRY4 (Prop_carry4_CI_CO[2])
|
|
0.229 0.540 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_32/CO[2]
|
|
net (fo=1, routed) 1.009 1.549 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_32_n_1
|
|
SLICE_X40Y47 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_9/I1
|
|
SLICE_X40Y47 LUT6 (Prop_lut6_I1_O) 0.310 1.859 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_9/O
|
|
net (fo=2, routed) 0.635 2.494 u_cpu/addr_trans/tlb_entry/match1[28]
|
|
SLICE_X38Y47 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/I2
|
|
SLICE_X38Y47 LUT4 (Prop_lut4_I2_O) 0.124 2.618 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/O
|
|
net (fo=2, routed) 0.667 3.285 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2_n_0
|
|
SLICE_X39Y47 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/I0
|
|
SLICE_X39Y47 LUT5 (Prop_lut5_I0_O) 0.124 3.409 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/O
|
|
net (fo=2, routed) 1.103 4.512 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2_n_0
|
|
SLICE_X38Y50 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/I0
|
|
SLICE_X38Y50 LUT6 (Prop_lut6_I0_O) 0.124 4.636 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/O
|
|
net (fo=89, routed) 1.162 5.797 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus[8]
|
|
SLICE_X42Y51 r u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_38__0/S
|
|
SLICE_X42Y51 MUXF7 (Prop_muxf7_S_O) 0.292 6.089 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_38__0/O
|
|
net (fo=1, routed) 0.000 6.089 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_38__0_n_0
|
|
SLICE_X42Y51 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_16__0/I1
|
|
SLICE_X42Y51 MUXF8 (Prop_muxf8_I1_O) 0.088 6.177 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_16__0/O
|
|
net (fo=1, routed) 0.957 7.134 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_16__0_n_0
|
|
SLICE_X42Y50 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7/I0
|
|
SLICE_X42Y50 LUT6 (Prop_lut6_I0_O) 0.319 7.453 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7/O
|
|
net (fo=1, routed) 0.435 7.888 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7_n_0
|
|
SLICE_X44Y50 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0/I5
|
|
SLICE_X44Y50 LUT6 (Prop_lut6_I5_O) 0.124 8.012 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0/O
|
|
net (fo=10, routed) 0.740 8.753 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0_n_0
|
|
SLICE_X44Y50 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[5]_i_1__0/I3
|
|
SLICE_X44Y50 LUT6 (Prop_lut6_I3_O) 0.124 8.877 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[5]_i_1__0/O
|
|
net (fo=6, routed) 0.845 9.722 u_cpu/u_csr/ms_to_ws_bus[13]
|
|
SLICE_X50Y46 r u_cpu/u_csr/write_buffer_way[1]_i_18/I3
|
|
SLICE_X50Y46 LUT6 (Prop_lut6_I3_O) 0.124 9.846 r u_cpu/u_csr/write_buffer_way[1]_i_18/O
|
|
net (fo=1, routed) 0.000 9.846 u_cpu/u_csr/write_buffer_way[1]_i_18_n_0
|
|
SLICE_X50Y46 r u_cpu/u_csr/write_buffer_way_reg[1]_i_11/S[0]
|
|
SLICE_X50Y46 CARRY4 (Prop_carry4_S[0]_CO[3])
|
|
0.532 10.378 f u_cpu/u_csr/write_buffer_way_reg[1]_i_11/CO[3]
|
|
net (fo=1, routed) 0.000 10.378 u_cpu/u_csr/write_buffer_way_reg[1]_i_11_n_0
|
|
SLICE_X50Y47 f u_cpu/u_csr/write_buffer_way_reg[1]_i_9/CI
|
|
SLICE_X50Y47 CARRY4 (Prop_carry4_CI_CO[1])
|
|
0.157 10.535 f u_cpu/u_csr/write_buffer_way_reg[1]_i_9/CO[1]
|
|
net (fo=2, routed) 0.791 11.326 u_cpu/wb_stage/CO[0]
|
|
SLICE_X46Y39 f u_cpu/wb_stage/write_buffer_way[1]_i_5/I1
|
|
SLICE_X46Y39 LUT6 (Prop_lut6_I1_O) 0.329 11.655 r u_cpu/wb_stage/write_buffer_way[1]_i_5/O
|
|
net (fo=7, routed) 0.762 12.417 u_cpu/addr_trans/tlb_entry/sc_cancel_req
|
|
SLICE_X46Y35 r u_cpu/addr_trans/tlb_entry/main_state[0]_i_3/I1
|
|
SLICE_X46Y35 LUT3 (Prop_lut3_I1_O) 0.124 12.541 r u_cpu/addr_trans/tlb_entry/main_state[0]_i_3/O
|
|
net (fo=3, routed) 0.719 13.260 u_cpu/dcache/main_state_reg[0]_2
|
|
SLICE_X43Y31 r u_cpu/dcache/ds_to_es_bus_r[235]_i_10/I3
|
|
SLICE_X43Y31 LUT6 (Prop_lut6_I3_O) 0.124 13.384 r u_cpu/dcache/ds_to_es_bus_r[235]_i_10/O
|
|
net (fo=3, routed) 0.415 13.799 u_cpu/mem_stage/data_data_ok
|
|
SLICE_X43Y30 r u_cpu/mem_stage/flush_inst_req_buffer[1]_i_15/I0
|
|
SLICE_X43Y30 LUT3 (Prop_lut3_I0_O) 0.124 13.923 r u_cpu/mem_stage/flush_inst_req_buffer[1]_i_15/O
|
|
net (fo=2, routed) 0.833 14.756 u_cpu/mem_stage/es_to_ms_bus_r_reg[70]_1
|
|
SLICE_X48Y30 r u_cpu/mem_stage/flush_inst_req_buffer[1]_i_14/I0
|
|
SLICE_X48Y30 LUT6 (Prop_lut6_I0_O) 0.124 14.880 r u_cpu/mem_stage/flush_inst_req_buffer[1]_i_14/O
|
|
net (fo=1, routed) 0.651 15.532 u_cpu/mem_stage/ms_ready_go
|
|
SLICE_X48Y25 r u_cpu/mem_stage/flush_inst_req_buffer[1]_i_13/I4
|
|
SLICE_X48Y25 LUT6 (Prop_lut6_I4_O) 0.124 15.656 r u_cpu/mem_stage/flush_inst_req_buffer[1]_i_13/O
|
|
net (fo=3, routed) 0.483 16.139 u_cpu/id_stage/flush_inst_req_buffer[31]_i_6
|
|
SLICE_X50Y25 r u_cpu/id_stage/flush_inst_req_buffer[1]_i_9/I1
|
|
SLICE_X50Y25 LUT6 (Prop_lut6_I1_O) 0.124 16.263 r u_cpu/id_stage/flush_inst_req_buffer[1]_i_9/O
|
|
net (fo=32, routed) 0.531 16.794 u_cpu/if_stage/nextpc5
|
|
SLICE_X51Y27 r u_cpu/if_stage/fetch_pc_r[6]_i_4/I2
|
|
SLICE_X51Y27 LUT6 (Prop_lut6_I2_O) 0.124 16.918 r u_cpu/if_stage/fetch_pc_r[6]_i_4/O
|
|
net (fo=1, routed) 3.059 19.977 u_cpu/if_stage/fetch_pc_r[6]_i_4_n_0
|
|
SLICE_X114Y28 r u_cpu/if_stage/fetch_pc_r[6]_i_2/I2
|
|
SLICE_X114Y28 LUT6 (Prop_lut6_I2_O) 0.124 20.101 r u_cpu/if_stage/fetch_pc_r[6]_i_2/O
|
|
net (fo=1, routed) 0.441 20.542 u_cpu/if_stage/fetch_pc_r[6]_i_2_n_0
|
|
SLICE_X114Y25 r u_cpu/if_stage/fetch_pc_r[6]_i_1/I2
|
|
SLICE_X114Y25 LUT6 (Prop_lut6_I2_O) 0.124 20.666 r u_cpu/if_stage/fetch_pc_r[6]_i_1/O
|
|
net (fo=6, routed) 3.249 23.915 u_cpu/icache/tagv_ram_way[1].u/mem_reg_reg_2[2]
|
|
SLICE_X49Y33 r u_cpu/icache/tagv_ram_way[1].u/mem_reg_reg_i_8/I4
|
|
SLICE_X49Y33 LUT5 (Prop_lut5_I4_O) 0.124 24.039 r u_cpu/icache/tagv_ram_way[1].u/mem_reg_reg_i_8/O
|
|
net (fo=16, routed) 1.477 25.516 u_cpu/icache/data_ram_way[0].data_ram_bank[2].u/ADDRBWRADDR[2]
|
|
RAMB18_X2Y2 RAMB18E1 r u_cpu/icache/data_ram_way[0].data_ram_bank[2].u/mem_reg_reg/ADDRBWRADDR[7]
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock cpu_clk rise edge) 30.323 30.323 r
|
|
clock source latency -5.674 24.648
|
|
propagated clock network latency
|
|
3.782 28.430
|
|
clock pessimism -0.418 28.012
|
|
clock uncertainty -0.074 27.938
|
|
RAMB18_X2Y2 RAMB18E1 (Setup_ramb18e1_CLKBWRCLK_ADDRBWRADDR[7])
|
|
-0.566 27.372 u_cpu/icache/data_ram_way[0].data_ram_bank[2].u/mem_reg_reg
|
|
-------------------------------------------------------------------
|
|
required time 27.372
|
|
arrival time -25.516
|
|
-------------------------------------------------------------------
|
|
slack 1.856
|
|
|
|
Slack (MET) : 1.856ns (required time - arrival time)
|
|
Source: u_cpu/addr_trans/data_vaddr_buffer_reg[14]/C
|
|
(rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns})
|
|
Destination: u_cpu/icache/data_ram_way[0].data_ram_bank[2].u/mem_reg_reg/ADDRBWRADDR[7]
|
|
(rising edge-triggered cell RAMB18E1 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns})
|
|
Path Group: cpu_clk
|
|
Path Type: Setup (Max at Slow Process Corner)
|
|
Requirement: 30.323ns (cpu_clk rise@30.323ns - cpu_clk rise@0.000ns)
|
|
Data Path Delay: 27.741ns (logic 5.333ns (19.224%) route 22.408ns (80.776%))
|
|
Logic Levels: 26 (CARRY4=4 LUT3=2 LUT4=1 LUT5=2 LUT6=15 MUXF7=1 MUXF8=1)
|
|
Clock Path Skew: -0.086ns (DCD - SCD + CPR)
|
|
Destination Clock Delay (DCD): -1.892ns = ( 28.430 - 30.323 )
|
|
Source Clock Delay (SCD): -2.225ns
|
|
Clock Pessimism Removal (CPR): -0.418ns
|
|
Clock Uncertainty: 0.074ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Discrete Jitter (DJ): 0.130ns
|
|
Phase Error (PE): 0.000ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock cpu_clk rise edge) 0.000 0.000 r
|
|
clock source latency -6.275 -6.275
|
|
propagated clock network latency
|
|
4.051 -2.225
|
|
SLICE_X35Y35 FDRE 0.000 -2.225 r u_cpu/addr_trans/data_vaddr_buffer_reg[14]/C
|
|
SLICE_X35Y35 FDRE (Prop_fdre_C_Q) 0.456 -1.769 r u_cpu/addr_trans/data_vaddr_buffer_reg[14]/Q
|
|
net (fo=33, routed) 1.442 -0.326 u_cpu/addr_trans/tlb_entry/data_vaddr_buffer[2]
|
|
SLICE_X42Y40 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_226/I5
|
|
SLICE_X42Y40 LUT6 (Prop_lut6_I5_O) 0.124 -0.202 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_226/O
|
|
net (fo=1, routed) 0.000 -0.202 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_226_n_0
|
|
SLICE_X42Y40 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_111/S[0]
|
|
SLICE_X42Y40 CARRY4 (Prop_carry4_S[0]_CO[3])
|
|
0.513 0.311 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_111/CO[3]
|
|
net (fo=1, routed) 0.000 0.311 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_111_n_0
|
|
SLICE_X42Y41 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_32/CI
|
|
SLICE_X42Y41 CARRY4 (Prop_carry4_CI_CO[2])
|
|
0.229 0.540 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_32/CO[2]
|
|
net (fo=1, routed) 1.009 1.549 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_32_n_1
|
|
SLICE_X40Y47 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_9/I1
|
|
SLICE_X40Y47 LUT6 (Prop_lut6_I1_O) 0.310 1.859 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_9/O
|
|
net (fo=2, routed) 0.635 2.494 u_cpu/addr_trans/tlb_entry/match1[28]
|
|
SLICE_X38Y47 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/I2
|
|
SLICE_X38Y47 LUT4 (Prop_lut4_I2_O) 0.124 2.618 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/O
|
|
net (fo=2, routed) 0.667 3.285 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2_n_0
|
|
SLICE_X39Y47 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/I0
|
|
SLICE_X39Y47 LUT5 (Prop_lut5_I0_O) 0.124 3.409 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/O
|
|
net (fo=2, routed) 1.103 4.512 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2_n_0
|
|
SLICE_X38Y50 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/I0
|
|
SLICE_X38Y50 LUT6 (Prop_lut6_I0_O) 0.124 4.636 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/O
|
|
net (fo=89, routed) 1.162 5.797 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus[8]
|
|
SLICE_X42Y51 r u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_38__0/S
|
|
SLICE_X42Y51 MUXF7 (Prop_muxf7_S_O) 0.292 6.089 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_38__0/O
|
|
net (fo=1, routed) 0.000 6.089 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_38__0_n_0
|
|
SLICE_X42Y51 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_16__0/I1
|
|
SLICE_X42Y51 MUXF8 (Prop_muxf8_I1_O) 0.088 6.177 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_16__0/O
|
|
net (fo=1, routed) 0.957 7.134 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_16__0_n_0
|
|
SLICE_X42Y50 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7/I0
|
|
SLICE_X42Y50 LUT6 (Prop_lut6_I0_O) 0.319 7.453 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7/O
|
|
net (fo=1, routed) 0.435 7.888 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7_n_0
|
|
SLICE_X44Y50 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0/I5
|
|
SLICE_X44Y50 LUT6 (Prop_lut6_I5_O) 0.124 8.012 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0/O
|
|
net (fo=10, routed) 0.740 8.753 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0_n_0
|
|
SLICE_X44Y50 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[5]_i_1__0/I3
|
|
SLICE_X44Y50 LUT6 (Prop_lut6_I3_O) 0.124 8.877 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[5]_i_1__0/O
|
|
net (fo=6, routed) 0.845 9.722 u_cpu/u_csr/ms_to_ws_bus[13]
|
|
SLICE_X50Y46 f u_cpu/u_csr/write_buffer_way[1]_i_18/I3
|
|
SLICE_X50Y46 LUT6 (Prop_lut6_I3_O) 0.124 9.846 r u_cpu/u_csr/write_buffer_way[1]_i_18/O
|
|
net (fo=1, routed) 0.000 9.846 u_cpu/u_csr/write_buffer_way[1]_i_18_n_0
|
|
SLICE_X50Y46 r u_cpu/u_csr/write_buffer_way_reg[1]_i_11/S[0]
|
|
SLICE_X50Y46 CARRY4 (Prop_carry4_S[0]_CO[3])
|
|
0.532 10.378 f u_cpu/u_csr/write_buffer_way_reg[1]_i_11/CO[3]
|
|
net (fo=1, routed) 0.000 10.378 u_cpu/u_csr/write_buffer_way_reg[1]_i_11_n_0
|
|
SLICE_X50Y47 f u_cpu/u_csr/write_buffer_way_reg[1]_i_9/CI
|
|
SLICE_X50Y47 CARRY4 (Prop_carry4_CI_CO[1])
|
|
0.157 10.535 f u_cpu/u_csr/write_buffer_way_reg[1]_i_9/CO[1]
|
|
net (fo=2, routed) 0.791 11.326 u_cpu/wb_stage/CO[0]
|
|
SLICE_X46Y39 f u_cpu/wb_stage/write_buffer_way[1]_i_5/I1
|
|
SLICE_X46Y39 LUT6 (Prop_lut6_I1_O) 0.329 11.655 r u_cpu/wb_stage/write_buffer_way[1]_i_5/O
|
|
net (fo=7, routed) 0.762 12.417 u_cpu/addr_trans/tlb_entry/sc_cancel_req
|
|
SLICE_X46Y35 r u_cpu/addr_trans/tlb_entry/main_state[0]_i_3/I1
|
|
SLICE_X46Y35 LUT3 (Prop_lut3_I1_O) 0.124 12.541 r u_cpu/addr_trans/tlb_entry/main_state[0]_i_3/O
|
|
net (fo=3, routed) 0.719 13.260 u_cpu/dcache/main_state_reg[0]_2
|
|
SLICE_X43Y31 r u_cpu/dcache/ds_to_es_bus_r[235]_i_10/I3
|
|
SLICE_X43Y31 LUT6 (Prop_lut6_I3_O) 0.124 13.384 r u_cpu/dcache/ds_to_es_bus_r[235]_i_10/O
|
|
net (fo=3, routed) 0.415 13.799 u_cpu/mem_stage/data_data_ok
|
|
SLICE_X43Y30 r u_cpu/mem_stage/flush_inst_req_buffer[1]_i_15/I0
|
|
SLICE_X43Y30 LUT3 (Prop_lut3_I0_O) 0.124 13.923 r u_cpu/mem_stage/flush_inst_req_buffer[1]_i_15/O
|
|
net (fo=2, routed) 0.833 14.756 u_cpu/mem_stage/es_to_ms_bus_r_reg[70]_1
|
|
SLICE_X48Y30 r u_cpu/mem_stage/flush_inst_req_buffer[1]_i_14/I0
|
|
SLICE_X48Y30 LUT6 (Prop_lut6_I0_O) 0.124 14.880 r u_cpu/mem_stage/flush_inst_req_buffer[1]_i_14/O
|
|
net (fo=1, routed) 0.651 15.532 u_cpu/mem_stage/ms_ready_go
|
|
SLICE_X48Y25 r u_cpu/mem_stage/flush_inst_req_buffer[1]_i_13/I4
|
|
SLICE_X48Y25 LUT6 (Prop_lut6_I4_O) 0.124 15.656 r u_cpu/mem_stage/flush_inst_req_buffer[1]_i_13/O
|
|
net (fo=3, routed) 0.483 16.139 u_cpu/id_stage/flush_inst_req_buffer[31]_i_6
|
|
SLICE_X50Y25 r u_cpu/id_stage/flush_inst_req_buffer[1]_i_9/I1
|
|
SLICE_X50Y25 LUT6 (Prop_lut6_I1_O) 0.124 16.263 r u_cpu/id_stage/flush_inst_req_buffer[1]_i_9/O
|
|
net (fo=32, routed) 0.531 16.794 u_cpu/if_stage/nextpc5
|
|
SLICE_X51Y27 r u_cpu/if_stage/fetch_pc_r[6]_i_4/I2
|
|
SLICE_X51Y27 LUT6 (Prop_lut6_I2_O) 0.124 16.918 r u_cpu/if_stage/fetch_pc_r[6]_i_4/O
|
|
net (fo=1, routed) 3.059 19.977 u_cpu/if_stage/fetch_pc_r[6]_i_4_n_0
|
|
SLICE_X114Y28 r u_cpu/if_stage/fetch_pc_r[6]_i_2/I2
|
|
SLICE_X114Y28 LUT6 (Prop_lut6_I2_O) 0.124 20.101 r u_cpu/if_stage/fetch_pc_r[6]_i_2/O
|
|
net (fo=1, routed) 0.441 20.542 u_cpu/if_stage/fetch_pc_r[6]_i_2_n_0
|
|
SLICE_X114Y25 r u_cpu/if_stage/fetch_pc_r[6]_i_1/I2
|
|
SLICE_X114Y25 LUT6 (Prop_lut6_I2_O) 0.124 20.666 r u_cpu/if_stage/fetch_pc_r[6]_i_1/O
|
|
net (fo=6, routed) 3.249 23.915 u_cpu/icache/tagv_ram_way[1].u/mem_reg_reg_2[2]
|
|
SLICE_X49Y33 r u_cpu/icache/tagv_ram_way[1].u/mem_reg_reg_i_8/I4
|
|
SLICE_X49Y33 LUT5 (Prop_lut5_I4_O) 0.124 24.039 r u_cpu/icache/tagv_ram_way[1].u/mem_reg_reg_i_8/O
|
|
net (fo=16, routed) 1.477 25.516 u_cpu/icache/data_ram_way[0].data_ram_bank[2].u/ADDRBWRADDR[2]
|
|
RAMB18_X2Y2 RAMB18E1 r u_cpu/icache/data_ram_way[0].data_ram_bank[2].u/mem_reg_reg/ADDRBWRADDR[7]
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock cpu_clk rise edge) 30.323 30.323 r
|
|
clock source latency -5.674 24.648
|
|
propagated clock network latency
|
|
3.782 28.430
|
|
clock pessimism -0.418 28.012
|
|
clock uncertainty -0.074 27.938
|
|
RAMB18_X2Y2 RAMB18E1 (Setup_ramb18e1_CLKBWRCLK_ADDRBWRADDR[7])
|
|
-0.566 27.372 u_cpu/icache/data_ram_way[0].data_ram_bank[2].u/mem_reg_reg
|
|
-------------------------------------------------------------------
|
|
required time 27.372
|
|
arrival time -25.516
|
|
-------------------------------------------------------------------
|
|
slack 1.856
|
|
|
|
Slack (MET) : 1.856ns (required time - arrival time)
|
|
Source: u_cpu/addr_trans/data_vaddr_buffer_reg[14]/C
|
|
(rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns})
|
|
Destination: u_cpu/icache/data_ram_way[0].data_ram_bank[2].u/mem_reg_reg/ADDRBWRADDR[7]
|
|
(rising edge-triggered cell RAMB18E1 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns})
|
|
Path Group: cpu_clk
|
|
Path Type: Setup (Max at Slow Process Corner)
|
|
Requirement: 30.323ns (cpu_clk rise@30.323ns - cpu_clk rise@0.000ns)
|
|
Data Path Delay: 27.741ns (logic 5.333ns (19.224%) route 22.408ns (80.776%))
|
|
Logic Levels: 26 (CARRY4=4 LUT3=2 LUT4=1 LUT5=2 LUT6=15 MUXF7=1 MUXF8=1)
|
|
Clock Path Skew: -0.086ns (DCD - SCD + CPR)
|
|
Destination Clock Delay (DCD): -1.892ns = ( 28.430 - 30.323 )
|
|
Source Clock Delay (SCD): -2.225ns
|
|
Clock Pessimism Removal (CPR): -0.418ns
|
|
Clock Uncertainty: 0.074ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Discrete Jitter (DJ): 0.130ns
|
|
Phase Error (PE): 0.000ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock cpu_clk rise edge) 0.000 0.000 r
|
|
clock source latency -6.275 -6.275
|
|
propagated clock network latency
|
|
4.051 -2.225
|
|
SLICE_X35Y35 FDRE 0.000 -2.225 r u_cpu/addr_trans/data_vaddr_buffer_reg[14]/C
|
|
SLICE_X35Y35 FDRE (Prop_fdre_C_Q) 0.456 -1.769 r u_cpu/addr_trans/data_vaddr_buffer_reg[14]/Q
|
|
net (fo=33, routed) 1.442 -0.326 u_cpu/addr_trans/tlb_entry/data_vaddr_buffer[2]
|
|
SLICE_X42Y40 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_226/I5
|
|
SLICE_X42Y40 LUT6 (Prop_lut6_I5_O) 0.124 -0.202 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_226/O
|
|
net (fo=1, routed) 0.000 -0.202 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_226_n_0
|
|
SLICE_X42Y40 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_111/S[0]
|
|
SLICE_X42Y40 CARRY4 (Prop_carry4_S[0]_CO[3])
|
|
0.513 0.311 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_111/CO[3]
|
|
net (fo=1, routed) 0.000 0.311 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_111_n_0
|
|
SLICE_X42Y41 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_32/CI
|
|
SLICE_X42Y41 CARRY4 (Prop_carry4_CI_CO[2])
|
|
0.229 0.540 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_32/CO[2]
|
|
net (fo=1, routed) 1.009 1.549 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_32_n_1
|
|
SLICE_X40Y47 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_9/I1
|
|
SLICE_X40Y47 LUT6 (Prop_lut6_I1_O) 0.310 1.859 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_9/O
|
|
net (fo=2, routed) 0.635 2.494 u_cpu/addr_trans/tlb_entry/match1[28]
|
|
SLICE_X38Y47 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/I2
|
|
SLICE_X38Y47 LUT4 (Prop_lut4_I2_O) 0.124 2.618 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/O
|
|
net (fo=2, routed) 0.667 3.285 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2_n_0
|
|
SLICE_X39Y47 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/I0
|
|
SLICE_X39Y47 LUT5 (Prop_lut5_I0_O) 0.124 3.409 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/O
|
|
net (fo=2, routed) 1.103 4.512 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2_n_0
|
|
SLICE_X38Y50 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/I0
|
|
SLICE_X38Y50 LUT6 (Prop_lut6_I0_O) 0.124 4.636 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/O
|
|
net (fo=89, routed) 1.162 5.797 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus[8]
|
|
SLICE_X42Y51 r u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_38__0/S
|
|
SLICE_X42Y51 MUXF7 (Prop_muxf7_S_O) 0.292 6.089 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_38__0/O
|
|
net (fo=1, routed) 0.000 6.089 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_38__0_n_0
|
|
SLICE_X42Y51 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_16__0/I1
|
|
SLICE_X42Y51 MUXF8 (Prop_muxf8_I1_O) 0.088 6.177 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_16__0/O
|
|
net (fo=1, routed) 0.957 7.134 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_16__0_n_0
|
|
SLICE_X42Y50 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7/I0
|
|
SLICE_X42Y50 LUT6 (Prop_lut6_I0_O) 0.319 7.453 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7/O
|
|
net (fo=1, routed) 0.435 7.888 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7_n_0
|
|
SLICE_X44Y50 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0/I5
|
|
SLICE_X44Y50 LUT6 (Prop_lut6_I5_O) 0.124 8.012 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0/O
|
|
net (fo=10, routed) 0.740 8.753 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0_n_0
|
|
SLICE_X44Y50 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[5]_i_1__0/I3
|
|
SLICE_X44Y50 LUT6 (Prop_lut6_I3_O) 0.124 8.877 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[5]_i_1__0/O
|
|
net (fo=6, routed) 0.845 9.722 u_cpu/u_csr/ms_to_ws_bus[13]
|
|
SLICE_X50Y46 r u_cpu/u_csr/write_buffer_way[1]_i_18/I3
|
|
SLICE_X50Y46 LUT6 (Prop_lut6_I3_O) 0.124 9.846 r u_cpu/u_csr/write_buffer_way[1]_i_18/O
|
|
net (fo=1, routed) 0.000 9.846 u_cpu/u_csr/write_buffer_way[1]_i_18_n_0
|
|
SLICE_X50Y46 r u_cpu/u_csr/write_buffer_way_reg[1]_i_11/S[0]
|
|
SLICE_X50Y46 CARRY4 (Prop_carry4_S[0]_CO[3])
|
|
0.532 10.378 r u_cpu/u_csr/write_buffer_way_reg[1]_i_11/CO[3]
|
|
net (fo=1, routed) 0.000 10.378 u_cpu/u_csr/write_buffer_way_reg[1]_i_11_n_0
|
|
SLICE_X50Y47 r u_cpu/u_csr/write_buffer_way_reg[1]_i_9/CI
|
|
SLICE_X50Y47 CARRY4 (Prop_carry4_CI_CO[1])
|
|
0.157 10.535 r u_cpu/u_csr/write_buffer_way_reg[1]_i_9/CO[1]
|
|
net (fo=2, routed) 0.791 11.326 u_cpu/wb_stage/CO[0]
|
|
SLICE_X46Y39 r u_cpu/wb_stage/write_buffer_way[1]_i_5/I1
|
|
SLICE_X46Y39 LUT6 (Prop_lut6_I1_O) 0.329 11.655 f u_cpu/wb_stage/write_buffer_way[1]_i_5/O
|
|
net (fo=7, routed) 0.762 12.417 u_cpu/addr_trans/tlb_entry/sc_cancel_req
|
|
SLICE_X46Y35 f u_cpu/addr_trans/tlb_entry/main_state[0]_i_3/I1
|
|
SLICE_X46Y35 LUT3 (Prop_lut3_I1_O) 0.124 12.541 f u_cpu/addr_trans/tlb_entry/main_state[0]_i_3/O
|
|
net (fo=3, routed) 0.719 13.260 u_cpu/dcache/main_state_reg[0]_2
|
|
SLICE_X43Y31 f u_cpu/dcache/ds_to_es_bus_r[235]_i_10/I3
|
|
SLICE_X43Y31 LUT6 (Prop_lut6_I3_O) 0.124 13.384 f u_cpu/dcache/ds_to_es_bus_r[235]_i_10/O
|
|
net (fo=3, routed) 0.415 13.799 u_cpu/mem_stage/data_data_ok
|
|
SLICE_X43Y30 f u_cpu/mem_stage/flush_inst_req_buffer[1]_i_15/I0
|
|
SLICE_X43Y30 LUT3 (Prop_lut3_I0_O) 0.124 13.923 f u_cpu/mem_stage/flush_inst_req_buffer[1]_i_15/O
|
|
net (fo=2, routed) 0.833 14.756 u_cpu/mem_stage/es_to_ms_bus_r_reg[70]_1
|
|
SLICE_X48Y30 f u_cpu/mem_stage/flush_inst_req_buffer[1]_i_14/I0
|
|
SLICE_X48Y30 LUT6 (Prop_lut6_I0_O) 0.124 14.880 f u_cpu/mem_stage/flush_inst_req_buffer[1]_i_14/O
|
|
net (fo=1, routed) 0.651 15.532 u_cpu/mem_stage/ms_ready_go
|
|
SLICE_X48Y25 f u_cpu/mem_stage/flush_inst_req_buffer[1]_i_13/I4
|
|
SLICE_X48Y25 LUT6 (Prop_lut6_I4_O) 0.124 15.656 f u_cpu/mem_stage/flush_inst_req_buffer[1]_i_13/O
|
|
net (fo=3, routed) 0.483 16.139 u_cpu/id_stage/flush_inst_req_buffer[31]_i_6
|
|
SLICE_X50Y25 f u_cpu/id_stage/flush_inst_req_buffer[1]_i_9/I1
|
|
SLICE_X50Y25 LUT6 (Prop_lut6_I1_O) 0.124 16.263 f u_cpu/id_stage/flush_inst_req_buffer[1]_i_9/O
|
|
net (fo=32, routed) 0.531 16.794 u_cpu/if_stage/nextpc5
|
|
SLICE_X51Y27 f u_cpu/if_stage/fetch_pc_r[6]_i_4/I2
|
|
SLICE_X51Y27 LUT6 (Prop_lut6_I2_O) 0.124 16.918 r u_cpu/if_stage/fetch_pc_r[6]_i_4/O
|
|
net (fo=1, routed) 3.059 19.977 u_cpu/if_stage/fetch_pc_r[6]_i_4_n_0
|
|
SLICE_X114Y28 r u_cpu/if_stage/fetch_pc_r[6]_i_2/I2
|
|
SLICE_X114Y28 LUT6 (Prop_lut6_I2_O) 0.124 20.101 r u_cpu/if_stage/fetch_pc_r[6]_i_2/O
|
|
net (fo=1, routed) 0.441 20.542 u_cpu/if_stage/fetch_pc_r[6]_i_2_n_0
|
|
SLICE_X114Y25 r u_cpu/if_stage/fetch_pc_r[6]_i_1/I2
|
|
SLICE_X114Y25 LUT6 (Prop_lut6_I2_O) 0.124 20.666 r u_cpu/if_stage/fetch_pc_r[6]_i_1/O
|
|
net (fo=6, routed) 3.249 23.915 u_cpu/icache/tagv_ram_way[1].u/mem_reg_reg_2[2]
|
|
SLICE_X49Y33 r u_cpu/icache/tagv_ram_way[1].u/mem_reg_reg_i_8/I4
|
|
SLICE_X49Y33 LUT5 (Prop_lut5_I4_O) 0.124 24.039 r u_cpu/icache/tagv_ram_way[1].u/mem_reg_reg_i_8/O
|
|
net (fo=16, routed) 1.477 25.516 u_cpu/icache/data_ram_way[0].data_ram_bank[2].u/ADDRBWRADDR[2]
|
|
RAMB18_X2Y2 RAMB18E1 r u_cpu/icache/data_ram_way[0].data_ram_bank[2].u/mem_reg_reg/ADDRBWRADDR[7]
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock cpu_clk rise edge) 30.323 30.323 r
|
|
clock source latency -5.674 24.648
|
|
propagated clock network latency
|
|
3.782 28.430
|
|
clock pessimism -0.418 28.012
|
|
clock uncertainty -0.074 27.938
|
|
RAMB18_X2Y2 RAMB18E1 (Setup_ramb18e1_CLKBWRCLK_ADDRBWRADDR[7])
|
|
-0.566 27.372 u_cpu/icache/data_ram_way[0].data_ram_bank[2].u/mem_reg_reg
|
|
-------------------------------------------------------------------
|
|
required time 27.372
|
|
arrival time -25.516
|
|
-------------------------------------------------------------------
|
|
slack 1.856
|
|
|
|
Slack (MET) : 1.856ns (required time - arrival time)
|
|
Source: u_cpu/addr_trans/data_vaddr_buffer_reg[14]/C
|
|
(rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns})
|
|
Destination: u_cpu/icache/data_ram_way[0].data_ram_bank[2].u/mem_reg_reg/ADDRBWRADDR[7]
|
|
(rising edge-triggered cell RAMB18E1 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns})
|
|
Path Group: cpu_clk
|
|
Path Type: Setup (Max at Slow Process Corner)
|
|
Requirement: 30.323ns (cpu_clk rise@30.323ns - cpu_clk rise@0.000ns)
|
|
Data Path Delay: 27.741ns (logic 5.333ns (19.224%) route 22.408ns (80.776%))
|
|
Logic Levels: 26 (CARRY4=4 LUT3=2 LUT4=1 LUT5=2 LUT6=15 MUXF7=1 MUXF8=1)
|
|
Clock Path Skew: -0.086ns (DCD - SCD + CPR)
|
|
Destination Clock Delay (DCD): -1.892ns = ( 28.430 - 30.323 )
|
|
Source Clock Delay (SCD): -2.225ns
|
|
Clock Pessimism Removal (CPR): -0.418ns
|
|
Clock Uncertainty: 0.074ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Discrete Jitter (DJ): 0.130ns
|
|
Phase Error (PE): 0.000ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock cpu_clk rise edge) 0.000 0.000 r
|
|
clock source latency -6.275 -6.275
|
|
propagated clock network latency
|
|
4.051 -2.225
|
|
SLICE_X35Y35 FDRE 0.000 -2.225 r u_cpu/addr_trans/data_vaddr_buffer_reg[14]/C
|
|
SLICE_X35Y35 FDRE (Prop_fdre_C_Q) 0.456 -1.769 r u_cpu/addr_trans/data_vaddr_buffer_reg[14]/Q
|
|
net (fo=33, routed) 1.442 -0.326 u_cpu/addr_trans/tlb_entry/data_vaddr_buffer[2]
|
|
SLICE_X42Y40 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_226/I5
|
|
SLICE_X42Y40 LUT6 (Prop_lut6_I5_O) 0.124 -0.202 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_226/O
|
|
net (fo=1, routed) 0.000 -0.202 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_226_n_0
|
|
SLICE_X42Y40 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_111/S[0]
|
|
SLICE_X42Y40 CARRY4 (Prop_carry4_S[0]_CO[3])
|
|
0.513 0.311 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_111/CO[3]
|
|
net (fo=1, routed) 0.000 0.311 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_111_n_0
|
|
SLICE_X42Y41 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_32/CI
|
|
SLICE_X42Y41 CARRY4 (Prop_carry4_CI_CO[2])
|
|
0.229 0.540 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_32/CO[2]
|
|
net (fo=1, routed) 1.009 1.549 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_32_n_1
|
|
SLICE_X40Y47 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_9/I1
|
|
SLICE_X40Y47 LUT6 (Prop_lut6_I1_O) 0.310 1.859 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_9/O
|
|
net (fo=2, routed) 0.635 2.494 u_cpu/addr_trans/tlb_entry/match1[28]
|
|
SLICE_X38Y47 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/I2
|
|
SLICE_X38Y47 LUT4 (Prop_lut4_I2_O) 0.124 2.618 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/O
|
|
net (fo=2, routed) 0.667 3.285 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2_n_0
|
|
SLICE_X39Y47 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/I0
|
|
SLICE_X39Y47 LUT5 (Prop_lut5_I0_O) 0.124 3.409 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/O
|
|
net (fo=2, routed) 1.103 4.512 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2_n_0
|
|
SLICE_X38Y50 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/I0
|
|
SLICE_X38Y50 LUT6 (Prop_lut6_I0_O) 0.124 4.636 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/O
|
|
net (fo=89, routed) 1.162 5.797 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus[8]
|
|
SLICE_X42Y51 r u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_38__0/S
|
|
SLICE_X42Y51 MUXF7 (Prop_muxf7_S_O) 0.292 6.089 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_38__0/O
|
|
net (fo=1, routed) 0.000 6.089 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_38__0_n_0
|
|
SLICE_X42Y51 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_16__0/I1
|
|
SLICE_X42Y51 MUXF8 (Prop_muxf8_I1_O) 0.088 6.177 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_16__0/O
|
|
net (fo=1, routed) 0.957 7.134 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_16__0_n_0
|
|
SLICE_X42Y50 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7/I0
|
|
SLICE_X42Y50 LUT6 (Prop_lut6_I0_O) 0.319 7.453 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7/O
|
|
net (fo=1, routed) 0.435 7.888 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7_n_0
|
|
SLICE_X44Y50 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0/I5
|
|
SLICE_X44Y50 LUT6 (Prop_lut6_I5_O) 0.124 8.012 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0/O
|
|
net (fo=10, routed) 0.740 8.753 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0_n_0
|
|
SLICE_X44Y50 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[5]_i_1__0/I3
|
|
SLICE_X44Y50 LUT6 (Prop_lut6_I3_O) 0.124 8.877 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[5]_i_1__0/O
|
|
net (fo=6, routed) 0.845 9.722 u_cpu/u_csr/ms_to_ws_bus[13]
|
|
SLICE_X50Y46 f u_cpu/u_csr/write_buffer_way[1]_i_18/I3
|
|
SLICE_X50Y46 LUT6 (Prop_lut6_I3_O) 0.124 9.846 r u_cpu/u_csr/write_buffer_way[1]_i_18/O
|
|
net (fo=1, routed) 0.000 9.846 u_cpu/u_csr/write_buffer_way[1]_i_18_n_0
|
|
SLICE_X50Y46 r u_cpu/u_csr/write_buffer_way_reg[1]_i_11/S[0]
|
|
SLICE_X50Y46 CARRY4 (Prop_carry4_S[0]_CO[3])
|
|
0.532 10.378 r u_cpu/u_csr/write_buffer_way_reg[1]_i_11/CO[3]
|
|
net (fo=1, routed) 0.000 10.378 u_cpu/u_csr/write_buffer_way_reg[1]_i_11_n_0
|
|
SLICE_X50Y47 r u_cpu/u_csr/write_buffer_way_reg[1]_i_9/CI
|
|
SLICE_X50Y47 CARRY4 (Prop_carry4_CI_CO[1])
|
|
0.157 10.535 r u_cpu/u_csr/write_buffer_way_reg[1]_i_9/CO[1]
|
|
net (fo=2, routed) 0.791 11.326 u_cpu/wb_stage/CO[0]
|
|
SLICE_X46Y39 r u_cpu/wb_stage/write_buffer_way[1]_i_5/I1
|
|
SLICE_X46Y39 LUT6 (Prop_lut6_I1_O) 0.329 11.655 f u_cpu/wb_stage/write_buffer_way[1]_i_5/O
|
|
net (fo=7, routed) 0.762 12.417 u_cpu/addr_trans/tlb_entry/sc_cancel_req
|
|
SLICE_X46Y35 f u_cpu/addr_trans/tlb_entry/main_state[0]_i_3/I1
|
|
SLICE_X46Y35 LUT3 (Prop_lut3_I1_O) 0.124 12.541 f u_cpu/addr_trans/tlb_entry/main_state[0]_i_3/O
|
|
net (fo=3, routed) 0.719 13.260 u_cpu/dcache/main_state_reg[0]_2
|
|
SLICE_X43Y31 f u_cpu/dcache/ds_to_es_bus_r[235]_i_10/I3
|
|
SLICE_X43Y31 LUT6 (Prop_lut6_I3_O) 0.124 13.384 f u_cpu/dcache/ds_to_es_bus_r[235]_i_10/O
|
|
net (fo=3, routed) 0.415 13.799 u_cpu/mem_stage/data_data_ok
|
|
SLICE_X43Y30 f u_cpu/mem_stage/flush_inst_req_buffer[1]_i_15/I0
|
|
SLICE_X43Y30 LUT3 (Prop_lut3_I0_O) 0.124 13.923 f u_cpu/mem_stage/flush_inst_req_buffer[1]_i_15/O
|
|
net (fo=2, routed) 0.833 14.756 u_cpu/mem_stage/es_to_ms_bus_r_reg[70]_1
|
|
SLICE_X48Y30 f u_cpu/mem_stage/flush_inst_req_buffer[1]_i_14/I0
|
|
SLICE_X48Y30 LUT6 (Prop_lut6_I0_O) 0.124 14.880 f u_cpu/mem_stage/flush_inst_req_buffer[1]_i_14/O
|
|
net (fo=1, routed) 0.651 15.532 u_cpu/mem_stage/ms_ready_go
|
|
SLICE_X48Y25 f u_cpu/mem_stage/flush_inst_req_buffer[1]_i_13/I4
|
|
SLICE_X48Y25 LUT6 (Prop_lut6_I4_O) 0.124 15.656 f u_cpu/mem_stage/flush_inst_req_buffer[1]_i_13/O
|
|
net (fo=3, routed) 0.483 16.139 u_cpu/id_stage/flush_inst_req_buffer[31]_i_6
|
|
SLICE_X50Y25 f u_cpu/id_stage/flush_inst_req_buffer[1]_i_9/I1
|
|
SLICE_X50Y25 LUT6 (Prop_lut6_I1_O) 0.124 16.263 f u_cpu/id_stage/flush_inst_req_buffer[1]_i_9/O
|
|
net (fo=32, routed) 0.531 16.794 u_cpu/if_stage/nextpc5
|
|
SLICE_X51Y27 f u_cpu/if_stage/fetch_pc_r[6]_i_4/I2
|
|
SLICE_X51Y27 LUT6 (Prop_lut6_I2_O) 0.124 16.918 r u_cpu/if_stage/fetch_pc_r[6]_i_4/O
|
|
net (fo=1, routed) 3.059 19.977 u_cpu/if_stage/fetch_pc_r[6]_i_4_n_0
|
|
SLICE_X114Y28 r u_cpu/if_stage/fetch_pc_r[6]_i_2/I2
|
|
SLICE_X114Y28 LUT6 (Prop_lut6_I2_O) 0.124 20.101 r u_cpu/if_stage/fetch_pc_r[6]_i_2/O
|
|
net (fo=1, routed) 0.441 20.542 u_cpu/if_stage/fetch_pc_r[6]_i_2_n_0
|
|
SLICE_X114Y25 r u_cpu/if_stage/fetch_pc_r[6]_i_1/I2
|
|
SLICE_X114Y25 LUT6 (Prop_lut6_I2_O) 0.124 20.666 r u_cpu/if_stage/fetch_pc_r[6]_i_1/O
|
|
net (fo=6, routed) 3.249 23.915 u_cpu/icache/tagv_ram_way[1].u/mem_reg_reg_2[2]
|
|
SLICE_X49Y33 r u_cpu/icache/tagv_ram_way[1].u/mem_reg_reg_i_8/I4
|
|
SLICE_X49Y33 LUT5 (Prop_lut5_I4_O) 0.124 24.039 r u_cpu/icache/tagv_ram_way[1].u/mem_reg_reg_i_8/O
|
|
net (fo=16, routed) 1.477 25.516 u_cpu/icache/data_ram_way[0].data_ram_bank[2].u/ADDRBWRADDR[2]
|
|
RAMB18_X2Y2 RAMB18E1 r u_cpu/icache/data_ram_way[0].data_ram_bank[2].u/mem_reg_reg/ADDRBWRADDR[7]
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock cpu_clk rise edge) 30.323 30.323 r
|
|
clock source latency -5.674 24.648
|
|
propagated clock network latency
|
|
3.782 28.430
|
|
clock pessimism -0.418 28.012
|
|
clock uncertainty -0.074 27.938
|
|
RAMB18_X2Y2 RAMB18E1 (Setup_ramb18e1_CLKBWRCLK_ADDRBWRADDR[7])
|
|
-0.566 27.372 u_cpu/icache/data_ram_way[0].data_ram_bank[2].u/mem_reg_reg
|
|
-------------------------------------------------------------------
|
|
required time 27.372
|
|
arrival time -25.516
|
|
-------------------------------------------------------------------
|
|
slack 1.856
|
|
|
|
Slack (MET) : 1.856ns (required time - arrival time)
|
|
Source: u_cpu/addr_trans/data_vaddr_buffer_reg[14]/C
|
|
(rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns})
|
|
Destination: u_cpu/icache/data_ram_way[0].data_ram_bank[2].u/mem_reg_reg/ADDRBWRADDR[7]
|
|
(rising edge-triggered cell RAMB18E1 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns})
|
|
Path Group: cpu_clk
|
|
Path Type: Setup (Max at Slow Process Corner)
|
|
Requirement: 30.323ns (cpu_clk rise@30.323ns - cpu_clk rise@0.000ns)
|
|
Data Path Delay: 27.741ns (logic 5.333ns (19.224%) route 22.408ns (80.776%))
|
|
Logic Levels: 26 (CARRY4=4 LUT3=2 LUT4=1 LUT5=2 LUT6=15 MUXF7=1 MUXF8=1)
|
|
Clock Path Skew: -0.086ns (DCD - SCD + CPR)
|
|
Destination Clock Delay (DCD): -1.892ns = ( 28.430 - 30.323 )
|
|
Source Clock Delay (SCD): -2.225ns
|
|
Clock Pessimism Removal (CPR): -0.418ns
|
|
Clock Uncertainty: 0.074ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Discrete Jitter (DJ): 0.130ns
|
|
Phase Error (PE): 0.000ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock cpu_clk rise edge) 0.000 0.000 r
|
|
clock source latency -6.275 -6.275
|
|
propagated clock network latency
|
|
4.051 -2.225
|
|
SLICE_X35Y35 FDRE 0.000 -2.225 r u_cpu/addr_trans/data_vaddr_buffer_reg[14]/C
|
|
SLICE_X35Y35 FDRE (Prop_fdre_C_Q) 0.456 -1.769 r u_cpu/addr_trans/data_vaddr_buffer_reg[14]/Q
|
|
net (fo=33, routed) 1.442 -0.326 u_cpu/addr_trans/tlb_entry/data_vaddr_buffer[2]
|
|
SLICE_X42Y40 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_226/I5
|
|
SLICE_X42Y40 LUT6 (Prop_lut6_I5_O) 0.124 -0.202 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_226/O
|
|
net (fo=1, routed) 0.000 -0.202 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_226_n_0
|
|
SLICE_X42Y40 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_111/S[0]
|
|
SLICE_X42Y40 CARRY4 (Prop_carry4_S[0]_CO[3])
|
|
0.513 0.311 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_111/CO[3]
|
|
net (fo=1, routed) 0.000 0.311 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_111_n_0
|
|
SLICE_X42Y41 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_32/CI
|
|
SLICE_X42Y41 CARRY4 (Prop_carry4_CI_CO[2])
|
|
0.229 0.540 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_32/CO[2]
|
|
net (fo=1, routed) 1.009 1.549 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_32_n_1
|
|
SLICE_X40Y47 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_9/I1
|
|
SLICE_X40Y47 LUT6 (Prop_lut6_I1_O) 0.310 1.859 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_9/O
|
|
net (fo=2, routed) 0.635 2.494 u_cpu/addr_trans/tlb_entry/match1[28]
|
|
SLICE_X38Y47 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/I2
|
|
SLICE_X38Y47 LUT4 (Prop_lut4_I2_O) 0.124 2.618 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/O
|
|
net (fo=2, routed) 0.667 3.285 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2_n_0
|
|
SLICE_X39Y47 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/I0
|
|
SLICE_X39Y47 LUT5 (Prop_lut5_I0_O) 0.124 3.409 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/O
|
|
net (fo=2, routed) 1.103 4.512 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2_n_0
|
|
SLICE_X38Y50 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/I0
|
|
SLICE_X38Y50 LUT6 (Prop_lut6_I0_O) 0.124 4.636 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/O
|
|
net (fo=89, routed) 1.162 5.797 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus[8]
|
|
SLICE_X42Y51 r u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_38__0/S
|
|
SLICE_X42Y51 MUXF7 (Prop_muxf7_S_O) 0.292 6.089 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_38__0/O
|
|
net (fo=1, routed) 0.000 6.089 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_38__0_n_0
|
|
SLICE_X42Y51 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_16__0/I1
|
|
SLICE_X42Y51 MUXF8 (Prop_muxf8_I1_O) 0.088 6.177 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_16__0/O
|
|
net (fo=1, routed) 0.957 7.134 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_16__0_n_0
|
|
SLICE_X42Y50 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7/I0
|
|
SLICE_X42Y50 LUT6 (Prop_lut6_I0_O) 0.319 7.453 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7/O
|
|
net (fo=1, routed) 0.435 7.888 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7_n_0
|
|
SLICE_X44Y50 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0/I5
|
|
SLICE_X44Y50 LUT6 (Prop_lut6_I5_O) 0.124 8.012 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0/O
|
|
net (fo=10, routed) 0.740 8.753 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0_n_0
|
|
SLICE_X44Y50 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[5]_i_1__0/I3
|
|
SLICE_X44Y50 LUT6 (Prop_lut6_I3_O) 0.124 8.877 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[5]_i_1__0/O
|
|
net (fo=6, routed) 0.845 9.722 u_cpu/u_csr/ms_to_ws_bus[13]
|
|
SLICE_X50Y46 r u_cpu/u_csr/write_buffer_way[1]_i_18/I3
|
|
SLICE_X50Y46 LUT6 (Prop_lut6_I3_O) 0.124 9.846 f u_cpu/u_csr/write_buffer_way[1]_i_18/O
|
|
net (fo=1, routed) 0.000 9.846 u_cpu/u_csr/write_buffer_way[1]_i_18_n_0
|
|
SLICE_X50Y46 f u_cpu/u_csr/write_buffer_way_reg[1]_i_11/S[0]
|
|
SLICE_X50Y46 CARRY4 (Prop_carry4_S[0]_CO[3])
|
|
0.532 10.378 r u_cpu/u_csr/write_buffer_way_reg[1]_i_11/CO[3]
|
|
net (fo=1, routed) 0.000 10.378 u_cpu/u_csr/write_buffer_way_reg[1]_i_11_n_0
|
|
SLICE_X50Y47 r u_cpu/u_csr/write_buffer_way_reg[1]_i_9/CI
|
|
SLICE_X50Y47 CARRY4 (Prop_carry4_CI_CO[1])
|
|
0.157 10.535 r u_cpu/u_csr/write_buffer_way_reg[1]_i_9/CO[1]
|
|
net (fo=2, routed) 0.791 11.326 u_cpu/wb_stage/CO[0]
|
|
SLICE_X46Y39 r u_cpu/wb_stage/write_buffer_way[1]_i_5/I1
|
|
SLICE_X46Y39 LUT6 (Prop_lut6_I1_O) 0.329 11.655 f u_cpu/wb_stage/write_buffer_way[1]_i_5/O
|
|
net (fo=7, routed) 0.762 12.417 u_cpu/addr_trans/tlb_entry/sc_cancel_req
|
|
SLICE_X46Y35 f u_cpu/addr_trans/tlb_entry/main_state[0]_i_3/I1
|
|
SLICE_X46Y35 LUT3 (Prop_lut3_I1_O) 0.124 12.541 f u_cpu/addr_trans/tlb_entry/main_state[0]_i_3/O
|
|
net (fo=3, routed) 0.719 13.260 u_cpu/dcache/main_state_reg[0]_2
|
|
SLICE_X43Y31 f u_cpu/dcache/ds_to_es_bus_r[235]_i_10/I3
|
|
SLICE_X43Y31 LUT6 (Prop_lut6_I3_O) 0.124 13.384 f u_cpu/dcache/ds_to_es_bus_r[235]_i_10/O
|
|
net (fo=3, routed) 0.415 13.799 u_cpu/mem_stage/data_data_ok
|
|
SLICE_X43Y30 f u_cpu/mem_stage/flush_inst_req_buffer[1]_i_15/I0
|
|
SLICE_X43Y30 LUT3 (Prop_lut3_I0_O) 0.124 13.923 f u_cpu/mem_stage/flush_inst_req_buffer[1]_i_15/O
|
|
net (fo=2, routed) 0.833 14.756 u_cpu/mem_stage/es_to_ms_bus_r_reg[70]_1
|
|
SLICE_X48Y30 f u_cpu/mem_stage/flush_inst_req_buffer[1]_i_14/I0
|
|
SLICE_X48Y30 LUT6 (Prop_lut6_I0_O) 0.124 14.880 f u_cpu/mem_stage/flush_inst_req_buffer[1]_i_14/O
|
|
net (fo=1, routed) 0.651 15.532 u_cpu/mem_stage/ms_ready_go
|
|
SLICE_X48Y25 f u_cpu/mem_stage/flush_inst_req_buffer[1]_i_13/I4
|
|
SLICE_X48Y25 LUT6 (Prop_lut6_I4_O) 0.124 15.656 f u_cpu/mem_stage/flush_inst_req_buffer[1]_i_13/O
|
|
net (fo=3, routed) 0.483 16.139 u_cpu/id_stage/flush_inst_req_buffer[31]_i_6
|
|
SLICE_X50Y25 f u_cpu/id_stage/flush_inst_req_buffer[1]_i_9/I1
|
|
SLICE_X50Y25 LUT6 (Prop_lut6_I1_O) 0.124 16.263 f u_cpu/id_stage/flush_inst_req_buffer[1]_i_9/O
|
|
net (fo=32, routed) 0.531 16.794 u_cpu/if_stage/nextpc5
|
|
SLICE_X51Y27 f u_cpu/if_stage/fetch_pc_r[6]_i_4/I2
|
|
SLICE_X51Y27 LUT6 (Prop_lut6_I2_O) 0.124 16.918 r u_cpu/if_stage/fetch_pc_r[6]_i_4/O
|
|
net (fo=1, routed) 3.059 19.977 u_cpu/if_stage/fetch_pc_r[6]_i_4_n_0
|
|
SLICE_X114Y28 r u_cpu/if_stage/fetch_pc_r[6]_i_2/I2
|
|
SLICE_X114Y28 LUT6 (Prop_lut6_I2_O) 0.124 20.101 r u_cpu/if_stage/fetch_pc_r[6]_i_2/O
|
|
net (fo=1, routed) 0.441 20.542 u_cpu/if_stage/fetch_pc_r[6]_i_2_n_0
|
|
SLICE_X114Y25 r u_cpu/if_stage/fetch_pc_r[6]_i_1/I2
|
|
SLICE_X114Y25 LUT6 (Prop_lut6_I2_O) 0.124 20.666 r u_cpu/if_stage/fetch_pc_r[6]_i_1/O
|
|
net (fo=6, routed) 3.249 23.915 u_cpu/icache/tagv_ram_way[1].u/mem_reg_reg_2[2]
|
|
SLICE_X49Y33 r u_cpu/icache/tagv_ram_way[1].u/mem_reg_reg_i_8/I4
|
|
SLICE_X49Y33 LUT5 (Prop_lut5_I4_O) 0.124 24.039 r u_cpu/icache/tagv_ram_way[1].u/mem_reg_reg_i_8/O
|
|
net (fo=16, routed) 1.477 25.516 u_cpu/icache/data_ram_way[0].data_ram_bank[2].u/ADDRBWRADDR[2]
|
|
RAMB18_X2Y2 RAMB18E1 r u_cpu/icache/data_ram_way[0].data_ram_bank[2].u/mem_reg_reg/ADDRBWRADDR[7]
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock cpu_clk rise edge) 30.323 30.323 r
|
|
clock source latency -5.674 24.648
|
|
propagated clock network latency
|
|
3.782 28.430
|
|
clock pessimism -0.418 28.012
|
|
clock uncertainty -0.074 27.938
|
|
RAMB18_X2Y2 RAMB18E1 (Setup_ramb18e1_CLKBWRCLK_ADDRBWRADDR[7])
|
|
-0.566 27.372 u_cpu/icache/data_ram_way[0].data_ram_bank[2].u/mem_reg_reg
|
|
-------------------------------------------------------------------
|
|
required time 27.372
|
|
arrival time -25.516
|
|
-------------------------------------------------------------------
|
|
slack 1.856
|
|
|
|
Slack (MET) : 1.856ns (required time - arrival time)
|
|
Source: u_cpu/addr_trans/data_vaddr_buffer_reg[14]/C
|
|
(rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns})
|
|
Destination: u_cpu/icache/data_ram_way[0].data_ram_bank[2].u/mem_reg_reg/ADDRBWRADDR[7]
|
|
(rising edge-triggered cell RAMB18E1 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns})
|
|
Path Group: cpu_clk
|
|
Path Type: Setup (Max at Slow Process Corner)
|
|
Requirement: 30.323ns (cpu_clk rise@30.323ns - cpu_clk rise@0.000ns)
|
|
Data Path Delay: 27.741ns (logic 5.333ns (19.224%) route 22.408ns (80.776%))
|
|
Logic Levels: 26 (CARRY4=4 LUT3=2 LUT4=1 LUT5=2 LUT6=15 MUXF7=1 MUXF8=1)
|
|
Clock Path Skew: -0.086ns (DCD - SCD + CPR)
|
|
Destination Clock Delay (DCD): -1.892ns = ( 28.430 - 30.323 )
|
|
Source Clock Delay (SCD): -2.225ns
|
|
Clock Pessimism Removal (CPR): -0.418ns
|
|
Clock Uncertainty: 0.074ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Discrete Jitter (DJ): 0.130ns
|
|
Phase Error (PE): 0.000ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock cpu_clk rise edge) 0.000 0.000 r
|
|
clock source latency -6.275 -6.275
|
|
propagated clock network latency
|
|
4.051 -2.225
|
|
SLICE_X35Y35 FDRE 0.000 -2.225 r u_cpu/addr_trans/data_vaddr_buffer_reg[14]/C
|
|
SLICE_X35Y35 FDRE (Prop_fdre_C_Q) 0.456 -1.769 r u_cpu/addr_trans/data_vaddr_buffer_reg[14]/Q
|
|
net (fo=33, routed) 1.442 -0.326 u_cpu/addr_trans/tlb_entry/data_vaddr_buffer[2]
|
|
SLICE_X42Y40 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_226/I5
|
|
SLICE_X42Y40 LUT6 (Prop_lut6_I5_O) 0.124 -0.202 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_226/O
|
|
net (fo=1, routed) 0.000 -0.202 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_226_n_0
|
|
SLICE_X42Y40 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_111/S[0]
|
|
SLICE_X42Y40 CARRY4 (Prop_carry4_S[0]_CO[3])
|
|
0.513 0.311 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_111/CO[3]
|
|
net (fo=1, routed) 0.000 0.311 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_111_n_0
|
|
SLICE_X42Y41 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_32/CI
|
|
SLICE_X42Y41 CARRY4 (Prop_carry4_CI_CO[2])
|
|
0.229 0.540 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_32/CO[2]
|
|
net (fo=1, routed) 1.009 1.549 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_32_n_1
|
|
SLICE_X40Y47 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_9/I1
|
|
SLICE_X40Y47 LUT6 (Prop_lut6_I1_O) 0.310 1.859 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_9/O
|
|
net (fo=2, routed) 0.635 2.494 u_cpu/addr_trans/tlb_entry/match1[28]
|
|
SLICE_X38Y47 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/I2
|
|
SLICE_X38Y47 LUT4 (Prop_lut4_I2_O) 0.124 2.618 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/O
|
|
net (fo=2, routed) 0.667 3.285 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2_n_0
|
|
SLICE_X39Y47 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/I0
|
|
SLICE_X39Y47 LUT5 (Prop_lut5_I0_O) 0.124 3.409 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/O
|
|
net (fo=2, routed) 1.103 4.512 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2_n_0
|
|
SLICE_X38Y50 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/I0
|
|
SLICE_X38Y50 LUT6 (Prop_lut6_I0_O) 0.124 4.636 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/O
|
|
net (fo=89, routed) 1.162 5.797 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus[8]
|
|
SLICE_X42Y51 r u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_38__0/S
|
|
SLICE_X42Y51 MUXF7 (Prop_muxf7_S_O) 0.292 6.089 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_38__0/O
|
|
net (fo=1, routed) 0.000 6.089 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_38__0_n_0
|
|
SLICE_X42Y51 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_16__0/I1
|
|
SLICE_X42Y51 MUXF8 (Prop_muxf8_I1_O) 0.088 6.177 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_16__0/O
|
|
net (fo=1, routed) 0.957 7.134 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_16__0_n_0
|
|
SLICE_X42Y50 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7/I0
|
|
SLICE_X42Y50 LUT6 (Prop_lut6_I0_O) 0.319 7.453 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7/O
|
|
net (fo=1, routed) 0.435 7.888 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7_n_0
|
|
SLICE_X44Y50 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0/I5
|
|
SLICE_X44Y50 LUT6 (Prop_lut6_I5_O) 0.124 8.012 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0/O
|
|
net (fo=10, routed) 0.740 8.753 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0_n_0
|
|
SLICE_X44Y50 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[5]_i_1__0/I3
|
|
SLICE_X44Y50 LUT6 (Prop_lut6_I3_O) 0.124 8.877 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[5]_i_1__0/O
|
|
net (fo=6, routed) 0.845 9.722 u_cpu/u_csr/ms_to_ws_bus[13]
|
|
SLICE_X50Y46 f u_cpu/u_csr/write_buffer_way[1]_i_18/I3
|
|
SLICE_X50Y46 LUT6 (Prop_lut6_I3_O) 0.124 9.846 f u_cpu/u_csr/write_buffer_way[1]_i_18/O
|
|
net (fo=1, routed) 0.000 9.846 u_cpu/u_csr/write_buffer_way[1]_i_18_n_0
|
|
SLICE_X50Y46 f u_cpu/u_csr/write_buffer_way_reg[1]_i_11/S[0]
|
|
SLICE_X50Y46 CARRY4 (Prop_carry4_S[0]_CO[3])
|
|
0.532 10.378 r u_cpu/u_csr/write_buffer_way_reg[1]_i_11/CO[3]
|
|
net (fo=1, routed) 0.000 10.378 u_cpu/u_csr/write_buffer_way_reg[1]_i_11_n_0
|
|
SLICE_X50Y47 r u_cpu/u_csr/write_buffer_way_reg[1]_i_9/CI
|
|
SLICE_X50Y47 CARRY4 (Prop_carry4_CI_CO[1])
|
|
0.157 10.535 r u_cpu/u_csr/write_buffer_way_reg[1]_i_9/CO[1]
|
|
net (fo=2, routed) 0.791 11.326 u_cpu/wb_stage/CO[0]
|
|
SLICE_X46Y39 r u_cpu/wb_stage/write_buffer_way[1]_i_5/I1
|
|
SLICE_X46Y39 LUT6 (Prop_lut6_I1_O) 0.329 11.655 f u_cpu/wb_stage/write_buffer_way[1]_i_5/O
|
|
net (fo=7, routed) 0.762 12.417 u_cpu/addr_trans/tlb_entry/sc_cancel_req
|
|
SLICE_X46Y35 f u_cpu/addr_trans/tlb_entry/main_state[0]_i_3/I1
|
|
SLICE_X46Y35 LUT3 (Prop_lut3_I1_O) 0.124 12.541 f u_cpu/addr_trans/tlb_entry/main_state[0]_i_3/O
|
|
net (fo=3, routed) 0.719 13.260 u_cpu/dcache/main_state_reg[0]_2
|
|
SLICE_X43Y31 f u_cpu/dcache/ds_to_es_bus_r[235]_i_10/I3
|
|
SLICE_X43Y31 LUT6 (Prop_lut6_I3_O) 0.124 13.384 f u_cpu/dcache/ds_to_es_bus_r[235]_i_10/O
|
|
net (fo=3, routed) 0.415 13.799 u_cpu/mem_stage/data_data_ok
|
|
SLICE_X43Y30 f u_cpu/mem_stage/flush_inst_req_buffer[1]_i_15/I0
|
|
SLICE_X43Y30 LUT3 (Prop_lut3_I0_O) 0.124 13.923 f u_cpu/mem_stage/flush_inst_req_buffer[1]_i_15/O
|
|
net (fo=2, routed) 0.833 14.756 u_cpu/mem_stage/es_to_ms_bus_r_reg[70]_1
|
|
SLICE_X48Y30 f u_cpu/mem_stage/flush_inst_req_buffer[1]_i_14/I0
|
|
SLICE_X48Y30 LUT6 (Prop_lut6_I0_O) 0.124 14.880 f u_cpu/mem_stage/flush_inst_req_buffer[1]_i_14/O
|
|
net (fo=1, routed) 0.651 15.532 u_cpu/mem_stage/ms_ready_go
|
|
SLICE_X48Y25 f u_cpu/mem_stage/flush_inst_req_buffer[1]_i_13/I4
|
|
SLICE_X48Y25 LUT6 (Prop_lut6_I4_O) 0.124 15.656 f u_cpu/mem_stage/flush_inst_req_buffer[1]_i_13/O
|
|
net (fo=3, routed) 0.483 16.139 u_cpu/id_stage/flush_inst_req_buffer[31]_i_6
|
|
SLICE_X50Y25 f u_cpu/id_stage/flush_inst_req_buffer[1]_i_9/I1
|
|
SLICE_X50Y25 LUT6 (Prop_lut6_I1_O) 0.124 16.263 f u_cpu/id_stage/flush_inst_req_buffer[1]_i_9/O
|
|
net (fo=32, routed) 0.531 16.794 u_cpu/if_stage/nextpc5
|
|
SLICE_X51Y27 f u_cpu/if_stage/fetch_pc_r[6]_i_4/I2
|
|
SLICE_X51Y27 LUT6 (Prop_lut6_I2_O) 0.124 16.918 r u_cpu/if_stage/fetch_pc_r[6]_i_4/O
|
|
net (fo=1, routed) 3.059 19.977 u_cpu/if_stage/fetch_pc_r[6]_i_4_n_0
|
|
SLICE_X114Y28 r u_cpu/if_stage/fetch_pc_r[6]_i_2/I2
|
|
SLICE_X114Y28 LUT6 (Prop_lut6_I2_O) 0.124 20.101 r u_cpu/if_stage/fetch_pc_r[6]_i_2/O
|
|
net (fo=1, routed) 0.441 20.542 u_cpu/if_stage/fetch_pc_r[6]_i_2_n_0
|
|
SLICE_X114Y25 r u_cpu/if_stage/fetch_pc_r[6]_i_1/I2
|
|
SLICE_X114Y25 LUT6 (Prop_lut6_I2_O) 0.124 20.666 r u_cpu/if_stage/fetch_pc_r[6]_i_1/O
|
|
net (fo=6, routed) 3.249 23.915 u_cpu/icache/tagv_ram_way[1].u/mem_reg_reg_2[2]
|
|
SLICE_X49Y33 r u_cpu/icache/tagv_ram_way[1].u/mem_reg_reg_i_8/I4
|
|
SLICE_X49Y33 LUT5 (Prop_lut5_I4_O) 0.124 24.039 r u_cpu/icache/tagv_ram_way[1].u/mem_reg_reg_i_8/O
|
|
net (fo=16, routed) 1.477 25.516 u_cpu/icache/data_ram_way[0].data_ram_bank[2].u/ADDRBWRADDR[2]
|
|
RAMB18_X2Y2 RAMB18E1 r u_cpu/icache/data_ram_way[0].data_ram_bank[2].u/mem_reg_reg/ADDRBWRADDR[7]
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock cpu_clk rise edge) 30.323 30.323 r
|
|
clock source latency -5.674 24.648
|
|
propagated clock network latency
|
|
3.782 28.430
|
|
clock pessimism -0.418 28.012
|
|
clock uncertainty -0.074 27.938
|
|
RAMB18_X2Y2 RAMB18E1 (Setup_ramb18e1_CLKBWRCLK_ADDRBWRADDR[7])
|
|
-0.566 27.372 u_cpu/icache/data_ram_way[0].data_ram_bank[2].u/mem_reg_reg
|
|
-------------------------------------------------------------------
|
|
required time 27.372
|
|
arrival time -25.516
|
|
-------------------------------------------------------------------
|
|
slack 1.856
|
|
|
|
Slack (MET) : 1.856ns (required time - arrival time)
|
|
Source: u_cpu/addr_trans/data_vaddr_buffer_reg[14]/C
|
|
(rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns})
|
|
Destination: u_cpu/icache/data_ram_way[0].data_ram_bank[3].u/mem_reg_reg/ADDRBWRADDR[7]
|
|
(rising edge-triggered cell RAMB18E1 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns})
|
|
Path Group: cpu_clk
|
|
Path Type: Setup (Max at Slow Process Corner)
|
|
Requirement: 30.323ns (cpu_clk rise@30.323ns - cpu_clk rise@0.000ns)
|
|
Data Path Delay: 27.741ns (logic 5.333ns (19.224%) route 22.408ns (80.776%))
|
|
Logic Levels: 26 (CARRY4=4 LUT3=2 LUT4=1 LUT5=2 LUT6=15 MUXF7=1 MUXF8=1)
|
|
Clock Path Skew: -0.086ns (DCD - SCD + CPR)
|
|
Destination Clock Delay (DCD): -1.892ns = ( 28.430 - 30.323 )
|
|
Source Clock Delay (SCD): -2.225ns
|
|
Clock Pessimism Removal (CPR): -0.418ns
|
|
Clock Uncertainty: 0.074ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Discrete Jitter (DJ): 0.130ns
|
|
Phase Error (PE): 0.000ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock cpu_clk rise edge) 0.000 0.000 r
|
|
clock source latency -6.275 -6.275
|
|
propagated clock network latency
|
|
4.051 -2.225
|
|
SLICE_X35Y35 FDRE 0.000 -2.225 r u_cpu/addr_trans/data_vaddr_buffer_reg[14]/C
|
|
SLICE_X35Y35 FDRE (Prop_fdre_C_Q) 0.456 -1.769 r u_cpu/addr_trans/data_vaddr_buffer_reg[14]/Q
|
|
net (fo=33, routed) 1.442 -0.326 u_cpu/addr_trans/tlb_entry/data_vaddr_buffer[2]
|
|
SLICE_X42Y40 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_226/I5
|
|
SLICE_X42Y40 LUT6 (Prop_lut6_I5_O) 0.124 -0.202 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_226/O
|
|
net (fo=1, routed) 0.000 -0.202 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_226_n_0
|
|
SLICE_X42Y40 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_111/S[0]
|
|
SLICE_X42Y40 CARRY4 (Prop_carry4_S[0]_CO[3])
|
|
0.513 0.311 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_111/CO[3]
|
|
net (fo=1, routed) 0.000 0.311 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_111_n_0
|
|
SLICE_X42Y41 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_32/CI
|
|
SLICE_X42Y41 CARRY4 (Prop_carry4_CI_CO[2])
|
|
0.229 0.540 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_32/CO[2]
|
|
net (fo=1, routed) 1.009 1.549 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_32_n_1
|
|
SLICE_X40Y47 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_9/I1
|
|
SLICE_X40Y47 LUT6 (Prop_lut6_I1_O) 0.310 1.859 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_9/O
|
|
net (fo=2, routed) 0.635 2.494 u_cpu/addr_trans/tlb_entry/match1[28]
|
|
SLICE_X38Y47 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/I2
|
|
SLICE_X38Y47 LUT4 (Prop_lut4_I2_O) 0.124 2.618 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/O
|
|
net (fo=2, routed) 0.667 3.285 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2_n_0
|
|
SLICE_X39Y47 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/I0
|
|
SLICE_X39Y47 LUT5 (Prop_lut5_I0_O) 0.124 3.409 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/O
|
|
net (fo=2, routed) 1.103 4.512 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2_n_0
|
|
SLICE_X38Y50 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/I0
|
|
SLICE_X38Y50 LUT6 (Prop_lut6_I0_O) 0.124 4.636 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/O
|
|
net (fo=89, routed) 1.162 5.797 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus[8]
|
|
SLICE_X42Y51 r u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_38__0/S
|
|
SLICE_X42Y51 MUXF7 (Prop_muxf7_S_O) 0.292 6.089 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_38__0/O
|
|
net (fo=1, routed) 0.000 6.089 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_38__0_n_0
|
|
SLICE_X42Y51 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_16__0/I1
|
|
SLICE_X42Y51 MUXF8 (Prop_muxf8_I1_O) 0.088 6.177 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_16__0/O
|
|
net (fo=1, routed) 0.957 7.134 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_16__0_n_0
|
|
SLICE_X42Y50 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7/I0
|
|
SLICE_X42Y50 LUT6 (Prop_lut6_I0_O) 0.319 7.453 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7/O
|
|
net (fo=1, routed) 0.435 7.888 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7_n_0
|
|
SLICE_X44Y50 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0/I5
|
|
SLICE_X44Y50 LUT6 (Prop_lut6_I5_O) 0.124 8.012 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0/O
|
|
net (fo=10, routed) 0.740 8.753 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0_n_0
|
|
SLICE_X44Y50 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[5]_i_1__0/I3
|
|
SLICE_X44Y50 LUT6 (Prop_lut6_I3_O) 0.124 8.877 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[5]_i_1__0/O
|
|
net (fo=6, routed) 0.845 9.722 u_cpu/u_csr/ms_to_ws_bus[13]
|
|
SLICE_X50Y46 r u_cpu/u_csr/write_buffer_way[1]_i_18/I3
|
|
SLICE_X50Y46 LUT6 (Prop_lut6_I3_O) 0.124 9.846 r u_cpu/u_csr/write_buffer_way[1]_i_18/O
|
|
net (fo=1, routed) 0.000 9.846 u_cpu/u_csr/write_buffer_way[1]_i_18_n_0
|
|
SLICE_X50Y46 r u_cpu/u_csr/write_buffer_way_reg[1]_i_11/S[0]
|
|
SLICE_X50Y46 CARRY4 (Prop_carry4_S[0]_CO[3])
|
|
0.532 10.378 r u_cpu/u_csr/write_buffer_way_reg[1]_i_11/CO[3]
|
|
net (fo=1, routed) 0.000 10.378 u_cpu/u_csr/write_buffer_way_reg[1]_i_11_n_0
|
|
SLICE_X50Y47 r u_cpu/u_csr/write_buffer_way_reg[1]_i_9/CI
|
|
SLICE_X50Y47 CARRY4 (Prop_carry4_CI_CO[1])
|
|
0.157 10.535 f u_cpu/u_csr/write_buffer_way_reg[1]_i_9/CO[1]
|
|
net (fo=2, routed) 0.791 11.326 u_cpu/wb_stage/CO[0]
|
|
SLICE_X46Y39 f u_cpu/wb_stage/write_buffer_way[1]_i_5/I1
|
|
SLICE_X46Y39 LUT6 (Prop_lut6_I1_O) 0.329 11.655 r u_cpu/wb_stage/write_buffer_way[1]_i_5/O
|
|
net (fo=7, routed) 0.762 12.417 u_cpu/addr_trans/tlb_entry/sc_cancel_req
|
|
SLICE_X46Y35 r u_cpu/addr_trans/tlb_entry/main_state[0]_i_3/I1
|
|
SLICE_X46Y35 LUT3 (Prop_lut3_I1_O) 0.124 12.541 r u_cpu/addr_trans/tlb_entry/main_state[0]_i_3/O
|
|
net (fo=3, routed) 0.719 13.260 u_cpu/dcache/main_state_reg[0]_2
|
|
SLICE_X43Y31 r u_cpu/dcache/ds_to_es_bus_r[235]_i_10/I3
|
|
SLICE_X43Y31 LUT6 (Prop_lut6_I3_O) 0.124 13.384 r u_cpu/dcache/ds_to_es_bus_r[235]_i_10/O
|
|
net (fo=3, routed) 0.415 13.799 u_cpu/mem_stage/data_data_ok
|
|
SLICE_X43Y30 r u_cpu/mem_stage/flush_inst_req_buffer[1]_i_15/I0
|
|
SLICE_X43Y30 LUT3 (Prop_lut3_I0_O) 0.124 13.923 r u_cpu/mem_stage/flush_inst_req_buffer[1]_i_15/O
|
|
net (fo=2, routed) 0.833 14.756 u_cpu/mem_stage/es_to_ms_bus_r_reg[70]_1
|
|
SLICE_X48Y30 r u_cpu/mem_stage/flush_inst_req_buffer[1]_i_14/I0
|
|
SLICE_X48Y30 LUT6 (Prop_lut6_I0_O) 0.124 14.880 r u_cpu/mem_stage/flush_inst_req_buffer[1]_i_14/O
|
|
net (fo=1, routed) 0.651 15.532 u_cpu/mem_stage/ms_ready_go
|
|
SLICE_X48Y25 r u_cpu/mem_stage/flush_inst_req_buffer[1]_i_13/I4
|
|
SLICE_X48Y25 LUT6 (Prop_lut6_I4_O) 0.124 15.656 r u_cpu/mem_stage/flush_inst_req_buffer[1]_i_13/O
|
|
net (fo=3, routed) 0.483 16.139 u_cpu/id_stage/flush_inst_req_buffer[31]_i_6
|
|
SLICE_X50Y25 r u_cpu/id_stage/flush_inst_req_buffer[1]_i_9/I1
|
|
SLICE_X50Y25 LUT6 (Prop_lut6_I1_O) 0.124 16.263 r u_cpu/id_stage/flush_inst_req_buffer[1]_i_9/O
|
|
net (fo=32, routed) 0.531 16.794 u_cpu/if_stage/nextpc5
|
|
SLICE_X51Y27 r u_cpu/if_stage/fetch_pc_r[6]_i_4/I2
|
|
SLICE_X51Y27 LUT6 (Prop_lut6_I2_O) 0.124 16.918 r u_cpu/if_stage/fetch_pc_r[6]_i_4/O
|
|
net (fo=1, routed) 3.059 19.977 u_cpu/if_stage/fetch_pc_r[6]_i_4_n_0
|
|
SLICE_X114Y28 r u_cpu/if_stage/fetch_pc_r[6]_i_2/I2
|
|
SLICE_X114Y28 LUT6 (Prop_lut6_I2_O) 0.124 20.101 r u_cpu/if_stage/fetch_pc_r[6]_i_2/O
|
|
net (fo=1, routed) 0.441 20.542 u_cpu/if_stage/fetch_pc_r[6]_i_2_n_0
|
|
SLICE_X114Y25 r u_cpu/if_stage/fetch_pc_r[6]_i_1/I2
|
|
SLICE_X114Y25 LUT6 (Prop_lut6_I2_O) 0.124 20.666 r u_cpu/if_stage/fetch_pc_r[6]_i_1/O
|
|
net (fo=6, routed) 3.249 23.915 u_cpu/icache/tagv_ram_way[1].u/mem_reg_reg_2[2]
|
|
SLICE_X49Y33 r u_cpu/icache/tagv_ram_way[1].u/mem_reg_reg_i_8/I4
|
|
SLICE_X49Y33 LUT5 (Prop_lut5_I4_O) 0.124 24.039 r u_cpu/icache/tagv_ram_way[1].u/mem_reg_reg_i_8/O
|
|
net (fo=16, routed) 1.477 25.516 u_cpu/icache/data_ram_way[0].data_ram_bank[3].u/ADDRBWRADDR[2]
|
|
RAMB18_X2Y3 RAMB18E1 r u_cpu/icache/data_ram_way[0].data_ram_bank[3].u/mem_reg_reg/ADDRBWRADDR[7]
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock cpu_clk rise edge) 30.323 30.323 r
|
|
clock source latency -5.674 24.648
|
|
propagated clock network latency
|
|
3.782 28.430
|
|
clock pessimism -0.418 28.012
|
|
clock uncertainty -0.074 27.938
|
|
RAMB18_X2Y3 RAMB18E1 (Setup_ramb18e1_CLKBWRCLK_ADDRBWRADDR[7])
|
|
-0.566 27.372 u_cpu/icache/data_ram_way[0].data_ram_bank[3].u/mem_reg_reg
|
|
-------------------------------------------------------------------
|
|
required time 27.372
|
|
arrival time -25.516
|
|
-------------------------------------------------------------------
|
|
slack 1.856
|
|
|
|
Slack (MET) : 1.856ns (required time - arrival time)
|
|
Source: u_cpu/addr_trans/data_vaddr_buffer_reg[14]/C
|
|
(rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns})
|
|
Destination: u_cpu/icache/data_ram_way[0].data_ram_bank[3].u/mem_reg_reg/ADDRBWRADDR[7]
|
|
(rising edge-triggered cell RAMB18E1 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns})
|
|
Path Group: cpu_clk
|
|
Path Type: Setup (Max at Slow Process Corner)
|
|
Requirement: 30.323ns (cpu_clk rise@30.323ns - cpu_clk rise@0.000ns)
|
|
Data Path Delay: 27.741ns (logic 5.333ns (19.224%) route 22.408ns (80.776%))
|
|
Logic Levels: 26 (CARRY4=4 LUT3=2 LUT4=1 LUT5=2 LUT6=15 MUXF7=1 MUXF8=1)
|
|
Clock Path Skew: -0.086ns (DCD - SCD + CPR)
|
|
Destination Clock Delay (DCD): -1.892ns = ( 28.430 - 30.323 )
|
|
Source Clock Delay (SCD): -2.225ns
|
|
Clock Pessimism Removal (CPR): -0.418ns
|
|
Clock Uncertainty: 0.074ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Discrete Jitter (DJ): 0.130ns
|
|
Phase Error (PE): 0.000ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock cpu_clk rise edge) 0.000 0.000 r
|
|
clock source latency -6.275 -6.275
|
|
propagated clock network latency
|
|
4.051 -2.225
|
|
SLICE_X35Y35 FDRE 0.000 -2.225 r u_cpu/addr_trans/data_vaddr_buffer_reg[14]/C
|
|
SLICE_X35Y35 FDRE (Prop_fdre_C_Q) 0.456 -1.769 r u_cpu/addr_trans/data_vaddr_buffer_reg[14]/Q
|
|
net (fo=33, routed) 1.442 -0.326 u_cpu/addr_trans/tlb_entry/data_vaddr_buffer[2]
|
|
SLICE_X42Y40 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_226/I5
|
|
SLICE_X42Y40 LUT6 (Prop_lut6_I5_O) 0.124 -0.202 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_226/O
|
|
net (fo=1, routed) 0.000 -0.202 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_226_n_0
|
|
SLICE_X42Y40 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_111/S[0]
|
|
SLICE_X42Y40 CARRY4 (Prop_carry4_S[0]_CO[3])
|
|
0.513 0.311 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_111/CO[3]
|
|
net (fo=1, routed) 0.000 0.311 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_111_n_0
|
|
SLICE_X42Y41 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_32/CI
|
|
SLICE_X42Y41 CARRY4 (Prop_carry4_CI_CO[2])
|
|
0.229 0.540 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_32/CO[2]
|
|
net (fo=1, routed) 1.009 1.549 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_32_n_1
|
|
SLICE_X40Y47 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_9/I1
|
|
SLICE_X40Y47 LUT6 (Prop_lut6_I1_O) 0.310 1.859 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_9/O
|
|
net (fo=2, routed) 0.635 2.494 u_cpu/addr_trans/tlb_entry/match1[28]
|
|
SLICE_X38Y47 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/I2
|
|
SLICE_X38Y47 LUT4 (Prop_lut4_I2_O) 0.124 2.618 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/O
|
|
net (fo=2, routed) 0.667 3.285 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2_n_0
|
|
SLICE_X39Y47 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/I0
|
|
SLICE_X39Y47 LUT5 (Prop_lut5_I0_O) 0.124 3.409 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/O
|
|
net (fo=2, routed) 1.103 4.512 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2_n_0
|
|
SLICE_X38Y50 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/I0
|
|
SLICE_X38Y50 LUT6 (Prop_lut6_I0_O) 0.124 4.636 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/O
|
|
net (fo=89, routed) 1.162 5.797 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus[8]
|
|
SLICE_X42Y51 r u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_38__0/S
|
|
SLICE_X42Y51 MUXF7 (Prop_muxf7_S_O) 0.292 6.089 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_38__0/O
|
|
net (fo=1, routed) 0.000 6.089 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_38__0_n_0
|
|
SLICE_X42Y51 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_16__0/I1
|
|
SLICE_X42Y51 MUXF8 (Prop_muxf8_I1_O) 0.088 6.177 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_16__0/O
|
|
net (fo=1, routed) 0.957 7.134 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_16__0_n_0
|
|
SLICE_X42Y50 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7/I0
|
|
SLICE_X42Y50 LUT6 (Prop_lut6_I0_O) 0.319 7.453 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7/O
|
|
net (fo=1, routed) 0.435 7.888 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7_n_0
|
|
SLICE_X44Y50 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0/I5
|
|
SLICE_X44Y50 LUT6 (Prop_lut6_I5_O) 0.124 8.012 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0/O
|
|
net (fo=10, routed) 0.740 8.753 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0_n_0
|
|
SLICE_X44Y50 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[5]_i_1__0/I3
|
|
SLICE_X44Y50 LUT6 (Prop_lut6_I3_O) 0.124 8.877 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[5]_i_1__0/O
|
|
net (fo=6, routed) 0.845 9.722 u_cpu/u_csr/ms_to_ws_bus[13]
|
|
SLICE_X50Y46 f u_cpu/u_csr/write_buffer_way[1]_i_18/I3
|
|
SLICE_X50Y46 LUT6 (Prop_lut6_I3_O) 0.124 9.846 r u_cpu/u_csr/write_buffer_way[1]_i_18/O
|
|
net (fo=1, routed) 0.000 9.846 u_cpu/u_csr/write_buffer_way[1]_i_18_n_0
|
|
SLICE_X50Y46 r u_cpu/u_csr/write_buffer_way_reg[1]_i_11/S[0]
|
|
SLICE_X50Y46 CARRY4 (Prop_carry4_S[0]_CO[3])
|
|
0.532 10.378 r u_cpu/u_csr/write_buffer_way_reg[1]_i_11/CO[3]
|
|
net (fo=1, routed) 0.000 10.378 u_cpu/u_csr/write_buffer_way_reg[1]_i_11_n_0
|
|
SLICE_X50Y47 r u_cpu/u_csr/write_buffer_way_reg[1]_i_9/CI
|
|
SLICE_X50Y47 CARRY4 (Prop_carry4_CI_CO[1])
|
|
0.157 10.535 f u_cpu/u_csr/write_buffer_way_reg[1]_i_9/CO[1]
|
|
net (fo=2, routed) 0.791 11.326 u_cpu/wb_stage/CO[0]
|
|
SLICE_X46Y39 f u_cpu/wb_stage/write_buffer_way[1]_i_5/I1
|
|
SLICE_X46Y39 LUT6 (Prop_lut6_I1_O) 0.329 11.655 r u_cpu/wb_stage/write_buffer_way[1]_i_5/O
|
|
net (fo=7, routed) 0.762 12.417 u_cpu/addr_trans/tlb_entry/sc_cancel_req
|
|
SLICE_X46Y35 r u_cpu/addr_trans/tlb_entry/main_state[0]_i_3/I1
|
|
SLICE_X46Y35 LUT3 (Prop_lut3_I1_O) 0.124 12.541 r u_cpu/addr_trans/tlb_entry/main_state[0]_i_3/O
|
|
net (fo=3, routed) 0.719 13.260 u_cpu/dcache/main_state_reg[0]_2
|
|
SLICE_X43Y31 r u_cpu/dcache/ds_to_es_bus_r[235]_i_10/I3
|
|
SLICE_X43Y31 LUT6 (Prop_lut6_I3_O) 0.124 13.384 r u_cpu/dcache/ds_to_es_bus_r[235]_i_10/O
|
|
net (fo=3, routed) 0.415 13.799 u_cpu/mem_stage/data_data_ok
|
|
SLICE_X43Y30 r u_cpu/mem_stage/flush_inst_req_buffer[1]_i_15/I0
|
|
SLICE_X43Y30 LUT3 (Prop_lut3_I0_O) 0.124 13.923 r u_cpu/mem_stage/flush_inst_req_buffer[1]_i_15/O
|
|
net (fo=2, routed) 0.833 14.756 u_cpu/mem_stage/es_to_ms_bus_r_reg[70]_1
|
|
SLICE_X48Y30 r u_cpu/mem_stage/flush_inst_req_buffer[1]_i_14/I0
|
|
SLICE_X48Y30 LUT6 (Prop_lut6_I0_O) 0.124 14.880 r u_cpu/mem_stage/flush_inst_req_buffer[1]_i_14/O
|
|
net (fo=1, routed) 0.651 15.532 u_cpu/mem_stage/ms_ready_go
|
|
SLICE_X48Y25 r u_cpu/mem_stage/flush_inst_req_buffer[1]_i_13/I4
|
|
SLICE_X48Y25 LUT6 (Prop_lut6_I4_O) 0.124 15.656 r u_cpu/mem_stage/flush_inst_req_buffer[1]_i_13/O
|
|
net (fo=3, routed) 0.483 16.139 u_cpu/id_stage/flush_inst_req_buffer[31]_i_6
|
|
SLICE_X50Y25 r u_cpu/id_stage/flush_inst_req_buffer[1]_i_9/I1
|
|
SLICE_X50Y25 LUT6 (Prop_lut6_I1_O) 0.124 16.263 r u_cpu/id_stage/flush_inst_req_buffer[1]_i_9/O
|
|
net (fo=32, routed) 0.531 16.794 u_cpu/if_stage/nextpc5
|
|
SLICE_X51Y27 r u_cpu/if_stage/fetch_pc_r[6]_i_4/I2
|
|
SLICE_X51Y27 LUT6 (Prop_lut6_I2_O) 0.124 16.918 r u_cpu/if_stage/fetch_pc_r[6]_i_4/O
|
|
net (fo=1, routed) 3.059 19.977 u_cpu/if_stage/fetch_pc_r[6]_i_4_n_0
|
|
SLICE_X114Y28 r u_cpu/if_stage/fetch_pc_r[6]_i_2/I2
|
|
SLICE_X114Y28 LUT6 (Prop_lut6_I2_O) 0.124 20.101 r u_cpu/if_stage/fetch_pc_r[6]_i_2/O
|
|
net (fo=1, routed) 0.441 20.542 u_cpu/if_stage/fetch_pc_r[6]_i_2_n_0
|
|
SLICE_X114Y25 r u_cpu/if_stage/fetch_pc_r[6]_i_1/I2
|
|
SLICE_X114Y25 LUT6 (Prop_lut6_I2_O) 0.124 20.666 r u_cpu/if_stage/fetch_pc_r[6]_i_1/O
|
|
net (fo=6, routed) 3.249 23.915 u_cpu/icache/tagv_ram_way[1].u/mem_reg_reg_2[2]
|
|
SLICE_X49Y33 r u_cpu/icache/tagv_ram_way[1].u/mem_reg_reg_i_8/I4
|
|
SLICE_X49Y33 LUT5 (Prop_lut5_I4_O) 0.124 24.039 r u_cpu/icache/tagv_ram_way[1].u/mem_reg_reg_i_8/O
|
|
net (fo=16, routed) 1.477 25.516 u_cpu/icache/data_ram_way[0].data_ram_bank[3].u/ADDRBWRADDR[2]
|
|
RAMB18_X2Y3 RAMB18E1 r u_cpu/icache/data_ram_way[0].data_ram_bank[3].u/mem_reg_reg/ADDRBWRADDR[7]
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock cpu_clk rise edge) 30.323 30.323 r
|
|
clock source latency -5.674 24.648
|
|
propagated clock network latency
|
|
3.782 28.430
|
|
clock pessimism -0.418 28.012
|
|
clock uncertainty -0.074 27.938
|
|
RAMB18_X2Y3 RAMB18E1 (Setup_ramb18e1_CLKBWRCLK_ADDRBWRADDR[7])
|
|
-0.566 27.372 u_cpu/icache/data_ram_way[0].data_ram_bank[3].u/mem_reg_reg
|
|
-------------------------------------------------------------------
|
|
required time 27.372
|
|
arrival time -25.516
|
|
-------------------------------------------------------------------
|
|
slack 1.856
|
|
|
|
Slack (MET) : 1.856ns (required time - arrival time)
|
|
Source: u_cpu/addr_trans/data_vaddr_buffer_reg[14]/C
|
|
(rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns})
|
|
Destination: u_cpu/icache/data_ram_way[0].data_ram_bank[3].u/mem_reg_reg/ADDRBWRADDR[7]
|
|
(rising edge-triggered cell RAMB18E1 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns})
|
|
Path Group: cpu_clk
|
|
Path Type: Setup (Max at Slow Process Corner)
|
|
Requirement: 30.323ns (cpu_clk rise@30.323ns - cpu_clk rise@0.000ns)
|
|
Data Path Delay: 27.741ns (logic 5.333ns (19.224%) route 22.408ns (80.776%))
|
|
Logic Levels: 26 (CARRY4=4 LUT3=2 LUT4=1 LUT5=2 LUT6=15 MUXF7=1 MUXF8=1)
|
|
Clock Path Skew: -0.086ns (DCD - SCD + CPR)
|
|
Destination Clock Delay (DCD): -1.892ns = ( 28.430 - 30.323 )
|
|
Source Clock Delay (SCD): -2.225ns
|
|
Clock Pessimism Removal (CPR): -0.418ns
|
|
Clock Uncertainty: 0.074ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Discrete Jitter (DJ): 0.130ns
|
|
Phase Error (PE): 0.000ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock cpu_clk rise edge) 0.000 0.000 r
|
|
clock source latency -6.275 -6.275
|
|
propagated clock network latency
|
|
4.051 -2.225
|
|
SLICE_X35Y35 FDRE 0.000 -2.225 r u_cpu/addr_trans/data_vaddr_buffer_reg[14]/C
|
|
SLICE_X35Y35 FDRE (Prop_fdre_C_Q) 0.456 -1.769 r u_cpu/addr_trans/data_vaddr_buffer_reg[14]/Q
|
|
net (fo=33, routed) 1.442 -0.326 u_cpu/addr_trans/tlb_entry/data_vaddr_buffer[2]
|
|
SLICE_X42Y40 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_226/I5
|
|
SLICE_X42Y40 LUT6 (Prop_lut6_I5_O) 0.124 -0.202 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_226/O
|
|
net (fo=1, routed) 0.000 -0.202 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_226_n_0
|
|
SLICE_X42Y40 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_111/S[0]
|
|
SLICE_X42Y40 CARRY4 (Prop_carry4_S[0]_CO[3])
|
|
0.513 0.311 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_111/CO[3]
|
|
net (fo=1, routed) 0.000 0.311 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_111_n_0
|
|
SLICE_X42Y41 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_32/CI
|
|
SLICE_X42Y41 CARRY4 (Prop_carry4_CI_CO[2])
|
|
0.229 0.540 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_32/CO[2]
|
|
net (fo=1, routed) 1.009 1.549 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_32_n_1
|
|
SLICE_X40Y47 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_9/I1
|
|
SLICE_X40Y47 LUT6 (Prop_lut6_I1_O) 0.310 1.859 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_9/O
|
|
net (fo=2, routed) 0.635 2.494 u_cpu/addr_trans/tlb_entry/match1[28]
|
|
SLICE_X38Y47 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/I2
|
|
SLICE_X38Y47 LUT4 (Prop_lut4_I2_O) 0.124 2.618 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/O
|
|
net (fo=2, routed) 0.667 3.285 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2_n_0
|
|
SLICE_X39Y47 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/I0
|
|
SLICE_X39Y47 LUT5 (Prop_lut5_I0_O) 0.124 3.409 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/O
|
|
net (fo=2, routed) 1.103 4.512 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2_n_0
|
|
SLICE_X38Y50 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/I0
|
|
SLICE_X38Y50 LUT6 (Prop_lut6_I0_O) 0.124 4.636 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/O
|
|
net (fo=89, routed) 1.162 5.797 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus[8]
|
|
SLICE_X42Y51 r u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_38__0/S
|
|
SLICE_X42Y51 MUXF7 (Prop_muxf7_S_O) 0.292 6.089 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_38__0/O
|
|
net (fo=1, routed) 0.000 6.089 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_38__0_n_0
|
|
SLICE_X42Y51 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_16__0/I1
|
|
SLICE_X42Y51 MUXF8 (Prop_muxf8_I1_O) 0.088 6.177 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_16__0/O
|
|
net (fo=1, routed) 0.957 7.134 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_16__0_n_0
|
|
SLICE_X42Y50 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7/I0
|
|
SLICE_X42Y50 LUT6 (Prop_lut6_I0_O) 0.319 7.453 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7/O
|
|
net (fo=1, routed) 0.435 7.888 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7_n_0
|
|
SLICE_X44Y50 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0/I5
|
|
SLICE_X44Y50 LUT6 (Prop_lut6_I5_O) 0.124 8.012 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0/O
|
|
net (fo=10, routed) 0.740 8.753 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0_n_0
|
|
SLICE_X44Y50 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[5]_i_1__0/I3
|
|
SLICE_X44Y50 LUT6 (Prop_lut6_I3_O) 0.124 8.877 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[5]_i_1__0/O
|
|
net (fo=6, routed) 0.845 9.722 u_cpu/u_csr/ms_to_ws_bus[13]
|
|
SLICE_X50Y46 r u_cpu/u_csr/write_buffer_way[1]_i_18/I3
|
|
SLICE_X50Y46 LUT6 (Prop_lut6_I3_O) 0.124 9.846 f u_cpu/u_csr/write_buffer_way[1]_i_18/O
|
|
net (fo=1, routed) 0.000 9.846 u_cpu/u_csr/write_buffer_way[1]_i_18_n_0
|
|
SLICE_X50Y46 f u_cpu/u_csr/write_buffer_way_reg[1]_i_11/S[0]
|
|
SLICE_X50Y46 CARRY4 (Prop_carry4_S[0]_CO[3])
|
|
0.532 10.378 r u_cpu/u_csr/write_buffer_way_reg[1]_i_11/CO[3]
|
|
net (fo=1, routed) 0.000 10.378 u_cpu/u_csr/write_buffer_way_reg[1]_i_11_n_0
|
|
SLICE_X50Y47 r u_cpu/u_csr/write_buffer_way_reg[1]_i_9/CI
|
|
SLICE_X50Y47 CARRY4 (Prop_carry4_CI_CO[1])
|
|
0.157 10.535 f u_cpu/u_csr/write_buffer_way_reg[1]_i_9/CO[1]
|
|
net (fo=2, routed) 0.791 11.326 u_cpu/wb_stage/CO[0]
|
|
SLICE_X46Y39 f u_cpu/wb_stage/write_buffer_way[1]_i_5/I1
|
|
SLICE_X46Y39 LUT6 (Prop_lut6_I1_O) 0.329 11.655 r u_cpu/wb_stage/write_buffer_way[1]_i_5/O
|
|
net (fo=7, routed) 0.762 12.417 u_cpu/addr_trans/tlb_entry/sc_cancel_req
|
|
SLICE_X46Y35 r u_cpu/addr_trans/tlb_entry/main_state[0]_i_3/I1
|
|
SLICE_X46Y35 LUT3 (Prop_lut3_I1_O) 0.124 12.541 r u_cpu/addr_trans/tlb_entry/main_state[0]_i_3/O
|
|
net (fo=3, routed) 0.719 13.260 u_cpu/dcache/main_state_reg[0]_2
|
|
SLICE_X43Y31 r u_cpu/dcache/ds_to_es_bus_r[235]_i_10/I3
|
|
SLICE_X43Y31 LUT6 (Prop_lut6_I3_O) 0.124 13.384 r u_cpu/dcache/ds_to_es_bus_r[235]_i_10/O
|
|
net (fo=3, routed) 0.415 13.799 u_cpu/mem_stage/data_data_ok
|
|
SLICE_X43Y30 r u_cpu/mem_stage/flush_inst_req_buffer[1]_i_15/I0
|
|
SLICE_X43Y30 LUT3 (Prop_lut3_I0_O) 0.124 13.923 r u_cpu/mem_stage/flush_inst_req_buffer[1]_i_15/O
|
|
net (fo=2, routed) 0.833 14.756 u_cpu/mem_stage/es_to_ms_bus_r_reg[70]_1
|
|
SLICE_X48Y30 r u_cpu/mem_stage/flush_inst_req_buffer[1]_i_14/I0
|
|
SLICE_X48Y30 LUT6 (Prop_lut6_I0_O) 0.124 14.880 r u_cpu/mem_stage/flush_inst_req_buffer[1]_i_14/O
|
|
net (fo=1, routed) 0.651 15.532 u_cpu/mem_stage/ms_ready_go
|
|
SLICE_X48Y25 r u_cpu/mem_stage/flush_inst_req_buffer[1]_i_13/I4
|
|
SLICE_X48Y25 LUT6 (Prop_lut6_I4_O) 0.124 15.656 r u_cpu/mem_stage/flush_inst_req_buffer[1]_i_13/O
|
|
net (fo=3, routed) 0.483 16.139 u_cpu/id_stage/flush_inst_req_buffer[31]_i_6
|
|
SLICE_X50Y25 r u_cpu/id_stage/flush_inst_req_buffer[1]_i_9/I1
|
|
SLICE_X50Y25 LUT6 (Prop_lut6_I1_O) 0.124 16.263 r u_cpu/id_stage/flush_inst_req_buffer[1]_i_9/O
|
|
net (fo=32, routed) 0.531 16.794 u_cpu/if_stage/nextpc5
|
|
SLICE_X51Y27 r u_cpu/if_stage/fetch_pc_r[6]_i_4/I2
|
|
SLICE_X51Y27 LUT6 (Prop_lut6_I2_O) 0.124 16.918 r u_cpu/if_stage/fetch_pc_r[6]_i_4/O
|
|
net (fo=1, routed) 3.059 19.977 u_cpu/if_stage/fetch_pc_r[6]_i_4_n_0
|
|
SLICE_X114Y28 r u_cpu/if_stage/fetch_pc_r[6]_i_2/I2
|
|
SLICE_X114Y28 LUT6 (Prop_lut6_I2_O) 0.124 20.101 r u_cpu/if_stage/fetch_pc_r[6]_i_2/O
|
|
net (fo=1, routed) 0.441 20.542 u_cpu/if_stage/fetch_pc_r[6]_i_2_n_0
|
|
SLICE_X114Y25 r u_cpu/if_stage/fetch_pc_r[6]_i_1/I2
|
|
SLICE_X114Y25 LUT6 (Prop_lut6_I2_O) 0.124 20.666 r u_cpu/if_stage/fetch_pc_r[6]_i_1/O
|
|
net (fo=6, routed) 3.249 23.915 u_cpu/icache/tagv_ram_way[1].u/mem_reg_reg_2[2]
|
|
SLICE_X49Y33 r u_cpu/icache/tagv_ram_way[1].u/mem_reg_reg_i_8/I4
|
|
SLICE_X49Y33 LUT5 (Prop_lut5_I4_O) 0.124 24.039 r u_cpu/icache/tagv_ram_way[1].u/mem_reg_reg_i_8/O
|
|
net (fo=16, routed) 1.477 25.516 u_cpu/icache/data_ram_way[0].data_ram_bank[3].u/ADDRBWRADDR[2]
|
|
RAMB18_X2Y3 RAMB18E1 r u_cpu/icache/data_ram_way[0].data_ram_bank[3].u/mem_reg_reg/ADDRBWRADDR[7]
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock cpu_clk rise edge) 30.323 30.323 r
|
|
clock source latency -5.674 24.648
|
|
propagated clock network latency
|
|
3.782 28.430
|
|
clock pessimism -0.418 28.012
|
|
clock uncertainty -0.074 27.938
|
|
RAMB18_X2Y3 RAMB18E1 (Setup_ramb18e1_CLKBWRCLK_ADDRBWRADDR[7])
|
|
-0.566 27.372 u_cpu/icache/data_ram_way[0].data_ram_bank[3].u/mem_reg_reg
|
|
-------------------------------------------------------------------
|
|
required time 27.372
|
|
arrival time -25.516
|
|
-------------------------------------------------------------------
|
|
slack 1.856
|
|
|
|
Slack (MET) : 1.856ns (required time - arrival time)
|
|
Source: u_cpu/addr_trans/data_vaddr_buffer_reg[14]/C
|
|
(rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns})
|
|
Destination: u_cpu/icache/data_ram_way[0].data_ram_bank[3].u/mem_reg_reg/ADDRBWRADDR[7]
|
|
(rising edge-triggered cell RAMB18E1 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns})
|
|
Path Group: cpu_clk
|
|
Path Type: Setup (Max at Slow Process Corner)
|
|
Requirement: 30.323ns (cpu_clk rise@30.323ns - cpu_clk rise@0.000ns)
|
|
Data Path Delay: 27.741ns (logic 5.333ns (19.224%) route 22.408ns (80.776%))
|
|
Logic Levels: 26 (CARRY4=4 LUT3=2 LUT4=1 LUT5=2 LUT6=15 MUXF7=1 MUXF8=1)
|
|
Clock Path Skew: -0.086ns (DCD - SCD + CPR)
|
|
Destination Clock Delay (DCD): -1.892ns = ( 28.430 - 30.323 )
|
|
Source Clock Delay (SCD): -2.225ns
|
|
Clock Pessimism Removal (CPR): -0.418ns
|
|
Clock Uncertainty: 0.074ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Discrete Jitter (DJ): 0.130ns
|
|
Phase Error (PE): 0.000ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock cpu_clk rise edge) 0.000 0.000 r
|
|
clock source latency -6.275 -6.275
|
|
propagated clock network latency
|
|
4.051 -2.225
|
|
SLICE_X35Y35 FDRE 0.000 -2.225 r u_cpu/addr_trans/data_vaddr_buffer_reg[14]/C
|
|
SLICE_X35Y35 FDRE (Prop_fdre_C_Q) 0.456 -1.769 r u_cpu/addr_trans/data_vaddr_buffer_reg[14]/Q
|
|
net (fo=33, routed) 1.442 -0.326 u_cpu/addr_trans/tlb_entry/data_vaddr_buffer[2]
|
|
SLICE_X42Y40 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_226/I5
|
|
SLICE_X42Y40 LUT6 (Prop_lut6_I5_O) 0.124 -0.202 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_226/O
|
|
net (fo=1, routed) 0.000 -0.202 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_226_n_0
|
|
SLICE_X42Y40 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_111/S[0]
|
|
SLICE_X42Y40 CARRY4 (Prop_carry4_S[0]_CO[3])
|
|
0.513 0.311 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_111/CO[3]
|
|
net (fo=1, routed) 0.000 0.311 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_111_n_0
|
|
SLICE_X42Y41 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_32/CI
|
|
SLICE_X42Y41 CARRY4 (Prop_carry4_CI_CO[2])
|
|
0.229 0.540 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_32/CO[2]
|
|
net (fo=1, routed) 1.009 1.549 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_32_n_1
|
|
SLICE_X40Y47 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_9/I1
|
|
SLICE_X40Y47 LUT6 (Prop_lut6_I1_O) 0.310 1.859 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_9/O
|
|
net (fo=2, routed) 0.635 2.494 u_cpu/addr_trans/tlb_entry/match1[28]
|
|
SLICE_X38Y47 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/I2
|
|
SLICE_X38Y47 LUT4 (Prop_lut4_I2_O) 0.124 2.618 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/O
|
|
net (fo=2, routed) 0.667 3.285 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2_n_0
|
|
SLICE_X39Y47 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/I0
|
|
SLICE_X39Y47 LUT5 (Prop_lut5_I0_O) 0.124 3.409 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/O
|
|
net (fo=2, routed) 1.103 4.512 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2_n_0
|
|
SLICE_X38Y50 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/I0
|
|
SLICE_X38Y50 LUT6 (Prop_lut6_I0_O) 0.124 4.636 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/O
|
|
net (fo=89, routed) 1.162 5.797 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus[8]
|
|
SLICE_X42Y51 r u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_38__0/S
|
|
SLICE_X42Y51 MUXF7 (Prop_muxf7_S_O) 0.292 6.089 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_38__0/O
|
|
net (fo=1, routed) 0.000 6.089 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_38__0_n_0
|
|
SLICE_X42Y51 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_16__0/I1
|
|
SLICE_X42Y51 MUXF8 (Prop_muxf8_I1_O) 0.088 6.177 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_16__0/O
|
|
net (fo=1, routed) 0.957 7.134 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_16__0_n_0
|
|
SLICE_X42Y50 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7/I0
|
|
SLICE_X42Y50 LUT6 (Prop_lut6_I0_O) 0.319 7.453 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7/O
|
|
net (fo=1, routed) 0.435 7.888 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7_n_0
|
|
SLICE_X44Y50 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0/I5
|
|
SLICE_X44Y50 LUT6 (Prop_lut6_I5_O) 0.124 8.012 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0/O
|
|
net (fo=10, routed) 0.740 8.753 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0_n_0
|
|
SLICE_X44Y50 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[5]_i_1__0/I3
|
|
SLICE_X44Y50 LUT6 (Prop_lut6_I3_O) 0.124 8.877 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[5]_i_1__0/O
|
|
net (fo=6, routed) 0.845 9.722 u_cpu/u_csr/ms_to_ws_bus[13]
|
|
SLICE_X50Y46 f u_cpu/u_csr/write_buffer_way[1]_i_18/I3
|
|
SLICE_X50Y46 LUT6 (Prop_lut6_I3_O) 0.124 9.846 f u_cpu/u_csr/write_buffer_way[1]_i_18/O
|
|
net (fo=1, routed) 0.000 9.846 u_cpu/u_csr/write_buffer_way[1]_i_18_n_0
|
|
SLICE_X50Y46 f u_cpu/u_csr/write_buffer_way_reg[1]_i_11/S[0]
|
|
SLICE_X50Y46 CARRY4 (Prop_carry4_S[0]_CO[3])
|
|
0.532 10.378 r u_cpu/u_csr/write_buffer_way_reg[1]_i_11/CO[3]
|
|
net (fo=1, routed) 0.000 10.378 u_cpu/u_csr/write_buffer_way_reg[1]_i_11_n_0
|
|
SLICE_X50Y47 r u_cpu/u_csr/write_buffer_way_reg[1]_i_9/CI
|
|
SLICE_X50Y47 CARRY4 (Prop_carry4_CI_CO[1])
|
|
0.157 10.535 f u_cpu/u_csr/write_buffer_way_reg[1]_i_9/CO[1]
|
|
net (fo=2, routed) 0.791 11.326 u_cpu/wb_stage/CO[0]
|
|
SLICE_X46Y39 f u_cpu/wb_stage/write_buffer_way[1]_i_5/I1
|
|
SLICE_X46Y39 LUT6 (Prop_lut6_I1_O) 0.329 11.655 r u_cpu/wb_stage/write_buffer_way[1]_i_5/O
|
|
net (fo=7, routed) 0.762 12.417 u_cpu/addr_trans/tlb_entry/sc_cancel_req
|
|
SLICE_X46Y35 r u_cpu/addr_trans/tlb_entry/main_state[0]_i_3/I1
|
|
SLICE_X46Y35 LUT3 (Prop_lut3_I1_O) 0.124 12.541 r u_cpu/addr_trans/tlb_entry/main_state[0]_i_3/O
|
|
net (fo=3, routed) 0.719 13.260 u_cpu/dcache/main_state_reg[0]_2
|
|
SLICE_X43Y31 r u_cpu/dcache/ds_to_es_bus_r[235]_i_10/I3
|
|
SLICE_X43Y31 LUT6 (Prop_lut6_I3_O) 0.124 13.384 r u_cpu/dcache/ds_to_es_bus_r[235]_i_10/O
|
|
net (fo=3, routed) 0.415 13.799 u_cpu/mem_stage/data_data_ok
|
|
SLICE_X43Y30 r u_cpu/mem_stage/flush_inst_req_buffer[1]_i_15/I0
|
|
SLICE_X43Y30 LUT3 (Prop_lut3_I0_O) 0.124 13.923 r u_cpu/mem_stage/flush_inst_req_buffer[1]_i_15/O
|
|
net (fo=2, routed) 0.833 14.756 u_cpu/mem_stage/es_to_ms_bus_r_reg[70]_1
|
|
SLICE_X48Y30 r u_cpu/mem_stage/flush_inst_req_buffer[1]_i_14/I0
|
|
SLICE_X48Y30 LUT6 (Prop_lut6_I0_O) 0.124 14.880 r u_cpu/mem_stage/flush_inst_req_buffer[1]_i_14/O
|
|
net (fo=1, routed) 0.651 15.532 u_cpu/mem_stage/ms_ready_go
|
|
SLICE_X48Y25 r u_cpu/mem_stage/flush_inst_req_buffer[1]_i_13/I4
|
|
SLICE_X48Y25 LUT6 (Prop_lut6_I4_O) 0.124 15.656 r u_cpu/mem_stage/flush_inst_req_buffer[1]_i_13/O
|
|
net (fo=3, routed) 0.483 16.139 u_cpu/id_stage/flush_inst_req_buffer[31]_i_6
|
|
SLICE_X50Y25 r u_cpu/id_stage/flush_inst_req_buffer[1]_i_9/I1
|
|
SLICE_X50Y25 LUT6 (Prop_lut6_I1_O) 0.124 16.263 r u_cpu/id_stage/flush_inst_req_buffer[1]_i_9/O
|
|
net (fo=32, routed) 0.531 16.794 u_cpu/if_stage/nextpc5
|
|
SLICE_X51Y27 r u_cpu/if_stage/fetch_pc_r[6]_i_4/I2
|
|
SLICE_X51Y27 LUT6 (Prop_lut6_I2_O) 0.124 16.918 r u_cpu/if_stage/fetch_pc_r[6]_i_4/O
|
|
net (fo=1, routed) 3.059 19.977 u_cpu/if_stage/fetch_pc_r[6]_i_4_n_0
|
|
SLICE_X114Y28 r u_cpu/if_stage/fetch_pc_r[6]_i_2/I2
|
|
SLICE_X114Y28 LUT6 (Prop_lut6_I2_O) 0.124 20.101 r u_cpu/if_stage/fetch_pc_r[6]_i_2/O
|
|
net (fo=1, routed) 0.441 20.542 u_cpu/if_stage/fetch_pc_r[6]_i_2_n_0
|
|
SLICE_X114Y25 r u_cpu/if_stage/fetch_pc_r[6]_i_1/I2
|
|
SLICE_X114Y25 LUT6 (Prop_lut6_I2_O) 0.124 20.666 r u_cpu/if_stage/fetch_pc_r[6]_i_1/O
|
|
net (fo=6, routed) 3.249 23.915 u_cpu/icache/tagv_ram_way[1].u/mem_reg_reg_2[2]
|
|
SLICE_X49Y33 r u_cpu/icache/tagv_ram_way[1].u/mem_reg_reg_i_8/I4
|
|
SLICE_X49Y33 LUT5 (Prop_lut5_I4_O) 0.124 24.039 r u_cpu/icache/tagv_ram_way[1].u/mem_reg_reg_i_8/O
|
|
net (fo=16, routed) 1.477 25.516 u_cpu/icache/data_ram_way[0].data_ram_bank[3].u/ADDRBWRADDR[2]
|
|
RAMB18_X2Y3 RAMB18E1 r u_cpu/icache/data_ram_way[0].data_ram_bank[3].u/mem_reg_reg/ADDRBWRADDR[7]
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock cpu_clk rise edge) 30.323 30.323 r
|
|
clock source latency -5.674 24.648
|
|
propagated clock network latency
|
|
3.782 28.430
|
|
clock pessimism -0.418 28.012
|
|
clock uncertainty -0.074 27.938
|
|
RAMB18_X2Y3 RAMB18E1 (Setup_ramb18e1_CLKBWRCLK_ADDRBWRADDR[7])
|
|
-0.566 27.372 u_cpu/icache/data_ram_way[0].data_ram_bank[3].u/mem_reg_reg
|
|
-------------------------------------------------------------------
|
|
required time 27.372
|
|
arrival time -25.516
|
|
-------------------------------------------------------------------
|
|
slack 1.856
|
|
|
|
Slack (MET) : 1.856ns (required time - arrival time)
|
|
Source: u_cpu/addr_trans/data_vaddr_buffer_reg[14]/C
|
|
(rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns})
|
|
Destination: u_cpu/icache/data_ram_way[0].data_ram_bank[3].u/mem_reg_reg/ADDRBWRADDR[7]
|
|
(rising edge-triggered cell RAMB18E1 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns})
|
|
Path Group: cpu_clk
|
|
Path Type: Setup (Max at Slow Process Corner)
|
|
Requirement: 30.323ns (cpu_clk rise@30.323ns - cpu_clk rise@0.000ns)
|
|
Data Path Delay: 27.741ns (logic 5.333ns (19.224%) route 22.408ns (80.776%))
|
|
Logic Levels: 26 (CARRY4=4 LUT3=2 LUT4=1 LUT5=2 LUT6=15 MUXF7=1 MUXF8=1)
|
|
Clock Path Skew: -0.086ns (DCD - SCD + CPR)
|
|
Destination Clock Delay (DCD): -1.892ns = ( 28.430 - 30.323 )
|
|
Source Clock Delay (SCD): -2.225ns
|
|
Clock Pessimism Removal (CPR): -0.418ns
|
|
Clock Uncertainty: 0.074ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Discrete Jitter (DJ): 0.130ns
|
|
Phase Error (PE): 0.000ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock cpu_clk rise edge) 0.000 0.000 r
|
|
clock source latency -6.275 -6.275
|
|
propagated clock network latency
|
|
4.051 -2.225
|
|
SLICE_X35Y35 FDRE 0.000 -2.225 r u_cpu/addr_trans/data_vaddr_buffer_reg[14]/C
|
|
SLICE_X35Y35 FDRE (Prop_fdre_C_Q) 0.456 -1.769 r u_cpu/addr_trans/data_vaddr_buffer_reg[14]/Q
|
|
net (fo=33, routed) 1.442 -0.326 u_cpu/addr_trans/tlb_entry/data_vaddr_buffer[2]
|
|
SLICE_X42Y40 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_226/I5
|
|
SLICE_X42Y40 LUT6 (Prop_lut6_I5_O) 0.124 -0.202 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_226/O
|
|
net (fo=1, routed) 0.000 -0.202 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_226_n_0
|
|
SLICE_X42Y40 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_111/S[0]
|
|
SLICE_X42Y40 CARRY4 (Prop_carry4_S[0]_CO[3])
|
|
0.513 0.311 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_111/CO[3]
|
|
net (fo=1, routed) 0.000 0.311 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_111_n_0
|
|
SLICE_X42Y41 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_32/CI
|
|
SLICE_X42Y41 CARRY4 (Prop_carry4_CI_CO[2])
|
|
0.229 0.540 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_32/CO[2]
|
|
net (fo=1, routed) 1.009 1.549 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_32_n_1
|
|
SLICE_X40Y47 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_9/I1
|
|
SLICE_X40Y47 LUT6 (Prop_lut6_I1_O) 0.310 1.859 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_9/O
|
|
net (fo=2, routed) 0.635 2.494 u_cpu/addr_trans/tlb_entry/match1[28]
|
|
SLICE_X38Y47 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/I2
|
|
SLICE_X38Y47 LUT4 (Prop_lut4_I2_O) 0.124 2.618 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/O
|
|
net (fo=2, routed) 0.667 3.285 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2_n_0
|
|
SLICE_X39Y47 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/I0
|
|
SLICE_X39Y47 LUT5 (Prop_lut5_I0_O) 0.124 3.409 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/O
|
|
net (fo=2, routed) 1.103 4.512 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2_n_0
|
|
SLICE_X38Y50 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/I0
|
|
SLICE_X38Y50 LUT6 (Prop_lut6_I0_O) 0.124 4.636 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/O
|
|
net (fo=89, routed) 1.162 5.797 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus[8]
|
|
SLICE_X42Y51 r u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_38__0/S
|
|
SLICE_X42Y51 MUXF7 (Prop_muxf7_S_O) 0.292 6.089 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_38__0/O
|
|
net (fo=1, routed) 0.000 6.089 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_38__0_n_0
|
|
SLICE_X42Y51 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_16__0/I1
|
|
SLICE_X42Y51 MUXF8 (Prop_muxf8_I1_O) 0.088 6.177 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_16__0/O
|
|
net (fo=1, routed) 0.957 7.134 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_16__0_n_0
|
|
SLICE_X42Y50 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7/I0
|
|
SLICE_X42Y50 LUT6 (Prop_lut6_I0_O) 0.319 7.453 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7/O
|
|
net (fo=1, routed) 0.435 7.888 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7_n_0
|
|
SLICE_X44Y50 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0/I5
|
|
SLICE_X44Y50 LUT6 (Prop_lut6_I5_O) 0.124 8.012 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0/O
|
|
net (fo=10, routed) 0.740 8.753 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0_n_0
|
|
SLICE_X44Y50 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[5]_i_1__0/I3
|
|
SLICE_X44Y50 LUT6 (Prop_lut6_I3_O) 0.124 8.877 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[5]_i_1__0/O
|
|
net (fo=6, routed) 0.845 9.722 u_cpu/u_csr/ms_to_ws_bus[13]
|
|
SLICE_X50Y46 r u_cpu/u_csr/write_buffer_way[1]_i_18/I3
|
|
SLICE_X50Y46 LUT6 (Prop_lut6_I3_O) 0.124 9.846 r u_cpu/u_csr/write_buffer_way[1]_i_18/O
|
|
net (fo=1, routed) 0.000 9.846 u_cpu/u_csr/write_buffer_way[1]_i_18_n_0
|
|
SLICE_X50Y46 r u_cpu/u_csr/write_buffer_way_reg[1]_i_11/S[0]
|
|
SLICE_X50Y46 CARRY4 (Prop_carry4_S[0]_CO[3])
|
|
0.532 10.378 r u_cpu/u_csr/write_buffer_way_reg[1]_i_11/CO[3]
|
|
net (fo=1, routed) 0.000 10.378 u_cpu/u_csr/write_buffer_way_reg[1]_i_11_n_0
|
|
SLICE_X50Y47 r u_cpu/u_csr/write_buffer_way_reg[1]_i_9/CI
|
|
SLICE_X50Y47 CARRY4 (Prop_carry4_CI_CO[1])
|
|
0.157 10.535 r u_cpu/u_csr/write_buffer_way_reg[1]_i_9/CO[1]
|
|
net (fo=2, routed) 0.791 11.326 u_cpu/wb_stage/CO[0]
|
|
SLICE_X46Y39 r u_cpu/wb_stage/write_buffer_way[1]_i_5/I1
|
|
SLICE_X46Y39 LUT6 (Prop_lut6_I1_O) 0.329 11.655 f u_cpu/wb_stage/write_buffer_way[1]_i_5/O
|
|
net (fo=7, routed) 0.762 12.417 u_cpu/addr_trans/tlb_entry/sc_cancel_req
|
|
SLICE_X46Y35 f u_cpu/addr_trans/tlb_entry/main_state[0]_i_3/I1
|
|
SLICE_X46Y35 LUT3 (Prop_lut3_I1_O) 0.124 12.541 f u_cpu/addr_trans/tlb_entry/main_state[0]_i_3/O
|
|
net (fo=3, routed) 0.719 13.260 u_cpu/dcache/main_state_reg[0]_2
|
|
SLICE_X43Y31 f u_cpu/dcache/ds_to_es_bus_r[235]_i_10/I3
|
|
SLICE_X43Y31 LUT6 (Prop_lut6_I3_O) 0.124 13.384 f u_cpu/dcache/ds_to_es_bus_r[235]_i_10/O
|
|
net (fo=3, routed) 0.415 13.799 u_cpu/mem_stage/data_data_ok
|
|
SLICE_X43Y30 f u_cpu/mem_stage/flush_inst_req_buffer[1]_i_15/I0
|
|
SLICE_X43Y30 LUT3 (Prop_lut3_I0_O) 0.124 13.923 f u_cpu/mem_stage/flush_inst_req_buffer[1]_i_15/O
|
|
net (fo=2, routed) 0.833 14.756 u_cpu/mem_stage/es_to_ms_bus_r_reg[70]_1
|
|
SLICE_X48Y30 f u_cpu/mem_stage/flush_inst_req_buffer[1]_i_14/I0
|
|
SLICE_X48Y30 LUT6 (Prop_lut6_I0_O) 0.124 14.880 f u_cpu/mem_stage/flush_inst_req_buffer[1]_i_14/O
|
|
net (fo=1, routed) 0.651 15.532 u_cpu/mem_stage/ms_ready_go
|
|
SLICE_X48Y25 f u_cpu/mem_stage/flush_inst_req_buffer[1]_i_13/I4
|
|
SLICE_X48Y25 LUT6 (Prop_lut6_I4_O) 0.124 15.656 f u_cpu/mem_stage/flush_inst_req_buffer[1]_i_13/O
|
|
net (fo=3, routed) 0.483 16.139 u_cpu/id_stage/flush_inst_req_buffer[31]_i_6
|
|
SLICE_X50Y25 f u_cpu/id_stage/flush_inst_req_buffer[1]_i_9/I1
|
|
SLICE_X50Y25 LUT6 (Prop_lut6_I1_O) 0.124 16.263 f u_cpu/id_stage/flush_inst_req_buffer[1]_i_9/O
|
|
net (fo=32, routed) 0.531 16.794 u_cpu/if_stage/nextpc5
|
|
SLICE_X51Y27 f u_cpu/if_stage/fetch_pc_r[6]_i_4/I2
|
|
SLICE_X51Y27 LUT6 (Prop_lut6_I2_O) 0.124 16.918 r u_cpu/if_stage/fetch_pc_r[6]_i_4/O
|
|
net (fo=1, routed) 3.059 19.977 u_cpu/if_stage/fetch_pc_r[6]_i_4_n_0
|
|
SLICE_X114Y28 r u_cpu/if_stage/fetch_pc_r[6]_i_2/I2
|
|
SLICE_X114Y28 LUT6 (Prop_lut6_I2_O) 0.124 20.101 r u_cpu/if_stage/fetch_pc_r[6]_i_2/O
|
|
net (fo=1, routed) 0.441 20.542 u_cpu/if_stage/fetch_pc_r[6]_i_2_n_0
|
|
SLICE_X114Y25 r u_cpu/if_stage/fetch_pc_r[6]_i_1/I2
|
|
SLICE_X114Y25 LUT6 (Prop_lut6_I2_O) 0.124 20.666 r u_cpu/if_stage/fetch_pc_r[6]_i_1/O
|
|
net (fo=6, routed) 3.249 23.915 u_cpu/icache/tagv_ram_way[1].u/mem_reg_reg_2[2]
|
|
SLICE_X49Y33 r u_cpu/icache/tagv_ram_way[1].u/mem_reg_reg_i_8/I4
|
|
SLICE_X49Y33 LUT5 (Prop_lut5_I4_O) 0.124 24.039 r u_cpu/icache/tagv_ram_way[1].u/mem_reg_reg_i_8/O
|
|
net (fo=16, routed) 1.477 25.516 u_cpu/icache/data_ram_way[0].data_ram_bank[3].u/ADDRBWRADDR[2]
|
|
RAMB18_X2Y3 RAMB18E1 r u_cpu/icache/data_ram_way[0].data_ram_bank[3].u/mem_reg_reg/ADDRBWRADDR[7]
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock cpu_clk rise edge) 30.323 30.323 r
|
|
clock source latency -5.674 24.648
|
|
propagated clock network latency
|
|
3.782 28.430
|
|
clock pessimism -0.418 28.012
|
|
clock uncertainty -0.074 27.938
|
|
RAMB18_X2Y3 RAMB18E1 (Setup_ramb18e1_CLKBWRCLK_ADDRBWRADDR[7])
|
|
-0.566 27.372 u_cpu/icache/data_ram_way[0].data_ram_bank[3].u/mem_reg_reg
|
|
-------------------------------------------------------------------
|
|
required time 27.372
|
|
arrival time -25.516
|
|
-------------------------------------------------------------------
|
|
slack 1.856
|
|
|
|
Slack (MET) : 1.856ns (required time - arrival time)
|
|
Source: u_cpu/addr_trans/data_vaddr_buffer_reg[14]/C
|
|
(rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns})
|
|
Destination: u_cpu/icache/data_ram_way[0].data_ram_bank[3].u/mem_reg_reg/ADDRBWRADDR[7]
|
|
(rising edge-triggered cell RAMB18E1 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns})
|
|
Path Group: cpu_clk
|
|
Path Type: Setup (Max at Slow Process Corner)
|
|
Requirement: 30.323ns (cpu_clk rise@30.323ns - cpu_clk rise@0.000ns)
|
|
Data Path Delay: 27.741ns (logic 5.333ns (19.224%) route 22.408ns (80.776%))
|
|
Logic Levels: 26 (CARRY4=4 LUT3=2 LUT4=1 LUT5=2 LUT6=15 MUXF7=1 MUXF8=1)
|
|
Clock Path Skew: -0.086ns (DCD - SCD + CPR)
|
|
Destination Clock Delay (DCD): -1.892ns = ( 28.430 - 30.323 )
|
|
Source Clock Delay (SCD): -2.225ns
|
|
Clock Pessimism Removal (CPR): -0.418ns
|
|
Clock Uncertainty: 0.074ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Discrete Jitter (DJ): 0.130ns
|
|
Phase Error (PE): 0.000ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock cpu_clk rise edge) 0.000 0.000 r
|
|
clock source latency -6.275 -6.275
|
|
propagated clock network latency
|
|
4.051 -2.225
|
|
SLICE_X35Y35 FDRE 0.000 -2.225 r u_cpu/addr_trans/data_vaddr_buffer_reg[14]/C
|
|
SLICE_X35Y35 FDRE (Prop_fdre_C_Q) 0.456 -1.769 r u_cpu/addr_trans/data_vaddr_buffer_reg[14]/Q
|
|
net (fo=33, routed) 1.442 -0.326 u_cpu/addr_trans/tlb_entry/data_vaddr_buffer[2]
|
|
SLICE_X42Y40 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_226/I5
|
|
SLICE_X42Y40 LUT6 (Prop_lut6_I5_O) 0.124 -0.202 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_226/O
|
|
net (fo=1, routed) 0.000 -0.202 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_226_n_0
|
|
SLICE_X42Y40 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_111/S[0]
|
|
SLICE_X42Y40 CARRY4 (Prop_carry4_S[0]_CO[3])
|
|
0.513 0.311 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_111/CO[3]
|
|
net (fo=1, routed) 0.000 0.311 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_111_n_0
|
|
SLICE_X42Y41 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_32/CI
|
|
SLICE_X42Y41 CARRY4 (Prop_carry4_CI_CO[2])
|
|
0.229 0.540 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_32/CO[2]
|
|
net (fo=1, routed) 1.009 1.549 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_32_n_1
|
|
SLICE_X40Y47 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_9/I1
|
|
SLICE_X40Y47 LUT6 (Prop_lut6_I1_O) 0.310 1.859 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_9/O
|
|
net (fo=2, routed) 0.635 2.494 u_cpu/addr_trans/tlb_entry/match1[28]
|
|
SLICE_X38Y47 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/I2
|
|
SLICE_X38Y47 LUT4 (Prop_lut4_I2_O) 0.124 2.618 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/O
|
|
net (fo=2, routed) 0.667 3.285 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2_n_0
|
|
SLICE_X39Y47 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/I0
|
|
SLICE_X39Y47 LUT5 (Prop_lut5_I0_O) 0.124 3.409 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/O
|
|
net (fo=2, routed) 1.103 4.512 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2_n_0
|
|
SLICE_X38Y50 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/I0
|
|
SLICE_X38Y50 LUT6 (Prop_lut6_I0_O) 0.124 4.636 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/O
|
|
net (fo=89, routed) 1.162 5.797 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus[8]
|
|
SLICE_X42Y51 r u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_38__0/S
|
|
SLICE_X42Y51 MUXF7 (Prop_muxf7_S_O) 0.292 6.089 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_38__0/O
|
|
net (fo=1, routed) 0.000 6.089 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_38__0_n_0
|
|
SLICE_X42Y51 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_16__0/I1
|
|
SLICE_X42Y51 MUXF8 (Prop_muxf8_I1_O) 0.088 6.177 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_16__0/O
|
|
net (fo=1, routed) 0.957 7.134 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_16__0_n_0
|
|
SLICE_X42Y50 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7/I0
|
|
SLICE_X42Y50 LUT6 (Prop_lut6_I0_O) 0.319 7.453 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7/O
|
|
net (fo=1, routed) 0.435 7.888 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7_n_0
|
|
SLICE_X44Y50 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0/I5
|
|
SLICE_X44Y50 LUT6 (Prop_lut6_I5_O) 0.124 8.012 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0/O
|
|
net (fo=10, routed) 0.740 8.753 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0_n_0
|
|
SLICE_X44Y50 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[5]_i_1__0/I3
|
|
SLICE_X44Y50 LUT6 (Prop_lut6_I3_O) 0.124 8.877 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[5]_i_1__0/O
|
|
net (fo=6, routed) 0.845 9.722 u_cpu/u_csr/ms_to_ws_bus[13]
|
|
SLICE_X50Y46 f u_cpu/u_csr/write_buffer_way[1]_i_18/I3
|
|
SLICE_X50Y46 LUT6 (Prop_lut6_I3_O) 0.124 9.846 r u_cpu/u_csr/write_buffer_way[1]_i_18/O
|
|
net (fo=1, routed) 0.000 9.846 u_cpu/u_csr/write_buffer_way[1]_i_18_n_0
|
|
SLICE_X50Y46 r u_cpu/u_csr/write_buffer_way_reg[1]_i_11/S[0]
|
|
SLICE_X50Y46 CARRY4 (Prop_carry4_S[0]_CO[3])
|
|
0.532 10.378 r u_cpu/u_csr/write_buffer_way_reg[1]_i_11/CO[3]
|
|
net (fo=1, routed) 0.000 10.378 u_cpu/u_csr/write_buffer_way_reg[1]_i_11_n_0
|
|
SLICE_X50Y47 r u_cpu/u_csr/write_buffer_way_reg[1]_i_9/CI
|
|
SLICE_X50Y47 CARRY4 (Prop_carry4_CI_CO[1])
|
|
0.157 10.535 r u_cpu/u_csr/write_buffer_way_reg[1]_i_9/CO[1]
|
|
net (fo=2, routed) 0.791 11.326 u_cpu/wb_stage/CO[0]
|
|
SLICE_X46Y39 r u_cpu/wb_stage/write_buffer_way[1]_i_5/I1
|
|
SLICE_X46Y39 LUT6 (Prop_lut6_I1_O) 0.329 11.655 f u_cpu/wb_stage/write_buffer_way[1]_i_5/O
|
|
net (fo=7, routed) 0.762 12.417 u_cpu/addr_trans/tlb_entry/sc_cancel_req
|
|
SLICE_X46Y35 f u_cpu/addr_trans/tlb_entry/main_state[0]_i_3/I1
|
|
SLICE_X46Y35 LUT3 (Prop_lut3_I1_O) 0.124 12.541 f u_cpu/addr_trans/tlb_entry/main_state[0]_i_3/O
|
|
net (fo=3, routed) 0.719 13.260 u_cpu/dcache/main_state_reg[0]_2
|
|
SLICE_X43Y31 f u_cpu/dcache/ds_to_es_bus_r[235]_i_10/I3
|
|
SLICE_X43Y31 LUT6 (Prop_lut6_I3_O) 0.124 13.384 f u_cpu/dcache/ds_to_es_bus_r[235]_i_10/O
|
|
net (fo=3, routed) 0.415 13.799 u_cpu/mem_stage/data_data_ok
|
|
SLICE_X43Y30 f u_cpu/mem_stage/flush_inst_req_buffer[1]_i_15/I0
|
|
SLICE_X43Y30 LUT3 (Prop_lut3_I0_O) 0.124 13.923 f u_cpu/mem_stage/flush_inst_req_buffer[1]_i_15/O
|
|
net (fo=2, routed) 0.833 14.756 u_cpu/mem_stage/es_to_ms_bus_r_reg[70]_1
|
|
SLICE_X48Y30 f u_cpu/mem_stage/flush_inst_req_buffer[1]_i_14/I0
|
|
SLICE_X48Y30 LUT6 (Prop_lut6_I0_O) 0.124 14.880 f u_cpu/mem_stage/flush_inst_req_buffer[1]_i_14/O
|
|
net (fo=1, routed) 0.651 15.532 u_cpu/mem_stage/ms_ready_go
|
|
SLICE_X48Y25 f u_cpu/mem_stage/flush_inst_req_buffer[1]_i_13/I4
|
|
SLICE_X48Y25 LUT6 (Prop_lut6_I4_O) 0.124 15.656 f u_cpu/mem_stage/flush_inst_req_buffer[1]_i_13/O
|
|
net (fo=3, routed) 0.483 16.139 u_cpu/id_stage/flush_inst_req_buffer[31]_i_6
|
|
SLICE_X50Y25 f u_cpu/id_stage/flush_inst_req_buffer[1]_i_9/I1
|
|
SLICE_X50Y25 LUT6 (Prop_lut6_I1_O) 0.124 16.263 f u_cpu/id_stage/flush_inst_req_buffer[1]_i_9/O
|
|
net (fo=32, routed) 0.531 16.794 u_cpu/if_stage/nextpc5
|
|
SLICE_X51Y27 f u_cpu/if_stage/fetch_pc_r[6]_i_4/I2
|
|
SLICE_X51Y27 LUT6 (Prop_lut6_I2_O) 0.124 16.918 r u_cpu/if_stage/fetch_pc_r[6]_i_4/O
|
|
net (fo=1, routed) 3.059 19.977 u_cpu/if_stage/fetch_pc_r[6]_i_4_n_0
|
|
SLICE_X114Y28 r u_cpu/if_stage/fetch_pc_r[6]_i_2/I2
|
|
SLICE_X114Y28 LUT6 (Prop_lut6_I2_O) 0.124 20.101 r u_cpu/if_stage/fetch_pc_r[6]_i_2/O
|
|
net (fo=1, routed) 0.441 20.542 u_cpu/if_stage/fetch_pc_r[6]_i_2_n_0
|
|
SLICE_X114Y25 r u_cpu/if_stage/fetch_pc_r[6]_i_1/I2
|
|
SLICE_X114Y25 LUT6 (Prop_lut6_I2_O) 0.124 20.666 r u_cpu/if_stage/fetch_pc_r[6]_i_1/O
|
|
net (fo=6, routed) 3.249 23.915 u_cpu/icache/tagv_ram_way[1].u/mem_reg_reg_2[2]
|
|
SLICE_X49Y33 r u_cpu/icache/tagv_ram_way[1].u/mem_reg_reg_i_8/I4
|
|
SLICE_X49Y33 LUT5 (Prop_lut5_I4_O) 0.124 24.039 r u_cpu/icache/tagv_ram_way[1].u/mem_reg_reg_i_8/O
|
|
net (fo=16, routed) 1.477 25.516 u_cpu/icache/data_ram_way[0].data_ram_bank[3].u/ADDRBWRADDR[2]
|
|
RAMB18_X2Y3 RAMB18E1 r u_cpu/icache/data_ram_way[0].data_ram_bank[3].u/mem_reg_reg/ADDRBWRADDR[7]
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock cpu_clk rise edge) 30.323 30.323 r
|
|
clock source latency -5.674 24.648
|
|
propagated clock network latency
|
|
3.782 28.430
|
|
clock pessimism -0.418 28.012
|
|
clock uncertainty -0.074 27.938
|
|
RAMB18_X2Y3 RAMB18E1 (Setup_ramb18e1_CLKBWRCLK_ADDRBWRADDR[7])
|
|
-0.566 27.372 u_cpu/icache/data_ram_way[0].data_ram_bank[3].u/mem_reg_reg
|
|
-------------------------------------------------------------------
|
|
required time 27.372
|
|
arrival time -25.516
|
|
-------------------------------------------------------------------
|
|
slack 1.856
|
|
|
|
Slack (MET) : 1.856ns (required time - arrival time)
|
|
Source: u_cpu/addr_trans/data_vaddr_buffer_reg[14]/C
|
|
(rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns})
|
|
Destination: u_cpu/icache/data_ram_way[0].data_ram_bank[3].u/mem_reg_reg/ADDRBWRADDR[7]
|
|
(rising edge-triggered cell RAMB18E1 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns})
|
|
Path Group: cpu_clk
|
|
Path Type: Setup (Max at Slow Process Corner)
|
|
Requirement: 30.323ns (cpu_clk rise@30.323ns - cpu_clk rise@0.000ns)
|
|
Data Path Delay: 27.741ns (logic 5.333ns (19.224%) route 22.408ns (80.776%))
|
|
Logic Levels: 26 (CARRY4=4 LUT3=2 LUT4=1 LUT5=2 LUT6=15 MUXF7=1 MUXF8=1)
|
|
Clock Path Skew: -0.086ns (DCD - SCD + CPR)
|
|
Destination Clock Delay (DCD): -1.892ns = ( 28.430 - 30.323 )
|
|
Source Clock Delay (SCD): -2.225ns
|
|
Clock Pessimism Removal (CPR): -0.418ns
|
|
Clock Uncertainty: 0.074ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Discrete Jitter (DJ): 0.130ns
|
|
Phase Error (PE): 0.000ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock cpu_clk rise edge) 0.000 0.000 r
|
|
clock source latency -6.275 -6.275
|
|
propagated clock network latency
|
|
4.051 -2.225
|
|
SLICE_X35Y35 FDRE 0.000 -2.225 r u_cpu/addr_trans/data_vaddr_buffer_reg[14]/C
|
|
SLICE_X35Y35 FDRE (Prop_fdre_C_Q) 0.456 -1.769 r u_cpu/addr_trans/data_vaddr_buffer_reg[14]/Q
|
|
net (fo=33, routed) 1.442 -0.326 u_cpu/addr_trans/tlb_entry/data_vaddr_buffer[2]
|
|
SLICE_X42Y40 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_226/I5
|
|
SLICE_X42Y40 LUT6 (Prop_lut6_I5_O) 0.124 -0.202 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_226/O
|
|
net (fo=1, routed) 0.000 -0.202 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_226_n_0
|
|
SLICE_X42Y40 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_111/S[0]
|
|
SLICE_X42Y40 CARRY4 (Prop_carry4_S[0]_CO[3])
|
|
0.513 0.311 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_111/CO[3]
|
|
net (fo=1, routed) 0.000 0.311 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_111_n_0
|
|
SLICE_X42Y41 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_32/CI
|
|
SLICE_X42Y41 CARRY4 (Prop_carry4_CI_CO[2])
|
|
0.229 0.540 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_32/CO[2]
|
|
net (fo=1, routed) 1.009 1.549 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_32_n_1
|
|
SLICE_X40Y47 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_9/I1
|
|
SLICE_X40Y47 LUT6 (Prop_lut6_I1_O) 0.310 1.859 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_9/O
|
|
net (fo=2, routed) 0.635 2.494 u_cpu/addr_trans/tlb_entry/match1[28]
|
|
SLICE_X38Y47 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/I2
|
|
SLICE_X38Y47 LUT4 (Prop_lut4_I2_O) 0.124 2.618 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/O
|
|
net (fo=2, routed) 0.667 3.285 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2_n_0
|
|
SLICE_X39Y47 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/I0
|
|
SLICE_X39Y47 LUT5 (Prop_lut5_I0_O) 0.124 3.409 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/O
|
|
net (fo=2, routed) 1.103 4.512 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2_n_0
|
|
SLICE_X38Y50 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/I0
|
|
SLICE_X38Y50 LUT6 (Prop_lut6_I0_O) 0.124 4.636 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/O
|
|
net (fo=89, routed) 1.162 5.797 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus[8]
|
|
SLICE_X42Y51 r u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_38__0/S
|
|
SLICE_X42Y51 MUXF7 (Prop_muxf7_S_O) 0.292 6.089 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_38__0/O
|
|
net (fo=1, routed) 0.000 6.089 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_38__0_n_0
|
|
SLICE_X42Y51 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_16__0/I1
|
|
SLICE_X42Y51 MUXF8 (Prop_muxf8_I1_O) 0.088 6.177 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_16__0/O
|
|
net (fo=1, routed) 0.957 7.134 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_16__0_n_0
|
|
SLICE_X42Y50 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7/I0
|
|
SLICE_X42Y50 LUT6 (Prop_lut6_I0_O) 0.319 7.453 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7/O
|
|
net (fo=1, routed) 0.435 7.888 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7_n_0
|
|
SLICE_X44Y50 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0/I5
|
|
SLICE_X44Y50 LUT6 (Prop_lut6_I5_O) 0.124 8.012 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0/O
|
|
net (fo=10, routed) 0.740 8.753 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0_n_0
|
|
SLICE_X44Y50 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[5]_i_1__0/I3
|
|
SLICE_X44Y50 LUT6 (Prop_lut6_I3_O) 0.124 8.877 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[5]_i_1__0/O
|
|
net (fo=6, routed) 0.845 9.722 u_cpu/u_csr/ms_to_ws_bus[13]
|
|
SLICE_X50Y46 r u_cpu/u_csr/write_buffer_way[1]_i_18/I3
|
|
SLICE_X50Y46 LUT6 (Prop_lut6_I3_O) 0.124 9.846 f u_cpu/u_csr/write_buffer_way[1]_i_18/O
|
|
net (fo=1, routed) 0.000 9.846 u_cpu/u_csr/write_buffer_way[1]_i_18_n_0
|
|
SLICE_X50Y46 f u_cpu/u_csr/write_buffer_way_reg[1]_i_11/S[0]
|
|
SLICE_X50Y46 CARRY4 (Prop_carry4_S[0]_CO[3])
|
|
0.532 10.378 r u_cpu/u_csr/write_buffer_way_reg[1]_i_11/CO[3]
|
|
net (fo=1, routed) 0.000 10.378 u_cpu/u_csr/write_buffer_way_reg[1]_i_11_n_0
|
|
SLICE_X50Y47 r u_cpu/u_csr/write_buffer_way_reg[1]_i_9/CI
|
|
SLICE_X50Y47 CARRY4 (Prop_carry4_CI_CO[1])
|
|
0.157 10.535 r u_cpu/u_csr/write_buffer_way_reg[1]_i_9/CO[1]
|
|
net (fo=2, routed) 0.791 11.326 u_cpu/wb_stage/CO[0]
|
|
SLICE_X46Y39 r u_cpu/wb_stage/write_buffer_way[1]_i_5/I1
|
|
SLICE_X46Y39 LUT6 (Prop_lut6_I1_O) 0.329 11.655 f u_cpu/wb_stage/write_buffer_way[1]_i_5/O
|
|
net (fo=7, routed) 0.762 12.417 u_cpu/addr_trans/tlb_entry/sc_cancel_req
|
|
SLICE_X46Y35 f u_cpu/addr_trans/tlb_entry/main_state[0]_i_3/I1
|
|
SLICE_X46Y35 LUT3 (Prop_lut3_I1_O) 0.124 12.541 f u_cpu/addr_trans/tlb_entry/main_state[0]_i_3/O
|
|
net (fo=3, routed) 0.719 13.260 u_cpu/dcache/main_state_reg[0]_2
|
|
SLICE_X43Y31 f u_cpu/dcache/ds_to_es_bus_r[235]_i_10/I3
|
|
SLICE_X43Y31 LUT6 (Prop_lut6_I3_O) 0.124 13.384 f u_cpu/dcache/ds_to_es_bus_r[235]_i_10/O
|
|
net (fo=3, routed) 0.415 13.799 u_cpu/mem_stage/data_data_ok
|
|
SLICE_X43Y30 f u_cpu/mem_stage/flush_inst_req_buffer[1]_i_15/I0
|
|
SLICE_X43Y30 LUT3 (Prop_lut3_I0_O) 0.124 13.923 f u_cpu/mem_stage/flush_inst_req_buffer[1]_i_15/O
|
|
net (fo=2, routed) 0.833 14.756 u_cpu/mem_stage/es_to_ms_bus_r_reg[70]_1
|
|
SLICE_X48Y30 f u_cpu/mem_stage/flush_inst_req_buffer[1]_i_14/I0
|
|
SLICE_X48Y30 LUT6 (Prop_lut6_I0_O) 0.124 14.880 f u_cpu/mem_stage/flush_inst_req_buffer[1]_i_14/O
|
|
net (fo=1, routed) 0.651 15.532 u_cpu/mem_stage/ms_ready_go
|
|
SLICE_X48Y25 f u_cpu/mem_stage/flush_inst_req_buffer[1]_i_13/I4
|
|
SLICE_X48Y25 LUT6 (Prop_lut6_I4_O) 0.124 15.656 f u_cpu/mem_stage/flush_inst_req_buffer[1]_i_13/O
|
|
net (fo=3, routed) 0.483 16.139 u_cpu/id_stage/flush_inst_req_buffer[31]_i_6
|
|
SLICE_X50Y25 f u_cpu/id_stage/flush_inst_req_buffer[1]_i_9/I1
|
|
SLICE_X50Y25 LUT6 (Prop_lut6_I1_O) 0.124 16.263 f u_cpu/id_stage/flush_inst_req_buffer[1]_i_9/O
|
|
net (fo=32, routed) 0.531 16.794 u_cpu/if_stage/nextpc5
|
|
SLICE_X51Y27 f u_cpu/if_stage/fetch_pc_r[6]_i_4/I2
|
|
SLICE_X51Y27 LUT6 (Prop_lut6_I2_O) 0.124 16.918 r u_cpu/if_stage/fetch_pc_r[6]_i_4/O
|
|
net (fo=1, routed) 3.059 19.977 u_cpu/if_stage/fetch_pc_r[6]_i_4_n_0
|
|
SLICE_X114Y28 r u_cpu/if_stage/fetch_pc_r[6]_i_2/I2
|
|
SLICE_X114Y28 LUT6 (Prop_lut6_I2_O) 0.124 20.101 r u_cpu/if_stage/fetch_pc_r[6]_i_2/O
|
|
net (fo=1, routed) 0.441 20.542 u_cpu/if_stage/fetch_pc_r[6]_i_2_n_0
|
|
SLICE_X114Y25 r u_cpu/if_stage/fetch_pc_r[6]_i_1/I2
|
|
SLICE_X114Y25 LUT6 (Prop_lut6_I2_O) 0.124 20.666 r u_cpu/if_stage/fetch_pc_r[6]_i_1/O
|
|
net (fo=6, routed) 3.249 23.915 u_cpu/icache/tagv_ram_way[1].u/mem_reg_reg_2[2]
|
|
SLICE_X49Y33 r u_cpu/icache/tagv_ram_way[1].u/mem_reg_reg_i_8/I4
|
|
SLICE_X49Y33 LUT5 (Prop_lut5_I4_O) 0.124 24.039 r u_cpu/icache/tagv_ram_way[1].u/mem_reg_reg_i_8/O
|
|
net (fo=16, routed) 1.477 25.516 u_cpu/icache/data_ram_way[0].data_ram_bank[3].u/ADDRBWRADDR[2]
|
|
RAMB18_X2Y3 RAMB18E1 r u_cpu/icache/data_ram_way[0].data_ram_bank[3].u/mem_reg_reg/ADDRBWRADDR[7]
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock cpu_clk rise edge) 30.323 30.323 r
|
|
clock source latency -5.674 24.648
|
|
propagated clock network latency
|
|
3.782 28.430
|
|
clock pessimism -0.418 28.012
|
|
clock uncertainty -0.074 27.938
|
|
RAMB18_X2Y3 RAMB18E1 (Setup_ramb18e1_CLKBWRCLK_ADDRBWRADDR[7])
|
|
-0.566 27.372 u_cpu/icache/data_ram_way[0].data_ram_bank[3].u/mem_reg_reg
|
|
-------------------------------------------------------------------
|
|
required time 27.372
|
|
arrival time -25.516
|
|
-------------------------------------------------------------------
|
|
slack 1.856
|
|
|
|
Slack (MET) : 1.856ns (required time - arrival time)
|
|
Source: u_cpu/addr_trans/data_vaddr_buffer_reg[14]/C
|
|
(rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns})
|
|
Destination: u_cpu/icache/data_ram_way[0].data_ram_bank[3].u/mem_reg_reg/ADDRBWRADDR[7]
|
|
(rising edge-triggered cell RAMB18E1 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns})
|
|
Path Group: cpu_clk
|
|
Path Type: Setup (Max at Slow Process Corner)
|
|
Requirement: 30.323ns (cpu_clk rise@30.323ns - cpu_clk rise@0.000ns)
|
|
Data Path Delay: 27.741ns (logic 5.333ns (19.224%) route 22.408ns (80.776%))
|
|
Logic Levels: 26 (CARRY4=4 LUT3=2 LUT4=1 LUT5=2 LUT6=15 MUXF7=1 MUXF8=1)
|
|
Clock Path Skew: -0.086ns (DCD - SCD + CPR)
|
|
Destination Clock Delay (DCD): -1.892ns = ( 28.430 - 30.323 )
|
|
Source Clock Delay (SCD): -2.225ns
|
|
Clock Pessimism Removal (CPR): -0.418ns
|
|
Clock Uncertainty: 0.074ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Discrete Jitter (DJ): 0.130ns
|
|
Phase Error (PE): 0.000ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock cpu_clk rise edge) 0.000 0.000 r
|
|
clock source latency -6.275 -6.275
|
|
propagated clock network latency
|
|
4.051 -2.225
|
|
SLICE_X35Y35 FDRE 0.000 -2.225 r u_cpu/addr_trans/data_vaddr_buffer_reg[14]/C
|
|
SLICE_X35Y35 FDRE (Prop_fdre_C_Q) 0.456 -1.769 r u_cpu/addr_trans/data_vaddr_buffer_reg[14]/Q
|
|
net (fo=33, routed) 1.442 -0.326 u_cpu/addr_trans/tlb_entry/data_vaddr_buffer[2]
|
|
SLICE_X42Y40 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_226/I5
|
|
SLICE_X42Y40 LUT6 (Prop_lut6_I5_O) 0.124 -0.202 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_226/O
|
|
net (fo=1, routed) 0.000 -0.202 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_226_n_0
|
|
SLICE_X42Y40 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_111/S[0]
|
|
SLICE_X42Y40 CARRY4 (Prop_carry4_S[0]_CO[3])
|
|
0.513 0.311 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_111/CO[3]
|
|
net (fo=1, routed) 0.000 0.311 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_111_n_0
|
|
SLICE_X42Y41 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_32/CI
|
|
SLICE_X42Y41 CARRY4 (Prop_carry4_CI_CO[2])
|
|
0.229 0.540 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_32/CO[2]
|
|
net (fo=1, routed) 1.009 1.549 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_32_n_1
|
|
SLICE_X40Y47 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_9/I1
|
|
SLICE_X40Y47 LUT6 (Prop_lut6_I1_O) 0.310 1.859 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_9/O
|
|
net (fo=2, routed) 0.635 2.494 u_cpu/addr_trans/tlb_entry/match1[28]
|
|
SLICE_X38Y47 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/I2
|
|
SLICE_X38Y47 LUT4 (Prop_lut4_I2_O) 0.124 2.618 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/O
|
|
net (fo=2, routed) 0.667 3.285 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2_n_0
|
|
SLICE_X39Y47 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/I0
|
|
SLICE_X39Y47 LUT5 (Prop_lut5_I0_O) 0.124 3.409 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/O
|
|
net (fo=2, routed) 1.103 4.512 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2_n_0
|
|
SLICE_X38Y50 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/I0
|
|
SLICE_X38Y50 LUT6 (Prop_lut6_I0_O) 0.124 4.636 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/O
|
|
net (fo=89, routed) 1.162 5.797 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus[8]
|
|
SLICE_X42Y51 r u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_38__0/S
|
|
SLICE_X42Y51 MUXF7 (Prop_muxf7_S_O) 0.292 6.089 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_38__0/O
|
|
net (fo=1, routed) 0.000 6.089 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_38__0_n_0
|
|
SLICE_X42Y51 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_16__0/I1
|
|
SLICE_X42Y51 MUXF8 (Prop_muxf8_I1_O) 0.088 6.177 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_16__0/O
|
|
net (fo=1, routed) 0.957 7.134 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_16__0_n_0
|
|
SLICE_X42Y50 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7/I0
|
|
SLICE_X42Y50 LUT6 (Prop_lut6_I0_O) 0.319 7.453 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7/O
|
|
net (fo=1, routed) 0.435 7.888 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7_n_0
|
|
SLICE_X44Y50 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0/I5
|
|
SLICE_X44Y50 LUT6 (Prop_lut6_I5_O) 0.124 8.012 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0/O
|
|
net (fo=10, routed) 0.740 8.753 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0_n_0
|
|
SLICE_X44Y50 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[5]_i_1__0/I3
|
|
SLICE_X44Y50 LUT6 (Prop_lut6_I3_O) 0.124 8.877 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[5]_i_1__0/O
|
|
net (fo=6, routed) 0.845 9.722 u_cpu/u_csr/ms_to_ws_bus[13]
|
|
SLICE_X50Y46 f u_cpu/u_csr/write_buffer_way[1]_i_18/I3
|
|
SLICE_X50Y46 LUT6 (Prop_lut6_I3_O) 0.124 9.846 f u_cpu/u_csr/write_buffer_way[1]_i_18/O
|
|
net (fo=1, routed) 0.000 9.846 u_cpu/u_csr/write_buffer_way[1]_i_18_n_0
|
|
SLICE_X50Y46 f u_cpu/u_csr/write_buffer_way_reg[1]_i_11/S[0]
|
|
SLICE_X50Y46 CARRY4 (Prop_carry4_S[0]_CO[3])
|
|
0.532 10.378 r u_cpu/u_csr/write_buffer_way_reg[1]_i_11/CO[3]
|
|
net (fo=1, routed) 0.000 10.378 u_cpu/u_csr/write_buffer_way_reg[1]_i_11_n_0
|
|
SLICE_X50Y47 r u_cpu/u_csr/write_buffer_way_reg[1]_i_9/CI
|
|
SLICE_X50Y47 CARRY4 (Prop_carry4_CI_CO[1])
|
|
0.157 10.535 r u_cpu/u_csr/write_buffer_way_reg[1]_i_9/CO[1]
|
|
net (fo=2, routed) 0.791 11.326 u_cpu/wb_stage/CO[0]
|
|
SLICE_X46Y39 r u_cpu/wb_stage/write_buffer_way[1]_i_5/I1
|
|
SLICE_X46Y39 LUT6 (Prop_lut6_I1_O) 0.329 11.655 f u_cpu/wb_stage/write_buffer_way[1]_i_5/O
|
|
net (fo=7, routed) 0.762 12.417 u_cpu/addr_trans/tlb_entry/sc_cancel_req
|
|
SLICE_X46Y35 f u_cpu/addr_trans/tlb_entry/main_state[0]_i_3/I1
|
|
SLICE_X46Y35 LUT3 (Prop_lut3_I1_O) 0.124 12.541 f u_cpu/addr_trans/tlb_entry/main_state[0]_i_3/O
|
|
net (fo=3, routed) 0.719 13.260 u_cpu/dcache/main_state_reg[0]_2
|
|
SLICE_X43Y31 f u_cpu/dcache/ds_to_es_bus_r[235]_i_10/I3
|
|
SLICE_X43Y31 LUT6 (Prop_lut6_I3_O) 0.124 13.384 f u_cpu/dcache/ds_to_es_bus_r[235]_i_10/O
|
|
net (fo=3, routed) 0.415 13.799 u_cpu/mem_stage/data_data_ok
|
|
SLICE_X43Y30 f u_cpu/mem_stage/flush_inst_req_buffer[1]_i_15/I0
|
|
SLICE_X43Y30 LUT3 (Prop_lut3_I0_O) 0.124 13.923 f u_cpu/mem_stage/flush_inst_req_buffer[1]_i_15/O
|
|
net (fo=2, routed) 0.833 14.756 u_cpu/mem_stage/es_to_ms_bus_r_reg[70]_1
|
|
SLICE_X48Y30 f u_cpu/mem_stage/flush_inst_req_buffer[1]_i_14/I0
|
|
SLICE_X48Y30 LUT6 (Prop_lut6_I0_O) 0.124 14.880 f u_cpu/mem_stage/flush_inst_req_buffer[1]_i_14/O
|
|
net (fo=1, routed) 0.651 15.532 u_cpu/mem_stage/ms_ready_go
|
|
SLICE_X48Y25 f u_cpu/mem_stage/flush_inst_req_buffer[1]_i_13/I4
|
|
SLICE_X48Y25 LUT6 (Prop_lut6_I4_O) 0.124 15.656 f u_cpu/mem_stage/flush_inst_req_buffer[1]_i_13/O
|
|
net (fo=3, routed) 0.483 16.139 u_cpu/id_stage/flush_inst_req_buffer[31]_i_6
|
|
SLICE_X50Y25 f u_cpu/id_stage/flush_inst_req_buffer[1]_i_9/I1
|
|
SLICE_X50Y25 LUT6 (Prop_lut6_I1_O) 0.124 16.263 f u_cpu/id_stage/flush_inst_req_buffer[1]_i_9/O
|
|
net (fo=32, routed) 0.531 16.794 u_cpu/if_stage/nextpc5
|
|
SLICE_X51Y27 f u_cpu/if_stage/fetch_pc_r[6]_i_4/I2
|
|
SLICE_X51Y27 LUT6 (Prop_lut6_I2_O) 0.124 16.918 r u_cpu/if_stage/fetch_pc_r[6]_i_4/O
|
|
net (fo=1, routed) 3.059 19.977 u_cpu/if_stage/fetch_pc_r[6]_i_4_n_0
|
|
SLICE_X114Y28 r u_cpu/if_stage/fetch_pc_r[6]_i_2/I2
|
|
SLICE_X114Y28 LUT6 (Prop_lut6_I2_O) 0.124 20.101 r u_cpu/if_stage/fetch_pc_r[6]_i_2/O
|
|
net (fo=1, routed) 0.441 20.542 u_cpu/if_stage/fetch_pc_r[6]_i_2_n_0
|
|
SLICE_X114Y25 r u_cpu/if_stage/fetch_pc_r[6]_i_1/I2
|
|
SLICE_X114Y25 LUT6 (Prop_lut6_I2_O) 0.124 20.666 r u_cpu/if_stage/fetch_pc_r[6]_i_1/O
|
|
net (fo=6, routed) 3.249 23.915 u_cpu/icache/tagv_ram_way[1].u/mem_reg_reg_2[2]
|
|
SLICE_X49Y33 r u_cpu/icache/tagv_ram_way[1].u/mem_reg_reg_i_8/I4
|
|
SLICE_X49Y33 LUT5 (Prop_lut5_I4_O) 0.124 24.039 r u_cpu/icache/tagv_ram_way[1].u/mem_reg_reg_i_8/O
|
|
net (fo=16, routed) 1.477 25.516 u_cpu/icache/data_ram_way[0].data_ram_bank[3].u/ADDRBWRADDR[2]
|
|
RAMB18_X2Y3 RAMB18E1 r u_cpu/icache/data_ram_way[0].data_ram_bank[3].u/mem_reg_reg/ADDRBWRADDR[7]
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock cpu_clk rise edge) 30.323 30.323 r
|
|
clock source latency -5.674 24.648
|
|
propagated clock network latency
|
|
3.782 28.430
|
|
clock pessimism -0.418 28.012
|
|
clock uncertainty -0.074 27.938
|
|
RAMB18_X2Y3 RAMB18E1 (Setup_ramb18e1_CLKBWRCLK_ADDRBWRADDR[7])
|
|
-0.566 27.372 u_cpu/icache/data_ram_way[0].data_ram_bank[3].u/mem_reg_reg
|
|
-------------------------------------------------------------------
|
|
required time 27.372
|
|
arrival time -25.516
|
|
-------------------------------------------------------------------
|
|
slack 1.856
|
|
|
|
Slack (MET) : 1.856ns (required time - arrival time)
|
|
Source: u_cpu/addr_trans/data_vaddr_buffer_reg[14]/C
|
|
(rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns})
|
|
Destination: u_cpu/icache/data_ram_way[0].data_ram_bank[3].u/mem_reg_reg/ADDRBWRADDR[7]
|
|
(rising edge-triggered cell RAMB18E1 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns})
|
|
Path Group: cpu_clk
|
|
Path Type: Setup (Max at Slow Process Corner)
|
|
Requirement: 30.323ns (cpu_clk rise@30.323ns - cpu_clk rise@0.000ns)
|
|
Data Path Delay: 27.741ns (logic 5.333ns (19.224%) route 22.408ns (80.776%))
|
|
Logic Levels: 26 (CARRY4=4 LUT3=2 LUT4=1 LUT5=2 LUT6=15 MUXF7=1 MUXF8=1)
|
|
Clock Path Skew: -0.086ns (DCD - SCD + CPR)
|
|
Destination Clock Delay (DCD): -1.892ns = ( 28.430 - 30.323 )
|
|
Source Clock Delay (SCD): -2.225ns
|
|
Clock Pessimism Removal (CPR): -0.418ns
|
|
Clock Uncertainty: 0.074ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Discrete Jitter (DJ): 0.130ns
|
|
Phase Error (PE): 0.000ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock cpu_clk rise edge) 0.000 0.000 r
|
|
clock source latency -6.275 -6.275
|
|
propagated clock network latency
|
|
4.051 -2.225
|
|
SLICE_X35Y35 FDRE 0.000 -2.225 r u_cpu/addr_trans/data_vaddr_buffer_reg[14]/C
|
|
SLICE_X35Y35 FDRE (Prop_fdre_C_Q) 0.456 -1.769 r u_cpu/addr_trans/data_vaddr_buffer_reg[14]/Q
|
|
net (fo=33, routed) 1.442 -0.326 u_cpu/addr_trans/tlb_entry/data_vaddr_buffer[2]
|
|
SLICE_X42Y40 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_226/I5
|
|
SLICE_X42Y40 LUT6 (Prop_lut6_I5_O) 0.124 -0.202 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_226/O
|
|
net (fo=1, routed) 0.000 -0.202 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_226_n_0
|
|
SLICE_X42Y40 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_111/S[0]
|
|
SLICE_X42Y40 CARRY4 (Prop_carry4_S[0]_CO[3])
|
|
0.513 0.311 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_111/CO[3]
|
|
net (fo=1, routed) 0.000 0.311 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_111_n_0
|
|
SLICE_X42Y41 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_32/CI
|
|
SLICE_X42Y41 CARRY4 (Prop_carry4_CI_CO[2])
|
|
0.229 0.540 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_32/CO[2]
|
|
net (fo=1, routed) 1.009 1.549 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_32_n_1
|
|
SLICE_X40Y47 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_9/I1
|
|
SLICE_X40Y47 LUT6 (Prop_lut6_I1_O) 0.310 1.859 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_9/O
|
|
net (fo=2, routed) 0.635 2.494 u_cpu/addr_trans/tlb_entry/match1[28]
|
|
SLICE_X38Y47 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/I2
|
|
SLICE_X38Y47 LUT4 (Prop_lut4_I2_O) 0.124 2.618 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/O
|
|
net (fo=2, routed) 0.667 3.285 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2_n_0
|
|
SLICE_X39Y47 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/I0
|
|
SLICE_X39Y47 LUT5 (Prop_lut5_I0_O) 0.124 3.409 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/O
|
|
net (fo=2, routed) 1.103 4.512 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2_n_0
|
|
SLICE_X38Y50 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/I0
|
|
SLICE_X38Y50 LUT6 (Prop_lut6_I0_O) 0.124 4.636 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/O
|
|
net (fo=89, routed) 1.162 5.797 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus[8]
|
|
SLICE_X42Y51 r u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_38__0/S
|
|
SLICE_X42Y51 MUXF7 (Prop_muxf7_S_O) 0.292 6.089 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_38__0/O
|
|
net (fo=1, routed) 0.000 6.089 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_38__0_n_0
|
|
SLICE_X42Y51 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_16__0/I1
|
|
SLICE_X42Y51 MUXF8 (Prop_muxf8_I1_O) 0.088 6.177 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_16__0/O
|
|
net (fo=1, routed) 0.957 7.134 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_16__0_n_0
|
|
SLICE_X42Y50 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7/I0
|
|
SLICE_X42Y50 LUT6 (Prop_lut6_I0_O) 0.319 7.453 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7/O
|
|
net (fo=1, routed) 0.435 7.888 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7_n_0
|
|
SLICE_X44Y50 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0/I5
|
|
SLICE_X44Y50 LUT6 (Prop_lut6_I5_O) 0.124 8.012 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0/O
|
|
net (fo=10, routed) 0.740 8.753 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0_n_0
|
|
SLICE_X44Y50 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[5]_i_1__0/I3
|
|
SLICE_X44Y50 LUT6 (Prop_lut6_I3_O) 0.124 8.877 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[5]_i_1__0/O
|
|
net (fo=6, routed) 0.845 9.722 u_cpu/u_csr/ms_to_ws_bus[13]
|
|
SLICE_X50Y46 r u_cpu/u_csr/write_buffer_way[1]_i_18/I3
|
|
SLICE_X50Y46 LUT6 (Prop_lut6_I3_O) 0.124 9.846 r u_cpu/u_csr/write_buffer_way[1]_i_18/O
|
|
net (fo=1, routed) 0.000 9.846 u_cpu/u_csr/write_buffer_way[1]_i_18_n_0
|
|
SLICE_X50Y46 r u_cpu/u_csr/write_buffer_way_reg[1]_i_11/S[0]
|
|
SLICE_X50Y46 CARRY4 (Prop_carry4_S[0]_CO[3])
|
|
0.532 10.378 f u_cpu/u_csr/write_buffer_way_reg[1]_i_11/CO[3]
|
|
net (fo=1, routed) 0.000 10.378 u_cpu/u_csr/write_buffer_way_reg[1]_i_11_n_0
|
|
SLICE_X50Y47 f u_cpu/u_csr/write_buffer_way_reg[1]_i_9/CI
|
|
SLICE_X50Y47 CARRY4 (Prop_carry4_CI_CO[1])
|
|
0.157 10.535 r u_cpu/u_csr/write_buffer_way_reg[1]_i_9/CO[1]
|
|
net (fo=2, routed) 0.791 11.326 u_cpu/wb_stage/CO[0]
|
|
SLICE_X46Y39 r u_cpu/wb_stage/write_buffer_way[1]_i_5/I1
|
|
SLICE_X46Y39 LUT6 (Prop_lut6_I1_O) 0.329 11.655 f u_cpu/wb_stage/write_buffer_way[1]_i_5/O
|
|
net (fo=7, routed) 0.762 12.417 u_cpu/addr_trans/tlb_entry/sc_cancel_req
|
|
SLICE_X46Y35 f u_cpu/addr_trans/tlb_entry/main_state[0]_i_3/I1
|
|
SLICE_X46Y35 LUT3 (Prop_lut3_I1_O) 0.124 12.541 f u_cpu/addr_trans/tlb_entry/main_state[0]_i_3/O
|
|
net (fo=3, routed) 0.719 13.260 u_cpu/dcache/main_state_reg[0]_2
|
|
SLICE_X43Y31 f u_cpu/dcache/ds_to_es_bus_r[235]_i_10/I3
|
|
SLICE_X43Y31 LUT6 (Prop_lut6_I3_O) 0.124 13.384 f u_cpu/dcache/ds_to_es_bus_r[235]_i_10/O
|
|
net (fo=3, routed) 0.415 13.799 u_cpu/mem_stage/data_data_ok
|
|
SLICE_X43Y30 f u_cpu/mem_stage/flush_inst_req_buffer[1]_i_15/I0
|
|
SLICE_X43Y30 LUT3 (Prop_lut3_I0_O) 0.124 13.923 f u_cpu/mem_stage/flush_inst_req_buffer[1]_i_15/O
|
|
net (fo=2, routed) 0.833 14.756 u_cpu/mem_stage/es_to_ms_bus_r_reg[70]_1
|
|
SLICE_X48Y30 f u_cpu/mem_stage/flush_inst_req_buffer[1]_i_14/I0
|
|
SLICE_X48Y30 LUT6 (Prop_lut6_I0_O) 0.124 14.880 f u_cpu/mem_stage/flush_inst_req_buffer[1]_i_14/O
|
|
net (fo=1, routed) 0.651 15.532 u_cpu/mem_stage/ms_ready_go
|
|
SLICE_X48Y25 f u_cpu/mem_stage/flush_inst_req_buffer[1]_i_13/I4
|
|
SLICE_X48Y25 LUT6 (Prop_lut6_I4_O) 0.124 15.656 f u_cpu/mem_stage/flush_inst_req_buffer[1]_i_13/O
|
|
net (fo=3, routed) 0.483 16.139 u_cpu/id_stage/flush_inst_req_buffer[31]_i_6
|
|
SLICE_X50Y25 f u_cpu/id_stage/flush_inst_req_buffer[1]_i_9/I1
|
|
SLICE_X50Y25 LUT6 (Prop_lut6_I1_O) 0.124 16.263 f u_cpu/id_stage/flush_inst_req_buffer[1]_i_9/O
|
|
net (fo=32, routed) 0.531 16.794 u_cpu/if_stage/nextpc5
|
|
SLICE_X51Y27 f u_cpu/if_stage/fetch_pc_r[6]_i_4/I2
|
|
SLICE_X51Y27 LUT6 (Prop_lut6_I2_O) 0.124 16.918 r u_cpu/if_stage/fetch_pc_r[6]_i_4/O
|
|
net (fo=1, routed) 3.059 19.977 u_cpu/if_stage/fetch_pc_r[6]_i_4_n_0
|
|
SLICE_X114Y28 r u_cpu/if_stage/fetch_pc_r[6]_i_2/I2
|
|
SLICE_X114Y28 LUT6 (Prop_lut6_I2_O) 0.124 20.101 r u_cpu/if_stage/fetch_pc_r[6]_i_2/O
|
|
net (fo=1, routed) 0.441 20.542 u_cpu/if_stage/fetch_pc_r[6]_i_2_n_0
|
|
SLICE_X114Y25 r u_cpu/if_stage/fetch_pc_r[6]_i_1/I2
|
|
SLICE_X114Y25 LUT6 (Prop_lut6_I2_O) 0.124 20.666 r u_cpu/if_stage/fetch_pc_r[6]_i_1/O
|
|
net (fo=6, routed) 3.249 23.915 u_cpu/icache/tagv_ram_way[1].u/mem_reg_reg_2[2]
|
|
SLICE_X49Y33 r u_cpu/icache/tagv_ram_way[1].u/mem_reg_reg_i_8/I4
|
|
SLICE_X49Y33 LUT5 (Prop_lut5_I4_O) 0.124 24.039 r u_cpu/icache/tagv_ram_way[1].u/mem_reg_reg_i_8/O
|
|
net (fo=16, routed) 1.477 25.516 u_cpu/icache/data_ram_way[0].data_ram_bank[3].u/ADDRBWRADDR[2]
|
|
RAMB18_X2Y3 RAMB18E1 r u_cpu/icache/data_ram_way[0].data_ram_bank[3].u/mem_reg_reg/ADDRBWRADDR[7]
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock cpu_clk rise edge) 30.323 30.323 r
|
|
clock source latency -5.674 24.648
|
|
propagated clock network latency
|
|
3.782 28.430
|
|
clock pessimism -0.418 28.012
|
|
clock uncertainty -0.074 27.938
|
|
RAMB18_X2Y3 RAMB18E1 (Setup_ramb18e1_CLKBWRCLK_ADDRBWRADDR[7])
|
|
-0.566 27.372 u_cpu/icache/data_ram_way[0].data_ram_bank[3].u/mem_reg_reg
|
|
-------------------------------------------------------------------
|
|
required time 27.372
|
|
arrival time -25.516
|
|
-------------------------------------------------------------------
|
|
slack 1.856
|
|
|
|
Slack (MET) : 1.856ns (required time - arrival time)
|
|
Source: u_cpu/addr_trans/data_vaddr_buffer_reg[14]/C
|
|
(rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns})
|
|
Destination: u_cpu/icache/data_ram_way[0].data_ram_bank[3].u/mem_reg_reg/ADDRBWRADDR[7]
|
|
(rising edge-triggered cell RAMB18E1 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns})
|
|
Path Group: cpu_clk
|
|
Path Type: Setup (Max at Slow Process Corner)
|
|
Requirement: 30.323ns (cpu_clk rise@30.323ns - cpu_clk rise@0.000ns)
|
|
Data Path Delay: 27.741ns (logic 5.333ns (19.224%) route 22.408ns (80.776%))
|
|
Logic Levels: 26 (CARRY4=4 LUT3=2 LUT4=1 LUT5=2 LUT6=15 MUXF7=1 MUXF8=1)
|
|
Clock Path Skew: -0.086ns (DCD - SCD + CPR)
|
|
Destination Clock Delay (DCD): -1.892ns = ( 28.430 - 30.323 )
|
|
Source Clock Delay (SCD): -2.225ns
|
|
Clock Pessimism Removal (CPR): -0.418ns
|
|
Clock Uncertainty: 0.074ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Discrete Jitter (DJ): 0.130ns
|
|
Phase Error (PE): 0.000ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock cpu_clk rise edge) 0.000 0.000 r
|
|
clock source latency -6.275 -6.275
|
|
propagated clock network latency
|
|
4.051 -2.225
|
|
SLICE_X35Y35 FDRE 0.000 -2.225 r u_cpu/addr_trans/data_vaddr_buffer_reg[14]/C
|
|
SLICE_X35Y35 FDRE (Prop_fdre_C_Q) 0.456 -1.769 r u_cpu/addr_trans/data_vaddr_buffer_reg[14]/Q
|
|
net (fo=33, routed) 1.442 -0.326 u_cpu/addr_trans/tlb_entry/data_vaddr_buffer[2]
|
|
SLICE_X42Y40 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_226/I5
|
|
SLICE_X42Y40 LUT6 (Prop_lut6_I5_O) 0.124 -0.202 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_226/O
|
|
net (fo=1, routed) 0.000 -0.202 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_226_n_0
|
|
SLICE_X42Y40 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_111/S[0]
|
|
SLICE_X42Y40 CARRY4 (Prop_carry4_S[0]_CO[3])
|
|
0.513 0.311 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_111/CO[3]
|
|
net (fo=1, routed) 0.000 0.311 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_111_n_0
|
|
SLICE_X42Y41 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_32/CI
|
|
SLICE_X42Y41 CARRY4 (Prop_carry4_CI_CO[2])
|
|
0.229 0.540 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_32/CO[2]
|
|
net (fo=1, routed) 1.009 1.549 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_32_n_1
|
|
SLICE_X40Y47 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_9/I1
|
|
SLICE_X40Y47 LUT6 (Prop_lut6_I1_O) 0.310 1.859 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_9/O
|
|
net (fo=2, routed) 0.635 2.494 u_cpu/addr_trans/tlb_entry/match1[28]
|
|
SLICE_X38Y47 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/I2
|
|
SLICE_X38Y47 LUT4 (Prop_lut4_I2_O) 0.124 2.618 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/O
|
|
net (fo=2, routed) 0.667 3.285 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2_n_0
|
|
SLICE_X39Y47 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/I0
|
|
SLICE_X39Y47 LUT5 (Prop_lut5_I0_O) 0.124 3.409 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/O
|
|
net (fo=2, routed) 1.103 4.512 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2_n_0
|
|
SLICE_X38Y50 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/I0
|
|
SLICE_X38Y50 LUT6 (Prop_lut6_I0_O) 0.124 4.636 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/O
|
|
net (fo=89, routed) 1.162 5.797 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus[8]
|
|
SLICE_X42Y51 r u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_38__0/S
|
|
SLICE_X42Y51 MUXF7 (Prop_muxf7_S_O) 0.292 6.089 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_38__0/O
|
|
net (fo=1, routed) 0.000 6.089 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_38__0_n_0
|
|
SLICE_X42Y51 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_16__0/I1
|
|
SLICE_X42Y51 MUXF8 (Prop_muxf8_I1_O) 0.088 6.177 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_16__0/O
|
|
net (fo=1, routed) 0.957 7.134 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_16__0_n_0
|
|
SLICE_X42Y50 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7/I0
|
|
SLICE_X42Y50 LUT6 (Prop_lut6_I0_O) 0.319 7.453 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7/O
|
|
net (fo=1, routed) 0.435 7.888 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7_n_0
|
|
SLICE_X44Y50 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0/I5
|
|
SLICE_X44Y50 LUT6 (Prop_lut6_I5_O) 0.124 8.012 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0/O
|
|
net (fo=10, routed) 0.740 8.753 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0_n_0
|
|
SLICE_X44Y50 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[5]_i_1__0/I3
|
|
SLICE_X44Y50 LUT6 (Prop_lut6_I3_O) 0.124 8.877 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[5]_i_1__0/O
|
|
net (fo=6, routed) 0.845 9.722 u_cpu/u_csr/ms_to_ws_bus[13]
|
|
SLICE_X50Y46 f u_cpu/u_csr/write_buffer_way[1]_i_18/I3
|
|
SLICE_X50Y46 LUT6 (Prop_lut6_I3_O) 0.124 9.846 r u_cpu/u_csr/write_buffer_way[1]_i_18/O
|
|
net (fo=1, routed) 0.000 9.846 u_cpu/u_csr/write_buffer_way[1]_i_18_n_0
|
|
SLICE_X50Y46 r u_cpu/u_csr/write_buffer_way_reg[1]_i_11/S[0]
|
|
SLICE_X50Y46 CARRY4 (Prop_carry4_S[0]_CO[3])
|
|
0.532 10.378 f u_cpu/u_csr/write_buffer_way_reg[1]_i_11/CO[3]
|
|
net (fo=1, routed) 0.000 10.378 u_cpu/u_csr/write_buffer_way_reg[1]_i_11_n_0
|
|
SLICE_X50Y47 f u_cpu/u_csr/write_buffer_way_reg[1]_i_9/CI
|
|
SLICE_X50Y47 CARRY4 (Prop_carry4_CI_CO[1])
|
|
0.157 10.535 r u_cpu/u_csr/write_buffer_way_reg[1]_i_9/CO[1]
|
|
net (fo=2, routed) 0.791 11.326 u_cpu/wb_stage/CO[0]
|
|
SLICE_X46Y39 r u_cpu/wb_stage/write_buffer_way[1]_i_5/I1
|
|
SLICE_X46Y39 LUT6 (Prop_lut6_I1_O) 0.329 11.655 f u_cpu/wb_stage/write_buffer_way[1]_i_5/O
|
|
net (fo=7, routed) 0.762 12.417 u_cpu/addr_trans/tlb_entry/sc_cancel_req
|
|
SLICE_X46Y35 f u_cpu/addr_trans/tlb_entry/main_state[0]_i_3/I1
|
|
SLICE_X46Y35 LUT3 (Prop_lut3_I1_O) 0.124 12.541 f u_cpu/addr_trans/tlb_entry/main_state[0]_i_3/O
|
|
net (fo=3, routed) 0.719 13.260 u_cpu/dcache/main_state_reg[0]_2
|
|
SLICE_X43Y31 f u_cpu/dcache/ds_to_es_bus_r[235]_i_10/I3
|
|
SLICE_X43Y31 LUT6 (Prop_lut6_I3_O) 0.124 13.384 f u_cpu/dcache/ds_to_es_bus_r[235]_i_10/O
|
|
net (fo=3, routed) 0.415 13.799 u_cpu/mem_stage/data_data_ok
|
|
SLICE_X43Y30 f u_cpu/mem_stage/flush_inst_req_buffer[1]_i_15/I0
|
|
SLICE_X43Y30 LUT3 (Prop_lut3_I0_O) 0.124 13.923 f u_cpu/mem_stage/flush_inst_req_buffer[1]_i_15/O
|
|
net (fo=2, routed) 0.833 14.756 u_cpu/mem_stage/es_to_ms_bus_r_reg[70]_1
|
|
SLICE_X48Y30 f u_cpu/mem_stage/flush_inst_req_buffer[1]_i_14/I0
|
|
SLICE_X48Y30 LUT6 (Prop_lut6_I0_O) 0.124 14.880 f u_cpu/mem_stage/flush_inst_req_buffer[1]_i_14/O
|
|
net (fo=1, routed) 0.651 15.532 u_cpu/mem_stage/ms_ready_go
|
|
SLICE_X48Y25 f u_cpu/mem_stage/flush_inst_req_buffer[1]_i_13/I4
|
|
SLICE_X48Y25 LUT6 (Prop_lut6_I4_O) 0.124 15.656 f u_cpu/mem_stage/flush_inst_req_buffer[1]_i_13/O
|
|
net (fo=3, routed) 0.483 16.139 u_cpu/id_stage/flush_inst_req_buffer[31]_i_6
|
|
SLICE_X50Y25 f u_cpu/id_stage/flush_inst_req_buffer[1]_i_9/I1
|
|
SLICE_X50Y25 LUT6 (Prop_lut6_I1_O) 0.124 16.263 f u_cpu/id_stage/flush_inst_req_buffer[1]_i_9/O
|
|
net (fo=32, routed) 0.531 16.794 u_cpu/if_stage/nextpc5
|
|
SLICE_X51Y27 f u_cpu/if_stage/fetch_pc_r[6]_i_4/I2
|
|
SLICE_X51Y27 LUT6 (Prop_lut6_I2_O) 0.124 16.918 r u_cpu/if_stage/fetch_pc_r[6]_i_4/O
|
|
net (fo=1, routed) 3.059 19.977 u_cpu/if_stage/fetch_pc_r[6]_i_4_n_0
|
|
SLICE_X114Y28 r u_cpu/if_stage/fetch_pc_r[6]_i_2/I2
|
|
SLICE_X114Y28 LUT6 (Prop_lut6_I2_O) 0.124 20.101 r u_cpu/if_stage/fetch_pc_r[6]_i_2/O
|
|
net (fo=1, routed) 0.441 20.542 u_cpu/if_stage/fetch_pc_r[6]_i_2_n_0
|
|
SLICE_X114Y25 r u_cpu/if_stage/fetch_pc_r[6]_i_1/I2
|
|
SLICE_X114Y25 LUT6 (Prop_lut6_I2_O) 0.124 20.666 r u_cpu/if_stage/fetch_pc_r[6]_i_1/O
|
|
net (fo=6, routed) 3.249 23.915 u_cpu/icache/tagv_ram_way[1].u/mem_reg_reg_2[2]
|
|
SLICE_X49Y33 r u_cpu/icache/tagv_ram_way[1].u/mem_reg_reg_i_8/I4
|
|
SLICE_X49Y33 LUT5 (Prop_lut5_I4_O) 0.124 24.039 r u_cpu/icache/tagv_ram_way[1].u/mem_reg_reg_i_8/O
|
|
net (fo=16, routed) 1.477 25.516 u_cpu/icache/data_ram_way[0].data_ram_bank[3].u/ADDRBWRADDR[2]
|
|
RAMB18_X2Y3 RAMB18E1 r u_cpu/icache/data_ram_way[0].data_ram_bank[3].u/mem_reg_reg/ADDRBWRADDR[7]
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock cpu_clk rise edge) 30.323 30.323 r
|
|
clock source latency -5.674 24.648
|
|
propagated clock network latency
|
|
3.782 28.430
|
|
clock pessimism -0.418 28.012
|
|
clock uncertainty -0.074 27.938
|
|
RAMB18_X2Y3 RAMB18E1 (Setup_ramb18e1_CLKBWRCLK_ADDRBWRADDR[7])
|
|
-0.566 27.372 u_cpu/icache/data_ram_way[0].data_ram_bank[3].u/mem_reg_reg
|
|
-------------------------------------------------------------------
|
|
required time 27.372
|
|
arrival time -25.516
|
|
-------------------------------------------------------------------
|
|
slack 1.856
|
|
|
|
Slack (MET) : 1.916ns (required time - arrival time)
|
|
Source: u_cpu/addr_trans/data_vaddr_buffer_reg[14]/C
|
|
(rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns})
|
|
Destination: u_cpu/icache/data_ram_way[0].data_ram_bank[0].u/mem_reg_reg/ADDRARDADDR[7]
|
|
(rising edge-triggered cell RAMB18E1 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns})
|
|
Path Group: cpu_clk
|
|
Path Type: Setup (Max at Slow Process Corner)
|
|
Requirement: 30.323ns (cpu_clk rise@30.323ns - cpu_clk rise@0.000ns)
|
|
Data Path Delay: 27.676ns (logic 5.333ns (19.269%) route 22.343ns (80.731%))
|
|
Logic Levels: 26 (CARRY4=4 LUT3=2 LUT4=1 LUT5=2 LUT6=15 MUXF7=1 MUXF8=1)
|
|
Clock Path Skew: -0.091ns (DCD - SCD + CPR)
|
|
Destination Clock Delay (DCD): -1.897ns = ( 28.425 - 30.323 )
|
|
Source Clock Delay (SCD): -2.225ns
|
|
Clock Pessimism Removal (CPR): -0.418ns
|
|
Clock Uncertainty: 0.074ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Discrete Jitter (DJ): 0.130ns
|
|
Phase Error (PE): 0.000ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock cpu_clk rise edge) 0.000 0.000 r
|
|
clock source latency -6.275 -6.275
|
|
propagated clock network latency
|
|
4.051 -2.225
|
|
SLICE_X35Y35 FDRE 0.000 -2.225 r u_cpu/addr_trans/data_vaddr_buffer_reg[14]/C
|
|
SLICE_X35Y35 FDRE (Prop_fdre_C_Q) 0.456 -1.769 r u_cpu/addr_trans/data_vaddr_buffer_reg[14]/Q
|
|
net (fo=33, routed) 1.442 -0.326 u_cpu/addr_trans/tlb_entry/data_vaddr_buffer[2]
|
|
SLICE_X42Y40 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_226/I5
|
|
SLICE_X42Y40 LUT6 (Prop_lut6_I5_O) 0.124 -0.202 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_226/O
|
|
net (fo=1, routed) 0.000 -0.202 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_226_n_0
|
|
SLICE_X42Y40 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_111/S[0]
|
|
SLICE_X42Y40 CARRY4 (Prop_carry4_S[0]_CO[3])
|
|
0.513 0.311 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_111/CO[3]
|
|
net (fo=1, routed) 0.000 0.311 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_111_n_0
|
|
SLICE_X42Y41 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_32/CI
|
|
SLICE_X42Y41 CARRY4 (Prop_carry4_CI_CO[2])
|
|
0.229 0.540 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_32/CO[2]
|
|
net (fo=1, routed) 1.009 1.549 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_32_n_1
|
|
SLICE_X40Y47 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_9/I1
|
|
SLICE_X40Y47 LUT6 (Prop_lut6_I1_O) 0.310 1.859 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_9/O
|
|
net (fo=2, routed) 0.635 2.494 u_cpu/addr_trans/tlb_entry/match1[28]
|
|
SLICE_X38Y47 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/I2
|
|
SLICE_X38Y47 LUT4 (Prop_lut4_I2_O) 0.124 2.618 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/O
|
|
net (fo=2, routed) 0.667 3.285 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2_n_0
|
|
SLICE_X39Y47 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/I0
|
|
SLICE_X39Y47 LUT5 (Prop_lut5_I0_O) 0.124 3.409 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/O
|
|
net (fo=2, routed) 1.103 4.512 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2_n_0
|
|
SLICE_X38Y50 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/I0
|
|
SLICE_X38Y50 LUT6 (Prop_lut6_I0_O) 0.124 4.636 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/O
|
|
net (fo=89, routed) 1.162 5.797 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus[8]
|
|
SLICE_X42Y51 r u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_38__0/S
|
|
SLICE_X42Y51 MUXF7 (Prop_muxf7_S_O) 0.292 6.089 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_38__0/O
|
|
net (fo=1, routed) 0.000 6.089 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_38__0_n_0
|
|
SLICE_X42Y51 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_16__0/I1
|
|
SLICE_X42Y51 MUXF8 (Prop_muxf8_I1_O) 0.088 6.177 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_16__0/O
|
|
net (fo=1, routed) 0.957 7.134 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_16__0_n_0
|
|
SLICE_X42Y50 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7/I0
|
|
SLICE_X42Y50 LUT6 (Prop_lut6_I0_O) 0.319 7.453 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7/O
|
|
net (fo=1, routed) 0.435 7.888 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7_n_0
|
|
SLICE_X44Y50 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0/I5
|
|
SLICE_X44Y50 LUT6 (Prop_lut6_I5_O) 0.124 8.012 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0/O
|
|
net (fo=10, routed) 0.740 8.753 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0_n_0
|
|
SLICE_X44Y50 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[5]_i_1__0/I3
|
|
SLICE_X44Y50 LUT6 (Prop_lut6_I3_O) 0.124 8.877 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[5]_i_1__0/O
|
|
net (fo=6, routed) 0.845 9.722 u_cpu/u_csr/ms_to_ws_bus[13]
|
|
SLICE_X50Y46 r u_cpu/u_csr/write_buffer_way[1]_i_18/I3
|
|
SLICE_X50Y46 LUT6 (Prop_lut6_I3_O) 0.124 9.846 r u_cpu/u_csr/write_buffer_way[1]_i_18/O
|
|
net (fo=1, routed) 0.000 9.846 u_cpu/u_csr/write_buffer_way[1]_i_18_n_0
|
|
SLICE_X50Y46 r u_cpu/u_csr/write_buffer_way_reg[1]_i_11/S[0]
|
|
SLICE_X50Y46 CARRY4 (Prop_carry4_S[0]_CO[3])
|
|
0.532 10.378 r u_cpu/u_csr/write_buffer_way_reg[1]_i_11/CO[3]
|
|
net (fo=1, routed) 0.000 10.378 u_cpu/u_csr/write_buffer_way_reg[1]_i_11_n_0
|
|
SLICE_X50Y47 r u_cpu/u_csr/write_buffer_way_reg[1]_i_9/CI
|
|
SLICE_X50Y47 CARRY4 (Prop_carry4_CI_CO[1])
|
|
0.157 10.535 f u_cpu/u_csr/write_buffer_way_reg[1]_i_9/CO[1]
|
|
net (fo=2, routed) 0.791 11.326 u_cpu/wb_stage/CO[0]
|
|
SLICE_X46Y39 f u_cpu/wb_stage/write_buffer_way[1]_i_5/I1
|
|
SLICE_X46Y39 LUT6 (Prop_lut6_I1_O) 0.329 11.655 r u_cpu/wb_stage/write_buffer_way[1]_i_5/O
|
|
net (fo=7, routed) 0.762 12.417 u_cpu/addr_trans/tlb_entry/sc_cancel_req
|
|
SLICE_X46Y35 r u_cpu/addr_trans/tlb_entry/main_state[0]_i_3/I1
|
|
SLICE_X46Y35 LUT3 (Prop_lut3_I1_O) 0.124 12.541 r u_cpu/addr_trans/tlb_entry/main_state[0]_i_3/O
|
|
net (fo=3, routed) 0.719 13.260 u_cpu/dcache/main_state_reg[0]_2
|
|
SLICE_X43Y31 r u_cpu/dcache/ds_to_es_bus_r[235]_i_10/I3
|
|
SLICE_X43Y31 LUT6 (Prop_lut6_I3_O) 0.124 13.384 r u_cpu/dcache/ds_to_es_bus_r[235]_i_10/O
|
|
net (fo=3, routed) 0.415 13.799 u_cpu/mem_stage/data_data_ok
|
|
SLICE_X43Y30 r u_cpu/mem_stage/flush_inst_req_buffer[1]_i_15/I0
|
|
SLICE_X43Y30 LUT3 (Prop_lut3_I0_O) 0.124 13.923 r u_cpu/mem_stage/flush_inst_req_buffer[1]_i_15/O
|
|
net (fo=2, routed) 0.833 14.756 u_cpu/mem_stage/es_to_ms_bus_r_reg[70]_1
|
|
SLICE_X48Y30 r u_cpu/mem_stage/flush_inst_req_buffer[1]_i_14/I0
|
|
SLICE_X48Y30 LUT6 (Prop_lut6_I0_O) 0.124 14.880 r u_cpu/mem_stage/flush_inst_req_buffer[1]_i_14/O
|
|
net (fo=1, routed) 0.651 15.532 u_cpu/mem_stage/ms_ready_go
|
|
SLICE_X48Y25 r u_cpu/mem_stage/flush_inst_req_buffer[1]_i_13/I4
|
|
SLICE_X48Y25 LUT6 (Prop_lut6_I4_O) 0.124 15.656 r u_cpu/mem_stage/flush_inst_req_buffer[1]_i_13/O
|
|
net (fo=3, routed) 0.483 16.139 u_cpu/id_stage/flush_inst_req_buffer[31]_i_6
|
|
SLICE_X50Y25 r u_cpu/id_stage/flush_inst_req_buffer[1]_i_9/I1
|
|
SLICE_X50Y25 LUT6 (Prop_lut6_I1_O) 0.124 16.263 r u_cpu/id_stage/flush_inst_req_buffer[1]_i_9/O
|
|
net (fo=32, routed) 0.531 16.794 u_cpu/if_stage/nextpc5
|
|
SLICE_X51Y27 r u_cpu/if_stage/fetch_pc_r[6]_i_4/I2
|
|
SLICE_X51Y27 LUT6 (Prop_lut6_I2_O) 0.124 16.918 r u_cpu/if_stage/fetch_pc_r[6]_i_4/O
|
|
net (fo=1, routed) 3.059 19.977 u_cpu/if_stage/fetch_pc_r[6]_i_4_n_0
|
|
SLICE_X114Y28 r u_cpu/if_stage/fetch_pc_r[6]_i_2/I2
|
|
SLICE_X114Y28 LUT6 (Prop_lut6_I2_O) 0.124 20.101 r u_cpu/if_stage/fetch_pc_r[6]_i_2/O
|
|
net (fo=1, routed) 0.441 20.542 u_cpu/if_stage/fetch_pc_r[6]_i_2_n_0
|
|
SLICE_X114Y25 r u_cpu/if_stage/fetch_pc_r[6]_i_1/I2
|
|
SLICE_X114Y25 LUT6 (Prop_lut6_I2_O) 0.124 20.666 r u_cpu/if_stage/fetch_pc_r[6]_i_1/O
|
|
net (fo=6, routed) 3.249 23.915 u_cpu/icache/tagv_ram_way[1].u/mem_reg_reg_2[2]
|
|
SLICE_X49Y33 r u_cpu/icache/tagv_ram_way[1].u/mem_reg_reg_i_8/I4
|
|
SLICE_X49Y33 LUT5 (Prop_lut5_I4_O) 0.124 24.039 r u_cpu/icache/tagv_ram_way[1].u/mem_reg_reg_i_8/O
|
|
net (fo=16, routed) 1.412 25.451 u_cpu/icache/data_ram_way[0].data_ram_bank[0].u/ADDRBWRADDR[2]
|
|
RAMB18_X2Y4 RAMB18E1 r u_cpu/icache/data_ram_way[0].data_ram_bank[0].u/mem_reg_reg/ADDRARDADDR[7]
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock cpu_clk rise edge) 30.323 30.323 r
|
|
clock source latency -5.674 24.648
|
|
propagated clock network latency
|
|
3.777 28.425
|
|
clock pessimism -0.418 28.007
|
|
clock uncertainty -0.074 27.933
|
|
RAMB18_X2Y4 RAMB18E1 (Setup_ramb18e1_CLKARDCLK_ADDRARDADDR[7])
|
|
-0.566 27.367 u_cpu/icache/data_ram_way[0].data_ram_bank[0].u/mem_reg_reg
|
|
-------------------------------------------------------------------
|
|
required time 27.367
|
|
arrival time -25.451
|
|
-------------------------------------------------------------------
|
|
slack 1.916
|
|
|
|
Slack (MET) : 1.916ns (required time - arrival time)
|
|
Source: u_cpu/addr_trans/data_vaddr_buffer_reg[14]/C
|
|
(rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns})
|
|
Destination: u_cpu/icache/data_ram_way[0].data_ram_bank[0].u/mem_reg_reg/ADDRARDADDR[7]
|
|
(rising edge-triggered cell RAMB18E1 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns})
|
|
Path Group: cpu_clk
|
|
Path Type: Setup (Max at Slow Process Corner)
|
|
Requirement: 30.323ns (cpu_clk rise@30.323ns - cpu_clk rise@0.000ns)
|
|
Data Path Delay: 27.676ns (logic 5.333ns (19.269%) route 22.343ns (80.731%))
|
|
Logic Levels: 26 (CARRY4=4 LUT3=2 LUT4=1 LUT5=2 LUT6=15 MUXF7=1 MUXF8=1)
|
|
Clock Path Skew: -0.091ns (DCD - SCD + CPR)
|
|
Destination Clock Delay (DCD): -1.897ns = ( 28.425 - 30.323 )
|
|
Source Clock Delay (SCD): -2.225ns
|
|
Clock Pessimism Removal (CPR): -0.418ns
|
|
Clock Uncertainty: 0.074ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Discrete Jitter (DJ): 0.130ns
|
|
Phase Error (PE): 0.000ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock cpu_clk rise edge) 0.000 0.000 r
|
|
clock source latency -6.275 -6.275
|
|
propagated clock network latency
|
|
4.051 -2.225
|
|
SLICE_X35Y35 FDRE 0.000 -2.225 r u_cpu/addr_trans/data_vaddr_buffer_reg[14]/C
|
|
SLICE_X35Y35 FDRE (Prop_fdre_C_Q) 0.456 -1.769 r u_cpu/addr_trans/data_vaddr_buffer_reg[14]/Q
|
|
net (fo=33, routed) 1.442 -0.326 u_cpu/addr_trans/tlb_entry/data_vaddr_buffer[2]
|
|
SLICE_X42Y40 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_226/I5
|
|
SLICE_X42Y40 LUT6 (Prop_lut6_I5_O) 0.124 -0.202 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_226/O
|
|
net (fo=1, routed) 0.000 -0.202 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_226_n_0
|
|
SLICE_X42Y40 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_111/S[0]
|
|
SLICE_X42Y40 CARRY4 (Prop_carry4_S[0]_CO[3])
|
|
0.513 0.311 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_111/CO[3]
|
|
net (fo=1, routed) 0.000 0.311 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_111_n_0
|
|
SLICE_X42Y41 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_32/CI
|
|
SLICE_X42Y41 CARRY4 (Prop_carry4_CI_CO[2])
|
|
0.229 0.540 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_32/CO[2]
|
|
net (fo=1, routed) 1.009 1.549 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_32_n_1
|
|
SLICE_X40Y47 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_9/I1
|
|
SLICE_X40Y47 LUT6 (Prop_lut6_I1_O) 0.310 1.859 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_9/O
|
|
net (fo=2, routed) 0.635 2.494 u_cpu/addr_trans/tlb_entry/match1[28]
|
|
SLICE_X38Y47 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/I2
|
|
SLICE_X38Y47 LUT4 (Prop_lut4_I2_O) 0.124 2.618 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/O
|
|
net (fo=2, routed) 0.667 3.285 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2_n_0
|
|
SLICE_X39Y47 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/I0
|
|
SLICE_X39Y47 LUT5 (Prop_lut5_I0_O) 0.124 3.409 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/O
|
|
net (fo=2, routed) 1.103 4.512 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2_n_0
|
|
SLICE_X38Y50 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/I0
|
|
SLICE_X38Y50 LUT6 (Prop_lut6_I0_O) 0.124 4.636 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/O
|
|
net (fo=89, routed) 1.162 5.797 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus[8]
|
|
SLICE_X42Y51 r u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_38__0/S
|
|
SLICE_X42Y51 MUXF7 (Prop_muxf7_S_O) 0.292 6.089 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_38__0/O
|
|
net (fo=1, routed) 0.000 6.089 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_38__0_n_0
|
|
SLICE_X42Y51 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_16__0/I1
|
|
SLICE_X42Y51 MUXF8 (Prop_muxf8_I1_O) 0.088 6.177 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_16__0/O
|
|
net (fo=1, routed) 0.957 7.134 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_16__0_n_0
|
|
SLICE_X42Y50 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7/I0
|
|
SLICE_X42Y50 LUT6 (Prop_lut6_I0_O) 0.319 7.453 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7/O
|
|
net (fo=1, routed) 0.435 7.888 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7_n_0
|
|
SLICE_X44Y50 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0/I5
|
|
SLICE_X44Y50 LUT6 (Prop_lut6_I5_O) 0.124 8.012 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0/O
|
|
net (fo=10, routed) 0.740 8.753 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0_n_0
|
|
SLICE_X44Y50 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[5]_i_1__0/I3
|
|
SLICE_X44Y50 LUT6 (Prop_lut6_I3_O) 0.124 8.877 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[5]_i_1__0/O
|
|
net (fo=6, routed) 0.845 9.722 u_cpu/u_csr/ms_to_ws_bus[13]
|
|
SLICE_X50Y46 f u_cpu/u_csr/write_buffer_way[1]_i_18/I3
|
|
SLICE_X50Y46 LUT6 (Prop_lut6_I3_O) 0.124 9.846 r u_cpu/u_csr/write_buffer_way[1]_i_18/O
|
|
net (fo=1, routed) 0.000 9.846 u_cpu/u_csr/write_buffer_way[1]_i_18_n_0
|
|
SLICE_X50Y46 r u_cpu/u_csr/write_buffer_way_reg[1]_i_11/S[0]
|
|
SLICE_X50Y46 CARRY4 (Prop_carry4_S[0]_CO[3])
|
|
0.532 10.378 r u_cpu/u_csr/write_buffer_way_reg[1]_i_11/CO[3]
|
|
net (fo=1, routed) 0.000 10.378 u_cpu/u_csr/write_buffer_way_reg[1]_i_11_n_0
|
|
SLICE_X50Y47 r u_cpu/u_csr/write_buffer_way_reg[1]_i_9/CI
|
|
SLICE_X50Y47 CARRY4 (Prop_carry4_CI_CO[1])
|
|
0.157 10.535 f u_cpu/u_csr/write_buffer_way_reg[1]_i_9/CO[1]
|
|
net (fo=2, routed) 0.791 11.326 u_cpu/wb_stage/CO[0]
|
|
SLICE_X46Y39 f u_cpu/wb_stage/write_buffer_way[1]_i_5/I1
|
|
SLICE_X46Y39 LUT6 (Prop_lut6_I1_O) 0.329 11.655 r u_cpu/wb_stage/write_buffer_way[1]_i_5/O
|
|
net (fo=7, routed) 0.762 12.417 u_cpu/addr_trans/tlb_entry/sc_cancel_req
|
|
SLICE_X46Y35 r u_cpu/addr_trans/tlb_entry/main_state[0]_i_3/I1
|
|
SLICE_X46Y35 LUT3 (Prop_lut3_I1_O) 0.124 12.541 r u_cpu/addr_trans/tlb_entry/main_state[0]_i_3/O
|
|
net (fo=3, routed) 0.719 13.260 u_cpu/dcache/main_state_reg[0]_2
|
|
SLICE_X43Y31 r u_cpu/dcache/ds_to_es_bus_r[235]_i_10/I3
|
|
SLICE_X43Y31 LUT6 (Prop_lut6_I3_O) 0.124 13.384 r u_cpu/dcache/ds_to_es_bus_r[235]_i_10/O
|
|
net (fo=3, routed) 0.415 13.799 u_cpu/mem_stage/data_data_ok
|
|
SLICE_X43Y30 r u_cpu/mem_stage/flush_inst_req_buffer[1]_i_15/I0
|
|
SLICE_X43Y30 LUT3 (Prop_lut3_I0_O) 0.124 13.923 r u_cpu/mem_stage/flush_inst_req_buffer[1]_i_15/O
|
|
net (fo=2, routed) 0.833 14.756 u_cpu/mem_stage/es_to_ms_bus_r_reg[70]_1
|
|
SLICE_X48Y30 r u_cpu/mem_stage/flush_inst_req_buffer[1]_i_14/I0
|
|
SLICE_X48Y30 LUT6 (Prop_lut6_I0_O) 0.124 14.880 r u_cpu/mem_stage/flush_inst_req_buffer[1]_i_14/O
|
|
net (fo=1, routed) 0.651 15.532 u_cpu/mem_stage/ms_ready_go
|
|
SLICE_X48Y25 r u_cpu/mem_stage/flush_inst_req_buffer[1]_i_13/I4
|
|
SLICE_X48Y25 LUT6 (Prop_lut6_I4_O) 0.124 15.656 r u_cpu/mem_stage/flush_inst_req_buffer[1]_i_13/O
|
|
net (fo=3, routed) 0.483 16.139 u_cpu/id_stage/flush_inst_req_buffer[31]_i_6
|
|
SLICE_X50Y25 r u_cpu/id_stage/flush_inst_req_buffer[1]_i_9/I1
|
|
SLICE_X50Y25 LUT6 (Prop_lut6_I1_O) 0.124 16.263 r u_cpu/id_stage/flush_inst_req_buffer[1]_i_9/O
|
|
net (fo=32, routed) 0.531 16.794 u_cpu/if_stage/nextpc5
|
|
SLICE_X51Y27 r u_cpu/if_stage/fetch_pc_r[6]_i_4/I2
|
|
SLICE_X51Y27 LUT6 (Prop_lut6_I2_O) 0.124 16.918 r u_cpu/if_stage/fetch_pc_r[6]_i_4/O
|
|
net (fo=1, routed) 3.059 19.977 u_cpu/if_stage/fetch_pc_r[6]_i_4_n_0
|
|
SLICE_X114Y28 r u_cpu/if_stage/fetch_pc_r[6]_i_2/I2
|
|
SLICE_X114Y28 LUT6 (Prop_lut6_I2_O) 0.124 20.101 r u_cpu/if_stage/fetch_pc_r[6]_i_2/O
|
|
net (fo=1, routed) 0.441 20.542 u_cpu/if_stage/fetch_pc_r[6]_i_2_n_0
|
|
SLICE_X114Y25 r u_cpu/if_stage/fetch_pc_r[6]_i_1/I2
|
|
SLICE_X114Y25 LUT6 (Prop_lut6_I2_O) 0.124 20.666 r u_cpu/if_stage/fetch_pc_r[6]_i_1/O
|
|
net (fo=6, routed) 3.249 23.915 u_cpu/icache/tagv_ram_way[1].u/mem_reg_reg_2[2]
|
|
SLICE_X49Y33 r u_cpu/icache/tagv_ram_way[1].u/mem_reg_reg_i_8/I4
|
|
SLICE_X49Y33 LUT5 (Prop_lut5_I4_O) 0.124 24.039 r u_cpu/icache/tagv_ram_way[1].u/mem_reg_reg_i_8/O
|
|
net (fo=16, routed) 1.412 25.451 u_cpu/icache/data_ram_way[0].data_ram_bank[0].u/ADDRBWRADDR[2]
|
|
RAMB18_X2Y4 RAMB18E1 r u_cpu/icache/data_ram_way[0].data_ram_bank[0].u/mem_reg_reg/ADDRARDADDR[7]
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock cpu_clk rise edge) 30.323 30.323 r
|
|
clock source latency -5.674 24.648
|
|
propagated clock network latency
|
|
3.777 28.425
|
|
clock pessimism -0.418 28.007
|
|
clock uncertainty -0.074 27.933
|
|
RAMB18_X2Y4 RAMB18E1 (Setup_ramb18e1_CLKARDCLK_ADDRARDADDR[7])
|
|
-0.566 27.367 u_cpu/icache/data_ram_way[0].data_ram_bank[0].u/mem_reg_reg
|
|
-------------------------------------------------------------------
|
|
required time 27.367
|
|
arrival time -25.451
|
|
-------------------------------------------------------------------
|
|
slack 1.916
|
|
|
|
Slack (MET) : 1.916ns (required time - arrival time)
|
|
Source: u_cpu/addr_trans/data_vaddr_buffer_reg[14]/C
|
|
(rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns})
|
|
Destination: u_cpu/icache/data_ram_way[0].data_ram_bank[0].u/mem_reg_reg/ADDRARDADDR[7]
|
|
(rising edge-triggered cell RAMB18E1 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns})
|
|
Path Group: cpu_clk
|
|
Path Type: Setup (Max at Slow Process Corner)
|
|
Requirement: 30.323ns (cpu_clk rise@30.323ns - cpu_clk rise@0.000ns)
|
|
Data Path Delay: 27.676ns (logic 5.333ns (19.269%) route 22.343ns (80.731%))
|
|
Logic Levels: 26 (CARRY4=4 LUT3=2 LUT4=1 LUT5=2 LUT6=15 MUXF7=1 MUXF8=1)
|
|
Clock Path Skew: -0.091ns (DCD - SCD + CPR)
|
|
Destination Clock Delay (DCD): -1.897ns = ( 28.425 - 30.323 )
|
|
Source Clock Delay (SCD): -2.225ns
|
|
Clock Pessimism Removal (CPR): -0.418ns
|
|
Clock Uncertainty: 0.074ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Discrete Jitter (DJ): 0.130ns
|
|
Phase Error (PE): 0.000ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock cpu_clk rise edge) 0.000 0.000 r
|
|
clock source latency -6.275 -6.275
|
|
propagated clock network latency
|
|
4.051 -2.225
|
|
SLICE_X35Y35 FDRE 0.000 -2.225 r u_cpu/addr_trans/data_vaddr_buffer_reg[14]/C
|
|
SLICE_X35Y35 FDRE (Prop_fdre_C_Q) 0.456 -1.769 r u_cpu/addr_trans/data_vaddr_buffer_reg[14]/Q
|
|
net (fo=33, routed) 1.442 -0.326 u_cpu/addr_trans/tlb_entry/data_vaddr_buffer[2]
|
|
SLICE_X42Y40 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_226/I5
|
|
SLICE_X42Y40 LUT6 (Prop_lut6_I5_O) 0.124 -0.202 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_226/O
|
|
net (fo=1, routed) 0.000 -0.202 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_226_n_0
|
|
SLICE_X42Y40 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_111/S[0]
|
|
SLICE_X42Y40 CARRY4 (Prop_carry4_S[0]_CO[3])
|
|
0.513 0.311 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_111/CO[3]
|
|
net (fo=1, routed) 0.000 0.311 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_111_n_0
|
|
SLICE_X42Y41 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_32/CI
|
|
SLICE_X42Y41 CARRY4 (Prop_carry4_CI_CO[2])
|
|
0.229 0.540 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_32/CO[2]
|
|
net (fo=1, routed) 1.009 1.549 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_32_n_1
|
|
SLICE_X40Y47 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_9/I1
|
|
SLICE_X40Y47 LUT6 (Prop_lut6_I1_O) 0.310 1.859 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_9/O
|
|
net (fo=2, routed) 0.635 2.494 u_cpu/addr_trans/tlb_entry/match1[28]
|
|
SLICE_X38Y47 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/I2
|
|
SLICE_X38Y47 LUT4 (Prop_lut4_I2_O) 0.124 2.618 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/O
|
|
net (fo=2, routed) 0.667 3.285 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2_n_0
|
|
SLICE_X39Y47 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/I0
|
|
SLICE_X39Y47 LUT5 (Prop_lut5_I0_O) 0.124 3.409 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/O
|
|
net (fo=2, routed) 1.103 4.512 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2_n_0
|
|
SLICE_X38Y50 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/I0
|
|
SLICE_X38Y50 LUT6 (Prop_lut6_I0_O) 0.124 4.636 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/O
|
|
net (fo=89, routed) 1.162 5.797 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus[8]
|
|
SLICE_X42Y51 r u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_38__0/S
|
|
SLICE_X42Y51 MUXF7 (Prop_muxf7_S_O) 0.292 6.089 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_38__0/O
|
|
net (fo=1, routed) 0.000 6.089 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_38__0_n_0
|
|
SLICE_X42Y51 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_16__0/I1
|
|
SLICE_X42Y51 MUXF8 (Prop_muxf8_I1_O) 0.088 6.177 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_16__0/O
|
|
net (fo=1, routed) 0.957 7.134 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_16__0_n_0
|
|
SLICE_X42Y50 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7/I0
|
|
SLICE_X42Y50 LUT6 (Prop_lut6_I0_O) 0.319 7.453 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7/O
|
|
net (fo=1, routed) 0.435 7.888 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7_n_0
|
|
SLICE_X44Y50 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0/I5
|
|
SLICE_X44Y50 LUT6 (Prop_lut6_I5_O) 0.124 8.012 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0/O
|
|
net (fo=10, routed) 0.740 8.753 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0_n_0
|
|
SLICE_X44Y50 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[5]_i_1__0/I3
|
|
SLICE_X44Y50 LUT6 (Prop_lut6_I3_O) 0.124 8.877 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[5]_i_1__0/O
|
|
net (fo=6, routed) 0.845 9.722 u_cpu/u_csr/ms_to_ws_bus[13]
|
|
SLICE_X50Y46 r u_cpu/u_csr/write_buffer_way[1]_i_18/I3
|
|
SLICE_X50Y46 LUT6 (Prop_lut6_I3_O) 0.124 9.846 f u_cpu/u_csr/write_buffer_way[1]_i_18/O
|
|
net (fo=1, routed) 0.000 9.846 u_cpu/u_csr/write_buffer_way[1]_i_18_n_0
|
|
SLICE_X50Y46 f u_cpu/u_csr/write_buffer_way_reg[1]_i_11/S[0]
|
|
SLICE_X50Y46 CARRY4 (Prop_carry4_S[0]_CO[3])
|
|
0.532 10.378 r u_cpu/u_csr/write_buffer_way_reg[1]_i_11/CO[3]
|
|
net (fo=1, routed) 0.000 10.378 u_cpu/u_csr/write_buffer_way_reg[1]_i_11_n_0
|
|
SLICE_X50Y47 r u_cpu/u_csr/write_buffer_way_reg[1]_i_9/CI
|
|
SLICE_X50Y47 CARRY4 (Prop_carry4_CI_CO[1])
|
|
0.157 10.535 f u_cpu/u_csr/write_buffer_way_reg[1]_i_9/CO[1]
|
|
net (fo=2, routed) 0.791 11.326 u_cpu/wb_stage/CO[0]
|
|
SLICE_X46Y39 f u_cpu/wb_stage/write_buffer_way[1]_i_5/I1
|
|
SLICE_X46Y39 LUT6 (Prop_lut6_I1_O) 0.329 11.655 r u_cpu/wb_stage/write_buffer_way[1]_i_5/O
|
|
net (fo=7, routed) 0.762 12.417 u_cpu/addr_trans/tlb_entry/sc_cancel_req
|
|
SLICE_X46Y35 r u_cpu/addr_trans/tlb_entry/main_state[0]_i_3/I1
|
|
SLICE_X46Y35 LUT3 (Prop_lut3_I1_O) 0.124 12.541 r u_cpu/addr_trans/tlb_entry/main_state[0]_i_3/O
|
|
net (fo=3, routed) 0.719 13.260 u_cpu/dcache/main_state_reg[0]_2
|
|
SLICE_X43Y31 r u_cpu/dcache/ds_to_es_bus_r[235]_i_10/I3
|
|
SLICE_X43Y31 LUT6 (Prop_lut6_I3_O) 0.124 13.384 r u_cpu/dcache/ds_to_es_bus_r[235]_i_10/O
|
|
net (fo=3, routed) 0.415 13.799 u_cpu/mem_stage/data_data_ok
|
|
SLICE_X43Y30 r u_cpu/mem_stage/flush_inst_req_buffer[1]_i_15/I0
|
|
SLICE_X43Y30 LUT3 (Prop_lut3_I0_O) 0.124 13.923 r u_cpu/mem_stage/flush_inst_req_buffer[1]_i_15/O
|
|
net (fo=2, routed) 0.833 14.756 u_cpu/mem_stage/es_to_ms_bus_r_reg[70]_1
|
|
SLICE_X48Y30 r u_cpu/mem_stage/flush_inst_req_buffer[1]_i_14/I0
|
|
SLICE_X48Y30 LUT6 (Prop_lut6_I0_O) 0.124 14.880 r u_cpu/mem_stage/flush_inst_req_buffer[1]_i_14/O
|
|
net (fo=1, routed) 0.651 15.532 u_cpu/mem_stage/ms_ready_go
|
|
SLICE_X48Y25 r u_cpu/mem_stage/flush_inst_req_buffer[1]_i_13/I4
|
|
SLICE_X48Y25 LUT6 (Prop_lut6_I4_O) 0.124 15.656 r u_cpu/mem_stage/flush_inst_req_buffer[1]_i_13/O
|
|
net (fo=3, routed) 0.483 16.139 u_cpu/id_stage/flush_inst_req_buffer[31]_i_6
|
|
SLICE_X50Y25 r u_cpu/id_stage/flush_inst_req_buffer[1]_i_9/I1
|
|
SLICE_X50Y25 LUT6 (Prop_lut6_I1_O) 0.124 16.263 r u_cpu/id_stage/flush_inst_req_buffer[1]_i_9/O
|
|
net (fo=32, routed) 0.531 16.794 u_cpu/if_stage/nextpc5
|
|
SLICE_X51Y27 r u_cpu/if_stage/fetch_pc_r[6]_i_4/I2
|
|
SLICE_X51Y27 LUT6 (Prop_lut6_I2_O) 0.124 16.918 r u_cpu/if_stage/fetch_pc_r[6]_i_4/O
|
|
net (fo=1, routed) 3.059 19.977 u_cpu/if_stage/fetch_pc_r[6]_i_4_n_0
|
|
SLICE_X114Y28 r u_cpu/if_stage/fetch_pc_r[6]_i_2/I2
|
|
SLICE_X114Y28 LUT6 (Prop_lut6_I2_O) 0.124 20.101 r u_cpu/if_stage/fetch_pc_r[6]_i_2/O
|
|
net (fo=1, routed) 0.441 20.542 u_cpu/if_stage/fetch_pc_r[6]_i_2_n_0
|
|
SLICE_X114Y25 r u_cpu/if_stage/fetch_pc_r[6]_i_1/I2
|
|
SLICE_X114Y25 LUT6 (Prop_lut6_I2_O) 0.124 20.666 r u_cpu/if_stage/fetch_pc_r[6]_i_1/O
|
|
net (fo=6, routed) 3.249 23.915 u_cpu/icache/tagv_ram_way[1].u/mem_reg_reg_2[2]
|
|
SLICE_X49Y33 r u_cpu/icache/tagv_ram_way[1].u/mem_reg_reg_i_8/I4
|
|
SLICE_X49Y33 LUT5 (Prop_lut5_I4_O) 0.124 24.039 r u_cpu/icache/tagv_ram_way[1].u/mem_reg_reg_i_8/O
|
|
net (fo=16, routed) 1.412 25.451 u_cpu/icache/data_ram_way[0].data_ram_bank[0].u/ADDRBWRADDR[2]
|
|
RAMB18_X2Y4 RAMB18E1 r u_cpu/icache/data_ram_way[0].data_ram_bank[0].u/mem_reg_reg/ADDRARDADDR[7]
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock cpu_clk rise edge) 30.323 30.323 r
|
|
clock source latency -5.674 24.648
|
|
propagated clock network latency
|
|
3.777 28.425
|
|
clock pessimism -0.418 28.007
|
|
clock uncertainty -0.074 27.933
|
|
RAMB18_X2Y4 RAMB18E1 (Setup_ramb18e1_CLKARDCLK_ADDRARDADDR[7])
|
|
-0.566 27.367 u_cpu/icache/data_ram_way[0].data_ram_bank[0].u/mem_reg_reg
|
|
-------------------------------------------------------------------
|
|
required time 27.367
|
|
arrival time -25.451
|
|
-------------------------------------------------------------------
|
|
slack 1.916
|
|
|
|
Slack (MET) : 1.916ns (required time - arrival time)
|
|
Source: u_cpu/addr_trans/data_vaddr_buffer_reg[14]/C
|
|
(rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns})
|
|
Destination: u_cpu/icache/data_ram_way[0].data_ram_bank[0].u/mem_reg_reg/ADDRARDADDR[7]
|
|
(rising edge-triggered cell RAMB18E1 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns})
|
|
Path Group: cpu_clk
|
|
Path Type: Setup (Max at Slow Process Corner)
|
|
Requirement: 30.323ns (cpu_clk rise@30.323ns - cpu_clk rise@0.000ns)
|
|
Data Path Delay: 27.676ns (logic 5.333ns (19.269%) route 22.343ns (80.731%))
|
|
Logic Levels: 26 (CARRY4=4 LUT3=2 LUT4=1 LUT5=2 LUT6=15 MUXF7=1 MUXF8=1)
|
|
Clock Path Skew: -0.091ns (DCD - SCD + CPR)
|
|
Destination Clock Delay (DCD): -1.897ns = ( 28.425 - 30.323 )
|
|
Source Clock Delay (SCD): -2.225ns
|
|
Clock Pessimism Removal (CPR): -0.418ns
|
|
Clock Uncertainty: 0.074ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Discrete Jitter (DJ): 0.130ns
|
|
Phase Error (PE): 0.000ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock cpu_clk rise edge) 0.000 0.000 r
|
|
clock source latency -6.275 -6.275
|
|
propagated clock network latency
|
|
4.051 -2.225
|
|
SLICE_X35Y35 FDRE 0.000 -2.225 r u_cpu/addr_trans/data_vaddr_buffer_reg[14]/C
|
|
SLICE_X35Y35 FDRE (Prop_fdre_C_Q) 0.456 -1.769 r u_cpu/addr_trans/data_vaddr_buffer_reg[14]/Q
|
|
net (fo=33, routed) 1.442 -0.326 u_cpu/addr_trans/tlb_entry/data_vaddr_buffer[2]
|
|
SLICE_X42Y40 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_226/I5
|
|
SLICE_X42Y40 LUT6 (Prop_lut6_I5_O) 0.124 -0.202 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_226/O
|
|
net (fo=1, routed) 0.000 -0.202 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_226_n_0
|
|
SLICE_X42Y40 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_111/S[0]
|
|
SLICE_X42Y40 CARRY4 (Prop_carry4_S[0]_CO[3])
|
|
0.513 0.311 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_111/CO[3]
|
|
net (fo=1, routed) 0.000 0.311 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_111_n_0
|
|
SLICE_X42Y41 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_32/CI
|
|
SLICE_X42Y41 CARRY4 (Prop_carry4_CI_CO[2])
|
|
0.229 0.540 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_32/CO[2]
|
|
net (fo=1, routed) 1.009 1.549 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_32_n_1
|
|
SLICE_X40Y47 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_9/I1
|
|
SLICE_X40Y47 LUT6 (Prop_lut6_I1_O) 0.310 1.859 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_9/O
|
|
net (fo=2, routed) 0.635 2.494 u_cpu/addr_trans/tlb_entry/match1[28]
|
|
SLICE_X38Y47 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/I2
|
|
SLICE_X38Y47 LUT4 (Prop_lut4_I2_O) 0.124 2.618 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/O
|
|
net (fo=2, routed) 0.667 3.285 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2_n_0
|
|
SLICE_X39Y47 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/I0
|
|
SLICE_X39Y47 LUT5 (Prop_lut5_I0_O) 0.124 3.409 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/O
|
|
net (fo=2, routed) 1.103 4.512 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2_n_0
|
|
SLICE_X38Y50 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/I0
|
|
SLICE_X38Y50 LUT6 (Prop_lut6_I0_O) 0.124 4.636 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/O
|
|
net (fo=89, routed) 1.162 5.797 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus[8]
|
|
SLICE_X42Y51 r u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_38__0/S
|
|
SLICE_X42Y51 MUXF7 (Prop_muxf7_S_O) 0.292 6.089 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_38__0/O
|
|
net (fo=1, routed) 0.000 6.089 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_38__0_n_0
|
|
SLICE_X42Y51 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_16__0/I1
|
|
SLICE_X42Y51 MUXF8 (Prop_muxf8_I1_O) 0.088 6.177 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_16__0/O
|
|
net (fo=1, routed) 0.957 7.134 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_16__0_n_0
|
|
SLICE_X42Y50 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7/I0
|
|
SLICE_X42Y50 LUT6 (Prop_lut6_I0_O) 0.319 7.453 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7/O
|
|
net (fo=1, routed) 0.435 7.888 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7_n_0
|
|
SLICE_X44Y50 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0/I5
|
|
SLICE_X44Y50 LUT6 (Prop_lut6_I5_O) 0.124 8.012 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0/O
|
|
net (fo=10, routed) 0.740 8.753 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0_n_0
|
|
SLICE_X44Y50 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[5]_i_1__0/I3
|
|
SLICE_X44Y50 LUT6 (Prop_lut6_I3_O) 0.124 8.877 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[5]_i_1__0/O
|
|
net (fo=6, routed) 0.845 9.722 u_cpu/u_csr/ms_to_ws_bus[13]
|
|
SLICE_X50Y46 f u_cpu/u_csr/write_buffer_way[1]_i_18/I3
|
|
SLICE_X50Y46 LUT6 (Prop_lut6_I3_O) 0.124 9.846 f u_cpu/u_csr/write_buffer_way[1]_i_18/O
|
|
net (fo=1, routed) 0.000 9.846 u_cpu/u_csr/write_buffer_way[1]_i_18_n_0
|
|
SLICE_X50Y46 f u_cpu/u_csr/write_buffer_way_reg[1]_i_11/S[0]
|
|
SLICE_X50Y46 CARRY4 (Prop_carry4_S[0]_CO[3])
|
|
0.532 10.378 r u_cpu/u_csr/write_buffer_way_reg[1]_i_11/CO[3]
|
|
net (fo=1, routed) 0.000 10.378 u_cpu/u_csr/write_buffer_way_reg[1]_i_11_n_0
|
|
SLICE_X50Y47 r u_cpu/u_csr/write_buffer_way_reg[1]_i_9/CI
|
|
SLICE_X50Y47 CARRY4 (Prop_carry4_CI_CO[1])
|
|
0.157 10.535 f u_cpu/u_csr/write_buffer_way_reg[1]_i_9/CO[1]
|
|
net (fo=2, routed) 0.791 11.326 u_cpu/wb_stage/CO[0]
|
|
SLICE_X46Y39 f u_cpu/wb_stage/write_buffer_way[1]_i_5/I1
|
|
SLICE_X46Y39 LUT6 (Prop_lut6_I1_O) 0.329 11.655 r u_cpu/wb_stage/write_buffer_way[1]_i_5/O
|
|
net (fo=7, routed) 0.762 12.417 u_cpu/addr_trans/tlb_entry/sc_cancel_req
|
|
SLICE_X46Y35 r u_cpu/addr_trans/tlb_entry/main_state[0]_i_3/I1
|
|
SLICE_X46Y35 LUT3 (Prop_lut3_I1_O) 0.124 12.541 r u_cpu/addr_trans/tlb_entry/main_state[0]_i_3/O
|
|
net (fo=3, routed) 0.719 13.260 u_cpu/dcache/main_state_reg[0]_2
|
|
SLICE_X43Y31 r u_cpu/dcache/ds_to_es_bus_r[235]_i_10/I3
|
|
SLICE_X43Y31 LUT6 (Prop_lut6_I3_O) 0.124 13.384 r u_cpu/dcache/ds_to_es_bus_r[235]_i_10/O
|
|
net (fo=3, routed) 0.415 13.799 u_cpu/mem_stage/data_data_ok
|
|
SLICE_X43Y30 r u_cpu/mem_stage/flush_inst_req_buffer[1]_i_15/I0
|
|
SLICE_X43Y30 LUT3 (Prop_lut3_I0_O) 0.124 13.923 r u_cpu/mem_stage/flush_inst_req_buffer[1]_i_15/O
|
|
net (fo=2, routed) 0.833 14.756 u_cpu/mem_stage/es_to_ms_bus_r_reg[70]_1
|
|
SLICE_X48Y30 r u_cpu/mem_stage/flush_inst_req_buffer[1]_i_14/I0
|
|
SLICE_X48Y30 LUT6 (Prop_lut6_I0_O) 0.124 14.880 r u_cpu/mem_stage/flush_inst_req_buffer[1]_i_14/O
|
|
net (fo=1, routed) 0.651 15.532 u_cpu/mem_stage/ms_ready_go
|
|
SLICE_X48Y25 r u_cpu/mem_stage/flush_inst_req_buffer[1]_i_13/I4
|
|
SLICE_X48Y25 LUT6 (Prop_lut6_I4_O) 0.124 15.656 r u_cpu/mem_stage/flush_inst_req_buffer[1]_i_13/O
|
|
net (fo=3, routed) 0.483 16.139 u_cpu/id_stage/flush_inst_req_buffer[31]_i_6
|
|
SLICE_X50Y25 r u_cpu/id_stage/flush_inst_req_buffer[1]_i_9/I1
|
|
SLICE_X50Y25 LUT6 (Prop_lut6_I1_O) 0.124 16.263 r u_cpu/id_stage/flush_inst_req_buffer[1]_i_9/O
|
|
net (fo=32, routed) 0.531 16.794 u_cpu/if_stage/nextpc5
|
|
SLICE_X51Y27 r u_cpu/if_stage/fetch_pc_r[6]_i_4/I2
|
|
SLICE_X51Y27 LUT6 (Prop_lut6_I2_O) 0.124 16.918 r u_cpu/if_stage/fetch_pc_r[6]_i_4/O
|
|
net (fo=1, routed) 3.059 19.977 u_cpu/if_stage/fetch_pc_r[6]_i_4_n_0
|
|
SLICE_X114Y28 r u_cpu/if_stage/fetch_pc_r[6]_i_2/I2
|
|
SLICE_X114Y28 LUT6 (Prop_lut6_I2_O) 0.124 20.101 r u_cpu/if_stage/fetch_pc_r[6]_i_2/O
|
|
net (fo=1, routed) 0.441 20.542 u_cpu/if_stage/fetch_pc_r[6]_i_2_n_0
|
|
SLICE_X114Y25 r u_cpu/if_stage/fetch_pc_r[6]_i_1/I2
|
|
SLICE_X114Y25 LUT6 (Prop_lut6_I2_O) 0.124 20.666 r u_cpu/if_stage/fetch_pc_r[6]_i_1/O
|
|
net (fo=6, routed) 3.249 23.915 u_cpu/icache/tagv_ram_way[1].u/mem_reg_reg_2[2]
|
|
SLICE_X49Y33 r u_cpu/icache/tagv_ram_way[1].u/mem_reg_reg_i_8/I4
|
|
SLICE_X49Y33 LUT5 (Prop_lut5_I4_O) 0.124 24.039 r u_cpu/icache/tagv_ram_way[1].u/mem_reg_reg_i_8/O
|
|
net (fo=16, routed) 1.412 25.451 u_cpu/icache/data_ram_way[0].data_ram_bank[0].u/ADDRBWRADDR[2]
|
|
RAMB18_X2Y4 RAMB18E1 r u_cpu/icache/data_ram_way[0].data_ram_bank[0].u/mem_reg_reg/ADDRARDADDR[7]
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock cpu_clk rise edge) 30.323 30.323 r
|
|
clock source latency -5.674 24.648
|
|
propagated clock network latency
|
|
3.777 28.425
|
|
clock pessimism -0.418 28.007
|
|
clock uncertainty -0.074 27.933
|
|
RAMB18_X2Y4 RAMB18E1 (Setup_ramb18e1_CLKARDCLK_ADDRARDADDR[7])
|
|
-0.566 27.367 u_cpu/icache/data_ram_way[0].data_ram_bank[0].u/mem_reg_reg
|
|
-------------------------------------------------------------------
|
|
required time 27.367
|
|
arrival time -25.451
|
|
-------------------------------------------------------------------
|
|
slack 1.916
|
|
|
|
Slack (MET) : 1.916ns (required time - arrival time)
|
|
Source: u_cpu/addr_trans/data_vaddr_buffer_reg[14]/C
|
|
(rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns})
|
|
Destination: u_cpu/icache/data_ram_way[0].data_ram_bank[0].u/mem_reg_reg/ADDRARDADDR[7]
|
|
(rising edge-triggered cell RAMB18E1 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns})
|
|
Path Group: cpu_clk
|
|
Path Type: Setup (Max at Slow Process Corner)
|
|
Requirement: 30.323ns (cpu_clk rise@30.323ns - cpu_clk rise@0.000ns)
|
|
Data Path Delay: 27.676ns (logic 5.333ns (19.269%) route 22.343ns (80.731%))
|
|
Logic Levels: 26 (CARRY4=4 LUT3=2 LUT4=1 LUT5=2 LUT6=15 MUXF7=1 MUXF8=1)
|
|
Clock Path Skew: -0.091ns (DCD - SCD + CPR)
|
|
Destination Clock Delay (DCD): -1.897ns = ( 28.425 - 30.323 )
|
|
Source Clock Delay (SCD): -2.225ns
|
|
Clock Pessimism Removal (CPR): -0.418ns
|
|
Clock Uncertainty: 0.074ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Discrete Jitter (DJ): 0.130ns
|
|
Phase Error (PE): 0.000ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock cpu_clk rise edge) 0.000 0.000 r
|
|
clock source latency -6.275 -6.275
|
|
propagated clock network latency
|
|
4.051 -2.225
|
|
SLICE_X35Y35 FDRE 0.000 -2.225 r u_cpu/addr_trans/data_vaddr_buffer_reg[14]/C
|
|
SLICE_X35Y35 FDRE (Prop_fdre_C_Q) 0.456 -1.769 r u_cpu/addr_trans/data_vaddr_buffer_reg[14]/Q
|
|
net (fo=33, routed) 1.442 -0.326 u_cpu/addr_trans/tlb_entry/data_vaddr_buffer[2]
|
|
SLICE_X42Y40 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_226/I5
|
|
SLICE_X42Y40 LUT6 (Prop_lut6_I5_O) 0.124 -0.202 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_226/O
|
|
net (fo=1, routed) 0.000 -0.202 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_226_n_0
|
|
SLICE_X42Y40 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_111/S[0]
|
|
SLICE_X42Y40 CARRY4 (Prop_carry4_S[0]_CO[3])
|
|
0.513 0.311 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_111/CO[3]
|
|
net (fo=1, routed) 0.000 0.311 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_111_n_0
|
|
SLICE_X42Y41 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_32/CI
|
|
SLICE_X42Y41 CARRY4 (Prop_carry4_CI_CO[2])
|
|
0.229 0.540 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_32/CO[2]
|
|
net (fo=1, routed) 1.009 1.549 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_32_n_1
|
|
SLICE_X40Y47 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_9/I1
|
|
SLICE_X40Y47 LUT6 (Prop_lut6_I1_O) 0.310 1.859 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_9/O
|
|
net (fo=2, routed) 0.635 2.494 u_cpu/addr_trans/tlb_entry/match1[28]
|
|
SLICE_X38Y47 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/I2
|
|
SLICE_X38Y47 LUT4 (Prop_lut4_I2_O) 0.124 2.618 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/O
|
|
net (fo=2, routed) 0.667 3.285 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2_n_0
|
|
SLICE_X39Y47 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/I0
|
|
SLICE_X39Y47 LUT5 (Prop_lut5_I0_O) 0.124 3.409 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/O
|
|
net (fo=2, routed) 1.103 4.512 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2_n_0
|
|
SLICE_X38Y50 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/I0
|
|
SLICE_X38Y50 LUT6 (Prop_lut6_I0_O) 0.124 4.636 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/O
|
|
net (fo=89, routed) 1.162 5.797 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus[8]
|
|
SLICE_X42Y51 r u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_38__0/S
|
|
SLICE_X42Y51 MUXF7 (Prop_muxf7_S_O) 0.292 6.089 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_38__0/O
|
|
net (fo=1, routed) 0.000 6.089 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_38__0_n_0
|
|
SLICE_X42Y51 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_16__0/I1
|
|
SLICE_X42Y51 MUXF8 (Prop_muxf8_I1_O) 0.088 6.177 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_16__0/O
|
|
net (fo=1, routed) 0.957 7.134 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_16__0_n_0
|
|
SLICE_X42Y50 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7/I0
|
|
SLICE_X42Y50 LUT6 (Prop_lut6_I0_O) 0.319 7.453 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7/O
|
|
net (fo=1, routed) 0.435 7.888 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7_n_0
|
|
SLICE_X44Y50 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0/I5
|
|
SLICE_X44Y50 LUT6 (Prop_lut6_I5_O) 0.124 8.012 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0/O
|
|
net (fo=10, routed) 0.740 8.753 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0_n_0
|
|
SLICE_X44Y50 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[5]_i_1__0/I3
|
|
SLICE_X44Y50 LUT6 (Prop_lut6_I3_O) 0.124 8.877 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[5]_i_1__0/O
|
|
net (fo=6, routed) 0.845 9.722 u_cpu/u_csr/ms_to_ws_bus[13]
|
|
SLICE_X50Y46 r u_cpu/u_csr/write_buffer_way[1]_i_18/I3
|
|
SLICE_X50Y46 LUT6 (Prop_lut6_I3_O) 0.124 9.846 r u_cpu/u_csr/write_buffer_way[1]_i_18/O
|
|
net (fo=1, routed) 0.000 9.846 u_cpu/u_csr/write_buffer_way[1]_i_18_n_0
|
|
SLICE_X50Y46 r u_cpu/u_csr/write_buffer_way_reg[1]_i_11/S[0]
|
|
SLICE_X50Y46 CARRY4 (Prop_carry4_S[0]_CO[3])
|
|
0.532 10.378 f u_cpu/u_csr/write_buffer_way_reg[1]_i_11/CO[3]
|
|
net (fo=1, routed) 0.000 10.378 u_cpu/u_csr/write_buffer_way_reg[1]_i_11_n_0
|
|
SLICE_X50Y47 f u_cpu/u_csr/write_buffer_way_reg[1]_i_9/CI
|
|
SLICE_X50Y47 CARRY4 (Prop_carry4_CI_CO[1])
|
|
0.157 10.535 f u_cpu/u_csr/write_buffer_way_reg[1]_i_9/CO[1]
|
|
net (fo=2, routed) 0.791 11.326 u_cpu/wb_stage/CO[0]
|
|
SLICE_X46Y39 f u_cpu/wb_stage/write_buffer_way[1]_i_5/I1
|
|
SLICE_X46Y39 LUT6 (Prop_lut6_I1_O) 0.329 11.655 r u_cpu/wb_stage/write_buffer_way[1]_i_5/O
|
|
net (fo=7, routed) 0.762 12.417 u_cpu/addr_trans/tlb_entry/sc_cancel_req
|
|
SLICE_X46Y35 r u_cpu/addr_trans/tlb_entry/main_state[0]_i_3/I1
|
|
SLICE_X46Y35 LUT3 (Prop_lut3_I1_O) 0.124 12.541 r u_cpu/addr_trans/tlb_entry/main_state[0]_i_3/O
|
|
net (fo=3, routed) 0.719 13.260 u_cpu/dcache/main_state_reg[0]_2
|
|
SLICE_X43Y31 r u_cpu/dcache/ds_to_es_bus_r[235]_i_10/I3
|
|
SLICE_X43Y31 LUT6 (Prop_lut6_I3_O) 0.124 13.384 r u_cpu/dcache/ds_to_es_bus_r[235]_i_10/O
|
|
net (fo=3, routed) 0.415 13.799 u_cpu/mem_stage/data_data_ok
|
|
SLICE_X43Y30 r u_cpu/mem_stage/flush_inst_req_buffer[1]_i_15/I0
|
|
SLICE_X43Y30 LUT3 (Prop_lut3_I0_O) 0.124 13.923 r u_cpu/mem_stage/flush_inst_req_buffer[1]_i_15/O
|
|
net (fo=2, routed) 0.833 14.756 u_cpu/mem_stage/es_to_ms_bus_r_reg[70]_1
|
|
SLICE_X48Y30 r u_cpu/mem_stage/flush_inst_req_buffer[1]_i_14/I0
|
|
SLICE_X48Y30 LUT6 (Prop_lut6_I0_O) 0.124 14.880 r u_cpu/mem_stage/flush_inst_req_buffer[1]_i_14/O
|
|
net (fo=1, routed) 0.651 15.532 u_cpu/mem_stage/ms_ready_go
|
|
SLICE_X48Y25 r u_cpu/mem_stage/flush_inst_req_buffer[1]_i_13/I4
|
|
SLICE_X48Y25 LUT6 (Prop_lut6_I4_O) 0.124 15.656 r u_cpu/mem_stage/flush_inst_req_buffer[1]_i_13/O
|
|
net (fo=3, routed) 0.483 16.139 u_cpu/id_stage/flush_inst_req_buffer[31]_i_6
|
|
SLICE_X50Y25 r u_cpu/id_stage/flush_inst_req_buffer[1]_i_9/I1
|
|
SLICE_X50Y25 LUT6 (Prop_lut6_I1_O) 0.124 16.263 r u_cpu/id_stage/flush_inst_req_buffer[1]_i_9/O
|
|
net (fo=32, routed) 0.531 16.794 u_cpu/if_stage/nextpc5
|
|
SLICE_X51Y27 r u_cpu/if_stage/fetch_pc_r[6]_i_4/I2
|
|
SLICE_X51Y27 LUT6 (Prop_lut6_I2_O) 0.124 16.918 r u_cpu/if_stage/fetch_pc_r[6]_i_4/O
|
|
net (fo=1, routed) 3.059 19.977 u_cpu/if_stage/fetch_pc_r[6]_i_4_n_0
|
|
SLICE_X114Y28 r u_cpu/if_stage/fetch_pc_r[6]_i_2/I2
|
|
SLICE_X114Y28 LUT6 (Prop_lut6_I2_O) 0.124 20.101 r u_cpu/if_stage/fetch_pc_r[6]_i_2/O
|
|
net (fo=1, routed) 0.441 20.542 u_cpu/if_stage/fetch_pc_r[6]_i_2_n_0
|
|
SLICE_X114Y25 r u_cpu/if_stage/fetch_pc_r[6]_i_1/I2
|
|
SLICE_X114Y25 LUT6 (Prop_lut6_I2_O) 0.124 20.666 r u_cpu/if_stage/fetch_pc_r[6]_i_1/O
|
|
net (fo=6, routed) 3.249 23.915 u_cpu/icache/tagv_ram_way[1].u/mem_reg_reg_2[2]
|
|
SLICE_X49Y33 r u_cpu/icache/tagv_ram_way[1].u/mem_reg_reg_i_8/I4
|
|
SLICE_X49Y33 LUT5 (Prop_lut5_I4_O) 0.124 24.039 r u_cpu/icache/tagv_ram_way[1].u/mem_reg_reg_i_8/O
|
|
net (fo=16, routed) 1.412 25.451 u_cpu/icache/data_ram_way[0].data_ram_bank[0].u/ADDRBWRADDR[2]
|
|
RAMB18_X2Y4 RAMB18E1 r u_cpu/icache/data_ram_way[0].data_ram_bank[0].u/mem_reg_reg/ADDRARDADDR[7]
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock cpu_clk rise edge) 30.323 30.323 r
|
|
clock source latency -5.674 24.648
|
|
propagated clock network latency
|
|
3.777 28.425
|
|
clock pessimism -0.418 28.007
|
|
clock uncertainty -0.074 27.933
|
|
RAMB18_X2Y4 RAMB18E1 (Setup_ramb18e1_CLKARDCLK_ADDRARDADDR[7])
|
|
-0.566 27.367 u_cpu/icache/data_ram_way[0].data_ram_bank[0].u/mem_reg_reg
|
|
-------------------------------------------------------------------
|
|
required time 27.367
|
|
arrival time -25.451
|
|
-------------------------------------------------------------------
|
|
slack 1.916
|
|
|
|
Slack (MET) : 1.916ns (required time - arrival time)
|
|
Source: u_cpu/addr_trans/data_vaddr_buffer_reg[14]/C
|
|
(rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns})
|
|
Destination: u_cpu/icache/data_ram_way[0].data_ram_bank[0].u/mem_reg_reg/ADDRARDADDR[7]
|
|
(rising edge-triggered cell RAMB18E1 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns})
|
|
Path Group: cpu_clk
|
|
Path Type: Setup (Max at Slow Process Corner)
|
|
Requirement: 30.323ns (cpu_clk rise@30.323ns - cpu_clk rise@0.000ns)
|
|
Data Path Delay: 27.676ns (logic 5.333ns (19.269%) route 22.343ns (80.731%))
|
|
Logic Levels: 26 (CARRY4=4 LUT3=2 LUT4=1 LUT5=2 LUT6=15 MUXF7=1 MUXF8=1)
|
|
Clock Path Skew: -0.091ns (DCD - SCD + CPR)
|
|
Destination Clock Delay (DCD): -1.897ns = ( 28.425 - 30.323 )
|
|
Source Clock Delay (SCD): -2.225ns
|
|
Clock Pessimism Removal (CPR): -0.418ns
|
|
Clock Uncertainty: 0.074ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Discrete Jitter (DJ): 0.130ns
|
|
Phase Error (PE): 0.000ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock cpu_clk rise edge) 0.000 0.000 r
|
|
clock source latency -6.275 -6.275
|
|
propagated clock network latency
|
|
4.051 -2.225
|
|
SLICE_X35Y35 FDRE 0.000 -2.225 r u_cpu/addr_trans/data_vaddr_buffer_reg[14]/C
|
|
SLICE_X35Y35 FDRE (Prop_fdre_C_Q) 0.456 -1.769 r u_cpu/addr_trans/data_vaddr_buffer_reg[14]/Q
|
|
net (fo=33, routed) 1.442 -0.326 u_cpu/addr_trans/tlb_entry/data_vaddr_buffer[2]
|
|
SLICE_X42Y40 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_226/I5
|
|
SLICE_X42Y40 LUT6 (Prop_lut6_I5_O) 0.124 -0.202 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_226/O
|
|
net (fo=1, routed) 0.000 -0.202 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_226_n_0
|
|
SLICE_X42Y40 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_111/S[0]
|
|
SLICE_X42Y40 CARRY4 (Prop_carry4_S[0]_CO[3])
|
|
0.513 0.311 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_111/CO[3]
|
|
net (fo=1, routed) 0.000 0.311 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_111_n_0
|
|
SLICE_X42Y41 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_32/CI
|
|
SLICE_X42Y41 CARRY4 (Prop_carry4_CI_CO[2])
|
|
0.229 0.540 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_32/CO[2]
|
|
net (fo=1, routed) 1.009 1.549 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_32_n_1
|
|
SLICE_X40Y47 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_9/I1
|
|
SLICE_X40Y47 LUT6 (Prop_lut6_I1_O) 0.310 1.859 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_9/O
|
|
net (fo=2, routed) 0.635 2.494 u_cpu/addr_trans/tlb_entry/match1[28]
|
|
SLICE_X38Y47 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/I2
|
|
SLICE_X38Y47 LUT4 (Prop_lut4_I2_O) 0.124 2.618 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/O
|
|
net (fo=2, routed) 0.667 3.285 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2_n_0
|
|
SLICE_X39Y47 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/I0
|
|
SLICE_X39Y47 LUT5 (Prop_lut5_I0_O) 0.124 3.409 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/O
|
|
net (fo=2, routed) 1.103 4.512 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2_n_0
|
|
SLICE_X38Y50 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/I0
|
|
SLICE_X38Y50 LUT6 (Prop_lut6_I0_O) 0.124 4.636 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/O
|
|
net (fo=89, routed) 1.162 5.797 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus[8]
|
|
SLICE_X42Y51 r u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_38__0/S
|
|
SLICE_X42Y51 MUXF7 (Prop_muxf7_S_O) 0.292 6.089 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_38__0/O
|
|
net (fo=1, routed) 0.000 6.089 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_38__0_n_0
|
|
SLICE_X42Y51 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_16__0/I1
|
|
SLICE_X42Y51 MUXF8 (Prop_muxf8_I1_O) 0.088 6.177 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_16__0/O
|
|
net (fo=1, routed) 0.957 7.134 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_16__0_n_0
|
|
SLICE_X42Y50 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7/I0
|
|
SLICE_X42Y50 LUT6 (Prop_lut6_I0_O) 0.319 7.453 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7/O
|
|
net (fo=1, routed) 0.435 7.888 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7_n_0
|
|
SLICE_X44Y50 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0/I5
|
|
SLICE_X44Y50 LUT6 (Prop_lut6_I5_O) 0.124 8.012 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0/O
|
|
net (fo=10, routed) 0.740 8.753 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0_n_0
|
|
SLICE_X44Y50 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[5]_i_1__0/I3
|
|
SLICE_X44Y50 LUT6 (Prop_lut6_I3_O) 0.124 8.877 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[5]_i_1__0/O
|
|
net (fo=6, routed) 0.845 9.722 u_cpu/u_csr/ms_to_ws_bus[13]
|
|
SLICE_X50Y46 f u_cpu/u_csr/write_buffer_way[1]_i_18/I3
|
|
SLICE_X50Y46 LUT6 (Prop_lut6_I3_O) 0.124 9.846 r u_cpu/u_csr/write_buffer_way[1]_i_18/O
|
|
net (fo=1, routed) 0.000 9.846 u_cpu/u_csr/write_buffer_way[1]_i_18_n_0
|
|
SLICE_X50Y46 r u_cpu/u_csr/write_buffer_way_reg[1]_i_11/S[0]
|
|
SLICE_X50Y46 CARRY4 (Prop_carry4_S[0]_CO[3])
|
|
0.532 10.378 f u_cpu/u_csr/write_buffer_way_reg[1]_i_11/CO[3]
|
|
net (fo=1, routed) 0.000 10.378 u_cpu/u_csr/write_buffer_way_reg[1]_i_11_n_0
|
|
SLICE_X50Y47 f u_cpu/u_csr/write_buffer_way_reg[1]_i_9/CI
|
|
SLICE_X50Y47 CARRY4 (Prop_carry4_CI_CO[1])
|
|
0.157 10.535 f u_cpu/u_csr/write_buffer_way_reg[1]_i_9/CO[1]
|
|
net (fo=2, routed) 0.791 11.326 u_cpu/wb_stage/CO[0]
|
|
SLICE_X46Y39 f u_cpu/wb_stage/write_buffer_way[1]_i_5/I1
|
|
SLICE_X46Y39 LUT6 (Prop_lut6_I1_O) 0.329 11.655 r u_cpu/wb_stage/write_buffer_way[1]_i_5/O
|
|
net (fo=7, routed) 0.762 12.417 u_cpu/addr_trans/tlb_entry/sc_cancel_req
|
|
SLICE_X46Y35 r u_cpu/addr_trans/tlb_entry/main_state[0]_i_3/I1
|
|
SLICE_X46Y35 LUT3 (Prop_lut3_I1_O) 0.124 12.541 r u_cpu/addr_trans/tlb_entry/main_state[0]_i_3/O
|
|
net (fo=3, routed) 0.719 13.260 u_cpu/dcache/main_state_reg[0]_2
|
|
SLICE_X43Y31 r u_cpu/dcache/ds_to_es_bus_r[235]_i_10/I3
|
|
SLICE_X43Y31 LUT6 (Prop_lut6_I3_O) 0.124 13.384 r u_cpu/dcache/ds_to_es_bus_r[235]_i_10/O
|
|
net (fo=3, routed) 0.415 13.799 u_cpu/mem_stage/data_data_ok
|
|
SLICE_X43Y30 r u_cpu/mem_stage/flush_inst_req_buffer[1]_i_15/I0
|
|
SLICE_X43Y30 LUT3 (Prop_lut3_I0_O) 0.124 13.923 r u_cpu/mem_stage/flush_inst_req_buffer[1]_i_15/O
|
|
net (fo=2, routed) 0.833 14.756 u_cpu/mem_stage/es_to_ms_bus_r_reg[70]_1
|
|
SLICE_X48Y30 r u_cpu/mem_stage/flush_inst_req_buffer[1]_i_14/I0
|
|
SLICE_X48Y30 LUT6 (Prop_lut6_I0_O) 0.124 14.880 r u_cpu/mem_stage/flush_inst_req_buffer[1]_i_14/O
|
|
net (fo=1, routed) 0.651 15.532 u_cpu/mem_stage/ms_ready_go
|
|
SLICE_X48Y25 r u_cpu/mem_stage/flush_inst_req_buffer[1]_i_13/I4
|
|
SLICE_X48Y25 LUT6 (Prop_lut6_I4_O) 0.124 15.656 r u_cpu/mem_stage/flush_inst_req_buffer[1]_i_13/O
|
|
net (fo=3, routed) 0.483 16.139 u_cpu/id_stage/flush_inst_req_buffer[31]_i_6
|
|
SLICE_X50Y25 r u_cpu/id_stage/flush_inst_req_buffer[1]_i_9/I1
|
|
SLICE_X50Y25 LUT6 (Prop_lut6_I1_O) 0.124 16.263 r u_cpu/id_stage/flush_inst_req_buffer[1]_i_9/O
|
|
net (fo=32, routed) 0.531 16.794 u_cpu/if_stage/nextpc5
|
|
SLICE_X51Y27 r u_cpu/if_stage/fetch_pc_r[6]_i_4/I2
|
|
SLICE_X51Y27 LUT6 (Prop_lut6_I2_O) 0.124 16.918 r u_cpu/if_stage/fetch_pc_r[6]_i_4/O
|
|
net (fo=1, routed) 3.059 19.977 u_cpu/if_stage/fetch_pc_r[6]_i_4_n_0
|
|
SLICE_X114Y28 r u_cpu/if_stage/fetch_pc_r[6]_i_2/I2
|
|
SLICE_X114Y28 LUT6 (Prop_lut6_I2_O) 0.124 20.101 r u_cpu/if_stage/fetch_pc_r[6]_i_2/O
|
|
net (fo=1, routed) 0.441 20.542 u_cpu/if_stage/fetch_pc_r[6]_i_2_n_0
|
|
SLICE_X114Y25 r u_cpu/if_stage/fetch_pc_r[6]_i_1/I2
|
|
SLICE_X114Y25 LUT6 (Prop_lut6_I2_O) 0.124 20.666 r u_cpu/if_stage/fetch_pc_r[6]_i_1/O
|
|
net (fo=6, routed) 3.249 23.915 u_cpu/icache/tagv_ram_way[1].u/mem_reg_reg_2[2]
|
|
SLICE_X49Y33 r u_cpu/icache/tagv_ram_way[1].u/mem_reg_reg_i_8/I4
|
|
SLICE_X49Y33 LUT5 (Prop_lut5_I4_O) 0.124 24.039 r u_cpu/icache/tagv_ram_way[1].u/mem_reg_reg_i_8/O
|
|
net (fo=16, routed) 1.412 25.451 u_cpu/icache/data_ram_way[0].data_ram_bank[0].u/ADDRBWRADDR[2]
|
|
RAMB18_X2Y4 RAMB18E1 r u_cpu/icache/data_ram_way[0].data_ram_bank[0].u/mem_reg_reg/ADDRARDADDR[7]
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock cpu_clk rise edge) 30.323 30.323 r
|
|
clock source latency -5.674 24.648
|
|
propagated clock network latency
|
|
3.777 28.425
|
|
clock pessimism -0.418 28.007
|
|
clock uncertainty -0.074 27.933
|
|
RAMB18_X2Y4 RAMB18E1 (Setup_ramb18e1_CLKARDCLK_ADDRARDADDR[7])
|
|
-0.566 27.367 u_cpu/icache/data_ram_way[0].data_ram_bank[0].u/mem_reg_reg
|
|
-------------------------------------------------------------------
|
|
required time 27.367
|
|
arrival time -25.451
|
|
-------------------------------------------------------------------
|
|
slack 1.916
|
|
|
|
Slack (MET) : 1.916ns (required time - arrival time)
|
|
Source: u_cpu/addr_trans/data_vaddr_buffer_reg[14]/C
|
|
(rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns})
|
|
Destination: u_cpu/icache/data_ram_way[0].data_ram_bank[0].u/mem_reg_reg/ADDRARDADDR[7]
|
|
(rising edge-triggered cell RAMB18E1 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns})
|
|
Path Group: cpu_clk
|
|
Path Type: Setup (Max at Slow Process Corner)
|
|
Requirement: 30.323ns (cpu_clk rise@30.323ns - cpu_clk rise@0.000ns)
|
|
Data Path Delay: 27.676ns (logic 5.333ns (19.269%) route 22.343ns (80.731%))
|
|
Logic Levels: 26 (CARRY4=4 LUT3=2 LUT4=1 LUT5=2 LUT6=15 MUXF7=1 MUXF8=1)
|
|
Clock Path Skew: -0.091ns (DCD - SCD + CPR)
|
|
Destination Clock Delay (DCD): -1.897ns = ( 28.425 - 30.323 )
|
|
Source Clock Delay (SCD): -2.225ns
|
|
Clock Pessimism Removal (CPR): -0.418ns
|
|
Clock Uncertainty: 0.074ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Discrete Jitter (DJ): 0.130ns
|
|
Phase Error (PE): 0.000ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock cpu_clk rise edge) 0.000 0.000 r
|
|
clock source latency -6.275 -6.275
|
|
propagated clock network latency
|
|
4.051 -2.225
|
|
SLICE_X35Y35 FDRE 0.000 -2.225 r u_cpu/addr_trans/data_vaddr_buffer_reg[14]/C
|
|
SLICE_X35Y35 FDRE (Prop_fdre_C_Q) 0.456 -1.769 r u_cpu/addr_trans/data_vaddr_buffer_reg[14]/Q
|
|
net (fo=33, routed) 1.442 -0.326 u_cpu/addr_trans/tlb_entry/data_vaddr_buffer[2]
|
|
SLICE_X42Y40 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_226/I5
|
|
SLICE_X42Y40 LUT6 (Prop_lut6_I5_O) 0.124 -0.202 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_226/O
|
|
net (fo=1, routed) 0.000 -0.202 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_226_n_0
|
|
SLICE_X42Y40 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_111/S[0]
|
|
SLICE_X42Y40 CARRY4 (Prop_carry4_S[0]_CO[3])
|
|
0.513 0.311 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_111/CO[3]
|
|
net (fo=1, routed) 0.000 0.311 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_111_n_0
|
|
SLICE_X42Y41 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_32/CI
|
|
SLICE_X42Y41 CARRY4 (Prop_carry4_CI_CO[2])
|
|
0.229 0.540 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_32/CO[2]
|
|
net (fo=1, routed) 1.009 1.549 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_32_n_1
|
|
SLICE_X40Y47 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_9/I1
|
|
SLICE_X40Y47 LUT6 (Prop_lut6_I1_O) 0.310 1.859 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_9/O
|
|
net (fo=2, routed) 0.635 2.494 u_cpu/addr_trans/tlb_entry/match1[28]
|
|
SLICE_X38Y47 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/I2
|
|
SLICE_X38Y47 LUT4 (Prop_lut4_I2_O) 0.124 2.618 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/O
|
|
net (fo=2, routed) 0.667 3.285 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2_n_0
|
|
SLICE_X39Y47 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/I0
|
|
SLICE_X39Y47 LUT5 (Prop_lut5_I0_O) 0.124 3.409 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/O
|
|
net (fo=2, routed) 1.103 4.512 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2_n_0
|
|
SLICE_X38Y50 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/I0
|
|
SLICE_X38Y50 LUT6 (Prop_lut6_I0_O) 0.124 4.636 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/O
|
|
net (fo=89, routed) 1.162 5.797 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus[8]
|
|
SLICE_X42Y51 r u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_38__0/S
|
|
SLICE_X42Y51 MUXF7 (Prop_muxf7_S_O) 0.292 6.089 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_38__0/O
|
|
net (fo=1, routed) 0.000 6.089 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_38__0_n_0
|
|
SLICE_X42Y51 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_16__0/I1
|
|
SLICE_X42Y51 MUXF8 (Prop_muxf8_I1_O) 0.088 6.177 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_16__0/O
|
|
net (fo=1, routed) 0.957 7.134 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_16__0_n_0
|
|
SLICE_X42Y50 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7/I0
|
|
SLICE_X42Y50 LUT6 (Prop_lut6_I0_O) 0.319 7.453 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7/O
|
|
net (fo=1, routed) 0.435 7.888 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7_n_0
|
|
SLICE_X44Y50 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0/I5
|
|
SLICE_X44Y50 LUT6 (Prop_lut6_I5_O) 0.124 8.012 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0/O
|
|
net (fo=10, routed) 0.740 8.753 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0_n_0
|
|
SLICE_X44Y50 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[5]_i_1__0/I3
|
|
SLICE_X44Y50 LUT6 (Prop_lut6_I3_O) 0.124 8.877 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[5]_i_1__0/O
|
|
net (fo=6, routed) 0.845 9.722 u_cpu/u_csr/ms_to_ws_bus[13]
|
|
SLICE_X50Y46 r u_cpu/u_csr/write_buffer_way[1]_i_18/I3
|
|
SLICE_X50Y46 LUT6 (Prop_lut6_I3_O) 0.124 9.846 r u_cpu/u_csr/write_buffer_way[1]_i_18/O
|
|
net (fo=1, routed) 0.000 9.846 u_cpu/u_csr/write_buffer_way[1]_i_18_n_0
|
|
SLICE_X50Y46 r u_cpu/u_csr/write_buffer_way_reg[1]_i_11/S[0]
|
|
SLICE_X50Y46 CARRY4 (Prop_carry4_S[0]_CO[3])
|
|
0.532 10.378 r u_cpu/u_csr/write_buffer_way_reg[1]_i_11/CO[3]
|
|
net (fo=1, routed) 0.000 10.378 u_cpu/u_csr/write_buffer_way_reg[1]_i_11_n_0
|
|
SLICE_X50Y47 r u_cpu/u_csr/write_buffer_way_reg[1]_i_9/CI
|
|
SLICE_X50Y47 CARRY4 (Prop_carry4_CI_CO[1])
|
|
0.157 10.535 r u_cpu/u_csr/write_buffer_way_reg[1]_i_9/CO[1]
|
|
net (fo=2, routed) 0.791 11.326 u_cpu/wb_stage/CO[0]
|
|
SLICE_X46Y39 r u_cpu/wb_stage/write_buffer_way[1]_i_5/I1
|
|
SLICE_X46Y39 LUT6 (Prop_lut6_I1_O) 0.329 11.655 f u_cpu/wb_stage/write_buffer_way[1]_i_5/O
|
|
net (fo=7, routed) 0.762 12.417 u_cpu/addr_trans/tlb_entry/sc_cancel_req
|
|
SLICE_X46Y35 f u_cpu/addr_trans/tlb_entry/main_state[0]_i_3/I1
|
|
SLICE_X46Y35 LUT3 (Prop_lut3_I1_O) 0.124 12.541 f u_cpu/addr_trans/tlb_entry/main_state[0]_i_3/O
|
|
net (fo=3, routed) 0.719 13.260 u_cpu/dcache/main_state_reg[0]_2
|
|
SLICE_X43Y31 f u_cpu/dcache/ds_to_es_bus_r[235]_i_10/I3
|
|
SLICE_X43Y31 LUT6 (Prop_lut6_I3_O) 0.124 13.384 f u_cpu/dcache/ds_to_es_bus_r[235]_i_10/O
|
|
net (fo=3, routed) 0.415 13.799 u_cpu/mem_stage/data_data_ok
|
|
SLICE_X43Y30 f u_cpu/mem_stage/flush_inst_req_buffer[1]_i_15/I0
|
|
SLICE_X43Y30 LUT3 (Prop_lut3_I0_O) 0.124 13.923 f u_cpu/mem_stage/flush_inst_req_buffer[1]_i_15/O
|
|
net (fo=2, routed) 0.833 14.756 u_cpu/mem_stage/es_to_ms_bus_r_reg[70]_1
|
|
SLICE_X48Y30 f u_cpu/mem_stage/flush_inst_req_buffer[1]_i_14/I0
|
|
SLICE_X48Y30 LUT6 (Prop_lut6_I0_O) 0.124 14.880 f u_cpu/mem_stage/flush_inst_req_buffer[1]_i_14/O
|
|
net (fo=1, routed) 0.651 15.532 u_cpu/mem_stage/ms_ready_go
|
|
SLICE_X48Y25 f u_cpu/mem_stage/flush_inst_req_buffer[1]_i_13/I4
|
|
SLICE_X48Y25 LUT6 (Prop_lut6_I4_O) 0.124 15.656 f u_cpu/mem_stage/flush_inst_req_buffer[1]_i_13/O
|
|
net (fo=3, routed) 0.483 16.139 u_cpu/id_stage/flush_inst_req_buffer[31]_i_6
|
|
SLICE_X50Y25 f u_cpu/id_stage/flush_inst_req_buffer[1]_i_9/I1
|
|
SLICE_X50Y25 LUT6 (Prop_lut6_I1_O) 0.124 16.263 f u_cpu/id_stage/flush_inst_req_buffer[1]_i_9/O
|
|
net (fo=32, routed) 0.531 16.794 u_cpu/if_stage/nextpc5
|
|
SLICE_X51Y27 f u_cpu/if_stage/fetch_pc_r[6]_i_4/I2
|
|
SLICE_X51Y27 LUT6 (Prop_lut6_I2_O) 0.124 16.918 r u_cpu/if_stage/fetch_pc_r[6]_i_4/O
|
|
net (fo=1, routed) 3.059 19.977 u_cpu/if_stage/fetch_pc_r[6]_i_4_n_0
|
|
SLICE_X114Y28 r u_cpu/if_stage/fetch_pc_r[6]_i_2/I2
|
|
SLICE_X114Y28 LUT6 (Prop_lut6_I2_O) 0.124 20.101 r u_cpu/if_stage/fetch_pc_r[6]_i_2/O
|
|
net (fo=1, routed) 0.441 20.542 u_cpu/if_stage/fetch_pc_r[6]_i_2_n_0
|
|
SLICE_X114Y25 r u_cpu/if_stage/fetch_pc_r[6]_i_1/I2
|
|
SLICE_X114Y25 LUT6 (Prop_lut6_I2_O) 0.124 20.666 r u_cpu/if_stage/fetch_pc_r[6]_i_1/O
|
|
net (fo=6, routed) 3.249 23.915 u_cpu/icache/tagv_ram_way[1].u/mem_reg_reg_2[2]
|
|
SLICE_X49Y33 r u_cpu/icache/tagv_ram_way[1].u/mem_reg_reg_i_8/I4
|
|
SLICE_X49Y33 LUT5 (Prop_lut5_I4_O) 0.124 24.039 r u_cpu/icache/tagv_ram_way[1].u/mem_reg_reg_i_8/O
|
|
net (fo=16, routed) 1.412 25.451 u_cpu/icache/data_ram_way[0].data_ram_bank[0].u/ADDRBWRADDR[2]
|
|
RAMB18_X2Y4 RAMB18E1 r u_cpu/icache/data_ram_way[0].data_ram_bank[0].u/mem_reg_reg/ADDRARDADDR[7]
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock cpu_clk rise edge) 30.323 30.323 r
|
|
clock source latency -5.674 24.648
|
|
propagated clock network latency
|
|
3.777 28.425
|
|
clock pessimism -0.418 28.007
|
|
clock uncertainty -0.074 27.933
|
|
RAMB18_X2Y4 RAMB18E1 (Setup_ramb18e1_CLKARDCLK_ADDRARDADDR[7])
|
|
-0.566 27.367 u_cpu/icache/data_ram_way[0].data_ram_bank[0].u/mem_reg_reg
|
|
-------------------------------------------------------------------
|
|
required time 27.367
|
|
arrival time -25.451
|
|
-------------------------------------------------------------------
|
|
slack 1.916
|
|
|
|
Slack (MET) : 1.916ns (required time - arrival time)
|
|
Source: u_cpu/addr_trans/data_vaddr_buffer_reg[14]/C
|
|
(rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns})
|
|
Destination: u_cpu/icache/data_ram_way[0].data_ram_bank[0].u/mem_reg_reg/ADDRARDADDR[7]
|
|
(rising edge-triggered cell RAMB18E1 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns})
|
|
Path Group: cpu_clk
|
|
Path Type: Setup (Max at Slow Process Corner)
|
|
Requirement: 30.323ns (cpu_clk rise@30.323ns - cpu_clk rise@0.000ns)
|
|
Data Path Delay: 27.676ns (logic 5.333ns (19.269%) route 22.343ns (80.731%))
|
|
Logic Levels: 26 (CARRY4=4 LUT3=2 LUT4=1 LUT5=2 LUT6=15 MUXF7=1 MUXF8=1)
|
|
Clock Path Skew: -0.091ns (DCD - SCD + CPR)
|
|
Destination Clock Delay (DCD): -1.897ns = ( 28.425 - 30.323 )
|
|
Source Clock Delay (SCD): -2.225ns
|
|
Clock Pessimism Removal (CPR): -0.418ns
|
|
Clock Uncertainty: 0.074ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Discrete Jitter (DJ): 0.130ns
|
|
Phase Error (PE): 0.000ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock cpu_clk rise edge) 0.000 0.000 r
|
|
clock source latency -6.275 -6.275
|
|
propagated clock network latency
|
|
4.051 -2.225
|
|
SLICE_X35Y35 FDRE 0.000 -2.225 r u_cpu/addr_trans/data_vaddr_buffer_reg[14]/C
|
|
SLICE_X35Y35 FDRE (Prop_fdre_C_Q) 0.456 -1.769 r u_cpu/addr_trans/data_vaddr_buffer_reg[14]/Q
|
|
net (fo=33, routed) 1.442 -0.326 u_cpu/addr_trans/tlb_entry/data_vaddr_buffer[2]
|
|
SLICE_X42Y40 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_226/I5
|
|
SLICE_X42Y40 LUT6 (Prop_lut6_I5_O) 0.124 -0.202 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_226/O
|
|
net (fo=1, routed) 0.000 -0.202 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_226_n_0
|
|
SLICE_X42Y40 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_111/S[0]
|
|
SLICE_X42Y40 CARRY4 (Prop_carry4_S[0]_CO[3])
|
|
0.513 0.311 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_111/CO[3]
|
|
net (fo=1, routed) 0.000 0.311 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_111_n_0
|
|
SLICE_X42Y41 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_32/CI
|
|
SLICE_X42Y41 CARRY4 (Prop_carry4_CI_CO[2])
|
|
0.229 0.540 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_32/CO[2]
|
|
net (fo=1, routed) 1.009 1.549 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_32_n_1
|
|
SLICE_X40Y47 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_9/I1
|
|
SLICE_X40Y47 LUT6 (Prop_lut6_I1_O) 0.310 1.859 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_9/O
|
|
net (fo=2, routed) 0.635 2.494 u_cpu/addr_trans/tlb_entry/match1[28]
|
|
SLICE_X38Y47 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/I2
|
|
SLICE_X38Y47 LUT4 (Prop_lut4_I2_O) 0.124 2.618 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/O
|
|
net (fo=2, routed) 0.667 3.285 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2_n_0
|
|
SLICE_X39Y47 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/I0
|
|
SLICE_X39Y47 LUT5 (Prop_lut5_I0_O) 0.124 3.409 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/O
|
|
net (fo=2, routed) 1.103 4.512 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2_n_0
|
|
SLICE_X38Y50 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/I0
|
|
SLICE_X38Y50 LUT6 (Prop_lut6_I0_O) 0.124 4.636 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/O
|
|
net (fo=89, routed) 1.162 5.797 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus[8]
|
|
SLICE_X42Y51 r u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_38__0/S
|
|
SLICE_X42Y51 MUXF7 (Prop_muxf7_S_O) 0.292 6.089 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_38__0/O
|
|
net (fo=1, routed) 0.000 6.089 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_38__0_n_0
|
|
SLICE_X42Y51 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_16__0/I1
|
|
SLICE_X42Y51 MUXF8 (Prop_muxf8_I1_O) 0.088 6.177 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_16__0/O
|
|
net (fo=1, routed) 0.957 7.134 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_16__0_n_0
|
|
SLICE_X42Y50 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7/I0
|
|
SLICE_X42Y50 LUT6 (Prop_lut6_I0_O) 0.319 7.453 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7/O
|
|
net (fo=1, routed) 0.435 7.888 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7_n_0
|
|
SLICE_X44Y50 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0/I5
|
|
SLICE_X44Y50 LUT6 (Prop_lut6_I5_O) 0.124 8.012 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0/O
|
|
net (fo=10, routed) 0.740 8.753 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0_n_0
|
|
SLICE_X44Y50 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[5]_i_1__0/I3
|
|
SLICE_X44Y50 LUT6 (Prop_lut6_I3_O) 0.124 8.877 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[5]_i_1__0/O
|
|
net (fo=6, routed) 0.845 9.722 u_cpu/u_csr/ms_to_ws_bus[13]
|
|
SLICE_X50Y46 f u_cpu/u_csr/write_buffer_way[1]_i_18/I3
|
|
SLICE_X50Y46 LUT6 (Prop_lut6_I3_O) 0.124 9.846 r u_cpu/u_csr/write_buffer_way[1]_i_18/O
|
|
net (fo=1, routed) 0.000 9.846 u_cpu/u_csr/write_buffer_way[1]_i_18_n_0
|
|
SLICE_X50Y46 r u_cpu/u_csr/write_buffer_way_reg[1]_i_11/S[0]
|
|
SLICE_X50Y46 CARRY4 (Prop_carry4_S[0]_CO[3])
|
|
0.532 10.378 r u_cpu/u_csr/write_buffer_way_reg[1]_i_11/CO[3]
|
|
net (fo=1, routed) 0.000 10.378 u_cpu/u_csr/write_buffer_way_reg[1]_i_11_n_0
|
|
SLICE_X50Y47 r u_cpu/u_csr/write_buffer_way_reg[1]_i_9/CI
|
|
SLICE_X50Y47 CARRY4 (Prop_carry4_CI_CO[1])
|
|
0.157 10.535 r u_cpu/u_csr/write_buffer_way_reg[1]_i_9/CO[1]
|
|
net (fo=2, routed) 0.791 11.326 u_cpu/wb_stage/CO[0]
|
|
SLICE_X46Y39 r u_cpu/wb_stage/write_buffer_way[1]_i_5/I1
|
|
SLICE_X46Y39 LUT6 (Prop_lut6_I1_O) 0.329 11.655 f u_cpu/wb_stage/write_buffer_way[1]_i_5/O
|
|
net (fo=7, routed) 0.762 12.417 u_cpu/addr_trans/tlb_entry/sc_cancel_req
|
|
SLICE_X46Y35 f u_cpu/addr_trans/tlb_entry/main_state[0]_i_3/I1
|
|
SLICE_X46Y35 LUT3 (Prop_lut3_I1_O) 0.124 12.541 f u_cpu/addr_trans/tlb_entry/main_state[0]_i_3/O
|
|
net (fo=3, routed) 0.719 13.260 u_cpu/dcache/main_state_reg[0]_2
|
|
SLICE_X43Y31 f u_cpu/dcache/ds_to_es_bus_r[235]_i_10/I3
|
|
SLICE_X43Y31 LUT6 (Prop_lut6_I3_O) 0.124 13.384 f u_cpu/dcache/ds_to_es_bus_r[235]_i_10/O
|
|
net (fo=3, routed) 0.415 13.799 u_cpu/mem_stage/data_data_ok
|
|
SLICE_X43Y30 f u_cpu/mem_stage/flush_inst_req_buffer[1]_i_15/I0
|
|
SLICE_X43Y30 LUT3 (Prop_lut3_I0_O) 0.124 13.923 f u_cpu/mem_stage/flush_inst_req_buffer[1]_i_15/O
|
|
net (fo=2, routed) 0.833 14.756 u_cpu/mem_stage/es_to_ms_bus_r_reg[70]_1
|
|
SLICE_X48Y30 f u_cpu/mem_stage/flush_inst_req_buffer[1]_i_14/I0
|
|
SLICE_X48Y30 LUT6 (Prop_lut6_I0_O) 0.124 14.880 f u_cpu/mem_stage/flush_inst_req_buffer[1]_i_14/O
|
|
net (fo=1, routed) 0.651 15.532 u_cpu/mem_stage/ms_ready_go
|
|
SLICE_X48Y25 f u_cpu/mem_stage/flush_inst_req_buffer[1]_i_13/I4
|
|
SLICE_X48Y25 LUT6 (Prop_lut6_I4_O) 0.124 15.656 f u_cpu/mem_stage/flush_inst_req_buffer[1]_i_13/O
|
|
net (fo=3, routed) 0.483 16.139 u_cpu/id_stage/flush_inst_req_buffer[31]_i_6
|
|
SLICE_X50Y25 f u_cpu/id_stage/flush_inst_req_buffer[1]_i_9/I1
|
|
SLICE_X50Y25 LUT6 (Prop_lut6_I1_O) 0.124 16.263 f u_cpu/id_stage/flush_inst_req_buffer[1]_i_9/O
|
|
net (fo=32, routed) 0.531 16.794 u_cpu/if_stage/nextpc5
|
|
SLICE_X51Y27 f u_cpu/if_stage/fetch_pc_r[6]_i_4/I2
|
|
SLICE_X51Y27 LUT6 (Prop_lut6_I2_O) 0.124 16.918 r u_cpu/if_stage/fetch_pc_r[6]_i_4/O
|
|
net (fo=1, routed) 3.059 19.977 u_cpu/if_stage/fetch_pc_r[6]_i_4_n_0
|
|
SLICE_X114Y28 r u_cpu/if_stage/fetch_pc_r[6]_i_2/I2
|
|
SLICE_X114Y28 LUT6 (Prop_lut6_I2_O) 0.124 20.101 r u_cpu/if_stage/fetch_pc_r[6]_i_2/O
|
|
net (fo=1, routed) 0.441 20.542 u_cpu/if_stage/fetch_pc_r[6]_i_2_n_0
|
|
SLICE_X114Y25 r u_cpu/if_stage/fetch_pc_r[6]_i_1/I2
|
|
SLICE_X114Y25 LUT6 (Prop_lut6_I2_O) 0.124 20.666 r u_cpu/if_stage/fetch_pc_r[6]_i_1/O
|
|
net (fo=6, routed) 3.249 23.915 u_cpu/icache/tagv_ram_way[1].u/mem_reg_reg_2[2]
|
|
SLICE_X49Y33 r u_cpu/icache/tagv_ram_way[1].u/mem_reg_reg_i_8/I4
|
|
SLICE_X49Y33 LUT5 (Prop_lut5_I4_O) 0.124 24.039 r u_cpu/icache/tagv_ram_way[1].u/mem_reg_reg_i_8/O
|
|
net (fo=16, routed) 1.412 25.451 u_cpu/icache/data_ram_way[0].data_ram_bank[0].u/ADDRBWRADDR[2]
|
|
RAMB18_X2Y4 RAMB18E1 r u_cpu/icache/data_ram_way[0].data_ram_bank[0].u/mem_reg_reg/ADDRARDADDR[7]
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock cpu_clk rise edge) 30.323 30.323 r
|
|
clock source latency -5.674 24.648
|
|
propagated clock network latency
|
|
3.777 28.425
|
|
clock pessimism -0.418 28.007
|
|
clock uncertainty -0.074 27.933
|
|
RAMB18_X2Y4 RAMB18E1 (Setup_ramb18e1_CLKARDCLK_ADDRARDADDR[7])
|
|
-0.566 27.367 u_cpu/icache/data_ram_way[0].data_ram_bank[0].u/mem_reg_reg
|
|
-------------------------------------------------------------------
|
|
required time 27.367
|
|
arrival time -25.451
|
|
-------------------------------------------------------------------
|
|
slack 1.916
|
|
|
|
Slack (MET) : 1.916ns (required time - arrival time)
|
|
Source: u_cpu/addr_trans/data_vaddr_buffer_reg[14]/C
|
|
(rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns})
|
|
Destination: u_cpu/icache/data_ram_way[0].data_ram_bank[0].u/mem_reg_reg/ADDRARDADDR[7]
|
|
(rising edge-triggered cell RAMB18E1 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns})
|
|
Path Group: cpu_clk
|
|
Path Type: Setup (Max at Slow Process Corner)
|
|
Requirement: 30.323ns (cpu_clk rise@30.323ns - cpu_clk rise@0.000ns)
|
|
Data Path Delay: 27.676ns (logic 5.333ns (19.269%) route 22.343ns (80.731%))
|
|
Logic Levels: 26 (CARRY4=4 LUT3=2 LUT4=1 LUT5=2 LUT6=15 MUXF7=1 MUXF8=1)
|
|
Clock Path Skew: -0.091ns (DCD - SCD + CPR)
|
|
Destination Clock Delay (DCD): -1.897ns = ( 28.425 - 30.323 )
|
|
Source Clock Delay (SCD): -2.225ns
|
|
Clock Pessimism Removal (CPR): -0.418ns
|
|
Clock Uncertainty: 0.074ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Discrete Jitter (DJ): 0.130ns
|
|
Phase Error (PE): 0.000ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock cpu_clk rise edge) 0.000 0.000 r
|
|
clock source latency -6.275 -6.275
|
|
propagated clock network latency
|
|
4.051 -2.225
|
|
SLICE_X35Y35 FDRE 0.000 -2.225 r u_cpu/addr_trans/data_vaddr_buffer_reg[14]/C
|
|
SLICE_X35Y35 FDRE (Prop_fdre_C_Q) 0.456 -1.769 r u_cpu/addr_trans/data_vaddr_buffer_reg[14]/Q
|
|
net (fo=33, routed) 1.442 -0.326 u_cpu/addr_trans/tlb_entry/data_vaddr_buffer[2]
|
|
SLICE_X42Y40 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_226/I5
|
|
SLICE_X42Y40 LUT6 (Prop_lut6_I5_O) 0.124 -0.202 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_226/O
|
|
net (fo=1, routed) 0.000 -0.202 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_226_n_0
|
|
SLICE_X42Y40 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_111/S[0]
|
|
SLICE_X42Y40 CARRY4 (Prop_carry4_S[0]_CO[3])
|
|
0.513 0.311 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_111/CO[3]
|
|
net (fo=1, routed) 0.000 0.311 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_111_n_0
|
|
SLICE_X42Y41 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_32/CI
|
|
SLICE_X42Y41 CARRY4 (Prop_carry4_CI_CO[2])
|
|
0.229 0.540 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_32/CO[2]
|
|
net (fo=1, routed) 1.009 1.549 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_32_n_1
|
|
SLICE_X40Y47 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_9/I1
|
|
SLICE_X40Y47 LUT6 (Prop_lut6_I1_O) 0.310 1.859 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_9/O
|
|
net (fo=2, routed) 0.635 2.494 u_cpu/addr_trans/tlb_entry/match1[28]
|
|
SLICE_X38Y47 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/I2
|
|
SLICE_X38Y47 LUT4 (Prop_lut4_I2_O) 0.124 2.618 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/O
|
|
net (fo=2, routed) 0.667 3.285 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2_n_0
|
|
SLICE_X39Y47 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/I0
|
|
SLICE_X39Y47 LUT5 (Prop_lut5_I0_O) 0.124 3.409 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/O
|
|
net (fo=2, routed) 1.103 4.512 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2_n_0
|
|
SLICE_X38Y50 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/I0
|
|
SLICE_X38Y50 LUT6 (Prop_lut6_I0_O) 0.124 4.636 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/O
|
|
net (fo=89, routed) 1.162 5.797 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus[8]
|
|
SLICE_X42Y51 r u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_38__0/S
|
|
SLICE_X42Y51 MUXF7 (Prop_muxf7_S_O) 0.292 6.089 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_38__0/O
|
|
net (fo=1, routed) 0.000 6.089 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_38__0_n_0
|
|
SLICE_X42Y51 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_16__0/I1
|
|
SLICE_X42Y51 MUXF8 (Prop_muxf8_I1_O) 0.088 6.177 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_16__0/O
|
|
net (fo=1, routed) 0.957 7.134 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_16__0_n_0
|
|
SLICE_X42Y50 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7/I0
|
|
SLICE_X42Y50 LUT6 (Prop_lut6_I0_O) 0.319 7.453 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7/O
|
|
net (fo=1, routed) 0.435 7.888 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7_n_0
|
|
SLICE_X44Y50 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0/I5
|
|
SLICE_X44Y50 LUT6 (Prop_lut6_I5_O) 0.124 8.012 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0/O
|
|
net (fo=10, routed) 0.740 8.753 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0_n_0
|
|
SLICE_X44Y50 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[5]_i_1__0/I3
|
|
SLICE_X44Y50 LUT6 (Prop_lut6_I3_O) 0.124 8.877 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[5]_i_1__0/O
|
|
net (fo=6, routed) 0.845 9.722 u_cpu/u_csr/ms_to_ws_bus[13]
|
|
SLICE_X50Y46 r u_cpu/u_csr/write_buffer_way[1]_i_18/I3
|
|
SLICE_X50Y46 LUT6 (Prop_lut6_I3_O) 0.124 9.846 f u_cpu/u_csr/write_buffer_way[1]_i_18/O
|
|
net (fo=1, routed) 0.000 9.846 u_cpu/u_csr/write_buffer_way[1]_i_18_n_0
|
|
SLICE_X50Y46 f u_cpu/u_csr/write_buffer_way_reg[1]_i_11/S[0]
|
|
SLICE_X50Y46 CARRY4 (Prop_carry4_S[0]_CO[3])
|
|
0.532 10.378 r u_cpu/u_csr/write_buffer_way_reg[1]_i_11/CO[3]
|
|
net (fo=1, routed) 0.000 10.378 u_cpu/u_csr/write_buffer_way_reg[1]_i_11_n_0
|
|
SLICE_X50Y47 r u_cpu/u_csr/write_buffer_way_reg[1]_i_9/CI
|
|
SLICE_X50Y47 CARRY4 (Prop_carry4_CI_CO[1])
|
|
0.157 10.535 r u_cpu/u_csr/write_buffer_way_reg[1]_i_9/CO[1]
|
|
net (fo=2, routed) 0.791 11.326 u_cpu/wb_stage/CO[0]
|
|
SLICE_X46Y39 r u_cpu/wb_stage/write_buffer_way[1]_i_5/I1
|
|
SLICE_X46Y39 LUT6 (Prop_lut6_I1_O) 0.329 11.655 f u_cpu/wb_stage/write_buffer_way[1]_i_5/O
|
|
net (fo=7, routed) 0.762 12.417 u_cpu/addr_trans/tlb_entry/sc_cancel_req
|
|
SLICE_X46Y35 f u_cpu/addr_trans/tlb_entry/main_state[0]_i_3/I1
|
|
SLICE_X46Y35 LUT3 (Prop_lut3_I1_O) 0.124 12.541 f u_cpu/addr_trans/tlb_entry/main_state[0]_i_3/O
|
|
net (fo=3, routed) 0.719 13.260 u_cpu/dcache/main_state_reg[0]_2
|
|
SLICE_X43Y31 f u_cpu/dcache/ds_to_es_bus_r[235]_i_10/I3
|
|
SLICE_X43Y31 LUT6 (Prop_lut6_I3_O) 0.124 13.384 f u_cpu/dcache/ds_to_es_bus_r[235]_i_10/O
|
|
net (fo=3, routed) 0.415 13.799 u_cpu/mem_stage/data_data_ok
|
|
SLICE_X43Y30 f u_cpu/mem_stage/flush_inst_req_buffer[1]_i_15/I0
|
|
SLICE_X43Y30 LUT3 (Prop_lut3_I0_O) 0.124 13.923 f u_cpu/mem_stage/flush_inst_req_buffer[1]_i_15/O
|
|
net (fo=2, routed) 0.833 14.756 u_cpu/mem_stage/es_to_ms_bus_r_reg[70]_1
|
|
SLICE_X48Y30 f u_cpu/mem_stage/flush_inst_req_buffer[1]_i_14/I0
|
|
SLICE_X48Y30 LUT6 (Prop_lut6_I0_O) 0.124 14.880 f u_cpu/mem_stage/flush_inst_req_buffer[1]_i_14/O
|
|
net (fo=1, routed) 0.651 15.532 u_cpu/mem_stage/ms_ready_go
|
|
SLICE_X48Y25 f u_cpu/mem_stage/flush_inst_req_buffer[1]_i_13/I4
|
|
SLICE_X48Y25 LUT6 (Prop_lut6_I4_O) 0.124 15.656 f u_cpu/mem_stage/flush_inst_req_buffer[1]_i_13/O
|
|
net (fo=3, routed) 0.483 16.139 u_cpu/id_stage/flush_inst_req_buffer[31]_i_6
|
|
SLICE_X50Y25 f u_cpu/id_stage/flush_inst_req_buffer[1]_i_9/I1
|
|
SLICE_X50Y25 LUT6 (Prop_lut6_I1_O) 0.124 16.263 f u_cpu/id_stage/flush_inst_req_buffer[1]_i_9/O
|
|
net (fo=32, routed) 0.531 16.794 u_cpu/if_stage/nextpc5
|
|
SLICE_X51Y27 f u_cpu/if_stage/fetch_pc_r[6]_i_4/I2
|
|
SLICE_X51Y27 LUT6 (Prop_lut6_I2_O) 0.124 16.918 r u_cpu/if_stage/fetch_pc_r[6]_i_4/O
|
|
net (fo=1, routed) 3.059 19.977 u_cpu/if_stage/fetch_pc_r[6]_i_4_n_0
|
|
SLICE_X114Y28 r u_cpu/if_stage/fetch_pc_r[6]_i_2/I2
|
|
SLICE_X114Y28 LUT6 (Prop_lut6_I2_O) 0.124 20.101 r u_cpu/if_stage/fetch_pc_r[6]_i_2/O
|
|
net (fo=1, routed) 0.441 20.542 u_cpu/if_stage/fetch_pc_r[6]_i_2_n_0
|
|
SLICE_X114Y25 r u_cpu/if_stage/fetch_pc_r[6]_i_1/I2
|
|
SLICE_X114Y25 LUT6 (Prop_lut6_I2_O) 0.124 20.666 r u_cpu/if_stage/fetch_pc_r[6]_i_1/O
|
|
net (fo=6, routed) 3.249 23.915 u_cpu/icache/tagv_ram_way[1].u/mem_reg_reg_2[2]
|
|
SLICE_X49Y33 r u_cpu/icache/tagv_ram_way[1].u/mem_reg_reg_i_8/I4
|
|
SLICE_X49Y33 LUT5 (Prop_lut5_I4_O) 0.124 24.039 r u_cpu/icache/tagv_ram_way[1].u/mem_reg_reg_i_8/O
|
|
net (fo=16, routed) 1.412 25.451 u_cpu/icache/data_ram_way[0].data_ram_bank[0].u/ADDRBWRADDR[2]
|
|
RAMB18_X2Y4 RAMB18E1 r u_cpu/icache/data_ram_way[0].data_ram_bank[0].u/mem_reg_reg/ADDRARDADDR[7]
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock cpu_clk rise edge) 30.323 30.323 r
|
|
clock source latency -5.674 24.648
|
|
propagated clock network latency
|
|
3.777 28.425
|
|
clock pessimism -0.418 28.007
|
|
clock uncertainty -0.074 27.933
|
|
RAMB18_X2Y4 RAMB18E1 (Setup_ramb18e1_CLKARDCLK_ADDRARDADDR[7])
|
|
-0.566 27.367 u_cpu/icache/data_ram_way[0].data_ram_bank[0].u/mem_reg_reg
|
|
-------------------------------------------------------------------
|
|
required time 27.367
|
|
arrival time -25.451
|
|
-------------------------------------------------------------------
|
|
slack 1.916
|
|
|
|
Slack (MET) : 1.916ns (required time - arrival time)
|
|
Source: u_cpu/addr_trans/data_vaddr_buffer_reg[14]/C
|
|
(rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns})
|
|
Destination: u_cpu/icache/data_ram_way[0].data_ram_bank[0].u/mem_reg_reg/ADDRARDADDR[7]
|
|
(rising edge-triggered cell RAMB18E1 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns})
|
|
Path Group: cpu_clk
|
|
Path Type: Setup (Max at Slow Process Corner)
|
|
Requirement: 30.323ns (cpu_clk rise@30.323ns - cpu_clk rise@0.000ns)
|
|
Data Path Delay: 27.676ns (logic 5.333ns (19.269%) route 22.343ns (80.731%))
|
|
Logic Levels: 26 (CARRY4=4 LUT3=2 LUT4=1 LUT5=2 LUT6=15 MUXF7=1 MUXF8=1)
|
|
Clock Path Skew: -0.091ns (DCD - SCD + CPR)
|
|
Destination Clock Delay (DCD): -1.897ns = ( 28.425 - 30.323 )
|
|
Source Clock Delay (SCD): -2.225ns
|
|
Clock Pessimism Removal (CPR): -0.418ns
|
|
Clock Uncertainty: 0.074ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Discrete Jitter (DJ): 0.130ns
|
|
Phase Error (PE): 0.000ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock cpu_clk rise edge) 0.000 0.000 r
|
|
clock source latency -6.275 -6.275
|
|
propagated clock network latency
|
|
4.051 -2.225
|
|
SLICE_X35Y35 FDRE 0.000 -2.225 r u_cpu/addr_trans/data_vaddr_buffer_reg[14]/C
|
|
SLICE_X35Y35 FDRE (Prop_fdre_C_Q) 0.456 -1.769 r u_cpu/addr_trans/data_vaddr_buffer_reg[14]/Q
|
|
net (fo=33, routed) 1.442 -0.326 u_cpu/addr_trans/tlb_entry/data_vaddr_buffer[2]
|
|
SLICE_X42Y40 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_226/I5
|
|
SLICE_X42Y40 LUT6 (Prop_lut6_I5_O) 0.124 -0.202 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_226/O
|
|
net (fo=1, routed) 0.000 -0.202 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_226_n_0
|
|
SLICE_X42Y40 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_111/S[0]
|
|
SLICE_X42Y40 CARRY4 (Prop_carry4_S[0]_CO[3])
|
|
0.513 0.311 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_111/CO[3]
|
|
net (fo=1, routed) 0.000 0.311 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_111_n_0
|
|
SLICE_X42Y41 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_32/CI
|
|
SLICE_X42Y41 CARRY4 (Prop_carry4_CI_CO[2])
|
|
0.229 0.540 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_32/CO[2]
|
|
net (fo=1, routed) 1.009 1.549 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_32_n_1
|
|
SLICE_X40Y47 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_9/I1
|
|
SLICE_X40Y47 LUT6 (Prop_lut6_I1_O) 0.310 1.859 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_9/O
|
|
net (fo=2, routed) 0.635 2.494 u_cpu/addr_trans/tlb_entry/match1[28]
|
|
SLICE_X38Y47 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/I2
|
|
SLICE_X38Y47 LUT4 (Prop_lut4_I2_O) 0.124 2.618 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/O
|
|
net (fo=2, routed) 0.667 3.285 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2_n_0
|
|
SLICE_X39Y47 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/I0
|
|
SLICE_X39Y47 LUT5 (Prop_lut5_I0_O) 0.124 3.409 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/O
|
|
net (fo=2, routed) 1.103 4.512 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2_n_0
|
|
SLICE_X38Y50 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/I0
|
|
SLICE_X38Y50 LUT6 (Prop_lut6_I0_O) 0.124 4.636 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/O
|
|
net (fo=89, routed) 1.162 5.797 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus[8]
|
|
SLICE_X42Y51 r u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_38__0/S
|
|
SLICE_X42Y51 MUXF7 (Prop_muxf7_S_O) 0.292 6.089 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_38__0/O
|
|
net (fo=1, routed) 0.000 6.089 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_38__0_n_0
|
|
SLICE_X42Y51 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_16__0/I1
|
|
SLICE_X42Y51 MUXF8 (Prop_muxf8_I1_O) 0.088 6.177 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_16__0/O
|
|
net (fo=1, routed) 0.957 7.134 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_16__0_n_0
|
|
SLICE_X42Y50 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7/I0
|
|
SLICE_X42Y50 LUT6 (Prop_lut6_I0_O) 0.319 7.453 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7/O
|
|
net (fo=1, routed) 0.435 7.888 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7_n_0
|
|
SLICE_X44Y50 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0/I5
|
|
SLICE_X44Y50 LUT6 (Prop_lut6_I5_O) 0.124 8.012 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0/O
|
|
net (fo=10, routed) 0.740 8.753 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0_n_0
|
|
SLICE_X44Y50 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[5]_i_1__0/I3
|
|
SLICE_X44Y50 LUT6 (Prop_lut6_I3_O) 0.124 8.877 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[5]_i_1__0/O
|
|
net (fo=6, routed) 0.845 9.722 u_cpu/u_csr/ms_to_ws_bus[13]
|
|
SLICE_X50Y46 f u_cpu/u_csr/write_buffer_way[1]_i_18/I3
|
|
SLICE_X50Y46 LUT6 (Prop_lut6_I3_O) 0.124 9.846 f u_cpu/u_csr/write_buffer_way[1]_i_18/O
|
|
net (fo=1, routed) 0.000 9.846 u_cpu/u_csr/write_buffer_way[1]_i_18_n_0
|
|
SLICE_X50Y46 f u_cpu/u_csr/write_buffer_way_reg[1]_i_11/S[0]
|
|
SLICE_X50Y46 CARRY4 (Prop_carry4_S[0]_CO[3])
|
|
0.532 10.378 r u_cpu/u_csr/write_buffer_way_reg[1]_i_11/CO[3]
|
|
net (fo=1, routed) 0.000 10.378 u_cpu/u_csr/write_buffer_way_reg[1]_i_11_n_0
|
|
SLICE_X50Y47 r u_cpu/u_csr/write_buffer_way_reg[1]_i_9/CI
|
|
SLICE_X50Y47 CARRY4 (Prop_carry4_CI_CO[1])
|
|
0.157 10.535 r u_cpu/u_csr/write_buffer_way_reg[1]_i_9/CO[1]
|
|
net (fo=2, routed) 0.791 11.326 u_cpu/wb_stage/CO[0]
|
|
SLICE_X46Y39 r u_cpu/wb_stage/write_buffer_way[1]_i_5/I1
|
|
SLICE_X46Y39 LUT6 (Prop_lut6_I1_O) 0.329 11.655 f u_cpu/wb_stage/write_buffer_way[1]_i_5/O
|
|
net (fo=7, routed) 0.762 12.417 u_cpu/addr_trans/tlb_entry/sc_cancel_req
|
|
SLICE_X46Y35 f u_cpu/addr_trans/tlb_entry/main_state[0]_i_3/I1
|
|
SLICE_X46Y35 LUT3 (Prop_lut3_I1_O) 0.124 12.541 f u_cpu/addr_trans/tlb_entry/main_state[0]_i_3/O
|
|
net (fo=3, routed) 0.719 13.260 u_cpu/dcache/main_state_reg[0]_2
|
|
SLICE_X43Y31 f u_cpu/dcache/ds_to_es_bus_r[235]_i_10/I3
|
|
SLICE_X43Y31 LUT6 (Prop_lut6_I3_O) 0.124 13.384 f u_cpu/dcache/ds_to_es_bus_r[235]_i_10/O
|
|
net (fo=3, routed) 0.415 13.799 u_cpu/mem_stage/data_data_ok
|
|
SLICE_X43Y30 f u_cpu/mem_stage/flush_inst_req_buffer[1]_i_15/I0
|
|
SLICE_X43Y30 LUT3 (Prop_lut3_I0_O) 0.124 13.923 f u_cpu/mem_stage/flush_inst_req_buffer[1]_i_15/O
|
|
net (fo=2, routed) 0.833 14.756 u_cpu/mem_stage/es_to_ms_bus_r_reg[70]_1
|
|
SLICE_X48Y30 f u_cpu/mem_stage/flush_inst_req_buffer[1]_i_14/I0
|
|
SLICE_X48Y30 LUT6 (Prop_lut6_I0_O) 0.124 14.880 f u_cpu/mem_stage/flush_inst_req_buffer[1]_i_14/O
|
|
net (fo=1, routed) 0.651 15.532 u_cpu/mem_stage/ms_ready_go
|
|
SLICE_X48Y25 f u_cpu/mem_stage/flush_inst_req_buffer[1]_i_13/I4
|
|
SLICE_X48Y25 LUT6 (Prop_lut6_I4_O) 0.124 15.656 f u_cpu/mem_stage/flush_inst_req_buffer[1]_i_13/O
|
|
net (fo=3, routed) 0.483 16.139 u_cpu/id_stage/flush_inst_req_buffer[31]_i_6
|
|
SLICE_X50Y25 f u_cpu/id_stage/flush_inst_req_buffer[1]_i_9/I1
|
|
SLICE_X50Y25 LUT6 (Prop_lut6_I1_O) 0.124 16.263 f u_cpu/id_stage/flush_inst_req_buffer[1]_i_9/O
|
|
net (fo=32, routed) 0.531 16.794 u_cpu/if_stage/nextpc5
|
|
SLICE_X51Y27 f u_cpu/if_stage/fetch_pc_r[6]_i_4/I2
|
|
SLICE_X51Y27 LUT6 (Prop_lut6_I2_O) 0.124 16.918 r u_cpu/if_stage/fetch_pc_r[6]_i_4/O
|
|
net (fo=1, routed) 3.059 19.977 u_cpu/if_stage/fetch_pc_r[6]_i_4_n_0
|
|
SLICE_X114Y28 r u_cpu/if_stage/fetch_pc_r[6]_i_2/I2
|
|
SLICE_X114Y28 LUT6 (Prop_lut6_I2_O) 0.124 20.101 r u_cpu/if_stage/fetch_pc_r[6]_i_2/O
|
|
net (fo=1, routed) 0.441 20.542 u_cpu/if_stage/fetch_pc_r[6]_i_2_n_0
|
|
SLICE_X114Y25 r u_cpu/if_stage/fetch_pc_r[6]_i_1/I2
|
|
SLICE_X114Y25 LUT6 (Prop_lut6_I2_O) 0.124 20.666 r u_cpu/if_stage/fetch_pc_r[6]_i_1/O
|
|
net (fo=6, routed) 3.249 23.915 u_cpu/icache/tagv_ram_way[1].u/mem_reg_reg_2[2]
|
|
SLICE_X49Y33 r u_cpu/icache/tagv_ram_way[1].u/mem_reg_reg_i_8/I4
|
|
SLICE_X49Y33 LUT5 (Prop_lut5_I4_O) 0.124 24.039 r u_cpu/icache/tagv_ram_way[1].u/mem_reg_reg_i_8/O
|
|
net (fo=16, routed) 1.412 25.451 u_cpu/icache/data_ram_way[0].data_ram_bank[0].u/ADDRBWRADDR[2]
|
|
RAMB18_X2Y4 RAMB18E1 r u_cpu/icache/data_ram_way[0].data_ram_bank[0].u/mem_reg_reg/ADDRARDADDR[7]
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock cpu_clk rise edge) 30.323 30.323 r
|
|
clock source latency -5.674 24.648
|
|
propagated clock network latency
|
|
3.777 28.425
|
|
clock pessimism -0.418 28.007
|
|
clock uncertainty -0.074 27.933
|
|
RAMB18_X2Y4 RAMB18E1 (Setup_ramb18e1_CLKARDCLK_ADDRARDADDR[7])
|
|
-0.566 27.367 u_cpu/icache/data_ram_way[0].data_ram_bank[0].u/mem_reg_reg
|
|
-------------------------------------------------------------------
|
|
required time 27.367
|
|
arrival time -25.451
|
|
-------------------------------------------------------------------
|
|
slack 1.916
|
|
|
|
Slack (MET) : 1.916ns (required time - arrival time)
|
|
Source: u_cpu/addr_trans/data_vaddr_buffer_reg[14]/C
|
|
(rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns})
|
|
Destination: u_cpu/icache/data_ram_way[1].data_ram_bank[2].u/mem_reg_reg/ADDRARDADDR[7]
|
|
(rising edge-triggered cell RAMB18E1 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns})
|
|
Path Group: cpu_clk
|
|
Path Type: Setup (Max at Slow Process Corner)
|
|
Requirement: 30.323ns (cpu_clk rise@30.323ns - cpu_clk rise@0.000ns)
|
|
Data Path Delay: 27.676ns (logic 5.333ns (19.269%) route 22.343ns (80.731%))
|
|
Logic Levels: 26 (CARRY4=4 LUT3=2 LUT4=1 LUT5=2 LUT6=15 MUXF7=1 MUXF8=1)
|
|
Clock Path Skew: -0.091ns (DCD - SCD + CPR)
|
|
Destination Clock Delay (DCD): -1.897ns = ( 28.425 - 30.323 )
|
|
Source Clock Delay (SCD): -2.225ns
|
|
Clock Pessimism Removal (CPR): -0.418ns
|
|
Clock Uncertainty: 0.074ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Discrete Jitter (DJ): 0.130ns
|
|
Phase Error (PE): 0.000ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock cpu_clk rise edge) 0.000 0.000 r
|
|
clock source latency -6.275 -6.275
|
|
propagated clock network latency
|
|
4.051 -2.225
|
|
SLICE_X35Y35 FDRE 0.000 -2.225 r u_cpu/addr_trans/data_vaddr_buffer_reg[14]/C
|
|
SLICE_X35Y35 FDRE (Prop_fdre_C_Q) 0.456 -1.769 r u_cpu/addr_trans/data_vaddr_buffer_reg[14]/Q
|
|
net (fo=33, routed) 1.442 -0.326 u_cpu/addr_trans/tlb_entry/data_vaddr_buffer[2]
|
|
SLICE_X42Y40 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_226/I5
|
|
SLICE_X42Y40 LUT6 (Prop_lut6_I5_O) 0.124 -0.202 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_226/O
|
|
net (fo=1, routed) 0.000 -0.202 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_226_n_0
|
|
SLICE_X42Y40 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_111/S[0]
|
|
SLICE_X42Y40 CARRY4 (Prop_carry4_S[0]_CO[3])
|
|
0.513 0.311 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_111/CO[3]
|
|
net (fo=1, routed) 0.000 0.311 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_111_n_0
|
|
SLICE_X42Y41 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_32/CI
|
|
SLICE_X42Y41 CARRY4 (Prop_carry4_CI_CO[2])
|
|
0.229 0.540 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_32/CO[2]
|
|
net (fo=1, routed) 1.009 1.549 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_32_n_1
|
|
SLICE_X40Y47 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_9/I1
|
|
SLICE_X40Y47 LUT6 (Prop_lut6_I1_O) 0.310 1.859 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_9/O
|
|
net (fo=2, routed) 0.635 2.494 u_cpu/addr_trans/tlb_entry/match1[28]
|
|
SLICE_X38Y47 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/I2
|
|
SLICE_X38Y47 LUT4 (Prop_lut4_I2_O) 0.124 2.618 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/O
|
|
net (fo=2, routed) 0.667 3.285 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2_n_0
|
|
SLICE_X39Y47 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/I0
|
|
SLICE_X39Y47 LUT5 (Prop_lut5_I0_O) 0.124 3.409 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/O
|
|
net (fo=2, routed) 1.103 4.512 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2_n_0
|
|
SLICE_X38Y50 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/I0
|
|
SLICE_X38Y50 LUT6 (Prop_lut6_I0_O) 0.124 4.636 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/O
|
|
net (fo=89, routed) 1.162 5.797 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus[8]
|
|
SLICE_X42Y51 r u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_38__0/S
|
|
SLICE_X42Y51 MUXF7 (Prop_muxf7_S_O) 0.292 6.089 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_38__0/O
|
|
net (fo=1, routed) 0.000 6.089 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_38__0_n_0
|
|
SLICE_X42Y51 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_16__0/I1
|
|
SLICE_X42Y51 MUXF8 (Prop_muxf8_I1_O) 0.088 6.177 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_16__0/O
|
|
net (fo=1, routed) 0.957 7.134 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_16__0_n_0
|
|
SLICE_X42Y50 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7/I0
|
|
SLICE_X42Y50 LUT6 (Prop_lut6_I0_O) 0.319 7.453 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7/O
|
|
net (fo=1, routed) 0.435 7.888 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7_n_0
|
|
SLICE_X44Y50 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0/I5
|
|
SLICE_X44Y50 LUT6 (Prop_lut6_I5_O) 0.124 8.012 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0/O
|
|
net (fo=10, routed) 0.740 8.753 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0_n_0
|
|
SLICE_X44Y50 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[5]_i_1__0/I3
|
|
SLICE_X44Y50 LUT6 (Prop_lut6_I3_O) 0.124 8.877 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[5]_i_1__0/O
|
|
net (fo=6, routed) 0.845 9.722 u_cpu/u_csr/ms_to_ws_bus[13]
|
|
SLICE_X50Y46 r u_cpu/u_csr/write_buffer_way[1]_i_18/I3
|
|
SLICE_X50Y46 LUT6 (Prop_lut6_I3_O) 0.124 9.846 r u_cpu/u_csr/write_buffer_way[1]_i_18/O
|
|
net (fo=1, routed) 0.000 9.846 u_cpu/u_csr/write_buffer_way[1]_i_18_n_0
|
|
SLICE_X50Y46 r u_cpu/u_csr/write_buffer_way_reg[1]_i_11/S[0]
|
|
SLICE_X50Y46 CARRY4 (Prop_carry4_S[0]_CO[3])
|
|
0.532 10.378 r u_cpu/u_csr/write_buffer_way_reg[1]_i_11/CO[3]
|
|
net (fo=1, routed) 0.000 10.378 u_cpu/u_csr/write_buffer_way_reg[1]_i_11_n_0
|
|
SLICE_X50Y47 r u_cpu/u_csr/write_buffer_way_reg[1]_i_9/CI
|
|
SLICE_X50Y47 CARRY4 (Prop_carry4_CI_CO[1])
|
|
0.157 10.535 f u_cpu/u_csr/write_buffer_way_reg[1]_i_9/CO[1]
|
|
net (fo=2, routed) 0.791 11.326 u_cpu/wb_stage/CO[0]
|
|
SLICE_X46Y39 f u_cpu/wb_stage/write_buffer_way[1]_i_5/I1
|
|
SLICE_X46Y39 LUT6 (Prop_lut6_I1_O) 0.329 11.655 r u_cpu/wb_stage/write_buffer_way[1]_i_5/O
|
|
net (fo=7, routed) 0.762 12.417 u_cpu/addr_trans/tlb_entry/sc_cancel_req
|
|
SLICE_X46Y35 r u_cpu/addr_trans/tlb_entry/main_state[0]_i_3/I1
|
|
SLICE_X46Y35 LUT3 (Prop_lut3_I1_O) 0.124 12.541 r u_cpu/addr_trans/tlb_entry/main_state[0]_i_3/O
|
|
net (fo=3, routed) 0.719 13.260 u_cpu/dcache/main_state_reg[0]_2
|
|
SLICE_X43Y31 r u_cpu/dcache/ds_to_es_bus_r[235]_i_10/I3
|
|
SLICE_X43Y31 LUT6 (Prop_lut6_I3_O) 0.124 13.384 r u_cpu/dcache/ds_to_es_bus_r[235]_i_10/O
|
|
net (fo=3, routed) 0.415 13.799 u_cpu/mem_stage/data_data_ok
|
|
SLICE_X43Y30 r u_cpu/mem_stage/flush_inst_req_buffer[1]_i_15/I0
|
|
SLICE_X43Y30 LUT3 (Prop_lut3_I0_O) 0.124 13.923 r u_cpu/mem_stage/flush_inst_req_buffer[1]_i_15/O
|
|
net (fo=2, routed) 0.833 14.756 u_cpu/mem_stage/es_to_ms_bus_r_reg[70]_1
|
|
SLICE_X48Y30 r u_cpu/mem_stage/flush_inst_req_buffer[1]_i_14/I0
|
|
SLICE_X48Y30 LUT6 (Prop_lut6_I0_O) 0.124 14.880 r u_cpu/mem_stage/flush_inst_req_buffer[1]_i_14/O
|
|
net (fo=1, routed) 0.651 15.532 u_cpu/mem_stage/ms_ready_go
|
|
SLICE_X48Y25 r u_cpu/mem_stage/flush_inst_req_buffer[1]_i_13/I4
|
|
SLICE_X48Y25 LUT6 (Prop_lut6_I4_O) 0.124 15.656 r u_cpu/mem_stage/flush_inst_req_buffer[1]_i_13/O
|
|
net (fo=3, routed) 0.483 16.139 u_cpu/id_stage/flush_inst_req_buffer[31]_i_6
|
|
SLICE_X50Y25 r u_cpu/id_stage/flush_inst_req_buffer[1]_i_9/I1
|
|
SLICE_X50Y25 LUT6 (Prop_lut6_I1_O) 0.124 16.263 r u_cpu/id_stage/flush_inst_req_buffer[1]_i_9/O
|
|
net (fo=32, routed) 0.531 16.794 u_cpu/if_stage/nextpc5
|
|
SLICE_X51Y27 r u_cpu/if_stage/fetch_pc_r[6]_i_4/I2
|
|
SLICE_X51Y27 LUT6 (Prop_lut6_I2_O) 0.124 16.918 r u_cpu/if_stage/fetch_pc_r[6]_i_4/O
|
|
net (fo=1, routed) 3.059 19.977 u_cpu/if_stage/fetch_pc_r[6]_i_4_n_0
|
|
SLICE_X114Y28 r u_cpu/if_stage/fetch_pc_r[6]_i_2/I2
|
|
SLICE_X114Y28 LUT6 (Prop_lut6_I2_O) 0.124 20.101 r u_cpu/if_stage/fetch_pc_r[6]_i_2/O
|
|
net (fo=1, routed) 0.441 20.542 u_cpu/if_stage/fetch_pc_r[6]_i_2_n_0
|
|
SLICE_X114Y25 r u_cpu/if_stage/fetch_pc_r[6]_i_1/I2
|
|
SLICE_X114Y25 LUT6 (Prop_lut6_I2_O) 0.124 20.666 r u_cpu/if_stage/fetch_pc_r[6]_i_1/O
|
|
net (fo=6, routed) 3.249 23.915 u_cpu/icache/tagv_ram_way[1].u/mem_reg_reg_2[2]
|
|
SLICE_X49Y33 r u_cpu/icache/tagv_ram_way[1].u/mem_reg_reg_i_8/I4
|
|
SLICE_X49Y33 LUT5 (Prop_lut5_I4_O) 0.124 24.039 r u_cpu/icache/tagv_ram_way[1].u/mem_reg_reg_i_8/O
|
|
net (fo=16, routed) 1.412 25.451 u_cpu/icache/data_ram_way[1].data_ram_bank[2].u/ADDRBWRADDR[2]
|
|
RAMB18_X2Y5 RAMB18E1 r u_cpu/icache/data_ram_way[1].data_ram_bank[2].u/mem_reg_reg/ADDRARDADDR[7]
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock cpu_clk rise edge) 30.323 30.323 r
|
|
clock source latency -5.674 24.648
|
|
propagated clock network latency
|
|
3.777 28.425
|
|
clock pessimism -0.418 28.007
|
|
clock uncertainty -0.074 27.933
|
|
RAMB18_X2Y5 RAMB18E1 (Setup_ramb18e1_CLKARDCLK_ADDRARDADDR[7])
|
|
-0.566 27.367 u_cpu/icache/data_ram_way[1].data_ram_bank[2].u/mem_reg_reg
|
|
-------------------------------------------------------------------
|
|
required time 27.367
|
|
arrival time -25.451
|
|
-------------------------------------------------------------------
|
|
slack 1.916
|
|
|
|
Slack (MET) : 1.916ns (required time - arrival time)
|
|
Source: u_cpu/addr_trans/data_vaddr_buffer_reg[14]/C
|
|
(rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns})
|
|
Destination: u_cpu/icache/data_ram_way[1].data_ram_bank[2].u/mem_reg_reg/ADDRARDADDR[7]
|
|
(rising edge-triggered cell RAMB18E1 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns})
|
|
Path Group: cpu_clk
|
|
Path Type: Setup (Max at Slow Process Corner)
|
|
Requirement: 30.323ns (cpu_clk rise@30.323ns - cpu_clk rise@0.000ns)
|
|
Data Path Delay: 27.676ns (logic 5.333ns (19.269%) route 22.343ns (80.731%))
|
|
Logic Levels: 26 (CARRY4=4 LUT3=2 LUT4=1 LUT5=2 LUT6=15 MUXF7=1 MUXF8=1)
|
|
Clock Path Skew: -0.091ns (DCD - SCD + CPR)
|
|
Destination Clock Delay (DCD): -1.897ns = ( 28.425 - 30.323 )
|
|
Source Clock Delay (SCD): -2.225ns
|
|
Clock Pessimism Removal (CPR): -0.418ns
|
|
Clock Uncertainty: 0.074ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Discrete Jitter (DJ): 0.130ns
|
|
Phase Error (PE): 0.000ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock cpu_clk rise edge) 0.000 0.000 r
|
|
clock source latency -6.275 -6.275
|
|
propagated clock network latency
|
|
4.051 -2.225
|
|
SLICE_X35Y35 FDRE 0.000 -2.225 r u_cpu/addr_trans/data_vaddr_buffer_reg[14]/C
|
|
SLICE_X35Y35 FDRE (Prop_fdre_C_Q) 0.456 -1.769 r u_cpu/addr_trans/data_vaddr_buffer_reg[14]/Q
|
|
net (fo=33, routed) 1.442 -0.326 u_cpu/addr_trans/tlb_entry/data_vaddr_buffer[2]
|
|
SLICE_X42Y40 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_226/I5
|
|
SLICE_X42Y40 LUT6 (Prop_lut6_I5_O) 0.124 -0.202 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_226/O
|
|
net (fo=1, routed) 0.000 -0.202 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_226_n_0
|
|
SLICE_X42Y40 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_111/S[0]
|
|
SLICE_X42Y40 CARRY4 (Prop_carry4_S[0]_CO[3])
|
|
0.513 0.311 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_111/CO[3]
|
|
net (fo=1, routed) 0.000 0.311 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_111_n_0
|
|
SLICE_X42Y41 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_32/CI
|
|
SLICE_X42Y41 CARRY4 (Prop_carry4_CI_CO[2])
|
|
0.229 0.540 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_32/CO[2]
|
|
net (fo=1, routed) 1.009 1.549 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_32_n_1
|
|
SLICE_X40Y47 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_9/I1
|
|
SLICE_X40Y47 LUT6 (Prop_lut6_I1_O) 0.310 1.859 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_9/O
|
|
net (fo=2, routed) 0.635 2.494 u_cpu/addr_trans/tlb_entry/match1[28]
|
|
SLICE_X38Y47 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/I2
|
|
SLICE_X38Y47 LUT4 (Prop_lut4_I2_O) 0.124 2.618 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/O
|
|
net (fo=2, routed) 0.667 3.285 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2_n_0
|
|
SLICE_X39Y47 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/I0
|
|
SLICE_X39Y47 LUT5 (Prop_lut5_I0_O) 0.124 3.409 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/O
|
|
net (fo=2, routed) 1.103 4.512 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2_n_0
|
|
SLICE_X38Y50 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/I0
|
|
SLICE_X38Y50 LUT6 (Prop_lut6_I0_O) 0.124 4.636 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/O
|
|
net (fo=89, routed) 1.162 5.797 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus[8]
|
|
SLICE_X42Y51 r u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_38__0/S
|
|
SLICE_X42Y51 MUXF7 (Prop_muxf7_S_O) 0.292 6.089 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_38__0/O
|
|
net (fo=1, routed) 0.000 6.089 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_38__0_n_0
|
|
SLICE_X42Y51 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_16__0/I1
|
|
SLICE_X42Y51 MUXF8 (Prop_muxf8_I1_O) 0.088 6.177 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_16__0/O
|
|
net (fo=1, routed) 0.957 7.134 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_16__0_n_0
|
|
SLICE_X42Y50 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7/I0
|
|
SLICE_X42Y50 LUT6 (Prop_lut6_I0_O) 0.319 7.453 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7/O
|
|
net (fo=1, routed) 0.435 7.888 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7_n_0
|
|
SLICE_X44Y50 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0/I5
|
|
SLICE_X44Y50 LUT6 (Prop_lut6_I5_O) 0.124 8.012 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0/O
|
|
net (fo=10, routed) 0.740 8.753 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0_n_0
|
|
SLICE_X44Y50 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[5]_i_1__0/I3
|
|
SLICE_X44Y50 LUT6 (Prop_lut6_I3_O) 0.124 8.877 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[5]_i_1__0/O
|
|
net (fo=6, routed) 0.845 9.722 u_cpu/u_csr/ms_to_ws_bus[13]
|
|
SLICE_X50Y46 f u_cpu/u_csr/write_buffer_way[1]_i_18/I3
|
|
SLICE_X50Y46 LUT6 (Prop_lut6_I3_O) 0.124 9.846 r u_cpu/u_csr/write_buffer_way[1]_i_18/O
|
|
net (fo=1, routed) 0.000 9.846 u_cpu/u_csr/write_buffer_way[1]_i_18_n_0
|
|
SLICE_X50Y46 r u_cpu/u_csr/write_buffer_way_reg[1]_i_11/S[0]
|
|
SLICE_X50Y46 CARRY4 (Prop_carry4_S[0]_CO[3])
|
|
0.532 10.378 r u_cpu/u_csr/write_buffer_way_reg[1]_i_11/CO[3]
|
|
net (fo=1, routed) 0.000 10.378 u_cpu/u_csr/write_buffer_way_reg[1]_i_11_n_0
|
|
SLICE_X50Y47 r u_cpu/u_csr/write_buffer_way_reg[1]_i_9/CI
|
|
SLICE_X50Y47 CARRY4 (Prop_carry4_CI_CO[1])
|
|
0.157 10.535 f u_cpu/u_csr/write_buffer_way_reg[1]_i_9/CO[1]
|
|
net (fo=2, routed) 0.791 11.326 u_cpu/wb_stage/CO[0]
|
|
SLICE_X46Y39 f u_cpu/wb_stage/write_buffer_way[1]_i_5/I1
|
|
SLICE_X46Y39 LUT6 (Prop_lut6_I1_O) 0.329 11.655 r u_cpu/wb_stage/write_buffer_way[1]_i_5/O
|
|
net (fo=7, routed) 0.762 12.417 u_cpu/addr_trans/tlb_entry/sc_cancel_req
|
|
SLICE_X46Y35 r u_cpu/addr_trans/tlb_entry/main_state[0]_i_3/I1
|
|
SLICE_X46Y35 LUT3 (Prop_lut3_I1_O) 0.124 12.541 r u_cpu/addr_trans/tlb_entry/main_state[0]_i_3/O
|
|
net (fo=3, routed) 0.719 13.260 u_cpu/dcache/main_state_reg[0]_2
|
|
SLICE_X43Y31 r u_cpu/dcache/ds_to_es_bus_r[235]_i_10/I3
|
|
SLICE_X43Y31 LUT6 (Prop_lut6_I3_O) 0.124 13.384 r u_cpu/dcache/ds_to_es_bus_r[235]_i_10/O
|
|
net (fo=3, routed) 0.415 13.799 u_cpu/mem_stage/data_data_ok
|
|
SLICE_X43Y30 r u_cpu/mem_stage/flush_inst_req_buffer[1]_i_15/I0
|
|
SLICE_X43Y30 LUT3 (Prop_lut3_I0_O) 0.124 13.923 r u_cpu/mem_stage/flush_inst_req_buffer[1]_i_15/O
|
|
net (fo=2, routed) 0.833 14.756 u_cpu/mem_stage/es_to_ms_bus_r_reg[70]_1
|
|
SLICE_X48Y30 r u_cpu/mem_stage/flush_inst_req_buffer[1]_i_14/I0
|
|
SLICE_X48Y30 LUT6 (Prop_lut6_I0_O) 0.124 14.880 r u_cpu/mem_stage/flush_inst_req_buffer[1]_i_14/O
|
|
net (fo=1, routed) 0.651 15.532 u_cpu/mem_stage/ms_ready_go
|
|
SLICE_X48Y25 r u_cpu/mem_stage/flush_inst_req_buffer[1]_i_13/I4
|
|
SLICE_X48Y25 LUT6 (Prop_lut6_I4_O) 0.124 15.656 r u_cpu/mem_stage/flush_inst_req_buffer[1]_i_13/O
|
|
net (fo=3, routed) 0.483 16.139 u_cpu/id_stage/flush_inst_req_buffer[31]_i_6
|
|
SLICE_X50Y25 r u_cpu/id_stage/flush_inst_req_buffer[1]_i_9/I1
|
|
SLICE_X50Y25 LUT6 (Prop_lut6_I1_O) 0.124 16.263 r u_cpu/id_stage/flush_inst_req_buffer[1]_i_9/O
|
|
net (fo=32, routed) 0.531 16.794 u_cpu/if_stage/nextpc5
|
|
SLICE_X51Y27 r u_cpu/if_stage/fetch_pc_r[6]_i_4/I2
|
|
SLICE_X51Y27 LUT6 (Prop_lut6_I2_O) 0.124 16.918 r u_cpu/if_stage/fetch_pc_r[6]_i_4/O
|
|
net (fo=1, routed) 3.059 19.977 u_cpu/if_stage/fetch_pc_r[6]_i_4_n_0
|
|
SLICE_X114Y28 r u_cpu/if_stage/fetch_pc_r[6]_i_2/I2
|
|
SLICE_X114Y28 LUT6 (Prop_lut6_I2_O) 0.124 20.101 r u_cpu/if_stage/fetch_pc_r[6]_i_2/O
|
|
net (fo=1, routed) 0.441 20.542 u_cpu/if_stage/fetch_pc_r[6]_i_2_n_0
|
|
SLICE_X114Y25 r u_cpu/if_stage/fetch_pc_r[6]_i_1/I2
|
|
SLICE_X114Y25 LUT6 (Prop_lut6_I2_O) 0.124 20.666 r u_cpu/if_stage/fetch_pc_r[6]_i_1/O
|
|
net (fo=6, routed) 3.249 23.915 u_cpu/icache/tagv_ram_way[1].u/mem_reg_reg_2[2]
|
|
SLICE_X49Y33 r u_cpu/icache/tagv_ram_way[1].u/mem_reg_reg_i_8/I4
|
|
SLICE_X49Y33 LUT5 (Prop_lut5_I4_O) 0.124 24.039 r u_cpu/icache/tagv_ram_way[1].u/mem_reg_reg_i_8/O
|
|
net (fo=16, routed) 1.412 25.451 u_cpu/icache/data_ram_way[1].data_ram_bank[2].u/ADDRBWRADDR[2]
|
|
RAMB18_X2Y5 RAMB18E1 r u_cpu/icache/data_ram_way[1].data_ram_bank[2].u/mem_reg_reg/ADDRARDADDR[7]
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock cpu_clk rise edge) 30.323 30.323 r
|
|
clock source latency -5.674 24.648
|
|
propagated clock network latency
|
|
3.777 28.425
|
|
clock pessimism -0.418 28.007
|
|
clock uncertainty -0.074 27.933
|
|
RAMB18_X2Y5 RAMB18E1 (Setup_ramb18e1_CLKARDCLK_ADDRARDADDR[7])
|
|
-0.566 27.367 u_cpu/icache/data_ram_way[1].data_ram_bank[2].u/mem_reg_reg
|
|
-------------------------------------------------------------------
|
|
required time 27.367
|
|
arrival time -25.451
|
|
-------------------------------------------------------------------
|
|
slack 1.916
|
|
|
|
Slack (MET) : 1.916ns (required time - arrival time)
|
|
Source: u_cpu/addr_trans/data_vaddr_buffer_reg[14]/C
|
|
(rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns})
|
|
Destination: u_cpu/icache/data_ram_way[1].data_ram_bank[2].u/mem_reg_reg/ADDRARDADDR[7]
|
|
(rising edge-triggered cell RAMB18E1 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns})
|
|
Path Group: cpu_clk
|
|
Path Type: Setup (Max at Slow Process Corner)
|
|
Requirement: 30.323ns (cpu_clk rise@30.323ns - cpu_clk rise@0.000ns)
|
|
Data Path Delay: 27.676ns (logic 5.333ns (19.269%) route 22.343ns (80.731%))
|
|
Logic Levels: 26 (CARRY4=4 LUT3=2 LUT4=1 LUT5=2 LUT6=15 MUXF7=1 MUXF8=1)
|
|
Clock Path Skew: -0.091ns (DCD - SCD + CPR)
|
|
Destination Clock Delay (DCD): -1.897ns = ( 28.425 - 30.323 )
|
|
Source Clock Delay (SCD): -2.225ns
|
|
Clock Pessimism Removal (CPR): -0.418ns
|
|
Clock Uncertainty: 0.074ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Discrete Jitter (DJ): 0.130ns
|
|
Phase Error (PE): 0.000ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock cpu_clk rise edge) 0.000 0.000 r
|
|
clock source latency -6.275 -6.275
|
|
propagated clock network latency
|
|
4.051 -2.225
|
|
SLICE_X35Y35 FDRE 0.000 -2.225 r u_cpu/addr_trans/data_vaddr_buffer_reg[14]/C
|
|
SLICE_X35Y35 FDRE (Prop_fdre_C_Q) 0.456 -1.769 r u_cpu/addr_trans/data_vaddr_buffer_reg[14]/Q
|
|
net (fo=33, routed) 1.442 -0.326 u_cpu/addr_trans/tlb_entry/data_vaddr_buffer[2]
|
|
SLICE_X42Y40 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_226/I5
|
|
SLICE_X42Y40 LUT6 (Prop_lut6_I5_O) 0.124 -0.202 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_226/O
|
|
net (fo=1, routed) 0.000 -0.202 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_226_n_0
|
|
SLICE_X42Y40 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_111/S[0]
|
|
SLICE_X42Y40 CARRY4 (Prop_carry4_S[0]_CO[3])
|
|
0.513 0.311 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_111/CO[3]
|
|
net (fo=1, routed) 0.000 0.311 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_111_n_0
|
|
SLICE_X42Y41 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_32/CI
|
|
SLICE_X42Y41 CARRY4 (Prop_carry4_CI_CO[2])
|
|
0.229 0.540 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_32/CO[2]
|
|
net (fo=1, routed) 1.009 1.549 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_32_n_1
|
|
SLICE_X40Y47 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_9/I1
|
|
SLICE_X40Y47 LUT6 (Prop_lut6_I1_O) 0.310 1.859 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_9/O
|
|
net (fo=2, routed) 0.635 2.494 u_cpu/addr_trans/tlb_entry/match1[28]
|
|
SLICE_X38Y47 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/I2
|
|
SLICE_X38Y47 LUT4 (Prop_lut4_I2_O) 0.124 2.618 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/O
|
|
net (fo=2, routed) 0.667 3.285 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2_n_0
|
|
SLICE_X39Y47 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/I0
|
|
SLICE_X39Y47 LUT5 (Prop_lut5_I0_O) 0.124 3.409 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/O
|
|
net (fo=2, routed) 1.103 4.512 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2_n_0
|
|
SLICE_X38Y50 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/I0
|
|
SLICE_X38Y50 LUT6 (Prop_lut6_I0_O) 0.124 4.636 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/O
|
|
net (fo=89, routed) 1.162 5.797 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus[8]
|
|
SLICE_X42Y51 r u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_38__0/S
|
|
SLICE_X42Y51 MUXF7 (Prop_muxf7_S_O) 0.292 6.089 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_38__0/O
|
|
net (fo=1, routed) 0.000 6.089 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_38__0_n_0
|
|
SLICE_X42Y51 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_16__0/I1
|
|
SLICE_X42Y51 MUXF8 (Prop_muxf8_I1_O) 0.088 6.177 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_16__0/O
|
|
net (fo=1, routed) 0.957 7.134 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_16__0_n_0
|
|
SLICE_X42Y50 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7/I0
|
|
SLICE_X42Y50 LUT6 (Prop_lut6_I0_O) 0.319 7.453 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7/O
|
|
net (fo=1, routed) 0.435 7.888 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7_n_0
|
|
SLICE_X44Y50 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0/I5
|
|
SLICE_X44Y50 LUT6 (Prop_lut6_I5_O) 0.124 8.012 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0/O
|
|
net (fo=10, routed) 0.740 8.753 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0_n_0
|
|
SLICE_X44Y50 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[5]_i_1__0/I3
|
|
SLICE_X44Y50 LUT6 (Prop_lut6_I3_O) 0.124 8.877 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[5]_i_1__0/O
|
|
net (fo=6, routed) 0.845 9.722 u_cpu/u_csr/ms_to_ws_bus[13]
|
|
SLICE_X50Y46 r u_cpu/u_csr/write_buffer_way[1]_i_18/I3
|
|
SLICE_X50Y46 LUT6 (Prop_lut6_I3_O) 0.124 9.846 f u_cpu/u_csr/write_buffer_way[1]_i_18/O
|
|
net (fo=1, routed) 0.000 9.846 u_cpu/u_csr/write_buffer_way[1]_i_18_n_0
|
|
SLICE_X50Y46 f u_cpu/u_csr/write_buffer_way_reg[1]_i_11/S[0]
|
|
SLICE_X50Y46 CARRY4 (Prop_carry4_S[0]_CO[3])
|
|
0.532 10.378 r u_cpu/u_csr/write_buffer_way_reg[1]_i_11/CO[3]
|
|
net (fo=1, routed) 0.000 10.378 u_cpu/u_csr/write_buffer_way_reg[1]_i_11_n_0
|
|
SLICE_X50Y47 r u_cpu/u_csr/write_buffer_way_reg[1]_i_9/CI
|
|
SLICE_X50Y47 CARRY4 (Prop_carry4_CI_CO[1])
|
|
0.157 10.535 f u_cpu/u_csr/write_buffer_way_reg[1]_i_9/CO[1]
|
|
net (fo=2, routed) 0.791 11.326 u_cpu/wb_stage/CO[0]
|
|
SLICE_X46Y39 f u_cpu/wb_stage/write_buffer_way[1]_i_5/I1
|
|
SLICE_X46Y39 LUT6 (Prop_lut6_I1_O) 0.329 11.655 r u_cpu/wb_stage/write_buffer_way[1]_i_5/O
|
|
net (fo=7, routed) 0.762 12.417 u_cpu/addr_trans/tlb_entry/sc_cancel_req
|
|
SLICE_X46Y35 r u_cpu/addr_trans/tlb_entry/main_state[0]_i_3/I1
|
|
SLICE_X46Y35 LUT3 (Prop_lut3_I1_O) 0.124 12.541 r u_cpu/addr_trans/tlb_entry/main_state[0]_i_3/O
|
|
net (fo=3, routed) 0.719 13.260 u_cpu/dcache/main_state_reg[0]_2
|
|
SLICE_X43Y31 r u_cpu/dcache/ds_to_es_bus_r[235]_i_10/I3
|
|
SLICE_X43Y31 LUT6 (Prop_lut6_I3_O) 0.124 13.384 r u_cpu/dcache/ds_to_es_bus_r[235]_i_10/O
|
|
net (fo=3, routed) 0.415 13.799 u_cpu/mem_stage/data_data_ok
|
|
SLICE_X43Y30 r u_cpu/mem_stage/flush_inst_req_buffer[1]_i_15/I0
|
|
SLICE_X43Y30 LUT3 (Prop_lut3_I0_O) 0.124 13.923 r u_cpu/mem_stage/flush_inst_req_buffer[1]_i_15/O
|
|
net (fo=2, routed) 0.833 14.756 u_cpu/mem_stage/es_to_ms_bus_r_reg[70]_1
|
|
SLICE_X48Y30 r u_cpu/mem_stage/flush_inst_req_buffer[1]_i_14/I0
|
|
SLICE_X48Y30 LUT6 (Prop_lut6_I0_O) 0.124 14.880 r u_cpu/mem_stage/flush_inst_req_buffer[1]_i_14/O
|
|
net (fo=1, routed) 0.651 15.532 u_cpu/mem_stage/ms_ready_go
|
|
SLICE_X48Y25 r u_cpu/mem_stage/flush_inst_req_buffer[1]_i_13/I4
|
|
SLICE_X48Y25 LUT6 (Prop_lut6_I4_O) 0.124 15.656 r u_cpu/mem_stage/flush_inst_req_buffer[1]_i_13/O
|
|
net (fo=3, routed) 0.483 16.139 u_cpu/id_stage/flush_inst_req_buffer[31]_i_6
|
|
SLICE_X50Y25 r u_cpu/id_stage/flush_inst_req_buffer[1]_i_9/I1
|
|
SLICE_X50Y25 LUT6 (Prop_lut6_I1_O) 0.124 16.263 r u_cpu/id_stage/flush_inst_req_buffer[1]_i_9/O
|
|
net (fo=32, routed) 0.531 16.794 u_cpu/if_stage/nextpc5
|
|
SLICE_X51Y27 r u_cpu/if_stage/fetch_pc_r[6]_i_4/I2
|
|
SLICE_X51Y27 LUT6 (Prop_lut6_I2_O) 0.124 16.918 r u_cpu/if_stage/fetch_pc_r[6]_i_4/O
|
|
net (fo=1, routed) 3.059 19.977 u_cpu/if_stage/fetch_pc_r[6]_i_4_n_0
|
|
SLICE_X114Y28 r u_cpu/if_stage/fetch_pc_r[6]_i_2/I2
|
|
SLICE_X114Y28 LUT6 (Prop_lut6_I2_O) 0.124 20.101 r u_cpu/if_stage/fetch_pc_r[6]_i_2/O
|
|
net (fo=1, routed) 0.441 20.542 u_cpu/if_stage/fetch_pc_r[6]_i_2_n_0
|
|
SLICE_X114Y25 r u_cpu/if_stage/fetch_pc_r[6]_i_1/I2
|
|
SLICE_X114Y25 LUT6 (Prop_lut6_I2_O) 0.124 20.666 r u_cpu/if_stage/fetch_pc_r[6]_i_1/O
|
|
net (fo=6, routed) 3.249 23.915 u_cpu/icache/tagv_ram_way[1].u/mem_reg_reg_2[2]
|
|
SLICE_X49Y33 r u_cpu/icache/tagv_ram_way[1].u/mem_reg_reg_i_8/I4
|
|
SLICE_X49Y33 LUT5 (Prop_lut5_I4_O) 0.124 24.039 r u_cpu/icache/tagv_ram_way[1].u/mem_reg_reg_i_8/O
|
|
net (fo=16, routed) 1.412 25.451 u_cpu/icache/data_ram_way[1].data_ram_bank[2].u/ADDRBWRADDR[2]
|
|
RAMB18_X2Y5 RAMB18E1 r u_cpu/icache/data_ram_way[1].data_ram_bank[2].u/mem_reg_reg/ADDRARDADDR[7]
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock cpu_clk rise edge) 30.323 30.323 r
|
|
clock source latency -5.674 24.648
|
|
propagated clock network latency
|
|
3.777 28.425
|
|
clock pessimism -0.418 28.007
|
|
clock uncertainty -0.074 27.933
|
|
RAMB18_X2Y5 RAMB18E1 (Setup_ramb18e1_CLKARDCLK_ADDRARDADDR[7])
|
|
-0.566 27.367 u_cpu/icache/data_ram_way[1].data_ram_bank[2].u/mem_reg_reg
|
|
-------------------------------------------------------------------
|
|
required time 27.367
|
|
arrival time -25.451
|
|
-------------------------------------------------------------------
|
|
slack 1.916
|
|
|
|
Slack (MET) : 1.916ns (required time - arrival time)
|
|
Source: u_cpu/addr_trans/data_vaddr_buffer_reg[14]/C
|
|
(rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns})
|
|
Destination: u_cpu/icache/data_ram_way[1].data_ram_bank[2].u/mem_reg_reg/ADDRARDADDR[7]
|
|
(rising edge-triggered cell RAMB18E1 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns})
|
|
Path Group: cpu_clk
|
|
Path Type: Setup (Max at Slow Process Corner)
|
|
Requirement: 30.323ns (cpu_clk rise@30.323ns - cpu_clk rise@0.000ns)
|
|
Data Path Delay: 27.676ns (logic 5.333ns (19.269%) route 22.343ns (80.731%))
|
|
Logic Levels: 26 (CARRY4=4 LUT3=2 LUT4=1 LUT5=2 LUT6=15 MUXF7=1 MUXF8=1)
|
|
Clock Path Skew: -0.091ns (DCD - SCD + CPR)
|
|
Destination Clock Delay (DCD): -1.897ns = ( 28.425 - 30.323 )
|
|
Source Clock Delay (SCD): -2.225ns
|
|
Clock Pessimism Removal (CPR): -0.418ns
|
|
Clock Uncertainty: 0.074ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Discrete Jitter (DJ): 0.130ns
|
|
Phase Error (PE): 0.000ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock cpu_clk rise edge) 0.000 0.000 r
|
|
clock source latency -6.275 -6.275
|
|
propagated clock network latency
|
|
4.051 -2.225
|
|
SLICE_X35Y35 FDRE 0.000 -2.225 r u_cpu/addr_trans/data_vaddr_buffer_reg[14]/C
|
|
SLICE_X35Y35 FDRE (Prop_fdre_C_Q) 0.456 -1.769 r u_cpu/addr_trans/data_vaddr_buffer_reg[14]/Q
|
|
net (fo=33, routed) 1.442 -0.326 u_cpu/addr_trans/tlb_entry/data_vaddr_buffer[2]
|
|
SLICE_X42Y40 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_226/I5
|
|
SLICE_X42Y40 LUT6 (Prop_lut6_I5_O) 0.124 -0.202 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_226/O
|
|
net (fo=1, routed) 0.000 -0.202 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_226_n_0
|
|
SLICE_X42Y40 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_111/S[0]
|
|
SLICE_X42Y40 CARRY4 (Prop_carry4_S[0]_CO[3])
|
|
0.513 0.311 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_111/CO[3]
|
|
net (fo=1, routed) 0.000 0.311 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_111_n_0
|
|
SLICE_X42Y41 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_32/CI
|
|
SLICE_X42Y41 CARRY4 (Prop_carry4_CI_CO[2])
|
|
0.229 0.540 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_32/CO[2]
|
|
net (fo=1, routed) 1.009 1.549 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_32_n_1
|
|
SLICE_X40Y47 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_9/I1
|
|
SLICE_X40Y47 LUT6 (Prop_lut6_I1_O) 0.310 1.859 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_9/O
|
|
net (fo=2, routed) 0.635 2.494 u_cpu/addr_trans/tlb_entry/match1[28]
|
|
SLICE_X38Y47 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/I2
|
|
SLICE_X38Y47 LUT4 (Prop_lut4_I2_O) 0.124 2.618 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/O
|
|
net (fo=2, routed) 0.667 3.285 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2_n_0
|
|
SLICE_X39Y47 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/I0
|
|
SLICE_X39Y47 LUT5 (Prop_lut5_I0_O) 0.124 3.409 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/O
|
|
net (fo=2, routed) 1.103 4.512 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2_n_0
|
|
SLICE_X38Y50 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/I0
|
|
SLICE_X38Y50 LUT6 (Prop_lut6_I0_O) 0.124 4.636 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/O
|
|
net (fo=89, routed) 1.162 5.797 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus[8]
|
|
SLICE_X42Y51 r u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_38__0/S
|
|
SLICE_X42Y51 MUXF7 (Prop_muxf7_S_O) 0.292 6.089 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_38__0/O
|
|
net (fo=1, routed) 0.000 6.089 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_38__0_n_0
|
|
SLICE_X42Y51 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_16__0/I1
|
|
SLICE_X42Y51 MUXF8 (Prop_muxf8_I1_O) 0.088 6.177 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_16__0/O
|
|
net (fo=1, routed) 0.957 7.134 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_16__0_n_0
|
|
SLICE_X42Y50 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7/I0
|
|
SLICE_X42Y50 LUT6 (Prop_lut6_I0_O) 0.319 7.453 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7/O
|
|
net (fo=1, routed) 0.435 7.888 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7_n_0
|
|
SLICE_X44Y50 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0/I5
|
|
SLICE_X44Y50 LUT6 (Prop_lut6_I5_O) 0.124 8.012 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0/O
|
|
net (fo=10, routed) 0.740 8.753 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0_n_0
|
|
SLICE_X44Y50 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[5]_i_1__0/I3
|
|
SLICE_X44Y50 LUT6 (Prop_lut6_I3_O) 0.124 8.877 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[5]_i_1__0/O
|
|
net (fo=6, routed) 0.845 9.722 u_cpu/u_csr/ms_to_ws_bus[13]
|
|
SLICE_X50Y46 f u_cpu/u_csr/write_buffer_way[1]_i_18/I3
|
|
SLICE_X50Y46 LUT6 (Prop_lut6_I3_O) 0.124 9.846 f u_cpu/u_csr/write_buffer_way[1]_i_18/O
|
|
net (fo=1, routed) 0.000 9.846 u_cpu/u_csr/write_buffer_way[1]_i_18_n_0
|
|
SLICE_X50Y46 f u_cpu/u_csr/write_buffer_way_reg[1]_i_11/S[0]
|
|
SLICE_X50Y46 CARRY4 (Prop_carry4_S[0]_CO[3])
|
|
0.532 10.378 r u_cpu/u_csr/write_buffer_way_reg[1]_i_11/CO[3]
|
|
net (fo=1, routed) 0.000 10.378 u_cpu/u_csr/write_buffer_way_reg[1]_i_11_n_0
|
|
SLICE_X50Y47 r u_cpu/u_csr/write_buffer_way_reg[1]_i_9/CI
|
|
SLICE_X50Y47 CARRY4 (Prop_carry4_CI_CO[1])
|
|
0.157 10.535 f u_cpu/u_csr/write_buffer_way_reg[1]_i_9/CO[1]
|
|
net (fo=2, routed) 0.791 11.326 u_cpu/wb_stage/CO[0]
|
|
SLICE_X46Y39 f u_cpu/wb_stage/write_buffer_way[1]_i_5/I1
|
|
SLICE_X46Y39 LUT6 (Prop_lut6_I1_O) 0.329 11.655 r u_cpu/wb_stage/write_buffer_way[1]_i_5/O
|
|
net (fo=7, routed) 0.762 12.417 u_cpu/addr_trans/tlb_entry/sc_cancel_req
|
|
SLICE_X46Y35 r u_cpu/addr_trans/tlb_entry/main_state[0]_i_3/I1
|
|
SLICE_X46Y35 LUT3 (Prop_lut3_I1_O) 0.124 12.541 r u_cpu/addr_trans/tlb_entry/main_state[0]_i_3/O
|
|
net (fo=3, routed) 0.719 13.260 u_cpu/dcache/main_state_reg[0]_2
|
|
SLICE_X43Y31 r u_cpu/dcache/ds_to_es_bus_r[235]_i_10/I3
|
|
SLICE_X43Y31 LUT6 (Prop_lut6_I3_O) 0.124 13.384 r u_cpu/dcache/ds_to_es_bus_r[235]_i_10/O
|
|
net (fo=3, routed) 0.415 13.799 u_cpu/mem_stage/data_data_ok
|
|
SLICE_X43Y30 r u_cpu/mem_stage/flush_inst_req_buffer[1]_i_15/I0
|
|
SLICE_X43Y30 LUT3 (Prop_lut3_I0_O) 0.124 13.923 r u_cpu/mem_stage/flush_inst_req_buffer[1]_i_15/O
|
|
net (fo=2, routed) 0.833 14.756 u_cpu/mem_stage/es_to_ms_bus_r_reg[70]_1
|
|
SLICE_X48Y30 r u_cpu/mem_stage/flush_inst_req_buffer[1]_i_14/I0
|
|
SLICE_X48Y30 LUT6 (Prop_lut6_I0_O) 0.124 14.880 r u_cpu/mem_stage/flush_inst_req_buffer[1]_i_14/O
|
|
net (fo=1, routed) 0.651 15.532 u_cpu/mem_stage/ms_ready_go
|
|
SLICE_X48Y25 r u_cpu/mem_stage/flush_inst_req_buffer[1]_i_13/I4
|
|
SLICE_X48Y25 LUT6 (Prop_lut6_I4_O) 0.124 15.656 r u_cpu/mem_stage/flush_inst_req_buffer[1]_i_13/O
|
|
net (fo=3, routed) 0.483 16.139 u_cpu/id_stage/flush_inst_req_buffer[31]_i_6
|
|
SLICE_X50Y25 r u_cpu/id_stage/flush_inst_req_buffer[1]_i_9/I1
|
|
SLICE_X50Y25 LUT6 (Prop_lut6_I1_O) 0.124 16.263 r u_cpu/id_stage/flush_inst_req_buffer[1]_i_9/O
|
|
net (fo=32, routed) 0.531 16.794 u_cpu/if_stage/nextpc5
|
|
SLICE_X51Y27 r u_cpu/if_stage/fetch_pc_r[6]_i_4/I2
|
|
SLICE_X51Y27 LUT6 (Prop_lut6_I2_O) 0.124 16.918 r u_cpu/if_stage/fetch_pc_r[6]_i_4/O
|
|
net (fo=1, routed) 3.059 19.977 u_cpu/if_stage/fetch_pc_r[6]_i_4_n_0
|
|
SLICE_X114Y28 r u_cpu/if_stage/fetch_pc_r[6]_i_2/I2
|
|
SLICE_X114Y28 LUT6 (Prop_lut6_I2_O) 0.124 20.101 r u_cpu/if_stage/fetch_pc_r[6]_i_2/O
|
|
net (fo=1, routed) 0.441 20.542 u_cpu/if_stage/fetch_pc_r[6]_i_2_n_0
|
|
SLICE_X114Y25 r u_cpu/if_stage/fetch_pc_r[6]_i_1/I2
|
|
SLICE_X114Y25 LUT6 (Prop_lut6_I2_O) 0.124 20.666 r u_cpu/if_stage/fetch_pc_r[6]_i_1/O
|
|
net (fo=6, routed) 3.249 23.915 u_cpu/icache/tagv_ram_way[1].u/mem_reg_reg_2[2]
|
|
SLICE_X49Y33 r u_cpu/icache/tagv_ram_way[1].u/mem_reg_reg_i_8/I4
|
|
SLICE_X49Y33 LUT5 (Prop_lut5_I4_O) 0.124 24.039 r u_cpu/icache/tagv_ram_way[1].u/mem_reg_reg_i_8/O
|
|
net (fo=16, routed) 1.412 25.451 u_cpu/icache/data_ram_way[1].data_ram_bank[2].u/ADDRBWRADDR[2]
|
|
RAMB18_X2Y5 RAMB18E1 r u_cpu/icache/data_ram_way[1].data_ram_bank[2].u/mem_reg_reg/ADDRARDADDR[7]
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock cpu_clk rise edge) 30.323 30.323 r
|
|
clock source latency -5.674 24.648
|
|
propagated clock network latency
|
|
3.777 28.425
|
|
clock pessimism -0.418 28.007
|
|
clock uncertainty -0.074 27.933
|
|
RAMB18_X2Y5 RAMB18E1 (Setup_ramb18e1_CLKARDCLK_ADDRARDADDR[7])
|
|
-0.566 27.367 u_cpu/icache/data_ram_way[1].data_ram_bank[2].u/mem_reg_reg
|
|
-------------------------------------------------------------------
|
|
required time 27.367
|
|
arrival time -25.451
|
|
-------------------------------------------------------------------
|
|
slack 1.916
|
|
|
|
Slack (MET) : 1.916ns (required time - arrival time)
|
|
Source: u_cpu/addr_trans/data_vaddr_buffer_reg[14]/C
|
|
(rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns})
|
|
Destination: u_cpu/icache/data_ram_way[1].data_ram_bank[2].u/mem_reg_reg/ADDRARDADDR[7]
|
|
(rising edge-triggered cell RAMB18E1 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns})
|
|
Path Group: cpu_clk
|
|
Path Type: Setup (Max at Slow Process Corner)
|
|
Requirement: 30.323ns (cpu_clk rise@30.323ns - cpu_clk rise@0.000ns)
|
|
Data Path Delay: 27.676ns (logic 5.333ns (19.269%) route 22.343ns (80.731%))
|
|
Logic Levels: 26 (CARRY4=4 LUT3=2 LUT4=1 LUT5=2 LUT6=15 MUXF7=1 MUXF8=1)
|
|
Clock Path Skew: -0.091ns (DCD - SCD + CPR)
|
|
Destination Clock Delay (DCD): -1.897ns = ( 28.425 - 30.323 )
|
|
Source Clock Delay (SCD): -2.225ns
|
|
Clock Pessimism Removal (CPR): -0.418ns
|
|
Clock Uncertainty: 0.074ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Discrete Jitter (DJ): 0.130ns
|
|
Phase Error (PE): 0.000ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock cpu_clk rise edge) 0.000 0.000 r
|
|
clock source latency -6.275 -6.275
|
|
propagated clock network latency
|
|
4.051 -2.225
|
|
SLICE_X35Y35 FDRE 0.000 -2.225 r u_cpu/addr_trans/data_vaddr_buffer_reg[14]/C
|
|
SLICE_X35Y35 FDRE (Prop_fdre_C_Q) 0.456 -1.769 r u_cpu/addr_trans/data_vaddr_buffer_reg[14]/Q
|
|
net (fo=33, routed) 1.442 -0.326 u_cpu/addr_trans/tlb_entry/data_vaddr_buffer[2]
|
|
SLICE_X42Y40 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_226/I5
|
|
SLICE_X42Y40 LUT6 (Prop_lut6_I5_O) 0.124 -0.202 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_226/O
|
|
net (fo=1, routed) 0.000 -0.202 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_226_n_0
|
|
SLICE_X42Y40 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_111/S[0]
|
|
SLICE_X42Y40 CARRY4 (Prop_carry4_S[0]_CO[3])
|
|
0.513 0.311 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_111/CO[3]
|
|
net (fo=1, routed) 0.000 0.311 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_111_n_0
|
|
SLICE_X42Y41 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_32/CI
|
|
SLICE_X42Y41 CARRY4 (Prop_carry4_CI_CO[2])
|
|
0.229 0.540 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_32/CO[2]
|
|
net (fo=1, routed) 1.009 1.549 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_32_n_1
|
|
SLICE_X40Y47 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_9/I1
|
|
SLICE_X40Y47 LUT6 (Prop_lut6_I1_O) 0.310 1.859 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_9/O
|
|
net (fo=2, routed) 0.635 2.494 u_cpu/addr_trans/tlb_entry/match1[28]
|
|
SLICE_X38Y47 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/I2
|
|
SLICE_X38Y47 LUT4 (Prop_lut4_I2_O) 0.124 2.618 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/O
|
|
net (fo=2, routed) 0.667 3.285 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2_n_0
|
|
SLICE_X39Y47 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/I0
|
|
SLICE_X39Y47 LUT5 (Prop_lut5_I0_O) 0.124 3.409 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/O
|
|
net (fo=2, routed) 1.103 4.512 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2_n_0
|
|
SLICE_X38Y50 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/I0
|
|
SLICE_X38Y50 LUT6 (Prop_lut6_I0_O) 0.124 4.636 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/O
|
|
net (fo=89, routed) 1.162 5.797 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus[8]
|
|
SLICE_X42Y51 r u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_38__0/S
|
|
SLICE_X42Y51 MUXF7 (Prop_muxf7_S_O) 0.292 6.089 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_38__0/O
|
|
net (fo=1, routed) 0.000 6.089 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_38__0_n_0
|
|
SLICE_X42Y51 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_16__0/I1
|
|
SLICE_X42Y51 MUXF8 (Prop_muxf8_I1_O) 0.088 6.177 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_16__0/O
|
|
net (fo=1, routed) 0.957 7.134 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_16__0_n_0
|
|
SLICE_X42Y50 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7/I0
|
|
SLICE_X42Y50 LUT6 (Prop_lut6_I0_O) 0.319 7.453 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7/O
|
|
net (fo=1, routed) 0.435 7.888 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7_n_0
|
|
SLICE_X44Y50 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0/I5
|
|
SLICE_X44Y50 LUT6 (Prop_lut6_I5_O) 0.124 8.012 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0/O
|
|
net (fo=10, routed) 0.740 8.753 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0_n_0
|
|
SLICE_X44Y50 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[5]_i_1__0/I3
|
|
SLICE_X44Y50 LUT6 (Prop_lut6_I3_O) 0.124 8.877 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[5]_i_1__0/O
|
|
net (fo=6, routed) 0.845 9.722 u_cpu/u_csr/ms_to_ws_bus[13]
|
|
SLICE_X50Y46 r u_cpu/u_csr/write_buffer_way[1]_i_18/I3
|
|
SLICE_X50Y46 LUT6 (Prop_lut6_I3_O) 0.124 9.846 r u_cpu/u_csr/write_buffer_way[1]_i_18/O
|
|
net (fo=1, routed) 0.000 9.846 u_cpu/u_csr/write_buffer_way[1]_i_18_n_0
|
|
SLICE_X50Y46 r u_cpu/u_csr/write_buffer_way_reg[1]_i_11/S[0]
|
|
SLICE_X50Y46 CARRY4 (Prop_carry4_S[0]_CO[3])
|
|
0.532 10.378 f u_cpu/u_csr/write_buffer_way_reg[1]_i_11/CO[3]
|
|
net (fo=1, routed) 0.000 10.378 u_cpu/u_csr/write_buffer_way_reg[1]_i_11_n_0
|
|
SLICE_X50Y47 f u_cpu/u_csr/write_buffer_way_reg[1]_i_9/CI
|
|
SLICE_X50Y47 CARRY4 (Prop_carry4_CI_CO[1])
|
|
0.157 10.535 f u_cpu/u_csr/write_buffer_way_reg[1]_i_9/CO[1]
|
|
net (fo=2, routed) 0.791 11.326 u_cpu/wb_stage/CO[0]
|
|
SLICE_X46Y39 f u_cpu/wb_stage/write_buffer_way[1]_i_5/I1
|
|
SLICE_X46Y39 LUT6 (Prop_lut6_I1_O) 0.329 11.655 r u_cpu/wb_stage/write_buffer_way[1]_i_5/O
|
|
net (fo=7, routed) 0.762 12.417 u_cpu/addr_trans/tlb_entry/sc_cancel_req
|
|
SLICE_X46Y35 r u_cpu/addr_trans/tlb_entry/main_state[0]_i_3/I1
|
|
SLICE_X46Y35 LUT3 (Prop_lut3_I1_O) 0.124 12.541 r u_cpu/addr_trans/tlb_entry/main_state[0]_i_3/O
|
|
net (fo=3, routed) 0.719 13.260 u_cpu/dcache/main_state_reg[0]_2
|
|
SLICE_X43Y31 r u_cpu/dcache/ds_to_es_bus_r[235]_i_10/I3
|
|
SLICE_X43Y31 LUT6 (Prop_lut6_I3_O) 0.124 13.384 r u_cpu/dcache/ds_to_es_bus_r[235]_i_10/O
|
|
net (fo=3, routed) 0.415 13.799 u_cpu/mem_stage/data_data_ok
|
|
SLICE_X43Y30 r u_cpu/mem_stage/flush_inst_req_buffer[1]_i_15/I0
|
|
SLICE_X43Y30 LUT3 (Prop_lut3_I0_O) 0.124 13.923 r u_cpu/mem_stage/flush_inst_req_buffer[1]_i_15/O
|
|
net (fo=2, routed) 0.833 14.756 u_cpu/mem_stage/es_to_ms_bus_r_reg[70]_1
|
|
SLICE_X48Y30 r u_cpu/mem_stage/flush_inst_req_buffer[1]_i_14/I0
|
|
SLICE_X48Y30 LUT6 (Prop_lut6_I0_O) 0.124 14.880 r u_cpu/mem_stage/flush_inst_req_buffer[1]_i_14/O
|
|
net (fo=1, routed) 0.651 15.532 u_cpu/mem_stage/ms_ready_go
|
|
SLICE_X48Y25 r u_cpu/mem_stage/flush_inst_req_buffer[1]_i_13/I4
|
|
SLICE_X48Y25 LUT6 (Prop_lut6_I4_O) 0.124 15.656 r u_cpu/mem_stage/flush_inst_req_buffer[1]_i_13/O
|
|
net (fo=3, routed) 0.483 16.139 u_cpu/id_stage/flush_inst_req_buffer[31]_i_6
|
|
SLICE_X50Y25 r u_cpu/id_stage/flush_inst_req_buffer[1]_i_9/I1
|
|
SLICE_X50Y25 LUT6 (Prop_lut6_I1_O) 0.124 16.263 r u_cpu/id_stage/flush_inst_req_buffer[1]_i_9/O
|
|
net (fo=32, routed) 0.531 16.794 u_cpu/if_stage/nextpc5
|
|
SLICE_X51Y27 r u_cpu/if_stage/fetch_pc_r[6]_i_4/I2
|
|
SLICE_X51Y27 LUT6 (Prop_lut6_I2_O) 0.124 16.918 r u_cpu/if_stage/fetch_pc_r[6]_i_4/O
|
|
net (fo=1, routed) 3.059 19.977 u_cpu/if_stage/fetch_pc_r[6]_i_4_n_0
|
|
SLICE_X114Y28 r u_cpu/if_stage/fetch_pc_r[6]_i_2/I2
|
|
SLICE_X114Y28 LUT6 (Prop_lut6_I2_O) 0.124 20.101 r u_cpu/if_stage/fetch_pc_r[6]_i_2/O
|
|
net (fo=1, routed) 0.441 20.542 u_cpu/if_stage/fetch_pc_r[6]_i_2_n_0
|
|
SLICE_X114Y25 r u_cpu/if_stage/fetch_pc_r[6]_i_1/I2
|
|
SLICE_X114Y25 LUT6 (Prop_lut6_I2_O) 0.124 20.666 r u_cpu/if_stage/fetch_pc_r[6]_i_1/O
|
|
net (fo=6, routed) 3.249 23.915 u_cpu/icache/tagv_ram_way[1].u/mem_reg_reg_2[2]
|
|
SLICE_X49Y33 r u_cpu/icache/tagv_ram_way[1].u/mem_reg_reg_i_8/I4
|
|
SLICE_X49Y33 LUT5 (Prop_lut5_I4_O) 0.124 24.039 r u_cpu/icache/tagv_ram_way[1].u/mem_reg_reg_i_8/O
|
|
net (fo=16, routed) 1.412 25.451 u_cpu/icache/data_ram_way[1].data_ram_bank[2].u/ADDRBWRADDR[2]
|
|
RAMB18_X2Y5 RAMB18E1 r u_cpu/icache/data_ram_way[1].data_ram_bank[2].u/mem_reg_reg/ADDRARDADDR[7]
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock cpu_clk rise edge) 30.323 30.323 r
|
|
clock source latency -5.674 24.648
|
|
propagated clock network latency
|
|
3.777 28.425
|
|
clock pessimism -0.418 28.007
|
|
clock uncertainty -0.074 27.933
|
|
RAMB18_X2Y5 RAMB18E1 (Setup_ramb18e1_CLKARDCLK_ADDRARDADDR[7])
|
|
-0.566 27.367 u_cpu/icache/data_ram_way[1].data_ram_bank[2].u/mem_reg_reg
|
|
-------------------------------------------------------------------
|
|
required time 27.367
|
|
arrival time -25.451
|
|
-------------------------------------------------------------------
|
|
slack 1.916
|
|
|
|
Slack (MET) : 1.916ns (required time - arrival time)
|
|
Source: u_cpu/addr_trans/data_vaddr_buffer_reg[14]/C
|
|
(rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns})
|
|
Destination: u_cpu/icache/data_ram_way[1].data_ram_bank[2].u/mem_reg_reg/ADDRARDADDR[7]
|
|
(rising edge-triggered cell RAMB18E1 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns})
|
|
Path Group: cpu_clk
|
|
Path Type: Setup (Max at Slow Process Corner)
|
|
Requirement: 30.323ns (cpu_clk rise@30.323ns - cpu_clk rise@0.000ns)
|
|
Data Path Delay: 27.676ns (logic 5.333ns (19.269%) route 22.343ns (80.731%))
|
|
Logic Levels: 26 (CARRY4=4 LUT3=2 LUT4=1 LUT5=2 LUT6=15 MUXF7=1 MUXF8=1)
|
|
Clock Path Skew: -0.091ns (DCD - SCD + CPR)
|
|
Destination Clock Delay (DCD): -1.897ns = ( 28.425 - 30.323 )
|
|
Source Clock Delay (SCD): -2.225ns
|
|
Clock Pessimism Removal (CPR): -0.418ns
|
|
Clock Uncertainty: 0.074ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Discrete Jitter (DJ): 0.130ns
|
|
Phase Error (PE): 0.000ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock cpu_clk rise edge) 0.000 0.000 r
|
|
clock source latency -6.275 -6.275
|
|
propagated clock network latency
|
|
4.051 -2.225
|
|
SLICE_X35Y35 FDRE 0.000 -2.225 r u_cpu/addr_trans/data_vaddr_buffer_reg[14]/C
|
|
SLICE_X35Y35 FDRE (Prop_fdre_C_Q) 0.456 -1.769 r u_cpu/addr_trans/data_vaddr_buffer_reg[14]/Q
|
|
net (fo=33, routed) 1.442 -0.326 u_cpu/addr_trans/tlb_entry/data_vaddr_buffer[2]
|
|
SLICE_X42Y40 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_226/I5
|
|
SLICE_X42Y40 LUT6 (Prop_lut6_I5_O) 0.124 -0.202 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_226/O
|
|
net (fo=1, routed) 0.000 -0.202 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_226_n_0
|
|
SLICE_X42Y40 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_111/S[0]
|
|
SLICE_X42Y40 CARRY4 (Prop_carry4_S[0]_CO[3])
|
|
0.513 0.311 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_111/CO[3]
|
|
net (fo=1, routed) 0.000 0.311 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_111_n_0
|
|
SLICE_X42Y41 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_32/CI
|
|
SLICE_X42Y41 CARRY4 (Prop_carry4_CI_CO[2])
|
|
0.229 0.540 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_32/CO[2]
|
|
net (fo=1, routed) 1.009 1.549 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_32_n_1
|
|
SLICE_X40Y47 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_9/I1
|
|
SLICE_X40Y47 LUT6 (Prop_lut6_I1_O) 0.310 1.859 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_9/O
|
|
net (fo=2, routed) 0.635 2.494 u_cpu/addr_trans/tlb_entry/match1[28]
|
|
SLICE_X38Y47 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/I2
|
|
SLICE_X38Y47 LUT4 (Prop_lut4_I2_O) 0.124 2.618 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/O
|
|
net (fo=2, routed) 0.667 3.285 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2_n_0
|
|
SLICE_X39Y47 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/I0
|
|
SLICE_X39Y47 LUT5 (Prop_lut5_I0_O) 0.124 3.409 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/O
|
|
net (fo=2, routed) 1.103 4.512 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2_n_0
|
|
SLICE_X38Y50 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/I0
|
|
SLICE_X38Y50 LUT6 (Prop_lut6_I0_O) 0.124 4.636 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/O
|
|
net (fo=89, routed) 1.162 5.797 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus[8]
|
|
SLICE_X42Y51 r u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_38__0/S
|
|
SLICE_X42Y51 MUXF7 (Prop_muxf7_S_O) 0.292 6.089 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_38__0/O
|
|
net (fo=1, routed) 0.000 6.089 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_38__0_n_0
|
|
SLICE_X42Y51 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_16__0/I1
|
|
SLICE_X42Y51 MUXF8 (Prop_muxf8_I1_O) 0.088 6.177 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_16__0/O
|
|
net (fo=1, routed) 0.957 7.134 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_16__0_n_0
|
|
SLICE_X42Y50 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7/I0
|
|
SLICE_X42Y50 LUT6 (Prop_lut6_I0_O) 0.319 7.453 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7/O
|
|
net (fo=1, routed) 0.435 7.888 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7_n_0
|
|
SLICE_X44Y50 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0/I5
|
|
SLICE_X44Y50 LUT6 (Prop_lut6_I5_O) 0.124 8.012 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0/O
|
|
net (fo=10, routed) 0.740 8.753 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0_n_0
|
|
SLICE_X44Y50 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[5]_i_1__0/I3
|
|
SLICE_X44Y50 LUT6 (Prop_lut6_I3_O) 0.124 8.877 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[5]_i_1__0/O
|
|
net (fo=6, routed) 0.845 9.722 u_cpu/u_csr/ms_to_ws_bus[13]
|
|
SLICE_X50Y46 f u_cpu/u_csr/write_buffer_way[1]_i_18/I3
|
|
SLICE_X50Y46 LUT6 (Prop_lut6_I3_O) 0.124 9.846 r u_cpu/u_csr/write_buffer_way[1]_i_18/O
|
|
net (fo=1, routed) 0.000 9.846 u_cpu/u_csr/write_buffer_way[1]_i_18_n_0
|
|
SLICE_X50Y46 r u_cpu/u_csr/write_buffer_way_reg[1]_i_11/S[0]
|
|
SLICE_X50Y46 CARRY4 (Prop_carry4_S[0]_CO[3])
|
|
0.532 10.378 f u_cpu/u_csr/write_buffer_way_reg[1]_i_11/CO[3]
|
|
net (fo=1, routed) 0.000 10.378 u_cpu/u_csr/write_buffer_way_reg[1]_i_11_n_0
|
|
SLICE_X50Y47 f u_cpu/u_csr/write_buffer_way_reg[1]_i_9/CI
|
|
SLICE_X50Y47 CARRY4 (Prop_carry4_CI_CO[1])
|
|
0.157 10.535 f u_cpu/u_csr/write_buffer_way_reg[1]_i_9/CO[1]
|
|
net (fo=2, routed) 0.791 11.326 u_cpu/wb_stage/CO[0]
|
|
SLICE_X46Y39 f u_cpu/wb_stage/write_buffer_way[1]_i_5/I1
|
|
SLICE_X46Y39 LUT6 (Prop_lut6_I1_O) 0.329 11.655 r u_cpu/wb_stage/write_buffer_way[1]_i_5/O
|
|
net (fo=7, routed) 0.762 12.417 u_cpu/addr_trans/tlb_entry/sc_cancel_req
|
|
SLICE_X46Y35 r u_cpu/addr_trans/tlb_entry/main_state[0]_i_3/I1
|
|
SLICE_X46Y35 LUT3 (Prop_lut3_I1_O) 0.124 12.541 r u_cpu/addr_trans/tlb_entry/main_state[0]_i_3/O
|
|
net (fo=3, routed) 0.719 13.260 u_cpu/dcache/main_state_reg[0]_2
|
|
SLICE_X43Y31 r u_cpu/dcache/ds_to_es_bus_r[235]_i_10/I3
|
|
SLICE_X43Y31 LUT6 (Prop_lut6_I3_O) 0.124 13.384 r u_cpu/dcache/ds_to_es_bus_r[235]_i_10/O
|
|
net (fo=3, routed) 0.415 13.799 u_cpu/mem_stage/data_data_ok
|
|
SLICE_X43Y30 r u_cpu/mem_stage/flush_inst_req_buffer[1]_i_15/I0
|
|
SLICE_X43Y30 LUT3 (Prop_lut3_I0_O) 0.124 13.923 r u_cpu/mem_stage/flush_inst_req_buffer[1]_i_15/O
|
|
net (fo=2, routed) 0.833 14.756 u_cpu/mem_stage/es_to_ms_bus_r_reg[70]_1
|
|
SLICE_X48Y30 r u_cpu/mem_stage/flush_inst_req_buffer[1]_i_14/I0
|
|
SLICE_X48Y30 LUT6 (Prop_lut6_I0_O) 0.124 14.880 r u_cpu/mem_stage/flush_inst_req_buffer[1]_i_14/O
|
|
net (fo=1, routed) 0.651 15.532 u_cpu/mem_stage/ms_ready_go
|
|
SLICE_X48Y25 r u_cpu/mem_stage/flush_inst_req_buffer[1]_i_13/I4
|
|
SLICE_X48Y25 LUT6 (Prop_lut6_I4_O) 0.124 15.656 r u_cpu/mem_stage/flush_inst_req_buffer[1]_i_13/O
|
|
net (fo=3, routed) 0.483 16.139 u_cpu/id_stage/flush_inst_req_buffer[31]_i_6
|
|
SLICE_X50Y25 r u_cpu/id_stage/flush_inst_req_buffer[1]_i_9/I1
|
|
SLICE_X50Y25 LUT6 (Prop_lut6_I1_O) 0.124 16.263 r u_cpu/id_stage/flush_inst_req_buffer[1]_i_9/O
|
|
net (fo=32, routed) 0.531 16.794 u_cpu/if_stage/nextpc5
|
|
SLICE_X51Y27 r u_cpu/if_stage/fetch_pc_r[6]_i_4/I2
|
|
SLICE_X51Y27 LUT6 (Prop_lut6_I2_O) 0.124 16.918 r u_cpu/if_stage/fetch_pc_r[6]_i_4/O
|
|
net (fo=1, routed) 3.059 19.977 u_cpu/if_stage/fetch_pc_r[6]_i_4_n_0
|
|
SLICE_X114Y28 r u_cpu/if_stage/fetch_pc_r[6]_i_2/I2
|
|
SLICE_X114Y28 LUT6 (Prop_lut6_I2_O) 0.124 20.101 r u_cpu/if_stage/fetch_pc_r[6]_i_2/O
|
|
net (fo=1, routed) 0.441 20.542 u_cpu/if_stage/fetch_pc_r[6]_i_2_n_0
|
|
SLICE_X114Y25 r u_cpu/if_stage/fetch_pc_r[6]_i_1/I2
|
|
SLICE_X114Y25 LUT6 (Prop_lut6_I2_O) 0.124 20.666 r u_cpu/if_stage/fetch_pc_r[6]_i_1/O
|
|
net (fo=6, routed) 3.249 23.915 u_cpu/icache/tagv_ram_way[1].u/mem_reg_reg_2[2]
|
|
SLICE_X49Y33 r u_cpu/icache/tagv_ram_way[1].u/mem_reg_reg_i_8/I4
|
|
SLICE_X49Y33 LUT5 (Prop_lut5_I4_O) 0.124 24.039 r u_cpu/icache/tagv_ram_way[1].u/mem_reg_reg_i_8/O
|
|
net (fo=16, routed) 1.412 25.451 u_cpu/icache/data_ram_way[1].data_ram_bank[2].u/ADDRBWRADDR[2]
|
|
RAMB18_X2Y5 RAMB18E1 r u_cpu/icache/data_ram_way[1].data_ram_bank[2].u/mem_reg_reg/ADDRARDADDR[7]
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock cpu_clk rise edge) 30.323 30.323 r
|
|
clock source latency -5.674 24.648
|
|
propagated clock network latency
|
|
3.777 28.425
|
|
clock pessimism -0.418 28.007
|
|
clock uncertainty -0.074 27.933
|
|
RAMB18_X2Y5 RAMB18E1 (Setup_ramb18e1_CLKARDCLK_ADDRARDADDR[7])
|
|
-0.566 27.367 u_cpu/icache/data_ram_way[1].data_ram_bank[2].u/mem_reg_reg
|
|
-------------------------------------------------------------------
|
|
required time 27.367
|
|
arrival time -25.451
|
|
-------------------------------------------------------------------
|
|
slack 1.916
|
|
|
|
Slack (MET) : 1.916ns (required time - arrival time)
|
|
Source: u_cpu/addr_trans/data_vaddr_buffer_reg[14]/C
|
|
(rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns})
|
|
Destination: u_cpu/icache/data_ram_way[1].data_ram_bank[2].u/mem_reg_reg/ADDRARDADDR[7]
|
|
(rising edge-triggered cell RAMB18E1 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns})
|
|
Path Group: cpu_clk
|
|
Path Type: Setup (Max at Slow Process Corner)
|
|
Requirement: 30.323ns (cpu_clk rise@30.323ns - cpu_clk rise@0.000ns)
|
|
Data Path Delay: 27.676ns (logic 5.333ns (19.269%) route 22.343ns (80.731%))
|
|
Logic Levels: 26 (CARRY4=4 LUT3=2 LUT4=1 LUT5=2 LUT6=15 MUXF7=1 MUXF8=1)
|
|
Clock Path Skew: -0.091ns (DCD - SCD + CPR)
|
|
Destination Clock Delay (DCD): -1.897ns = ( 28.425 - 30.323 )
|
|
Source Clock Delay (SCD): -2.225ns
|
|
Clock Pessimism Removal (CPR): -0.418ns
|
|
Clock Uncertainty: 0.074ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Discrete Jitter (DJ): 0.130ns
|
|
Phase Error (PE): 0.000ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock cpu_clk rise edge) 0.000 0.000 r
|
|
clock source latency -6.275 -6.275
|
|
propagated clock network latency
|
|
4.051 -2.225
|
|
SLICE_X35Y35 FDRE 0.000 -2.225 r u_cpu/addr_trans/data_vaddr_buffer_reg[14]/C
|
|
SLICE_X35Y35 FDRE (Prop_fdre_C_Q) 0.456 -1.769 r u_cpu/addr_trans/data_vaddr_buffer_reg[14]/Q
|
|
net (fo=33, routed) 1.442 -0.326 u_cpu/addr_trans/tlb_entry/data_vaddr_buffer[2]
|
|
SLICE_X42Y40 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_226/I5
|
|
SLICE_X42Y40 LUT6 (Prop_lut6_I5_O) 0.124 -0.202 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_226/O
|
|
net (fo=1, routed) 0.000 -0.202 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_226_n_0
|
|
SLICE_X42Y40 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_111/S[0]
|
|
SLICE_X42Y40 CARRY4 (Prop_carry4_S[0]_CO[3])
|
|
0.513 0.311 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_111/CO[3]
|
|
net (fo=1, routed) 0.000 0.311 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_111_n_0
|
|
SLICE_X42Y41 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_32/CI
|
|
SLICE_X42Y41 CARRY4 (Prop_carry4_CI_CO[2])
|
|
0.229 0.540 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_32/CO[2]
|
|
net (fo=1, routed) 1.009 1.549 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_32_n_1
|
|
SLICE_X40Y47 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_9/I1
|
|
SLICE_X40Y47 LUT6 (Prop_lut6_I1_O) 0.310 1.859 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_9/O
|
|
net (fo=2, routed) 0.635 2.494 u_cpu/addr_trans/tlb_entry/match1[28]
|
|
SLICE_X38Y47 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/I2
|
|
SLICE_X38Y47 LUT4 (Prop_lut4_I2_O) 0.124 2.618 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/O
|
|
net (fo=2, routed) 0.667 3.285 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2_n_0
|
|
SLICE_X39Y47 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/I0
|
|
SLICE_X39Y47 LUT5 (Prop_lut5_I0_O) 0.124 3.409 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/O
|
|
net (fo=2, routed) 1.103 4.512 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2_n_0
|
|
SLICE_X38Y50 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/I0
|
|
SLICE_X38Y50 LUT6 (Prop_lut6_I0_O) 0.124 4.636 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/O
|
|
net (fo=89, routed) 1.162 5.797 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus[8]
|
|
SLICE_X42Y51 r u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_38__0/S
|
|
SLICE_X42Y51 MUXF7 (Prop_muxf7_S_O) 0.292 6.089 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_38__0/O
|
|
net (fo=1, routed) 0.000 6.089 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_38__0_n_0
|
|
SLICE_X42Y51 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_16__0/I1
|
|
SLICE_X42Y51 MUXF8 (Prop_muxf8_I1_O) 0.088 6.177 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_16__0/O
|
|
net (fo=1, routed) 0.957 7.134 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_16__0_n_0
|
|
SLICE_X42Y50 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7/I0
|
|
SLICE_X42Y50 LUT6 (Prop_lut6_I0_O) 0.319 7.453 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7/O
|
|
net (fo=1, routed) 0.435 7.888 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7_n_0
|
|
SLICE_X44Y50 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0/I5
|
|
SLICE_X44Y50 LUT6 (Prop_lut6_I5_O) 0.124 8.012 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0/O
|
|
net (fo=10, routed) 0.740 8.753 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0_n_0
|
|
SLICE_X44Y50 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[5]_i_1__0/I3
|
|
SLICE_X44Y50 LUT6 (Prop_lut6_I3_O) 0.124 8.877 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[5]_i_1__0/O
|
|
net (fo=6, routed) 0.845 9.722 u_cpu/u_csr/ms_to_ws_bus[13]
|
|
SLICE_X50Y46 r u_cpu/u_csr/write_buffer_way[1]_i_18/I3
|
|
SLICE_X50Y46 LUT6 (Prop_lut6_I3_O) 0.124 9.846 r u_cpu/u_csr/write_buffer_way[1]_i_18/O
|
|
net (fo=1, routed) 0.000 9.846 u_cpu/u_csr/write_buffer_way[1]_i_18_n_0
|
|
SLICE_X50Y46 r u_cpu/u_csr/write_buffer_way_reg[1]_i_11/S[0]
|
|
SLICE_X50Y46 CARRY4 (Prop_carry4_S[0]_CO[3])
|
|
0.532 10.378 r u_cpu/u_csr/write_buffer_way_reg[1]_i_11/CO[3]
|
|
net (fo=1, routed) 0.000 10.378 u_cpu/u_csr/write_buffer_way_reg[1]_i_11_n_0
|
|
SLICE_X50Y47 r u_cpu/u_csr/write_buffer_way_reg[1]_i_9/CI
|
|
SLICE_X50Y47 CARRY4 (Prop_carry4_CI_CO[1])
|
|
0.157 10.535 r u_cpu/u_csr/write_buffer_way_reg[1]_i_9/CO[1]
|
|
net (fo=2, routed) 0.791 11.326 u_cpu/wb_stage/CO[0]
|
|
SLICE_X46Y39 r u_cpu/wb_stage/write_buffer_way[1]_i_5/I1
|
|
SLICE_X46Y39 LUT6 (Prop_lut6_I1_O) 0.329 11.655 f u_cpu/wb_stage/write_buffer_way[1]_i_5/O
|
|
net (fo=7, routed) 0.762 12.417 u_cpu/addr_trans/tlb_entry/sc_cancel_req
|
|
SLICE_X46Y35 f u_cpu/addr_trans/tlb_entry/main_state[0]_i_3/I1
|
|
SLICE_X46Y35 LUT3 (Prop_lut3_I1_O) 0.124 12.541 f u_cpu/addr_trans/tlb_entry/main_state[0]_i_3/O
|
|
net (fo=3, routed) 0.719 13.260 u_cpu/dcache/main_state_reg[0]_2
|
|
SLICE_X43Y31 f u_cpu/dcache/ds_to_es_bus_r[235]_i_10/I3
|
|
SLICE_X43Y31 LUT6 (Prop_lut6_I3_O) 0.124 13.384 f u_cpu/dcache/ds_to_es_bus_r[235]_i_10/O
|
|
net (fo=3, routed) 0.415 13.799 u_cpu/mem_stage/data_data_ok
|
|
SLICE_X43Y30 f u_cpu/mem_stage/flush_inst_req_buffer[1]_i_15/I0
|
|
SLICE_X43Y30 LUT3 (Prop_lut3_I0_O) 0.124 13.923 f u_cpu/mem_stage/flush_inst_req_buffer[1]_i_15/O
|
|
net (fo=2, routed) 0.833 14.756 u_cpu/mem_stage/es_to_ms_bus_r_reg[70]_1
|
|
SLICE_X48Y30 f u_cpu/mem_stage/flush_inst_req_buffer[1]_i_14/I0
|
|
SLICE_X48Y30 LUT6 (Prop_lut6_I0_O) 0.124 14.880 f u_cpu/mem_stage/flush_inst_req_buffer[1]_i_14/O
|
|
net (fo=1, routed) 0.651 15.532 u_cpu/mem_stage/ms_ready_go
|
|
SLICE_X48Y25 f u_cpu/mem_stage/flush_inst_req_buffer[1]_i_13/I4
|
|
SLICE_X48Y25 LUT6 (Prop_lut6_I4_O) 0.124 15.656 f u_cpu/mem_stage/flush_inst_req_buffer[1]_i_13/O
|
|
net (fo=3, routed) 0.483 16.139 u_cpu/id_stage/flush_inst_req_buffer[31]_i_6
|
|
SLICE_X50Y25 f u_cpu/id_stage/flush_inst_req_buffer[1]_i_9/I1
|
|
SLICE_X50Y25 LUT6 (Prop_lut6_I1_O) 0.124 16.263 f u_cpu/id_stage/flush_inst_req_buffer[1]_i_9/O
|
|
net (fo=32, routed) 0.531 16.794 u_cpu/if_stage/nextpc5
|
|
SLICE_X51Y27 f u_cpu/if_stage/fetch_pc_r[6]_i_4/I2
|
|
SLICE_X51Y27 LUT6 (Prop_lut6_I2_O) 0.124 16.918 r u_cpu/if_stage/fetch_pc_r[6]_i_4/O
|
|
net (fo=1, routed) 3.059 19.977 u_cpu/if_stage/fetch_pc_r[6]_i_4_n_0
|
|
SLICE_X114Y28 r u_cpu/if_stage/fetch_pc_r[6]_i_2/I2
|
|
SLICE_X114Y28 LUT6 (Prop_lut6_I2_O) 0.124 20.101 r u_cpu/if_stage/fetch_pc_r[6]_i_2/O
|
|
net (fo=1, routed) 0.441 20.542 u_cpu/if_stage/fetch_pc_r[6]_i_2_n_0
|
|
SLICE_X114Y25 r u_cpu/if_stage/fetch_pc_r[6]_i_1/I2
|
|
SLICE_X114Y25 LUT6 (Prop_lut6_I2_O) 0.124 20.666 r u_cpu/if_stage/fetch_pc_r[6]_i_1/O
|
|
net (fo=6, routed) 3.249 23.915 u_cpu/icache/tagv_ram_way[1].u/mem_reg_reg_2[2]
|
|
SLICE_X49Y33 r u_cpu/icache/tagv_ram_way[1].u/mem_reg_reg_i_8/I4
|
|
SLICE_X49Y33 LUT5 (Prop_lut5_I4_O) 0.124 24.039 r u_cpu/icache/tagv_ram_way[1].u/mem_reg_reg_i_8/O
|
|
net (fo=16, routed) 1.412 25.451 u_cpu/icache/data_ram_way[1].data_ram_bank[2].u/ADDRBWRADDR[2]
|
|
RAMB18_X2Y5 RAMB18E1 r u_cpu/icache/data_ram_way[1].data_ram_bank[2].u/mem_reg_reg/ADDRARDADDR[7]
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock cpu_clk rise edge) 30.323 30.323 r
|
|
clock source latency -5.674 24.648
|
|
propagated clock network latency
|
|
3.777 28.425
|
|
clock pessimism -0.418 28.007
|
|
clock uncertainty -0.074 27.933
|
|
RAMB18_X2Y5 RAMB18E1 (Setup_ramb18e1_CLKARDCLK_ADDRARDADDR[7])
|
|
-0.566 27.367 u_cpu/icache/data_ram_way[1].data_ram_bank[2].u/mem_reg_reg
|
|
-------------------------------------------------------------------
|
|
required time 27.367
|
|
arrival time -25.451
|
|
-------------------------------------------------------------------
|
|
slack 1.916
|
|
|
|
Slack (MET) : 1.916ns (required time - arrival time)
|
|
Source: u_cpu/addr_trans/data_vaddr_buffer_reg[14]/C
|
|
(rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns})
|
|
Destination: u_cpu/icache/data_ram_way[1].data_ram_bank[2].u/mem_reg_reg/ADDRARDADDR[7]
|
|
(rising edge-triggered cell RAMB18E1 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns})
|
|
Path Group: cpu_clk
|
|
Path Type: Setup (Max at Slow Process Corner)
|
|
Requirement: 30.323ns (cpu_clk rise@30.323ns - cpu_clk rise@0.000ns)
|
|
Data Path Delay: 27.676ns (logic 5.333ns (19.269%) route 22.343ns (80.731%))
|
|
Logic Levels: 26 (CARRY4=4 LUT3=2 LUT4=1 LUT5=2 LUT6=15 MUXF7=1 MUXF8=1)
|
|
Clock Path Skew: -0.091ns (DCD - SCD + CPR)
|
|
Destination Clock Delay (DCD): -1.897ns = ( 28.425 - 30.323 )
|
|
Source Clock Delay (SCD): -2.225ns
|
|
Clock Pessimism Removal (CPR): -0.418ns
|
|
Clock Uncertainty: 0.074ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Discrete Jitter (DJ): 0.130ns
|
|
Phase Error (PE): 0.000ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock cpu_clk rise edge) 0.000 0.000 r
|
|
clock source latency -6.275 -6.275
|
|
propagated clock network latency
|
|
4.051 -2.225
|
|
SLICE_X35Y35 FDRE 0.000 -2.225 r u_cpu/addr_trans/data_vaddr_buffer_reg[14]/C
|
|
SLICE_X35Y35 FDRE (Prop_fdre_C_Q) 0.456 -1.769 r u_cpu/addr_trans/data_vaddr_buffer_reg[14]/Q
|
|
net (fo=33, routed) 1.442 -0.326 u_cpu/addr_trans/tlb_entry/data_vaddr_buffer[2]
|
|
SLICE_X42Y40 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_226/I5
|
|
SLICE_X42Y40 LUT6 (Prop_lut6_I5_O) 0.124 -0.202 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_226/O
|
|
net (fo=1, routed) 0.000 -0.202 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_226_n_0
|
|
SLICE_X42Y40 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_111/S[0]
|
|
SLICE_X42Y40 CARRY4 (Prop_carry4_S[0]_CO[3])
|
|
0.513 0.311 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_111/CO[3]
|
|
net (fo=1, routed) 0.000 0.311 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_111_n_0
|
|
SLICE_X42Y41 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_32/CI
|
|
SLICE_X42Y41 CARRY4 (Prop_carry4_CI_CO[2])
|
|
0.229 0.540 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_32/CO[2]
|
|
net (fo=1, routed) 1.009 1.549 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_32_n_1
|
|
SLICE_X40Y47 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_9/I1
|
|
SLICE_X40Y47 LUT6 (Prop_lut6_I1_O) 0.310 1.859 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_9/O
|
|
net (fo=2, routed) 0.635 2.494 u_cpu/addr_trans/tlb_entry/match1[28]
|
|
SLICE_X38Y47 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/I2
|
|
SLICE_X38Y47 LUT4 (Prop_lut4_I2_O) 0.124 2.618 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/O
|
|
net (fo=2, routed) 0.667 3.285 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2_n_0
|
|
SLICE_X39Y47 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/I0
|
|
SLICE_X39Y47 LUT5 (Prop_lut5_I0_O) 0.124 3.409 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/O
|
|
net (fo=2, routed) 1.103 4.512 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2_n_0
|
|
SLICE_X38Y50 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/I0
|
|
SLICE_X38Y50 LUT6 (Prop_lut6_I0_O) 0.124 4.636 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/O
|
|
net (fo=89, routed) 1.162 5.797 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus[8]
|
|
SLICE_X42Y51 r u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_38__0/S
|
|
SLICE_X42Y51 MUXF7 (Prop_muxf7_S_O) 0.292 6.089 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_38__0/O
|
|
net (fo=1, routed) 0.000 6.089 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_38__0_n_0
|
|
SLICE_X42Y51 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_16__0/I1
|
|
SLICE_X42Y51 MUXF8 (Prop_muxf8_I1_O) 0.088 6.177 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_16__0/O
|
|
net (fo=1, routed) 0.957 7.134 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_16__0_n_0
|
|
SLICE_X42Y50 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7/I0
|
|
SLICE_X42Y50 LUT6 (Prop_lut6_I0_O) 0.319 7.453 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7/O
|
|
net (fo=1, routed) 0.435 7.888 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7_n_0
|
|
SLICE_X44Y50 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0/I5
|
|
SLICE_X44Y50 LUT6 (Prop_lut6_I5_O) 0.124 8.012 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0/O
|
|
net (fo=10, routed) 0.740 8.753 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0_n_0
|
|
SLICE_X44Y50 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[5]_i_1__0/I3
|
|
SLICE_X44Y50 LUT6 (Prop_lut6_I3_O) 0.124 8.877 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[5]_i_1__0/O
|
|
net (fo=6, routed) 0.845 9.722 u_cpu/u_csr/ms_to_ws_bus[13]
|
|
SLICE_X50Y46 f u_cpu/u_csr/write_buffer_way[1]_i_18/I3
|
|
SLICE_X50Y46 LUT6 (Prop_lut6_I3_O) 0.124 9.846 r u_cpu/u_csr/write_buffer_way[1]_i_18/O
|
|
net (fo=1, routed) 0.000 9.846 u_cpu/u_csr/write_buffer_way[1]_i_18_n_0
|
|
SLICE_X50Y46 r u_cpu/u_csr/write_buffer_way_reg[1]_i_11/S[0]
|
|
SLICE_X50Y46 CARRY4 (Prop_carry4_S[0]_CO[3])
|
|
0.532 10.378 r u_cpu/u_csr/write_buffer_way_reg[1]_i_11/CO[3]
|
|
net (fo=1, routed) 0.000 10.378 u_cpu/u_csr/write_buffer_way_reg[1]_i_11_n_0
|
|
SLICE_X50Y47 r u_cpu/u_csr/write_buffer_way_reg[1]_i_9/CI
|
|
SLICE_X50Y47 CARRY4 (Prop_carry4_CI_CO[1])
|
|
0.157 10.535 r u_cpu/u_csr/write_buffer_way_reg[1]_i_9/CO[1]
|
|
net (fo=2, routed) 0.791 11.326 u_cpu/wb_stage/CO[0]
|
|
SLICE_X46Y39 r u_cpu/wb_stage/write_buffer_way[1]_i_5/I1
|
|
SLICE_X46Y39 LUT6 (Prop_lut6_I1_O) 0.329 11.655 f u_cpu/wb_stage/write_buffer_way[1]_i_5/O
|
|
net (fo=7, routed) 0.762 12.417 u_cpu/addr_trans/tlb_entry/sc_cancel_req
|
|
SLICE_X46Y35 f u_cpu/addr_trans/tlb_entry/main_state[0]_i_3/I1
|
|
SLICE_X46Y35 LUT3 (Prop_lut3_I1_O) 0.124 12.541 f u_cpu/addr_trans/tlb_entry/main_state[0]_i_3/O
|
|
net (fo=3, routed) 0.719 13.260 u_cpu/dcache/main_state_reg[0]_2
|
|
SLICE_X43Y31 f u_cpu/dcache/ds_to_es_bus_r[235]_i_10/I3
|
|
SLICE_X43Y31 LUT6 (Prop_lut6_I3_O) 0.124 13.384 f u_cpu/dcache/ds_to_es_bus_r[235]_i_10/O
|
|
net (fo=3, routed) 0.415 13.799 u_cpu/mem_stage/data_data_ok
|
|
SLICE_X43Y30 f u_cpu/mem_stage/flush_inst_req_buffer[1]_i_15/I0
|
|
SLICE_X43Y30 LUT3 (Prop_lut3_I0_O) 0.124 13.923 f u_cpu/mem_stage/flush_inst_req_buffer[1]_i_15/O
|
|
net (fo=2, routed) 0.833 14.756 u_cpu/mem_stage/es_to_ms_bus_r_reg[70]_1
|
|
SLICE_X48Y30 f u_cpu/mem_stage/flush_inst_req_buffer[1]_i_14/I0
|
|
SLICE_X48Y30 LUT6 (Prop_lut6_I0_O) 0.124 14.880 f u_cpu/mem_stage/flush_inst_req_buffer[1]_i_14/O
|
|
net (fo=1, routed) 0.651 15.532 u_cpu/mem_stage/ms_ready_go
|
|
SLICE_X48Y25 f u_cpu/mem_stage/flush_inst_req_buffer[1]_i_13/I4
|
|
SLICE_X48Y25 LUT6 (Prop_lut6_I4_O) 0.124 15.656 f u_cpu/mem_stage/flush_inst_req_buffer[1]_i_13/O
|
|
net (fo=3, routed) 0.483 16.139 u_cpu/id_stage/flush_inst_req_buffer[31]_i_6
|
|
SLICE_X50Y25 f u_cpu/id_stage/flush_inst_req_buffer[1]_i_9/I1
|
|
SLICE_X50Y25 LUT6 (Prop_lut6_I1_O) 0.124 16.263 f u_cpu/id_stage/flush_inst_req_buffer[1]_i_9/O
|
|
net (fo=32, routed) 0.531 16.794 u_cpu/if_stage/nextpc5
|
|
SLICE_X51Y27 f u_cpu/if_stage/fetch_pc_r[6]_i_4/I2
|
|
SLICE_X51Y27 LUT6 (Prop_lut6_I2_O) 0.124 16.918 r u_cpu/if_stage/fetch_pc_r[6]_i_4/O
|
|
net (fo=1, routed) 3.059 19.977 u_cpu/if_stage/fetch_pc_r[6]_i_4_n_0
|
|
SLICE_X114Y28 r u_cpu/if_stage/fetch_pc_r[6]_i_2/I2
|
|
SLICE_X114Y28 LUT6 (Prop_lut6_I2_O) 0.124 20.101 r u_cpu/if_stage/fetch_pc_r[6]_i_2/O
|
|
net (fo=1, routed) 0.441 20.542 u_cpu/if_stage/fetch_pc_r[6]_i_2_n_0
|
|
SLICE_X114Y25 r u_cpu/if_stage/fetch_pc_r[6]_i_1/I2
|
|
SLICE_X114Y25 LUT6 (Prop_lut6_I2_O) 0.124 20.666 r u_cpu/if_stage/fetch_pc_r[6]_i_1/O
|
|
net (fo=6, routed) 3.249 23.915 u_cpu/icache/tagv_ram_way[1].u/mem_reg_reg_2[2]
|
|
SLICE_X49Y33 r u_cpu/icache/tagv_ram_way[1].u/mem_reg_reg_i_8/I4
|
|
SLICE_X49Y33 LUT5 (Prop_lut5_I4_O) 0.124 24.039 r u_cpu/icache/tagv_ram_way[1].u/mem_reg_reg_i_8/O
|
|
net (fo=16, routed) 1.412 25.451 u_cpu/icache/data_ram_way[1].data_ram_bank[2].u/ADDRBWRADDR[2]
|
|
RAMB18_X2Y5 RAMB18E1 r u_cpu/icache/data_ram_way[1].data_ram_bank[2].u/mem_reg_reg/ADDRARDADDR[7]
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock cpu_clk rise edge) 30.323 30.323 r
|
|
clock source latency -5.674 24.648
|
|
propagated clock network latency
|
|
3.777 28.425
|
|
clock pessimism -0.418 28.007
|
|
clock uncertainty -0.074 27.933
|
|
RAMB18_X2Y5 RAMB18E1 (Setup_ramb18e1_CLKARDCLK_ADDRARDADDR[7])
|
|
-0.566 27.367 u_cpu/icache/data_ram_way[1].data_ram_bank[2].u/mem_reg_reg
|
|
-------------------------------------------------------------------
|
|
required time 27.367
|
|
arrival time -25.451
|
|
-------------------------------------------------------------------
|
|
slack 1.916
|
|
|
|
Slack (MET) : 1.916ns (required time - arrival time)
|
|
Source: u_cpu/addr_trans/data_vaddr_buffer_reg[14]/C
|
|
(rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns})
|
|
Destination: u_cpu/icache/data_ram_way[1].data_ram_bank[2].u/mem_reg_reg/ADDRARDADDR[7]
|
|
(rising edge-triggered cell RAMB18E1 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns})
|
|
Path Group: cpu_clk
|
|
Path Type: Setup (Max at Slow Process Corner)
|
|
Requirement: 30.323ns (cpu_clk rise@30.323ns - cpu_clk rise@0.000ns)
|
|
Data Path Delay: 27.676ns (logic 5.333ns (19.269%) route 22.343ns (80.731%))
|
|
Logic Levels: 26 (CARRY4=4 LUT3=2 LUT4=1 LUT5=2 LUT6=15 MUXF7=1 MUXF8=1)
|
|
Clock Path Skew: -0.091ns (DCD - SCD + CPR)
|
|
Destination Clock Delay (DCD): -1.897ns = ( 28.425 - 30.323 )
|
|
Source Clock Delay (SCD): -2.225ns
|
|
Clock Pessimism Removal (CPR): -0.418ns
|
|
Clock Uncertainty: 0.074ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Discrete Jitter (DJ): 0.130ns
|
|
Phase Error (PE): 0.000ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock cpu_clk rise edge) 0.000 0.000 r
|
|
clock source latency -6.275 -6.275
|
|
propagated clock network latency
|
|
4.051 -2.225
|
|
SLICE_X35Y35 FDRE 0.000 -2.225 r u_cpu/addr_trans/data_vaddr_buffer_reg[14]/C
|
|
SLICE_X35Y35 FDRE (Prop_fdre_C_Q) 0.456 -1.769 r u_cpu/addr_trans/data_vaddr_buffer_reg[14]/Q
|
|
net (fo=33, routed) 1.442 -0.326 u_cpu/addr_trans/tlb_entry/data_vaddr_buffer[2]
|
|
SLICE_X42Y40 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_226/I5
|
|
SLICE_X42Y40 LUT6 (Prop_lut6_I5_O) 0.124 -0.202 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_226/O
|
|
net (fo=1, routed) 0.000 -0.202 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_226_n_0
|
|
SLICE_X42Y40 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_111/S[0]
|
|
SLICE_X42Y40 CARRY4 (Prop_carry4_S[0]_CO[3])
|
|
0.513 0.311 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_111/CO[3]
|
|
net (fo=1, routed) 0.000 0.311 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_111_n_0
|
|
SLICE_X42Y41 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_32/CI
|
|
SLICE_X42Y41 CARRY4 (Prop_carry4_CI_CO[2])
|
|
0.229 0.540 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_32/CO[2]
|
|
net (fo=1, routed) 1.009 1.549 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_32_n_1
|
|
SLICE_X40Y47 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_9/I1
|
|
SLICE_X40Y47 LUT6 (Prop_lut6_I1_O) 0.310 1.859 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_9/O
|
|
net (fo=2, routed) 0.635 2.494 u_cpu/addr_trans/tlb_entry/match1[28]
|
|
SLICE_X38Y47 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/I2
|
|
SLICE_X38Y47 LUT4 (Prop_lut4_I2_O) 0.124 2.618 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/O
|
|
net (fo=2, routed) 0.667 3.285 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2_n_0
|
|
SLICE_X39Y47 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/I0
|
|
SLICE_X39Y47 LUT5 (Prop_lut5_I0_O) 0.124 3.409 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/O
|
|
net (fo=2, routed) 1.103 4.512 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2_n_0
|
|
SLICE_X38Y50 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/I0
|
|
SLICE_X38Y50 LUT6 (Prop_lut6_I0_O) 0.124 4.636 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/O
|
|
net (fo=89, routed) 1.162 5.797 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus[8]
|
|
SLICE_X42Y51 r u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_38__0/S
|
|
SLICE_X42Y51 MUXF7 (Prop_muxf7_S_O) 0.292 6.089 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_38__0/O
|
|
net (fo=1, routed) 0.000 6.089 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_38__0_n_0
|
|
SLICE_X42Y51 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_16__0/I1
|
|
SLICE_X42Y51 MUXF8 (Prop_muxf8_I1_O) 0.088 6.177 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_16__0/O
|
|
net (fo=1, routed) 0.957 7.134 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_16__0_n_0
|
|
SLICE_X42Y50 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7/I0
|
|
SLICE_X42Y50 LUT6 (Prop_lut6_I0_O) 0.319 7.453 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7/O
|
|
net (fo=1, routed) 0.435 7.888 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7_n_0
|
|
SLICE_X44Y50 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0/I5
|
|
SLICE_X44Y50 LUT6 (Prop_lut6_I5_O) 0.124 8.012 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0/O
|
|
net (fo=10, routed) 0.740 8.753 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0_n_0
|
|
SLICE_X44Y50 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[5]_i_1__0/I3
|
|
SLICE_X44Y50 LUT6 (Prop_lut6_I3_O) 0.124 8.877 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[5]_i_1__0/O
|
|
net (fo=6, routed) 0.845 9.722 u_cpu/u_csr/ms_to_ws_bus[13]
|
|
SLICE_X50Y46 r u_cpu/u_csr/write_buffer_way[1]_i_18/I3
|
|
SLICE_X50Y46 LUT6 (Prop_lut6_I3_O) 0.124 9.846 f u_cpu/u_csr/write_buffer_way[1]_i_18/O
|
|
net (fo=1, routed) 0.000 9.846 u_cpu/u_csr/write_buffer_way[1]_i_18_n_0
|
|
SLICE_X50Y46 f u_cpu/u_csr/write_buffer_way_reg[1]_i_11/S[0]
|
|
SLICE_X50Y46 CARRY4 (Prop_carry4_S[0]_CO[3])
|
|
0.532 10.378 r u_cpu/u_csr/write_buffer_way_reg[1]_i_11/CO[3]
|
|
net (fo=1, routed) 0.000 10.378 u_cpu/u_csr/write_buffer_way_reg[1]_i_11_n_0
|
|
SLICE_X50Y47 r u_cpu/u_csr/write_buffer_way_reg[1]_i_9/CI
|
|
SLICE_X50Y47 CARRY4 (Prop_carry4_CI_CO[1])
|
|
0.157 10.535 r u_cpu/u_csr/write_buffer_way_reg[1]_i_9/CO[1]
|
|
net (fo=2, routed) 0.791 11.326 u_cpu/wb_stage/CO[0]
|
|
SLICE_X46Y39 r u_cpu/wb_stage/write_buffer_way[1]_i_5/I1
|
|
SLICE_X46Y39 LUT6 (Prop_lut6_I1_O) 0.329 11.655 f u_cpu/wb_stage/write_buffer_way[1]_i_5/O
|
|
net (fo=7, routed) 0.762 12.417 u_cpu/addr_trans/tlb_entry/sc_cancel_req
|
|
SLICE_X46Y35 f u_cpu/addr_trans/tlb_entry/main_state[0]_i_3/I1
|
|
SLICE_X46Y35 LUT3 (Prop_lut3_I1_O) 0.124 12.541 f u_cpu/addr_trans/tlb_entry/main_state[0]_i_3/O
|
|
net (fo=3, routed) 0.719 13.260 u_cpu/dcache/main_state_reg[0]_2
|
|
SLICE_X43Y31 f u_cpu/dcache/ds_to_es_bus_r[235]_i_10/I3
|
|
SLICE_X43Y31 LUT6 (Prop_lut6_I3_O) 0.124 13.384 f u_cpu/dcache/ds_to_es_bus_r[235]_i_10/O
|
|
net (fo=3, routed) 0.415 13.799 u_cpu/mem_stage/data_data_ok
|
|
SLICE_X43Y30 f u_cpu/mem_stage/flush_inst_req_buffer[1]_i_15/I0
|
|
SLICE_X43Y30 LUT3 (Prop_lut3_I0_O) 0.124 13.923 f u_cpu/mem_stage/flush_inst_req_buffer[1]_i_15/O
|
|
net (fo=2, routed) 0.833 14.756 u_cpu/mem_stage/es_to_ms_bus_r_reg[70]_1
|
|
SLICE_X48Y30 f u_cpu/mem_stage/flush_inst_req_buffer[1]_i_14/I0
|
|
SLICE_X48Y30 LUT6 (Prop_lut6_I0_O) 0.124 14.880 f u_cpu/mem_stage/flush_inst_req_buffer[1]_i_14/O
|
|
net (fo=1, routed) 0.651 15.532 u_cpu/mem_stage/ms_ready_go
|
|
SLICE_X48Y25 f u_cpu/mem_stage/flush_inst_req_buffer[1]_i_13/I4
|
|
SLICE_X48Y25 LUT6 (Prop_lut6_I4_O) 0.124 15.656 f u_cpu/mem_stage/flush_inst_req_buffer[1]_i_13/O
|
|
net (fo=3, routed) 0.483 16.139 u_cpu/id_stage/flush_inst_req_buffer[31]_i_6
|
|
SLICE_X50Y25 f u_cpu/id_stage/flush_inst_req_buffer[1]_i_9/I1
|
|
SLICE_X50Y25 LUT6 (Prop_lut6_I1_O) 0.124 16.263 f u_cpu/id_stage/flush_inst_req_buffer[1]_i_9/O
|
|
net (fo=32, routed) 0.531 16.794 u_cpu/if_stage/nextpc5
|
|
SLICE_X51Y27 f u_cpu/if_stage/fetch_pc_r[6]_i_4/I2
|
|
SLICE_X51Y27 LUT6 (Prop_lut6_I2_O) 0.124 16.918 r u_cpu/if_stage/fetch_pc_r[6]_i_4/O
|
|
net (fo=1, routed) 3.059 19.977 u_cpu/if_stage/fetch_pc_r[6]_i_4_n_0
|
|
SLICE_X114Y28 r u_cpu/if_stage/fetch_pc_r[6]_i_2/I2
|
|
SLICE_X114Y28 LUT6 (Prop_lut6_I2_O) 0.124 20.101 r u_cpu/if_stage/fetch_pc_r[6]_i_2/O
|
|
net (fo=1, routed) 0.441 20.542 u_cpu/if_stage/fetch_pc_r[6]_i_2_n_0
|
|
SLICE_X114Y25 r u_cpu/if_stage/fetch_pc_r[6]_i_1/I2
|
|
SLICE_X114Y25 LUT6 (Prop_lut6_I2_O) 0.124 20.666 r u_cpu/if_stage/fetch_pc_r[6]_i_1/O
|
|
net (fo=6, routed) 3.249 23.915 u_cpu/icache/tagv_ram_way[1].u/mem_reg_reg_2[2]
|
|
SLICE_X49Y33 r u_cpu/icache/tagv_ram_way[1].u/mem_reg_reg_i_8/I4
|
|
SLICE_X49Y33 LUT5 (Prop_lut5_I4_O) 0.124 24.039 r u_cpu/icache/tagv_ram_way[1].u/mem_reg_reg_i_8/O
|
|
net (fo=16, routed) 1.412 25.451 u_cpu/icache/data_ram_way[1].data_ram_bank[2].u/ADDRBWRADDR[2]
|
|
RAMB18_X2Y5 RAMB18E1 r u_cpu/icache/data_ram_way[1].data_ram_bank[2].u/mem_reg_reg/ADDRARDADDR[7]
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock cpu_clk rise edge) 30.323 30.323 r
|
|
clock source latency -5.674 24.648
|
|
propagated clock network latency
|
|
3.777 28.425
|
|
clock pessimism -0.418 28.007
|
|
clock uncertainty -0.074 27.933
|
|
RAMB18_X2Y5 RAMB18E1 (Setup_ramb18e1_CLKARDCLK_ADDRARDADDR[7])
|
|
-0.566 27.367 u_cpu/icache/data_ram_way[1].data_ram_bank[2].u/mem_reg_reg
|
|
-------------------------------------------------------------------
|
|
required time 27.367
|
|
arrival time -25.451
|
|
-------------------------------------------------------------------
|
|
slack 1.916
|
|
|
|
Slack (MET) : 1.916ns (required time - arrival time)
|
|
Source: u_cpu/addr_trans/data_vaddr_buffer_reg[14]/C
|
|
(rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns})
|
|
Destination: u_cpu/icache/data_ram_way[1].data_ram_bank[2].u/mem_reg_reg/ADDRARDADDR[7]
|
|
(rising edge-triggered cell RAMB18E1 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns})
|
|
Path Group: cpu_clk
|
|
Path Type: Setup (Max at Slow Process Corner)
|
|
Requirement: 30.323ns (cpu_clk rise@30.323ns - cpu_clk rise@0.000ns)
|
|
Data Path Delay: 27.676ns (logic 5.333ns (19.269%) route 22.343ns (80.731%))
|
|
Logic Levels: 26 (CARRY4=4 LUT3=2 LUT4=1 LUT5=2 LUT6=15 MUXF7=1 MUXF8=1)
|
|
Clock Path Skew: -0.091ns (DCD - SCD + CPR)
|
|
Destination Clock Delay (DCD): -1.897ns = ( 28.425 - 30.323 )
|
|
Source Clock Delay (SCD): -2.225ns
|
|
Clock Pessimism Removal (CPR): -0.418ns
|
|
Clock Uncertainty: 0.074ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Discrete Jitter (DJ): 0.130ns
|
|
Phase Error (PE): 0.000ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock cpu_clk rise edge) 0.000 0.000 r
|
|
clock source latency -6.275 -6.275
|
|
propagated clock network latency
|
|
4.051 -2.225
|
|
SLICE_X35Y35 FDRE 0.000 -2.225 r u_cpu/addr_trans/data_vaddr_buffer_reg[14]/C
|
|
SLICE_X35Y35 FDRE (Prop_fdre_C_Q) 0.456 -1.769 r u_cpu/addr_trans/data_vaddr_buffer_reg[14]/Q
|
|
net (fo=33, routed) 1.442 -0.326 u_cpu/addr_trans/tlb_entry/data_vaddr_buffer[2]
|
|
SLICE_X42Y40 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_226/I5
|
|
SLICE_X42Y40 LUT6 (Prop_lut6_I5_O) 0.124 -0.202 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_226/O
|
|
net (fo=1, routed) 0.000 -0.202 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_226_n_0
|
|
SLICE_X42Y40 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_111/S[0]
|
|
SLICE_X42Y40 CARRY4 (Prop_carry4_S[0]_CO[3])
|
|
0.513 0.311 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_111/CO[3]
|
|
net (fo=1, routed) 0.000 0.311 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_111_n_0
|
|
SLICE_X42Y41 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_32/CI
|
|
SLICE_X42Y41 CARRY4 (Prop_carry4_CI_CO[2])
|
|
0.229 0.540 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_32/CO[2]
|
|
net (fo=1, routed) 1.009 1.549 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_32_n_1
|
|
SLICE_X40Y47 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_9/I1
|
|
SLICE_X40Y47 LUT6 (Prop_lut6_I1_O) 0.310 1.859 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_9/O
|
|
net (fo=2, routed) 0.635 2.494 u_cpu/addr_trans/tlb_entry/match1[28]
|
|
SLICE_X38Y47 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/I2
|
|
SLICE_X38Y47 LUT4 (Prop_lut4_I2_O) 0.124 2.618 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/O
|
|
net (fo=2, routed) 0.667 3.285 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2_n_0
|
|
SLICE_X39Y47 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/I0
|
|
SLICE_X39Y47 LUT5 (Prop_lut5_I0_O) 0.124 3.409 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/O
|
|
net (fo=2, routed) 1.103 4.512 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2_n_0
|
|
SLICE_X38Y50 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/I0
|
|
SLICE_X38Y50 LUT6 (Prop_lut6_I0_O) 0.124 4.636 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/O
|
|
net (fo=89, routed) 1.162 5.797 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus[8]
|
|
SLICE_X42Y51 r u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_38__0/S
|
|
SLICE_X42Y51 MUXF7 (Prop_muxf7_S_O) 0.292 6.089 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_38__0/O
|
|
net (fo=1, routed) 0.000 6.089 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_38__0_n_0
|
|
SLICE_X42Y51 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_16__0/I1
|
|
SLICE_X42Y51 MUXF8 (Prop_muxf8_I1_O) 0.088 6.177 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_16__0/O
|
|
net (fo=1, routed) 0.957 7.134 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_16__0_n_0
|
|
SLICE_X42Y50 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7/I0
|
|
SLICE_X42Y50 LUT6 (Prop_lut6_I0_O) 0.319 7.453 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7/O
|
|
net (fo=1, routed) 0.435 7.888 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7_n_0
|
|
SLICE_X44Y50 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0/I5
|
|
SLICE_X44Y50 LUT6 (Prop_lut6_I5_O) 0.124 8.012 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0/O
|
|
net (fo=10, routed) 0.740 8.753 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0_n_0
|
|
SLICE_X44Y50 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[5]_i_1__0/I3
|
|
SLICE_X44Y50 LUT6 (Prop_lut6_I3_O) 0.124 8.877 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[5]_i_1__0/O
|
|
net (fo=6, routed) 0.845 9.722 u_cpu/u_csr/ms_to_ws_bus[13]
|
|
SLICE_X50Y46 f u_cpu/u_csr/write_buffer_way[1]_i_18/I3
|
|
SLICE_X50Y46 LUT6 (Prop_lut6_I3_O) 0.124 9.846 f u_cpu/u_csr/write_buffer_way[1]_i_18/O
|
|
net (fo=1, routed) 0.000 9.846 u_cpu/u_csr/write_buffer_way[1]_i_18_n_0
|
|
SLICE_X50Y46 f u_cpu/u_csr/write_buffer_way_reg[1]_i_11/S[0]
|
|
SLICE_X50Y46 CARRY4 (Prop_carry4_S[0]_CO[3])
|
|
0.532 10.378 r u_cpu/u_csr/write_buffer_way_reg[1]_i_11/CO[3]
|
|
net (fo=1, routed) 0.000 10.378 u_cpu/u_csr/write_buffer_way_reg[1]_i_11_n_0
|
|
SLICE_X50Y47 r u_cpu/u_csr/write_buffer_way_reg[1]_i_9/CI
|
|
SLICE_X50Y47 CARRY4 (Prop_carry4_CI_CO[1])
|
|
0.157 10.535 r u_cpu/u_csr/write_buffer_way_reg[1]_i_9/CO[1]
|
|
net (fo=2, routed) 0.791 11.326 u_cpu/wb_stage/CO[0]
|
|
SLICE_X46Y39 r u_cpu/wb_stage/write_buffer_way[1]_i_5/I1
|
|
SLICE_X46Y39 LUT6 (Prop_lut6_I1_O) 0.329 11.655 f u_cpu/wb_stage/write_buffer_way[1]_i_5/O
|
|
net (fo=7, routed) 0.762 12.417 u_cpu/addr_trans/tlb_entry/sc_cancel_req
|
|
SLICE_X46Y35 f u_cpu/addr_trans/tlb_entry/main_state[0]_i_3/I1
|
|
SLICE_X46Y35 LUT3 (Prop_lut3_I1_O) 0.124 12.541 f u_cpu/addr_trans/tlb_entry/main_state[0]_i_3/O
|
|
net (fo=3, routed) 0.719 13.260 u_cpu/dcache/main_state_reg[0]_2
|
|
SLICE_X43Y31 f u_cpu/dcache/ds_to_es_bus_r[235]_i_10/I3
|
|
SLICE_X43Y31 LUT6 (Prop_lut6_I3_O) 0.124 13.384 f u_cpu/dcache/ds_to_es_bus_r[235]_i_10/O
|
|
net (fo=3, routed) 0.415 13.799 u_cpu/mem_stage/data_data_ok
|
|
SLICE_X43Y30 f u_cpu/mem_stage/flush_inst_req_buffer[1]_i_15/I0
|
|
SLICE_X43Y30 LUT3 (Prop_lut3_I0_O) 0.124 13.923 f u_cpu/mem_stage/flush_inst_req_buffer[1]_i_15/O
|
|
net (fo=2, routed) 0.833 14.756 u_cpu/mem_stage/es_to_ms_bus_r_reg[70]_1
|
|
SLICE_X48Y30 f u_cpu/mem_stage/flush_inst_req_buffer[1]_i_14/I0
|
|
SLICE_X48Y30 LUT6 (Prop_lut6_I0_O) 0.124 14.880 f u_cpu/mem_stage/flush_inst_req_buffer[1]_i_14/O
|
|
net (fo=1, routed) 0.651 15.532 u_cpu/mem_stage/ms_ready_go
|
|
SLICE_X48Y25 f u_cpu/mem_stage/flush_inst_req_buffer[1]_i_13/I4
|
|
SLICE_X48Y25 LUT6 (Prop_lut6_I4_O) 0.124 15.656 f u_cpu/mem_stage/flush_inst_req_buffer[1]_i_13/O
|
|
net (fo=3, routed) 0.483 16.139 u_cpu/id_stage/flush_inst_req_buffer[31]_i_6
|
|
SLICE_X50Y25 f u_cpu/id_stage/flush_inst_req_buffer[1]_i_9/I1
|
|
SLICE_X50Y25 LUT6 (Prop_lut6_I1_O) 0.124 16.263 f u_cpu/id_stage/flush_inst_req_buffer[1]_i_9/O
|
|
net (fo=32, routed) 0.531 16.794 u_cpu/if_stage/nextpc5
|
|
SLICE_X51Y27 f u_cpu/if_stage/fetch_pc_r[6]_i_4/I2
|
|
SLICE_X51Y27 LUT6 (Prop_lut6_I2_O) 0.124 16.918 r u_cpu/if_stage/fetch_pc_r[6]_i_4/O
|
|
net (fo=1, routed) 3.059 19.977 u_cpu/if_stage/fetch_pc_r[6]_i_4_n_0
|
|
SLICE_X114Y28 r u_cpu/if_stage/fetch_pc_r[6]_i_2/I2
|
|
SLICE_X114Y28 LUT6 (Prop_lut6_I2_O) 0.124 20.101 r u_cpu/if_stage/fetch_pc_r[6]_i_2/O
|
|
net (fo=1, routed) 0.441 20.542 u_cpu/if_stage/fetch_pc_r[6]_i_2_n_0
|
|
SLICE_X114Y25 r u_cpu/if_stage/fetch_pc_r[6]_i_1/I2
|
|
SLICE_X114Y25 LUT6 (Prop_lut6_I2_O) 0.124 20.666 r u_cpu/if_stage/fetch_pc_r[6]_i_1/O
|
|
net (fo=6, routed) 3.249 23.915 u_cpu/icache/tagv_ram_way[1].u/mem_reg_reg_2[2]
|
|
SLICE_X49Y33 r u_cpu/icache/tagv_ram_way[1].u/mem_reg_reg_i_8/I4
|
|
SLICE_X49Y33 LUT5 (Prop_lut5_I4_O) 0.124 24.039 r u_cpu/icache/tagv_ram_way[1].u/mem_reg_reg_i_8/O
|
|
net (fo=16, routed) 1.412 25.451 u_cpu/icache/data_ram_way[1].data_ram_bank[2].u/ADDRBWRADDR[2]
|
|
RAMB18_X2Y5 RAMB18E1 r u_cpu/icache/data_ram_way[1].data_ram_bank[2].u/mem_reg_reg/ADDRARDADDR[7]
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock cpu_clk rise edge) 30.323 30.323 r
|
|
clock source latency -5.674 24.648
|
|
propagated clock network latency
|
|
3.777 28.425
|
|
clock pessimism -0.418 28.007
|
|
clock uncertainty -0.074 27.933
|
|
RAMB18_X2Y5 RAMB18E1 (Setup_ramb18e1_CLKARDCLK_ADDRARDADDR[7])
|
|
-0.566 27.367 u_cpu/icache/data_ram_way[1].data_ram_bank[2].u/mem_reg_reg
|
|
-------------------------------------------------------------------
|
|
required time 27.367
|
|
arrival time -25.451
|
|
-------------------------------------------------------------------
|
|
slack 1.916
|
|
|
|
Slack (MET) : 1.920ns (required time - arrival time)
|
|
Source: u_cpu/addr_trans/data_vaddr_buffer_reg[14]/C
|
|
(rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns})
|
|
Destination: u_cpu/icache/data_ram_way[0].data_ram_bank[0].u/mem_reg_reg/ADDRBWRADDR[7]
|
|
(rising edge-triggered cell RAMB18E1 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns})
|
|
Path Group: cpu_clk
|
|
Path Type: Setup (Max at Slow Process Corner)
|
|
Requirement: 30.323ns (cpu_clk rise@30.323ns - cpu_clk rise@0.000ns)
|
|
Data Path Delay: 27.674ns (logic 5.333ns (19.271%) route 22.341ns (80.729%))
|
|
Logic Levels: 26 (CARRY4=4 LUT3=2 LUT4=1 LUT5=2 LUT6=15 MUXF7=1 MUXF8=1)
|
|
Clock Path Skew: -0.089ns (DCD - SCD + CPR)
|
|
Destination Clock Delay (DCD): -1.895ns = ( 28.427 - 30.323 )
|
|
Source Clock Delay (SCD): -2.225ns
|
|
Clock Pessimism Removal (CPR): -0.418ns
|
|
Clock Uncertainty: 0.074ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Discrete Jitter (DJ): 0.130ns
|
|
Phase Error (PE): 0.000ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock cpu_clk rise edge) 0.000 0.000 r
|
|
clock source latency -6.275 -6.275
|
|
propagated clock network latency
|
|
4.051 -2.225
|
|
SLICE_X35Y35 FDRE 0.000 -2.225 r u_cpu/addr_trans/data_vaddr_buffer_reg[14]/C
|
|
SLICE_X35Y35 FDRE (Prop_fdre_C_Q) 0.456 -1.769 r u_cpu/addr_trans/data_vaddr_buffer_reg[14]/Q
|
|
net (fo=33, routed) 1.442 -0.326 u_cpu/addr_trans/tlb_entry/data_vaddr_buffer[2]
|
|
SLICE_X42Y40 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_226/I5
|
|
SLICE_X42Y40 LUT6 (Prop_lut6_I5_O) 0.124 -0.202 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_226/O
|
|
net (fo=1, routed) 0.000 -0.202 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_226_n_0
|
|
SLICE_X42Y40 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_111/S[0]
|
|
SLICE_X42Y40 CARRY4 (Prop_carry4_S[0]_CO[3])
|
|
0.513 0.311 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_111/CO[3]
|
|
net (fo=1, routed) 0.000 0.311 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_111_n_0
|
|
SLICE_X42Y41 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_32/CI
|
|
SLICE_X42Y41 CARRY4 (Prop_carry4_CI_CO[2])
|
|
0.229 0.540 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_32/CO[2]
|
|
net (fo=1, routed) 1.009 1.549 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_32_n_1
|
|
SLICE_X40Y47 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_9/I1
|
|
SLICE_X40Y47 LUT6 (Prop_lut6_I1_O) 0.310 1.859 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_9/O
|
|
net (fo=2, routed) 0.635 2.494 u_cpu/addr_trans/tlb_entry/match1[28]
|
|
SLICE_X38Y47 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/I2
|
|
SLICE_X38Y47 LUT4 (Prop_lut4_I2_O) 0.124 2.618 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/O
|
|
net (fo=2, routed) 0.667 3.285 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2_n_0
|
|
SLICE_X39Y47 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/I0
|
|
SLICE_X39Y47 LUT5 (Prop_lut5_I0_O) 0.124 3.409 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/O
|
|
net (fo=2, routed) 1.103 4.512 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2_n_0
|
|
SLICE_X38Y50 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/I0
|
|
SLICE_X38Y50 LUT6 (Prop_lut6_I0_O) 0.124 4.636 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/O
|
|
net (fo=89, routed) 1.162 5.797 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus[8]
|
|
SLICE_X42Y51 r u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_38__0/S
|
|
SLICE_X42Y51 MUXF7 (Prop_muxf7_S_O) 0.292 6.089 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_38__0/O
|
|
net (fo=1, routed) 0.000 6.089 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_38__0_n_0
|
|
SLICE_X42Y51 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_16__0/I1
|
|
SLICE_X42Y51 MUXF8 (Prop_muxf8_I1_O) 0.088 6.177 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_16__0/O
|
|
net (fo=1, routed) 0.957 7.134 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_16__0_n_0
|
|
SLICE_X42Y50 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7/I0
|
|
SLICE_X42Y50 LUT6 (Prop_lut6_I0_O) 0.319 7.453 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7/O
|
|
net (fo=1, routed) 0.435 7.888 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7_n_0
|
|
SLICE_X44Y50 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0/I5
|
|
SLICE_X44Y50 LUT6 (Prop_lut6_I5_O) 0.124 8.012 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0/O
|
|
net (fo=10, routed) 0.740 8.753 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0_n_0
|
|
SLICE_X44Y50 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[5]_i_1__0/I3
|
|
SLICE_X44Y50 LUT6 (Prop_lut6_I3_O) 0.124 8.877 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[5]_i_1__0/O
|
|
net (fo=6, routed) 0.845 9.722 u_cpu/u_csr/ms_to_ws_bus[13]
|
|
SLICE_X50Y46 r u_cpu/u_csr/write_buffer_way[1]_i_18/I3
|
|
SLICE_X50Y46 LUT6 (Prop_lut6_I3_O) 0.124 9.846 r u_cpu/u_csr/write_buffer_way[1]_i_18/O
|
|
net (fo=1, routed) 0.000 9.846 u_cpu/u_csr/write_buffer_way[1]_i_18_n_0
|
|
SLICE_X50Y46 r u_cpu/u_csr/write_buffer_way_reg[1]_i_11/S[0]
|
|
SLICE_X50Y46 CARRY4 (Prop_carry4_S[0]_CO[3])
|
|
0.532 10.378 r u_cpu/u_csr/write_buffer_way_reg[1]_i_11/CO[3]
|
|
net (fo=1, routed) 0.000 10.378 u_cpu/u_csr/write_buffer_way_reg[1]_i_11_n_0
|
|
SLICE_X50Y47 r u_cpu/u_csr/write_buffer_way_reg[1]_i_9/CI
|
|
SLICE_X50Y47 CARRY4 (Prop_carry4_CI_CO[1])
|
|
0.157 10.535 f u_cpu/u_csr/write_buffer_way_reg[1]_i_9/CO[1]
|
|
net (fo=2, routed) 0.791 11.326 u_cpu/wb_stage/CO[0]
|
|
SLICE_X46Y39 f u_cpu/wb_stage/write_buffer_way[1]_i_5/I1
|
|
SLICE_X46Y39 LUT6 (Prop_lut6_I1_O) 0.329 11.655 r u_cpu/wb_stage/write_buffer_way[1]_i_5/O
|
|
net (fo=7, routed) 0.762 12.417 u_cpu/addr_trans/tlb_entry/sc_cancel_req
|
|
SLICE_X46Y35 r u_cpu/addr_trans/tlb_entry/main_state[0]_i_3/I1
|
|
SLICE_X46Y35 LUT3 (Prop_lut3_I1_O) 0.124 12.541 r u_cpu/addr_trans/tlb_entry/main_state[0]_i_3/O
|
|
net (fo=3, routed) 0.719 13.260 u_cpu/dcache/main_state_reg[0]_2
|
|
SLICE_X43Y31 r u_cpu/dcache/ds_to_es_bus_r[235]_i_10/I3
|
|
SLICE_X43Y31 LUT6 (Prop_lut6_I3_O) 0.124 13.384 r u_cpu/dcache/ds_to_es_bus_r[235]_i_10/O
|
|
net (fo=3, routed) 0.415 13.799 u_cpu/mem_stage/data_data_ok
|
|
SLICE_X43Y30 r u_cpu/mem_stage/flush_inst_req_buffer[1]_i_15/I0
|
|
SLICE_X43Y30 LUT3 (Prop_lut3_I0_O) 0.124 13.923 r u_cpu/mem_stage/flush_inst_req_buffer[1]_i_15/O
|
|
net (fo=2, routed) 0.833 14.756 u_cpu/mem_stage/es_to_ms_bus_r_reg[70]_1
|
|
SLICE_X48Y30 r u_cpu/mem_stage/flush_inst_req_buffer[1]_i_14/I0
|
|
SLICE_X48Y30 LUT6 (Prop_lut6_I0_O) 0.124 14.880 r u_cpu/mem_stage/flush_inst_req_buffer[1]_i_14/O
|
|
net (fo=1, routed) 0.651 15.532 u_cpu/mem_stage/ms_ready_go
|
|
SLICE_X48Y25 r u_cpu/mem_stage/flush_inst_req_buffer[1]_i_13/I4
|
|
SLICE_X48Y25 LUT6 (Prop_lut6_I4_O) 0.124 15.656 r u_cpu/mem_stage/flush_inst_req_buffer[1]_i_13/O
|
|
net (fo=3, routed) 0.483 16.139 u_cpu/id_stage/flush_inst_req_buffer[31]_i_6
|
|
SLICE_X50Y25 r u_cpu/id_stage/flush_inst_req_buffer[1]_i_9/I1
|
|
SLICE_X50Y25 LUT6 (Prop_lut6_I1_O) 0.124 16.263 r u_cpu/id_stage/flush_inst_req_buffer[1]_i_9/O
|
|
net (fo=32, routed) 0.531 16.794 u_cpu/if_stage/nextpc5
|
|
SLICE_X51Y27 r u_cpu/if_stage/fetch_pc_r[6]_i_4/I2
|
|
SLICE_X51Y27 LUT6 (Prop_lut6_I2_O) 0.124 16.918 r u_cpu/if_stage/fetch_pc_r[6]_i_4/O
|
|
net (fo=1, routed) 3.059 19.977 u_cpu/if_stage/fetch_pc_r[6]_i_4_n_0
|
|
SLICE_X114Y28 r u_cpu/if_stage/fetch_pc_r[6]_i_2/I2
|
|
SLICE_X114Y28 LUT6 (Prop_lut6_I2_O) 0.124 20.101 r u_cpu/if_stage/fetch_pc_r[6]_i_2/O
|
|
net (fo=1, routed) 0.441 20.542 u_cpu/if_stage/fetch_pc_r[6]_i_2_n_0
|
|
SLICE_X114Y25 r u_cpu/if_stage/fetch_pc_r[6]_i_1/I2
|
|
SLICE_X114Y25 LUT6 (Prop_lut6_I2_O) 0.124 20.666 r u_cpu/if_stage/fetch_pc_r[6]_i_1/O
|
|
net (fo=6, routed) 3.249 23.915 u_cpu/icache/tagv_ram_way[1].u/mem_reg_reg_2[2]
|
|
SLICE_X49Y33 r u_cpu/icache/tagv_ram_way[1].u/mem_reg_reg_i_8/I4
|
|
SLICE_X49Y33 LUT5 (Prop_lut5_I4_O) 0.124 24.039 r u_cpu/icache/tagv_ram_way[1].u/mem_reg_reg_i_8/O
|
|
net (fo=16, routed) 1.410 25.450 u_cpu/icache/data_ram_way[0].data_ram_bank[0].u/ADDRBWRADDR[2]
|
|
RAMB18_X2Y4 RAMB18E1 r u_cpu/icache/data_ram_way[0].data_ram_bank[0].u/mem_reg_reg/ADDRBWRADDR[7]
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock cpu_clk rise edge) 30.323 30.323 r
|
|
clock source latency -5.674 24.648
|
|
propagated clock network latency
|
|
3.779 28.427
|
|
clock pessimism -0.418 28.009
|
|
clock uncertainty -0.074 27.935
|
|
RAMB18_X2Y4 RAMB18E1 (Setup_ramb18e1_CLKBWRCLK_ADDRBWRADDR[7])
|
|
-0.566 27.369 u_cpu/icache/data_ram_way[0].data_ram_bank[0].u/mem_reg_reg
|
|
-------------------------------------------------------------------
|
|
required time 27.369
|
|
arrival time -25.450
|
|
-------------------------------------------------------------------
|
|
slack 1.920
|
|
|
|
Slack (MET) : 1.920ns (required time - arrival time)
|
|
Source: u_cpu/addr_trans/data_vaddr_buffer_reg[14]/C
|
|
(rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns})
|
|
Destination: u_cpu/icache/data_ram_way[0].data_ram_bank[0].u/mem_reg_reg/ADDRBWRADDR[7]
|
|
(rising edge-triggered cell RAMB18E1 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns})
|
|
Path Group: cpu_clk
|
|
Path Type: Setup (Max at Slow Process Corner)
|
|
Requirement: 30.323ns (cpu_clk rise@30.323ns - cpu_clk rise@0.000ns)
|
|
Data Path Delay: 27.674ns (logic 5.333ns (19.271%) route 22.341ns (80.729%))
|
|
Logic Levels: 26 (CARRY4=4 LUT3=2 LUT4=1 LUT5=2 LUT6=15 MUXF7=1 MUXF8=1)
|
|
Clock Path Skew: -0.089ns (DCD - SCD + CPR)
|
|
Destination Clock Delay (DCD): -1.895ns = ( 28.427 - 30.323 )
|
|
Source Clock Delay (SCD): -2.225ns
|
|
Clock Pessimism Removal (CPR): -0.418ns
|
|
Clock Uncertainty: 0.074ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Discrete Jitter (DJ): 0.130ns
|
|
Phase Error (PE): 0.000ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock cpu_clk rise edge) 0.000 0.000 r
|
|
clock source latency -6.275 -6.275
|
|
propagated clock network latency
|
|
4.051 -2.225
|
|
SLICE_X35Y35 FDRE 0.000 -2.225 r u_cpu/addr_trans/data_vaddr_buffer_reg[14]/C
|
|
SLICE_X35Y35 FDRE (Prop_fdre_C_Q) 0.456 -1.769 r u_cpu/addr_trans/data_vaddr_buffer_reg[14]/Q
|
|
net (fo=33, routed) 1.442 -0.326 u_cpu/addr_trans/tlb_entry/data_vaddr_buffer[2]
|
|
SLICE_X42Y40 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_226/I5
|
|
SLICE_X42Y40 LUT6 (Prop_lut6_I5_O) 0.124 -0.202 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_226/O
|
|
net (fo=1, routed) 0.000 -0.202 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_226_n_0
|
|
SLICE_X42Y40 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_111/S[0]
|
|
SLICE_X42Y40 CARRY4 (Prop_carry4_S[0]_CO[3])
|
|
0.513 0.311 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_111/CO[3]
|
|
net (fo=1, routed) 0.000 0.311 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_111_n_0
|
|
SLICE_X42Y41 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_32/CI
|
|
SLICE_X42Y41 CARRY4 (Prop_carry4_CI_CO[2])
|
|
0.229 0.540 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_32/CO[2]
|
|
net (fo=1, routed) 1.009 1.549 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_32_n_1
|
|
SLICE_X40Y47 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_9/I1
|
|
SLICE_X40Y47 LUT6 (Prop_lut6_I1_O) 0.310 1.859 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_9/O
|
|
net (fo=2, routed) 0.635 2.494 u_cpu/addr_trans/tlb_entry/match1[28]
|
|
SLICE_X38Y47 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/I2
|
|
SLICE_X38Y47 LUT4 (Prop_lut4_I2_O) 0.124 2.618 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/O
|
|
net (fo=2, routed) 0.667 3.285 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2_n_0
|
|
SLICE_X39Y47 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/I0
|
|
SLICE_X39Y47 LUT5 (Prop_lut5_I0_O) 0.124 3.409 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/O
|
|
net (fo=2, routed) 1.103 4.512 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2_n_0
|
|
SLICE_X38Y50 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/I0
|
|
SLICE_X38Y50 LUT6 (Prop_lut6_I0_O) 0.124 4.636 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/O
|
|
net (fo=89, routed) 1.162 5.797 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus[8]
|
|
SLICE_X42Y51 r u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_38__0/S
|
|
SLICE_X42Y51 MUXF7 (Prop_muxf7_S_O) 0.292 6.089 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_38__0/O
|
|
net (fo=1, routed) 0.000 6.089 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_38__0_n_0
|
|
SLICE_X42Y51 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_16__0/I1
|
|
SLICE_X42Y51 MUXF8 (Prop_muxf8_I1_O) 0.088 6.177 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_16__0/O
|
|
net (fo=1, routed) 0.957 7.134 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_16__0_n_0
|
|
SLICE_X42Y50 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7/I0
|
|
SLICE_X42Y50 LUT6 (Prop_lut6_I0_O) 0.319 7.453 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7/O
|
|
net (fo=1, routed) 0.435 7.888 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7_n_0
|
|
SLICE_X44Y50 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0/I5
|
|
SLICE_X44Y50 LUT6 (Prop_lut6_I5_O) 0.124 8.012 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0/O
|
|
net (fo=10, routed) 0.740 8.753 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0_n_0
|
|
SLICE_X44Y50 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[5]_i_1__0/I3
|
|
SLICE_X44Y50 LUT6 (Prop_lut6_I3_O) 0.124 8.877 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[5]_i_1__0/O
|
|
net (fo=6, routed) 0.845 9.722 u_cpu/u_csr/ms_to_ws_bus[13]
|
|
SLICE_X50Y46 f u_cpu/u_csr/write_buffer_way[1]_i_18/I3
|
|
SLICE_X50Y46 LUT6 (Prop_lut6_I3_O) 0.124 9.846 r u_cpu/u_csr/write_buffer_way[1]_i_18/O
|
|
net (fo=1, routed) 0.000 9.846 u_cpu/u_csr/write_buffer_way[1]_i_18_n_0
|
|
SLICE_X50Y46 r u_cpu/u_csr/write_buffer_way_reg[1]_i_11/S[0]
|
|
SLICE_X50Y46 CARRY4 (Prop_carry4_S[0]_CO[3])
|
|
0.532 10.378 r u_cpu/u_csr/write_buffer_way_reg[1]_i_11/CO[3]
|
|
net (fo=1, routed) 0.000 10.378 u_cpu/u_csr/write_buffer_way_reg[1]_i_11_n_0
|
|
SLICE_X50Y47 r u_cpu/u_csr/write_buffer_way_reg[1]_i_9/CI
|
|
SLICE_X50Y47 CARRY4 (Prop_carry4_CI_CO[1])
|
|
0.157 10.535 f u_cpu/u_csr/write_buffer_way_reg[1]_i_9/CO[1]
|
|
net (fo=2, routed) 0.791 11.326 u_cpu/wb_stage/CO[0]
|
|
SLICE_X46Y39 f u_cpu/wb_stage/write_buffer_way[1]_i_5/I1
|
|
SLICE_X46Y39 LUT6 (Prop_lut6_I1_O) 0.329 11.655 r u_cpu/wb_stage/write_buffer_way[1]_i_5/O
|
|
net (fo=7, routed) 0.762 12.417 u_cpu/addr_trans/tlb_entry/sc_cancel_req
|
|
SLICE_X46Y35 r u_cpu/addr_trans/tlb_entry/main_state[0]_i_3/I1
|
|
SLICE_X46Y35 LUT3 (Prop_lut3_I1_O) 0.124 12.541 r u_cpu/addr_trans/tlb_entry/main_state[0]_i_3/O
|
|
net (fo=3, routed) 0.719 13.260 u_cpu/dcache/main_state_reg[0]_2
|
|
SLICE_X43Y31 r u_cpu/dcache/ds_to_es_bus_r[235]_i_10/I3
|
|
SLICE_X43Y31 LUT6 (Prop_lut6_I3_O) 0.124 13.384 r u_cpu/dcache/ds_to_es_bus_r[235]_i_10/O
|
|
net (fo=3, routed) 0.415 13.799 u_cpu/mem_stage/data_data_ok
|
|
SLICE_X43Y30 r u_cpu/mem_stage/flush_inst_req_buffer[1]_i_15/I0
|
|
SLICE_X43Y30 LUT3 (Prop_lut3_I0_O) 0.124 13.923 r u_cpu/mem_stage/flush_inst_req_buffer[1]_i_15/O
|
|
net (fo=2, routed) 0.833 14.756 u_cpu/mem_stage/es_to_ms_bus_r_reg[70]_1
|
|
SLICE_X48Y30 r u_cpu/mem_stage/flush_inst_req_buffer[1]_i_14/I0
|
|
SLICE_X48Y30 LUT6 (Prop_lut6_I0_O) 0.124 14.880 r u_cpu/mem_stage/flush_inst_req_buffer[1]_i_14/O
|
|
net (fo=1, routed) 0.651 15.532 u_cpu/mem_stage/ms_ready_go
|
|
SLICE_X48Y25 r u_cpu/mem_stage/flush_inst_req_buffer[1]_i_13/I4
|
|
SLICE_X48Y25 LUT6 (Prop_lut6_I4_O) 0.124 15.656 r u_cpu/mem_stage/flush_inst_req_buffer[1]_i_13/O
|
|
net (fo=3, routed) 0.483 16.139 u_cpu/id_stage/flush_inst_req_buffer[31]_i_6
|
|
SLICE_X50Y25 r u_cpu/id_stage/flush_inst_req_buffer[1]_i_9/I1
|
|
SLICE_X50Y25 LUT6 (Prop_lut6_I1_O) 0.124 16.263 r u_cpu/id_stage/flush_inst_req_buffer[1]_i_9/O
|
|
net (fo=32, routed) 0.531 16.794 u_cpu/if_stage/nextpc5
|
|
SLICE_X51Y27 r u_cpu/if_stage/fetch_pc_r[6]_i_4/I2
|
|
SLICE_X51Y27 LUT6 (Prop_lut6_I2_O) 0.124 16.918 r u_cpu/if_stage/fetch_pc_r[6]_i_4/O
|
|
net (fo=1, routed) 3.059 19.977 u_cpu/if_stage/fetch_pc_r[6]_i_4_n_0
|
|
SLICE_X114Y28 r u_cpu/if_stage/fetch_pc_r[6]_i_2/I2
|
|
SLICE_X114Y28 LUT6 (Prop_lut6_I2_O) 0.124 20.101 r u_cpu/if_stage/fetch_pc_r[6]_i_2/O
|
|
net (fo=1, routed) 0.441 20.542 u_cpu/if_stage/fetch_pc_r[6]_i_2_n_0
|
|
SLICE_X114Y25 r u_cpu/if_stage/fetch_pc_r[6]_i_1/I2
|
|
SLICE_X114Y25 LUT6 (Prop_lut6_I2_O) 0.124 20.666 r u_cpu/if_stage/fetch_pc_r[6]_i_1/O
|
|
net (fo=6, routed) 3.249 23.915 u_cpu/icache/tagv_ram_way[1].u/mem_reg_reg_2[2]
|
|
SLICE_X49Y33 r u_cpu/icache/tagv_ram_way[1].u/mem_reg_reg_i_8/I4
|
|
SLICE_X49Y33 LUT5 (Prop_lut5_I4_O) 0.124 24.039 r u_cpu/icache/tagv_ram_way[1].u/mem_reg_reg_i_8/O
|
|
net (fo=16, routed) 1.410 25.450 u_cpu/icache/data_ram_way[0].data_ram_bank[0].u/ADDRBWRADDR[2]
|
|
RAMB18_X2Y4 RAMB18E1 r u_cpu/icache/data_ram_way[0].data_ram_bank[0].u/mem_reg_reg/ADDRBWRADDR[7]
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock cpu_clk rise edge) 30.323 30.323 r
|
|
clock source latency -5.674 24.648
|
|
propagated clock network latency
|
|
3.779 28.427
|
|
clock pessimism -0.418 28.009
|
|
clock uncertainty -0.074 27.935
|
|
RAMB18_X2Y4 RAMB18E1 (Setup_ramb18e1_CLKBWRCLK_ADDRBWRADDR[7])
|
|
-0.566 27.369 u_cpu/icache/data_ram_way[0].data_ram_bank[0].u/mem_reg_reg
|
|
-------------------------------------------------------------------
|
|
required time 27.369
|
|
arrival time -25.450
|
|
-------------------------------------------------------------------
|
|
slack 1.920
|
|
|
|
Slack (MET) : 1.920ns (required time - arrival time)
|
|
Source: u_cpu/addr_trans/data_vaddr_buffer_reg[14]/C
|
|
(rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns})
|
|
Destination: u_cpu/icache/data_ram_way[0].data_ram_bank[0].u/mem_reg_reg/ADDRBWRADDR[7]
|
|
(rising edge-triggered cell RAMB18E1 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns})
|
|
Path Group: cpu_clk
|
|
Path Type: Setup (Max at Slow Process Corner)
|
|
Requirement: 30.323ns (cpu_clk rise@30.323ns - cpu_clk rise@0.000ns)
|
|
Data Path Delay: 27.674ns (logic 5.333ns (19.271%) route 22.341ns (80.729%))
|
|
Logic Levels: 26 (CARRY4=4 LUT3=2 LUT4=1 LUT5=2 LUT6=15 MUXF7=1 MUXF8=1)
|
|
Clock Path Skew: -0.089ns (DCD - SCD + CPR)
|
|
Destination Clock Delay (DCD): -1.895ns = ( 28.427 - 30.323 )
|
|
Source Clock Delay (SCD): -2.225ns
|
|
Clock Pessimism Removal (CPR): -0.418ns
|
|
Clock Uncertainty: 0.074ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Discrete Jitter (DJ): 0.130ns
|
|
Phase Error (PE): 0.000ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock cpu_clk rise edge) 0.000 0.000 r
|
|
clock source latency -6.275 -6.275
|
|
propagated clock network latency
|
|
4.051 -2.225
|
|
SLICE_X35Y35 FDRE 0.000 -2.225 r u_cpu/addr_trans/data_vaddr_buffer_reg[14]/C
|
|
SLICE_X35Y35 FDRE (Prop_fdre_C_Q) 0.456 -1.769 r u_cpu/addr_trans/data_vaddr_buffer_reg[14]/Q
|
|
net (fo=33, routed) 1.442 -0.326 u_cpu/addr_trans/tlb_entry/data_vaddr_buffer[2]
|
|
SLICE_X42Y40 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_226/I5
|
|
SLICE_X42Y40 LUT6 (Prop_lut6_I5_O) 0.124 -0.202 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_226/O
|
|
net (fo=1, routed) 0.000 -0.202 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_226_n_0
|
|
SLICE_X42Y40 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_111/S[0]
|
|
SLICE_X42Y40 CARRY4 (Prop_carry4_S[0]_CO[3])
|
|
0.513 0.311 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_111/CO[3]
|
|
net (fo=1, routed) 0.000 0.311 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_111_n_0
|
|
SLICE_X42Y41 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_32/CI
|
|
SLICE_X42Y41 CARRY4 (Prop_carry4_CI_CO[2])
|
|
0.229 0.540 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_32/CO[2]
|
|
net (fo=1, routed) 1.009 1.549 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_32_n_1
|
|
SLICE_X40Y47 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_9/I1
|
|
SLICE_X40Y47 LUT6 (Prop_lut6_I1_O) 0.310 1.859 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_9/O
|
|
net (fo=2, routed) 0.635 2.494 u_cpu/addr_trans/tlb_entry/match1[28]
|
|
SLICE_X38Y47 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/I2
|
|
SLICE_X38Y47 LUT4 (Prop_lut4_I2_O) 0.124 2.618 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/O
|
|
net (fo=2, routed) 0.667 3.285 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2_n_0
|
|
SLICE_X39Y47 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/I0
|
|
SLICE_X39Y47 LUT5 (Prop_lut5_I0_O) 0.124 3.409 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/O
|
|
net (fo=2, routed) 1.103 4.512 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2_n_0
|
|
SLICE_X38Y50 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/I0
|
|
SLICE_X38Y50 LUT6 (Prop_lut6_I0_O) 0.124 4.636 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/O
|
|
net (fo=89, routed) 1.162 5.797 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus[8]
|
|
SLICE_X42Y51 r u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_38__0/S
|
|
SLICE_X42Y51 MUXF7 (Prop_muxf7_S_O) 0.292 6.089 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_38__0/O
|
|
net (fo=1, routed) 0.000 6.089 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_38__0_n_0
|
|
SLICE_X42Y51 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_16__0/I1
|
|
SLICE_X42Y51 MUXF8 (Prop_muxf8_I1_O) 0.088 6.177 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_16__0/O
|
|
net (fo=1, routed) 0.957 7.134 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_16__0_n_0
|
|
SLICE_X42Y50 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7/I0
|
|
SLICE_X42Y50 LUT6 (Prop_lut6_I0_O) 0.319 7.453 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7/O
|
|
net (fo=1, routed) 0.435 7.888 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7_n_0
|
|
SLICE_X44Y50 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0/I5
|
|
SLICE_X44Y50 LUT6 (Prop_lut6_I5_O) 0.124 8.012 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0/O
|
|
net (fo=10, routed) 0.740 8.753 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0_n_0
|
|
SLICE_X44Y50 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[5]_i_1__0/I3
|
|
SLICE_X44Y50 LUT6 (Prop_lut6_I3_O) 0.124 8.877 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[5]_i_1__0/O
|
|
net (fo=6, routed) 0.845 9.722 u_cpu/u_csr/ms_to_ws_bus[13]
|
|
SLICE_X50Y46 r u_cpu/u_csr/write_buffer_way[1]_i_18/I3
|
|
SLICE_X50Y46 LUT6 (Prop_lut6_I3_O) 0.124 9.846 f u_cpu/u_csr/write_buffer_way[1]_i_18/O
|
|
net (fo=1, routed) 0.000 9.846 u_cpu/u_csr/write_buffer_way[1]_i_18_n_0
|
|
SLICE_X50Y46 f u_cpu/u_csr/write_buffer_way_reg[1]_i_11/S[0]
|
|
SLICE_X50Y46 CARRY4 (Prop_carry4_S[0]_CO[3])
|
|
0.532 10.378 r u_cpu/u_csr/write_buffer_way_reg[1]_i_11/CO[3]
|
|
net (fo=1, routed) 0.000 10.378 u_cpu/u_csr/write_buffer_way_reg[1]_i_11_n_0
|
|
SLICE_X50Y47 r u_cpu/u_csr/write_buffer_way_reg[1]_i_9/CI
|
|
SLICE_X50Y47 CARRY4 (Prop_carry4_CI_CO[1])
|
|
0.157 10.535 f u_cpu/u_csr/write_buffer_way_reg[1]_i_9/CO[1]
|
|
net (fo=2, routed) 0.791 11.326 u_cpu/wb_stage/CO[0]
|
|
SLICE_X46Y39 f u_cpu/wb_stage/write_buffer_way[1]_i_5/I1
|
|
SLICE_X46Y39 LUT6 (Prop_lut6_I1_O) 0.329 11.655 r u_cpu/wb_stage/write_buffer_way[1]_i_5/O
|
|
net (fo=7, routed) 0.762 12.417 u_cpu/addr_trans/tlb_entry/sc_cancel_req
|
|
SLICE_X46Y35 r u_cpu/addr_trans/tlb_entry/main_state[0]_i_3/I1
|
|
SLICE_X46Y35 LUT3 (Prop_lut3_I1_O) 0.124 12.541 r u_cpu/addr_trans/tlb_entry/main_state[0]_i_3/O
|
|
net (fo=3, routed) 0.719 13.260 u_cpu/dcache/main_state_reg[0]_2
|
|
SLICE_X43Y31 r u_cpu/dcache/ds_to_es_bus_r[235]_i_10/I3
|
|
SLICE_X43Y31 LUT6 (Prop_lut6_I3_O) 0.124 13.384 r u_cpu/dcache/ds_to_es_bus_r[235]_i_10/O
|
|
net (fo=3, routed) 0.415 13.799 u_cpu/mem_stage/data_data_ok
|
|
SLICE_X43Y30 r u_cpu/mem_stage/flush_inst_req_buffer[1]_i_15/I0
|
|
SLICE_X43Y30 LUT3 (Prop_lut3_I0_O) 0.124 13.923 r u_cpu/mem_stage/flush_inst_req_buffer[1]_i_15/O
|
|
net (fo=2, routed) 0.833 14.756 u_cpu/mem_stage/es_to_ms_bus_r_reg[70]_1
|
|
SLICE_X48Y30 r u_cpu/mem_stage/flush_inst_req_buffer[1]_i_14/I0
|
|
SLICE_X48Y30 LUT6 (Prop_lut6_I0_O) 0.124 14.880 r u_cpu/mem_stage/flush_inst_req_buffer[1]_i_14/O
|
|
net (fo=1, routed) 0.651 15.532 u_cpu/mem_stage/ms_ready_go
|
|
SLICE_X48Y25 r u_cpu/mem_stage/flush_inst_req_buffer[1]_i_13/I4
|
|
SLICE_X48Y25 LUT6 (Prop_lut6_I4_O) 0.124 15.656 r u_cpu/mem_stage/flush_inst_req_buffer[1]_i_13/O
|
|
net (fo=3, routed) 0.483 16.139 u_cpu/id_stage/flush_inst_req_buffer[31]_i_6
|
|
SLICE_X50Y25 r u_cpu/id_stage/flush_inst_req_buffer[1]_i_9/I1
|
|
SLICE_X50Y25 LUT6 (Prop_lut6_I1_O) 0.124 16.263 r u_cpu/id_stage/flush_inst_req_buffer[1]_i_9/O
|
|
net (fo=32, routed) 0.531 16.794 u_cpu/if_stage/nextpc5
|
|
SLICE_X51Y27 r u_cpu/if_stage/fetch_pc_r[6]_i_4/I2
|
|
SLICE_X51Y27 LUT6 (Prop_lut6_I2_O) 0.124 16.918 r u_cpu/if_stage/fetch_pc_r[6]_i_4/O
|
|
net (fo=1, routed) 3.059 19.977 u_cpu/if_stage/fetch_pc_r[6]_i_4_n_0
|
|
SLICE_X114Y28 r u_cpu/if_stage/fetch_pc_r[6]_i_2/I2
|
|
SLICE_X114Y28 LUT6 (Prop_lut6_I2_O) 0.124 20.101 r u_cpu/if_stage/fetch_pc_r[6]_i_2/O
|
|
net (fo=1, routed) 0.441 20.542 u_cpu/if_stage/fetch_pc_r[6]_i_2_n_0
|
|
SLICE_X114Y25 r u_cpu/if_stage/fetch_pc_r[6]_i_1/I2
|
|
SLICE_X114Y25 LUT6 (Prop_lut6_I2_O) 0.124 20.666 r u_cpu/if_stage/fetch_pc_r[6]_i_1/O
|
|
net (fo=6, routed) 3.249 23.915 u_cpu/icache/tagv_ram_way[1].u/mem_reg_reg_2[2]
|
|
SLICE_X49Y33 r u_cpu/icache/tagv_ram_way[1].u/mem_reg_reg_i_8/I4
|
|
SLICE_X49Y33 LUT5 (Prop_lut5_I4_O) 0.124 24.039 r u_cpu/icache/tagv_ram_way[1].u/mem_reg_reg_i_8/O
|
|
net (fo=16, routed) 1.410 25.450 u_cpu/icache/data_ram_way[0].data_ram_bank[0].u/ADDRBWRADDR[2]
|
|
RAMB18_X2Y4 RAMB18E1 r u_cpu/icache/data_ram_way[0].data_ram_bank[0].u/mem_reg_reg/ADDRBWRADDR[7]
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock cpu_clk rise edge) 30.323 30.323 r
|
|
clock source latency -5.674 24.648
|
|
propagated clock network latency
|
|
3.779 28.427
|
|
clock pessimism -0.418 28.009
|
|
clock uncertainty -0.074 27.935
|
|
RAMB18_X2Y4 RAMB18E1 (Setup_ramb18e1_CLKBWRCLK_ADDRBWRADDR[7])
|
|
-0.566 27.369 u_cpu/icache/data_ram_way[0].data_ram_bank[0].u/mem_reg_reg
|
|
-------------------------------------------------------------------
|
|
required time 27.369
|
|
arrival time -25.450
|
|
-------------------------------------------------------------------
|
|
slack 1.920
|
|
|
|
Slack (MET) : 1.920ns (required time - arrival time)
|
|
Source: u_cpu/addr_trans/data_vaddr_buffer_reg[14]/C
|
|
(rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns})
|
|
Destination: u_cpu/icache/data_ram_way[0].data_ram_bank[0].u/mem_reg_reg/ADDRBWRADDR[7]
|
|
(rising edge-triggered cell RAMB18E1 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns})
|
|
Path Group: cpu_clk
|
|
Path Type: Setup (Max at Slow Process Corner)
|
|
Requirement: 30.323ns (cpu_clk rise@30.323ns - cpu_clk rise@0.000ns)
|
|
Data Path Delay: 27.674ns (logic 5.333ns (19.271%) route 22.341ns (80.729%))
|
|
Logic Levels: 26 (CARRY4=4 LUT3=2 LUT4=1 LUT5=2 LUT6=15 MUXF7=1 MUXF8=1)
|
|
Clock Path Skew: -0.089ns (DCD - SCD + CPR)
|
|
Destination Clock Delay (DCD): -1.895ns = ( 28.427 - 30.323 )
|
|
Source Clock Delay (SCD): -2.225ns
|
|
Clock Pessimism Removal (CPR): -0.418ns
|
|
Clock Uncertainty: 0.074ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Discrete Jitter (DJ): 0.130ns
|
|
Phase Error (PE): 0.000ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock cpu_clk rise edge) 0.000 0.000 r
|
|
clock source latency -6.275 -6.275
|
|
propagated clock network latency
|
|
4.051 -2.225
|
|
SLICE_X35Y35 FDRE 0.000 -2.225 r u_cpu/addr_trans/data_vaddr_buffer_reg[14]/C
|
|
SLICE_X35Y35 FDRE (Prop_fdre_C_Q) 0.456 -1.769 r u_cpu/addr_trans/data_vaddr_buffer_reg[14]/Q
|
|
net (fo=33, routed) 1.442 -0.326 u_cpu/addr_trans/tlb_entry/data_vaddr_buffer[2]
|
|
SLICE_X42Y40 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_226/I5
|
|
SLICE_X42Y40 LUT6 (Prop_lut6_I5_O) 0.124 -0.202 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_226/O
|
|
net (fo=1, routed) 0.000 -0.202 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_226_n_0
|
|
SLICE_X42Y40 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_111/S[0]
|
|
SLICE_X42Y40 CARRY4 (Prop_carry4_S[0]_CO[3])
|
|
0.513 0.311 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_111/CO[3]
|
|
net (fo=1, routed) 0.000 0.311 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_111_n_0
|
|
SLICE_X42Y41 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_32/CI
|
|
SLICE_X42Y41 CARRY4 (Prop_carry4_CI_CO[2])
|
|
0.229 0.540 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_32/CO[2]
|
|
net (fo=1, routed) 1.009 1.549 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_32_n_1
|
|
SLICE_X40Y47 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_9/I1
|
|
SLICE_X40Y47 LUT6 (Prop_lut6_I1_O) 0.310 1.859 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_9/O
|
|
net (fo=2, routed) 0.635 2.494 u_cpu/addr_trans/tlb_entry/match1[28]
|
|
SLICE_X38Y47 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/I2
|
|
SLICE_X38Y47 LUT4 (Prop_lut4_I2_O) 0.124 2.618 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/O
|
|
net (fo=2, routed) 0.667 3.285 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2_n_0
|
|
SLICE_X39Y47 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/I0
|
|
SLICE_X39Y47 LUT5 (Prop_lut5_I0_O) 0.124 3.409 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/O
|
|
net (fo=2, routed) 1.103 4.512 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2_n_0
|
|
SLICE_X38Y50 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/I0
|
|
SLICE_X38Y50 LUT6 (Prop_lut6_I0_O) 0.124 4.636 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/O
|
|
net (fo=89, routed) 1.162 5.797 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus[8]
|
|
SLICE_X42Y51 r u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_38__0/S
|
|
SLICE_X42Y51 MUXF7 (Prop_muxf7_S_O) 0.292 6.089 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_38__0/O
|
|
net (fo=1, routed) 0.000 6.089 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_38__0_n_0
|
|
SLICE_X42Y51 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_16__0/I1
|
|
SLICE_X42Y51 MUXF8 (Prop_muxf8_I1_O) 0.088 6.177 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_16__0/O
|
|
net (fo=1, routed) 0.957 7.134 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_16__0_n_0
|
|
SLICE_X42Y50 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7/I0
|
|
SLICE_X42Y50 LUT6 (Prop_lut6_I0_O) 0.319 7.453 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7/O
|
|
net (fo=1, routed) 0.435 7.888 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7_n_0
|
|
SLICE_X44Y50 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0/I5
|
|
SLICE_X44Y50 LUT6 (Prop_lut6_I5_O) 0.124 8.012 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0/O
|
|
net (fo=10, routed) 0.740 8.753 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0_n_0
|
|
SLICE_X44Y50 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[5]_i_1__0/I3
|
|
SLICE_X44Y50 LUT6 (Prop_lut6_I3_O) 0.124 8.877 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[5]_i_1__0/O
|
|
net (fo=6, routed) 0.845 9.722 u_cpu/u_csr/ms_to_ws_bus[13]
|
|
SLICE_X50Y46 f u_cpu/u_csr/write_buffer_way[1]_i_18/I3
|
|
SLICE_X50Y46 LUT6 (Prop_lut6_I3_O) 0.124 9.846 f u_cpu/u_csr/write_buffer_way[1]_i_18/O
|
|
net (fo=1, routed) 0.000 9.846 u_cpu/u_csr/write_buffer_way[1]_i_18_n_0
|
|
SLICE_X50Y46 f u_cpu/u_csr/write_buffer_way_reg[1]_i_11/S[0]
|
|
SLICE_X50Y46 CARRY4 (Prop_carry4_S[0]_CO[3])
|
|
0.532 10.378 r u_cpu/u_csr/write_buffer_way_reg[1]_i_11/CO[3]
|
|
net (fo=1, routed) 0.000 10.378 u_cpu/u_csr/write_buffer_way_reg[1]_i_11_n_0
|
|
SLICE_X50Y47 r u_cpu/u_csr/write_buffer_way_reg[1]_i_9/CI
|
|
SLICE_X50Y47 CARRY4 (Prop_carry4_CI_CO[1])
|
|
0.157 10.535 f u_cpu/u_csr/write_buffer_way_reg[1]_i_9/CO[1]
|
|
net (fo=2, routed) 0.791 11.326 u_cpu/wb_stage/CO[0]
|
|
SLICE_X46Y39 f u_cpu/wb_stage/write_buffer_way[1]_i_5/I1
|
|
SLICE_X46Y39 LUT6 (Prop_lut6_I1_O) 0.329 11.655 r u_cpu/wb_stage/write_buffer_way[1]_i_5/O
|
|
net (fo=7, routed) 0.762 12.417 u_cpu/addr_trans/tlb_entry/sc_cancel_req
|
|
SLICE_X46Y35 r u_cpu/addr_trans/tlb_entry/main_state[0]_i_3/I1
|
|
SLICE_X46Y35 LUT3 (Prop_lut3_I1_O) 0.124 12.541 r u_cpu/addr_trans/tlb_entry/main_state[0]_i_3/O
|
|
net (fo=3, routed) 0.719 13.260 u_cpu/dcache/main_state_reg[0]_2
|
|
SLICE_X43Y31 r u_cpu/dcache/ds_to_es_bus_r[235]_i_10/I3
|
|
SLICE_X43Y31 LUT6 (Prop_lut6_I3_O) 0.124 13.384 r u_cpu/dcache/ds_to_es_bus_r[235]_i_10/O
|
|
net (fo=3, routed) 0.415 13.799 u_cpu/mem_stage/data_data_ok
|
|
SLICE_X43Y30 r u_cpu/mem_stage/flush_inst_req_buffer[1]_i_15/I0
|
|
SLICE_X43Y30 LUT3 (Prop_lut3_I0_O) 0.124 13.923 r u_cpu/mem_stage/flush_inst_req_buffer[1]_i_15/O
|
|
net (fo=2, routed) 0.833 14.756 u_cpu/mem_stage/es_to_ms_bus_r_reg[70]_1
|
|
SLICE_X48Y30 r u_cpu/mem_stage/flush_inst_req_buffer[1]_i_14/I0
|
|
SLICE_X48Y30 LUT6 (Prop_lut6_I0_O) 0.124 14.880 r u_cpu/mem_stage/flush_inst_req_buffer[1]_i_14/O
|
|
net (fo=1, routed) 0.651 15.532 u_cpu/mem_stage/ms_ready_go
|
|
SLICE_X48Y25 r u_cpu/mem_stage/flush_inst_req_buffer[1]_i_13/I4
|
|
SLICE_X48Y25 LUT6 (Prop_lut6_I4_O) 0.124 15.656 r u_cpu/mem_stage/flush_inst_req_buffer[1]_i_13/O
|
|
net (fo=3, routed) 0.483 16.139 u_cpu/id_stage/flush_inst_req_buffer[31]_i_6
|
|
SLICE_X50Y25 r u_cpu/id_stage/flush_inst_req_buffer[1]_i_9/I1
|
|
SLICE_X50Y25 LUT6 (Prop_lut6_I1_O) 0.124 16.263 r u_cpu/id_stage/flush_inst_req_buffer[1]_i_9/O
|
|
net (fo=32, routed) 0.531 16.794 u_cpu/if_stage/nextpc5
|
|
SLICE_X51Y27 r u_cpu/if_stage/fetch_pc_r[6]_i_4/I2
|
|
SLICE_X51Y27 LUT6 (Prop_lut6_I2_O) 0.124 16.918 r u_cpu/if_stage/fetch_pc_r[6]_i_4/O
|
|
net (fo=1, routed) 3.059 19.977 u_cpu/if_stage/fetch_pc_r[6]_i_4_n_0
|
|
SLICE_X114Y28 r u_cpu/if_stage/fetch_pc_r[6]_i_2/I2
|
|
SLICE_X114Y28 LUT6 (Prop_lut6_I2_O) 0.124 20.101 r u_cpu/if_stage/fetch_pc_r[6]_i_2/O
|
|
net (fo=1, routed) 0.441 20.542 u_cpu/if_stage/fetch_pc_r[6]_i_2_n_0
|
|
SLICE_X114Y25 r u_cpu/if_stage/fetch_pc_r[6]_i_1/I2
|
|
SLICE_X114Y25 LUT6 (Prop_lut6_I2_O) 0.124 20.666 r u_cpu/if_stage/fetch_pc_r[6]_i_1/O
|
|
net (fo=6, routed) 3.249 23.915 u_cpu/icache/tagv_ram_way[1].u/mem_reg_reg_2[2]
|
|
SLICE_X49Y33 r u_cpu/icache/tagv_ram_way[1].u/mem_reg_reg_i_8/I4
|
|
SLICE_X49Y33 LUT5 (Prop_lut5_I4_O) 0.124 24.039 r u_cpu/icache/tagv_ram_way[1].u/mem_reg_reg_i_8/O
|
|
net (fo=16, routed) 1.410 25.450 u_cpu/icache/data_ram_way[0].data_ram_bank[0].u/ADDRBWRADDR[2]
|
|
RAMB18_X2Y4 RAMB18E1 r u_cpu/icache/data_ram_way[0].data_ram_bank[0].u/mem_reg_reg/ADDRBWRADDR[7]
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock cpu_clk rise edge) 30.323 30.323 r
|
|
clock source latency -5.674 24.648
|
|
propagated clock network latency
|
|
3.779 28.427
|
|
clock pessimism -0.418 28.009
|
|
clock uncertainty -0.074 27.935
|
|
RAMB18_X2Y4 RAMB18E1 (Setup_ramb18e1_CLKBWRCLK_ADDRBWRADDR[7])
|
|
-0.566 27.369 u_cpu/icache/data_ram_way[0].data_ram_bank[0].u/mem_reg_reg
|
|
-------------------------------------------------------------------
|
|
required time 27.369
|
|
arrival time -25.450
|
|
-------------------------------------------------------------------
|
|
slack 1.920
|
|
|
|
Slack (MET) : 1.920ns (required time - arrival time)
|
|
Source: u_cpu/addr_trans/data_vaddr_buffer_reg[14]/C
|
|
(rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns})
|
|
Destination: u_cpu/icache/data_ram_way[0].data_ram_bank[0].u/mem_reg_reg/ADDRBWRADDR[7]
|
|
(rising edge-triggered cell RAMB18E1 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns})
|
|
Path Group: cpu_clk
|
|
Path Type: Setup (Max at Slow Process Corner)
|
|
Requirement: 30.323ns (cpu_clk rise@30.323ns - cpu_clk rise@0.000ns)
|
|
Data Path Delay: 27.674ns (logic 5.333ns (19.271%) route 22.341ns (80.729%))
|
|
Logic Levels: 26 (CARRY4=4 LUT3=2 LUT4=1 LUT5=2 LUT6=15 MUXF7=1 MUXF8=1)
|
|
Clock Path Skew: -0.089ns (DCD - SCD + CPR)
|
|
Destination Clock Delay (DCD): -1.895ns = ( 28.427 - 30.323 )
|
|
Source Clock Delay (SCD): -2.225ns
|
|
Clock Pessimism Removal (CPR): -0.418ns
|
|
Clock Uncertainty: 0.074ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Discrete Jitter (DJ): 0.130ns
|
|
Phase Error (PE): 0.000ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock cpu_clk rise edge) 0.000 0.000 r
|
|
clock source latency -6.275 -6.275
|
|
propagated clock network latency
|
|
4.051 -2.225
|
|
SLICE_X35Y35 FDRE 0.000 -2.225 r u_cpu/addr_trans/data_vaddr_buffer_reg[14]/C
|
|
SLICE_X35Y35 FDRE (Prop_fdre_C_Q) 0.456 -1.769 r u_cpu/addr_trans/data_vaddr_buffer_reg[14]/Q
|
|
net (fo=33, routed) 1.442 -0.326 u_cpu/addr_trans/tlb_entry/data_vaddr_buffer[2]
|
|
SLICE_X42Y40 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_226/I5
|
|
SLICE_X42Y40 LUT6 (Prop_lut6_I5_O) 0.124 -0.202 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_226/O
|
|
net (fo=1, routed) 0.000 -0.202 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_226_n_0
|
|
SLICE_X42Y40 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_111/S[0]
|
|
SLICE_X42Y40 CARRY4 (Prop_carry4_S[0]_CO[3])
|
|
0.513 0.311 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_111/CO[3]
|
|
net (fo=1, routed) 0.000 0.311 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_111_n_0
|
|
SLICE_X42Y41 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_32/CI
|
|
SLICE_X42Y41 CARRY4 (Prop_carry4_CI_CO[2])
|
|
0.229 0.540 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_32/CO[2]
|
|
net (fo=1, routed) 1.009 1.549 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_32_n_1
|
|
SLICE_X40Y47 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_9/I1
|
|
SLICE_X40Y47 LUT6 (Prop_lut6_I1_O) 0.310 1.859 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_9/O
|
|
net (fo=2, routed) 0.635 2.494 u_cpu/addr_trans/tlb_entry/match1[28]
|
|
SLICE_X38Y47 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/I2
|
|
SLICE_X38Y47 LUT4 (Prop_lut4_I2_O) 0.124 2.618 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/O
|
|
net (fo=2, routed) 0.667 3.285 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2_n_0
|
|
SLICE_X39Y47 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/I0
|
|
SLICE_X39Y47 LUT5 (Prop_lut5_I0_O) 0.124 3.409 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/O
|
|
net (fo=2, routed) 1.103 4.512 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2_n_0
|
|
SLICE_X38Y50 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/I0
|
|
SLICE_X38Y50 LUT6 (Prop_lut6_I0_O) 0.124 4.636 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/O
|
|
net (fo=89, routed) 1.162 5.797 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus[8]
|
|
SLICE_X42Y51 r u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_38__0/S
|
|
SLICE_X42Y51 MUXF7 (Prop_muxf7_S_O) 0.292 6.089 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_38__0/O
|
|
net (fo=1, routed) 0.000 6.089 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_38__0_n_0
|
|
SLICE_X42Y51 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_16__0/I1
|
|
SLICE_X42Y51 MUXF8 (Prop_muxf8_I1_O) 0.088 6.177 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_16__0/O
|
|
net (fo=1, routed) 0.957 7.134 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_16__0_n_0
|
|
SLICE_X42Y50 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7/I0
|
|
SLICE_X42Y50 LUT6 (Prop_lut6_I0_O) 0.319 7.453 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7/O
|
|
net (fo=1, routed) 0.435 7.888 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7_n_0
|
|
SLICE_X44Y50 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0/I5
|
|
SLICE_X44Y50 LUT6 (Prop_lut6_I5_O) 0.124 8.012 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0/O
|
|
net (fo=10, routed) 0.740 8.753 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0_n_0
|
|
SLICE_X44Y50 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[5]_i_1__0/I3
|
|
SLICE_X44Y50 LUT6 (Prop_lut6_I3_O) 0.124 8.877 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[5]_i_1__0/O
|
|
net (fo=6, routed) 0.845 9.722 u_cpu/u_csr/ms_to_ws_bus[13]
|
|
SLICE_X50Y46 r u_cpu/u_csr/write_buffer_way[1]_i_18/I3
|
|
SLICE_X50Y46 LUT6 (Prop_lut6_I3_O) 0.124 9.846 r u_cpu/u_csr/write_buffer_way[1]_i_18/O
|
|
net (fo=1, routed) 0.000 9.846 u_cpu/u_csr/write_buffer_way[1]_i_18_n_0
|
|
SLICE_X50Y46 r u_cpu/u_csr/write_buffer_way_reg[1]_i_11/S[0]
|
|
SLICE_X50Y46 CARRY4 (Prop_carry4_S[0]_CO[3])
|
|
0.532 10.378 f u_cpu/u_csr/write_buffer_way_reg[1]_i_11/CO[3]
|
|
net (fo=1, routed) 0.000 10.378 u_cpu/u_csr/write_buffer_way_reg[1]_i_11_n_0
|
|
SLICE_X50Y47 f u_cpu/u_csr/write_buffer_way_reg[1]_i_9/CI
|
|
SLICE_X50Y47 CARRY4 (Prop_carry4_CI_CO[1])
|
|
0.157 10.535 f u_cpu/u_csr/write_buffer_way_reg[1]_i_9/CO[1]
|
|
net (fo=2, routed) 0.791 11.326 u_cpu/wb_stage/CO[0]
|
|
SLICE_X46Y39 f u_cpu/wb_stage/write_buffer_way[1]_i_5/I1
|
|
SLICE_X46Y39 LUT6 (Prop_lut6_I1_O) 0.329 11.655 r u_cpu/wb_stage/write_buffer_way[1]_i_5/O
|
|
net (fo=7, routed) 0.762 12.417 u_cpu/addr_trans/tlb_entry/sc_cancel_req
|
|
SLICE_X46Y35 r u_cpu/addr_trans/tlb_entry/main_state[0]_i_3/I1
|
|
SLICE_X46Y35 LUT3 (Prop_lut3_I1_O) 0.124 12.541 r u_cpu/addr_trans/tlb_entry/main_state[0]_i_3/O
|
|
net (fo=3, routed) 0.719 13.260 u_cpu/dcache/main_state_reg[0]_2
|
|
SLICE_X43Y31 r u_cpu/dcache/ds_to_es_bus_r[235]_i_10/I3
|
|
SLICE_X43Y31 LUT6 (Prop_lut6_I3_O) 0.124 13.384 r u_cpu/dcache/ds_to_es_bus_r[235]_i_10/O
|
|
net (fo=3, routed) 0.415 13.799 u_cpu/mem_stage/data_data_ok
|
|
SLICE_X43Y30 r u_cpu/mem_stage/flush_inst_req_buffer[1]_i_15/I0
|
|
SLICE_X43Y30 LUT3 (Prop_lut3_I0_O) 0.124 13.923 r u_cpu/mem_stage/flush_inst_req_buffer[1]_i_15/O
|
|
net (fo=2, routed) 0.833 14.756 u_cpu/mem_stage/es_to_ms_bus_r_reg[70]_1
|
|
SLICE_X48Y30 r u_cpu/mem_stage/flush_inst_req_buffer[1]_i_14/I0
|
|
SLICE_X48Y30 LUT6 (Prop_lut6_I0_O) 0.124 14.880 r u_cpu/mem_stage/flush_inst_req_buffer[1]_i_14/O
|
|
net (fo=1, routed) 0.651 15.532 u_cpu/mem_stage/ms_ready_go
|
|
SLICE_X48Y25 r u_cpu/mem_stage/flush_inst_req_buffer[1]_i_13/I4
|
|
SLICE_X48Y25 LUT6 (Prop_lut6_I4_O) 0.124 15.656 r u_cpu/mem_stage/flush_inst_req_buffer[1]_i_13/O
|
|
net (fo=3, routed) 0.483 16.139 u_cpu/id_stage/flush_inst_req_buffer[31]_i_6
|
|
SLICE_X50Y25 r u_cpu/id_stage/flush_inst_req_buffer[1]_i_9/I1
|
|
SLICE_X50Y25 LUT6 (Prop_lut6_I1_O) 0.124 16.263 r u_cpu/id_stage/flush_inst_req_buffer[1]_i_9/O
|
|
net (fo=32, routed) 0.531 16.794 u_cpu/if_stage/nextpc5
|
|
SLICE_X51Y27 r u_cpu/if_stage/fetch_pc_r[6]_i_4/I2
|
|
SLICE_X51Y27 LUT6 (Prop_lut6_I2_O) 0.124 16.918 r u_cpu/if_stage/fetch_pc_r[6]_i_4/O
|
|
net (fo=1, routed) 3.059 19.977 u_cpu/if_stage/fetch_pc_r[6]_i_4_n_0
|
|
SLICE_X114Y28 r u_cpu/if_stage/fetch_pc_r[6]_i_2/I2
|
|
SLICE_X114Y28 LUT6 (Prop_lut6_I2_O) 0.124 20.101 r u_cpu/if_stage/fetch_pc_r[6]_i_2/O
|
|
net (fo=1, routed) 0.441 20.542 u_cpu/if_stage/fetch_pc_r[6]_i_2_n_0
|
|
SLICE_X114Y25 r u_cpu/if_stage/fetch_pc_r[6]_i_1/I2
|
|
SLICE_X114Y25 LUT6 (Prop_lut6_I2_O) 0.124 20.666 r u_cpu/if_stage/fetch_pc_r[6]_i_1/O
|
|
net (fo=6, routed) 3.249 23.915 u_cpu/icache/tagv_ram_way[1].u/mem_reg_reg_2[2]
|
|
SLICE_X49Y33 r u_cpu/icache/tagv_ram_way[1].u/mem_reg_reg_i_8/I4
|
|
SLICE_X49Y33 LUT5 (Prop_lut5_I4_O) 0.124 24.039 r u_cpu/icache/tagv_ram_way[1].u/mem_reg_reg_i_8/O
|
|
net (fo=16, routed) 1.410 25.450 u_cpu/icache/data_ram_way[0].data_ram_bank[0].u/ADDRBWRADDR[2]
|
|
RAMB18_X2Y4 RAMB18E1 r u_cpu/icache/data_ram_way[0].data_ram_bank[0].u/mem_reg_reg/ADDRBWRADDR[7]
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock cpu_clk rise edge) 30.323 30.323 r
|
|
clock source latency -5.674 24.648
|
|
propagated clock network latency
|
|
3.779 28.427
|
|
clock pessimism -0.418 28.009
|
|
clock uncertainty -0.074 27.935
|
|
RAMB18_X2Y4 RAMB18E1 (Setup_ramb18e1_CLKBWRCLK_ADDRBWRADDR[7])
|
|
-0.566 27.369 u_cpu/icache/data_ram_way[0].data_ram_bank[0].u/mem_reg_reg
|
|
-------------------------------------------------------------------
|
|
required time 27.369
|
|
arrival time -25.450
|
|
-------------------------------------------------------------------
|
|
slack 1.920
|
|
|
|
Slack (MET) : 1.920ns (required time - arrival time)
|
|
Source: u_cpu/addr_trans/data_vaddr_buffer_reg[14]/C
|
|
(rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns})
|
|
Destination: u_cpu/icache/data_ram_way[0].data_ram_bank[0].u/mem_reg_reg/ADDRBWRADDR[7]
|
|
(rising edge-triggered cell RAMB18E1 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns})
|
|
Path Group: cpu_clk
|
|
Path Type: Setup (Max at Slow Process Corner)
|
|
Requirement: 30.323ns (cpu_clk rise@30.323ns - cpu_clk rise@0.000ns)
|
|
Data Path Delay: 27.674ns (logic 5.333ns (19.271%) route 22.341ns (80.729%))
|
|
Logic Levels: 26 (CARRY4=4 LUT3=2 LUT4=1 LUT5=2 LUT6=15 MUXF7=1 MUXF8=1)
|
|
Clock Path Skew: -0.089ns (DCD - SCD + CPR)
|
|
Destination Clock Delay (DCD): -1.895ns = ( 28.427 - 30.323 )
|
|
Source Clock Delay (SCD): -2.225ns
|
|
Clock Pessimism Removal (CPR): -0.418ns
|
|
Clock Uncertainty: 0.074ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Discrete Jitter (DJ): 0.130ns
|
|
Phase Error (PE): 0.000ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock cpu_clk rise edge) 0.000 0.000 r
|
|
clock source latency -6.275 -6.275
|
|
propagated clock network latency
|
|
4.051 -2.225
|
|
SLICE_X35Y35 FDRE 0.000 -2.225 r u_cpu/addr_trans/data_vaddr_buffer_reg[14]/C
|
|
SLICE_X35Y35 FDRE (Prop_fdre_C_Q) 0.456 -1.769 r u_cpu/addr_trans/data_vaddr_buffer_reg[14]/Q
|
|
net (fo=33, routed) 1.442 -0.326 u_cpu/addr_trans/tlb_entry/data_vaddr_buffer[2]
|
|
SLICE_X42Y40 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_226/I5
|
|
SLICE_X42Y40 LUT6 (Prop_lut6_I5_O) 0.124 -0.202 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_226/O
|
|
net (fo=1, routed) 0.000 -0.202 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_226_n_0
|
|
SLICE_X42Y40 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_111/S[0]
|
|
SLICE_X42Y40 CARRY4 (Prop_carry4_S[0]_CO[3])
|
|
0.513 0.311 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_111/CO[3]
|
|
net (fo=1, routed) 0.000 0.311 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_111_n_0
|
|
SLICE_X42Y41 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_32/CI
|
|
SLICE_X42Y41 CARRY4 (Prop_carry4_CI_CO[2])
|
|
0.229 0.540 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_32/CO[2]
|
|
net (fo=1, routed) 1.009 1.549 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_32_n_1
|
|
SLICE_X40Y47 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_9/I1
|
|
SLICE_X40Y47 LUT6 (Prop_lut6_I1_O) 0.310 1.859 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_9/O
|
|
net (fo=2, routed) 0.635 2.494 u_cpu/addr_trans/tlb_entry/match1[28]
|
|
SLICE_X38Y47 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/I2
|
|
SLICE_X38Y47 LUT4 (Prop_lut4_I2_O) 0.124 2.618 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/O
|
|
net (fo=2, routed) 0.667 3.285 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2_n_0
|
|
SLICE_X39Y47 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/I0
|
|
SLICE_X39Y47 LUT5 (Prop_lut5_I0_O) 0.124 3.409 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/O
|
|
net (fo=2, routed) 1.103 4.512 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2_n_0
|
|
SLICE_X38Y50 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/I0
|
|
SLICE_X38Y50 LUT6 (Prop_lut6_I0_O) 0.124 4.636 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/O
|
|
net (fo=89, routed) 1.162 5.797 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus[8]
|
|
SLICE_X42Y51 r u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_38__0/S
|
|
SLICE_X42Y51 MUXF7 (Prop_muxf7_S_O) 0.292 6.089 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_38__0/O
|
|
net (fo=1, routed) 0.000 6.089 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_38__0_n_0
|
|
SLICE_X42Y51 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_16__0/I1
|
|
SLICE_X42Y51 MUXF8 (Prop_muxf8_I1_O) 0.088 6.177 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_16__0/O
|
|
net (fo=1, routed) 0.957 7.134 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_16__0_n_0
|
|
SLICE_X42Y50 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7/I0
|
|
SLICE_X42Y50 LUT6 (Prop_lut6_I0_O) 0.319 7.453 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7/O
|
|
net (fo=1, routed) 0.435 7.888 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7_n_0
|
|
SLICE_X44Y50 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0/I5
|
|
SLICE_X44Y50 LUT6 (Prop_lut6_I5_O) 0.124 8.012 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0/O
|
|
net (fo=10, routed) 0.740 8.753 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0_n_0
|
|
SLICE_X44Y50 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[5]_i_1__0/I3
|
|
SLICE_X44Y50 LUT6 (Prop_lut6_I3_O) 0.124 8.877 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[5]_i_1__0/O
|
|
net (fo=6, routed) 0.845 9.722 u_cpu/u_csr/ms_to_ws_bus[13]
|
|
SLICE_X50Y46 f u_cpu/u_csr/write_buffer_way[1]_i_18/I3
|
|
SLICE_X50Y46 LUT6 (Prop_lut6_I3_O) 0.124 9.846 r u_cpu/u_csr/write_buffer_way[1]_i_18/O
|
|
net (fo=1, routed) 0.000 9.846 u_cpu/u_csr/write_buffer_way[1]_i_18_n_0
|
|
SLICE_X50Y46 r u_cpu/u_csr/write_buffer_way_reg[1]_i_11/S[0]
|
|
SLICE_X50Y46 CARRY4 (Prop_carry4_S[0]_CO[3])
|
|
0.532 10.378 f u_cpu/u_csr/write_buffer_way_reg[1]_i_11/CO[3]
|
|
net (fo=1, routed) 0.000 10.378 u_cpu/u_csr/write_buffer_way_reg[1]_i_11_n_0
|
|
SLICE_X50Y47 f u_cpu/u_csr/write_buffer_way_reg[1]_i_9/CI
|
|
SLICE_X50Y47 CARRY4 (Prop_carry4_CI_CO[1])
|
|
0.157 10.535 f u_cpu/u_csr/write_buffer_way_reg[1]_i_9/CO[1]
|
|
net (fo=2, routed) 0.791 11.326 u_cpu/wb_stage/CO[0]
|
|
SLICE_X46Y39 f u_cpu/wb_stage/write_buffer_way[1]_i_5/I1
|
|
SLICE_X46Y39 LUT6 (Prop_lut6_I1_O) 0.329 11.655 r u_cpu/wb_stage/write_buffer_way[1]_i_5/O
|
|
net (fo=7, routed) 0.762 12.417 u_cpu/addr_trans/tlb_entry/sc_cancel_req
|
|
SLICE_X46Y35 r u_cpu/addr_trans/tlb_entry/main_state[0]_i_3/I1
|
|
SLICE_X46Y35 LUT3 (Prop_lut3_I1_O) 0.124 12.541 r u_cpu/addr_trans/tlb_entry/main_state[0]_i_3/O
|
|
net (fo=3, routed) 0.719 13.260 u_cpu/dcache/main_state_reg[0]_2
|
|
SLICE_X43Y31 r u_cpu/dcache/ds_to_es_bus_r[235]_i_10/I3
|
|
SLICE_X43Y31 LUT6 (Prop_lut6_I3_O) 0.124 13.384 r u_cpu/dcache/ds_to_es_bus_r[235]_i_10/O
|
|
net (fo=3, routed) 0.415 13.799 u_cpu/mem_stage/data_data_ok
|
|
SLICE_X43Y30 r u_cpu/mem_stage/flush_inst_req_buffer[1]_i_15/I0
|
|
SLICE_X43Y30 LUT3 (Prop_lut3_I0_O) 0.124 13.923 r u_cpu/mem_stage/flush_inst_req_buffer[1]_i_15/O
|
|
net (fo=2, routed) 0.833 14.756 u_cpu/mem_stage/es_to_ms_bus_r_reg[70]_1
|
|
SLICE_X48Y30 r u_cpu/mem_stage/flush_inst_req_buffer[1]_i_14/I0
|
|
SLICE_X48Y30 LUT6 (Prop_lut6_I0_O) 0.124 14.880 r u_cpu/mem_stage/flush_inst_req_buffer[1]_i_14/O
|
|
net (fo=1, routed) 0.651 15.532 u_cpu/mem_stage/ms_ready_go
|
|
SLICE_X48Y25 r u_cpu/mem_stage/flush_inst_req_buffer[1]_i_13/I4
|
|
SLICE_X48Y25 LUT6 (Prop_lut6_I4_O) 0.124 15.656 r u_cpu/mem_stage/flush_inst_req_buffer[1]_i_13/O
|
|
net (fo=3, routed) 0.483 16.139 u_cpu/id_stage/flush_inst_req_buffer[31]_i_6
|
|
SLICE_X50Y25 r u_cpu/id_stage/flush_inst_req_buffer[1]_i_9/I1
|
|
SLICE_X50Y25 LUT6 (Prop_lut6_I1_O) 0.124 16.263 r u_cpu/id_stage/flush_inst_req_buffer[1]_i_9/O
|
|
net (fo=32, routed) 0.531 16.794 u_cpu/if_stage/nextpc5
|
|
SLICE_X51Y27 r u_cpu/if_stage/fetch_pc_r[6]_i_4/I2
|
|
SLICE_X51Y27 LUT6 (Prop_lut6_I2_O) 0.124 16.918 r u_cpu/if_stage/fetch_pc_r[6]_i_4/O
|
|
net (fo=1, routed) 3.059 19.977 u_cpu/if_stage/fetch_pc_r[6]_i_4_n_0
|
|
SLICE_X114Y28 r u_cpu/if_stage/fetch_pc_r[6]_i_2/I2
|
|
SLICE_X114Y28 LUT6 (Prop_lut6_I2_O) 0.124 20.101 r u_cpu/if_stage/fetch_pc_r[6]_i_2/O
|
|
net (fo=1, routed) 0.441 20.542 u_cpu/if_stage/fetch_pc_r[6]_i_2_n_0
|
|
SLICE_X114Y25 r u_cpu/if_stage/fetch_pc_r[6]_i_1/I2
|
|
SLICE_X114Y25 LUT6 (Prop_lut6_I2_O) 0.124 20.666 r u_cpu/if_stage/fetch_pc_r[6]_i_1/O
|
|
net (fo=6, routed) 3.249 23.915 u_cpu/icache/tagv_ram_way[1].u/mem_reg_reg_2[2]
|
|
SLICE_X49Y33 r u_cpu/icache/tagv_ram_way[1].u/mem_reg_reg_i_8/I4
|
|
SLICE_X49Y33 LUT5 (Prop_lut5_I4_O) 0.124 24.039 r u_cpu/icache/tagv_ram_way[1].u/mem_reg_reg_i_8/O
|
|
net (fo=16, routed) 1.410 25.450 u_cpu/icache/data_ram_way[0].data_ram_bank[0].u/ADDRBWRADDR[2]
|
|
RAMB18_X2Y4 RAMB18E1 r u_cpu/icache/data_ram_way[0].data_ram_bank[0].u/mem_reg_reg/ADDRBWRADDR[7]
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock cpu_clk rise edge) 30.323 30.323 r
|
|
clock source latency -5.674 24.648
|
|
propagated clock network latency
|
|
3.779 28.427
|
|
clock pessimism -0.418 28.009
|
|
clock uncertainty -0.074 27.935
|
|
RAMB18_X2Y4 RAMB18E1 (Setup_ramb18e1_CLKBWRCLK_ADDRBWRADDR[7])
|
|
-0.566 27.369 u_cpu/icache/data_ram_way[0].data_ram_bank[0].u/mem_reg_reg
|
|
-------------------------------------------------------------------
|
|
required time 27.369
|
|
arrival time -25.450
|
|
-------------------------------------------------------------------
|
|
slack 1.920
|
|
|
|
Slack (MET) : 1.920ns (required time - arrival time)
|
|
Source: u_cpu/addr_trans/data_vaddr_buffer_reg[14]/C
|
|
(rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns})
|
|
Destination: u_cpu/icache/data_ram_way[0].data_ram_bank[0].u/mem_reg_reg/ADDRBWRADDR[7]
|
|
(rising edge-triggered cell RAMB18E1 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns})
|
|
Path Group: cpu_clk
|
|
Path Type: Setup (Max at Slow Process Corner)
|
|
Requirement: 30.323ns (cpu_clk rise@30.323ns - cpu_clk rise@0.000ns)
|
|
Data Path Delay: 27.674ns (logic 5.333ns (19.271%) route 22.341ns (80.729%))
|
|
Logic Levels: 26 (CARRY4=4 LUT3=2 LUT4=1 LUT5=2 LUT6=15 MUXF7=1 MUXF8=1)
|
|
Clock Path Skew: -0.089ns (DCD - SCD + CPR)
|
|
Destination Clock Delay (DCD): -1.895ns = ( 28.427 - 30.323 )
|
|
Source Clock Delay (SCD): -2.225ns
|
|
Clock Pessimism Removal (CPR): -0.418ns
|
|
Clock Uncertainty: 0.074ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Discrete Jitter (DJ): 0.130ns
|
|
Phase Error (PE): 0.000ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock cpu_clk rise edge) 0.000 0.000 r
|
|
clock source latency -6.275 -6.275
|
|
propagated clock network latency
|
|
4.051 -2.225
|
|
SLICE_X35Y35 FDRE 0.000 -2.225 r u_cpu/addr_trans/data_vaddr_buffer_reg[14]/C
|
|
SLICE_X35Y35 FDRE (Prop_fdre_C_Q) 0.456 -1.769 r u_cpu/addr_trans/data_vaddr_buffer_reg[14]/Q
|
|
net (fo=33, routed) 1.442 -0.326 u_cpu/addr_trans/tlb_entry/data_vaddr_buffer[2]
|
|
SLICE_X42Y40 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_226/I5
|
|
SLICE_X42Y40 LUT6 (Prop_lut6_I5_O) 0.124 -0.202 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_226/O
|
|
net (fo=1, routed) 0.000 -0.202 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_226_n_0
|
|
SLICE_X42Y40 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_111/S[0]
|
|
SLICE_X42Y40 CARRY4 (Prop_carry4_S[0]_CO[3])
|
|
0.513 0.311 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_111/CO[3]
|
|
net (fo=1, routed) 0.000 0.311 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_111_n_0
|
|
SLICE_X42Y41 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_32/CI
|
|
SLICE_X42Y41 CARRY4 (Prop_carry4_CI_CO[2])
|
|
0.229 0.540 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_32/CO[2]
|
|
net (fo=1, routed) 1.009 1.549 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_32_n_1
|
|
SLICE_X40Y47 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_9/I1
|
|
SLICE_X40Y47 LUT6 (Prop_lut6_I1_O) 0.310 1.859 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_9/O
|
|
net (fo=2, routed) 0.635 2.494 u_cpu/addr_trans/tlb_entry/match1[28]
|
|
SLICE_X38Y47 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/I2
|
|
SLICE_X38Y47 LUT4 (Prop_lut4_I2_O) 0.124 2.618 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/O
|
|
net (fo=2, routed) 0.667 3.285 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2_n_0
|
|
SLICE_X39Y47 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/I0
|
|
SLICE_X39Y47 LUT5 (Prop_lut5_I0_O) 0.124 3.409 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/O
|
|
net (fo=2, routed) 1.103 4.512 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2_n_0
|
|
SLICE_X38Y50 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/I0
|
|
SLICE_X38Y50 LUT6 (Prop_lut6_I0_O) 0.124 4.636 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/O
|
|
net (fo=89, routed) 1.162 5.797 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus[8]
|
|
SLICE_X42Y51 r u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_38__0/S
|
|
SLICE_X42Y51 MUXF7 (Prop_muxf7_S_O) 0.292 6.089 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_38__0/O
|
|
net (fo=1, routed) 0.000 6.089 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_38__0_n_0
|
|
SLICE_X42Y51 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_16__0/I1
|
|
SLICE_X42Y51 MUXF8 (Prop_muxf8_I1_O) 0.088 6.177 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_16__0/O
|
|
net (fo=1, routed) 0.957 7.134 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_16__0_n_0
|
|
SLICE_X42Y50 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7/I0
|
|
SLICE_X42Y50 LUT6 (Prop_lut6_I0_O) 0.319 7.453 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7/O
|
|
net (fo=1, routed) 0.435 7.888 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7_n_0
|
|
SLICE_X44Y50 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0/I5
|
|
SLICE_X44Y50 LUT6 (Prop_lut6_I5_O) 0.124 8.012 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0/O
|
|
net (fo=10, routed) 0.740 8.753 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0_n_0
|
|
SLICE_X44Y50 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[5]_i_1__0/I3
|
|
SLICE_X44Y50 LUT6 (Prop_lut6_I3_O) 0.124 8.877 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[5]_i_1__0/O
|
|
net (fo=6, routed) 0.845 9.722 u_cpu/u_csr/ms_to_ws_bus[13]
|
|
SLICE_X50Y46 r u_cpu/u_csr/write_buffer_way[1]_i_18/I3
|
|
SLICE_X50Y46 LUT6 (Prop_lut6_I3_O) 0.124 9.846 r u_cpu/u_csr/write_buffer_way[1]_i_18/O
|
|
net (fo=1, routed) 0.000 9.846 u_cpu/u_csr/write_buffer_way[1]_i_18_n_0
|
|
SLICE_X50Y46 r u_cpu/u_csr/write_buffer_way_reg[1]_i_11/S[0]
|
|
SLICE_X50Y46 CARRY4 (Prop_carry4_S[0]_CO[3])
|
|
0.532 10.378 r u_cpu/u_csr/write_buffer_way_reg[1]_i_11/CO[3]
|
|
net (fo=1, routed) 0.000 10.378 u_cpu/u_csr/write_buffer_way_reg[1]_i_11_n_0
|
|
SLICE_X50Y47 r u_cpu/u_csr/write_buffer_way_reg[1]_i_9/CI
|
|
SLICE_X50Y47 CARRY4 (Prop_carry4_CI_CO[1])
|
|
0.157 10.535 r u_cpu/u_csr/write_buffer_way_reg[1]_i_9/CO[1]
|
|
net (fo=2, routed) 0.791 11.326 u_cpu/wb_stage/CO[0]
|
|
SLICE_X46Y39 r u_cpu/wb_stage/write_buffer_way[1]_i_5/I1
|
|
SLICE_X46Y39 LUT6 (Prop_lut6_I1_O) 0.329 11.655 f u_cpu/wb_stage/write_buffer_way[1]_i_5/O
|
|
net (fo=7, routed) 0.762 12.417 u_cpu/addr_trans/tlb_entry/sc_cancel_req
|
|
SLICE_X46Y35 f u_cpu/addr_trans/tlb_entry/main_state[0]_i_3/I1
|
|
SLICE_X46Y35 LUT3 (Prop_lut3_I1_O) 0.124 12.541 f u_cpu/addr_trans/tlb_entry/main_state[0]_i_3/O
|
|
net (fo=3, routed) 0.719 13.260 u_cpu/dcache/main_state_reg[0]_2
|
|
SLICE_X43Y31 f u_cpu/dcache/ds_to_es_bus_r[235]_i_10/I3
|
|
SLICE_X43Y31 LUT6 (Prop_lut6_I3_O) 0.124 13.384 f u_cpu/dcache/ds_to_es_bus_r[235]_i_10/O
|
|
net (fo=3, routed) 0.415 13.799 u_cpu/mem_stage/data_data_ok
|
|
SLICE_X43Y30 f u_cpu/mem_stage/flush_inst_req_buffer[1]_i_15/I0
|
|
SLICE_X43Y30 LUT3 (Prop_lut3_I0_O) 0.124 13.923 f u_cpu/mem_stage/flush_inst_req_buffer[1]_i_15/O
|
|
net (fo=2, routed) 0.833 14.756 u_cpu/mem_stage/es_to_ms_bus_r_reg[70]_1
|
|
SLICE_X48Y30 f u_cpu/mem_stage/flush_inst_req_buffer[1]_i_14/I0
|
|
SLICE_X48Y30 LUT6 (Prop_lut6_I0_O) 0.124 14.880 f u_cpu/mem_stage/flush_inst_req_buffer[1]_i_14/O
|
|
net (fo=1, routed) 0.651 15.532 u_cpu/mem_stage/ms_ready_go
|
|
SLICE_X48Y25 f u_cpu/mem_stage/flush_inst_req_buffer[1]_i_13/I4
|
|
SLICE_X48Y25 LUT6 (Prop_lut6_I4_O) 0.124 15.656 f u_cpu/mem_stage/flush_inst_req_buffer[1]_i_13/O
|
|
net (fo=3, routed) 0.483 16.139 u_cpu/id_stage/flush_inst_req_buffer[31]_i_6
|
|
SLICE_X50Y25 f u_cpu/id_stage/flush_inst_req_buffer[1]_i_9/I1
|
|
SLICE_X50Y25 LUT6 (Prop_lut6_I1_O) 0.124 16.263 f u_cpu/id_stage/flush_inst_req_buffer[1]_i_9/O
|
|
net (fo=32, routed) 0.531 16.794 u_cpu/if_stage/nextpc5
|
|
SLICE_X51Y27 f u_cpu/if_stage/fetch_pc_r[6]_i_4/I2
|
|
SLICE_X51Y27 LUT6 (Prop_lut6_I2_O) 0.124 16.918 r u_cpu/if_stage/fetch_pc_r[6]_i_4/O
|
|
net (fo=1, routed) 3.059 19.977 u_cpu/if_stage/fetch_pc_r[6]_i_4_n_0
|
|
SLICE_X114Y28 r u_cpu/if_stage/fetch_pc_r[6]_i_2/I2
|
|
SLICE_X114Y28 LUT6 (Prop_lut6_I2_O) 0.124 20.101 r u_cpu/if_stage/fetch_pc_r[6]_i_2/O
|
|
net (fo=1, routed) 0.441 20.542 u_cpu/if_stage/fetch_pc_r[6]_i_2_n_0
|
|
SLICE_X114Y25 r u_cpu/if_stage/fetch_pc_r[6]_i_1/I2
|
|
SLICE_X114Y25 LUT6 (Prop_lut6_I2_O) 0.124 20.666 r u_cpu/if_stage/fetch_pc_r[6]_i_1/O
|
|
net (fo=6, routed) 3.249 23.915 u_cpu/icache/tagv_ram_way[1].u/mem_reg_reg_2[2]
|
|
SLICE_X49Y33 r u_cpu/icache/tagv_ram_way[1].u/mem_reg_reg_i_8/I4
|
|
SLICE_X49Y33 LUT5 (Prop_lut5_I4_O) 0.124 24.039 r u_cpu/icache/tagv_ram_way[1].u/mem_reg_reg_i_8/O
|
|
net (fo=16, routed) 1.410 25.450 u_cpu/icache/data_ram_way[0].data_ram_bank[0].u/ADDRBWRADDR[2]
|
|
RAMB18_X2Y4 RAMB18E1 r u_cpu/icache/data_ram_way[0].data_ram_bank[0].u/mem_reg_reg/ADDRBWRADDR[7]
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock cpu_clk rise edge) 30.323 30.323 r
|
|
clock source latency -5.674 24.648
|
|
propagated clock network latency
|
|
3.779 28.427
|
|
clock pessimism -0.418 28.009
|
|
clock uncertainty -0.074 27.935
|
|
RAMB18_X2Y4 RAMB18E1 (Setup_ramb18e1_CLKBWRCLK_ADDRBWRADDR[7])
|
|
-0.566 27.369 u_cpu/icache/data_ram_way[0].data_ram_bank[0].u/mem_reg_reg
|
|
-------------------------------------------------------------------
|
|
required time 27.369
|
|
arrival time -25.450
|
|
-------------------------------------------------------------------
|
|
slack 1.920
|
|
|
|
Slack (MET) : 1.920ns (required time - arrival time)
|
|
Source: u_cpu/addr_trans/data_vaddr_buffer_reg[14]/C
|
|
(rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns})
|
|
Destination: u_cpu/icache/data_ram_way[0].data_ram_bank[0].u/mem_reg_reg/ADDRBWRADDR[7]
|
|
(rising edge-triggered cell RAMB18E1 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns})
|
|
Path Group: cpu_clk
|
|
Path Type: Setup (Max at Slow Process Corner)
|
|
Requirement: 30.323ns (cpu_clk rise@30.323ns - cpu_clk rise@0.000ns)
|
|
Data Path Delay: 27.674ns (logic 5.333ns (19.271%) route 22.341ns (80.729%))
|
|
Logic Levels: 26 (CARRY4=4 LUT3=2 LUT4=1 LUT5=2 LUT6=15 MUXF7=1 MUXF8=1)
|
|
Clock Path Skew: -0.089ns (DCD - SCD + CPR)
|
|
Destination Clock Delay (DCD): -1.895ns = ( 28.427 - 30.323 )
|
|
Source Clock Delay (SCD): -2.225ns
|
|
Clock Pessimism Removal (CPR): -0.418ns
|
|
Clock Uncertainty: 0.074ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Discrete Jitter (DJ): 0.130ns
|
|
Phase Error (PE): 0.000ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock cpu_clk rise edge) 0.000 0.000 r
|
|
clock source latency -6.275 -6.275
|
|
propagated clock network latency
|
|
4.051 -2.225
|
|
SLICE_X35Y35 FDRE 0.000 -2.225 r u_cpu/addr_trans/data_vaddr_buffer_reg[14]/C
|
|
SLICE_X35Y35 FDRE (Prop_fdre_C_Q) 0.456 -1.769 r u_cpu/addr_trans/data_vaddr_buffer_reg[14]/Q
|
|
net (fo=33, routed) 1.442 -0.326 u_cpu/addr_trans/tlb_entry/data_vaddr_buffer[2]
|
|
SLICE_X42Y40 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_226/I5
|
|
SLICE_X42Y40 LUT6 (Prop_lut6_I5_O) 0.124 -0.202 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_226/O
|
|
net (fo=1, routed) 0.000 -0.202 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_226_n_0
|
|
SLICE_X42Y40 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_111/S[0]
|
|
SLICE_X42Y40 CARRY4 (Prop_carry4_S[0]_CO[3])
|
|
0.513 0.311 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_111/CO[3]
|
|
net (fo=1, routed) 0.000 0.311 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_111_n_0
|
|
SLICE_X42Y41 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_32/CI
|
|
SLICE_X42Y41 CARRY4 (Prop_carry4_CI_CO[2])
|
|
0.229 0.540 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_32/CO[2]
|
|
net (fo=1, routed) 1.009 1.549 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_32_n_1
|
|
SLICE_X40Y47 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_9/I1
|
|
SLICE_X40Y47 LUT6 (Prop_lut6_I1_O) 0.310 1.859 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_9/O
|
|
net (fo=2, routed) 0.635 2.494 u_cpu/addr_trans/tlb_entry/match1[28]
|
|
SLICE_X38Y47 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/I2
|
|
SLICE_X38Y47 LUT4 (Prop_lut4_I2_O) 0.124 2.618 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/O
|
|
net (fo=2, routed) 0.667 3.285 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2_n_0
|
|
SLICE_X39Y47 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/I0
|
|
SLICE_X39Y47 LUT5 (Prop_lut5_I0_O) 0.124 3.409 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/O
|
|
net (fo=2, routed) 1.103 4.512 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2_n_0
|
|
SLICE_X38Y50 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/I0
|
|
SLICE_X38Y50 LUT6 (Prop_lut6_I0_O) 0.124 4.636 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/O
|
|
net (fo=89, routed) 1.162 5.797 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus[8]
|
|
SLICE_X42Y51 r u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_38__0/S
|
|
SLICE_X42Y51 MUXF7 (Prop_muxf7_S_O) 0.292 6.089 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_38__0/O
|
|
net (fo=1, routed) 0.000 6.089 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_38__0_n_0
|
|
SLICE_X42Y51 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_16__0/I1
|
|
SLICE_X42Y51 MUXF8 (Prop_muxf8_I1_O) 0.088 6.177 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_16__0/O
|
|
net (fo=1, routed) 0.957 7.134 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_16__0_n_0
|
|
SLICE_X42Y50 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7/I0
|
|
SLICE_X42Y50 LUT6 (Prop_lut6_I0_O) 0.319 7.453 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7/O
|
|
net (fo=1, routed) 0.435 7.888 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7_n_0
|
|
SLICE_X44Y50 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0/I5
|
|
SLICE_X44Y50 LUT6 (Prop_lut6_I5_O) 0.124 8.012 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0/O
|
|
net (fo=10, routed) 0.740 8.753 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0_n_0
|
|
SLICE_X44Y50 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[5]_i_1__0/I3
|
|
SLICE_X44Y50 LUT6 (Prop_lut6_I3_O) 0.124 8.877 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[5]_i_1__0/O
|
|
net (fo=6, routed) 0.845 9.722 u_cpu/u_csr/ms_to_ws_bus[13]
|
|
SLICE_X50Y46 f u_cpu/u_csr/write_buffer_way[1]_i_18/I3
|
|
SLICE_X50Y46 LUT6 (Prop_lut6_I3_O) 0.124 9.846 r u_cpu/u_csr/write_buffer_way[1]_i_18/O
|
|
net (fo=1, routed) 0.000 9.846 u_cpu/u_csr/write_buffer_way[1]_i_18_n_0
|
|
SLICE_X50Y46 r u_cpu/u_csr/write_buffer_way_reg[1]_i_11/S[0]
|
|
SLICE_X50Y46 CARRY4 (Prop_carry4_S[0]_CO[3])
|
|
0.532 10.378 r u_cpu/u_csr/write_buffer_way_reg[1]_i_11/CO[3]
|
|
net (fo=1, routed) 0.000 10.378 u_cpu/u_csr/write_buffer_way_reg[1]_i_11_n_0
|
|
SLICE_X50Y47 r u_cpu/u_csr/write_buffer_way_reg[1]_i_9/CI
|
|
SLICE_X50Y47 CARRY4 (Prop_carry4_CI_CO[1])
|
|
0.157 10.535 r u_cpu/u_csr/write_buffer_way_reg[1]_i_9/CO[1]
|
|
net (fo=2, routed) 0.791 11.326 u_cpu/wb_stage/CO[0]
|
|
SLICE_X46Y39 r u_cpu/wb_stage/write_buffer_way[1]_i_5/I1
|
|
SLICE_X46Y39 LUT6 (Prop_lut6_I1_O) 0.329 11.655 f u_cpu/wb_stage/write_buffer_way[1]_i_5/O
|
|
net (fo=7, routed) 0.762 12.417 u_cpu/addr_trans/tlb_entry/sc_cancel_req
|
|
SLICE_X46Y35 f u_cpu/addr_trans/tlb_entry/main_state[0]_i_3/I1
|
|
SLICE_X46Y35 LUT3 (Prop_lut3_I1_O) 0.124 12.541 f u_cpu/addr_trans/tlb_entry/main_state[0]_i_3/O
|
|
net (fo=3, routed) 0.719 13.260 u_cpu/dcache/main_state_reg[0]_2
|
|
SLICE_X43Y31 f u_cpu/dcache/ds_to_es_bus_r[235]_i_10/I3
|
|
SLICE_X43Y31 LUT6 (Prop_lut6_I3_O) 0.124 13.384 f u_cpu/dcache/ds_to_es_bus_r[235]_i_10/O
|
|
net (fo=3, routed) 0.415 13.799 u_cpu/mem_stage/data_data_ok
|
|
SLICE_X43Y30 f u_cpu/mem_stage/flush_inst_req_buffer[1]_i_15/I0
|
|
SLICE_X43Y30 LUT3 (Prop_lut3_I0_O) 0.124 13.923 f u_cpu/mem_stage/flush_inst_req_buffer[1]_i_15/O
|
|
net (fo=2, routed) 0.833 14.756 u_cpu/mem_stage/es_to_ms_bus_r_reg[70]_1
|
|
SLICE_X48Y30 f u_cpu/mem_stage/flush_inst_req_buffer[1]_i_14/I0
|
|
SLICE_X48Y30 LUT6 (Prop_lut6_I0_O) 0.124 14.880 f u_cpu/mem_stage/flush_inst_req_buffer[1]_i_14/O
|
|
net (fo=1, routed) 0.651 15.532 u_cpu/mem_stage/ms_ready_go
|
|
SLICE_X48Y25 f u_cpu/mem_stage/flush_inst_req_buffer[1]_i_13/I4
|
|
SLICE_X48Y25 LUT6 (Prop_lut6_I4_O) 0.124 15.656 f u_cpu/mem_stage/flush_inst_req_buffer[1]_i_13/O
|
|
net (fo=3, routed) 0.483 16.139 u_cpu/id_stage/flush_inst_req_buffer[31]_i_6
|
|
SLICE_X50Y25 f u_cpu/id_stage/flush_inst_req_buffer[1]_i_9/I1
|
|
SLICE_X50Y25 LUT6 (Prop_lut6_I1_O) 0.124 16.263 f u_cpu/id_stage/flush_inst_req_buffer[1]_i_9/O
|
|
net (fo=32, routed) 0.531 16.794 u_cpu/if_stage/nextpc5
|
|
SLICE_X51Y27 f u_cpu/if_stage/fetch_pc_r[6]_i_4/I2
|
|
SLICE_X51Y27 LUT6 (Prop_lut6_I2_O) 0.124 16.918 r u_cpu/if_stage/fetch_pc_r[6]_i_4/O
|
|
net (fo=1, routed) 3.059 19.977 u_cpu/if_stage/fetch_pc_r[6]_i_4_n_0
|
|
SLICE_X114Y28 r u_cpu/if_stage/fetch_pc_r[6]_i_2/I2
|
|
SLICE_X114Y28 LUT6 (Prop_lut6_I2_O) 0.124 20.101 r u_cpu/if_stage/fetch_pc_r[6]_i_2/O
|
|
net (fo=1, routed) 0.441 20.542 u_cpu/if_stage/fetch_pc_r[6]_i_2_n_0
|
|
SLICE_X114Y25 r u_cpu/if_stage/fetch_pc_r[6]_i_1/I2
|
|
SLICE_X114Y25 LUT6 (Prop_lut6_I2_O) 0.124 20.666 r u_cpu/if_stage/fetch_pc_r[6]_i_1/O
|
|
net (fo=6, routed) 3.249 23.915 u_cpu/icache/tagv_ram_way[1].u/mem_reg_reg_2[2]
|
|
SLICE_X49Y33 r u_cpu/icache/tagv_ram_way[1].u/mem_reg_reg_i_8/I4
|
|
SLICE_X49Y33 LUT5 (Prop_lut5_I4_O) 0.124 24.039 r u_cpu/icache/tagv_ram_way[1].u/mem_reg_reg_i_8/O
|
|
net (fo=16, routed) 1.410 25.450 u_cpu/icache/data_ram_way[0].data_ram_bank[0].u/ADDRBWRADDR[2]
|
|
RAMB18_X2Y4 RAMB18E1 r u_cpu/icache/data_ram_way[0].data_ram_bank[0].u/mem_reg_reg/ADDRBWRADDR[7]
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock cpu_clk rise edge) 30.323 30.323 r
|
|
clock source latency -5.674 24.648
|
|
propagated clock network latency
|
|
3.779 28.427
|
|
clock pessimism -0.418 28.009
|
|
clock uncertainty -0.074 27.935
|
|
RAMB18_X2Y4 RAMB18E1 (Setup_ramb18e1_CLKBWRCLK_ADDRBWRADDR[7])
|
|
-0.566 27.369 u_cpu/icache/data_ram_way[0].data_ram_bank[0].u/mem_reg_reg
|
|
-------------------------------------------------------------------
|
|
required time 27.369
|
|
arrival time -25.450
|
|
-------------------------------------------------------------------
|
|
slack 1.920
|
|
|
|
Slack (MET) : 1.920ns (required time - arrival time)
|
|
Source: u_cpu/addr_trans/data_vaddr_buffer_reg[14]/C
|
|
(rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns})
|
|
Destination: u_cpu/icache/data_ram_way[0].data_ram_bank[0].u/mem_reg_reg/ADDRBWRADDR[7]
|
|
(rising edge-triggered cell RAMB18E1 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns})
|
|
Path Group: cpu_clk
|
|
Path Type: Setup (Max at Slow Process Corner)
|
|
Requirement: 30.323ns (cpu_clk rise@30.323ns - cpu_clk rise@0.000ns)
|
|
Data Path Delay: 27.674ns (logic 5.333ns (19.271%) route 22.341ns (80.729%))
|
|
Logic Levels: 26 (CARRY4=4 LUT3=2 LUT4=1 LUT5=2 LUT6=15 MUXF7=1 MUXF8=1)
|
|
Clock Path Skew: -0.089ns (DCD - SCD + CPR)
|
|
Destination Clock Delay (DCD): -1.895ns = ( 28.427 - 30.323 )
|
|
Source Clock Delay (SCD): -2.225ns
|
|
Clock Pessimism Removal (CPR): -0.418ns
|
|
Clock Uncertainty: 0.074ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Discrete Jitter (DJ): 0.130ns
|
|
Phase Error (PE): 0.000ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock cpu_clk rise edge) 0.000 0.000 r
|
|
clock source latency -6.275 -6.275
|
|
propagated clock network latency
|
|
4.051 -2.225
|
|
SLICE_X35Y35 FDRE 0.000 -2.225 r u_cpu/addr_trans/data_vaddr_buffer_reg[14]/C
|
|
SLICE_X35Y35 FDRE (Prop_fdre_C_Q) 0.456 -1.769 r u_cpu/addr_trans/data_vaddr_buffer_reg[14]/Q
|
|
net (fo=33, routed) 1.442 -0.326 u_cpu/addr_trans/tlb_entry/data_vaddr_buffer[2]
|
|
SLICE_X42Y40 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_226/I5
|
|
SLICE_X42Y40 LUT6 (Prop_lut6_I5_O) 0.124 -0.202 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_226/O
|
|
net (fo=1, routed) 0.000 -0.202 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_226_n_0
|
|
SLICE_X42Y40 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_111/S[0]
|
|
SLICE_X42Y40 CARRY4 (Prop_carry4_S[0]_CO[3])
|
|
0.513 0.311 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_111/CO[3]
|
|
net (fo=1, routed) 0.000 0.311 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_111_n_0
|
|
SLICE_X42Y41 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_32/CI
|
|
SLICE_X42Y41 CARRY4 (Prop_carry4_CI_CO[2])
|
|
0.229 0.540 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_32/CO[2]
|
|
net (fo=1, routed) 1.009 1.549 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_32_n_1
|
|
SLICE_X40Y47 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_9/I1
|
|
SLICE_X40Y47 LUT6 (Prop_lut6_I1_O) 0.310 1.859 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_9/O
|
|
net (fo=2, routed) 0.635 2.494 u_cpu/addr_trans/tlb_entry/match1[28]
|
|
SLICE_X38Y47 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/I2
|
|
SLICE_X38Y47 LUT4 (Prop_lut4_I2_O) 0.124 2.618 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/O
|
|
net (fo=2, routed) 0.667 3.285 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2_n_0
|
|
SLICE_X39Y47 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/I0
|
|
SLICE_X39Y47 LUT5 (Prop_lut5_I0_O) 0.124 3.409 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/O
|
|
net (fo=2, routed) 1.103 4.512 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2_n_0
|
|
SLICE_X38Y50 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/I0
|
|
SLICE_X38Y50 LUT6 (Prop_lut6_I0_O) 0.124 4.636 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/O
|
|
net (fo=89, routed) 1.162 5.797 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus[8]
|
|
SLICE_X42Y51 r u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_38__0/S
|
|
SLICE_X42Y51 MUXF7 (Prop_muxf7_S_O) 0.292 6.089 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_38__0/O
|
|
net (fo=1, routed) 0.000 6.089 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_38__0_n_0
|
|
SLICE_X42Y51 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_16__0/I1
|
|
SLICE_X42Y51 MUXF8 (Prop_muxf8_I1_O) 0.088 6.177 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_16__0/O
|
|
net (fo=1, routed) 0.957 7.134 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_16__0_n_0
|
|
SLICE_X42Y50 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7/I0
|
|
SLICE_X42Y50 LUT6 (Prop_lut6_I0_O) 0.319 7.453 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7/O
|
|
net (fo=1, routed) 0.435 7.888 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7_n_0
|
|
SLICE_X44Y50 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0/I5
|
|
SLICE_X44Y50 LUT6 (Prop_lut6_I5_O) 0.124 8.012 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0/O
|
|
net (fo=10, routed) 0.740 8.753 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0_n_0
|
|
SLICE_X44Y50 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[5]_i_1__0/I3
|
|
SLICE_X44Y50 LUT6 (Prop_lut6_I3_O) 0.124 8.877 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[5]_i_1__0/O
|
|
net (fo=6, routed) 0.845 9.722 u_cpu/u_csr/ms_to_ws_bus[13]
|
|
SLICE_X50Y46 r u_cpu/u_csr/write_buffer_way[1]_i_18/I3
|
|
SLICE_X50Y46 LUT6 (Prop_lut6_I3_O) 0.124 9.846 f u_cpu/u_csr/write_buffer_way[1]_i_18/O
|
|
net (fo=1, routed) 0.000 9.846 u_cpu/u_csr/write_buffer_way[1]_i_18_n_0
|
|
SLICE_X50Y46 f u_cpu/u_csr/write_buffer_way_reg[1]_i_11/S[0]
|
|
SLICE_X50Y46 CARRY4 (Prop_carry4_S[0]_CO[3])
|
|
0.532 10.378 r u_cpu/u_csr/write_buffer_way_reg[1]_i_11/CO[3]
|
|
net (fo=1, routed) 0.000 10.378 u_cpu/u_csr/write_buffer_way_reg[1]_i_11_n_0
|
|
SLICE_X50Y47 r u_cpu/u_csr/write_buffer_way_reg[1]_i_9/CI
|
|
SLICE_X50Y47 CARRY4 (Prop_carry4_CI_CO[1])
|
|
0.157 10.535 r u_cpu/u_csr/write_buffer_way_reg[1]_i_9/CO[1]
|
|
net (fo=2, routed) 0.791 11.326 u_cpu/wb_stage/CO[0]
|
|
SLICE_X46Y39 r u_cpu/wb_stage/write_buffer_way[1]_i_5/I1
|
|
SLICE_X46Y39 LUT6 (Prop_lut6_I1_O) 0.329 11.655 f u_cpu/wb_stage/write_buffer_way[1]_i_5/O
|
|
net (fo=7, routed) 0.762 12.417 u_cpu/addr_trans/tlb_entry/sc_cancel_req
|
|
SLICE_X46Y35 f u_cpu/addr_trans/tlb_entry/main_state[0]_i_3/I1
|
|
SLICE_X46Y35 LUT3 (Prop_lut3_I1_O) 0.124 12.541 f u_cpu/addr_trans/tlb_entry/main_state[0]_i_3/O
|
|
net (fo=3, routed) 0.719 13.260 u_cpu/dcache/main_state_reg[0]_2
|
|
SLICE_X43Y31 f u_cpu/dcache/ds_to_es_bus_r[235]_i_10/I3
|
|
SLICE_X43Y31 LUT6 (Prop_lut6_I3_O) 0.124 13.384 f u_cpu/dcache/ds_to_es_bus_r[235]_i_10/O
|
|
net (fo=3, routed) 0.415 13.799 u_cpu/mem_stage/data_data_ok
|
|
SLICE_X43Y30 f u_cpu/mem_stage/flush_inst_req_buffer[1]_i_15/I0
|
|
SLICE_X43Y30 LUT3 (Prop_lut3_I0_O) 0.124 13.923 f u_cpu/mem_stage/flush_inst_req_buffer[1]_i_15/O
|
|
net (fo=2, routed) 0.833 14.756 u_cpu/mem_stage/es_to_ms_bus_r_reg[70]_1
|
|
SLICE_X48Y30 f u_cpu/mem_stage/flush_inst_req_buffer[1]_i_14/I0
|
|
SLICE_X48Y30 LUT6 (Prop_lut6_I0_O) 0.124 14.880 f u_cpu/mem_stage/flush_inst_req_buffer[1]_i_14/O
|
|
net (fo=1, routed) 0.651 15.532 u_cpu/mem_stage/ms_ready_go
|
|
SLICE_X48Y25 f u_cpu/mem_stage/flush_inst_req_buffer[1]_i_13/I4
|
|
SLICE_X48Y25 LUT6 (Prop_lut6_I4_O) 0.124 15.656 f u_cpu/mem_stage/flush_inst_req_buffer[1]_i_13/O
|
|
net (fo=3, routed) 0.483 16.139 u_cpu/id_stage/flush_inst_req_buffer[31]_i_6
|
|
SLICE_X50Y25 f u_cpu/id_stage/flush_inst_req_buffer[1]_i_9/I1
|
|
SLICE_X50Y25 LUT6 (Prop_lut6_I1_O) 0.124 16.263 f u_cpu/id_stage/flush_inst_req_buffer[1]_i_9/O
|
|
net (fo=32, routed) 0.531 16.794 u_cpu/if_stage/nextpc5
|
|
SLICE_X51Y27 f u_cpu/if_stage/fetch_pc_r[6]_i_4/I2
|
|
SLICE_X51Y27 LUT6 (Prop_lut6_I2_O) 0.124 16.918 r u_cpu/if_stage/fetch_pc_r[6]_i_4/O
|
|
net (fo=1, routed) 3.059 19.977 u_cpu/if_stage/fetch_pc_r[6]_i_4_n_0
|
|
SLICE_X114Y28 r u_cpu/if_stage/fetch_pc_r[6]_i_2/I2
|
|
SLICE_X114Y28 LUT6 (Prop_lut6_I2_O) 0.124 20.101 r u_cpu/if_stage/fetch_pc_r[6]_i_2/O
|
|
net (fo=1, routed) 0.441 20.542 u_cpu/if_stage/fetch_pc_r[6]_i_2_n_0
|
|
SLICE_X114Y25 r u_cpu/if_stage/fetch_pc_r[6]_i_1/I2
|
|
SLICE_X114Y25 LUT6 (Prop_lut6_I2_O) 0.124 20.666 r u_cpu/if_stage/fetch_pc_r[6]_i_1/O
|
|
net (fo=6, routed) 3.249 23.915 u_cpu/icache/tagv_ram_way[1].u/mem_reg_reg_2[2]
|
|
SLICE_X49Y33 r u_cpu/icache/tagv_ram_way[1].u/mem_reg_reg_i_8/I4
|
|
SLICE_X49Y33 LUT5 (Prop_lut5_I4_O) 0.124 24.039 r u_cpu/icache/tagv_ram_way[1].u/mem_reg_reg_i_8/O
|
|
net (fo=16, routed) 1.410 25.450 u_cpu/icache/data_ram_way[0].data_ram_bank[0].u/ADDRBWRADDR[2]
|
|
RAMB18_X2Y4 RAMB18E1 r u_cpu/icache/data_ram_way[0].data_ram_bank[0].u/mem_reg_reg/ADDRBWRADDR[7]
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock cpu_clk rise edge) 30.323 30.323 r
|
|
clock source latency -5.674 24.648
|
|
propagated clock network latency
|
|
3.779 28.427
|
|
clock pessimism -0.418 28.009
|
|
clock uncertainty -0.074 27.935
|
|
RAMB18_X2Y4 RAMB18E1 (Setup_ramb18e1_CLKBWRCLK_ADDRBWRADDR[7])
|
|
-0.566 27.369 u_cpu/icache/data_ram_way[0].data_ram_bank[0].u/mem_reg_reg
|
|
-------------------------------------------------------------------
|
|
required time 27.369
|
|
arrival time -25.450
|
|
-------------------------------------------------------------------
|
|
slack 1.920
|
|
|
|
Slack (MET) : 1.920ns (required time - arrival time)
|
|
Source: u_cpu/addr_trans/data_vaddr_buffer_reg[14]/C
|
|
(rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns})
|
|
Destination: u_cpu/icache/data_ram_way[0].data_ram_bank[0].u/mem_reg_reg/ADDRBWRADDR[7]
|
|
(rising edge-triggered cell RAMB18E1 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns})
|
|
Path Group: cpu_clk
|
|
Path Type: Setup (Max at Slow Process Corner)
|
|
Requirement: 30.323ns (cpu_clk rise@30.323ns - cpu_clk rise@0.000ns)
|
|
Data Path Delay: 27.674ns (logic 5.333ns (19.271%) route 22.341ns (80.729%))
|
|
Logic Levels: 26 (CARRY4=4 LUT3=2 LUT4=1 LUT5=2 LUT6=15 MUXF7=1 MUXF8=1)
|
|
Clock Path Skew: -0.089ns (DCD - SCD + CPR)
|
|
Destination Clock Delay (DCD): -1.895ns = ( 28.427 - 30.323 )
|
|
Source Clock Delay (SCD): -2.225ns
|
|
Clock Pessimism Removal (CPR): -0.418ns
|
|
Clock Uncertainty: 0.074ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Discrete Jitter (DJ): 0.130ns
|
|
Phase Error (PE): 0.000ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock cpu_clk rise edge) 0.000 0.000 r
|
|
clock source latency -6.275 -6.275
|
|
propagated clock network latency
|
|
4.051 -2.225
|
|
SLICE_X35Y35 FDRE 0.000 -2.225 r u_cpu/addr_trans/data_vaddr_buffer_reg[14]/C
|
|
SLICE_X35Y35 FDRE (Prop_fdre_C_Q) 0.456 -1.769 r u_cpu/addr_trans/data_vaddr_buffer_reg[14]/Q
|
|
net (fo=33, routed) 1.442 -0.326 u_cpu/addr_trans/tlb_entry/data_vaddr_buffer[2]
|
|
SLICE_X42Y40 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_226/I5
|
|
SLICE_X42Y40 LUT6 (Prop_lut6_I5_O) 0.124 -0.202 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_226/O
|
|
net (fo=1, routed) 0.000 -0.202 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_226_n_0
|
|
SLICE_X42Y40 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_111/S[0]
|
|
SLICE_X42Y40 CARRY4 (Prop_carry4_S[0]_CO[3])
|
|
0.513 0.311 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_111/CO[3]
|
|
net (fo=1, routed) 0.000 0.311 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_111_n_0
|
|
SLICE_X42Y41 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_32/CI
|
|
SLICE_X42Y41 CARRY4 (Prop_carry4_CI_CO[2])
|
|
0.229 0.540 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_32/CO[2]
|
|
net (fo=1, routed) 1.009 1.549 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_32_n_1
|
|
SLICE_X40Y47 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_9/I1
|
|
SLICE_X40Y47 LUT6 (Prop_lut6_I1_O) 0.310 1.859 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_9/O
|
|
net (fo=2, routed) 0.635 2.494 u_cpu/addr_trans/tlb_entry/match1[28]
|
|
SLICE_X38Y47 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/I2
|
|
SLICE_X38Y47 LUT4 (Prop_lut4_I2_O) 0.124 2.618 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/O
|
|
net (fo=2, routed) 0.667 3.285 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2_n_0
|
|
SLICE_X39Y47 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/I0
|
|
SLICE_X39Y47 LUT5 (Prop_lut5_I0_O) 0.124 3.409 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/O
|
|
net (fo=2, routed) 1.103 4.512 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2_n_0
|
|
SLICE_X38Y50 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/I0
|
|
SLICE_X38Y50 LUT6 (Prop_lut6_I0_O) 0.124 4.636 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/O
|
|
net (fo=89, routed) 1.162 5.797 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus[8]
|
|
SLICE_X42Y51 r u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_38__0/S
|
|
SLICE_X42Y51 MUXF7 (Prop_muxf7_S_O) 0.292 6.089 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_38__0/O
|
|
net (fo=1, routed) 0.000 6.089 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_38__0_n_0
|
|
SLICE_X42Y51 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_16__0/I1
|
|
SLICE_X42Y51 MUXF8 (Prop_muxf8_I1_O) 0.088 6.177 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_16__0/O
|
|
net (fo=1, routed) 0.957 7.134 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_16__0_n_0
|
|
SLICE_X42Y50 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7/I0
|
|
SLICE_X42Y50 LUT6 (Prop_lut6_I0_O) 0.319 7.453 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7/O
|
|
net (fo=1, routed) 0.435 7.888 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7_n_0
|
|
SLICE_X44Y50 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0/I5
|
|
SLICE_X44Y50 LUT6 (Prop_lut6_I5_O) 0.124 8.012 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0/O
|
|
net (fo=10, routed) 0.740 8.753 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0_n_0
|
|
SLICE_X44Y50 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[5]_i_1__0/I3
|
|
SLICE_X44Y50 LUT6 (Prop_lut6_I3_O) 0.124 8.877 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[5]_i_1__0/O
|
|
net (fo=6, routed) 0.845 9.722 u_cpu/u_csr/ms_to_ws_bus[13]
|
|
SLICE_X50Y46 f u_cpu/u_csr/write_buffer_way[1]_i_18/I3
|
|
SLICE_X50Y46 LUT6 (Prop_lut6_I3_O) 0.124 9.846 f u_cpu/u_csr/write_buffer_way[1]_i_18/O
|
|
net (fo=1, routed) 0.000 9.846 u_cpu/u_csr/write_buffer_way[1]_i_18_n_0
|
|
SLICE_X50Y46 f u_cpu/u_csr/write_buffer_way_reg[1]_i_11/S[0]
|
|
SLICE_X50Y46 CARRY4 (Prop_carry4_S[0]_CO[3])
|
|
0.532 10.378 r u_cpu/u_csr/write_buffer_way_reg[1]_i_11/CO[3]
|
|
net (fo=1, routed) 0.000 10.378 u_cpu/u_csr/write_buffer_way_reg[1]_i_11_n_0
|
|
SLICE_X50Y47 r u_cpu/u_csr/write_buffer_way_reg[1]_i_9/CI
|
|
SLICE_X50Y47 CARRY4 (Prop_carry4_CI_CO[1])
|
|
0.157 10.535 r u_cpu/u_csr/write_buffer_way_reg[1]_i_9/CO[1]
|
|
net (fo=2, routed) 0.791 11.326 u_cpu/wb_stage/CO[0]
|
|
SLICE_X46Y39 r u_cpu/wb_stage/write_buffer_way[1]_i_5/I1
|
|
SLICE_X46Y39 LUT6 (Prop_lut6_I1_O) 0.329 11.655 f u_cpu/wb_stage/write_buffer_way[1]_i_5/O
|
|
net (fo=7, routed) 0.762 12.417 u_cpu/addr_trans/tlb_entry/sc_cancel_req
|
|
SLICE_X46Y35 f u_cpu/addr_trans/tlb_entry/main_state[0]_i_3/I1
|
|
SLICE_X46Y35 LUT3 (Prop_lut3_I1_O) 0.124 12.541 f u_cpu/addr_trans/tlb_entry/main_state[0]_i_3/O
|
|
net (fo=3, routed) 0.719 13.260 u_cpu/dcache/main_state_reg[0]_2
|
|
SLICE_X43Y31 f u_cpu/dcache/ds_to_es_bus_r[235]_i_10/I3
|
|
SLICE_X43Y31 LUT6 (Prop_lut6_I3_O) 0.124 13.384 f u_cpu/dcache/ds_to_es_bus_r[235]_i_10/O
|
|
net (fo=3, routed) 0.415 13.799 u_cpu/mem_stage/data_data_ok
|
|
SLICE_X43Y30 f u_cpu/mem_stage/flush_inst_req_buffer[1]_i_15/I0
|
|
SLICE_X43Y30 LUT3 (Prop_lut3_I0_O) 0.124 13.923 f u_cpu/mem_stage/flush_inst_req_buffer[1]_i_15/O
|
|
net (fo=2, routed) 0.833 14.756 u_cpu/mem_stage/es_to_ms_bus_r_reg[70]_1
|
|
SLICE_X48Y30 f u_cpu/mem_stage/flush_inst_req_buffer[1]_i_14/I0
|
|
SLICE_X48Y30 LUT6 (Prop_lut6_I0_O) 0.124 14.880 f u_cpu/mem_stage/flush_inst_req_buffer[1]_i_14/O
|
|
net (fo=1, routed) 0.651 15.532 u_cpu/mem_stage/ms_ready_go
|
|
SLICE_X48Y25 f u_cpu/mem_stage/flush_inst_req_buffer[1]_i_13/I4
|
|
SLICE_X48Y25 LUT6 (Prop_lut6_I4_O) 0.124 15.656 f u_cpu/mem_stage/flush_inst_req_buffer[1]_i_13/O
|
|
net (fo=3, routed) 0.483 16.139 u_cpu/id_stage/flush_inst_req_buffer[31]_i_6
|
|
SLICE_X50Y25 f u_cpu/id_stage/flush_inst_req_buffer[1]_i_9/I1
|
|
SLICE_X50Y25 LUT6 (Prop_lut6_I1_O) 0.124 16.263 f u_cpu/id_stage/flush_inst_req_buffer[1]_i_9/O
|
|
net (fo=32, routed) 0.531 16.794 u_cpu/if_stage/nextpc5
|
|
SLICE_X51Y27 f u_cpu/if_stage/fetch_pc_r[6]_i_4/I2
|
|
SLICE_X51Y27 LUT6 (Prop_lut6_I2_O) 0.124 16.918 r u_cpu/if_stage/fetch_pc_r[6]_i_4/O
|
|
net (fo=1, routed) 3.059 19.977 u_cpu/if_stage/fetch_pc_r[6]_i_4_n_0
|
|
SLICE_X114Y28 r u_cpu/if_stage/fetch_pc_r[6]_i_2/I2
|
|
SLICE_X114Y28 LUT6 (Prop_lut6_I2_O) 0.124 20.101 r u_cpu/if_stage/fetch_pc_r[6]_i_2/O
|
|
net (fo=1, routed) 0.441 20.542 u_cpu/if_stage/fetch_pc_r[6]_i_2_n_0
|
|
SLICE_X114Y25 r u_cpu/if_stage/fetch_pc_r[6]_i_1/I2
|
|
SLICE_X114Y25 LUT6 (Prop_lut6_I2_O) 0.124 20.666 r u_cpu/if_stage/fetch_pc_r[6]_i_1/O
|
|
net (fo=6, routed) 3.249 23.915 u_cpu/icache/tagv_ram_way[1].u/mem_reg_reg_2[2]
|
|
SLICE_X49Y33 r u_cpu/icache/tagv_ram_way[1].u/mem_reg_reg_i_8/I4
|
|
SLICE_X49Y33 LUT5 (Prop_lut5_I4_O) 0.124 24.039 r u_cpu/icache/tagv_ram_way[1].u/mem_reg_reg_i_8/O
|
|
net (fo=16, routed) 1.410 25.450 u_cpu/icache/data_ram_way[0].data_ram_bank[0].u/ADDRBWRADDR[2]
|
|
RAMB18_X2Y4 RAMB18E1 r u_cpu/icache/data_ram_way[0].data_ram_bank[0].u/mem_reg_reg/ADDRBWRADDR[7]
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock cpu_clk rise edge) 30.323 30.323 r
|
|
clock source latency -5.674 24.648
|
|
propagated clock network latency
|
|
3.779 28.427
|
|
clock pessimism -0.418 28.009
|
|
clock uncertainty -0.074 27.935
|
|
RAMB18_X2Y4 RAMB18E1 (Setup_ramb18e1_CLKBWRCLK_ADDRBWRADDR[7])
|
|
-0.566 27.369 u_cpu/icache/data_ram_way[0].data_ram_bank[0].u/mem_reg_reg
|
|
-------------------------------------------------------------------
|
|
required time 27.369
|
|
arrival time -25.450
|
|
-------------------------------------------------------------------
|
|
slack 1.920
|
|
|
|
Slack (MET) : 1.920ns (required time - arrival time)
|
|
Source: u_cpu/addr_trans/data_vaddr_buffer_reg[14]/C
|
|
(rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns})
|
|
Destination: u_cpu/icache/data_ram_way[1].data_ram_bank[2].u/mem_reg_reg/ADDRBWRADDR[7]
|
|
(rising edge-triggered cell RAMB18E1 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns})
|
|
Path Group: cpu_clk
|
|
Path Type: Setup (Max at Slow Process Corner)
|
|
Requirement: 30.323ns (cpu_clk rise@30.323ns - cpu_clk rise@0.000ns)
|
|
Data Path Delay: 27.674ns (logic 5.333ns (19.271%) route 22.341ns (80.729%))
|
|
Logic Levels: 26 (CARRY4=4 LUT3=2 LUT4=1 LUT5=2 LUT6=15 MUXF7=1 MUXF8=1)
|
|
Clock Path Skew: -0.089ns (DCD - SCD + CPR)
|
|
Destination Clock Delay (DCD): -1.895ns = ( 28.427 - 30.323 )
|
|
Source Clock Delay (SCD): -2.225ns
|
|
Clock Pessimism Removal (CPR): -0.418ns
|
|
Clock Uncertainty: 0.074ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Discrete Jitter (DJ): 0.130ns
|
|
Phase Error (PE): 0.000ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock cpu_clk rise edge) 0.000 0.000 r
|
|
clock source latency -6.275 -6.275
|
|
propagated clock network latency
|
|
4.051 -2.225
|
|
SLICE_X35Y35 FDRE 0.000 -2.225 r u_cpu/addr_trans/data_vaddr_buffer_reg[14]/C
|
|
SLICE_X35Y35 FDRE (Prop_fdre_C_Q) 0.456 -1.769 r u_cpu/addr_trans/data_vaddr_buffer_reg[14]/Q
|
|
net (fo=33, routed) 1.442 -0.326 u_cpu/addr_trans/tlb_entry/data_vaddr_buffer[2]
|
|
SLICE_X42Y40 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_226/I5
|
|
SLICE_X42Y40 LUT6 (Prop_lut6_I5_O) 0.124 -0.202 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_226/O
|
|
net (fo=1, routed) 0.000 -0.202 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_226_n_0
|
|
SLICE_X42Y40 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_111/S[0]
|
|
SLICE_X42Y40 CARRY4 (Prop_carry4_S[0]_CO[3])
|
|
0.513 0.311 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_111/CO[3]
|
|
net (fo=1, routed) 0.000 0.311 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_111_n_0
|
|
SLICE_X42Y41 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_32/CI
|
|
SLICE_X42Y41 CARRY4 (Prop_carry4_CI_CO[2])
|
|
0.229 0.540 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_32/CO[2]
|
|
net (fo=1, routed) 1.009 1.549 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_32_n_1
|
|
SLICE_X40Y47 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_9/I1
|
|
SLICE_X40Y47 LUT6 (Prop_lut6_I1_O) 0.310 1.859 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_9/O
|
|
net (fo=2, routed) 0.635 2.494 u_cpu/addr_trans/tlb_entry/match1[28]
|
|
SLICE_X38Y47 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/I2
|
|
SLICE_X38Y47 LUT4 (Prop_lut4_I2_O) 0.124 2.618 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/O
|
|
net (fo=2, routed) 0.667 3.285 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2_n_0
|
|
SLICE_X39Y47 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/I0
|
|
SLICE_X39Y47 LUT5 (Prop_lut5_I0_O) 0.124 3.409 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/O
|
|
net (fo=2, routed) 1.103 4.512 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2_n_0
|
|
SLICE_X38Y50 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/I0
|
|
SLICE_X38Y50 LUT6 (Prop_lut6_I0_O) 0.124 4.636 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/O
|
|
net (fo=89, routed) 1.162 5.797 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus[8]
|
|
SLICE_X42Y51 r u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_38__0/S
|
|
SLICE_X42Y51 MUXF7 (Prop_muxf7_S_O) 0.292 6.089 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_38__0/O
|
|
net (fo=1, routed) 0.000 6.089 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_38__0_n_0
|
|
SLICE_X42Y51 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_16__0/I1
|
|
SLICE_X42Y51 MUXF8 (Prop_muxf8_I1_O) 0.088 6.177 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_16__0/O
|
|
net (fo=1, routed) 0.957 7.134 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_16__0_n_0
|
|
SLICE_X42Y50 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7/I0
|
|
SLICE_X42Y50 LUT6 (Prop_lut6_I0_O) 0.319 7.453 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7/O
|
|
net (fo=1, routed) 0.435 7.888 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7_n_0
|
|
SLICE_X44Y50 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0/I5
|
|
SLICE_X44Y50 LUT6 (Prop_lut6_I5_O) 0.124 8.012 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0/O
|
|
net (fo=10, routed) 0.740 8.753 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0_n_0
|
|
SLICE_X44Y50 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[5]_i_1__0/I3
|
|
SLICE_X44Y50 LUT6 (Prop_lut6_I3_O) 0.124 8.877 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[5]_i_1__0/O
|
|
net (fo=6, routed) 0.845 9.722 u_cpu/u_csr/ms_to_ws_bus[13]
|
|
SLICE_X50Y46 r u_cpu/u_csr/write_buffer_way[1]_i_18/I3
|
|
SLICE_X50Y46 LUT6 (Prop_lut6_I3_O) 0.124 9.846 r u_cpu/u_csr/write_buffer_way[1]_i_18/O
|
|
net (fo=1, routed) 0.000 9.846 u_cpu/u_csr/write_buffer_way[1]_i_18_n_0
|
|
SLICE_X50Y46 r u_cpu/u_csr/write_buffer_way_reg[1]_i_11/S[0]
|
|
SLICE_X50Y46 CARRY4 (Prop_carry4_S[0]_CO[3])
|
|
0.532 10.378 r u_cpu/u_csr/write_buffer_way_reg[1]_i_11/CO[3]
|
|
net (fo=1, routed) 0.000 10.378 u_cpu/u_csr/write_buffer_way_reg[1]_i_11_n_0
|
|
SLICE_X50Y47 r u_cpu/u_csr/write_buffer_way_reg[1]_i_9/CI
|
|
SLICE_X50Y47 CARRY4 (Prop_carry4_CI_CO[1])
|
|
0.157 10.535 f u_cpu/u_csr/write_buffer_way_reg[1]_i_9/CO[1]
|
|
net (fo=2, routed) 0.791 11.326 u_cpu/wb_stage/CO[0]
|
|
SLICE_X46Y39 f u_cpu/wb_stage/write_buffer_way[1]_i_5/I1
|
|
SLICE_X46Y39 LUT6 (Prop_lut6_I1_O) 0.329 11.655 r u_cpu/wb_stage/write_buffer_way[1]_i_5/O
|
|
net (fo=7, routed) 0.762 12.417 u_cpu/addr_trans/tlb_entry/sc_cancel_req
|
|
SLICE_X46Y35 r u_cpu/addr_trans/tlb_entry/main_state[0]_i_3/I1
|
|
SLICE_X46Y35 LUT3 (Prop_lut3_I1_O) 0.124 12.541 r u_cpu/addr_trans/tlb_entry/main_state[0]_i_3/O
|
|
net (fo=3, routed) 0.719 13.260 u_cpu/dcache/main_state_reg[0]_2
|
|
SLICE_X43Y31 r u_cpu/dcache/ds_to_es_bus_r[235]_i_10/I3
|
|
SLICE_X43Y31 LUT6 (Prop_lut6_I3_O) 0.124 13.384 r u_cpu/dcache/ds_to_es_bus_r[235]_i_10/O
|
|
net (fo=3, routed) 0.415 13.799 u_cpu/mem_stage/data_data_ok
|
|
SLICE_X43Y30 r u_cpu/mem_stage/flush_inst_req_buffer[1]_i_15/I0
|
|
SLICE_X43Y30 LUT3 (Prop_lut3_I0_O) 0.124 13.923 r u_cpu/mem_stage/flush_inst_req_buffer[1]_i_15/O
|
|
net (fo=2, routed) 0.833 14.756 u_cpu/mem_stage/es_to_ms_bus_r_reg[70]_1
|
|
SLICE_X48Y30 r u_cpu/mem_stage/flush_inst_req_buffer[1]_i_14/I0
|
|
SLICE_X48Y30 LUT6 (Prop_lut6_I0_O) 0.124 14.880 r u_cpu/mem_stage/flush_inst_req_buffer[1]_i_14/O
|
|
net (fo=1, routed) 0.651 15.532 u_cpu/mem_stage/ms_ready_go
|
|
SLICE_X48Y25 r u_cpu/mem_stage/flush_inst_req_buffer[1]_i_13/I4
|
|
SLICE_X48Y25 LUT6 (Prop_lut6_I4_O) 0.124 15.656 r u_cpu/mem_stage/flush_inst_req_buffer[1]_i_13/O
|
|
net (fo=3, routed) 0.483 16.139 u_cpu/id_stage/flush_inst_req_buffer[31]_i_6
|
|
SLICE_X50Y25 r u_cpu/id_stage/flush_inst_req_buffer[1]_i_9/I1
|
|
SLICE_X50Y25 LUT6 (Prop_lut6_I1_O) 0.124 16.263 r u_cpu/id_stage/flush_inst_req_buffer[1]_i_9/O
|
|
net (fo=32, routed) 0.531 16.794 u_cpu/if_stage/nextpc5
|
|
SLICE_X51Y27 r u_cpu/if_stage/fetch_pc_r[6]_i_4/I2
|
|
SLICE_X51Y27 LUT6 (Prop_lut6_I2_O) 0.124 16.918 r u_cpu/if_stage/fetch_pc_r[6]_i_4/O
|
|
net (fo=1, routed) 3.059 19.977 u_cpu/if_stage/fetch_pc_r[6]_i_4_n_0
|
|
SLICE_X114Y28 r u_cpu/if_stage/fetch_pc_r[6]_i_2/I2
|
|
SLICE_X114Y28 LUT6 (Prop_lut6_I2_O) 0.124 20.101 r u_cpu/if_stage/fetch_pc_r[6]_i_2/O
|
|
net (fo=1, routed) 0.441 20.542 u_cpu/if_stage/fetch_pc_r[6]_i_2_n_0
|
|
SLICE_X114Y25 r u_cpu/if_stage/fetch_pc_r[6]_i_1/I2
|
|
SLICE_X114Y25 LUT6 (Prop_lut6_I2_O) 0.124 20.666 r u_cpu/if_stage/fetch_pc_r[6]_i_1/O
|
|
net (fo=6, routed) 3.249 23.915 u_cpu/icache/tagv_ram_way[1].u/mem_reg_reg_2[2]
|
|
SLICE_X49Y33 r u_cpu/icache/tagv_ram_way[1].u/mem_reg_reg_i_8/I4
|
|
SLICE_X49Y33 LUT5 (Prop_lut5_I4_O) 0.124 24.039 r u_cpu/icache/tagv_ram_way[1].u/mem_reg_reg_i_8/O
|
|
net (fo=16, routed) 1.410 25.450 u_cpu/icache/data_ram_way[1].data_ram_bank[2].u/ADDRBWRADDR[2]
|
|
RAMB18_X2Y5 RAMB18E1 r u_cpu/icache/data_ram_way[1].data_ram_bank[2].u/mem_reg_reg/ADDRBWRADDR[7]
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock cpu_clk rise edge) 30.323 30.323 r
|
|
clock source latency -5.674 24.648
|
|
propagated clock network latency
|
|
3.779 28.427
|
|
clock pessimism -0.418 28.009
|
|
clock uncertainty -0.074 27.935
|
|
RAMB18_X2Y5 RAMB18E1 (Setup_ramb18e1_CLKBWRCLK_ADDRBWRADDR[7])
|
|
-0.566 27.369 u_cpu/icache/data_ram_way[1].data_ram_bank[2].u/mem_reg_reg
|
|
-------------------------------------------------------------------
|
|
required time 27.369
|
|
arrival time -25.450
|
|
-------------------------------------------------------------------
|
|
slack 1.920
|
|
|
|
Slack (MET) : 1.920ns (required time - arrival time)
|
|
Source: u_cpu/addr_trans/data_vaddr_buffer_reg[14]/C
|
|
(rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns})
|
|
Destination: u_cpu/icache/data_ram_way[1].data_ram_bank[2].u/mem_reg_reg/ADDRBWRADDR[7]
|
|
(rising edge-triggered cell RAMB18E1 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns})
|
|
Path Group: cpu_clk
|
|
Path Type: Setup (Max at Slow Process Corner)
|
|
Requirement: 30.323ns (cpu_clk rise@30.323ns - cpu_clk rise@0.000ns)
|
|
Data Path Delay: 27.674ns (logic 5.333ns (19.271%) route 22.341ns (80.729%))
|
|
Logic Levels: 26 (CARRY4=4 LUT3=2 LUT4=1 LUT5=2 LUT6=15 MUXF7=1 MUXF8=1)
|
|
Clock Path Skew: -0.089ns (DCD - SCD + CPR)
|
|
Destination Clock Delay (DCD): -1.895ns = ( 28.427 - 30.323 )
|
|
Source Clock Delay (SCD): -2.225ns
|
|
Clock Pessimism Removal (CPR): -0.418ns
|
|
Clock Uncertainty: 0.074ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Discrete Jitter (DJ): 0.130ns
|
|
Phase Error (PE): 0.000ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock cpu_clk rise edge) 0.000 0.000 r
|
|
clock source latency -6.275 -6.275
|
|
propagated clock network latency
|
|
4.051 -2.225
|
|
SLICE_X35Y35 FDRE 0.000 -2.225 r u_cpu/addr_trans/data_vaddr_buffer_reg[14]/C
|
|
SLICE_X35Y35 FDRE (Prop_fdre_C_Q) 0.456 -1.769 r u_cpu/addr_trans/data_vaddr_buffer_reg[14]/Q
|
|
net (fo=33, routed) 1.442 -0.326 u_cpu/addr_trans/tlb_entry/data_vaddr_buffer[2]
|
|
SLICE_X42Y40 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_226/I5
|
|
SLICE_X42Y40 LUT6 (Prop_lut6_I5_O) 0.124 -0.202 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_226/O
|
|
net (fo=1, routed) 0.000 -0.202 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_226_n_0
|
|
SLICE_X42Y40 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_111/S[0]
|
|
SLICE_X42Y40 CARRY4 (Prop_carry4_S[0]_CO[3])
|
|
0.513 0.311 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_111/CO[3]
|
|
net (fo=1, routed) 0.000 0.311 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_111_n_0
|
|
SLICE_X42Y41 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_32/CI
|
|
SLICE_X42Y41 CARRY4 (Prop_carry4_CI_CO[2])
|
|
0.229 0.540 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_32/CO[2]
|
|
net (fo=1, routed) 1.009 1.549 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_32_n_1
|
|
SLICE_X40Y47 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_9/I1
|
|
SLICE_X40Y47 LUT6 (Prop_lut6_I1_O) 0.310 1.859 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_9/O
|
|
net (fo=2, routed) 0.635 2.494 u_cpu/addr_trans/tlb_entry/match1[28]
|
|
SLICE_X38Y47 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/I2
|
|
SLICE_X38Y47 LUT4 (Prop_lut4_I2_O) 0.124 2.618 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/O
|
|
net (fo=2, routed) 0.667 3.285 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2_n_0
|
|
SLICE_X39Y47 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/I0
|
|
SLICE_X39Y47 LUT5 (Prop_lut5_I0_O) 0.124 3.409 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/O
|
|
net (fo=2, routed) 1.103 4.512 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2_n_0
|
|
SLICE_X38Y50 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/I0
|
|
SLICE_X38Y50 LUT6 (Prop_lut6_I0_O) 0.124 4.636 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/O
|
|
net (fo=89, routed) 1.162 5.797 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus[8]
|
|
SLICE_X42Y51 r u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_38__0/S
|
|
SLICE_X42Y51 MUXF7 (Prop_muxf7_S_O) 0.292 6.089 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_38__0/O
|
|
net (fo=1, routed) 0.000 6.089 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_38__0_n_0
|
|
SLICE_X42Y51 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_16__0/I1
|
|
SLICE_X42Y51 MUXF8 (Prop_muxf8_I1_O) 0.088 6.177 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_16__0/O
|
|
net (fo=1, routed) 0.957 7.134 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_16__0_n_0
|
|
SLICE_X42Y50 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7/I0
|
|
SLICE_X42Y50 LUT6 (Prop_lut6_I0_O) 0.319 7.453 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7/O
|
|
net (fo=1, routed) 0.435 7.888 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7_n_0
|
|
SLICE_X44Y50 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0/I5
|
|
SLICE_X44Y50 LUT6 (Prop_lut6_I5_O) 0.124 8.012 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0/O
|
|
net (fo=10, routed) 0.740 8.753 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0_n_0
|
|
SLICE_X44Y50 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[5]_i_1__0/I3
|
|
SLICE_X44Y50 LUT6 (Prop_lut6_I3_O) 0.124 8.877 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[5]_i_1__0/O
|
|
net (fo=6, routed) 0.845 9.722 u_cpu/u_csr/ms_to_ws_bus[13]
|
|
SLICE_X50Y46 f u_cpu/u_csr/write_buffer_way[1]_i_18/I3
|
|
SLICE_X50Y46 LUT6 (Prop_lut6_I3_O) 0.124 9.846 r u_cpu/u_csr/write_buffer_way[1]_i_18/O
|
|
net (fo=1, routed) 0.000 9.846 u_cpu/u_csr/write_buffer_way[1]_i_18_n_0
|
|
SLICE_X50Y46 r u_cpu/u_csr/write_buffer_way_reg[1]_i_11/S[0]
|
|
SLICE_X50Y46 CARRY4 (Prop_carry4_S[0]_CO[3])
|
|
0.532 10.378 r u_cpu/u_csr/write_buffer_way_reg[1]_i_11/CO[3]
|
|
net (fo=1, routed) 0.000 10.378 u_cpu/u_csr/write_buffer_way_reg[1]_i_11_n_0
|
|
SLICE_X50Y47 r u_cpu/u_csr/write_buffer_way_reg[1]_i_9/CI
|
|
SLICE_X50Y47 CARRY4 (Prop_carry4_CI_CO[1])
|
|
0.157 10.535 f u_cpu/u_csr/write_buffer_way_reg[1]_i_9/CO[1]
|
|
net (fo=2, routed) 0.791 11.326 u_cpu/wb_stage/CO[0]
|
|
SLICE_X46Y39 f u_cpu/wb_stage/write_buffer_way[1]_i_5/I1
|
|
SLICE_X46Y39 LUT6 (Prop_lut6_I1_O) 0.329 11.655 r u_cpu/wb_stage/write_buffer_way[1]_i_5/O
|
|
net (fo=7, routed) 0.762 12.417 u_cpu/addr_trans/tlb_entry/sc_cancel_req
|
|
SLICE_X46Y35 r u_cpu/addr_trans/tlb_entry/main_state[0]_i_3/I1
|
|
SLICE_X46Y35 LUT3 (Prop_lut3_I1_O) 0.124 12.541 r u_cpu/addr_trans/tlb_entry/main_state[0]_i_3/O
|
|
net (fo=3, routed) 0.719 13.260 u_cpu/dcache/main_state_reg[0]_2
|
|
SLICE_X43Y31 r u_cpu/dcache/ds_to_es_bus_r[235]_i_10/I3
|
|
SLICE_X43Y31 LUT6 (Prop_lut6_I3_O) 0.124 13.384 r u_cpu/dcache/ds_to_es_bus_r[235]_i_10/O
|
|
net (fo=3, routed) 0.415 13.799 u_cpu/mem_stage/data_data_ok
|
|
SLICE_X43Y30 r u_cpu/mem_stage/flush_inst_req_buffer[1]_i_15/I0
|
|
SLICE_X43Y30 LUT3 (Prop_lut3_I0_O) 0.124 13.923 r u_cpu/mem_stage/flush_inst_req_buffer[1]_i_15/O
|
|
net (fo=2, routed) 0.833 14.756 u_cpu/mem_stage/es_to_ms_bus_r_reg[70]_1
|
|
SLICE_X48Y30 r u_cpu/mem_stage/flush_inst_req_buffer[1]_i_14/I0
|
|
SLICE_X48Y30 LUT6 (Prop_lut6_I0_O) 0.124 14.880 r u_cpu/mem_stage/flush_inst_req_buffer[1]_i_14/O
|
|
net (fo=1, routed) 0.651 15.532 u_cpu/mem_stage/ms_ready_go
|
|
SLICE_X48Y25 r u_cpu/mem_stage/flush_inst_req_buffer[1]_i_13/I4
|
|
SLICE_X48Y25 LUT6 (Prop_lut6_I4_O) 0.124 15.656 r u_cpu/mem_stage/flush_inst_req_buffer[1]_i_13/O
|
|
net (fo=3, routed) 0.483 16.139 u_cpu/id_stage/flush_inst_req_buffer[31]_i_6
|
|
SLICE_X50Y25 r u_cpu/id_stage/flush_inst_req_buffer[1]_i_9/I1
|
|
SLICE_X50Y25 LUT6 (Prop_lut6_I1_O) 0.124 16.263 r u_cpu/id_stage/flush_inst_req_buffer[1]_i_9/O
|
|
net (fo=32, routed) 0.531 16.794 u_cpu/if_stage/nextpc5
|
|
SLICE_X51Y27 r u_cpu/if_stage/fetch_pc_r[6]_i_4/I2
|
|
SLICE_X51Y27 LUT6 (Prop_lut6_I2_O) 0.124 16.918 r u_cpu/if_stage/fetch_pc_r[6]_i_4/O
|
|
net (fo=1, routed) 3.059 19.977 u_cpu/if_stage/fetch_pc_r[6]_i_4_n_0
|
|
SLICE_X114Y28 r u_cpu/if_stage/fetch_pc_r[6]_i_2/I2
|
|
SLICE_X114Y28 LUT6 (Prop_lut6_I2_O) 0.124 20.101 r u_cpu/if_stage/fetch_pc_r[6]_i_2/O
|
|
net (fo=1, routed) 0.441 20.542 u_cpu/if_stage/fetch_pc_r[6]_i_2_n_0
|
|
SLICE_X114Y25 r u_cpu/if_stage/fetch_pc_r[6]_i_1/I2
|
|
SLICE_X114Y25 LUT6 (Prop_lut6_I2_O) 0.124 20.666 r u_cpu/if_stage/fetch_pc_r[6]_i_1/O
|
|
net (fo=6, routed) 3.249 23.915 u_cpu/icache/tagv_ram_way[1].u/mem_reg_reg_2[2]
|
|
SLICE_X49Y33 r u_cpu/icache/tagv_ram_way[1].u/mem_reg_reg_i_8/I4
|
|
SLICE_X49Y33 LUT5 (Prop_lut5_I4_O) 0.124 24.039 r u_cpu/icache/tagv_ram_way[1].u/mem_reg_reg_i_8/O
|
|
net (fo=16, routed) 1.410 25.450 u_cpu/icache/data_ram_way[1].data_ram_bank[2].u/ADDRBWRADDR[2]
|
|
RAMB18_X2Y5 RAMB18E1 r u_cpu/icache/data_ram_way[1].data_ram_bank[2].u/mem_reg_reg/ADDRBWRADDR[7]
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock cpu_clk rise edge) 30.323 30.323 r
|
|
clock source latency -5.674 24.648
|
|
propagated clock network latency
|
|
3.779 28.427
|
|
clock pessimism -0.418 28.009
|
|
clock uncertainty -0.074 27.935
|
|
RAMB18_X2Y5 RAMB18E1 (Setup_ramb18e1_CLKBWRCLK_ADDRBWRADDR[7])
|
|
-0.566 27.369 u_cpu/icache/data_ram_way[1].data_ram_bank[2].u/mem_reg_reg
|
|
-------------------------------------------------------------------
|
|
required time 27.369
|
|
arrival time -25.450
|
|
-------------------------------------------------------------------
|
|
slack 1.920
|
|
|
|
Slack (MET) : 1.920ns (required time - arrival time)
|
|
Source: u_cpu/addr_trans/data_vaddr_buffer_reg[14]/C
|
|
(rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns})
|
|
Destination: u_cpu/icache/data_ram_way[1].data_ram_bank[2].u/mem_reg_reg/ADDRBWRADDR[7]
|
|
(rising edge-triggered cell RAMB18E1 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns})
|
|
Path Group: cpu_clk
|
|
Path Type: Setup (Max at Slow Process Corner)
|
|
Requirement: 30.323ns (cpu_clk rise@30.323ns - cpu_clk rise@0.000ns)
|
|
Data Path Delay: 27.674ns (logic 5.333ns (19.271%) route 22.341ns (80.729%))
|
|
Logic Levels: 26 (CARRY4=4 LUT3=2 LUT4=1 LUT5=2 LUT6=15 MUXF7=1 MUXF8=1)
|
|
Clock Path Skew: -0.089ns (DCD - SCD + CPR)
|
|
Destination Clock Delay (DCD): -1.895ns = ( 28.427 - 30.323 )
|
|
Source Clock Delay (SCD): -2.225ns
|
|
Clock Pessimism Removal (CPR): -0.418ns
|
|
Clock Uncertainty: 0.074ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Discrete Jitter (DJ): 0.130ns
|
|
Phase Error (PE): 0.000ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock cpu_clk rise edge) 0.000 0.000 r
|
|
clock source latency -6.275 -6.275
|
|
propagated clock network latency
|
|
4.051 -2.225
|
|
SLICE_X35Y35 FDRE 0.000 -2.225 r u_cpu/addr_trans/data_vaddr_buffer_reg[14]/C
|
|
SLICE_X35Y35 FDRE (Prop_fdre_C_Q) 0.456 -1.769 r u_cpu/addr_trans/data_vaddr_buffer_reg[14]/Q
|
|
net (fo=33, routed) 1.442 -0.326 u_cpu/addr_trans/tlb_entry/data_vaddr_buffer[2]
|
|
SLICE_X42Y40 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_226/I5
|
|
SLICE_X42Y40 LUT6 (Prop_lut6_I5_O) 0.124 -0.202 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_226/O
|
|
net (fo=1, routed) 0.000 -0.202 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_226_n_0
|
|
SLICE_X42Y40 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_111/S[0]
|
|
SLICE_X42Y40 CARRY4 (Prop_carry4_S[0]_CO[3])
|
|
0.513 0.311 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_111/CO[3]
|
|
net (fo=1, routed) 0.000 0.311 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_111_n_0
|
|
SLICE_X42Y41 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_32/CI
|
|
SLICE_X42Y41 CARRY4 (Prop_carry4_CI_CO[2])
|
|
0.229 0.540 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_32/CO[2]
|
|
net (fo=1, routed) 1.009 1.549 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_32_n_1
|
|
SLICE_X40Y47 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_9/I1
|
|
SLICE_X40Y47 LUT6 (Prop_lut6_I1_O) 0.310 1.859 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_9/O
|
|
net (fo=2, routed) 0.635 2.494 u_cpu/addr_trans/tlb_entry/match1[28]
|
|
SLICE_X38Y47 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/I2
|
|
SLICE_X38Y47 LUT4 (Prop_lut4_I2_O) 0.124 2.618 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/O
|
|
net (fo=2, routed) 0.667 3.285 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2_n_0
|
|
SLICE_X39Y47 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/I0
|
|
SLICE_X39Y47 LUT5 (Prop_lut5_I0_O) 0.124 3.409 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/O
|
|
net (fo=2, routed) 1.103 4.512 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2_n_0
|
|
SLICE_X38Y50 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/I0
|
|
SLICE_X38Y50 LUT6 (Prop_lut6_I0_O) 0.124 4.636 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/O
|
|
net (fo=89, routed) 1.162 5.797 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus[8]
|
|
SLICE_X42Y51 r u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_38__0/S
|
|
SLICE_X42Y51 MUXF7 (Prop_muxf7_S_O) 0.292 6.089 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_38__0/O
|
|
net (fo=1, routed) 0.000 6.089 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_38__0_n_0
|
|
SLICE_X42Y51 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_16__0/I1
|
|
SLICE_X42Y51 MUXF8 (Prop_muxf8_I1_O) 0.088 6.177 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_16__0/O
|
|
net (fo=1, routed) 0.957 7.134 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_16__0_n_0
|
|
SLICE_X42Y50 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7/I0
|
|
SLICE_X42Y50 LUT6 (Prop_lut6_I0_O) 0.319 7.453 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7/O
|
|
net (fo=1, routed) 0.435 7.888 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7_n_0
|
|
SLICE_X44Y50 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0/I5
|
|
SLICE_X44Y50 LUT6 (Prop_lut6_I5_O) 0.124 8.012 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0/O
|
|
net (fo=10, routed) 0.740 8.753 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0_n_0
|
|
SLICE_X44Y50 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[5]_i_1__0/I3
|
|
SLICE_X44Y50 LUT6 (Prop_lut6_I3_O) 0.124 8.877 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[5]_i_1__0/O
|
|
net (fo=6, routed) 0.845 9.722 u_cpu/u_csr/ms_to_ws_bus[13]
|
|
SLICE_X50Y46 r u_cpu/u_csr/write_buffer_way[1]_i_18/I3
|
|
SLICE_X50Y46 LUT6 (Prop_lut6_I3_O) 0.124 9.846 f u_cpu/u_csr/write_buffer_way[1]_i_18/O
|
|
net (fo=1, routed) 0.000 9.846 u_cpu/u_csr/write_buffer_way[1]_i_18_n_0
|
|
SLICE_X50Y46 f u_cpu/u_csr/write_buffer_way_reg[1]_i_11/S[0]
|
|
SLICE_X50Y46 CARRY4 (Prop_carry4_S[0]_CO[3])
|
|
0.532 10.378 r u_cpu/u_csr/write_buffer_way_reg[1]_i_11/CO[3]
|
|
net (fo=1, routed) 0.000 10.378 u_cpu/u_csr/write_buffer_way_reg[1]_i_11_n_0
|
|
SLICE_X50Y47 r u_cpu/u_csr/write_buffer_way_reg[1]_i_9/CI
|
|
SLICE_X50Y47 CARRY4 (Prop_carry4_CI_CO[1])
|
|
0.157 10.535 f u_cpu/u_csr/write_buffer_way_reg[1]_i_9/CO[1]
|
|
net (fo=2, routed) 0.791 11.326 u_cpu/wb_stage/CO[0]
|
|
SLICE_X46Y39 f u_cpu/wb_stage/write_buffer_way[1]_i_5/I1
|
|
SLICE_X46Y39 LUT6 (Prop_lut6_I1_O) 0.329 11.655 r u_cpu/wb_stage/write_buffer_way[1]_i_5/O
|
|
net (fo=7, routed) 0.762 12.417 u_cpu/addr_trans/tlb_entry/sc_cancel_req
|
|
SLICE_X46Y35 r u_cpu/addr_trans/tlb_entry/main_state[0]_i_3/I1
|
|
SLICE_X46Y35 LUT3 (Prop_lut3_I1_O) 0.124 12.541 r u_cpu/addr_trans/tlb_entry/main_state[0]_i_3/O
|
|
net (fo=3, routed) 0.719 13.260 u_cpu/dcache/main_state_reg[0]_2
|
|
SLICE_X43Y31 r u_cpu/dcache/ds_to_es_bus_r[235]_i_10/I3
|
|
SLICE_X43Y31 LUT6 (Prop_lut6_I3_O) 0.124 13.384 r u_cpu/dcache/ds_to_es_bus_r[235]_i_10/O
|
|
net (fo=3, routed) 0.415 13.799 u_cpu/mem_stage/data_data_ok
|
|
SLICE_X43Y30 r u_cpu/mem_stage/flush_inst_req_buffer[1]_i_15/I0
|
|
SLICE_X43Y30 LUT3 (Prop_lut3_I0_O) 0.124 13.923 r u_cpu/mem_stage/flush_inst_req_buffer[1]_i_15/O
|
|
net (fo=2, routed) 0.833 14.756 u_cpu/mem_stage/es_to_ms_bus_r_reg[70]_1
|
|
SLICE_X48Y30 r u_cpu/mem_stage/flush_inst_req_buffer[1]_i_14/I0
|
|
SLICE_X48Y30 LUT6 (Prop_lut6_I0_O) 0.124 14.880 r u_cpu/mem_stage/flush_inst_req_buffer[1]_i_14/O
|
|
net (fo=1, routed) 0.651 15.532 u_cpu/mem_stage/ms_ready_go
|
|
SLICE_X48Y25 r u_cpu/mem_stage/flush_inst_req_buffer[1]_i_13/I4
|
|
SLICE_X48Y25 LUT6 (Prop_lut6_I4_O) 0.124 15.656 r u_cpu/mem_stage/flush_inst_req_buffer[1]_i_13/O
|
|
net (fo=3, routed) 0.483 16.139 u_cpu/id_stage/flush_inst_req_buffer[31]_i_6
|
|
SLICE_X50Y25 r u_cpu/id_stage/flush_inst_req_buffer[1]_i_9/I1
|
|
SLICE_X50Y25 LUT6 (Prop_lut6_I1_O) 0.124 16.263 r u_cpu/id_stage/flush_inst_req_buffer[1]_i_9/O
|
|
net (fo=32, routed) 0.531 16.794 u_cpu/if_stage/nextpc5
|
|
SLICE_X51Y27 r u_cpu/if_stage/fetch_pc_r[6]_i_4/I2
|
|
SLICE_X51Y27 LUT6 (Prop_lut6_I2_O) 0.124 16.918 r u_cpu/if_stage/fetch_pc_r[6]_i_4/O
|
|
net (fo=1, routed) 3.059 19.977 u_cpu/if_stage/fetch_pc_r[6]_i_4_n_0
|
|
SLICE_X114Y28 r u_cpu/if_stage/fetch_pc_r[6]_i_2/I2
|
|
SLICE_X114Y28 LUT6 (Prop_lut6_I2_O) 0.124 20.101 r u_cpu/if_stage/fetch_pc_r[6]_i_2/O
|
|
net (fo=1, routed) 0.441 20.542 u_cpu/if_stage/fetch_pc_r[6]_i_2_n_0
|
|
SLICE_X114Y25 r u_cpu/if_stage/fetch_pc_r[6]_i_1/I2
|
|
SLICE_X114Y25 LUT6 (Prop_lut6_I2_O) 0.124 20.666 r u_cpu/if_stage/fetch_pc_r[6]_i_1/O
|
|
net (fo=6, routed) 3.249 23.915 u_cpu/icache/tagv_ram_way[1].u/mem_reg_reg_2[2]
|
|
SLICE_X49Y33 r u_cpu/icache/tagv_ram_way[1].u/mem_reg_reg_i_8/I4
|
|
SLICE_X49Y33 LUT5 (Prop_lut5_I4_O) 0.124 24.039 r u_cpu/icache/tagv_ram_way[1].u/mem_reg_reg_i_8/O
|
|
net (fo=16, routed) 1.410 25.450 u_cpu/icache/data_ram_way[1].data_ram_bank[2].u/ADDRBWRADDR[2]
|
|
RAMB18_X2Y5 RAMB18E1 r u_cpu/icache/data_ram_way[1].data_ram_bank[2].u/mem_reg_reg/ADDRBWRADDR[7]
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock cpu_clk rise edge) 30.323 30.323 r
|
|
clock source latency -5.674 24.648
|
|
propagated clock network latency
|
|
3.779 28.427
|
|
clock pessimism -0.418 28.009
|
|
clock uncertainty -0.074 27.935
|
|
RAMB18_X2Y5 RAMB18E1 (Setup_ramb18e1_CLKBWRCLK_ADDRBWRADDR[7])
|
|
-0.566 27.369 u_cpu/icache/data_ram_way[1].data_ram_bank[2].u/mem_reg_reg
|
|
-------------------------------------------------------------------
|
|
required time 27.369
|
|
arrival time -25.450
|
|
-------------------------------------------------------------------
|
|
slack 1.920
|
|
|
|
Slack (MET) : 1.920ns (required time - arrival time)
|
|
Source: u_cpu/addr_trans/data_vaddr_buffer_reg[14]/C
|
|
(rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns})
|
|
Destination: u_cpu/icache/data_ram_way[1].data_ram_bank[2].u/mem_reg_reg/ADDRBWRADDR[7]
|
|
(rising edge-triggered cell RAMB18E1 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns})
|
|
Path Group: cpu_clk
|
|
Path Type: Setup (Max at Slow Process Corner)
|
|
Requirement: 30.323ns (cpu_clk rise@30.323ns - cpu_clk rise@0.000ns)
|
|
Data Path Delay: 27.674ns (logic 5.333ns (19.271%) route 22.341ns (80.729%))
|
|
Logic Levels: 26 (CARRY4=4 LUT3=2 LUT4=1 LUT5=2 LUT6=15 MUXF7=1 MUXF8=1)
|
|
Clock Path Skew: -0.089ns (DCD - SCD + CPR)
|
|
Destination Clock Delay (DCD): -1.895ns = ( 28.427 - 30.323 )
|
|
Source Clock Delay (SCD): -2.225ns
|
|
Clock Pessimism Removal (CPR): -0.418ns
|
|
Clock Uncertainty: 0.074ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Discrete Jitter (DJ): 0.130ns
|
|
Phase Error (PE): 0.000ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock cpu_clk rise edge) 0.000 0.000 r
|
|
clock source latency -6.275 -6.275
|
|
propagated clock network latency
|
|
4.051 -2.225
|
|
SLICE_X35Y35 FDRE 0.000 -2.225 r u_cpu/addr_trans/data_vaddr_buffer_reg[14]/C
|
|
SLICE_X35Y35 FDRE (Prop_fdre_C_Q) 0.456 -1.769 r u_cpu/addr_trans/data_vaddr_buffer_reg[14]/Q
|
|
net (fo=33, routed) 1.442 -0.326 u_cpu/addr_trans/tlb_entry/data_vaddr_buffer[2]
|
|
SLICE_X42Y40 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_226/I5
|
|
SLICE_X42Y40 LUT6 (Prop_lut6_I5_O) 0.124 -0.202 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_226/O
|
|
net (fo=1, routed) 0.000 -0.202 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_226_n_0
|
|
SLICE_X42Y40 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_111/S[0]
|
|
SLICE_X42Y40 CARRY4 (Prop_carry4_S[0]_CO[3])
|
|
0.513 0.311 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_111/CO[3]
|
|
net (fo=1, routed) 0.000 0.311 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_111_n_0
|
|
SLICE_X42Y41 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_32/CI
|
|
SLICE_X42Y41 CARRY4 (Prop_carry4_CI_CO[2])
|
|
0.229 0.540 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_32/CO[2]
|
|
net (fo=1, routed) 1.009 1.549 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_32_n_1
|
|
SLICE_X40Y47 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_9/I1
|
|
SLICE_X40Y47 LUT6 (Prop_lut6_I1_O) 0.310 1.859 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_9/O
|
|
net (fo=2, routed) 0.635 2.494 u_cpu/addr_trans/tlb_entry/match1[28]
|
|
SLICE_X38Y47 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/I2
|
|
SLICE_X38Y47 LUT4 (Prop_lut4_I2_O) 0.124 2.618 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/O
|
|
net (fo=2, routed) 0.667 3.285 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2_n_0
|
|
SLICE_X39Y47 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/I0
|
|
SLICE_X39Y47 LUT5 (Prop_lut5_I0_O) 0.124 3.409 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/O
|
|
net (fo=2, routed) 1.103 4.512 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2_n_0
|
|
SLICE_X38Y50 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/I0
|
|
SLICE_X38Y50 LUT6 (Prop_lut6_I0_O) 0.124 4.636 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/O
|
|
net (fo=89, routed) 1.162 5.797 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus[8]
|
|
SLICE_X42Y51 r u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_38__0/S
|
|
SLICE_X42Y51 MUXF7 (Prop_muxf7_S_O) 0.292 6.089 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_38__0/O
|
|
net (fo=1, routed) 0.000 6.089 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_38__0_n_0
|
|
SLICE_X42Y51 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_16__0/I1
|
|
SLICE_X42Y51 MUXF8 (Prop_muxf8_I1_O) 0.088 6.177 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_16__0/O
|
|
net (fo=1, routed) 0.957 7.134 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_16__0_n_0
|
|
SLICE_X42Y50 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7/I0
|
|
SLICE_X42Y50 LUT6 (Prop_lut6_I0_O) 0.319 7.453 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7/O
|
|
net (fo=1, routed) 0.435 7.888 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7_n_0
|
|
SLICE_X44Y50 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0/I5
|
|
SLICE_X44Y50 LUT6 (Prop_lut6_I5_O) 0.124 8.012 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0/O
|
|
net (fo=10, routed) 0.740 8.753 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0_n_0
|
|
SLICE_X44Y50 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[5]_i_1__0/I3
|
|
SLICE_X44Y50 LUT6 (Prop_lut6_I3_O) 0.124 8.877 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[5]_i_1__0/O
|
|
net (fo=6, routed) 0.845 9.722 u_cpu/u_csr/ms_to_ws_bus[13]
|
|
SLICE_X50Y46 f u_cpu/u_csr/write_buffer_way[1]_i_18/I3
|
|
SLICE_X50Y46 LUT6 (Prop_lut6_I3_O) 0.124 9.846 f u_cpu/u_csr/write_buffer_way[1]_i_18/O
|
|
net (fo=1, routed) 0.000 9.846 u_cpu/u_csr/write_buffer_way[1]_i_18_n_0
|
|
SLICE_X50Y46 f u_cpu/u_csr/write_buffer_way_reg[1]_i_11/S[0]
|
|
SLICE_X50Y46 CARRY4 (Prop_carry4_S[0]_CO[3])
|
|
0.532 10.378 r u_cpu/u_csr/write_buffer_way_reg[1]_i_11/CO[3]
|
|
net (fo=1, routed) 0.000 10.378 u_cpu/u_csr/write_buffer_way_reg[1]_i_11_n_0
|
|
SLICE_X50Y47 r u_cpu/u_csr/write_buffer_way_reg[1]_i_9/CI
|
|
SLICE_X50Y47 CARRY4 (Prop_carry4_CI_CO[1])
|
|
0.157 10.535 f u_cpu/u_csr/write_buffer_way_reg[1]_i_9/CO[1]
|
|
net (fo=2, routed) 0.791 11.326 u_cpu/wb_stage/CO[0]
|
|
SLICE_X46Y39 f u_cpu/wb_stage/write_buffer_way[1]_i_5/I1
|
|
SLICE_X46Y39 LUT6 (Prop_lut6_I1_O) 0.329 11.655 r u_cpu/wb_stage/write_buffer_way[1]_i_5/O
|
|
net (fo=7, routed) 0.762 12.417 u_cpu/addr_trans/tlb_entry/sc_cancel_req
|
|
SLICE_X46Y35 r u_cpu/addr_trans/tlb_entry/main_state[0]_i_3/I1
|
|
SLICE_X46Y35 LUT3 (Prop_lut3_I1_O) 0.124 12.541 r u_cpu/addr_trans/tlb_entry/main_state[0]_i_3/O
|
|
net (fo=3, routed) 0.719 13.260 u_cpu/dcache/main_state_reg[0]_2
|
|
SLICE_X43Y31 r u_cpu/dcache/ds_to_es_bus_r[235]_i_10/I3
|
|
SLICE_X43Y31 LUT6 (Prop_lut6_I3_O) 0.124 13.384 r u_cpu/dcache/ds_to_es_bus_r[235]_i_10/O
|
|
net (fo=3, routed) 0.415 13.799 u_cpu/mem_stage/data_data_ok
|
|
SLICE_X43Y30 r u_cpu/mem_stage/flush_inst_req_buffer[1]_i_15/I0
|
|
SLICE_X43Y30 LUT3 (Prop_lut3_I0_O) 0.124 13.923 r u_cpu/mem_stage/flush_inst_req_buffer[1]_i_15/O
|
|
net (fo=2, routed) 0.833 14.756 u_cpu/mem_stage/es_to_ms_bus_r_reg[70]_1
|
|
SLICE_X48Y30 r u_cpu/mem_stage/flush_inst_req_buffer[1]_i_14/I0
|
|
SLICE_X48Y30 LUT6 (Prop_lut6_I0_O) 0.124 14.880 r u_cpu/mem_stage/flush_inst_req_buffer[1]_i_14/O
|
|
net (fo=1, routed) 0.651 15.532 u_cpu/mem_stage/ms_ready_go
|
|
SLICE_X48Y25 r u_cpu/mem_stage/flush_inst_req_buffer[1]_i_13/I4
|
|
SLICE_X48Y25 LUT6 (Prop_lut6_I4_O) 0.124 15.656 r u_cpu/mem_stage/flush_inst_req_buffer[1]_i_13/O
|
|
net (fo=3, routed) 0.483 16.139 u_cpu/id_stage/flush_inst_req_buffer[31]_i_6
|
|
SLICE_X50Y25 r u_cpu/id_stage/flush_inst_req_buffer[1]_i_9/I1
|
|
SLICE_X50Y25 LUT6 (Prop_lut6_I1_O) 0.124 16.263 r u_cpu/id_stage/flush_inst_req_buffer[1]_i_9/O
|
|
net (fo=32, routed) 0.531 16.794 u_cpu/if_stage/nextpc5
|
|
SLICE_X51Y27 r u_cpu/if_stage/fetch_pc_r[6]_i_4/I2
|
|
SLICE_X51Y27 LUT6 (Prop_lut6_I2_O) 0.124 16.918 r u_cpu/if_stage/fetch_pc_r[6]_i_4/O
|
|
net (fo=1, routed) 3.059 19.977 u_cpu/if_stage/fetch_pc_r[6]_i_4_n_0
|
|
SLICE_X114Y28 r u_cpu/if_stage/fetch_pc_r[6]_i_2/I2
|
|
SLICE_X114Y28 LUT6 (Prop_lut6_I2_O) 0.124 20.101 r u_cpu/if_stage/fetch_pc_r[6]_i_2/O
|
|
net (fo=1, routed) 0.441 20.542 u_cpu/if_stage/fetch_pc_r[6]_i_2_n_0
|
|
SLICE_X114Y25 r u_cpu/if_stage/fetch_pc_r[6]_i_1/I2
|
|
SLICE_X114Y25 LUT6 (Prop_lut6_I2_O) 0.124 20.666 r u_cpu/if_stage/fetch_pc_r[6]_i_1/O
|
|
net (fo=6, routed) 3.249 23.915 u_cpu/icache/tagv_ram_way[1].u/mem_reg_reg_2[2]
|
|
SLICE_X49Y33 r u_cpu/icache/tagv_ram_way[1].u/mem_reg_reg_i_8/I4
|
|
SLICE_X49Y33 LUT5 (Prop_lut5_I4_O) 0.124 24.039 r u_cpu/icache/tagv_ram_way[1].u/mem_reg_reg_i_8/O
|
|
net (fo=16, routed) 1.410 25.450 u_cpu/icache/data_ram_way[1].data_ram_bank[2].u/ADDRBWRADDR[2]
|
|
RAMB18_X2Y5 RAMB18E1 r u_cpu/icache/data_ram_way[1].data_ram_bank[2].u/mem_reg_reg/ADDRBWRADDR[7]
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock cpu_clk rise edge) 30.323 30.323 r
|
|
clock source latency -5.674 24.648
|
|
propagated clock network latency
|
|
3.779 28.427
|
|
clock pessimism -0.418 28.009
|
|
clock uncertainty -0.074 27.935
|
|
RAMB18_X2Y5 RAMB18E1 (Setup_ramb18e1_CLKBWRCLK_ADDRBWRADDR[7])
|
|
-0.566 27.369 u_cpu/icache/data_ram_way[1].data_ram_bank[2].u/mem_reg_reg
|
|
-------------------------------------------------------------------
|
|
required time 27.369
|
|
arrival time -25.450
|
|
-------------------------------------------------------------------
|
|
slack 1.920
|
|
|
|
Slack (MET) : 1.920ns (required time - arrival time)
|
|
Source: u_cpu/addr_trans/data_vaddr_buffer_reg[14]/C
|
|
(rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns})
|
|
Destination: u_cpu/icache/data_ram_way[1].data_ram_bank[2].u/mem_reg_reg/ADDRBWRADDR[7]
|
|
(rising edge-triggered cell RAMB18E1 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns})
|
|
Path Group: cpu_clk
|
|
Path Type: Setup (Max at Slow Process Corner)
|
|
Requirement: 30.323ns (cpu_clk rise@30.323ns - cpu_clk rise@0.000ns)
|
|
Data Path Delay: 27.674ns (logic 5.333ns (19.271%) route 22.341ns (80.729%))
|
|
Logic Levels: 26 (CARRY4=4 LUT3=2 LUT4=1 LUT5=2 LUT6=15 MUXF7=1 MUXF8=1)
|
|
Clock Path Skew: -0.089ns (DCD - SCD + CPR)
|
|
Destination Clock Delay (DCD): -1.895ns = ( 28.427 - 30.323 )
|
|
Source Clock Delay (SCD): -2.225ns
|
|
Clock Pessimism Removal (CPR): -0.418ns
|
|
Clock Uncertainty: 0.074ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Discrete Jitter (DJ): 0.130ns
|
|
Phase Error (PE): 0.000ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock cpu_clk rise edge) 0.000 0.000 r
|
|
clock source latency -6.275 -6.275
|
|
propagated clock network latency
|
|
4.051 -2.225
|
|
SLICE_X35Y35 FDRE 0.000 -2.225 r u_cpu/addr_trans/data_vaddr_buffer_reg[14]/C
|
|
SLICE_X35Y35 FDRE (Prop_fdre_C_Q) 0.456 -1.769 r u_cpu/addr_trans/data_vaddr_buffer_reg[14]/Q
|
|
net (fo=33, routed) 1.442 -0.326 u_cpu/addr_trans/tlb_entry/data_vaddr_buffer[2]
|
|
SLICE_X42Y40 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_226/I5
|
|
SLICE_X42Y40 LUT6 (Prop_lut6_I5_O) 0.124 -0.202 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_226/O
|
|
net (fo=1, routed) 0.000 -0.202 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_226_n_0
|
|
SLICE_X42Y40 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_111/S[0]
|
|
SLICE_X42Y40 CARRY4 (Prop_carry4_S[0]_CO[3])
|
|
0.513 0.311 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_111/CO[3]
|
|
net (fo=1, routed) 0.000 0.311 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_111_n_0
|
|
SLICE_X42Y41 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_32/CI
|
|
SLICE_X42Y41 CARRY4 (Prop_carry4_CI_CO[2])
|
|
0.229 0.540 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_32/CO[2]
|
|
net (fo=1, routed) 1.009 1.549 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_32_n_1
|
|
SLICE_X40Y47 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_9/I1
|
|
SLICE_X40Y47 LUT6 (Prop_lut6_I1_O) 0.310 1.859 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_9/O
|
|
net (fo=2, routed) 0.635 2.494 u_cpu/addr_trans/tlb_entry/match1[28]
|
|
SLICE_X38Y47 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/I2
|
|
SLICE_X38Y47 LUT4 (Prop_lut4_I2_O) 0.124 2.618 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/O
|
|
net (fo=2, routed) 0.667 3.285 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2_n_0
|
|
SLICE_X39Y47 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/I0
|
|
SLICE_X39Y47 LUT5 (Prop_lut5_I0_O) 0.124 3.409 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/O
|
|
net (fo=2, routed) 1.103 4.512 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2_n_0
|
|
SLICE_X38Y50 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/I0
|
|
SLICE_X38Y50 LUT6 (Prop_lut6_I0_O) 0.124 4.636 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/O
|
|
net (fo=89, routed) 1.162 5.797 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus[8]
|
|
SLICE_X42Y51 r u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_38__0/S
|
|
SLICE_X42Y51 MUXF7 (Prop_muxf7_S_O) 0.292 6.089 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_38__0/O
|
|
net (fo=1, routed) 0.000 6.089 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_38__0_n_0
|
|
SLICE_X42Y51 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_16__0/I1
|
|
SLICE_X42Y51 MUXF8 (Prop_muxf8_I1_O) 0.088 6.177 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_16__0/O
|
|
net (fo=1, routed) 0.957 7.134 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_16__0_n_0
|
|
SLICE_X42Y50 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7/I0
|
|
SLICE_X42Y50 LUT6 (Prop_lut6_I0_O) 0.319 7.453 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7/O
|
|
net (fo=1, routed) 0.435 7.888 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7_n_0
|
|
SLICE_X44Y50 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0/I5
|
|
SLICE_X44Y50 LUT6 (Prop_lut6_I5_O) 0.124 8.012 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0/O
|
|
net (fo=10, routed) 0.740 8.753 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0_n_0
|
|
SLICE_X44Y50 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[5]_i_1__0/I3
|
|
SLICE_X44Y50 LUT6 (Prop_lut6_I3_O) 0.124 8.877 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[5]_i_1__0/O
|
|
net (fo=6, routed) 0.845 9.722 u_cpu/u_csr/ms_to_ws_bus[13]
|
|
SLICE_X50Y46 r u_cpu/u_csr/write_buffer_way[1]_i_18/I3
|
|
SLICE_X50Y46 LUT6 (Prop_lut6_I3_O) 0.124 9.846 r u_cpu/u_csr/write_buffer_way[1]_i_18/O
|
|
net (fo=1, routed) 0.000 9.846 u_cpu/u_csr/write_buffer_way[1]_i_18_n_0
|
|
SLICE_X50Y46 r u_cpu/u_csr/write_buffer_way_reg[1]_i_11/S[0]
|
|
SLICE_X50Y46 CARRY4 (Prop_carry4_S[0]_CO[3])
|
|
0.532 10.378 f u_cpu/u_csr/write_buffer_way_reg[1]_i_11/CO[3]
|
|
net (fo=1, routed) 0.000 10.378 u_cpu/u_csr/write_buffer_way_reg[1]_i_11_n_0
|
|
SLICE_X50Y47 f u_cpu/u_csr/write_buffer_way_reg[1]_i_9/CI
|
|
SLICE_X50Y47 CARRY4 (Prop_carry4_CI_CO[1])
|
|
0.157 10.535 f u_cpu/u_csr/write_buffer_way_reg[1]_i_9/CO[1]
|
|
net (fo=2, routed) 0.791 11.326 u_cpu/wb_stage/CO[0]
|
|
SLICE_X46Y39 f u_cpu/wb_stage/write_buffer_way[1]_i_5/I1
|
|
SLICE_X46Y39 LUT6 (Prop_lut6_I1_O) 0.329 11.655 r u_cpu/wb_stage/write_buffer_way[1]_i_5/O
|
|
net (fo=7, routed) 0.762 12.417 u_cpu/addr_trans/tlb_entry/sc_cancel_req
|
|
SLICE_X46Y35 r u_cpu/addr_trans/tlb_entry/main_state[0]_i_3/I1
|
|
SLICE_X46Y35 LUT3 (Prop_lut3_I1_O) 0.124 12.541 r u_cpu/addr_trans/tlb_entry/main_state[0]_i_3/O
|
|
net (fo=3, routed) 0.719 13.260 u_cpu/dcache/main_state_reg[0]_2
|
|
SLICE_X43Y31 r u_cpu/dcache/ds_to_es_bus_r[235]_i_10/I3
|
|
SLICE_X43Y31 LUT6 (Prop_lut6_I3_O) 0.124 13.384 r u_cpu/dcache/ds_to_es_bus_r[235]_i_10/O
|
|
net (fo=3, routed) 0.415 13.799 u_cpu/mem_stage/data_data_ok
|
|
SLICE_X43Y30 r u_cpu/mem_stage/flush_inst_req_buffer[1]_i_15/I0
|
|
SLICE_X43Y30 LUT3 (Prop_lut3_I0_O) 0.124 13.923 r u_cpu/mem_stage/flush_inst_req_buffer[1]_i_15/O
|
|
net (fo=2, routed) 0.833 14.756 u_cpu/mem_stage/es_to_ms_bus_r_reg[70]_1
|
|
SLICE_X48Y30 r u_cpu/mem_stage/flush_inst_req_buffer[1]_i_14/I0
|
|
SLICE_X48Y30 LUT6 (Prop_lut6_I0_O) 0.124 14.880 r u_cpu/mem_stage/flush_inst_req_buffer[1]_i_14/O
|
|
net (fo=1, routed) 0.651 15.532 u_cpu/mem_stage/ms_ready_go
|
|
SLICE_X48Y25 r u_cpu/mem_stage/flush_inst_req_buffer[1]_i_13/I4
|
|
SLICE_X48Y25 LUT6 (Prop_lut6_I4_O) 0.124 15.656 r u_cpu/mem_stage/flush_inst_req_buffer[1]_i_13/O
|
|
net (fo=3, routed) 0.483 16.139 u_cpu/id_stage/flush_inst_req_buffer[31]_i_6
|
|
SLICE_X50Y25 r u_cpu/id_stage/flush_inst_req_buffer[1]_i_9/I1
|
|
SLICE_X50Y25 LUT6 (Prop_lut6_I1_O) 0.124 16.263 r u_cpu/id_stage/flush_inst_req_buffer[1]_i_9/O
|
|
net (fo=32, routed) 0.531 16.794 u_cpu/if_stage/nextpc5
|
|
SLICE_X51Y27 r u_cpu/if_stage/fetch_pc_r[6]_i_4/I2
|
|
SLICE_X51Y27 LUT6 (Prop_lut6_I2_O) 0.124 16.918 r u_cpu/if_stage/fetch_pc_r[6]_i_4/O
|
|
net (fo=1, routed) 3.059 19.977 u_cpu/if_stage/fetch_pc_r[6]_i_4_n_0
|
|
SLICE_X114Y28 r u_cpu/if_stage/fetch_pc_r[6]_i_2/I2
|
|
SLICE_X114Y28 LUT6 (Prop_lut6_I2_O) 0.124 20.101 r u_cpu/if_stage/fetch_pc_r[6]_i_2/O
|
|
net (fo=1, routed) 0.441 20.542 u_cpu/if_stage/fetch_pc_r[6]_i_2_n_0
|
|
SLICE_X114Y25 r u_cpu/if_stage/fetch_pc_r[6]_i_1/I2
|
|
SLICE_X114Y25 LUT6 (Prop_lut6_I2_O) 0.124 20.666 r u_cpu/if_stage/fetch_pc_r[6]_i_1/O
|
|
net (fo=6, routed) 3.249 23.915 u_cpu/icache/tagv_ram_way[1].u/mem_reg_reg_2[2]
|
|
SLICE_X49Y33 r u_cpu/icache/tagv_ram_way[1].u/mem_reg_reg_i_8/I4
|
|
SLICE_X49Y33 LUT5 (Prop_lut5_I4_O) 0.124 24.039 r u_cpu/icache/tagv_ram_way[1].u/mem_reg_reg_i_8/O
|
|
net (fo=16, routed) 1.410 25.450 u_cpu/icache/data_ram_way[1].data_ram_bank[2].u/ADDRBWRADDR[2]
|
|
RAMB18_X2Y5 RAMB18E1 r u_cpu/icache/data_ram_way[1].data_ram_bank[2].u/mem_reg_reg/ADDRBWRADDR[7]
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock cpu_clk rise edge) 30.323 30.323 r
|
|
clock source latency -5.674 24.648
|
|
propagated clock network latency
|
|
3.779 28.427
|
|
clock pessimism -0.418 28.009
|
|
clock uncertainty -0.074 27.935
|
|
RAMB18_X2Y5 RAMB18E1 (Setup_ramb18e1_CLKBWRCLK_ADDRBWRADDR[7])
|
|
-0.566 27.369 u_cpu/icache/data_ram_way[1].data_ram_bank[2].u/mem_reg_reg
|
|
-------------------------------------------------------------------
|
|
required time 27.369
|
|
arrival time -25.450
|
|
-------------------------------------------------------------------
|
|
slack 1.920
|
|
|
|
Slack (MET) : 1.920ns (required time - arrival time)
|
|
Source: u_cpu/addr_trans/data_vaddr_buffer_reg[14]/C
|
|
(rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns})
|
|
Destination: u_cpu/icache/data_ram_way[1].data_ram_bank[2].u/mem_reg_reg/ADDRBWRADDR[7]
|
|
(rising edge-triggered cell RAMB18E1 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns})
|
|
Path Group: cpu_clk
|
|
Path Type: Setup (Max at Slow Process Corner)
|
|
Requirement: 30.323ns (cpu_clk rise@30.323ns - cpu_clk rise@0.000ns)
|
|
Data Path Delay: 27.674ns (logic 5.333ns (19.271%) route 22.341ns (80.729%))
|
|
Logic Levels: 26 (CARRY4=4 LUT3=2 LUT4=1 LUT5=2 LUT6=15 MUXF7=1 MUXF8=1)
|
|
Clock Path Skew: -0.089ns (DCD - SCD + CPR)
|
|
Destination Clock Delay (DCD): -1.895ns = ( 28.427 - 30.323 )
|
|
Source Clock Delay (SCD): -2.225ns
|
|
Clock Pessimism Removal (CPR): -0.418ns
|
|
Clock Uncertainty: 0.074ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Discrete Jitter (DJ): 0.130ns
|
|
Phase Error (PE): 0.000ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock cpu_clk rise edge) 0.000 0.000 r
|
|
clock source latency -6.275 -6.275
|
|
propagated clock network latency
|
|
4.051 -2.225
|
|
SLICE_X35Y35 FDRE 0.000 -2.225 r u_cpu/addr_trans/data_vaddr_buffer_reg[14]/C
|
|
SLICE_X35Y35 FDRE (Prop_fdre_C_Q) 0.456 -1.769 r u_cpu/addr_trans/data_vaddr_buffer_reg[14]/Q
|
|
net (fo=33, routed) 1.442 -0.326 u_cpu/addr_trans/tlb_entry/data_vaddr_buffer[2]
|
|
SLICE_X42Y40 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_226/I5
|
|
SLICE_X42Y40 LUT6 (Prop_lut6_I5_O) 0.124 -0.202 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_226/O
|
|
net (fo=1, routed) 0.000 -0.202 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_226_n_0
|
|
SLICE_X42Y40 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_111/S[0]
|
|
SLICE_X42Y40 CARRY4 (Prop_carry4_S[0]_CO[3])
|
|
0.513 0.311 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_111/CO[3]
|
|
net (fo=1, routed) 0.000 0.311 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_111_n_0
|
|
SLICE_X42Y41 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_32/CI
|
|
SLICE_X42Y41 CARRY4 (Prop_carry4_CI_CO[2])
|
|
0.229 0.540 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_32/CO[2]
|
|
net (fo=1, routed) 1.009 1.549 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_32_n_1
|
|
SLICE_X40Y47 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_9/I1
|
|
SLICE_X40Y47 LUT6 (Prop_lut6_I1_O) 0.310 1.859 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_9/O
|
|
net (fo=2, routed) 0.635 2.494 u_cpu/addr_trans/tlb_entry/match1[28]
|
|
SLICE_X38Y47 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/I2
|
|
SLICE_X38Y47 LUT4 (Prop_lut4_I2_O) 0.124 2.618 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/O
|
|
net (fo=2, routed) 0.667 3.285 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2_n_0
|
|
SLICE_X39Y47 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/I0
|
|
SLICE_X39Y47 LUT5 (Prop_lut5_I0_O) 0.124 3.409 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/O
|
|
net (fo=2, routed) 1.103 4.512 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2_n_0
|
|
SLICE_X38Y50 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/I0
|
|
SLICE_X38Y50 LUT6 (Prop_lut6_I0_O) 0.124 4.636 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/O
|
|
net (fo=89, routed) 1.162 5.797 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus[8]
|
|
SLICE_X42Y51 r u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_38__0/S
|
|
SLICE_X42Y51 MUXF7 (Prop_muxf7_S_O) 0.292 6.089 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_38__0/O
|
|
net (fo=1, routed) 0.000 6.089 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_38__0_n_0
|
|
SLICE_X42Y51 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_16__0/I1
|
|
SLICE_X42Y51 MUXF8 (Prop_muxf8_I1_O) 0.088 6.177 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_16__0/O
|
|
net (fo=1, routed) 0.957 7.134 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_16__0_n_0
|
|
SLICE_X42Y50 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7/I0
|
|
SLICE_X42Y50 LUT6 (Prop_lut6_I0_O) 0.319 7.453 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7/O
|
|
net (fo=1, routed) 0.435 7.888 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7_n_0
|
|
SLICE_X44Y50 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0/I5
|
|
SLICE_X44Y50 LUT6 (Prop_lut6_I5_O) 0.124 8.012 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0/O
|
|
net (fo=10, routed) 0.740 8.753 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0_n_0
|
|
SLICE_X44Y50 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[5]_i_1__0/I3
|
|
SLICE_X44Y50 LUT6 (Prop_lut6_I3_O) 0.124 8.877 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[5]_i_1__0/O
|
|
net (fo=6, routed) 0.845 9.722 u_cpu/u_csr/ms_to_ws_bus[13]
|
|
SLICE_X50Y46 f u_cpu/u_csr/write_buffer_way[1]_i_18/I3
|
|
SLICE_X50Y46 LUT6 (Prop_lut6_I3_O) 0.124 9.846 r u_cpu/u_csr/write_buffer_way[1]_i_18/O
|
|
net (fo=1, routed) 0.000 9.846 u_cpu/u_csr/write_buffer_way[1]_i_18_n_0
|
|
SLICE_X50Y46 r u_cpu/u_csr/write_buffer_way_reg[1]_i_11/S[0]
|
|
SLICE_X50Y46 CARRY4 (Prop_carry4_S[0]_CO[3])
|
|
0.532 10.378 f u_cpu/u_csr/write_buffer_way_reg[1]_i_11/CO[3]
|
|
net (fo=1, routed) 0.000 10.378 u_cpu/u_csr/write_buffer_way_reg[1]_i_11_n_0
|
|
SLICE_X50Y47 f u_cpu/u_csr/write_buffer_way_reg[1]_i_9/CI
|
|
SLICE_X50Y47 CARRY4 (Prop_carry4_CI_CO[1])
|
|
0.157 10.535 f u_cpu/u_csr/write_buffer_way_reg[1]_i_9/CO[1]
|
|
net (fo=2, routed) 0.791 11.326 u_cpu/wb_stage/CO[0]
|
|
SLICE_X46Y39 f u_cpu/wb_stage/write_buffer_way[1]_i_5/I1
|
|
SLICE_X46Y39 LUT6 (Prop_lut6_I1_O) 0.329 11.655 r u_cpu/wb_stage/write_buffer_way[1]_i_5/O
|
|
net (fo=7, routed) 0.762 12.417 u_cpu/addr_trans/tlb_entry/sc_cancel_req
|
|
SLICE_X46Y35 r u_cpu/addr_trans/tlb_entry/main_state[0]_i_3/I1
|
|
SLICE_X46Y35 LUT3 (Prop_lut3_I1_O) 0.124 12.541 r u_cpu/addr_trans/tlb_entry/main_state[0]_i_3/O
|
|
net (fo=3, routed) 0.719 13.260 u_cpu/dcache/main_state_reg[0]_2
|
|
SLICE_X43Y31 r u_cpu/dcache/ds_to_es_bus_r[235]_i_10/I3
|
|
SLICE_X43Y31 LUT6 (Prop_lut6_I3_O) 0.124 13.384 r u_cpu/dcache/ds_to_es_bus_r[235]_i_10/O
|
|
net (fo=3, routed) 0.415 13.799 u_cpu/mem_stage/data_data_ok
|
|
SLICE_X43Y30 r u_cpu/mem_stage/flush_inst_req_buffer[1]_i_15/I0
|
|
SLICE_X43Y30 LUT3 (Prop_lut3_I0_O) 0.124 13.923 r u_cpu/mem_stage/flush_inst_req_buffer[1]_i_15/O
|
|
net (fo=2, routed) 0.833 14.756 u_cpu/mem_stage/es_to_ms_bus_r_reg[70]_1
|
|
SLICE_X48Y30 r u_cpu/mem_stage/flush_inst_req_buffer[1]_i_14/I0
|
|
SLICE_X48Y30 LUT6 (Prop_lut6_I0_O) 0.124 14.880 r u_cpu/mem_stage/flush_inst_req_buffer[1]_i_14/O
|
|
net (fo=1, routed) 0.651 15.532 u_cpu/mem_stage/ms_ready_go
|
|
SLICE_X48Y25 r u_cpu/mem_stage/flush_inst_req_buffer[1]_i_13/I4
|
|
SLICE_X48Y25 LUT6 (Prop_lut6_I4_O) 0.124 15.656 r u_cpu/mem_stage/flush_inst_req_buffer[1]_i_13/O
|
|
net (fo=3, routed) 0.483 16.139 u_cpu/id_stage/flush_inst_req_buffer[31]_i_6
|
|
SLICE_X50Y25 r u_cpu/id_stage/flush_inst_req_buffer[1]_i_9/I1
|
|
SLICE_X50Y25 LUT6 (Prop_lut6_I1_O) 0.124 16.263 r u_cpu/id_stage/flush_inst_req_buffer[1]_i_9/O
|
|
net (fo=32, routed) 0.531 16.794 u_cpu/if_stage/nextpc5
|
|
SLICE_X51Y27 r u_cpu/if_stage/fetch_pc_r[6]_i_4/I2
|
|
SLICE_X51Y27 LUT6 (Prop_lut6_I2_O) 0.124 16.918 r u_cpu/if_stage/fetch_pc_r[6]_i_4/O
|
|
net (fo=1, routed) 3.059 19.977 u_cpu/if_stage/fetch_pc_r[6]_i_4_n_0
|
|
SLICE_X114Y28 r u_cpu/if_stage/fetch_pc_r[6]_i_2/I2
|
|
SLICE_X114Y28 LUT6 (Prop_lut6_I2_O) 0.124 20.101 r u_cpu/if_stage/fetch_pc_r[6]_i_2/O
|
|
net (fo=1, routed) 0.441 20.542 u_cpu/if_stage/fetch_pc_r[6]_i_2_n_0
|
|
SLICE_X114Y25 r u_cpu/if_stage/fetch_pc_r[6]_i_1/I2
|
|
SLICE_X114Y25 LUT6 (Prop_lut6_I2_O) 0.124 20.666 r u_cpu/if_stage/fetch_pc_r[6]_i_1/O
|
|
net (fo=6, routed) 3.249 23.915 u_cpu/icache/tagv_ram_way[1].u/mem_reg_reg_2[2]
|
|
SLICE_X49Y33 r u_cpu/icache/tagv_ram_way[1].u/mem_reg_reg_i_8/I4
|
|
SLICE_X49Y33 LUT5 (Prop_lut5_I4_O) 0.124 24.039 r u_cpu/icache/tagv_ram_way[1].u/mem_reg_reg_i_8/O
|
|
net (fo=16, routed) 1.410 25.450 u_cpu/icache/data_ram_way[1].data_ram_bank[2].u/ADDRBWRADDR[2]
|
|
RAMB18_X2Y5 RAMB18E1 r u_cpu/icache/data_ram_way[1].data_ram_bank[2].u/mem_reg_reg/ADDRBWRADDR[7]
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock cpu_clk rise edge) 30.323 30.323 r
|
|
clock source latency -5.674 24.648
|
|
propagated clock network latency
|
|
3.779 28.427
|
|
clock pessimism -0.418 28.009
|
|
clock uncertainty -0.074 27.935
|
|
RAMB18_X2Y5 RAMB18E1 (Setup_ramb18e1_CLKBWRCLK_ADDRBWRADDR[7])
|
|
-0.566 27.369 u_cpu/icache/data_ram_way[1].data_ram_bank[2].u/mem_reg_reg
|
|
-------------------------------------------------------------------
|
|
required time 27.369
|
|
arrival time -25.450
|
|
-------------------------------------------------------------------
|
|
slack 1.920
|
|
|
|
Slack (MET) : 1.920ns (required time - arrival time)
|
|
Source: u_cpu/addr_trans/data_vaddr_buffer_reg[14]/C
|
|
(rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns})
|
|
Destination: u_cpu/icache/data_ram_way[1].data_ram_bank[2].u/mem_reg_reg/ADDRBWRADDR[7]
|
|
(rising edge-triggered cell RAMB18E1 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns})
|
|
Path Group: cpu_clk
|
|
Path Type: Setup (Max at Slow Process Corner)
|
|
Requirement: 30.323ns (cpu_clk rise@30.323ns - cpu_clk rise@0.000ns)
|
|
Data Path Delay: 27.674ns (logic 5.333ns (19.271%) route 22.341ns (80.729%))
|
|
Logic Levels: 26 (CARRY4=4 LUT3=2 LUT4=1 LUT5=2 LUT6=15 MUXF7=1 MUXF8=1)
|
|
Clock Path Skew: -0.089ns (DCD - SCD + CPR)
|
|
Destination Clock Delay (DCD): -1.895ns = ( 28.427 - 30.323 )
|
|
Source Clock Delay (SCD): -2.225ns
|
|
Clock Pessimism Removal (CPR): -0.418ns
|
|
Clock Uncertainty: 0.074ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Discrete Jitter (DJ): 0.130ns
|
|
Phase Error (PE): 0.000ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock cpu_clk rise edge) 0.000 0.000 r
|
|
clock source latency -6.275 -6.275
|
|
propagated clock network latency
|
|
4.051 -2.225
|
|
SLICE_X35Y35 FDRE 0.000 -2.225 r u_cpu/addr_trans/data_vaddr_buffer_reg[14]/C
|
|
SLICE_X35Y35 FDRE (Prop_fdre_C_Q) 0.456 -1.769 r u_cpu/addr_trans/data_vaddr_buffer_reg[14]/Q
|
|
net (fo=33, routed) 1.442 -0.326 u_cpu/addr_trans/tlb_entry/data_vaddr_buffer[2]
|
|
SLICE_X42Y40 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_226/I5
|
|
SLICE_X42Y40 LUT6 (Prop_lut6_I5_O) 0.124 -0.202 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_226/O
|
|
net (fo=1, routed) 0.000 -0.202 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_226_n_0
|
|
SLICE_X42Y40 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_111/S[0]
|
|
SLICE_X42Y40 CARRY4 (Prop_carry4_S[0]_CO[3])
|
|
0.513 0.311 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_111/CO[3]
|
|
net (fo=1, routed) 0.000 0.311 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_111_n_0
|
|
SLICE_X42Y41 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_32/CI
|
|
SLICE_X42Y41 CARRY4 (Prop_carry4_CI_CO[2])
|
|
0.229 0.540 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_32/CO[2]
|
|
net (fo=1, routed) 1.009 1.549 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_32_n_1
|
|
SLICE_X40Y47 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_9/I1
|
|
SLICE_X40Y47 LUT6 (Prop_lut6_I1_O) 0.310 1.859 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_9/O
|
|
net (fo=2, routed) 0.635 2.494 u_cpu/addr_trans/tlb_entry/match1[28]
|
|
SLICE_X38Y47 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/I2
|
|
SLICE_X38Y47 LUT4 (Prop_lut4_I2_O) 0.124 2.618 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/O
|
|
net (fo=2, routed) 0.667 3.285 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2_n_0
|
|
SLICE_X39Y47 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/I0
|
|
SLICE_X39Y47 LUT5 (Prop_lut5_I0_O) 0.124 3.409 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/O
|
|
net (fo=2, routed) 1.103 4.512 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2_n_0
|
|
SLICE_X38Y50 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/I0
|
|
SLICE_X38Y50 LUT6 (Prop_lut6_I0_O) 0.124 4.636 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/O
|
|
net (fo=89, routed) 1.162 5.797 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus[8]
|
|
SLICE_X42Y51 r u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_38__0/S
|
|
SLICE_X42Y51 MUXF7 (Prop_muxf7_S_O) 0.292 6.089 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_38__0/O
|
|
net (fo=1, routed) 0.000 6.089 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_38__0_n_0
|
|
SLICE_X42Y51 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_16__0/I1
|
|
SLICE_X42Y51 MUXF8 (Prop_muxf8_I1_O) 0.088 6.177 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_16__0/O
|
|
net (fo=1, routed) 0.957 7.134 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_16__0_n_0
|
|
SLICE_X42Y50 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7/I0
|
|
SLICE_X42Y50 LUT6 (Prop_lut6_I0_O) 0.319 7.453 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7/O
|
|
net (fo=1, routed) 0.435 7.888 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7_n_0
|
|
SLICE_X44Y50 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0/I5
|
|
SLICE_X44Y50 LUT6 (Prop_lut6_I5_O) 0.124 8.012 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0/O
|
|
net (fo=10, routed) 0.740 8.753 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0_n_0
|
|
SLICE_X44Y50 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[5]_i_1__0/I3
|
|
SLICE_X44Y50 LUT6 (Prop_lut6_I3_O) 0.124 8.877 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[5]_i_1__0/O
|
|
net (fo=6, routed) 0.845 9.722 u_cpu/u_csr/ms_to_ws_bus[13]
|
|
SLICE_X50Y46 r u_cpu/u_csr/write_buffer_way[1]_i_18/I3
|
|
SLICE_X50Y46 LUT6 (Prop_lut6_I3_O) 0.124 9.846 r u_cpu/u_csr/write_buffer_way[1]_i_18/O
|
|
net (fo=1, routed) 0.000 9.846 u_cpu/u_csr/write_buffer_way[1]_i_18_n_0
|
|
SLICE_X50Y46 r u_cpu/u_csr/write_buffer_way_reg[1]_i_11/S[0]
|
|
SLICE_X50Y46 CARRY4 (Prop_carry4_S[0]_CO[3])
|
|
0.532 10.378 r u_cpu/u_csr/write_buffer_way_reg[1]_i_11/CO[3]
|
|
net (fo=1, routed) 0.000 10.378 u_cpu/u_csr/write_buffer_way_reg[1]_i_11_n_0
|
|
SLICE_X50Y47 r u_cpu/u_csr/write_buffer_way_reg[1]_i_9/CI
|
|
SLICE_X50Y47 CARRY4 (Prop_carry4_CI_CO[1])
|
|
0.157 10.535 r u_cpu/u_csr/write_buffer_way_reg[1]_i_9/CO[1]
|
|
net (fo=2, routed) 0.791 11.326 u_cpu/wb_stage/CO[0]
|
|
SLICE_X46Y39 r u_cpu/wb_stage/write_buffer_way[1]_i_5/I1
|
|
SLICE_X46Y39 LUT6 (Prop_lut6_I1_O) 0.329 11.655 f u_cpu/wb_stage/write_buffer_way[1]_i_5/O
|
|
net (fo=7, routed) 0.762 12.417 u_cpu/addr_trans/tlb_entry/sc_cancel_req
|
|
SLICE_X46Y35 f u_cpu/addr_trans/tlb_entry/main_state[0]_i_3/I1
|
|
SLICE_X46Y35 LUT3 (Prop_lut3_I1_O) 0.124 12.541 f u_cpu/addr_trans/tlb_entry/main_state[0]_i_3/O
|
|
net (fo=3, routed) 0.719 13.260 u_cpu/dcache/main_state_reg[0]_2
|
|
SLICE_X43Y31 f u_cpu/dcache/ds_to_es_bus_r[235]_i_10/I3
|
|
SLICE_X43Y31 LUT6 (Prop_lut6_I3_O) 0.124 13.384 f u_cpu/dcache/ds_to_es_bus_r[235]_i_10/O
|
|
net (fo=3, routed) 0.415 13.799 u_cpu/mem_stage/data_data_ok
|
|
SLICE_X43Y30 f u_cpu/mem_stage/flush_inst_req_buffer[1]_i_15/I0
|
|
SLICE_X43Y30 LUT3 (Prop_lut3_I0_O) 0.124 13.923 f u_cpu/mem_stage/flush_inst_req_buffer[1]_i_15/O
|
|
net (fo=2, routed) 0.833 14.756 u_cpu/mem_stage/es_to_ms_bus_r_reg[70]_1
|
|
SLICE_X48Y30 f u_cpu/mem_stage/flush_inst_req_buffer[1]_i_14/I0
|
|
SLICE_X48Y30 LUT6 (Prop_lut6_I0_O) 0.124 14.880 f u_cpu/mem_stage/flush_inst_req_buffer[1]_i_14/O
|
|
net (fo=1, routed) 0.651 15.532 u_cpu/mem_stage/ms_ready_go
|
|
SLICE_X48Y25 f u_cpu/mem_stage/flush_inst_req_buffer[1]_i_13/I4
|
|
SLICE_X48Y25 LUT6 (Prop_lut6_I4_O) 0.124 15.656 f u_cpu/mem_stage/flush_inst_req_buffer[1]_i_13/O
|
|
net (fo=3, routed) 0.483 16.139 u_cpu/id_stage/flush_inst_req_buffer[31]_i_6
|
|
SLICE_X50Y25 f u_cpu/id_stage/flush_inst_req_buffer[1]_i_9/I1
|
|
SLICE_X50Y25 LUT6 (Prop_lut6_I1_O) 0.124 16.263 f u_cpu/id_stage/flush_inst_req_buffer[1]_i_9/O
|
|
net (fo=32, routed) 0.531 16.794 u_cpu/if_stage/nextpc5
|
|
SLICE_X51Y27 f u_cpu/if_stage/fetch_pc_r[6]_i_4/I2
|
|
SLICE_X51Y27 LUT6 (Prop_lut6_I2_O) 0.124 16.918 r u_cpu/if_stage/fetch_pc_r[6]_i_4/O
|
|
net (fo=1, routed) 3.059 19.977 u_cpu/if_stage/fetch_pc_r[6]_i_4_n_0
|
|
SLICE_X114Y28 r u_cpu/if_stage/fetch_pc_r[6]_i_2/I2
|
|
SLICE_X114Y28 LUT6 (Prop_lut6_I2_O) 0.124 20.101 r u_cpu/if_stage/fetch_pc_r[6]_i_2/O
|
|
net (fo=1, routed) 0.441 20.542 u_cpu/if_stage/fetch_pc_r[6]_i_2_n_0
|
|
SLICE_X114Y25 r u_cpu/if_stage/fetch_pc_r[6]_i_1/I2
|
|
SLICE_X114Y25 LUT6 (Prop_lut6_I2_O) 0.124 20.666 r u_cpu/if_stage/fetch_pc_r[6]_i_1/O
|
|
net (fo=6, routed) 3.249 23.915 u_cpu/icache/tagv_ram_way[1].u/mem_reg_reg_2[2]
|
|
SLICE_X49Y33 r u_cpu/icache/tagv_ram_way[1].u/mem_reg_reg_i_8/I4
|
|
SLICE_X49Y33 LUT5 (Prop_lut5_I4_O) 0.124 24.039 r u_cpu/icache/tagv_ram_way[1].u/mem_reg_reg_i_8/O
|
|
net (fo=16, routed) 1.410 25.450 u_cpu/icache/data_ram_way[1].data_ram_bank[2].u/ADDRBWRADDR[2]
|
|
RAMB18_X2Y5 RAMB18E1 r u_cpu/icache/data_ram_way[1].data_ram_bank[2].u/mem_reg_reg/ADDRBWRADDR[7]
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock cpu_clk rise edge) 30.323 30.323 r
|
|
clock source latency -5.674 24.648
|
|
propagated clock network latency
|
|
3.779 28.427
|
|
clock pessimism -0.418 28.009
|
|
clock uncertainty -0.074 27.935
|
|
RAMB18_X2Y5 RAMB18E1 (Setup_ramb18e1_CLKBWRCLK_ADDRBWRADDR[7])
|
|
-0.566 27.369 u_cpu/icache/data_ram_way[1].data_ram_bank[2].u/mem_reg_reg
|
|
-------------------------------------------------------------------
|
|
required time 27.369
|
|
arrival time -25.450
|
|
-------------------------------------------------------------------
|
|
slack 1.920
|
|
|
|
Slack (MET) : 1.920ns (required time - arrival time)
|
|
Source: u_cpu/addr_trans/data_vaddr_buffer_reg[14]/C
|
|
(rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns})
|
|
Destination: u_cpu/icache/data_ram_way[1].data_ram_bank[2].u/mem_reg_reg/ADDRBWRADDR[7]
|
|
(rising edge-triggered cell RAMB18E1 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns})
|
|
Path Group: cpu_clk
|
|
Path Type: Setup (Max at Slow Process Corner)
|
|
Requirement: 30.323ns (cpu_clk rise@30.323ns - cpu_clk rise@0.000ns)
|
|
Data Path Delay: 27.674ns (logic 5.333ns (19.271%) route 22.341ns (80.729%))
|
|
Logic Levels: 26 (CARRY4=4 LUT3=2 LUT4=1 LUT5=2 LUT6=15 MUXF7=1 MUXF8=1)
|
|
Clock Path Skew: -0.089ns (DCD - SCD + CPR)
|
|
Destination Clock Delay (DCD): -1.895ns = ( 28.427 - 30.323 )
|
|
Source Clock Delay (SCD): -2.225ns
|
|
Clock Pessimism Removal (CPR): -0.418ns
|
|
Clock Uncertainty: 0.074ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Discrete Jitter (DJ): 0.130ns
|
|
Phase Error (PE): 0.000ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock cpu_clk rise edge) 0.000 0.000 r
|
|
clock source latency -6.275 -6.275
|
|
propagated clock network latency
|
|
4.051 -2.225
|
|
SLICE_X35Y35 FDRE 0.000 -2.225 r u_cpu/addr_trans/data_vaddr_buffer_reg[14]/C
|
|
SLICE_X35Y35 FDRE (Prop_fdre_C_Q) 0.456 -1.769 r u_cpu/addr_trans/data_vaddr_buffer_reg[14]/Q
|
|
net (fo=33, routed) 1.442 -0.326 u_cpu/addr_trans/tlb_entry/data_vaddr_buffer[2]
|
|
SLICE_X42Y40 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_226/I5
|
|
SLICE_X42Y40 LUT6 (Prop_lut6_I5_O) 0.124 -0.202 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_226/O
|
|
net (fo=1, routed) 0.000 -0.202 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_226_n_0
|
|
SLICE_X42Y40 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_111/S[0]
|
|
SLICE_X42Y40 CARRY4 (Prop_carry4_S[0]_CO[3])
|
|
0.513 0.311 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_111/CO[3]
|
|
net (fo=1, routed) 0.000 0.311 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_111_n_0
|
|
SLICE_X42Y41 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_32/CI
|
|
SLICE_X42Y41 CARRY4 (Prop_carry4_CI_CO[2])
|
|
0.229 0.540 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_32/CO[2]
|
|
net (fo=1, routed) 1.009 1.549 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_32_n_1
|
|
SLICE_X40Y47 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_9/I1
|
|
SLICE_X40Y47 LUT6 (Prop_lut6_I1_O) 0.310 1.859 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_9/O
|
|
net (fo=2, routed) 0.635 2.494 u_cpu/addr_trans/tlb_entry/match1[28]
|
|
SLICE_X38Y47 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/I2
|
|
SLICE_X38Y47 LUT4 (Prop_lut4_I2_O) 0.124 2.618 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/O
|
|
net (fo=2, routed) 0.667 3.285 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2_n_0
|
|
SLICE_X39Y47 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/I0
|
|
SLICE_X39Y47 LUT5 (Prop_lut5_I0_O) 0.124 3.409 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/O
|
|
net (fo=2, routed) 1.103 4.512 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2_n_0
|
|
SLICE_X38Y50 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/I0
|
|
SLICE_X38Y50 LUT6 (Prop_lut6_I0_O) 0.124 4.636 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/O
|
|
net (fo=89, routed) 1.162 5.797 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus[8]
|
|
SLICE_X42Y51 r u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_38__0/S
|
|
SLICE_X42Y51 MUXF7 (Prop_muxf7_S_O) 0.292 6.089 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_38__0/O
|
|
net (fo=1, routed) 0.000 6.089 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_38__0_n_0
|
|
SLICE_X42Y51 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_16__0/I1
|
|
SLICE_X42Y51 MUXF8 (Prop_muxf8_I1_O) 0.088 6.177 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_16__0/O
|
|
net (fo=1, routed) 0.957 7.134 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_16__0_n_0
|
|
SLICE_X42Y50 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7/I0
|
|
SLICE_X42Y50 LUT6 (Prop_lut6_I0_O) 0.319 7.453 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7/O
|
|
net (fo=1, routed) 0.435 7.888 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7_n_0
|
|
SLICE_X44Y50 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0/I5
|
|
SLICE_X44Y50 LUT6 (Prop_lut6_I5_O) 0.124 8.012 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0/O
|
|
net (fo=10, routed) 0.740 8.753 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0_n_0
|
|
SLICE_X44Y50 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[5]_i_1__0/I3
|
|
SLICE_X44Y50 LUT6 (Prop_lut6_I3_O) 0.124 8.877 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[5]_i_1__0/O
|
|
net (fo=6, routed) 0.845 9.722 u_cpu/u_csr/ms_to_ws_bus[13]
|
|
SLICE_X50Y46 f u_cpu/u_csr/write_buffer_way[1]_i_18/I3
|
|
SLICE_X50Y46 LUT6 (Prop_lut6_I3_O) 0.124 9.846 r u_cpu/u_csr/write_buffer_way[1]_i_18/O
|
|
net (fo=1, routed) 0.000 9.846 u_cpu/u_csr/write_buffer_way[1]_i_18_n_0
|
|
SLICE_X50Y46 r u_cpu/u_csr/write_buffer_way_reg[1]_i_11/S[0]
|
|
SLICE_X50Y46 CARRY4 (Prop_carry4_S[0]_CO[3])
|
|
0.532 10.378 r u_cpu/u_csr/write_buffer_way_reg[1]_i_11/CO[3]
|
|
net (fo=1, routed) 0.000 10.378 u_cpu/u_csr/write_buffer_way_reg[1]_i_11_n_0
|
|
SLICE_X50Y47 r u_cpu/u_csr/write_buffer_way_reg[1]_i_9/CI
|
|
SLICE_X50Y47 CARRY4 (Prop_carry4_CI_CO[1])
|
|
0.157 10.535 r u_cpu/u_csr/write_buffer_way_reg[1]_i_9/CO[1]
|
|
net (fo=2, routed) 0.791 11.326 u_cpu/wb_stage/CO[0]
|
|
SLICE_X46Y39 r u_cpu/wb_stage/write_buffer_way[1]_i_5/I1
|
|
SLICE_X46Y39 LUT6 (Prop_lut6_I1_O) 0.329 11.655 f u_cpu/wb_stage/write_buffer_way[1]_i_5/O
|
|
net (fo=7, routed) 0.762 12.417 u_cpu/addr_trans/tlb_entry/sc_cancel_req
|
|
SLICE_X46Y35 f u_cpu/addr_trans/tlb_entry/main_state[0]_i_3/I1
|
|
SLICE_X46Y35 LUT3 (Prop_lut3_I1_O) 0.124 12.541 f u_cpu/addr_trans/tlb_entry/main_state[0]_i_3/O
|
|
net (fo=3, routed) 0.719 13.260 u_cpu/dcache/main_state_reg[0]_2
|
|
SLICE_X43Y31 f u_cpu/dcache/ds_to_es_bus_r[235]_i_10/I3
|
|
SLICE_X43Y31 LUT6 (Prop_lut6_I3_O) 0.124 13.384 f u_cpu/dcache/ds_to_es_bus_r[235]_i_10/O
|
|
net (fo=3, routed) 0.415 13.799 u_cpu/mem_stage/data_data_ok
|
|
SLICE_X43Y30 f u_cpu/mem_stage/flush_inst_req_buffer[1]_i_15/I0
|
|
SLICE_X43Y30 LUT3 (Prop_lut3_I0_O) 0.124 13.923 f u_cpu/mem_stage/flush_inst_req_buffer[1]_i_15/O
|
|
net (fo=2, routed) 0.833 14.756 u_cpu/mem_stage/es_to_ms_bus_r_reg[70]_1
|
|
SLICE_X48Y30 f u_cpu/mem_stage/flush_inst_req_buffer[1]_i_14/I0
|
|
SLICE_X48Y30 LUT6 (Prop_lut6_I0_O) 0.124 14.880 f u_cpu/mem_stage/flush_inst_req_buffer[1]_i_14/O
|
|
net (fo=1, routed) 0.651 15.532 u_cpu/mem_stage/ms_ready_go
|
|
SLICE_X48Y25 f u_cpu/mem_stage/flush_inst_req_buffer[1]_i_13/I4
|
|
SLICE_X48Y25 LUT6 (Prop_lut6_I4_O) 0.124 15.656 f u_cpu/mem_stage/flush_inst_req_buffer[1]_i_13/O
|
|
net (fo=3, routed) 0.483 16.139 u_cpu/id_stage/flush_inst_req_buffer[31]_i_6
|
|
SLICE_X50Y25 f u_cpu/id_stage/flush_inst_req_buffer[1]_i_9/I1
|
|
SLICE_X50Y25 LUT6 (Prop_lut6_I1_O) 0.124 16.263 f u_cpu/id_stage/flush_inst_req_buffer[1]_i_9/O
|
|
net (fo=32, routed) 0.531 16.794 u_cpu/if_stage/nextpc5
|
|
SLICE_X51Y27 f u_cpu/if_stage/fetch_pc_r[6]_i_4/I2
|
|
SLICE_X51Y27 LUT6 (Prop_lut6_I2_O) 0.124 16.918 r u_cpu/if_stage/fetch_pc_r[6]_i_4/O
|
|
net (fo=1, routed) 3.059 19.977 u_cpu/if_stage/fetch_pc_r[6]_i_4_n_0
|
|
SLICE_X114Y28 r u_cpu/if_stage/fetch_pc_r[6]_i_2/I2
|
|
SLICE_X114Y28 LUT6 (Prop_lut6_I2_O) 0.124 20.101 r u_cpu/if_stage/fetch_pc_r[6]_i_2/O
|
|
net (fo=1, routed) 0.441 20.542 u_cpu/if_stage/fetch_pc_r[6]_i_2_n_0
|
|
SLICE_X114Y25 r u_cpu/if_stage/fetch_pc_r[6]_i_1/I2
|
|
SLICE_X114Y25 LUT6 (Prop_lut6_I2_O) 0.124 20.666 r u_cpu/if_stage/fetch_pc_r[6]_i_1/O
|
|
net (fo=6, routed) 3.249 23.915 u_cpu/icache/tagv_ram_way[1].u/mem_reg_reg_2[2]
|
|
SLICE_X49Y33 r u_cpu/icache/tagv_ram_way[1].u/mem_reg_reg_i_8/I4
|
|
SLICE_X49Y33 LUT5 (Prop_lut5_I4_O) 0.124 24.039 r u_cpu/icache/tagv_ram_way[1].u/mem_reg_reg_i_8/O
|
|
net (fo=16, routed) 1.410 25.450 u_cpu/icache/data_ram_way[1].data_ram_bank[2].u/ADDRBWRADDR[2]
|
|
RAMB18_X2Y5 RAMB18E1 r u_cpu/icache/data_ram_way[1].data_ram_bank[2].u/mem_reg_reg/ADDRBWRADDR[7]
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock cpu_clk rise edge) 30.323 30.323 r
|
|
clock source latency -5.674 24.648
|
|
propagated clock network latency
|
|
3.779 28.427
|
|
clock pessimism -0.418 28.009
|
|
clock uncertainty -0.074 27.935
|
|
RAMB18_X2Y5 RAMB18E1 (Setup_ramb18e1_CLKBWRCLK_ADDRBWRADDR[7])
|
|
-0.566 27.369 u_cpu/icache/data_ram_way[1].data_ram_bank[2].u/mem_reg_reg
|
|
-------------------------------------------------------------------
|
|
required time 27.369
|
|
arrival time -25.450
|
|
-------------------------------------------------------------------
|
|
slack 1.920
|
|
|
|
Slack (MET) : 1.920ns (required time - arrival time)
|
|
Source: u_cpu/addr_trans/data_vaddr_buffer_reg[14]/C
|
|
(rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns})
|
|
Destination: u_cpu/icache/data_ram_way[1].data_ram_bank[2].u/mem_reg_reg/ADDRBWRADDR[7]
|
|
(rising edge-triggered cell RAMB18E1 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns})
|
|
Path Group: cpu_clk
|
|
Path Type: Setup (Max at Slow Process Corner)
|
|
Requirement: 30.323ns (cpu_clk rise@30.323ns - cpu_clk rise@0.000ns)
|
|
Data Path Delay: 27.674ns (logic 5.333ns (19.271%) route 22.341ns (80.729%))
|
|
Logic Levels: 26 (CARRY4=4 LUT3=2 LUT4=1 LUT5=2 LUT6=15 MUXF7=1 MUXF8=1)
|
|
Clock Path Skew: -0.089ns (DCD - SCD + CPR)
|
|
Destination Clock Delay (DCD): -1.895ns = ( 28.427 - 30.323 )
|
|
Source Clock Delay (SCD): -2.225ns
|
|
Clock Pessimism Removal (CPR): -0.418ns
|
|
Clock Uncertainty: 0.074ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Discrete Jitter (DJ): 0.130ns
|
|
Phase Error (PE): 0.000ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock cpu_clk rise edge) 0.000 0.000 r
|
|
clock source latency -6.275 -6.275
|
|
propagated clock network latency
|
|
4.051 -2.225
|
|
SLICE_X35Y35 FDRE 0.000 -2.225 r u_cpu/addr_trans/data_vaddr_buffer_reg[14]/C
|
|
SLICE_X35Y35 FDRE (Prop_fdre_C_Q) 0.456 -1.769 r u_cpu/addr_trans/data_vaddr_buffer_reg[14]/Q
|
|
net (fo=33, routed) 1.442 -0.326 u_cpu/addr_trans/tlb_entry/data_vaddr_buffer[2]
|
|
SLICE_X42Y40 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_226/I5
|
|
SLICE_X42Y40 LUT6 (Prop_lut6_I5_O) 0.124 -0.202 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_226/O
|
|
net (fo=1, routed) 0.000 -0.202 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_226_n_0
|
|
SLICE_X42Y40 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_111/S[0]
|
|
SLICE_X42Y40 CARRY4 (Prop_carry4_S[0]_CO[3])
|
|
0.513 0.311 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_111/CO[3]
|
|
net (fo=1, routed) 0.000 0.311 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_111_n_0
|
|
SLICE_X42Y41 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_32/CI
|
|
SLICE_X42Y41 CARRY4 (Prop_carry4_CI_CO[2])
|
|
0.229 0.540 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_32/CO[2]
|
|
net (fo=1, routed) 1.009 1.549 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_32_n_1
|
|
SLICE_X40Y47 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_9/I1
|
|
SLICE_X40Y47 LUT6 (Prop_lut6_I1_O) 0.310 1.859 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_9/O
|
|
net (fo=2, routed) 0.635 2.494 u_cpu/addr_trans/tlb_entry/match1[28]
|
|
SLICE_X38Y47 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/I2
|
|
SLICE_X38Y47 LUT4 (Prop_lut4_I2_O) 0.124 2.618 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/O
|
|
net (fo=2, routed) 0.667 3.285 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2_n_0
|
|
SLICE_X39Y47 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/I0
|
|
SLICE_X39Y47 LUT5 (Prop_lut5_I0_O) 0.124 3.409 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/O
|
|
net (fo=2, routed) 1.103 4.512 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2_n_0
|
|
SLICE_X38Y50 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/I0
|
|
SLICE_X38Y50 LUT6 (Prop_lut6_I0_O) 0.124 4.636 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/O
|
|
net (fo=89, routed) 1.162 5.797 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus[8]
|
|
SLICE_X42Y51 r u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_38__0/S
|
|
SLICE_X42Y51 MUXF7 (Prop_muxf7_S_O) 0.292 6.089 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_38__0/O
|
|
net (fo=1, routed) 0.000 6.089 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_38__0_n_0
|
|
SLICE_X42Y51 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_16__0/I1
|
|
SLICE_X42Y51 MUXF8 (Prop_muxf8_I1_O) 0.088 6.177 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_16__0/O
|
|
net (fo=1, routed) 0.957 7.134 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_16__0_n_0
|
|
SLICE_X42Y50 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7/I0
|
|
SLICE_X42Y50 LUT6 (Prop_lut6_I0_O) 0.319 7.453 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7/O
|
|
net (fo=1, routed) 0.435 7.888 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7_n_0
|
|
SLICE_X44Y50 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0/I5
|
|
SLICE_X44Y50 LUT6 (Prop_lut6_I5_O) 0.124 8.012 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0/O
|
|
net (fo=10, routed) 0.740 8.753 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0_n_0
|
|
SLICE_X44Y50 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[5]_i_1__0/I3
|
|
SLICE_X44Y50 LUT6 (Prop_lut6_I3_O) 0.124 8.877 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[5]_i_1__0/O
|
|
net (fo=6, routed) 0.845 9.722 u_cpu/u_csr/ms_to_ws_bus[13]
|
|
SLICE_X50Y46 r u_cpu/u_csr/write_buffer_way[1]_i_18/I3
|
|
SLICE_X50Y46 LUT6 (Prop_lut6_I3_O) 0.124 9.846 f u_cpu/u_csr/write_buffer_way[1]_i_18/O
|
|
net (fo=1, routed) 0.000 9.846 u_cpu/u_csr/write_buffer_way[1]_i_18_n_0
|
|
SLICE_X50Y46 f u_cpu/u_csr/write_buffer_way_reg[1]_i_11/S[0]
|
|
SLICE_X50Y46 CARRY4 (Prop_carry4_S[0]_CO[3])
|
|
0.532 10.378 r u_cpu/u_csr/write_buffer_way_reg[1]_i_11/CO[3]
|
|
net (fo=1, routed) 0.000 10.378 u_cpu/u_csr/write_buffer_way_reg[1]_i_11_n_0
|
|
SLICE_X50Y47 r u_cpu/u_csr/write_buffer_way_reg[1]_i_9/CI
|
|
SLICE_X50Y47 CARRY4 (Prop_carry4_CI_CO[1])
|
|
0.157 10.535 r u_cpu/u_csr/write_buffer_way_reg[1]_i_9/CO[1]
|
|
net (fo=2, routed) 0.791 11.326 u_cpu/wb_stage/CO[0]
|
|
SLICE_X46Y39 r u_cpu/wb_stage/write_buffer_way[1]_i_5/I1
|
|
SLICE_X46Y39 LUT6 (Prop_lut6_I1_O) 0.329 11.655 f u_cpu/wb_stage/write_buffer_way[1]_i_5/O
|
|
net (fo=7, routed) 0.762 12.417 u_cpu/addr_trans/tlb_entry/sc_cancel_req
|
|
SLICE_X46Y35 f u_cpu/addr_trans/tlb_entry/main_state[0]_i_3/I1
|
|
SLICE_X46Y35 LUT3 (Prop_lut3_I1_O) 0.124 12.541 f u_cpu/addr_trans/tlb_entry/main_state[0]_i_3/O
|
|
net (fo=3, routed) 0.719 13.260 u_cpu/dcache/main_state_reg[0]_2
|
|
SLICE_X43Y31 f u_cpu/dcache/ds_to_es_bus_r[235]_i_10/I3
|
|
SLICE_X43Y31 LUT6 (Prop_lut6_I3_O) 0.124 13.384 f u_cpu/dcache/ds_to_es_bus_r[235]_i_10/O
|
|
net (fo=3, routed) 0.415 13.799 u_cpu/mem_stage/data_data_ok
|
|
SLICE_X43Y30 f u_cpu/mem_stage/flush_inst_req_buffer[1]_i_15/I0
|
|
SLICE_X43Y30 LUT3 (Prop_lut3_I0_O) 0.124 13.923 f u_cpu/mem_stage/flush_inst_req_buffer[1]_i_15/O
|
|
net (fo=2, routed) 0.833 14.756 u_cpu/mem_stage/es_to_ms_bus_r_reg[70]_1
|
|
SLICE_X48Y30 f u_cpu/mem_stage/flush_inst_req_buffer[1]_i_14/I0
|
|
SLICE_X48Y30 LUT6 (Prop_lut6_I0_O) 0.124 14.880 f u_cpu/mem_stage/flush_inst_req_buffer[1]_i_14/O
|
|
net (fo=1, routed) 0.651 15.532 u_cpu/mem_stage/ms_ready_go
|
|
SLICE_X48Y25 f u_cpu/mem_stage/flush_inst_req_buffer[1]_i_13/I4
|
|
SLICE_X48Y25 LUT6 (Prop_lut6_I4_O) 0.124 15.656 f u_cpu/mem_stage/flush_inst_req_buffer[1]_i_13/O
|
|
net (fo=3, routed) 0.483 16.139 u_cpu/id_stage/flush_inst_req_buffer[31]_i_6
|
|
SLICE_X50Y25 f u_cpu/id_stage/flush_inst_req_buffer[1]_i_9/I1
|
|
SLICE_X50Y25 LUT6 (Prop_lut6_I1_O) 0.124 16.263 f u_cpu/id_stage/flush_inst_req_buffer[1]_i_9/O
|
|
net (fo=32, routed) 0.531 16.794 u_cpu/if_stage/nextpc5
|
|
SLICE_X51Y27 f u_cpu/if_stage/fetch_pc_r[6]_i_4/I2
|
|
SLICE_X51Y27 LUT6 (Prop_lut6_I2_O) 0.124 16.918 r u_cpu/if_stage/fetch_pc_r[6]_i_4/O
|
|
net (fo=1, routed) 3.059 19.977 u_cpu/if_stage/fetch_pc_r[6]_i_4_n_0
|
|
SLICE_X114Y28 r u_cpu/if_stage/fetch_pc_r[6]_i_2/I2
|
|
SLICE_X114Y28 LUT6 (Prop_lut6_I2_O) 0.124 20.101 r u_cpu/if_stage/fetch_pc_r[6]_i_2/O
|
|
net (fo=1, routed) 0.441 20.542 u_cpu/if_stage/fetch_pc_r[6]_i_2_n_0
|
|
SLICE_X114Y25 r u_cpu/if_stage/fetch_pc_r[6]_i_1/I2
|
|
SLICE_X114Y25 LUT6 (Prop_lut6_I2_O) 0.124 20.666 r u_cpu/if_stage/fetch_pc_r[6]_i_1/O
|
|
net (fo=6, routed) 3.249 23.915 u_cpu/icache/tagv_ram_way[1].u/mem_reg_reg_2[2]
|
|
SLICE_X49Y33 r u_cpu/icache/tagv_ram_way[1].u/mem_reg_reg_i_8/I4
|
|
SLICE_X49Y33 LUT5 (Prop_lut5_I4_O) 0.124 24.039 r u_cpu/icache/tagv_ram_way[1].u/mem_reg_reg_i_8/O
|
|
net (fo=16, routed) 1.410 25.450 u_cpu/icache/data_ram_way[1].data_ram_bank[2].u/ADDRBWRADDR[2]
|
|
RAMB18_X2Y5 RAMB18E1 r u_cpu/icache/data_ram_way[1].data_ram_bank[2].u/mem_reg_reg/ADDRBWRADDR[7]
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock cpu_clk rise edge) 30.323 30.323 r
|
|
clock source latency -5.674 24.648
|
|
propagated clock network latency
|
|
3.779 28.427
|
|
clock pessimism -0.418 28.009
|
|
clock uncertainty -0.074 27.935
|
|
RAMB18_X2Y5 RAMB18E1 (Setup_ramb18e1_CLKBWRCLK_ADDRBWRADDR[7])
|
|
-0.566 27.369 u_cpu/icache/data_ram_way[1].data_ram_bank[2].u/mem_reg_reg
|
|
-------------------------------------------------------------------
|
|
required time 27.369
|
|
arrival time -25.450
|
|
-------------------------------------------------------------------
|
|
slack 1.920
|
|
|
|
Slack (MET) : 1.920ns (required time - arrival time)
|
|
Source: u_cpu/addr_trans/data_vaddr_buffer_reg[14]/C
|
|
(rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns})
|
|
Destination: u_cpu/icache/data_ram_way[1].data_ram_bank[2].u/mem_reg_reg/ADDRBWRADDR[7]
|
|
(rising edge-triggered cell RAMB18E1 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns})
|
|
Path Group: cpu_clk
|
|
Path Type: Setup (Max at Slow Process Corner)
|
|
Requirement: 30.323ns (cpu_clk rise@30.323ns - cpu_clk rise@0.000ns)
|
|
Data Path Delay: 27.674ns (logic 5.333ns (19.271%) route 22.341ns (80.729%))
|
|
Logic Levels: 26 (CARRY4=4 LUT3=2 LUT4=1 LUT5=2 LUT6=15 MUXF7=1 MUXF8=1)
|
|
Clock Path Skew: -0.089ns (DCD - SCD + CPR)
|
|
Destination Clock Delay (DCD): -1.895ns = ( 28.427 - 30.323 )
|
|
Source Clock Delay (SCD): -2.225ns
|
|
Clock Pessimism Removal (CPR): -0.418ns
|
|
Clock Uncertainty: 0.074ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Discrete Jitter (DJ): 0.130ns
|
|
Phase Error (PE): 0.000ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock cpu_clk rise edge) 0.000 0.000 r
|
|
clock source latency -6.275 -6.275
|
|
propagated clock network latency
|
|
4.051 -2.225
|
|
SLICE_X35Y35 FDRE 0.000 -2.225 r u_cpu/addr_trans/data_vaddr_buffer_reg[14]/C
|
|
SLICE_X35Y35 FDRE (Prop_fdre_C_Q) 0.456 -1.769 r u_cpu/addr_trans/data_vaddr_buffer_reg[14]/Q
|
|
net (fo=33, routed) 1.442 -0.326 u_cpu/addr_trans/tlb_entry/data_vaddr_buffer[2]
|
|
SLICE_X42Y40 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_226/I5
|
|
SLICE_X42Y40 LUT6 (Prop_lut6_I5_O) 0.124 -0.202 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_226/O
|
|
net (fo=1, routed) 0.000 -0.202 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_226_n_0
|
|
SLICE_X42Y40 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_111/S[0]
|
|
SLICE_X42Y40 CARRY4 (Prop_carry4_S[0]_CO[3])
|
|
0.513 0.311 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_111/CO[3]
|
|
net (fo=1, routed) 0.000 0.311 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_111_n_0
|
|
SLICE_X42Y41 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_32/CI
|
|
SLICE_X42Y41 CARRY4 (Prop_carry4_CI_CO[2])
|
|
0.229 0.540 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_32/CO[2]
|
|
net (fo=1, routed) 1.009 1.549 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_32_n_1
|
|
SLICE_X40Y47 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_9/I1
|
|
SLICE_X40Y47 LUT6 (Prop_lut6_I1_O) 0.310 1.859 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_9/O
|
|
net (fo=2, routed) 0.635 2.494 u_cpu/addr_trans/tlb_entry/match1[28]
|
|
SLICE_X38Y47 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/I2
|
|
SLICE_X38Y47 LUT4 (Prop_lut4_I2_O) 0.124 2.618 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/O
|
|
net (fo=2, routed) 0.667 3.285 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2_n_0
|
|
SLICE_X39Y47 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/I0
|
|
SLICE_X39Y47 LUT5 (Prop_lut5_I0_O) 0.124 3.409 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/O
|
|
net (fo=2, routed) 1.103 4.512 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2_n_0
|
|
SLICE_X38Y50 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/I0
|
|
SLICE_X38Y50 LUT6 (Prop_lut6_I0_O) 0.124 4.636 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/O
|
|
net (fo=89, routed) 1.162 5.797 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus[8]
|
|
SLICE_X42Y51 r u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_38__0/S
|
|
SLICE_X42Y51 MUXF7 (Prop_muxf7_S_O) 0.292 6.089 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_38__0/O
|
|
net (fo=1, routed) 0.000 6.089 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_38__0_n_0
|
|
SLICE_X42Y51 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_16__0/I1
|
|
SLICE_X42Y51 MUXF8 (Prop_muxf8_I1_O) 0.088 6.177 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_16__0/O
|
|
net (fo=1, routed) 0.957 7.134 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_16__0_n_0
|
|
SLICE_X42Y50 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7/I0
|
|
SLICE_X42Y50 LUT6 (Prop_lut6_I0_O) 0.319 7.453 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7/O
|
|
net (fo=1, routed) 0.435 7.888 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7_n_0
|
|
SLICE_X44Y50 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0/I5
|
|
SLICE_X44Y50 LUT6 (Prop_lut6_I5_O) 0.124 8.012 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0/O
|
|
net (fo=10, routed) 0.740 8.753 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0_n_0
|
|
SLICE_X44Y50 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[5]_i_1__0/I3
|
|
SLICE_X44Y50 LUT6 (Prop_lut6_I3_O) 0.124 8.877 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[5]_i_1__0/O
|
|
net (fo=6, routed) 0.845 9.722 u_cpu/u_csr/ms_to_ws_bus[13]
|
|
SLICE_X50Y46 f u_cpu/u_csr/write_buffer_way[1]_i_18/I3
|
|
SLICE_X50Y46 LUT6 (Prop_lut6_I3_O) 0.124 9.846 f u_cpu/u_csr/write_buffer_way[1]_i_18/O
|
|
net (fo=1, routed) 0.000 9.846 u_cpu/u_csr/write_buffer_way[1]_i_18_n_0
|
|
SLICE_X50Y46 f u_cpu/u_csr/write_buffer_way_reg[1]_i_11/S[0]
|
|
SLICE_X50Y46 CARRY4 (Prop_carry4_S[0]_CO[3])
|
|
0.532 10.378 r u_cpu/u_csr/write_buffer_way_reg[1]_i_11/CO[3]
|
|
net (fo=1, routed) 0.000 10.378 u_cpu/u_csr/write_buffer_way_reg[1]_i_11_n_0
|
|
SLICE_X50Y47 r u_cpu/u_csr/write_buffer_way_reg[1]_i_9/CI
|
|
SLICE_X50Y47 CARRY4 (Prop_carry4_CI_CO[1])
|
|
0.157 10.535 r u_cpu/u_csr/write_buffer_way_reg[1]_i_9/CO[1]
|
|
net (fo=2, routed) 0.791 11.326 u_cpu/wb_stage/CO[0]
|
|
SLICE_X46Y39 r u_cpu/wb_stage/write_buffer_way[1]_i_5/I1
|
|
SLICE_X46Y39 LUT6 (Prop_lut6_I1_O) 0.329 11.655 f u_cpu/wb_stage/write_buffer_way[1]_i_5/O
|
|
net (fo=7, routed) 0.762 12.417 u_cpu/addr_trans/tlb_entry/sc_cancel_req
|
|
SLICE_X46Y35 f u_cpu/addr_trans/tlb_entry/main_state[0]_i_3/I1
|
|
SLICE_X46Y35 LUT3 (Prop_lut3_I1_O) 0.124 12.541 f u_cpu/addr_trans/tlb_entry/main_state[0]_i_3/O
|
|
net (fo=3, routed) 0.719 13.260 u_cpu/dcache/main_state_reg[0]_2
|
|
SLICE_X43Y31 f u_cpu/dcache/ds_to_es_bus_r[235]_i_10/I3
|
|
SLICE_X43Y31 LUT6 (Prop_lut6_I3_O) 0.124 13.384 f u_cpu/dcache/ds_to_es_bus_r[235]_i_10/O
|
|
net (fo=3, routed) 0.415 13.799 u_cpu/mem_stage/data_data_ok
|
|
SLICE_X43Y30 f u_cpu/mem_stage/flush_inst_req_buffer[1]_i_15/I0
|
|
SLICE_X43Y30 LUT3 (Prop_lut3_I0_O) 0.124 13.923 f u_cpu/mem_stage/flush_inst_req_buffer[1]_i_15/O
|
|
net (fo=2, routed) 0.833 14.756 u_cpu/mem_stage/es_to_ms_bus_r_reg[70]_1
|
|
SLICE_X48Y30 f u_cpu/mem_stage/flush_inst_req_buffer[1]_i_14/I0
|
|
SLICE_X48Y30 LUT6 (Prop_lut6_I0_O) 0.124 14.880 f u_cpu/mem_stage/flush_inst_req_buffer[1]_i_14/O
|
|
net (fo=1, routed) 0.651 15.532 u_cpu/mem_stage/ms_ready_go
|
|
SLICE_X48Y25 f u_cpu/mem_stage/flush_inst_req_buffer[1]_i_13/I4
|
|
SLICE_X48Y25 LUT6 (Prop_lut6_I4_O) 0.124 15.656 f u_cpu/mem_stage/flush_inst_req_buffer[1]_i_13/O
|
|
net (fo=3, routed) 0.483 16.139 u_cpu/id_stage/flush_inst_req_buffer[31]_i_6
|
|
SLICE_X50Y25 f u_cpu/id_stage/flush_inst_req_buffer[1]_i_9/I1
|
|
SLICE_X50Y25 LUT6 (Prop_lut6_I1_O) 0.124 16.263 f u_cpu/id_stage/flush_inst_req_buffer[1]_i_9/O
|
|
net (fo=32, routed) 0.531 16.794 u_cpu/if_stage/nextpc5
|
|
SLICE_X51Y27 f u_cpu/if_stage/fetch_pc_r[6]_i_4/I2
|
|
SLICE_X51Y27 LUT6 (Prop_lut6_I2_O) 0.124 16.918 r u_cpu/if_stage/fetch_pc_r[6]_i_4/O
|
|
net (fo=1, routed) 3.059 19.977 u_cpu/if_stage/fetch_pc_r[6]_i_4_n_0
|
|
SLICE_X114Y28 r u_cpu/if_stage/fetch_pc_r[6]_i_2/I2
|
|
SLICE_X114Y28 LUT6 (Prop_lut6_I2_O) 0.124 20.101 r u_cpu/if_stage/fetch_pc_r[6]_i_2/O
|
|
net (fo=1, routed) 0.441 20.542 u_cpu/if_stage/fetch_pc_r[6]_i_2_n_0
|
|
SLICE_X114Y25 r u_cpu/if_stage/fetch_pc_r[6]_i_1/I2
|
|
SLICE_X114Y25 LUT6 (Prop_lut6_I2_O) 0.124 20.666 r u_cpu/if_stage/fetch_pc_r[6]_i_1/O
|
|
net (fo=6, routed) 3.249 23.915 u_cpu/icache/tagv_ram_way[1].u/mem_reg_reg_2[2]
|
|
SLICE_X49Y33 r u_cpu/icache/tagv_ram_way[1].u/mem_reg_reg_i_8/I4
|
|
SLICE_X49Y33 LUT5 (Prop_lut5_I4_O) 0.124 24.039 r u_cpu/icache/tagv_ram_way[1].u/mem_reg_reg_i_8/O
|
|
net (fo=16, routed) 1.410 25.450 u_cpu/icache/data_ram_way[1].data_ram_bank[2].u/ADDRBWRADDR[2]
|
|
RAMB18_X2Y5 RAMB18E1 r u_cpu/icache/data_ram_way[1].data_ram_bank[2].u/mem_reg_reg/ADDRBWRADDR[7]
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock cpu_clk rise edge) 30.323 30.323 r
|
|
clock source latency -5.674 24.648
|
|
propagated clock network latency
|
|
3.779 28.427
|
|
clock pessimism -0.418 28.009
|
|
clock uncertainty -0.074 27.935
|
|
RAMB18_X2Y5 RAMB18E1 (Setup_ramb18e1_CLKBWRCLK_ADDRBWRADDR[7])
|
|
-0.566 27.369 u_cpu/icache/data_ram_way[1].data_ram_bank[2].u/mem_reg_reg
|
|
-------------------------------------------------------------------
|
|
required time 27.369
|
|
arrival time -25.450
|
|
-------------------------------------------------------------------
|
|
slack 1.920
|
|
|
|
Slack (MET) : 8.003ns (required time - arrival time)
|
|
Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_cnt_reg[3]/C
|
|
(rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_B_reg[198][0]/CLR
|
|
(recovery check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Path Group: **async_default**
|
|
Path Type: Recovery (Max at Slow Process Corner)
|
|
Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns)
|
|
Data Path Delay: 10.967ns (logic 0.668ns (6.091%) route 10.299ns (93.909%))
|
|
Logic Levels: 1 (LUT5=1)
|
|
Clock Path Skew: -0.331ns (DCD - SCD + CPR)
|
|
Destination Clock Delay (DCD): -2.305ns = ( 17.695 - 20.000 )
|
|
Source Clock Delay (SCD): -2.488ns
|
|
Clock Pessimism Removal (CPR): -0.514ns
|
|
Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Discrete Jitter (DJ): 0.122ns
|
|
Phase Error (PE): 0.000ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock sys_clk rise edge) 0.000 0.000 r
|
|
clock source latency -6.275 -6.275
|
|
propagated clock network latency
|
|
3.788 -2.488
|
|
SLICE_X112Y65 FDCE 0.000 -2.488 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_cnt_reg[3]/C
|
|
SLICE_X112Y65 FDCE (Prop_fdce_C_Q) 0.518 -1.970 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_cnt_reg[3]/Q
|
|
net (fo=5, routed) 1.052 -0.917 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/srst_cnt_reg[3]
|
|
SLICE_X112Y66 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/p_s1[23]_i_9/I4
|
|
SLICE_X112Y66 LUT5 (Prop_lut5_I4_O) 0.150 -0.767 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/p_s1[23]_i_9/O
|
|
net (fo=24670, routed) 9.247 8.480 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/delay_reg[1]
|
|
SLICE_X63Y167 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_B_reg[198][0]/CLR
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock sys_clk rise edge) 20.000 20.000 r
|
|
clock source latency -5.674 14.326
|
|
propagated clock network latency
|
|
3.370 17.695
|
|
clock pessimism -0.514 17.182
|
|
clock uncertainty -0.071 17.111
|
|
SLICE_X63Y167 FDCE (Recov_fdce_C_CLR) -0.629 16.482 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_B_reg[198][0]
|
|
-------------------------------------------------------------------
|
|
required time 16.482
|
|
arrival time -8.480
|
|
-------------------------------------------------------------------
|
|
slack 8.003
|
|
|
|
Slack (MET) : 8.062ns (required time - arrival time)
|
|
Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_cnt_reg[1]/C
|
|
(rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_B_reg[198][0]/CLR
|
|
(recovery check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Path Group: **async_default**
|
|
Path Type: Recovery (Max at Slow Process Corner)
|
|
Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns)
|
|
Data Path Delay: 10.907ns (logic 0.670ns (6.143%) route 10.237ns (93.857%))
|
|
Logic Levels: 1 (LUT5=1)
|
|
Clock Path Skew: -0.331ns (DCD - SCD + CPR)
|
|
Destination Clock Delay (DCD): -2.305ns = ( 17.695 - 20.000 )
|
|
Source Clock Delay (SCD): -2.488ns
|
|
Clock Pessimism Removal (CPR): -0.514ns
|
|
Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Discrete Jitter (DJ): 0.122ns
|
|
Phase Error (PE): 0.000ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock sys_clk rise edge) 0.000 0.000 r
|
|
clock source latency -6.275 -6.275
|
|
propagated clock network latency
|
|
3.788 -2.488
|
|
SLICE_X112Y65 FDCE 0.000 -2.488 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_cnt_reg[1]/C
|
|
SLICE_X112Y65 FDCE (Prop_fdce_C_Q) 0.518 -1.970 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_cnt_reg[1]/Q
|
|
net (fo=7, routed) 0.990 -0.979 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/srst_cnt_reg[1]
|
|
SLICE_X112Y66 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/p_s1[23]_i_9/I1
|
|
SLICE_X112Y66 LUT5 (Prop_lut5_I1_O) 0.152 -0.827 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/p_s1[23]_i_9/O
|
|
net (fo=24670, routed) 9.247 8.420 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/delay_reg[1]
|
|
SLICE_X63Y167 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_B_reg[198][0]/CLR
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock sys_clk rise edge) 20.000 20.000 r
|
|
clock source latency -5.674 14.326
|
|
propagated clock network latency
|
|
3.370 17.695
|
|
clock pessimism -0.514 17.182
|
|
clock uncertainty -0.071 17.111
|
|
SLICE_X63Y167 FDCE (Recov_fdce_C_CLR) -0.629 16.482 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_B_reg[198][0]
|
|
-------------------------------------------------------------------
|
|
required time 16.482
|
|
arrival time -8.420
|
|
-------------------------------------------------------------------
|
|
slack 8.062
|
|
|
|
Slack (MET) : 8.086ns (required time - arrival time)
|
|
Source: pll_clk.u_rst_sys/delay_reg[1]/C
|
|
(rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_B_reg[198][0]/CLR
|
|
(recovery check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Path Group: **async_default**
|
|
Path Type: Recovery (Max at Slow Process Corner)
|
|
Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns)
|
|
Data Path Delay: 10.891ns (logic 0.608ns (5.582%) route 10.283ns (94.418%))
|
|
Logic Levels: 1 (LUT5=1)
|
|
Clock Path Skew: -0.323ns (DCD - SCD + CPR)
|
|
Destination Clock Delay (DCD): -2.305ns = ( 17.695 - 20.000 )
|
|
Source Clock Delay (SCD): -2.496ns
|
|
Clock Pessimism Removal (CPR): -0.514ns
|
|
Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Discrete Jitter (DJ): 0.122ns
|
|
Phase Error (PE): 0.000ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock sys_clk rise edge) 0.000 0.000 r
|
|
clock source latency -6.275 -6.275
|
|
propagated clock network latency
|
|
3.780 -2.496
|
|
SLICE_X106Y69 FDCE 0.000 -2.496 r pll_clk.u_rst_sys/delay_reg[1]/C
|
|
SLICE_X106Y69 FDCE (Prop_fdce_C_Q) 0.456 -2.040 r pll_clk.u_rst_sys/delay_reg[1]/Q
|
|
net (fo=125, routed) 1.036 -1.003 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/valid_sr_reg[6][0]
|
|
SLICE_X112Y66 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/p_s1[23]_i_9/I0
|
|
SLICE_X112Y66 LUT5 (Prop_lut5_I0_O) 0.152 -0.851 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/p_s1[23]_i_9/O
|
|
net (fo=24670, routed) 9.247 8.396 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/delay_reg[1]
|
|
SLICE_X63Y167 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_B_reg[198][0]/CLR
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock sys_clk rise edge) 20.000 20.000 r
|
|
clock source latency -5.674 14.326
|
|
propagated clock network latency
|
|
3.370 17.695
|
|
clock pessimism -0.514 17.182
|
|
clock uncertainty -0.071 17.111
|
|
SLICE_X63Y167 FDCE (Recov_fdce_C_CLR) -0.629 16.482 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_B_reg[198][0]
|
|
-------------------------------------------------------------------
|
|
required time 16.482
|
|
arrival time -8.396
|
|
-------------------------------------------------------------------
|
|
slack 8.086
|
|
|
|
Slack (MET) : 8.089ns (required time - arrival time)
|
|
Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_cnt_reg[3]/C
|
|
(rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_A_reg[208][10]/CLR
|
|
(recovery check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Path Group: **async_default**
|
|
Path Type: Recovery (Max at Slow Process Corner)
|
|
Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns)
|
|
Data Path Delay: 10.967ns (logic 0.668ns (6.091%) route 10.299ns (93.909%))
|
|
Logic Levels: 1 (LUT5=1)
|
|
Clock Path Skew: -0.331ns (DCD - SCD + CPR)
|
|
Destination Clock Delay (DCD): -2.305ns = ( 17.695 - 20.000 )
|
|
Source Clock Delay (SCD): -2.488ns
|
|
Clock Pessimism Removal (CPR): -0.514ns
|
|
Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Discrete Jitter (DJ): 0.122ns
|
|
Phase Error (PE): 0.000ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock sys_clk rise edge) 0.000 0.000 r
|
|
clock source latency -6.275 -6.275
|
|
propagated clock network latency
|
|
3.788 -2.488
|
|
SLICE_X112Y65 FDCE 0.000 -2.488 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_cnt_reg[3]/C
|
|
SLICE_X112Y65 FDCE (Prop_fdce_C_Q) 0.518 -1.970 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_cnt_reg[3]/Q
|
|
net (fo=5, routed) 1.052 -0.917 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/srst_cnt_reg[3]
|
|
SLICE_X112Y66 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/p_s1[23]_i_9/I4
|
|
SLICE_X112Y66 LUT5 (Prop_lut5_I4_O) 0.150 -0.767 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/p_s1[23]_i_9/O
|
|
net (fo=24670, routed) 9.247 8.480 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/delay_reg[1]
|
|
SLICE_X62Y167 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_A_reg[208][10]/CLR
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock sys_clk rise edge) 20.000 20.000 r
|
|
clock source latency -5.674 14.326
|
|
propagated clock network latency
|
|
3.370 17.695
|
|
clock pessimism -0.514 17.182
|
|
clock uncertainty -0.071 17.111
|
|
SLICE_X62Y167 FDCE (Recov_fdce_C_CLR) -0.543 16.568 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_A_reg[208][10]
|
|
-------------------------------------------------------------------
|
|
required time 16.568
|
|
arrival time -8.480
|
|
-------------------------------------------------------------------
|
|
slack 8.089
|
|
|
|
Slack (MET) : 8.089ns (required time - arrival time)
|
|
Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_cnt_reg[3]/C
|
|
(rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_B_reg[208][0]/CLR
|
|
(recovery check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Path Group: **async_default**
|
|
Path Type: Recovery (Max at Slow Process Corner)
|
|
Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns)
|
|
Data Path Delay: 10.967ns (logic 0.668ns (6.091%) route 10.299ns (93.909%))
|
|
Logic Levels: 1 (LUT5=1)
|
|
Clock Path Skew: -0.331ns (DCD - SCD + CPR)
|
|
Destination Clock Delay (DCD): -2.305ns = ( 17.695 - 20.000 )
|
|
Source Clock Delay (SCD): -2.488ns
|
|
Clock Pessimism Removal (CPR): -0.514ns
|
|
Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Discrete Jitter (DJ): 0.122ns
|
|
Phase Error (PE): 0.000ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock sys_clk rise edge) 0.000 0.000 r
|
|
clock source latency -6.275 -6.275
|
|
propagated clock network latency
|
|
3.788 -2.488
|
|
SLICE_X112Y65 FDCE 0.000 -2.488 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_cnt_reg[3]/C
|
|
SLICE_X112Y65 FDCE (Prop_fdce_C_Q) 0.518 -1.970 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_cnt_reg[3]/Q
|
|
net (fo=5, routed) 1.052 -0.917 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/srst_cnt_reg[3]
|
|
SLICE_X112Y66 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/p_s1[23]_i_9/I4
|
|
SLICE_X112Y66 LUT5 (Prop_lut5_I4_O) 0.150 -0.767 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/p_s1[23]_i_9/O
|
|
net (fo=24670, routed) 9.247 8.480 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/delay_reg[1]
|
|
SLICE_X62Y167 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_B_reg[208][0]/CLR
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock sys_clk rise edge) 20.000 20.000 r
|
|
clock source latency -5.674 14.326
|
|
propagated clock network latency
|
|
3.370 17.695
|
|
clock pessimism -0.514 17.182
|
|
clock uncertainty -0.071 17.111
|
|
SLICE_X62Y167 FDCE (Recov_fdce_C_CLR) -0.543 16.568 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_B_reg[208][0]
|
|
-------------------------------------------------------------------
|
|
required time 16.568
|
|
arrival time -8.480
|
|
-------------------------------------------------------------------
|
|
slack 8.089
|
|
|
|
Slack (MET) : 8.089ns (required time - arrival time)
|
|
Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_cnt_reg[3]/C
|
|
(rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_B_reg[208][11]/CLR
|
|
(recovery check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Path Group: **async_default**
|
|
Path Type: Recovery (Max at Slow Process Corner)
|
|
Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns)
|
|
Data Path Delay: 10.967ns (logic 0.668ns (6.091%) route 10.299ns (93.909%))
|
|
Logic Levels: 1 (LUT5=1)
|
|
Clock Path Skew: -0.331ns (DCD - SCD + CPR)
|
|
Destination Clock Delay (DCD): -2.305ns = ( 17.695 - 20.000 )
|
|
Source Clock Delay (SCD): -2.488ns
|
|
Clock Pessimism Removal (CPR): -0.514ns
|
|
Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Discrete Jitter (DJ): 0.122ns
|
|
Phase Error (PE): 0.000ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock sys_clk rise edge) 0.000 0.000 r
|
|
clock source latency -6.275 -6.275
|
|
propagated clock network latency
|
|
3.788 -2.488
|
|
SLICE_X112Y65 FDCE 0.000 -2.488 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_cnt_reg[3]/C
|
|
SLICE_X112Y65 FDCE (Prop_fdce_C_Q) 0.518 -1.970 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_cnt_reg[3]/Q
|
|
net (fo=5, routed) 1.052 -0.917 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/srst_cnt_reg[3]
|
|
SLICE_X112Y66 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/p_s1[23]_i_9/I4
|
|
SLICE_X112Y66 LUT5 (Prop_lut5_I4_O) 0.150 -0.767 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/p_s1[23]_i_9/O
|
|
net (fo=24670, routed) 9.247 8.480 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/delay_reg[1]
|
|
SLICE_X62Y167 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_B_reg[208][11]/CLR
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock sys_clk rise edge) 20.000 20.000 r
|
|
clock source latency -5.674 14.326
|
|
propagated clock network latency
|
|
3.370 17.695
|
|
clock pessimism -0.514 17.182
|
|
clock uncertainty -0.071 17.111
|
|
SLICE_X62Y167 FDCE (Recov_fdce_C_CLR) -0.543 16.568 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_B_reg[208][11]
|
|
-------------------------------------------------------------------
|
|
required time 16.568
|
|
arrival time -8.480
|
|
-------------------------------------------------------------------
|
|
slack 8.089
|
|
|
|
Slack (MET) : 8.148ns (required time - arrival time)
|
|
Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_cnt_reg[1]/C
|
|
(rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_A_reg[208][10]/CLR
|
|
(recovery check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Path Group: **async_default**
|
|
Path Type: Recovery (Max at Slow Process Corner)
|
|
Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns)
|
|
Data Path Delay: 10.907ns (logic 0.670ns (6.143%) route 10.237ns (93.857%))
|
|
Logic Levels: 1 (LUT5=1)
|
|
Clock Path Skew: -0.331ns (DCD - SCD + CPR)
|
|
Destination Clock Delay (DCD): -2.305ns = ( 17.695 - 20.000 )
|
|
Source Clock Delay (SCD): -2.488ns
|
|
Clock Pessimism Removal (CPR): -0.514ns
|
|
Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Discrete Jitter (DJ): 0.122ns
|
|
Phase Error (PE): 0.000ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock sys_clk rise edge) 0.000 0.000 r
|
|
clock source latency -6.275 -6.275
|
|
propagated clock network latency
|
|
3.788 -2.488
|
|
SLICE_X112Y65 FDCE 0.000 -2.488 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_cnt_reg[1]/C
|
|
SLICE_X112Y65 FDCE (Prop_fdce_C_Q) 0.518 -1.970 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_cnt_reg[1]/Q
|
|
net (fo=7, routed) 0.990 -0.979 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/srst_cnt_reg[1]
|
|
SLICE_X112Y66 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/p_s1[23]_i_9/I1
|
|
SLICE_X112Y66 LUT5 (Prop_lut5_I1_O) 0.152 -0.827 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/p_s1[23]_i_9/O
|
|
net (fo=24670, routed) 9.247 8.420 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/delay_reg[1]
|
|
SLICE_X62Y167 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_A_reg[208][10]/CLR
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock sys_clk rise edge) 20.000 20.000 r
|
|
clock source latency -5.674 14.326
|
|
propagated clock network latency
|
|
3.370 17.695
|
|
clock pessimism -0.514 17.182
|
|
clock uncertainty -0.071 17.111
|
|
SLICE_X62Y167 FDCE (Recov_fdce_C_CLR) -0.543 16.568 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_A_reg[208][10]
|
|
-------------------------------------------------------------------
|
|
required time 16.568
|
|
arrival time -8.420
|
|
-------------------------------------------------------------------
|
|
slack 8.148
|
|
|
|
Slack (MET) : 8.148ns (required time - arrival time)
|
|
Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_cnt_reg[1]/C
|
|
(rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_B_reg[208][0]/CLR
|
|
(recovery check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Path Group: **async_default**
|
|
Path Type: Recovery (Max at Slow Process Corner)
|
|
Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns)
|
|
Data Path Delay: 10.907ns (logic 0.670ns (6.143%) route 10.237ns (93.857%))
|
|
Logic Levels: 1 (LUT5=1)
|
|
Clock Path Skew: -0.331ns (DCD - SCD + CPR)
|
|
Destination Clock Delay (DCD): -2.305ns = ( 17.695 - 20.000 )
|
|
Source Clock Delay (SCD): -2.488ns
|
|
Clock Pessimism Removal (CPR): -0.514ns
|
|
Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Discrete Jitter (DJ): 0.122ns
|
|
Phase Error (PE): 0.000ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock sys_clk rise edge) 0.000 0.000 r
|
|
clock source latency -6.275 -6.275
|
|
propagated clock network latency
|
|
3.788 -2.488
|
|
SLICE_X112Y65 FDCE 0.000 -2.488 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_cnt_reg[1]/C
|
|
SLICE_X112Y65 FDCE (Prop_fdce_C_Q) 0.518 -1.970 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_cnt_reg[1]/Q
|
|
net (fo=7, routed) 0.990 -0.979 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/srst_cnt_reg[1]
|
|
SLICE_X112Y66 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/p_s1[23]_i_9/I1
|
|
SLICE_X112Y66 LUT5 (Prop_lut5_I1_O) 0.152 -0.827 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/p_s1[23]_i_9/O
|
|
net (fo=24670, routed) 9.247 8.420 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/delay_reg[1]
|
|
SLICE_X62Y167 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_B_reg[208][0]/CLR
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock sys_clk rise edge) 20.000 20.000 r
|
|
clock source latency -5.674 14.326
|
|
propagated clock network latency
|
|
3.370 17.695
|
|
clock pessimism -0.514 17.182
|
|
clock uncertainty -0.071 17.111
|
|
SLICE_X62Y167 FDCE (Recov_fdce_C_CLR) -0.543 16.568 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_B_reg[208][0]
|
|
-------------------------------------------------------------------
|
|
required time 16.568
|
|
arrival time -8.420
|
|
-------------------------------------------------------------------
|
|
slack 8.148
|
|
|
|
Slack (MET) : 8.148ns (required time - arrival time)
|
|
Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_cnt_reg[1]/C
|
|
(rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_B_reg[208][11]/CLR
|
|
(recovery check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Path Group: **async_default**
|
|
Path Type: Recovery (Max at Slow Process Corner)
|
|
Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns)
|
|
Data Path Delay: 10.907ns (logic 0.670ns (6.143%) route 10.237ns (93.857%))
|
|
Logic Levels: 1 (LUT5=1)
|
|
Clock Path Skew: -0.331ns (DCD - SCD + CPR)
|
|
Destination Clock Delay (DCD): -2.305ns = ( 17.695 - 20.000 )
|
|
Source Clock Delay (SCD): -2.488ns
|
|
Clock Pessimism Removal (CPR): -0.514ns
|
|
Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Discrete Jitter (DJ): 0.122ns
|
|
Phase Error (PE): 0.000ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock sys_clk rise edge) 0.000 0.000 r
|
|
clock source latency -6.275 -6.275
|
|
propagated clock network latency
|
|
3.788 -2.488
|
|
SLICE_X112Y65 FDCE 0.000 -2.488 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_cnt_reg[1]/C
|
|
SLICE_X112Y65 FDCE (Prop_fdce_C_Q) 0.518 -1.970 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_cnt_reg[1]/Q
|
|
net (fo=7, routed) 0.990 -0.979 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/srst_cnt_reg[1]
|
|
SLICE_X112Y66 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/p_s1[23]_i_9/I1
|
|
SLICE_X112Y66 LUT5 (Prop_lut5_I1_O) 0.152 -0.827 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/p_s1[23]_i_9/O
|
|
net (fo=24670, routed) 9.247 8.420 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/delay_reg[1]
|
|
SLICE_X62Y167 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_B_reg[208][11]/CLR
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock sys_clk rise edge) 20.000 20.000 r
|
|
clock source latency -5.674 14.326
|
|
propagated clock network latency
|
|
3.370 17.695
|
|
clock pessimism -0.514 17.182
|
|
clock uncertainty -0.071 17.111
|
|
SLICE_X62Y167 FDCE (Recov_fdce_C_CLR) -0.543 16.568 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_B_reg[208][11]
|
|
-------------------------------------------------------------------
|
|
required time 16.568
|
|
arrival time -8.420
|
|
-------------------------------------------------------------------
|
|
slack 8.148
|
|
|
|
Slack (MET) : 8.172ns (required time - arrival time)
|
|
Source: pll_clk.u_rst_sys/delay_reg[1]/C
|
|
(rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_A_reg[208][10]/CLR
|
|
(recovery check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Path Group: **async_default**
|
|
Path Type: Recovery (Max at Slow Process Corner)
|
|
Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns)
|
|
Data Path Delay: 10.891ns (logic 0.608ns (5.582%) route 10.283ns (94.418%))
|
|
Logic Levels: 1 (LUT5=1)
|
|
Clock Path Skew: -0.323ns (DCD - SCD + CPR)
|
|
Destination Clock Delay (DCD): -2.305ns = ( 17.695 - 20.000 )
|
|
Source Clock Delay (SCD): -2.496ns
|
|
Clock Pessimism Removal (CPR): -0.514ns
|
|
Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Discrete Jitter (DJ): 0.122ns
|
|
Phase Error (PE): 0.000ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock sys_clk rise edge) 0.000 0.000 r
|
|
clock source latency -6.275 -6.275
|
|
propagated clock network latency
|
|
3.780 -2.496
|
|
SLICE_X106Y69 FDCE 0.000 -2.496 r pll_clk.u_rst_sys/delay_reg[1]/C
|
|
SLICE_X106Y69 FDCE (Prop_fdce_C_Q) 0.456 -2.040 r pll_clk.u_rst_sys/delay_reg[1]/Q
|
|
net (fo=125, routed) 1.036 -1.003 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/valid_sr_reg[6][0]
|
|
SLICE_X112Y66 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/p_s1[23]_i_9/I0
|
|
SLICE_X112Y66 LUT5 (Prop_lut5_I0_O) 0.152 -0.851 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/p_s1[23]_i_9/O
|
|
net (fo=24670, routed) 9.247 8.396 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/delay_reg[1]
|
|
SLICE_X62Y167 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_A_reg[208][10]/CLR
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock sys_clk rise edge) 20.000 20.000 r
|
|
clock source latency -5.674 14.326
|
|
propagated clock network latency
|
|
3.370 17.695
|
|
clock pessimism -0.514 17.182
|
|
clock uncertainty -0.071 17.111
|
|
SLICE_X62Y167 FDCE (Recov_fdce_C_CLR) -0.543 16.568 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_A_reg[208][10]
|
|
-------------------------------------------------------------------
|
|
required time 16.568
|
|
arrival time -8.396
|
|
-------------------------------------------------------------------
|
|
slack 8.172
|
|
|
|
Slack (MET) : 8.172ns (required time - arrival time)
|
|
Source: pll_clk.u_rst_sys/delay_reg[1]/C
|
|
(rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_B_reg[208][0]/CLR
|
|
(recovery check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Path Group: **async_default**
|
|
Path Type: Recovery (Max at Slow Process Corner)
|
|
Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns)
|
|
Data Path Delay: 10.891ns (logic 0.608ns (5.582%) route 10.283ns (94.418%))
|
|
Logic Levels: 1 (LUT5=1)
|
|
Clock Path Skew: -0.323ns (DCD - SCD + CPR)
|
|
Destination Clock Delay (DCD): -2.305ns = ( 17.695 - 20.000 )
|
|
Source Clock Delay (SCD): -2.496ns
|
|
Clock Pessimism Removal (CPR): -0.514ns
|
|
Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Discrete Jitter (DJ): 0.122ns
|
|
Phase Error (PE): 0.000ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock sys_clk rise edge) 0.000 0.000 r
|
|
clock source latency -6.275 -6.275
|
|
propagated clock network latency
|
|
3.780 -2.496
|
|
SLICE_X106Y69 FDCE 0.000 -2.496 r pll_clk.u_rst_sys/delay_reg[1]/C
|
|
SLICE_X106Y69 FDCE (Prop_fdce_C_Q) 0.456 -2.040 r pll_clk.u_rst_sys/delay_reg[1]/Q
|
|
net (fo=125, routed) 1.036 -1.003 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/valid_sr_reg[6][0]
|
|
SLICE_X112Y66 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/p_s1[23]_i_9/I0
|
|
SLICE_X112Y66 LUT5 (Prop_lut5_I0_O) 0.152 -0.851 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/p_s1[23]_i_9/O
|
|
net (fo=24670, routed) 9.247 8.396 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/delay_reg[1]
|
|
SLICE_X62Y167 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_B_reg[208][0]/CLR
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock sys_clk rise edge) 20.000 20.000 r
|
|
clock source latency -5.674 14.326
|
|
propagated clock network latency
|
|
3.370 17.695
|
|
clock pessimism -0.514 17.182
|
|
clock uncertainty -0.071 17.111
|
|
SLICE_X62Y167 FDCE (Recov_fdce_C_CLR) -0.543 16.568 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_B_reg[208][0]
|
|
-------------------------------------------------------------------
|
|
required time 16.568
|
|
arrival time -8.396
|
|
-------------------------------------------------------------------
|
|
slack 8.172
|
|
|
|
Slack (MET) : 8.172ns (required time - arrival time)
|
|
Source: pll_clk.u_rst_sys/delay_reg[1]/C
|
|
(rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_B_reg[208][11]/CLR
|
|
(recovery check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Path Group: **async_default**
|
|
Path Type: Recovery (Max at Slow Process Corner)
|
|
Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns)
|
|
Data Path Delay: 10.891ns (logic 0.608ns (5.582%) route 10.283ns (94.418%))
|
|
Logic Levels: 1 (LUT5=1)
|
|
Clock Path Skew: -0.323ns (DCD - SCD + CPR)
|
|
Destination Clock Delay (DCD): -2.305ns = ( 17.695 - 20.000 )
|
|
Source Clock Delay (SCD): -2.496ns
|
|
Clock Pessimism Removal (CPR): -0.514ns
|
|
Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Discrete Jitter (DJ): 0.122ns
|
|
Phase Error (PE): 0.000ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock sys_clk rise edge) 0.000 0.000 r
|
|
clock source latency -6.275 -6.275
|
|
propagated clock network latency
|
|
3.780 -2.496
|
|
SLICE_X106Y69 FDCE 0.000 -2.496 r pll_clk.u_rst_sys/delay_reg[1]/C
|
|
SLICE_X106Y69 FDCE (Prop_fdce_C_Q) 0.456 -2.040 r pll_clk.u_rst_sys/delay_reg[1]/Q
|
|
net (fo=125, routed) 1.036 -1.003 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/valid_sr_reg[6][0]
|
|
SLICE_X112Y66 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/p_s1[23]_i_9/I0
|
|
SLICE_X112Y66 LUT5 (Prop_lut5_I0_O) 0.152 -0.851 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/p_s1[23]_i_9/O
|
|
net (fo=24670, routed) 9.247 8.396 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/delay_reg[1]
|
|
SLICE_X62Y167 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_B_reg[208][11]/CLR
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock sys_clk rise edge) 20.000 20.000 r
|
|
clock source latency -5.674 14.326
|
|
propagated clock network latency
|
|
3.370 17.695
|
|
clock pessimism -0.514 17.182
|
|
clock uncertainty -0.071 17.111
|
|
SLICE_X62Y167 FDCE (Recov_fdce_C_CLR) -0.543 16.568 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_B_reg[208][11]
|
|
-------------------------------------------------------------------
|
|
required time 16.568
|
|
arrival time -8.396
|
|
-------------------------------------------------------------------
|
|
slack 8.172
|
|
|
|
Slack (MET) : 8.372ns (required time - arrival time)
|
|
Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_cnt_reg[3]/C
|
|
(rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_A_reg[202][2]/CLR
|
|
(recovery check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Path Group: **async_default**
|
|
Path Type: Recovery (Max at Slow Process Corner)
|
|
Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns)
|
|
Data Path Delay: 10.601ns (logic 0.668ns (6.301%) route 9.933ns (93.699%))
|
|
Logic Levels: 1 (LUT5=1)
|
|
Clock Path Skew: -0.327ns (DCD - SCD + CPR)
|
|
Destination Clock Delay (DCD): -2.301ns = ( 17.699 - 20.000 )
|
|
Source Clock Delay (SCD): -2.488ns
|
|
Clock Pessimism Removal (CPR): -0.514ns
|
|
Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Discrete Jitter (DJ): 0.122ns
|
|
Phase Error (PE): 0.000ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock sys_clk rise edge) 0.000 0.000 r
|
|
clock source latency -6.275 -6.275
|
|
propagated clock network latency
|
|
3.788 -2.488
|
|
SLICE_X112Y65 FDCE 0.000 -2.488 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_cnt_reg[3]/C
|
|
SLICE_X112Y65 FDCE (Prop_fdce_C_Q) 0.518 -1.970 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_cnt_reg[3]/Q
|
|
net (fo=5, routed) 1.052 -0.917 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/srst_cnt_reg[3]
|
|
SLICE_X112Y66 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/p_s1[23]_i_9/I4
|
|
SLICE_X112Y66 LUT5 (Prop_lut5_I4_O) 0.150 -0.767 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/p_s1[23]_i_9/O
|
|
net (fo=24670, routed) 8.881 8.114 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/delay_reg[1]
|
|
SLICE_X61Y167 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_A_reg[202][2]/CLR
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock sys_clk rise edge) 20.000 20.000 r
|
|
clock source latency -5.674 14.326
|
|
propagated clock network latency
|
|
3.374 17.699
|
|
clock pessimism -0.514 17.186
|
|
clock uncertainty -0.071 17.115
|
|
SLICE_X61Y167 FDCE (Recov_fdce_C_CLR) -0.629 16.486 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_A_reg[202][2]
|
|
-------------------------------------------------------------------
|
|
required time 16.486
|
|
arrival time -8.114
|
|
-------------------------------------------------------------------
|
|
slack 8.372
|
|
|
|
Slack (MET) : 8.372ns (required time - arrival time)
|
|
Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_cnt_reg[3]/C
|
|
(rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_A_reg[202][9]/CLR
|
|
(recovery check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Path Group: **async_default**
|
|
Path Type: Recovery (Max at Slow Process Corner)
|
|
Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns)
|
|
Data Path Delay: 10.601ns (logic 0.668ns (6.301%) route 9.933ns (93.699%))
|
|
Logic Levels: 1 (LUT5=1)
|
|
Clock Path Skew: -0.327ns (DCD - SCD + CPR)
|
|
Destination Clock Delay (DCD): -2.301ns = ( 17.699 - 20.000 )
|
|
Source Clock Delay (SCD): -2.488ns
|
|
Clock Pessimism Removal (CPR): -0.514ns
|
|
Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Discrete Jitter (DJ): 0.122ns
|
|
Phase Error (PE): 0.000ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock sys_clk rise edge) 0.000 0.000 r
|
|
clock source latency -6.275 -6.275
|
|
propagated clock network latency
|
|
3.788 -2.488
|
|
SLICE_X112Y65 FDCE 0.000 -2.488 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_cnt_reg[3]/C
|
|
SLICE_X112Y65 FDCE (Prop_fdce_C_Q) 0.518 -1.970 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_cnt_reg[3]/Q
|
|
net (fo=5, routed) 1.052 -0.917 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/srst_cnt_reg[3]
|
|
SLICE_X112Y66 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/p_s1[23]_i_9/I4
|
|
SLICE_X112Y66 LUT5 (Prop_lut5_I4_O) 0.150 -0.767 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/p_s1[23]_i_9/O
|
|
net (fo=24670, routed) 8.881 8.114 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/delay_reg[1]
|
|
SLICE_X61Y167 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_A_reg[202][9]/CLR
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock sys_clk rise edge) 20.000 20.000 r
|
|
clock source latency -5.674 14.326
|
|
propagated clock network latency
|
|
3.374 17.699
|
|
clock pessimism -0.514 17.186
|
|
clock uncertainty -0.071 17.115
|
|
SLICE_X61Y167 FDCE (Recov_fdce_C_CLR) -0.629 16.486 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_A_reg[202][9]
|
|
-------------------------------------------------------------------
|
|
required time 16.486
|
|
arrival time -8.114
|
|
-------------------------------------------------------------------
|
|
slack 8.372
|
|
|
|
Slack (MET) : 8.372ns (required time - arrival time)
|
|
Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_cnt_reg[3]/C
|
|
(rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_B_reg[202][0]/CLR
|
|
(recovery check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Path Group: **async_default**
|
|
Path Type: Recovery (Max at Slow Process Corner)
|
|
Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns)
|
|
Data Path Delay: 10.601ns (logic 0.668ns (6.301%) route 9.933ns (93.699%))
|
|
Logic Levels: 1 (LUT5=1)
|
|
Clock Path Skew: -0.327ns (DCD - SCD + CPR)
|
|
Destination Clock Delay (DCD): -2.301ns = ( 17.699 - 20.000 )
|
|
Source Clock Delay (SCD): -2.488ns
|
|
Clock Pessimism Removal (CPR): -0.514ns
|
|
Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Discrete Jitter (DJ): 0.122ns
|
|
Phase Error (PE): 0.000ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock sys_clk rise edge) 0.000 0.000 r
|
|
clock source latency -6.275 -6.275
|
|
propagated clock network latency
|
|
3.788 -2.488
|
|
SLICE_X112Y65 FDCE 0.000 -2.488 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_cnt_reg[3]/C
|
|
SLICE_X112Y65 FDCE (Prop_fdce_C_Q) 0.518 -1.970 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_cnt_reg[3]/Q
|
|
net (fo=5, routed) 1.052 -0.917 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/srst_cnt_reg[3]
|
|
SLICE_X112Y66 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/p_s1[23]_i_9/I4
|
|
SLICE_X112Y66 LUT5 (Prop_lut5_I4_O) 0.150 -0.767 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/p_s1[23]_i_9/O
|
|
net (fo=24670, routed) 8.881 8.114 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/delay_reg[1]
|
|
SLICE_X61Y167 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_B_reg[202][0]/CLR
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock sys_clk rise edge) 20.000 20.000 r
|
|
clock source latency -5.674 14.326
|
|
propagated clock network latency
|
|
3.374 17.699
|
|
clock pessimism -0.514 17.186
|
|
clock uncertainty -0.071 17.115
|
|
SLICE_X61Y167 FDCE (Recov_fdce_C_CLR) -0.629 16.486 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_B_reg[202][0]
|
|
-------------------------------------------------------------------
|
|
required time 16.486
|
|
arrival time -8.114
|
|
-------------------------------------------------------------------
|
|
slack 8.372
|
|
|
|
Slack (MET) : 8.372ns (required time - arrival time)
|
|
Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_cnt_reg[3]/C
|
|
(rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_B_reg[202][11]/CLR
|
|
(recovery check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Path Group: **async_default**
|
|
Path Type: Recovery (Max at Slow Process Corner)
|
|
Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns)
|
|
Data Path Delay: 10.601ns (logic 0.668ns (6.301%) route 9.933ns (93.699%))
|
|
Logic Levels: 1 (LUT5=1)
|
|
Clock Path Skew: -0.327ns (DCD - SCD + CPR)
|
|
Destination Clock Delay (DCD): -2.301ns = ( 17.699 - 20.000 )
|
|
Source Clock Delay (SCD): -2.488ns
|
|
Clock Pessimism Removal (CPR): -0.514ns
|
|
Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Discrete Jitter (DJ): 0.122ns
|
|
Phase Error (PE): 0.000ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock sys_clk rise edge) 0.000 0.000 r
|
|
clock source latency -6.275 -6.275
|
|
propagated clock network latency
|
|
3.788 -2.488
|
|
SLICE_X112Y65 FDCE 0.000 -2.488 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_cnt_reg[3]/C
|
|
SLICE_X112Y65 FDCE (Prop_fdce_C_Q) 0.518 -1.970 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_cnt_reg[3]/Q
|
|
net (fo=5, routed) 1.052 -0.917 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/srst_cnt_reg[3]
|
|
SLICE_X112Y66 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/p_s1[23]_i_9/I4
|
|
SLICE_X112Y66 LUT5 (Prop_lut5_I4_O) 0.150 -0.767 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/p_s1[23]_i_9/O
|
|
net (fo=24670, routed) 8.881 8.114 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/delay_reg[1]
|
|
SLICE_X61Y167 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_B_reg[202][11]/CLR
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock sys_clk rise edge) 20.000 20.000 r
|
|
clock source latency -5.674 14.326
|
|
propagated clock network latency
|
|
3.374 17.699
|
|
clock pessimism -0.514 17.186
|
|
clock uncertainty -0.071 17.115
|
|
SLICE_X61Y167 FDCE (Recov_fdce_C_CLR) -0.629 16.486 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_B_reg[202][11]
|
|
-------------------------------------------------------------------
|
|
required time 16.486
|
|
arrival time -8.114
|
|
-------------------------------------------------------------------
|
|
slack 8.372
|
|
|
|
Slack (MET) : 8.372ns (required time - arrival time)
|
|
Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_cnt_reg[3]/C
|
|
(rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_B_reg[202][4]/CLR
|
|
(recovery check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Path Group: **async_default**
|
|
Path Type: Recovery (Max at Slow Process Corner)
|
|
Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns)
|
|
Data Path Delay: 10.601ns (logic 0.668ns (6.301%) route 9.933ns (93.699%))
|
|
Logic Levels: 1 (LUT5=1)
|
|
Clock Path Skew: -0.327ns (DCD - SCD + CPR)
|
|
Destination Clock Delay (DCD): -2.301ns = ( 17.699 - 20.000 )
|
|
Source Clock Delay (SCD): -2.488ns
|
|
Clock Pessimism Removal (CPR): -0.514ns
|
|
Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Discrete Jitter (DJ): 0.122ns
|
|
Phase Error (PE): 0.000ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock sys_clk rise edge) 0.000 0.000 r
|
|
clock source latency -6.275 -6.275
|
|
propagated clock network latency
|
|
3.788 -2.488
|
|
SLICE_X112Y65 FDCE 0.000 -2.488 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_cnt_reg[3]/C
|
|
SLICE_X112Y65 FDCE (Prop_fdce_C_Q) 0.518 -1.970 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_cnt_reg[3]/Q
|
|
net (fo=5, routed) 1.052 -0.917 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/srst_cnt_reg[3]
|
|
SLICE_X112Y66 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/p_s1[23]_i_9/I4
|
|
SLICE_X112Y66 LUT5 (Prop_lut5_I4_O) 0.150 -0.767 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/p_s1[23]_i_9/O
|
|
net (fo=24670, routed) 8.881 8.114 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/delay_reg[1]
|
|
SLICE_X61Y167 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_B_reg[202][4]/CLR
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock sys_clk rise edge) 20.000 20.000 r
|
|
clock source latency -5.674 14.326
|
|
propagated clock network latency
|
|
3.374 17.699
|
|
clock pessimism -0.514 17.186
|
|
clock uncertainty -0.071 17.115
|
|
SLICE_X61Y167 FDCE (Recov_fdce_C_CLR) -0.629 16.486 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_B_reg[202][4]
|
|
-------------------------------------------------------------------
|
|
required time 16.486
|
|
arrival time -8.114
|
|
-------------------------------------------------------------------
|
|
slack 8.372
|
|
|
|
Slack (MET) : 8.421ns (required time - arrival time)
|
|
Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_cnt_reg[0]/C
|
|
(rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_B_reg[198][0]/CLR
|
|
(recovery check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Path Group: **async_default**
|
|
Path Type: Recovery (Max at Slow Process Corner)
|
|
Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns)
|
|
Data Path Delay: 10.548ns (logic 0.668ns (6.333%) route 9.880ns (93.667%))
|
|
Logic Levels: 1 (LUT5=1)
|
|
Clock Path Skew: -0.331ns (DCD - SCD + CPR)
|
|
Destination Clock Delay (DCD): -2.305ns = ( 17.695 - 20.000 )
|
|
Source Clock Delay (SCD): -2.488ns
|
|
Clock Pessimism Removal (CPR): -0.514ns
|
|
Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Discrete Jitter (DJ): 0.122ns
|
|
Phase Error (PE): 0.000ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock sys_clk rise edge) 0.000 0.000 r
|
|
clock source latency -6.275 -6.275
|
|
propagated clock network latency
|
|
3.788 -2.488
|
|
SLICE_X112Y65 FDCE 0.000 -2.488 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_cnt_reg[0]/C
|
|
SLICE_X112Y65 FDCE (Prop_fdce_C_Q) 0.518 -1.970 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_cnt_reg[0]/Q
|
|
net (fo=8, routed) 0.633 -1.336 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/srst_cnt_reg[0]
|
|
SLICE_X112Y66 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/p_s1[23]_i_9/I2
|
|
SLICE_X112Y66 LUT5 (Prop_lut5_I2_O) 0.150 -1.186 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/p_s1[23]_i_9/O
|
|
net (fo=24670, routed) 9.247 8.061 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/delay_reg[1]
|
|
SLICE_X63Y167 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_B_reg[198][0]/CLR
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock sys_clk rise edge) 20.000 20.000 r
|
|
clock source latency -5.674 14.326
|
|
propagated clock network latency
|
|
3.370 17.695
|
|
clock pessimism -0.514 17.182
|
|
clock uncertainty -0.071 17.111
|
|
SLICE_X63Y167 FDCE (Recov_fdce_C_CLR) -0.629 16.482 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_B_reg[198][0]
|
|
-------------------------------------------------------------------
|
|
required time 16.482
|
|
arrival time -8.061
|
|
-------------------------------------------------------------------
|
|
slack 8.421
|
|
|
|
Slack (MET) : 8.432ns (required time - arrival time)
|
|
Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_cnt_reg[1]/C
|
|
(rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_A_reg[202][2]/CLR
|
|
(recovery check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Path Group: **async_default**
|
|
Path Type: Recovery (Max at Slow Process Corner)
|
|
Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns)
|
|
Data Path Delay: 10.541ns (logic 0.670ns (6.356%) route 9.871ns (93.644%))
|
|
Logic Levels: 1 (LUT5=1)
|
|
Clock Path Skew: -0.327ns (DCD - SCD + CPR)
|
|
Destination Clock Delay (DCD): -2.301ns = ( 17.699 - 20.000 )
|
|
Source Clock Delay (SCD): -2.488ns
|
|
Clock Pessimism Removal (CPR): -0.514ns
|
|
Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Discrete Jitter (DJ): 0.122ns
|
|
Phase Error (PE): 0.000ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock sys_clk rise edge) 0.000 0.000 r
|
|
clock source latency -6.275 -6.275
|
|
propagated clock network latency
|
|
3.788 -2.488
|
|
SLICE_X112Y65 FDCE 0.000 -2.488 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_cnt_reg[1]/C
|
|
SLICE_X112Y65 FDCE (Prop_fdce_C_Q) 0.518 -1.970 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_cnt_reg[1]/Q
|
|
net (fo=7, routed) 0.990 -0.979 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/srst_cnt_reg[1]
|
|
SLICE_X112Y66 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/p_s1[23]_i_9/I1
|
|
SLICE_X112Y66 LUT5 (Prop_lut5_I1_O) 0.152 -0.827 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/p_s1[23]_i_9/O
|
|
net (fo=24670, routed) 8.881 8.054 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/delay_reg[1]
|
|
SLICE_X61Y167 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_A_reg[202][2]/CLR
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock sys_clk rise edge) 20.000 20.000 r
|
|
clock source latency -5.674 14.326
|
|
propagated clock network latency
|
|
3.374 17.699
|
|
clock pessimism -0.514 17.186
|
|
clock uncertainty -0.071 17.115
|
|
SLICE_X61Y167 FDCE (Recov_fdce_C_CLR) -0.629 16.486 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_A_reg[202][2]
|
|
-------------------------------------------------------------------
|
|
required time 16.486
|
|
arrival time -8.054
|
|
-------------------------------------------------------------------
|
|
slack 8.432
|
|
|
|
Slack (MET) : 8.432ns (required time - arrival time)
|
|
Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_cnt_reg[1]/C
|
|
(rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_A_reg[202][9]/CLR
|
|
(recovery check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Path Group: **async_default**
|
|
Path Type: Recovery (Max at Slow Process Corner)
|
|
Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns)
|
|
Data Path Delay: 10.541ns (logic 0.670ns (6.356%) route 9.871ns (93.644%))
|
|
Logic Levels: 1 (LUT5=1)
|
|
Clock Path Skew: -0.327ns (DCD - SCD + CPR)
|
|
Destination Clock Delay (DCD): -2.301ns = ( 17.699 - 20.000 )
|
|
Source Clock Delay (SCD): -2.488ns
|
|
Clock Pessimism Removal (CPR): -0.514ns
|
|
Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Discrete Jitter (DJ): 0.122ns
|
|
Phase Error (PE): 0.000ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock sys_clk rise edge) 0.000 0.000 r
|
|
clock source latency -6.275 -6.275
|
|
propagated clock network latency
|
|
3.788 -2.488
|
|
SLICE_X112Y65 FDCE 0.000 -2.488 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_cnt_reg[1]/C
|
|
SLICE_X112Y65 FDCE (Prop_fdce_C_Q) 0.518 -1.970 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_cnt_reg[1]/Q
|
|
net (fo=7, routed) 0.990 -0.979 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/srst_cnt_reg[1]
|
|
SLICE_X112Y66 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/p_s1[23]_i_9/I1
|
|
SLICE_X112Y66 LUT5 (Prop_lut5_I1_O) 0.152 -0.827 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/p_s1[23]_i_9/O
|
|
net (fo=24670, routed) 8.881 8.054 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/delay_reg[1]
|
|
SLICE_X61Y167 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_A_reg[202][9]/CLR
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock sys_clk rise edge) 20.000 20.000 r
|
|
clock source latency -5.674 14.326
|
|
propagated clock network latency
|
|
3.374 17.699
|
|
clock pessimism -0.514 17.186
|
|
clock uncertainty -0.071 17.115
|
|
SLICE_X61Y167 FDCE (Recov_fdce_C_CLR) -0.629 16.486 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_A_reg[202][9]
|
|
-------------------------------------------------------------------
|
|
required time 16.486
|
|
arrival time -8.054
|
|
-------------------------------------------------------------------
|
|
slack 8.432
|
|
|
|
Slack (MET) : 8.432ns (required time - arrival time)
|
|
Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_cnt_reg[1]/C
|
|
(rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_B_reg[202][0]/CLR
|
|
(recovery check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Path Group: **async_default**
|
|
Path Type: Recovery (Max at Slow Process Corner)
|
|
Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns)
|
|
Data Path Delay: 10.541ns (logic 0.670ns (6.356%) route 9.871ns (93.644%))
|
|
Logic Levels: 1 (LUT5=1)
|
|
Clock Path Skew: -0.327ns (DCD - SCD + CPR)
|
|
Destination Clock Delay (DCD): -2.301ns = ( 17.699 - 20.000 )
|
|
Source Clock Delay (SCD): -2.488ns
|
|
Clock Pessimism Removal (CPR): -0.514ns
|
|
Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Discrete Jitter (DJ): 0.122ns
|
|
Phase Error (PE): 0.000ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock sys_clk rise edge) 0.000 0.000 r
|
|
clock source latency -6.275 -6.275
|
|
propagated clock network latency
|
|
3.788 -2.488
|
|
SLICE_X112Y65 FDCE 0.000 -2.488 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_cnt_reg[1]/C
|
|
SLICE_X112Y65 FDCE (Prop_fdce_C_Q) 0.518 -1.970 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_cnt_reg[1]/Q
|
|
net (fo=7, routed) 0.990 -0.979 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/srst_cnt_reg[1]
|
|
SLICE_X112Y66 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/p_s1[23]_i_9/I1
|
|
SLICE_X112Y66 LUT5 (Prop_lut5_I1_O) 0.152 -0.827 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/p_s1[23]_i_9/O
|
|
net (fo=24670, routed) 8.881 8.054 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/delay_reg[1]
|
|
SLICE_X61Y167 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_B_reg[202][0]/CLR
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock sys_clk rise edge) 20.000 20.000 r
|
|
clock source latency -5.674 14.326
|
|
propagated clock network latency
|
|
3.374 17.699
|
|
clock pessimism -0.514 17.186
|
|
clock uncertainty -0.071 17.115
|
|
SLICE_X61Y167 FDCE (Recov_fdce_C_CLR) -0.629 16.486 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_B_reg[202][0]
|
|
-------------------------------------------------------------------
|
|
required time 16.486
|
|
arrival time -8.054
|
|
-------------------------------------------------------------------
|
|
slack 8.432
|
|
|
|
Slack (MET) : 8.432ns (required time - arrival time)
|
|
Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_cnt_reg[1]/C
|
|
(rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_B_reg[202][11]/CLR
|
|
(recovery check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Path Group: **async_default**
|
|
Path Type: Recovery (Max at Slow Process Corner)
|
|
Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns)
|
|
Data Path Delay: 10.541ns (logic 0.670ns (6.356%) route 9.871ns (93.644%))
|
|
Logic Levels: 1 (LUT5=1)
|
|
Clock Path Skew: -0.327ns (DCD - SCD + CPR)
|
|
Destination Clock Delay (DCD): -2.301ns = ( 17.699 - 20.000 )
|
|
Source Clock Delay (SCD): -2.488ns
|
|
Clock Pessimism Removal (CPR): -0.514ns
|
|
Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Discrete Jitter (DJ): 0.122ns
|
|
Phase Error (PE): 0.000ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock sys_clk rise edge) 0.000 0.000 r
|
|
clock source latency -6.275 -6.275
|
|
propagated clock network latency
|
|
3.788 -2.488
|
|
SLICE_X112Y65 FDCE 0.000 -2.488 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_cnt_reg[1]/C
|
|
SLICE_X112Y65 FDCE (Prop_fdce_C_Q) 0.518 -1.970 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_cnt_reg[1]/Q
|
|
net (fo=7, routed) 0.990 -0.979 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/srst_cnt_reg[1]
|
|
SLICE_X112Y66 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/p_s1[23]_i_9/I1
|
|
SLICE_X112Y66 LUT5 (Prop_lut5_I1_O) 0.152 -0.827 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/p_s1[23]_i_9/O
|
|
net (fo=24670, routed) 8.881 8.054 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/delay_reg[1]
|
|
SLICE_X61Y167 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_B_reg[202][11]/CLR
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock sys_clk rise edge) 20.000 20.000 r
|
|
clock source latency -5.674 14.326
|
|
propagated clock network latency
|
|
3.374 17.699
|
|
clock pessimism -0.514 17.186
|
|
clock uncertainty -0.071 17.115
|
|
SLICE_X61Y167 FDCE (Recov_fdce_C_CLR) -0.629 16.486 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_B_reg[202][11]
|
|
-------------------------------------------------------------------
|
|
required time 16.486
|
|
arrival time -8.054
|
|
-------------------------------------------------------------------
|
|
slack 8.432
|
|
|
|
Slack (MET) : 8.432ns (required time - arrival time)
|
|
Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_cnt_reg[1]/C
|
|
(rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_B_reg[202][4]/CLR
|
|
(recovery check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Path Group: **async_default**
|
|
Path Type: Recovery (Max at Slow Process Corner)
|
|
Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns)
|
|
Data Path Delay: 10.541ns (logic 0.670ns (6.356%) route 9.871ns (93.644%))
|
|
Logic Levels: 1 (LUT5=1)
|
|
Clock Path Skew: -0.327ns (DCD - SCD + CPR)
|
|
Destination Clock Delay (DCD): -2.301ns = ( 17.699 - 20.000 )
|
|
Source Clock Delay (SCD): -2.488ns
|
|
Clock Pessimism Removal (CPR): -0.514ns
|
|
Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Discrete Jitter (DJ): 0.122ns
|
|
Phase Error (PE): 0.000ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock sys_clk rise edge) 0.000 0.000 r
|
|
clock source latency -6.275 -6.275
|
|
propagated clock network latency
|
|
3.788 -2.488
|
|
SLICE_X112Y65 FDCE 0.000 -2.488 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_cnt_reg[1]/C
|
|
SLICE_X112Y65 FDCE (Prop_fdce_C_Q) 0.518 -1.970 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_cnt_reg[1]/Q
|
|
net (fo=7, routed) 0.990 -0.979 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/srst_cnt_reg[1]
|
|
SLICE_X112Y66 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/p_s1[23]_i_9/I1
|
|
SLICE_X112Y66 LUT5 (Prop_lut5_I1_O) 0.152 -0.827 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/p_s1[23]_i_9/O
|
|
net (fo=24670, routed) 8.881 8.054 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/delay_reg[1]
|
|
SLICE_X61Y167 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_B_reg[202][4]/CLR
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock sys_clk rise edge) 20.000 20.000 r
|
|
clock source latency -5.674 14.326
|
|
propagated clock network latency
|
|
3.374 17.699
|
|
clock pessimism -0.514 17.186
|
|
clock uncertainty -0.071 17.115
|
|
SLICE_X61Y167 FDCE (Recov_fdce_C_CLR) -0.629 16.486 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_B_reg[202][4]
|
|
-------------------------------------------------------------------
|
|
required time 16.486
|
|
arrival time -8.054
|
|
-------------------------------------------------------------------
|
|
slack 8.432
|
|
|
|
Slack (MET) : 8.456ns (required time - arrival time)
|
|
Source: pll_clk.u_rst_sys/delay_reg[1]/C
|
|
(rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_A_reg[202][2]/CLR
|
|
(recovery check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Path Group: **async_default**
|
|
Path Type: Recovery (Max at Slow Process Corner)
|
|
Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns)
|
|
Data Path Delay: 10.526ns (logic 0.608ns (5.776%) route 9.918ns (94.224%))
|
|
Logic Levels: 1 (LUT5=1)
|
|
Clock Path Skew: -0.319ns (DCD - SCD + CPR)
|
|
Destination Clock Delay (DCD): -2.301ns = ( 17.699 - 20.000 )
|
|
Source Clock Delay (SCD): -2.496ns
|
|
Clock Pessimism Removal (CPR): -0.514ns
|
|
Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Discrete Jitter (DJ): 0.122ns
|
|
Phase Error (PE): 0.000ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock sys_clk rise edge) 0.000 0.000 r
|
|
clock source latency -6.275 -6.275
|
|
propagated clock network latency
|
|
3.780 -2.496
|
|
SLICE_X106Y69 FDCE 0.000 -2.496 r pll_clk.u_rst_sys/delay_reg[1]/C
|
|
SLICE_X106Y69 FDCE (Prop_fdce_C_Q) 0.456 -2.040 r pll_clk.u_rst_sys/delay_reg[1]/Q
|
|
net (fo=125, routed) 1.036 -1.003 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/valid_sr_reg[6][0]
|
|
SLICE_X112Y66 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/p_s1[23]_i_9/I0
|
|
SLICE_X112Y66 LUT5 (Prop_lut5_I0_O) 0.152 -0.851 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/p_s1[23]_i_9/O
|
|
net (fo=24670, routed) 8.881 8.030 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/delay_reg[1]
|
|
SLICE_X61Y167 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_A_reg[202][2]/CLR
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock sys_clk rise edge) 20.000 20.000 r
|
|
clock source latency -5.674 14.326
|
|
propagated clock network latency
|
|
3.374 17.699
|
|
clock pessimism -0.514 17.186
|
|
clock uncertainty -0.071 17.115
|
|
SLICE_X61Y167 FDCE (Recov_fdce_C_CLR) -0.629 16.486 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_A_reg[202][2]
|
|
-------------------------------------------------------------------
|
|
required time 16.486
|
|
arrival time -8.030
|
|
-------------------------------------------------------------------
|
|
slack 8.456
|
|
|
|
Slack (MET) : 8.456ns (required time - arrival time)
|
|
Source: pll_clk.u_rst_sys/delay_reg[1]/C
|
|
(rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_A_reg[202][9]/CLR
|
|
(recovery check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Path Group: **async_default**
|
|
Path Type: Recovery (Max at Slow Process Corner)
|
|
Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns)
|
|
Data Path Delay: 10.526ns (logic 0.608ns (5.776%) route 9.918ns (94.224%))
|
|
Logic Levels: 1 (LUT5=1)
|
|
Clock Path Skew: -0.319ns (DCD - SCD + CPR)
|
|
Destination Clock Delay (DCD): -2.301ns = ( 17.699 - 20.000 )
|
|
Source Clock Delay (SCD): -2.496ns
|
|
Clock Pessimism Removal (CPR): -0.514ns
|
|
Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Discrete Jitter (DJ): 0.122ns
|
|
Phase Error (PE): 0.000ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock sys_clk rise edge) 0.000 0.000 r
|
|
clock source latency -6.275 -6.275
|
|
propagated clock network latency
|
|
3.780 -2.496
|
|
SLICE_X106Y69 FDCE 0.000 -2.496 r pll_clk.u_rst_sys/delay_reg[1]/C
|
|
SLICE_X106Y69 FDCE (Prop_fdce_C_Q) 0.456 -2.040 r pll_clk.u_rst_sys/delay_reg[1]/Q
|
|
net (fo=125, routed) 1.036 -1.003 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/valid_sr_reg[6][0]
|
|
SLICE_X112Y66 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/p_s1[23]_i_9/I0
|
|
SLICE_X112Y66 LUT5 (Prop_lut5_I0_O) 0.152 -0.851 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/p_s1[23]_i_9/O
|
|
net (fo=24670, routed) 8.881 8.030 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/delay_reg[1]
|
|
SLICE_X61Y167 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_A_reg[202][9]/CLR
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock sys_clk rise edge) 20.000 20.000 r
|
|
clock source latency -5.674 14.326
|
|
propagated clock network latency
|
|
3.374 17.699
|
|
clock pessimism -0.514 17.186
|
|
clock uncertainty -0.071 17.115
|
|
SLICE_X61Y167 FDCE (Recov_fdce_C_CLR) -0.629 16.486 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_A_reg[202][9]
|
|
-------------------------------------------------------------------
|
|
required time 16.486
|
|
arrival time -8.030
|
|
-------------------------------------------------------------------
|
|
slack 8.456
|
|
|
|
Slack (MET) : 8.456ns (required time - arrival time)
|
|
Source: pll_clk.u_rst_sys/delay_reg[1]/C
|
|
(rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_B_reg[202][0]/CLR
|
|
(recovery check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Path Group: **async_default**
|
|
Path Type: Recovery (Max at Slow Process Corner)
|
|
Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns)
|
|
Data Path Delay: 10.526ns (logic 0.608ns (5.776%) route 9.918ns (94.224%))
|
|
Logic Levels: 1 (LUT5=1)
|
|
Clock Path Skew: -0.319ns (DCD - SCD + CPR)
|
|
Destination Clock Delay (DCD): -2.301ns = ( 17.699 - 20.000 )
|
|
Source Clock Delay (SCD): -2.496ns
|
|
Clock Pessimism Removal (CPR): -0.514ns
|
|
Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Discrete Jitter (DJ): 0.122ns
|
|
Phase Error (PE): 0.000ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock sys_clk rise edge) 0.000 0.000 r
|
|
clock source latency -6.275 -6.275
|
|
propagated clock network latency
|
|
3.780 -2.496
|
|
SLICE_X106Y69 FDCE 0.000 -2.496 r pll_clk.u_rst_sys/delay_reg[1]/C
|
|
SLICE_X106Y69 FDCE (Prop_fdce_C_Q) 0.456 -2.040 r pll_clk.u_rst_sys/delay_reg[1]/Q
|
|
net (fo=125, routed) 1.036 -1.003 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/valid_sr_reg[6][0]
|
|
SLICE_X112Y66 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/p_s1[23]_i_9/I0
|
|
SLICE_X112Y66 LUT5 (Prop_lut5_I0_O) 0.152 -0.851 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/p_s1[23]_i_9/O
|
|
net (fo=24670, routed) 8.881 8.030 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/delay_reg[1]
|
|
SLICE_X61Y167 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_B_reg[202][0]/CLR
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock sys_clk rise edge) 20.000 20.000 r
|
|
clock source latency -5.674 14.326
|
|
propagated clock network latency
|
|
3.374 17.699
|
|
clock pessimism -0.514 17.186
|
|
clock uncertainty -0.071 17.115
|
|
SLICE_X61Y167 FDCE (Recov_fdce_C_CLR) -0.629 16.486 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_B_reg[202][0]
|
|
-------------------------------------------------------------------
|
|
required time 16.486
|
|
arrival time -8.030
|
|
-------------------------------------------------------------------
|
|
slack 8.456
|
|
|
|
Slack (MET) : 8.456ns (required time - arrival time)
|
|
Source: pll_clk.u_rst_sys/delay_reg[1]/C
|
|
(rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_B_reg[202][11]/CLR
|
|
(recovery check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Path Group: **async_default**
|
|
Path Type: Recovery (Max at Slow Process Corner)
|
|
Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns)
|
|
Data Path Delay: 10.526ns (logic 0.608ns (5.776%) route 9.918ns (94.224%))
|
|
Logic Levels: 1 (LUT5=1)
|
|
Clock Path Skew: -0.319ns (DCD - SCD + CPR)
|
|
Destination Clock Delay (DCD): -2.301ns = ( 17.699 - 20.000 )
|
|
Source Clock Delay (SCD): -2.496ns
|
|
Clock Pessimism Removal (CPR): -0.514ns
|
|
Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Discrete Jitter (DJ): 0.122ns
|
|
Phase Error (PE): 0.000ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock sys_clk rise edge) 0.000 0.000 r
|
|
clock source latency -6.275 -6.275
|
|
propagated clock network latency
|
|
3.780 -2.496
|
|
SLICE_X106Y69 FDCE 0.000 -2.496 r pll_clk.u_rst_sys/delay_reg[1]/C
|
|
SLICE_X106Y69 FDCE (Prop_fdce_C_Q) 0.456 -2.040 r pll_clk.u_rst_sys/delay_reg[1]/Q
|
|
net (fo=125, routed) 1.036 -1.003 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/valid_sr_reg[6][0]
|
|
SLICE_X112Y66 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/p_s1[23]_i_9/I0
|
|
SLICE_X112Y66 LUT5 (Prop_lut5_I0_O) 0.152 -0.851 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/p_s1[23]_i_9/O
|
|
net (fo=24670, routed) 8.881 8.030 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/delay_reg[1]
|
|
SLICE_X61Y167 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_B_reg[202][11]/CLR
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock sys_clk rise edge) 20.000 20.000 r
|
|
clock source latency -5.674 14.326
|
|
propagated clock network latency
|
|
3.374 17.699
|
|
clock pessimism -0.514 17.186
|
|
clock uncertainty -0.071 17.115
|
|
SLICE_X61Y167 FDCE (Recov_fdce_C_CLR) -0.629 16.486 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_B_reg[202][11]
|
|
-------------------------------------------------------------------
|
|
required time 16.486
|
|
arrival time -8.030
|
|
-------------------------------------------------------------------
|
|
slack 8.456
|
|
|
|
Slack (MET) : 8.456ns (required time - arrival time)
|
|
Source: pll_clk.u_rst_sys/delay_reg[1]/C
|
|
(rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_B_reg[202][4]/CLR
|
|
(recovery check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Path Group: **async_default**
|
|
Path Type: Recovery (Max at Slow Process Corner)
|
|
Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns)
|
|
Data Path Delay: 10.526ns (logic 0.608ns (5.776%) route 9.918ns (94.224%))
|
|
Logic Levels: 1 (LUT5=1)
|
|
Clock Path Skew: -0.319ns (DCD - SCD + CPR)
|
|
Destination Clock Delay (DCD): -2.301ns = ( 17.699 - 20.000 )
|
|
Source Clock Delay (SCD): -2.496ns
|
|
Clock Pessimism Removal (CPR): -0.514ns
|
|
Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Discrete Jitter (DJ): 0.122ns
|
|
Phase Error (PE): 0.000ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock sys_clk rise edge) 0.000 0.000 r
|
|
clock source latency -6.275 -6.275
|
|
propagated clock network latency
|
|
3.780 -2.496
|
|
SLICE_X106Y69 FDCE 0.000 -2.496 r pll_clk.u_rst_sys/delay_reg[1]/C
|
|
SLICE_X106Y69 FDCE (Prop_fdce_C_Q) 0.456 -2.040 r pll_clk.u_rst_sys/delay_reg[1]/Q
|
|
net (fo=125, routed) 1.036 -1.003 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/valid_sr_reg[6][0]
|
|
SLICE_X112Y66 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/p_s1[23]_i_9/I0
|
|
SLICE_X112Y66 LUT5 (Prop_lut5_I0_O) 0.152 -0.851 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/p_s1[23]_i_9/O
|
|
net (fo=24670, routed) 8.881 8.030 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/delay_reg[1]
|
|
SLICE_X61Y167 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_B_reg[202][4]/CLR
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock sys_clk rise edge) 20.000 20.000 r
|
|
clock source latency -5.674 14.326
|
|
propagated clock network latency
|
|
3.374 17.699
|
|
clock pessimism -0.514 17.186
|
|
clock uncertainty -0.071 17.115
|
|
SLICE_X61Y167 FDCE (Recov_fdce_C_CLR) -0.629 16.486 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_B_reg[202][4]
|
|
-------------------------------------------------------------------
|
|
required time 16.486
|
|
arrival time -8.030
|
|
-------------------------------------------------------------------
|
|
slack 8.456
|
|
|
|
Slack (MET) : 8.458ns (required time - arrival time)
|
|
Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_cnt_reg[3]/C
|
|
(rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_B_reg[216][2]/CLR
|
|
(recovery check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Path Group: **async_default**
|
|
Path Type: Recovery (Max at Slow Process Corner)
|
|
Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns)
|
|
Data Path Delay: 10.601ns (logic 0.668ns (6.301%) route 9.933ns (93.699%))
|
|
Logic Levels: 1 (LUT5=1)
|
|
Clock Path Skew: -0.327ns (DCD - SCD + CPR)
|
|
Destination Clock Delay (DCD): -2.301ns = ( 17.699 - 20.000 )
|
|
Source Clock Delay (SCD): -2.488ns
|
|
Clock Pessimism Removal (CPR): -0.514ns
|
|
Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Discrete Jitter (DJ): 0.122ns
|
|
Phase Error (PE): 0.000ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock sys_clk rise edge) 0.000 0.000 r
|
|
clock source latency -6.275 -6.275
|
|
propagated clock network latency
|
|
3.788 -2.488
|
|
SLICE_X112Y65 FDCE 0.000 -2.488 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_cnt_reg[3]/C
|
|
SLICE_X112Y65 FDCE (Prop_fdce_C_Q) 0.518 -1.970 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_cnt_reg[3]/Q
|
|
net (fo=5, routed) 1.052 -0.917 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/srst_cnt_reg[3]
|
|
SLICE_X112Y66 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/p_s1[23]_i_9/I4
|
|
SLICE_X112Y66 LUT5 (Prop_lut5_I4_O) 0.150 -0.767 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/p_s1[23]_i_9/O
|
|
net (fo=24670, routed) 8.881 8.114 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/delay_reg[1]
|
|
SLICE_X60Y167 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_B_reg[216][2]/CLR
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock sys_clk rise edge) 20.000 20.000 r
|
|
clock source latency -5.674 14.326
|
|
propagated clock network latency
|
|
3.374 17.699
|
|
clock pessimism -0.514 17.186
|
|
clock uncertainty -0.071 17.115
|
|
SLICE_X60Y167 FDCE (Recov_fdce_C_CLR) -0.543 16.572 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_B_reg[216][2]
|
|
-------------------------------------------------------------------
|
|
required time 16.572
|
|
arrival time -8.114
|
|
-------------------------------------------------------------------
|
|
slack 8.458
|
|
|
|
Slack (MET) : 8.458ns (required time - arrival time)
|
|
Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_cnt_reg[3]/C
|
|
(rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_B_reg[216][4]/CLR
|
|
(recovery check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Path Group: **async_default**
|
|
Path Type: Recovery (Max at Slow Process Corner)
|
|
Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns)
|
|
Data Path Delay: 10.601ns (logic 0.668ns (6.301%) route 9.933ns (93.699%))
|
|
Logic Levels: 1 (LUT5=1)
|
|
Clock Path Skew: -0.327ns (DCD - SCD + CPR)
|
|
Destination Clock Delay (DCD): -2.301ns = ( 17.699 - 20.000 )
|
|
Source Clock Delay (SCD): -2.488ns
|
|
Clock Pessimism Removal (CPR): -0.514ns
|
|
Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Discrete Jitter (DJ): 0.122ns
|
|
Phase Error (PE): 0.000ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock sys_clk rise edge) 0.000 0.000 r
|
|
clock source latency -6.275 -6.275
|
|
propagated clock network latency
|
|
3.788 -2.488
|
|
SLICE_X112Y65 FDCE 0.000 -2.488 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_cnt_reg[3]/C
|
|
SLICE_X112Y65 FDCE (Prop_fdce_C_Q) 0.518 -1.970 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_cnt_reg[3]/Q
|
|
net (fo=5, routed) 1.052 -0.917 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/srst_cnt_reg[3]
|
|
SLICE_X112Y66 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/p_s1[23]_i_9/I4
|
|
SLICE_X112Y66 LUT5 (Prop_lut5_I4_O) 0.150 -0.767 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/p_s1[23]_i_9/O
|
|
net (fo=24670, routed) 8.881 8.114 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/delay_reg[1]
|
|
SLICE_X60Y167 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_B_reg[216][4]/CLR
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock sys_clk rise edge) 20.000 20.000 r
|
|
clock source latency -5.674 14.326
|
|
propagated clock network latency
|
|
3.374 17.699
|
|
clock pessimism -0.514 17.186
|
|
clock uncertainty -0.071 17.115
|
|
SLICE_X60Y167 FDCE (Recov_fdce_C_CLR) -0.543 16.572 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_B_reg[216][4]
|
|
-------------------------------------------------------------------
|
|
required time 16.572
|
|
arrival time -8.114
|
|
-------------------------------------------------------------------
|
|
slack 8.458
|
|
|
|
Slack (MET) : 8.458ns (required time - arrival time)
|
|
Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_cnt_reg[3]/C
|
|
(rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_B_reg[216][5]/CLR
|
|
(recovery check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Path Group: **async_default**
|
|
Path Type: Recovery (Max at Slow Process Corner)
|
|
Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns)
|
|
Data Path Delay: 10.601ns (logic 0.668ns (6.301%) route 9.933ns (93.699%))
|
|
Logic Levels: 1 (LUT5=1)
|
|
Clock Path Skew: -0.327ns (DCD - SCD + CPR)
|
|
Destination Clock Delay (DCD): -2.301ns = ( 17.699 - 20.000 )
|
|
Source Clock Delay (SCD): -2.488ns
|
|
Clock Pessimism Removal (CPR): -0.514ns
|
|
Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Discrete Jitter (DJ): 0.122ns
|
|
Phase Error (PE): 0.000ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock sys_clk rise edge) 0.000 0.000 r
|
|
clock source latency -6.275 -6.275
|
|
propagated clock network latency
|
|
3.788 -2.488
|
|
SLICE_X112Y65 FDCE 0.000 -2.488 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_cnt_reg[3]/C
|
|
SLICE_X112Y65 FDCE (Prop_fdce_C_Q) 0.518 -1.970 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_cnt_reg[3]/Q
|
|
net (fo=5, routed) 1.052 -0.917 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/srst_cnt_reg[3]
|
|
SLICE_X112Y66 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/p_s1[23]_i_9/I4
|
|
SLICE_X112Y66 LUT5 (Prop_lut5_I4_O) 0.150 -0.767 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/p_s1[23]_i_9/O
|
|
net (fo=24670, routed) 8.881 8.114 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/delay_reg[1]
|
|
SLICE_X60Y167 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_B_reg[216][5]/CLR
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock sys_clk rise edge) 20.000 20.000 r
|
|
clock source latency -5.674 14.326
|
|
propagated clock network latency
|
|
3.374 17.699
|
|
clock pessimism -0.514 17.186
|
|
clock uncertainty -0.071 17.115
|
|
SLICE_X60Y167 FDCE (Recov_fdce_C_CLR) -0.543 16.572 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_B_reg[216][5]
|
|
-------------------------------------------------------------------
|
|
required time 16.572
|
|
arrival time -8.114
|
|
-------------------------------------------------------------------
|
|
slack 8.458
|
|
|
|
Slack (MET) : 8.458ns (required time - arrival time)
|
|
Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_cnt_reg[3]/C
|
|
(rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_B_reg[216][9]/CLR
|
|
(recovery check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Path Group: **async_default**
|
|
Path Type: Recovery (Max at Slow Process Corner)
|
|
Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns)
|
|
Data Path Delay: 10.601ns (logic 0.668ns (6.301%) route 9.933ns (93.699%))
|
|
Logic Levels: 1 (LUT5=1)
|
|
Clock Path Skew: -0.327ns (DCD - SCD + CPR)
|
|
Destination Clock Delay (DCD): -2.301ns = ( 17.699 - 20.000 )
|
|
Source Clock Delay (SCD): -2.488ns
|
|
Clock Pessimism Removal (CPR): -0.514ns
|
|
Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Discrete Jitter (DJ): 0.122ns
|
|
Phase Error (PE): 0.000ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock sys_clk rise edge) 0.000 0.000 r
|
|
clock source latency -6.275 -6.275
|
|
propagated clock network latency
|
|
3.788 -2.488
|
|
SLICE_X112Y65 FDCE 0.000 -2.488 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_cnt_reg[3]/C
|
|
SLICE_X112Y65 FDCE (Prop_fdce_C_Q) 0.518 -1.970 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_cnt_reg[3]/Q
|
|
net (fo=5, routed) 1.052 -0.917 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/srst_cnt_reg[3]
|
|
SLICE_X112Y66 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/p_s1[23]_i_9/I4
|
|
SLICE_X112Y66 LUT5 (Prop_lut5_I4_O) 0.150 -0.767 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/p_s1[23]_i_9/O
|
|
net (fo=24670, routed) 8.881 8.114 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/delay_reg[1]
|
|
SLICE_X60Y167 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_B_reg[216][9]/CLR
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock sys_clk rise edge) 20.000 20.000 r
|
|
clock source latency -5.674 14.326
|
|
propagated clock network latency
|
|
3.374 17.699
|
|
clock pessimism -0.514 17.186
|
|
clock uncertainty -0.071 17.115
|
|
SLICE_X60Y167 FDCE (Recov_fdce_C_CLR) -0.543 16.572 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_B_reg[216][9]
|
|
-------------------------------------------------------------------
|
|
required time 16.572
|
|
arrival time -8.114
|
|
-------------------------------------------------------------------
|
|
slack 8.458
|
|
|
|
Slack (MET) : 8.467ns (required time - arrival time)
|
|
Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_cnt_reg[2]/C
|
|
(rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_B_reg[198][0]/CLR
|
|
(recovery check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Path Group: **async_default**
|
|
Path Type: Recovery (Max at Slow Process Corner)
|
|
Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns)
|
|
Data Path Delay: 10.503ns (logic 0.766ns (7.293%) route 9.737ns (92.707%))
|
|
Logic Levels: 1 (LUT5=1)
|
|
Clock Path Skew: -0.331ns (DCD - SCD + CPR)
|
|
Destination Clock Delay (DCD): -2.305ns = ( 17.695 - 20.000 )
|
|
Source Clock Delay (SCD): -2.488ns
|
|
Clock Pessimism Removal (CPR): -0.514ns
|
|
Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Discrete Jitter (DJ): 0.122ns
|
|
Phase Error (PE): 0.000ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock sys_clk rise edge) 0.000 0.000 r
|
|
clock source latency -6.275 -6.275
|
|
propagated clock network latency
|
|
3.788 -2.488
|
|
SLICE_X112Y65 FDCE 0.000 -2.488 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_cnt_reg[2]/C
|
|
SLICE_X112Y65 FDCE (Prop_fdce_C_Q) 0.478 -2.010 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_cnt_reg[2]/Q
|
|
net (fo=6, routed) 0.490 -1.520 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/srst_cnt_reg[2]
|
|
SLICE_X112Y66 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/p_s1[23]_i_9/I3
|
|
SLICE_X112Y66 LUT5 (Prop_lut5_I3_O) 0.288 -1.232 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/p_s1[23]_i_9/O
|
|
net (fo=24670, routed) 9.247 8.015 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/delay_reg[1]
|
|
SLICE_X63Y167 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_B_reg[198][0]/CLR
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock sys_clk rise edge) 20.000 20.000 r
|
|
clock source latency -5.674 14.326
|
|
propagated clock network latency
|
|
3.370 17.695
|
|
clock pessimism -0.514 17.182
|
|
clock uncertainty -0.071 17.111
|
|
SLICE_X63Y167 FDCE (Recov_fdce_C_CLR) -0.629 16.482 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_B_reg[198][0]
|
|
-------------------------------------------------------------------
|
|
required time 16.482
|
|
arrival time -8.015
|
|
-------------------------------------------------------------------
|
|
slack 8.467
|
|
|
|
Slack (MET) : 8.507ns (required time - arrival time)
|
|
Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_cnt_reg[0]/C
|
|
(rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_A_reg[208][10]/CLR
|
|
(recovery check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Path Group: **async_default**
|
|
Path Type: Recovery (Max at Slow Process Corner)
|
|
Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns)
|
|
Data Path Delay: 10.548ns (logic 0.668ns (6.333%) route 9.880ns (93.667%))
|
|
Logic Levels: 1 (LUT5=1)
|
|
Clock Path Skew: -0.331ns (DCD - SCD + CPR)
|
|
Destination Clock Delay (DCD): -2.305ns = ( 17.695 - 20.000 )
|
|
Source Clock Delay (SCD): -2.488ns
|
|
Clock Pessimism Removal (CPR): -0.514ns
|
|
Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Discrete Jitter (DJ): 0.122ns
|
|
Phase Error (PE): 0.000ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock sys_clk rise edge) 0.000 0.000 r
|
|
clock source latency -6.275 -6.275
|
|
propagated clock network latency
|
|
3.788 -2.488
|
|
SLICE_X112Y65 FDCE 0.000 -2.488 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_cnt_reg[0]/C
|
|
SLICE_X112Y65 FDCE (Prop_fdce_C_Q) 0.518 -1.970 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_cnt_reg[0]/Q
|
|
net (fo=8, routed) 0.633 -1.336 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/srst_cnt_reg[0]
|
|
SLICE_X112Y66 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/p_s1[23]_i_9/I2
|
|
SLICE_X112Y66 LUT5 (Prop_lut5_I2_O) 0.150 -1.186 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/p_s1[23]_i_9/O
|
|
net (fo=24670, routed) 9.247 8.061 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/delay_reg[1]
|
|
SLICE_X62Y167 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_A_reg[208][10]/CLR
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock sys_clk rise edge) 20.000 20.000 r
|
|
clock source latency -5.674 14.326
|
|
propagated clock network latency
|
|
3.370 17.695
|
|
clock pessimism -0.514 17.182
|
|
clock uncertainty -0.071 17.111
|
|
SLICE_X62Y167 FDCE (Recov_fdce_C_CLR) -0.543 16.568 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_A_reg[208][10]
|
|
-------------------------------------------------------------------
|
|
required time 16.568
|
|
arrival time -8.061
|
|
-------------------------------------------------------------------
|
|
slack 8.507
|
|
|
|
Slack (MET) : 8.507ns (required time - arrival time)
|
|
Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_cnt_reg[0]/C
|
|
(rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_B_reg[208][0]/CLR
|
|
(recovery check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Path Group: **async_default**
|
|
Path Type: Recovery (Max at Slow Process Corner)
|
|
Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns)
|
|
Data Path Delay: 10.548ns (logic 0.668ns (6.333%) route 9.880ns (93.667%))
|
|
Logic Levels: 1 (LUT5=1)
|
|
Clock Path Skew: -0.331ns (DCD - SCD + CPR)
|
|
Destination Clock Delay (DCD): -2.305ns = ( 17.695 - 20.000 )
|
|
Source Clock Delay (SCD): -2.488ns
|
|
Clock Pessimism Removal (CPR): -0.514ns
|
|
Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Discrete Jitter (DJ): 0.122ns
|
|
Phase Error (PE): 0.000ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock sys_clk rise edge) 0.000 0.000 r
|
|
clock source latency -6.275 -6.275
|
|
propagated clock network latency
|
|
3.788 -2.488
|
|
SLICE_X112Y65 FDCE 0.000 -2.488 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_cnt_reg[0]/C
|
|
SLICE_X112Y65 FDCE (Prop_fdce_C_Q) 0.518 -1.970 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_cnt_reg[0]/Q
|
|
net (fo=8, routed) 0.633 -1.336 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/srst_cnt_reg[0]
|
|
SLICE_X112Y66 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/p_s1[23]_i_9/I2
|
|
SLICE_X112Y66 LUT5 (Prop_lut5_I2_O) 0.150 -1.186 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/p_s1[23]_i_9/O
|
|
net (fo=24670, routed) 9.247 8.061 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/delay_reg[1]
|
|
SLICE_X62Y167 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_B_reg[208][0]/CLR
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock sys_clk rise edge) 20.000 20.000 r
|
|
clock source latency -5.674 14.326
|
|
propagated clock network latency
|
|
3.370 17.695
|
|
clock pessimism -0.514 17.182
|
|
clock uncertainty -0.071 17.111
|
|
SLICE_X62Y167 FDCE (Recov_fdce_C_CLR) -0.543 16.568 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_B_reg[208][0]
|
|
-------------------------------------------------------------------
|
|
required time 16.568
|
|
arrival time -8.061
|
|
-------------------------------------------------------------------
|
|
slack 8.507
|
|
|
|
Slack (MET) : 8.507ns (required time - arrival time)
|
|
Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_cnt_reg[0]/C
|
|
(rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_B_reg[208][11]/CLR
|
|
(recovery check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Path Group: **async_default**
|
|
Path Type: Recovery (Max at Slow Process Corner)
|
|
Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns)
|
|
Data Path Delay: 10.548ns (logic 0.668ns (6.333%) route 9.880ns (93.667%))
|
|
Logic Levels: 1 (LUT5=1)
|
|
Clock Path Skew: -0.331ns (DCD - SCD + CPR)
|
|
Destination Clock Delay (DCD): -2.305ns = ( 17.695 - 20.000 )
|
|
Source Clock Delay (SCD): -2.488ns
|
|
Clock Pessimism Removal (CPR): -0.514ns
|
|
Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Discrete Jitter (DJ): 0.122ns
|
|
Phase Error (PE): 0.000ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock sys_clk rise edge) 0.000 0.000 r
|
|
clock source latency -6.275 -6.275
|
|
propagated clock network latency
|
|
3.788 -2.488
|
|
SLICE_X112Y65 FDCE 0.000 -2.488 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_cnt_reg[0]/C
|
|
SLICE_X112Y65 FDCE (Prop_fdce_C_Q) 0.518 -1.970 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_cnt_reg[0]/Q
|
|
net (fo=8, routed) 0.633 -1.336 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/srst_cnt_reg[0]
|
|
SLICE_X112Y66 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/p_s1[23]_i_9/I2
|
|
SLICE_X112Y66 LUT5 (Prop_lut5_I2_O) 0.150 -1.186 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/p_s1[23]_i_9/O
|
|
net (fo=24670, routed) 9.247 8.061 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/delay_reg[1]
|
|
SLICE_X62Y167 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_B_reg[208][11]/CLR
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock sys_clk rise edge) 20.000 20.000 r
|
|
clock source latency -5.674 14.326
|
|
propagated clock network latency
|
|
3.370 17.695
|
|
clock pessimism -0.514 17.182
|
|
clock uncertainty -0.071 17.111
|
|
SLICE_X62Y167 FDCE (Recov_fdce_C_CLR) -0.543 16.568 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_B_reg[208][11]
|
|
-------------------------------------------------------------------
|
|
required time 16.568
|
|
arrival time -8.061
|
|
-------------------------------------------------------------------
|
|
slack 8.507
|
|
|
|
Slack (MET) : 8.518ns (required time - arrival time)
|
|
Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_cnt_reg[1]/C
|
|
(rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_B_reg[216][2]/CLR
|
|
(recovery check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Path Group: **async_default**
|
|
Path Type: Recovery (Max at Slow Process Corner)
|
|
Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns)
|
|
Data Path Delay: 10.541ns (logic 0.670ns (6.356%) route 9.871ns (93.644%))
|
|
Logic Levels: 1 (LUT5=1)
|
|
Clock Path Skew: -0.327ns (DCD - SCD + CPR)
|
|
Destination Clock Delay (DCD): -2.301ns = ( 17.699 - 20.000 )
|
|
Source Clock Delay (SCD): -2.488ns
|
|
Clock Pessimism Removal (CPR): -0.514ns
|
|
Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Discrete Jitter (DJ): 0.122ns
|
|
Phase Error (PE): 0.000ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock sys_clk rise edge) 0.000 0.000 r
|
|
clock source latency -6.275 -6.275
|
|
propagated clock network latency
|
|
3.788 -2.488
|
|
SLICE_X112Y65 FDCE 0.000 -2.488 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_cnt_reg[1]/C
|
|
SLICE_X112Y65 FDCE (Prop_fdce_C_Q) 0.518 -1.970 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_cnt_reg[1]/Q
|
|
net (fo=7, routed) 0.990 -0.979 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/srst_cnt_reg[1]
|
|
SLICE_X112Y66 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/p_s1[23]_i_9/I1
|
|
SLICE_X112Y66 LUT5 (Prop_lut5_I1_O) 0.152 -0.827 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/p_s1[23]_i_9/O
|
|
net (fo=24670, routed) 8.881 8.054 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/delay_reg[1]
|
|
SLICE_X60Y167 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_B_reg[216][2]/CLR
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock sys_clk rise edge) 20.000 20.000 r
|
|
clock source latency -5.674 14.326
|
|
propagated clock network latency
|
|
3.374 17.699
|
|
clock pessimism -0.514 17.186
|
|
clock uncertainty -0.071 17.115
|
|
SLICE_X60Y167 FDCE (Recov_fdce_C_CLR) -0.543 16.572 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_B_reg[216][2]
|
|
-------------------------------------------------------------------
|
|
required time 16.572
|
|
arrival time -8.054
|
|
-------------------------------------------------------------------
|
|
slack 8.518
|
|
|
|
Slack (MET) : 8.518ns (required time - arrival time)
|
|
Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_cnt_reg[1]/C
|
|
(rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_B_reg[216][4]/CLR
|
|
(recovery check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Path Group: **async_default**
|
|
Path Type: Recovery (Max at Slow Process Corner)
|
|
Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns)
|
|
Data Path Delay: 10.541ns (logic 0.670ns (6.356%) route 9.871ns (93.644%))
|
|
Logic Levels: 1 (LUT5=1)
|
|
Clock Path Skew: -0.327ns (DCD - SCD + CPR)
|
|
Destination Clock Delay (DCD): -2.301ns = ( 17.699 - 20.000 )
|
|
Source Clock Delay (SCD): -2.488ns
|
|
Clock Pessimism Removal (CPR): -0.514ns
|
|
Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Discrete Jitter (DJ): 0.122ns
|
|
Phase Error (PE): 0.000ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock sys_clk rise edge) 0.000 0.000 r
|
|
clock source latency -6.275 -6.275
|
|
propagated clock network latency
|
|
3.788 -2.488
|
|
SLICE_X112Y65 FDCE 0.000 -2.488 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_cnt_reg[1]/C
|
|
SLICE_X112Y65 FDCE (Prop_fdce_C_Q) 0.518 -1.970 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_cnt_reg[1]/Q
|
|
net (fo=7, routed) 0.990 -0.979 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/srst_cnt_reg[1]
|
|
SLICE_X112Y66 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/p_s1[23]_i_9/I1
|
|
SLICE_X112Y66 LUT5 (Prop_lut5_I1_O) 0.152 -0.827 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/p_s1[23]_i_9/O
|
|
net (fo=24670, routed) 8.881 8.054 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/delay_reg[1]
|
|
SLICE_X60Y167 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_B_reg[216][4]/CLR
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock sys_clk rise edge) 20.000 20.000 r
|
|
clock source latency -5.674 14.326
|
|
propagated clock network latency
|
|
3.374 17.699
|
|
clock pessimism -0.514 17.186
|
|
clock uncertainty -0.071 17.115
|
|
SLICE_X60Y167 FDCE (Recov_fdce_C_CLR) -0.543 16.572 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_B_reg[216][4]
|
|
-------------------------------------------------------------------
|
|
required time 16.572
|
|
arrival time -8.054
|
|
-------------------------------------------------------------------
|
|
slack 8.518
|
|
|
|
Slack (MET) : 8.518ns (required time - arrival time)
|
|
Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_cnt_reg[1]/C
|
|
(rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_B_reg[216][5]/CLR
|
|
(recovery check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Path Group: **async_default**
|
|
Path Type: Recovery (Max at Slow Process Corner)
|
|
Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns)
|
|
Data Path Delay: 10.541ns (logic 0.670ns (6.356%) route 9.871ns (93.644%))
|
|
Logic Levels: 1 (LUT5=1)
|
|
Clock Path Skew: -0.327ns (DCD - SCD + CPR)
|
|
Destination Clock Delay (DCD): -2.301ns = ( 17.699 - 20.000 )
|
|
Source Clock Delay (SCD): -2.488ns
|
|
Clock Pessimism Removal (CPR): -0.514ns
|
|
Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Discrete Jitter (DJ): 0.122ns
|
|
Phase Error (PE): 0.000ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock sys_clk rise edge) 0.000 0.000 r
|
|
clock source latency -6.275 -6.275
|
|
propagated clock network latency
|
|
3.788 -2.488
|
|
SLICE_X112Y65 FDCE 0.000 -2.488 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_cnt_reg[1]/C
|
|
SLICE_X112Y65 FDCE (Prop_fdce_C_Q) 0.518 -1.970 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_cnt_reg[1]/Q
|
|
net (fo=7, routed) 0.990 -0.979 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/srst_cnt_reg[1]
|
|
SLICE_X112Y66 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/p_s1[23]_i_9/I1
|
|
SLICE_X112Y66 LUT5 (Prop_lut5_I1_O) 0.152 -0.827 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/p_s1[23]_i_9/O
|
|
net (fo=24670, routed) 8.881 8.054 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/delay_reg[1]
|
|
SLICE_X60Y167 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_B_reg[216][5]/CLR
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock sys_clk rise edge) 20.000 20.000 r
|
|
clock source latency -5.674 14.326
|
|
propagated clock network latency
|
|
3.374 17.699
|
|
clock pessimism -0.514 17.186
|
|
clock uncertainty -0.071 17.115
|
|
SLICE_X60Y167 FDCE (Recov_fdce_C_CLR) -0.543 16.572 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_B_reg[216][5]
|
|
-------------------------------------------------------------------
|
|
required time 16.572
|
|
arrival time -8.054
|
|
-------------------------------------------------------------------
|
|
slack 8.518
|
|
|
|
Slack (MET) : 8.518ns (required time - arrival time)
|
|
Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_cnt_reg[1]/C
|
|
(rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_B_reg[216][9]/CLR
|
|
(recovery check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Path Group: **async_default**
|
|
Path Type: Recovery (Max at Slow Process Corner)
|
|
Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns)
|
|
Data Path Delay: 10.541ns (logic 0.670ns (6.356%) route 9.871ns (93.644%))
|
|
Logic Levels: 1 (LUT5=1)
|
|
Clock Path Skew: -0.327ns (DCD - SCD + CPR)
|
|
Destination Clock Delay (DCD): -2.301ns = ( 17.699 - 20.000 )
|
|
Source Clock Delay (SCD): -2.488ns
|
|
Clock Pessimism Removal (CPR): -0.514ns
|
|
Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Discrete Jitter (DJ): 0.122ns
|
|
Phase Error (PE): 0.000ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock sys_clk rise edge) 0.000 0.000 r
|
|
clock source latency -6.275 -6.275
|
|
propagated clock network latency
|
|
3.788 -2.488
|
|
SLICE_X112Y65 FDCE 0.000 -2.488 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_cnt_reg[1]/C
|
|
SLICE_X112Y65 FDCE (Prop_fdce_C_Q) 0.518 -1.970 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_cnt_reg[1]/Q
|
|
net (fo=7, routed) 0.990 -0.979 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/srst_cnt_reg[1]
|
|
SLICE_X112Y66 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/p_s1[23]_i_9/I1
|
|
SLICE_X112Y66 LUT5 (Prop_lut5_I1_O) 0.152 -0.827 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/p_s1[23]_i_9/O
|
|
net (fo=24670, routed) 8.881 8.054 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/delay_reg[1]
|
|
SLICE_X60Y167 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_B_reg[216][9]/CLR
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock sys_clk rise edge) 20.000 20.000 r
|
|
clock source latency -5.674 14.326
|
|
propagated clock network latency
|
|
3.374 17.699
|
|
clock pessimism -0.514 17.186
|
|
clock uncertainty -0.071 17.115
|
|
SLICE_X60Y167 FDCE (Recov_fdce_C_CLR) -0.543 16.572 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_B_reg[216][9]
|
|
-------------------------------------------------------------------
|
|
required time 16.572
|
|
arrival time -8.054
|
|
-------------------------------------------------------------------
|
|
slack 8.518
|
|
|
|
Slack (MET) : 8.542ns (required time - arrival time)
|
|
Source: pll_clk.u_rst_sys/delay_reg[1]/C
|
|
(rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_B_reg[216][2]/CLR
|
|
(recovery check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Path Group: **async_default**
|
|
Path Type: Recovery (Max at Slow Process Corner)
|
|
Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns)
|
|
Data Path Delay: 10.526ns (logic 0.608ns (5.776%) route 9.918ns (94.224%))
|
|
Logic Levels: 1 (LUT5=1)
|
|
Clock Path Skew: -0.319ns (DCD - SCD + CPR)
|
|
Destination Clock Delay (DCD): -2.301ns = ( 17.699 - 20.000 )
|
|
Source Clock Delay (SCD): -2.496ns
|
|
Clock Pessimism Removal (CPR): -0.514ns
|
|
Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Discrete Jitter (DJ): 0.122ns
|
|
Phase Error (PE): 0.000ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock sys_clk rise edge) 0.000 0.000 r
|
|
clock source latency -6.275 -6.275
|
|
propagated clock network latency
|
|
3.780 -2.496
|
|
SLICE_X106Y69 FDCE 0.000 -2.496 r pll_clk.u_rst_sys/delay_reg[1]/C
|
|
SLICE_X106Y69 FDCE (Prop_fdce_C_Q) 0.456 -2.040 r pll_clk.u_rst_sys/delay_reg[1]/Q
|
|
net (fo=125, routed) 1.036 -1.003 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/valid_sr_reg[6][0]
|
|
SLICE_X112Y66 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/p_s1[23]_i_9/I0
|
|
SLICE_X112Y66 LUT5 (Prop_lut5_I0_O) 0.152 -0.851 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/p_s1[23]_i_9/O
|
|
net (fo=24670, routed) 8.881 8.030 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/delay_reg[1]
|
|
SLICE_X60Y167 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_B_reg[216][2]/CLR
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock sys_clk rise edge) 20.000 20.000 r
|
|
clock source latency -5.674 14.326
|
|
propagated clock network latency
|
|
3.374 17.699
|
|
clock pessimism -0.514 17.186
|
|
clock uncertainty -0.071 17.115
|
|
SLICE_X60Y167 FDCE (Recov_fdce_C_CLR) -0.543 16.572 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_B_reg[216][2]
|
|
-------------------------------------------------------------------
|
|
required time 16.572
|
|
arrival time -8.030
|
|
-------------------------------------------------------------------
|
|
slack 8.542
|
|
|
|
Slack (MET) : 8.542ns (required time - arrival time)
|
|
Source: pll_clk.u_rst_sys/delay_reg[1]/C
|
|
(rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_B_reg[216][4]/CLR
|
|
(recovery check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Path Group: **async_default**
|
|
Path Type: Recovery (Max at Slow Process Corner)
|
|
Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns)
|
|
Data Path Delay: 10.526ns (logic 0.608ns (5.776%) route 9.918ns (94.224%))
|
|
Logic Levels: 1 (LUT5=1)
|
|
Clock Path Skew: -0.319ns (DCD - SCD + CPR)
|
|
Destination Clock Delay (DCD): -2.301ns = ( 17.699 - 20.000 )
|
|
Source Clock Delay (SCD): -2.496ns
|
|
Clock Pessimism Removal (CPR): -0.514ns
|
|
Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Discrete Jitter (DJ): 0.122ns
|
|
Phase Error (PE): 0.000ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock sys_clk rise edge) 0.000 0.000 r
|
|
clock source latency -6.275 -6.275
|
|
propagated clock network latency
|
|
3.780 -2.496
|
|
SLICE_X106Y69 FDCE 0.000 -2.496 r pll_clk.u_rst_sys/delay_reg[1]/C
|
|
SLICE_X106Y69 FDCE (Prop_fdce_C_Q) 0.456 -2.040 r pll_clk.u_rst_sys/delay_reg[1]/Q
|
|
net (fo=125, routed) 1.036 -1.003 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/valid_sr_reg[6][0]
|
|
SLICE_X112Y66 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/p_s1[23]_i_9/I0
|
|
SLICE_X112Y66 LUT5 (Prop_lut5_I0_O) 0.152 -0.851 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/p_s1[23]_i_9/O
|
|
net (fo=24670, routed) 8.881 8.030 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/delay_reg[1]
|
|
SLICE_X60Y167 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_B_reg[216][4]/CLR
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock sys_clk rise edge) 20.000 20.000 r
|
|
clock source latency -5.674 14.326
|
|
propagated clock network latency
|
|
3.374 17.699
|
|
clock pessimism -0.514 17.186
|
|
clock uncertainty -0.071 17.115
|
|
SLICE_X60Y167 FDCE (Recov_fdce_C_CLR) -0.543 16.572 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_B_reg[216][4]
|
|
-------------------------------------------------------------------
|
|
required time 16.572
|
|
arrival time -8.030
|
|
-------------------------------------------------------------------
|
|
slack 8.542
|
|
|
|
Slack (MET) : 8.542ns (required time - arrival time)
|
|
Source: pll_clk.u_rst_sys/delay_reg[1]/C
|
|
(rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_B_reg[216][5]/CLR
|
|
(recovery check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Path Group: **async_default**
|
|
Path Type: Recovery (Max at Slow Process Corner)
|
|
Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns)
|
|
Data Path Delay: 10.526ns (logic 0.608ns (5.776%) route 9.918ns (94.224%))
|
|
Logic Levels: 1 (LUT5=1)
|
|
Clock Path Skew: -0.319ns (DCD - SCD + CPR)
|
|
Destination Clock Delay (DCD): -2.301ns = ( 17.699 - 20.000 )
|
|
Source Clock Delay (SCD): -2.496ns
|
|
Clock Pessimism Removal (CPR): -0.514ns
|
|
Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Discrete Jitter (DJ): 0.122ns
|
|
Phase Error (PE): 0.000ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock sys_clk rise edge) 0.000 0.000 r
|
|
clock source latency -6.275 -6.275
|
|
propagated clock network latency
|
|
3.780 -2.496
|
|
SLICE_X106Y69 FDCE 0.000 -2.496 r pll_clk.u_rst_sys/delay_reg[1]/C
|
|
SLICE_X106Y69 FDCE (Prop_fdce_C_Q) 0.456 -2.040 r pll_clk.u_rst_sys/delay_reg[1]/Q
|
|
net (fo=125, routed) 1.036 -1.003 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/valid_sr_reg[6][0]
|
|
SLICE_X112Y66 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/p_s1[23]_i_9/I0
|
|
SLICE_X112Y66 LUT5 (Prop_lut5_I0_O) 0.152 -0.851 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/p_s1[23]_i_9/O
|
|
net (fo=24670, routed) 8.881 8.030 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/delay_reg[1]
|
|
SLICE_X60Y167 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_B_reg[216][5]/CLR
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock sys_clk rise edge) 20.000 20.000 r
|
|
clock source latency -5.674 14.326
|
|
propagated clock network latency
|
|
3.374 17.699
|
|
clock pessimism -0.514 17.186
|
|
clock uncertainty -0.071 17.115
|
|
SLICE_X60Y167 FDCE (Recov_fdce_C_CLR) -0.543 16.572 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_B_reg[216][5]
|
|
-------------------------------------------------------------------
|
|
required time 16.572
|
|
arrival time -8.030
|
|
-------------------------------------------------------------------
|
|
slack 8.542
|
|
|
|
Slack (MET) : 8.542ns (required time - arrival time)
|
|
Source: pll_clk.u_rst_sys/delay_reg[1]/C
|
|
(rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_B_reg[216][9]/CLR
|
|
(recovery check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Path Group: **async_default**
|
|
Path Type: Recovery (Max at Slow Process Corner)
|
|
Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns)
|
|
Data Path Delay: 10.526ns (logic 0.608ns (5.776%) route 9.918ns (94.224%))
|
|
Logic Levels: 1 (LUT5=1)
|
|
Clock Path Skew: -0.319ns (DCD - SCD + CPR)
|
|
Destination Clock Delay (DCD): -2.301ns = ( 17.699 - 20.000 )
|
|
Source Clock Delay (SCD): -2.496ns
|
|
Clock Pessimism Removal (CPR): -0.514ns
|
|
Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Discrete Jitter (DJ): 0.122ns
|
|
Phase Error (PE): 0.000ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock sys_clk rise edge) 0.000 0.000 r
|
|
clock source latency -6.275 -6.275
|
|
propagated clock network latency
|
|
3.780 -2.496
|
|
SLICE_X106Y69 FDCE 0.000 -2.496 r pll_clk.u_rst_sys/delay_reg[1]/C
|
|
SLICE_X106Y69 FDCE (Prop_fdce_C_Q) 0.456 -2.040 r pll_clk.u_rst_sys/delay_reg[1]/Q
|
|
net (fo=125, routed) 1.036 -1.003 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/valid_sr_reg[6][0]
|
|
SLICE_X112Y66 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/p_s1[23]_i_9/I0
|
|
SLICE_X112Y66 LUT5 (Prop_lut5_I0_O) 0.152 -0.851 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/p_s1[23]_i_9/O
|
|
net (fo=24670, routed) 8.881 8.030 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/delay_reg[1]
|
|
SLICE_X60Y167 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_B_reg[216][9]/CLR
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock sys_clk rise edge) 20.000 20.000 r
|
|
clock source latency -5.674 14.326
|
|
propagated clock network latency
|
|
3.374 17.699
|
|
clock pessimism -0.514 17.186
|
|
clock uncertainty -0.071 17.115
|
|
SLICE_X60Y167 FDCE (Recov_fdce_C_CLR) -0.543 16.572 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_B_reg[216][9]
|
|
-------------------------------------------------------------------
|
|
required time 16.572
|
|
arrival time -8.030
|
|
-------------------------------------------------------------------
|
|
slack 8.542
|
|
|
|
Slack (MET) : 8.553ns (required time - arrival time)
|
|
Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_cnt_reg[2]/C
|
|
(rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_A_reg[208][10]/CLR
|
|
(recovery check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Path Group: **async_default**
|
|
Path Type: Recovery (Max at Slow Process Corner)
|
|
Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns)
|
|
Data Path Delay: 10.503ns (logic 0.766ns (7.293%) route 9.737ns (92.707%))
|
|
Logic Levels: 1 (LUT5=1)
|
|
Clock Path Skew: -0.331ns (DCD - SCD + CPR)
|
|
Destination Clock Delay (DCD): -2.305ns = ( 17.695 - 20.000 )
|
|
Source Clock Delay (SCD): -2.488ns
|
|
Clock Pessimism Removal (CPR): -0.514ns
|
|
Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Discrete Jitter (DJ): 0.122ns
|
|
Phase Error (PE): 0.000ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock sys_clk rise edge) 0.000 0.000 r
|
|
clock source latency -6.275 -6.275
|
|
propagated clock network latency
|
|
3.788 -2.488
|
|
SLICE_X112Y65 FDCE 0.000 -2.488 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_cnt_reg[2]/C
|
|
SLICE_X112Y65 FDCE (Prop_fdce_C_Q) 0.478 -2.010 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_cnt_reg[2]/Q
|
|
net (fo=6, routed) 0.490 -1.520 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/srst_cnt_reg[2]
|
|
SLICE_X112Y66 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/p_s1[23]_i_9/I3
|
|
SLICE_X112Y66 LUT5 (Prop_lut5_I3_O) 0.288 -1.232 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/p_s1[23]_i_9/O
|
|
net (fo=24670, routed) 9.247 8.015 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/delay_reg[1]
|
|
SLICE_X62Y167 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_A_reg[208][10]/CLR
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock sys_clk rise edge) 20.000 20.000 r
|
|
clock source latency -5.674 14.326
|
|
propagated clock network latency
|
|
3.370 17.695
|
|
clock pessimism -0.514 17.182
|
|
clock uncertainty -0.071 17.111
|
|
SLICE_X62Y167 FDCE (Recov_fdce_C_CLR) -0.543 16.568 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_A_reg[208][10]
|
|
-------------------------------------------------------------------
|
|
required time 16.568
|
|
arrival time -8.015
|
|
-------------------------------------------------------------------
|
|
slack 8.553
|
|
|
|
Slack (MET) : 8.553ns (required time - arrival time)
|
|
Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_cnt_reg[2]/C
|
|
(rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_B_reg[208][0]/CLR
|
|
(recovery check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Path Group: **async_default**
|
|
Path Type: Recovery (Max at Slow Process Corner)
|
|
Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns)
|
|
Data Path Delay: 10.503ns (logic 0.766ns (7.293%) route 9.737ns (92.707%))
|
|
Logic Levels: 1 (LUT5=1)
|
|
Clock Path Skew: -0.331ns (DCD - SCD + CPR)
|
|
Destination Clock Delay (DCD): -2.305ns = ( 17.695 - 20.000 )
|
|
Source Clock Delay (SCD): -2.488ns
|
|
Clock Pessimism Removal (CPR): -0.514ns
|
|
Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Discrete Jitter (DJ): 0.122ns
|
|
Phase Error (PE): 0.000ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock sys_clk rise edge) 0.000 0.000 r
|
|
clock source latency -6.275 -6.275
|
|
propagated clock network latency
|
|
3.788 -2.488
|
|
SLICE_X112Y65 FDCE 0.000 -2.488 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_cnt_reg[2]/C
|
|
SLICE_X112Y65 FDCE (Prop_fdce_C_Q) 0.478 -2.010 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_cnt_reg[2]/Q
|
|
net (fo=6, routed) 0.490 -1.520 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/srst_cnt_reg[2]
|
|
SLICE_X112Y66 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/p_s1[23]_i_9/I3
|
|
SLICE_X112Y66 LUT5 (Prop_lut5_I3_O) 0.288 -1.232 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/p_s1[23]_i_9/O
|
|
net (fo=24670, routed) 9.247 8.015 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/delay_reg[1]
|
|
SLICE_X62Y167 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_B_reg[208][0]/CLR
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock sys_clk rise edge) 20.000 20.000 r
|
|
clock source latency -5.674 14.326
|
|
propagated clock network latency
|
|
3.370 17.695
|
|
clock pessimism -0.514 17.182
|
|
clock uncertainty -0.071 17.111
|
|
SLICE_X62Y167 FDCE (Recov_fdce_C_CLR) -0.543 16.568 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_B_reg[208][0]
|
|
-------------------------------------------------------------------
|
|
required time 16.568
|
|
arrival time -8.015
|
|
-------------------------------------------------------------------
|
|
slack 8.553
|
|
|
|
Slack (MET) : 8.553ns (required time - arrival time)
|
|
Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_cnt_reg[2]/C
|
|
(rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_B_reg[208][11]/CLR
|
|
(recovery check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Path Group: **async_default**
|
|
Path Type: Recovery (Max at Slow Process Corner)
|
|
Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns)
|
|
Data Path Delay: 10.503ns (logic 0.766ns (7.293%) route 9.737ns (92.707%))
|
|
Logic Levels: 1 (LUT5=1)
|
|
Clock Path Skew: -0.331ns (DCD - SCD + CPR)
|
|
Destination Clock Delay (DCD): -2.305ns = ( 17.695 - 20.000 )
|
|
Source Clock Delay (SCD): -2.488ns
|
|
Clock Pessimism Removal (CPR): -0.514ns
|
|
Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Discrete Jitter (DJ): 0.122ns
|
|
Phase Error (PE): 0.000ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock sys_clk rise edge) 0.000 0.000 r
|
|
clock source latency -6.275 -6.275
|
|
propagated clock network latency
|
|
3.788 -2.488
|
|
SLICE_X112Y65 FDCE 0.000 -2.488 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_cnt_reg[2]/C
|
|
SLICE_X112Y65 FDCE (Prop_fdce_C_Q) 0.478 -2.010 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_cnt_reg[2]/Q
|
|
net (fo=6, routed) 0.490 -1.520 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/srst_cnt_reg[2]
|
|
SLICE_X112Y66 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/p_s1[23]_i_9/I3
|
|
SLICE_X112Y66 LUT5 (Prop_lut5_I3_O) 0.288 -1.232 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/p_s1[23]_i_9/O
|
|
net (fo=24670, routed) 9.247 8.015 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/delay_reg[1]
|
|
SLICE_X62Y167 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_B_reg[208][11]/CLR
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock sys_clk rise edge) 20.000 20.000 r
|
|
clock source latency -5.674 14.326
|
|
propagated clock network latency
|
|
3.370 17.695
|
|
clock pessimism -0.514 17.182
|
|
clock uncertainty -0.071 17.111
|
|
SLICE_X62Y167 FDCE (Recov_fdce_C_CLR) -0.543 16.568 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_B_reg[208][11]
|
|
-------------------------------------------------------------------
|
|
required time 16.568
|
|
arrival time -8.015
|
|
-------------------------------------------------------------------
|
|
slack 8.553
|
|
|
|
Slack (MET) : 8.665ns (required time - arrival time)
|
|
Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_cnt_reg[3]/C
|
|
(rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_B_reg[198][4]/CLR
|
|
(recovery check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Path Group: **async_default**
|
|
Path Type: Recovery (Max at Slow Process Corner)
|
|
Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns)
|
|
Data Path Delay: 10.309ns (logic 0.668ns (6.480%) route 9.641ns (93.520%))
|
|
Logic Levels: 1 (LUT5=1)
|
|
Clock Path Skew: -0.327ns (DCD - SCD + CPR)
|
|
Destination Clock Delay (DCD): -2.301ns = ( 17.699 - 20.000 )
|
|
Source Clock Delay (SCD): -2.488ns
|
|
Clock Pessimism Removal (CPR): -0.514ns
|
|
Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Discrete Jitter (DJ): 0.122ns
|
|
Phase Error (PE): 0.000ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock sys_clk rise edge) 0.000 0.000 r
|
|
clock source latency -6.275 -6.275
|
|
propagated clock network latency
|
|
3.788 -2.488
|
|
SLICE_X112Y65 FDCE 0.000 -2.488 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_cnt_reg[3]/C
|
|
SLICE_X112Y65 FDCE (Prop_fdce_C_Q) 0.518 -1.970 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_cnt_reg[3]/Q
|
|
net (fo=5, routed) 1.052 -0.917 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/srst_cnt_reg[3]
|
|
SLICE_X112Y66 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/p_s1[23]_i_9/I4
|
|
SLICE_X112Y66 LUT5 (Prop_lut5_I4_O) 0.150 -0.767 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/p_s1[23]_i_9/O
|
|
net (fo=24670, routed) 8.589 7.821 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/delay_reg[1]
|
|
SLICE_X57Y167 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_B_reg[198][4]/CLR
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock sys_clk rise edge) 20.000 20.000 r
|
|
clock source latency -5.674 14.326
|
|
propagated clock network latency
|
|
3.374 17.699
|
|
clock pessimism -0.514 17.186
|
|
clock uncertainty -0.071 17.115
|
|
SLICE_X57Y167 FDCE (Recov_fdce_C_CLR) -0.629 16.486 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_B_reg[198][4]
|
|
-------------------------------------------------------------------
|
|
required time 16.486
|
|
arrival time -7.821
|
|
-------------------------------------------------------------------
|
|
slack 8.665
|
|
|
|
Slack (MET) : 8.725ns (required time - arrival time)
|
|
Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_cnt_reg[1]/C
|
|
(rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_B_reg[198][4]/CLR
|
|
(recovery check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Path Group: **async_default**
|
|
Path Type: Recovery (Max at Slow Process Corner)
|
|
Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns)
|
|
Data Path Delay: 10.249ns (logic 0.670ns (6.537%) route 9.579ns (93.463%))
|
|
Logic Levels: 1 (LUT5=1)
|
|
Clock Path Skew: -0.327ns (DCD - SCD + CPR)
|
|
Destination Clock Delay (DCD): -2.301ns = ( 17.699 - 20.000 )
|
|
Source Clock Delay (SCD): -2.488ns
|
|
Clock Pessimism Removal (CPR): -0.514ns
|
|
Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Discrete Jitter (DJ): 0.122ns
|
|
Phase Error (PE): 0.000ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock sys_clk rise edge) 0.000 0.000 r
|
|
clock source latency -6.275 -6.275
|
|
propagated clock network latency
|
|
3.788 -2.488
|
|
SLICE_X112Y65 FDCE 0.000 -2.488 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_cnt_reg[1]/C
|
|
SLICE_X112Y65 FDCE (Prop_fdce_C_Q) 0.518 -1.970 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_cnt_reg[1]/Q
|
|
net (fo=7, routed) 0.990 -0.979 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/srst_cnt_reg[1]
|
|
SLICE_X112Y66 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/p_s1[23]_i_9/I1
|
|
SLICE_X112Y66 LUT5 (Prop_lut5_I1_O) 0.152 -0.827 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/p_s1[23]_i_9/O
|
|
net (fo=24670, routed) 8.589 7.761 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/delay_reg[1]
|
|
SLICE_X57Y167 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_B_reg[198][4]/CLR
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock sys_clk rise edge) 20.000 20.000 r
|
|
clock source latency -5.674 14.326
|
|
propagated clock network latency
|
|
3.374 17.699
|
|
clock pessimism -0.514 17.186
|
|
clock uncertainty -0.071 17.115
|
|
SLICE_X57Y167 FDCE (Recov_fdce_C_CLR) -0.629 16.486 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_B_reg[198][4]
|
|
-------------------------------------------------------------------
|
|
required time 16.486
|
|
arrival time -7.761
|
|
-------------------------------------------------------------------
|
|
slack 8.725
|
|
|
|
Slack (MET) : 8.749ns (required time - arrival time)
|
|
Source: pll_clk.u_rst_sys/delay_reg[1]/C
|
|
(rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_B_reg[198][4]/CLR
|
|
(recovery check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Path Group: **async_default**
|
|
Path Type: Recovery (Max at Slow Process Corner)
|
|
Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns)
|
|
Data Path Delay: 10.233ns (logic 0.608ns (5.942%) route 9.625ns (94.058%))
|
|
Logic Levels: 1 (LUT5=1)
|
|
Clock Path Skew: -0.319ns (DCD - SCD + CPR)
|
|
Destination Clock Delay (DCD): -2.301ns = ( 17.699 - 20.000 )
|
|
Source Clock Delay (SCD): -2.496ns
|
|
Clock Pessimism Removal (CPR): -0.514ns
|
|
Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Discrete Jitter (DJ): 0.122ns
|
|
Phase Error (PE): 0.000ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock sys_clk rise edge) 0.000 0.000 r
|
|
clock source latency -6.275 -6.275
|
|
propagated clock network latency
|
|
3.780 -2.496
|
|
SLICE_X106Y69 FDCE 0.000 -2.496 r pll_clk.u_rst_sys/delay_reg[1]/C
|
|
SLICE_X106Y69 FDCE (Prop_fdce_C_Q) 0.456 -2.040 r pll_clk.u_rst_sys/delay_reg[1]/Q
|
|
net (fo=125, routed) 1.036 -1.003 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/valid_sr_reg[6][0]
|
|
SLICE_X112Y66 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/p_s1[23]_i_9/I0
|
|
SLICE_X112Y66 LUT5 (Prop_lut5_I0_O) 0.152 -0.851 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/p_s1[23]_i_9/O
|
|
net (fo=24670, routed) 8.589 7.737 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/delay_reg[1]
|
|
SLICE_X57Y167 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_B_reg[198][4]/CLR
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock sys_clk rise edge) 20.000 20.000 r
|
|
clock source latency -5.674 14.326
|
|
propagated clock network latency
|
|
3.374 17.699
|
|
clock pessimism -0.514 17.186
|
|
clock uncertainty -0.071 17.115
|
|
SLICE_X57Y167 FDCE (Recov_fdce_C_CLR) -0.629 16.486 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_B_reg[198][4]
|
|
-------------------------------------------------------------------
|
|
required time 16.486
|
|
arrival time -7.737
|
|
-------------------------------------------------------------------
|
|
slack 8.749
|
|
|
|
Slack (MET) : 8.751ns (required time - arrival time)
|
|
Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_cnt_reg[3]/C
|
|
(rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_B_reg[218][9]/CLR
|
|
(recovery check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Path Group: **async_default**
|
|
Path Type: Recovery (Max at Slow Process Corner)
|
|
Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns)
|
|
Data Path Delay: 10.309ns (logic 0.668ns (6.480%) route 9.641ns (93.520%))
|
|
Logic Levels: 1 (LUT5=1)
|
|
Clock Path Skew: -0.327ns (DCD - SCD + CPR)
|
|
Destination Clock Delay (DCD): -2.301ns = ( 17.699 - 20.000 )
|
|
Source Clock Delay (SCD): -2.488ns
|
|
Clock Pessimism Removal (CPR): -0.514ns
|
|
Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Discrete Jitter (DJ): 0.122ns
|
|
Phase Error (PE): 0.000ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock sys_clk rise edge) 0.000 0.000 r
|
|
clock source latency -6.275 -6.275
|
|
propagated clock network latency
|
|
3.788 -2.488
|
|
SLICE_X112Y65 FDCE 0.000 -2.488 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_cnt_reg[3]/C
|
|
SLICE_X112Y65 FDCE (Prop_fdce_C_Q) 0.518 -1.970 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_cnt_reg[3]/Q
|
|
net (fo=5, routed) 1.052 -0.917 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/srst_cnt_reg[3]
|
|
SLICE_X112Y66 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/p_s1[23]_i_9/I4
|
|
SLICE_X112Y66 LUT5 (Prop_lut5_I4_O) 0.150 -0.767 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/p_s1[23]_i_9/O
|
|
net (fo=24670, routed) 8.589 7.821 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/delay_reg[1]
|
|
SLICE_X56Y167 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_B_reg[218][9]/CLR
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock sys_clk rise edge) 20.000 20.000 r
|
|
clock source latency -5.674 14.326
|
|
propagated clock network latency
|
|
3.374 17.699
|
|
clock pessimism -0.514 17.186
|
|
clock uncertainty -0.071 17.115
|
|
SLICE_X56Y167 FDCE (Recov_fdce_C_CLR) -0.543 16.572 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_B_reg[218][9]
|
|
-------------------------------------------------------------------
|
|
required time 16.572
|
|
arrival time -7.821
|
|
-------------------------------------------------------------------
|
|
slack 8.751
|
|
|
|
Slack (MET) : 8.791ns (required time - arrival time)
|
|
Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_cnt_reg[0]/C
|
|
(rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_A_reg[202][2]/CLR
|
|
(recovery check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Path Group: **async_default**
|
|
Path Type: Recovery (Max at Slow Process Corner)
|
|
Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns)
|
|
Data Path Delay: 10.182ns (logic 0.668ns (6.560%) route 9.514ns (93.440%))
|
|
Logic Levels: 1 (LUT5=1)
|
|
Clock Path Skew: -0.327ns (DCD - SCD + CPR)
|
|
Destination Clock Delay (DCD): -2.301ns = ( 17.699 - 20.000 )
|
|
Source Clock Delay (SCD): -2.488ns
|
|
Clock Pessimism Removal (CPR): -0.514ns
|
|
Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Discrete Jitter (DJ): 0.122ns
|
|
Phase Error (PE): 0.000ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock sys_clk rise edge) 0.000 0.000 r
|
|
clock source latency -6.275 -6.275
|
|
propagated clock network latency
|
|
3.788 -2.488
|
|
SLICE_X112Y65 FDCE 0.000 -2.488 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_cnt_reg[0]/C
|
|
SLICE_X112Y65 FDCE (Prop_fdce_C_Q) 0.518 -1.970 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_cnt_reg[0]/Q
|
|
net (fo=8, routed) 0.633 -1.336 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/srst_cnt_reg[0]
|
|
SLICE_X112Y66 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/p_s1[23]_i_9/I2
|
|
SLICE_X112Y66 LUT5 (Prop_lut5_I2_O) 0.150 -1.186 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/p_s1[23]_i_9/O
|
|
net (fo=24670, routed) 8.881 7.695 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/delay_reg[1]
|
|
SLICE_X61Y167 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_A_reg[202][2]/CLR
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock sys_clk rise edge) 20.000 20.000 r
|
|
clock source latency -5.674 14.326
|
|
propagated clock network latency
|
|
3.374 17.699
|
|
clock pessimism -0.514 17.186
|
|
clock uncertainty -0.071 17.115
|
|
SLICE_X61Y167 FDCE (Recov_fdce_C_CLR) -0.629 16.486 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_A_reg[202][2]
|
|
-------------------------------------------------------------------
|
|
required time 16.486
|
|
arrival time -7.695
|
|
-------------------------------------------------------------------
|
|
slack 8.791
|
|
|
|
Slack (MET) : 8.791ns (required time - arrival time)
|
|
Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_cnt_reg[0]/C
|
|
(rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_A_reg[202][9]/CLR
|
|
(recovery check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Path Group: **async_default**
|
|
Path Type: Recovery (Max at Slow Process Corner)
|
|
Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns)
|
|
Data Path Delay: 10.182ns (logic 0.668ns (6.560%) route 9.514ns (93.440%))
|
|
Logic Levels: 1 (LUT5=1)
|
|
Clock Path Skew: -0.327ns (DCD - SCD + CPR)
|
|
Destination Clock Delay (DCD): -2.301ns = ( 17.699 - 20.000 )
|
|
Source Clock Delay (SCD): -2.488ns
|
|
Clock Pessimism Removal (CPR): -0.514ns
|
|
Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Discrete Jitter (DJ): 0.122ns
|
|
Phase Error (PE): 0.000ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock sys_clk rise edge) 0.000 0.000 r
|
|
clock source latency -6.275 -6.275
|
|
propagated clock network latency
|
|
3.788 -2.488
|
|
SLICE_X112Y65 FDCE 0.000 -2.488 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_cnt_reg[0]/C
|
|
SLICE_X112Y65 FDCE (Prop_fdce_C_Q) 0.518 -1.970 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_cnt_reg[0]/Q
|
|
net (fo=8, routed) 0.633 -1.336 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/srst_cnt_reg[0]
|
|
SLICE_X112Y66 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/p_s1[23]_i_9/I2
|
|
SLICE_X112Y66 LUT5 (Prop_lut5_I2_O) 0.150 -1.186 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/p_s1[23]_i_9/O
|
|
net (fo=24670, routed) 8.881 7.695 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/delay_reg[1]
|
|
SLICE_X61Y167 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_A_reg[202][9]/CLR
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock sys_clk rise edge) 20.000 20.000 r
|
|
clock source latency -5.674 14.326
|
|
propagated clock network latency
|
|
3.374 17.699
|
|
clock pessimism -0.514 17.186
|
|
clock uncertainty -0.071 17.115
|
|
SLICE_X61Y167 FDCE (Recov_fdce_C_CLR) -0.629 16.486 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_A_reg[202][9]
|
|
-------------------------------------------------------------------
|
|
required time 16.486
|
|
arrival time -7.695
|
|
-------------------------------------------------------------------
|
|
slack 8.791
|
|
|
|
Slack (MET) : 8.791ns (required time - arrival time)
|
|
Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_cnt_reg[0]/C
|
|
(rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_B_reg[202][0]/CLR
|
|
(recovery check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Path Group: **async_default**
|
|
Path Type: Recovery (Max at Slow Process Corner)
|
|
Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns)
|
|
Data Path Delay: 10.182ns (logic 0.668ns (6.560%) route 9.514ns (93.440%))
|
|
Logic Levels: 1 (LUT5=1)
|
|
Clock Path Skew: -0.327ns (DCD - SCD + CPR)
|
|
Destination Clock Delay (DCD): -2.301ns = ( 17.699 - 20.000 )
|
|
Source Clock Delay (SCD): -2.488ns
|
|
Clock Pessimism Removal (CPR): -0.514ns
|
|
Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Discrete Jitter (DJ): 0.122ns
|
|
Phase Error (PE): 0.000ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock sys_clk rise edge) 0.000 0.000 r
|
|
clock source latency -6.275 -6.275
|
|
propagated clock network latency
|
|
3.788 -2.488
|
|
SLICE_X112Y65 FDCE 0.000 -2.488 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_cnt_reg[0]/C
|
|
SLICE_X112Y65 FDCE (Prop_fdce_C_Q) 0.518 -1.970 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_cnt_reg[0]/Q
|
|
net (fo=8, routed) 0.633 -1.336 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/srst_cnt_reg[0]
|
|
SLICE_X112Y66 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/p_s1[23]_i_9/I2
|
|
SLICE_X112Y66 LUT5 (Prop_lut5_I2_O) 0.150 -1.186 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/p_s1[23]_i_9/O
|
|
net (fo=24670, routed) 8.881 7.695 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/delay_reg[1]
|
|
SLICE_X61Y167 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_B_reg[202][0]/CLR
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock sys_clk rise edge) 20.000 20.000 r
|
|
clock source latency -5.674 14.326
|
|
propagated clock network latency
|
|
3.374 17.699
|
|
clock pessimism -0.514 17.186
|
|
clock uncertainty -0.071 17.115
|
|
SLICE_X61Y167 FDCE (Recov_fdce_C_CLR) -0.629 16.486 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_B_reg[202][0]
|
|
-------------------------------------------------------------------
|
|
required time 16.486
|
|
arrival time -7.695
|
|
-------------------------------------------------------------------
|
|
slack 8.791
|
|
|
|
Slack (MET) : 8.791ns (required time - arrival time)
|
|
Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_cnt_reg[0]/C
|
|
(rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_B_reg[202][11]/CLR
|
|
(recovery check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Path Group: **async_default**
|
|
Path Type: Recovery (Max at Slow Process Corner)
|
|
Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns)
|
|
Data Path Delay: 10.182ns (logic 0.668ns (6.560%) route 9.514ns (93.440%))
|
|
Logic Levels: 1 (LUT5=1)
|
|
Clock Path Skew: -0.327ns (DCD - SCD + CPR)
|
|
Destination Clock Delay (DCD): -2.301ns = ( 17.699 - 20.000 )
|
|
Source Clock Delay (SCD): -2.488ns
|
|
Clock Pessimism Removal (CPR): -0.514ns
|
|
Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Discrete Jitter (DJ): 0.122ns
|
|
Phase Error (PE): 0.000ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock sys_clk rise edge) 0.000 0.000 r
|
|
clock source latency -6.275 -6.275
|
|
propagated clock network latency
|
|
3.788 -2.488
|
|
SLICE_X112Y65 FDCE 0.000 -2.488 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_cnt_reg[0]/C
|
|
SLICE_X112Y65 FDCE (Prop_fdce_C_Q) 0.518 -1.970 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_cnt_reg[0]/Q
|
|
net (fo=8, routed) 0.633 -1.336 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/srst_cnt_reg[0]
|
|
SLICE_X112Y66 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/p_s1[23]_i_9/I2
|
|
SLICE_X112Y66 LUT5 (Prop_lut5_I2_O) 0.150 -1.186 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/p_s1[23]_i_9/O
|
|
net (fo=24670, routed) 8.881 7.695 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/delay_reg[1]
|
|
SLICE_X61Y167 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_B_reg[202][11]/CLR
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock sys_clk rise edge) 20.000 20.000 r
|
|
clock source latency -5.674 14.326
|
|
propagated clock network latency
|
|
3.374 17.699
|
|
clock pessimism -0.514 17.186
|
|
clock uncertainty -0.071 17.115
|
|
SLICE_X61Y167 FDCE (Recov_fdce_C_CLR) -0.629 16.486 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_B_reg[202][11]
|
|
-------------------------------------------------------------------
|
|
required time 16.486
|
|
arrival time -7.695
|
|
-------------------------------------------------------------------
|
|
slack 8.791
|
|
|
|
Slack (MET) : 8.791ns (required time - arrival time)
|
|
Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_cnt_reg[0]/C
|
|
(rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_B_reg[202][4]/CLR
|
|
(recovery check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Path Group: **async_default**
|
|
Path Type: Recovery (Max at Slow Process Corner)
|
|
Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns)
|
|
Data Path Delay: 10.182ns (logic 0.668ns (6.560%) route 9.514ns (93.440%))
|
|
Logic Levels: 1 (LUT5=1)
|
|
Clock Path Skew: -0.327ns (DCD - SCD + CPR)
|
|
Destination Clock Delay (DCD): -2.301ns = ( 17.699 - 20.000 )
|
|
Source Clock Delay (SCD): -2.488ns
|
|
Clock Pessimism Removal (CPR): -0.514ns
|
|
Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Discrete Jitter (DJ): 0.122ns
|
|
Phase Error (PE): 0.000ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock sys_clk rise edge) 0.000 0.000 r
|
|
clock source latency -6.275 -6.275
|
|
propagated clock network latency
|
|
3.788 -2.488
|
|
SLICE_X112Y65 FDCE 0.000 -2.488 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_cnt_reg[0]/C
|
|
SLICE_X112Y65 FDCE (Prop_fdce_C_Q) 0.518 -1.970 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_cnt_reg[0]/Q
|
|
net (fo=8, routed) 0.633 -1.336 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/srst_cnt_reg[0]
|
|
SLICE_X112Y66 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/p_s1[23]_i_9/I2
|
|
SLICE_X112Y66 LUT5 (Prop_lut5_I2_O) 0.150 -1.186 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/p_s1[23]_i_9/O
|
|
net (fo=24670, routed) 8.881 7.695 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/delay_reg[1]
|
|
SLICE_X61Y167 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_B_reg[202][4]/CLR
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock sys_clk rise edge) 20.000 20.000 r
|
|
clock source latency -5.674 14.326
|
|
propagated clock network latency
|
|
3.374 17.699
|
|
clock pessimism -0.514 17.186
|
|
clock uncertainty -0.071 17.115
|
|
SLICE_X61Y167 FDCE (Recov_fdce_C_CLR) -0.629 16.486 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_B_reg[202][4]
|
|
-------------------------------------------------------------------
|
|
required time 16.486
|
|
arrival time -7.695
|
|
-------------------------------------------------------------------
|
|
slack 8.791
|
|
|
|
Slack (MET) : 8.811ns (required time - arrival time)
|
|
Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_cnt_reg[1]/C
|
|
(rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_B_reg[218][9]/CLR
|
|
(recovery check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Path Group: **async_default**
|
|
Path Type: Recovery (Max at Slow Process Corner)
|
|
Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns)
|
|
Data Path Delay: 10.249ns (logic 0.670ns (6.537%) route 9.579ns (93.463%))
|
|
Logic Levels: 1 (LUT5=1)
|
|
Clock Path Skew: -0.327ns (DCD - SCD + CPR)
|
|
Destination Clock Delay (DCD): -2.301ns = ( 17.699 - 20.000 )
|
|
Source Clock Delay (SCD): -2.488ns
|
|
Clock Pessimism Removal (CPR): -0.514ns
|
|
Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Discrete Jitter (DJ): 0.122ns
|
|
Phase Error (PE): 0.000ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock sys_clk rise edge) 0.000 0.000 r
|
|
clock source latency -6.275 -6.275
|
|
propagated clock network latency
|
|
3.788 -2.488
|
|
SLICE_X112Y65 FDCE 0.000 -2.488 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_cnt_reg[1]/C
|
|
SLICE_X112Y65 FDCE (Prop_fdce_C_Q) 0.518 -1.970 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_cnt_reg[1]/Q
|
|
net (fo=7, routed) 0.990 -0.979 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/srst_cnt_reg[1]
|
|
SLICE_X112Y66 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/p_s1[23]_i_9/I1
|
|
SLICE_X112Y66 LUT5 (Prop_lut5_I1_O) 0.152 -0.827 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/p_s1[23]_i_9/O
|
|
net (fo=24670, routed) 8.589 7.761 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/delay_reg[1]
|
|
SLICE_X56Y167 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_B_reg[218][9]/CLR
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock sys_clk rise edge) 20.000 20.000 r
|
|
clock source latency -5.674 14.326
|
|
propagated clock network latency
|
|
3.374 17.699
|
|
clock pessimism -0.514 17.186
|
|
clock uncertainty -0.071 17.115
|
|
SLICE_X56Y167 FDCE (Recov_fdce_C_CLR) -0.543 16.572 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_B_reg[218][9]
|
|
-------------------------------------------------------------------
|
|
required time 16.572
|
|
arrival time -7.761
|
|
-------------------------------------------------------------------
|
|
slack 8.811
|
|
|
|
Slack (MET) : 8.835ns (required time - arrival time)
|
|
Source: pll_clk.u_rst_sys/delay_reg[1]/C
|
|
(rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_B_reg[218][9]/CLR
|
|
(recovery check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Path Group: **async_default**
|
|
Path Type: Recovery (Max at Slow Process Corner)
|
|
Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns)
|
|
Data Path Delay: 10.233ns (logic 0.608ns (5.942%) route 9.625ns (94.058%))
|
|
Logic Levels: 1 (LUT5=1)
|
|
Clock Path Skew: -0.319ns (DCD - SCD + CPR)
|
|
Destination Clock Delay (DCD): -2.301ns = ( 17.699 - 20.000 )
|
|
Source Clock Delay (SCD): -2.496ns
|
|
Clock Pessimism Removal (CPR): -0.514ns
|
|
Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Discrete Jitter (DJ): 0.122ns
|
|
Phase Error (PE): 0.000ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock sys_clk rise edge) 0.000 0.000 r
|
|
clock source latency -6.275 -6.275
|
|
propagated clock network latency
|
|
3.780 -2.496
|
|
SLICE_X106Y69 FDCE 0.000 -2.496 r pll_clk.u_rst_sys/delay_reg[1]/C
|
|
SLICE_X106Y69 FDCE (Prop_fdce_C_Q) 0.456 -2.040 r pll_clk.u_rst_sys/delay_reg[1]/Q
|
|
net (fo=125, routed) 1.036 -1.003 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/valid_sr_reg[6][0]
|
|
SLICE_X112Y66 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/p_s1[23]_i_9/I0
|
|
SLICE_X112Y66 LUT5 (Prop_lut5_I0_O) 0.152 -0.851 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/p_s1[23]_i_9/O
|
|
net (fo=24670, routed) 8.589 7.737 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/delay_reg[1]
|
|
SLICE_X56Y167 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_B_reg[218][9]/CLR
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock sys_clk rise edge) 20.000 20.000 r
|
|
clock source latency -5.674 14.326
|
|
propagated clock network latency
|
|
3.374 17.699
|
|
clock pessimism -0.514 17.186
|
|
clock uncertainty -0.071 17.115
|
|
SLICE_X56Y167 FDCE (Recov_fdce_C_CLR) -0.543 16.572 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_B_reg[218][9]
|
|
-------------------------------------------------------------------
|
|
required time 16.572
|
|
arrival time -7.737
|
|
-------------------------------------------------------------------
|
|
slack 8.835
|
|
|
|
Slack (MET) : 8.837ns (required time - arrival time)
|
|
Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_cnt_reg[2]/C
|
|
(rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_A_reg[202][2]/CLR
|
|
(recovery check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Path Group: **async_default**
|
|
Path Type: Recovery (Max at Slow Process Corner)
|
|
Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns)
|
|
Data Path Delay: 10.137ns (logic 0.766ns (7.557%) route 9.371ns (92.443%))
|
|
Logic Levels: 1 (LUT5=1)
|
|
Clock Path Skew: -0.327ns (DCD - SCD + CPR)
|
|
Destination Clock Delay (DCD): -2.301ns = ( 17.699 - 20.000 )
|
|
Source Clock Delay (SCD): -2.488ns
|
|
Clock Pessimism Removal (CPR): -0.514ns
|
|
Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Discrete Jitter (DJ): 0.122ns
|
|
Phase Error (PE): 0.000ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock sys_clk rise edge) 0.000 0.000 r
|
|
clock source latency -6.275 -6.275
|
|
propagated clock network latency
|
|
3.788 -2.488
|
|
SLICE_X112Y65 FDCE 0.000 -2.488 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_cnt_reg[2]/C
|
|
SLICE_X112Y65 FDCE (Prop_fdce_C_Q) 0.478 -2.010 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_cnt_reg[2]/Q
|
|
net (fo=6, routed) 0.490 -1.520 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/srst_cnt_reg[2]
|
|
SLICE_X112Y66 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/p_s1[23]_i_9/I3
|
|
SLICE_X112Y66 LUT5 (Prop_lut5_I3_O) 0.288 -1.232 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/p_s1[23]_i_9/O
|
|
net (fo=24670, routed) 8.881 7.649 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/delay_reg[1]
|
|
SLICE_X61Y167 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_A_reg[202][2]/CLR
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock sys_clk rise edge) 20.000 20.000 r
|
|
clock source latency -5.674 14.326
|
|
propagated clock network latency
|
|
3.374 17.699
|
|
clock pessimism -0.514 17.186
|
|
clock uncertainty -0.071 17.115
|
|
SLICE_X61Y167 FDCE (Recov_fdce_C_CLR) -0.629 16.486 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_A_reg[202][2]
|
|
-------------------------------------------------------------------
|
|
required time 16.486
|
|
arrival time -7.649
|
|
-------------------------------------------------------------------
|
|
slack 8.837
|
|
|
|
Slack (MET) : 8.837ns (required time - arrival time)
|
|
Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_cnt_reg[2]/C
|
|
(rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_A_reg[202][9]/CLR
|
|
(recovery check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Path Group: **async_default**
|
|
Path Type: Recovery (Max at Slow Process Corner)
|
|
Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns)
|
|
Data Path Delay: 10.137ns (logic 0.766ns (7.557%) route 9.371ns (92.443%))
|
|
Logic Levels: 1 (LUT5=1)
|
|
Clock Path Skew: -0.327ns (DCD - SCD + CPR)
|
|
Destination Clock Delay (DCD): -2.301ns = ( 17.699 - 20.000 )
|
|
Source Clock Delay (SCD): -2.488ns
|
|
Clock Pessimism Removal (CPR): -0.514ns
|
|
Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Discrete Jitter (DJ): 0.122ns
|
|
Phase Error (PE): 0.000ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock sys_clk rise edge) 0.000 0.000 r
|
|
clock source latency -6.275 -6.275
|
|
propagated clock network latency
|
|
3.788 -2.488
|
|
SLICE_X112Y65 FDCE 0.000 -2.488 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_cnt_reg[2]/C
|
|
SLICE_X112Y65 FDCE (Prop_fdce_C_Q) 0.478 -2.010 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_cnt_reg[2]/Q
|
|
net (fo=6, routed) 0.490 -1.520 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/srst_cnt_reg[2]
|
|
SLICE_X112Y66 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/p_s1[23]_i_9/I3
|
|
SLICE_X112Y66 LUT5 (Prop_lut5_I3_O) 0.288 -1.232 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/p_s1[23]_i_9/O
|
|
net (fo=24670, routed) 8.881 7.649 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/delay_reg[1]
|
|
SLICE_X61Y167 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_A_reg[202][9]/CLR
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock sys_clk rise edge) 20.000 20.000 r
|
|
clock source latency -5.674 14.326
|
|
propagated clock network latency
|
|
3.374 17.699
|
|
clock pessimism -0.514 17.186
|
|
clock uncertainty -0.071 17.115
|
|
SLICE_X61Y167 FDCE (Recov_fdce_C_CLR) -0.629 16.486 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_A_reg[202][9]
|
|
-------------------------------------------------------------------
|
|
required time 16.486
|
|
arrival time -7.649
|
|
-------------------------------------------------------------------
|
|
slack 8.837
|
|
|
|
Slack (MET) : 8.837ns (required time - arrival time)
|
|
Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_cnt_reg[2]/C
|
|
(rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_B_reg[202][0]/CLR
|
|
(recovery check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Path Group: **async_default**
|
|
Path Type: Recovery (Max at Slow Process Corner)
|
|
Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns)
|
|
Data Path Delay: 10.137ns (logic 0.766ns (7.557%) route 9.371ns (92.443%))
|
|
Logic Levels: 1 (LUT5=1)
|
|
Clock Path Skew: -0.327ns (DCD - SCD + CPR)
|
|
Destination Clock Delay (DCD): -2.301ns = ( 17.699 - 20.000 )
|
|
Source Clock Delay (SCD): -2.488ns
|
|
Clock Pessimism Removal (CPR): -0.514ns
|
|
Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Discrete Jitter (DJ): 0.122ns
|
|
Phase Error (PE): 0.000ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock sys_clk rise edge) 0.000 0.000 r
|
|
clock source latency -6.275 -6.275
|
|
propagated clock network latency
|
|
3.788 -2.488
|
|
SLICE_X112Y65 FDCE 0.000 -2.488 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_cnt_reg[2]/C
|
|
SLICE_X112Y65 FDCE (Prop_fdce_C_Q) 0.478 -2.010 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_cnt_reg[2]/Q
|
|
net (fo=6, routed) 0.490 -1.520 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/srst_cnt_reg[2]
|
|
SLICE_X112Y66 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/p_s1[23]_i_9/I3
|
|
SLICE_X112Y66 LUT5 (Prop_lut5_I3_O) 0.288 -1.232 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/p_s1[23]_i_9/O
|
|
net (fo=24670, routed) 8.881 7.649 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/delay_reg[1]
|
|
SLICE_X61Y167 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_B_reg[202][0]/CLR
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock sys_clk rise edge) 20.000 20.000 r
|
|
clock source latency -5.674 14.326
|
|
propagated clock network latency
|
|
3.374 17.699
|
|
clock pessimism -0.514 17.186
|
|
clock uncertainty -0.071 17.115
|
|
SLICE_X61Y167 FDCE (Recov_fdce_C_CLR) -0.629 16.486 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_B_reg[202][0]
|
|
-------------------------------------------------------------------
|
|
required time 16.486
|
|
arrival time -7.649
|
|
-------------------------------------------------------------------
|
|
slack 8.837
|
|
|
|
Slack (MET) : 8.837ns (required time - arrival time)
|
|
Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_cnt_reg[2]/C
|
|
(rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_B_reg[202][11]/CLR
|
|
(recovery check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Path Group: **async_default**
|
|
Path Type: Recovery (Max at Slow Process Corner)
|
|
Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns)
|
|
Data Path Delay: 10.137ns (logic 0.766ns (7.557%) route 9.371ns (92.443%))
|
|
Logic Levels: 1 (LUT5=1)
|
|
Clock Path Skew: -0.327ns (DCD - SCD + CPR)
|
|
Destination Clock Delay (DCD): -2.301ns = ( 17.699 - 20.000 )
|
|
Source Clock Delay (SCD): -2.488ns
|
|
Clock Pessimism Removal (CPR): -0.514ns
|
|
Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Discrete Jitter (DJ): 0.122ns
|
|
Phase Error (PE): 0.000ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock sys_clk rise edge) 0.000 0.000 r
|
|
clock source latency -6.275 -6.275
|
|
propagated clock network latency
|
|
3.788 -2.488
|
|
SLICE_X112Y65 FDCE 0.000 -2.488 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_cnt_reg[2]/C
|
|
SLICE_X112Y65 FDCE (Prop_fdce_C_Q) 0.478 -2.010 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_cnt_reg[2]/Q
|
|
net (fo=6, routed) 0.490 -1.520 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/srst_cnt_reg[2]
|
|
SLICE_X112Y66 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/p_s1[23]_i_9/I3
|
|
SLICE_X112Y66 LUT5 (Prop_lut5_I3_O) 0.288 -1.232 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/p_s1[23]_i_9/O
|
|
net (fo=24670, routed) 8.881 7.649 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/delay_reg[1]
|
|
SLICE_X61Y167 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_B_reg[202][11]/CLR
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock sys_clk rise edge) 20.000 20.000 r
|
|
clock source latency -5.674 14.326
|
|
propagated clock network latency
|
|
3.374 17.699
|
|
clock pessimism -0.514 17.186
|
|
clock uncertainty -0.071 17.115
|
|
SLICE_X61Y167 FDCE (Recov_fdce_C_CLR) -0.629 16.486 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_B_reg[202][11]
|
|
-------------------------------------------------------------------
|
|
required time 16.486
|
|
arrival time -7.649
|
|
-------------------------------------------------------------------
|
|
slack 8.837
|
|
|
|
Slack (MET) : 8.837ns (required time - arrival time)
|
|
Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_cnt_reg[2]/C
|
|
(rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_B_reg[202][4]/CLR
|
|
(recovery check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Path Group: **async_default**
|
|
Path Type: Recovery (Max at Slow Process Corner)
|
|
Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns)
|
|
Data Path Delay: 10.137ns (logic 0.766ns (7.557%) route 9.371ns (92.443%))
|
|
Logic Levels: 1 (LUT5=1)
|
|
Clock Path Skew: -0.327ns (DCD - SCD + CPR)
|
|
Destination Clock Delay (DCD): -2.301ns = ( 17.699 - 20.000 )
|
|
Source Clock Delay (SCD): -2.488ns
|
|
Clock Pessimism Removal (CPR): -0.514ns
|
|
Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Discrete Jitter (DJ): 0.122ns
|
|
Phase Error (PE): 0.000ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock sys_clk rise edge) 0.000 0.000 r
|
|
clock source latency -6.275 -6.275
|
|
propagated clock network latency
|
|
3.788 -2.488
|
|
SLICE_X112Y65 FDCE 0.000 -2.488 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_cnt_reg[2]/C
|
|
SLICE_X112Y65 FDCE (Prop_fdce_C_Q) 0.478 -2.010 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_cnt_reg[2]/Q
|
|
net (fo=6, routed) 0.490 -1.520 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/srst_cnt_reg[2]
|
|
SLICE_X112Y66 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/p_s1[23]_i_9/I3
|
|
SLICE_X112Y66 LUT5 (Prop_lut5_I3_O) 0.288 -1.232 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/p_s1[23]_i_9/O
|
|
net (fo=24670, routed) 8.881 7.649 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/delay_reg[1]
|
|
SLICE_X61Y167 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_B_reg[202][4]/CLR
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock sys_clk rise edge) 20.000 20.000 r
|
|
clock source latency -5.674 14.326
|
|
propagated clock network latency
|
|
3.374 17.699
|
|
clock pessimism -0.514 17.186
|
|
clock uncertainty -0.071 17.115
|
|
SLICE_X61Y167 FDCE (Recov_fdce_C_CLR) -0.629 16.486 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_B_reg[202][4]
|
|
-------------------------------------------------------------------
|
|
required time 16.486
|
|
arrival time -7.649
|
|
-------------------------------------------------------------------
|
|
slack 8.837
|
|
|
|
Slack (MET) : 8.856ns (required time - arrival time)
|
|
Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_cnt_reg[3]/C
|
|
(rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_B_reg[214][10]/CLR
|
|
(recovery check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Path Group: **async_default**
|
|
Path Type: Recovery (Max at Slow Process Corner)
|
|
Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns)
|
|
Data Path Delay: 10.115ns (logic 0.668ns (6.604%) route 9.447ns (93.396%))
|
|
Logic Levels: 1 (LUT5=1)
|
|
Clock Path Skew: -0.329ns (DCD - SCD + CPR)
|
|
Destination Clock Delay (DCD): -2.303ns = ( 17.697 - 20.000 )
|
|
Source Clock Delay (SCD): -2.488ns
|
|
Clock Pessimism Removal (CPR): -0.514ns
|
|
Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Discrete Jitter (DJ): 0.122ns
|
|
Phase Error (PE): 0.000ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock sys_clk rise edge) 0.000 0.000 r
|
|
clock source latency -6.275 -6.275
|
|
propagated clock network latency
|
|
3.788 -2.488
|
|
SLICE_X112Y65 FDCE 0.000 -2.488 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_cnt_reg[3]/C
|
|
SLICE_X112Y65 FDCE (Prop_fdce_C_Q) 0.518 -1.970 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_cnt_reg[3]/Q
|
|
net (fo=5, routed) 1.052 -0.917 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/srst_cnt_reg[3]
|
|
SLICE_X112Y66 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/p_s1[23]_i_9/I4
|
|
SLICE_X112Y66 LUT5 (Prop_lut5_I4_O) 0.150 -0.767 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/p_s1[23]_i_9/O
|
|
net (fo=24670, routed) 8.395 7.628 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/delay_reg[1]
|
|
SLICE_X53Y169 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_B_reg[214][10]/CLR
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock sys_clk rise edge) 20.000 20.000 r
|
|
clock source latency -5.674 14.326
|
|
propagated clock network latency
|
|
3.372 17.697
|
|
clock pessimism -0.514 17.184
|
|
clock uncertainty -0.071 17.113
|
|
SLICE_X53Y169 FDCE (Recov_fdce_C_CLR) -0.629 16.484 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_B_reg[214][10]
|
|
-------------------------------------------------------------------
|
|
required time 16.484
|
|
arrival time -7.628
|
|
-------------------------------------------------------------------
|
|
slack 8.856
|
|
|
|
Slack (MET) : 8.856ns (required time - arrival time)
|
|
Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_cnt_reg[3]/C
|
|
(rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_B_reg[214][3]/CLR
|
|
(recovery check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Path Group: **async_default**
|
|
Path Type: Recovery (Max at Slow Process Corner)
|
|
Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns)
|
|
Data Path Delay: 10.115ns (logic 0.668ns (6.604%) route 9.447ns (93.396%))
|
|
Logic Levels: 1 (LUT5=1)
|
|
Clock Path Skew: -0.329ns (DCD - SCD + CPR)
|
|
Destination Clock Delay (DCD): -2.303ns = ( 17.697 - 20.000 )
|
|
Source Clock Delay (SCD): -2.488ns
|
|
Clock Pessimism Removal (CPR): -0.514ns
|
|
Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Discrete Jitter (DJ): 0.122ns
|
|
Phase Error (PE): 0.000ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock sys_clk rise edge) 0.000 0.000 r
|
|
clock source latency -6.275 -6.275
|
|
propagated clock network latency
|
|
3.788 -2.488
|
|
SLICE_X112Y65 FDCE 0.000 -2.488 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_cnt_reg[3]/C
|
|
SLICE_X112Y65 FDCE (Prop_fdce_C_Q) 0.518 -1.970 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_cnt_reg[3]/Q
|
|
net (fo=5, routed) 1.052 -0.917 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/srst_cnt_reg[3]
|
|
SLICE_X112Y66 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/p_s1[23]_i_9/I4
|
|
SLICE_X112Y66 LUT5 (Prop_lut5_I4_O) 0.150 -0.767 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/p_s1[23]_i_9/O
|
|
net (fo=24670, routed) 8.395 7.628 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/delay_reg[1]
|
|
SLICE_X53Y169 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_B_reg[214][3]/CLR
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock sys_clk rise edge) 20.000 20.000 r
|
|
clock source latency -5.674 14.326
|
|
propagated clock network latency
|
|
3.372 17.697
|
|
clock pessimism -0.514 17.184
|
|
clock uncertainty -0.071 17.113
|
|
SLICE_X53Y169 FDCE (Recov_fdce_C_CLR) -0.629 16.484 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_B_reg[214][3]
|
|
-------------------------------------------------------------------
|
|
required time 16.484
|
|
arrival time -7.628
|
|
-------------------------------------------------------------------
|
|
slack 8.856
|
|
|
|
Slack (MET) : 8.856ns (required time - arrival time)
|
|
Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_cnt_reg[3]/C
|
|
(rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_B_reg[214][8]/CLR
|
|
(recovery check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Path Group: **async_default**
|
|
Path Type: Recovery (Max at Slow Process Corner)
|
|
Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns)
|
|
Data Path Delay: 10.115ns (logic 0.668ns (6.604%) route 9.447ns (93.396%))
|
|
Logic Levels: 1 (LUT5=1)
|
|
Clock Path Skew: -0.329ns (DCD - SCD + CPR)
|
|
Destination Clock Delay (DCD): -2.303ns = ( 17.697 - 20.000 )
|
|
Source Clock Delay (SCD): -2.488ns
|
|
Clock Pessimism Removal (CPR): -0.514ns
|
|
Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Discrete Jitter (DJ): 0.122ns
|
|
Phase Error (PE): 0.000ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock sys_clk rise edge) 0.000 0.000 r
|
|
clock source latency -6.275 -6.275
|
|
propagated clock network latency
|
|
3.788 -2.488
|
|
SLICE_X112Y65 FDCE 0.000 -2.488 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_cnt_reg[3]/C
|
|
SLICE_X112Y65 FDCE (Prop_fdce_C_Q) 0.518 -1.970 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_cnt_reg[3]/Q
|
|
net (fo=5, routed) 1.052 -0.917 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/srst_cnt_reg[3]
|
|
SLICE_X112Y66 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/p_s1[23]_i_9/I4
|
|
SLICE_X112Y66 LUT5 (Prop_lut5_I4_O) 0.150 -0.767 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/p_s1[23]_i_9/O
|
|
net (fo=24670, routed) 8.395 7.628 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/delay_reg[1]
|
|
SLICE_X53Y169 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_B_reg[214][8]/CLR
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock sys_clk rise edge) 20.000 20.000 r
|
|
clock source latency -5.674 14.326
|
|
propagated clock network latency
|
|
3.372 17.697
|
|
clock pessimism -0.514 17.184
|
|
clock uncertainty -0.071 17.113
|
|
SLICE_X53Y169 FDCE (Recov_fdce_C_CLR) -0.629 16.484 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_B_reg[214][8]
|
|
-------------------------------------------------------------------
|
|
required time 16.484
|
|
arrival time -7.628
|
|
-------------------------------------------------------------------
|
|
slack 8.856
|
|
|
|
Slack (MET) : 8.877ns (required time - arrival time)
|
|
Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_cnt_reg[0]/C
|
|
(rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_B_reg[216][2]/CLR
|
|
(recovery check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Path Group: **async_default**
|
|
Path Type: Recovery (Max at Slow Process Corner)
|
|
Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns)
|
|
Data Path Delay: 10.182ns (logic 0.668ns (6.560%) route 9.514ns (93.440%))
|
|
Logic Levels: 1 (LUT5=1)
|
|
Clock Path Skew: -0.327ns (DCD - SCD + CPR)
|
|
Destination Clock Delay (DCD): -2.301ns = ( 17.699 - 20.000 )
|
|
Source Clock Delay (SCD): -2.488ns
|
|
Clock Pessimism Removal (CPR): -0.514ns
|
|
Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Discrete Jitter (DJ): 0.122ns
|
|
Phase Error (PE): 0.000ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock sys_clk rise edge) 0.000 0.000 r
|
|
clock source latency -6.275 -6.275
|
|
propagated clock network latency
|
|
3.788 -2.488
|
|
SLICE_X112Y65 FDCE 0.000 -2.488 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_cnt_reg[0]/C
|
|
SLICE_X112Y65 FDCE (Prop_fdce_C_Q) 0.518 -1.970 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_cnt_reg[0]/Q
|
|
net (fo=8, routed) 0.633 -1.336 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/srst_cnt_reg[0]
|
|
SLICE_X112Y66 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/p_s1[23]_i_9/I2
|
|
SLICE_X112Y66 LUT5 (Prop_lut5_I2_O) 0.150 -1.186 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/p_s1[23]_i_9/O
|
|
net (fo=24670, routed) 8.881 7.695 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/delay_reg[1]
|
|
SLICE_X60Y167 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_B_reg[216][2]/CLR
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock sys_clk rise edge) 20.000 20.000 r
|
|
clock source latency -5.674 14.326
|
|
propagated clock network latency
|
|
3.374 17.699
|
|
clock pessimism -0.514 17.186
|
|
clock uncertainty -0.071 17.115
|
|
SLICE_X60Y167 FDCE (Recov_fdce_C_CLR) -0.543 16.572 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_B_reg[216][2]
|
|
-------------------------------------------------------------------
|
|
required time 16.572
|
|
arrival time -7.695
|
|
-------------------------------------------------------------------
|
|
slack 8.877
|
|
|
|
Slack (MET) : 8.877ns (required time - arrival time)
|
|
Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_cnt_reg[0]/C
|
|
(rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_B_reg[216][4]/CLR
|
|
(recovery check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Path Group: **async_default**
|
|
Path Type: Recovery (Max at Slow Process Corner)
|
|
Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns)
|
|
Data Path Delay: 10.182ns (logic 0.668ns (6.560%) route 9.514ns (93.440%))
|
|
Logic Levels: 1 (LUT5=1)
|
|
Clock Path Skew: -0.327ns (DCD - SCD + CPR)
|
|
Destination Clock Delay (DCD): -2.301ns = ( 17.699 - 20.000 )
|
|
Source Clock Delay (SCD): -2.488ns
|
|
Clock Pessimism Removal (CPR): -0.514ns
|
|
Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Discrete Jitter (DJ): 0.122ns
|
|
Phase Error (PE): 0.000ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock sys_clk rise edge) 0.000 0.000 r
|
|
clock source latency -6.275 -6.275
|
|
propagated clock network latency
|
|
3.788 -2.488
|
|
SLICE_X112Y65 FDCE 0.000 -2.488 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_cnt_reg[0]/C
|
|
SLICE_X112Y65 FDCE (Prop_fdce_C_Q) 0.518 -1.970 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_cnt_reg[0]/Q
|
|
net (fo=8, routed) 0.633 -1.336 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/srst_cnt_reg[0]
|
|
SLICE_X112Y66 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/p_s1[23]_i_9/I2
|
|
SLICE_X112Y66 LUT5 (Prop_lut5_I2_O) 0.150 -1.186 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/p_s1[23]_i_9/O
|
|
net (fo=24670, routed) 8.881 7.695 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/delay_reg[1]
|
|
SLICE_X60Y167 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_B_reg[216][4]/CLR
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock sys_clk rise edge) 20.000 20.000 r
|
|
clock source latency -5.674 14.326
|
|
propagated clock network latency
|
|
3.374 17.699
|
|
clock pessimism -0.514 17.186
|
|
clock uncertainty -0.071 17.115
|
|
SLICE_X60Y167 FDCE (Recov_fdce_C_CLR) -0.543 16.572 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_B_reg[216][4]
|
|
-------------------------------------------------------------------
|
|
required time 16.572
|
|
arrival time -7.695
|
|
-------------------------------------------------------------------
|
|
slack 8.877
|
|
|
|
Slack (MET) : 8.877ns (required time - arrival time)
|
|
Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_cnt_reg[0]/C
|
|
(rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_B_reg[216][5]/CLR
|
|
(recovery check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Path Group: **async_default**
|
|
Path Type: Recovery (Max at Slow Process Corner)
|
|
Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns)
|
|
Data Path Delay: 10.182ns (logic 0.668ns (6.560%) route 9.514ns (93.440%))
|
|
Logic Levels: 1 (LUT5=1)
|
|
Clock Path Skew: -0.327ns (DCD - SCD + CPR)
|
|
Destination Clock Delay (DCD): -2.301ns = ( 17.699 - 20.000 )
|
|
Source Clock Delay (SCD): -2.488ns
|
|
Clock Pessimism Removal (CPR): -0.514ns
|
|
Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Discrete Jitter (DJ): 0.122ns
|
|
Phase Error (PE): 0.000ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock sys_clk rise edge) 0.000 0.000 r
|
|
clock source latency -6.275 -6.275
|
|
propagated clock network latency
|
|
3.788 -2.488
|
|
SLICE_X112Y65 FDCE 0.000 -2.488 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_cnt_reg[0]/C
|
|
SLICE_X112Y65 FDCE (Prop_fdce_C_Q) 0.518 -1.970 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_cnt_reg[0]/Q
|
|
net (fo=8, routed) 0.633 -1.336 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/srst_cnt_reg[0]
|
|
SLICE_X112Y66 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/p_s1[23]_i_9/I2
|
|
SLICE_X112Y66 LUT5 (Prop_lut5_I2_O) 0.150 -1.186 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/p_s1[23]_i_9/O
|
|
net (fo=24670, routed) 8.881 7.695 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/delay_reg[1]
|
|
SLICE_X60Y167 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_B_reg[216][5]/CLR
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock sys_clk rise edge) 20.000 20.000 r
|
|
clock source latency -5.674 14.326
|
|
propagated clock network latency
|
|
3.374 17.699
|
|
clock pessimism -0.514 17.186
|
|
clock uncertainty -0.071 17.115
|
|
SLICE_X60Y167 FDCE (Recov_fdce_C_CLR) -0.543 16.572 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_B_reg[216][5]
|
|
-------------------------------------------------------------------
|
|
required time 16.572
|
|
arrival time -7.695
|
|
-------------------------------------------------------------------
|
|
slack 8.877
|
|
|
|
Slack (MET) : 8.877ns (required time - arrival time)
|
|
Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_cnt_reg[0]/C
|
|
(rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_B_reg[216][9]/CLR
|
|
(recovery check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Path Group: **async_default**
|
|
Path Type: Recovery (Max at Slow Process Corner)
|
|
Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns)
|
|
Data Path Delay: 10.182ns (logic 0.668ns (6.560%) route 9.514ns (93.440%))
|
|
Logic Levels: 1 (LUT5=1)
|
|
Clock Path Skew: -0.327ns (DCD - SCD + CPR)
|
|
Destination Clock Delay (DCD): -2.301ns = ( 17.699 - 20.000 )
|
|
Source Clock Delay (SCD): -2.488ns
|
|
Clock Pessimism Removal (CPR): -0.514ns
|
|
Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Discrete Jitter (DJ): 0.122ns
|
|
Phase Error (PE): 0.000ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock sys_clk rise edge) 0.000 0.000 r
|
|
clock source latency -6.275 -6.275
|
|
propagated clock network latency
|
|
3.788 -2.488
|
|
SLICE_X112Y65 FDCE 0.000 -2.488 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_cnt_reg[0]/C
|
|
SLICE_X112Y65 FDCE (Prop_fdce_C_Q) 0.518 -1.970 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_cnt_reg[0]/Q
|
|
net (fo=8, routed) 0.633 -1.336 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/srst_cnt_reg[0]
|
|
SLICE_X112Y66 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/p_s1[23]_i_9/I2
|
|
SLICE_X112Y66 LUT5 (Prop_lut5_I2_O) 0.150 -1.186 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/p_s1[23]_i_9/O
|
|
net (fo=24670, routed) 8.881 7.695 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/delay_reg[1]
|
|
SLICE_X60Y167 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_B_reg[216][9]/CLR
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock sys_clk rise edge) 20.000 20.000 r
|
|
clock source latency -5.674 14.326
|
|
propagated clock network latency
|
|
3.374 17.699
|
|
clock pessimism -0.514 17.186
|
|
clock uncertainty -0.071 17.115
|
|
SLICE_X60Y167 FDCE (Recov_fdce_C_CLR) -0.543 16.572 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_B_reg[216][9]
|
|
-------------------------------------------------------------------
|
|
required time 16.572
|
|
arrival time -7.695
|
|
-------------------------------------------------------------------
|
|
slack 8.877
|
|
|
|
Slack (MET) : 8.896ns (required time - arrival time)
|
|
Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_cnt_reg[3]/C
|
|
(rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/cr_reg[45][1]/CLR
|
|
(recovery check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Path Group: **async_default**
|
|
Path Type: Recovery (Max at Slow Process Corner)
|
|
Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns)
|
|
Data Path Delay: 10.245ns (logic 0.668ns (6.520%) route 9.577ns (93.480%))
|
|
Logic Levels: 1 (LUT5=1)
|
|
Clock Path Skew: -0.159ns (DCD - SCD + CPR)
|
|
Destination Clock Delay (DCD): -2.133ns = ( 17.867 - 20.000 )
|
|
Source Clock Delay (SCD): -2.488ns
|
|
Clock Pessimism Removal (CPR): -0.514ns
|
|
Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Discrete Jitter (DJ): 0.122ns
|
|
Phase Error (PE): 0.000ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock sys_clk rise edge) 0.000 0.000 r
|
|
clock source latency -6.275 -6.275
|
|
propagated clock network latency
|
|
3.788 -2.488
|
|
SLICE_X112Y65 FDCE 0.000 -2.488 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_cnt_reg[3]/C
|
|
SLICE_X112Y65 FDCE (Prop_fdce_C_Q) 0.518 -1.970 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_cnt_reg[3]/Q
|
|
net (fo=5, routed) 1.052 -0.917 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/srst_cnt_reg[3]
|
|
SLICE_X112Y66 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/p_s1[23]_i_9/I4
|
|
SLICE_X112Y66 LUT5 (Prop_lut5_I4_O) 0.150 -0.767 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/p_s1[23]_i_9/O
|
|
net (fo=24670, routed) 8.525 7.758 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/valid_sr_reg[6]
|
|
SLICE_X159Y190 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/cr_reg[45][1]/CLR
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock sys_clk rise edge) 20.000 20.000 r
|
|
clock source latency -5.674 14.326
|
|
propagated clock network latency
|
|
3.542 17.867
|
|
clock pessimism -0.514 17.354
|
|
clock uncertainty -0.071 17.283
|
|
SLICE_X159Y190 FDCE (Recov_fdce_C_CLR) -0.629 16.654 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/cr_reg[45][1]
|
|
-------------------------------------------------------------------
|
|
required time 16.654
|
|
arrival time -7.758
|
|
-------------------------------------------------------------------
|
|
slack 8.896
|
|
|
|
Slack (MET) : 8.896ns (required time - arrival time)
|
|
Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_cnt_reg[3]/C
|
|
(rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/cr_reg[45][2]/CLR
|
|
(recovery check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Path Group: **async_default**
|
|
Path Type: Recovery (Max at Slow Process Corner)
|
|
Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns)
|
|
Data Path Delay: 10.245ns (logic 0.668ns (6.520%) route 9.577ns (93.480%))
|
|
Logic Levels: 1 (LUT5=1)
|
|
Clock Path Skew: -0.159ns (DCD - SCD + CPR)
|
|
Destination Clock Delay (DCD): -2.133ns = ( 17.867 - 20.000 )
|
|
Source Clock Delay (SCD): -2.488ns
|
|
Clock Pessimism Removal (CPR): -0.514ns
|
|
Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Discrete Jitter (DJ): 0.122ns
|
|
Phase Error (PE): 0.000ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock sys_clk rise edge) 0.000 0.000 r
|
|
clock source latency -6.275 -6.275
|
|
propagated clock network latency
|
|
3.788 -2.488
|
|
SLICE_X112Y65 FDCE 0.000 -2.488 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_cnt_reg[3]/C
|
|
SLICE_X112Y65 FDCE (Prop_fdce_C_Q) 0.518 -1.970 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_cnt_reg[3]/Q
|
|
net (fo=5, routed) 1.052 -0.917 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/srst_cnt_reg[3]
|
|
SLICE_X112Y66 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/p_s1[23]_i_9/I4
|
|
SLICE_X112Y66 LUT5 (Prop_lut5_I4_O) 0.150 -0.767 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/p_s1[23]_i_9/O
|
|
net (fo=24670, routed) 8.525 7.758 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/valid_sr_reg[6]
|
|
SLICE_X159Y190 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/cr_reg[45][2]/CLR
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock sys_clk rise edge) 20.000 20.000 r
|
|
clock source latency -5.674 14.326
|
|
propagated clock network latency
|
|
3.542 17.867
|
|
clock pessimism -0.514 17.354
|
|
clock uncertainty -0.071 17.283
|
|
SLICE_X159Y190 FDCE (Recov_fdce_C_CLR) -0.629 16.654 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/cr_reg[45][2]
|
|
-------------------------------------------------------------------
|
|
required time 16.654
|
|
arrival time -7.758
|
|
-------------------------------------------------------------------
|
|
slack 8.896
|
|
|
|
Slack (MET) : 8.896ns (required time - arrival time)
|
|
Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_cnt_reg[3]/C
|
|
(rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/cr_reg[45][4]/CLR
|
|
(recovery check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Path Group: **async_default**
|
|
Path Type: Recovery (Max at Slow Process Corner)
|
|
Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns)
|
|
Data Path Delay: 10.245ns (logic 0.668ns (6.520%) route 9.577ns (93.480%))
|
|
Logic Levels: 1 (LUT5=1)
|
|
Clock Path Skew: -0.159ns (DCD - SCD + CPR)
|
|
Destination Clock Delay (DCD): -2.133ns = ( 17.867 - 20.000 )
|
|
Source Clock Delay (SCD): -2.488ns
|
|
Clock Pessimism Removal (CPR): -0.514ns
|
|
Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Discrete Jitter (DJ): 0.122ns
|
|
Phase Error (PE): 0.000ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock sys_clk rise edge) 0.000 0.000 r
|
|
clock source latency -6.275 -6.275
|
|
propagated clock network latency
|
|
3.788 -2.488
|
|
SLICE_X112Y65 FDCE 0.000 -2.488 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_cnt_reg[3]/C
|
|
SLICE_X112Y65 FDCE (Prop_fdce_C_Q) 0.518 -1.970 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_cnt_reg[3]/Q
|
|
net (fo=5, routed) 1.052 -0.917 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/srst_cnt_reg[3]
|
|
SLICE_X112Y66 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/p_s1[23]_i_9/I4
|
|
SLICE_X112Y66 LUT5 (Prop_lut5_I4_O) 0.150 -0.767 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/p_s1[23]_i_9/O
|
|
net (fo=24670, routed) 8.525 7.758 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/valid_sr_reg[6]
|
|
SLICE_X159Y190 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/cr_reg[45][4]/CLR
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock sys_clk rise edge) 20.000 20.000 r
|
|
clock source latency -5.674 14.326
|
|
propagated clock network latency
|
|
3.542 17.867
|
|
clock pessimism -0.514 17.354
|
|
clock uncertainty -0.071 17.283
|
|
SLICE_X159Y190 FDCE (Recov_fdce_C_CLR) -0.629 16.654 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/cr_reg[45][4]
|
|
-------------------------------------------------------------------
|
|
required time 16.654
|
|
arrival time -7.758
|
|
-------------------------------------------------------------------
|
|
slack 8.896
|
|
|
|
Slack (MET) : 8.896ns (required time - arrival time)
|
|
Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_cnt_reg[3]/C
|
|
(rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/cr_reg[45][5]/CLR
|
|
(recovery check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Path Group: **async_default**
|
|
Path Type: Recovery (Max at Slow Process Corner)
|
|
Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns)
|
|
Data Path Delay: 10.245ns (logic 0.668ns (6.520%) route 9.577ns (93.480%))
|
|
Logic Levels: 1 (LUT5=1)
|
|
Clock Path Skew: -0.159ns (DCD - SCD + CPR)
|
|
Destination Clock Delay (DCD): -2.133ns = ( 17.867 - 20.000 )
|
|
Source Clock Delay (SCD): -2.488ns
|
|
Clock Pessimism Removal (CPR): -0.514ns
|
|
Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Discrete Jitter (DJ): 0.122ns
|
|
Phase Error (PE): 0.000ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock sys_clk rise edge) 0.000 0.000 r
|
|
clock source latency -6.275 -6.275
|
|
propagated clock network latency
|
|
3.788 -2.488
|
|
SLICE_X112Y65 FDCE 0.000 -2.488 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_cnt_reg[3]/C
|
|
SLICE_X112Y65 FDCE (Prop_fdce_C_Q) 0.518 -1.970 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_cnt_reg[3]/Q
|
|
net (fo=5, routed) 1.052 -0.917 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/srst_cnt_reg[3]
|
|
SLICE_X112Y66 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/p_s1[23]_i_9/I4
|
|
SLICE_X112Y66 LUT5 (Prop_lut5_I4_O) 0.150 -0.767 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/p_s1[23]_i_9/O
|
|
net (fo=24670, routed) 8.525 7.758 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/valid_sr_reg[6]
|
|
SLICE_X159Y190 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/cr_reg[45][5]/CLR
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock sys_clk rise edge) 20.000 20.000 r
|
|
clock source latency -5.674 14.326
|
|
propagated clock network latency
|
|
3.542 17.867
|
|
clock pessimism -0.514 17.354
|
|
clock uncertainty -0.071 17.283
|
|
SLICE_X159Y190 FDCE (Recov_fdce_C_CLR) -0.629 16.654 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/cr_reg[45][5]
|
|
-------------------------------------------------------------------
|
|
required time 16.654
|
|
arrival time -7.758
|
|
-------------------------------------------------------------------
|
|
slack 8.896
|
|
|
|
Slack (MET) : 8.916ns (required time - arrival time)
|
|
Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_cnt_reg[1]/C
|
|
(rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_B_reg[214][10]/CLR
|
|
(recovery check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Path Group: **async_default**
|
|
Path Type: Recovery (Max at Slow Process Corner)
|
|
Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns)
|
|
Data Path Delay: 10.056ns (logic 0.670ns (6.663%) route 9.386ns (93.337%))
|
|
Logic Levels: 1 (LUT5=1)
|
|
Clock Path Skew: -0.329ns (DCD - SCD + CPR)
|
|
Destination Clock Delay (DCD): -2.303ns = ( 17.697 - 20.000 )
|
|
Source Clock Delay (SCD): -2.488ns
|
|
Clock Pessimism Removal (CPR): -0.514ns
|
|
Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Discrete Jitter (DJ): 0.122ns
|
|
Phase Error (PE): 0.000ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock sys_clk rise edge) 0.000 0.000 r
|
|
clock source latency -6.275 -6.275
|
|
propagated clock network latency
|
|
3.788 -2.488
|
|
SLICE_X112Y65 FDCE 0.000 -2.488 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_cnt_reg[1]/C
|
|
SLICE_X112Y65 FDCE (Prop_fdce_C_Q) 0.518 -1.970 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_cnt_reg[1]/Q
|
|
net (fo=7, routed) 0.990 -0.979 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/srst_cnt_reg[1]
|
|
SLICE_X112Y66 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/p_s1[23]_i_9/I1
|
|
SLICE_X112Y66 LUT5 (Prop_lut5_I1_O) 0.152 -0.827 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/p_s1[23]_i_9/O
|
|
net (fo=24670, routed) 8.395 7.568 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/delay_reg[1]
|
|
SLICE_X53Y169 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_B_reg[214][10]/CLR
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock sys_clk rise edge) 20.000 20.000 r
|
|
clock source latency -5.674 14.326
|
|
propagated clock network latency
|
|
3.372 17.697
|
|
clock pessimism -0.514 17.184
|
|
clock uncertainty -0.071 17.113
|
|
SLICE_X53Y169 FDCE (Recov_fdce_C_CLR) -0.629 16.484 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_B_reg[214][10]
|
|
-------------------------------------------------------------------
|
|
required time 16.484
|
|
arrival time -7.568
|
|
-------------------------------------------------------------------
|
|
slack 8.916
|
|
|
|
Slack (MET) : 8.916ns (required time - arrival time)
|
|
Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_cnt_reg[1]/C
|
|
(rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_B_reg[214][3]/CLR
|
|
(recovery check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Path Group: **async_default**
|
|
Path Type: Recovery (Max at Slow Process Corner)
|
|
Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns)
|
|
Data Path Delay: 10.056ns (logic 0.670ns (6.663%) route 9.386ns (93.337%))
|
|
Logic Levels: 1 (LUT5=1)
|
|
Clock Path Skew: -0.329ns (DCD - SCD + CPR)
|
|
Destination Clock Delay (DCD): -2.303ns = ( 17.697 - 20.000 )
|
|
Source Clock Delay (SCD): -2.488ns
|
|
Clock Pessimism Removal (CPR): -0.514ns
|
|
Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Discrete Jitter (DJ): 0.122ns
|
|
Phase Error (PE): 0.000ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock sys_clk rise edge) 0.000 0.000 r
|
|
clock source latency -6.275 -6.275
|
|
propagated clock network latency
|
|
3.788 -2.488
|
|
SLICE_X112Y65 FDCE 0.000 -2.488 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_cnt_reg[1]/C
|
|
SLICE_X112Y65 FDCE (Prop_fdce_C_Q) 0.518 -1.970 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_cnt_reg[1]/Q
|
|
net (fo=7, routed) 0.990 -0.979 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/srst_cnt_reg[1]
|
|
SLICE_X112Y66 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/p_s1[23]_i_9/I1
|
|
SLICE_X112Y66 LUT5 (Prop_lut5_I1_O) 0.152 -0.827 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/p_s1[23]_i_9/O
|
|
net (fo=24670, routed) 8.395 7.568 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/delay_reg[1]
|
|
SLICE_X53Y169 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_B_reg[214][3]/CLR
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock sys_clk rise edge) 20.000 20.000 r
|
|
clock source latency -5.674 14.326
|
|
propagated clock network latency
|
|
3.372 17.697
|
|
clock pessimism -0.514 17.184
|
|
clock uncertainty -0.071 17.113
|
|
SLICE_X53Y169 FDCE (Recov_fdce_C_CLR) -0.629 16.484 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_B_reg[214][3]
|
|
-------------------------------------------------------------------
|
|
required time 16.484
|
|
arrival time -7.568
|
|
-------------------------------------------------------------------
|
|
slack 8.916
|
|
|
|
Slack (MET) : 8.916ns (required time - arrival time)
|
|
Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_cnt_reg[1]/C
|
|
(rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_B_reg[214][8]/CLR
|
|
(recovery check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Path Group: **async_default**
|
|
Path Type: Recovery (Max at Slow Process Corner)
|
|
Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns)
|
|
Data Path Delay: 10.056ns (logic 0.670ns (6.663%) route 9.386ns (93.337%))
|
|
Logic Levels: 1 (LUT5=1)
|
|
Clock Path Skew: -0.329ns (DCD - SCD + CPR)
|
|
Destination Clock Delay (DCD): -2.303ns = ( 17.697 - 20.000 )
|
|
Source Clock Delay (SCD): -2.488ns
|
|
Clock Pessimism Removal (CPR): -0.514ns
|
|
Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Discrete Jitter (DJ): 0.122ns
|
|
Phase Error (PE): 0.000ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock sys_clk rise edge) 0.000 0.000 r
|
|
clock source latency -6.275 -6.275
|
|
propagated clock network latency
|
|
3.788 -2.488
|
|
SLICE_X112Y65 FDCE 0.000 -2.488 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_cnt_reg[1]/C
|
|
SLICE_X112Y65 FDCE (Prop_fdce_C_Q) 0.518 -1.970 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_cnt_reg[1]/Q
|
|
net (fo=7, routed) 0.990 -0.979 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/srst_cnt_reg[1]
|
|
SLICE_X112Y66 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/p_s1[23]_i_9/I1
|
|
SLICE_X112Y66 LUT5 (Prop_lut5_I1_O) 0.152 -0.827 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/p_s1[23]_i_9/O
|
|
net (fo=24670, routed) 8.395 7.568 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/delay_reg[1]
|
|
SLICE_X53Y169 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_B_reg[214][8]/CLR
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock sys_clk rise edge) 20.000 20.000 r
|
|
clock source latency -5.674 14.326
|
|
propagated clock network latency
|
|
3.372 17.697
|
|
clock pessimism -0.514 17.184
|
|
clock uncertainty -0.071 17.113
|
|
SLICE_X53Y169 FDCE (Recov_fdce_C_CLR) -0.629 16.484 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_B_reg[214][8]
|
|
-------------------------------------------------------------------
|
|
required time 16.484
|
|
arrival time -7.568
|
|
-------------------------------------------------------------------
|
|
slack 8.916
|
|
|
|
Slack (MET) : 8.923ns (required time - arrival time)
|
|
Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_cnt_reg[3]/C
|
|
(rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/cr_reg[198][0]/CLR
|
|
(recovery check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Path Group: **async_default**
|
|
Path Type: Recovery (Max at Slow Process Corner)
|
|
Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns)
|
|
Data Path Delay: 10.338ns (logic 0.668ns (6.462%) route 9.670ns (93.538%))
|
|
Logic Levels: 1 (LUT5=1)
|
|
Clock Path Skew: -0.040ns (DCD - SCD + CPR)
|
|
Destination Clock Delay (DCD): -2.014ns = ( 17.986 - 20.000 )
|
|
Source Clock Delay (SCD): -2.488ns
|
|
Clock Pessimism Removal (CPR): -0.514ns
|
|
Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Discrete Jitter (DJ): 0.122ns
|
|
Phase Error (PE): 0.000ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock sys_clk rise edge) 0.000 0.000 r
|
|
clock source latency -6.275 -6.275
|
|
propagated clock network latency
|
|
3.788 -2.488
|
|
SLICE_X112Y65 FDCE 0.000 -2.488 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_cnt_reg[3]/C
|
|
SLICE_X112Y65 FDCE (Prop_fdce_C_Q) 0.518 -1.970 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_cnt_reg[3]/Q
|
|
net (fo=5, routed) 1.052 -0.917 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/srst_cnt_reg[3]
|
|
SLICE_X112Y66 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/p_s1[23]_i_9/I4
|
|
SLICE_X112Y66 LUT5 (Prop_lut5_I4_O) 0.150 -0.767 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/p_s1[23]_i_9/O
|
|
net (fo=24670, routed) 8.617 7.850 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/valid_sr_reg[6]
|
|
SLICE_X149Y205 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/cr_reg[198][0]/CLR
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock sys_clk rise edge) 20.000 20.000 r
|
|
clock source latency -5.674 14.326
|
|
propagated clock network latency
|
|
3.660 17.986
|
|
clock pessimism -0.514 17.472
|
|
clock uncertainty -0.071 17.402
|
|
SLICE_X149Y205 FDCE (Recov_fdce_C_CLR) -0.629 16.773 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/cr_reg[198][0]
|
|
-------------------------------------------------------------------
|
|
required time 16.773
|
|
arrival time -7.850
|
|
-------------------------------------------------------------------
|
|
slack 8.923
|
|
|
|
Slack (MET) : 8.923ns (required time - arrival time)
|
|
Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_cnt_reg[3]/C
|
|
(rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/cr_reg[198][2]/CLR
|
|
(recovery check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Path Group: **async_default**
|
|
Path Type: Recovery (Max at Slow Process Corner)
|
|
Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns)
|
|
Data Path Delay: 10.338ns (logic 0.668ns (6.462%) route 9.670ns (93.538%))
|
|
Logic Levels: 1 (LUT5=1)
|
|
Clock Path Skew: -0.040ns (DCD - SCD + CPR)
|
|
Destination Clock Delay (DCD): -2.014ns = ( 17.986 - 20.000 )
|
|
Source Clock Delay (SCD): -2.488ns
|
|
Clock Pessimism Removal (CPR): -0.514ns
|
|
Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Discrete Jitter (DJ): 0.122ns
|
|
Phase Error (PE): 0.000ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock sys_clk rise edge) 0.000 0.000 r
|
|
clock source latency -6.275 -6.275
|
|
propagated clock network latency
|
|
3.788 -2.488
|
|
SLICE_X112Y65 FDCE 0.000 -2.488 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_cnt_reg[3]/C
|
|
SLICE_X112Y65 FDCE (Prop_fdce_C_Q) 0.518 -1.970 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_cnt_reg[3]/Q
|
|
net (fo=5, routed) 1.052 -0.917 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/srst_cnt_reg[3]
|
|
SLICE_X112Y66 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/p_s1[23]_i_9/I4
|
|
SLICE_X112Y66 LUT5 (Prop_lut5_I4_O) 0.150 -0.767 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/p_s1[23]_i_9/O
|
|
net (fo=24670, routed) 8.617 7.850 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/valid_sr_reg[6]
|
|
SLICE_X149Y205 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/cr_reg[198][2]/CLR
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock sys_clk rise edge) 20.000 20.000 r
|
|
clock source latency -5.674 14.326
|
|
propagated clock network latency
|
|
3.660 17.986
|
|
clock pessimism -0.514 17.472
|
|
clock uncertainty -0.071 17.402
|
|
SLICE_X149Y205 FDCE (Recov_fdce_C_CLR) -0.629 16.773 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/cr_reg[198][2]
|
|
-------------------------------------------------------------------
|
|
required time 16.773
|
|
arrival time -7.850
|
|
-------------------------------------------------------------------
|
|
slack 8.923
|
|
|
|
Slack (MET) : 8.923ns (required time - arrival time)
|
|
Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_cnt_reg[3]/C
|
|
(rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/cr_reg[198][5]/CLR
|
|
(recovery check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Path Group: **async_default**
|
|
Path Type: Recovery (Max at Slow Process Corner)
|
|
Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns)
|
|
Data Path Delay: 10.338ns (logic 0.668ns (6.462%) route 9.670ns (93.538%))
|
|
Logic Levels: 1 (LUT5=1)
|
|
Clock Path Skew: -0.040ns (DCD - SCD + CPR)
|
|
Destination Clock Delay (DCD): -2.014ns = ( 17.986 - 20.000 )
|
|
Source Clock Delay (SCD): -2.488ns
|
|
Clock Pessimism Removal (CPR): -0.514ns
|
|
Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Discrete Jitter (DJ): 0.122ns
|
|
Phase Error (PE): 0.000ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock sys_clk rise edge) 0.000 0.000 r
|
|
clock source latency -6.275 -6.275
|
|
propagated clock network latency
|
|
3.788 -2.488
|
|
SLICE_X112Y65 FDCE 0.000 -2.488 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_cnt_reg[3]/C
|
|
SLICE_X112Y65 FDCE (Prop_fdce_C_Q) 0.518 -1.970 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_cnt_reg[3]/Q
|
|
net (fo=5, routed) 1.052 -0.917 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/srst_cnt_reg[3]
|
|
SLICE_X112Y66 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/p_s1[23]_i_9/I4
|
|
SLICE_X112Y66 LUT5 (Prop_lut5_I4_O) 0.150 -0.767 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/p_s1[23]_i_9/O
|
|
net (fo=24670, routed) 8.617 7.850 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/valid_sr_reg[6]
|
|
SLICE_X149Y205 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/cr_reg[198][5]/CLR
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock sys_clk rise edge) 20.000 20.000 r
|
|
clock source latency -5.674 14.326
|
|
propagated clock network latency
|
|
3.660 17.986
|
|
clock pessimism -0.514 17.472
|
|
clock uncertainty -0.071 17.402
|
|
SLICE_X149Y205 FDCE (Recov_fdce_C_CLR) -0.629 16.773 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/cr_reg[198][5]
|
|
-------------------------------------------------------------------
|
|
required time 16.773
|
|
arrival time -7.850
|
|
-------------------------------------------------------------------
|
|
slack 8.923
|
|
|
|
Slack (MET) : 8.923ns (required time - arrival time)
|
|
Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_cnt_reg[2]/C
|
|
(rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_B_reg[216][2]/CLR
|
|
(recovery check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Path Group: **async_default**
|
|
Path Type: Recovery (Max at Slow Process Corner)
|
|
Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns)
|
|
Data Path Delay: 10.137ns (logic 0.766ns (7.557%) route 9.371ns (92.443%))
|
|
Logic Levels: 1 (LUT5=1)
|
|
Clock Path Skew: -0.327ns (DCD - SCD + CPR)
|
|
Destination Clock Delay (DCD): -2.301ns = ( 17.699 - 20.000 )
|
|
Source Clock Delay (SCD): -2.488ns
|
|
Clock Pessimism Removal (CPR): -0.514ns
|
|
Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Discrete Jitter (DJ): 0.122ns
|
|
Phase Error (PE): 0.000ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock sys_clk rise edge) 0.000 0.000 r
|
|
clock source latency -6.275 -6.275
|
|
propagated clock network latency
|
|
3.788 -2.488
|
|
SLICE_X112Y65 FDCE 0.000 -2.488 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_cnt_reg[2]/C
|
|
SLICE_X112Y65 FDCE (Prop_fdce_C_Q) 0.478 -2.010 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_cnt_reg[2]/Q
|
|
net (fo=6, routed) 0.490 -1.520 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/srst_cnt_reg[2]
|
|
SLICE_X112Y66 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/p_s1[23]_i_9/I3
|
|
SLICE_X112Y66 LUT5 (Prop_lut5_I3_O) 0.288 -1.232 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/p_s1[23]_i_9/O
|
|
net (fo=24670, routed) 8.881 7.649 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/delay_reg[1]
|
|
SLICE_X60Y167 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_B_reg[216][2]/CLR
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock sys_clk rise edge) 20.000 20.000 r
|
|
clock source latency -5.674 14.326
|
|
propagated clock network latency
|
|
3.374 17.699
|
|
clock pessimism -0.514 17.186
|
|
clock uncertainty -0.071 17.115
|
|
SLICE_X60Y167 FDCE (Recov_fdce_C_CLR) -0.543 16.572 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_B_reg[216][2]
|
|
-------------------------------------------------------------------
|
|
required time 16.572
|
|
arrival time -7.649
|
|
-------------------------------------------------------------------
|
|
slack 8.923
|
|
|
|
Slack (MET) : 8.923ns (required time - arrival time)
|
|
Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_cnt_reg[2]/C
|
|
(rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_B_reg[216][4]/CLR
|
|
(recovery check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Path Group: **async_default**
|
|
Path Type: Recovery (Max at Slow Process Corner)
|
|
Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns)
|
|
Data Path Delay: 10.137ns (logic 0.766ns (7.557%) route 9.371ns (92.443%))
|
|
Logic Levels: 1 (LUT5=1)
|
|
Clock Path Skew: -0.327ns (DCD - SCD + CPR)
|
|
Destination Clock Delay (DCD): -2.301ns = ( 17.699 - 20.000 )
|
|
Source Clock Delay (SCD): -2.488ns
|
|
Clock Pessimism Removal (CPR): -0.514ns
|
|
Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Discrete Jitter (DJ): 0.122ns
|
|
Phase Error (PE): 0.000ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock sys_clk rise edge) 0.000 0.000 r
|
|
clock source latency -6.275 -6.275
|
|
propagated clock network latency
|
|
3.788 -2.488
|
|
SLICE_X112Y65 FDCE 0.000 -2.488 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_cnt_reg[2]/C
|
|
SLICE_X112Y65 FDCE (Prop_fdce_C_Q) 0.478 -2.010 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_cnt_reg[2]/Q
|
|
net (fo=6, routed) 0.490 -1.520 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/srst_cnt_reg[2]
|
|
SLICE_X112Y66 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/p_s1[23]_i_9/I3
|
|
SLICE_X112Y66 LUT5 (Prop_lut5_I3_O) 0.288 -1.232 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/p_s1[23]_i_9/O
|
|
net (fo=24670, routed) 8.881 7.649 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/delay_reg[1]
|
|
SLICE_X60Y167 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_B_reg[216][4]/CLR
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock sys_clk rise edge) 20.000 20.000 r
|
|
clock source latency -5.674 14.326
|
|
propagated clock network latency
|
|
3.374 17.699
|
|
clock pessimism -0.514 17.186
|
|
clock uncertainty -0.071 17.115
|
|
SLICE_X60Y167 FDCE (Recov_fdce_C_CLR) -0.543 16.572 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_B_reg[216][4]
|
|
-------------------------------------------------------------------
|
|
required time 16.572
|
|
arrival time -7.649
|
|
-------------------------------------------------------------------
|
|
slack 8.923
|
|
|
|
Slack (MET) : 8.923ns (required time - arrival time)
|
|
Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_cnt_reg[2]/C
|
|
(rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_B_reg[216][5]/CLR
|
|
(recovery check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Path Group: **async_default**
|
|
Path Type: Recovery (Max at Slow Process Corner)
|
|
Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns)
|
|
Data Path Delay: 10.137ns (logic 0.766ns (7.557%) route 9.371ns (92.443%))
|
|
Logic Levels: 1 (LUT5=1)
|
|
Clock Path Skew: -0.327ns (DCD - SCD + CPR)
|
|
Destination Clock Delay (DCD): -2.301ns = ( 17.699 - 20.000 )
|
|
Source Clock Delay (SCD): -2.488ns
|
|
Clock Pessimism Removal (CPR): -0.514ns
|
|
Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Discrete Jitter (DJ): 0.122ns
|
|
Phase Error (PE): 0.000ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock sys_clk rise edge) 0.000 0.000 r
|
|
clock source latency -6.275 -6.275
|
|
propagated clock network latency
|
|
3.788 -2.488
|
|
SLICE_X112Y65 FDCE 0.000 -2.488 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_cnt_reg[2]/C
|
|
SLICE_X112Y65 FDCE (Prop_fdce_C_Q) 0.478 -2.010 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_cnt_reg[2]/Q
|
|
net (fo=6, routed) 0.490 -1.520 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/srst_cnt_reg[2]
|
|
SLICE_X112Y66 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/p_s1[23]_i_9/I3
|
|
SLICE_X112Y66 LUT5 (Prop_lut5_I3_O) 0.288 -1.232 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/p_s1[23]_i_9/O
|
|
net (fo=24670, routed) 8.881 7.649 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/delay_reg[1]
|
|
SLICE_X60Y167 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_B_reg[216][5]/CLR
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock sys_clk rise edge) 20.000 20.000 r
|
|
clock source latency -5.674 14.326
|
|
propagated clock network latency
|
|
3.374 17.699
|
|
clock pessimism -0.514 17.186
|
|
clock uncertainty -0.071 17.115
|
|
SLICE_X60Y167 FDCE (Recov_fdce_C_CLR) -0.543 16.572 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_B_reg[216][5]
|
|
-------------------------------------------------------------------
|
|
required time 16.572
|
|
arrival time -7.649
|
|
-------------------------------------------------------------------
|
|
slack 8.923
|
|
|
|
Slack (MET) : 8.923ns (required time - arrival time)
|
|
Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_cnt_reg[2]/C
|
|
(rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_B_reg[216][9]/CLR
|
|
(recovery check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Path Group: **async_default**
|
|
Path Type: Recovery (Max at Slow Process Corner)
|
|
Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns)
|
|
Data Path Delay: 10.137ns (logic 0.766ns (7.557%) route 9.371ns (92.443%))
|
|
Logic Levels: 1 (LUT5=1)
|
|
Clock Path Skew: -0.327ns (DCD - SCD + CPR)
|
|
Destination Clock Delay (DCD): -2.301ns = ( 17.699 - 20.000 )
|
|
Source Clock Delay (SCD): -2.488ns
|
|
Clock Pessimism Removal (CPR): -0.514ns
|
|
Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Discrete Jitter (DJ): 0.122ns
|
|
Phase Error (PE): 0.000ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock sys_clk rise edge) 0.000 0.000 r
|
|
clock source latency -6.275 -6.275
|
|
propagated clock network latency
|
|
3.788 -2.488
|
|
SLICE_X112Y65 FDCE 0.000 -2.488 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_cnt_reg[2]/C
|
|
SLICE_X112Y65 FDCE (Prop_fdce_C_Q) 0.478 -2.010 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_cnt_reg[2]/Q
|
|
net (fo=6, routed) 0.490 -1.520 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/srst_cnt_reg[2]
|
|
SLICE_X112Y66 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/p_s1[23]_i_9/I3
|
|
SLICE_X112Y66 LUT5 (Prop_lut5_I3_O) 0.288 -1.232 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/p_s1[23]_i_9/O
|
|
net (fo=24670, routed) 8.881 7.649 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/delay_reg[1]
|
|
SLICE_X60Y167 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_B_reg[216][9]/CLR
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock sys_clk rise edge) 20.000 20.000 r
|
|
clock source latency -5.674 14.326
|
|
propagated clock network latency
|
|
3.374 17.699
|
|
clock pessimism -0.514 17.186
|
|
clock uncertainty -0.071 17.115
|
|
SLICE_X60Y167 FDCE (Recov_fdce_C_CLR) -0.543 16.572 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_B_reg[216][9]
|
|
-------------------------------------------------------------------
|
|
required time 16.572
|
|
arrival time -7.649
|
|
-------------------------------------------------------------------
|
|
slack 8.923
|
|
|
|
Slack (MET) : 8.940ns (required time - arrival time)
|
|
Source: pll_clk.u_rst_sys/delay_reg[1]/C
|
|
(rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_B_reg[214][10]/CLR
|
|
(recovery check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Path Group: **async_default**
|
|
Path Type: Recovery (Max at Slow Process Corner)
|
|
Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns)
|
|
Data Path Delay: 10.040ns (logic 0.608ns (6.056%) route 9.432ns (93.944%))
|
|
Logic Levels: 1 (LUT5=1)
|
|
Clock Path Skew: -0.321ns (DCD - SCD + CPR)
|
|
Destination Clock Delay (DCD): -2.303ns = ( 17.697 - 20.000 )
|
|
Source Clock Delay (SCD): -2.496ns
|
|
Clock Pessimism Removal (CPR): -0.514ns
|
|
Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Discrete Jitter (DJ): 0.122ns
|
|
Phase Error (PE): 0.000ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock sys_clk rise edge) 0.000 0.000 r
|
|
clock source latency -6.275 -6.275
|
|
propagated clock network latency
|
|
3.780 -2.496
|
|
SLICE_X106Y69 FDCE 0.000 -2.496 r pll_clk.u_rst_sys/delay_reg[1]/C
|
|
SLICE_X106Y69 FDCE (Prop_fdce_C_Q) 0.456 -2.040 r pll_clk.u_rst_sys/delay_reg[1]/Q
|
|
net (fo=125, routed) 1.036 -1.003 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/valid_sr_reg[6][0]
|
|
SLICE_X112Y66 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/p_s1[23]_i_9/I0
|
|
SLICE_X112Y66 LUT5 (Prop_lut5_I0_O) 0.152 -0.851 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/p_s1[23]_i_9/O
|
|
net (fo=24670, routed) 8.395 7.544 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/delay_reg[1]
|
|
SLICE_X53Y169 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_B_reg[214][10]/CLR
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock sys_clk rise edge) 20.000 20.000 r
|
|
clock source latency -5.674 14.326
|
|
propagated clock network latency
|
|
3.372 17.697
|
|
clock pessimism -0.514 17.184
|
|
clock uncertainty -0.071 17.113
|
|
SLICE_X53Y169 FDCE (Recov_fdce_C_CLR) -0.629 16.484 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_B_reg[214][10]
|
|
-------------------------------------------------------------------
|
|
required time 16.484
|
|
arrival time -7.544
|
|
-------------------------------------------------------------------
|
|
slack 8.940
|
|
|
|
Slack (MET) : 8.940ns (required time - arrival time)
|
|
Source: pll_clk.u_rst_sys/delay_reg[1]/C
|
|
(rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_B_reg[214][3]/CLR
|
|
(recovery check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Path Group: **async_default**
|
|
Path Type: Recovery (Max at Slow Process Corner)
|
|
Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns)
|
|
Data Path Delay: 10.040ns (logic 0.608ns (6.056%) route 9.432ns (93.944%))
|
|
Logic Levels: 1 (LUT5=1)
|
|
Clock Path Skew: -0.321ns (DCD - SCD + CPR)
|
|
Destination Clock Delay (DCD): -2.303ns = ( 17.697 - 20.000 )
|
|
Source Clock Delay (SCD): -2.496ns
|
|
Clock Pessimism Removal (CPR): -0.514ns
|
|
Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Discrete Jitter (DJ): 0.122ns
|
|
Phase Error (PE): 0.000ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock sys_clk rise edge) 0.000 0.000 r
|
|
clock source latency -6.275 -6.275
|
|
propagated clock network latency
|
|
3.780 -2.496
|
|
SLICE_X106Y69 FDCE 0.000 -2.496 r pll_clk.u_rst_sys/delay_reg[1]/C
|
|
SLICE_X106Y69 FDCE (Prop_fdce_C_Q) 0.456 -2.040 r pll_clk.u_rst_sys/delay_reg[1]/Q
|
|
net (fo=125, routed) 1.036 -1.003 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/valid_sr_reg[6][0]
|
|
SLICE_X112Y66 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/p_s1[23]_i_9/I0
|
|
SLICE_X112Y66 LUT5 (Prop_lut5_I0_O) 0.152 -0.851 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/p_s1[23]_i_9/O
|
|
net (fo=24670, routed) 8.395 7.544 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/delay_reg[1]
|
|
SLICE_X53Y169 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_B_reg[214][3]/CLR
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock sys_clk rise edge) 20.000 20.000 r
|
|
clock source latency -5.674 14.326
|
|
propagated clock network latency
|
|
3.372 17.697
|
|
clock pessimism -0.514 17.184
|
|
clock uncertainty -0.071 17.113
|
|
SLICE_X53Y169 FDCE (Recov_fdce_C_CLR) -0.629 16.484 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_B_reg[214][3]
|
|
-------------------------------------------------------------------
|
|
required time 16.484
|
|
arrival time -7.544
|
|
-------------------------------------------------------------------
|
|
slack 8.940
|
|
|
|
Slack (MET) : 8.940ns (required time - arrival time)
|
|
Source: pll_clk.u_rst_sys/delay_reg[1]/C
|
|
(rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_B_reg[214][8]/CLR
|
|
(recovery check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Path Group: **async_default**
|
|
Path Type: Recovery (Max at Slow Process Corner)
|
|
Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns)
|
|
Data Path Delay: 10.040ns (logic 0.608ns (6.056%) route 9.432ns (93.944%))
|
|
Logic Levels: 1 (LUT5=1)
|
|
Clock Path Skew: -0.321ns (DCD - SCD + CPR)
|
|
Destination Clock Delay (DCD): -2.303ns = ( 17.697 - 20.000 )
|
|
Source Clock Delay (SCD): -2.496ns
|
|
Clock Pessimism Removal (CPR): -0.514ns
|
|
Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Discrete Jitter (DJ): 0.122ns
|
|
Phase Error (PE): 0.000ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock sys_clk rise edge) 0.000 0.000 r
|
|
clock source latency -6.275 -6.275
|
|
propagated clock network latency
|
|
3.780 -2.496
|
|
SLICE_X106Y69 FDCE 0.000 -2.496 r pll_clk.u_rst_sys/delay_reg[1]/C
|
|
SLICE_X106Y69 FDCE (Prop_fdce_C_Q) 0.456 -2.040 r pll_clk.u_rst_sys/delay_reg[1]/Q
|
|
net (fo=125, routed) 1.036 -1.003 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/valid_sr_reg[6][0]
|
|
SLICE_X112Y66 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/p_s1[23]_i_9/I0
|
|
SLICE_X112Y66 LUT5 (Prop_lut5_I0_O) 0.152 -0.851 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/p_s1[23]_i_9/O
|
|
net (fo=24670, routed) 8.395 7.544 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/delay_reg[1]
|
|
SLICE_X53Y169 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_B_reg[214][8]/CLR
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock sys_clk rise edge) 20.000 20.000 r
|
|
clock source latency -5.674 14.326
|
|
propagated clock network latency
|
|
3.372 17.697
|
|
clock pessimism -0.514 17.184
|
|
clock uncertainty -0.071 17.113
|
|
SLICE_X53Y169 FDCE (Recov_fdce_C_CLR) -0.629 16.484 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_B_reg[214][8]
|
|
-------------------------------------------------------------------
|
|
required time 16.484
|
|
arrival time -7.544
|
|
-------------------------------------------------------------------
|
|
slack 8.940
|
|
|
|
Slack (MET) : 8.942ns (required time - arrival time)
|
|
Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_cnt_reg[3]/C
|
|
(rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_B_reg[222][8]/CLR
|
|
(recovery check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Path Group: **async_default**
|
|
Path Type: Recovery (Max at Slow Process Corner)
|
|
Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns)
|
|
Data Path Delay: 10.115ns (logic 0.668ns (6.604%) route 9.447ns (93.396%))
|
|
Logic Levels: 1 (LUT5=1)
|
|
Clock Path Skew: -0.329ns (DCD - SCD + CPR)
|
|
Destination Clock Delay (DCD): -2.303ns = ( 17.697 - 20.000 )
|
|
Source Clock Delay (SCD): -2.488ns
|
|
Clock Pessimism Removal (CPR): -0.514ns
|
|
Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Discrete Jitter (DJ): 0.122ns
|
|
Phase Error (PE): 0.000ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock sys_clk rise edge) 0.000 0.000 r
|
|
clock source latency -6.275 -6.275
|
|
propagated clock network latency
|
|
3.788 -2.488
|
|
SLICE_X112Y65 FDCE 0.000 -2.488 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_cnt_reg[3]/C
|
|
SLICE_X112Y65 FDCE (Prop_fdce_C_Q) 0.518 -1.970 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_cnt_reg[3]/Q
|
|
net (fo=5, routed) 1.052 -0.917 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/srst_cnt_reg[3]
|
|
SLICE_X112Y66 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/p_s1[23]_i_9/I4
|
|
SLICE_X112Y66 LUT5 (Prop_lut5_I4_O) 0.150 -0.767 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/p_s1[23]_i_9/O
|
|
net (fo=24670, routed) 8.395 7.628 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/delay_reg[1]
|
|
SLICE_X52Y169 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_B_reg[222][8]/CLR
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock sys_clk rise edge) 20.000 20.000 r
|
|
clock source latency -5.674 14.326
|
|
propagated clock network latency
|
|
3.372 17.697
|
|
clock pessimism -0.514 17.184
|
|
clock uncertainty -0.071 17.113
|
|
SLICE_X52Y169 FDCE (Recov_fdce_C_CLR) -0.543 16.570 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_B_reg[222][8]
|
|
-------------------------------------------------------------------
|
|
required time 16.570
|
|
arrival time -7.628
|
|
-------------------------------------------------------------------
|
|
slack 8.942
|
|
|
|
Slack (MET) : 8.944ns (required time - arrival time)
|
|
Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_cnt_reg[3]/C
|
|
(rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/load_cnt_reg[4]_rep__1/CLR
|
|
(recovery check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Path Group: **async_default**
|
|
Path Type: Recovery (Max at Slow Process Corner)
|
|
Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns)
|
|
Data Path Delay: 10.392ns (logic 0.668ns (6.428%) route 9.724ns (93.572%))
|
|
Logic Levels: 1 (LUT5=1)
|
|
Clock Path Skew: 0.036ns (DCD - SCD + CPR)
|
|
Destination Clock Delay (DCD): -1.938ns = ( 18.062 - 20.000 )
|
|
Source Clock Delay (SCD): -2.488ns
|
|
Clock Pessimism Removal (CPR): -0.514ns
|
|
Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Discrete Jitter (DJ): 0.122ns
|
|
Phase Error (PE): 0.000ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock sys_clk rise edge) 0.000 0.000 r
|
|
clock source latency -6.275 -6.275
|
|
propagated clock network latency
|
|
3.788 -2.488
|
|
SLICE_X112Y65 FDCE 0.000 -2.488 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_cnt_reg[3]/C
|
|
SLICE_X112Y65 FDCE (Prop_fdce_C_Q) 0.518 -1.970 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_cnt_reg[3]/Q
|
|
net (fo=5, routed) 1.052 -0.917 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/srst_cnt_reg[3]
|
|
SLICE_X112Y66 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/p_s1[23]_i_9/I4
|
|
SLICE_X112Y66 LUT5 (Prop_lut5_I4_O) 0.150 -0.767 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/p_s1[23]_i_9/O
|
|
net (fo=24670, routed) 8.672 7.904 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/valid_sr_reg[6]
|
|
SLICE_X156Y206 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/load_cnt_reg[4]_rep__1/CLR
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock sys_clk rise edge) 20.000 20.000 r
|
|
clock source latency -5.674 14.326
|
|
propagated clock network latency
|
|
3.736 18.062
|
|
clock pessimism -0.514 17.548
|
|
clock uncertainty -0.071 17.478
|
|
SLICE_X156Y206 FDCE (Recov_fdce_C_CLR) -0.629 16.849 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/load_cnt_reg[4]_rep__1
|
|
-------------------------------------------------------------------
|
|
required time 16.849
|
|
arrival time -7.904
|
|
-------------------------------------------------------------------
|
|
slack 8.944
|
|
|
|
Slack (MET) : 8.944ns (required time - arrival time)
|
|
Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_cnt_reg[3]/C
|
|
(rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/load_cnt_reg[5]_rep__1/CLR
|
|
(recovery check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Path Group: **async_default**
|
|
Path Type: Recovery (Max at Slow Process Corner)
|
|
Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns)
|
|
Data Path Delay: 10.392ns (logic 0.668ns (6.428%) route 9.724ns (93.572%))
|
|
Logic Levels: 1 (LUT5=1)
|
|
Clock Path Skew: 0.036ns (DCD - SCD + CPR)
|
|
Destination Clock Delay (DCD): -1.938ns = ( 18.062 - 20.000 )
|
|
Source Clock Delay (SCD): -2.488ns
|
|
Clock Pessimism Removal (CPR): -0.514ns
|
|
Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Discrete Jitter (DJ): 0.122ns
|
|
Phase Error (PE): 0.000ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock sys_clk rise edge) 0.000 0.000 r
|
|
clock source latency -6.275 -6.275
|
|
propagated clock network latency
|
|
3.788 -2.488
|
|
SLICE_X112Y65 FDCE 0.000 -2.488 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_cnt_reg[3]/C
|
|
SLICE_X112Y65 FDCE (Prop_fdce_C_Q) 0.518 -1.970 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_cnt_reg[3]/Q
|
|
net (fo=5, routed) 1.052 -0.917 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/srst_cnt_reg[3]
|
|
SLICE_X112Y66 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/p_s1[23]_i_9/I4
|
|
SLICE_X112Y66 LUT5 (Prop_lut5_I4_O) 0.150 -0.767 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/p_s1[23]_i_9/O
|
|
net (fo=24670, routed) 8.672 7.904 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/valid_sr_reg[6]
|
|
SLICE_X156Y206 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/load_cnt_reg[5]_rep__1/CLR
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock sys_clk rise edge) 20.000 20.000 r
|
|
clock source latency -5.674 14.326
|
|
propagated clock network latency
|
|
3.736 18.062
|
|
clock pessimism -0.514 17.548
|
|
clock uncertainty -0.071 17.478
|
|
SLICE_X156Y206 FDCE (Recov_fdce_C_CLR) -0.629 16.849 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/load_cnt_reg[5]_rep__1
|
|
-------------------------------------------------------------------
|
|
required time 16.849
|
|
arrival time -7.904
|
|
-------------------------------------------------------------------
|
|
slack 8.944
|
|
|
|
Slack (MET) : 8.944ns (required time - arrival time)
|
|
Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_cnt_reg[3]/C
|
|
(rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/load_cnt_reg[5]_rep__2/CLR
|
|
(recovery check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Path Group: **async_default**
|
|
Path Type: Recovery (Max at Slow Process Corner)
|
|
Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns)
|
|
Data Path Delay: 10.392ns (logic 0.668ns (6.428%) route 9.724ns (93.572%))
|
|
Logic Levels: 1 (LUT5=1)
|
|
Clock Path Skew: 0.036ns (DCD - SCD + CPR)
|
|
Destination Clock Delay (DCD): -1.938ns = ( 18.062 - 20.000 )
|
|
Source Clock Delay (SCD): -2.488ns
|
|
Clock Pessimism Removal (CPR): -0.514ns
|
|
Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Discrete Jitter (DJ): 0.122ns
|
|
Phase Error (PE): 0.000ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock sys_clk rise edge) 0.000 0.000 r
|
|
clock source latency -6.275 -6.275
|
|
propagated clock network latency
|
|
3.788 -2.488
|
|
SLICE_X112Y65 FDCE 0.000 -2.488 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_cnt_reg[3]/C
|
|
SLICE_X112Y65 FDCE (Prop_fdce_C_Q) 0.518 -1.970 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_cnt_reg[3]/Q
|
|
net (fo=5, routed) 1.052 -0.917 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/srst_cnt_reg[3]
|
|
SLICE_X112Y66 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/p_s1[23]_i_9/I4
|
|
SLICE_X112Y66 LUT5 (Prop_lut5_I4_O) 0.150 -0.767 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/p_s1[23]_i_9/O
|
|
net (fo=24670, routed) 8.672 7.904 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/valid_sr_reg[6]
|
|
SLICE_X156Y206 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/load_cnt_reg[5]_rep__2/CLR
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock sys_clk rise edge) 20.000 20.000 r
|
|
clock source latency -5.674 14.326
|
|
propagated clock network latency
|
|
3.736 18.062
|
|
clock pessimism -0.514 17.548
|
|
clock uncertainty -0.071 17.478
|
|
SLICE_X156Y206 FDCE (Recov_fdce_C_CLR) -0.629 16.849 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/load_cnt_reg[5]_rep__2
|
|
-------------------------------------------------------------------
|
|
required time 16.849
|
|
arrival time -7.904
|
|
-------------------------------------------------------------------
|
|
slack 8.944
|
|
|
|
Slack (MET) : 8.956ns (required time - arrival time)
|
|
Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_cnt_reg[1]/C
|
|
(rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/cr_reg[45][1]/CLR
|
|
(recovery check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Path Group: **async_default**
|
|
Path Type: Recovery (Max at Slow Process Corner)
|
|
Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns)
|
|
Data Path Delay: 10.185ns (logic 0.670ns (6.578%) route 9.515ns (93.422%))
|
|
Logic Levels: 1 (LUT5=1)
|
|
Clock Path Skew: -0.159ns (DCD - SCD + CPR)
|
|
Destination Clock Delay (DCD): -2.133ns = ( 17.867 - 20.000 )
|
|
Source Clock Delay (SCD): -2.488ns
|
|
Clock Pessimism Removal (CPR): -0.514ns
|
|
Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Discrete Jitter (DJ): 0.122ns
|
|
Phase Error (PE): 0.000ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock sys_clk rise edge) 0.000 0.000 r
|
|
clock source latency -6.275 -6.275
|
|
propagated clock network latency
|
|
3.788 -2.488
|
|
SLICE_X112Y65 FDCE 0.000 -2.488 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_cnt_reg[1]/C
|
|
SLICE_X112Y65 FDCE (Prop_fdce_C_Q) 0.518 -1.970 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_cnt_reg[1]/Q
|
|
net (fo=7, routed) 0.990 -0.979 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/srst_cnt_reg[1]
|
|
SLICE_X112Y66 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/p_s1[23]_i_9/I1
|
|
SLICE_X112Y66 LUT5 (Prop_lut5_I1_O) 0.152 -0.827 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/p_s1[23]_i_9/O
|
|
net (fo=24670, routed) 8.525 7.698 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/valid_sr_reg[6]
|
|
SLICE_X159Y190 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/cr_reg[45][1]/CLR
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock sys_clk rise edge) 20.000 20.000 r
|
|
clock source latency -5.674 14.326
|
|
propagated clock network latency
|
|
3.542 17.867
|
|
clock pessimism -0.514 17.354
|
|
clock uncertainty -0.071 17.283
|
|
SLICE_X159Y190 FDCE (Recov_fdce_C_CLR) -0.629 16.654 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/cr_reg[45][1]
|
|
-------------------------------------------------------------------
|
|
required time 16.654
|
|
arrival time -7.698
|
|
-------------------------------------------------------------------
|
|
slack 8.956
|
|
|
|
Slack (MET) : 8.956ns (required time - arrival time)
|
|
Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_cnt_reg[1]/C
|
|
(rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/cr_reg[45][2]/CLR
|
|
(recovery check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Path Group: **async_default**
|
|
Path Type: Recovery (Max at Slow Process Corner)
|
|
Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns)
|
|
Data Path Delay: 10.185ns (logic 0.670ns (6.578%) route 9.515ns (93.422%))
|
|
Logic Levels: 1 (LUT5=1)
|
|
Clock Path Skew: -0.159ns (DCD - SCD + CPR)
|
|
Destination Clock Delay (DCD): -2.133ns = ( 17.867 - 20.000 )
|
|
Source Clock Delay (SCD): -2.488ns
|
|
Clock Pessimism Removal (CPR): -0.514ns
|
|
Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Discrete Jitter (DJ): 0.122ns
|
|
Phase Error (PE): 0.000ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock sys_clk rise edge) 0.000 0.000 r
|
|
clock source latency -6.275 -6.275
|
|
propagated clock network latency
|
|
3.788 -2.488
|
|
SLICE_X112Y65 FDCE 0.000 -2.488 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_cnt_reg[1]/C
|
|
SLICE_X112Y65 FDCE (Prop_fdce_C_Q) 0.518 -1.970 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_cnt_reg[1]/Q
|
|
net (fo=7, routed) 0.990 -0.979 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/srst_cnt_reg[1]
|
|
SLICE_X112Y66 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/p_s1[23]_i_9/I1
|
|
SLICE_X112Y66 LUT5 (Prop_lut5_I1_O) 0.152 -0.827 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/p_s1[23]_i_9/O
|
|
net (fo=24670, routed) 8.525 7.698 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/valid_sr_reg[6]
|
|
SLICE_X159Y190 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/cr_reg[45][2]/CLR
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock sys_clk rise edge) 20.000 20.000 r
|
|
clock source latency -5.674 14.326
|
|
propagated clock network latency
|
|
3.542 17.867
|
|
clock pessimism -0.514 17.354
|
|
clock uncertainty -0.071 17.283
|
|
SLICE_X159Y190 FDCE (Recov_fdce_C_CLR) -0.629 16.654 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/cr_reg[45][2]
|
|
-------------------------------------------------------------------
|
|
required time 16.654
|
|
arrival time -7.698
|
|
-------------------------------------------------------------------
|
|
slack 8.956
|
|
|
|
Slack (MET) : 8.956ns (required time - arrival time)
|
|
Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_cnt_reg[1]/C
|
|
(rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/cr_reg[45][4]/CLR
|
|
(recovery check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Path Group: **async_default**
|
|
Path Type: Recovery (Max at Slow Process Corner)
|
|
Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns)
|
|
Data Path Delay: 10.185ns (logic 0.670ns (6.578%) route 9.515ns (93.422%))
|
|
Logic Levels: 1 (LUT5=1)
|
|
Clock Path Skew: -0.159ns (DCD - SCD + CPR)
|
|
Destination Clock Delay (DCD): -2.133ns = ( 17.867 - 20.000 )
|
|
Source Clock Delay (SCD): -2.488ns
|
|
Clock Pessimism Removal (CPR): -0.514ns
|
|
Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Discrete Jitter (DJ): 0.122ns
|
|
Phase Error (PE): 0.000ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock sys_clk rise edge) 0.000 0.000 r
|
|
clock source latency -6.275 -6.275
|
|
propagated clock network latency
|
|
3.788 -2.488
|
|
SLICE_X112Y65 FDCE 0.000 -2.488 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_cnt_reg[1]/C
|
|
SLICE_X112Y65 FDCE (Prop_fdce_C_Q) 0.518 -1.970 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_cnt_reg[1]/Q
|
|
net (fo=7, routed) 0.990 -0.979 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/srst_cnt_reg[1]
|
|
SLICE_X112Y66 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/p_s1[23]_i_9/I1
|
|
SLICE_X112Y66 LUT5 (Prop_lut5_I1_O) 0.152 -0.827 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/p_s1[23]_i_9/O
|
|
net (fo=24670, routed) 8.525 7.698 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/valid_sr_reg[6]
|
|
SLICE_X159Y190 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/cr_reg[45][4]/CLR
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock sys_clk rise edge) 20.000 20.000 r
|
|
clock source latency -5.674 14.326
|
|
propagated clock network latency
|
|
3.542 17.867
|
|
clock pessimism -0.514 17.354
|
|
clock uncertainty -0.071 17.283
|
|
SLICE_X159Y190 FDCE (Recov_fdce_C_CLR) -0.629 16.654 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/cr_reg[45][4]
|
|
-------------------------------------------------------------------
|
|
required time 16.654
|
|
arrival time -7.698
|
|
-------------------------------------------------------------------
|
|
slack 8.956
|
|
|
|
Slack (MET) : 8.956ns (required time - arrival time)
|
|
Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_cnt_reg[1]/C
|
|
(rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/cr_reg[45][5]/CLR
|
|
(recovery check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Path Group: **async_default**
|
|
Path Type: Recovery (Max at Slow Process Corner)
|
|
Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns)
|
|
Data Path Delay: 10.185ns (logic 0.670ns (6.578%) route 9.515ns (93.422%))
|
|
Logic Levels: 1 (LUT5=1)
|
|
Clock Path Skew: -0.159ns (DCD - SCD + CPR)
|
|
Destination Clock Delay (DCD): -2.133ns = ( 17.867 - 20.000 )
|
|
Source Clock Delay (SCD): -2.488ns
|
|
Clock Pessimism Removal (CPR): -0.514ns
|
|
Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Discrete Jitter (DJ): 0.122ns
|
|
Phase Error (PE): 0.000ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock sys_clk rise edge) 0.000 0.000 r
|
|
clock source latency -6.275 -6.275
|
|
propagated clock network latency
|
|
3.788 -2.488
|
|
SLICE_X112Y65 FDCE 0.000 -2.488 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_cnt_reg[1]/C
|
|
SLICE_X112Y65 FDCE (Prop_fdce_C_Q) 0.518 -1.970 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_cnt_reg[1]/Q
|
|
net (fo=7, routed) 0.990 -0.979 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/srst_cnt_reg[1]
|
|
SLICE_X112Y66 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/p_s1[23]_i_9/I1
|
|
SLICE_X112Y66 LUT5 (Prop_lut5_I1_O) 0.152 -0.827 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/p_s1[23]_i_9/O
|
|
net (fo=24670, routed) 8.525 7.698 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/valid_sr_reg[6]
|
|
SLICE_X159Y190 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/cr_reg[45][5]/CLR
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock sys_clk rise edge) 20.000 20.000 r
|
|
clock source latency -5.674 14.326
|
|
propagated clock network latency
|
|
3.542 17.867
|
|
clock pessimism -0.514 17.354
|
|
clock uncertainty -0.071 17.283
|
|
SLICE_X159Y190 FDCE (Recov_fdce_C_CLR) -0.629 16.654 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/cr_reg[45][5]
|
|
-------------------------------------------------------------------
|
|
required time 16.654
|
|
arrival time -7.698
|
|
-------------------------------------------------------------------
|
|
slack 8.956
|
|
|
|
Slack (MET) : 8.980ns (required time - arrival time)
|
|
Source: pll_clk.u_rst_sys/delay_reg[1]/C
|
|
(rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/cr_reg[45][1]/CLR
|
|
(recovery check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Path Group: **async_default**
|
|
Path Type: Recovery (Max at Slow Process Corner)
|
|
Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns)
|
|
Data Path Delay: 10.170ns (logic 0.608ns (5.979%) route 9.562ns (94.021%))
|
|
Logic Levels: 1 (LUT5=1)
|
|
Clock Path Skew: -0.151ns (DCD - SCD + CPR)
|
|
Destination Clock Delay (DCD): -2.133ns = ( 17.867 - 20.000 )
|
|
Source Clock Delay (SCD): -2.496ns
|
|
Clock Pessimism Removal (CPR): -0.514ns
|
|
Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Discrete Jitter (DJ): 0.122ns
|
|
Phase Error (PE): 0.000ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock sys_clk rise edge) 0.000 0.000 r
|
|
clock source latency -6.275 -6.275
|
|
propagated clock network latency
|
|
3.780 -2.496
|
|
SLICE_X106Y69 FDCE 0.000 -2.496 r pll_clk.u_rst_sys/delay_reg[1]/C
|
|
SLICE_X106Y69 FDCE (Prop_fdce_C_Q) 0.456 -2.040 r pll_clk.u_rst_sys/delay_reg[1]/Q
|
|
net (fo=125, routed) 1.036 -1.003 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/valid_sr_reg[6][0]
|
|
SLICE_X112Y66 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/p_s1[23]_i_9/I0
|
|
SLICE_X112Y66 LUT5 (Prop_lut5_I0_O) 0.152 -0.851 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/p_s1[23]_i_9/O
|
|
net (fo=24670, routed) 8.525 7.674 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/valid_sr_reg[6]
|
|
SLICE_X159Y190 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/cr_reg[45][1]/CLR
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock sys_clk rise edge) 20.000 20.000 r
|
|
clock source latency -5.674 14.326
|
|
propagated clock network latency
|
|
3.542 17.867
|
|
clock pessimism -0.514 17.354
|
|
clock uncertainty -0.071 17.283
|
|
SLICE_X159Y190 FDCE (Recov_fdce_C_CLR) -0.629 16.654 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/cr_reg[45][1]
|
|
-------------------------------------------------------------------
|
|
required time 16.654
|
|
arrival time -7.674
|
|
-------------------------------------------------------------------
|
|
slack 8.980
|
|
|
|
Slack (MET) : 8.980ns (required time - arrival time)
|
|
Source: pll_clk.u_rst_sys/delay_reg[1]/C
|
|
(rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/cr_reg[45][2]/CLR
|
|
(recovery check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Path Group: **async_default**
|
|
Path Type: Recovery (Max at Slow Process Corner)
|
|
Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns)
|
|
Data Path Delay: 10.170ns (logic 0.608ns (5.979%) route 9.562ns (94.021%))
|
|
Logic Levels: 1 (LUT5=1)
|
|
Clock Path Skew: -0.151ns (DCD - SCD + CPR)
|
|
Destination Clock Delay (DCD): -2.133ns = ( 17.867 - 20.000 )
|
|
Source Clock Delay (SCD): -2.496ns
|
|
Clock Pessimism Removal (CPR): -0.514ns
|
|
Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Discrete Jitter (DJ): 0.122ns
|
|
Phase Error (PE): 0.000ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock sys_clk rise edge) 0.000 0.000 r
|
|
clock source latency -6.275 -6.275
|
|
propagated clock network latency
|
|
3.780 -2.496
|
|
SLICE_X106Y69 FDCE 0.000 -2.496 r pll_clk.u_rst_sys/delay_reg[1]/C
|
|
SLICE_X106Y69 FDCE (Prop_fdce_C_Q) 0.456 -2.040 r pll_clk.u_rst_sys/delay_reg[1]/Q
|
|
net (fo=125, routed) 1.036 -1.003 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/valid_sr_reg[6][0]
|
|
SLICE_X112Y66 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/p_s1[23]_i_9/I0
|
|
SLICE_X112Y66 LUT5 (Prop_lut5_I0_O) 0.152 -0.851 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/p_s1[23]_i_9/O
|
|
net (fo=24670, routed) 8.525 7.674 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/valid_sr_reg[6]
|
|
SLICE_X159Y190 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/cr_reg[45][2]/CLR
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock sys_clk rise edge) 20.000 20.000 r
|
|
clock source latency -5.674 14.326
|
|
propagated clock network latency
|
|
3.542 17.867
|
|
clock pessimism -0.514 17.354
|
|
clock uncertainty -0.071 17.283
|
|
SLICE_X159Y190 FDCE (Recov_fdce_C_CLR) -0.629 16.654 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/cr_reg[45][2]
|
|
-------------------------------------------------------------------
|
|
required time 16.654
|
|
arrival time -7.674
|
|
-------------------------------------------------------------------
|
|
slack 8.980
|
|
|
|
Slack (MET) : 8.980ns (required time - arrival time)
|
|
Source: pll_clk.u_rst_sys/delay_reg[1]/C
|
|
(rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/cr_reg[45][4]/CLR
|
|
(recovery check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Path Group: **async_default**
|
|
Path Type: Recovery (Max at Slow Process Corner)
|
|
Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns)
|
|
Data Path Delay: 10.170ns (logic 0.608ns (5.979%) route 9.562ns (94.021%))
|
|
Logic Levels: 1 (LUT5=1)
|
|
Clock Path Skew: -0.151ns (DCD - SCD + CPR)
|
|
Destination Clock Delay (DCD): -2.133ns = ( 17.867 - 20.000 )
|
|
Source Clock Delay (SCD): -2.496ns
|
|
Clock Pessimism Removal (CPR): -0.514ns
|
|
Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Discrete Jitter (DJ): 0.122ns
|
|
Phase Error (PE): 0.000ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock sys_clk rise edge) 0.000 0.000 r
|
|
clock source latency -6.275 -6.275
|
|
propagated clock network latency
|
|
3.780 -2.496
|
|
SLICE_X106Y69 FDCE 0.000 -2.496 r pll_clk.u_rst_sys/delay_reg[1]/C
|
|
SLICE_X106Y69 FDCE (Prop_fdce_C_Q) 0.456 -2.040 r pll_clk.u_rst_sys/delay_reg[1]/Q
|
|
net (fo=125, routed) 1.036 -1.003 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/valid_sr_reg[6][0]
|
|
SLICE_X112Y66 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/p_s1[23]_i_9/I0
|
|
SLICE_X112Y66 LUT5 (Prop_lut5_I0_O) 0.152 -0.851 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/p_s1[23]_i_9/O
|
|
net (fo=24670, routed) 8.525 7.674 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/valid_sr_reg[6]
|
|
SLICE_X159Y190 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/cr_reg[45][4]/CLR
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock sys_clk rise edge) 20.000 20.000 r
|
|
clock source latency -5.674 14.326
|
|
propagated clock network latency
|
|
3.542 17.867
|
|
clock pessimism -0.514 17.354
|
|
clock uncertainty -0.071 17.283
|
|
SLICE_X159Y190 FDCE (Recov_fdce_C_CLR) -0.629 16.654 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/cr_reg[45][4]
|
|
-------------------------------------------------------------------
|
|
required time 16.654
|
|
arrival time -7.674
|
|
-------------------------------------------------------------------
|
|
slack 8.980
|
|
|
|
Slack (MET) : 8.980ns (required time - arrival time)
|
|
Source: pll_clk.u_rst_sys/delay_reg[1]/C
|
|
(rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/cr_reg[45][5]/CLR
|
|
(recovery check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Path Group: **async_default**
|
|
Path Type: Recovery (Max at Slow Process Corner)
|
|
Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns)
|
|
Data Path Delay: 10.170ns (logic 0.608ns (5.979%) route 9.562ns (94.021%))
|
|
Logic Levels: 1 (LUT5=1)
|
|
Clock Path Skew: -0.151ns (DCD - SCD + CPR)
|
|
Destination Clock Delay (DCD): -2.133ns = ( 17.867 - 20.000 )
|
|
Source Clock Delay (SCD): -2.496ns
|
|
Clock Pessimism Removal (CPR): -0.514ns
|
|
Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Discrete Jitter (DJ): 0.122ns
|
|
Phase Error (PE): 0.000ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock sys_clk rise edge) 0.000 0.000 r
|
|
clock source latency -6.275 -6.275
|
|
propagated clock network latency
|
|
3.780 -2.496
|
|
SLICE_X106Y69 FDCE 0.000 -2.496 r pll_clk.u_rst_sys/delay_reg[1]/C
|
|
SLICE_X106Y69 FDCE (Prop_fdce_C_Q) 0.456 -2.040 r pll_clk.u_rst_sys/delay_reg[1]/Q
|
|
net (fo=125, routed) 1.036 -1.003 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/valid_sr_reg[6][0]
|
|
SLICE_X112Y66 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/p_s1[23]_i_9/I0
|
|
SLICE_X112Y66 LUT5 (Prop_lut5_I0_O) 0.152 -0.851 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/p_s1[23]_i_9/O
|
|
net (fo=24670, routed) 8.525 7.674 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/valid_sr_reg[6]
|
|
SLICE_X159Y190 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/cr_reg[45][5]/CLR
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock sys_clk rise edge) 20.000 20.000 r
|
|
clock source latency -5.674 14.326
|
|
propagated clock network latency
|
|
3.542 17.867
|
|
clock pessimism -0.514 17.354
|
|
clock uncertainty -0.071 17.283
|
|
SLICE_X159Y190 FDCE (Recov_fdce_C_CLR) -0.629 16.654 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/cr_reg[45][5]
|
|
-------------------------------------------------------------------
|
|
required time 16.654
|
|
arrival time -7.674
|
|
-------------------------------------------------------------------
|
|
slack 8.980
|
|
|
|
Slack (MET) : 8.982ns (required time - arrival time)
|
|
Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_cnt_reg[3]/C
|
|
(rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/cr_reg[237][4]/CLR
|
|
(recovery check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Path Group: **async_default**
|
|
Path Type: Recovery (Max at Slow Process Corner)
|
|
Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns)
|
|
Data Path Delay: 10.245ns (logic 0.668ns (6.520%) route 9.577ns (93.480%))
|
|
Logic Levels: 1 (LUT5=1)
|
|
Clock Path Skew: -0.159ns (DCD - SCD + CPR)
|
|
Destination Clock Delay (DCD): -2.133ns = ( 17.867 - 20.000 )
|
|
Source Clock Delay (SCD): -2.488ns
|
|
Clock Pessimism Removal (CPR): -0.514ns
|
|
Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Discrete Jitter (DJ): 0.122ns
|
|
Phase Error (PE): 0.000ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock sys_clk rise edge) 0.000 0.000 r
|
|
clock source latency -6.275 -6.275
|
|
propagated clock network latency
|
|
3.788 -2.488
|
|
SLICE_X112Y65 FDCE 0.000 -2.488 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_cnt_reg[3]/C
|
|
SLICE_X112Y65 FDCE (Prop_fdce_C_Q) 0.518 -1.970 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_cnt_reg[3]/Q
|
|
net (fo=5, routed) 1.052 -0.917 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/srst_cnt_reg[3]
|
|
SLICE_X112Y66 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/p_s1[23]_i_9/I4
|
|
SLICE_X112Y66 LUT5 (Prop_lut5_I4_O) 0.150 -0.767 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/p_s1[23]_i_9/O
|
|
net (fo=24670, routed) 8.525 7.758 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/valid_sr_reg[6]
|
|
SLICE_X158Y190 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/cr_reg[237][4]/CLR
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock sys_clk rise edge) 20.000 20.000 r
|
|
clock source latency -5.674 14.326
|
|
propagated clock network latency
|
|
3.542 17.867
|
|
clock pessimism -0.514 17.354
|
|
clock uncertainty -0.071 17.283
|
|
SLICE_X158Y190 FDCE (Recov_fdce_C_CLR) -0.543 16.740 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/cr_reg[237][4]
|
|
-------------------------------------------------------------------
|
|
required time 16.740
|
|
arrival time -7.758
|
|
-------------------------------------------------------------------
|
|
slack 8.982
|
|
|
|
|
|
|
|
|