FallenSigh
c5072d7170
Wrap mlkem_top in an AXI4 burst slave (mlkem_axi_slave) mapped to the freed FFT slot 6 at 0x1f400000 (virtual 0xbf400000). The core runs on sys_clk/2 (25 MHz); the wrapper handles the clock-domain crossing: start toggle->pulse, wait-stated byte-preload handshake, busy/done sync, and direct readback taps (ek/dk/ct/ss). CPU drives it via a register map (CTRL/STATUS/CONFIG, d/z/msg, preload + readback windows). Wire into soc_top on the existing axiOut_6 nets (no crossbar change), add mlkem_intr on intrpt[3]. Add sdk mlkem_test example running a KeyGen->Encaps->Decaps self-consistency round trip.
46 lines
1.8 KiB
Verilog
46 lines
1.8 KiB
Verilog
// basecase_mul.v - NTT-domain degree-1 polynomial multiplication
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//
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// Computes pointwise product of two degree-1 NTT-domain polynomials:
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// c0 = (a0*b0 + a1*b1*zeta) mod Q
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// c1 = (a0*b1 + a1*b0) mod Q
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//
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// Uses three barrett_mul instances for modular multiplications
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// and pure combinational modular addition for the final sums.
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//
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// All inputs/outputs are 12-bit values in [0, Q-1] where Q = 3329.
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module basecase_mul (
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input [11:0] a0, a1, // first polynomial: degree-0 and degree-1 coeffs
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input [11:0] b0, b1, // second polynomial: degree-0 and degree-1 coeffs
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input [11:0] zeta, // precomputed twiddle factor (zeta^2 * 17 mod Q)
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output [11:0] c0, c1 // result polynomial coefficients
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);
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localparam Q = 3329;
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// Barrett modular multiplication outputs
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wire [11:0] t1; // a0 * b0 mod Q
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wire [11:0] t2; // a1 * b1 mod Q
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wire [11:0] t3; // a1 * b0 mod Q
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wire [11:0] t4; // a0 * b1 mod Q
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wire [11:0] t2_zeta; // (a1 * b1) * zeta mod Q
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// Four Barrett multiplications for the scalar products
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barrett_mul u_mul1 (.a(a0), .b(b0), .product(t1));
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barrett_mul u_mul2 (.a(a1), .b(b1), .product(t2));
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barrett_mul u_mul3 (.a(a1), .b(b0), .product(t3));
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barrett_mul u_mul4 (.a(a0), .b(b1), .product(t4));
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// Multiply t2 by zeta for the zeta term in c0
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barrett_mul u_mul_zeta (.a(t2), .b(zeta), .product(t2_zeta));
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// Combinational modular addition: each sum is in [0, 2Q-1)
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// Subtract Q once if >= Q
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wire [12:0] sum_c0 = {1'b0, t1} + {1'b0, t2_zeta};
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wire [12:0] sum_c1 = {1'b0, t3} + {1'b0, t4};
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assign c0 = (sum_c0 >= Q) ? sum_c0[11:0] - Q[11:0] : sum_c0[11:0];
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assign c1 = (sum_c1 >= Q) ? sum_c1[11:0] - Q[11:0] : sum_c1[11:0];
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endmodule
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