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FallenSigh 4538ec496f perf(mlkem): register butterfly inputs to cut the 100 MHz NTT critical path ...

At mlkem_clk=100 MHz the worst path (WNS -2.14 ns) was coeff_bram read ->
butterfly diff (b-a) -> barrett first multiply stage, all in one cycle. The
butterfly took its operands combinationally from the BRAM read (unlike
poly_mul's basecase, which already registers them). Add an input register
stage (a/b/zeta/mode/valid) in butterfly_unit_pipe so the BRAM read and the
first multiply land in separate cycles; feed the a/b/mode alignment delay
lines from the registered inputs. Butterfly latency 8->9; ntt_core writeback
address delay lines deepened 9->10 to match.

Verified byte-exact vs NIST KAT: NTT standalone TB 19/19 (fwd+inv), Encaps
9/9, Decaps 9/9, hello_world e2e — all PASS.

Co-Authored-By: Claude Opus 4.8 (1M context) <noreply@anthropic.com>

2026-07-11 07:05:12 +08:00

..

barrett_mul_pipe.v

remove dsp usage

2026-07-08 03:18:10 +08:00

barrett_mul.v

remove dsp usage

2026-07-08 03:18:10 +08:00

butterfly_unit_pipe.v

perf(mlkem): register butterfly inputs to cut the 100 MHz NTT critical path

2026-07-11 07:05:12 +08:00

butterfly_unit.v

feat: add ML-KEM accelerator with AXI slave wrapper

2026-06-30 01:39:35 +08:00

coeff_bram_4way.v

perf(mlkem): move NTT coeff storage to 4-way banked BRAM

2026-07-11 05:16:58 +08:00

ntt_core.v

perf(mlkem): register butterfly inputs to cut the 100 MHz NTT critical path

2026-07-11 07:05:12 +08:00

ntt_sync.v

feat: add ML-KEM accelerator with AXI slave wrapper

2026-06-30 01:39:35 +08:00

zeta_rom.v

feat: add ML-KEM accelerator with AXI slave wrapper

2026-06-30 01:39:35 +08:00