1933 lines
132 KiB
Plaintext
1933 lines
132 KiB
Plaintext
Copyright 1986-2019 Xilinx, Inc. All Rights Reserved.
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| Tool Version : Vivado v.2019.2 (lin64) Build 2708876 Wed Nov 6 21:39:14 MST 2019
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| Date : Sat Jul 11 09:20:56 2026
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| Host : fedora running 64-bit unknown
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| Command : report_timing -from [get_clocks sys_clk] -to [get_clocks mlkem_clk] -delay_type max -max_paths 50 -nworst 10 -path_type full -input_pins -file /home/fallensigh/Dev/ciciec2026_loongson_regional/fpga/vivado_reports_nodsp/cdc_sys_to_mlkem.rpt
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| Design : soc_top
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| Device : 7a200t-fbg676
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| Speed File : -1 PRODUCTION 1.23 2018-06-13
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Timing Report
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Slack: inf
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Source: pll_clk.u_rst_sys/delay_reg[1]/C
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(rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
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Destination: pll_clk.u_rst_mlkem/delay_reg[0]/CLR
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(recovery check against rising-edge clock mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns})
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Path Group: (none)
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Path Type: Recovery (Max at Slow Process Corner)
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Data Path Delay: 10.980ns (logic 0.668ns (6.084%) route 10.312ns (93.916%))
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Logic Levels: 1 (LUT1=1)
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Clock Path Skew: 0.301ns (DCD - SCD + CPR)
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Destination Clock Delay (DCD): -2.273ns
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Source Clock Delay (SCD): -2.574ns
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Clock Pessimism Removal (CPR): 0.000ns
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Clock Uncertainty: 0.222ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
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Total System Jitter (TSJ): 0.071ns
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Discrete Jitter (DJ): 0.192ns
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Phase Error (PE): 0.120ns
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Timing Exception: Asynchronous Clock Groups
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Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
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------------------------------------------------------------------- -------------------
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(clock sys_clk rise edge) 0.000 0.000 r
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clock source latency -6.275 -6.275
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propagated clock network latency
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3.702 -2.574
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SLICE_X22Y139 FDCE 0.000 -2.574 r pll_clk.u_rst_sys/delay_reg[1]/C
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SLICE_X22Y139 FDCE (Prop_fdce_C_Q) 0.518 -2.056 r pll_clk.u_rst_sys/delay_reg[1]/Q
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net (fo=117, routed) 3.113 1.057 pll_clk.u_rst_sys/Q[0]
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SLICE_X48Y97 r pll_clk.u_rst_sys/bf2_do_en_i_1/I0
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SLICE_X48Y97 LUT1 (Prop_lut1_I0_O) 0.150 1.207 f pll_clk.u_rst_sys/bf2_do_en_i_1/O
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net (fo=4121, routed) 7.199 8.406 pll_clk.u_rst_mlkem/p_0_in
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SLICE_X96Y101 FDCE f pll_clk.u_rst_mlkem/delay_reg[0]/CLR
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------------------------------------------------------------------- -------------------
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(clock mlkem_clk rise edge)
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0.000 0.000 r
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clock source latency -5.674 -5.674
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propagated clock network latency
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3.402 -2.273
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Slack: inf
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Source: pll_clk.u_rst_sys/delay_reg[1]/C
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(rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
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Destination: pll_clk.u_rst_mlkem/delay_reg[1]/CLR
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(recovery check against rising-edge clock mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns})
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Path Group: (none)
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Path Type: Recovery (Max at Slow Process Corner)
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Data Path Delay: 10.561ns (logic 0.668ns (6.325%) route 9.893ns (93.675%))
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Logic Levels: 1 (LUT1=1)
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Clock Path Skew: 0.297ns (DCD - SCD + CPR)
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Destination Clock Delay (DCD): -2.277ns
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Source Clock Delay (SCD): -2.574ns
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Clock Pessimism Removal (CPR): 0.000ns
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Clock Uncertainty: 0.222ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
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Total System Jitter (TSJ): 0.071ns
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Discrete Jitter (DJ): 0.192ns
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Phase Error (PE): 0.120ns
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Timing Exception: Asynchronous Clock Groups
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Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
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------------------------------------------------------------------- -------------------
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(clock sys_clk rise edge) 0.000 0.000 r
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clock source latency -6.275 -6.275
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propagated clock network latency
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3.702 -2.574
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SLICE_X22Y139 FDCE 0.000 -2.574 r pll_clk.u_rst_sys/delay_reg[1]/C
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SLICE_X22Y139 FDCE (Prop_fdce_C_Q) 0.518 -2.056 r pll_clk.u_rst_sys/delay_reg[1]/Q
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net (fo=117, routed) 3.113 1.057 pll_clk.u_rst_sys/Q[0]
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SLICE_X48Y97 r pll_clk.u_rst_sys/bf2_do_en_i_1/I0
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SLICE_X48Y97 LUT1 (Prop_lut1_I0_O) 0.150 1.207 f pll_clk.u_rst_sys/bf2_do_en_i_1/O
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net (fo=4121, routed) 6.780 7.987 pll_clk.u_rst_mlkem/p_0_in
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SLICE_X92Y102 FDCE f pll_clk.u_rst_mlkem/delay_reg[1]/CLR
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------------------------------------------------------------------- -------------------
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(clock mlkem_clk rise edge)
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0.000 0.000 r
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clock source latency -5.674 -5.674
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propagated clock network latency
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3.398 -2.277
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Slack: inf
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Source: pll_clk.u_rst_sys/delay_reg[1]/C
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(rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
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Destination: pll_clk.u_rst_mlkem/delay_reg[0]/CLR
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(recovery check against rising-edge clock mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns})
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Path Group: (none)
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Path Type: Recovery (Max at Fast Process Corner)
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Data Path Delay: 5.593ns (logic 0.261ns (4.667%) route 5.332ns (95.333%))
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Logic Levels: 1 (LUT1=1)
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Clock Path Skew: -0.267ns (DCD - SCD + CPR)
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Destination Clock Delay (DCD): -0.679ns
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Source Clock Delay (SCD): -0.412ns
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Clock Pessimism Removal (CPR): 0.000ns
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Clock Uncertainty: 0.222ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
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Total System Jitter (TSJ): 0.071ns
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Discrete Jitter (DJ): 0.192ns
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Phase Error (PE): 0.120ns
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Timing Exception: Asynchronous Clock Groups
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Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
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------------------------------------------------------------------- -------------------
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(clock sys_clk rise edge) 0.000 0.000 r
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clock source latency -1.947 -1.947
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propagated clock network latency
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1.535 -0.412
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SLICE_X22Y139 FDCE 0.000 -0.412 r pll_clk.u_rst_sys/delay_reg[1]/C
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SLICE_X22Y139 FDCE (Prop_fdce_C_Q) 0.204 -0.208 r pll_clk.u_rst_sys/delay_reg[1]/Q
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net (fo=117, routed) 1.683 1.475 pll_clk.u_rst_sys/Q[0]
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SLICE_X48Y97 r pll_clk.u_rst_sys/bf2_do_en_i_1/I0
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SLICE_X48Y97 LUT1 (Prop_lut1_I0_O) 0.057 1.532 f pll_clk.u_rst_sys/bf2_do_en_i_1/O
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net (fo=4121, routed) 3.649 5.181 pll_clk.u_rst_mlkem/p_0_in
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SLICE_X96Y101 FDCE f pll_clk.u_rst_mlkem/delay_reg[0]/CLR
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------------------------------------------------------------------- -------------------
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(clock mlkem_clk rise edge)
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0.000 0.000 r
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clock source latency -1.848 -1.848
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propagated clock network latency
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1.169 -0.679
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Slack: inf
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Source: pll_clk.u_rst_sys/delay_reg[1]/C
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(rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
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Destination: pll_clk.u_rst_mlkem/delay_reg[1]/CLR
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(recovery check against rising-edge clock mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns})
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Path Group: (none)
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Path Type: Recovery (Max at Fast Process Corner)
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Data Path Delay: 5.410ns (logic 0.261ns (4.824%) route 5.149ns (95.176%))
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Logic Levels: 1 (LUT1=1)
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Clock Path Skew: -0.268ns (DCD - SCD + CPR)
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Destination Clock Delay (DCD): -0.680ns
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Source Clock Delay (SCD): -0.412ns
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Clock Pessimism Removal (CPR): 0.000ns
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Clock Uncertainty: 0.222ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
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Total System Jitter (TSJ): 0.071ns
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Discrete Jitter (DJ): 0.192ns
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Phase Error (PE): 0.120ns
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Timing Exception: Asynchronous Clock Groups
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Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
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------------------------------------------------------------------- -------------------
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(clock sys_clk rise edge) 0.000 0.000 r
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clock source latency -1.947 -1.947
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propagated clock network latency
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1.535 -0.412
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SLICE_X22Y139 FDCE 0.000 -0.412 r pll_clk.u_rst_sys/delay_reg[1]/C
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SLICE_X22Y139 FDCE (Prop_fdce_C_Q) 0.204 -0.208 r pll_clk.u_rst_sys/delay_reg[1]/Q
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net (fo=117, routed) 1.683 1.475 pll_clk.u_rst_sys/Q[0]
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SLICE_X48Y97 r pll_clk.u_rst_sys/bf2_do_en_i_1/I0
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SLICE_X48Y97 LUT1 (Prop_lut1_I0_O) 0.057 1.532 f pll_clk.u_rst_sys/bf2_do_en_i_1/O
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net (fo=4121, routed) 3.466 4.998 pll_clk.u_rst_mlkem/p_0_in
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SLICE_X92Y102 FDCE f pll_clk.u_rst_mlkem/delay_reg[1]/CLR
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------------------------------------------------------------------- -------------------
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(clock mlkem_clk rise edge)
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0.000 0.000 r
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clock source latency -1.848 -1.848
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propagated clock network latency
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1.168 -0.680
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Slack: inf
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Source: pll_clk.u_rst_sys/delay_reg[1]/C
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(rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
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Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/buffers_0_reg/CLR
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(recovery check against rising-edge clock mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns})
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Path Group: (none)
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Path Type: Recovery (Max at Slow Process Corner)
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Data Path Delay: 6.643ns (logic 0.668ns (10.055%) route 5.975ns (89.945%))
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Logic Levels: 1 (LUT1=1)
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Clock Path Skew: 0.294ns (DCD - SCD + CPR)
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Destination Clock Delay (DCD): -2.280ns
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Source Clock Delay (SCD): -2.574ns
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Clock Pessimism Removal (CPR): 0.000ns
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Clock Uncertainty: 0.222ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
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Total System Jitter (TSJ): 0.071ns
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Discrete Jitter (DJ): 0.192ns
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Phase Error (PE): 0.120ns
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Timing Exception: Asynchronous Clock Groups
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Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
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------------------------------------------------------------------- -------------------
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(clock sys_clk rise edge) 0.000 0.000 r
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clock source latency -6.275 -6.275
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propagated clock network latency
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3.702 -2.574
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SLICE_X22Y139 FDCE 0.000 -2.574 r pll_clk.u_rst_sys/delay_reg[1]/C
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SLICE_X22Y139 FDCE (Prop_fdce_C_Q) 0.518 -2.056 r pll_clk.u_rst_sys/delay_reg[1]/Q
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net (fo=117, routed) 3.113 1.057 pll_clk.u_rst_sys/Q[0]
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SLICE_X48Y97 r pll_clk.u_rst_sys/bf2_do_en_i_1/I0
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SLICE_X48Y97 LUT1 (Prop_lut1_I0_O) 0.150 1.207 f pll_clk.u_rst_sys/bf2_do_en_i_1/O
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net (fo=4121, routed) 2.863 4.070 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/p_0_in
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SLICE_X65Y102 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/buffers_0_reg/CLR
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------------------------------------------------------------------- -------------------
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(clock mlkem_clk rise edge)
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0.000 0.000 r
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clock source latency -5.674 -5.674
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propagated clock network latency
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3.395 -2.280
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Slack: inf
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Source: pll_clk.u_rst_sys/delay_reg[1]/C
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(rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
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Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/buffers_1_reg/CLR
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(recovery check against rising-edge clock mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns})
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Path Group: (none)
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Path Type: Recovery (Max at Slow Process Corner)
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Data Path Delay: 6.643ns (logic 0.668ns (10.055%) route 5.975ns (89.945%))
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Logic Levels: 1 (LUT1=1)
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Clock Path Skew: 0.294ns (DCD - SCD + CPR)
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Destination Clock Delay (DCD): -2.280ns
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Source Clock Delay (SCD): -2.574ns
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Clock Pessimism Removal (CPR): 0.000ns
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Clock Uncertainty: 0.222ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
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Total System Jitter (TSJ): 0.071ns
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Discrete Jitter (DJ): 0.192ns
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Phase Error (PE): 0.120ns
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Timing Exception: Asynchronous Clock Groups
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Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
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------------------------------------------------------------------- -------------------
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(clock sys_clk rise edge) 0.000 0.000 r
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clock source latency -6.275 -6.275
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propagated clock network latency
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3.702 -2.574
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SLICE_X22Y139 FDCE 0.000 -2.574 r pll_clk.u_rst_sys/delay_reg[1]/C
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SLICE_X22Y139 FDCE (Prop_fdce_C_Q) 0.518 -2.056 r pll_clk.u_rst_sys/delay_reg[1]/Q
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net (fo=117, routed) 3.113 1.057 pll_clk.u_rst_sys/Q[0]
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SLICE_X48Y97 r pll_clk.u_rst_sys/bf2_do_en_i_1/I0
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SLICE_X48Y97 LUT1 (Prop_lut1_I0_O) 0.150 1.207 f pll_clk.u_rst_sys/bf2_do_en_i_1/O
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net (fo=4121, routed) 2.863 4.070 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/p_0_in
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SLICE_X65Y102 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/buffers_1_reg/CLR
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------------------------------------------------------------------- -------------------
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(clock mlkem_clk rise edge)
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0.000 0.000 r
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clock source latency -5.674 -5.674
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propagated clock network latency
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3.395 -2.280
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Slack: inf
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Source: pll_clk.u_rst_sys/delay_reg[1]/C
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(rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
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Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/buffers_0_reg/CLR
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(recovery check against rising-edge clock mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns})
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Path Group: (none)
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Path Type: Recovery (Max at Fast Process Corner)
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Data Path Delay: 3.391ns (logic 0.261ns (7.696%) route 3.130ns (92.304%))
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Logic Levels: 1 (LUT1=1)
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Clock Path Skew: -0.268ns (DCD - SCD + CPR)
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Destination Clock Delay (DCD): -0.680ns
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Source Clock Delay (SCD): -0.412ns
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Clock Pessimism Removal (CPR): 0.000ns
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Clock Uncertainty: 0.222ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
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Total System Jitter (TSJ): 0.071ns
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Discrete Jitter (DJ): 0.192ns
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Phase Error (PE): 0.120ns
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Timing Exception: Asynchronous Clock Groups
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Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
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------------------------------------------------------------------- -------------------
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(clock sys_clk rise edge) 0.000 0.000 r
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clock source latency -1.947 -1.947
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propagated clock network latency
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1.535 -0.412
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SLICE_X22Y139 FDCE 0.000 -0.412 r pll_clk.u_rst_sys/delay_reg[1]/C
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SLICE_X22Y139 FDCE (Prop_fdce_C_Q) 0.204 -0.208 r pll_clk.u_rst_sys/delay_reg[1]/Q
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net (fo=117, routed) 1.683 1.475 pll_clk.u_rst_sys/Q[0]
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SLICE_X48Y97 r pll_clk.u_rst_sys/bf2_do_en_i_1/I0
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SLICE_X48Y97 LUT1 (Prop_lut1_I0_O) 0.057 1.532 f pll_clk.u_rst_sys/bf2_do_en_i_1/O
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net (fo=4121, routed) 1.448 2.979 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/p_0_in
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SLICE_X65Y102 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/buffers_0_reg/CLR
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------------------------------------------------------------------- -------------------
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(clock mlkem_clk rise edge)
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0.000 0.000 r
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clock source latency -1.848 -1.848
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propagated clock network latency
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1.168 -0.680
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Slack: inf
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Source: pll_clk.u_rst_sys/delay_reg[1]/C
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(rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
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Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/buffers_1_reg/CLR
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(recovery check against rising-edge clock mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns})
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Path Group: (none)
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Path Type: Recovery (Max at Fast Process Corner)
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Data Path Delay: 3.391ns (logic 0.261ns (7.696%) route 3.130ns (92.304%))
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Logic Levels: 1 (LUT1=1)
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Clock Path Skew: -0.268ns (DCD - SCD + CPR)
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Destination Clock Delay (DCD): -0.680ns
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Source Clock Delay (SCD): -0.412ns
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Clock Pessimism Removal (CPR): 0.000ns
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Clock Uncertainty: 0.222ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
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Total System Jitter (TSJ): 0.071ns
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Discrete Jitter (DJ): 0.192ns
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Phase Error (PE): 0.120ns
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Timing Exception: Asynchronous Clock Groups
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Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
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------------------------------------------------------------------- -------------------
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(clock sys_clk rise edge) 0.000 0.000 r
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clock source latency -1.947 -1.947
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propagated clock network latency
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1.535 -0.412
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SLICE_X22Y139 FDCE 0.000 -0.412 r pll_clk.u_rst_sys/delay_reg[1]/C
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SLICE_X22Y139 FDCE (Prop_fdce_C_Q) 0.204 -0.208 r pll_clk.u_rst_sys/delay_reg[1]/Q
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net (fo=117, routed) 1.683 1.475 pll_clk.u_rst_sys/Q[0]
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SLICE_X48Y97 r pll_clk.u_rst_sys/bf2_do_en_i_1/I0
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SLICE_X48Y97 LUT1 (Prop_lut1_I0_O) 0.057 1.532 f pll_clk.u_rst_sys/bf2_do_en_i_1/O
|
|
net (fo=4121, routed) 1.448 2.979 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/p_0_in
|
|
SLICE_X65Y102 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/buffers_1_reg/CLR
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock mlkem_clk rise edge)
|
|
0.000 0.000 r
|
|
clock source latency -1.848 -1.848
|
|
propagated clock network latency
|
|
1.168 -0.680
|
|
|
|
Slack: inf
|
|
Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_36_41/RAMA/CLK
|
|
(rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/_zz_ram_port1_reg[36]/D
|
|
(rising edge-triggered cell FDRE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns})
|
|
Path Group: (none)
|
|
Path Type: Setup (Max at Fast Process Corner)
|
|
Data Path Delay: 1.143ns (logic 0.612ns (53.534%) route 0.531ns (46.466%))
|
|
Logic Levels: 0
|
|
Clock Path Skew: -0.229ns (DCD - SCD + CPR)
|
|
Destination Clock Delay (DCD): -0.616ns
|
|
Source Clock Delay (SCD): -0.387ns
|
|
Clock Pessimism Removal (CPR): 0.000ns
|
|
Clock Uncertainty: 0.222ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Discrete Jitter (DJ): 0.192ns
|
|
Phase Error (PE): 0.120ns
|
|
Timing Exception: Asynchronous Clock Groups
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock sys_clk rise edge) 0.000 0.000 r
|
|
clock source latency -1.947 -1.947
|
|
propagated clock network latency
|
|
1.560 -0.387
|
|
SLICE_X70Y97 RAMD32 0.000 -0.387 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_36_41/RAMA/CLK
|
|
SLICE_X70Y97 RAMD32 (Prop_ramd32_CLK_O)
|
|
0.612 0.225 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_36_41/RAMA/O
|
|
net (fo=1, routed) 0.531 0.756 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/_zz_ram_port10__2[36]
|
|
SLICE_X67Y93 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/_zz_ram_port1_reg[36]/D
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock mlkem_clk rise edge)
|
|
0.000 0.000 r
|
|
clock source latency -1.848 -1.848
|
|
propagated clock network latency
|
|
1.232 -0.616
|
|
|
|
Slack: inf
|
|
Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_36_41/RAMA/CLK
|
|
(rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/_zz_ram_port1_reg[36]/D
|
|
(rising edge-triggered cell FDRE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns})
|
|
Path Group: (none)
|
|
Path Type: Setup (Max at Fast Process Corner)
|
|
Data Path Delay: 1.143ns (logic 0.612ns (53.534%) route 0.531ns (46.466%))
|
|
Logic Levels: 0
|
|
Clock Path Skew: -0.229ns (DCD - SCD + CPR)
|
|
Destination Clock Delay (DCD): -0.616ns
|
|
Source Clock Delay (SCD): -0.387ns
|
|
Clock Pessimism Removal (CPR): 0.000ns
|
|
Clock Uncertainty: 0.222ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Discrete Jitter (DJ): 0.192ns
|
|
Phase Error (PE): 0.120ns
|
|
Timing Exception: Asynchronous Clock Groups
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock sys_clk rise edge) 0.000 0.000 r
|
|
clock source latency -1.947 -1.947
|
|
propagated clock network latency
|
|
1.560 -0.387
|
|
SLICE_X70Y97 RAMD32 0.000 -0.387 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_36_41/RAMA/CLK
|
|
SLICE_X70Y97 RAMD32 (Prop_ramd32_CLK_O)
|
|
0.612 0.225 f u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_36_41/RAMA/O
|
|
net (fo=1, routed) 0.531 0.756 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/_zz_ram_port10__2[36]
|
|
SLICE_X67Y93 FDRE f u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/_zz_ram_port1_reg[36]/D
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock mlkem_clk rise edge)
|
|
0.000 0.000 r
|
|
clock source latency -1.848 -1.848
|
|
propagated clock network latency
|
|
1.232 -0.616
|
|
|
|
Slack: inf
|
|
Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/ram_reg_0_7_24_29/RAMA/CLK
|
|
(rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/_zz_ram_port1_reg[24]/D
|
|
(rising edge-triggered cell FDRE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns})
|
|
Path Group: (none)
|
|
Path Type: Setup (Max at Fast Process Corner)
|
|
Data Path Delay: 1.059ns (logic 0.612ns (57.810%) route 0.447ns (42.190%))
|
|
Logic Levels: 0
|
|
Clock Path Skew: -0.225ns (DCD - SCD + CPR)
|
|
Destination Clock Delay (DCD): -0.613ns
|
|
Source Clock Delay (SCD): -0.388ns
|
|
Clock Pessimism Removal (CPR): 0.000ns
|
|
Clock Uncertainty: 0.222ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Discrete Jitter (DJ): 0.192ns
|
|
Phase Error (PE): 0.120ns
|
|
Timing Exception: Asynchronous Clock Groups
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock sys_clk rise edge) 0.000 0.000 r
|
|
clock source latency -1.947 -1.947
|
|
propagated clock network latency
|
|
1.559 -0.388
|
|
SLICE_X44Y81 RAMD32 0.000 -0.388 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/ram_reg_0_7_24_29/RAMA/CLK
|
|
SLICE_X44Y81 RAMD32 (Prop_ramd32_CLK_O)
|
|
0.612 0.224 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/ram_reg_0_7_24_29/RAMA/O
|
|
net (fo=1, routed) 0.447 0.670 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/_zz_ram_port10__0[24]
|
|
SLICE_X45Y83 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/_zz_ram_port1_reg[24]/D
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock mlkem_clk rise edge)
|
|
0.000 0.000 r
|
|
clock source latency -1.848 -1.848
|
|
propagated clock network latency
|
|
1.235 -0.613
|
|
|
|
Slack: inf
|
|
Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/ram_reg_0_7_24_29/RAMA/CLK
|
|
(rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/_zz_ram_port1_reg[24]/D
|
|
(rising edge-triggered cell FDRE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns})
|
|
Path Group: (none)
|
|
Path Type: Setup (Max at Fast Process Corner)
|
|
Data Path Delay: 1.059ns (logic 0.612ns (57.810%) route 0.447ns (42.190%))
|
|
Logic Levels: 0
|
|
Clock Path Skew: -0.225ns (DCD - SCD + CPR)
|
|
Destination Clock Delay (DCD): -0.613ns
|
|
Source Clock Delay (SCD): -0.388ns
|
|
Clock Pessimism Removal (CPR): 0.000ns
|
|
Clock Uncertainty: 0.222ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Discrete Jitter (DJ): 0.192ns
|
|
Phase Error (PE): 0.120ns
|
|
Timing Exception: Asynchronous Clock Groups
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock sys_clk rise edge) 0.000 0.000 r
|
|
clock source latency -1.947 -1.947
|
|
propagated clock network latency
|
|
1.559 -0.388
|
|
SLICE_X44Y81 RAMD32 0.000 -0.388 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/ram_reg_0_7_24_29/RAMA/CLK
|
|
SLICE_X44Y81 RAMD32 (Prop_ramd32_CLK_O)
|
|
0.612 0.224 f u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/ram_reg_0_7_24_29/RAMA/O
|
|
net (fo=1, routed) 0.447 0.670 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/_zz_ram_port10__0[24]
|
|
SLICE_X45Y83 FDRE f u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/_zz_ram_port1_reg[24]/D
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock mlkem_clk rise edge)
|
|
0.000 0.000 r
|
|
clock source latency -1.848 -1.848
|
|
propagated clock network latency
|
|
1.235 -0.613
|
|
|
|
Slack: inf
|
|
Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/ram_reg_0_3_6_11/RAMA_D1/CLK
|
|
(rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/_zz_ram_port1_reg[7]/D
|
|
(rising edge-triggered cell FDRE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns})
|
|
Path Group: (none)
|
|
Path Type: Setup (Max at Fast Process Corner)
|
|
Data Path Delay: 1.002ns (logic 0.595ns (59.409%) route 0.407ns (40.591%))
|
|
Logic Levels: 0
|
|
Clock Path Skew: -0.226ns (DCD - SCD + CPR)
|
|
Destination Clock Delay (DCD): -0.613ns
|
|
Source Clock Delay (SCD): -0.387ns
|
|
Clock Pessimism Removal (CPR): 0.000ns
|
|
Clock Uncertainty: 0.222ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Discrete Jitter (DJ): 0.192ns
|
|
Phase Error (PE): 0.120ns
|
|
Timing Exception: Asynchronous Clock Groups
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock sys_clk rise edge) 0.000 0.000 r
|
|
clock source latency -1.947 -1.947
|
|
propagated clock network latency
|
|
1.560 -0.387
|
|
SLICE_X52Y83 RAMD32 0.000 -0.387 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/ram_reg_0_3_6_11/RAMA_D1/CLK
|
|
SLICE_X52Y83 RAMD32 (Prop_ramd32_CLK_O)
|
|
0.595 0.208 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/ram_reg_0_3_6_11/RAMA_D1/O
|
|
net (fo=1, routed) 0.407 0.614 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/_zz_ram_port10[7]
|
|
SLICE_X54Y85 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/_zz_ram_port1_reg[7]/D
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock mlkem_clk rise edge)
|
|
0.000 0.000 r
|
|
clock source latency -1.848 -1.848
|
|
propagated clock network latency
|
|
1.235 -0.613
|
|
|
|
Slack: inf
|
|
Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/ram_reg_0_3_6_11/RAMA_D1/CLK
|
|
(rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/_zz_ram_port1_reg[7]/D
|
|
(rising edge-triggered cell FDRE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns})
|
|
Path Group: (none)
|
|
Path Type: Setup (Max at Fast Process Corner)
|
|
Data Path Delay: 1.002ns (logic 0.595ns (59.409%) route 0.407ns (40.591%))
|
|
Logic Levels: 0
|
|
Clock Path Skew: -0.226ns (DCD - SCD + CPR)
|
|
Destination Clock Delay (DCD): -0.613ns
|
|
Source Clock Delay (SCD): -0.387ns
|
|
Clock Pessimism Removal (CPR): 0.000ns
|
|
Clock Uncertainty: 0.222ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Discrete Jitter (DJ): 0.192ns
|
|
Phase Error (PE): 0.120ns
|
|
Timing Exception: Asynchronous Clock Groups
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock sys_clk rise edge) 0.000 0.000 r
|
|
clock source latency -1.947 -1.947
|
|
propagated clock network latency
|
|
1.560 -0.387
|
|
SLICE_X52Y83 RAMD32 0.000 -0.387 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/ram_reg_0_3_6_11/RAMA_D1/CLK
|
|
SLICE_X52Y83 RAMD32 (Prop_ramd32_CLK_O)
|
|
0.595 0.208 f u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/ram_reg_0_3_6_11/RAMA_D1/O
|
|
net (fo=1, routed) 0.407 0.614 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/_zz_ram_port10[7]
|
|
SLICE_X54Y85 FDRE f u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/_zz_ram_port1_reg[7]/D
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock mlkem_clk rise edge)
|
|
0.000 0.000 r
|
|
clock source latency -1.848 -1.848
|
|
propagated clock network latency
|
|
1.235 -0.613
|
|
|
|
Slack: inf
|
|
Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_48_53/RAMA/CLK
|
|
(rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/_zz_ram_port1_reg[48]/D
|
|
(rising edge-triggered cell FDRE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns})
|
|
Path Group: (none)
|
|
Path Type: Setup (Max at Fast Process Corner)
|
|
Data Path Delay: 0.994ns (logic 0.612ns (61.564%) route 0.382ns (38.436%))
|
|
Logic Levels: 0
|
|
Clock Path Skew: -0.231ns (DCD - SCD + CPR)
|
|
Destination Clock Delay (DCD): -0.617ns
|
|
Source Clock Delay (SCD): -0.386ns
|
|
Clock Pessimism Removal (CPR): 0.000ns
|
|
Clock Uncertainty: 0.222ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Discrete Jitter (DJ): 0.192ns
|
|
Phase Error (PE): 0.120ns
|
|
Timing Exception: Asynchronous Clock Groups
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock sys_clk rise edge) 0.000 0.000 r
|
|
clock source latency -1.947 -1.947
|
|
propagated clock network latency
|
|
1.561 -0.386
|
|
SLICE_X68Y97 RAMD32 0.000 -0.386 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_48_53/RAMA/CLK
|
|
SLICE_X68Y97 RAMD32 (Prop_ramd32_CLK_O)
|
|
0.612 0.226 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_48_53/RAMA/O
|
|
net (fo=1, routed) 0.382 0.608 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/_zz_ram_port10__2[48]
|
|
SLICE_X70Y93 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/_zz_ram_port1_reg[48]/D
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock mlkem_clk rise edge)
|
|
0.000 0.000 r
|
|
clock source latency -1.848 -1.848
|
|
propagated clock network latency
|
|
1.231 -0.617
|
|
|
|
Slack: inf
|
|
Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_48_53/RAMA/CLK
|
|
(rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/_zz_ram_port1_reg[48]/D
|
|
(rising edge-triggered cell FDRE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns})
|
|
Path Group: (none)
|
|
Path Type: Setup (Max at Fast Process Corner)
|
|
Data Path Delay: 0.994ns (logic 0.612ns (61.564%) route 0.382ns (38.436%))
|
|
Logic Levels: 0
|
|
Clock Path Skew: -0.231ns (DCD - SCD + CPR)
|
|
Destination Clock Delay (DCD): -0.617ns
|
|
Source Clock Delay (SCD): -0.386ns
|
|
Clock Pessimism Removal (CPR): 0.000ns
|
|
Clock Uncertainty: 0.222ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Discrete Jitter (DJ): 0.192ns
|
|
Phase Error (PE): 0.120ns
|
|
Timing Exception: Asynchronous Clock Groups
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock sys_clk rise edge) 0.000 0.000 r
|
|
clock source latency -1.947 -1.947
|
|
propagated clock network latency
|
|
1.561 -0.386
|
|
SLICE_X68Y97 RAMD32 0.000 -0.386 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_48_53/RAMA/CLK
|
|
SLICE_X68Y97 RAMD32 (Prop_ramd32_CLK_O)
|
|
0.612 0.226 f u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_48_53/RAMA/O
|
|
net (fo=1, routed) 0.382 0.608 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/_zz_ram_port10__2[48]
|
|
SLICE_X70Y93 FDRE f u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/_zz_ram_port1_reg[48]/D
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock mlkem_clk rise edge)
|
|
0.000 0.000 r
|
|
clock source latency -1.848 -1.848
|
|
propagated clock network latency
|
|
1.231 -0.617
|
|
|
|
Slack: inf
|
|
Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_0_5/RAMA/CLK
|
|
(rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/_zz_ram_port1_reg[0]/D
|
|
(rising edge-triggered cell FDRE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns})
|
|
Path Group: (none)
|
|
Path Type: Setup (Max at Fast Process Corner)
|
|
Data Path Delay: 0.982ns (logic 0.612ns (62.344%) route 0.370ns (37.656%))
|
|
Logic Levels: 0
|
|
Clock Path Skew: -0.230ns (DCD - SCD + CPR)
|
|
Destination Clock Delay (DCD): -0.614ns
|
|
Source Clock Delay (SCD): -0.384ns
|
|
Clock Pessimism Removal (CPR): 0.000ns
|
|
Clock Uncertainty: 0.222ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Discrete Jitter (DJ): 0.192ns
|
|
Phase Error (PE): 0.120ns
|
|
Timing Exception: Asynchronous Clock Groups
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock sys_clk rise edge) 0.000 0.000 r
|
|
clock source latency -1.947 -1.947
|
|
propagated clock network latency
|
|
1.563 -0.384
|
|
SLICE_X62Y93 RAMD32 0.000 -0.384 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_0_5/RAMA/CLK
|
|
SLICE_X62Y93 RAMD32 (Prop_ramd32_CLK_O)
|
|
0.612 0.228 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_0_5/RAMA/O
|
|
net (fo=1, routed) 0.370 0.597 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/_zz_ram_port10__2[0]
|
|
SLICE_X65Y96 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/_zz_ram_port1_reg[0]/D
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock mlkem_clk rise edge)
|
|
0.000 0.000 r
|
|
clock source latency -1.848 -1.848
|
|
propagated clock network latency
|
|
1.234 -0.614
|
|
|
|
Slack: inf
|
|
Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_0_5/RAMA/CLK
|
|
(rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/_zz_ram_port1_reg[0]/D
|
|
(rising edge-triggered cell FDRE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns})
|
|
Path Group: (none)
|
|
Path Type: Setup (Max at Fast Process Corner)
|
|
Data Path Delay: 0.982ns (logic 0.612ns (62.344%) route 0.370ns (37.656%))
|
|
Logic Levels: 0
|
|
Clock Path Skew: -0.230ns (DCD - SCD + CPR)
|
|
Destination Clock Delay (DCD): -0.614ns
|
|
Source Clock Delay (SCD): -0.384ns
|
|
Clock Pessimism Removal (CPR): 0.000ns
|
|
Clock Uncertainty: 0.222ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Discrete Jitter (DJ): 0.192ns
|
|
Phase Error (PE): 0.120ns
|
|
Timing Exception: Asynchronous Clock Groups
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock sys_clk rise edge) 0.000 0.000 r
|
|
clock source latency -1.947 -1.947
|
|
propagated clock network latency
|
|
1.563 -0.384
|
|
SLICE_X62Y93 RAMD32 0.000 -0.384 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_0_5/RAMA/CLK
|
|
SLICE_X62Y93 RAMD32 (Prop_ramd32_CLK_O)
|
|
0.612 0.228 f u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_0_5/RAMA/O
|
|
net (fo=1, routed) 0.370 0.597 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/_zz_ram_port10__2[0]
|
|
SLICE_X65Y96 FDRE f u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/_zz_ram_port1_reg[0]/D
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock mlkem_clk rise edge)
|
|
0.000 0.000 r
|
|
clock source latency -1.848 -1.848
|
|
propagated clock network latency
|
|
1.234 -0.614
|
|
|
|
Slack: inf
|
|
Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/ram_reg_0_3_36_41/RAMA/CLK
|
|
(rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/_zz_ram_port1_reg[36]/D
|
|
(rising edge-triggered cell FDRE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns})
|
|
Path Group: (none)
|
|
Path Type: Setup (Max at Fast Process Corner)
|
|
Data Path Delay: 0.966ns (logic 0.612ns (63.335%) route 0.354ns (36.665%))
|
|
Logic Levels: 0
|
|
Clock Path Skew: -0.231ns (DCD - SCD + CPR)
|
|
Destination Clock Delay (DCD): -0.611ns
|
|
Source Clock Delay (SCD): -0.380ns
|
|
Clock Pessimism Removal (CPR): 0.000ns
|
|
Clock Uncertainty: 0.222ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Discrete Jitter (DJ): 0.192ns
|
|
Phase Error (PE): 0.120ns
|
|
Timing Exception: Asynchronous Clock Groups
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock sys_clk rise edge) 0.000 0.000 r
|
|
clock source latency -1.947 -1.947
|
|
propagated clock network latency
|
|
1.567 -0.380
|
|
SLICE_X56Y93 RAMD32 0.000 -0.380 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/ram_reg_0_3_36_41/RAMA/CLK
|
|
SLICE_X56Y93 RAMD32 (Prop_ramd32_CLK_O)
|
|
0.612 0.232 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/ram_reg_0_3_36_41/RAMA/O
|
|
net (fo=1, routed) 0.354 0.586 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/_zz_ram_port10[36]
|
|
SLICE_X56Y89 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/_zz_ram_port1_reg[36]/D
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock mlkem_clk rise edge)
|
|
0.000 0.000 r
|
|
clock source latency -1.848 -1.848
|
|
propagated clock network latency
|
|
1.237 -0.611
|
|
|
|
Slack: inf
|
|
Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/ram_reg_0_3_36_41/RAMA/CLK
|
|
(rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/_zz_ram_port1_reg[36]/D
|
|
(rising edge-triggered cell FDRE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns})
|
|
Path Group: (none)
|
|
Path Type: Setup (Max at Fast Process Corner)
|
|
Data Path Delay: 0.966ns (logic 0.612ns (63.335%) route 0.354ns (36.665%))
|
|
Logic Levels: 0
|
|
Clock Path Skew: -0.231ns (DCD - SCD + CPR)
|
|
Destination Clock Delay (DCD): -0.611ns
|
|
Source Clock Delay (SCD): -0.380ns
|
|
Clock Pessimism Removal (CPR): 0.000ns
|
|
Clock Uncertainty: 0.222ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Discrete Jitter (DJ): 0.192ns
|
|
Phase Error (PE): 0.120ns
|
|
Timing Exception: Asynchronous Clock Groups
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock sys_clk rise edge) 0.000 0.000 r
|
|
clock source latency -1.947 -1.947
|
|
propagated clock network latency
|
|
1.567 -0.380
|
|
SLICE_X56Y93 RAMD32 0.000 -0.380 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/ram_reg_0_3_36_41/RAMA/CLK
|
|
SLICE_X56Y93 RAMD32 (Prop_ramd32_CLK_O)
|
|
0.612 0.232 f u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/ram_reg_0_3_36_41/RAMA/O
|
|
net (fo=1, routed) 0.354 0.586 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/_zz_ram_port10[36]
|
|
SLICE_X56Y89 FDRE f u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/_zz_ram_port1_reg[36]/D
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock mlkem_clk rise edge)
|
|
0.000 0.000 r
|
|
clock source latency -1.848 -1.848
|
|
propagated clock network latency
|
|
1.237 -0.611
|
|
|
|
Slack: inf
|
|
Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_0_5/RAMB/CLK
|
|
(rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/_zz_ram_port1_reg[2]/D
|
|
(rising edge-triggered cell FDRE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns})
|
|
Path Group: (none)
|
|
Path Type: Setup (Max at Fast Process Corner)
|
|
Data Path Delay: 0.963ns (logic 0.491ns (50.975%) route 0.472ns (49.025%))
|
|
Logic Levels: 0
|
|
Clock Path Skew: -0.230ns (DCD - SCD + CPR)
|
|
Destination Clock Delay (DCD): -0.614ns
|
|
Source Clock Delay (SCD): -0.384ns
|
|
Clock Pessimism Removal (CPR): 0.000ns
|
|
Clock Uncertainty: 0.222ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Discrete Jitter (DJ): 0.192ns
|
|
Phase Error (PE): 0.120ns
|
|
Timing Exception: Asynchronous Clock Groups
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock sys_clk rise edge) 0.000 0.000 r
|
|
clock source latency -1.947 -1.947
|
|
propagated clock network latency
|
|
1.563 -0.384
|
|
SLICE_X62Y93 RAMD32 0.000 -0.384 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_0_5/RAMB/CLK
|
|
SLICE_X62Y93 RAMD32 (Prop_ramd32_CLK_O)
|
|
0.491 0.107 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_0_5/RAMB/O
|
|
net (fo=1, routed) 0.472 0.579 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/_zz_ram_port10__2[2]
|
|
SLICE_X65Y96 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/_zz_ram_port1_reg[2]/D
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock mlkem_clk rise edge)
|
|
0.000 0.000 r
|
|
clock source latency -1.848 -1.848
|
|
propagated clock network latency
|
|
1.234 -0.614
|
|
|
|
Slack: inf
|
|
Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_0_5/RAMB/CLK
|
|
(rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/_zz_ram_port1_reg[2]/D
|
|
(rising edge-triggered cell FDRE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns})
|
|
Path Group: (none)
|
|
Path Type: Setup (Max at Fast Process Corner)
|
|
Data Path Delay: 0.963ns (logic 0.491ns (50.975%) route 0.472ns (49.025%))
|
|
Logic Levels: 0
|
|
Clock Path Skew: -0.230ns (DCD - SCD + CPR)
|
|
Destination Clock Delay (DCD): -0.614ns
|
|
Source Clock Delay (SCD): -0.384ns
|
|
Clock Pessimism Removal (CPR): 0.000ns
|
|
Clock Uncertainty: 0.222ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Discrete Jitter (DJ): 0.192ns
|
|
Phase Error (PE): 0.120ns
|
|
Timing Exception: Asynchronous Clock Groups
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock sys_clk rise edge) 0.000 0.000 r
|
|
clock source latency -1.947 -1.947
|
|
propagated clock network latency
|
|
1.563 -0.384
|
|
SLICE_X62Y93 RAMD32 0.000 -0.384 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_0_5/RAMB/CLK
|
|
SLICE_X62Y93 RAMD32 (Prop_ramd32_CLK_O)
|
|
0.491 0.107 f u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_0_5/RAMB/O
|
|
net (fo=1, routed) 0.472 0.579 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/_zz_ram_port10__2[2]
|
|
SLICE_X65Y96 FDRE f u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/_zz_ram_port1_reg[2]/D
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock mlkem_clk rise edge)
|
|
0.000 0.000 r
|
|
clock source latency -1.848 -1.848
|
|
propagated clock network latency
|
|
1.234 -0.614
|
|
|
|
Slack: inf
|
|
Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_12_17/RAMA_D1/CLK
|
|
(rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/_zz_ram_port1_reg[13]/D
|
|
(rising edge-triggered cell FDRE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns})
|
|
Path Group: (none)
|
|
Path Type: Setup (Max at Fast Process Corner)
|
|
Data Path Delay: 0.957ns (logic 0.595ns (62.185%) route 0.362ns (37.815%))
|
|
Logic Levels: 0
|
|
Clock Path Skew: -0.232ns (DCD - SCD + CPR)
|
|
Destination Clock Delay (DCD): -0.617ns
|
|
Source Clock Delay (SCD): -0.385ns
|
|
Clock Pessimism Removal (CPR): 0.000ns
|
|
Clock Uncertainty: 0.222ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Discrete Jitter (DJ): 0.192ns
|
|
Phase Error (PE): 0.120ns
|
|
Timing Exception: Asynchronous Clock Groups
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock sys_clk rise edge) 0.000 0.000 r
|
|
clock source latency -1.947 -1.947
|
|
propagated clock network latency
|
|
1.562 -0.385
|
|
SLICE_X64Y94 RAMD32 0.000 -0.385 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_12_17/RAMA_D1/CLK
|
|
SLICE_X64Y94 RAMD32 (Prop_ramd32_CLK_O)
|
|
0.595 0.210 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_12_17/RAMA_D1/O
|
|
net (fo=1, routed) 0.362 0.572 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/_zz_ram_port10__2[13]
|
|
SLICE_X70Y93 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/_zz_ram_port1_reg[13]/D
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock mlkem_clk rise edge)
|
|
0.000 0.000 r
|
|
clock source latency -1.848 -1.848
|
|
propagated clock network latency
|
|
1.231 -0.617
|
|
|
|
Slack: inf
|
|
Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_12_17/RAMA_D1/CLK
|
|
(rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/_zz_ram_port1_reg[13]/D
|
|
(rising edge-triggered cell FDRE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns})
|
|
Path Group: (none)
|
|
Path Type: Setup (Max at Fast Process Corner)
|
|
Data Path Delay: 0.957ns (logic 0.595ns (62.185%) route 0.362ns (37.815%))
|
|
Logic Levels: 0
|
|
Clock Path Skew: -0.232ns (DCD - SCD + CPR)
|
|
Destination Clock Delay (DCD): -0.617ns
|
|
Source Clock Delay (SCD): -0.385ns
|
|
Clock Pessimism Removal (CPR): 0.000ns
|
|
Clock Uncertainty: 0.222ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Discrete Jitter (DJ): 0.192ns
|
|
Phase Error (PE): 0.120ns
|
|
Timing Exception: Asynchronous Clock Groups
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock sys_clk rise edge) 0.000 0.000 r
|
|
clock source latency -1.947 -1.947
|
|
propagated clock network latency
|
|
1.562 -0.385
|
|
SLICE_X64Y94 RAMD32 0.000 -0.385 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_12_17/RAMA_D1/CLK
|
|
SLICE_X64Y94 RAMD32 (Prop_ramd32_CLK_O)
|
|
0.595 0.210 f u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_12_17/RAMA_D1/O
|
|
net (fo=1, routed) 0.362 0.572 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/_zz_ram_port10__2[13]
|
|
SLICE_X70Y93 FDRE f u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/_zz_ram_port1_reg[13]/D
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock mlkem_clk rise edge)
|
|
0.000 0.000 r
|
|
clock source latency -1.848 -1.848
|
|
propagated clock network latency
|
|
1.231 -0.617
|
|
|
|
Slack: inf
|
|
Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_12_17/RAMB_D1/CLK
|
|
(rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/_zz_ram_port1_reg[15]/D
|
|
(rising edge-triggered cell FDRE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns})
|
|
Path Group: (none)
|
|
Path Type: Setup (Max at Fast Process Corner)
|
|
Data Path Delay: 0.957ns (logic 0.482ns (50.382%) route 0.475ns (49.618%))
|
|
Logic Levels: 0
|
|
Clock Path Skew: -0.232ns (DCD - SCD + CPR)
|
|
Destination Clock Delay (DCD): -0.617ns
|
|
Source Clock Delay (SCD): -0.385ns
|
|
Clock Pessimism Removal (CPR): 0.000ns
|
|
Clock Uncertainty: 0.222ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Discrete Jitter (DJ): 0.192ns
|
|
Phase Error (PE): 0.120ns
|
|
Timing Exception: Asynchronous Clock Groups
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock sys_clk rise edge) 0.000 0.000 r
|
|
clock source latency -1.947 -1.947
|
|
propagated clock network latency
|
|
1.562 -0.385
|
|
SLICE_X64Y94 RAMD32 0.000 -0.385 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_12_17/RAMB_D1/CLK
|
|
SLICE_X64Y94 RAMD32 (Prop_ramd32_CLK_O)
|
|
0.482 0.097 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_12_17/RAMB_D1/O
|
|
net (fo=1, routed) 0.475 0.572 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/_zz_ram_port10__2[15]
|
|
SLICE_X70Y93 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/_zz_ram_port1_reg[15]/D
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock mlkem_clk rise edge)
|
|
0.000 0.000 r
|
|
clock source latency -1.848 -1.848
|
|
propagated clock network latency
|
|
1.231 -0.617
|
|
|
|
Slack: inf
|
|
Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_12_17/RAMB_D1/CLK
|
|
(rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/_zz_ram_port1_reg[15]/D
|
|
(rising edge-triggered cell FDRE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns})
|
|
Path Group: (none)
|
|
Path Type: Setup (Max at Fast Process Corner)
|
|
Data Path Delay: 0.957ns (logic 0.482ns (50.382%) route 0.475ns (49.618%))
|
|
Logic Levels: 0
|
|
Clock Path Skew: -0.232ns (DCD - SCD + CPR)
|
|
Destination Clock Delay (DCD): -0.617ns
|
|
Source Clock Delay (SCD): -0.385ns
|
|
Clock Pessimism Removal (CPR): 0.000ns
|
|
Clock Uncertainty: 0.222ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Discrete Jitter (DJ): 0.192ns
|
|
Phase Error (PE): 0.120ns
|
|
Timing Exception: Asynchronous Clock Groups
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock sys_clk rise edge) 0.000 0.000 r
|
|
clock source latency -1.947 -1.947
|
|
propagated clock network latency
|
|
1.562 -0.385
|
|
SLICE_X64Y94 RAMD32 0.000 -0.385 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_12_17/RAMB_D1/CLK
|
|
SLICE_X64Y94 RAMD32 (Prop_ramd32_CLK_O)
|
|
0.482 0.097 f u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_12_17/RAMB_D1/O
|
|
net (fo=1, routed) 0.475 0.572 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/_zz_ram_port10__2[15]
|
|
SLICE_X70Y93 FDRE f u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/_zz_ram_port1_reg[15]/D
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock mlkem_clk rise edge)
|
|
0.000 0.000 r
|
|
clock source latency -1.848 -1.848
|
|
propagated clock network latency
|
|
1.231 -0.617
|
|
|
|
Slack: inf
|
|
Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/ram_reg_0_3_6_11/RAMB_D1/CLK
|
|
(rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/_zz_ram_port1_reg[9]/D
|
|
(rising edge-triggered cell FDRE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns})
|
|
Path Group: (none)
|
|
Path Type: Setup (Max at Fast Process Corner)
|
|
Data Path Delay: 0.954ns (logic 0.482ns (50.537%) route 0.472ns (49.463%))
|
|
Logic Levels: 0
|
|
Clock Path Skew: -0.226ns (DCD - SCD + CPR)
|
|
Destination Clock Delay (DCD): -0.613ns
|
|
Source Clock Delay (SCD): -0.387ns
|
|
Clock Pessimism Removal (CPR): 0.000ns
|
|
Clock Uncertainty: 0.222ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Discrete Jitter (DJ): 0.192ns
|
|
Phase Error (PE): 0.120ns
|
|
Timing Exception: Asynchronous Clock Groups
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock sys_clk rise edge) 0.000 0.000 r
|
|
clock source latency -1.947 -1.947
|
|
propagated clock network latency
|
|
1.560 -0.387
|
|
SLICE_X52Y83 RAMD32 0.000 -0.387 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/ram_reg_0_3_6_11/RAMB_D1/CLK
|
|
SLICE_X52Y83 RAMD32 (Prop_ramd32_CLK_O)
|
|
0.482 0.095 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/ram_reg_0_3_6_11/RAMB_D1/O
|
|
net (fo=1, routed) 0.472 0.567 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/_zz_ram_port10[9]
|
|
SLICE_X54Y86 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/_zz_ram_port1_reg[9]/D
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock mlkem_clk rise edge)
|
|
0.000 0.000 r
|
|
clock source latency -1.848 -1.848
|
|
propagated clock network latency
|
|
1.235 -0.613
|
|
|
|
Slack: inf
|
|
Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/ram_reg_0_3_6_11/RAMB_D1/CLK
|
|
(rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/_zz_ram_port1_reg[9]/D
|
|
(rising edge-triggered cell FDRE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns})
|
|
Path Group: (none)
|
|
Path Type: Setup (Max at Fast Process Corner)
|
|
Data Path Delay: 0.954ns (logic 0.482ns (50.537%) route 0.472ns (49.463%))
|
|
Logic Levels: 0
|
|
Clock Path Skew: -0.226ns (DCD - SCD + CPR)
|
|
Destination Clock Delay (DCD): -0.613ns
|
|
Source Clock Delay (SCD): -0.387ns
|
|
Clock Pessimism Removal (CPR): 0.000ns
|
|
Clock Uncertainty: 0.222ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Discrete Jitter (DJ): 0.192ns
|
|
Phase Error (PE): 0.120ns
|
|
Timing Exception: Asynchronous Clock Groups
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock sys_clk rise edge) 0.000 0.000 r
|
|
clock source latency -1.947 -1.947
|
|
propagated clock network latency
|
|
1.560 -0.387
|
|
SLICE_X52Y83 RAMD32 0.000 -0.387 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/ram_reg_0_3_6_11/RAMB_D1/CLK
|
|
SLICE_X52Y83 RAMD32 (Prop_ramd32_CLK_O)
|
|
0.482 0.095 f u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/ram_reg_0_3_6_11/RAMB_D1/O
|
|
net (fo=1, routed) 0.472 0.567 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/_zz_ram_port10[9]
|
|
SLICE_X54Y86 FDRE f u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/_zz_ram_port1_reg[9]/D
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock mlkem_clk rise edge)
|
|
0.000 0.000 r
|
|
clock source latency -1.848 -1.848
|
|
propagated clock network latency
|
|
1.235 -0.613
|
|
|
|
Slack: inf
|
|
Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/ram_reg_0_7_0_5/RAMA_D1/CLK
|
|
(rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/_zz_ram_port1_reg[1]/D
|
|
(rising edge-triggered cell FDRE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns})
|
|
Path Group: (none)
|
|
Path Type: Setup (Max at Fast Process Corner)
|
|
Data Path Delay: 0.940ns (logic 0.595ns (63.287%) route 0.345ns (36.713%))
|
|
Logic Levels: 0
|
|
Clock Path Skew: -0.227ns (DCD - SCD + CPR)
|
|
Destination Clock Delay (DCD): -0.616ns
|
|
Source Clock Delay (SCD): -0.389ns
|
|
Clock Pessimism Removal (CPR): 0.000ns
|
|
Clock Uncertainty: 0.222ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Discrete Jitter (DJ): 0.192ns
|
|
Phase Error (PE): 0.120ns
|
|
Timing Exception: Asynchronous Clock Groups
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock sys_clk rise edge) 0.000 0.000 r
|
|
clock source latency -1.947 -1.947
|
|
propagated clock network latency
|
|
1.558 -0.389
|
|
SLICE_X44Y80 RAMD32 0.000 -0.389 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/ram_reg_0_7_0_5/RAMA_D1/CLK
|
|
SLICE_X44Y80 RAMD32 (Prop_ramd32_CLK_O)
|
|
0.595 0.206 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/ram_reg_0_7_0_5/RAMA_D1/O
|
|
net (fo=1, routed) 0.345 0.551 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/_zz_ram_port10__0[1]
|
|
SLICE_X42Y80 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/_zz_ram_port1_reg[1]/D
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock mlkem_clk rise edge)
|
|
0.000 0.000 r
|
|
clock source latency -1.848 -1.848
|
|
propagated clock network latency
|
|
1.232 -0.616
|
|
|
|
Slack: inf
|
|
Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/ram_reg_0_7_0_5/RAMA_D1/CLK
|
|
(rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/_zz_ram_port1_reg[1]/D
|
|
(rising edge-triggered cell FDRE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns})
|
|
Path Group: (none)
|
|
Path Type: Setup (Max at Fast Process Corner)
|
|
Data Path Delay: 0.940ns (logic 0.595ns (63.287%) route 0.345ns (36.713%))
|
|
Logic Levels: 0
|
|
Clock Path Skew: -0.227ns (DCD - SCD + CPR)
|
|
Destination Clock Delay (DCD): -0.616ns
|
|
Source Clock Delay (SCD): -0.389ns
|
|
Clock Pessimism Removal (CPR): 0.000ns
|
|
Clock Uncertainty: 0.222ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Discrete Jitter (DJ): 0.192ns
|
|
Phase Error (PE): 0.120ns
|
|
Timing Exception: Asynchronous Clock Groups
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock sys_clk rise edge) 0.000 0.000 r
|
|
clock source latency -1.947 -1.947
|
|
propagated clock network latency
|
|
1.558 -0.389
|
|
SLICE_X44Y80 RAMD32 0.000 -0.389 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/ram_reg_0_7_0_5/RAMA_D1/CLK
|
|
SLICE_X44Y80 RAMD32 (Prop_ramd32_CLK_O)
|
|
0.595 0.206 f u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/ram_reg_0_7_0_5/RAMA_D1/O
|
|
net (fo=1, routed) 0.345 0.551 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/_zz_ram_port10__0[1]
|
|
SLICE_X42Y80 FDRE f u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/_zz_ram_port1_reg[1]/D
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock mlkem_clk rise edge)
|
|
0.000 0.000 r
|
|
clock source latency -1.848 -1.848
|
|
propagated clock network latency
|
|
1.232 -0.616
|
|
|
|
Slack: inf
|
|
Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_12_17/RAMA/CLK
|
|
(rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/_zz_ram_port1_reg[12]/D
|
|
(rising edge-triggered cell FDRE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns})
|
|
Path Group: (none)
|
|
Path Type: Setup (Max at Fast Process Corner)
|
|
Data Path Delay: 0.935ns (logic 0.612ns (65.444%) route 0.323ns (34.556%))
|
|
Logic Levels: 0
|
|
Clock Path Skew: -0.231ns (DCD - SCD + CPR)
|
|
Destination Clock Delay (DCD): -0.616ns
|
|
Source Clock Delay (SCD): -0.385ns
|
|
Clock Pessimism Removal (CPR): 0.000ns
|
|
Clock Uncertainty: 0.222ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Discrete Jitter (DJ): 0.192ns
|
|
Phase Error (PE): 0.120ns
|
|
Timing Exception: Asynchronous Clock Groups
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock sys_clk rise edge) 0.000 0.000 r
|
|
clock source latency -1.947 -1.947
|
|
propagated clock network latency
|
|
1.562 -0.385
|
|
SLICE_X64Y94 RAMD32 0.000 -0.385 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_12_17/RAMA/CLK
|
|
SLICE_X64Y94 RAMD32 (Prop_ramd32_CLK_O)
|
|
0.612 0.227 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_12_17/RAMA/O
|
|
net (fo=1, routed) 0.323 0.550 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/_zz_ram_port10__2[12]
|
|
SLICE_X67Y94 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/_zz_ram_port1_reg[12]/D
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock mlkem_clk rise edge)
|
|
0.000 0.000 r
|
|
clock source latency -1.848 -1.848
|
|
propagated clock network latency
|
|
1.232 -0.616
|
|
|
|
Slack: inf
|
|
Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_12_17/RAMA/CLK
|
|
(rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/_zz_ram_port1_reg[12]/D
|
|
(rising edge-triggered cell FDRE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns})
|
|
Path Group: (none)
|
|
Path Type: Setup (Max at Fast Process Corner)
|
|
Data Path Delay: 0.935ns (logic 0.612ns (65.444%) route 0.323ns (34.556%))
|
|
Logic Levels: 0
|
|
Clock Path Skew: -0.231ns (DCD - SCD + CPR)
|
|
Destination Clock Delay (DCD): -0.616ns
|
|
Source Clock Delay (SCD): -0.385ns
|
|
Clock Pessimism Removal (CPR): 0.000ns
|
|
Clock Uncertainty: 0.222ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Discrete Jitter (DJ): 0.192ns
|
|
Phase Error (PE): 0.120ns
|
|
Timing Exception: Asynchronous Clock Groups
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock sys_clk rise edge) 0.000 0.000 r
|
|
clock source latency -1.947 -1.947
|
|
propagated clock network latency
|
|
1.562 -0.385
|
|
SLICE_X64Y94 RAMD32 0.000 -0.385 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_12_17/RAMA/CLK
|
|
SLICE_X64Y94 RAMD32 (Prop_ramd32_CLK_O)
|
|
0.612 0.227 f u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_12_17/RAMA/O
|
|
net (fo=1, routed) 0.323 0.550 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/_zz_ram_port10__2[12]
|
|
SLICE_X67Y94 FDRE f u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/_zz_ram_port1_reg[12]/D
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock mlkem_clk rise edge)
|
|
0.000 0.000 r
|
|
clock source latency -1.848 -1.848
|
|
propagated clock network latency
|
|
1.232 -0.616
|
|
|
|
Slack: inf
|
|
Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/ram_reg_0_7_24_29/RAMA_D1/CLK
|
|
(rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/_zz_ram_port1_reg[25]/D
|
|
(rising edge-triggered cell FDRE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns})
|
|
Path Group: (none)
|
|
Path Type: Setup (Max at Fast Process Corner)
|
|
Data Path Delay: 0.927ns (logic 0.595ns (64.162%) route 0.332ns (35.838%))
|
|
Logic Levels: 0
|
|
Clock Path Skew: -0.225ns (DCD - SCD + CPR)
|
|
Destination Clock Delay (DCD): -0.613ns
|
|
Source Clock Delay (SCD): -0.388ns
|
|
Clock Pessimism Removal (CPR): 0.000ns
|
|
Clock Uncertainty: 0.222ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Discrete Jitter (DJ): 0.192ns
|
|
Phase Error (PE): 0.120ns
|
|
Timing Exception: Asynchronous Clock Groups
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock sys_clk rise edge) 0.000 0.000 r
|
|
clock source latency -1.947 -1.947
|
|
propagated clock network latency
|
|
1.559 -0.388
|
|
SLICE_X44Y81 RAMD32 0.000 -0.388 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/ram_reg_0_7_24_29/RAMA_D1/CLK
|
|
SLICE_X44Y81 RAMD32 (Prop_ramd32_CLK_O)
|
|
0.595 0.207 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/ram_reg_0_7_24_29/RAMA_D1/O
|
|
net (fo=1, routed) 0.332 0.539 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/_zz_ram_port10__0[25]
|
|
SLICE_X45Y83 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/_zz_ram_port1_reg[25]/D
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock mlkem_clk rise edge)
|
|
0.000 0.000 r
|
|
clock source latency -1.848 -1.848
|
|
propagated clock network latency
|
|
1.235 -0.613
|
|
|
|
Slack: inf
|
|
Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/ram_reg_0_7_24_29/RAMA_D1/CLK
|
|
(rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/_zz_ram_port1_reg[25]/D
|
|
(rising edge-triggered cell FDRE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns})
|
|
Path Group: (none)
|
|
Path Type: Setup (Max at Fast Process Corner)
|
|
Data Path Delay: 0.927ns (logic 0.595ns (64.162%) route 0.332ns (35.838%))
|
|
Logic Levels: 0
|
|
Clock Path Skew: -0.225ns (DCD - SCD + CPR)
|
|
Destination Clock Delay (DCD): -0.613ns
|
|
Source Clock Delay (SCD): -0.388ns
|
|
Clock Pessimism Removal (CPR): 0.000ns
|
|
Clock Uncertainty: 0.222ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Discrete Jitter (DJ): 0.192ns
|
|
Phase Error (PE): 0.120ns
|
|
Timing Exception: Asynchronous Clock Groups
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock sys_clk rise edge) 0.000 0.000 r
|
|
clock source latency -1.947 -1.947
|
|
propagated clock network latency
|
|
1.559 -0.388
|
|
SLICE_X44Y81 RAMD32 0.000 -0.388 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/ram_reg_0_7_24_29/RAMA_D1/CLK
|
|
SLICE_X44Y81 RAMD32 (Prop_ramd32_CLK_O)
|
|
0.595 0.207 f u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/ram_reg_0_7_24_29/RAMA_D1/O
|
|
net (fo=1, routed) 0.332 0.539 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/_zz_ram_port10__0[25]
|
|
SLICE_X45Y83 FDRE f u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/_zz_ram_port1_reg[25]/D
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock mlkem_clk rise edge)
|
|
0.000 0.000 r
|
|
clock source latency -1.848 -1.848
|
|
propagated clock network latency
|
|
1.235 -0.613
|
|
|
|
Slack: inf
|
|
Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/ram_reg_0_7_6_11/RAMA_D1/CLK
|
|
(rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/_zz_ram_port1_reg[7]/D
|
|
(rising edge-triggered cell FDRE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns})
|
|
Path Group: (none)
|
|
Path Type: Setup (Max at Fast Process Corner)
|
|
Data Path Delay: 0.925ns (logic 0.595ns (64.303%) route 0.330ns (35.697%))
|
|
Logic Levels: 0
|
|
Clock Path Skew: -0.224ns (DCD - SCD + CPR)
|
|
Destination Clock Delay (DCD): -0.615ns
|
|
Source Clock Delay (SCD): -0.391ns
|
|
Clock Pessimism Removal (CPR): 0.000ns
|
|
Clock Uncertainty: 0.222ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Discrete Jitter (DJ): 0.192ns
|
|
Phase Error (PE): 0.120ns
|
|
Timing Exception: Asynchronous Clock Groups
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock sys_clk rise edge) 0.000 0.000 r
|
|
clock source latency -1.947 -1.947
|
|
propagated clock network latency
|
|
1.556 -0.391
|
|
SLICE_X46Y79 RAMD32 0.000 -0.391 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/ram_reg_0_7_6_11/RAMA_D1/CLK
|
|
SLICE_X46Y79 RAMD32 (Prop_ramd32_CLK_O)
|
|
0.595 0.204 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/ram_reg_0_7_6_11/RAMA_D1/O
|
|
net (fo=1, routed) 0.330 0.534 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/_zz_ram_port10__0[7]
|
|
SLICE_X51Y81 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/_zz_ram_port1_reg[7]/D
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock mlkem_clk rise edge)
|
|
0.000 0.000 r
|
|
clock source latency -1.848 -1.848
|
|
propagated clock network latency
|
|
1.233 -0.615
|
|
|
|
Slack: inf
|
|
Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/ram_reg_0_7_6_11/RAMA_D1/CLK
|
|
(rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/_zz_ram_port1_reg[7]/D
|
|
(rising edge-triggered cell FDRE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns})
|
|
Path Group: (none)
|
|
Path Type: Setup (Max at Fast Process Corner)
|
|
Data Path Delay: 0.925ns (logic 0.595ns (64.303%) route 0.330ns (35.697%))
|
|
Logic Levels: 0
|
|
Clock Path Skew: -0.224ns (DCD - SCD + CPR)
|
|
Destination Clock Delay (DCD): -0.615ns
|
|
Source Clock Delay (SCD): -0.391ns
|
|
Clock Pessimism Removal (CPR): 0.000ns
|
|
Clock Uncertainty: 0.222ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Discrete Jitter (DJ): 0.192ns
|
|
Phase Error (PE): 0.120ns
|
|
Timing Exception: Asynchronous Clock Groups
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock sys_clk rise edge) 0.000 0.000 r
|
|
clock source latency -1.947 -1.947
|
|
propagated clock network latency
|
|
1.556 -0.391
|
|
SLICE_X46Y79 RAMD32 0.000 -0.391 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/ram_reg_0_7_6_11/RAMA_D1/CLK
|
|
SLICE_X46Y79 RAMD32 (Prop_ramd32_CLK_O)
|
|
0.595 0.204 f u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/ram_reg_0_7_6_11/RAMA_D1/O
|
|
net (fo=1, routed) 0.330 0.534 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/_zz_ram_port10__0[7]
|
|
SLICE_X51Y81 FDRE f u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/_zz_ram_port1_reg[7]/D
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock mlkem_clk rise edge)
|
|
0.000 0.000 r
|
|
clock source latency -1.848 -1.848
|
|
propagated clock network latency
|
|
1.233 -0.615
|
|
|
|
Slack: inf
|
|
Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_6_11/RAMA_D1/CLK
|
|
(rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/_zz_ram_port1_reg[7]/D
|
|
(rising edge-triggered cell FDRE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns})
|
|
Path Group: (none)
|
|
Path Type: Setup (Max at Fast Process Corner)
|
|
Data Path Delay: 0.919ns (logic 0.595ns (64.745%) route 0.324ns (35.255%))
|
|
Logic Levels: 0
|
|
Clock Path Skew: -0.231ns (DCD - SCD + CPR)
|
|
Destination Clock Delay (DCD): -0.616ns
|
|
Source Clock Delay (SCD): -0.385ns
|
|
Clock Pessimism Removal (CPR): 0.000ns
|
|
Clock Uncertainty: 0.222ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Discrete Jitter (DJ): 0.192ns
|
|
Phase Error (PE): 0.120ns
|
|
Timing Exception: Asynchronous Clock Groups
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock sys_clk rise edge) 0.000 0.000 r
|
|
clock source latency -1.947 -1.947
|
|
propagated clock network latency
|
|
1.562 -0.385
|
|
SLICE_X64Y93 RAMD32 0.000 -0.385 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_6_11/RAMA_D1/CLK
|
|
SLICE_X64Y93 RAMD32 (Prop_ramd32_CLK_O)
|
|
0.595 0.210 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_6_11/RAMA_D1/O
|
|
net (fo=1, routed) 0.324 0.534 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/_zz_ram_port10__2[7]
|
|
SLICE_X67Y93 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/_zz_ram_port1_reg[7]/D
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock mlkem_clk rise edge)
|
|
0.000 0.000 r
|
|
clock source latency -1.848 -1.848
|
|
propagated clock network latency
|
|
1.232 -0.616
|
|
|
|
Slack: inf
|
|
Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_6_11/RAMA_D1/CLK
|
|
(rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/_zz_ram_port1_reg[7]/D
|
|
(rising edge-triggered cell FDRE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns})
|
|
Path Group: (none)
|
|
Path Type: Setup (Max at Fast Process Corner)
|
|
Data Path Delay: 0.919ns (logic 0.595ns (64.745%) route 0.324ns (35.255%))
|
|
Logic Levels: 0
|
|
Clock Path Skew: -0.231ns (DCD - SCD + CPR)
|
|
Destination Clock Delay (DCD): -0.616ns
|
|
Source Clock Delay (SCD): -0.385ns
|
|
Clock Pessimism Removal (CPR): 0.000ns
|
|
Clock Uncertainty: 0.222ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Discrete Jitter (DJ): 0.192ns
|
|
Phase Error (PE): 0.120ns
|
|
Timing Exception: Asynchronous Clock Groups
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock sys_clk rise edge) 0.000 0.000 r
|
|
clock source latency -1.947 -1.947
|
|
propagated clock network latency
|
|
1.562 -0.385
|
|
SLICE_X64Y93 RAMD32 0.000 -0.385 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_6_11/RAMA_D1/CLK
|
|
SLICE_X64Y93 RAMD32 (Prop_ramd32_CLK_O)
|
|
0.595 0.210 f u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_6_11/RAMA_D1/O
|
|
net (fo=1, routed) 0.324 0.534 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/_zz_ram_port10__2[7]
|
|
SLICE_X67Y93 FDRE f u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/_zz_ram_port1_reg[7]/D
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock mlkem_clk rise edge)
|
|
0.000 0.000 r
|
|
clock source latency -1.848 -1.848
|
|
propagated clock network latency
|
|
1.232 -0.616
|
|
|
|
Slack: inf
|
|
Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_42_47/RAMA/CLK
|
|
(rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/_zz_ram_port1_reg[42]/D
|
|
(rising edge-triggered cell FDRE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns})
|
|
Path Group: (none)
|
|
Path Type: Setup (Max at Fast Process Corner)
|
|
Data Path Delay: 0.908ns (logic 0.612ns (67.424%) route 0.296ns (32.576%))
|
|
Logic Levels: 0
|
|
Clock Path Skew: -0.229ns (DCD - SCD + CPR)
|
|
Destination Clock Delay (DCD): -0.616ns
|
|
Source Clock Delay (SCD): -0.387ns
|
|
Clock Pessimism Removal (CPR): 0.000ns
|
|
Clock Uncertainty: 0.222ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Discrete Jitter (DJ): 0.192ns
|
|
Phase Error (PE): 0.120ns
|
|
Timing Exception: Asynchronous Clock Groups
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock sys_clk rise edge) 0.000 0.000 r
|
|
clock source latency -1.947 -1.947
|
|
propagated clock network latency
|
|
1.560 -0.387
|
|
SLICE_X70Y98 RAMD32 0.000 -0.387 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_42_47/RAMA/CLK
|
|
SLICE_X70Y98 RAMD32 (Prop_ramd32_CLK_O)
|
|
0.612 0.225 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_42_47/RAMA/O
|
|
net (fo=1, routed) 0.296 0.521 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/_zz_ram_port10__2[42]
|
|
SLICE_X72Y97 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/_zz_ram_port1_reg[42]/D
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock mlkem_clk rise edge)
|
|
0.000 0.000 r
|
|
clock source latency -1.848 -1.848
|
|
propagated clock network latency
|
|
1.232 -0.616
|
|
|
|
Slack: inf
|
|
Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_42_47/RAMA/CLK
|
|
(rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/_zz_ram_port1_reg[42]/D
|
|
(rising edge-triggered cell FDRE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns})
|
|
Path Group: (none)
|
|
Path Type: Setup (Max at Fast Process Corner)
|
|
Data Path Delay: 0.908ns (logic 0.612ns (67.424%) route 0.296ns (32.576%))
|
|
Logic Levels: 0
|
|
Clock Path Skew: -0.229ns (DCD - SCD + CPR)
|
|
Destination Clock Delay (DCD): -0.616ns
|
|
Source Clock Delay (SCD): -0.387ns
|
|
Clock Pessimism Removal (CPR): 0.000ns
|
|
Clock Uncertainty: 0.222ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Discrete Jitter (DJ): 0.192ns
|
|
Phase Error (PE): 0.120ns
|
|
Timing Exception: Asynchronous Clock Groups
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock sys_clk rise edge) 0.000 0.000 r
|
|
clock source latency -1.947 -1.947
|
|
propagated clock network latency
|
|
1.560 -0.387
|
|
SLICE_X70Y98 RAMD32 0.000 -0.387 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_42_47/RAMA/CLK
|
|
SLICE_X70Y98 RAMD32 (Prop_ramd32_CLK_O)
|
|
0.612 0.225 f u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_42_47/RAMA/O
|
|
net (fo=1, routed) 0.296 0.521 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/_zz_ram_port10__2[42]
|
|
SLICE_X72Y97 FDRE f u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/_zz_ram_port1_reg[42]/D
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock mlkem_clk rise edge)
|
|
0.000 0.000 r
|
|
clock source latency -1.848 -1.848
|
|
propagated clock network latency
|
|
1.232 -0.616
|
|
|
|
Slack: inf
|
|
Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/ram_reg_0_7_6_11/RAMA/CLK
|
|
(rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/_zz_ram_port1_reg[6]/D
|
|
(rising edge-triggered cell FDRE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns})
|
|
Path Group: (none)
|
|
Path Type: Setup (Max at Fast Process Corner)
|
|
Data Path Delay: 0.911ns (logic 0.612ns (67.168%) route 0.299ns (32.832%))
|
|
Logic Levels: 0
|
|
Clock Path Skew: -0.224ns (DCD - SCD + CPR)
|
|
Destination Clock Delay (DCD): -0.615ns
|
|
Source Clock Delay (SCD): -0.391ns
|
|
Clock Pessimism Removal (CPR): 0.000ns
|
|
Clock Uncertainty: 0.222ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Discrete Jitter (DJ): 0.192ns
|
|
Phase Error (PE): 0.120ns
|
|
Timing Exception: Asynchronous Clock Groups
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock sys_clk rise edge) 0.000 0.000 r
|
|
clock source latency -1.947 -1.947
|
|
propagated clock network latency
|
|
1.556 -0.391
|
|
SLICE_X46Y79 RAMD32 0.000 -0.391 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/ram_reg_0_7_6_11/RAMA/CLK
|
|
SLICE_X46Y79 RAMD32 (Prop_ramd32_CLK_O)
|
|
0.612 0.221 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/ram_reg_0_7_6_11/RAMA/O
|
|
net (fo=1, routed) 0.299 0.520 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/_zz_ram_port10__0[6]
|
|
SLICE_X49Y81 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/_zz_ram_port1_reg[6]/D
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock mlkem_clk rise edge)
|
|
0.000 0.000 r
|
|
clock source latency -1.848 -1.848
|
|
propagated clock network latency
|
|
1.233 -0.615
|
|
|
|
Slack: inf
|
|
Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/ram_reg_0_7_6_11/RAMA/CLK
|
|
(rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/_zz_ram_port1_reg[6]/D
|
|
(rising edge-triggered cell FDRE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns})
|
|
Path Group: (none)
|
|
Path Type: Setup (Max at Fast Process Corner)
|
|
Data Path Delay: 0.911ns (logic 0.612ns (67.168%) route 0.299ns (32.832%))
|
|
Logic Levels: 0
|
|
Clock Path Skew: -0.224ns (DCD - SCD + CPR)
|
|
Destination Clock Delay (DCD): -0.615ns
|
|
Source Clock Delay (SCD): -0.391ns
|
|
Clock Pessimism Removal (CPR): 0.000ns
|
|
Clock Uncertainty: 0.222ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Discrete Jitter (DJ): 0.192ns
|
|
Phase Error (PE): 0.120ns
|
|
Timing Exception: Asynchronous Clock Groups
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock sys_clk rise edge) 0.000 0.000 r
|
|
clock source latency -1.947 -1.947
|
|
propagated clock network latency
|
|
1.556 -0.391
|
|
SLICE_X46Y79 RAMD32 0.000 -0.391 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/ram_reg_0_7_6_11/RAMA/CLK
|
|
SLICE_X46Y79 RAMD32 (Prop_ramd32_CLK_O)
|
|
0.612 0.221 f u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/ram_reg_0_7_6_11/RAMA/O
|
|
net (fo=1, routed) 0.299 0.520 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/_zz_ram_port10__0[6]
|
|
SLICE_X49Y81 FDRE f u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/_zz_ram_port1_reg[6]/D
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock mlkem_clk rise edge)
|
|
0.000 0.000 r
|
|
clock source latency -1.848 -1.848
|
|
propagated clock network latency
|
|
1.233 -0.615
|
|
|
|
Slack: inf
|
|
Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/ram_reg_0_3_0_5/RAMB_D1/CLK
|
|
(rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/_zz_ram_port1_reg[3]/D
|
|
(rising edge-triggered cell FDRE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns})
|
|
Path Group: (none)
|
|
Path Type: Setup (Max at Fast Process Corner)
|
|
Data Path Delay: 0.889ns (logic 0.482ns (54.189%) route 0.407ns (45.811%))
|
|
Logic Levels: 0
|
|
Clock Path Skew: -0.227ns (DCD - SCD + CPR)
|
|
Destination Clock Delay (DCD): -0.613ns
|
|
Source Clock Delay (SCD): -0.386ns
|
|
Clock Pessimism Removal (CPR): 0.000ns
|
|
Clock Uncertainty: 0.222ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Discrete Jitter (DJ): 0.192ns
|
|
Phase Error (PE): 0.120ns
|
|
Timing Exception: Asynchronous Clock Groups
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock sys_clk rise edge) 0.000 0.000 r
|
|
clock source latency -1.947 -1.947
|
|
propagated clock network latency
|
|
1.561 -0.386
|
|
SLICE_X52Y84 RAMD32 0.000 -0.386 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/ram_reg_0_3_0_5/RAMB_D1/CLK
|
|
SLICE_X52Y84 RAMD32 (Prop_ramd32_CLK_O)
|
|
0.482 0.096 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/ram_reg_0_3_0_5/RAMB_D1/O
|
|
net (fo=1, routed) 0.407 0.503 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/_zz_ram_port10[3]
|
|
SLICE_X54Y85 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/_zz_ram_port1_reg[3]/D
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock mlkem_clk rise edge)
|
|
0.000 0.000 r
|
|
clock source latency -1.848 -1.848
|
|
propagated clock network latency
|
|
1.235 -0.613
|
|
|
|
Slack: inf
|
|
Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/ram_reg_0_3_0_5/RAMB_D1/CLK
|
|
(rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/_zz_ram_port1_reg[3]/D
|
|
(rising edge-triggered cell FDRE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns})
|
|
Path Group: (none)
|
|
Path Type: Setup (Max at Fast Process Corner)
|
|
Data Path Delay: 0.889ns (logic 0.482ns (54.189%) route 0.407ns (45.811%))
|
|
Logic Levels: 0
|
|
Clock Path Skew: -0.227ns (DCD - SCD + CPR)
|
|
Destination Clock Delay (DCD): -0.613ns
|
|
Source Clock Delay (SCD): -0.386ns
|
|
Clock Pessimism Removal (CPR): 0.000ns
|
|
Clock Uncertainty: 0.222ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Discrete Jitter (DJ): 0.192ns
|
|
Phase Error (PE): 0.120ns
|
|
Timing Exception: Asynchronous Clock Groups
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock sys_clk rise edge) 0.000 0.000 r
|
|
clock source latency -1.947 -1.947
|
|
propagated clock network latency
|
|
1.561 -0.386
|
|
SLICE_X52Y84 RAMD32 0.000 -0.386 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/ram_reg_0_3_0_5/RAMB_D1/CLK
|
|
SLICE_X52Y84 RAMD32 (Prop_ramd32_CLK_O)
|
|
0.482 0.096 f u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/ram_reg_0_3_0_5/RAMB_D1/O
|
|
net (fo=1, routed) 0.407 0.503 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/_zz_ram_port10[3]
|
|
SLICE_X54Y85 FDRE f u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/_zz_ram_port1_reg[3]/D
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock mlkem_clk rise edge)
|
|
0.000 0.000 r
|
|
clock source latency -1.848 -1.848
|
|
propagated clock network latency
|
|
1.235 -0.613
|
|
|
|
Slack: inf
|
|
Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/ram_reg_0_3_12_17/RAMA_D1/CLK
|
|
(rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/_zz_ram_port1_reg[13]/D
|
|
(rising edge-triggered cell FDRE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns})
|
|
Path Group: (none)
|
|
Path Type: Setup (Max at Fast Process Corner)
|
|
Data Path Delay: 0.866ns (logic 0.595ns (68.739%) route 0.271ns (31.261%))
|
|
Logic Levels: 0
|
|
Clock Path Skew: -0.228ns (DCD - SCD + CPR)
|
|
Destination Clock Delay (DCD): -0.613ns
|
|
Source Clock Delay (SCD): -0.385ns
|
|
Clock Pessimism Removal (CPR): 0.000ns
|
|
Clock Uncertainty: 0.222ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Discrete Jitter (DJ): 0.192ns
|
|
Phase Error (PE): 0.120ns
|
|
Timing Exception: Asynchronous Clock Groups
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock sys_clk rise edge) 0.000 0.000 r
|
|
clock source latency -1.947 -1.947
|
|
propagated clock network latency
|
|
1.562 -0.385
|
|
SLICE_X52Y85 RAMD32 0.000 -0.385 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/ram_reg_0_3_12_17/RAMA_D1/CLK
|
|
SLICE_X52Y85 RAMD32 (Prop_ramd32_CLK_O)
|
|
0.595 0.210 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/ram_reg_0_3_12_17/RAMA_D1/O
|
|
net (fo=1, routed) 0.271 0.480 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/_zz_ram_port10[13]
|
|
SLICE_X54Y86 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/_zz_ram_port1_reg[13]/D
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock mlkem_clk rise edge)
|
|
0.000 0.000 r
|
|
clock source latency -1.848 -1.848
|
|
propagated clock network latency
|
|
1.235 -0.613
|
|
|
|
Slack: inf
|
|
Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/ram_reg_0_3_12_17/RAMA_D1/CLK
|
|
(rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/_zz_ram_port1_reg[13]/D
|
|
(rising edge-triggered cell FDRE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns})
|
|
Path Group: (none)
|
|
Path Type: Setup (Max at Fast Process Corner)
|
|
Data Path Delay: 0.866ns (logic 0.595ns (68.739%) route 0.271ns (31.261%))
|
|
Logic Levels: 0
|
|
Clock Path Skew: -0.228ns (DCD - SCD + CPR)
|
|
Destination Clock Delay (DCD): -0.613ns
|
|
Source Clock Delay (SCD): -0.385ns
|
|
Clock Pessimism Removal (CPR): 0.000ns
|
|
Clock Uncertainty: 0.222ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Discrete Jitter (DJ): 0.192ns
|
|
Phase Error (PE): 0.120ns
|
|
Timing Exception: Asynchronous Clock Groups
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock sys_clk rise edge) 0.000 0.000 r
|
|
clock source latency -1.947 -1.947
|
|
propagated clock network latency
|
|
1.562 -0.385
|
|
SLICE_X52Y85 RAMD32 0.000 -0.385 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/ram_reg_0_3_12_17/RAMA_D1/CLK
|
|
SLICE_X52Y85 RAMD32 (Prop_ramd32_CLK_O)
|
|
0.595 0.210 f u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/ram_reg_0_3_12_17/RAMA_D1/O
|
|
net (fo=1, routed) 0.271 0.480 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/_zz_ram_port10[13]
|
|
SLICE_X54Y86 FDRE f u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/_zz_ram_port1_reg[13]/D
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock mlkem_clk rise edge)
|
|
0.000 0.000 r
|
|
clock source latency -1.848 -1.848
|
|
propagated clock network latency
|
|
1.235 -0.613
|
|
|
|
Slack: inf
|
|
Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/ram_reg_0_3_6_11/RAMC_D1/CLK
|
|
(rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/_zz_ram_port1_reg[11]/D
|
|
(rising edge-triggered cell FDRE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns})
|
|
Path Group: (none)
|
|
Path Type: Setup (Max at Fast Process Corner)
|
|
Data Path Delay: 0.858ns (logic 0.480ns (55.963%) route 0.378ns (44.037%))
|
|
Logic Levels: 0
|
|
Clock Path Skew: -0.226ns (DCD - SCD + CPR)
|
|
Destination Clock Delay (DCD): -0.613ns
|
|
Source Clock Delay (SCD): -0.387ns
|
|
Clock Pessimism Removal (CPR): 0.000ns
|
|
Clock Uncertainty: 0.222ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Discrete Jitter (DJ): 0.192ns
|
|
Phase Error (PE): 0.120ns
|
|
Timing Exception: Asynchronous Clock Groups
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock sys_clk rise edge) 0.000 0.000 r
|
|
clock source latency -1.947 -1.947
|
|
propagated clock network latency
|
|
1.560 -0.387
|
|
SLICE_X52Y83 RAMD32 0.000 -0.387 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/ram_reg_0_3_6_11/RAMC_D1/CLK
|
|
SLICE_X52Y83 RAMD32 (Prop_ramd32_CLK_O)
|
|
0.480 0.093 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/ram_reg_0_3_6_11/RAMC_D1/O
|
|
net (fo=1, routed) 0.378 0.471 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/_zz_ram_port10[11]
|
|
SLICE_X54Y85 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/_zz_ram_port1_reg[11]/D
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock mlkem_clk rise edge)
|
|
0.000 0.000 r
|
|
clock source latency -1.848 -1.848
|
|
propagated clock network latency
|
|
1.235 -0.613
|
|
|
|
Slack: inf
|
|
Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/ram_reg_0_3_6_11/RAMC_D1/CLK
|
|
(rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/_zz_ram_port1_reg[11]/D
|
|
(rising edge-triggered cell FDRE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns})
|
|
Path Group: (none)
|
|
Path Type: Setup (Max at Fast Process Corner)
|
|
Data Path Delay: 0.858ns (logic 0.480ns (55.963%) route 0.378ns (44.037%))
|
|
Logic Levels: 0
|
|
Clock Path Skew: -0.226ns (DCD - SCD + CPR)
|
|
Destination Clock Delay (DCD): -0.613ns
|
|
Source Clock Delay (SCD): -0.387ns
|
|
Clock Pessimism Removal (CPR): 0.000ns
|
|
Clock Uncertainty: 0.222ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Discrete Jitter (DJ): 0.192ns
|
|
Phase Error (PE): 0.120ns
|
|
Timing Exception: Asynchronous Clock Groups
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock sys_clk rise edge) 0.000 0.000 r
|
|
clock source latency -1.947 -1.947
|
|
propagated clock network latency
|
|
1.560 -0.387
|
|
SLICE_X52Y83 RAMD32 0.000 -0.387 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/ram_reg_0_3_6_11/RAMC_D1/CLK
|
|
SLICE_X52Y83 RAMD32 (Prop_ramd32_CLK_O)
|
|
0.480 0.093 f u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/ram_reg_0_3_6_11/RAMC_D1/O
|
|
net (fo=1, routed) 0.378 0.471 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/_zz_ram_port10[11]
|
|
SLICE_X54Y85 FDRE f u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/_zz_ram_port1_reg[11]/D
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock mlkem_clk rise edge)
|
|
0.000 0.000 r
|
|
clock source latency -1.848 -1.848
|
|
propagated clock network latency
|
|
1.235 -0.613
|
|
|
|
Slack: inf
|
|
Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_6_11/RAMA/CLK
|
|
(rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/_zz_ram_port1_reg[6]/D
|
|
(rising edge-triggered cell FDRE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns})
|
|
Path Group: (none)
|
|
Path Type: Setup (Max at Fast Process Corner)
|
|
Data Path Delay: 0.849ns (logic 0.612ns (72.044%) route 0.237ns (27.956%))
|
|
Logic Levels: 0
|
|
Clock Path Skew: -0.229ns (DCD - SCD + CPR)
|
|
Destination Clock Delay (DCD): -0.614ns
|
|
Source Clock Delay (SCD): -0.385ns
|
|
Clock Pessimism Removal (CPR): 0.000ns
|
|
Clock Uncertainty: 0.222ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Discrete Jitter (DJ): 0.192ns
|
|
Phase Error (PE): 0.120ns
|
|
Timing Exception: Asynchronous Clock Groups
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock sys_clk rise edge) 0.000 0.000 r
|
|
clock source latency -1.947 -1.947
|
|
propagated clock network latency
|
|
1.562 -0.385
|
|
SLICE_X64Y93 RAMD32 0.000 -0.385 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_6_11/RAMA/CLK
|
|
SLICE_X64Y93 RAMD32 (Prop_ramd32_CLK_O)
|
|
0.612 0.227 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_6_11/RAMA/O
|
|
net (fo=1, routed) 0.237 0.464 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/_zz_ram_port10__2[6]
|
|
SLICE_X65Y93 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/_zz_ram_port1_reg[6]/D
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock mlkem_clk rise edge)
|
|
0.000 0.000 r
|
|
clock source latency -1.848 -1.848
|
|
propagated clock network latency
|
|
1.234 -0.614
|
|
|
|
Slack: inf
|
|
Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_6_11/RAMA/CLK
|
|
(rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/_zz_ram_port1_reg[6]/D
|
|
(rising edge-triggered cell FDRE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns})
|
|
Path Group: (none)
|
|
Path Type: Setup (Max at Fast Process Corner)
|
|
Data Path Delay: 0.849ns (logic 0.612ns (72.044%) route 0.237ns (27.956%))
|
|
Logic Levels: 0
|
|
Clock Path Skew: -0.229ns (DCD - SCD + CPR)
|
|
Destination Clock Delay (DCD): -0.614ns
|
|
Source Clock Delay (SCD): -0.385ns
|
|
Clock Pessimism Removal (CPR): 0.000ns
|
|
Clock Uncertainty: 0.222ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Discrete Jitter (DJ): 0.192ns
|
|
Phase Error (PE): 0.120ns
|
|
Timing Exception: Asynchronous Clock Groups
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock sys_clk rise edge) 0.000 0.000 r
|
|
clock source latency -1.947 -1.947
|
|
propagated clock network latency
|
|
1.562 -0.385
|
|
SLICE_X64Y93 RAMD32 0.000 -0.385 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_6_11/RAMA/CLK
|
|
SLICE_X64Y93 RAMD32 (Prop_ramd32_CLK_O)
|
|
0.612 0.227 f u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_6_11/RAMA/O
|
|
net (fo=1, routed) 0.237 0.464 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/_zz_ram_port10__2[6]
|
|
SLICE_X65Y93 FDRE f u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/_zz_ram_port1_reg[6]/D
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock mlkem_clk rise edge)
|
|
0.000 0.000 r
|
|
clock source latency -1.848 -1.848
|
|
propagated clock network latency
|
|
1.234 -0.614
|
|
|
|
|
|
|
|
|