1925 lines
131 KiB
Plaintext
1925 lines
131 KiB
Plaintext
Copyright 1986-2019 Xilinx, Inc. All Rights Reserved.
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| Tool Version : Vivado v.2019.2 (lin64) Build 2708876 Wed Nov 6 21:39:14 MST 2019
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| Date : Sat Jul 11 09:20:56 2026
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| Host : fedora running 64-bit unknown
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| Command : report_timing -from [get_clocks mlkem_clk] -to [get_clocks sys_clk] -delay_type max -max_paths 50 -nworst 10 -path_type full -input_pins -file /home/fallensigh/Dev/ciciec2026_loongson_regional/fpga/vivado_reports_nodsp/cdc_mlkem_to_sys.rpt
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| Design : soc_top
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| Device : 7a200t-fbg676
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| Speed File : -1 PRODUCTION 1.23 2018-06-13
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Timing Report
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Slack: inf
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Source: pll_clk.u_rst_mlkem/delay_reg[1]/C
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(rising edge-triggered cell FDCE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns})
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Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/buffers_0_reg/CLR
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(recovery check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
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Path Group: (none)
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Path Type: Recovery (Max at Slow Process Corner)
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Data Path Delay: 5.746ns (logic 0.642ns (11.174%) route 5.104ns (88.826%))
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Logic Levels: 1 (LUT1=1)
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Clock Path Skew: 0.546ns (DCD - SCD + CPR)
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Destination Clock Delay (DCD): -2.123ns
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Source Clock Delay (SCD): -2.670ns
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Clock Pessimism Removal (CPR): 0.000ns
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Clock Uncertainty: 0.222ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
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Total System Jitter (TSJ): 0.071ns
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Discrete Jitter (DJ): 0.192ns
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Phase Error (PE): 0.120ns
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Timing Exception: Asynchronous Clock Groups
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Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
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------------------------------------------------------------------- -------------------
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(clock mlkem_clk rise edge)
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0.000 0.000 r
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clock source latency -6.275 -6.275
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propagated clock network latency
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3.606 -2.670
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SLICE_X92Y102 FDCE 0.000 -2.670 r pll_clk.u_rst_mlkem/delay_reg[1]/C
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SLICE_X92Y102 FDCE (Prop_fdce_C_Q) 0.518 -2.152 r pll_clk.u_rst_mlkem/delay_reg[1]/Q
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net (fo=4, routed) 2.430 0.278 pll_clk.u_rst_mlkem/Q[0]
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SLICE_X55Y88 r pll_clk.u_rst_mlkem/w_state[2]_i_2/I0
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SLICE_X55Y88 LUT1 (Prop_lut1_I0_O) 0.124 0.402 f pll_clk.u_rst_mlkem/w_state[2]_i_2/O
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net (fo=1066, routed) 2.674 3.076 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/buffers_1_reg_1
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SLICE_X67Y87 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/buffers_0_reg/CLR
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------------------------------------------------------------------- -------------------
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(clock sys_clk rise edge) 0.000 0.000 r
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clock source latency -5.674 -5.674
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propagated clock network latency
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3.551 -2.123
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Slack: inf
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Source: pll_clk.u_rst_mlkem/delay_reg[1]/C
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(rising edge-triggered cell FDCE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns})
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Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/buffers_1_reg/CLR
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(recovery check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
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Path Group: (none)
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Path Type: Recovery (Max at Slow Process Corner)
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Data Path Delay: 5.746ns (logic 0.642ns (11.174%) route 5.104ns (88.826%))
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Logic Levels: 1 (LUT1=1)
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Clock Path Skew: 0.546ns (DCD - SCD + CPR)
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Destination Clock Delay (DCD): -2.123ns
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Source Clock Delay (SCD): -2.670ns
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Clock Pessimism Removal (CPR): 0.000ns
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Clock Uncertainty: 0.222ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
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Total System Jitter (TSJ): 0.071ns
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Discrete Jitter (DJ): 0.192ns
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Phase Error (PE): 0.120ns
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Timing Exception: Asynchronous Clock Groups
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Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
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------------------------------------------------------------------- -------------------
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(clock mlkem_clk rise edge)
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0.000 0.000 r
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clock source latency -6.275 -6.275
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propagated clock network latency
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3.606 -2.670
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SLICE_X92Y102 FDCE 0.000 -2.670 r pll_clk.u_rst_mlkem/delay_reg[1]/C
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SLICE_X92Y102 FDCE (Prop_fdce_C_Q) 0.518 -2.152 r pll_clk.u_rst_mlkem/delay_reg[1]/Q
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net (fo=4, routed) 2.430 0.278 pll_clk.u_rst_mlkem/Q[0]
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SLICE_X55Y88 r pll_clk.u_rst_mlkem/w_state[2]_i_2/I0
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SLICE_X55Y88 LUT1 (Prop_lut1_I0_O) 0.124 0.402 f pll_clk.u_rst_mlkem/w_state[2]_i_2/O
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net (fo=1066, routed) 2.674 3.076 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/buffers_1_reg_1
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SLICE_X67Y87 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/buffers_1_reg/CLR
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------------------------------------------------------------------- -------------------
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(clock sys_clk rise edge) 0.000 0.000 r
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clock source latency -5.674 -5.674
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propagated clock network latency
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3.551 -2.123
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Slack: inf
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Source: pll_clk.u_rst_mlkem/delay_reg[1]/C
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(rising edge-triggered cell FDCE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns})
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Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/buffers_0_reg/CLR
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(recovery check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
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Path Group: (none)
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Path Type: Recovery (Max at Fast Process Corner)
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Data Path Delay: 2.891ns (logic 0.260ns (8.995%) route 2.631ns (91.005%))
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Logic Levels: 1 (LUT1=1)
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Clock Path Skew: -0.164ns (DCD - SCD + CPR)
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Destination Clock Delay (DCD): -0.619ns
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Source Clock Delay (SCD): -0.455ns
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Clock Pessimism Removal (CPR): 0.000ns
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Clock Uncertainty: 0.222ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
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Total System Jitter (TSJ): 0.071ns
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Discrete Jitter (DJ): 0.192ns
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Phase Error (PE): 0.120ns
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Timing Exception: Asynchronous Clock Groups
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Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
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------------------------------------------------------------------- -------------------
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(clock mlkem_clk rise edge)
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0.000 0.000 r
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clock source latency -1.947 -1.947
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propagated clock network latency
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1.492 -0.455
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SLICE_X92Y102 FDCE 0.000 -0.455 r pll_clk.u_rst_mlkem/delay_reg[1]/C
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SLICE_X92Y102 FDCE (Prop_fdce_C_Q) 0.204 -0.251 r pll_clk.u_rst_mlkem/delay_reg[1]/Q
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net (fo=4, routed) 1.300 1.049 pll_clk.u_rst_mlkem/Q[0]
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SLICE_X55Y88 r pll_clk.u_rst_mlkem/w_state[2]_i_2/I0
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SLICE_X55Y88 LUT1 (Prop_lut1_I0_O) 0.056 1.105 f pll_clk.u_rst_mlkem/w_state[2]_i_2/O
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net (fo=1066, routed) 1.331 2.435 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/buffers_1_reg_1
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SLICE_X67Y87 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/buffers_0_reg/CLR
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------------------------------------------------------------------- -------------------
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(clock sys_clk rise edge) 0.000 0.000 r
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clock source latency -1.848 -1.848
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propagated clock network latency
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1.229 -0.619
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Slack: inf
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Source: pll_clk.u_rst_mlkem/delay_reg[1]/C
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(rising edge-triggered cell FDCE clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns})
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Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/buffers_1_reg/CLR
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(recovery check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
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Path Group: (none)
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Path Type: Recovery (Max at Fast Process Corner)
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Data Path Delay: 2.891ns (logic 0.260ns (8.995%) route 2.631ns (91.005%))
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Logic Levels: 1 (LUT1=1)
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Clock Path Skew: -0.164ns (DCD - SCD + CPR)
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Destination Clock Delay (DCD): -0.619ns
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Source Clock Delay (SCD): -0.455ns
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Clock Pessimism Removal (CPR): 0.000ns
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Clock Uncertainty: 0.222ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
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Total System Jitter (TSJ): 0.071ns
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Discrete Jitter (DJ): 0.192ns
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Phase Error (PE): 0.120ns
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Timing Exception: Asynchronous Clock Groups
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Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
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------------------------------------------------------------------- -------------------
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(clock mlkem_clk rise edge)
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0.000 0.000 r
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clock source latency -1.947 -1.947
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propagated clock network latency
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1.492 -0.455
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SLICE_X92Y102 FDCE 0.000 -0.455 r pll_clk.u_rst_mlkem/delay_reg[1]/C
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SLICE_X92Y102 FDCE (Prop_fdce_C_Q) 0.204 -0.251 r pll_clk.u_rst_mlkem/delay_reg[1]/Q
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net (fo=4, routed) 1.300 1.049 pll_clk.u_rst_mlkem/Q[0]
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SLICE_X55Y88 r pll_clk.u_rst_mlkem/w_state[2]_i_2/I0
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SLICE_X55Y88 LUT1 (Prop_lut1_I0_O) 0.056 1.105 f pll_clk.u_rst_mlkem/w_state[2]_i_2/O
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net (fo=1066, routed) 1.331 2.435 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/buffers_1_reg_1
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SLICE_X67Y87 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/buffers_1_reg/CLR
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------------------------------------------------------------------- -------------------
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(clock sys_clk rise edge) 0.000 0.000 r
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clock source latency -1.848 -1.848
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propagated clock network latency
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1.229 -0.619
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Slack: inf
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Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_30_35/RAMA/CLK
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(rising edge-triggered cell RAMD32 clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns})
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Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[30]/D
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(rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
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Path Group: (none)
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Path Type: Setup (Max at Fast Process Corner)
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Data Path Delay: 1.364ns (logic 0.612ns (44.884%) route 0.752ns (55.116%))
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Logic Levels: 0
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Clock Path Skew: -0.223ns (DCD - SCD + CPR)
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Destination Clock Delay (DCD): -0.609ns
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Source Clock Delay (SCD): -0.386ns
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Clock Pessimism Removal (CPR): 0.000ns
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Clock Uncertainty: 0.222ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
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Total System Jitter (TSJ): 0.071ns
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Discrete Jitter (DJ): 0.192ns
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Phase Error (PE): 0.120ns
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Timing Exception: Asynchronous Clock Groups
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Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
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------------------------------------------------------------------- -------------------
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(clock mlkem_clk rise edge)
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0.000 0.000 r
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clock source latency -1.947 -1.947
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propagated clock network latency
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1.561 -0.386
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SLICE_X64Y91 RAMD32 0.000 -0.386 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_30_35/RAMA/CLK
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SLICE_X64Y91 RAMD32 (Prop_ramd32_CLK_O)
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0.612 0.226 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_30_35/RAMA/O
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net (fo=1, routed) 0.752 0.977 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port10__3[30]
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SLICE_X46Y90 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[30]/D
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------------------------------------------------------------------- -------------------
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(clock sys_clk rise edge) 0.000 0.000 r
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clock source latency -1.848 -1.848
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propagated clock network latency
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1.239 -0.609
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Slack: inf
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Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_30_35/RAMA/CLK
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(rising edge-triggered cell RAMD32 clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns})
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Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[30]/D
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(rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
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Path Group: (none)
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Path Type: Setup (Max at Fast Process Corner)
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Data Path Delay: 1.364ns (logic 0.612ns (44.884%) route 0.752ns (55.116%))
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Logic Levels: 0
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Clock Path Skew: -0.223ns (DCD - SCD + CPR)
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Destination Clock Delay (DCD): -0.609ns
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Source Clock Delay (SCD): -0.386ns
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Clock Pessimism Removal (CPR): 0.000ns
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Clock Uncertainty: 0.222ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
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Total System Jitter (TSJ): 0.071ns
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Discrete Jitter (DJ): 0.192ns
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Phase Error (PE): 0.120ns
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Timing Exception: Asynchronous Clock Groups
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Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
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------------------------------------------------------------------- -------------------
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(clock mlkem_clk rise edge)
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0.000 0.000 r
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clock source latency -1.947 -1.947
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propagated clock network latency
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1.561 -0.386
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SLICE_X64Y91 RAMD32 0.000 -0.386 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_30_35/RAMA/CLK
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SLICE_X64Y91 RAMD32 (Prop_ramd32_CLK_O)
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0.612 0.226 f u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_30_35/RAMA/O
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net (fo=1, routed) 0.752 0.977 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port10__3[30]
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SLICE_X46Y90 FDRE f u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[30]/D
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------------------------------------------------------------------- -------------------
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(clock sys_clk rise edge) 0.000 0.000 r
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clock source latency -1.848 -1.848
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propagated clock network latency
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1.239 -0.609
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Slack: inf
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Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_0_5/RAMA/CLK
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(rising edge-triggered cell RAMD32 clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns})
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Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[0]/D
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(rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
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Path Group: (none)
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Path Type: Setup (Max at Fast Process Corner)
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Data Path Delay: 1.284ns (logic 0.612ns (47.657%) route 0.672ns (52.343%))
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Logic Levels: 0
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Clock Path Skew: -0.221ns (DCD - SCD + CPR)
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Destination Clock Delay (DCD): -0.610ns
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Source Clock Delay (SCD): -0.389ns
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Clock Pessimism Removal (CPR): 0.000ns
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Clock Uncertainty: 0.222ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
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Total System Jitter (TSJ): 0.071ns
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Discrete Jitter (DJ): 0.192ns
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Phase Error (PE): 0.120ns
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Timing Exception: Asynchronous Clock Groups
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Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
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------------------------------------------------------------------- -------------------
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(clock mlkem_clk rise edge)
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0.000 0.000 r
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clock source latency -1.947 -1.947
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propagated clock network latency
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1.558 -0.389
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SLICE_X68Y89 RAMD32 0.000 -0.389 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_0_5/RAMA/CLK
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SLICE_X68Y89 RAMD32 (Prop_ramd32_CLK_O)
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0.612 0.223 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_0_5/RAMA/O
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net (fo=1, routed) 0.672 0.895 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port10__3[0]
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SLICE_X49Y88 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[0]/D
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------------------------------------------------------------------- -------------------
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(clock sys_clk rise edge) 0.000 0.000 r
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clock source latency -1.848 -1.848
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propagated clock network latency
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1.238 -0.610
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Slack: inf
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Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_0_5/RAMA/CLK
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(rising edge-triggered cell RAMD32 clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns})
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Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[0]/D
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(rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
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Path Group: (none)
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Path Type: Setup (Max at Fast Process Corner)
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Data Path Delay: 1.284ns (logic 0.612ns (47.657%) route 0.672ns (52.343%))
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Logic Levels: 0
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Clock Path Skew: -0.221ns (DCD - SCD + CPR)
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Destination Clock Delay (DCD): -0.610ns
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Source Clock Delay (SCD): -0.389ns
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Clock Pessimism Removal (CPR): 0.000ns
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Clock Uncertainty: 0.222ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
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Total System Jitter (TSJ): 0.071ns
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Discrete Jitter (DJ): 0.192ns
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Phase Error (PE): 0.120ns
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Timing Exception: Asynchronous Clock Groups
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Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
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------------------------------------------------------------------- -------------------
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(clock mlkem_clk rise edge)
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0.000 0.000 r
|
|
clock source latency -1.947 -1.947
|
|
propagated clock network latency
|
|
1.558 -0.389
|
|
SLICE_X68Y89 RAMD32 0.000 -0.389 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_0_5/RAMA/CLK
|
|
SLICE_X68Y89 RAMD32 (Prop_ramd32_CLK_O)
|
|
0.612 0.223 f u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_0_5/RAMA/O
|
|
net (fo=1, routed) 0.672 0.895 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port10__3[0]
|
|
SLICE_X49Y88 FDRE f u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[0]/D
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock sys_clk rise edge) 0.000 0.000 r
|
|
clock source latency -1.848 -1.848
|
|
propagated clock network latency
|
|
1.238 -0.610
|
|
|
|
Slack: inf
|
|
Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_6_11/RAMA_D1/CLK
|
|
(rising edge-triggered cell RAMD32 clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns})
|
|
Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[7]/D
|
|
(rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Path Group: (none)
|
|
Path Type: Setup (Max at Fast Process Corner)
|
|
Data Path Delay: 1.195ns (logic 0.595ns (49.811%) route 0.600ns (50.189%))
|
|
Logic Levels: 0
|
|
Clock Path Skew: -0.221ns (DCD - SCD + CPR)
|
|
Destination Clock Delay (DCD): -0.609ns
|
|
Source Clock Delay (SCD): -0.388ns
|
|
Clock Pessimism Removal (CPR): 0.000ns
|
|
Clock Uncertainty: 0.222ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Discrete Jitter (DJ): 0.192ns
|
|
Phase Error (PE): 0.120ns
|
|
Timing Exception: Asynchronous Clock Groups
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock mlkem_clk rise edge)
|
|
0.000 0.000 r
|
|
clock source latency -1.947 -1.947
|
|
propagated clock network latency
|
|
1.559 -0.388
|
|
SLICE_X68Y90 RAMD32 0.000 -0.388 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_6_11/RAMA_D1/CLK
|
|
SLICE_X68Y90 RAMD32 (Prop_ramd32_CLK_O)
|
|
0.595 0.207 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_6_11/RAMA_D1/O
|
|
net (fo=1, routed) 0.600 0.806 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port10__3[7]
|
|
SLICE_X50Y90 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[7]/D
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock sys_clk rise edge) 0.000 0.000 r
|
|
clock source latency -1.848 -1.848
|
|
propagated clock network latency
|
|
1.239 -0.609
|
|
|
|
Slack: inf
|
|
Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_6_11/RAMA_D1/CLK
|
|
(rising edge-triggered cell RAMD32 clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns})
|
|
Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[7]/D
|
|
(rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Path Group: (none)
|
|
Path Type: Setup (Max at Fast Process Corner)
|
|
Data Path Delay: 1.195ns (logic 0.595ns (49.811%) route 0.600ns (50.189%))
|
|
Logic Levels: 0
|
|
Clock Path Skew: -0.221ns (DCD - SCD + CPR)
|
|
Destination Clock Delay (DCD): -0.609ns
|
|
Source Clock Delay (SCD): -0.388ns
|
|
Clock Pessimism Removal (CPR): 0.000ns
|
|
Clock Uncertainty: 0.222ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Discrete Jitter (DJ): 0.192ns
|
|
Phase Error (PE): 0.120ns
|
|
Timing Exception: Asynchronous Clock Groups
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock mlkem_clk rise edge)
|
|
0.000 0.000 r
|
|
clock source latency -1.947 -1.947
|
|
propagated clock network latency
|
|
1.559 -0.388
|
|
SLICE_X68Y90 RAMD32 0.000 -0.388 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_6_11/RAMA_D1/CLK
|
|
SLICE_X68Y90 RAMD32 (Prop_ramd32_CLK_O)
|
|
0.595 0.207 f u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_6_11/RAMA_D1/O
|
|
net (fo=1, routed) 0.600 0.806 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port10__3[7]
|
|
SLICE_X50Y90 FDRE f u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[7]/D
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock sys_clk rise edge) 0.000 0.000 r
|
|
clock source latency -1.848 -1.848
|
|
propagated clock network latency
|
|
1.239 -0.609
|
|
|
|
Slack: inf
|
|
Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_30_35/RAMA_D1/CLK
|
|
(rising edge-triggered cell RAMD32 clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns})
|
|
Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[31]/D
|
|
(rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Path Group: (none)
|
|
Path Type: Setup (Max at Fast Process Corner)
|
|
Data Path Delay: 1.183ns (logic 0.595ns (50.304%) route 0.588ns (49.696%))
|
|
Logic Levels: 0
|
|
Clock Path Skew: -0.223ns (DCD - SCD + CPR)
|
|
Destination Clock Delay (DCD): -0.609ns
|
|
Source Clock Delay (SCD): -0.386ns
|
|
Clock Pessimism Removal (CPR): 0.000ns
|
|
Clock Uncertainty: 0.222ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Discrete Jitter (DJ): 0.192ns
|
|
Phase Error (PE): 0.120ns
|
|
Timing Exception: Asynchronous Clock Groups
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock mlkem_clk rise edge)
|
|
0.000 0.000 r
|
|
clock source latency -1.947 -1.947
|
|
propagated clock network latency
|
|
1.561 -0.386
|
|
SLICE_X64Y91 RAMD32 0.000 -0.386 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_30_35/RAMA_D1/CLK
|
|
SLICE_X64Y91 RAMD32 (Prop_ramd32_CLK_O)
|
|
0.595 0.209 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_30_35/RAMA_D1/O
|
|
net (fo=1, routed) 0.588 0.797 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port10__3[31]
|
|
SLICE_X50Y90 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[31]/D
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock sys_clk rise edge) 0.000 0.000 r
|
|
clock source latency -1.848 -1.848
|
|
propagated clock network latency
|
|
1.239 -0.609
|
|
|
|
Slack: inf
|
|
Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_30_35/RAMA_D1/CLK
|
|
(rising edge-triggered cell RAMD32 clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns})
|
|
Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[31]/D
|
|
(rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Path Group: (none)
|
|
Path Type: Setup (Max at Fast Process Corner)
|
|
Data Path Delay: 1.183ns (logic 0.595ns (50.304%) route 0.588ns (49.696%))
|
|
Logic Levels: 0
|
|
Clock Path Skew: -0.223ns (DCD - SCD + CPR)
|
|
Destination Clock Delay (DCD): -0.609ns
|
|
Source Clock Delay (SCD): -0.386ns
|
|
Clock Pessimism Removal (CPR): 0.000ns
|
|
Clock Uncertainty: 0.222ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Discrete Jitter (DJ): 0.192ns
|
|
Phase Error (PE): 0.120ns
|
|
Timing Exception: Asynchronous Clock Groups
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock mlkem_clk rise edge)
|
|
0.000 0.000 r
|
|
clock source latency -1.947 -1.947
|
|
propagated clock network latency
|
|
1.561 -0.386
|
|
SLICE_X64Y91 RAMD32 0.000 -0.386 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_30_35/RAMA_D1/CLK
|
|
SLICE_X64Y91 RAMD32 (Prop_ramd32_CLK_O)
|
|
0.595 0.209 f u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_30_35/RAMA_D1/O
|
|
net (fo=1, routed) 0.588 0.797 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port10__3[31]
|
|
SLICE_X50Y90 FDRE f u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[31]/D
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock sys_clk rise edge) 0.000 0.000 r
|
|
clock source latency -1.848 -1.848
|
|
propagated clock network latency
|
|
1.239 -0.609
|
|
|
|
Slack: inf
|
|
Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_18_23/RAMA/CLK
|
|
(rising edge-triggered cell RAMD32 clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns})
|
|
Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[18]/D
|
|
(rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Path Group: (none)
|
|
Path Type: Setup (Max at Fast Process Corner)
|
|
Data Path Delay: 1.169ns (logic 0.612ns (52.356%) route 0.557ns (47.644%))
|
|
Logic Levels: 0
|
|
Clock Path Skew: -0.223ns (DCD - SCD + CPR)
|
|
Destination Clock Delay (DCD): -0.612ns
|
|
Source Clock Delay (SCD): -0.389ns
|
|
Clock Pessimism Removal (CPR): 0.000ns
|
|
Clock Uncertainty: 0.222ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Discrete Jitter (DJ): 0.192ns
|
|
Phase Error (PE): 0.120ns
|
|
Timing Exception: Asynchronous Clock Groups
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock mlkem_clk rise edge)
|
|
0.000 0.000 r
|
|
clock source latency -1.947 -1.947
|
|
propagated clock network latency
|
|
1.558 -0.389
|
|
SLICE_X68Y88 RAMD32 0.000 -0.389 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_18_23/RAMA/CLK
|
|
SLICE_X68Y88 RAMD32 (Prop_ramd32_CLK_O)
|
|
0.612 0.223 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_18_23/RAMA/O
|
|
net (fo=1, routed) 0.557 0.780 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port10__3[18]
|
|
SLICE_X51Y85 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[18]/D
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock sys_clk rise edge) 0.000 0.000 r
|
|
clock source latency -1.848 -1.848
|
|
propagated clock network latency
|
|
1.236 -0.612
|
|
|
|
Slack: inf
|
|
Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_18_23/RAMA/CLK
|
|
(rising edge-triggered cell RAMD32 clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns})
|
|
Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[18]/D
|
|
(rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Path Group: (none)
|
|
Path Type: Setup (Max at Fast Process Corner)
|
|
Data Path Delay: 1.169ns (logic 0.612ns (52.356%) route 0.557ns (47.644%))
|
|
Logic Levels: 0
|
|
Clock Path Skew: -0.223ns (DCD - SCD + CPR)
|
|
Destination Clock Delay (DCD): -0.612ns
|
|
Source Clock Delay (SCD): -0.389ns
|
|
Clock Pessimism Removal (CPR): 0.000ns
|
|
Clock Uncertainty: 0.222ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Discrete Jitter (DJ): 0.192ns
|
|
Phase Error (PE): 0.120ns
|
|
Timing Exception: Asynchronous Clock Groups
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock mlkem_clk rise edge)
|
|
0.000 0.000 r
|
|
clock source latency -1.947 -1.947
|
|
propagated clock network latency
|
|
1.558 -0.389
|
|
SLICE_X68Y88 RAMD32 0.000 -0.389 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_18_23/RAMA/CLK
|
|
SLICE_X68Y88 RAMD32 (Prop_ramd32_CLK_O)
|
|
0.612 0.223 f u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_18_23/RAMA/O
|
|
net (fo=1, routed) 0.557 0.780 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port10__3[18]
|
|
SLICE_X51Y85 FDRE f u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[18]/D
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock sys_clk rise edge) 0.000 0.000 r
|
|
clock source latency -1.848 -1.848
|
|
propagated clock network latency
|
|
1.236 -0.612
|
|
|
|
Slack: inf
|
|
Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_6_11/RAMA/CLK
|
|
(rising edge-triggered cell RAMD32 clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns})
|
|
Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[6]/D
|
|
(rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Path Group: (none)
|
|
Path Type: Setup (Max at Fast Process Corner)
|
|
Data Path Delay: 1.167ns (logic 0.612ns (52.454%) route 0.555ns (47.546%))
|
|
Logic Levels: 0
|
|
Clock Path Skew: -0.221ns (DCD - SCD + CPR)
|
|
Destination Clock Delay (DCD): -0.609ns
|
|
Source Clock Delay (SCD): -0.388ns
|
|
Clock Pessimism Removal (CPR): 0.000ns
|
|
Clock Uncertainty: 0.222ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Discrete Jitter (DJ): 0.192ns
|
|
Phase Error (PE): 0.120ns
|
|
Timing Exception: Asynchronous Clock Groups
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock mlkem_clk rise edge)
|
|
0.000 0.000 r
|
|
clock source latency -1.947 -1.947
|
|
propagated clock network latency
|
|
1.559 -0.388
|
|
SLICE_X68Y90 RAMD32 0.000 -0.388 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_6_11/RAMA/CLK
|
|
SLICE_X68Y90 RAMD32 (Prop_ramd32_CLK_O)
|
|
0.612 0.224 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_6_11/RAMA/O
|
|
net (fo=1, routed) 0.555 0.779 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port10__3[6]
|
|
SLICE_X50Y90 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[6]/D
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock sys_clk rise edge) 0.000 0.000 r
|
|
clock source latency -1.848 -1.848
|
|
propagated clock network latency
|
|
1.239 -0.609
|
|
|
|
Slack: inf
|
|
Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_6_11/RAMA/CLK
|
|
(rising edge-triggered cell RAMD32 clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns})
|
|
Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[6]/D
|
|
(rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Path Group: (none)
|
|
Path Type: Setup (Max at Fast Process Corner)
|
|
Data Path Delay: 1.167ns (logic 0.612ns (52.454%) route 0.555ns (47.546%))
|
|
Logic Levels: 0
|
|
Clock Path Skew: -0.221ns (DCD - SCD + CPR)
|
|
Destination Clock Delay (DCD): -0.609ns
|
|
Source Clock Delay (SCD): -0.388ns
|
|
Clock Pessimism Removal (CPR): 0.000ns
|
|
Clock Uncertainty: 0.222ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Discrete Jitter (DJ): 0.192ns
|
|
Phase Error (PE): 0.120ns
|
|
Timing Exception: Asynchronous Clock Groups
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock mlkem_clk rise edge)
|
|
0.000 0.000 r
|
|
clock source latency -1.947 -1.947
|
|
propagated clock network latency
|
|
1.559 -0.388
|
|
SLICE_X68Y90 RAMD32 0.000 -0.388 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_6_11/RAMA/CLK
|
|
SLICE_X68Y90 RAMD32 (Prop_ramd32_CLK_O)
|
|
0.612 0.224 f u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_6_11/RAMA/O
|
|
net (fo=1, routed) 0.555 0.779 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port10__3[6]
|
|
SLICE_X50Y90 FDRE f u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[6]/D
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock sys_clk rise edge) 0.000 0.000 r
|
|
clock source latency -1.848 -1.848
|
|
propagated clock network latency
|
|
1.239 -0.609
|
|
|
|
Slack: inf
|
|
Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_6_11/RAMC_D1/CLK
|
|
(rising edge-triggered cell RAMD32 clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns})
|
|
Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[11]/D
|
|
(rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Path Group: (none)
|
|
Path Type: Setup (Max at Fast Process Corner)
|
|
Data Path Delay: 1.166ns (logic 0.480ns (41.172%) route 0.686ns (58.828%))
|
|
Logic Levels: 0
|
|
Clock Path Skew: -0.221ns (DCD - SCD + CPR)
|
|
Destination Clock Delay (DCD): -0.609ns
|
|
Source Clock Delay (SCD): -0.388ns
|
|
Clock Pessimism Removal (CPR): 0.000ns
|
|
Clock Uncertainty: 0.222ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Discrete Jitter (DJ): 0.192ns
|
|
Phase Error (PE): 0.120ns
|
|
Timing Exception: Asynchronous Clock Groups
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock mlkem_clk rise edge)
|
|
0.000 0.000 r
|
|
clock source latency -1.947 -1.947
|
|
propagated clock network latency
|
|
1.559 -0.388
|
|
SLICE_X68Y90 RAMD32 0.000 -0.388 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_6_11/RAMC_D1/CLK
|
|
SLICE_X68Y90 RAMD32 (Prop_ramd32_CLK_O)
|
|
0.480 0.092 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_6_11/RAMC_D1/O
|
|
net (fo=1, routed) 0.686 0.778 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port10__3[11]
|
|
SLICE_X46Y90 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[11]/D
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock sys_clk rise edge) 0.000 0.000 r
|
|
clock source latency -1.848 -1.848
|
|
propagated clock network latency
|
|
1.239 -0.609
|
|
|
|
Slack: inf
|
|
Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_6_11/RAMC_D1/CLK
|
|
(rising edge-triggered cell RAMD32 clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns})
|
|
Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[11]/D
|
|
(rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Path Group: (none)
|
|
Path Type: Setup (Max at Fast Process Corner)
|
|
Data Path Delay: 1.166ns (logic 0.480ns (41.172%) route 0.686ns (58.828%))
|
|
Logic Levels: 0
|
|
Clock Path Skew: -0.221ns (DCD - SCD + CPR)
|
|
Destination Clock Delay (DCD): -0.609ns
|
|
Source Clock Delay (SCD): -0.388ns
|
|
Clock Pessimism Removal (CPR): 0.000ns
|
|
Clock Uncertainty: 0.222ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Discrete Jitter (DJ): 0.192ns
|
|
Phase Error (PE): 0.120ns
|
|
Timing Exception: Asynchronous Clock Groups
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock mlkem_clk rise edge)
|
|
0.000 0.000 r
|
|
clock source latency -1.947 -1.947
|
|
propagated clock network latency
|
|
1.559 -0.388
|
|
SLICE_X68Y90 RAMD32 0.000 -0.388 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_6_11/RAMC_D1/CLK
|
|
SLICE_X68Y90 RAMD32 (Prop_ramd32_CLK_O)
|
|
0.480 0.092 f u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_6_11/RAMC_D1/O
|
|
net (fo=1, routed) 0.686 0.778 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port10__3[11]
|
|
SLICE_X46Y90 FDRE f u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[11]/D
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock sys_clk rise edge) 0.000 0.000 r
|
|
clock source latency -1.848 -1.848
|
|
propagated clock network latency
|
|
1.239 -0.609
|
|
|
|
Slack: inf
|
|
Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_24_29/RAMA/CLK
|
|
(rising edge-triggered cell RAMD32 clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns})
|
|
Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[24]/D
|
|
(rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Path Group: (none)
|
|
Path Type: Setup (Max at Fast Process Corner)
|
|
Data Path Delay: 1.160ns (logic 0.612ns (52.737%) route 0.548ns (47.263%))
|
|
Logic Levels: 0
|
|
Clock Path Skew: -0.221ns (DCD - SCD + CPR)
|
|
Destination Clock Delay (DCD): -0.610ns
|
|
Source Clock Delay (SCD): -0.389ns
|
|
Clock Pessimism Removal (CPR): 0.000ns
|
|
Clock Uncertainty: 0.222ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Discrete Jitter (DJ): 0.192ns
|
|
Phase Error (PE): 0.120ns
|
|
Timing Exception: Asynchronous Clock Groups
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock mlkem_clk rise edge)
|
|
0.000 0.000 r
|
|
clock source latency -1.947 -1.947
|
|
propagated clock network latency
|
|
1.558 -0.389
|
|
SLICE_X66Y89 RAMD32 0.000 -0.389 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_24_29/RAMA/CLK
|
|
SLICE_X66Y89 RAMD32 (Prop_ramd32_CLK_O)
|
|
0.612 0.223 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_24_29/RAMA/O
|
|
net (fo=1, routed) 0.548 0.771 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port10__3[24]
|
|
SLICE_X50Y89 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[24]/D
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock sys_clk rise edge) 0.000 0.000 r
|
|
clock source latency -1.848 -1.848
|
|
propagated clock network latency
|
|
1.238 -0.610
|
|
|
|
Slack: inf
|
|
Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_24_29/RAMA/CLK
|
|
(rising edge-triggered cell RAMD32 clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns})
|
|
Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[24]/D
|
|
(rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Path Group: (none)
|
|
Path Type: Setup (Max at Fast Process Corner)
|
|
Data Path Delay: 1.160ns (logic 0.612ns (52.737%) route 0.548ns (47.263%))
|
|
Logic Levels: 0
|
|
Clock Path Skew: -0.221ns (DCD - SCD + CPR)
|
|
Destination Clock Delay (DCD): -0.610ns
|
|
Source Clock Delay (SCD): -0.389ns
|
|
Clock Pessimism Removal (CPR): 0.000ns
|
|
Clock Uncertainty: 0.222ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Discrete Jitter (DJ): 0.192ns
|
|
Phase Error (PE): 0.120ns
|
|
Timing Exception: Asynchronous Clock Groups
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock mlkem_clk rise edge)
|
|
0.000 0.000 r
|
|
clock source latency -1.947 -1.947
|
|
propagated clock network latency
|
|
1.558 -0.389
|
|
SLICE_X66Y89 RAMD32 0.000 -0.389 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_24_29/RAMA/CLK
|
|
SLICE_X66Y89 RAMD32 (Prop_ramd32_CLK_O)
|
|
0.612 0.223 f u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_24_29/RAMA/O
|
|
net (fo=1, routed) 0.548 0.771 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port10__3[24]
|
|
SLICE_X50Y89 FDRE f u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[24]/D
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock sys_clk rise edge) 0.000 0.000 r
|
|
clock source latency -1.848 -1.848
|
|
propagated clock network latency
|
|
1.238 -0.610
|
|
|
|
Slack: inf
|
|
Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_12_17/RAMA/CLK
|
|
(rising edge-triggered cell RAMD32 clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns})
|
|
Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[12]/D
|
|
(rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Path Group: (none)
|
|
Path Type: Setup (Max at Fast Process Corner)
|
|
Data Path Delay: 1.139ns (logic 0.612ns (53.734%) route 0.527ns (46.266%))
|
|
Logic Levels: 0
|
|
Clock Path Skew: -0.221ns (DCD - SCD + CPR)
|
|
Destination Clock Delay (DCD): -0.610ns
|
|
Source Clock Delay (SCD): -0.389ns
|
|
Clock Pessimism Removal (CPR): 0.000ns
|
|
Clock Uncertainty: 0.222ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Discrete Jitter (DJ): 0.192ns
|
|
Phase Error (PE): 0.120ns
|
|
Timing Exception: Asynchronous Clock Groups
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock mlkem_clk rise edge)
|
|
0.000 0.000 r
|
|
clock source latency -1.947 -1.947
|
|
propagated clock network latency
|
|
1.558 -0.389
|
|
SLICE_X66Y88 RAMD32 0.000 -0.389 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_12_17/RAMA/CLK
|
|
SLICE_X66Y88 RAMD32 (Prop_ramd32_CLK_O)
|
|
0.612 0.223 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_12_17/RAMA/O
|
|
net (fo=1, routed) 0.527 0.750 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port10__3[12]
|
|
SLICE_X50Y89 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[12]/D
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock sys_clk rise edge) 0.000 0.000 r
|
|
clock source latency -1.848 -1.848
|
|
propagated clock network latency
|
|
1.238 -0.610
|
|
|
|
Slack: inf
|
|
Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_12_17/RAMA/CLK
|
|
(rising edge-triggered cell RAMD32 clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns})
|
|
Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[12]/D
|
|
(rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Path Group: (none)
|
|
Path Type: Setup (Max at Fast Process Corner)
|
|
Data Path Delay: 1.139ns (logic 0.612ns (53.734%) route 0.527ns (46.266%))
|
|
Logic Levels: 0
|
|
Clock Path Skew: -0.221ns (DCD - SCD + CPR)
|
|
Destination Clock Delay (DCD): -0.610ns
|
|
Source Clock Delay (SCD): -0.389ns
|
|
Clock Pessimism Removal (CPR): 0.000ns
|
|
Clock Uncertainty: 0.222ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Discrete Jitter (DJ): 0.192ns
|
|
Phase Error (PE): 0.120ns
|
|
Timing Exception: Asynchronous Clock Groups
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock mlkem_clk rise edge)
|
|
0.000 0.000 r
|
|
clock source latency -1.947 -1.947
|
|
propagated clock network latency
|
|
1.558 -0.389
|
|
SLICE_X66Y88 RAMD32 0.000 -0.389 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_12_17/RAMA/CLK
|
|
SLICE_X66Y88 RAMD32 (Prop_ramd32_CLK_O)
|
|
0.612 0.223 f u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_12_17/RAMA/O
|
|
net (fo=1, routed) 0.527 0.750 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port10__3[12]
|
|
SLICE_X50Y89 FDRE f u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[12]/D
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock sys_clk rise edge) 0.000 0.000 r
|
|
clock source latency -1.848 -1.848
|
|
propagated clock network latency
|
|
1.238 -0.610
|
|
|
|
Slack: inf
|
|
Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_12_17/RAMA_D1/CLK
|
|
(rising edge-triggered cell RAMD32 clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns})
|
|
Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[13]/D
|
|
(rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Path Group: (none)
|
|
Path Type: Setup (Max at Fast Process Corner)
|
|
Data Path Delay: 1.128ns (logic 0.595ns (52.742%) route 0.533ns (47.258%))
|
|
Logic Levels: 0
|
|
Clock Path Skew: -0.221ns (DCD - SCD + CPR)
|
|
Destination Clock Delay (DCD): -0.610ns
|
|
Source Clock Delay (SCD): -0.389ns
|
|
Clock Pessimism Removal (CPR): 0.000ns
|
|
Clock Uncertainty: 0.222ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Discrete Jitter (DJ): 0.192ns
|
|
Phase Error (PE): 0.120ns
|
|
Timing Exception: Asynchronous Clock Groups
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock mlkem_clk rise edge)
|
|
0.000 0.000 r
|
|
clock source latency -1.947 -1.947
|
|
propagated clock network latency
|
|
1.558 -0.389
|
|
SLICE_X66Y88 RAMD32 0.000 -0.389 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_12_17/RAMA_D1/CLK
|
|
SLICE_X66Y88 RAMD32 (Prop_ramd32_CLK_O)
|
|
0.595 0.206 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_12_17/RAMA_D1/O
|
|
net (fo=1, routed) 0.533 0.739 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port10__3[13]
|
|
SLICE_X49Y88 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[13]/D
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock sys_clk rise edge) 0.000 0.000 r
|
|
clock source latency -1.848 -1.848
|
|
propagated clock network latency
|
|
1.238 -0.610
|
|
|
|
Slack: inf
|
|
Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_12_17/RAMA_D1/CLK
|
|
(rising edge-triggered cell RAMD32 clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns})
|
|
Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[13]/D
|
|
(rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Path Group: (none)
|
|
Path Type: Setup (Max at Fast Process Corner)
|
|
Data Path Delay: 1.128ns (logic 0.595ns (52.742%) route 0.533ns (47.258%))
|
|
Logic Levels: 0
|
|
Clock Path Skew: -0.221ns (DCD - SCD + CPR)
|
|
Destination Clock Delay (DCD): -0.610ns
|
|
Source Clock Delay (SCD): -0.389ns
|
|
Clock Pessimism Removal (CPR): 0.000ns
|
|
Clock Uncertainty: 0.222ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Discrete Jitter (DJ): 0.192ns
|
|
Phase Error (PE): 0.120ns
|
|
Timing Exception: Asynchronous Clock Groups
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock mlkem_clk rise edge)
|
|
0.000 0.000 r
|
|
clock source latency -1.947 -1.947
|
|
propagated clock network latency
|
|
1.558 -0.389
|
|
SLICE_X66Y88 RAMD32 0.000 -0.389 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_12_17/RAMA_D1/CLK
|
|
SLICE_X66Y88 RAMD32 (Prop_ramd32_CLK_O)
|
|
0.595 0.206 f u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_12_17/RAMA_D1/O
|
|
net (fo=1, routed) 0.533 0.739 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port10__3[13]
|
|
SLICE_X49Y88 FDRE f u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[13]/D
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock sys_clk rise edge) 0.000 0.000 r
|
|
clock source latency -1.848 -1.848
|
|
propagated clock network latency
|
|
1.238 -0.610
|
|
|
|
Slack: inf
|
|
Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_18_23/RAMA_D1/CLK
|
|
(rising edge-triggered cell RAMD32 clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns})
|
|
Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[19]/D
|
|
(rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Path Group: (none)
|
|
Path Type: Setup (Max at Fast Process Corner)
|
|
Data Path Delay: 1.122ns (logic 0.595ns (53.042%) route 0.527ns (46.958%))
|
|
Logic Levels: 0
|
|
Clock Path Skew: -0.221ns (DCD - SCD + CPR)
|
|
Destination Clock Delay (DCD): -0.610ns
|
|
Source Clock Delay (SCD): -0.389ns
|
|
Clock Pessimism Removal (CPR): 0.000ns
|
|
Clock Uncertainty: 0.222ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Discrete Jitter (DJ): 0.192ns
|
|
Phase Error (PE): 0.120ns
|
|
Timing Exception: Asynchronous Clock Groups
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock mlkem_clk rise edge)
|
|
0.000 0.000 r
|
|
clock source latency -1.947 -1.947
|
|
propagated clock network latency
|
|
1.558 -0.389
|
|
SLICE_X68Y88 RAMD32 0.000 -0.389 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_18_23/RAMA_D1/CLK
|
|
SLICE_X68Y88 RAMD32 (Prop_ramd32_CLK_O)
|
|
0.595 0.206 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_18_23/RAMA_D1/O
|
|
net (fo=1, routed) 0.527 0.733 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port10__3[19]
|
|
SLICE_X49Y88 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[19]/D
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock sys_clk rise edge) 0.000 0.000 r
|
|
clock source latency -1.848 -1.848
|
|
propagated clock network latency
|
|
1.238 -0.610
|
|
|
|
Slack: inf
|
|
Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_18_23/RAMA_D1/CLK
|
|
(rising edge-triggered cell RAMD32 clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns})
|
|
Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[19]/D
|
|
(rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Path Group: (none)
|
|
Path Type: Setup (Max at Fast Process Corner)
|
|
Data Path Delay: 1.122ns (logic 0.595ns (53.042%) route 0.527ns (46.958%))
|
|
Logic Levels: 0
|
|
Clock Path Skew: -0.221ns (DCD - SCD + CPR)
|
|
Destination Clock Delay (DCD): -0.610ns
|
|
Source Clock Delay (SCD): -0.389ns
|
|
Clock Pessimism Removal (CPR): 0.000ns
|
|
Clock Uncertainty: 0.222ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Discrete Jitter (DJ): 0.192ns
|
|
Phase Error (PE): 0.120ns
|
|
Timing Exception: Asynchronous Clock Groups
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock mlkem_clk rise edge)
|
|
0.000 0.000 r
|
|
clock source latency -1.947 -1.947
|
|
propagated clock network latency
|
|
1.558 -0.389
|
|
SLICE_X68Y88 RAMD32 0.000 -0.389 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_18_23/RAMA_D1/CLK
|
|
SLICE_X68Y88 RAMD32 (Prop_ramd32_CLK_O)
|
|
0.595 0.206 f u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_18_23/RAMA_D1/O
|
|
net (fo=1, routed) 0.527 0.733 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port10__3[19]
|
|
SLICE_X49Y88 FDRE f u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[19]/D
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock sys_clk rise edge) 0.000 0.000 r
|
|
clock source latency -1.848 -1.848
|
|
propagated clock network latency
|
|
1.238 -0.610
|
|
|
|
Slack: inf
|
|
Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_18_23/RAMB_D1/CLK
|
|
(rising edge-triggered cell RAMD32 clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns})
|
|
Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[21]/D
|
|
(rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Path Group: (none)
|
|
Path Type: Setup (Max at Fast Process Corner)
|
|
Data Path Delay: 1.103ns (logic 0.482ns (43.685%) route 0.621ns (56.315%))
|
|
Logic Levels: 0
|
|
Clock Path Skew: -0.221ns (DCD - SCD + CPR)
|
|
Destination Clock Delay (DCD): -0.610ns
|
|
Source Clock Delay (SCD): -0.389ns
|
|
Clock Pessimism Removal (CPR): 0.000ns
|
|
Clock Uncertainty: 0.222ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Discrete Jitter (DJ): 0.192ns
|
|
Phase Error (PE): 0.120ns
|
|
Timing Exception: Asynchronous Clock Groups
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock mlkem_clk rise edge)
|
|
0.000 0.000 r
|
|
clock source latency -1.947 -1.947
|
|
propagated clock network latency
|
|
1.558 -0.389
|
|
SLICE_X68Y88 RAMD32 0.000 -0.389 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_18_23/RAMB_D1/CLK
|
|
SLICE_X68Y88 RAMD32 (Prop_ramd32_CLK_O)
|
|
0.482 0.093 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_18_23/RAMB_D1/O
|
|
net (fo=1, routed) 0.621 0.714 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port10__3[21]
|
|
SLICE_X49Y88 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[21]/D
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock sys_clk rise edge) 0.000 0.000 r
|
|
clock source latency -1.848 -1.848
|
|
propagated clock network latency
|
|
1.238 -0.610
|
|
|
|
Slack: inf
|
|
Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_18_23/RAMB_D1/CLK
|
|
(rising edge-triggered cell RAMD32 clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns})
|
|
Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[21]/D
|
|
(rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Path Group: (none)
|
|
Path Type: Setup (Max at Fast Process Corner)
|
|
Data Path Delay: 1.103ns (logic 0.482ns (43.685%) route 0.621ns (56.315%))
|
|
Logic Levels: 0
|
|
Clock Path Skew: -0.221ns (DCD - SCD + CPR)
|
|
Destination Clock Delay (DCD): -0.610ns
|
|
Source Clock Delay (SCD): -0.389ns
|
|
Clock Pessimism Removal (CPR): 0.000ns
|
|
Clock Uncertainty: 0.222ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Discrete Jitter (DJ): 0.192ns
|
|
Phase Error (PE): 0.120ns
|
|
Timing Exception: Asynchronous Clock Groups
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock mlkem_clk rise edge)
|
|
0.000 0.000 r
|
|
clock source latency -1.947 -1.947
|
|
propagated clock network latency
|
|
1.558 -0.389
|
|
SLICE_X68Y88 RAMD32 0.000 -0.389 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_18_23/RAMB_D1/CLK
|
|
SLICE_X68Y88 RAMD32 (Prop_ramd32_CLK_O)
|
|
0.482 0.093 f u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_18_23/RAMB_D1/O
|
|
net (fo=1, routed) 0.621 0.714 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port10__3[21]
|
|
SLICE_X49Y88 FDRE f u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[21]/D
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock sys_clk rise edge) 0.000 0.000 r
|
|
clock source latency -1.848 -1.848
|
|
propagated clock network latency
|
|
1.238 -0.610
|
|
|
|
Slack: inf
|
|
Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_6_11/RAMC/CLK
|
|
(rising edge-triggered cell RAMD32 clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns})
|
|
Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[10]/D
|
|
(rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Path Group: (none)
|
|
Path Type: Setup (Max at Fast Process Corner)
|
|
Data Path Delay: 1.093ns (logic 0.485ns (44.377%) route 0.608ns (55.623%))
|
|
Logic Levels: 0
|
|
Clock Path Skew: -0.222ns (DCD - SCD + CPR)
|
|
Destination Clock Delay (DCD): -0.610ns
|
|
Source Clock Delay (SCD): -0.388ns
|
|
Clock Pessimism Removal (CPR): 0.000ns
|
|
Clock Uncertainty: 0.222ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Discrete Jitter (DJ): 0.192ns
|
|
Phase Error (PE): 0.120ns
|
|
Timing Exception: Asynchronous Clock Groups
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock mlkem_clk rise edge)
|
|
0.000 0.000 r
|
|
clock source latency -1.947 -1.947
|
|
propagated clock network latency
|
|
1.559 -0.388
|
|
SLICE_X68Y90 RAMD32 0.000 -0.388 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_6_11/RAMC/CLK
|
|
SLICE_X68Y90 RAMD32 (Prop_ramd32_CLK_O)
|
|
0.485 0.097 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_6_11/RAMC/O
|
|
net (fo=1, routed) 0.608 0.705 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port10__3[10]
|
|
SLICE_X48Y89 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[10]/D
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock sys_clk rise edge) 0.000 0.000 r
|
|
clock source latency -1.848 -1.848
|
|
propagated clock network latency
|
|
1.238 -0.610
|
|
|
|
Slack: inf
|
|
Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_6_11/RAMC/CLK
|
|
(rising edge-triggered cell RAMD32 clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns})
|
|
Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[10]/D
|
|
(rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Path Group: (none)
|
|
Path Type: Setup (Max at Fast Process Corner)
|
|
Data Path Delay: 1.093ns (logic 0.485ns (44.377%) route 0.608ns (55.623%))
|
|
Logic Levels: 0
|
|
Clock Path Skew: -0.222ns (DCD - SCD + CPR)
|
|
Destination Clock Delay (DCD): -0.610ns
|
|
Source Clock Delay (SCD): -0.388ns
|
|
Clock Pessimism Removal (CPR): 0.000ns
|
|
Clock Uncertainty: 0.222ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Discrete Jitter (DJ): 0.192ns
|
|
Phase Error (PE): 0.120ns
|
|
Timing Exception: Asynchronous Clock Groups
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock mlkem_clk rise edge)
|
|
0.000 0.000 r
|
|
clock source latency -1.947 -1.947
|
|
propagated clock network latency
|
|
1.559 -0.388
|
|
SLICE_X68Y90 RAMD32 0.000 -0.388 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_6_11/RAMC/CLK
|
|
SLICE_X68Y90 RAMD32 (Prop_ramd32_CLK_O)
|
|
0.485 0.097 f u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_6_11/RAMC/O
|
|
net (fo=1, routed) 0.608 0.705 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port10__3[10]
|
|
SLICE_X48Y89 FDRE f u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[10]/D
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock sys_clk rise edge) 0.000 0.000 r
|
|
clock source latency -1.848 -1.848
|
|
propagated clock network latency
|
|
1.238 -0.610
|
|
|
|
Slack: inf
|
|
Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_0_5/RAMA_D1/CLK
|
|
(rising edge-triggered cell RAMD32 clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns})
|
|
Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[1]/D
|
|
(rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Path Group: (none)
|
|
Path Type: Setup (Max at Fast Process Corner)
|
|
Data Path Delay: 1.073ns (logic 0.595ns (55.460%) route 0.478ns (44.540%))
|
|
Logic Levels: 0
|
|
Clock Path Skew: -0.221ns (DCD - SCD + CPR)
|
|
Destination Clock Delay (DCD): -0.610ns
|
|
Source Clock Delay (SCD): -0.389ns
|
|
Clock Pessimism Removal (CPR): 0.000ns
|
|
Clock Uncertainty: 0.222ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Discrete Jitter (DJ): 0.192ns
|
|
Phase Error (PE): 0.120ns
|
|
Timing Exception: Asynchronous Clock Groups
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock mlkem_clk rise edge)
|
|
0.000 0.000 r
|
|
clock source latency -1.947 -1.947
|
|
propagated clock network latency
|
|
1.558 -0.389
|
|
SLICE_X68Y89 RAMD32 0.000 -0.389 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_0_5/RAMA_D1/CLK
|
|
SLICE_X68Y89 RAMD32 (Prop_ramd32_CLK_O)
|
|
0.595 0.206 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_0_5/RAMA_D1/O
|
|
net (fo=1, routed) 0.478 0.684 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port10__3[1]
|
|
SLICE_X48Y89 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[1]/D
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock sys_clk rise edge) 0.000 0.000 r
|
|
clock source latency -1.848 -1.848
|
|
propagated clock network latency
|
|
1.238 -0.610
|
|
|
|
Slack: inf
|
|
Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_0_5/RAMA_D1/CLK
|
|
(rising edge-triggered cell RAMD32 clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns})
|
|
Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[1]/D
|
|
(rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Path Group: (none)
|
|
Path Type: Setup (Max at Fast Process Corner)
|
|
Data Path Delay: 1.073ns (logic 0.595ns (55.460%) route 0.478ns (44.540%))
|
|
Logic Levels: 0
|
|
Clock Path Skew: -0.221ns (DCD - SCD + CPR)
|
|
Destination Clock Delay (DCD): -0.610ns
|
|
Source Clock Delay (SCD): -0.389ns
|
|
Clock Pessimism Removal (CPR): 0.000ns
|
|
Clock Uncertainty: 0.222ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Discrete Jitter (DJ): 0.192ns
|
|
Phase Error (PE): 0.120ns
|
|
Timing Exception: Asynchronous Clock Groups
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock mlkem_clk rise edge)
|
|
0.000 0.000 r
|
|
clock source latency -1.947 -1.947
|
|
propagated clock network latency
|
|
1.558 -0.389
|
|
SLICE_X68Y89 RAMD32 0.000 -0.389 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_0_5/RAMA_D1/CLK
|
|
SLICE_X68Y89 RAMD32 (Prop_ramd32_CLK_O)
|
|
0.595 0.206 f u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_0_5/RAMA_D1/O
|
|
net (fo=1, routed) 0.478 0.684 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port10__3[1]
|
|
SLICE_X48Y89 FDRE f u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[1]/D
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock sys_clk rise edge) 0.000 0.000 r
|
|
clock source latency -1.848 -1.848
|
|
propagated clock network latency
|
|
1.238 -0.610
|
|
|
|
Slack: inf
|
|
Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_24_29/RAMA_D1/CLK
|
|
(rising edge-triggered cell RAMD32 clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns})
|
|
Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[25]/D
|
|
(rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Path Group: (none)
|
|
Path Type: Setup (Max at Fast Process Corner)
|
|
Data Path Delay: 1.071ns (logic 0.595ns (55.545%) route 0.476ns (44.455%))
|
|
Logic Levels: 0
|
|
Clock Path Skew: -0.221ns (DCD - SCD + CPR)
|
|
Destination Clock Delay (DCD): -0.610ns
|
|
Source Clock Delay (SCD): -0.389ns
|
|
Clock Pessimism Removal (CPR): 0.000ns
|
|
Clock Uncertainty: 0.222ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Discrete Jitter (DJ): 0.192ns
|
|
Phase Error (PE): 0.120ns
|
|
Timing Exception: Asynchronous Clock Groups
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock mlkem_clk rise edge)
|
|
0.000 0.000 r
|
|
clock source latency -1.947 -1.947
|
|
propagated clock network latency
|
|
1.558 -0.389
|
|
SLICE_X66Y89 RAMD32 0.000 -0.389 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_24_29/RAMA_D1/CLK
|
|
SLICE_X66Y89 RAMD32 (Prop_ramd32_CLK_O)
|
|
0.595 0.206 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_24_29/RAMA_D1/O
|
|
net (fo=1, routed) 0.476 0.682 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port10__3[25]
|
|
SLICE_X48Y88 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[25]/D
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock sys_clk rise edge) 0.000 0.000 r
|
|
clock source latency -1.848 -1.848
|
|
propagated clock network latency
|
|
1.238 -0.610
|
|
|
|
Slack: inf
|
|
Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_24_29/RAMA_D1/CLK
|
|
(rising edge-triggered cell RAMD32 clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns})
|
|
Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[25]/D
|
|
(rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Path Group: (none)
|
|
Path Type: Setup (Max at Fast Process Corner)
|
|
Data Path Delay: 1.071ns (logic 0.595ns (55.545%) route 0.476ns (44.455%))
|
|
Logic Levels: 0
|
|
Clock Path Skew: -0.221ns (DCD - SCD + CPR)
|
|
Destination Clock Delay (DCD): -0.610ns
|
|
Source Clock Delay (SCD): -0.389ns
|
|
Clock Pessimism Removal (CPR): 0.000ns
|
|
Clock Uncertainty: 0.222ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Discrete Jitter (DJ): 0.192ns
|
|
Phase Error (PE): 0.120ns
|
|
Timing Exception: Asynchronous Clock Groups
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock mlkem_clk rise edge)
|
|
0.000 0.000 r
|
|
clock source latency -1.947 -1.947
|
|
propagated clock network latency
|
|
1.558 -0.389
|
|
SLICE_X66Y89 RAMD32 0.000 -0.389 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_24_29/RAMA_D1/CLK
|
|
SLICE_X66Y89 RAMD32 (Prop_ramd32_CLK_O)
|
|
0.595 0.206 f u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_24_29/RAMA_D1/O
|
|
net (fo=1, routed) 0.476 0.682 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port10__3[25]
|
|
SLICE_X48Y88 FDRE f u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[25]/D
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock sys_clk rise edge) 0.000 0.000 r
|
|
clock source latency -1.848 -1.848
|
|
propagated clock network latency
|
|
1.238 -0.610
|
|
|
|
Slack: inf
|
|
Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_24_29/RAMC/CLK
|
|
(rising edge-triggered cell RAMD32 clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns})
|
|
Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[28]/D
|
|
(rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Path Group: (none)
|
|
Path Type: Setup (Max at Fast Process Corner)
|
|
Data Path Delay: 1.064ns (logic 0.485ns (45.566%) route 0.579ns (54.434%))
|
|
Logic Levels: 0
|
|
Clock Path Skew: -0.220ns (DCD - SCD + CPR)
|
|
Destination Clock Delay (DCD): -0.609ns
|
|
Source Clock Delay (SCD): -0.389ns
|
|
Clock Pessimism Removal (CPR): 0.000ns
|
|
Clock Uncertainty: 0.222ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Discrete Jitter (DJ): 0.192ns
|
|
Phase Error (PE): 0.120ns
|
|
Timing Exception: Asynchronous Clock Groups
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock mlkem_clk rise edge)
|
|
0.000 0.000 r
|
|
clock source latency -1.947 -1.947
|
|
propagated clock network latency
|
|
1.558 -0.389
|
|
SLICE_X66Y89 RAMD32 0.000 -0.389 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_24_29/RAMC/CLK
|
|
SLICE_X66Y89 RAMD32 (Prop_ramd32_CLK_O)
|
|
0.485 0.096 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_24_29/RAMC/O
|
|
net (fo=1, routed) 0.579 0.675 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port10__3[28]
|
|
SLICE_X50Y90 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[28]/D
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock sys_clk rise edge) 0.000 0.000 r
|
|
clock source latency -1.848 -1.848
|
|
propagated clock network latency
|
|
1.239 -0.609
|
|
|
|
Slack: inf
|
|
Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_24_29/RAMC/CLK
|
|
(rising edge-triggered cell RAMD32 clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns})
|
|
Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[28]/D
|
|
(rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Path Group: (none)
|
|
Path Type: Setup (Max at Fast Process Corner)
|
|
Data Path Delay: 1.064ns (logic 0.485ns (45.566%) route 0.579ns (54.434%))
|
|
Logic Levels: 0
|
|
Clock Path Skew: -0.220ns (DCD - SCD + CPR)
|
|
Destination Clock Delay (DCD): -0.609ns
|
|
Source Clock Delay (SCD): -0.389ns
|
|
Clock Pessimism Removal (CPR): 0.000ns
|
|
Clock Uncertainty: 0.222ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Discrete Jitter (DJ): 0.192ns
|
|
Phase Error (PE): 0.120ns
|
|
Timing Exception: Asynchronous Clock Groups
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock mlkem_clk rise edge)
|
|
0.000 0.000 r
|
|
clock source latency -1.947 -1.947
|
|
propagated clock network latency
|
|
1.558 -0.389
|
|
SLICE_X66Y89 RAMD32 0.000 -0.389 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_24_29/RAMC/CLK
|
|
SLICE_X66Y89 RAMD32 (Prop_ramd32_CLK_O)
|
|
0.485 0.096 f u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_24_29/RAMC/O
|
|
net (fo=1, routed) 0.579 0.675 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port10__3[28]
|
|
SLICE_X50Y90 FDRE f u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[28]/D
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock sys_clk rise edge) 0.000 0.000 r
|
|
clock source latency -1.848 -1.848
|
|
propagated clock network latency
|
|
1.239 -0.609
|
|
|
|
Slack: inf
|
|
Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_0_5/RAMC/CLK
|
|
(rising edge-triggered cell RAMD32 clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns})
|
|
Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[4]/D
|
|
(rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Path Group: (none)
|
|
Path Type: Setup (Max at Fast Process Corner)
|
|
Data Path Delay: 1.051ns (logic 0.485ns (46.153%) route 0.566ns (53.847%))
|
|
Logic Levels: 0
|
|
Clock Path Skew: -0.221ns (DCD - SCD + CPR)
|
|
Destination Clock Delay (DCD): -0.610ns
|
|
Source Clock Delay (SCD): -0.389ns
|
|
Clock Pessimism Removal (CPR): 0.000ns
|
|
Clock Uncertainty: 0.222ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Discrete Jitter (DJ): 0.192ns
|
|
Phase Error (PE): 0.120ns
|
|
Timing Exception: Asynchronous Clock Groups
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock mlkem_clk rise edge)
|
|
0.000 0.000 r
|
|
clock source latency -1.947 -1.947
|
|
propagated clock network latency
|
|
1.558 -0.389
|
|
SLICE_X68Y89 RAMD32 0.000 -0.389 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_0_5/RAMC/CLK
|
|
SLICE_X68Y89 RAMD32 (Prop_ramd32_CLK_O)
|
|
0.485 0.096 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_0_5/RAMC/O
|
|
net (fo=1, routed) 0.566 0.662 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port10__3[4]
|
|
SLICE_X50Y89 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[4]/D
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock sys_clk rise edge) 0.000 0.000 r
|
|
clock source latency -1.848 -1.848
|
|
propagated clock network latency
|
|
1.238 -0.610
|
|
|
|
Slack: inf
|
|
Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_0_5/RAMC/CLK
|
|
(rising edge-triggered cell RAMD32 clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns})
|
|
Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[4]/D
|
|
(rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Path Group: (none)
|
|
Path Type: Setup (Max at Fast Process Corner)
|
|
Data Path Delay: 1.051ns (logic 0.485ns (46.153%) route 0.566ns (53.847%))
|
|
Logic Levels: 0
|
|
Clock Path Skew: -0.221ns (DCD - SCD + CPR)
|
|
Destination Clock Delay (DCD): -0.610ns
|
|
Source Clock Delay (SCD): -0.389ns
|
|
Clock Pessimism Removal (CPR): 0.000ns
|
|
Clock Uncertainty: 0.222ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Discrete Jitter (DJ): 0.192ns
|
|
Phase Error (PE): 0.120ns
|
|
Timing Exception: Asynchronous Clock Groups
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock mlkem_clk rise edge)
|
|
0.000 0.000 r
|
|
clock source latency -1.947 -1.947
|
|
propagated clock network latency
|
|
1.558 -0.389
|
|
SLICE_X68Y89 RAMD32 0.000 -0.389 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_0_5/RAMC/CLK
|
|
SLICE_X68Y89 RAMD32 (Prop_ramd32_CLK_O)
|
|
0.485 0.096 f u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_0_5/RAMC/O
|
|
net (fo=1, routed) 0.566 0.662 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port10__3[4]
|
|
SLICE_X50Y89 FDRE f u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[4]/D
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock sys_clk rise edge) 0.000 0.000 r
|
|
clock source latency -1.848 -1.848
|
|
propagated clock network latency
|
|
1.238 -0.610
|
|
|
|
Slack: inf
|
|
Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_18_23/RAMC/CLK
|
|
(rising edge-triggered cell RAMD32 clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns})
|
|
Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[22]/D
|
|
(rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Path Group: (none)
|
|
Path Type: Setup (Max at Fast Process Corner)
|
|
Data Path Delay: 1.028ns (logic 0.485ns (47.163%) route 0.543ns (52.837%))
|
|
Logic Levels: 0
|
|
Clock Path Skew: -0.221ns (DCD - SCD + CPR)
|
|
Destination Clock Delay (DCD): -0.610ns
|
|
Source Clock Delay (SCD): -0.389ns
|
|
Clock Pessimism Removal (CPR): 0.000ns
|
|
Clock Uncertainty: 0.222ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Discrete Jitter (DJ): 0.192ns
|
|
Phase Error (PE): 0.120ns
|
|
Timing Exception: Asynchronous Clock Groups
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock mlkem_clk rise edge)
|
|
0.000 0.000 r
|
|
clock source latency -1.947 -1.947
|
|
propagated clock network latency
|
|
1.558 -0.389
|
|
SLICE_X68Y88 RAMD32 0.000 -0.389 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_18_23/RAMC/CLK
|
|
SLICE_X68Y88 RAMD32 (Prop_ramd32_CLK_O)
|
|
0.485 0.096 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_18_23/RAMC/O
|
|
net (fo=1, routed) 0.543 0.639 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port10__3[22]
|
|
SLICE_X48Y88 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[22]/D
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock sys_clk rise edge) 0.000 0.000 r
|
|
clock source latency -1.848 -1.848
|
|
propagated clock network latency
|
|
1.238 -0.610
|
|
|
|
Slack: inf
|
|
Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_18_23/RAMC/CLK
|
|
(rising edge-triggered cell RAMD32 clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns})
|
|
Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[22]/D
|
|
(rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Path Group: (none)
|
|
Path Type: Setup (Max at Fast Process Corner)
|
|
Data Path Delay: 1.028ns (logic 0.485ns (47.163%) route 0.543ns (52.837%))
|
|
Logic Levels: 0
|
|
Clock Path Skew: -0.221ns (DCD - SCD + CPR)
|
|
Destination Clock Delay (DCD): -0.610ns
|
|
Source Clock Delay (SCD): -0.389ns
|
|
Clock Pessimism Removal (CPR): 0.000ns
|
|
Clock Uncertainty: 0.222ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Discrete Jitter (DJ): 0.192ns
|
|
Phase Error (PE): 0.120ns
|
|
Timing Exception: Asynchronous Clock Groups
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock mlkem_clk rise edge)
|
|
0.000 0.000 r
|
|
clock source latency -1.947 -1.947
|
|
propagated clock network latency
|
|
1.558 -0.389
|
|
SLICE_X68Y88 RAMD32 0.000 -0.389 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_18_23/RAMC/CLK
|
|
SLICE_X68Y88 RAMD32 (Prop_ramd32_CLK_O)
|
|
0.485 0.096 f u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_18_23/RAMC/O
|
|
net (fo=1, routed) 0.543 0.639 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port10__3[22]
|
|
SLICE_X48Y88 FDRE f u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[22]/D
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock sys_clk rise edge) 0.000 0.000 r
|
|
clock source latency -1.848 -1.848
|
|
propagated clock network latency
|
|
1.238 -0.610
|
|
|
|
Slack: inf
|
|
Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_0_5/RAMB_D1/CLK
|
|
(rising edge-triggered cell RAMD32 clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns})
|
|
Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[3]/D
|
|
(rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Path Group: (none)
|
|
Path Type: Setup (Max at Fast Process Corner)
|
|
Data Path Delay: 1.026ns (logic 0.482ns (46.972%) route 0.544ns (53.028%))
|
|
Logic Levels: 0
|
|
Clock Path Skew: -0.221ns (DCD - SCD + CPR)
|
|
Destination Clock Delay (DCD): -0.610ns
|
|
Source Clock Delay (SCD): -0.389ns
|
|
Clock Pessimism Removal (CPR): 0.000ns
|
|
Clock Uncertainty: 0.222ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Discrete Jitter (DJ): 0.192ns
|
|
Phase Error (PE): 0.120ns
|
|
Timing Exception: Asynchronous Clock Groups
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock mlkem_clk rise edge)
|
|
0.000 0.000 r
|
|
clock source latency -1.947 -1.947
|
|
propagated clock network latency
|
|
1.558 -0.389
|
|
SLICE_X68Y89 RAMD32 0.000 -0.389 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_0_5/RAMB_D1/CLK
|
|
SLICE_X68Y89 RAMD32 (Prop_ramd32_CLK_O)
|
|
0.482 0.093 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_0_5/RAMB_D1/O
|
|
net (fo=1, routed) 0.544 0.637 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port10__3[3]
|
|
SLICE_X48Y88 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[3]/D
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock sys_clk rise edge) 0.000 0.000 r
|
|
clock source latency -1.848 -1.848
|
|
propagated clock network latency
|
|
1.238 -0.610
|
|
|
|
Slack: inf
|
|
Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_0_5/RAMB_D1/CLK
|
|
(rising edge-triggered cell RAMD32 clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns})
|
|
Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[3]/D
|
|
(rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Path Group: (none)
|
|
Path Type: Setup (Max at Fast Process Corner)
|
|
Data Path Delay: 1.026ns (logic 0.482ns (46.972%) route 0.544ns (53.028%))
|
|
Logic Levels: 0
|
|
Clock Path Skew: -0.221ns (DCD - SCD + CPR)
|
|
Destination Clock Delay (DCD): -0.610ns
|
|
Source Clock Delay (SCD): -0.389ns
|
|
Clock Pessimism Removal (CPR): 0.000ns
|
|
Clock Uncertainty: 0.222ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Discrete Jitter (DJ): 0.192ns
|
|
Phase Error (PE): 0.120ns
|
|
Timing Exception: Asynchronous Clock Groups
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock mlkem_clk rise edge)
|
|
0.000 0.000 r
|
|
clock source latency -1.947 -1.947
|
|
propagated clock network latency
|
|
1.558 -0.389
|
|
SLICE_X68Y89 RAMD32 0.000 -0.389 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_0_5/RAMB_D1/CLK
|
|
SLICE_X68Y89 RAMD32 (Prop_ramd32_CLK_O)
|
|
0.482 0.093 f u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_0_5/RAMB_D1/O
|
|
net (fo=1, routed) 0.544 0.637 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port10__3[3]
|
|
SLICE_X48Y88 FDRE f u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[3]/D
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock sys_clk rise edge) 0.000 0.000 r
|
|
clock source latency -1.848 -1.848
|
|
propagated clock network latency
|
|
1.238 -0.610
|
|
|
|
Slack: inf
|
|
Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_6_11/RAMB/CLK
|
|
(rising edge-triggered cell RAMD32 clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns})
|
|
Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[8]/D
|
|
(rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Path Group: (none)
|
|
Path Type: Setup (Max at Fast Process Corner)
|
|
Data Path Delay: 1.007ns (logic 0.491ns (48.781%) route 0.516ns (51.219%))
|
|
Logic Levels: 0
|
|
Clock Path Skew: -0.221ns (DCD - SCD + CPR)
|
|
Destination Clock Delay (DCD): -0.609ns
|
|
Source Clock Delay (SCD): -0.388ns
|
|
Clock Pessimism Removal (CPR): 0.000ns
|
|
Clock Uncertainty: 0.222ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Discrete Jitter (DJ): 0.192ns
|
|
Phase Error (PE): 0.120ns
|
|
Timing Exception: Asynchronous Clock Groups
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock mlkem_clk rise edge)
|
|
0.000 0.000 r
|
|
clock source latency -1.947 -1.947
|
|
propagated clock network latency
|
|
1.559 -0.388
|
|
SLICE_X68Y90 RAMD32 0.000 -0.388 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_6_11/RAMB/CLK
|
|
SLICE_X68Y90 RAMD32 (Prop_ramd32_CLK_O)
|
|
0.491 0.103 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_6_11/RAMB/O
|
|
net (fo=1, routed) 0.516 0.618 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port10__3[8]
|
|
SLICE_X46Y90 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[8]/D
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock sys_clk rise edge) 0.000 0.000 r
|
|
clock source latency -1.848 -1.848
|
|
propagated clock network latency
|
|
1.239 -0.609
|
|
|
|
Slack: inf
|
|
Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_6_11/RAMB/CLK
|
|
(rising edge-triggered cell RAMD32 clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns})
|
|
Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[8]/D
|
|
(rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Path Group: (none)
|
|
Path Type: Setup (Max at Fast Process Corner)
|
|
Data Path Delay: 1.007ns (logic 0.491ns (48.781%) route 0.516ns (51.219%))
|
|
Logic Levels: 0
|
|
Clock Path Skew: -0.221ns (DCD - SCD + CPR)
|
|
Destination Clock Delay (DCD): -0.609ns
|
|
Source Clock Delay (SCD): -0.388ns
|
|
Clock Pessimism Removal (CPR): 0.000ns
|
|
Clock Uncertainty: 0.222ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Discrete Jitter (DJ): 0.192ns
|
|
Phase Error (PE): 0.120ns
|
|
Timing Exception: Asynchronous Clock Groups
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock mlkem_clk rise edge)
|
|
0.000 0.000 r
|
|
clock source latency -1.947 -1.947
|
|
propagated clock network latency
|
|
1.559 -0.388
|
|
SLICE_X68Y90 RAMD32 0.000 -0.388 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_6_11/RAMB/CLK
|
|
SLICE_X68Y90 RAMD32 (Prop_ramd32_CLK_O)
|
|
0.491 0.103 f u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_6_11/RAMB/O
|
|
net (fo=1, routed) 0.516 0.618 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port10__3[8]
|
|
SLICE_X46Y90 FDRE f u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[8]/D
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock sys_clk rise edge) 0.000 0.000 r
|
|
clock source latency -1.848 -1.848
|
|
propagated clock network latency
|
|
1.239 -0.609
|
|
|
|
Slack: inf
|
|
Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_12_17/RAMC/CLK
|
|
(rising edge-triggered cell RAMD32 clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns})
|
|
Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[16]/D
|
|
(rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Path Group: (none)
|
|
Path Type: Setup (Max at Fast Process Corner)
|
|
Data Path Delay: 1.001ns (logic 0.485ns (48.445%) route 0.516ns (51.555%))
|
|
Logic Levels: 0
|
|
Clock Path Skew: -0.221ns (DCD - SCD + CPR)
|
|
Destination Clock Delay (DCD): -0.610ns
|
|
Source Clock Delay (SCD): -0.389ns
|
|
Clock Pessimism Removal (CPR): 0.000ns
|
|
Clock Uncertainty: 0.222ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Discrete Jitter (DJ): 0.192ns
|
|
Phase Error (PE): 0.120ns
|
|
Timing Exception: Asynchronous Clock Groups
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock mlkem_clk rise edge)
|
|
0.000 0.000 r
|
|
clock source latency -1.947 -1.947
|
|
propagated clock network latency
|
|
1.558 -0.389
|
|
SLICE_X66Y88 RAMD32 0.000 -0.389 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_12_17/RAMC/CLK
|
|
SLICE_X66Y88 RAMD32 (Prop_ramd32_CLK_O)
|
|
0.485 0.096 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_12_17/RAMC/O
|
|
net (fo=1, routed) 0.516 0.612 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port10__3[16]
|
|
SLICE_X50Y89 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[16]/D
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock sys_clk rise edge) 0.000 0.000 r
|
|
clock source latency -1.848 -1.848
|
|
propagated clock network latency
|
|
1.238 -0.610
|
|
|
|
Slack: inf
|
|
Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_12_17/RAMC/CLK
|
|
(rising edge-triggered cell RAMD32 clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns})
|
|
Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[16]/D
|
|
(rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Path Group: (none)
|
|
Path Type: Setup (Max at Fast Process Corner)
|
|
Data Path Delay: 1.001ns (logic 0.485ns (48.445%) route 0.516ns (51.555%))
|
|
Logic Levels: 0
|
|
Clock Path Skew: -0.221ns (DCD - SCD + CPR)
|
|
Destination Clock Delay (DCD): -0.610ns
|
|
Source Clock Delay (SCD): -0.389ns
|
|
Clock Pessimism Removal (CPR): 0.000ns
|
|
Clock Uncertainty: 0.222ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Discrete Jitter (DJ): 0.192ns
|
|
Phase Error (PE): 0.120ns
|
|
Timing Exception: Asynchronous Clock Groups
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock mlkem_clk rise edge)
|
|
0.000 0.000 r
|
|
clock source latency -1.947 -1.947
|
|
propagated clock network latency
|
|
1.558 -0.389
|
|
SLICE_X66Y88 RAMD32 0.000 -0.389 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_12_17/RAMC/CLK
|
|
SLICE_X66Y88 RAMD32 (Prop_ramd32_CLK_O)
|
|
0.485 0.096 f u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_12_17/RAMC/O
|
|
net (fo=1, routed) 0.516 0.612 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port10__3[16]
|
|
SLICE_X50Y89 FDRE f u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[16]/D
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock sys_clk rise edge) 0.000 0.000 r
|
|
clock source latency -1.848 -1.848
|
|
propagated clock network latency
|
|
1.238 -0.610
|
|
|
|
Slack: inf
|
|
Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_0_5/RAMC_D1/CLK
|
|
(rising edge-triggered cell RAMD32 clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns})
|
|
Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[5]/D
|
|
(rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Path Group: (none)
|
|
Path Type: Setup (Max at Fast Process Corner)
|
|
Data Path Delay: 0.998ns (logic 0.480ns (48.113%) route 0.518ns (51.887%))
|
|
Logic Levels: 0
|
|
Clock Path Skew: -0.220ns (DCD - SCD + CPR)
|
|
Destination Clock Delay (DCD): -0.609ns
|
|
Source Clock Delay (SCD): -0.389ns
|
|
Clock Pessimism Removal (CPR): 0.000ns
|
|
Clock Uncertainty: 0.222ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Discrete Jitter (DJ): 0.192ns
|
|
Phase Error (PE): 0.120ns
|
|
Timing Exception: Asynchronous Clock Groups
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock mlkem_clk rise edge)
|
|
0.000 0.000 r
|
|
clock source latency -1.947 -1.947
|
|
propagated clock network latency
|
|
1.558 -0.389
|
|
SLICE_X68Y89 RAMD32 0.000 -0.389 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_0_5/RAMC_D1/CLK
|
|
SLICE_X68Y89 RAMD32 (Prop_ramd32_CLK_O)
|
|
0.480 0.091 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_0_5/RAMC_D1/O
|
|
net (fo=1, routed) 0.518 0.608 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port10__3[5]
|
|
SLICE_X50Y90 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[5]/D
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock sys_clk rise edge) 0.000 0.000 r
|
|
clock source latency -1.848 -1.848
|
|
propagated clock network latency
|
|
1.239 -0.609
|
|
|
|
Slack: inf
|
|
Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_0_5/RAMC_D1/CLK
|
|
(rising edge-triggered cell RAMD32 clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns})
|
|
Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[5]/D
|
|
(rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Path Group: (none)
|
|
Path Type: Setup (Max at Fast Process Corner)
|
|
Data Path Delay: 0.998ns (logic 0.480ns (48.113%) route 0.518ns (51.887%))
|
|
Logic Levels: 0
|
|
Clock Path Skew: -0.220ns (DCD - SCD + CPR)
|
|
Destination Clock Delay (DCD): -0.609ns
|
|
Source Clock Delay (SCD): -0.389ns
|
|
Clock Pessimism Removal (CPR): 0.000ns
|
|
Clock Uncertainty: 0.222ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Discrete Jitter (DJ): 0.192ns
|
|
Phase Error (PE): 0.120ns
|
|
Timing Exception: Asynchronous Clock Groups
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock mlkem_clk rise edge)
|
|
0.000 0.000 r
|
|
clock source latency -1.947 -1.947
|
|
propagated clock network latency
|
|
1.558 -0.389
|
|
SLICE_X68Y89 RAMD32 0.000 -0.389 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_0_5/RAMC_D1/CLK
|
|
SLICE_X68Y89 RAMD32 (Prop_ramd32_CLK_O)
|
|
0.480 0.091 f u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_0_5/RAMC_D1/O
|
|
net (fo=1, routed) 0.518 0.608 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port10__3[5]
|
|
SLICE_X50Y90 FDRE f u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[5]/D
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock sys_clk rise edge) 0.000 0.000 r
|
|
clock source latency -1.848 -1.848
|
|
propagated clock network latency
|
|
1.239 -0.609
|
|
|
|
Slack: inf
|
|
Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_0_5/RAMB/CLK
|
|
(rising edge-triggered cell RAMD32 clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns})
|
|
Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[2]/D
|
|
(rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Path Group: (none)
|
|
Path Type: Setup (Max at Fast Process Corner)
|
|
Data Path Delay: 0.998ns (logic 0.491ns (49.223%) route 0.507ns (50.777%))
|
|
Logic Levels: 0
|
|
Clock Path Skew: -0.221ns (DCD - SCD + CPR)
|
|
Destination Clock Delay (DCD): -0.610ns
|
|
Source Clock Delay (SCD): -0.389ns
|
|
Clock Pessimism Removal (CPR): 0.000ns
|
|
Clock Uncertainty: 0.222ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Discrete Jitter (DJ): 0.192ns
|
|
Phase Error (PE): 0.120ns
|
|
Timing Exception: Asynchronous Clock Groups
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock mlkem_clk rise edge)
|
|
0.000 0.000 r
|
|
clock source latency -1.947 -1.947
|
|
propagated clock network latency
|
|
1.558 -0.389
|
|
SLICE_X68Y89 RAMD32 0.000 -0.389 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_0_5/RAMB/CLK
|
|
SLICE_X68Y89 RAMD32 (Prop_ramd32_CLK_O)
|
|
0.491 0.102 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_0_5/RAMB/O
|
|
net (fo=1, routed) 0.507 0.608 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port10__3[2]
|
|
SLICE_X50Y89 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[2]/D
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock sys_clk rise edge) 0.000 0.000 r
|
|
clock source latency -1.848 -1.848
|
|
propagated clock network latency
|
|
1.238 -0.610
|
|
|
|
Slack: inf
|
|
Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_0_5/RAMB/CLK
|
|
(rising edge-triggered cell RAMD32 clocked by mlkem_clk {rise@0.000ns fall@6.500ns period=13.000ns})
|
|
Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[2]/D
|
|
(rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Path Group: (none)
|
|
Path Type: Setup (Max at Fast Process Corner)
|
|
Data Path Delay: 0.998ns (logic 0.491ns (49.223%) route 0.507ns (50.777%))
|
|
Logic Levels: 0
|
|
Clock Path Skew: -0.221ns (DCD - SCD + CPR)
|
|
Destination Clock Delay (DCD): -0.610ns
|
|
Source Clock Delay (SCD): -0.389ns
|
|
Clock Pessimism Removal (CPR): 0.000ns
|
|
Clock Uncertainty: 0.222ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Discrete Jitter (DJ): 0.192ns
|
|
Phase Error (PE): 0.120ns
|
|
Timing Exception: Asynchronous Clock Groups
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock mlkem_clk rise edge)
|
|
0.000 0.000 r
|
|
clock source latency -1.947 -1.947
|
|
propagated clock network latency
|
|
1.558 -0.389
|
|
SLICE_X68Y89 RAMD32 0.000 -0.389 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_0_5/RAMB/CLK
|
|
SLICE_X68Y89 RAMD32 (Prop_ramd32_CLK_O)
|
|
0.491 0.102 f u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_0_5/RAMB/O
|
|
net (fo=1, routed) 0.507 0.608 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port10__3[2]
|
|
SLICE_X50Y89 FDRE f u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[2]/D
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock sys_clk rise edge) 0.000 0.000 r
|
|
clock source latency -1.848 -1.848
|
|
propagated clock network latency
|
|
1.238 -0.610
|
|
|
|
|
|
|
|
|