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FallenSigh a2b496ca8d Restore timing + switch to polling + disable CPU interrupts (IE=0)

2026-06-26 01:01:48 +08:00

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convert.c

Initial commit: Loongson FPGA SoC project for 2026 CIC-IEC

2026-06-23 01:22:45 +08:00

script.lds

Initial commit: Loongson FPGA SoC project for 2026 CIC-IEC

2026-06-23 01:22:45 +08:00

start.S

Restore timing + switch to polling + disable CPU interrupts (IE=0)

2026-06-26 01:01:48 +08:00

trap_handler.S

Restore timing + switch to polling + disable CPU interrupts (IE=0)

2026-06-26 01:01:48 +08:00