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FallenSigh db2ad12dbb Add verilator pragma to suppress BLKLOOPINIT in DelayBuffer.v

2026-06-24 20:41:52 +08:00

..

axi_fft_wrapper.v

Initial commit: Loongson FPGA SoC project for 2026 CIC-IEC

2026-06-23 01:22:45 +08:00

Butterfly.v

Initial commit: Loongson FPGA SoC project for 2026 CIC-IEC

2026-06-23 01:22:45 +08:00

DelayBuffer.v

Add verilator pragma to suppress BLKLOOPINIT in DelayBuffer.v

2026-06-24 20:41:52 +08:00

FFT1024_32B.v

Initial commit: Loongson FPGA SoC project for 2026 CIC-IEC

2026-06-23 01:22:45 +08:00

Multiply.v

Initial commit: Loongson FPGA SoC project for 2026 CIC-IEC

2026-06-23 01:22:45 +08:00

SdfUnit.v

Initial commit: Loongson FPGA SoC project for 2026 CIC-IEC

2026-06-23 01:22:45 +08:00

Twiddle1024_32B.v

Initial commit: Loongson FPGA SoC project for 2026 CIC-IEC

2026-06-23 01:22:45 +08:00