FallenSigh
542495cb52
Verilator does not recognize UNUSEDPARAM or UNUSEDSIGNAL. Correct suppression code is UNUSED.
24 lines
1.2 KiB
Verilog
24 lines
1.2 KiB
Verilog
// Copyright 1986-2019 Xilinx, Inc. All Rights Reserved.
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// --------------------------------------------------------------------------------
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// Tool Version: Vivado v.2019.2 (lin64) Build 2708876 Wed Nov 6 21:39:14 MST 2019
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// Date : Tue Jun 30 01:14:25 2026
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// Host : fedora running 64-bit unknown
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// Command : write_verilog -force -mode synth_stub
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// /home/fallensigh/Dev/ciciec2026_loongson_regional/rtl/ip/PLL_2019_2/clk_pll_stub.v
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// Design : clk_pll
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// Purpose : Stub declaration of top-level module interface
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// Device : xc7a200tfbg676-1
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// --------------------------------------------------------------------------------
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// This empty module with port declaration file causes synthesis tools to infer a black box for IP.
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// The synthesis directives are for Synopsys Synplify support to prevent IO buffer insertion.
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// Please paste the declaration into a Verilog source file or add the file as an additional source.
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module clk_pll(cpu_clk, sys_clk, resetn, locked, clk_in1)
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/* synthesis syn_black_box black_box_pad_pin="cpu_clk,sys_clk,resetn,locked,clk_in1" */;
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output cpu_clk;
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output sys_clk;
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input resetn;
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output locked;
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input clk_in1;
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endmodule
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