1654 lines
146 KiB
Plaintext
1654 lines
146 KiB
Plaintext
Copyright 1986-2019 Xilinx, Inc. All Rights Reserved.
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| Tool Version : Vivado v.2019.2 (lin64) Build 2708876 Wed Nov 6 21:39:14 MST 2019
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| Date : Wed Jul 8 02:57:49 2026
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| Host : fedora running 64-bit unknown
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| Command : report_methodology -file /home/fallensigh/vivado_reports_withdsp/methodology.rpt
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| Design : soc_top
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| Device : xc7a200tfbg676-1
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| Speed File : -1
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| Design State : Fully Routed
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--------------------------------------------------------------------------------------------------
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Report Methodology
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Table of Contents
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-----------------
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1. REPORT SUMMARY
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2. REPORT DETAILS
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1. REPORT SUMMARY
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-----------------
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Netlist: netlist
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Floorplan: impl_1
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Design limits: <entire design considered>
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Max violations: <unlimited>
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Violations found: 321
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+-----------+----------+-------------------------------------------------------------------+------------+
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| Rule | Severity | Description | Violations |
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+-----------+----------+-------------------------------------------------------------------+------------+
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| DPIR-1 | Warning | Asynchronous driver check | 207 |
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| LUTAR-1 | Warning | LUT drives async reset alert | 1 |
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| SYNTH-5 | Warning | Mapped onto distributed RAM because of timing constraints | 8 |
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| SYNTH-10 | Warning | Wide multiplier | 16 |
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| SYNTH-16 | Warning | Address collision | 8 |
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| TIMING-10 | Warning | Missing property on synchronizer | 1 |
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| TIMING-18 | Warning | Missing input or output delay | 76 |
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| TIMING-47 | Warning | False path or asynchronous clock group between synchronous clocks | 2 |
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| XDCC-1 | Warning | Scoped Clock constraint overwritten with the same name | 1 |
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| XDCC-7 | Warning | Scoped Clock constraint overwritten on the same source | 1 |
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+-----------+----------+-------------------------------------------------------------------+------------+
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2. REPORT DETAILS
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-----------------
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DPIR-1#1 Warning
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Asynchronous driver check
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DSP u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/comp_q_mul_q_s40 input pin u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/comp_q_mul_q_s40/A[0] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.
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Related violations: <none>
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DPIR-1#2 Warning
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Asynchronous driver check
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DSP u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/comp_q_mul_q_s40 input pin u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/comp_q_mul_q_s40/A[10] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.
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Related violations: <none>
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DPIR-1#3 Warning
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Asynchronous driver check
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DSP u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/comp_q_mul_q_s40 input pin u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/comp_q_mul_q_s40/A[11] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.
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Related violations: <none>
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DPIR-1#4 Warning
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Asynchronous driver check
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DSP u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/comp_q_mul_q_s40 input pin u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/comp_q_mul_q_s40/A[12] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.
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Related violations: <none>
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DPIR-1#5 Warning
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Asynchronous driver check
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DSP u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/comp_q_mul_q_s40 input pin u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/comp_q_mul_q_s40/A[1] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.
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Related violations: <none>
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DPIR-1#6 Warning
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Asynchronous driver check
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DSP u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/comp_q_mul_q_s40 input pin u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/comp_q_mul_q_s40/A[2] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.
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Related violations: <none>
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DPIR-1#7 Warning
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Asynchronous driver check
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DSP u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/comp_q_mul_q_s40 input pin u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/comp_q_mul_q_s40/A[3] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.
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Related violations: <none>
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DPIR-1#8 Warning
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Asynchronous driver check
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DSP u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/comp_q_mul_q_s40 input pin u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/comp_q_mul_q_s40/A[4] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.
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Related violations: <none>
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DPIR-1#9 Warning
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Asynchronous driver check
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DSP u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/comp_q_mul_q_s40 input pin u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/comp_q_mul_q_s40/A[5] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.
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Related violations: <none>
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DPIR-1#10 Warning
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Asynchronous driver check
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DSP u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/comp_q_mul_q_s40 input pin u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/comp_q_mul_q_s40/A[6] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.
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Related violations: <none>
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DPIR-1#11 Warning
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Asynchronous driver check
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DSP u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/comp_q_mul_q_s40 input pin u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/comp_q_mul_q_s40/A[7] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.
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Related violations: <none>
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DPIR-1#12 Warning
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Asynchronous driver check
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DSP u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/comp_q_mul_q_s40 input pin u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/comp_q_mul_q_s40/A[8] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.
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Related violations: <none>
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DPIR-1#13 Warning
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Asynchronous driver check
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DSP u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/comp_q_mul_q_s40 input pin u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/comp_q_mul_q_s40/A[9] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.
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Related violations: <none>
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DPIR-1#14 Warning
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Asynchronous driver check
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DSP u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/comp_qprod_est_s20 input pin u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/comp_qprod_est_s20/A[0] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.
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Related violations: <none>
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DPIR-1#15 Warning
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Asynchronous driver check
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DSP u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/comp_qprod_est_s20 input pin u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/comp_qprod_est_s20/A[10] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.
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Related violations: <none>
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DPIR-1#16 Warning
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Asynchronous driver check
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DSP u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/comp_qprod_est_s20 input pin u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/comp_qprod_est_s20/A[11] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.
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Related violations: <none>
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DPIR-1#17 Warning
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Asynchronous driver check
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DSP u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/comp_qprod_est_s20 input pin u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/comp_qprod_est_s20/A[12] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.
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Related violations: <none>
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DPIR-1#18 Warning
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Asynchronous driver check
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DSP u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/comp_qprod_est_s20 input pin u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/comp_qprod_est_s20/A[13] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.
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Related violations: <none>
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DPIR-1#19 Warning
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Asynchronous driver check
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DSP u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/comp_qprod_est_s20 input pin u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/comp_qprod_est_s20/A[14] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.
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Related violations: <none>
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DPIR-1#20 Warning
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Asynchronous driver check
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DSP u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/comp_qprod_est_s20 input pin u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/comp_qprod_est_s20/A[15] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.
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Related violations: <none>
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DPIR-1#21 Warning
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Asynchronous driver check
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DSP u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/comp_qprod_est_s20 input pin u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/comp_qprod_est_s20/A[16] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.
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Related violations: <none>
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DPIR-1#22 Warning
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Asynchronous driver check
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DSP u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/comp_qprod_est_s20 input pin u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/comp_qprod_est_s20/A[17] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.
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Related violations: <none>
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DPIR-1#23 Warning
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Asynchronous driver check
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DSP u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/comp_qprod_est_s20 input pin u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/comp_qprod_est_s20/A[18] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.
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Related violations: <none>
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DPIR-1#24 Warning
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Asynchronous driver check
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DSP u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/comp_qprod_est_s20 input pin u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/comp_qprod_est_s20/A[19] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.
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Related violations: <none>
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DPIR-1#25 Warning
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Asynchronous driver check
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DSP u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/comp_qprod_est_s20 input pin u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/comp_qprod_est_s20/A[1] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.
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Related violations: <none>
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DPIR-1#26 Warning
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Asynchronous driver check
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DSP u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/comp_qprod_est_s20 input pin u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/comp_qprod_est_s20/A[20] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.
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Related violations: <none>
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DPIR-1#27 Warning
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Asynchronous driver check
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DSP u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/comp_qprod_est_s20 input pin u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/comp_qprod_est_s20/A[21] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.
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Related violations: <none>
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DPIR-1#28 Warning
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Asynchronous driver check
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DSP u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/comp_qprod_est_s20 input pin u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/comp_qprod_est_s20/A[22] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.
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Related violations: <none>
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DPIR-1#29 Warning
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Asynchronous driver check
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DSP u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/comp_qprod_est_s20 input pin u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/comp_qprod_est_s20/A[23] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.
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Related violations: <none>
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DPIR-1#30 Warning
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Asynchronous driver check
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DSP u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/comp_qprod_est_s20 input pin u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/comp_qprod_est_s20/A[2] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.
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Related violations: <none>
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DPIR-1#31 Warning
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Asynchronous driver check
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DSP u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/comp_qprod_est_s20 input pin u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/comp_qprod_est_s20/A[3] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.
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Related violations: <none>
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DPIR-1#32 Warning
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Asynchronous driver check
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DSP u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/comp_qprod_est_s20 input pin u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/comp_qprod_est_s20/A[4] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.
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Related violations: <none>
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DPIR-1#33 Warning
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Asynchronous driver check
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DSP u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/comp_qprod_est_s20 input pin u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/comp_qprod_est_s20/A[5] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.
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Related violations: <none>
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DPIR-1#34 Warning
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Asynchronous driver check
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DSP u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/comp_qprod_est_s20 input pin u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/comp_qprod_est_s20/A[6] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.
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|
Related violations: <none>
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|
|
|
DPIR-1#35 Warning
|
|
Asynchronous driver check
|
|
DSP u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/comp_qprod_est_s20 input pin u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/comp_qprod_est_s20/A[7] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.
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|
Related violations: <none>
|
|
|
|
DPIR-1#36 Warning
|
|
Asynchronous driver check
|
|
DSP u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/comp_qprod_est_s20 input pin u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/comp_qprod_est_s20/A[8] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.
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|
Related violations: <none>
|
|
|
|
DPIR-1#37 Warning
|
|
Asynchronous driver check
|
|
DSP u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/comp_qprod_est_s20 input pin u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/comp_qprod_est_s20/A[9] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.
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|
Related violations: <none>
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|
|
|
DPIR-1#38 Warning
|
|
Asynchronous driver check
|
|
DSP u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/decomp_round_next input pin u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/decomp_round_next/A[0] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.
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|
Related violations: <none>
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|
|
|
DPIR-1#39 Warning
|
|
Asynchronous driver check
|
|
DSP u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/decomp_round_next input pin u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/decomp_round_next/A[10] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.
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|
Related violations: <none>
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|
|
|
DPIR-1#40 Warning
|
|
Asynchronous driver check
|
|
DSP u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/decomp_round_next input pin u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/decomp_round_next/A[11] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.
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|
Related violations: <none>
|
|
|
|
DPIR-1#41 Warning
|
|
Asynchronous driver check
|
|
DSP u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/decomp_round_next input pin u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/decomp_round_next/A[1] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.
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|
Related violations: <none>
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|
|
|
DPIR-1#42 Warning
|
|
Asynchronous driver check
|
|
DSP u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/decomp_round_next input pin u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/decomp_round_next/A[2] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.
|
|
Related violations: <none>
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|
|
|
DPIR-1#43 Warning
|
|
Asynchronous driver check
|
|
DSP u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/decomp_round_next input pin u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/decomp_round_next/A[3] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.
|
|
Related violations: <none>
|
|
|
|
DPIR-1#44 Warning
|
|
Asynchronous driver check
|
|
DSP u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/decomp_round_next input pin u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/decomp_round_next/A[4] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.
|
|
Related violations: <none>
|
|
|
|
DPIR-1#45 Warning
|
|
Asynchronous driver check
|
|
DSP u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/decomp_round_next input pin u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/decomp_round_next/A[5] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.
|
|
Related violations: <none>
|
|
|
|
DPIR-1#46 Warning
|
|
Asynchronous driver check
|
|
DSP u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/decomp_round_next input pin u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/decomp_round_next/A[6] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.
|
|
Related violations: <none>
|
|
|
|
DPIR-1#47 Warning
|
|
Asynchronous driver check
|
|
DSP u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/decomp_round_next input pin u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/decomp_round_next/A[7] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.
|
|
Related violations: <none>
|
|
|
|
DPIR-1#48 Warning
|
|
Asynchronous driver check
|
|
DSP u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/decomp_round_next input pin u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/decomp_round_next/A[8] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.
|
|
Related violations: <none>
|
|
|
|
DPIR-1#49 Warning
|
|
Asynchronous driver check
|
|
DSP u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/decomp_round_next input pin u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/decomp_round_next/A[9] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.
|
|
Related violations: <none>
|
|
|
|
DPIR-1#50 Warning
|
|
Asynchronous driver check
|
|
DSP u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/qprod_s40 input pin u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/qprod_s40/A[0] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.
|
|
Related violations: <none>
|
|
|
|
DPIR-1#51 Warning
|
|
Asynchronous driver check
|
|
DSP u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/qprod_s40 input pin u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/qprod_s40/A[10] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.
|
|
Related violations: <none>
|
|
|
|
DPIR-1#52 Warning
|
|
Asynchronous driver check
|
|
DSP u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/qprod_s40 input pin u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/qprod_s40/A[11] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.
|
|
Related violations: <none>
|
|
|
|
DPIR-1#53 Warning
|
|
Asynchronous driver check
|
|
DSP u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/qprod_s40 input pin u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/qprod_s40/A[12] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.
|
|
Related violations: <none>
|
|
|
|
DPIR-1#54 Warning
|
|
Asynchronous driver check
|
|
DSP u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/qprod_s40 input pin u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/qprod_s40/A[1] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.
|
|
Related violations: <none>
|
|
|
|
DPIR-1#55 Warning
|
|
Asynchronous driver check
|
|
DSP u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/qprod_s40 input pin u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/qprod_s40/A[2] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.
|
|
Related violations: <none>
|
|
|
|
DPIR-1#56 Warning
|
|
Asynchronous driver check
|
|
DSP u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/qprod_s40 input pin u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/qprod_s40/A[3] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.
|
|
Related violations: <none>
|
|
|
|
DPIR-1#57 Warning
|
|
Asynchronous driver check
|
|
DSP u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/qprod_s40 input pin u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/qprod_s40/A[4] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.
|
|
Related violations: <none>
|
|
|
|
DPIR-1#58 Warning
|
|
Asynchronous driver check
|
|
DSP u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/qprod_s40 input pin u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/qprod_s40/A[5] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.
|
|
Related violations: <none>
|
|
|
|
DPIR-1#59 Warning
|
|
Asynchronous driver check
|
|
DSP u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/qprod_s40 input pin u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/qprod_s40/A[6] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.
|
|
Related violations: <none>
|
|
|
|
DPIR-1#60 Warning
|
|
Asynchronous driver check
|
|
DSP u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/qprod_s40 input pin u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/qprod_s40/A[7] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.
|
|
Related violations: <none>
|
|
|
|
DPIR-1#61 Warning
|
|
Asynchronous driver check
|
|
DSP u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/qprod_s40 input pin u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/qprod_s40/A[8] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.
|
|
Related violations: <none>
|
|
|
|
DPIR-1#62 Warning
|
|
Asynchronous driver check
|
|
DSP u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/qprod_s40 input pin u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/qprod_s40/A[9] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.
|
|
Related violations: <none>
|
|
|
|
DPIR-1#63 Warning
|
|
Asynchronous driver check
|
|
DSP u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_scl/p_s10 input pin u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_scl/p_s10/A[0] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.
|
|
Related violations: <none>
|
|
|
|
DPIR-1#64 Warning
|
|
Asynchronous driver check
|
|
DSP u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_scl/p_s10 input pin u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_scl/p_s10/A[10] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.
|
|
Related violations: <none>
|
|
|
|
DPIR-1#65 Warning
|
|
Asynchronous driver check
|
|
DSP u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_scl/p_s10 input pin u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_scl/p_s10/A[11] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.
|
|
Related violations: <none>
|
|
|
|
DPIR-1#66 Warning
|
|
Asynchronous driver check
|
|
DSP u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_scl/p_s10 input pin u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_scl/p_s10/A[1] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.
|
|
Related violations: <none>
|
|
|
|
DPIR-1#67 Warning
|
|
Asynchronous driver check
|
|
DSP u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_scl/p_s10 input pin u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_scl/p_s10/A[2] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.
|
|
Related violations: <none>
|
|
|
|
DPIR-1#68 Warning
|
|
Asynchronous driver check
|
|
DSP u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_scl/p_s10 input pin u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_scl/p_s10/A[3] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.
|
|
Related violations: <none>
|
|
|
|
DPIR-1#69 Warning
|
|
Asynchronous driver check
|
|
DSP u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_scl/p_s10 input pin u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_scl/p_s10/A[4] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.
|
|
Related violations: <none>
|
|
|
|
DPIR-1#70 Warning
|
|
Asynchronous driver check
|
|
DSP u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_scl/p_s10 input pin u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_scl/p_s10/A[5] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.
|
|
Related violations: <none>
|
|
|
|
DPIR-1#71 Warning
|
|
Asynchronous driver check
|
|
DSP u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_scl/p_s10 input pin u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_scl/p_s10/A[6] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.
|
|
Related violations: <none>
|
|
|
|
DPIR-1#72 Warning
|
|
Asynchronous driver check
|
|
DSP u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_scl/p_s10 input pin u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_scl/p_s10/A[7] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.
|
|
Related violations: <none>
|
|
|
|
DPIR-1#73 Warning
|
|
Asynchronous driver check
|
|
DSP u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_scl/p_s10 input pin u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_scl/p_s10/A[8] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.
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|
Related violations: <none>
|
|
|
|
DPIR-1#74 Warning
|
|
Asynchronous driver check
|
|
DSP u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_scl/p_s10 input pin u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_scl/p_s10/A[9] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.
|
|
Related violations: <none>
|
|
|
|
DPIR-1#75 Warning
|
|
Asynchronous driver check
|
|
DSP u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_scl/qprod_s40 input pin u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_scl/qprod_s40/A[0] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.
|
|
Related violations: <none>
|
|
|
|
DPIR-1#76 Warning
|
|
Asynchronous driver check
|
|
DSP u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_scl/qprod_s40 input pin u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_scl/qprod_s40/A[10] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.
|
|
Related violations: <none>
|
|
|
|
DPIR-1#77 Warning
|
|
Asynchronous driver check
|
|
DSP u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_scl/qprod_s40 input pin u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_scl/qprod_s40/A[11] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.
|
|
Related violations: <none>
|
|
|
|
DPIR-1#78 Warning
|
|
Asynchronous driver check
|
|
DSP u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_scl/qprod_s40 input pin u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_scl/qprod_s40/A[12] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.
|
|
Related violations: <none>
|
|
|
|
DPIR-1#79 Warning
|
|
Asynchronous driver check
|
|
DSP u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_scl/qprod_s40 input pin u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_scl/qprod_s40/A[1] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.
|
|
Related violations: <none>
|
|
|
|
DPIR-1#80 Warning
|
|
Asynchronous driver check
|
|
DSP u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_scl/qprod_s40 input pin u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_scl/qprod_s40/A[2] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.
|
|
Related violations: <none>
|
|
|
|
DPIR-1#81 Warning
|
|
Asynchronous driver check
|
|
DSP u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_scl/qprod_s40 input pin u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_scl/qprod_s40/A[3] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.
|
|
Related violations: <none>
|
|
|
|
DPIR-1#82 Warning
|
|
Asynchronous driver check
|
|
DSP u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_scl/qprod_s40 input pin u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_scl/qprod_s40/A[4] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.
|
|
Related violations: <none>
|
|
|
|
DPIR-1#83 Warning
|
|
Asynchronous driver check
|
|
DSP u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_scl/qprod_s40 input pin u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_scl/qprod_s40/A[5] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.
|
|
Related violations: <none>
|
|
|
|
DPIR-1#84 Warning
|
|
Asynchronous driver check
|
|
DSP u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_scl/qprod_s40 input pin u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_scl/qprod_s40/A[6] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.
|
|
Related violations: <none>
|
|
|
|
DPIR-1#85 Warning
|
|
Asynchronous driver check
|
|
DSP u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_scl/qprod_s40 input pin u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_scl/qprod_s40/A[7] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.
|
|
Related violations: <none>
|
|
|
|
DPIR-1#86 Warning
|
|
Asynchronous driver check
|
|
DSP u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_scl/qprod_s40 input pin u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_scl/qprod_s40/A[8] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.
|
|
Related violations: <none>
|
|
|
|
DPIR-1#87 Warning
|
|
Asynchronous driver check
|
|
DSP u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_scl/qprod_s40 input pin u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_scl/qprod_s40/A[9] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.
|
|
Related violations: <none>
|
|
|
|
DPIR-1#88 Warning
|
|
Asynchronous driver check
|
|
DSP u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/u_bc/p0 input pin u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/u_bc/p0/A[0] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.
|
|
Related violations: <none>
|
|
|
|
DPIR-1#89 Warning
|
|
Asynchronous driver check
|
|
DSP u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/u_bc/p0 input pin u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/u_bc/p0/A[10] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.
|
|
Related violations: <none>
|
|
|
|
DPIR-1#90 Warning
|
|
Asynchronous driver check
|
|
DSP u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/u_bc/p0 input pin u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/u_bc/p0/A[11] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.
|
|
Related violations: <none>
|
|
|
|
DPIR-1#91 Warning
|
|
Asynchronous driver check
|
|
DSP u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/u_bc/p0 input pin u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/u_bc/p0/A[1] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.
|
|
Related violations: <none>
|
|
|
|
DPIR-1#92 Warning
|
|
Asynchronous driver check
|
|
DSP u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/u_bc/p0 input pin u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/u_bc/p0/A[2] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.
|
|
Related violations: <none>
|
|
|
|
DPIR-1#93 Warning
|
|
Asynchronous driver check
|
|
DSP u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/u_bc/p0 input pin u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/u_bc/p0/A[3] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.
|
|
Related violations: <none>
|
|
|
|
DPIR-1#94 Warning
|
|
Asynchronous driver check
|
|
DSP u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/u_bc/p0 input pin u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/u_bc/p0/A[4] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.
|
|
Related violations: <none>
|
|
|
|
DPIR-1#95 Warning
|
|
Asynchronous driver check
|
|
DSP u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/u_bc/p0 input pin u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/u_bc/p0/A[5] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.
|
|
Related violations: <none>
|
|
|
|
DPIR-1#96 Warning
|
|
Asynchronous driver check
|
|
DSP u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/u_bc/p0 input pin u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/u_bc/p0/A[6] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.
|
|
Related violations: <none>
|
|
|
|
DPIR-1#97 Warning
|
|
Asynchronous driver check
|
|
DSP u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/u_bc/p0 input pin u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/u_bc/p0/A[7] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.
|
|
Related violations: <none>
|
|
|
|
DPIR-1#98 Warning
|
|
Asynchronous driver check
|
|
DSP u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/u_bc/p0 input pin u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/u_bc/p0/A[8] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.
|
|
Related violations: <none>
|
|
|
|
DPIR-1#99 Warning
|
|
Asynchronous driver check
|
|
DSP u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/u_bc/p0 input pin u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/u_bc/p0/A[9] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.
|
|
Related violations: <none>
|
|
|
|
DPIR-1#100 Warning
|
|
Asynchronous driver check
|
|
DSP u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/u_bc/p0 input pin u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/u_bc/p0/B[0] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.
|
|
Related violations: <none>
|
|
|
|
DPIR-1#101 Warning
|
|
Asynchronous driver check
|
|
DSP u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/u_bc/p0 input pin u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/u_bc/p0/B[10] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.
|
|
Related violations: <none>
|
|
|
|
DPIR-1#102 Warning
|
|
Asynchronous driver check
|
|
DSP u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/u_bc/p0 input pin u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/u_bc/p0/B[11] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.
|
|
Related violations: <none>
|
|
|
|
DPIR-1#103 Warning
|
|
Asynchronous driver check
|
|
DSP u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/u_bc/p0 input pin u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/u_bc/p0/B[1] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.
|
|
Related violations: <none>
|
|
|
|
DPIR-1#104 Warning
|
|
Asynchronous driver check
|
|
DSP u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/u_bc/p0 input pin u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/u_bc/p0/B[2] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.
|
|
Related violations: <none>
|
|
|
|
DPIR-1#105 Warning
|
|
Asynchronous driver check
|
|
DSP u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/u_bc/p0 input pin u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/u_bc/p0/B[3] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.
|
|
Related violations: <none>
|
|
|
|
DPIR-1#106 Warning
|
|
Asynchronous driver check
|
|
DSP u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/u_bc/p0 input pin u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/u_bc/p0/B[4] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.
|
|
Related violations: <none>
|
|
|
|
DPIR-1#107 Warning
|
|
Asynchronous driver check
|
|
DSP u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/u_bc/p0 input pin u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/u_bc/p0/B[5] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.
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|
Related violations: <none>
|
|
|
|
DPIR-1#108 Warning
|
|
Asynchronous driver check
|
|
DSP u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/u_bc/p0 input pin u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/u_bc/p0/B[6] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.
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|
Related violations: <none>
|
|
|
|
DPIR-1#109 Warning
|
|
Asynchronous driver check
|
|
DSP u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/u_bc/p0 input pin u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/u_bc/p0/B[7] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.
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|
Related violations: <none>
|
|
|
|
DPIR-1#110 Warning
|
|
Asynchronous driver check
|
|
DSP u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/u_bc/p0 input pin u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/u_bc/p0/B[8] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.
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|
Related violations: <none>
|
|
|
|
DPIR-1#111 Warning
|
|
Asynchronous driver check
|
|
DSP u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/u_bc/p0 input pin u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/u_bc/p0/B[9] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.
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|
Related violations: <none>
|
|
|
|
DPIR-1#112 Warning
|
|
Asynchronous driver check
|
|
DSP u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/u_bc/p0__0 input pin u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/u_bc/p0__0/A[0] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.
|
|
Related violations: <none>
|
|
|
|
DPIR-1#113 Warning
|
|
Asynchronous driver check
|
|
DSP u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/u_bc/p0__0 input pin u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/u_bc/p0__0/A[10] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.
|
|
Related violations: <none>
|
|
|
|
DPIR-1#114 Warning
|
|
Asynchronous driver check
|
|
DSP u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/u_bc/p0__0 input pin u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/u_bc/p0__0/A[11] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.
|
|
Related violations: <none>
|
|
|
|
DPIR-1#115 Warning
|
|
Asynchronous driver check
|
|
DSP u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/u_bc/p0__0 input pin u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/u_bc/p0__0/A[1] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.
|
|
Related violations: <none>
|
|
|
|
DPIR-1#116 Warning
|
|
Asynchronous driver check
|
|
DSP u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/u_bc/p0__0 input pin u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/u_bc/p0__0/A[2] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.
|
|
Related violations: <none>
|
|
|
|
DPIR-1#117 Warning
|
|
Asynchronous driver check
|
|
DSP u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/u_bc/p0__0 input pin u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/u_bc/p0__0/A[3] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.
|
|
Related violations: <none>
|
|
|
|
DPIR-1#118 Warning
|
|
Asynchronous driver check
|
|
DSP u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/u_bc/p0__0 input pin u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/u_bc/p0__0/A[4] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.
|
|
Related violations: <none>
|
|
|
|
DPIR-1#119 Warning
|
|
Asynchronous driver check
|
|
DSP u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/u_bc/p0__0 input pin u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/u_bc/p0__0/A[5] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.
|
|
Related violations: <none>
|
|
|
|
DPIR-1#120 Warning
|
|
Asynchronous driver check
|
|
DSP u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/u_bc/p0__0 input pin u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/u_bc/p0__0/A[6] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.
|
|
Related violations: <none>
|
|
|
|
DPIR-1#121 Warning
|
|
Asynchronous driver check
|
|
DSP u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/u_bc/p0__0 input pin u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/u_bc/p0__0/A[7] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.
|
|
Related violations: <none>
|
|
|
|
DPIR-1#122 Warning
|
|
Asynchronous driver check
|
|
DSP u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/u_bc/p0__0 input pin u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/u_bc/p0__0/A[8] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.
|
|
Related violations: <none>
|
|
|
|
DPIR-1#123 Warning
|
|
Asynchronous driver check
|
|
DSP u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/u_bc/p0__0 input pin u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/u_bc/p0__0/A[9] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.
|
|
Related violations: <none>
|
|
|
|
DPIR-1#124 Warning
|
|
Asynchronous driver check
|
|
DSP u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/u_bc/p0__0 input pin u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/u_bc/p0__0/B[0] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.
|
|
Related violations: <none>
|
|
|
|
DPIR-1#125 Warning
|
|
Asynchronous driver check
|
|
DSP u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/u_bc/p0__0 input pin u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/u_bc/p0__0/B[10] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.
|
|
Related violations: <none>
|
|
|
|
DPIR-1#126 Warning
|
|
Asynchronous driver check
|
|
DSP u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/u_bc/p0__0 input pin u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/u_bc/p0__0/B[11] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.
|
|
Related violations: <none>
|
|
|
|
DPIR-1#127 Warning
|
|
Asynchronous driver check
|
|
DSP u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/u_bc/p0__0 input pin u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/u_bc/p0__0/B[1] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.
|
|
Related violations: <none>
|
|
|
|
DPIR-1#128 Warning
|
|
Asynchronous driver check
|
|
DSP u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/u_bc/p0__0 input pin u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/u_bc/p0__0/B[2] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.
|
|
Related violations: <none>
|
|
|
|
DPIR-1#129 Warning
|
|
Asynchronous driver check
|
|
DSP u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/u_bc/p0__0 input pin u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/u_bc/p0__0/B[3] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.
|
|
Related violations: <none>
|
|
|
|
DPIR-1#130 Warning
|
|
Asynchronous driver check
|
|
DSP u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/u_bc/p0__0 input pin u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/u_bc/p0__0/B[4] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.
|
|
Related violations: <none>
|
|
|
|
DPIR-1#131 Warning
|
|
Asynchronous driver check
|
|
DSP u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/u_bc/p0__0 input pin u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/u_bc/p0__0/B[5] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.
|
|
Related violations: <none>
|
|
|
|
DPIR-1#132 Warning
|
|
Asynchronous driver check
|
|
DSP u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/u_bc/p0__0 input pin u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/u_bc/p0__0/B[6] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.
|
|
Related violations: <none>
|
|
|
|
DPIR-1#133 Warning
|
|
Asynchronous driver check
|
|
DSP u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/u_bc/p0__0 input pin u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/u_bc/p0__0/B[7] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.
|
|
Related violations: <none>
|
|
|
|
DPIR-1#134 Warning
|
|
Asynchronous driver check
|
|
DSP u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/u_bc/p0__0 input pin u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/u_bc/p0__0/B[8] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.
|
|
Related violations: <none>
|
|
|
|
DPIR-1#135 Warning
|
|
Asynchronous driver check
|
|
DSP u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/u_bc/p0__0 input pin u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/u_bc/p0__0/B[9] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.
|
|
Related violations: <none>
|
|
|
|
DPIR-1#136 Warning
|
|
Asynchronous driver check
|
|
DSP u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/u_bc/p0__1 input pin u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/u_bc/p0__1/A[0] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.
|
|
Related violations: <none>
|
|
|
|
DPIR-1#137 Warning
|
|
Asynchronous driver check
|
|
DSP u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/u_bc/p0__1 input pin u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/u_bc/p0__1/A[10] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.
|
|
Related violations: <none>
|
|
|
|
DPIR-1#138 Warning
|
|
Asynchronous driver check
|
|
DSP u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/u_bc/p0__1 input pin u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/u_bc/p0__1/A[11] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.
|
|
Related violations: <none>
|
|
|
|
DPIR-1#139 Warning
|
|
Asynchronous driver check
|
|
DSP u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/u_bc/p0__1 input pin u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/u_bc/p0__1/A[1] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.
|
|
Related violations: <none>
|
|
|
|
DPIR-1#140 Warning
|
|
Asynchronous driver check
|
|
DSP u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/u_bc/p0__1 input pin u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/u_bc/p0__1/A[2] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.
|
|
Related violations: <none>
|
|
|
|
DPIR-1#141 Warning
|
|
Asynchronous driver check
|
|
DSP u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/u_bc/p0__1 input pin u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/u_bc/p0__1/A[3] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.
|
|
Related violations: <none>
|
|
|
|
DPIR-1#142 Warning
|
|
Asynchronous driver check
|
|
DSP u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/u_bc/p0__1 input pin u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/u_bc/p0__1/A[4] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.
|
|
Related violations: <none>
|
|
|
|
DPIR-1#143 Warning
|
|
Asynchronous driver check
|
|
DSP u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/u_bc/p0__1 input pin u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/u_bc/p0__1/A[5] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.
|
|
Related violations: <none>
|
|
|
|
DPIR-1#144 Warning
|
|
Asynchronous driver check
|
|
DSP u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/u_bc/p0__1 input pin u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/u_bc/p0__1/A[6] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.
|
|
Related violations: <none>
|
|
|
|
DPIR-1#145 Warning
|
|
Asynchronous driver check
|
|
DSP u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/u_bc/p0__1 input pin u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/u_bc/p0__1/A[7] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.
|
|
Related violations: <none>
|
|
|
|
DPIR-1#146 Warning
|
|
Asynchronous driver check
|
|
DSP u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/u_bc/p0__1 input pin u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/u_bc/p0__1/A[8] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.
|
|
Related violations: <none>
|
|
|
|
DPIR-1#147 Warning
|
|
Asynchronous driver check
|
|
DSP u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/u_bc/p0__1 input pin u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/u_bc/p0__1/A[9] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.
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|
Related violations: <none>
|
|
|
|
DPIR-1#148 Warning
|
|
Asynchronous driver check
|
|
DSP u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/u_bc/p0__1 input pin u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/u_bc/p0__1/B[0] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.
|
|
Related violations: <none>
|
|
|
|
DPIR-1#149 Warning
|
|
Asynchronous driver check
|
|
DSP u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/u_bc/p0__1 input pin u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/u_bc/p0__1/B[10] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.
|
|
Related violations: <none>
|
|
|
|
DPIR-1#150 Warning
|
|
Asynchronous driver check
|
|
DSP u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/u_bc/p0__1 input pin u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/u_bc/p0__1/B[11] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.
|
|
Related violations: <none>
|
|
|
|
DPIR-1#151 Warning
|
|
Asynchronous driver check
|
|
DSP u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/u_bc/p0__1 input pin u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/u_bc/p0__1/B[1] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.
|
|
Related violations: <none>
|
|
|
|
DPIR-1#152 Warning
|
|
Asynchronous driver check
|
|
DSP u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/u_bc/p0__1 input pin u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/u_bc/p0__1/B[2] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.
|
|
Related violations: <none>
|
|
|
|
DPIR-1#153 Warning
|
|
Asynchronous driver check
|
|
DSP u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/u_bc/p0__1 input pin u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/u_bc/p0__1/B[3] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.
|
|
Related violations: <none>
|
|
|
|
DPIR-1#154 Warning
|
|
Asynchronous driver check
|
|
DSP u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/u_bc/p0__1 input pin u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/u_bc/p0__1/B[4] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.
|
|
Related violations: <none>
|
|
|
|
DPIR-1#155 Warning
|
|
Asynchronous driver check
|
|
DSP u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/u_bc/p0__1 input pin u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/u_bc/p0__1/B[5] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.
|
|
Related violations: <none>
|
|
|
|
DPIR-1#156 Warning
|
|
Asynchronous driver check
|
|
DSP u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/u_bc/p0__1 input pin u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/u_bc/p0__1/B[6] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.
|
|
Related violations: <none>
|
|
|
|
DPIR-1#157 Warning
|
|
Asynchronous driver check
|
|
DSP u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/u_bc/p0__1 input pin u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/u_bc/p0__1/B[7] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.
|
|
Related violations: <none>
|
|
|
|
DPIR-1#158 Warning
|
|
Asynchronous driver check
|
|
DSP u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/u_bc/p0__1 input pin u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/u_bc/p0__1/B[8] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.
|
|
Related violations: <none>
|
|
|
|
DPIR-1#159 Warning
|
|
Asynchronous driver check
|
|
DSP u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/u_bc/p0__1 input pin u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/u_bc/p0__1/B[9] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.
|
|
Related violations: <none>
|
|
|
|
DPIR-1#160 Warning
|
|
Asynchronous driver check
|
|
DSP u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/u_bc/p0__2 input pin u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/u_bc/p0__2/A[0] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.
|
|
Related violations: <none>
|
|
|
|
DPIR-1#161 Warning
|
|
Asynchronous driver check
|
|
DSP u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/u_bc/p0__2 input pin u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/u_bc/p0__2/A[10] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.
|
|
Related violations: <none>
|
|
|
|
DPIR-1#162 Warning
|
|
Asynchronous driver check
|
|
DSP u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/u_bc/p0__2 input pin u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/u_bc/p0__2/A[11] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.
|
|
Related violations: <none>
|
|
|
|
DPIR-1#163 Warning
|
|
Asynchronous driver check
|
|
DSP u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/u_bc/p0__2 input pin u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/u_bc/p0__2/A[1] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.
|
|
Related violations: <none>
|
|
|
|
DPIR-1#164 Warning
|
|
Asynchronous driver check
|
|
DSP u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/u_bc/p0__2 input pin u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/u_bc/p0__2/A[2] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.
|
|
Related violations: <none>
|
|
|
|
DPIR-1#165 Warning
|
|
Asynchronous driver check
|
|
DSP u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/u_bc/p0__2 input pin u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/u_bc/p0__2/A[3] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.
|
|
Related violations: <none>
|
|
|
|
DPIR-1#166 Warning
|
|
Asynchronous driver check
|
|
DSP u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/u_bc/p0__2 input pin u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/u_bc/p0__2/A[4] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.
|
|
Related violations: <none>
|
|
|
|
DPIR-1#167 Warning
|
|
Asynchronous driver check
|
|
DSP u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/u_bc/p0__2 input pin u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/u_bc/p0__2/A[5] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.
|
|
Related violations: <none>
|
|
|
|
DPIR-1#168 Warning
|
|
Asynchronous driver check
|
|
DSP u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/u_bc/p0__2 input pin u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/u_bc/p0__2/A[6] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.
|
|
Related violations: <none>
|
|
|
|
DPIR-1#169 Warning
|
|
Asynchronous driver check
|
|
DSP u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/u_bc/p0__2 input pin u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/u_bc/p0__2/A[7] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.
|
|
Related violations: <none>
|
|
|
|
DPIR-1#170 Warning
|
|
Asynchronous driver check
|
|
DSP u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/u_bc/p0__2 input pin u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/u_bc/p0__2/A[8] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.
|
|
Related violations: <none>
|
|
|
|
DPIR-1#171 Warning
|
|
Asynchronous driver check
|
|
DSP u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/u_bc/p0__2 input pin u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/u_bc/p0__2/A[9] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.
|
|
Related violations: <none>
|
|
|
|
DPIR-1#172 Warning
|
|
Asynchronous driver check
|
|
DSP u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/u_bc/p0__2 input pin u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/u_bc/p0__2/B[0] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.
|
|
Related violations: <none>
|
|
|
|
DPIR-1#173 Warning
|
|
Asynchronous driver check
|
|
DSP u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/u_bc/p0__2 input pin u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/u_bc/p0__2/B[10] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.
|
|
Related violations: <none>
|
|
|
|
DPIR-1#174 Warning
|
|
Asynchronous driver check
|
|
DSP u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/u_bc/p0__2 input pin u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/u_bc/p0__2/B[11] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.
|
|
Related violations: <none>
|
|
|
|
DPIR-1#175 Warning
|
|
Asynchronous driver check
|
|
DSP u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/u_bc/p0__2 input pin u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/u_bc/p0__2/B[1] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.
|
|
Related violations: <none>
|
|
|
|
DPIR-1#176 Warning
|
|
Asynchronous driver check
|
|
DSP u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/u_bc/p0__2 input pin u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/u_bc/p0__2/B[2] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.
|
|
Related violations: <none>
|
|
|
|
DPIR-1#177 Warning
|
|
Asynchronous driver check
|
|
DSP u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/u_bc/p0__2 input pin u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/u_bc/p0__2/B[3] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.
|
|
Related violations: <none>
|
|
|
|
DPIR-1#178 Warning
|
|
Asynchronous driver check
|
|
DSP u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/u_bc/p0__2 input pin u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/u_bc/p0__2/B[4] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.
|
|
Related violations: <none>
|
|
|
|
DPIR-1#179 Warning
|
|
Asynchronous driver check
|
|
DSP u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/u_bc/p0__2 input pin u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/u_bc/p0__2/B[5] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.
|
|
Related violations: <none>
|
|
|
|
DPIR-1#180 Warning
|
|
Asynchronous driver check
|
|
DSP u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/u_bc/p0__2 input pin u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/u_bc/p0__2/B[6] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.
|
|
Related violations: <none>
|
|
|
|
DPIR-1#181 Warning
|
|
Asynchronous driver check
|
|
DSP u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/u_bc/p0__2 input pin u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/u_bc/p0__2/B[7] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.
|
|
Related violations: <none>
|
|
|
|
DPIR-1#182 Warning
|
|
Asynchronous driver check
|
|
DSP u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/u_bc/p0__2 input pin u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/u_bc/p0__2/B[8] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.
|
|
Related violations: <none>
|
|
|
|
DPIR-1#183 Warning
|
|
Asynchronous driver check
|
|
DSP u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/u_bc/p0__2 input pin u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/u_bc/p0__2/B[9] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.
|
|
Related violations: <none>
|
|
|
|
DPIR-1#184 Warning
|
|
Asynchronous driver check
|
|
DSP u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/u_bc/p0__3 input pin u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/u_bc/p0__3/A[0] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.
|
|
Related violations: <none>
|
|
|
|
DPIR-1#185 Warning
|
|
Asynchronous driver check
|
|
DSP u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/u_bc/p0__3 input pin u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/u_bc/p0__3/A[10] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.
|
|
Related violations: <none>
|
|
|
|
DPIR-1#186 Warning
|
|
Asynchronous driver check
|
|
DSP u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/u_bc/p0__3 input pin u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/u_bc/p0__3/A[11] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.
|
|
Related violations: <none>
|
|
|
|
DPIR-1#187 Warning
|
|
Asynchronous driver check
|
|
DSP u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/u_bc/p0__3 input pin u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/u_bc/p0__3/A[1] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.
|
|
Related violations: <none>
|
|
|
|
DPIR-1#188 Warning
|
|
Asynchronous driver check
|
|
DSP u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/u_bc/p0__3 input pin u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/u_bc/p0__3/A[2] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.
|
|
Related violations: <none>
|
|
|
|
DPIR-1#189 Warning
|
|
Asynchronous driver check
|
|
DSP u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/u_bc/p0__3 input pin u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/u_bc/p0__3/A[3] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.
|
|
Related violations: <none>
|
|
|
|
DPIR-1#190 Warning
|
|
Asynchronous driver check
|
|
DSP u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/u_bc/p0__3 input pin u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/u_bc/p0__3/A[4] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.
|
|
Related violations: <none>
|
|
|
|
DPIR-1#191 Warning
|
|
Asynchronous driver check
|
|
DSP u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/u_bc/p0__3 input pin u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/u_bc/p0__3/A[5] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.
|
|
Related violations: <none>
|
|
|
|
DPIR-1#192 Warning
|
|
Asynchronous driver check
|
|
DSP u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/u_bc/p0__3 input pin u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/u_bc/p0__3/A[6] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.
|
|
Related violations: <none>
|
|
|
|
DPIR-1#193 Warning
|
|
Asynchronous driver check
|
|
DSP u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/u_bc/p0__3 input pin u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/u_bc/p0__3/A[7] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.
|
|
Related violations: <none>
|
|
|
|
DPIR-1#194 Warning
|
|
Asynchronous driver check
|
|
DSP u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/u_bc/p0__3 input pin u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/u_bc/p0__3/A[8] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.
|
|
Related violations: <none>
|
|
|
|
DPIR-1#195 Warning
|
|
Asynchronous driver check
|
|
DSP u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/u_bc/p0__3 input pin u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/u_bc/p0__3/A[9] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.
|
|
Related violations: <none>
|
|
|
|
DPIR-1#196 Warning
|
|
Asynchronous driver check
|
|
DSP u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/u_bc/p0__3 input pin u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/u_bc/p0__3/B[0] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.
|
|
Related violations: <none>
|
|
|
|
DPIR-1#197 Warning
|
|
Asynchronous driver check
|
|
DSP u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/u_bc/p0__3 input pin u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/u_bc/p0__3/B[10] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.
|
|
Related violations: <none>
|
|
|
|
DPIR-1#198 Warning
|
|
Asynchronous driver check
|
|
DSP u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/u_bc/p0__3 input pin u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/u_bc/p0__3/B[11] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.
|
|
Related violations: <none>
|
|
|
|
DPIR-1#199 Warning
|
|
Asynchronous driver check
|
|
DSP u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/u_bc/p0__3 input pin u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/u_bc/p0__3/B[1] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.
|
|
Related violations: <none>
|
|
|
|
DPIR-1#200 Warning
|
|
Asynchronous driver check
|
|
DSP u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/u_bc/p0__3 input pin u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/u_bc/p0__3/B[2] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.
|
|
Related violations: <none>
|
|
|
|
DPIR-1#201 Warning
|
|
Asynchronous driver check
|
|
DSP u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/u_bc/p0__3 input pin u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/u_bc/p0__3/B[3] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.
|
|
Related violations: <none>
|
|
|
|
DPIR-1#202 Warning
|
|
Asynchronous driver check
|
|
DSP u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/u_bc/p0__3 input pin u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/u_bc/p0__3/B[4] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.
|
|
Related violations: <none>
|
|
|
|
DPIR-1#203 Warning
|
|
Asynchronous driver check
|
|
DSP u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/u_bc/p0__3 input pin u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/u_bc/p0__3/B[5] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.
|
|
Related violations: <none>
|
|
|
|
DPIR-1#204 Warning
|
|
Asynchronous driver check
|
|
DSP u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/u_bc/p0__3 input pin u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/u_bc/p0__3/B[6] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.
|
|
Related violations: <none>
|
|
|
|
DPIR-1#205 Warning
|
|
Asynchronous driver check
|
|
DSP u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/u_bc/p0__3 input pin u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/u_bc/p0__3/B[7] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.
|
|
Related violations: <none>
|
|
|
|
DPIR-1#206 Warning
|
|
Asynchronous driver check
|
|
DSP u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/u_bc/p0__3 input pin u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/u_bc/p0__3/B[8] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.
|
|
Related violations: <none>
|
|
|
|
DPIR-1#207 Warning
|
|
Asynchronous driver check
|
|
DSP u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/u_bc/p0__3 input pin u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/u_bc/p0__3/B[9] is connected to registers with an asynchronous reset. This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.
|
|
Related violations: <none>
|
|
|
|
LUTAR-1#1 Warning
|
|
LUT drives async reset alert
|
|
LUT cell u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_c_in_bram/q_s3[12]_i_4, with 2 or more inputs, drives asynchronous preset/clear pin(s) _i_1/CLR, comp_q_est_s3_reg[12]_i_2/CLR, q_s3_reg[12]_i_3/CLR, tk_s20_i_25/CLR, tk_s20_i_25__0/CLR, u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/a_busy_reg/CLR, u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/a_i_reg[0]/CLR, u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/a_i_reg[1]/CLR, u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/a_i_reg[2]/CLR, u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/a_j_reg[0]/CLR, u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/a_j_reg[1]/CLR, u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/a_j_reg[2]/CLR, u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/a_pair_reg[0]/CLR, u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/a_pair_reg[1]/CLR, u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/a_pair_reg[2]/CLR (the first 15 of 24215 listed). The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path.
|
|
Related violations: <none>
|
|
|
|
SYNTH-5#1 Warning
|
|
Mapped onto distributed RAM because of timing constraints
|
|
The instance u_cpu/dcache/way_d_reg_reg_r1_0_127_0_0 is implemented as distributed LUT RAM for the following reason: The timing constraints suggest that the chosen mapping will yield a better timing.
|
|
Related violations: <none>
|
|
|
|
SYNTH-5#2 Warning
|
|
Mapped onto distributed RAM because of timing constraints
|
|
The instance u_cpu/dcache/way_d_reg_reg_r1_0_127_1_1 is implemented as distributed LUT RAM for the following reason: The timing constraints suggest that the chosen mapping will yield a better timing.
|
|
Related violations: <none>
|
|
|
|
SYNTH-5#3 Warning
|
|
Mapped onto distributed RAM because of timing constraints
|
|
The instance u_cpu/dcache/way_d_reg_reg_r1_128_255_0_0 is implemented as distributed LUT RAM for the following reason: The timing constraints suggest that the chosen mapping will yield a better timing.
|
|
Related violations: <none>
|
|
|
|
SYNTH-5#4 Warning
|
|
Mapped onto distributed RAM because of timing constraints
|
|
The instance u_cpu/dcache/way_d_reg_reg_r1_128_255_1_1 is implemented as distributed LUT RAM for the following reason: The timing constraints suggest that the chosen mapping will yield a better timing.
|
|
Related violations: <none>
|
|
|
|
SYNTH-5#5 Warning
|
|
Mapped onto distributed RAM because of timing constraints
|
|
The instance u_cpu/dcache/way_d_reg_reg_r2_0_127_0_0 is implemented as distributed LUT RAM for the following reason: The timing constraints suggest that the chosen mapping will yield a better timing.
|
|
Related violations: <none>
|
|
|
|
SYNTH-5#6 Warning
|
|
Mapped onto distributed RAM because of timing constraints
|
|
The instance u_cpu/dcache/way_d_reg_reg_r2_0_127_1_1 is implemented as distributed LUT RAM for the following reason: The timing constraints suggest that the chosen mapping will yield a better timing.
|
|
Related violations: <none>
|
|
|
|
SYNTH-5#7 Warning
|
|
Mapped onto distributed RAM because of timing constraints
|
|
The instance u_cpu/dcache/way_d_reg_reg_r2_128_255_0_0 is implemented as distributed LUT RAM for the following reason: The timing constraints suggest that the chosen mapping will yield a better timing.
|
|
Related violations: <none>
|
|
|
|
SYNTH-5#8 Warning
|
|
Mapped onto distributed RAM because of timing constraints
|
|
The instance u_cpu/dcache/way_d_reg_reg_r2_128_255_1_1 is implemented as distributed LUT RAM for the following reason: The timing constraints suggest that the chosen mapping will yield a better timing.
|
|
Related violations: <none>
|
|
|
|
SYNTH-10#1 Warning
|
|
Wide multiplier
|
|
Detected multiplier at u_matmul_axi_slave/mult_inst[0].u_mult/prod0__16 of size 16x18, it is decomposed from a wide multipler into 4 DSP blocks.
|
|
Related violations: <none>
|
|
|
|
SYNTH-10#2 Warning
|
|
Wide multiplier
|
|
Detected multiplier at u_matmul_axi_slave/mult_inst[0].u_mult/prod0__17 of size 18x18, it is decomposed from a wide multipler into 4 DSP blocks.
|
|
Related violations: <none>
|
|
|
|
SYNTH-10#3 Warning
|
|
Wide multiplier
|
|
Detected multiplier at u_matmul_axi_slave/mult_inst[0].u_mult/prod_reg of size 16x16, it is decomposed from a wide multipler into 4 DSP blocks.
|
|
Related violations: <none>
|
|
|
|
SYNTH-10#4 Warning
|
|
Wide multiplier
|
|
Detected multiplier at u_matmul_axi_slave/mult_inst[0].u_mult/prod_reg__0 of size 18x16, it is decomposed from a wide multipler into 4 DSP blocks.
|
|
Related violations: <none>
|
|
|
|
SYNTH-10#5 Warning
|
|
Wide multiplier
|
|
Detected multiplier at u_matmul_axi_slave/mult_inst[1].u_mult/prod0 of size 16x18, it is decomposed from a wide multipler into 4 DSP blocks.
|
|
Related violations: <none>
|
|
|
|
SYNTH-10#6 Warning
|
|
Wide multiplier
|
|
Detected multiplier at u_matmul_axi_slave/mult_inst[1].u_mult/prod0__17 of size 18x18, it is decomposed from a wide multipler into 4 DSP blocks.
|
|
Related violations: <none>
|
|
|
|
SYNTH-10#7 Warning
|
|
Wide multiplier
|
|
Detected multiplier at u_matmul_axi_slave/mult_inst[1].u_mult/prod_reg of size 16x16, it is decomposed from a wide multipler into 4 DSP blocks.
|
|
Related violations: <none>
|
|
|
|
SYNTH-10#8 Warning
|
|
Wide multiplier
|
|
Detected multiplier at u_matmul_axi_slave/mult_inst[1].u_mult/prod_reg__0 of size 18x16, it is decomposed from a wide multipler into 4 DSP blocks.
|
|
Related violations: <none>
|
|
|
|
SYNTH-10#9 Warning
|
|
Wide multiplier
|
|
Detected multiplier at u_matmul_axi_slave/mult_inst[2].u_mult/prod0 of size 16x18, it is decomposed from a wide multipler into 4 DSP blocks.
|
|
Related violations: <none>
|
|
|
|
SYNTH-10#10 Warning
|
|
Wide multiplier
|
|
Detected multiplier at u_matmul_axi_slave/mult_inst[2].u_mult/prod0__17 of size 18x18, it is decomposed from a wide multipler into 4 DSP blocks.
|
|
Related violations: <none>
|
|
|
|
SYNTH-10#11 Warning
|
|
Wide multiplier
|
|
Detected multiplier at u_matmul_axi_slave/mult_inst[2].u_mult/prod_reg of size 16x16, it is decomposed from a wide multipler into 4 DSP blocks.
|
|
Related violations: <none>
|
|
|
|
SYNTH-10#12 Warning
|
|
Wide multiplier
|
|
Detected multiplier at u_matmul_axi_slave/mult_inst[2].u_mult/prod_reg__0 of size 18x16, it is decomposed from a wide multipler into 4 DSP blocks.
|
|
Related violations: <none>
|
|
|
|
SYNTH-10#13 Warning
|
|
Wide multiplier
|
|
Detected multiplier at u_matmul_axi_slave/mult_inst[3].u_mult/prod0 of size 16x18, it is decomposed from a wide multipler into 4 DSP blocks.
|
|
Related violations: <none>
|
|
|
|
SYNTH-10#14 Warning
|
|
Wide multiplier
|
|
Detected multiplier at u_matmul_axi_slave/mult_inst[3].u_mult/prod0__17 of size 18x18, it is decomposed from a wide multipler into 4 DSP blocks.
|
|
Related violations: <none>
|
|
|
|
SYNTH-10#15 Warning
|
|
Wide multiplier
|
|
Detected multiplier at u_matmul_axi_slave/mult_inst[3].u_mult/prod_reg of size 16x16, it is decomposed from a wide multipler into 4 DSP blocks.
|
|
Related violations: <none>
|
|
|
|
SYNTH-10#16 Warning
|
|
Wide multiplier
|
|
Detected multiplier at u_matmul_axi_slave/mult_inst[3].u_mult/prod_reg__0 of size 18x16, it is decomposed from a wide multipler into 4 DSP blocks.
|
|
Related violations: <none>
|
|
|
|
SYNTH-16#1 Warning
|
|
Address collision
|
|
Block RAM u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_a/mem_reg_0 may get memory collision error if read and write address collide. Use of address collision resolution circuitry is recommended.
|
|
Related violations: <none>
|
|
|
|
SYNTH-16#2 Warning
|
|
Address collision
|
|
Block RAM u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_a/mem_reg_1 may get memory collision error if read and write address collide. Use of address collision resolution circuitry is recommended.
|
|
Related violations: <none>
|
|
|
|
SYNTH-16#3 Warning
|
|
Address collision
|
|
Block RAM u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_se/mem_reg may get memory collision error if read and write address collide. Use of address collision resolution circuitry is recommended.
|
|
Related violations: <none>
|
|
|
|
SYNTH-16#4 Warning
|
|
Address collision
|
|
Block RAM u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg may get memory collision error if read and write address collide. Use of address collision resolution circuitry is recommended.
|
|
Related violations: <none>
|
|
|
|
SYNTH-16#5 Warning
|
|
Address collision
|
|
Block RAM u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_c_in_bram/mem_reg may get memory collision error if read and write address collide. Use of address collision resolution circuitry is recommended.
|
|
Related violations: <none>
|
|
|
|
SYNTH-16#6 Warning
|
|
Address collision
|
|
Block RAM u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ct_bram/mem_reg may get memory collision error if read and write address collide. Use of address collision resolution circuitry is recommended.
|
|
Related violations: <none>
|
|
|
|
SYNTH-16#7 Warning
|
|
Address collision
|
|
Block RAM u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_dkp_bram/mem_reg may get memory collision error if read and write address collide. Use of address collision resolution circuitry is recommended.
|
|
Related violations: <none>
|
|
|
|
SYNTH-16#8 Warning
|
|
Address collision
|
|
Block RAM u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/mem_reg may get memory collision error if read and write address collide. Use of address collision resolution circuitry is recommended.
|
|
Related violations: <none>
|
|
|
|
TIMING-10#1 Warning
|
|
Missing property on synchronizer
|
|
One or more logic synchronizer has been detected between 2 clock domains but the synchronizer does not have the property ASYNC_REG defined on one or both registers. It is recommended to run report_cdc for a complete and detailed CDC coverage
|
|
Related violations: <none>
|
|
|
|
TIMING-18#1 Warning
|
|
Missing input or output delay
|
|
An input delay is missing on UART_RX relative to clock(s) clk
|
|
Related violations: <none>
|
|
|
|
TIMING-18#2 Warning
|
|
Missing input or output delay
|
|
An input delay is missing on UART_TX relative to clock(s) clk
|
|
Related violations: <none>
|
|
|
|
TIMING-18#3 Warning
|
|
Missing input or output delay
|
|
An input delay is missing on dip_sw[0] relative to clock(s) clk
|
|
Related violations: <none>
|
|
|
|
TIMING-18#4 Warning
|
|
Missing input or output delay
|
|
An input delay is missing on dip_sw[10] relative to clock(s) clk
|
|
Related violations: <none>
|
|
|
|
TIMING-18#5 Warning
|
|
Missing input or output delay
|
|
An input delay is missing on dip_sw[11] relative to clock(s) clk
|
|
Related violations: <none>
|
|
|
|
TIMING-18#6 Warning
|
|
Missing input or output delay
|
|
An input delay is missing on dip_sw[12] relative to clock(s) clk
|
|
Related violations: <none>
|
|
|
|
TIMING-18#7 Warning
|
|
Missing input or output delay
|
|
An input delay is missing on dip_sw[13] relative to clock(s) clk
|
|
Related violations: <none>
|
|
|
|
TIMING-18#8 Warning
|
|
Missing input or output delay
|
|
An input delay is missing on dip_sw[14] relative to clock(s) clk
|
|
Related violations: <none>
|
|
|
|
TIMING-18#9 Warning
|
|
Missing input or output delay
|
|
An input delay is missing on dip_sw[15] relative to clock(s) clk
|
|
Related violations: <none>
|
|
|
|
TIMING-18#10 Warning
|
|
Missing input or output delay
|
|
An input delay is missing on dip_sw[16] relative to clock(s) clk
|
|
Related violations: <none>
|
|
|
|
TIMING-18#11 Warning
|
|
Missing input or output delay
|
|
An input delay is missing on dip_sw[17] relative to clock(s) clk
|
|
Related violations: <none>
|
|
|
|
TIMING-18#12 Warning
|
|
Missing input or output delay
|
|
An input delay is missing on dip_sw[18] relative to clock(s) clk
|
|
Related violations: <none>
|
|
|
|
TIMING-18#13 Warning
|
|
Missing input or output delay
|
|
An input delay is missing on dip_sw[19] relative to clock(s) clk
|
|
Related violations: <none>
|
|
|
|
TIMING-18#14 Warning
|
|
Missing input or output delay
|
|
An input delay is missing on dip_sw[1] relative to clock(s) clk
|
|
Related violations: <none>
|
|
|
|
TIMING-18#15 Warning
|
|
Missing input or output delay
|
|
An input delay is missing on dip_sw[20] relative to clock(s) clk
|
|
Related violations: <none>
|
|
|
|
TIMING-18#16 Warning
|
|
Missing input or output delay
|
|
An input delay is missing on dip_sw[21] relative to clock(s) clk
|
|
Related violations: <none>
|
|
|
|
TIMING-18#17 Warning
|
|
Missing input or output delay
|
|
An input delay is missing on dip_sw[22] relative to clock(s) clk
|
|
Related violations: <none>
|
|
|
|
TIMING-18#18 Warning
|
|
Missing input or output delay
|
|
An input delay is missing on dip_sw[23] relative to clock(s) clk
|
|
Related violations: <none>
|
|
|
|
TIMING-18#19 Warning
|
|
Missing input or output delay
|
|
An input delay is missing on dip_sw[24] relative to clock(s) clk
|
|
Related violations: <none>
|
|
|
|
TIMING-18#20 Warning
|
|
Missing input or output delay
|
|
An input delay is missing on dip_sw[25] relative to clock(s) clk
|
|
Related violations: <none>
|
|
|
|
TIMING-18#21 Warning
|
|
Missing input or output delay
|
|
An input delay is missing on dip_sw[26] relative to clock(s) clk
|
|
Related violations: <none>
|
|
|
|
TIMING-18#22 Warning
|
|
Missing input or output delay
|
|
An input delay is missing on dip_sw[27] relative to clock(s) clk
|
|
Related violations: <none>
|
|
|
|
TIMING-18#23 Warning
|
|
Missing input or output delay
|
|
An input delay is missing on dip_sw[28] relative to clock(s) clk
|
|
Related violations: <none>
|
|
|
|
TIMING-18#24 Warning
|
|
Missing input or output delay
|
|
An input delay is missing on dip_sw[29] relative to clock(s) clk
|
|
Related violations: <none>
|
|
|
|
TIMING-18#25 Warning
|
|
Missing input or output delay
|
|
An input delay is missing on dip_sw[2] relative to clock(s) clk
|
|
Related violations: <none>
|
|
|
|
TIMING-18#26 Warning
|
|
Missing input or output delay
|
|
An input delay is missing on dip_sw[30] relative to clock(s) clk
|
|
Related violations: <none>
|
|
|
|
TIMING-18#27 Warning
|
|
Missing input or output delay
|
|
An input delay is missing on dip_sw[31] relative to clock(s) clk
|
|
Related violations: <none>
|
|
|
|
TIMING-18#28 Warning
|
|
Missing input or output delay
|
|
An input delay is missing on dip_sw[3] relative to clock(s) clk
|
|
Related violations: <none>
|
|
|
|
TIMING-18#29 Warning
|
|
Missing input or output delay
|
|
An input delay is missing on dip_sw[4] relative to clock(s) clk
|
|
Related violations: <none>
|
|
|
|
TIMING-18#30 Warning
|
|
Missing input or output delay
|
|
An input delay is missing on dip_sw[5] relative to clock(s) clk
|
|
Related violations: <none>
|
|
|
|
TIMING-18#31 Warning
|
|
Missing input or output delay
|
|
An input delay is missing on dip_sw[6] relative to clock(s) clk
|
|
Related violations: <none>
|
|
|
|
TIMING-18#32 Warning
|
|
Missing input or output delay
|
|
An input delay is missing on dip_sw[7] relative to clock(s) clk
|
|
Related violations: <none>
|
|
|
|
TIMING-18#33 Warning
|
|
Missing input or output delay
|
|
An input delay is missing on dip_sw[8] relative to clock(s) clk
|
|
Related violations: <none>
|
|
|
|
TIMING-18#34 Warning
|
|
Missing input or output delay
|
|
An input delay is missing on dip_sw[9] relative to clock(s) clk
|
|
Related violations: <none>
|
|
|
|
TIMING-18#35 Warning
|
|
Missing input or output delay
|
|
An input delay is missing on touch_btn[0] relative to clock(s) clk
|
|
Related violations: <none>
|
|
|
|
TIMING-18#36 Warning
|
|
Missing input or output delay
|
|
An input delay is missing on touch_btn[1] relative to clock(s) clk
|
|
Related violations: <none>
|
|
|
|
TIMING-18#37 Warning
|
|
Missing input or output delay
|
|
An input delay is missing on touch_btn[2] relative to clock(s) clk
|
|
Related violations: <none>
|
|
|
|
TIMING-18#38 Warning
|
|
Missing input or output delay
|
|
An input delay is missing on touch_btn[3] relative to clock(s) clk
|
|
Related violations: <none>
|
|
|
|
TIMING-18#39 Warning
|
|
Missing input or output delay
|
|
An output delay is missing on dpy0[0] relative to clock(s) clk
|
|
Related violations: <none>
|
|
|
|
TIMING-18#40 Warning
|
|
Missing input or output delay
|
|
An output delay is missing on dpy0[1] relative to clock(s) clk
|
|
Related violations: <none>
|
|
|
|
TIMING-18#41 Warning
|
|
Missing input or output delay
|
|
An output delay is missing on dpy0[2] relative to clock(s) clk
|
|
Related violations: <none>
|
|
|
|
TIMING-18#42 Warning
|
|
Missing input or output delay
|
|
An output delay is missing on dpy0[3] relative to clock(s) clk
|
|
Related violations: <none>
|
|
|
|
TIMING-18#43 Warning
|
|
Missing input or output delay
|
|
An output delay is missing on dpy0[4] relative to clock(s) clk
|
|
Related violations: <none>
|
|
|
|
TIMING-18#44 Warning
|
|
Missing input or output delay
|
|
An output delay is missing on dpy0[5] relative to clock(s) clk
|
|
Related violations: <none>
|
|
|
|
TIMING-18#45 Warning
|
|
Missing input or output delay
|
|
An output delay is missing on dpy0[6] relative to clock(s) clk
|
|
Related violations: <none>
|
|
|
|
TIMING-18#46 Warning
|
|
Missing input or output delay
|
|
An output delay is missing on dpy0[7] relative to clock(s) clk
|
|
Related violations: <none>
|
|
|
|
TIMING-18#47 Warning
|
|
Missing input or output delay
|
|
An output delay is missing on dpy1[0] relative to clock(s) clk
|
|
Related violations: <none>
|
|
|
|
TIMING-18#48 Warning
|
|
Missing input or output delay
|
|
An output delay is missing on dpy1[1] relative to clock(s) clk
|
|
Related violations: <none>
|
|
|
|
TIMING-18#49 Warning
|
|
Missing input or output delay
|
|
An output delay is missing on dpy1[2] relative to clock(s) clk
|
|
Related violations: <none>
|
|
|
|
TIMING-18#50 Warning
|
|
Missing input or output delay
|
|
An output delay is missing on dpy1[3] relative to clock(s) clk
|
|
Related violations: <none>
|
|
|
|
TIMING-18#51 Warning
|
|
Missing input or output delay
|
|
An output delay is missing on dpy1[4] relative to clock(s) clk
|
|
Related violations: <none>
|
|
|
|
TIMING-18#52 Warning
|
|
Missing input or output delay
|
|
An output delay is missing on dpy1[5] relative to clock(s) clk
|
|
Related violations: <none>
|
|
|
|
TIMING-18#53 Warning
|
|
Missing input or output delay
|
|
An output delay is missing on dpy1[6] relative to clock(s) clk
|
|
Related violations: <none>
|
|
|
|
TIMING-18#54 Warning
|
|
Missing input or output delay
|
|
An output delay is missing on dpy1[7] relative to clock(s) clk
|
|
Related violations: <none>
|
|
|
|
TIMING-18#55 Warning
|
|
Missing input or output delay
|
|
An output delay is missing on leds[0] relative to clock(s) clk
|
|
Related violations: <none>
|
|
|
|
TIMING-18#56 Warning
|
|
Missing input or output delay
|
|
An output delay is missing on leds[10] relative to clock(s) clk
|
|
Related violations: <none>
|
|
|
|
TIMING-18#57 Warning
|
|
Missing input or output delay
|
|
An output delay is missing on leds[11] relative to clock(s) clk
|
|
Related violations: <none>
|
|
|
|
TIMING-18#58 Warning
|
|
Missing input or output delay
|
|
An output delay is missing on leds[12] relative to clock(s) clk
|
|
Related violations: <none>
|
|
|
|
TIMING-18#59 Warning
|
|
Missing input or output delay
|
|
An output delay is missing on leds[13] relative to clock(s) clk
|
|
Related violations: <none>
|
|
|
|
TIMING-18#60 Warning
|
|
Missing input or output delay
|
|
An output delay is missing on leds[14] relative to clock(s) clk
|
|
Related violations: <none>
|
|
|
|
TIMING-18#61 Warning
|
|
Missing input or output delay
|
|
An output delay is missing on leds[15] relative to clock(s) clk
|
|
Related violations: <none>
|
|
|
|
TIMING-18#62 Warning
|
|
Missing input or output delay
|
|
An output delay is missing on leds[1] relative to clock(s) clk
|
|
Related violations: <none>
|
|
|
|
TIMING-18#63 Warning
|
|
Missing input or output delay
|
|
An output delay is missing on leds[2] relative to clock(s) clk
|
|
Related violations: <none>
|
|
|
|
TIMING-18#64 Warning
|
|
Missing input or output delay
|
|
An output delay is missing on leds[3] relative to clock(s) clk
|
|
Related violations: <none>
|
|
|
|
TIMING-18#65 Warning
|
|
Missing input or output delay
|
|
An output delay is missing on leds[4] relative to clock(s) clk
|
|
Related violations: <none>
|
|
|
|
TIMING-18#66 Warning
|
|
Missing input or output delay
|
|
An output delay is missing on leds[5] relative to clock(s) clk
|
|
Related violations: <none>
|
|
|
|
TIMING-18#67 Warning
|
|
Missing input or output delay
|
|
An output delay is missing on leds[6] relative to clock(s) clk
|
|
Related violations: <none>
|
|
|
|
TIMING-18#68 Warning
|
|
Missing input or output delay
|
|
An output delay is missing on leds[7] relative to clock(s) clk
|
|
Related violations: <none>
|
|
|
|
TIMING-18#69 Warning
|
|
Missing input or output delay
|
|
An output delay is missing on leds[8] relative to clock(s) clk
|
|
Related violations: <none>
|
|
|
|
TIMING-18#70 Warning
|
|
Missing input or output delay
|
|
An output delay is missing on leds[9] relative to clock(s) clk
|
|
Related violations: <none>
|
|
|
|
TIMING-18#71 Warning
|
|
Missing input or output delay
|
|
An output delay is missing on video_de relative to clock(s) clk
|
|
Related violations: <none>
|
|
|
|
TIMING-18#72 Warning
|
|
Missing input or output delay
|
|
An output delay is missing on video_hsync relative to clock(s) clk
|
|
Related violations: <none>
|
|
|
|
TIMING-18#73 Warning
|
|
Missing input or output delay
|
|
An output delay is missing on video_red[0] relative to clock(s) clk
|
|
Related violations: <none>
|
|
|
|
TIMING-18#74 Warning
|
|
Missing input or output delay
|
|
An output delay is missing on video_red[1] relative to clock(s) clk
|
|
Related violations: <none>
|
|
|
|
TIMING-18#75 Warning
|
|
Missing input or output delay
|
|
An output delay is missing on video_red[2] relative to clock(s) clk
|
|
Related violations: <none>
|
|
|
|
TIMING-18#76 Warning
|
|
Missing input or output delay
|
|
An output delay is missing on video_vsync relative to clock(s) clk
|
|
Related violations: <none>
|
|
|
|
TIMING-47#1 Warning
|
|
False path or asynchronous clock group between synchronous clocks
|
|
A Clock Group timing constraint is set between synchronous clocks cpu_clk and sys_clk (see constraint position 6 in the Timing Constraint window in Vivado IDE). It is not recommended to cover synchronous clock domains with constraints that prevent timing analysis as the design could fail in hardware.
|
|
Related violations: <none>
|
|
|
|
TIMING-47#2 Warning
|
|
False path or asynchronous clock group between synchronous clocks
|
|
A Clock Group timing constraint is set between synchronous clocks sys_clk and cpu_clk (see constraint position 6 in the Timing Constraint window in Vivado IDE). It is not recommended to cover synchronous clock domains with constraints that prevent timing analysis as the design could fail in hardware.
|
|
Related violations: <none>
|
|
|
|
XDCC-1#1 Warning
|
|
Scoped Clock constraint overwritten with the same name
|
|
A new clock constraint create_clock overrides a previous scoped clock constraint with the same name. It is not recommended to override a scoped (typically an IP) clock constraint and could result in unexpected behaviors.
|
|
New: create_clock -period 20.000 -name clk -waveform {0.000 10.000} [get_ports clk] (Source: /home/fallensigh/Dev/ciciec2026_loongson_regional/fpga/constraints/soc.xdc (Line: 4))
|
|
Previous: create_clock -period 20.000 [get_ports clk] (Source: /home/fallensigh/Dev/ciciec2026_loongson_regional/fpga/project/ipgen/clk_pll/clk_pll.xdc (Line: 56))
|
|
Related violations: <none>
|
|
|
|
XDCC-7#1 Warning
|
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Scoped Clock constraint overwritten on the same source
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A new clock constraint create_clock overrides a previous scoped clock constraint defined on the same source. It is not recommended to override a scoped (typically an IP) clock constraint and could result in unexpected behaviors.
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New: create_clock -period 20.000 -name clk -waveform {0.000 10.000} [get_ports clk] (Source: /home/fallensigh/Dev/ciciec2026_loongson_regional/fpga/constraints/soc.xdc (Line: 4))
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Previous: create_clock -period 20.000 [get_ports clk] (Source: /home/fallensigh/Dev/ciciec2026_loongson_regional/fpga/project/ipgen/clk_pll/clk_pll.xdc (Line: 56))
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Related violations: <none>
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