89 lines
6.0 KiB
Plaintext
89 lines
6.0 KiB
Plaintext
Copyright 1986-2019 Xilinx, Inc. All Rights Reserved.
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| Tool Version : Vivado v.2019.2 (lin64) Build 2708876 Wed Nov 6 21:39:14 MST 2019
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<<<<<<< Updated upstream
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| Date : Fri Jul 10 04:15:09 2026
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=======
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| Date : Sat Jul 11 09:21:05 2026
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>>>>>>> Stashed changes
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| Host : fedora running 64-bit unknown
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| Command : report_design_analysis -timing -file /home/fallensigh/Dev/ciciec2026_loongson_regional/fpga/vivado_reports_nodsp/design_analysis_timing.rpt
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| Design : soc_top
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| Device : xc7a200t
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| Design State : Routed
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Report Design Analysis
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Table of Contents
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-----------------
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1. Setup Path Characteristics 1-1
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1. Setup Path Characteristics 1-1
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---------------------------------
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<<<<<<< Updated upstream
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+---------------------------+----------------------------------------------------------------------------------------+
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| Characteristics | Path #1 |
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+---------------------------+----------------------------------------------------------------------------------------+
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| Requirement | 20.000 |
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| Path Delay | 15.529 |
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| Logic Delay | 6.868(45%) |
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| Net Delay | 8.661(55%) |
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| Clock Skew | -3.955 |
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| Slack | 0.146 |
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| Clock Relationship | Safely Timed |
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| Logic Levels | 14 |
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| Routes | 12 |
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| Logical Path | FDCE LUT4 LUT5 LUT6 CARRY4 CARRY4 CARRY4 CARRY4 LUT4 CARRY4 CARRY4 LUT6 LUT6 LUT6 OBUF |
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| Start Point Clock | sys_clk |
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| End Point Clock | sys_clk |
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| DSP Block | None |
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| BRAM | None |
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| IO Crossings | 3 |
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| Config Crossings | 0 |
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| SLR Crossings | 0 |
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| PBlocks | 0 |
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| High Fanout | 80 |
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| Dont Touch | 0 |
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| Mark Debug | 0 |
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| Start Point Pin Primitive | FDCE/C |
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| End Point Pin Primitive | base_ram_be_n[3] |
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| Start Point Pin | ax_req_q_len_reg[3]/C |
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| End Point Pin | base_ram_be_n[3] |
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+---------------------------+----------------------------------------------------------------------------------------+
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=======
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+---------------------------+-----------------------+
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| Characteristics | Path #1 |
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+---------------------------+-----------------------+
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| Requirement | 13.000 |
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| Path Delay | 13.035 |
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| Logic Delay | 0.752(6%) |
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| Net Delay | 12.283(94%) |
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| Clock Skew | 0.135 |
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| Slack | 0.070 |
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| Clock Relationship | Safely Timed |
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| Logic Levels | 1 |
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| Routes | 1 |
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| Logical Path | FDRE MUXF7 FDCE |
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| Start Point Clock | mlkem_clk |
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| End Point Clock | mlkem_clk |
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| DSP Block | None |
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| BRAM | None |
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| IO Crossings | 0 |
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| Config Crossings | 0 |
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| SLR Crossings | 0 |
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| PBlocks | 0 |
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| High Fanout | 1088 |
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| Dont Touch | 0 |
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| Mark Debug | 0 |
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| Start Point Pin Primitive | FDRE/C |
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| End Point Pin Primitive | FDCE/D |
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| Start Point Pin | dj_wb_inz_reg/C |
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| End Point Pin | dj_block_r_reg[732]/D |
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+---------------------------+-----------------------+
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>>>>>>> Stashed changes
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* Bounding box calculated as % of dimensions for the target device (436, 500)
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