67 lines
5.6 KiB
Plaintext
67 lines
5.6 KiB
Plaintext
Copyright 1986-2019 Xilinx, Inc. All Rights Reserved.
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| Tool Version : Vivado v.2019.2 (lin64) Build 2708876 Wed Nov 6 21:39:14 MST 2019
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| Date : Sun Jul 5 23:38:45 2026
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| Host : fedora running 64-bit unknown
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| Command : report_design_analysis -timing -logic_level_distribution -file ./vivado_reports/impl_design_analysis.rpt
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| Design : soc_top
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| Device : xc7a200t
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| Design State : Synthesized
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Report Design Analysis
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Table of Contents
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-----------------
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1. Setup Path Characteristics 1-1
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2. Logic Level Distribution
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1. Setup Path Characteristics 1-1
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---------------------------------
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+---------------------------+-----------------------------------------------------------------------------------------------------------+
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| Characteristics | Path #1 |
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+---------------------------+-----------------------------------------------------------------------------------------------------------+
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| Requirement | 20.000 |
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| Path Delay | 17.702 |
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| Logic Delay | 4.444(26%) |
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| Net Delay | 13.258(74%) |
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| Clock Skew | -0.145 |
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| Slack | 2.111 |
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| Clock Relationship | Safely Timed |
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| Logic Levels | 18 |
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| Routes | 0 |
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| Logical Path | FDRE LUT2 CARRY4 CARRY4 LUT2 CARRY4 LUT6 LUT6 LUT6 LUT6 LUT6 LUT5 LUT6 LUT5 LUT5 LUT5 LUT5 LUT6 LUT6 FDSE |
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| Start Point Clock | sys_clk |
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| End Point Clock | sys_clk |
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| DSP Block | None |
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| BRAM | None |
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| IO Crossings | 0 |
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| Config Crossings | 0 |
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| SLR Crossings | 0 |
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| PBlocks | 0 |
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| High Fanout | 16 |
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| Dont Touch | 0 |
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| Mark Debug | 0 |
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| Start Point Pin Primitive | FDRE/C |
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| End Point Pin Primitive | FDSE/D |
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| Start Point Pin | p_reg[1]/C |
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| End Point Pin | crc_reg_reg[18]/D |
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+---------------------------+-----------------------------------------------------------------------------------------------------------+
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* Bounding box calculated as % of dimensions for the target device (436, 500)
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2. Logic Level Distribution
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---------------------------
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+-----------------+-------------+----+-----+----+-----+-----+----+----+----+----+----+----+----+----+----+
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| End Point Clock | Requirement | 10 | 12 | 13 | 14 | 15 | 16 | 17 | 18 | 19 | 20 | 29 | 30 | 31 | 32 |
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+-----------------+-------------+----+-----+----+-----+-----+----+----+----+----+----+----+----+----+----+
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| cpu_clk | 30.323ns | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 65 | 40 | 34 | 62 |
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| sys_clk | 20.000ns | 2 | 120 | 72 | 122 | 348 | 89 | 7 | 37 | 1 | 1 | 0 | 0 | 0 | 0 |
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+-----------------+-------------+----+-----+----+-----+-----+----+----+----+----+----+----+----+----+----+
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* Columns represent the logic levels per end point clock
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** Distribution is for top worst 1000 paths
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