257 lines
37 KiB
Plaintext
257 lines
37 KiB
Plaintext
Copyright 1986-2019 Xilinx, Inc. All Rights Reserved.
|
|
---------------------------------------------------------------------------------------------------------------------------------
|
|
| Tool Version : Vivado v.2019.2 (lin64) Build 2708876 Wed Nov 6 21:39:14 MST 2019
|
|
| Date : Sun Jul 5 23:45:46 2026
|
|
| Host : fedora running 64-bit unknown
|
|
| Command : report_utilization -hierarchical -hierarchical_depth 10 -file ./vivado_reports_impl/routed_utilization_hier.rpt
|
|
| Design : soc_top
|
|
| Device : 7a200tfbg676-1
|
|
| Design State : Routed
|
|
---------------------------------------------------------------------------------------------------------------------------------
|
|
|
|
Utilization Design Information
|
|
|
|
Table of Contents
|
|
-----------------
|
|
1. Utilization by Hierarchy
|
|
|
|
1. Utilization by Hierarchy
|
|
---------------------------
|
|
|
|
+------------------------------------------+------------------------------+------------+------------+---------+------+-------+--------+--------+--------------+
|
|
| Instance | Module | Total LUTs | Logic LUTs | LUTRAMs | SRLs | FFs | RAMB36 | RAMB18 | DSP48 Blocks |
|
|
+------------------------------------------+------------------------------+------------+------------+---------+------+-------+--------+--------+--------------+
|
|
| soc_top | (top) | 74191 | 72517 | 628 | 1046 | 38619 | 10 | 31 | 0 |
|
|
| (soc_top) | (top) | 2094 | 2038 | 56 | 0 | 4 | 0 | 0 | 0 |
|
|
| pll_clk.u_clk_pll | clk_pll | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
|
|
| inst | clk_pll_clk_pll_clk_wiz | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
|
|
| pll_clk.u_rst_cpu | rst_sync | 1 | 1 | 0 | 0 | 2 | 0 | 0 | 0 |
|
|
| pll_clk.u_rst_sys | rst_sync_0 | 2 | 2 | 0 | 0 | 2 | 0 | 0 | 0 |
|
|
| u_AxiCrossbar_2x8 | AxiCrossbar_2x8 | 518 | 518 | 0 | 0 | 151 | 0 | 0 | 0 |
|
|
| (u_AxiCrossbar_2x8) | AxiCrossbar_2x8 | 8 | 8 | 0 | 0 | 24 | 0 | 0 | 0 |
|
|
| axi4ReadOnlyArbiter_4 | Axi4ReadOnlyArbiter | 12 | 12 | 0 | 0 | 3 | 0 | 0 | 0 |
|
|
| cmdArbiter | StreamArbiter_7_67 | 12 | 12 | 0 | 0 | 3 | 0 | 0 | 0 |
|
|
| axi4ReadOnlyArbiter_5 | Axi4ReadOnlyArbiter_50 | 6 | 6 | 0 | 0 | 2 | 0 | 0 | 0 |
|
|
| cmdArbiter | StreamArbiter_7_66 | 6 | 6 | 0 | 0 | 2 | 0 | 0 | 0 |
|
|
| axi4ReadOnlyArbiter_6 | Axi4ReadOnlyArbiter_51 | 12 | 12 | 0 | 0 | 3 | 0 | 0 | 0 |
|
|
| cmdArbiter | StreamArbiter_7_65 | 12 | 12 | 0 | 0 | 3 | 0 | 0 | 0 |
|
|
| axi4ReadOnlyArbiter_7 | Axi4ReadOnlyArbiter_52 | 13 | 13 | 0 | 0 | 3 | 0 | 0 | 0 |
|
|
| cmdArbiter | StreamArbiter_7_64 | 13 | 13 | 0 | 0 | 3 | 0 | 0 | 0 |
|
|
| axi4WriteOnlyArbiter_4 | Axi4WriteOnlyArbiter | 31 | 31 | 0 | 0 | 11 | 0 | 0 | 0 |
|
|
| (axi4WriteOnlyArbiter_4) | Axi4WriteOnlyArbiter | 0 | 0 | 0 | 0 | 2 | 0 | 0 | 0 |
|
|
| cmdArbiter | StreamArbiter_7_61 | 25 | 25 | 0 | 0 | 3 | 0 | 0 | 0 |
|
|
| cmdRouteFork_translated_fifo | StreamFifoLowLatency_3_62 | 7 | 7 | 0 | 0 | 6 | 0 | 0 | 0 |
|
|
| fifo | StreamFifo_3_63 | 7 | 7 | 0 | 0 | 6 | 0 | 0 | 0 |
|
|
| axi4WriteOnlyArbiter_5 | Axi4WriteOnlyArbiter_1 | 15 | 15 | 0 | 0 | 9 | 0 | 0 | 0 |
|
|
| cmdArbiter | StreamArbiter_7_58 | 9 | 9 | 0 | 0 | 3 | 0 | 0 | 0 |
|
|
| cmdRouteFork_translated_fifo | StreamFifoLowLatency_3_59 | 6 | 6 | 0 | 0 | 6 | 0 | 0 | 0 |
|
|
| fifo | StreamFifo_3_60 | 6 | 6 | 0 | 0 | 6 | 0 | 0 | 0 |
|
|
| axi4WriteOnlyArbiter_6 | Axi4WriteOnlyArbiter_2 | 29 | 29 | 0 | 0 | 11 | 0 | 0 | 0 |
|
|
| (axi4WriteOnlyArbiter_6) | Axi4WriteOnlyArbiter_2 | 0 | 0 | 0 | 0 | 2 | 0 | 0 | 0 |
|
|
| cmdArbiter | StreamArbiter_7_55 | 15 | 15 | 0 | 0 | 3 | 0 | 0 | 0 |
|
|
| cmdRouteFork_translated_fifo | StreamFifoLowLatency_3_56 | 14 | 14 | 0 | 0 | 6 | 0 | 0 | 0 |
|
|
| fifo | StreamFifo_3_57 | 14 | 14 | 0 | 0 | 6 | 0 | 0 | 0 |
|
|
| axi4WriteOnlyArbiter_7 | Axi4WriteOnlyArbiter_3 | 60 | 60 | 0 | 0 | 11 | 0 | 0 | 0 |
|
|
| (axi4WriteOnlyArbiter_7) | Axi4WriteOnlyArbiter_3 | 0 | 0 | 0 | 0 | 2 | 0 | 0 | 0 |
|
|
| cmdArbiter | StreamArbiter_7 | 48 | 48 | 0 | 0 | 3 | 0 | 0 | 0 |
|
|
| cmdRouteFork_translated_fifo | StreamFifoLowLatency_3 | 12 | 12 | 0 | 0 | 6 | 0 | 0 | 0 |
|
|
| fifo | StreamFifo_3 | 12 | 12 | 0 | 0 | 6 | 0 | 0 | 0 |
|
|
| axiIn_0_readOnly_decoder | Axi4ReadOnlyDecoder | 89 | 89 | 0 | 0 | 25 | 0 | 0 | 0 |
|
|
| (axiIn_0_readOnly_decoder) | Axi4ReadOnlyDecoder | 73 | 73 | 0 | 0 | 12 | 0 | 0 | 0 |
|
|
| errorSlave | Axi4ReadOnlyErrorSlave_1_54 | 16 | 16 | 0 | 0 | 13 | 0 | 0 | 0 |
|
|
| axiIn_0_writeOnly_decoder | Axi4WriteOnlyDecoder | 36 | 36 | 0 | 0 | 18 | 0 | 0 | 0 |
|
|
| (axiIn_0_writeOnly_decoder) | Axi4WriteOnlyDecoder | 16 | 16 | 0 | 0 | 16 | 0 | 0 | 0 |
|
|
| errorSlave | Axi4WriteOnlyErrorSlave_1_53 | 20 | 20 | 0 | 0 | 2 | 0 | 0 | 0 |
|
|
| axiIn_1_readOnly_decoder | Axi4ReadOnlyDecoder_1 | 181 | 181 | 0 | 0 | 17 | 0 | 0 | 0 |
|
|
| (axiIn_1_readOnly_decoder) | Axi4ReadOnlyDecoder_1 | 165 | 165 | 0 | 0 | 8 | 0 | 0 | 0 |
|
|
| errorSlave | Axi4ReadOnlyErrorSlave_1 | 16 | 16 | 0 | 0 | 9 | 0 | 0 | 0 |
|
|
| axiIn_1_writeOnly_decoder | Axi4WriteOnlyDecoder_1 | 26 | 26 | 0 | 0 | 14 | 0 | 0 | 0 |
|
|
| (axiIn_1_writeOnly_decoder) | Axi4WriteOnlyDecoder_1 | 19 | 19 | 0 | 0 | 12 | 0 | 0 | 0 |
|
|
| errorSlave | Axi4WriteOnlyErrorSlave_1 | 7 | 7 | 0 | 0 | 2 | 0 | 0 | 0 |
|
|
| u_Axi_CDC | Axi_CDC | 495 | 367 | 128 | 0 | 309 | 0 | 0 | 0 |
|
|
| arFifo | StreamFifoCC_3 | 257 | 221 | 36 | 0 | 73 | 0 | 0 | 0 |
|
|
| (arFifo) | StreamFifoCC_3 | 251 | 215 | 36 | 0 | 61 | 0 | 0 | 0 |
|
|
| popToPushGray_buffercc | BufferCC_9_48 | 1 | 1 | 0 | 0 | 6 | 0 | 0 | 0 |
|
|
| pushToPopGray_buffercc | BufferCC_11_49 | 5 | 5 | 0 | 0 | 6 | 0 | 0 | 0 |
|
|
| awFifo | StreamFifoCC | 111 | 75 | 36 | 0 | 75 | 0 | 0 | 0 |
|
|
| (awFifo) | StreamFifoCC | 104 | 68 | 36 | 0 | 61 | 0 | 0 | 0 |
|
|
| bufferCC_12 | BufferCC_10 | 1 | 1 | 0 | 0 | 2 | 0 | 0 | 0 |
|
|
| popToPushGray_buffercc | BufferCC_9 | 2 | 2 | 0 | 0 | 6 | 0 | 0 | 0 |
|
|
| pushToPopGray_buffercc | BufferCC_11 | 4 | 4 | 0 | 0 | 6 | 0 | 0 | 0 |
|
|
| bFifo | StreamFifoCC_2 | 14 | 14 | 0 | 0 | 26 | 0 | 0 | 0 |
|
|
| (bFifo) | StreamFifoCC_2 | 7 | 7 | 0 | 0 | 12 | 0 | 0 | 0 |
|
|
| bufferCC_12 | BufferCC_5 | 1 | 1 | 0 | 0 | 2 | 0 | 0 | 0 |
|
|
| popToPushGray_buffercc | BufferCC_4 | 2 | 2 | 0 | 0 | 6 | 0 | 0 | 0 |
|
|
| pushToPopGray_buffercc | BufferCC_6 | 4 | 4 | 0 | 0 | 6 | 0 | 0 | 0 |
|
|
| rFifo | StreamFifoCC_4 | 45 | 17 | 28 | 0 | 66 | 0 | 0 | 0 |
|
|
| (rFifo) | StreamFifoCC_4 | 41 | 13 | 28 | 0 | 50 | 0 | 0 | 0 |
|
|
| popToPushGray_buffercc | BufferCC | 3 | 3 | 0 | 0 | 8 | 0 | 0 | 0 |
|
|
| pushToPopGray_buffercc | BufferCC_1 | 2 | 2 | 0 | 0 | 8 | 0 | 0 | 0 |
|
|
| wFifo | StreamFifoCC_1 | 68 | 40 | 28 | 0 | 69 | 0 | 0 | 0 |
|
|
| (wFifo) | StreamFifoCC_1 | 64 | 36 | 28 | 0 | 53 | 0 | 0 | 0 |
|
|
| popToPushGray_buffercc | BufferCC_7 | 3 | 3 | 0 | 0 | 8 | 0 | 0 | 0 |
|
|
| pushToPopGray_buffercc | BufferCC_8 | 2 | 2 | 0 | 0 | 8 | 0 | 0 | 0 |
|
|
| u_axi_axil_adapter | axi_axil_adapter | 1339 | 1339 | 0 | 0 | 161 | 0 | 0 | 0 |
|
|
| axi_axil_adapter_rd_inst | axi_axil_adapter_rd | 635 | 635 | 0 | 0 | 81 | 0 | 0 | 0 |
|
|
| axi_axil_adapter_wr_inst | axi_axil_adapter_wr | 704 | 704 | 0 | 0 | 80 | 0 | 0 | 0 |
|
|
| u_axi_dvi | axi_dvi | 284 | 284 | 0 | 0 | 211 | 0 | 0 | 0 |
|
|
| u_axi_ram | axi_wrap_ram_sp_external | 355 | 355 | 0 | 0 | 78 | 0 | 0 | 0 |
|
|
| u_axi_sram_sp | axi2sram_sp_external | 355 | 355 | 0 | 0 | 78 | 0 | 0 | 0 |
|
|
| u_axi_uart_controller | axi_uart_controller | 686 | 670 | 16 | 0 | 457 | 0 | 0 | 0 |
|
|
| AA_axi2apb_bridge_cpu | axi2apb_bridge | 252 | 252 | 0 | 0 | 120 | 0 | 0 | 0 |
|
|
| uart0 | UART_TOP | 434 | 418 | 16 | 0 | 337 | 0 | 0 | 0 |
|
|
| regs | uart_regs | 434 | 418 | 16 | 0 | 337 | 0 | 0 | 0 |
|
|
| (regs) | uart_regs | 118 | 118 | 0 | 0 | 155 | 0 | 0 | 0 |
|
|
| i_uart_sync_flops | uart_sync_flops | 3 | 3 | 0 | 0 | 2 | 0 | 0 | 0 |
|
|
| receiver | uart_receiver | 229 | 221 | 8 | 0 | 124 | 0 | 0 | 0 |
|
|
| (receiver) | uart_receiver | 68 | 68 | 0 | 0 | 54 | 0 | 0 | 0 |
|
|
| fifo_rx | uart_rfifo | 161 | 153 | 8 | 0 | 70 | 0 | 0 | 0 |
|
|
| (fifo_rx) | uart_rfifo | 143 | 143 | 0 | 0 | 62 | 0 | 0 | 0 |
|
|
| rfifo | raminfr_47 | 19 | 11 | 8 | 0 | 8 | 0 | 0 | 0 |
|
|
| transmitter | uart_transmitter | 84 | 76 | 8 | 0 | 56 | 0 | 0 | 0 |
|
|
| (transmitter) | uart_transmitter | 41 | 41 | 0 | 0 | 35 | 0 | 0 | 0 |
|
|
| fifo_tx | uart_tfifo | 43 | 35 | 8 | 0 | 21 | 0 | 0 | 0 |
|
|
| (fifo_tx) | uart_tfifo | 24 | 24 | 0 | 0 | 13 | 0 | 0 | 0 |
|
|
| tfifo | raminfr | 19 | 11 | 8 | 0 | 8 | 0 | 0 | 0 |
|
|
| u_cdma_matmul_bridge | cdma_matmul_bridge | 247 | 247 | 0 | 0 | 578 | 0 | 0 | 0 |
|
|
| u_confreg | confreg | 390 | 390 | 0 | 0 | 476 | 0 | 0 | 0 |
|
|
| (u_confreg) | confreg | 230 | 230 | 0 | 0 | 399 | 0 | 0 | 0 |
|
|
| u_digitaltube_controller | digitaltube_controller | 16 | 16 | 0 | 0 | 24 | 0 | 0 | 0 |
|
|
| u_int_ctrl | int_ctrl | 144 | 144 | 0 | 0 | 53 | 0 | 0 | 0 |
|
|
| u_cpu | core_top | 8552 | 8300 | 252 | 0 | 5591 | 0 | 20 | 0 |
|
|
| (u_cpu) | core_top | 519 | 519 | 0 | 0 | 1 | 0 | 0 | 0 |
|
|
| addr_trans | addr_trans | 2246 | 2106 | 140 | 0 | 1244 | 0 | 0 | 0 |
|
|
| (addr_trans) | addr_trans | 0 | 0 | 0 | 0 | 40 | 0 | 0 | 0 |
|
|
| tlb_entry | tlb_entry | 2246 | 2106 | 140 | 0 | 1204 | 0 | 0 | 0 |
|
|
| axi_bridge | axi_bridge | 39 | 39 | 0 | 0 | 214 | 0 | 0 | 0 |
|
|
| btb | btb | 1048 | 968 | 80 | 0 | 1611 | 0 | 0 | 0 |
|
|
| (btb) | btb | 1045 | 965 | 80 | 0 | 1611 | 0 | 0 | 0 |
|
|
| dec_btb_add_entry | decoder_5_32 | 3 | 3 | 0 | 0 | 0 | 0 | 0 | 0 |
|
|
| dcache | dcache | 553 | 521 | 32 | 0 | 146 | 0 | 10 | 0 |
|
|
| (dcache) | dcache | 88 | 56 | 32 | 0 | 138 | 0 | 0 | 0 |
|
|
| data_ram_way[0].data_ram_bank[0].u | data_bank_sram_36 | 49 | 49 | 0 | 0 | 0 | 0 | 1 | 0 |
|
|
| data_ram_way[0].data_ram_bank[1].u | data_bank_sram_37 | 17 | 17 | 0 | 0 | 0 | 0 | 1 | 0 |
|
|
| data_ram_way[0].data_ram_bank[2].u | data_bank_sram_38 | 49 | 49 | 0 | 0 | 0 | 0 | 1 | 0 |
|
|
| data_ram_way[0].data_ram_bank[3].u | data_bank_sram_39 | 51 | 51 | 0 | 0 | 0 | 0 | 1 | 0 |
|
|
| data_ram_way[1].data_ram_bank[0].u | data_bank_sram_40 | 17 | 17 | 0 | 0 | 0 | 0 | 1 | 0 |
|
|
| data_ram_way[1].data_ram_bank[1].u | data_bank_sram_41 | 49 | 49 | 0 | 0 | 0 | 0 | 1 | 0 |
|
|
| data_ram_way[1].data_ram_bank[2].u | data_bank_sram_42 | 81 | 81 | 0 | 0 | 0 | 0 | 1 | 0 |
|
|
| data_ram_way[1].data_ram_bank[3].u | data_bank_sram_43 | 54 | 54 | 0 | 0 | 0 | 0 | 1 | 0 |
|
|
| lfsr | lfsr_44 | 2 | 2 | 0 | 0 | 8 | 0 | 0 | 0 |
|
|
| tagv_ram_way[0].u | tagv_sram_45 | 62 | 62 | 0 | 0 | 0 | 0 | 1 | 0 |
|
|
| tagv_ram_way[1].u | tagv_sram_46 | 42 | 42 | 0 | 0 | 0 | 0 | 1 | 0 |
|
|
| exe_stage | exe_stage | 664 | 664 | 0 | 0 | 233 | 0 | 0 | 0 |
|
|
| (exe_stage) | exe_stage | 633 | 633 | 0 | 0 | 233 | 0 | 0 | 0 |
|
|
| u_alu | alu | 33 | 33 | 0 | 0 | 0 | 0 | 0 | 0 |
|
|
| icache | icache | 235 | 235 | 0 | 0 | 55 | 0 | 10 | 0 |
|
|
| (icache) | icache | 12 | 12 | 0 | 0 | 47 | 0 | 0 | 0 |
|
|
| data_ram_way[0].data_ram_bank[0].u | data_bank_sram | 4 | 4 | 0 | 0 | 0 | 0 | 1 | 0 |
|
|
| data_ram_way[0].data_ram_bank[1].u | data_bank_sram_28 | 3 | 3 | 0 | 0 | 0 | 0 | 1 | 0 |
|
|
| data_ram_way[0].data_ram_bank[2].u | data_bank_sram_29 | 67 | 67 | 0 | 0 | 0 | 0 | 1 | 0 |
|
|
| data_ram_way[0].data_ram_bank[3].u | data_bank_sram_30 | 3 | 3 | 0 | 0 | 0 | 0 | 1 | 0 |
|
|
| data_ram_way[1].data_ram_bank[0].u | data_bank_sram_31 | 3 | 3 | 0 | 0 | 0 | 0 | 1 | 0 |
|
|
| data_ram_way[1].data_ram_bank[1].u | data_bank_sram_32 | 3 | 3 | 0 | 0 | 0 | 0 | 1 | 0 |
|
|
| data_ram_way[1].data_ram_bank[2].u | data_bank_sram_33 | 35 | 35 | 0 | 0 | 0 | 0 | 1 | 0 |
|
|
| data_ram_way[1].data_ram_bank[3].u | data_bank_sram_34 | 4 | 4 | 0 | 0 | 0 | 0 | 1 | 0 |
|
|
| lfsr | lfsr | 2 | 2 | 0 | 0 | 8 | 0 | 0 | 0 |
|
|
| tagv_ram_way[0].u | tagv_sram | 15 | 15 | 0 | 0 | 0 | 0 | 1 | 0 |
|
|
| tagv_ram_way[1].u | tagv_sram_35 | 88 | 88 | 0 | 0 | 0 | 0 | 1 | 0 |
|
|
| id_stage | id_stage | 1050 | 1050 | 0 | 0 | 108 | 0 | 0 | 0 |
|
|
| if_stage | if_stage | 134 | 134 | 0 | 0 | 173 | 0 | 0 | 0 |
|
|
| mem_stage | mem_stage | 115 | 115 | 0 | 0 | 211 | 0 | 0 | 0 |
|
|
| u_csr | csr | 200 | 200 | 0 | 0 | 663 | 0 | 0 | 0 |
|
|
| u_div | div | 142 | 142 | 0 | 0 | 107 | 0 | 0 | 0 |
|
|
| u_mul | mul | 935 | 935 | 0 | 0 | 592 | 0 | 0 | 0 |
|
|
| wb_stage | wb_stage | 684 | 684 | 0 | 0 | 233 | 0 | 0 | 0 |
|
|
| u_fft_mlkem_axi_slave | fft_mlkem_axi_slave | 47584 | 46544 | 0 | 1040 | 25915 | 10 | 10 | 0 |
|
|
| (u_fft_mlkem_axi_slave) | fft_mlkem_axi_slave | 17 | 17 | 0 | 0 | 6 | 0 | 0 | 0 |
|
|
| u_fft_controller | fft_controller | 6890 | 5850 | 0 | 1040 | 1087 | 8 | 4 | 0 |
|
|
| (u_fft_controller) | fft_controller | 90 | 90 | 0 | 0 | 104 | 0 | 0 | 0 |
|
|
| u_FFT | FFT | 6781 | 5741 | 0 | 1040 | 983 | 8 | 0 | 0 |
|
|
| SU1 | SdfUnit | 2145 | 1377 | 0 | 768 | 197 | 2 | 0 | 0 |
|
|
| (SU1) | SdfUnit | 39 | 39 | 0 | 0 | 133 | 0 | 0 | 0 |
|
|
| BF1 | Butterfly_24 | 16 | 16 | 0 | 0 | 0 | 0 | 0 | 0 |
|
|
| BF2 | Butterfly__parameterized0_25 | 32 | 32 | 0 | 0 | 0 | 0 | 0 | 0 |
|
|
| DB1 | DelayBuffer | 624 | 112 | 0 | 512 | 32 | 0 | 0 | 0 |
|
|
| DB2 | DelayBuffer__parameterized0 | 320 | 64 | 0 | 256 | 32 | 0 | 0 | 0 |
|
|
| MU | Multiply_26 | 611 | 611 | 0 | 0 | 0 | 0 | 0 | 0 |
|
|
| TW | Twiddle_27 | 543 | 543 | 0 | 0 | 0 | 2 | 0 | 0 |
|
|
| SU2 | SdfUnit__parameterized0 | 1566 | 1374 | 0 | 192 | 197 | 2 | 0 | 0 |
|
|
| (SU2) | SdfUnit__parameterized0 | 38 | 38 | 0 | 0 | 133 | 0 | 0 | 0 |
|
|
| BF1 | Butterfly_20 | 16 | 16 | 0 | 0 | 0 | 0 | 0 | 0 |
|
|
| BF2 | Butterfly__parameterized0_21 | 32 | 32 | 0 | 0 | 0 | 0 | 0 | 0 |
|
|
| DB1 | DelayBuffer__parameterized1 | 240 | 112 | 0 | 128 | 32 | 0 | 0 | 0 |
|
|
| DB2 | DelayBuffer__parameterized2 | 128 | 64 | 0 | 64 | 32 | 0 | 0 | 0 |
|
|
| MU | Multiply_22 | 611 | 611 | 0 | 0 | 0 | 0 | 0 | 0 |
|
|
| TW | Twiddle_23 | 541 | 541 | 0 | 0 | 0 | 2 | 0 | 0 |
|
|
| SU3 | SdfUnit__parameterized1 | 1415 | 1367 | 0 | 48 | 197 | 2 | 0 | 0 |
|
|
| (SU3) | SdfUnit__parameterized1 | 35 | 35 | 0 | 0 | 133 | 0 | 0 | 0 |
|
|
| BF1 | Butterfly_16 | 16 | 16 | 0 | 0 | 0 | 0 | 0 | 0 |
|
|
| BF2 | Butterfly__parameterized0_17 | 32 | 32 | 0 | 0 | 0 | 0 | 0 | 0 |
|
|
| DB1 | DelayBuffer__parameterized3 | 144 | 112 | 0 | 32 | 32 | 0 | 0 | 0 |
|
|
| DB2 | DelayBuffer__parameterized4 | 80 | 64 | 0 | 16 | 32 | 0 | 0 | 0 |
|
|
| MU | Multiply_18 | 609 | 609 | 0 | 0 | 0 | 0 | 0 | 0 |
|
|
| TW | Twiddle_19 | 539 | 539 | 0 | 0 | 0 | 2 | 0 | 0 |
|
|
| SU4 | SdfUnit__parameterized2 | 1397 | 1365 | 0 | 32 | 197 | 2 | 0 | 0 |
|
|
| (SU4) | SdfUnit__parameterized2 | 34 | 34 | 0 | 0 | 133 | 0 | 0 | 0 |
|
|
| BF1 | Butterfly_14 | 16 | 16 | 0 | 0 | 0 | 0 | 0 | 0 |
|
|
| BF2 | Butterfly__parameterized0_15 | 32 | 32 | 0 | 0 | 0 | 0 | 0 | 0 |
|
|
| DB1 | DelayBuffer__parameterized5 | 128 | 112 | 0 | 16 | 32 | 0 | 0 | 0 |
|
|
| DB2 | DelayBuffer__parameterized6 | 80 | 64 | 0 | 16 | 32 | 0 | 0 | 0 |
|
|
| MU | Multiply | 611 | 611 | 0 | 0 | 0 | 0 | 0 | 0 |
|
|
| TW | Twiddle | 536 | 536 | 0 | 0 | 0 | 2 | 0 | 0 |
|
|
| SU5 | SdfUnit__parameterized3 | 259 | 259 | 0 | 0 | 195 | 0 | 0 | 0 |
|
|
| (SU5) | SdfUnit__parameterized3 | 35 | 35 | 0 | 0 | 99 | 0 | 0 | 0 |
|
|
| BF1 | Butterfly | 16 | 16 | 0 | 0 | 0 | 0 | 0 | 0 |
|
|
| BF2 | Butterfly__parameterized0 | 32 | 32 | 0 | 0 | 0 | 0 | 0 | 0 |
|
|
| DB1 | DelayBuffer__parameterized7 | 112 | 112 | 0 | 0 | 64 | 0 | 0 | 0 |
|
|
| DB2 | DelayBuffer__parameterized8 | 64 | 64 | 0 | 0 | 32 | 0 | 0 | 0 |
|
|
| u_in0 | my_bram0 | 2 | 2 | 0 | 0 | 0 | 0 | 1 | 0 |
|
|
| u_in1 | my_bram0_11 | 2 | 2 | 0 | 0 | 0 | 0 | 1 | 0 |
|
|
| u_out0 | my_bram0_12 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 |
|
|
| u_out1 | my_bram0_13 | 17 | 17 | 0 | 0 | 0 | 0 | 1 | 0 |
|
|
| u_mlkem_axi_slave | mlkem_axi_slave | 40179 | 40179 | 0 | 0 | 24484 | 2 | 6 | 0 |
|
|
| (u_mlkem_axi_slave) | mlkem_axi_slave | 3620 | 3620 | 0 | 0 | 1021 | 0 | 0 | 0 |
|
|
| u_mlkem | mlkem_top | 36605 | 36605 | 0 | 0 | 23463 | 2 | 6 | 0 |
|
|
| (u_mlkem) | mlkem_top | 2505 | 2505 | 0 | 0 | 4907 | 0 | 0 | 0 |
|
|
| u_bank_a | sd_bram__parameterized0 | 39 | 39 | 0 | 0 | 0 | 1 | 1 | 0 |
|
|
| u_bank_se | sd_bram__parameterized1 | 62 | 62 | 0 | 0 | 0 | 1 | 0 | 0 |
|
|
| u_bank_t | sd_bram__parameterized2 | 468 | 468 | 0 | 0 | 0 | 0 | 1 | 0 |
|
|
| u_c_in_bram | sd_bram | 1291 | 1291 | 0 | 0 | 0 | 0 | 1 | 0 |
|
|
| u_cbd | sample_cbd_sync_shared | 2459 | 2459 | 0 | 0 | 3199 | 0 | 0 | 0 |
|
|
| u_comp | comp_decomp_sync | 177 | 177 | 0 | 0 | 13 | 0 | 0 | 0 |
|
|
| u_pipe | pipeline_reg | 177 | 177 | 0 | 0 | 13 | 0 | 0 | 0 |
|
|
| u_ct_bram | sd_bram_4 | 15 | 15 | 0 | 0 | 0 | 0 | 1 | 0 |
|
|
| u_dkp_bram | sd_bram_5 | 100 | 100 | 0 | 0 | 0 | 0 | 1 | 0 |
|
|
| u_ek_bram | sd_bram_6 | 225 | 225 | 0 | 0 | 0 | 0 | 1 | 0 |
|
|
| u_keccak | keccak_core | 5240 | 5240 | 0 | 0 | 1619 | 0 | 0 | 0 |
|
|
| u_ntt | ntt_core | 13299 | 13299 | 0 | 0 | 3354 | 0 | 0 | 0 |
|
|
| u_pmul | poly_mul_sync | 7336 | 7336 | 0 | 0 | 6314 | 0 | 0 | 0 |
|
|
| (u_pmul) | poly_mul_sync | 4958 | 4958 | 0 | 0 | 6314 | 0 | 0 | 0 |
|
|
| u_bc | basecase_mul | 2378 | 2378 | 0 | 0 | 0 | 0 | 0 | 0 |
|
|
| (u_bc) | basecase_mul | 52 | 52 | 0 | 0 | 0 | 0 | 0 | 0 |
|
|
| u_mul1 | barrett_mul | 969 | 969 | 0 | 0 | 0 | 0 | 0 | 0 |
|
|
| u_mul2 | barrett_mul_7 | 118 | 118 | 0 | 0 | 0 | 0 | 0 | 0 |
|
|
| u_mul3 | barrett_mul_8 | 561 | 561 | 0 | 0 | 0 | 0 | 0 | 0 |
|
|
| u_mul4 | barrett_mul_9 | 549 | 549 | 0 | 0 | 0 | 0 | 0 | 0 |
|
|
| u_mul_zeta | barrett_mul_10 | 129 | 129 | 0 | 0 | 0 | 0 | 0 | 0 |
|
|
| u_sha3 | sha3_top_shared | 1970 | 1970 | 0 | 0 | 2388 | 0 | 0 | 0 |
|
|
| u_snt | sample_ntt_sync_shared | 1433 | 1433 | 0 | 0 | 1669 | 0 | 0 | 0 |
|
|
| u_prng_axi_slave | prng_axi_slave | 500 | 500 | 0 | 0 | 338 | 0 | 0 | 0 |
|
|
| u_matmul_axi_slave | matmul_axi_slave | 9858 | 9676 | 176 | 6 | 3208 | 0 | 0 | 0 |
|
|
| (u_matmul_axi_slave) | matmul_axi_slave | 5742 | 5560 | 176 | 6 | 2440 | 0 | 0 | 0 |
|
|
| mult_inst[0].u_mult | pipelined_mult_32x32 | 1062 | 1062 | 0 | 0 | 192 | 0 | 0 | 0 |
|
|
| mult_inst[1].u_mult | pipelined_mult_32x32_1 | 998 | 998 | 0 | 0 | 192 | 0 | 0 | 0 |
|
|
| mult_inst[2].u_mult | pipelined_mult_32x32_2 | 1061 | 1061 | 0 | 0 | 192 | 0 | 0 | 0 |
|
|
| mult_inst[3].u_mult | pipelined_mult_32x32_3 | 996 | 996 | 0 | 0 | 192 | 0 | 0 | 0 |
|
|
| u_snix_axil_cdma_mux_8ch | snix_axil_cdma_mux | 1813 | 1813 | 0 | 0 | 1476 | 0 | 1 | 0 |
|
|
| (u_snix_axil_cdma_mux_8ch) | snix_axil_cdma_mux | 604 | 604 | 0 | 0 | 1180 | 0 | 0 | 0 |
|
|
| u_core_engine | snix_axi_mm2mm | 1211 | 1211 | 0 | 0 | 296 | 0 | 1 | 0 |
|
|
| (u_core_engine) | snix_axi_mm2mm | 773 | 773 | 0 | 0 | 243 | 0 | 0 | 0 |
|
|
| axis_fifo_u0 | snix_axis_fifo | 438 | 438 | 0 | 0 | 53 | 0 | 1 | 0 |
|
|
| u_fifo | snix_sync_fifo | 438 | 438 | 0 | 0 | 53 | 0 | 1 | 0 |
|
|
+------------------------------------------+------------------------------+------------+------------+---------+------+-------+--------+--------+--------------+
|
|
* Note: The sum of lower-level cells may be larger than their parent cells total, due to cross-hierarchy LUT combining
|
|
|
|
|