439 lines
39 KiB
Plaintext
439 lines
39 KiB
Plaintext
Copyright 1986-2019 Xilinx, Inc. All Rights Reserved.
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| Tool Version : Vivado v.2019.2 (lin64) Build 2708876 Wed Nov 6 21:39:14 MST 2019
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| Date : Sun Jul 5 23:46:27 2026
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| Host : fedora running 64-bit unknown
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| Command : report_clock_utilization -file ./vivado_reports_impl/routed_clock_utilization.rpt
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| Design : soc_top
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| Device : 7a200t-fbg676
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| Speed File : -1 PRODUCTION 1.23 2018-06-13
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| Design State : Routed
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Clock Utilization Report
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Table of Contents
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-----------------
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1. Clock Primitive Utilization
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2. Global Clock Resources
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3. Global Clock Source Details
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4. Clock Regions: Key Resource Utilization
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5. Clock Regions : Global Clock Summary
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6. Device Cell Placement Summary for Global Clock g0
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7. Device Cell Placement Summary for Global Clock g1
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8. Device Cell Placement Summary for Global Clock g2
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9. Device Cell Placement Summary for Global Clock g3
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10. Device Cell Placement Summary for Global Clock g4
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11. Clock Region Cell Placement per Global Clock: Region X0Y0
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12. Clock Region Cell Placement per Global Clock: Region X1Y0
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13. Clock Region Cell Placement per Global Clock: Region X0Y1
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14. Clock Region Cell Placement per Global Clock: Region X1Y1
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15. Clock Region Cell Placement per Global Clock: Region X0Y2
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16. Clock Region Cell Placement per Global Clock: Region X1Y2
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17. Clock Region Cell Placement per Global Clock: Region X0Y3
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18. Clock Region Cell Placement per Global Clock: Region X1Y3
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19. Clock Region Cell Placement per Global Clock: Region X0Y4
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20. Clock Region Cell Placement per Global Clock: Region X1Y4
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1. Clock Primitive Utilization
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------------------------------
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+----------+------+-----------+-----+--------------+--------+
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| Type | Used | Available | LOC | Clock Region | Pblock |
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+----------+------+-----------+-----+--------------+--------+
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| BUFGCTRL | 5 | 32 | 0 | 0 | 0 |
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| BUFH | 0 | 120 | 0 | 0 | 0 |
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| BUFIO | 0 | 40 | 0 | 0 | 0 |
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| BUFMR | 0 | 20 | 0 | 0 | 0 |
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| BUFR | 0 | 40 | 0 | 0 | 0 |
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| MMCM | 0 | 10 | 0 | 0 | 0 |
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| PLL | 1 | 10 | 0 | 0 | 0 |
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+----------+------+-----------+-----+--------------+--------+
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2. Global Clock Resources
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-------------------------
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+-----------+-----------+-----------------+------------+----------------+--------------+-------------------+-------------+-----------------+--------------+------------------+--------------------------------------+---------------------------------------------+
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| Global Id | Source Id | Driver Type/Pin | Constraint | Site | Clock Region | Load Clock Region | Clock Loads | Non-Clock Loads | Clock Period | Clock | Driver Pin | Net |
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+-----------+-----------+-----------------+------------+----------------+--------------+-------------------+-------------+-----------------+--------------+------------------+--------------------------------------+---------------------------------------------+
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| g0 | src0 | BUFG/O | None | BUFGCTRL_X0Y1 | n/a | 8 | 23490 | 0 | | | r_wb_reg[7]_i_3/O | u_mlkem_axi_slave/mlkem_clk |
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| g1 | src1 | BUFG/O | None | BUFGCTRL_X0Y16 | n/a | 7 | 10620 | 1 | 20.000 | sys_clk | pll_clk.u_clk_pll/inst/clkout2_buf/O | pll_clk.u_clk_pll/inst/sys_clk |
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| g2 | src1 | BUFG/O | None | BUFGCTRL_X0Y17 | n/a | 4 | 5859 | 0 | 30.323 | cpu_clk | pll_clk.u_clk_pll/inst/clkout1_buf/O | pll_clk.u_clk_pll/inst/cpu_clk |
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| g3 | src1 | BUFG/O | None | BUFGCTRL_X0Y18 | n/a | 1 | 1 | 0 | 20.000 | clkfbout_clk_pll | pll_clk.u_clk_pll/inst/clkf_buf/O | pll_clk.u_clk_pll/inst/clkfbout_buf_clk_pll |
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| g4 | src2 | BUFG/O | None | BUFGCTRL_X0Y0 | n/a | 10 | 0 | 28783 | n/a | n/a | pll_clk.u_rst_sys/p_0_in_BUFG_inst/O | pll_clk.u_rst_sys/p_0_in_BUFG |
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+-----------+-----------+-----------------+------------+----------------+--------------+-------------------+-------------+-----------------+--------------+------------------+--------------------------------------+---------------------------------------------+
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* Clock Loads column represents the clock pin loads (pin count)
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** Non-Clock Loads column represents the non-clock pin loads (pin count)
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3. Global Clock Source Details
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------------------------------
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+-----------+-----------+--------------------+------------+----------------+--------------+-------------+-----------------+---------------------+------------------+---------------------------------------------------------+---------------------------------------------------------+
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| Source Id | Global Id | Driver Type/Pin | Constraint | Site | Clock Region | Clock Loads | Non-Clock Loads | Source Clock Period | Source Clock | Driver Pin | Net |
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+-----------+-----------+--------------------+------------+----------------+--------------+-------------+-----------------+---------------------+------------------+---------------------------------------------------------+---------------------------------------------------------+
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| src0 | g0 | FDCE/Q | None | SLICE_X84Y146 | X1Y2 | 1 | 1 | | | u_fft_mlkem_axi_slave/u_mlkem_axi_slave/mlkem_clk_reg/Q | u_fft_mlkem_axi_slave/u_mlkem_axi_slave/mlkem_clk_reg_0 |
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| src1 | g3 | PLLE2_ADV/CLKFBOUT | None | PLLE2_ADV_X0Y3 | X0Y3 | 1 | 0 | 20.000 | clkfbout_clk_pll | pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKFBOUT | pll_clk.u_clk_pll/inst/clkfbout_clk_pll |
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| src1 | g2 | PLLE2_ADV/CLKOUT0 | None | PLLE2_ADV_X0Y3 | X0Y3 | 1 | 0 | 30.323 | cpu_clk | pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 | pll_clk.u_clk_pll/inst/cpu_clk_clk_pll |
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| src1 | g1 | PLLE2_ADV/CLKOUT1 | None | PLLE2_ADV_X0Y3 | X0Y3 | 1 | 0 | 20.000 | sys_clk | pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 | pll_clk.u_clk_pll/inst/sys_clk_clk_pll |
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| src2 | g4 | LUT1/O | None | SLICE_X132Y68 | X1Y1 | 1 | 0 | | | pll_clk.u_rst_sys/r_wb[7]_i_4/O | pll_clk.u_rst_sys/p_0_in |
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+-----------+-----------+--------------------+------------+----------------+--------------+-------------+-----------------+---------------------+------------------+---------------------------------------------------------+---------------------------------------------------------+
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* Clock Loads column represents the clock pin loads (pin count)
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** Non-Clock Loads column represents the non-clock pin loads (pin count)
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4. Clock Regions: Key Resource Utilization
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------------------------------------------
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+-------------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+
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| | Global Clock | BUFRs | BUFMRs | BUFIOs | MMCM | PLL | GT | PCI | ILOGIC | OLOGIC | FF | LUTM | RAMB18 | RAMB36 | DSP48E2 |
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+-------------------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+
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| Clock Region Name | Used | Avail | Used | Avail | Used | Avail | Used | Avail | Used | Avail | Used | Avail | Used | Avail | Used | Avail | Used | Avail | Used | Avail | Used | Avail | Used | Avail | Used | Avail | Used | Avail | Used | Avail |
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+-------------------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+
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| X0Y0 | 3 | 12 | 0 | 4 | 0 | 2 | 0 | 4 | 0 | 1 | 0 | 1 | 0 | 4 | 0 | 0 | 0 | 50 | 0 | 50 | 5680 | 2700 | 1523 | 800 | 8 | 60 | 0 | 30 | 0 | 60 |
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| X1Y0 | 3 | 12 | 0 | 4 | 0 | 2 | 0 | 4 | 0 | 1 | 0 | 1 | 0 | 4 | 0 | 0 | 0 | 50 | 0 | 50 | 922 | 2500 | 677 | 800 | 0 | 40 | 6 | 20 | 0 | 40 |
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| X0Y1 | 4 | 12 | 0 | 4 | 0 | 2 | 0 | 4 | 0 | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 50 | 0 | 50 | 8433 | 4200 | 2794 | 1400 | 1 | 100 | 0 | 50 | 0 | 100 |
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| X1Y1 | 4 | 12 | 0 | 4 | 0 | 2 | 0 | 4 | 0 | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 50 | 0 | 50 | 6621 | 4000 | 2851 | 1400 | 3 | 80 | 2 | 40 | 0 | 80 |
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| X0Y2 | 3 | 12 | 0 | 4 | 0 | 2 | 0 | 4 | 0 | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 50 | 0 | 50 | 3500 | 3600 | 1397 | 1400 | 0 | 100 | 0 | 50 | 0 | 100 |
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| X1Y2 | 3 | 12 | 0 | 4 | 0 | 2 | 0 | 4 | 0 | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 50 | 0 | 50 | 4349 | 4000 | 1624 | 1400 | 1 | 80 | 2 | 40 | 0 | 80 |
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| X0Y3 | 4 | 12 | 0 | 4 | 0 | 2 | 0 | 4 | 0 | 1 | 1 | 1 | 0 | 0 | 0 | 0 | 0 | 50 | 0 | 50 | 5614 | 3600 | 2576 | 1400 | 0 | 100 | 0 | 50 | 0 | 100 |
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| X1Y3 | 2 | 12 | 0 | 4 | 0 | 2 | 0 | 4 | 0 | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 50 | 0 | 50 | 2775 | 4000 | 1183 | 1400 | 0 | 80 | 0 | 40 | 0 | 80 |
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| X0Y4 | 2 | 12 | 0 | 4 | 0 | 2 | 0 | 4 | 0 | 1 | 0 | 1 | 0 | 4 | 0 | 1 | 0 | 50 | 0 | 50 | 671 | 2550 | 155 | 750 | 0 | 50 | 0 | 25 | 0 | 60 |
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| X1Y4 | 2 | 12 | 0 | 4 | 0 | 2 | 0 | 4 | 0 | 1 | 0 | 1 | 0 | 4 | 0 | 0 | 0 | 50 | 0 | 50 | 54 | 2500 | 18 | 800 | 0 | 40 | 0 | 20 | 0 | 40 |
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+-------------------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+
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* Global Clock column represents track count; while other columns represents cell counts
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5. Clock Regions : Global Clock Summary
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---------------------------------------
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All Modules
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+----+----+----+
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| | X0 | X1 |
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+----+----+----+
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| Y4 | 2 | 2 |
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| Y3 | 4 | 2 |
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| Y2 | 3 | 3 |
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| Y1 | 4 | 4 |
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| Y0 | 3 | 3 |
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+----+----+----+
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6. Device Cell Placement Summary for Global Clock g0
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----------------------------------------------------
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+-----------+-----------------+-------------------+-------+-------------+---------------+-------------+----------+----------------+----------+-----------------------------+
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| Global Id | Driver Type/Pin | Driver Region (D) | Clock | Period (ns) | Waveform (ns) | Slice Loads | IO Loads | Clocking Loads | GT Loads | Net |
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+-----------+-----------------+-------------------+-------+-------------+---------------+-------------+----------+----------------+----------+-----------------------------+
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| g0 | BUFG/O | n/a | | | | 23482 | 0 | 0 | 0 | u_mlkem_axi_slave/mlkem_clk |
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+-----------+-----------------+-------------------+-------+-------------+---------------+-------------+----------+----------------+----------+-----------------------------+
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* Slice Loads column represents load cell count of all cell types other than IO, GT and clock resources
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** IO Loads column represents load cell count of IO types
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*** Clocking Loads column represents load cell count that are clock resources (global clock buffer, MMCM, PLL, etc)
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**** GT Loads column represents load cell count of GT types
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+----+-------+-------+
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| | X0 | X1 |
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+----+-------+-------+
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| Y4 | 671 | 54 |
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| Y3 | 5614 | 2775 |
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| Y2 | 2763 | 4352 |
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| Y1 | 1435 | 5818 |
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| Y0 | 0 | 0 |
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+----+-------+-------+
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7. Device Cell Placement Summary for Global Clock g1
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----------------------------------------------------
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+-----------+-----------------+-------------------+---------+-------------+----------------+-------------+----------+----------------+----------+--------------------------------+
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| Global Id | Driver Type/Pin | Driver Region (D) | Clock | Period (ns) | Waveform (ns) | Slice Loads | IO Loads | Clocking Loads | GT Loads | Net |
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+-----------+-----------------+-------------------+---------+-------------+----------------+-------------+----------+----------------+----------+--------------------------------+
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| g1 | BUFG/O | n/a | sys_clk | 20.000 | {0.000 10.000} | 10556 | 1 | 0 | 0 | pll_clk.u_clk_pll/inst/sys_clk |
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+-----------+-----------------+-------------------+---------+-------------+----------------+-------------+----------+----------------+----------+--------------------------------+
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* Slice Loads column represents load cell count of all cell types other than IO, GT and clock resources
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** IO Loads column represents load cell count of IO types
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*** Clocking Loads column represents load cell count that are clock resources (global clock buffer, MMCM, PLL, etc)
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**** GT Loads column represents load cell count of GT types
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+----+-------+-------+
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| | X0 | X1 |
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+----+-------+-------+
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| Y4 | 0 | 0 |
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| Y3 | 1 | 0 |
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| Y2 | 737 | 1 |
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| Y1 | 6977 | 1518 |
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| Y0 | 174 | 1149 |
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+----+-------+-------+
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8. Device Cell Placement Summary for Global Clock g2
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----------------------------------------------------
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+-----------+-----------------+-------------------+---------+-------------+----------------+-------------+----------+----------------+----------+--------------------------------+
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| Global Id | Driver Type/Pin | Driver Region (D) | Clock | Period (ns) | Waveform (ns) | Slice Loads | IO Loads | Clocking Loads | GT Loads | Net |
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+-----------+-----------------+-------------------+---------+-------------+----------------+-------------+----------+----------------+----------+--------------------------------+
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| g2 | BUFG/O | n/a | cpu_clk | 30.323 | {0.000 15.161} | 5716 | 0 | 0 | 0 | pll_clk.u_clk_pll/inst/cpu_clk |
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+-----------+-----------------+-------------------+---------+-------------+----------------+-------------+----------+----------------+----------+--------------------------------+
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* Slice Loads column represents load cell count of all cell types other than IO, GT and clock resources
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** IO Loads column represents load cell count of IO types
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*** Clocking Loads column represents load cell count that are clock resources (global clock buffer, MMCM, PLL, etc)
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**** GT Loads column represents load cell count of GT types
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+----+-------+-----+
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| | X0 | X1 |
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+----+-------+-----+
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| Y4 | 0 | 0 |
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| Y3 | 0 | 0 |
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| Y2 | 0 | 0 |
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| Y1 | 86 | 9 |
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| Y0 | 5526 | 95 |
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+----+-------+-----+
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9. Device Cell Placement Summary for Global Clock g3
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----------------------------------------------------
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+-----------+-----------------+-------------------+------------------+-------------+----------------+-------------+----------+----------------+----------+---------------------------------------------+
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| Global Id | Driver Type/Pin | Driver Region (D) | Clock | Period (ns) | Waveform (ns) | Slice Loads | IO Loads | Clocking Loads | GT Loads | Net |
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+-----------+-----------------+-------------------+------------------+-------------+----------------+-------------+----------+----------------+----------+---------------------------------------------+
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| g3 | BUFG/O | n/a | clkfbout_clk_pll | 20.000 | {0.000 10.000} | 0 | 0 | 1 | 0 | pll_clk.u_clk_pll/inst/clkfbout_buf_clk_pll |
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+-----------+-----------------+-------------------+------------------+-------------+----------------+-------------+----------+----------------+----------+---------------------------------------------+
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* Slice Loads column represents load cell count of all cell types other than IO, GT and clock resources
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** IO Loads column represents load cell count of IO types
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*** Clocking Loads column represents load cell count that are clock resources (global clock buffer, MMCM, PLL, etc)
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**** GT Loads column represents load cell count of GT types
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+----+----+----+
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| | X0 | X1 |
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+----+----+----+
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| Y4 | 0 | 0 |
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| Y3 | 1 | 0 |
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| Y2 | 0 | 0 |
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| Y1 | 0 | 0 |
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| Y0 | 0 | 0 |
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+----+----+----+
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10. Device Cell Placement Summary for Global Clock g4
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-----------------------------------------------------
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+-----------+-----------------+-------------------+-------+-------------+---------------+-------------+----------+----------------+----------+-------------------------------+
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| Global Id | Driver Type/Pin | Driver Region (D) | Clock | Period (ns) | Waveform (ns) | Slice Loads | IO Loads | Clocking Loads | GT Loads | Net |
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+-----------+-----------------+-------------------+-------+-------------+---------------+-------------+----------+----------------+----------+-------------------------------+
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| g4 | BUFG/O | n/a | | | | 28783 | 0 | 0 | 0 | pll_clk.u_rst_sys/p_0_in_BUFG |
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+-----------+-----------------+-------------------+-------+-------------+---------------+-------------+----------+----------------+----------+-------------------------------+
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* Slice Loads column represents load cell count of all cell types other than IO, GT and clock resources
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** IO Loads column represents load cell count of IO types
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*** Clocking Loads column represents load cell count that are clock resources (global clock buffer, MMCM, PLL, etc)
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**** GT Loads column represents load cell count of GT types
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+----+-------+-------+
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| | X0 | X1 |
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+----+-------+-------+
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| Y4 | 671 | 54 |
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| Y3 | 5614 | 2775 |
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| Y2 | 3295 | 4349 |
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| Y1 | 5550 | 6266 |
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| Y0 | 61 | 148 |
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+----+-------+-------+
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11. Clock Region Cell Placement per Global Clock: Region X0Y0
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-------------------------------------------------------------
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+-----------+-------+-----------------+------------+-------------+-----------------+------+--------+------+-----+----+------+-----+---------+--------------------------------+
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| Global Id | Track | Driver Type/Pin | Constraint | Clock Loads | Non-Clock Loads | FF | LUTRAM | RAMB | DSP | GT | MMCM | PLL | Hard IP | Net |
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+-----------+-------+-----------------+------------+-------------+-----------------+------+--------+------+-----+----+------+-----+---------+--------------------------------+
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| g1 | n/a | BUFG/O | None | 174 | 0 | 174 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | pll_clk.u_clk_pll/inst/sys_clk |
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| g2 | n/a | BUFG/O | None | 5526 | 0 | 5506 | 0 | 8 | 0 | 0 | 0 | 0 | 0 | pll_clk.u_clk_pll/inst/cpu_clk |
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| g4 | n/a | BUFG/O | None | 0 | 61 | 61 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | pll_clk.u_rst_sys/p_0_in_BUFG |
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+-----------+-------+-----------------+------------+-------------+-----------------+------+--------+------+-----+----+------+-----+---------+--------------------------------+
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* Clock Loads column represents the clock pin loads (pin count)
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** Non-Clock Loads column represents the non-clock pin loads (pin count)
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*** Columns FF, LUTRAM, RAMB through 'Hard IP' represents load cell counts
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12. Clock Region Cell Placement per Global Clock: Region X1Y0
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-------------------------------------------------------------
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+-----------+-------+-----------------+------------+-------------+-----------------+-----+--------+------+-----+----+------+-----+---------+--------------------------------+
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| Global Id | Track | Driver Type/Pin | Constraint | Clock Loads | Non-Clock Loads | FF | LUTRAM | RAMB | DSP | GT | MMCM | PLL | Hard IP | Net |
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+-----------+-------+-----------------+------------+-------------+-----------------+-----+--------+------+-----+----+------+-----+---------+--------------------------------+
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| g1 | n/a | BUFG/O | None | 1149 | 0 | 827 | 316 | 6 | 0 | 0 | 0 | 0 | 0 | pll_clk.u_clk_pll/inst/sys_clk |
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| g2 | n/a | BUFG/O | None | 95 | 0 | 95 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | pll_clk.u_clk_pll/inst/cpu_clk |
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| g4 | n/a | BUFG/O | None | 0 | 148 | 148 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | pll_clk.u_rst_sys/p_0_in_BUFG |
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+-----------+-------+-----------------+------------+-------------+-----------------+-----+--------+------+-----+----+------+-----+---------+--------------------------------+
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* Clock Loads column represents the clock pin loads (pin count)
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** Non-Clock Loads column represents the non-clock pin loads (pin count)
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*** Columns FF, LUTRAM, RAMB through 'Hard IP' represents load cell counts
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13. Clock Region Cell Placement per Global Clock: Region X0Y1
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-------------------------------------------------------------
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+-----------+-------+-----------------+------------+-------------+-----------------+------+--------+------+-----+----+------+-----+---------+--------------------------------+
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| Global Id | Track | Driver Type/Pin | Constraint | Clock Loads | Non-Clock Loads | FF | LUTRAM | RAMB | DSP | GT | MMCM | PLL | Hard IP | Net |
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+-----------+-------+-----------------+------------+-------------+-----------------+------+--------+------+-----+----+------+-----+---------+--------------------------------+
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| g0 | n/a | BUFG/O | None | 1435 | 0 | 1435 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | u_mlkem_axi_slave/mlkem_clk |
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| g1 | n/a | BUFG/O | None | 6977 | 0 | 6912 | 62 | 1 | 0 | 0 | 0 | 0 | 0 | pll_clk.u_clk_pll/inst/sys_clk |
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| g2 | n/a | BUFG/O | None | 86 | 0 | 86 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | pll_clk.u_clk_pll/inst/cpu_clk |
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| g4 | n/a | BUFG/O | None | 0 | 5550 | 5550 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | pll_clk.u_rst_sys/p_0_in_BUFG |
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+-----------+-------+-----------------+------------+-------------+-----------------+------+--------+------+-----+----+------+-----+---------+--------------------------------+
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* Clock Loads column represents the clock pin loads (pin count)
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** Non-Clock Loads column represents the non-clock pin loads (pin count)
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*** Columns FF, LUTRAM, RAMB through 'Hard IP' represents load cell counts
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14. Clock Region Cell Placement per Global Clock: Region X1Y1
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-------------------------------------------------------------
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+-----------+-------+-----------------+------------+-------------+-----------------+------+--------+------+-----+----+------+-----+---------+--------------------------------+
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| Global Id | Track | Driver Type/Pin | Constraint | Clock Loads | Non-Clock Loads | FF | LUTRAM | RAMB | DSP | GT | MMCM | PLL | Hard IP | Net |
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+-----------+-------+-----------------+------------+-------------+-----------------+------+--------+------+-----+----+------+-----+---------+--------------------------------+
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| g0 | n/a | BUFG/O | None | 5818 | 0 | 5814 | 0 | 2 | 0 | 0 | 0 | 0 | 0 | u_mlkem_axi_slave/mlkem_clk |
|
|
| g1 | n/a | BUFG/O | None | 1518 | 0 | 798 | 716 | 3 | 0 | 0 | 0 | 0 | 0 | pll_clk.u_clk_pll/inst/sys_clk |
|
|
| g2 | n/a | BUFG/O | None | 9 | 0 | 9 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | pll_clk.u_clk_pll/inst/cpu_clk |
|
|
| g4 | n/a | BUFG/O | None | 0 | 6266 | 6266 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | pll_clk.u_rst_sys/p_0_in_BUFG |
|
|
+-----------+-------+-----------------+------------+-------------+-----------------+------+--------+------+-----+----+------+-----+---------+--------------------------------+
|
|
* Clock Loads column represents the clock pin loads (pin count)
|
|
** Non-Clock Loads column represents the non-clock pin loads (pin count)
|
|
*** Columns FF, LUTRAM, RAMB through 'Hard IP' represents load cell counts
|
|
|
|
|
|
15. Clock Region Cell Placement per Global Clock: Region X0Y2
|
|
-------------------------------------------------------------
|
|
|
|
+-----------+-------+-----------------+------------+-------------+-----------------+------+--------+------+-----+----+------+-----+---------+--------------------------------+
|
|
| Global Id | Track | Driver Type/Pin | Constraint | Clock Loads | Non-Clock Loads | FF | LUTRAM | RAMB | DSP | GT | MMCM | PLL | Hard IP | Net |
|
|
+-----------+-------+-----------------+------------+-------------+-----------------+------+--------+------+-----+----+------+-----+---------+--------------------------------+
|
|
| g0 | n/a | BUFG/O | None | 2763 | 0 | 2763 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | u_mlkem_axi_slave/mlkem_clk |
|
|
| g1 | n/a | BUFG/O | None | 737 | 0 | 737 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | pll_clk.u_clk_pll/inst/sys_clk |
|
|
| g4 | n/a | BUFG/O | None | 0 | 3295 | 3295 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | pll_clk.u_rst_sys/p_0_in_BUFG |
|
|
+-----------+-------+-----------------+------------+-------------+-----------------+------+--------+------+-----+----+------+-----+---------+--------------------------------+
|
|
* Clock Loads column represents the clock pin loads (pin count)
|
|
** Non-Clock Loads column represents the non-clock pin loads (pin count)
|
|
*** Columns FF, LUTRAM, RAMB through 'Hard IP' represents load cell counts
|
|
|
|
|
|
16. Clock Region Cell Placement per Global Clock: Region X1Y2
|
|
-------------------------------------------------------------
|
|
|
|
+-----------+-------+-----------------+------------+-------------+-----------------+------+--------+------+-----+----+------+-----+---------+--------------------------------+
|
|
| Global Id | Track | Driver Type/Pin | Constraint | Clock Loads | Non-Clock Loads | FF | LUTRAM | RAMB | DSP | GT | MMCM | PLL | Hard IP | Net |
|
|
+-----------+-------+-----------------+------------+-------------+-----------------+------+--------+------+-----+----+------+-----+---------+--------------------------------+
|
|
| g0 | n/a | BUFG/O | None | 4352 | 0 | 4348 | 0 | 3 | 0 | 0 | 0 | 0 | 0 | u_mlkem_axi_slave/mlkem_clk |
|
|
| g1 | n/a | BUFG/O | None | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | pll_clk.u_clk_pll/inst/sys_clk |
|
|
| g4 | n/a | BUFG/O | None | 0 | 4349 | 4349 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | pll_clk.u_rst_sys/p_0_in_BUFG |
|
|
+-----------+-------+-----------------+------------+-------------+-----------------+------+--------+------+-----+----+------+-----+---------+--------------------------------+
|
|
* Clock Loads column represents the clock pin loads (pin count)
|
|
** Non-Clock Loads column represents the non-clock pin loads (pin count)
|
|
*** Columns FF, LUTRAM, RAMB through 'Hard IP' represents load cell counts
|
|
|
|
|
|
17. Clock Region Cell Placement per Global Clock: Region X0Y3
|
|
-------------------------------------------------------------
|
|
|
|
+-----------+-------+-----------------+------------+-------------+-----------------+------+--------+------+-----+----+------+-----+---------+---------------------------------------------+
|
|
| Global Id | Track | Driver Type/Pin | Constraint | Clock Loads | Non-Clock Loads | FF | LUTRAM | RAMB | DSP | GT | MMCM | PLL | Hard IP | Net |
|
|
+-----------+-------+-----------------+------------+-------------+-----------------+------+--------+------+-----+----+------+-----+---------+---------------------------------------------+
|
|
| g0 | n/a | BUFG/O | None | 5614 | 0 | 5614 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | u_mlkem_axi_slave/mlkem_clk |
|
|
| g1 | n/a | BUFG/O | None | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | pll_clk.u_clk_pll/inst/sys_clk |
|
|
| g3 | n/a | BUFG/O | None | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | pll_clk.u_clk_pll/inst/clkfbout_buf_clk_pll |
|
|
| g4 | n/a | BUFG/O | None | 0 | 5614 | 5614 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | pll_clk.u_rst_sys/p_0_in_BUFG |
|
|
+-----------+-------+-----------------+------------+-------------+-----------------+------+--------+------+-----+----+------+-----+---------+---------------------------------------------+
|
|
* Clock Loads column represents the clock pin loads (pin count)
|
|
** Non-Clock Loads column represents the non-clock pin loads (pin count)
|
|
*** Columns FF, LUTRAM, RAMB through 'Hard IP' represents load cell counts
|
|
|
|
|
|
18. Clock Region Cell Placement per Global Clock: Region X1Y3
|
|
-------------------------------------------------------------
|
|
|
|
+-----------+-------+-----------------+------------+-------------+-----------------+------+--------+------+-----+----+------+-----+---------+-------------------------------+
|
|
| Global Id | Track | Driver Type/Pin | Constraint | Clock Loads | Non-Clock Loads | FF | LUTRAM | RAMB | DSP | GT | MMCM | PLL | Hard IP | Net |
|
|
+-----------+-------+-----------------+------------+-------------+-----------------+------+--------+------+-----+----+------+-----+---------+-------------------------------+
|
|
| g0 | n/a | BUFG/O | None | 2775 | 0 | 2775 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | u_mlkem_axi_slave/mlkem_clk |
|
|
| g4 | n/a | BUFG/O | None | 0 | 2775 | 2775 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | pll_clk.u_rst_sys/p_0_in_BUFG |
|
|
+-----------+-------+-----------------+------------+-------------+-----------------+------+--------+------+-----+----+------+-----+---------+-------------------------------+
|
|
* Clock Loads column represents the clock pin loads (pin count)
|
|
** Non-Clock Loads column represents the non-clock pin loads (pin count)
|
|
*** Columns FF, LUTRAM, RAMB through 'Hard IP' represents load cell counts
|
|
|
|
|
|
19. Clock Region Cell Placement per Global Clock: Region X0Y4
|
|
-------------------------------------------------------------
|
|
|
|
+-----------+-------+-----------------+------------+-------------+-----------------+-----+--------+------+-----+----+------+-----+---------+-------------------------------+
|
|
| Global Id | Track | Driver Type/Pin | Constraint | Clock Loads | Non-Clock Loads | FF | LUTRAM | RAMB | DSP | GT | MMCM | PLL | Hard IP | Net |
|
|
+-----------+-------+-----------------+------------+-------------+-----------------+-----+--------+------+-----+----+------+-----+---------+-------------------------------+
|
|
| g0 | n/a | BUFG/O | None | 671 | 0 | 671 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | u_mlkem_axi_slave/mlkem_clk |
|
|
| g4 | n/a | BUFG/O | None | 0 | 671 | 671 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | pll_clk.u_rst_sys/p_0_in_BUFG |
|
|
+-----------+-------+-----------------+------------+-------------+-----------------+-----+--------+------+-----+----+------+-----+---------+-------------------------------+
|
|
* Clock Loads column represents the clock pin loads (pin count)
|
|
** Non-Clock Loads column represents the non-clock pin loads (pin count)
|
|
*** Columns FF, LUTRAM, RAMB through 'Hard IP' represents load cell counts
|
|
|
|
|
|
20. Clock Region Cell Placement per Global Clock: Region X1Y4
|
|
-------------------------------------------------------------
|
|
|
|
+-----------+-------+-----------------+------------+-------------+-----------------+----+--------+------+-----+----+------+-----+---------+-------------------------------+
|
|
| Global Id | Track | Driver Type/Pin | Constraint | Clock Loads | Non-Clock Loads | FF | LUTRAM | RAMB | DSP | GT | MMCM | PLL | Hard IP | Net |
|
|
+-----------+-------+-----------------+------------+-------------+-----------------+----+--------+------+-----+----+------+-----+---------+-------------------------------+
|
|
| g0 | n/a | BUFG/O | None | 54 | 0 | 54 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | u_mlkem_axi_slave/mlkem_clk |
|
|
| g4 | n/a | BUFG/O | None | 0 | 54 | 54 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | pll_clk.u_rst_sys/p_0_in_BUFG |
|
|
+-----------+-------+-----------------+------------+-------------+-----------------+----+--------+------+-----+----+------+-----+---------+-------------------------------+
|
|
* Clock Loads column represents the clock pin loads (pin count)
|
|
** Non-Clock Loads column represents the non-clock pin loads (pin count)
|
|
*** Columns FF, LUTRAM, RAMB through 'Hard IP' represents load cell counts
|
|
|
|
|
|
|
|
# Location of BUFG Primitives
|
|
set_property LOC BUFGCTRL_X0Y1 [get_cells r_wb_reg[7]_i_3]
|
|
set_property LOC BUFGCTRL_X0Y0 [get_cells pll_clk.u_rst_sys/p_0_in_BUFG_inst]
|
|
set_property LOC BUFGCTRL_X0Y16 [get_cells pll_clk.u_clk_pll/inst/clkout2_buf]
|
|
set_property LOC BUFGCTRL_X0Y17 [get_cells pll_clk.u_clk_pll/inst/clkout1_buf]
|
|
set_property LOC BUFGCTRL_X0Y18 [get_cells pll_clk.u_clk_pll/inst/clkf_buf]
|
|
|
|
# Location of IO Primitives which is load of clock spine
|
|
set_property LOC IOB_X0Y173 [get_cells video_clk_OBUF_inst]
|
|
|
|
# Location of clock ports
|
|
set_property LOC IOB_X0Y176 [get_ports clk]
|
|
|
|
# Clock net "u_mlkem_axi_slave/mlkem_clk" driven by instance "r_wb_reg[7]_i_3" located at site "BUFGCTRL_X0Y1"
|
|
#startgroup
|
|
create_pblock {CLKAG_u_mlkem_axi_slave/mlkem_clk}
|
|
add_cells_to_pblock [get_pblocks {CLKAG_u_mlkem_axi_slave/mlkem_clk}] [get_cells -filter { PRIMITIVE_GROUP != I/O && IS_PRIMITIVE==1 && PRIMITIVE_LEVEL !=INTERNAL } -of_object [get_pins -filter {DIRECTION==IN} -of_objects [get_nets -hierarchical -filter {PARENT=="u_mlkem_axi_slave/mlkem_clk"}]]]
|
|
resize_pblock [get_pblocks {CLKAG_u_mlkem_axi_slave/mlkem_clk}] -add {CLOCKREGION_X0Y1:CLOCKREGION_X0Y1 CLOCKREGION_X0Y2:CLOCKREGION_X0Y2 CLOCKREGION_X0Y3:CLOCKREGION_X0Y3 CLOCKREGION_X0Y4:CLOCKREGION_X0Y4 CLOCKREGION_X1Y1:CLOCKREGION_X1Y1 CLOCKREGION_X1Y2:CLOCKREGION_X1Y2 CLOCKREGION_X1Y3:CLOCKREGION_X1Y3 CLOCKREGION_X1Y4:CLOCKREGION_X1Y4}
|
|
#endgroup
|
|
|
|
# Clock net "pll_clk.u_rst_sys/p_0_in_BUFG" driven by instance "pll_clk.u_rst_sys/p_0_in_BUFG_inst" located at site "BUFGCTRL_X0Y0"
|
|
#startgroup
|
|
create_pblock {CLKAG_pll_clk.u_rst_sys/p_0_in_BUFG}
|
|
add_cells_to_pblock [get_pblocks {CLKAG_pll_clk.u_rst_sys/p_0_in_BUFG}] [get_cells -filter { PRIMITIVE_GROUP != I/O && IS_PRIMITIVE==1 && PRIMITIVE_LEVEL !=INTERNAL } -of_object [get_pins -filter {DIRECTION==IN} -of_objects [get_nets -hierarchical -filter {PARENT=="pll_clk.u_rst_sys/p_0_in_BUFG"}]]]
|
|
resize_pblock [get_pblocks {CLKAG_pll_clk.u_rst_sys/p_0_in_BUFG}] -add {CLOCKREGION_X0Y0:CLOCKREGION_X0Y0 CLOCKREGION_X0Y1:CLOCKREGION_X0Y1 CLOCKREGION_X0Y2:CLOCKREGION_X0Y2 CLOCKREGION_X0Y3:CLOCKREGION_X0Y3 CLOCKREGION_X0Y4:CLOCKREGION_X0Y4 CLOCKREGION_X1Y0:CLOCKREGION_X1Y0 CLOCKREGION_X1Y1:CLOCKREGION_X1Y1 CLOCKREGION_X1Y2:CLOCKREGION_X1Y2 CLOCKREGION_X1Y3:CLOCKREGION_X1Y3 CLOCKREGION_X1Y4:CLOCKREGION_X1Y4}
|
|
#endgroup
|
|
|
|
# Clock net "pll_clk.u_clk_pll/inst/sys_clk" driven by instance "pll_clk.u_clk_pll/inst/clkout2_buf" located at site "BUFGCTRL_X0Y16"
|
|
#startgroup
|
|
create_pblock {CLKAG_pll_clk.u_clk_pll/inst/sys_clk}
|
|
add_cells_to_pblock [get_pblocks {CLKAG_pll_clk.u_clk_pll/inst/sys_clk}] [get_cells -filter { PRIMITIVE_GROUP != I/O && IS_PRIMITIVE==1 && PRIMITIVE_LEVEL !=INTERNAL && NAME!=video_clk_OBUF_inst} -of_object [get_pins -filter {DIRECTION==IN} -of_objects [get_nets -hierarchical -filter {PARENT=="pll_clk.u_clk_pll/inst/sys_clk"}]]]
|
|
resize_pblock [get_pblocks {CLKAG_pll_clk.u_clk_pll/inst/sys_clk}] -add {CLOCKREGION_X0Y0:CLOCKREGION_X0Y0 CLOCKREGION_X0Y1:CLOCKREGION_X0Y1 CLOCKREGION_X0Y2:CLOCKREGION_X0Y2 CLOCKREGION_X1Y0:CLOCKREGION_X1Y0 CLOCKREGION_X1Y1:CLOCKREGION_X1Y1 CLOCKREGION_X1Y2:CLOCKREGION_X1Y2}
|
|
#endgroup
|
|
|
|
# Clock net "pll_clk.u_clk_pll/inst/cpu_clk" driven by instance "pll_clk.u_clk_pll/inst/clkout1_buf" located at site "BUFGCTRL_X0Y17"
|
|
#startgroup
|
|
create_pblock {CLKAG_pll_clk.u_clk_pll/inst/cpu_clk}
|
|
add_cells_to_pblock [get_pblocks {CLKAG_pll_clk.u_clk_pll/inst/cpu_clk}] [get_cells -filter { PRIMITIVE_GROUP != I/O && IS_PRIMITIVE==1 && PRIMITIVE_LEVEL !=INTERNAL } -of_object [get_pins -filter {DIRECTION==IN} -of_objects [get_nets -hierarchical -filter {PARENT=="pll_clk.u_clk_pll/inst/cpu_clk"}]]]
|
|
resize_pblock [get_pblocks {CLKAG_pll_clk.u_clk_pll/inst/cpu_clk}] -add {CLOCKREGION_X0Y0:CLOCKREGION_X0Y0 CLOCKREGION_X0Y1:CLOCKREGION_X0Y1 CLOCKREGION_X1Y0:CLOCKREGION_X1Y0 CLOCKREGION_X1Y1:CLOCKREGION_X1Y1}
|
|
#endgroup
|