17095 lines
1.3 MiB
17095 lines
1.3 MiB
Copyright 1986-2019 Xilinx, Inc. All Rights Reserved.
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| Tool Version : Vivado v.2019.2 (lin64) Build 2708876 Wed Nov 6 21:39:14 MST 2019
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| Date : Wed Jul 8 03:34:13 2026
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| Host : fedora running 64-bit unknown
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| Command : report_timing -delay_type min -sort_by group -max_paths 100 -nworst 10 -path_type full -input_pins -file /home/fallensigh/vivado_reports_nodsp/timing_hold_paths.rpt
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| Design : soc_top
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| Device : 7a200t-fbg676
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| Speed File : -1 PRODUCTION 1.23 2018-06-13
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Timing Report
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Slack (MET) : 0.032ns (arrival time - required time)
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Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_30_35/RAMC/CLK
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(rising edge-triggered cell RAMD32 clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns})
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Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[34]/D
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(rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
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Path Group: sys_clk
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Path Type: Hold (Min at Fast Process Corner)
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Requirement: 0.000ns (sys_clk rise@0.000ns - mlkem_clk_clk_pll rise@0.000ns)
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Data Path Delay: 0.560ns (logic 0.390ns (69.595%) route 0.170ns (30.405%))
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Logic Levels: 0
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Clock Path Skew: 0.328ns (DCD - SCD - CPR)
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Destination Clock Delay (DCD): -0.352ns
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Source Clock Delay (SCD): -0.581ns
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Clock Pessimism Removal (CPR): -0.099ns
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Clock Uncertainty: 0.197ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
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Total System Jitter (TSJ): 0.071ns
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Discrete Jitter (DJ): 0.136ns
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Phase Error (PE): 0.120ns
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Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
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------------------------------------------------------------------- -------------------
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(clock mlkem_clk_clk_pll rise edge)
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0.000 0.000 r
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clock source latency -1.848 -1.848
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propagated clock network latency
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1.267 -0.581
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SLICE_X20Y76 RAMD32 0.000 -0.581 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_30_35/RAMC/CLK
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SLICE_X20Y76 RAMD32 (Prop_ramd32_CLK_O)
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0.390 -0.191 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_30_35/RAMC/O
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net (fo=1, routed) 0.170 -0.021 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port10__3[34]
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SLICE_X19Y76 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[34]/D
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------------------------------------------------------------------- -------------------
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(clock sys_clk rise edge) 0.000 0.000 r
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clock source latency -1.947 -1.947
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propagated clock network latency
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1.595 -0.352
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clock pessimism 0.099 -0.253
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clock uncertainty 0.197 -0.057
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SLICE_X19Y76 FDRE (Hold_fdre_C_D) 0.004 -0.053 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[34]
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-------------------------------------------------------------------
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required time 0.053
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arrival time -0.021
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-------------------------------------------------------------------
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slack 0.032
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Slack (MET) : 0.032ns (arrival time - required time)
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Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_30_35/RAMC/CLK
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(rising edge-triggered cell RAMD32 clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns})
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Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[34]/D
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(rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
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Path Group: sys_clk
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Path Type: Hold (Min at Fast Process Corner)
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Requirement: 0.000ns (sys_clk rise@0.000ns - mlkem_clk_clk_pll rise@0.000ns)
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Data Path Delay: 0.560ns (logic 0.390ns (69.595%) route 0.170ns (30.405%))
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Logic Levels: 0
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Clock Path Skew: 0.328ns (DCD - SCD - CPR)
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Destination Clock Delay (DCD): -0.352ns
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Source Clock Delay (SCD): -0.581ns
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Clock Pessimism Removal (CPR): -0.099ns
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Clock Uncertainty: 0.197ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
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Total System Jitter (TSJ): 0.071ns
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Discrete Jitter (DJ): 0.136ns
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Phase Error (PE): 0.120ns
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Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
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------------------------------------------------------------------- -------------------
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(clock mlkem_clk_clk_pll rise edge)
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0.000 0.000 r
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clock source latency -1.848 -1.848
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propagated clock network latency
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1.267 -0.581
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SLICE_X20Y76 RAMD32 0.000 -0.581 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_30_35/RAMC/CLK
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SLICE_X20Y76 RAMD32 (Prop_ramd32_CLK_O)
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0.390 -0.191 f u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_30_35/RAMC/O
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net (fo=1, routed) 0.170 -0.021 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port10__3[34]
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SLICE_X19Y76 FDRE f u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[34]/D
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------------------------------------------------------------------- -------------------
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(clock sys_clk rise edge) 0.000 0.000 r
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clock source latency -1.947 -1.947
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propagated clock network latency
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1.595 -0.352
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clock pessimism 0.099 -0.253
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clock uncertainty 0.197 -0.057
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SLICE_X19Y76 FDRE (Hold_fdre_C_D) 0.004 -0.053 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[34]
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-------------------------------------------------------------------
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required time 0.053
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arrival time -0.021
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-------------------------------------------------------------------
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slack 0.032
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Slack (MET) : 0.042ns (arrival time - required time)
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Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_36_39/RAMB/CLK
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(rising edge-triggered cell RAMD32 clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns})
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Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[38]/D
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(rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
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Path Group: sys_clk
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Path Type: Hold (Min at Fast Process Corner)
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Requirement: 0.000ns (sys_clk rise@0.000ns - mlkem_clk_clk_pll rise@0.000ns)
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Data Path Delay: 0.558ns (logic 0.394ns (70.575%) route 0.164ns (29.425%))
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Logic Levels: 0
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Clock Path Skew: 0.327ns (DCD - SCD - CPR)
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Destination Clock Delay (DCD): -0.349ns
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Source Clock Delay (SCD): -0.577ns
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Clock Pessimism Removal (CPR): -0.099ns
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Clock Uncertainty: 0.197ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
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Total System Jitter (TSJ): 0.071ns
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Discrete Jitter (DJ): 0.136ns
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Phase Error (PE): 0.120ns
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Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
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------------------------------------------------------------------- -------------------
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(clock mlkem_clk_clk_pll rise edge)
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0.000 0.000 r
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clock source latency -1.848 -1.848
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propagated clock network latency
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1.271 -0.577
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SLICE_X18Y78 RAMD32 0.000 -0.577 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_36_39/RAMB/CLK
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SLICE_X18Y78 RAMD32 (Prop_ramd32_CLK_O)
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0.394 -0.183 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_36_39/RAMB/O
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net (fo=1, routed) 0.164 -0.019 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port10__3[38]
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SLICE_X17Y78 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[38]/D
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------------------------------------------------------------------- -------------------
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(clock sys_clk rise edge) 0.000 0.000 r
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clock source latency -1.947 -1.947
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propagated clock network latency
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1.598 -0.349
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clock pessimism 0.099 -0.250
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clock uncertainty 0.197 -0.054
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SLICE_X17Y78 FDRE (Hold_fdre_C_D) -0.007 -0.061 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[38]
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-------------------------------------------------------------------
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required time 0.061
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arrival time -0.019
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-------------------------------------------------------------------
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slack 0.042
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Slack (MET) : 0.042ns (arrival time - required time)
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Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_36_39/RAMB/CLK
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(rising edge-triggered cell RAMD32 clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns})
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Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[38]/D
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(rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
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Path Group: sys_clk
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Path Type: Hold (Min at Fast Process Corner)
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Requirement: 0.000ns (sys_clk rise@0.000ns - mlkem_clk_clk_pll rise@0.000ns)
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Data Path Delay: 0.558ns (logic 0.394ns (70.575%) route 0.164ns (29.425%))
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Logic Levels: 0
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Clock Path Skew: 0.327ns (DCD - SCD - CPR)
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Destination Clock Delay (DCD): -0.349ns
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Source Clock Delay (SCD): -0.577ns
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Clock Pessimism Removal (CPR): -0.099ns
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Clock Uncertainty: 0.197ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
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Total System Jitter (TSJ): 0.071ns
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Discrete Jitter (DJ): 0.136ns
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Phase Error (PE): 0.120ns
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Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
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------------------------------------------------------------------- -------------------
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(clock mlkem_clk_clk_pll rise edge)
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0.000 0.000 r
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clock source latency -1.848 -1.848
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propagated clock network latency
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1.271 -0.577
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SLICE_X18Y78 RAMD32 0.000 -0.577 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_36_39/RAMB/CLK
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SLICE_X18Y78 RAMD32 (Prop_ramd32_CLK_O)
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0.394 -0.183 f u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_36_39/RAMB/O
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net (fo=1, routed) 0.164 -0.019 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port10__3[38]
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SLICE_X17Y78 FDRE f u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[38]/D
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------------------------------------------------------------------- -------------------
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(clock sys_clk rise edge) 0.000 0.000 r
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clock source latency -1.947 -1.947
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propagated clock network latency
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1.598 -0.349
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clock pessimism 0.099 -0.250
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clock uncertainty 0.197 -0.054
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SLICE_X17Y78 FDRE (Hold_fdre_C_D) -0.007 -0.061 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[38]
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-------------------------------------------------------------------
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required time 0.061
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arrival time -0.019
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-------------------------------------------------------------------
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slack 0.042
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Slack (MET) : 0.049ns (arrival time - required time)
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Source: u_cpu/u_csr/csr_tlbelo0_reg[14]/C
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(rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns})
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Destination: u_cpu/addr_trans/tlb_entry/tlb_ppn0_reg_r3_0_31_6_11/RAMA/I
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(rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns})
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Path Group: cpu_clk
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Path Type: Hold (Min at Fast Process Corner)
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Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns)
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Data Path Delay: 0.209ns (logic 0.141ns (67.454%) route 0.068ns (32.546%))
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Logic Levels: 0
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Clock Path Skew: 0.013ns (DCD - SCD - CPR)
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Destination Clock Delay (DCD): -0.310ns
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Source Clock Delay (SCD): -0.541ns
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Clock Pessimism Removal (CPR): 0.218ns
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Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
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------------------------------------------------------------------- -------------------
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(clock cpu_clk rise edge) 0.000 0.000 r
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clock source latency -1.848 -1.848
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propagated clock network latency
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1.308 -0.541
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SLICE_X47Y34 FDRE 0.000 -0.541 r u_cpu/u_csr/csr_tlbelo0_reg[14]/C
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SLICE_X47Y34 FDRE (Prop_fdre_C_Q) 0.141 -0.400 r u_cpu/u_csr/csr_tlbelo0_reg[14]/Q
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net (fo=4, routed) 0.068 -0.332 u_cpu/addr_trans/tlb_entry/tlb_ppn0_reg_r3_0_31_6_11/DIA0
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SLICE_X46Y34 RAMD32 r u_cpu/addr_trans/tlb_entry/tlb_ppn0_reg_r3_0_31_6_11/RAMA/I
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------------------------------------------------------------------- -------------------
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(clock cpu_clk rise edge) 0.000 0.000 r
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clock source latency -1.947 -1.947
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propagated clock network latency
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1.637 -0.310
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clock pessimism -0.218 -0.528
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SLICE_X46Y34 RAMD32 (Hold_ramd32_CLK_I)
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0.147 -0.381 u_cpu/addr_trans/tlb_entry/tlb_ppn0_reg_r3_0_31_6_11/RAMA
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-------------------------------------------------------------------
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required time 0.381
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arrival time -0.332
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-------------------------------------------------------------------
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slack 0.049
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Slack (MET) : 0.049ns (arrival time - required time)
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Source: u_cpu/u_csr/csr_tlbelo0_reg[14]/C
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(rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns})
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Destination: u_cpu/addr_trans/tlb_entry/tlb_ppn0_reg_r3_0_31_6_11/RAMA/I
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(rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns})
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Path Group: cpu_clk
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Path Type: Hold (Min at Fast Process Corner)
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Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns)
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Data Path Delay: 0.209ns (logic 0.141ns (67.454%) route 0.068ns (32.546%))
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Logic Levels: 0
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Clock Path Skew: 0.013ns (DCD - SCD - CPR)
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Destination Clock Delay (DCD): -0.310ns
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Source Clock Delay (SCD): -0.541ns
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Clock Pessimism Removal (CPR): 0.218ns
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Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
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------------------------------------------------------------------- -------------------
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(clock cpu_clk rise edge) 0.000 0.000 r
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clock source latency -1.848 -1.848
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propagated clock network latency
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1.308 -0.541
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SLICE_X47Y34 FDRE 0.000 -0.541 r u_cpu/u_csr/csr_tlbelo0_reg[14]/C
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SLICE_X47Y34 FDRE (Prop_fdre_C_Q) 0.141 -0.400 f u_cpu/u_csr/csr_tlbelo0_reg[14]/Q
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net (fo=4, routed) 0.068 -0.332 u_cpu/addr_trans/tlb_entry/tlb_ppn0_reg_r3_0_31_6_11/DIA0
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SLICE_X46Y34 RAMD32 f u_cpu/addr_trans/tlb_entry/tlb_ppn0_reg_r3_0_31_6_11/RAMA/I
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------------------------------------------------------------------- -------------------
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(clock cpu_clk rise edge) 0.000 0.000 r
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clock source latency -1.947 -1.947
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propagated clock network latency
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1.637 -0.310
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clock pessimism -0.218 -0.528
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SLICE_X46Y34 RAMD32 (Hold_ramd32_CLK_I)
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0.147 -0.381 u_cpu/addr_trans/tlb_entry/tlb_ppn0_reg_r3_0_31_6_11/RAMA
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-------------------------------------------------------------------
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required time 0.381
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arrival time -0.332
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-------------------------------------------------------------------
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slack 0.049
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Slack (MET) : 0.052ns (arrival time - required time)
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Source: u_cpu/u_csr/csr_tlbelo0_reg[3]/C
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(rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns})
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Destination: u_cpu/addr_trans/tlb_entry/tlb_plv0_reg_r3_0_31_1_1/SP/I
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(rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns})
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Path Group: cpu_clk
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Path Type: Hold (Min at Fast Process Corner)
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Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns)
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Data Path Delay: 0.209ns (logic 0.141ns (67.433%) route 0.068ns (32.567%))
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Logic Levels: 0
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Clock Path Skew: 0.013ns (DCD - SCD - CPR)
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Destination Clock Delay (DCD): -0.308ns
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Source Clock Delay (SCD): -0.540ns
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Clock Pessimism Removal (CPR): 0.219ns
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Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
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------------------------------------------------------------------- -------------------
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(clock cpu_clk rise edge) 0.000 0.000 r
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clock source latency -1.848 -1.848
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propagated clock network latency
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1.309 -0.540
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SLICE_X43Y35 FDRE 0.000 -0.540 r u_cpu/u_csr/csr_tlbelo0_reg[3]/C
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SLICE_X43Y35 FDRE (Prop_fdre_C_Q) 0.141 -0.399 r u_cpu/u_csr/csr_tlbelo0_reg[3]/Q
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net (fo=7, routed) 0.068 -0.331 u_cpu/addr_trans/tlb_entry/tlb_plv0_reg_r3_0_31_1_1/D
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SLICE_X42Y35 RAMD32 r u_cpu/addr_trans/tlb_entry/tlb_plv0_reg_r3_0_31_1_1/SP/I
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------------------------------------------------------------------- -------------------
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(clock cpu_clk rise edge) 0.000 0.000 r
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clock source latency -1.947 -1.947
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propagated clock network latency
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1.639 -0.308
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clock pessimism -0.219 -0.527
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SLICE_X42Y35 RAMD32 (Hold_ramd32_CLK_I)
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0.144 -0.383 u_cpu/addr_trans/tlb_entry/tlb_plv0_reg_r3_0_31_1_1/SP
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-------------------------------------------------------------------
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required time 0.383
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arrival time -0.331
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-------------------------------------------------------------------
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slack 0.052
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|
|
Slack (MET) : 0.052ns (arrival time - required time)
|
|
Source: u_cpu/u_csr/csr_tlbelo0_reg[3]/C
|
|
(rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns})
|
|
Destination: u_cpu/addr_trans/tlb_entry/tlb_plv0_reg_r3_0_31_1_1/SP/I
|
|
(rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns})
|
|
Path Group: cpu_clk
|
|
Path Type: Hold (Min at Fast Process Corner)
|
|
Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns)
|
|
Data Path Delay: 0.209ns (logic 0.141ns (67.433%) route 0.068ns (32.567%))
|
|
Logic Levels: 0
|
|
Clock Path Skew: 0.013ns (DCD - SCD - CPR)
|
|
Destination Clock Delay (DCD): -0.308ns
|
|
Source Clock Delay (SCD): -0.540ns
|
|
Clock Pessimism Removal (CPR): 0.219ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock cpu_clk rise edge) 0.000 0.000 r
|
|
clock source latency -1.848 -1.848
|
|
propagated clock network latency
|
|
1.309 -0.540
|
|
SLICE_X43Y35 FDRE 0.000 -0.540 r u_cpu/u_csr/csr_tlbelo0_reg[3]/C
|
|
SLICE_X43Y35 FDRE (Prop_fdre_C_Q) 0.141 -0.399 f u_cpu/u_csr/csr_tlbelo0_reg[3]/Q
|
|
net (fo=7, routed) 0.068 -0.331 u_cpu/addr_trans/tlb_entry/tlb_plv0_reg_r3_0_31_1_1/D
|
|
SLICE_X42Y35 RAMD32 f u_cpu/addr_trans/tlb_entry/tlb_plv0_reg_r3_0_31_1_1/SP/I
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock cpu_clk rise edge) 0.000 0.000 r
|
|
clock source latency -1.947 -1.947
|
|
propagated clock network latency
|
|
1.639 -0.308
|
|
clock pessimism -0.219 -0.527
|
|
SLICE_X42Y35 RAMD32 (Hold_ramd32_CLK_I)
|
|
0.144 -0.383 u_cpu/addr_trans/tlb_entry/tlb_plv0_reg_r3_0_31_1_1/SP
|
|
-------------------------------------------------------------------
|
|
required time 0.383
|
|
arrival time -0.331
|
|
-------------------------------------------------------------------
|
|
slack 0.052
|
|
|
|
Slack (MET) : 0.054ns (arrival time - required time)
|
|
Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_12_17/RAMB/CLK
|
|
(rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/_zz_ram_port1_reg[14]/D
|
|
(rising edge-triggered cell FDRE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns})
|
|
Path Group: mlkem_clk_clk_pll
|
|
Path Type: Hold (Min at Fast Process Corner)
|
|
Requirement: 0.000ns (mlkem_clk_clk_pll rise@0.000ns - sys_clk rise@0.000ns)
|
|
Data Path Delay: 0.567ns (logic 0.394ns (69.509%) route 0.173ns (30.491%))
|
|
Logic Levels: 0
|
|
Clock Path Skew: 0.323ns (DCD - SCD - CPR)
|
|
Destination Clock Delay (DCD): -0.355ns
|
|
Source Clock Delay (SCD): -0.579ns
|
|
Clock Pessimism Removal (CPR): -0.099ns
|
|
Clock Uncertainty: 0.197ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Discrete Jitter (DJ): 0.136ns
|
|
Phase Error (PE): 0.120ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock sys_clk rise edge) 0.000 0.000 r
|
|
clock source latency -1.848 -1.848
|
|
propagated clock network latency
|
|
1.269 -0.579
|
|
SLICE_X20Y72 RAMD32 0.000 -0.579 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_12_17/RAMB/CLK
|
|
SLICE_X20Y72 RAMD32 (Prop_ramd32_CLK_O)
|
|
0.394 -0.185 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_12_17/RAMB/O
|
|
net (fo=1, routed) 0.173 -0.013 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/_zz_ram_port10__2[14]
|
|
SLICE_X23Y73 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/_zz_ram_port1_reg[14]/D
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock mlkem_clk_clk_pll rise edge)
|
|
0.000 0.000 r
|
|
clock source latency -1.947 -1.947
|
|
propagated clock network latency
|
|
1.592 -0.355
|
|
clock pessimism 0.099 -0.256
|
|
clock uncertainty 0.197 -0.060
|
|
SLICE_X23Y73 FDRE (Hold_fdre_C_D) -0.007 -0.067 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/_zz_ram_port1_reg[14]
|
|
-------------------------------------------------------------------
|
|
required time 0.067
|
|
arrival time -0.013
|
|
-------------------------------------------------------------------
|
|
slack 0.054
|
|
|
|
Slack (MET) : 0.054ns (arrival time - required time)
|
|
Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_12_17/RAMB/CLK
|
|
(rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/_zz_ram_port1_reg[14]/D
|
|
(rising edge-triggered cell FDRE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns})
|
|
Path Group: mlkem_clk_clk_pll
|
|
Path Type: Hold (Min at Fast Process Corner)
|
|
Requirement: 0.000ns (mlkem_clk_clk_pll rise@0.000ns - sys_clk rise@0.000ns)
|
|
Data Path Delay: 0.567ns (logic 0.394ns (69.509%) route 0.173ns (30.491%))
|
|
Logic Levels: 0
|
|
Clock Path Skew: 0.323ns (DCD - SCD - CPR)
|
|
Destination Clock Delay (DCD): -0.355ns
|
|
Source Clock Delay (SCD): -0.579ns
|
|
Clock Pessimism Removal (CPR): -0.099ns
|
|
Clock Uncertainty: 0.197ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Discrete Jitter (DJ): 0.136ns
|
|
Phase Error (PE): 0.120ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock sys_clk rise edge) 0.000 0.000 r
|
|
clock source latency -1.848 -1.848
|
|
propagated clock network latency
|
|
1.269 -0.579
|
|
SLICE_X20Y72 RAMD32 0.000 -0.579 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_12_17/RAMB/CLK
|
|
SLICE_X20Y72 RAMD32 (Prop_ramd32_CLK_O)
|
|
0.394 -0.185 f u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_12_17/RAMB/O
|
|
net (fo=1, routed) 0.173 -0.013 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/_zz_ram_port10__2[14]
|
|
SLICE_X23Y73 FDRE f u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/_zz_ram_port1_reg[14]/D
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock mlkem_clk_clk_pll rise edge)
|
|
0.000 0.000 r
|
|
clock source latency -1.947 -1.947
|
|
propagated clock network latency
|
|
1.592 -0.355
|
|
clock pessimism 0.099 -0.256
|
|
clock uncertainty 0.197 -0.060
|
|
SLICE_X23Y73 FDRE (Hold_fdre_C_D) -0.007 -0.067 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/_zz_ram_port1_reg[14]
|
|
-------------------------------------------------------------------
|
|
required time 0.067
|
|
arrival time -0.013
|
|
-------------------------------------------------------------------
|
|
slack 0.054
|
|
|
|
Slack (MET) : 0.057ns (arrival time - required time)
|
|
Source: u_cpu/axi_bridge/awaddr_reg[10]/C
|
|
(rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns})
|
|
Destination: u_Axi_CDC/awFifo/ram_reg_0_3_6_11/RAMC/I
|
|
(rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns})
|
|
Path Group: cpu_clk
|
|
Path Type: Hold (Min at Fast Process Corner)
|
|
Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns)
|
|
Data Path Delay: 0.395ns (logic 0.141ns (35.653%) route 0.254ns (64.347%))
|
|
Logic Levels: 0
|
|
Clock Path Skew: 0.194ns (DCD - SCD - CPR)
|
|
Destination Clock Delay (DCD): -0.338ns
|
|
Source Clock Delay (SCD): -0.496ns
|
|
Clock Pessimism Removal (CPR): -0.037ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock cpu_clk rise edge) 0.000 0.000 r
|
|
clock source latency -1.848 -1.848
|
|
propagated clock network latency
|
|
1.353 -0.496
|
|
SLICE_X17Y49 FDRE 0.000 -0.496 r u_cpu/axi_bridge/awaddr_reg[10]/C
|
|
SLICE_X17Y49 FDRE (Prop_fdre_C_Q) 0.141 -0.355 r u_cpu/axi_bridge/awaddr_reg[10]/Q
|
|
net (fo=1, routed) 0.254 -0.100 u_Axi_CDC/awFifo/ram_reg_0_3_6_11/DIC0
|
|
SLICE_X16Y57 RAMD32 r u_Axi_CDC/awFifo/ram_reg_0_3_6_11/RAMC/I
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock cpu_clk rise edge) 0.000 0.000 r
|
|
clock source latency -1.947 -1.947
|
|
propagated clock network latency
|
|
1.609 -0.338
|
|
clock pessimism 0.037 -0.301
|
|
SLICE_X16Y57 RAMD32 (Hold_ramd32_CLK_I)
|
|
0.144 -0.157 u_Axi_CDC/awFifo/ram_reg_0_3_6_11/RAMC
|
|
-------------------------------------------------------------------
|
|
required time 0.157
|
|
arrival time -0.100
|
|
-------------------------------------------------------------------
|
|
slack 0.057
|
|
|
|
Slack (MET) : 0.057ns (arrival time - required time)
|
|
Source: u_cpu/axi_bridge/awaddr_reg[10]/C
|
|
(rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns})
|
|
Destination: u_Axi_CDC/awFifo/ram_reg_0_3_6_11/RAMC/I
|
|
(rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns})
|
|
Path Group: cpu_clk
|
|
Path Type: Hold (Min at Fast Process Corner)
|
|
Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns)
|
|
Data Path Delay: 0.395ns (logic 0.141ns (35.653%) route 0.254ns (64.347%))
|
|
Logic Levels: 0
|
|
Clock Path Skew: 0.194ns (DCD - SCD - CPR)
|
|
Destination Clock Delay (DCD): -0.338ns
|
|
Source Clock Delay (SCD): -0.496ns
|
|
Clock Pessimism Removal (CPR): -0.037ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock cpu_clk rise edge) 0.000 0.000 r
|
|
clock source latency -1.848 -1.848
|
|
propagated clock network latency
|
|
1.353 -0.496
|
|
SLICE_X17Y49 FDRE 0.000 -0.496 r u_cpu/axi_bridge/awaddr_reg[10]/C
|
|
SLICE_X17Y49 FDRE (Prop_fdre_C_Q) 0.141 -0.355 f u_cpu/axi_bridge/awaddr_reg[10]/Q
|
|
net (fo=1, routed) 0.254 -0.100 u_Axi_CDC/awFifo/ram_reg_0_3_6_11/DIC0
|
|
SLICE_X16Y57 RAMD32 f u_Axi_CDC/awFifo/ram_reg_0_3_6_11/RAMC/I
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock cpu_clk rise edge) 0.000 0.000 r
|
|
clock source latency -1.947 -1.947
|
|
propagated clock network latency
|
|
1.609 -0.338
|
|
clock pessimism 0.037 -0.301
|
|
SLICE_X16Y57 RAMD32 (Hold_ramd32_CLK_I)
|
|
0.144 -0.157 u_Axi_CDC/awFifo/ram_reg_0_3_6_11/RAMC
|
|
-------------------------------------------------------------------
|
|
required time 0.157
|
|
arrival time -0.100
|
|
-------------------------------------------------------------------
|
|
slack 0.057
|
|
|
|
Slack (MET) : 0.058ns (arrival time - required time)
|
|
Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/valid_sr_reg[5]_u_fft_mlkem_axi_slave_u_mlkem_axi_slave_u_mlkem_u_ntt_u_scl_valid_sr_reg_c_3/C
|
|
(rising edge-triggered cell FDRE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns})
|
|
Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/valid_sr_reg[6]/D
|
|
(rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns})
|
|
Path Group: mlkem_clk_clk_pll
|
|
Path Type: Hold (Min at Fast Process Corner)
|
|
Requirement: 0.000ns (mlkem_clk_clk_pll rise@0.000ns - mlkem_clk_clk_pll rise@0.000ns)
|
|
Data Path Delay: 0.444ns (logic 0.247ns (55.601%) route 0.197ns (44.399%))
|
|
Logic Levels: 1 (LUT2=1)
|
|
Clock Path Skew: 0.265ns (DCD - SCD - CPR)
|
|
Destination Clock Delay (DCD): -0.475ns
|
|
Source Clock Delay (SCD): -0.695ns
|
|
Clock Pessimism Removal (CPR): -0.045ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock mlkem_clk_clk_pll rise edge)
|
|
0.000 0.000 r
|
|
clock source latency -1.848 -1.848
|
|
propagated clock network latency
|
|
1.153 -0.695
|
|
SLICE_X84Y144 FDRE 0.000 -0.695 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/valid_sr_reg[5]_u_fft_mlkem_axi_slave_u_mlkem_axi_slave_u_mlkem_u_ntt_u_scl_valid_sr_reg_c_3/C
|
|
SLICE_X84Y144 FDRE (Prop_fdre_C_Q) 0.148 -0.547 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/valid_sr_reg[5]_u_fft_mlkem_axi_slave_u_mlkem_axi_slave_u_mlkem_u_ntt_u_scl_valid_sr_reg_c_3/Q
|
|
net (fo=1, routed) 0.197 -0.350 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/valid_sr_reg[5]_u_fft_mlkem_axi_slave_u_mlkem_axi_slave_u_mlkem_u_ntt_u_scl_valid_sr_reg_c_3_n_0
|
|
SLICE_X84Y151 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/valid_sr_reg_gate/I0
|
|
SLICE_X84Y151 LUT2 (Prop_lut2_I0_O) 0.099 -0.251 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/valid_sr_reg_gate/O
|
|
net (fo=1, routed) 0.000 -0.251 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/valid_sr_reg_gate_n_0
|
|
SLICE_X84Y151 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/valid_sr_reg[6]/D
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock mlkem_clk_clk_pll rise edge)
|
|
0.000 0.000 r
|
|
clock source latency -1.947 -1.947
|
|
propagated clock network latency
|
|
1.472 -0.475
|
|
clock pessimism 0.045 -0.430
|
|
SLICE_X84Y151 FDCE (Hold_fdce_C_D) 0.121 -0.309 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/valid_sr_reg[6]
|
|
-------------------------------------------------------------------
|
|
required time 0.309
|
|
arrival time -0.251
|
|
-------------------------------------------------------------------
|
|
slack 0.058
|
|
|
|
Slack (MET) : 0.058ns (arrival time - required time)
|
|
Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/valid_sr_reg[5]_u_fft_mlkem_axi_slave_u_mlkem_axi_slave_u_mlkem_u_ntt_u_scl_valid_sr_reg_c_3/C
|
|
(rising edge-triggered cell FDRE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns})
|
|
Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/valid_sr_reg[6]/D
|
|
(rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns})
|
|
Path Group: mlkem_clk_clk_pll
|
|
Path Type: Hold (Min at Fast Process Corner)
|
|
Requirement: 0.000ns (mlkem_clk_clk_pll rise@0.000ns - mlkem_clk_clk_pll rise@0.000ns)
|
|
Data Path Delay: 0.444ns (logic 0.247ns (55.601%) route 0.197ns (44.399%))
|
|
Logic Levels: 1 (LUT2=1)
|
|
Clock Path Skew: 0.265ns (DCD - SCD - CPR)
|
|
Destination Clock Delay (DCD): -0.475ns
|
|
Source Clock Delay (SCD): -0.695ns
|
|
Clock Pessimism Removal (CPR): -0.045ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock mlkem_clk_clk_pll rise edge)
|
|
0.000 0.000 r
|
|
clock source latency -1.848 -1.848
|
|
propagated clock network latency
|
|
1.153 -0.695
|
|
SLICE_X84Y144 FDRE 0.000 -0.695 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/valid_sr_reg[5]_u_fft_mlkem_axi_slave_u_mlkem_axi_slave_u_mlkem_u_ntt_u_scl_valid_sr_reg_c_3/C
|
|
SLICE_X84Y144 FDRE (Prop_fdre_C_Q) 0.148 -0.547 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/valid_sr_reg[5]_u_fft_mlkem_axi_slave_u_mlkem_axi_slave_u_mlkem_u_ntt_u_scl_valid_sr_reg_c_3/Q
|
|
net (fo=1, routed) 0.197 -0.350 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/valid_sr_reg[5]_u_fft_mlkem_axi_slave_u_mlkem_axi_slave_u_mlkem_u_ntt_u_scl_valid_sr_reg_c_3_n_0
|
|
SLICE_X84Y151 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/valid_sr_reg_gate/I0
|
|
SLICE_X84Y151 LUT2 (Prop_lut2_I0_O) 0.099 -0.251 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/valid_sr_reg_gate/O
|
|
net (fo=1, routed) 0.000 -0.251 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/valid_sr_reg_gate_n_0
|
|
SLICE_X84Y151 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/valid_sr_reg[6]/D
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock mlkem_clk_clk_pll rise edge)
|
|
0.000 0.000 r
|
|
clock source latency -1.947 -1.947
|
|
propagated clock network latency
|
|
1.472 -0.475
|
|
clock pessimism 0.045 -0.430
|
|
SLICE_X84Y151 FDCE (Hold_fdce_C_D) 0.121 -0.309 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/valid_sr_reg[6]
|
|
-------------------------------------------------------------------
|
|
required time 0.309
|
|
arrival time -0.251
|
|
-------------------------------------------------------------------
|
|
slack 0.058
|
|
|
|
Slack (MET) : 0.058ns (arrival time - required time)
|
|
Source: u_cpu/axi_bridge/awaddr_reg[0]/C
|
|
(rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns})
|
|
Destination: u_Axi_CDC/awFifo/ram_reg_0_3_0_5/RAMA/I
|
|
(rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns})
|
|
Path Group: cpu_clk
|
|
Path Type: Hold (Min at Fast Process Corner)
|
|
Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns)
|
|
Data Path Delay: 0.400ns (logic 0.141ns (35.262%) route 0.259ns (64.738%))
|
|
Logic Levels: 0
|
|
Clock Path Skew: 0.194ns (DCD - SCD - CPR)
|
|
Destination Clock Delay (DCD): -0.339ns
|
|
Source Clock Delay (SCD): -0.497ns
|
|
Clock Pessimism Removal (CPR): -0.037ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock cpu_clk rise edge) 0.000 0.000 r
|
|
clock source latency -1.848 -1.848
|
|
propagated clock network latency
|
|
1.352 -0.497
|
|
SLICE_X23Y49 FDRE 0.000 -0.497 r u_cpu/axi_bridge/awaddr_reg[0]/C
|
|
SLICE_X23Y49 FDRE (Prop_fdre_C_Q) 0.141 -0.356 r u_cpu/axi_bridge/awaddr_reg[0]/Q
|
|
net (fo=1, routed) 0.259 -0.097 u_Axi_CDC/awFifo/ram_reg_0_3_0_5/DIA0
|
|
SLICE_X20Y58 RAMD32 r u_Axi_CDC/awFifo/ram_reg_0_3_0_5/RAMA/I
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock cpu_clk rise edge) 0.000 0.000 r
|
|
clock source latency -1.947 -1.947
|
|
propagated clock network latency
|
|
1.608 -0.339
|
|
clock pessimism 0.037 -0.302
|
|
SLICE_X20Y58 RAMD32 (Hold_ramd32_CLK_I)
|
|
0.147 -0.155 u_Axi_CDC/awFifo/ram_reg_0_3_0_5/RAMA
|
|
-------------------------------------------------------------------
|
|
required time 0.155
|
|
arrival time -0.097
|
|
-------------------------------------------------------------------
|
|
slack 0.058
|
|
|
|
Slack (MET) : 0.058ns (arrival time - required time)
|
|
Source: u_cpu/axi_bridge/awaddr_reg[0]/C
|
|
(rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns})
|
|
Destination: u_Axi_CDC/awFifo/ram_reg_0_3_0_5/RAMA/I
|
|
(rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns})
|
|
Path Group: cpu_clk
|
|
Path Type: Hold (Min at Fast Process Corner)
|
|
Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns)
|
|
Data Path Delay: 0.400ns (logic 0.141ns (35.262%) route 0.259ns (64.738%))
|
|
Logic Levels: 0
|
|
Clock Path Skew: 0.194ns (DCD - SCD - CPR)
|
|
Destination Clock Delay (DCD): -0.339ns
|
|
Source Clock Delay (SCD): -0.497ns
|
|
Clock Pessimism Removal (CPR): -0.037ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock cpu_clk rise edge) 0.000 0.000 r
|
|
clock source latency -1.848 -1.848
|
|
propagated clock network latency
|
|
1.352 -0.497
|
|
SLICE_X23Y49 FDRE 0.000 -0.497 r u_cpu/axi_bridge/awaddr_reg[0]/C
|
|
SLICE_X23Y49 FDRE (Prop_fdre_C_Q) 0.141 -0.356 f u_cpu/axi_bridge/awaddr_reg[0]/Q
|
|
net (fo=1, routed) 0.259 -0.097 u_Axi_CDC/awFifo/ram_reg_0_3_0_5/DIA0
|
|
SLICE_X20Y58 RAMD32 f u_Axi_CDC/awFifo/ram_reg_0_3_0_5/RAMA/I
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock cpu_clk rise edge) 0.000 0.000 r
|
|
clock source latency -1.947 -1.947
|
|
propagated clock network latency
|
|
1.608 -0.339
|
|
clock pessimism 0.037 -0.302
|
|
SLICE_X20Y58 RAMD32 (Hold_ramd32_CLK_I)
|
|
0.147 -0.155 u_Axi_CDC/awFifo/ram_reg_0_3_0_5/RAMA
|
|
-------------------------------------------------------------------
|
|
required time 0.155
|
|
arrival time -0.097
|
|
-------------------------------------------------------------------
|
|
slack 0.058
|
|
|
|
Slack (MET) : 0.061ns (arrival time - required time)
|
|
Source: u_cpu/u_csr/csr_tlbelo1_reg[20]/C
|
|
(rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns})
|
|
Destination: u_cpu/addr_trans/tlb_entry/tlb_ppn1_reg_r3_0_31_12_17/RAMA/I
|
|
(rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns})
|
|
Path Group: cpu_clk
|
|
Path Type: Hold (Min at Fast Process Corner)
|
|
Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns)
|
|
Data Path Delay: 0.221ns (logic 0.141ns (63.716%) route 0.080ns (36.284%))
|
|
Logic Levels: 0
|
|
Clock Path Skew: 0.013ns (DCD - SCD - CPR)
|
|
Destination Clock Delay (DCD): -0.273ns
|
|
Source Clock Delay (SCD): -0.507ns
|
|
Clock Pessimism Removal (CPR): 0.221ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock cpu_clk rise edge) 0.000 0.000 r
|
|
clock source latency -1.848 -1.848
|
|
propagated clock network latency
|
|
1.342 -0.507
|
|
SLICE_X37Y38 FDRE 0.000 -0.507 r u_cpu/u_csr/csr_tlbelo1_reg[20]/C
|
|
SLICE_X37Y38 FDRE (Prop_fdre_C_Q) 0.141 -0.366 r u_cpu/u_csr/csr_tlbelo1_reg[20]/Q
|
|
net (fo=4, routed) 0.080 -0.285 u_cpu/addr_trans/tlb_entry/tlb_ppn1_reg_r3_0_31_12_17/DIA0
|
|
SLICE_X36Y38 RAMD32 r u_cpu/addr_trans/tlb_entry/tlb_ppn1_reg_r3_0_31_12_17/RAMA/I
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock cpu_clk rise edge) 0.000 0.000 r
|
|
clock source latency -1.947 -1.947
|
|
propagated clock network latency
|
|
1.674 -0.273
|
|
clock pessimism -0.221 -0.494
|
|
SLICE_X36Y38 RAMD32 (Hold_ramd32_CLK_I)
|
|
0.147 -0.347 u_cpu/addr_trans/tlb_entry/tlb_ppn1_reg_r3_0_31_12_17/RAMA
|
|
-------------------------------------------------------------------
|
|
required time 0.347
|
|
arrival time -0.285
|
|
-------------------------------------------------------------------
|
|
slack 0.061
|
|
|
|
Slack (MET) : 0.061ns (arrival time - required time)
|
|
Source: u_cpu/u_csr/csr_tlbelo1_reg[20]/C
|
|
(rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns})
|
|
Destination: u_cpu/addr_trans/tlb_entry/tlb_ppn1_reg_r3_0_31_12_17/RAMA/I
|
|
(rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns})
|
|
Path Group: cpu_clk
|
|
Path Type: Hold (Min at Fast Process Corner)
|
|
Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns)
|
|
Data Path Delay: 0.221ns (logic 0.141ns (63.716%) route 0.080ns (36.284%))
|
|
Logic Levels: 0
|
|
Clock Path Skew: 0.013ns (DCD - SCD - CPR)
|
|
Destination Clock Delay (DCD): -0.273ns
|
|
Source Clock Delay (SCD): -0.507ns
|
|
Clock Pessimism Removal (CPR): 0.221ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock cpu_clk rise edge) 0.000 0.000 r
|
|
clock source latency -1.848 -1.848
|
|
propagated clock network latency
|
|
1.342 -0.507
|
|
SLICE_X37Y38 FDRE 0.000 -0.507 r u_cpu/u_csr/csr_tlbelo1_reg[20]/C
|
|
SLICE_X37Y38 FDRE (Prop_fdre_C_Q) 0.141 -0.366 f u_cpu/u_csr/csr_tlbelo1_reg[20]/Q
|
|
net (fo=4, routed) 0.080 -0.285 u_cpu/addr_trans/tlb_entry/tlb_ppn1_reg_r3_0_31_12_17/DIA0
|
|
SLICE_X36Y38 RAMD32 f u_cpu/addr_trans/tlb_entry/tlb_ppn1_reg_r3_0_31_12_17/RAMA/I
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock cpu_clk rise edge) 0.000 0.000 r
|
|
clock source latency -1.947 -1.947
|
|
propagated clock network latency
|
|
1.674 -0.273
|
|
clock pessimism -0.221 -0.494
|
|
SLICE_X36Y38 RAMD32 (Hold_ramd32_CLK_I)
|
|
0.147 -0.347 u_cpu/addr_trans/tlb_entry/tlb_ppn1_reg_r3_0_31_12_17/RAMA
|
|
-------------------------------------------------------------------
|
|
required time 0.347
|
|
arrival time -0.285
|
|
-------------------------------------------------------------------
|
|
slack 0.061
|
|
|
|
Slack (MET) : 0.066ns (arrival time - required time)
|
|
Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_18_23/RAMC_D1/CLK
|
|
(rising edge-triggered cell RAMD32 clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns})
|
|
Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[23]/D
|
|
(rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Path Group: sys_clk
|
|
Path Type: Hold (Min at Fast Process Corner)
|
|
Requirement: 0.000ns (sys_clk rise@0.000ns - mlkem_clk_clk_pll rise@0.000ns)
|
|
Data Path Delay: 0.647ns (logic 0.386ns (59.641%) route 0.261ns (40.359%))
|
|
Logic Levels: 0
|
|
Clock Path Skew: 0.333ns (DCD - SCD - CPR)
|
|
Destination Clock Delay (DCD): -0.393ns
|
|
Source Clock Delay (SCD): -0.627ns
|
|
Clock Pessimism Removal (CPR): -0.099ns
|
|
Clock Uncertainty: 0.197ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Discrete Jitter (DJ): 0.136ns
|
|
Phase Error (PE): 0.120ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock mlkem_clk_clk_pll rise edge)
|
|
0.000 0.000 r
|
|
clock source latency -1.848 -1.848
|
|
propagated clock network latency
|
|
1.221 -0.627
|
|
SLICE_X64Y75 RAMD32 0.000 -0.627 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_18_23/RAMC_D1/CLK
|
|
SLICE_X64Y75 RAMD32 (Prop_ramd32_CLK_O)
|
|
0.386 -0.241 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_18_23/RAMC_D1/O
|
|
net (fo=1, routed) 0.261 0.020 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port10__3[23]
|
|
SLICE_X62Y81 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[23]/D
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock sys_clk rise edge) 0.000 0.000 r
|
|
clock source latency -1.947 -1.947
|
|
propagated clock network latency
|
|
1.554 -0.393
|
|
clock pessimism 0.099 -0.294
|
|
clock uncertainty 0.197 -0.098
|
|
SLICE_X62Y81 FDRE (Hold_fdre_C_D) 0.052 -0.046 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[23]
|
|
-------------------------------------------------------------------
|
|
required time 0.046
|
|
arrival time 0.020
|
|
-------------------------------------------------------------------
|
|
slack 0.066
|
|
|
|
Slack (MET) : 0.066ns (arrival time - required time)
|
|
Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_18_23/RAMC_D1/CLK
|
|
(rising edge-triggered cell RAMD32 clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns})
|
|
Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[23]/D
|
|
(rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Path Group: sys_clk
|
|
Path Type: Hold (Min at Fast Process Corner)
|
|
Requirement: 0.000ns (sys_clk rise@0.000ns - mlkem_clk_clk_pll rise@0.000ns)
|
|
Data Path Delay: 0.647ns (logic 0.386ns (59.641%) route 0.261ns (40.359%))
|
|
Logic Levels: 0
|
|
Clock Path Skew: 0.333ns (DCD - SCD - CPR)
|
|
Destination Clock Delay (DCD): -0.393ns
|
|
Source Clock Delay (SCD): -0.627ns
|
|
Clock Pessimism Removal (CPR): -0.099ns
|
|
Clock Uncertainty: 0.197ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Discrete Jitter (DJ): 0.136ns
|
|
Phase Error (PE): 0.120ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock mlkem_clk_clk_pll rise edge)
|
|
0.000 0.000 r
|
|
clock source latency -1.848 -1.848
|
|
propagated clock network latency
|
|
1.221 -0.627
|
|
SLICE_X64Y75 RAMD32 0.000 -0.627 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_18_23/RAMC_D1/CLK
|
|
SLICE_X64Y75 RAMD32 (Prop_ramd32_CLK_O)
|
|
0.386 -0.241 f u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_18_23/RAMC_D1/O
|
|
net (fo=1, routed) 0.261 0.020 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port10__3[23]
|
|
SLICE_X62Y81 FDRE f u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[23]/D
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock sys_clk rise edge) 0.000 0.000 r
|
|
clock source latency -1.947 -1.947
|
|
propagated clock network latency
|
|
1.554 -0.393
|
|
clock pessimism 0.099 -0.294
|
|
clock uncertainty 0.197 -0.098
|
|
SLICE_X62Y81 FDRE (Hold_fdre_C_D) 0.052 -0.046 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[23]
|
|
-------------------------------------------------------------------
|
|
required time 0.046
|
|
arrival time 0.020
|
|
-------------------------------------------------------------------
|
|
slack 0.066
|
|
|
|
Slack (MET) : 0.077ns (arrival time - required time)
|
|
Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/wb_b_data_r_reg[2]/C
|
|
(rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns})
|
|
Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/cr_reg[241][2]/D
|
|
(rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns})
|
|
Path Group: mlkem_clk_clk_pll
|
|
Path Type: Hold (Min at Fast Process Corner)
|
|
Requirement: 0.000ns (mlkem_clk_clk_pll rise@0.000ns - mlkem_clk_clk_pll rise@0.000ns)
|
|
Data Path Delay: 0.446ns (logic 0.186ns (41.734%) route 0.260ns (58.266%))
|
|
Logic Levels: 1 (LUT6=1)
|
|
Clock Path Skew: 0.277ns (DCD - SCD - CPR)
|
|
Destination Clock Delay (DCD): -0.469ns
|
|
Source Clock Delay (SCD): -0.701ns
|
|
Clock Pessimism Removal (CPR): -0.045ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock mlkem_clk_clk_pll rise edge)
|
|
0.000 0.000 r
|
|
clock source latency -1.848 -1.848
|
|
propagated clock network latency
|
|
1.148 -0.701
|
|
SLICE_X86Y154 FDCE 0.000 -0.701 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/wb_b_data_r_reg[2]/C
|
|
SLICE_X86Y154 FDCE (Prop_fdce_C_Q) 0.141 -0.560 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/wb_b_data_r_reg[2]/Q
|
|
net (fo=234, routed) 0.260 -0.300 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/wb_b_data_r[2]
|
|
SLICE_X86Y148 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/cr[241][2]_i_1/I0
|
|
SLICE_X86Y148 LUT6 (Prop_lut6_I0_O) 0.045 -0.255 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/cr[241][2]_i_1/O
|
|
net (fo=1, routed) 0.000 -0.255 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/cr[241][2]_i_1_n_0
|
|
SLICE_X86Y148 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/cr_reg[241][2]/D
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock mlkem_clk_clk_pll rise edge)
|
|
0.000 0.000 r
|
|
clock source latency -1.947 -1.947
|
|
propagated clock network latency
|
|
1.478 -0.469
|
|
clock pessimism 0.045 -0.424
|
|
SLICE_X86Y148 FDCE (Hold_fdce_C_D) 0.092 -0.332 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/cr_reg[241][2]
|
|
-------------------------------------------------------------------
|
|
required time 0.332
|
|
arrival time -0.255
|
|
-------------------------------------------------------------------
|
|
slack 0.077
|
|
|
|
Slack (MET) : 0.077ns (arrival time - required time)
|
|
Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/wb_b_data_r_reg[2]/C
|
|
(rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns})
|
|
Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/cr_reg[241][2]/D
|
|
(rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns})
|
|
Path Group: mlkem_clk_clk_pll
|
|
Path Type: Hold (Min at Fast Process Corner)
|
|
Requirement: 0.000ns (mlkem_clk_clk_pll rise@0.000ns - mlkem_clk_clk_pll rise@0.000ns)
|
|
Data Path Delay: 0.446ns (logic 0.186ns (41.734%) route 0.260ns (58.266%))
|
|
Logic Levels: 1 (LUT6=1)
|
|
Clock Path Skew: 0.277ns (DCD - SCD - CPR)
|
|
Destination Clock Delay (DCD): -0.469ns
|
|
Source Clock Delay (SCD): -0.701ns
|
|
Clock Pessimism Removal (CPR): -0.045ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock mlkem_clk_clk_pll rise edge)
|
|
0.000 0.000 r
|
|
clock source latency -1.848 -1.848
|
|
propagated clock network latency
|
|
1.148 -0.701
|
|
SLICE_X86Y154 FDCE 0.000 -0.701 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/wb_b_data_r_reg[2]/C
|
|
SLICE_X86Y154 FDCE (Prop_fdce_C_Q) 0.141 -0.560 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/wb_b_data_r_reg[2]/Q
|
|
net (fo=234, routed) 0.260 -0.300 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/wb_b_data_r[2]
|
|
SLICE_X86Y148 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/cr[241][2]_i_1/I0
|
|
SLICE_X86Y148 LUT6 (Prop_lut6_I0_O) 0.045 -0.255 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/cr[241][2]_i_1/O
|
|
net (fo=1, routed) 0.000 -0.255 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/cr[241][2]_i_1_n_0
|
|
SLICE_X86Y148 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/cr_reg[241][2]/D
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock mlkem_clk_clk_pll rise edge)
|
|
0.000 0.000 r
|
|
clock source latency -1.947 -1.947
|
|
propagated clock network latency
|
|
1.478 -0.469
|
|
clock pessimism 0.045 -0.424
|
|
SLICE_X86Y148 FDCE (Hold_fdce_C_D) 0.092 -0.332 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/cr_reg[241][2]
|
|
-------------------------------------------------------------------
|
|
required time 0.332
|
|
arrival time -0.255
|
|
-------------------------------------------------------------------
|
|
slack 0.077
|
|
|
|
Slack (MET) : 0.079ns (arrival time - required time)
|
|
Source: u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/DB1/buf_re_reg[127][2]_srl32/CLK
|
|
(rising edge-triggered cell SRLC32E clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Destination: u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/DB1/buf_re_reg[159][2]_srl32/D
|
|
(rising edge-triggered cell SRLC32E clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Path Group: sys_clk
|
|
Path Type: Hold (Min at Fast Process Corner)
|
|
Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns)
|
|
Data Path Delay: 0.544ns (logic 0.378ns (69.538%) route 0.166ns (30.462%))
|
|
Logic Levels: 0
|
|
Clock Path Skew: 0.343ns (DCD - SCD - CPR)
|
|
Destination Clock Delay (DCD): -0.260ns
|
|
Source Clock Delay (SCD): -0.566ns
|
|
Clock Pessimism Removal (CPR): -0.037ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock sys_clk rise edge) 0.000 0.000 r
|
|
clock source latency -1.848 -1.848
|
|
propagated clock network latency
|
|
1.282 -0.566
|
|
SLICE_X18Y50 SRLC32E 0.000 -0.566 r u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/DB1/buf_re_reg[127][2]_srl32/CLK
|
|
SLICE_X18Y50 SRLC32E (Prop_srlc32e_CLK_Q31)
|
|
0.378 -0.188 r u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/DB1/buf_re_reg[127][2]_srl32/Q31
|
|
net (fo=1, routed) 0.166 -0.023 u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/DB1/xlnx_opt__56
|
|
SLICE_X14Y49 SRLC32E r u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/DB1/buf_re_reg[159][2]_srl32/D
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock sys_clk rise edge) 0.000 0.000 r
|
|
clock source latency -1.947 -1.947
|
|
propagated clock network latency
|
|
1.687 -0.260
|
|
clock pessimism 0.037 -0.223
|
|
SLICE_X14Y49 SRLC32E (Hold_srlc32e_CLK_D)
|
|
0.122 -0.101 u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/DB1/buf_re_reg[159][2]_srl32
|
|
-------------------------------------------------------------------
|
|
required time 0.101
|
|
arrival time -0.023
|
|
-------------------------------------------------------------------
|
|
slack 0.079
|
|
|
|
Slack (MET) : 0.079ns (arrival time - required time)
|
|
Source: u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/DB1/buf_re_reg[127][2]_srl32/CLK
|
|
(rising edge-triggered cell SRLC32E clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Destination: u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/DB1/buf_re_reg[159][2]_srl32/D
|
|
(rising edge-triggered cell SRLC32E clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Path Group: sys_clk
|
|
Path Type: Hold (Min at Fast Process Corner)
|
|
Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns)
|
|
Data Path Delay: 0.544ns (logic 0.378ns (69.538%) route 0.166ns (30.462%))
|
|
Logic Levels: 0
|
|
Clock Path Skew: 0.343ns (DCD - SCD - CPR)
|
|
Destination Clock Delay (DCD): -0.260ns
|
|
Source Clock Delay (SCD): -0.566ns
|
|
Clock Pessimism Removal (CPR): -0.037ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock sys_clk rise edge) 0.000 0.000 r
|
|
clock source latency -1.848 -1.848
|
|
propagated clock network latency
|
|
1.282 -0.566
|
|
SLICE_X18Y50 SRLC32E 0.000 -0.566 r u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/DB1/buf_re_reg[127][2]_srl32/CLK
|
|
SLICE_X18Y50 SRLC32E (Prop_srlc32e_CLK_Q31)
|
|
0.378 -0.188 f u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/DB1/buf_re_reg[127][2]_srl32/Q31
|
|
net (fo=1, routed) 0.166 -0.023 u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/DB1/xlnx_opt__56
|
|
SLICE_X14Y49 SRLC32E f u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/DB1/buf_re_reg[159][2]_srl32/D
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock sys_clk rise edge) 0.000 0.000 r
|
|
clock source latency -1.947 -1.947
|
|
propagated clock network latency
|
|
1.687 -0.260
|
|
clock pessimism 0.037 -0.223
|
|
SLICE_X14Y49 SRLC32E (Hold_srlc32e_CLK_D)
|
|
0.122 -0.101 u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/DB1/buf_re_reg[159][2]_srl32
|
|
-------------------------------------------------------------------
|
|
required time 0.101
|
|
arrival time -0.023
|
|
-------------------------------------------------------------------
|
|
slack 0.079
|
|
|
|
Slack (MET) : 0.079ns (arrival time - required time)
|
|
Source: u_axi_uart_controller/uart0/regs/receiver/rf_data_in_reg[5]/C
|
|
(rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Destination: u_axi_uart_controller/uart0/regs/receiver/fifo_rx/rfifo/ram_reg_0_15_0_5/RAMB/I
|
|
(rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Path Group: sys_clk
|
|
Path Type: Hold (Min at Fast Process Corner)
|
|
Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns)
|
|
Data Path Delay: 0.242ns (logic 0.141ns (58.248%) route 0.101ns (41.752%))
|
|
Logic Levels: 0
|
|
Clock Path Skew: 0.017ns (DCD - SCD - CPR)
|
|
Destination Clock Delay (DCD): -0.308ns
|
|
Source Clock Delay (SCD): -0.541ns
|
|
Clock Pessimism Removal (CPR): 0.216ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock sys_clk rise edge) 0.000 0.000 r
|
|
clock source latency -1.848 -1.848
|
|
propagated clock network latency
|
|
1.307 -0.541
|
|
SLICE_X4Y57 FDRE 0.000 -0.541 r u_axi_uart_controller/uart0/regs/receiver/rf_data_in_reg[5]/C
|
|
SLICE_X4Y57 FDRE (Prop_fdre_C_Q) 0.141 -0.400 r u_axi_uart_controller/uart0/regs/receiver/rf_data_in_reg[5]/Q
|
|
net (fo=1, routed) 0.101 -0.299 u_axi_uart_controller/uart0/regs/receiver/fifo_rx/rfifo/ram_reg_0_15_0_5/DIB0
|
|
SLICE_X6Y56 RAMD32 r u_axi_uart_controller/uart0/regs/receiver/fifo_rx/rfifo/ram_reg_0_15_0_5/RAMB/I
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock sys_clk rise edge) 0.000 0.000 r
|
|
clock source latency -1.947 -1.947
|
|
propagated clock network latency
|
|
1.639 -0.308
|
|
clock pessimism -0.216 -0.524
|
|
SLICE_X6Y56 RAMD32 (Hold_ramd32_CLK_I)
|
|
0.146 -0.378 u_axi_uart_controller/uart0/regs/receiver/fifo_rx/rfifo/ram_reg_0_15_0_5/RAMB
|
|
-------------------------------------------------------------------
|
|
required time 0.378
|
|
arrival time -0.299
|
|
-------------------------------------------------------------------
|
|
slack 0.079
|
|
|
|
Slack (MET) : 0.079ns (arrival time - required time)
|
|
Source: u_axi_uart_controller/uart0/regs/receiver/rf_data_in_reg[5]/C
|
|
(rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Destination: u_axi_uart_controller/uart0/regs/receiver/fifo_rx/rfifo/ram_reg_0_15_0_5/RAMB/I
|
|
(rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Path Group: sys_clk
|
|
Path Type: Hold (Min at Fast Process Corner)
|
|
Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns)
|
|
Data Path Delay: 0.242ns (logic 0.141ns (58.248%) route 0.101ns (41.752%))
|
|
Logic Levels: 0
|
|
Clock Path Skew: 0.017ns (DCD - SCD - CPR)
|
|
Destination Clock Delay (DCD): -0.308ns
|
|
Source Clock Delay (SCD): -0.541ns
|
|
Clock Pessimism Removal (CPR): 0.216ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock sys_clk rise edge) 0.000 0.000 r
|
|
clock source latency -1.848 -1.848
|
|
propagated clock network latency
|
|
1.307 -0.541
|
|
SLICE_X4Y57 FDRE 0.000 -0.541 r u_axi_uart_controller/uart0/regs/receiver/rf_data_in_reg[5]/C
|
|
SLICE_X4Y57 FDRE (Prop_fdre_C_Q) 0.141 -0.400 f u_axi_uart_controller/uart0/regs/receiver/rf_data_in_reg[5]/Q
|
|
net (fo=1, routed) 0.101 -0.299 u_axi_uart_controller/uart0/regs/receiver/fifo_rx/rfifo/ram_reg_0_15_0_5/DIB0
|
|
SLICE_X6Y56 RAMD32 f u_axi_uart_controller/uart0/regs/receiver/fifo_rx/rfifo/ram_reg_0_15_0_5/RAMB/I
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock sys_clk rise edge) 0.000 0.000 r
|
|
clock source latency -1.947 -1.947
|
|
propagated clock network latency
|
|
1.639 -0.308
|
|
clock pessimism -0.216 -0.524
|
|
SLICE_X6Y56 RAMD32 (Hold_ramd32_CLK_I)
|
|
0.146 -0.378 u_axi_uart_controller/uart0/regs/receiver/fifo_rx/rfifo/ram_reg_0_15_0_5/RAMB
|
|
-------------------------------------------------------------------
|
|
required time 0.378
|
|
arrival time -0.299
|
|
-------------------------------------------------------------------
|
|
slack 0.079
|
|
|
|
Slack (MET) : 0.079ns (arrival time - required time)
|
|
Source: u_cpu/u_csr/csr_tlbelo0_reg[3]/C
|
|
(rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns})
|
|
Destination: u_cpu/addr_trans/tlb_entry/tlb_plv0_reg_r3_0_31_1_1/DP/I
|
|
(rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns})
|
|
Path Group: cpu_clk
|
|
Path Type: Hold (Min at Fast Process Corner)
|
|
Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns)
|
|
Data Path Delay: 0.209ns (logic 0.141ns (67.433%) route 0.068ns (32.567%))
|
|
Logic Levels: 0
|
|
Clock Path Skew: 0.013ns (DCD - SCD - CPR)
|
|
Destination Clock Delay (DCD): -0.308ns
|
|
Source Clock Delay (SCD): -0.540ns
|
|
Clock Pessimism Removal (CPR): 0.219ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock cpu_clk rise edge) 0.000 0.000 r
|
|
clock source latency -1.848 -1.848
|
|
propagated clock network latency
|
|
1.309 -0.540
|
|
SLICE_X43Y35 FDRE 0.000 -0.540 r u_cpu/u_csr/csr_tlbelo0_reg[3]/C
|
|
SLICE_X43Y35 FDRE (Prop_fdre_C_Q) 0.141 -0.399 r u_cpu/u_csr/csr_tlbelo0_reg[3]/Q
|
|
net (fo=7, routed) 0.068 -0.331 u_cpu/addr_trans/tlb_entry/tlb_plv0_reg_r3_0_31_1_1/D
|
|
SLICE_X42Y35 RAMD32 r u_cpu/addr_trans/tlb_entry/tlb_plv0_reg_r3_0_31_1_1/DP/I
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock cpu_clk rise edge) 0.000 0.000 r
|
|
clock source latency -1.947 -1.947
|
|
propagated clock network latency
|
|
1.639 -0.308
|
|
clock pessimism -0.219 -0.527
|
|
SLICE_X42Y35 RAMD32 (Hold_ramd32_CLK_I)
|
|
0.117 -0.410 u_cpu/addr_trans/tlb_entry/tlb_plv0_reg_r3_0_31_1_1/DP
|
|
-------------------------------------------------------------------
|
|
required time 0.410
|
|
arrival time -0.331
|
|
-------------------------------------------------------------------
|
|
slack 0.079
|
|
|
|
Slack (MET) : 0.079ns (arrival time - required time)
|
|
Source: u_cpu/u_csr/csr_tlbelo0_reg[3]/C
|
|
(rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns})
|
|
Destination: u_cpu/addr_trans/tlb_entry/tlb_plv0_reg_r3_0_31_1_1/DP/I
|
|
(rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns})
|
|
Path Group: cpu_clk
|
|
Path Type: Hold (Min at Fast Process Corner)
|
|
Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns)
|
|
Data Path Delay: 0.209ns (logic 0.141ns (67.433%) route 0.068ns (32.567%))
|
|
Logic Levels: 0
|
|
Clock Path Skew: 0.013ns (DCD - SCD - CPR)
|
|
Destination Clock Delay (DCD): -0.308ns
|
|
Source Clock Delay (SCD): -0.540ns
|
|
Clock Pessimism Removal (CPR): 0.219ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock cpu_clk rise edge) 0.000 0.000 r
|
|
clock source latency -1.848 -1.848
|
|
propagated clock network latency
|
|
1.309 -0.540
|
|
SLICE_X43Y35 FDRE 0.000 -0.540 r u_cpu/u_csr/csr_tlbelo0_reg[3]/C
|
|
SLICE_X43Y35 FDRE (Prop_fdre_C_Q) 0.141 -0.399 f u_cpu/u_csr/csr_tlbelo0_reg[3]/Q
|
|
net (fo=7, routed) 0.068 -0.331 u_cpu/addr_trans/tlb_entry/tlb_plv0_reg_r3_0_31_1_1/D
|
|
SLICE_X42Y35 RAMD32 f u_cpu/addr_trans/tlb_entry/tlb_plv0_reg_r3_0_31_1_1/DP/I
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock cpu_clk rise edge) 0.000 0.000 r
|
|
clock source latency -1.947 -1.947
|
|
propagated clock network latency
|
|
1.639 -0.308
|
|
clock pessimism -0.219 -0.527
|
|
SLICE_X42Y35 RAMD32 (Hold_ramd32_CLK_I)
|
|
0.117 -0.410 u_cpu/addr_trans/tlb_entry/tlb_plv0_reg_r3_0_31_1_1/DP
|
|
-------------------------------------------------------------------
|
|
required time 0.410
|
|
arrival time -0.331
|
|
-------------------------------------------------------------------
|
|
slack 0.079
|
|
|
|
Slack (MET) : 0.080ns (arrival time - required time)
|
|
Source: u_axi_uart_controller/uart0/regs/receiver/rf_data_in_reg[3]/C
|
|
(rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Destination: u_axi_uart_controller/uart0/regs/receiver/fifo_rx/rfifo/ram_reg_0_15_0_5/RAMA/I
|
|
(rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Path Group: sys_clk
|
|
Path Type: Hold (Min at Fast Process Corner)
|
|
Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns)
|
|
Data Path Delay: 0.244ns (logic 0.141ns (57.830%) route 0.103ns (42.170%))
|
|
Logic Levels: 0
|
|
Clock Path Skew: 0.017ns (DCD - SCD - CPR)
|
|
Destination Clock Delay (DCD): -0.308ns
|
|
Source Clock Delay (SCD): -0.541ns
|
|
Clock Pessimism Removal (CPR): 0.216ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock sys_clk rise edge) 0.000 0.000 r
|
|
clock source latency -1.848 -1.848
|
|
propagated clock network latency
|
|
1.307 -0.541
|
|
SLICE_X4Y57 FDRE 0.000 -0.541 r u_axi_uart_controller/uart0/regs/receiver/rf_data_in_reg[3]/C
|
|
SLICE_X4Y57 FDRE (Prop_fdre_C_Q) 0.141 -0.400 r u_axi_uart_controller/uart0/regs/receiver/rf_data_in_reg[3]/Q
|
|
net (fo=1, routed) 0.103 -0.298 u_axi_uart_controller/uart0/regs/receiver/fifo_rx/rfifo/ram_reg_0_15_0_5/DIA0
|
|
SLICE_X6Y56 RAMD32 r u_axi_uart_controller/uart0/regs/receiver/fifo_rx/rfifo/ram_reg_0_15_0_5/RAMA/I
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock sys_clk rise edge) 0.000 0.000 r
|
|
clock source latency -1.947 -1.947
|
|
propagated clock network latency
|
|
1.639 -0.308
|
|
clock pessimism -0.216 -0.524
|
|
SLICE_X6Y56 RAMD32 (Hold_ramd32_CLK_I)
|
|
0.147 -0.377 u_axi_uart_controller/uart0/regs/receiver/fifo_rx/rfifo/ram_reg_0_15_0_5/RAMA
|
|
-------------------------------------------------------------------
|
|
required time 0.377
|
|
arrival time -0.298
|
|
-------------------------------------------------------------------
|
|
slack 0.080
|
|
|
|
Slack (MET) : 0.080ns (arrival time - required time)
|
|
Source: u_axi_uart_controller/uart0/regs/receiver/rf_data_in_reg[3]/C
|
|
(rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Destination: u_axi_uart_controller/uart0/regs/receiver/fifo_rx/rfifo/ram_reg_0_15_0_5/RAMA/I
|
|
(rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Path Group: sys_clk
|
|
Path Type: Hold (Min at Fast Process Corner)
|
|
Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns)
|
|
Data Path Delay: 0.244ns (logic 0.141ns (57.830%) route 0.103ns (42.170%))
|
|
Logic Levels: 0
|
|
Clock Path Skew: 0.017ns (DCD - SCD - CPR)
|
|
Destination Clock Delay (DCD): -0.308ns
|
|
Source Clock Delay (SCD): -0.541ns
|
|
Clock Pessimism Removal (CPR): 0.216ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock sys_clk rise edge) 0.000 0.000 r
|
|
clock source latency -1.848 -1.848
|
|
propagated clock network latency
|
|
1.307 -0.541
|
|
SLICE_X4Y57 FDRE 0.000 -0.541 r u_axi_uart_controller/uart0/regs/receiver/rf_data_in_reg[3]/C
|
|
SLICE_X4Y57 FDRE (Prop_fdre_C_Q) 0.141 -0.400 f u_axi_uart_controller/uart0/regs/receiver/rf_data_in_reg[3]/Q
|
|
net (fo=1, routed) 0.103 -0.298 u_axi_uart_controller/uart0/regs/receiver/fifo_rx/rfifo/ram_reg_0_15_0_5/DIA0
|
|
SLICE_X6Y56 RAMD32 f u_axi_uart_controller/uart0/regs/receiver/fifo_rx/rfifo/ram_reg_0_15_0_5/RAMA/I
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock sys_clk rise edge) 0.000 0.000 r
|
|
clock source latency -1.947 -1.947
|
|
propagated clock network latency
|
|
1.639 -0.308
|
|
clock pessimism -0.216 -0.524
|
|
SLICE_X6Y56 RAMD32 (Hold_ramd32_CLK_I)
|
|
0.147 -0.377 u_axi_uart_controller/uart0/regs/receiver/fifo_rx/rfifo/ram_reg_0_15_0_5/RAMA
|
|
-------------------------------------------------------------------
|
|
required time 0.377
|
|
arrival time -0.298
|
|
-------------------------------------------------------------------
|
|
slack 0.080
|
|
|
|
Slack (MET) : 0.083ns (arrival time - required time)
|
|
Source: u_matmul_axi_slave/mult_inst[1].u_mult/prod_reg[49]/C
|
|
(rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Destination: u_matmul_axi_slave/mult_inst[1].u_mult/p_reg[49]/D
|
|
(rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Path Group: sys_clk
|
|
Path Type: Hold (Min at Fast Process Corner)
|
|
Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns)
|
|
Data Path Delay: 0.488ns (logic 0.164ns (33.640%) route 0.324ns (66.360%))
|
|
Logic Levels: 0
|
|
Clock Path Skew: 0.335ns (DCD - SCD - CPR)
|
|
Destination Clock Delay (DCD): -0.338ns
|
|
Source Clock Delay (SCD): -0.633ns
|
|
Clock Pessimism Removal (CPR): -0.040ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock sys_clk rise edge) 0.000 0.000 r
|
|
clock source latency -1.848 -1.848
|
|
propagated clock network latency
|
|
1.215 -0.633
|
|
SLICE_X14Y102 FDRE 0.000 -0.633 r u_matmul_axi_slave/mult_inst[1].u_mult/prod_reg[49]/C
|
|
SLICE_X14Y102 FDRE (Prop_fdre_C_Q) 0.164 -0.469 r u_matmul_axi_slave/mult_inst[1].u_mult/prod_reg[49]/Q
|
|
net (fo=1, routed) 0.324 -0.145 u_matmul_axi_slave/mult_inst[1].u_mult/prod[49]
|
|
SLICE_X17Y92 FDRE r u_matmul_axi_slave/mult_inst[1].u_mult/p_reg[49]/D
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock sys_clk rise edge) 0.000 0.000 r
|
|
clock source latency -1.947 -1.947
|
|
propagated clock network latency
|
|
1.609 -0.338
|
|
clock pessimism 0.040 -0.298
|
|
SLICE_X17Y92 FDRE (Hold_fdre_C_D) 0.070 -0.228 u_matmul_axi_slave/mult_inst[1].u_mult/p_reg[49]
|
|
-------------------------------------------------------------------
|
|
required time 0.228
|
|
arrival time -0.145
|
|
-------------------------------------------------------------------
|
|
slack 0.083
|
|
|
|
Slack (MET) : 0.083ns (arrival time - required time)
|
|
Source: u_matmul_axi_slave/mult_inst[1].u_mult/prod_reg[49]/C
|
|
(rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Destination: u_matmul_axi_slave/mult_inst[1].u_mult/p_reg[49]/D
|
|
(rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Path Group: sys_clk
|
|
Path Type: Hold (Min at Fast Process Corner)
|
|
Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns)
|
|
Data Path Delay: 0.488ns (logic 0.164ns (33.640%) route 0.324ns (66.360%))
|
|
Logic Levels: 0
|
|
Clock Path Skew: 0.335ns (DCD - SCD - CPR)
|
|
Destination Clock Delay (DCD): -0.338ns
|
|
Source Clock Delay (SCD): -0.633ns
|
|
Clock Pessimism Removal (CPR): -0.040ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock sys_clk rise edge) 0.000 0.000 r
|
|
clock source latency -1.848 -1.848
|
|
propagated clock network latency
|
|
1.215 -0.633
|
|
SLICE_X14Y102 FDRE 0.000 -0.633 r u_matmul_axi_slave/mult_inst[1].u_mult/prod_reg[49]/C
|
|
SLICE_X14Y102 FDRE (Prop_fdre_C_Q) 0.164 -0.469 f u_matmul_axi_slave/mult_inst[1].u_mult/prod_reg[49]/Q
|
|
net (fo=1, routed) 0.324 -0.145 u_matmul_axi_slave/mult_inst[1].u_mult/prod[49]
|
|
SLICE_X17Y92 FDRE f u_matmul_axi_slave/mult_inst[1].u_mult/p_reg[49]/D
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock sys_clk rise edge) 0.000 0.000 r
|
|
clock source latency -1.947 -1.947
|
|
propagated clock network latency
|
|
1.609 -0.338
|
|
clock pessimism 0.040 -0.298
|
|
SLICE_X17Y92 FDRE (Hold_fdre_C_D) 0.070 -0.228 u_matmul_axi_slave/mult_inst[1].u_mult/p_reg[49]
|
|
-------------------------------------------------------------------
|
|
required time 0.228
|
|
arrival time -0.145
|
|
-------------------------------------------------------------------
|
|
slack 0.083
|
|
|
|
Slack (MET) : 0.083ns (arrival time - required time)
|
|
Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/wb_valid_r_reg_rep__5/C
|
|
(rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns})
|
|
Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/cr_reg[130][5]/D
|
|
(rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns})
|
|
Path Group: mlkem_clk_clk_pll
|
|
Path Type: Hold (Min at Fast Process Corner)
|
|
Requirement: 0.000ns (mlkem_clk_clk_pll rise@0.000ns - mlkem_clk_clk_pll rise@0.000ns)
|
|
Data Path Delay: 0.453ns (logic 0.186ns (41.036%) route 0.267ns (58.964%))
|
|
Logic Levels: 1 (LUT6=1)
|
|
Clock Path Skew: 0.278ns (DCD - SCD - CPR)
|
|
Destination Clock Delay (DCD): -0.439ns
|
|
Source Clock Delay (SCD): -0.672ns
|
|
Clock Pessimism Removal (CPR): -0.045ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock mlkem_clk_clk_pll rise edge)
|
|
0.000 0.000 r
|
|
clock source latency -1.848 -1.848
|
|
propagated clock network latency
|
|
1.177 -0.672
|
|
SLICE_X138Y154 FDCE 0.000 -0.672 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/wb_valid_r_reg_rep__5/C
|
|
SLICE_X138Y154 FDCE (Prop_fdce_C_Q) 0.141 -0.531 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/wb_valid_r_reg_rep__5/Q
|
|
net (fo=127, routed) 0.267 -0.264 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/wb_valid_r_reg_rep__5_n_0
|
|
SLICE_X137Y147 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/cr[130][5]_i_1/I3
|
|
SLICE_X137Y147 LUT6 (Prop_lut6_I3_O) 0.045 -0.219 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/cr[130][5]_i_1/O
|
|
net (fo=1, routed) 0.000 -0.219 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/cr[130][5]_i_1_n_0
|
|
SLICE_X137Y147 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/cr_reg[130][5]/D
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock mlkem_clk_clk_pll rise edge)
|
|
0.000 0.000 r
|
|
clock source latency -1.947 -1.947
|
|
propagated clock network latency
|
|
1.508 -0.439
|
|
clock pessimism 0.045 -0.394
|
|
SLICE_X137Y147 FDCE (Hold_fdce_C_D) 0.092 -0.302 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/cr_reg[130][5]
|
|
-------------------------------------------------------------------
|
|
required time 0.302
|
|
arrival time -0.219
|
|
-------------------------------------------------------------------
|
|
slack 0.083
|
|
|
|
Slack (MET) : 0.083ns (arrival time - required time)
|
|
Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/wb_valid_r_reg_rep__5/C
|
|
(rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns})
|
|
Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/cr_reg[130][5]/D
|
|
(rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns})
|
|
Path Group: mlkem_clk_clk_pll
|
|
Path Type: Hold (Min at Fast Process Corner)
|
|
Requirement: 0.000ns (mlkem_clk_clk_pll rise@0.000ns - mlkem_clk_clk_pll rise@0.000ns)
|
|
Data Path Delay: 0.453ns (logic 0.186ns (41.036%) route 0.267ns (58.964%))
|
|
Logic Levels: 1 (LUT6=1)
|
|
Clock Path Skew: 0.278ns (DCD - SCD - CPR)
|
|
Destination Clock Delay (DCD): -0.439ns
|
|
Source Clock Delay (SCD): -0.672ns
|
|
Clock Pessimism Removal (CPR): -0.045ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock mlkem_clk_clk_pll rise edge)
|
|
0.000 0.000 r
|
|
clock source latency -1.848 -1.848
|
|
propagated clock network latency
|
|
1.177 -0.672
|
|
SLICE_X138Y154 FDCE 0.000 -0.672 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/wb_valid_r_reg_rep__5/C
|
|
SLICE_X138Y154 FDCE (Prop_fdce_C_Q) 0.141 -0.531 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/wb_valid_r_reg_rep__5/Q
|
|
net (fo=127, routed) 0.267 -0.264 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/wb_valid_r_reg_rep__5_n_0
|
|
SLICE_X137Y147 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/cr[130][5]_i_1/I3
|
|
SLICE_X137Y147 LUT6 (Prop_lut6_I3_O) 0.045 -0.219 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/cr[130][5]_i_1/O
|
|
net (fo=1, routed) 0.000 -0.219 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/cr[130][5]_i_1_n_0
|
|
SLICE_X137Y147 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/cr_reg[130][5]/D
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock mlkem_clk_clk_pll rise edge)
|
|
0.000 0.000 r
|
|
clock source latency -1.947 -1.947
|
|
propagated clock network latency
|
|
1.508 -0.439
|
|
clock pessimism 0.045 -0.394
|
|
SLICE_X137Y147 FDCE (Hold_fdce_C_D) 0.092 -0.302 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/cr_reg[130][5]
|
|
-------------------------------------------------------------------
|
|
required time 0.302
|
|
arrival time -0.219
|
|
-------------------------------------------------------------------
|
|
slack 0.083
|
|
|
|
Slack (MET) : 0.083ns (arrival time - required time)
|
|
Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/wb_valid_r_reg_rep__5/C
|
|
(rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns})
|
|
Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/cr_reg[130][5]/D
|
|
(rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns})
|
|
Path Group: mlkem_clk_clk_pll
|
|
Path Type: Hold (Min at Fast Process Corner)
|
|
Requirement: 0.000ns (mlkem_clk_clk_pll rise@0.000ns - mlkem_clk_clk_pll rise@0.000ns)
|
|
Data Path Delay: 0.453ns (logic 0.186ns (41.036%) route 0.267ns (58.964%))
|
|
Logic Levels: 1 (LUT6=1)
|
|
Clock Path Skew: 0.278ns (DCD - SCD - CPR)
|
|
Destination Clock Delay (DCD): -0.439ns
|
|
Source Clock Delay (SCD): -0.672ns
|
|
Clock Pessimism Removal (CPR): -0.045ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock mlkem_clk_clk_pll rise edge)
|
|
0.000 0.000 r
|
|
clock source latency -1.848 -1.848
|
|
propagated clock network latency
|
|
1.177 -0.672
|
|
SLICE_X138Y154 FDCE 0.000 -0.672 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/wb_valid_r_reg_rep__5/C
|
|
SLICE_X138Y154 FDCE (Prop_fdce_C_Q) 0.141 -0.531 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/wb_valid_r_reg_rep__5/Q
|
|
net (fo=127, routed) 0.267 -0.264 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/wb_valid_r_reg_rep__5_n_0
|
|
SLICE_X137Y147 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/cr[130][5]_i_1/I3
|
|
SLICE_X137Y147 LUT6 (Prop_lut6_I3_O) 0.045 -0.219 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/cr[130][5]_i_1/O
|
|
net (fo=1, routed) 0.000 -0.219 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/cr[130][5]_i_1_n_0
|
|
SLICE_X137Y147 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/cr_reg[130][5]/D
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock mlkem_clk_clk_pll rise edge)
|
|
0.000 0.000 r
|
|
clock source latency -1.947 -1.947
|
|
propagated clock network latency
|
|
1.508 -0.439
|
|
clock pessimism 0.045 -0.394
|
|
SLICE_X137Y147 FDCE (Hold_fdce_C_D) 0.092 -0.302 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/cr_reg[130][5]
|
|
-------------------------------------------------------------------
|
|
required time 0.302
|
|
arrival time -0.219
|
|
-------------------------------------------------------------------
|
|
slack 0.083
|
|
|
|
Slack (MET) : 0.083ns (arrival time - required time)
|
|
Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/wb_valid_r_reg_rep__5/C
|
|
(rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns})
|
|
Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/cr_reg[130][5]/D
|
|
(rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns})
|
|
Path Group: mlkem_clk_clk_pll
|
|
Path Type: Hold (Min at Fast Process Corner)
|
|
Requirement: 0.000ns (mlkem_clk_clk_pll rise@0.000ns - mlkem_clk_clk_pll rise@0.000ns)
|
|
Data Path Delay: 0.453ns (logic 0.186ns (41.036%) route 0.267ns (58.964%))
|
|
Logic Levels: 1 (LUT6=1)
|
|
Clock Path Skew: 0.278ns (DCD - SCD - CPR)
|
|
Destination Clock Delay (DCD): -0.439ns
|
|
Source Clock Delay (SCD): -0.672ns
|
|
Clock Pessimism Removal (CPR): -0.045ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock mlkem_clk_clk_pll rise edge)
|
|
0.000 0.000 r
|
|
clock source latency -1.848 -1.848
|
|
propagated clock network latency
|
|
1.177 -0.672
|
|
SLICE_X138Y154 FDCE 0.000 -0.672 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/wb_valid_r_reg_rep__5/C
|
|
SLICE_X138Y154 FDCE (Prop_fdce_C_Q) 0.141 -0.531 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/wb_valid_r_reg_rep__5/Q
|
|
net (fo=127, routed) 0.267 -0.264 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/wb_valid_r_reg_rep__5_n_0
|
|
SLICE_X137Y147 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/cr[130][5]_i_1/I3
|
|
SLICE_X137Y147 LUT6 (Prop_lut6_I3_O) 0.045 -0.219 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/cr[130][5]_i_1/O
|
|
net (fo=1, routed) 0.000 -0.219 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/cr[130][5]_i_1_n_0
|
|
SLICE_X137Y147 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/cr_reg[130][5]/D
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock mlkem_clk_clk_pll rise edge)
|
|
0.000 0.000 r
|
|
clock source latency -1.947 -1.947
|
|
propagated clock network latency
|
|
1.508 -0.439
|
|
clock pessimism 0.045 -0.394
|
|
SLICE_X137Y147 FDCE (Hold_fdce_C_D) 0.092 -0.302 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/cr_reg[130][5]
|
|
-------------------------------------------------------------------
|
|
required time 0.302
|
|
arrival time -0.219
|
|
-------------------------------------------------------------------
|
|
slack 0.083
|
|
|
|
Slack (MET) : 0.085ns (arrival time - required time)
|
|
Source: u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/wptr_reg[5]/C
|
|
(rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Destination: u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/mem_reg/ADDRBWRADDR[10]
|
|
(rising edge-triggered cell RAMB18E1 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Path Group: sys_clk
|
|
Path Type: Hold (Min at Fast Process Corner)
|
|
Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns)
|
|
Data Path Delay: 0.324ns (logic 0.164ns (50.614%) route 0.160ns (49.386%))
|
|
Logic Levels: 0
|
|
Clock Path Skew: 0.056ns (DCD - SCD - CPR)
|
|
Destination Clock Delay (DCD): -0.357ns
|
|
Source Clock Delay (SCD): -0.626ns
|
|
Clock Pessimism Removal (CPR): 0.213ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock sys_clk rise edge) 0.000 0.000 r
|
|
clock source latency -1.848 -1.848
|
|
propagated clock network latency
|
|
1.222 -0.626
|
|
SLICE_X62Y75 FDCE 0.000 -0.626 r u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/wptr_reg[5]/C
|
|
SLICE_X62Y75 FDCE (Prop_fdce_C_Q) 0.164 -0.462 r u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/wptr_reg[5]/Q
|
|
net (fo=2, routed) 0.160 -0.302 u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/wptr_reg[5]
|
|
RAMB18_X3Y30 RAMB18E1 r u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/mem_reg/ADDRBWRADDR[10]
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock sys_clk rise edge) 0.000 0.000 r
|
|
clock source latency -1.947 -1.947
|
|
propagated clock network latency
|
|
1.591 -0.357
|
|
clock pessimism -0.213 -0.570
|
|
RAMB18_X3Y30 RAMB18E1 (Hold_ramb18e1_CLKBWRCLK_ADDRBWRADDR[10])
|
|
0.183 -0.387 u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/mem_reg
|
|
-------------------------------------------------------------------
|
|
required time 0.387
|
|
arrival time -0.302
|
|
-------------------------------------------------------------------
|
|
slack 0.085
|
|
|
|
Slack (MET) : 0.085ns (arrival time - required time)
|
|
Source: u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/wptr_reg[5]/C
|
|
(rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Destination: u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/mem_reg/ADDRBWRADDR[10]
|
|
(rising edge-triggered cell RAMB18E1 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Path Group: sys_clk
|
|
Path Type: Hold (Min at Fast Process Corner)
|
|
Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns)
|
|
Data Path Delay: 0.324ns (logic 0.164ns (50.614%) route 0.160ns (49.386%))
|
|
Logic Levels: 0
|
|
Clock Path Skew: 0.056ns (DCD - SCD - CPR)
|
|
Destination Clock Delay (DCD): -0.357ns
|
|
Source Clock Delay (SCD): -0.626ns
|
|
Clock Pessimism Removal (CPR): 0.213ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock sys_clk rise edge) 0.000 0.000 r
|
|
clock source latency -1.848 -1.848
|
|
propagated clock network latency
|
|
1.222 -0.626
|
|
SLICE_X62Y75 FDCE 0.000 -0.626 r u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/wptr_reg[5]/C
|
|
SLICE_X62Y75 FDCE (Prop_fdce_C_Q) 0.164 -0.462 f u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/wptr_reg[5]/Q
|
|
net (fo=2, routed) 0.160 -0.302 u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/wptr_reg[5]
|
|
RAMB18_X3Y30 RAMB18E1 f u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/mem_reg/ADDRBWRADDR[10]
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock sys_clk rise edge) 0.000 0.000 r
|
|
clock source latency -1.947 -1.947
|
|
propagated clock network latency
|
|
1.591 -0.357
|
|
clock pessimism -0.213 -0.570
|
|
RAMB18_X3Y30 RAMB18E1 (Hold_ramb18e1_CLKBWRCLK_ADDRBWRADDR[10])
|
|
0.183 -0.387 u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/mem_reg
|
|
-------------------------------------------------------------------
|
|
required time 0.387
|
|
arrival time -0.302
|
|
-------------------------------------------------------------------
|
|
slack 0.085
|
|
|
|
Slack (MET) : 0.085ns (arrival time - required time)
|
|
Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_30_35/RAMC_D1/CLK
|
|
(rising edge-triggered cell RAMD32 clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns})
|
|
Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[35]/D
|
|
(rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Path Group: sys_clk
|
|
Path Type: Hold (Min at Fast Process Corner)
|
|
Requirement: 0.000ns (sys_clk rise@0.000ns - mlkem_clk_clk_pll rise@0.000ns)
|
|
Data Path Delay: 0.665ns (logic 0.386ns (58.079%) route 0.279ns (41.921%))
|
|
Logic Levels: 0
|
|
Clock Path Skew: 0.331ns (DCD - SCD - CPR)
|
|
Destination Clock Delay (DCD): -0.349ns
|
|
Source Clock Delay (SCD): -0.581ns
|
|
Clock Pessimism Removal (CPR): -0.099ns
|
|
Clock Uncertainty: 0.197ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Discrete Jitter (DJ): 0.136ns
|
|
Phase Error (PE): 0.120ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock mlkem_clk_clk_pll rise edge)
|
|
0.000 0.000 r
|
|
clock source latency -1.848 -1.848
|
|
propagated clock network latency
|
|
1.267 -0.581
|
|
SLICE_X20Y76 RAMD32 0.000 -0.581 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_30_35/RAMC_D1/CLK
|
|
SLICE_X20Y76 RAMD32 (Prop_ramd32_CLK_O)
|
|
0.386 -0.195 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_30_35/RAMC_D1/O
|
|
net (fo=1, routed) 0.279 0.083 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port10__3[35]
|
|
SLICE_X14Y78 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[35]/D
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock sys_clk rise edge) 0.000 0.000 r
|
|
clock source latency -1.947 -1.947
|
|
propagated clock network latency
|
|
1.598 -0.349
|
|
clock pessimism 0.099 -0.250
|
|
clock uncertainty 0.197 -0.054
|
|
SLICE_X14Y78 FDRE (Hold_fdre_C_D) 0.052 -0.002 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[35]
|
|
-------------------------------------------------------------------
|
|
required time 0.002
|
|
arrival time 0.083
|
|
-------------------------------------------------------------------
|
|
slack 0.085
|
|
|
|
Slack (MET) : 0.085ns (arrival time - required time)
|
|
Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_30_35/RAMC_D1/CLK
|
|
(rising edge-triggered cell RAMD32 clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns})
|
|
Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[35]/D
|
|
(rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Path Group: sys_clk
|
|
Path Type: Hold (Min at Fast Process Corner)
|
|
Requirement: 0.000ns (sys_clk rise@0.000ns - mlkem_clk_clk_pll rise@0.000ns)
|
|
Data Path Delay: 0.665ns (logic 0.386ns (58.079%) route 0.279ns (41.921%))
|
|
Logic Levels: 0
|
|
Clock Path Skew: 0.331ns (DCD - SCD - CPR)
|
|
Destination Clock Delay (DCD): -0.349ns
|
|
Source Clock Delay (SCD): -0.581ns
|
|
Clock Pessimism Removal (CPR): -0.099ns
|
|
Clock Uncertainty: 0.197ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Discrete Jitter (DJ): 0.136ns
|
|
Phase Error (PE): 0.120ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock mlkem_clk_clk_pll rise edge)
|
|
0.000 0.000 r
|
|
clock source latency -1.848 -1.848
|
|
propagated clock network latency
|
|
1.267 -0.581
|
|
SLICE_X20Y76 RAMD32 0.000 -0.581 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_30_35/RAMC_D1/CLK
|
|
SLICE_X20Y76 RAMD32 (Prop_ramd32_CLK_O)
|
|
0.386 -0.195 f u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_30_35/RAMC_D1/O
|
|
net (fo=1, routed) 0.279 0.083 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port10__3[35]
|
|
SLICE_X14Y78 FDRE f u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[35]/D
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock sys_clk rise edge) 0.000 0.000 r
|
|
clock source latency -1.947 -1.947
|
|
propagated clock network latency
|
|
1.598 -0.349
|
|
clock pessimism 0.099 -0.250
|
|
clock uncertainty 0.197 -0.054
|
|
SLICE_X14Y78 FDRE (Hold_fdre_C_D) 0.052 -0.002 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[35]
|
|
-------------------------------------------------------------------
|
|
required time 0.002
|
|
arrival time 0.083
|
|
-------------------------------------------------------------------
|
|
slack 0.085
|
|
|
|
Slack (MET) : 0.085ns (arrival time - required time)
|
|
Source: u_cpu/axi_bridge/awaddr_reg[1]/C
|
|
(rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns})
|
|
Destination: u_Axi_CDC/awFifo/ram_reg_0_3_0_5/RAMA_D1/I
|
|
(rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns})
|
|
Path Group: cpu_clk
|
|
Path Type: Hold (Min at Fast Process Corner)
|
|
Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns)
|
|
Data Path Delay: 0.400ns (logic 0.141ns (35.262%) route 0.259ns (64.738%))
|
|
Logic Levels: 0
|
|
Clock Path Skew: 0.194ns (DCD - SCD - CPR)
|
|
Destination Clock Delay (DCD): -0.339ns
|
|
Source Clock Delay (SCD): -0.497ns
|
|
Clock Pessimism Removal (CPR): -0.037ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock cpu_clk rise edge) 0.000 0.000 r
|
|
clock source latency -1.848 -1.848
|
|
propagated clock network latency
|
|
1.352 -0.497
|
|
SLICE_X23Y49 FDRE 0.000 -0.497 r u_cpu/axi_bridge/awaddr_reg[1]/C
|
|
SLICE_X23Y49 FDRE (Prop_fdre_C_Q) 0.141 -0.356 r u_cpu/axi_bridge/awaddr_reg[1]/Q
|
|
net (fo=1, routed) 0.259 -0.097 u_Axi_CDC/awFifo/ram_reg_0_3_0_5/DIA1
|
|
SLICE_X20Y58 RAMD32 r u_Axi_CDC/awFifo/ram_reg_0_3_0_5/RAMA_D1/I
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock cpu_clk rise edge) 0.000 0.000 r
|
|
clock source latency -1.947 -1.947
|
|
propagated clock network latency
|
|
1.608 -0.339
|
|
clock pessimism 0.037 -0.302
|
|
SLICE_X20Y58 RAMD32 (Hold_ramd32_CLK_I)
|
|
0.120 -0.182 u_Axi_CDC/awFifo/ram_reg_0_3_0_5/RAMA_D1
|
|
-------------------------------------------------------------------
|
|
required time 0.182
|
|
arrival time -0.097
|
|
-------------------------------------------------------------------
|
|
slack 0.085
|
|
|
|
Slack (MET) : 0.085ns (arrival time - required time)
|
|
Source: u_cpu/axi_bridge/awaddr_reg[1]/C
|
|
(rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns})
|
|
Destination: u_Axi_CDC/awFifo/ram_reg_0_3_0_5/RAMA_D1/I
|
|
(rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns})
|
|
Path Group: cpu_clk
|
|
Path Type: Hold (Min at Fast Process Corner)
|
|
Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns)
|
|
Data Path Delay: 0.400ns (logic 0.141ns (35.262%) route 0.259ns (64.738%))
|
|
Logic Levels: 0
|
|
Clock Path Skew: 0.194ns (DCD - SCD - CPR)
|
|
Destination Clock Delay (DCD): -0.339ns
|
|
Source Clock Delay (SCD): -0.497ns
|
|
Clock Pessimism Removal (CPR): -0.037ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock cpu_clk rise edge) 0.000 0.000 r
|
|
clock source latency -1.848 -1.848
|
|
propagated clock network latency
|
|
1.352 -0.497
|
|
SLICE_X23Y49 FDRE 0.000 -0.497 r u_cpu/axi_bridge/awaddr_reg[1]/C
|
|
SLICE_X23Y49 FDRE (Prop_fdre_C_Q) 0.141 -0.356 f u_cpu/axi_bridge/awaddr_reg[1]/Q
|
|
net (fo=1, routed) 0.259 -0.097 u_Axi_CDC/awFifo/ram_reg_0_3_0_5/DIA1
|
|
SLICE_X20Y58 RAMD32 f u_Axi_CDC/awFifo/ram_reg_0_3_0_5/RAMA_D1/I
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock cpu_clk rise edge) 0.000 0.000 r
|
|
clock source latency -1.947 -1.947
|
|
propagated clock network latency
|
|
1.608 -0.339
|
|
clock pessimism 0.037 -0.302
|
|
SLICE_X20Y58 RAMD32 (Hold_ramd32_CLK_I)
|
|
0.120 -0.182 u_Axi_CDC/awFifo/ram_reg_0_3_0_5/RAMA_D1
|
|
-------------------------------------------------------------------
|
|
required time 0.182
|
|
arrival time -0.097
|
|
-------------------------------------------------------------------
|
|
slack 0.085
|
|
|
|
Slack (MET) : 0.087ns (arrival time - required time)
|
|
Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_30_35/RAMA/CLK
|
|
(rising edge-triggered cell RAMD32 clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns})
|
|
Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[30]/D
|
|
(rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Path Group: sys_clk
|
|
Path Type: Hold (Min at Fast Process Corner)
|
|
Requirement: 0.000ns (sys_clk rise@0.000ns - mlkem_clk_clk_pll rise@0.000ns)
|
|
Data Path Delay: 0.611ns (logic 0.492ns (80.558%) route 0.119ns (19.442%))
|
|
Logic Levels: 0
|
|
Clock Path Skew: 0.327ns (DCD - SCD - CPR)
|
|
Destination Clock Delay (DCD): -0.353ns
|
|
Source Clock Delay (SCD): -0.581ns
|
|
Clock Pessimism Removal (CPR): -0.099ns
|
|
Clock Uncertainty: 0.197ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Discrete Jitter (DJ): 0.136ns
|
|
Phase Error (PE): 0.120ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock mlkem_clk_clk_pll rise edge)
|
|
0.000 0.000 r
|
|
clock source latency -1.848 -1.848
|
|
propagated clock network latency
|
|
1.267 -0.581
|
|
SLICE_X20Y76 RAMD32 0.000 -0.581 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_30_35/RAMA/CLK
|
|
SLICE_X20Y76 RAMD32 (Prop_ramd32_CLK_O)
|
|
0.492 -0.089 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_30_35/RAMA/O
|
|
net (fo=1, routed) 0.119 0.029 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port10__3[30]
|
|
SLICE_X23Y77 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[30]/D
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock sys_clk rise edge) 0.000 0.000 r
|
|
clock source latency -1.947 -1.947
|
|
propagated clock network latency
|
|
1.594 -0.353
|
|
clock pessimism 0.099 -0.254
|
|
clock uncertainty 0.197 -0.058
|
|
SLICE_X23Y77 FDRE (Hold_fdre_C_D) 0.000 -0.058 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[30]
|
|
-------------------------------------------------------------------
|
|
required time 0.058
|
|
arrival time 0.029
|
|
-------------------------------------------------------------------
|
|
slack 0.087
|
|
|
|
Slack (MET) : 0.087ns (arrival time - required time)
|
|
Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_30_35/RAMA/CLK
|
|
(rising edge-triggered cell RAMD32 clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns})
|
|
Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[30]/D
|
|
(rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Path Group: sys_clk
|
|
Path Type: Hold (Min at Fast Process Corner)
|
|
Requirement: 0.000ns (sys_clk rise@0.000ns - mlkem_clk_clk_pll rise@0.000ns)
|
|
Data Path Delay: 0.611ns (logic 0.492ns (80.558%) route 0.119ns (19.442%))
|
|
Logic Levels: 0
|
|
Clock Path Skew: 0.327ns (DCD - SCD - CPR)
|
|
Destination Clock Delay (DCD): -0.353ns
|
|
Source Clock Delay (SCD): -0.581ns
|
|
Clock Pessimism Removal (CPR): -0.099ns
|
|
Clock Uncertainty: 0.197ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Discrete Jitter (DJ): 0.136ns
|
|
Phase Error (PE): 0.120ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock mlkem_clk_clk_pll rise edge)
|
|
0.000 0.000 r
|
|
clock source latency -1.848 -1.848
|
|
propagated clock network latency
|
|
1.267 -0.581
|
|
SLICE_X20Y76 RAMD32 0.000 -0.581 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_30_35/RAMA/CLK
|
|
SLICE_X20Y76 RAMD32 (Prop_ramd32_CLK_O)
|
|
0.492 -0.089 f u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_30_35/RAMA/O
|
|
net (fo=1, routed) 0.119 0.029 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port10__3[30]
|
|
SLICE_X23Y77 FDRE f u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[30]/D
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock sys_clk rise edge) 0.000 0.000 r
|
|
clock source latency -1.947 -1.947
|
|
propagated clock network latency
|
|
1.594 -0.353
|
|
clock pessimism 0.099 -0.254
|
|
clock uncertainty 0.197 -0.058
|
|
SLICE_X23Y77 FDRE (Hold_fdre_C_D) 0.000 -0.058 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[30]
|
|
-------------------------------------------------------------------
|
|
required time 0.058
|
|
arrival time 0.029
|
|
-------------------------------------------------------------------
|
|
slack 0.087
|
|
|
|
Slack (MET) : 0.094ns (arrival time - required time)
|
|
Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/qprod_s4_reg[0]/C
|
|
(rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns})
|
|
Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[0]/D
|
|
(rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns})
|
|
Path Group: mlkem_clk_clk_pll
|
|
Path Type: Hold (Min at Fast Process Corner)
|
|
Requirement: 0.000ns (mlkem_clk_clk_pll rise@0.000ns - mlkem_clk_clk_pll rise@0.000ns)
|
|
Data Path Delay: 0.463ns (logic 0.256ns (55.346%) route 0.207ns (44.654%))
|
|
Logic Levels: 2 (CARRY4=1 LUT2=1)
|
|
Clock Path Skew: 0.264ns (DCD - SCD - CPR)
|
|
Destination Clock Delay (DCD): -0.477ns
|
|
Source Clock Delay (SCD): -0.701ns
|
|
Clock Pessimism Removal (CPR): -0.040ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock mlkem_clk_clk_pll rise edge)
|
|
0.000 0.000 r
|
|
clock source latency -1.848 -1.848
|
|
propagated clock network latency
|
|
1.148 -0.701
|
|
SLICE_X85Y156 FDCE 0.000 -0.701 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/qprod_s4_reg[0]/C
|
|
SLICE_X85Y156 FDCE (Prop_fdce_C_Q) 0.141 -0.560 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/qprod_s4_reg[0]/Q
|
|
net (fo=1, routed) 0.207 -0.353 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/qprod_s4[0]
|
|
SLICE_X83Y154 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5[3]_i_5/I1
|
|
SLICE_X83Y154 LUT2 (Prop_lut2_I1_O) 0.045 -0.308 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5[3]_i_5/O
|
|
net (fo=1, routed) 0.000 -0.308 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5[3]_i_5_n_0
|
|
SLICE_X83Y154 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[3]_i_1/S[0]
|
|
SLICE_X83Y154 CARRY4 (Prop_carry4_S[0]_O[0])
|
|
0.070 -0.238 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[3]_i_1/O[0]
|
|
net (fo=1, routed) 0.000 -0.238 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s50[0]
|
|
SLICE_X83Y154 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[0]/D
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock mlkem_clk_clk_pll rise edge)
|
|
0.000 0.000 r
|
|
clock source latency -1.947 -1.947
|
|
propagated clock network latency
|
|
1.470 -0.477
|
|
clock pessimism 0.040 -0.437
|
|
SLICE_X83Y154 FDCE (Hold_fdce_C_D) 0.105 -0.332 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[0]
|
|
-------------------------------------------------------------------
|
|
required time 0.332
|
|
arrival time -0.238
|
|
-------------------------------------------------------------------
|
|
slack 0.094
|
|
|
|
Slack (MET) : 0.094ns (arrival time - required time)
|
|
Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/qprod_s4_reg[0]/C
|
|
(rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns})
|
|
Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[0]/D
|
|
(rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns})
|
|
Path Group: mlkem_clk_clk_pll
|
|
Path Type: Hold (Min at Fast Process Corner)
|
|
Requirement: 0.000ns (mlkem_clk_clk_pll rise@0.000ns - mlkem_clk_clk_pll rise@0.000ns)
|
|
Data Path Delay: 0.463ns (logic 0.256ns (55.346%) route 0.207ns (44.654%))
|
|
Logic Levels: 2 (CARRY4=1 LUT2=1)
|
|
Clock Path Skew: 0.264ns (DCD - SCD - CPR)
|
|
Destination Clock Delay (DCD): -0.477ns
|
|
Source Clock Delay (SCD): -0.701ns
|
|
Clock Pessimism Removal (CPR): -0.040ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock mlkem_clk_clk_pll rise edge)
|
|
0.000 0.000 r
|
|
clock source latency -1.848 -1.848
|
|
propagated clock network latency
|
|
1.148 -0.701
|
|
SLICE_X85Y156 FDCE 0.000 -0.701 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/qprod_s4_reg[0]/C
|
|
SLICE_X85Y156 FDCE (Prop_fdce_C_Q) 0.141 -0.560 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/qprod_s4_reg[0]/Q
|
|
net (fo=1, routed) 0.207 -0.353 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/qprod_s4[0]
|
|
SLICE_X83Y154 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5[3]_i_5/I1
|
|
SLICE_X83Y154 LUT2 (Prop_lut2_I1_O) 0.045 -0.308 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5[3]_i_5/O
|
|
net (fo=1, routed) 0.000 -0.308 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5[3]_i_5_n_0
|
|
SLICE_X83Y154 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[3]_i_1/S[0]
|
|
SLICE_X83Y154 CARRY4 (Prop_carry4_S[0]_O[0])
|
|
0.070 -0.238 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[3]_i_1/O[0]
|
|
net (fo=1, routed) 0.000 -0.238 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s50[0]
|
|
SLICE_X83Y154 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[0]/D
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock mlkem_clk_clk_pll rise edge)
|
|
0.000 0.000 r
|
|
clock source latency -1.947 -1.947
|
|
propagated clock network latency
|
|
1.470 -0.477
|
|
clock pessimism 0.040 -0.437
|
|
SLICE_X83Y154 FDCE (Hold_fdce_C_D) 0.105 -0.332 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[0]
|
|
-------------------------------------------------------------------
|
|
required time 0.332
|
|
arrival time -0.238
|
|
-------------------------------------------------------------------
|
|
slack 0.094
|
|
|
|
Slack (MET) : 0.094ns (arrival time - required time)
|
|
Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/qprod_s4_reg[0]/C
|
|
(rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns})
|
|
Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[0]/D
|
|
(rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns})
|
|
Path Group: mlkem_clk_clk_pll
|
|
Path Type: Hold (Min at Fast Process Corner)
|
|
Requirement: 0.000ns (mlkem_clk_clk_pll rise@0.000ns - mlkem_clk_clk_pll rise@0.000ns)
|
|
Data Path Delay: 0.463ns (logic 0.256ns (55.346%) route 0.207ns (44.654%))
|
|
Logic Levels: 2 (CARRY4=1 LUT2=1)
|
|
Clock Path Skew: 0.264ns (DCD - SCD - CPR)
|
|
Destination Clock Delay (DCD): -0.477ns
|
|
Source Clock Delay (SCD): -0.701ns
|
|
Clock Pessimism Removal (CPR): -0.040ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock mlkem_clk_clk_pll rise edge)
|
|
0.000 0.000 r
|
|
clock source latency -1.848 -1.848
|
|
propagated clock network latency
|
|
1.148 -0.701
|
|
SLICE_X85Y156 FDCE 0.000 -0.701 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/qprod_s4_reg[0]/C
|
|
SLICE_X85Y156 FDCE (Prop_fdce_C_Q) 0.141 -0.560 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/qprod_s4_reg[0]/Q
|
|
net (fo=1, routed) 0.207 -0.353 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/qprod_s4[0]
|
|
SLICE_X83Y154 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5[3]_i_5/I1
|
|
SLICE_X83Y154 LUT2 (Prop_lut2_I1_O) 0.045 -0.308 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5[3]_i_5/O
|
|
net (fo=1, routed) 0.000 -0.308 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5[3]_i_5_n_0
|
|
SLICE_X83Y154 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[3]_i_1/S[0]
|
|
SLICE_X83Y154 CARRY4 (Prop_carry4_S[0]_O[0])
|
|
0.070 -0.238 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[3]_i_1/O[0]
|
|
net (fo=1, routed) 0.000 -0.238 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s50[0]
|
|
SLICE_X83Y154 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[0]/D
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock mlkem_clk_clk_pll rise edge)
|
|
0.000 0.000 r
|
|
clock source latency -1.947 -1.947
|
|
propagated clock network latency
|
|
1.470 -0.477
|
|
clock pessimism 0.040 -0.437
|
|
SLICE_X83Y154 FDCE (Hold_fdce_C_D) 0.105 -0.332 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[0]
|
|
-------------------------------------------------------------------
|
|
required time 0.332
|
|
arrival time -0.238
|
|
-------------------------------------------------------------------
|
|
slack 0.094
|
|
|
|
Slack (MET) : 0.094ns (arrival time - required time)
|
|
Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/qprod_s4_reg[0]/C
|
|
(rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns})
|
|
Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[0]/D
|
|
(rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns})
|
|
Path Group: mlkem_clk_clk_pll
|
|
Path Type: Hold (Min at Fast Process Corner)
|
|
Requirement: 0.000ns (mlkem_clk_clk_pll rise@0.000ns - mlkem_clk_clk_pll rise@0.000ns)
|
|
Data Path Delay: 0.463ns (logic 0.256ns (55.346%) route 0.207ns (44.654%))
|
|
Logic Levels: 2 (CARRY4=1 LUT2=1)
|
|
Clock Path Skew: 0.264ns (DCD - SCD - CPR)
|
|
Destination Clock Delay (DCD): -0.477ns
|
|
Source Clock Delay (SCD): -0.701ns
|
|
Clock Pessimism Removal (CPR): -0.040ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock mlkem_clk_clk_pll rise edge)
|
|
0.000 0.000 r
|
|
clock source latency -1.848 -1.848
|
|
propagated clock network latency
|
|
1.148 -0.701
|
|
SLICE_X85Y156 FDCE 0.000 -0.701 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/qprod_s4_reg[0]/C
|
|
SLICE_X85Y156 FDCE (Prop_fdce_C_Q) 0.141 -0.560 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/qprod_s4_reg[0]/Q
|
|
net (fo=1, routed) 0.207 -0.353 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/qprod_s4[0]
|
|
SLICE_X83Y154 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5[3]_i_5/I1
|
|
SLICE_X83Y154 LUT2 (Prop_lut2_I1_O) 0.045 -0.308 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5[3]_i_5/O
|
|
net (fo=1, routed) 0.000 -0.308 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5[3]_i_5_n_0
|
|
SLICE_X83Y154 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[3]_i_1/S[0]
|
|
SLICE_X83Y154 CARRY4 (Prop_carry4_S[0]_O[0])
|
|
0.070 -0.238 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[3]_i_1/O[0]
|
|
net (fo=1, routed) 0.000 -0.238 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s50[0]
|
|
SLICE_X83Y154 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[0]/D
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock mlkem_clk_clk_pll rise edge)
|
|
0.000 0.000 r
|
|
clock source latency -1.947 -1.947
|
|
propagated clock network latency
|
|
1.470 -0.477
|
|
clock pessimism 0.040 -0.437
|
|
SLICE_X83Y154 FDCE (Hold_fdce_C_D) 0.105 -0.332 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[0]
|
|
-------------------------------------------------------------------
|
|
required time 0.332
|
|
arrival time -0.238
|
|
-------------------------------------------------------------------
|
|
slack 0.094
|
|
|
|
Slack (MET) : 0.094ns (arrival time - required time)
|
|
Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/qprod_s4_reg[0]/C
|
|
(rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns})
|
|
Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[0]/D
|
|
(rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns})
|
|
Path Group: mlkem_clk_clk_pll
|
|
Path Type: Hold (Min at Fast Process Corner)
|
|
Requirement: 0.000ns (mlkem_clk_clk_pll rise@0.000ns - mlkem_clk_clk_pll rise@0.000ns)
|
|
Data Path Delay: 0.463ns (logic 0.256ns (55.346%) route 0.207ns (44.654%))
|
|
Logic Levels: 2 (CARRY4=1 LUT2=1)
|
|
Clock Path Skew: 0.264ns (DCD - SCD - CPR)
|
|
Destination Clock Delay (DCD): -0.477ns
|
|
Source Clock Delay (SCD): -0.701ns
|
|
Clock Pessimism Removal (CPR): -0.040ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock mlkem_clk_clk_pll rise edge)
|
|
0.000 0.000 r
|
|
clock source latency -1.848 -1.848
|
|
propagated clock network latency
|
|
1.148 -0.701
|
|
SLICE_X85Y156 FDCE 0.000 -0.701 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/qprod_s4_reg[0]/C
|
|
SLICE_X85Y156 FDCE (Prop_fdce_C_Q) 0.141 -0.560 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/qprod_s4_reg[0]/Q
|
|
net (fo=1, routed) 0.207 -0.353 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/qprod_s4[0]
|
|
SLICE_X83Y154 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5[3]_i_5/I1
|
|
SLICE_X83Y154 LUT2 (Prop_lut2_I1_O) 0.045 -0.308 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5[3]_i_5/O
|
|
net (fo=1, routed) 0.000 -0.308 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5[3]_i_5_n_0
|
|
SLICE_X83Y154 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[3]_i_1/S[0]
|
|
SLICE_X83Y154 CARRY4 (Prop_carry4_S[0]_O[0])
|
|
0.070 -0.238 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[3]_i_1/O[0]
|
|
net (fo=1, routed) 0.000 -0.238 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s50[0]
|
|
SLICE_X83Y154 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[0]/D
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock mlkem_clk_clk_pll rise edge)
|
|
0.000 0.000 r
|
|
clock source latency -1.947 -1.947
|
|
propagated clock network latency
|
|
1.470 -0.477
|
|
clock pessimism 0.040 -0.437
|
|
SLICE_X83Y154 FDCE (Hold_fdce_C_D) 0.105 -0.332 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[0]
|
|
-------------------------------------------------------------------
|
|
required time 0.332
|
|
arrival time -0.238
|
|
-------------------------------------------------------------------
|
|
slack 0.094
|
|
|
|
Slack (MET) : 0.094ns (arrival time - required time)
|
|
Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/qprod_s4_reg[0]/C
|
|
(rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns})
|
|
Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[0]/D
|
|
(rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns})
|
|
Path Group: mlkem_clk_clk_pll
|
|
Path Type: Hold (Min at Fast Process Corner)
|
|
Requirement: 0.000ns (mlkem_clk_clk_pll rise@0.000ns - mlkem_clk_clk_pll rise@0.000ns)
|
|
Data Path Delay: 0.463ns (logic 0.256ns (55.346%) route 0.207ns (44.654%))
|
|
Logic Levels: 2 (CARRY4=1 LUT2=1)
|
|
Clock Path Skew: 0.264ns (DCD - SCD - CPR)
|
|
Destination Clock Delay (DCD): -0.477ns
|
|
Source Clock Delay (SCD): -0.701ns
|
|
Clock Pessimism Removal (CPR): -0.040ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock mlkem_clk_clk_pll rise edge)
|
|
0.000 0.000 r
|
|
clock source latency -1.848 -1.848
|
|
propagated clock network latency
|
|
1.148 -0.701
|
|
SLICE_X85Y156 FDCE 0.000 -0.701 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/qprod_s4_reg[0]/C
|
|
SLICE_X85Y156 FDCE (Prop_fdce_C_Q) 0.141 -0.560 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/qprod_s4_reg[0]/Q
|
|
net (fo=1, routed) 0.207 -0.353 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/qprod_s4[0]
|
|
SLICE_X83Y154 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5[3]_i_5/I1
|
|
SLICE_X83Y154 LUT2 (Prop_lut2_I1_O) 0.045 -0.308 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5[3]_i_5/O
|
|
net (fo=1, routed) 0.000 -0.308 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5[3]_i_5_n_0
|
|
SLICE_X83Y154 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[3]_i_1/S[0]
|
|
SLICE_X83Y154 CARRY4 (Prop_carry4_S[0]_O[0])
|
|
0.070 -0.238 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[3]_i_1/O[0]
|
|
net (fo=1, routed) 0.000 -0.238 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s50[0]
|
|
SLICE_X83Y154 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[0]/D
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock mlkem_clk_clk_pll rise edge)
|
|
0.000 0.000 r
|
|
clock source latency -1.947 -1.947
|
|
propagated clock network latency
|
|
1.470 -0.477
|
|
clock pessimism 0.040 -0.437
|
|
SLICE_X83Y154 FDCE (Hold_fdce_C_D) 0.105 -0.332 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[0]
|
|
-------------------------------------------------------------------
|
|
required time 0.332
|
|
arrival time -0.238
|
|
-------------------------------------------------------------------
|
|
slack 0.094
|
|
|
|
Slack (MET) : 0.094ns (arrival time - required time)
|
|
Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/qprod_s4_reg[0]/C
|
|
(rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns})
|
|
Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[0]/D
|
|
(rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns})
|
|
Path Group: mlkem_clk_clk_pll
|
|
Path Type: Hold (Min at Fast Process Corner)
|
|
Requirement: 0.000ns (mlkem_clk_clk_pll rise@0.000ns - mlkem_clk_clk_pll rise@0.000ns)
|
|
Data Path Delay: 0.463ns (logic 0.256ns (55.346%) route 0.207ns (44.654%))
|
|
Logic Levels: 2 (CARRY4=1 LUT2=1)
|
|
Clock Path Skew: 0.264ns (DCD - SCD - CPR)
|
|
Destination Clock Delay (DCD): -0.477ns
|
|
Source Clock Delay (SCD): -0.701ns
|
|
Clock Pessimism Removal (CPR): -0.040ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock mlkem_clk_clk_pll rise edge)
|
|
0.000 0.000 r
|
|
clock source latency -1.848 -1.848
|
|
propagated clock network latency
|
|
1.148 -0.701
|
|
SLICE_X85Y156 FDCE 0.000 -0.701 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/qprod_s4_reg[0]/C
|
|
SLICE_X85Y156 FDCE (Prop_fdce_C_Q) 0.141 -0.560 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/qprod_s4_reg[0]/Q
|
|
net (fo=1, routed) 0.207 -0.353 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/qprod_s4[0]
|
|
SLICE_X83Y154 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5[3]_i_5/I1
|
|
SLICE_X83Y154 LUT2 (Prop_lut2_I1_O) 0.045 -0.308 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5[3]_i_5/O
|
|
net (fo=1, routed) 0.000 -0.308 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5[3]_i_5_n_0
|
|
SLICE_X83Y154 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[3]_i_1/S[0]
|
|
SLICE_X83Y154 CARRY4 (Prop_carry4_S[0]_O[0])
|
|
0.070 -0.238 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[3]_i_1/O[0]
|
|
net (fo=1, routed) 0.000 -0.238 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s50[0]
|
|
SLICE_X83Y154 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[0]/D
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock mlkem_clk_clk_pll rise edge)
|
|
0.000 0.000 r
|
|
clock source latency -1.947 -1.947
|
|
propagated clock network latency
|
|
1.470 -0.477
|
|
clock pessimism 0.040 -0.437
|
|
SLICE_X83Y154 FDCE (Hold_fdce_C_D) 0.105 -0.332 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[0]
|
|
-------------------------------------------------------------------
|
|
required time 0.332
|
|
arrival time -0.238
|
|
-------------------------------------------------------------------
|
|
slack 0.094
|
|
|
|
Slack (MET) : 0.094ns (arrival time - required time)
|
|
Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/qprod_s4_reg[0]/C
|
|
(rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns})
|
|
Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[0]/D
|
|
(rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns})
|
|
Path Group: mlkem_clk_clk_pll
|
|
Path Type: Hold (Min at Fast Process Corner)
|
|
Requirement: 0.000ns (mlkem_clk_clk_pll rise@0.000ns - mlkem_clk_clk_pll rise@0.000ns)
|
|
Data Path Delay: 0.463ns (logic 0.256ns (55.346%) route 0.207ns (44.654%))
|
|
Logic Levels: 2 (CARRY4=1 LUT2=1)
|
|
Clock Path Skew: 0.264ns (DCD - SCD - CPR)
|
|
Destination Clock Delay (DCD): -0.477ns
|
|
Source Clock Delay (SCD): -0.701ns
|
|
Clock Pessimism Removal (CPR): -0.040ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock mlkem_clk_clk_pll rise edge)
|
|
0.000 0.000 r
|
|
clock source latency -1.848 -1.848
|
|
propagated clock network latency
|
|
1.148 -0.701
|
|
SLICE_X85Y156 FDCE 0.000 -0.701 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/qprod_s4_reg[0]/C
|
|
SLICE_X85Y156 FDCE (Prop_fdce_C_Q) 0.141 -0.560 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/qprod_s4_reg[0]/Q
|
|
net (fo=1, routed) 0.207 -0.353 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/qprod_s4[0]
|
|
SLICE_X83Y154 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5[3]_i_5/I1
|
|
SLICE_X83Y154 LUT2 (Prop_lut2_I1_O) 0.045 -0.308 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5[3]_i_5/O
|
|
net (fo=1, routed) 0.000 -0.308 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5[3]_i_5_n_0
|
|
SLICE_X83Y154 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[3]_i_1/S[0]
|
|
SLICE_X83Y154 CARRY4 (Prop_carry4_S[0]_O[0])
|
|
0.070 -0.238 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[3]_i_1/O[0]
|
|
net (fo=1, routed) 0.000 -0.238 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s50[0]
|
|
SLICE_X83Y154 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[0]/D
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock mlkem_clk_clk_pll rise edge)
|
|
0.000 0.000 r
|
|
clock source latency -1.947 -1.947
|
|
propagated clock network latency
|
|
1.470 -0.477
|
|
clock pessimism 0.040 -0.437
|
|
SLICE_X83Y154 FDCE (Hold_fdce_C_D) 0.105 -0.332 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[0]
|
|
-------------------------------------------------------------------
|
|
required time 0.332
|
|
arrival time -0.238
|
|
-------------------------------------------------------------------
|
|
slack 0.094
|
|
|
|
Slack (MET) : 0.095ns (arrival time - required time)
|
|
Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/p_s1_reg[16]/C
|
|
(rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns})
|
|
Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/p_s2_reg[16]/D
|
|
(rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns})
|
|
Path Group: mlkem_clk_clk_pll
|
|
Path Type: Hold (Min at Fast Process Corner)
|
|
Requirement: 0.000ns (mlkem_clk_clk_pll rise@0.000ns - mlkem_clk_clk_pll rise@0.000ns)
|
|
Data Path Delay: 0.416ns (logic 0.141ns (33.875%) route 0.275ns (66.125%))
|
|
Logic Levels: 0
|
|
Clock Path Skew: 0.264ns (DCD - SCD - CPR)
|
|
Destination Clock Delay (DCD): -0.464ns
|
|
Source Clock Delay (SCD): -0.683ns
|
|
Clock Pessimism Removal (CPR): -0.045ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock mlkem_clk_clk_pll rise edge)
|
|
0.000 0.000 r
|
|
clock source latency -1.848 -1.848
|
|
propagated clock network latency
|
|
1.165 -0.683
|
|
SLICE_X73Y148 FDCE 0.000 -0.683 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/p_s1_reg[16]/C
|
|
SLICE_X73Y148 FDCE (Prop_fdce_C_Q) 0.141 -0.542 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/p_s1_reg[16]/Q
|
|
net (fo=14, routed) 0.275 -0.267 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/Q[16]
|
|
SLICE_X73Y154 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/p_s2_reg[16]/D
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock mlkem_clk_clk_pll rise edge)
|
|
0.000 0.000 r
|
|
clock source latency -1.947 -1.947
|
|
propagated clock network latency
|
|
1.483 -0.464
|
|
clock pessimism 0.045 -0.419
|
|
SLICE_X73Y154 FDCE (Hold_fdce_C_D) 0.057 -0.362 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/p_s2_reg[16]
|
|
-------------------------------------------------------------------
|
|
required time 0.362
|
|
arrival time -0.267
|
|
-------------------------------------------------------------------
|
|
slack 0.095
|
|
|
|
Slack (MET) : 0.095ns (arrival time - required time)
|
|
Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/p_s1_reg[16]/C
|
|
(rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns})
|
|
Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/p_s2_reg[16]/D
|
|
(rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns})
|
|
Path Group: mlkem_clk_clk_pll
|
|
Path Type: Hold (Min at Fast Process Corner)
|
|
Requirement: 0.000ns (mlkem_clk_clk_pll rise@0.000ns - mlkem_clk_clk_pll rise@0.000ns)
|
|
Data Path Delay: 0.416ns (logic 0.141ns (33.875%) route 0.275ns (66.125%))
|
|
Logic Levels: 0
|
|
Clock Path Skew: 0.264ns (DCD - SCD - CPR)
|
|
Destination Clock Delay (DCD): -0.464ns
|
|
Source Clock Delay (SCD): -0.683ns
|
|
Clock Pessimism Removal (CPR): -0.045ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock mlkem_clk_clk_pll rise edge)
|
|
0.000 0.000 r
|
|
clock source latency -1.848 -1.848
|
|
propagated clock network latency
|
|
1.165 -0.683
|
|
SLICE_X73Y148 FDCE 0.000 -0.683 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/p_s1_reg[16]/C
|
|
SLICE_X73Y148 FDCE (Prop_fdce_C_Q) 0.141 -0.542 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/p_s1_reg[16]/Q
|
|
net (fo=14, routed) 0.275 -0.267 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/Q[16]
|
|
SLICE_X73Y154 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/p_s2_reg[16]/D
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock mlkem_clk_clk_pll rise edge)
|
|
0.000 0.000 r
|
|
clock source latency -1.947 -1.947
|
|
propagated clock network latency
|
|
1.483 -0.464
|
|
clock pessimism 0.045 -0.419
|
|
SLICE_X73Y154 FDCE (Hold_fdce_C_D) 0.057 -0.362 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/p_s2_reg[16]
|
|
-------------------------------------------------------------------
|
|
required time 0.362
|
|
arrival time -0.267
|
|
-------------------------------------------------------------------
|
|
slack 0.095
|
|
|
|
Slack (MET) : 0.096ns (arrival time - required time)
|
|
Source: u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/DB1/buf_re_reg[127][1]_srl32/CLK
|
|
(rising edge-triggered cell SRLC32E clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Destination: u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/DB1/buf_re_reg[159][1]_srl32/D
|
|
(rising edge-triggered cell SRLC32E clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Path Group: sys_clk
|
|
Path Type: Hold (Min at Fast Process Corner)
|
|
Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns)
|
|
Data Path Delay: 0.561ns (logic 0.378ns (67.415%) route 0.183ns (32.585%))
|
|
Logic Levels: 0
|
|
Clock Path Skew: 0.343ns (DCD - SCD - CPR)
|
|
Destination Clock Delay (DCD): -0.262ns
|
|
Source Clock Delay (SCD): -0.568ns
|
|
Clock Pessimism Removal (CPR): -0.037ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock sys_clk rise edge) 0.000 0.000 r
|
|
clock source latency -1.848 -1.848
|
|
propagated clock network latency
|
|
1.280 -0.568
|
|
SLICE_X20Y50 SRLC32E 0.000 -0.568 r u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/DB1/buf_re_reg[127][1]_srl32/CLK
|
|
SLICE_X20Y50 SRLC32E (Prop_srlc32e_CLK_Q31)
|
|
0.378 -0.190 r u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/DB1/buf_re_reg[127][1]_srl32/Q31
|
|
net (fo=1, routed) 0.183 -0.008 u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/DB1/xlnx_opt__55
|
|
SLICE_X20Y49 SRLC32E r u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/DB1/buf_re_reg[159][1]_srl32/D
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock sys_clk rise edge) 0.000 0.000 r
|
|
clock source latency -1.947 -1.947
|
|
propagated clock network latency
|
|
1.685 -0.262
|
|
clock pessimism 0.037 -0.225
|
|
SLICE_X20Y49 SRLC32E (Hold_srlc32e_CLK_D)
|
|
0.122 -0.103 u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/DB1/buf_re_reg[159][1]_srl32
|
|
-------------------------------------------------------------------
|
|
required time 0.103
|
|
arrival time -0.008
|
|
-------------------------------------------------------------------
|
|
slack 0.096
|
|
|
|
Slack (MET) : 0.096ns (arrival time - required time)
|
|
Source: u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/DB1/buf_re_reg[127][1]_srl32/CLK
|
|
(rising edge-triggered cell SRLC32E clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Destination: u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/DB1/buf_re_reg[159][1]_srl32/D
|
|
(rising edge-triggered cell SRLC32E clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Path Group: sys_clk
|
|
Path Type: Hold (Min at Fast Process Corner)
|
|
Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns)
|
|
Data Path Delay: 0.561ns (logic 0.378ns (67.415%) route 0.183ns (32.585%))
|
|
Logic Levels: 0
|
|
Clock Path Skew: 0.343ns (DCD - SCD - CPR)
|
|
Destination Clock Delay (DCD): -0.262ns
|
|
Source Clock Delay (SCD): -0.568ns
|
|
Clock Pessimism Removal (CPR): -0.037ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock sys_clk rise edge) 0.000 0.000 r
|
|
clock source latency -1.848 -1.848
|
|
propagated clock network latency
|
|
1.280 -0.568
|
|
SLICE_X20Y50 SRLC32E 0.000 -0.568 r u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/DB1/buf_re_reg[127][1]_srl32/CLK
|
|
SLICE_X20Y50 SRLC32E (Prop_srlc32e_CLK_Q31)
|
|
0.378 -0.190 f u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/DB1/buf_re_reg[127][1]_srl32/Q31
|
|
net (fo=1, routed) 0.183 -0.008 u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/DB1/xlnx_opt__55
|
|
SLICE_X20Y49 SRLC32E f u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/DB1/buf_re_reg[159][1]_srl32/D
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock sys_clk rise edge) 0.000 0.000 r
|
|
clock source latency -1.947 -1.947
|
|
propagated clock network latency
|
|
1.685 -0.262
|
|
clock pessimism 0.037 -0.225
|
|
SLICE_X20Y49 SRLC32E (Hold_srlc32e_CLK_D)
|
|
0.122 -0.103 u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/DB1/buf_re_reg[159][1]_srl32
|
|
-------------------------------------------------------------------
|
|
required time 0.103
|
|
arrival time -0.008
|
|
-------------------------------------------------------------------
|
|
slack 0.096
|
|
|
|
Slack (MET) : 0.096ns (arrival time - required time)
|
|
Source: u_cpu/axi_bridge/wdata_reg[14]/C
|
|
(rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns})
|
|
Destination: u_Axi_CDC/wFifo/ram_reg_0_7_12_17/RAMB/I
|
|
(rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns})
|
|
Path Group: cpu_clk
|
|
Path Type: Hold (Min at Fast Process Corner)
|
|
Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns)
|
|
Data Path Delay: 0.257ns (logic 0.141ns (54.812%) route 0.116ns (45.188%))
|
|
Logic Levels: 0
|
|
Clock Path Skew: 0.015ns (DCD - SCD - CPR)
|
|
Destination Clock Delay (DCD): -0.232ns
|
|
Source Clock Delay (SCD): -0.467ns
|
|
Clock Pessimism Removal (CPR): 0.220ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock cpu_clk rise edge) 0.000 0.000 r
|
|
clock source latency -1.848 -1.848
|
|
propagated clock network latency
|
|
1.382 -0.467
|
|
SLICE_X7Y48 FDRE 0.000 -0.467 r u_cpu/axi_bridge/wdata_reg[14]/C
|
|
SLICE_X7Y48 FDRE (Prop_fdre_C_Q) 0.141 -0.326 r u_cpu/axi_bridge/wdata_reg[14]/Q
|
|
net (fo=1, routed) 0.116 -0.210 u_Axi_CDC/wFifo/ram_reg_0_7_12_17/DIB0
|
|
SLICE_X6Y46 RAMD32 r u_Axi_CDC/wFifo/ram_reg_0_7_12_17/RAMB/I
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock cpu_clk rise edge) 0.000 0.000 r
|
|
clock source latency -1.947 -1.947
|
|
propagated clock network latency
|
|
1.715 -0.232
|
|
clock pessimism -0.220 -0.452
|
|
SLICE_X6Y46 RAMD32 (Hold_ramd32_CLK_I)
|
|
0.146 -0.306 u_Axi_CDC/wFifo/ram_reg_0_7_12_17/RAMB
|
|
-------------------------------------------------------------------
|
|
required time 0.306
|
|
arrival time -0.210
|
|
-------------------------------------------------------------------
|
|
slack 0.096
|
|
|
|
Slack (MET) : 0.096ns (arrival time - required time)
|
|
Source: u_cpu/axi_bridge/wdata_reg[14]/C
|
|
(rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns})
|
|
Destination: u_Axi_CDC/wFifo/ram_reg_0_7_12_17/RAMB/I
|
|
(rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns})
|
|
Path Group: cpu_clk
|
|
Path Type: Hold (Min at Fast Process Corner)
|
|
Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns)
|
|
Data Path Delay: 0.257ns (logic 0.141ns (54.812%) route 0.116ns (45.188%))
|
|
Logic Levels: 0
|
|
Clock Path Skew: 0.015ns (DCD - SCD - CPR)
|
|
Destination Clock Delay (DCD): -0.232ns
|
|
Source Clock Delay (SCD): -0.467ns
|
|
Clock Pessimism Removal (CPR): 0.220ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock cpu_clk rise edge) 0.000 0.000 r
|
|
clock source latency -1.848 -1.848
|
|
propagated clock network latency
|
|
1.382 -0.467
|
|
SLICE_X7Y48 FDRE 0.000 -0.467 r u_cpu/axi_bridge/wdata_reg[14]/C
|
|
SLICE_X7Y48 FDRE (Prop_fdre_C_Q) 0.141 -0.326 f u_cpu/axi_bridge/wdata_reg[14]/Q
|
|
net (fo=1, routed) 0.116 -0.210 u_Axi_CDC/wFifo/ram_reg_0_7_12_17/DIB0
|
|
SLICE_X6Y46 RAMD32 f u_Axi_CDC/wFifo/ram_reg_0_7_12_17/RAMB/I
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock cpu_clk rise edge) 0.000 0.000 r
|
|
clock source latency -1.947 -1.947
|
|
propagated clock network latency
|
|
1.715 -0.232
|
|
clock pessimism -0.220 -0.452
|
|
SLICE_X6Y46 RAMD32 (Hold_ramd32_CLK_I)
|
|
0.146 -0.306 u_Axi_CDC/wFifo/ram_reg_0_7_12_17/RAMB
|
|
-------------------------------------------------------------------
|
|
required time 0.306
|
|
arrival time -0.210
|
|
-------------------------------------------------------------------
|
|
slack 0.096
|
|
|
|
Slack (MET) : 0.099ns (arrival time - required time)
|
|
Source: u_cpu/u_csr/csr_tlbelo1_reg[26]/C
|
|
(rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns})
|
|
Destination: u_cpu/addr_trans/tlb_entry/tlb_ppn1_reg_r1_0_31_18_19/RAMA/I
|
|
(rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns})
|
|
Path Group: cpu_clk
|
|
Path Type: Hold (Min at Fast Process Corner)
|
|
Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns)
|
|
Data Path Delay: 0.261ns (logic 0.141ns (54.037%) route 0.120ns (45.963%))
|
|
Logic Levels: 0
|
|
Clock Path Skew: 0.015ns (DCD - SCD - CPR)
|
|
Destination Clock Delay (DCD): -0.309ns
|
|
Source Clock Delay (SCD): -0.541ns
|
|
Clock Pessimism Removal (CPR): 0.217ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock cpu_clk rise edge) 0.000 0.000 r
|
|
clock source latency -1.848 -1.848
|
|
propagated clock network latency
|
|
1.308 -0.541
|
|
SLICE_X47Y35 FDRE 0.000 -0.541 r u_cpu/u_csr/csr_tlbelo1_reg[26]/C
|
|
SLICE_X47Y35 FDRE (Prop_fdre_C_Q) 0.141 -0.400 r u_cpu/u_csr/csr_tlbelo1_reg[26]/Q
|
|
net (fo=4, routed) 0.120 -0.280 u_cpu/addr_trans/tlb_entry/tlb_ppn1_reg_r1_0_31_18_19/DIA0
|
|
SLICE_X46Y36 RAMD32 r u_cpu/addr_trans/tlb_entry/tlb_ppn1_reg_r1_0_31_18_19/RAMA/I
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock cpu_clk rise edge) 0.000 0.000 r
|
|
clock source latency -1.947 -1.947
|
|
propagated clock network latency
|
|
1.638 -0.309
|
|
clock pessimism -0.217 -0.526
|
|
SLICE_X46Y36 RAMD32 (Hold_ramd32_CLK_I)
|
|
0.147 -0.379 u_cpu/addr_trans/tlb_entry/tlb_ppn1_reg_r1_0_31_18_19/RAMA
|
|
-------------------------------------------------------------------
|
|
required time 0.379
|
|
arrival time -0.280
|
|
-------------------------------------------------------------------
|
|
slack 0.099
|
|
|
|
Slack (MET) : 0.099ns (arrival time - required time)
|
|
Source: u_cpu/u_csr/csr_tlbelo1_reg[26]/C
|
|
(rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns})
|
|
Destination: u_cpu/addr_trans/tlb_entry/tlb_ppn1_reg_r1_0_31_18_19/RAMA/I
|
|
(rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns})
|
|
Path Group: cpu_clk
|
|
Path Type: Hold (Min at Fast Process Corner)
|
|
Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns)
|
|
Data Path Delay: 0.261ns (logic 0.141ns (54.037%) route 0.120ns (45.963%))
|
|
Logic Levels: 0
|
|
Clock Path Skew: 0.015ns (DCD - SCD - CPR)
|
|
Destination Clock Delay (DCD): -0.309ns
|
|
Source Clock Delay (SCD): -0.541ns
|
|
Clock Pessimism Removal (CPR): 0.217ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock cpu_clk rise edge) 0.000 0.000 r
|
|
clock source latency -1.848 -1.848
|
|
propagated clock network latency
|
|
1.308 -0.541
|
|
SLICE_X47Y35 FDRE 0.000 -0.541 r u_cpu/u_csr/csr_tlbelo1_reg[26]/C
|
|
SLICE_X47Y35 FDRE (Prop_fdre_C_Q) 0.141 -0.400 f u_cpu/u_csr/csr_tlbelo1_reg[26]/Q
|
|
net (fo=4, routed) 0.120 -0.280 u_cpu/addr_trans/tlb_entry/tlb_ppn1_reg_r1_0_31_18_19/DIA0
|
|
SLICE_X46Y36 RAMD32 f u_cpu/addr_trans/tlb_entry/tlb_ppn1_reg_r1_0_31_18_19/RAMA/I
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock cpu_clk rise edge) 0.000 0.000 r
|
|
clock source latency -1.947 -1.947
|
|
propagated clock network latency
|
|
1.638 -0.309
|
|
clock pessimism -0.217 -0.526
|
|
SLICE_X46Y36 RAMD32 (Hold_ramd32_CLK_I)
|
|
0.147 -0.379 u_cpu/addr_trans/tlb_entry/tlb_ppn1_reg_r1_0_31_18_19/RAMA
|
|
-------------------------------------------------------------------
|
|
required time 0.379
|
|
arrival time -0.280
|
|
-------------------------------------------------------------------
|
|
slack 0.099
|
|
|
|
Slack (MET) : 0.099ns (arrival time - required time)
|
|
Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_scl/p_s4_reg[2]/C
|
|
(rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns})
|
|
Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_scl/r0_s5_reg[2]/D
|
|
(rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns})
|
|
Path Group: mlkem_clk_clk_pll
|
|
Path Type: Hold (Min at Fast Process Corner)
|
|
Requirement: 0.000ns (mlkem_clk_clk_pll rise@0.000ns - mlkem_clk_clk_pll rise@0.000ns)
|
|
Data Path Delay: 0.470ns (logic 0.252ns (53.610%) route 0.218ns (46.390%))
|
|
Logic Levels: 2 (CARRY4=1 LUT2=1)
|
|
Clock Path Skew: 0.266ns (DCD - SCD - CPR)
|
|
Destination Clock Delay (DCD): -0.477ns
|
|
Source Clock Delay (SCD): -0.703ns
|
|
Clock Pessimism Removal (CPR): -0.040ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock mlkem_clk_clk_pll rise edge)
|
|
0.000 0.000 r
|
|
clock source latency -1.848 -1.848
|
|
propagated clock network latency
|
|
1.146 -0.703
|
|
SLICE_X85Y160 FDCE 0.000 -0.703 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_scl/p_s4_reg[2]/C
|
|
SLICE_X85Y160 FDCE (Prop_fdce_C_Q) 0.141 -0.562 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_scl/p_s4_reg[2]/Q
|
|
net (fo=2, routed) 0.218 -0.344 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_scl/p_s4[2]
|
|
SLICE_X79Y160 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_scl/r0_s5[3]_i_3__0/I0
|
|
SLICE_X79Y160 LUT2 (Prop_lut2_I0_O) 0.045 -0.299 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_scl/r0_s5[3]_i_3__0/O
|
|
net (fo=1, routed) 0.000 -0.299 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_scl/r0_s5[3]_i_3__0_n_0
|
|
SLICE_X79Y160 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_scl/r0_s5_reg[3]_i_1__0/S[2]
|
|
SLICE_X79Y160 CARRY4 (Prop_carry4_S[2]_O[2])
|
|
0.066 -0.233 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_scl/r0_s5_reg[3]_i_1__0/O[2]
|
|
net (fo=1, routed) 0.000 -0.233 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_scl/r0_s50[2]
|
|
SLICE_X79Y160 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_scl/r0_s5_reg[2]/D
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock mlkem_clk_clk_pll rise edge)
|
|
0.000 0.000 r
|
|
clock source latency -1.947 -1.947
|
|
propagated clock network latency
|
|
1.470 -0.477
|
|
clock pessimism 0.040 -0.437
|
|
SLICE_X79Y160 FDCE (Hold_fdce_C_D) 0.105 -0.332 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_scl/r0_s5_reg[2]
|
|
-------------------------------------------------------------------
|
|
required time 0.332
|
|
arrival time -0.233
|
|
-------------------------------------------------------------------
|
|
slack 0.099
|
|
|
|
Slack (MET) : 0.099ns (arrival time - required time)
|
|
Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_scl/p_s4_reg[2]/C
|
|
(rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns})
|
|
Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_scl/r0_s5_reg[2]/D
|
|
(rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns})
|
|
Path Group: mlkem_clk_clk_pll
|
|
Path Type: Hold (Min at Fast Process Corner)
|
|
Requirement: 0.000ns (mlkem_clk_clk_pll rise@0.000ns - mlkem_clk_clk_pll rise@0.000ns)
|
|
Data Path Delay: 0.470ns (logic 0.252ns (53.610%) route 0.218ns (46.390%))
|
|
Logic Levels: 2 (CARRY4=1 LUT2=1)
|
|
Clock Path Skew: 0.266ns (DCD - SCD - CPR)
|
|
Destination Clock Delay (DCD): -0.477ns
|
|
Source Clock Delay (SCD): -0.703ns
|
|
Clock Pessimism Removal (CPR): -0.040ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock mlkem_clk_clk_pll rise edge)
|
|
0.000 0.000 r
|
|
clock source latency -1.848 -1.848
|
|
propagated clock network latency
|
|
1.146 -0.703
|
|
SLICE_X85Y160 FDCE 0.000 -0.703 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_scl/p_s4_reg[2]/C
|
|
SLICE_X85Y160 FDCE (Prop_fdce_C_Q) 0.141 -0.562 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_scl/p_s4_reg[2]/Q
|
|
net (fo=2, routed) 0.218 -0.344 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_scl/p_s4[2]
|
|
SLICE_X79Y160 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_scl/r0_s5[3]_i_3__0/I0
|
|
SLICE_X79Y160 LUT2 (Prop_lut2_I0_O) 0.045 -0.299 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_scl/r0_s5[3]_i_3__0/O
|
|
net (fo=1, routed) 0.000 -0.299 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_scl/r0_s5[3]_i_3__0_n_0
|
|
SLICE_X79Y160 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_scl/r0_s5_reg[3]_i_1__0/S[2]
|
|
SLICE_X79Y160 CARRY4 (Prop_carry4_S[2]_O[2])
|
|
0.066 -0.233 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_scl/r0_s5_reg[3]_i_1__0/O[2]
|
|
net (fo=1, routed) 0.000 -0.233 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_scl/r0_s50[2]
|
|
SLICE_X79Y160 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_scl/r0_s5_reg[2]/D
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock mlkem_clk_clk_pll rise edge)
|
|
0.000 0.000 r
|
|
clock source latency -1.947 -1.947
|
|
propagated clock network latency
|
|
1.470 -0.477
|
|
clock pessimism 0.040 -0.437
|
|
SLICE_X79Y160 FDCE (Hold_fdce_C_D) 0.105 -0.332 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_scl/r0_s5_reg[2]
|
|
-------------------------------------------------------------------
|
|
required time 0.332
|
|
arrival time -0.233
|
|
-------------------------------------------------------------------
|
|
slack 0.099
|
|
|
|
Slack (MET) : 0.099ns (arrival time - required time)
|
|
Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_scl/p_s4_reg[2]/C
|
|
(rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns})
|
|
Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_scl/r0_s5_reg[2]/D
|
|
(rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns})
|
|
Path Group: mlkem_clk_clk_pll
|
|
Path Type: Hold (Min at Fast Process Corner)
|
|
Requirement: 0.000ns (mlkem_clk_clk_pll rise@0.000ns - mlkem_clk_clk_pll rise@0.000ns)
|
|
Data Path Delay: 0.470ns (logic 0.252ns (53.610%) route 0.218ns (46.390%))
|
|
Logic Levels: 2 (CARRY4=1 LUT2=1)
|
|
Clock Path Skew: 0.266ns (DCD - SCD - CPR)
|
|
Destination Clock Delay (DCD): -0.477ns
|
|
Source Clock Delay (SCD): -0.703ns
|
|
Clock Pessimism Removal (CPR): -0.040ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock mlkem_clk_clk_pll rise edge)
|
|
0.000 0.000 r
|
|
clock source latency -1.848 -1.848
|
|
propagated clock network latency
|
|
1.146 -0.703
|
|
SLICE_X85Y160 FDCE 0.000 -0.703 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_scl/p_s4_reg[2]/C
|
|
SLICE_X85Y160 FDCE (Prop_fdce_C_Q) 0.141 -0.562 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_scl/p_s4_reg[2]/Q
|
|
net (fo=2, routed) 0.218 -0.344 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_scl/p_s4[2]
|
|
SLICE_X79Y160 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_scl/r0_s5[3]_i_3__0/I0
|
|
SLICE_X79Y160 LUT2 (Prop_lut2_I0_O) 0.045 -0.299 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_scl/r0_s5[3]_i_3__0/O
|
|
net (fo=1, routed) 0.000 -0.299 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_scl/r0_s5[3]_i_3__0_n_0
|
|
SLICE_X79Y160 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_scl/r0_s5_reg[3]_i_1__0/S[2]
|
|
SLICE_X79Y160 CARRY4 (Prop_carry4_S[2]_O[2])
|
|
0.066 -0.233 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_scl/r0_s5_reg[3]_i_1__0/O[2]
|
|
net (fo=1, routed) 0.000 -0.233 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_scl/r0_s50[2]
|
|
SLICE_X79Y160 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_scl/r0_s5_reg[2]/D
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock mlkem_clk_clk_pll rise edge)
|
|
0.000 0.000 r
|
|
clock source latency -1.947 -1.947
|
|
propagated clock network latency
|
|
1.470 -0.477
|
|
clock pessimism 0.040 -0.437
|
|
SLICE_X79Y160 FDCE (Hold_fdce_C_D) 0.105 -0.332 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_scl/r0_s5_reg[2]
|
|
-------------------------------------------------------------------
|
|
required time 0.332
|
|
arrival time -0.233
|
|
-------------------------------------------------------------------
|
|
slack 0.099
|
|
|
|
Slack (MET) : 0.099ns (arrival time - required time)
|
|
Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_scl/p_s4_reg[2]/C
|
|
(rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns})
|
|
Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_scl/r0_s5_reg[2]/D
|
|
(rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns})
|
|
Path Group: mlkem_clk_clk_pll
|
|
Path Type: Hold (Min at Fast Process Corner)
|
|
Requirement: 0.000ns (mlkem_clk_clk_pll rise@0.000ns - mlkem_clk_clk_pll rise@0.000ns)
|
|
Data Path Delay: 0.470ns (logic 0.252ns (53.610%) route 0.218ns (46.390%))
|
|
Logic Levels: 2 (CARRY4=1 LUT2=1)
|
|
Clock Path Skew: 0.266ns (DCD - SCD - CPR)
|
|
Destination Clock Delay (DCD): -0.477ns
|
|
Source Clock Delay (SCD): -0.703ns
|
|
Clock Pessimism Removal (CPR): -0.040ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock mlkem_clk_clk_pll rise edge)
|
|
0.000 0.000 r
|
|
clock source latency -1.848 -1.848
|
|
propagated clock network latency
|
|
1.146 -0.703
|
|
SLICE_X85Y160 FDCE 0.000 -0.703 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_scl/p_s4_reg[2]/C
|
|
SLICE_X85Y160 FDCE (Prop_fdce_C_Q) 0.141 -0.562 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_scl/p_s4_reg[2]/Q
|
|
net (fo=2, routed) 0.218 -0.344 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_scl/p_s4[2]
|
|
SLICE_X79Y160 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_scl/r0_s5[3]_i_3__0/I0
|
|
SLICE_X79Y160 LUT2 (Prop_lut2_I0_O) 0.045 -0.299 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_scl/r0_s5[3]_i_3__0/O
|
|
net (fo=1, routed) 0.000 -0.299 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_scl/r0_s5[3]_i_3__0_n_0
|
|
SLICE_X79Y160 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_scl/r0_s5_reg[3]_i_1__0/S[2]
|
|
SLICE_X79Y160 CARRY4 (Prop_carry4_S[2]_O[2])
|
|
0.066 -0.233 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_scl/r0_s5_reg[3]_i_1__0/O[2]
|
|
net (fo=1, routed) 0.000 -0.233 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_scl/r0_s50[2]
|
|
SLICE_X79Y160 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_scl/r0_s5_reg[2]/D
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock mlkem_clk_clk_pll rise edge)
|
|
0.000 0.000 r
|
|
clock source latency -1.947 -1.947
|
|
propagated clock network latency
|
|
1.470 -0.477
|
|
clock pessimism 0.040 -0.437
|
|
SLICE_X79Y160 FDCE (Hold_fdce_C_D) 0.105 -0.332 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_scl/r0_s5_reg[2]
|
|
-------------------------------------------------------------------
|
|
required time 0.332
|
|
arrival time -0.233
|
|
-------------------------------------------------------------------
|
|
slack 0.099
|
|
|
|
Slack (MET) : 0.099ns (arrival time - required time)
|
|
Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_scl/p_s4_reg[2]/C
|
|
(rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns})
|
|
Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_scl/r0_s5_reg[2]/D
|
|
(rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns})
|
|
Path Group: mlkem_clk_clk_pll
|
|
Path Type: Hold (Min at Fast Process Corner)
|
|
Requirement: 0.000ns (mlkem_clk_clk_pll rise@0.000ns - mlkem_clk_clk_pll rise@0.000ns)
|
|
Data Path Delay: 0.470ns (logic 0.252ns (53.610%) route 0.218ns (46.390%))
|
|
Logic Levels: 2 (CARRY4=1 LUT2=1)
|
|
Clock Path Skew: 0.266ns (DCD - SCD - CPR)
|
|
Destination Clock Delay (DCD): -0.477ns
|
|
Source Clock Delay (SCD): -0.703ns
|
|
Clock Pessimism Removal (CPR): -0.040ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock mlkem_clk_clk_pll rise edge)
|
|
0.000 0.000 r
|
|
clock source latency -1.848 -1.848
|
|
propagated clock network latency
|
|
1.146 -0.703
|
|
SLICE_X85Y160 FDCE 0.000 -0.703 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_scl/p_s4_reg[2]/C
|
|
SLICE_X85Y160 FDCE (Prop_fdce_C_Q) 0.141 -0.562 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_scl/p_s4_reg[2]/Q
|
|
net (fo=2, routed) 0.218 -0.344 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_scl/p_s4[2]
|
|
SLICE_X79Y160 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_scl/r0_s5[3]_i_3__0/I0
|
|
SLICE_X79Y160 LUT2 (Prop_lut2_I0_O) 0.045 -0.299 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_scl/r0_s5[3]_i_3__0/O
|
|
net (fo=1, routed) 0.000 -0.299 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_scl/r0_s5[3]_i_3__0_n_0
|
|
SLICE_X79Y160 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_scl/r0_s5_reg[3]_i_1__0/S[2]
|
|
SLICE_X79Y160 CARRY4 (Prop_carry4_S[2]_O[2])
|
|
0.066 -0.233 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_scl/r0_s5_reg[3]_i_1__0/O[2]
|
|
net (fo=1, routed) 0.000 -0.233 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_scl/r0_s50[2]
|
|
SLICE_X79Y160 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_scl/r0_s5_reg[2]/D
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock mlkem_clk_clk_pll rise edge)
|
|
0.000 0.000 r
|
|
clock source latency -1.947 -1.947
|
|
propagated clock network latency
|
|
1.470 -0.477
|
|
clock pessimism 0.040 -0.437
|
|
SLICE_X79Y160 FDCE (Hold_fdce_C_D) 0.105 -0.332 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_scl/r0_s5_reg[2]
|
|
-------------------------------------------------------------------
|
|
required time 0.332
|
|
arrival time -0.233
|
|
-------------------------------------------------------------------
|
|
slack 0.099
|
|
|
|
Slack (MET) : 0.099ns (arrival time - required time)
|
|
Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_scl/p_s4_reg[2]/C
|
|
(rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns})
|
|
Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_scl/r0_s5_reg[2]/D
|
|
(rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns})
|
|
Path Group: mlkem_clk_clk_pll
|
|
Path Type: Hold (Min at Fast Process Corner)
|
|
Requirement: 0.000ns (mlkem_clk_clk_pll rise@0.000ns - mlkem_clk_clk_pll rise@0.000ns)
|
|
Data Path Delay: 0.470ns (logic 0.252ns (53.610%) route 0.218ns (46.390%))
|
|
Logic Levels: 2 (CARRY4=1 LUT2=1)
|
|
Clock Path Skew: 0.266ns (DCD - SCD - CPR)
|
|
Destination Clock Delay (DCD): -0.477ns
|
|
Source Clock Delay (SCD): -0.703ns
|
|
Clock Pessimism Removal (CPR): -0.040ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock mlkem_clk_clk_pll rise edge)
|
|
0.000 0.000 r
|
|
clock source latency -1.848 -1.848
|
|
propagated clock network latency
|
|
1.146 -0.703
|
|
SLICE_X85Y160 FDCE 0.000 -0.703 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_scl/p_s4_reg[2]/C
|
|
SLICE_X85Y160 FDCE (Prop_fdce_C_Q) 0.141 -0.562 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_scl/p_s4_reg[2]/Q
|
|
net (fo=2, routed) 0.218 -0.344 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_scl/p_s4[2]
|
|
SLICE_X79Y160 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_scl/r0_s5[3]_i_3__0/I0
|
|
SLICE_X79Y160 LUT2 (Prop_lut2_I0_O) 0.045 -0.299 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_scl/r0_s5[3]_i_3__0/O
|
|
net (fo=1, routed) 0.000 -0.299 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_scl/r0_s5[3]_i_3__0_n_0
|
|
SLICE_X79Y160 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_scl/r0_s5_reg[3]_i_1__0/S[2]
|
|
SLICE_X79Y160 CARRY4 (Prop_carry4_S[2]_O[2])
|
|
0.066 -0.233 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_scl/r0_s5_reg[3]_i_1__0/O[2]
|
|
net (fo=1, routed) 0.000 -0.233 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_scl/r0_s50[2]
|
|
SLICE_X79Y160 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_scl/r0_s5_reg[2]/D
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock mlkem_clk_clk_pll rise edge)
|
|
0.000 0.000 r
|
|
clock source latency -1.947 -1.947
|
|
propagated clock network latency
|
|
1.470 -0.477
|
|
clock pessimism 0.040 -0.437
|
|
SLICE_X79Y160 FDCE (Hold_fdce_C_D) 0.105 -0.332 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_scl/r0_s5_reg[2]
|
|
-------------------------------------------------------------------
|
|
required time 0.332
|
|
arrival time -0.233
|
|
-------------------------------------------------------------------
|
|
slack 0.099
|
|
|
|
Slack (MET) : 0.099ns (arrival time - required time)
|
|
Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_scl/p_s4_reg[2]/C
|
|
(rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns})
|
|
Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_scl/r0_s5_reg[2]/D
|
|
(rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns})
|
|
Path Group: mlkem_clk_clk_pll
|
|
Path Type: Hold (Min at Fast Process Corner)
|
|
Requirement: 0.000ns (mlkem_clk_clk_pll rise@0.000ns - mlkem_clk_clk_pll rise@0.000ns)
|
|
Data Path Delay: 0.470ns (logic 0.252ns (53.610%) route 0.218ns (46.390%))
|
|
Logic Levels: 2 (CARRY4=1 LUT2=1)
|
|
Clock Path Skew: 0.266ns (DCD - SCD - CPR)
|
|
Destination Clock Delay (DCD): -0.477ns
|
|
Source Clock Delay (SCD): -0.703ns
|
|
Clock Pessimism Removal (CPR): -0.040ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock mlkem_clk_clk_pll rise edge)
|
|
0.000 0.000 r
|
|
clock source latency -1.848 -1.848
|
|
propagated clock network latency
|
|
1.146 -0.703
|
|
SLICE_X85Y160 FDCE 0.000 -0.703 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_scl/p_s4_reg[2]/C
|
|
SLICE_X85Y160 FDCE (Prop_fdce_C_Q) 0.141 -0.562 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_scl/p_s4_reg[2]/Q
|
|
net (fo=2, routed) 0.218 -0.344 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_scl/p_s4[2]
|
|
SLICE_X79Y160 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_scl/r0_s5[3]_i_3__0/I0
|
|
SLICE_X79Y160 LUT2 (Prop_lut2_I0_O) 0.045 -0.299 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_scl/r0_s5[3]_i_3__0/O
|
|
net (fo=1, routed) 0.000 -0.299 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_scl/r0_s5[3]_i_3__0_n_0
|
|
SLICE_X79Y160 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_scl/r0_s5_reg[3]_i_1__0/S[2]
|
|
SLICE_X79Y160 CARRY4 (Prop_carry4_S[2]_O[2])
|
|
0.066 -0.233 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_scl/r0_s5_reg[3]_i_1__0/O[2]
|
|
net (fo=1, routed) 0.000 -0.233 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_scl/r0_s50[2]
|
|
SLICE_X79Y160 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_scl/r0_s5_reg[2]/D
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock mlkem_clk_clk_pll rise edge)
|
|
0.000 0.000 r
|
|
clock source latency -1.947 -1.947
|
|
propagated clock network latency
|
|
1.470 -0.477
|
|
clock pessimism 0.040 -0.437
|
|
SLICE_X79Y160 FDCE (Hold_fdce_C_D) 0.105 -0.332 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_scl/r0_s5_reg[2]
|
|
-------------------------------------------------------------------
|
|
required time 0.332
|
|
arrival time -0.233
|
|
-------------------------------------------------------------------
|
|
slack 0.099
|
|
|
|
Slack (MET) : 0.099ns (arrival time - required time)
|
|
Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_scl/p_s4_reg[2]/C
|
|
(rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns})
|
|
Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_scl/r0_s5_reg[2]/D
|
|
(rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns})
|
|
Path Group: mlkem_clk_clk_pll
|
|
Path Type: Hold (Min at Fast Process Corner)
|
|
Requirement: 0.000ns (mlkem_clk_clk_pll rise@0.000ns - mlkem_clk_clk_pll rise@0.000ns)
|
|
Data Path Delay: 0.470ns (logic 0.252ns (53.610%) route 0.218ns (46.390%))
|
|
Logic Levels: 2 (CARRY4=1 LUT2=1)
|
|
Clock Path Skew: 0.266ns (DCD - SCD - CPR)
|
|
Destination Clock Delay (DCD): -0.477ns
|
|
Source Clock Delay (SCD): -0.703ns
|
|
Clock Pessimism Removal (CPR): -0.040ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock mlkem_clk_clk_pll rise edge)
|
|
0.000 0.000 r
|
|
clock source latency -1.848 -1.848
|
|
propagated clock network latency
|
|
1.146 -0.703
|
|
SLICE_X85Y160 FDCE 0.000 -0.703 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_scl/p_s4_reg[2]/C
|
|
SLICE_X85Y160 FDCE (Prop_fdce_C_Q) 0.141 -0.562 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_scl/p_s4_reg[2]/Q
|
|
net (fo=2, routed) 0.218 -0.344 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_scl/p_s4[2]
|
|
SLICE_X79Y160 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_scl/r0_s5[3]_i_3__0/I0
|
|
SLICE_X79Y160 LUT2 (Prop_lut2_I0_O) 0.045 -0.299 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_scl/r0_s5[3]_i_3__0/O
|
|
net (fo=1, routed) 0.000 -0.299 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_scl/r0_s5[3]_i_3__0_n_0
|
|
SLICE_X79Y160 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_scl/r0_s5_reg[3]_i_1__0/S[2]
|
|
SLICE_X79Y160 CARRY4 (Prop_carry4_S[2]_O[2])
|
|
0.066 -0.233 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_scl/r0_s5_reg[3]_i_1__0/O[2]
|
|
net (fo=1, routed) 0.000 -0.233 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_scl/r0_s50[2]
|
|
SLICE_X79Y160 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_scl/r0_s5_reg[2]/D
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock mlkem_clk_clk_pll rise edge)
|
|
0.000 0.000 r
|
|
clock source latency -1.947 -1.947
|
|
propagated clock network latency
|
|
1.470 -0.477
|
|
clock pessimism 0.040 -0.437
|
|
SLICE_X79Y160 FDCE (Hold_fdce_C_D) 0.105 -0.332 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_scl/r0_s5_reg[2]
|
|
-------------------------------------------------------------------
|
|
required time 0.332
|
|
arrival time -0.233
|
|
-------------------------------------------------------------------
|
|
slack 0.099
|
|
|
|
Slack (MET) : 0.101ns (arrival time - required time)
|
|
Source: u_matmul_axi_slave/mult_inst[1].u_mult/prod_reg[51]/C
|
|
(rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Destination: u_matmul_axi_slave/mult_inst[1].u_mult/p_reg[51]/D
|
|
(rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Path Group: sys_clk
|
|
Path Type: Hold (Min at Fast Process Corner)
|
|
Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns)
|
|
Data Path Delay: 0.505ns (logic 0.164ns (32.465%) route 0.341ns (67.535%))
|
|
Logic Levels: 0
|
|
Clock Path Skew: 0.334ns (DCD - SCD - CPR)
|
|
Destination Clock Delay (DCD): -0.339ns
|
|
Source Clock Delay (SCD): -0.633ns
|
|
Clock Pessimism Removal (CPR): -0.040ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock sys_clk rise edge) 0.000 0.000 r
|
|
clock source latency -1.848 -1.848
|
|
propagated clock network latency
|
|
1.215 -0.633
|
|
SLICE_X14Y102 FDRE 0.000 -0.633 r u_matmul_axi_slave/mult_inst[1].u_mult/prod_reg[51]/C
|
|
SLICE_X14Y102 FDRE (Prop_fdre_C_Q) 0.164 -0.469 r u_matmul_axi_slave/mult_inst[1].u_mult/prod_reg[51]/Q
|
|
net (fo=1, routed) 0.341 -0.128 u_matmul_axi_slave/mult_inst[1].u_mult/prod[51]
|
|
SLICE_X15Y89 FDRE r u_matmul_axi_slave/mult_inst[1].u_mult/p_reg[51]/D
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock sys_clk rise edge) 0.000 0.000 r
|
|
clock source latency -1.947 -1.947
|
|
propagated clock network latency
|
|
1.608 -0.339
|
|
clock pessimism 0.040 -0.299
|
|
SLICE_X15Y89 FDRE (Hold_fdre_C_D) 0.070 -0.229 u_matmul_axi_slave/mult_inst[1].u_mult/p_reg[51]
|
|
-------------------------------------------------------------------
|
|
required time 0.229
|
|
arrival time -0.128
|
|
-------------------------------------------------------------------
|
|
slack 0.101
|
|
|
|
Slack (MET) : 0.101ns (arrival time - required time)
|
|
Source: u_matmul_axi_slave/mult_inst[1].u_mult/prod_reg[51]/C
|
|
(rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Destination: u_matmul_axi_slave/mult_inst[1].u_mult/p_reg[51]/D
|
|
(rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Path Group: sys_clk
|
|
Path Type: Hold (Min at Fast Process Corner)
|
|
Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns)
|
|
Data Path Delay: 0.505ns (logic 0.164ns (32.465%) route 0.341ns (67.535%))
|
|
Logic Levels: 0
|
|
Clock Path Skew: 0.334ns (DCD - SCD - CPR)
|
|
Destination Clock Delay (DCD): -0.339ns
|
|
Source Clock Delay (SCD): -0.633ns
|
|
Clock Pessimism Removal (CPR): -0.040ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock sys_clk rise edge) 0.000 0.000 r
|
|
clock source latency -1.848 -1.848
|
|
propagated clock network latency
|
|
1.215 -0.633
|
|
SLICE_X14Y102 FDRE 0.000 -0.633 r u_matmul_axi_slave/mult_inst[1].u_mult/prod_reg[51]/C
|
|
SLICE_X14Y102 FDRE (Prop_fdre_C_Q) 0.164 -0.469 f u_matmul_axi_slave/mult_inst[1].u_mult/prod_reg[51]/Q
|
|
net (fo=1, routed) 0.341 -0.128 u_matmul_axi_slave/mult_inst[1].u_mult/prod[51]
|
|
SLICE_X15Y89 FDRE f u_matmul_axi_slave/mult_inst[1].u_mult/p_reg[51]/D
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock sys_clk rise edge) 0.000 0.000 r
|
|
clock source latency -1.947 -1.947
|
|
propagated clock network latency
|
|
1.608 -0.339
|
|
clock pessimism 0.040 -0.299
|
|
SLICE_X15Y89 FDRE (Hold_fdre_C_D) 0.070 -0.229 u_matmul_axi_slave/mult_inst[1].u_mult/p_reg[51]
|
|
-------------------------------------------------------------------
|
|
required time 0.229
|
|
arrival time -0.128
|
|
-------------------------------------------------------------------
|
|
slack 0.101
|
|
|
|
Slack (MET) : 0.101ns (arrival time - required time)
|
|
Source: u_matmul_axi_slave/mult_inst[1].u_mult/prod_reg[59]/C
|
|
(rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Destination: u_matmul_axi_slave/mult_inst[1].u_mult/p_reg[59]/D
|
|
(rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Path Group: sys_clk
|
|
Path Type: Hold (Min at Fast Process Corner)
|
|
Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns)
|
|
Data Path Delay: 0.509ns (logic 0.164ns (32.198%) route 0.345ns (67.802%))
|
|
Logic Levels: 0
|
|
Clock Path Skew: 0.336ns (DCD - SCD - CPR)
|
|
Destination Clock Delay (DCD): -0.338ns
|
|
Source Clock Delay (SCD): -0.634ns
|
|
Clock Pessimism Removal (CPR): -0.040ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock sys_clk rise edge) 0.000 0.000 r
|
|
clock source latency -1.848 -1.848
|
|
propagated clock network latency
|
|
1.214 -0.634
|
|
SLICE_X14Y104 FDRE 0.000 -0.634 r u_matmul_axi_slave/mult_inst[1].u_mult/prod_reg[59]/C
|
|
SLICE_X14Y104 FDRE (Prop_fdre_C_Q) 0.164 -0.470 r u_matmul_axi_slave/mult_inst[1].u_mult/prod_reg[59]/Q
|
|
net (fo=1, routed) 0.345 -0.125 u_matmul_axi_slave/mult_inst[1].u_mult/prod[59]
|
|
SLICE_X17Y92 FDRE r u_matmul_axi_slave/mult_inst[1].u_mult/p_reg[59]/D
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock sys_clk rise edge) 0.000 0.000 r
|
|
clock source latency -1.947 -1.947
|
|
propagated clock network latency
|
|
1.609 -0.338
|
|
clock pessimism 0.040 -0.298
|
|
SLICE_X17Y92 FDRE (Hold_fdre_C_D) 0.072 -0.226 u_matmul_axi_slave/mult_inst[1].u_mult/p_reg[59]
|
|
-------------------------------------------------------------------
|
|
required time 0.226
|
|
arrival time -0.125
|
|
-------------------------------------------------------------------
|
|
slack 0.101
|
|
|
|
Slack (MET) : 0.101ns (arrival time - required time)
|
|
Source: u_matmul_axi_slave/mult_inst[1].u_mult/prod_reg[59]/C
|
|
(rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Destination: u_matmul_axi_slave/mult_inst[1].u_mult/p_reg[59]/D
|
|
(rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Path Group: sys_clk
|
|
Path Type: Hold (Min at Fast Process Corner)
|
|
Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns)
|
|
Data Path Delay: 0.509ns (logic 0.164ns (32.198%) route 0.345ns (67.802%))
|
|
Logic Levels: 0
|
|
Clock Path Skew: 0.336ns (DCD - SCD - CPR)
|
|
Destination Clock Delay (DCD): -0.338ns
|
|
Source Clock Delay (SCD): -0.634ns
|
|
Clock Pessimism Removal (CPR): -0.040ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock sys_clk rise edge) 0.000 0.000 r
|
|
clock source latency -1.848 -1.848
|
|
propagated clock network latency
|
|
1.214 -0.634
|
|
SLICE_X14Y104 FDRE 0.000 -0.634 r u_matmul_axi_slave/mult_inst[1].u_mult/prod_reg[59]/C
|
|
SLICE_X14Y104 FDRE (Prop_fdre_C_Q) 0.164 -0.470 f u_matmul_axi_slave/mult_inst[1].u_mult/prod_reg[59]/Q
|
|
net (fo=1, routed) 0.345 -0.125 u_matmul_axi_slave/mult_inst[1].u_mult/prod[59]
|
|
SLICE_X17Y92 FDRE f u_matmul_axi_slave/mult_inst[1].u_mult/p_reg[59]/D
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock sys_clk rise edge) 0.000 0.000 r
|
|
clock source latency -1.947 -1.947
|
|
propagated clock network latency
|
|
1.609 -0.338
|
|
clock pessimism 0.040 -0.298
|
|
SLICE_X17Y92 FDRE (Hold_fdre_C_D) 0.072 -0.226 u_matmul_axi_slave/mult_inst[1].u_mult/p_reg[59]
|
|
-------------------------------------------------------------------
|
|
required time 0.226
|
|
arrival time -0.125
|
|
-------------------------------------------------------------------
|
|
slack 0.101
|
|
|
|
Slack (MET) : 0.103ns (arrival time - required time)
|
|
Source: u_cpu/axi_bridge/awaddr_reg[3]/C
|
|
(rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns})
|
|
Destination: u_Axi_CDC/awFifo/ram_reg_0_3_0_5/RAMB_D1/I
|
|
(rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns})
|
|
Path Group: cpu_clk
|
|
Path Type: Hold (Min at Fast Process Corner)
|
|
Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns)
|
|
Data Path Delay: 0.422ns (logic 0.141ns (33.450%) route 0.281ns (66.550%))
|
|
Logic Levels: 0
|
|
Clock Path Skew: 0.194ns (DCD - SCD - CPR)
|
|
Destination Clock Delay (DCD): -0.339ns
|
|
Source Clock Delay (SCD): -0.497ns
|
|
Clock Pessimism Removal (CPR): -0.037ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock cpu_clk rise edge) 0.000 0.000 r
|
|
clock source latency -1.848 -1.848
|
|
propagated clock network latency
|
|
1.352 -0.497
|
|
SLICE_X21Y48 FDRE 0.000 -0.497 r u_cpu/axi_bridge/awaddr_reg[3]/C
|
|
SLICE_X21Y48 FDRE (Prop_fdre_C_Q) 0.141 -0.356 r u_cpu/axi_bridge/awaddr_reg[3]/Q
|
|
net (fo=1, routed) 0.281 -0.075 u_Axi_CDC/awFifo/ram_reg_0_3_0_5/DIB1
|
|
SLICE_X20Y58 RAMD32 r u_Axi_CDC/awFifo/ram_reg_0_3_0_5/RAMB_D1/I
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock cpu_clk rise edge) 0.000 0.000 r
|
|
clock source latency -1.947 -1.947
|
|
propagated clock network latency
|
|
1.608 -0.339
|
|
clock pessimism 0.037 -0.302
|
|
SLICE_X20Y58 RAMD32 (Hold_ramd32_CLK_I)
|
|
0.124 -0.178 u_Axi_CDC/awFifo/ram_reg_0_3_0_5/RAMB_D1
|
|
-------------------------------------------------------------------
|
|
required time 0.178
|
|
arrival time -0.075
|
|
-------------------------------------------------------------------
|
|
slack 0.103
|
|
|
|
Slack (MET) : 0.103ns (arrival time - required time)
|
|
Source: u_cpu/axi_bridge/awaddr_reg[3]/C
|
|
(rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns})
|
|
Destination: u_Axi_CDC/awFifo/ram_reg_0_3_0_5/RAMB_D1/I
|
|
(rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns})
|
|
Path Group: cpu_clk
|
|
Path Type: Hold (Min at Fast Process Corner)
|
|
Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns)
|
|
Data Path Delay: 0.422ns (logic 0.141ns (33.450%) route 0.281ns (66.550%))
|
|
Logic Levels: 0
|
|
Clock Path Skew: 0.194ns (DCD - SCD - CPR)
|
|
Destination Clock Delay (DCD): -0.339ns
|
|
Source Clock Delay (SCD): -0.497ns
|
|
Clock Pessimism Removal (CPR): -0.037ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock cpu_clk rise edge) 0.000 0.000 r
|
|
clock source latency -1.848 -1.848
|
|
propagated clock network latency
|
|
1.352 -0.497
|
|
SLICE_X21Y48 FDRE 0.000 -0.497 r u_cpu/axi_bridge/awaddr_reg[3]/C
|
|
SLICE_X21Y48 FDRE (Prop_fdre_C_Q) 0.141 -0.356 f u_cpu/axi_bridge/awaddr_reg[3]/Q
|
|
net (fo=1, routed) 0.281 -0.075 u_Axi_CDC/awFifo/ram_reg_0_3_0_5/DIB1
|
|
SLICE_X20Y58 RAMD32 f u_Axi_CDC/awFifo/ram_reg_0_3_0_5/RAMB_D1/I
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock cpu_clk rise edge) 0.000 0.000 r
|
|
clock source latency -1.947 -1.947
|
|
propagated clock network latency
|
|
1.608 -0.339
|
|
clock pessimism 0.037 -0.302
|
|
SLICE_X20Y58 RAMD32 (Hold_ramd32_CLK_I)
|
|
0.124 -0.178 u_Axi_CDC/awFifo/ram_reg_0_3_0_5/RAMB_D1
|
|
-------------------------------------------------------------------
|
|
required time 0.178
|
|
arrival time -0.075
|
|
-------------------------------------------------------------------
|
|
slack 0.103
|
|
|
|
Slack (MET) : 0.103ns (arrival time - required time)
|
|
Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_36_39/RAMA_D1/CLK
|
|
(rising edge-triggered cell RAMD32 clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns})
|
|
Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[37]/D
|
|
(rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Path Group: sys_clk
|
|
Path Type: Hold (Min at Fast Process Corner)
|
|
Requirement: 0.000ns (sys_clk rise@0.000ns - mlkem_clk_clk_pll rise@0.000ns)
|
|
Data Path Delay: 0.697ns (logic 0.478ns (68.593%) route 0.219ns (31.407%))
|
|
Logic Levels: 0
|
|
Clock Path Skew: 0.327ns (DCD - SCD - CPR)
|
|
Destination Clock Delay (DCD): -0.349ns
|
|
Source Clock Delay (SCD): -0.577ns
|
|
Clock Pessimism Removal (CPR): -0.099ns
|
|
Clock Uncertainty: 0.197ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Discrete Jitter (DJ): 0.136ns
|
|
Phase Error (PE): 0.120ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock mlkem_clk_clk_pll rise edge)
|
|
0.000 0.000 r
|
|
clock source latency -1.848 -1.848
|
|
propagated clock network latency
|
|
1.271 -0.577
|
|
SLICE_X18Y78 RAMD32 0.000 -0.577 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_36_39/RAMA_D1/CLK
|
|
SLICE_X18Y78 RAMD32 (Prop_ramd32_CLK_O)
|
|
0.478 -0.099 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_36_39/RAMA_D1/O
|
|
net (fo=1, routed) 0.219 0.119 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port10__3[37]
|
|
SLICE_X15Y78 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[37]/D
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock sys_clk rise edge) 0.000 0.000 r
|
|
clock source latency -1.947 -1.947
|
|
propagated clock network latency
|
|
1.598 -0.349
|
|
clock pessimism 0.099 -0.250
|
|
clock uncertainty 0.197 -0.054
|
|
SLICE_X15Y78 FDRE (Hold_fdre_C_D) 0.070 0.016 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[37]
|
|
-------------------------------------------------------------------
|
|
required time -0.016
|
|
arrival time 0.119
|
|
-------------------------------------------------------------------
|
|
slack 0.103
|
|
|
|
Slack (MET) : 0.103ns (arrival time - required time)
|
|
Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_36_39/RAMA_D1/CLK
|
|
(rising edge-triggered cell RAMD32 clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns})
|
|
Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[37]/D
|
|
(rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Path Group: sys_clk
|
|
Path Type: Hold (Min at Fast Process Corner)
|
|
Requirement: 0.000ns (sys_clk rise@0.000ns - mlkem_clk_clk_pll rise@0.000ns)
|
|
Data Path Delay: 0.697ns (logic 0.478ns (68.593%) route 0.219ns (31.407%))
|
|
Logic Levels: 0
|
|
Clock Path Skew: 0.327ns (DCD - SCD - CPR)
|
|
Destination Clock Delay (DCD): -0.349ns
|
|
Source Clock Delay (SCD): -0.577ns
|
|
Clock Pessimism Removal (CPR): -0.099ns
|
|
Clock Uncertainty: 0.197ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Discrete Jitter (DJ): 0.136ns
|
|
Phase Error (PE): 0.120ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock mlkem_clk_clk_pll rise edge)
|
|
0.000 0.000 r
|
|
clock source latency -1.848 -1.848
|
|
propagated clock network latency
|
|
1.271 -0.577
|
|
SLICE_X18Y78 RAMD32 0.000 -0.577 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_36_39/RAMA_D1/CLK
|
|
SLICE_X18Y78 RAMD32 (Prop_ramd32_CLK_O)
|
|
0.478 -0.099 f u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_36_39/RAMA_D1/O
|
|
net (fo=1, routed) 0.219 0.119 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port10__3[37]
|
|
SLICE_X15Y78 FDRE f u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[37]/D
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock sys_clk rise edge) 0.000 0.000 r
|
|
clock source latency -1.947 -1.947
|
|
propagated clock network latency
|
|
1.598 -0.349
|
|
clock pessimism 0.099 -0.250
|
|
clock uncertainty 0.197 -0.054
|
|
SLICE_X15Y78 FDRE (Hold_fdre_C_D) 0.070 0.016 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[37]
|
|
-------------------------------------------------------------------
|
|
required time -0.016
|
|
arrival time 0.119
|
|
-------------------------------------------------------------------
|
|
slack 0.103
|
|
|
|
Slack (MET) : 0.105ns (arrival time - required time)
|
|
Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[5]/C
|
|
(rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns})
|
|
Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r1_s6_reg[5]/D
|
|
(rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns})
|
|
Path Group: mlkem_clk_clk_pll
|
|
Path Type: Hold (Min at Fast Process Corner)
|
|
Requirement: 0.000ns (mlkem_clk_clk_pll rise@0.000ns - mlkem_clk_clk_pll rise@0.000ns)
|
|
Data Path Delay: 0.502ns (logic 0.185ns (36.874%) route 0.317ns (63.126%))
|
|
Logic Levels: 1 (LUT3=1)
|
|
Clock Path Skew: 0.266ns (DCD - SCD - CPR)
|
|
Destination Clock Delay (DCD): -0.476ns
|
|
Source Clock Delay (SCD): -0.702ns
|
|
Clock Pessimism Removal (CPR): -0.040ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock mlkem_clk_clk_pll rise edge)
|
|
0.000 0.000 r
|
|
clock source latency -1.848 -1.848
|
|
propagated clock network latency
|
|
1.147 -0.702
|
|
SLICE_X83Y155 FDCE 0.000 -0.702 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[5]/C
|
|
SLICE_X83Y155 FDCE (Prop_fdce_C_Q) 0.141 -0.561 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[5]/Q
|
|
net (fo=4, routed) 0.317 -0.244 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5[5]
|
|
SLICE_X84Y155 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r1_s6[5]_i_1/I0
|
|
SLICE_X84Y155 LUT3 (Prop_lut3_I0_O) 0.044 -0.200 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r1_s6[5]_i_1/O
|
|
net (fo=1, routed) 0.000 -0.200 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r1_s6[5]_i_1_n_0
|
|
SLICE_X84Y155 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r1_s6_reg[5]/D
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock mlkem_clk_clk_pll rise edge)
|
|
0.000 0.000 r
|
|
clock source latency -1.947 -1.947
|
|
propagated clock network latency
|
|
1.471 -0.476
|
|
clock pessimism 0.040 -0.436
|
|
SLICE_X84Y155 FDCE (Hold_fdce_C_D) 0.131 -0.305 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r1_s6_reg[5]
|
|
-------------------------------------------------------------------
|
|
required time 0.305
|
|
arrival time -0.200
|
|
-------------------------------------------------------------------
|
|
slack 0.105
|
|
|
|
Slack (MET) : 0.105ns (arrival time - required time)
|
|
Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[5]/C
|
|
(rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns})
|
|
Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r1_s6_reg[5]/D
|
|
(rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns})
|
|
Path Group: mlkem_clk_clk_pll
|
|
Path Type: Hold (Min at Fast Process Corner)
|
|
Requirement: 0.000ns (mlkem_clk_clk_pll rise@0.000ns - mlkem_clk_clk_pll rise@0.000ns)
|
|
Data Path Delay: 0.502ns (logic 0.185ns (36.874%) route 0.317ns (63.126%))
|
|
Logic Levels: 1 (LUT3=1)
|
|
Clock Path Skew: 0.266ns (DCD - SCD - CPR)
|
|
Destination Clock Delay (DCD): -0.476ns
|
|
Source Clock Delay (SCD): -0.702ns
|
|
Clock Pessimism Removal (CPR): -0.040ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock mlkem_clk_clk_pll rise edge)
|
|
0.000 0.000 r
|
|
clock source latency -1.848 -1.848
|
|
propagated clock network latency
|
|
1.147 -0.702
|
|
SLICE_X83Y155 FDCE 0.000 -0.702 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[5]/C
|
|
SLICE_X83Y155 FDCE (Prop_fdce_C_Q) 0.141 -0.561 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[5]/Q
|
|
net (fo=4, routed) 0.317 -0.244 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5[5]
|
|
SLICE_X84Y155 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r1_s6[5]_i_1/I0
|
|
SLICE_X84Y155 LUT3 (Prop_lut3_I0_O) 0.044 -0.200 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r1_s6[5]_i_1/O
|
|
net (fo=1, routed) 0.000 -0.200 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r1_s6[5]_i_1_n_0
|
|
SLICE_X84Y155 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r1_s6_reg[5]/D
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock mlkem_clk_clk_pll rise edge)
|
|
0.000 0.000 r
|
|
clock source latency -1.947 -1.947
|
|
propagated clock network latency
|
|
1.471 -0.476
|
|
clock pessimism 0.040 -0.436
|
|
SLICE_X84Y155 FDCE (Hold_fdce_C_D) 0.131 -0.305 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r1_s6_reg[5]
|
|
-------------------------------------------------------------------
|
|
required time 0.305
|
|
arrival time -0.200
|
|
-------------------------------------------------------------------
|
|
slack 0.105
|
|
|
|
Slack (MET) : 0.106ns (arrival time - required time)
|
|
Source: u_cpu/axi_bridge/wdata_reg[1]/C
|
|
(rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns})
|
|
Destination: u_Axi_CDC/wFifo/ram_reg_0_7_0_5/RAMA_D1/I
|
|
(rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns})
|
|
Path Group: cpu_clk
|
|
Path Type: Hold (Min at Fast Process Corner)
|
|
Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns)
|
|
Data Path Delay: 0.242ns (logic 0.141ns (58.263%) route 0.101ns (41.737%))
|
|
Logic Levels: 0
|
|
Clock Path Skew: 0.016ns (DCD - SCD - CPR)
|
|
Destination Clock Delay (DCD): -0.232ns
|
|
Source Clock Delay (SCD): -0.468ns
|
|
Clock Pessimism Removal (CPR): 0.220ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock cpu_clk rise edge) 0.000 0.000 r
|
|
clock source latency -1.848 -1.848
|
|
propagated clock network latency
|
|
1.381 -0.468
|
|
SLICE_X5Y45 FDRE 0.000 -0.468 r u_cpu/axi_bridge/wdata_reg[1]/C
|
|
SLICE_X5Y45 FDRE (Prop_fdre_C_Q) 0.141 -0.327 r u_cpu/axi_bridge/wdata_reg[1]/Q
|
|
net (fo=1, routed) 0.101 -0.226 u_Axi_CDC/wFifo/ram_reg_0_7_0_5/DIA1
|
|
SLICE_X6Y45 RAMD32 r u_Axi_CDC/wFifo/ram_reg_0_7_0_5/RAMA_D1/I
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock cpu_clk rise edge) 0.000 0.000 r
|
|
clock source latency -1.947 -1.947
|
|
propagated clock network latency
|
|
1.715 -0.232
|
|
clock pessimism -0.220 -0.452
|
|
SLICE_X6Y45 RAMD32 (Hold_ramd32_CLK_I)
|
|
0.120 -0.332 u_Axi_CDC/wFifo/ram_reg_0_7_0_5/RAMA_D1
|
|
-------------------------------------------------------------------
|
|
required time 0.332
|
|
arrival time -0.226
|
|
-------------------------------------------------------------------
|
|
slack 0.106
|
|
|
|
Slack (MET) : 0.106ns (arrival time - required time)
|
|
Source: u_cpu/axi_bridge/wdata_reg[1]/C
|
|
(rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns})
|
|
Destination: u_Axi_CDC/wFifo/ram_reg_0_7_0_5/RAMA_D1/I
|
|
(rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns})
|
|
Path Group: cpu_clk
|
|
Path Type: Hold (Min at Fast Process Corner)
|
|
Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns)
|
|
Data Path Delay: 0.242ns (logic 0.141ns (58.263%) route 0.101ns (41.737%))
|
|
Logic Levels: 0
|
|
Clock Path Skew: 0.016ns (DCD - SCD - CPR)
|
|
Destination Clock Delay (DCD): -0.232ns
|
|
Source Clock Delay (SCD): -0.468ns
|
|
Clock Pessimism Removal (CPR): 0.220ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock cpu_clk rise edge) 0.000 0.000 r
|
|
clock source latency -1.848 -1.848
|
|
propagated clock network latency
|
|
1.381 -0.468
|
|
SLICE_X5Y45 FDRE 0.000 -0.468 r u_cpu/axi_bridge/wdata_reg[1]/C
|
|
SLICE_X5Y45 FDRE (Prop_fdre_C_Q) 0.141 -0.327 f u_cpu/axi_bridge/wdata_reg[1]/Q
|
|
net (fo=1, routed) 0.101 -0.226 u_Axi_CDC/wFifo/ram_reg_0_7_0_5/DIA1
|
|
SLICE_X6Y45 RAMD32 f u_Axi_CDC/wFifo/ram_reg_0_7_0_5/RAMA_D1/I
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock cpu_clk rise edge) 0.000 0.000 r
|
|
clock source latency -1.947 -1.947
|
|
propagated clock network latency
|
|
1.715 -0.232
|
|
clock pessimism -0.220 -0.452
|
|
SLICE_X6Y45 RAMD32 (Hold_ramd32_CLK_I)
|
|
0.120 -0.332 u_Axi_CDC/wFifo/ram_reg_0_7_0_5/RAMA_D1
|
|
-------------------------------------------------------------------
|
|
required time 0.332
|
|
arrival time -0.226
|
|
-------------------------------------------------------------------
|
|
slack 0.106
|
|
|
|
Slack (MET) : 0.106ns (arrival time - required time)
|
|
Source: u_matmul_axi_slave/mult_inst[1].u_mult/prod_reg[57]/C
|
|
(rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Destination: u_matmul_axi_slave/mult_inst[1].u_mult/p_reg[57]/D
|
|
(rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Path Group: sys_clk
|
|
Path Type: Hold (Min at Fast Process Corner)
|
|
Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns)
|
|
Data Path Delay: 0.507ns (logic 0.164ns (32.320%) route 0.343ns (67.680%))
|
|
Logic Levels: 0
|
|
Clock Path Skew: 0.335ns (DCD - SCD - CPR)
|
|
Destination Clock Delay (DCD): -0.339ns
|
|
Source Clock Delay (SCD): -0.634ns
|
|
Clock Pessimism Removal (CPR): -0.040ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock sys_clk rise edge) 0.000 0.000 r
|
|
clock source latency -1.848 -1.848
|
|
propagated clock network latency
|
|
1.214 -0.634
|
|
SLICE_X14Y104 FDRE 0.000 -0.634 r u_matmul_axi_slave/mult_inst[1].u_mult/prod_reg[57]/C
|
|
SLICE_X14Y104 FDRE (Prop_fdre_C_Q) 0.164 -0.470 r u_matmul_axi_slave/mult_inst[1].u_mult/prod_reg[57]/Q
|
|
net (fo=1, routed) 0.343 -0.127 u_matmul_axi_slave/mult_inst[1].u_mult/prod[57]
|
|
SLICE_X15Y89 FDRE r u_matmul_axi_slave/mult_inst[1].u_mult/p_reg[57]/D
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock sys_clk rise edge) 0.000 0.000 r
|
|
clock source latency -1.947 -1.947
|
|
propagated clock network latency
|
|
1.608 -0.339
|
|
clock pessimism 0.040 -0.299
|
|
SLICE_X15Y89 FDRE (Hold_fdre_C_D) 0.066 -0.233 u_matmul_axi_slave/mult_inst[1].u_mult/p_reg[57]
|
|
-------------------------------------------------------------------
|
|
required time 0.233
|
|
arrival time -0.127
|
|
-------------------------------------------------------------------
|
|
slack 0.106
|
|
|
|
Slack (MET) : 0.106ns (arrival time - required time)
|
|
Source: u_matmul_axi_slave/mult_inst[1].u_mult/prod_reg[57]/C
|
|
(rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Destination: u_matmul_axi_slave/mult_inst[1].u_mult/p_reg[57]/D
|
|
(rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Path Group: sys_clk
|
|
Path Type: Hold (Min at Fast Process Corner)
|
|
Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns)
|
|
Data Path Delay: 0.507ns (logic 0.164ns (32.320%) route 0.343ns (67.680%))
|
|
Logic Levels: 0
|
|
Clock Path Skew: 0.335ns (DCD - SCD - CPR)
|
|
Destination Clock Delay (DCD): -0.339ns
|
|
Source Clock Delay (SCD): -0.634ns
|
|
Clock Pessimism Removal (CPR): -0.040ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock sys_clk rise edge) 0.000 0.000 r
|
|
clock source latency -1.848 -1.848
|
|
propagated clock network latency
|
|
1.214 -0.634
|
|
SLICE_X14Y104 FDRE 0.000 -0.634 r u_matmul_axi_slave/mult_inst[1].u_mult/prod_reg[57]/C
|
|
SLICE_X14Y104 FDRE (Prop_fdre_C_Q) 0.164 -0.470 f u_matmul_axi_slave/mult_inst[1].u_mult/prod_reg[57]/Q
|
|
net (fo=1, routed) 0.343 -0.127 u_matmul_axi_slave/mult_inst[1].u_mult/prod[57]
|
|
SLICE_X15Y89 FDRE f u_matmul_axi_slave/mult_inst[1].u_mult/p_reg[57]/D
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock sys_clk rise edge) 0.000 0.000 r
|
|
clock source latency -1.947 -1.947
|
|
propagated clock network latency
|
|
1.608 -0.339
|
|
clock pessimism 0.040 -0.299
|
|
SLICE_X15Y89 FDRE (Hold_fdre_C_D) 0.066 -0.233 u_matmul_axi_slave/mult_inst[1].u_mult/p_reg[57]
|
|
-------------------------------------------------------------------
|
|
required time 0.233
|
|
arrival time -0.127
|
|
-------------------------------------------------------------------
|
|
slack 0.106
|
|
|
|
Slack (MET) : 0.107ns (arrival time - required time)
|
|
Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/qprod_s4_reg[10]/C
|
|
(rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns})
|
|
Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[10]/D
|
|
(rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns})
|
|
Path Group: mlkem_clk_clk_pll
|
|
Path Type: Hold (Min at Fast Process Corner)
|
|
Requirement: 0.000ns (mlkem_clk_clk_pll rise@0.000ns - mlkem_clk_clk_pll rise@0.000ns)
|
|
Data Path Delay: 0.475ns (logic 0.275ns (57.843%) route 0.200ns (42.157%))
|
|
Logic Levels: 2 (CARRY4=1 LUT2=1)
|
|
Clock Path Skew: 0.264ns (DCD - SCD - CPR)
|
|
Destination Clock Delay (DCD): -0.477ns
|
|
Source Clock Delay (SCD): -0.701ns
|
|
Clock Pessimism Removal (CPR): -0.040ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock mlkem_clk_clk_pll rise edge)
|
|
0.000 0.000 r
|
|
clock source latency -1.848 -1.848
|
|
propagated clock network latency
|
|
1.148 -0.701
|
|
SLICE_X84Y156 FDCE 0.000 -0.701 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/qprod_s4_reg[10]/C
|
|
SLICE_X84Y156 FDCE (Prop_fdce_C_Q) 0.164 -0.537 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/qprod_s4_reg[10]/Q
|
|
net (fo=1, routed) 0.200 -0.336 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/qprod_s4[10]
|
|
SLICE_X83Y156 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5[11]_i_3/I1
|
|
SLICE_X83Y156 LUT2 (Prop_lut2_I1_O) 0.045 -0.291 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5[11]_i_3/O
|
|
net (fo=1, routed) 0.000 -0.291 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5[11]_i_3_n_0
|
|
SLICE_X83Y156 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[11]_i_1/S[2]
|
|
SLICE_X83Y156 CARRY4 (Prop_carry4_S[2]_O[2])
|
|
0.066 -0.225 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[11]_i_1/O[2]
|
|
net (fo=1, routed) 0.000 -0.225 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s50[10]
|
|
SLICE_X83Y156 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[10]/D
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock mlkem_clk_clk_pll rise edge)
|
|
0.000 0.000 r
|
|
clock source latency -1.947 -1.947
|
|
propagated clock network latency
|
|
1.470 -0.477
|
|
clock pessimism 0.040 -0.437
|
|
SLICE_X83Y156 FDCE (Hold_fdce_C_D) 0.105 -0.332 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[10]
|
|
-------------------------------------------------------------------
|
|
required time 0.332
|
|
arrival time -0.225
|
|
-------------------------------------------------------------------
|
|
slack 0.107
|
|
|
|
Slack (MET) : 0.107ns (arrival time - required time)
|
|
Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/qprod_s4_reg[10]/C
|
|
(rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns})
|
|
Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[10]/D
|
|
(rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns})
|
|
Path Group: mlkem_clk_clk_pll
|
|
Path Type: Hold (Min at Fast Process Corner)
|
|
Requirement: 0.000ns (mlkem_clk_clk_pll rise@0.000ns - mlkem_clk_clk_pll rise@0.000ns)
|
|
Data Path Delay: 0.475ns (logic 0.275ns (57.843%) route 0.200ns (42.157%))
|
|
Logic Levels: 2 (CARRY4=1 LUT2=1)
|
|
Clock Path Skew: 0.264ns (DCD - SCD - CPR)
|
|
Destination Clock Delay (DCD): -0.477ns
|
|
Source Clock Delay (SCD): -0.701ns
|
|
Clock Pessimism Removal (CPR): -0.040ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock mlkem_clk_clk_pll rise edge)
|
|
0.000 0.000 r
|
|
clock source latency -1.848 -1.848
|
|
propagated clock network latency
|
|
1.148 -0.701
|
|
SLICE_X84Y156 FDCE 0.000 -0.701 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/qprod_s4_reg[10]/C
|
|
SLICE_X84Y156 FDCE (Prop_fdce_C_Q) 0.164 -0.537 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/qprod_s4_reg[10]/Q
|
|
net (fo=1, routed) 0.200 -0.336 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/qprod_s4[10]
|
|
SLICE_X83Y156 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5[11]_i_3/I1
|
|
SLICE_X83Y156 LUT2 (Prop_lut2_I1_O) 0.045 -0.291 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5[11]_i_3/O
|
|
net (fo=1, routed) 0.000 -0.291 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5[11]_i_3_n_0
|
|
SLICE_X83Y156 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[11]_i_1/S[2]
|
|
SLICE_X83Y156 CARRY4 (Prop_carry4_S[2]_O[2])
|
|
0.066 -0.225 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[11]_i_1/O[2]
|
|
net (fo=1, routed) 0.000 -0.225 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s50[10]
|
|
SLICE_X83Y156 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[10]/D
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock mlkem_clk_clk_pll rise edge)
|
|
0.000 0.000 r
|
|
clock source latency -1.947 -1.947
|
|
propagated clock network latency
|
|
1.470 -0.477
|
|
clock pessimism 0.040 -0.437
|
|
SLICE_X83Y156 FDCE (Hold_fdce_C_D) 0.105 -0.332 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[10]
|
|
-------------------------------------------------------------------
|
|
required time 0.332
|
|
arrival time -0.225
|
|
-------------------------------------------------------------------
|
|
slack 0.107
|
|
|
|
Slack (MET) : 0.107ns (arrival time - required time)
|
|
Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/qprod_s4_reg[10]/C
|
|
(rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns})
|
|
Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[10]/D
|
|
(rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns})
|
|
Path Group: mlkem_clk_clk_pll
|
|
Path Type: Hold (Min at Fast Process Corner)
|
|
Requirement: 0.000ns (mlkem_clk_clk_pll rise@0.000ns - mlkem_clk_clk_pll rise@0.000ns)
|
|
Data Path Delay: 0.475ns (logic 0.275ns (57.843%) route 0.200ns (42.157%))
|
|
Logic Levels: 2 (CARRY4=1 LUT2=1)
|
|
Clock Path Skew: 0.264ns (DCD - SCD - CPR)
|
|
Destination Clock Delay (DCD): -0.477ns
|
|
Source Clock Delay (SCD): -0.701ns
|
|
Clock Pessimism Removal (CPR): -0.040ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock mlkem_clk_clk_pll rise edge)
|
|
0.000 0.000 r
|
|
clock source latency -1.848 -1.848
|
|
propagated clock network latency
|
|
1.148 -0.701
|
|
SLICE_X84Y156 FDCE 0.000 -0.701 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/qprod_s4_reg[10]/C
|
|
SLICE_X84Y156 FDCE (Prop_fdce_C_Q) 0.164 -0.537 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/qprod_s4_reg[10]/Q
|
|
net (fo=1, routed) 0.200 -0.336 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/qprod_s4[10]
|
|
SLICE_X83Y156 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5[11]_i_3/I1
|
|
SLICE_X83Y156 LUT2 (Prop_lut2_I1_O) 0.045 -0.291 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5[11]_i_3/O
|
|
net (fo=1, routed) 0.000 -0.291 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5[11]_i_3_n_0
|
|
SLICE_X83Y156 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[11]_i_1/S[2]
|
|
SLICE_X83Y156 CARRY4 (Prop_carry4_S[2]_O[2])
|
|
0.066 -0.225 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[11]_i_1/O[2]
|
|
net (fo=1, routed) 0.000 -0.225 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s50[10]
|
|
SLICE_X83Y156 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[10]/D
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock mlkem_clk_clk_pll rise edge)
|
|
0.000 0.000 r
|
|
clock source latency -1.947 -1.947
|
|
propagated clock network latency
|
|
1.470 -0.477
|
|
clock pessimism 0.040 -0.437
|
|
SLICE_X83Y156 FDCE (Hold_fdce_C_D) 0.105 -0.332 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[10]
|
|
-------------------------------------------------------------------
|
|
required time 0.332
|
|
arrival time -0.225
|
|
-------------------------------------------------------------------
|
|
slack 0.107
|
|
|
|
Slack (MET) : 0.107ns (arrival time - required time)
|
|
Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/qprod_s4_reg[10]/C
|
|
(rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns})
|
|
Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[10]/D
|
|
(rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns})
|
|
Path Group: mlkem_clk_clk_pll
|
|
Path Type: Hold (Min at Fast Process Corner)
|
|
Requirement: 0.000ns (mlkem_clk_clk_pll rise@0.000ns - mlkem_clk_clk_pll rise@0.000ns)
|
|
Data Path Delay: 0.475ns (logic 0.275ns (57.843%) route 0.200ns (42.157%))
|
|
Logic Levels: 2 (CARRY4=1 LUT2=1)
|
|
Clock Path Skew: 0.264ns (DCD - SCD - CPR)
|
|
Destination Clock Delay (DCD): -0.477ns
|
|
Source Clock Delay (SCD): -0.701ns
|
|
Clock Pessimism Removal (CPR): -0.040ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock mlkem_clk_clk_pll rise edge)
|
|
0.000 0.000 r
|
|
clock source latency -1.848 -1.848
|
|
propagated clock network latency
|
|
1.148 -0.701
|
|
SLICE_X84Y156 FDCE 0.000 -0.701 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/qprod_s4_reg[10]/C
|
|
SLICE_X84Y156 FDCE (Prop_fdce_C_Q) 0.164 -0.537 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/qprod_s4_reg[10]/Q
|
|
net (fo=1, routed) 0.200 -0.336 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/qprod_s4[10]
|
|
SLICE_X83Y156 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5[11]_i_3/I1
|
|
SLICE_X83Y156 LUT2 (Prop_lut2_I1_O) 0.045 -0.291 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5[11]_i_3/O
|
|
net (fo=1, routed) 0.000 -0.291 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5[11]_i_3_n_0
|
|
SLICE_X83Y156 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[11]_i_1/S[2]
|
|
SLICE_X83Y156 CARRY4 (Prop_carry4_S[2]_O[2])
|
|
0.066 -0.225 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[11]_i_1/O[2]
|
|
net (fo=1, routed) 0.000 -0.225 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s50[10]
|
|
SLICE_X83Y156 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[10]/D
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock mlkem_clk_clk_pll rise edge)
|
|
0.000 0.000 r
|
|
clock source latency -1.947 -1.947
|
|
propagated clock network latency
|
|
1.470 -0.477
|
|
clock pessimism 0.040 -0.437
|
|
SLICE_X83Y156 FDCE (Hold_fdce_C_D) 0.105 -0.332 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[10]
|
|
-------------------------------------------------------------------
|
|
required time 0.332
|
|
arrival time -0.225
|
|
-------------------------------------------------------------------
|
|
slack 0.107
|
|
|
|
Slack (MET) : 0.107ns (arrival time - required time)
|
|
Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/qprod_s4_reg[10]/C
|
|
(rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns})
|
|
Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[10]/D
|
|
(rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns})
|
|
Path Group: mlkem_clk_clk_pll
|
|
Path Type: Hold (Min at Fast Process Corner)
|
|
Requirement: 0.000ns (mlkem_clk_clk_pll rise@0.000ns - mlkem_clk_clk_pll rise@0.000ns)
|
|
Data Path Delay: 0.475ns (logic 0.275ns (57.843%) route 0.200ns (42.157%))
|
|
Logic Levels: 2 (CARRY4=1 LUT2=1)
|
|
Clock Path Skew: 0.264ns (DCD - SCD - CPR)
|
|
Destination Clock Delay (DCD): -0.477ns
|
|
Source Clock Delay (SCD): -0.701ns
|
|
Clock Pessimism Removal (CPR): -0.040ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock mlkem_clk_clk_pll rise edge)
|
|
0.000 0.000 r
|
|
clock source latency -1.848 -1.848
|
|
propagated clock network latency
|
|
1.148 -0.701
|
|
SLICE_X84Y156 FDCE 0.000 -0.701 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/qprod_s4_reg[10]/C
|
|
SLICE_X84Y156 FDCE (Prop_fdce_C_Q) 0.164 -0.537 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/qprod_s4_reg[10]/Q
|
|
net (fo=1, routed) 0.200 -0.336 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/qprod_s4[10]
|
|
SLICE_X83Y156 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5[11]_i_3/I1
|
|
SLICE_X83Y156 LUT2 (Prop_lut2_I1_O) 0.045 -0.291 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5[11]_i_3/O
|
|
net (fo=1, routed) 0.000 -0.291 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5[11]_i_3_n_0
|
|
SLICE_X83Y156 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[11]_i_1/S[2]
|
|
SLICE_X83Y156 CARRY4 (Prop_carry4_S[2]_O[2])
|
|
0.066 -0.225 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[11]_i_1/O[2]
|
|
net (fo=1, routed) 0.000 -0.225 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s50[10]
|
|
SLICE_X83Y156 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[10]/D
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock mlkem_clk_clk_pll rise edge)
|
|
0.000 0.000 r
|
|
clock source latency -1.947 -1.947
|
|
propagated clock network latency
|
|
1.470 -0.477
|
|
clock pessimism 0.040 -0.437
|
|
SLICE_X83Y156 FDCE (Hold_fdce_C_D) 0.105 -0.332 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[10]
|
|
-------------------------------------------------------------------
|
|
required time 0.332
|
|
arrival time -0.225
|
|
-------------------------------------------------------------------
|
|
slack 0.107
|
|
|
|
Slack (MET) : 0.107ns (arrival time - required time)
|
|
Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/qprod_s4_reg[10]/C
|
|
(rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns})
|
|
Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[10]/D
|
|
(rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns})
|
|
Path Group: mlkem_clk_clk_pll
|
|
Path Type: Hold (Min at Fast Process Corner)
|
|
Requirement: 0.000ns (mlkem_clk_clk_pll rise@0.000ns - mlkem_clk_clk_pll rise@0.000ns)
|
|
Data Path Delay: 0.475ns (logic 0.275ns (57.843%) route 0.200ns (42.157%))
|
|
Logic Levels: 2 (CARRY4=1 LUT2=1)
|
|
Clock Path Skew: 0.264ns (DCD - SCD - CPR)
|
|
Destination Clock Delay (DCD): -0.477ns
|
|
Source Clock Delay (SCD): -0.701ns
|
|
Clock Pessimism Removal (CPR): -0.040ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock mlkem_clk_clk_pll rise edge)
|
|
0.000 0.000 r
|
|
clock source latency -1.848 -1.848
|
|
propagated clock network latency
|
|
1.148 -0.701
|
|
SLICE_X84Y156 FDCE 0.000 -0.701 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/qprod_s4_reg[10]/C
|
|
SLICE_X84Y156 FDCE (Prop_fdce_C_Q) 0.164 -0.537 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/qprod_s4_reg[10]/Q
|
|
net (fo=1, routed) 0.200 -0.336 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/qprod_s4[10]
|
|
SLICE_X83Y156 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5[11]_i_3/I1
|
|
SLICE_X83Y156 LUT2 (Prop_lut2_I1_O) 0.045 -0.291 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5[11]_i_3/O
|
|
net (fo=1, routed) 0.000 -0.291 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5[11]_i_3_n_0
|
|
SLICE_X83Y156 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[11]_i_1/S[2]
|
|
SLICE_X83Y156 CARRY4 (Prop_carry4_S[2]_O[2])
|
|
0.066 -0.225 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[11]_i_1/O[2]
|
|
net (fo=1, routed) 0.000 -0.225 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s50[10]
|
|
SLICE_X83Y156 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[10]/D
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock mlkem_clk_clk_pll rise edge)
|
|
0.000 0.000 r
|
|
clock source latency -1.947 -1.947
|
|
propagated clock network latency
|
|
1.470 -0.477
|
|
clock pessimism 0.040 -0.437
|
|
SLICE_X83Y156 FDCE (Hold_fdce_C_D) 0.105 -0.332 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[10]
|
|
-------------------------------------------------------------------
|
|
required time 0.332
|
|
arrival time -0.225
|
|
-------------------------------------------------------------------
|
|
slack 0.107
|
|
|
|
Slack (MET) : 0.107ns (arrival time - required time)
|
|
Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/qprod_s4_reg[10]/C
|
|
(rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns})
|
|
Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[10]/D
|
|
(rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns})
|
|
Path Group: mlkem_clk_clk_pll
|
|
Path Type: Hold (Min at Fast Process Corner)
|
|
Requirement: 0.000ns (mlkem_clk_clk_pll rise@0.000ns - mlkem_clk_clk_pll rise@0.000ns)
|
|
Data Path Delay: 0.475ns (logic 0.275ns (57.843%) route 0.200ns (42.157%))
|
|
Logic Levels: 2 (CARRY4=1 LUT2=1)
|
|
Clock Path Skew: 0.264ns (DCD - SCD - CPR)
|
|
Destination Clock Delay (DCD): -0.477ns
|
|
Source Clock Delay (SCD): -0.701ns
|
|
Clock Pessimism Removal (CPR): -0.040ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock mlkem_clk_clk_pll rise edge)
|
|
0.000 0.000 r
|
|
clock source latency -1.848 -1.848
|
|
propagated clock network latency
|
|
1.148 -0.701
|
|
SLICE_X84Y156 FDCE 0.000 -0.701 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/qprod_s4_reg[10]/C
|
|
SLICE_X84Y156 FDCE (Prop_fdce_C_Q) 0.164 -0.537 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/qprod_s4_reg[10]/Q
|
|
net (fo=1, routed) 0.200 -0.336 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/qprod_s4[10]
|
|
SLICE_X83Y156 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5[11]_i_3/I1
|
|
SLICE_X83Y156 LUT2 (Prop_lut2_I1_O) 0.045 -0.291 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5[11]_i_3/O
|
|
net (fo=1, routed) 0.000 -0.291 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5[11]_i_3_n_0
|
|
SLICE_X83Y156 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[11]_i_1/S[2]
|
|
SLICE_X83Y156 CARRY4 (Prop_carry4_S[2]_O[2])
|
|
0.066 -0.225 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[11]_i_1/O[2]
|
|
net (fo=1, routed) 0.000 -0.225 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s50[10]
|
|
SLICE_X83Y156 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[10]/D
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock mlkem_clk_clk_pll rise edge)
|
|
0.000 0.000 r
|
|
clock source latency -1.947 -1.947
|
|
propagated clock network latency
|
|
1.470 -0.477
|
|
clock pessimism 0.040 -0.437
|
|
SLICE_X83Y156 FDCE (Hold_fdce_C_D) 0.105 -0.332 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[10]
|
|
-------------------------------------------------------------------
|
|
required time 0.332
|
|
arrival time -0.225
|
|
-------------------------------------------------------------------
|
|
slack 0.107
|
|
|
|
Slack (MET) : 0.107ns (arrival time - required time)
|
|
Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/qprod_s4_reg[10]/C
|
|
(rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns})
|
|
Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[10]/D
|
|
(rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns})
|
|
Path Group: mlkem_clk_clk_pll
|
|
Path Type: Hold (Min at Fast Process Corner)
|
|
Requirement: 0.000ns (mlkem_clk_clk_pll rise@0.000ns - mlkem_clk_clk_pll rise@0.000ns)
|
|
Data Path Delay: 0.475ns (logic 0.275ns (57.843%) route 0.200ns (42.157%))
|
|
Logic Levels: 2 (CARRY4=1 LUT2=1)
|
|
Clock Path Skew: 0.264ns (DCD - SCD - CPR)
|
|
Destination Clock Delay (DCD): -0.477ns
|
|
Source Clock Delay (SCD): -0.701ns
|
|
Clock Pessimism Removal (CPR): -0.040ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock mlkem_clk_clk_pll rise edge)
|
|
0.000 0.000 r
|
|
clock source latency -1.848 -1.848
|
|
propagated clock network latency
|
|
1.148 -0.701
|
|
SLICE_X84Y156 FDCE 0.000 -0.701 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/qprod_s4_reg[10]/C
|
|
SLICE_X84Y156 FDCE (Prop_fdce_C_Q) 0.164 -0.537 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/qprod_s4_reg[10]/Q
|
|
net (fo=1, routed) 0.200 -0.336 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/qprod_s4[10]
|
|
SLICE_X83Y156 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5[11]_i_3/I1
|
|
SLICE_X83Y156 LUT2 (Prop_lut2_I1_O) 0.045 -0.291 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5[11]_i_3/O
|
|
net (fo=1, routed) 0.000 -0.291 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5[11]_i_3_n_0
|
|
SLICE_X83Y156 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[11]_i_1/S[2]
|
|
SLICE_X83Y156 CARRY4 (Prop_carry4_S[2]_O[2])
|
|
0.066 -0.225 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[11]_i_1/O[2]
|
|
net (fo=1, routed) 0.000 -0.225 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s50[10]
|
|
SLICE_X83Y156 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[10]/D
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock mlkem_clk_clk_pll rise edge)
|
|
0.000 0.000 r
|
|
clock source latency -1.947 -1.947
|
|
propagated clock network latency
|
|
1.470 -0.477
|
|
clock pessimism 0.040 -0.437
|
|
SLICE_X83Y156 FDCE (Hold_fdce_C_D) 0.105 -0.332 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[10]
|
|
-------------------------------------------------------------------
|
|
required time 0.332
|
|
arrival time -0.225
|
|
-------------------------------------------------------------------
|
|
slack 0.107
|
|
|
|
Slack (MET) : 0.107ns (arrival time - required time)
|
|
Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/qprod_s4_reg[14]/C
|
|
(rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns})
|
|
Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[14]/D
|
|
(rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns})
|
|
Path Group: mlkem_clk_clk_pll
|
|
Path Type: Hold (Min at Fast Process Corner)
|
|
Requirement: 0.000ns (mlkem_clk_clk_pll rise@0.000ns - mlkem_clk_clk_pll rise@0.000ns)
|
|
Data Path Delay: 0.475ns (logic 0.275ns (57.843%) route 0.200ns (42.157%))
|
|
Logic Levels: 2 (CARRY4=1 LUT2=1)
|
|
Clock Path Skew: 0.264ns (DCD - SCD - CPR)
|
|
Destination Clock Delay (DCD): -0.478ns
|
|
Source Clock Delay (SCD): -0.702ns
|
|
Clock Pessimism Removal (CPR): -0.040ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock mlkem_clk_clk_pll rise edge)
|
|
0.000 0.000 r
|
|
clock source latency -1.848 -1.848
|
|
propagated clock network latency
|
|
1.147 -0.702
|
|
SLICE_X84Y157 FDCE 0.000 -0.702 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/qprod_s4_reg[14]/C
|
|
SLICE_X84Y157 FDCE (Prop_fdce_C_Q) 0.164 -0.538 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/qprod_s4_reg[14]/Q
|
|
net (fo=1, routed) 0.200 -0.337 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/qprod_s4[14]
|
|
SLICE_X83Y157 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5[15]_i_3/I1
|
|
SLICE_X83Y157 LUT2 (Prop_lut2_I1_O) 0.045 -0.292 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5[15]_i_3/O
|
|
net (fo=1, routed) 0.000 -0.292 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5[15]_i_3_n_0
|
|
SLICE_X83Y157 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[15]_i_1/S[2]
|
|
SLICE_X83Y157 CARRY4 (Prop_carry4_S[2]_O[2])
|
|
0.066 -0.226 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[15]_i_1/O[2]
|
|
net (fo=1, routed) 0.000 -0.226 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s50[14]
|
|
SLICE_X83Y157 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[14]/D
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock mlkem_clk_clk_pll rise edge)
|
|
0.000 0.000 r
|
|
clock source latency -1.947 -1.947
|
|
propagated clock network latency
|
|
1.469 -0.478
|
|
clock pessimism 0.040 -0.438
|
|
SLICE_X83Y157 FDCE (Hold_fdce_C_D) 0.105 -0.333 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[14]
|
|
-------------------------------------------------------------------
|
|
required time 0.333
|
|
arrival time -0.226
|
|
-------------------------------------------------------------------
|
|
slack 0.107
|
|
|
|
Slack (MET) : 0.107ns (arrival time - required time)
|
|
Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/qprod_s4_reg[14]/C
|
|
(rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns})
|
|
Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[14]/D
|
|
(rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns})
|
|
Path Group: mlkem_clk_clk_pll
|
|
Path Type: Hold (Min at Fast Process Corner)
|
|
Requirement: 0.000ns (mlkem_clk_clk_pll rise@0.000ns - mlkem_clk_clk_pll rise@0.000ns)
|
|
Data Path Delay: 0.475ns (logic 0.275ns (57.843%) route 0.200ns (42.157%))
|
|
Logic Levels: 2 (CARRY4=1 LUT2=1)
|
|
Clock Path Skew: 0.264ns (DCD - SCD - CPR)
|
|
Destination Clock Delay (DCD): -0.478ns
|
|
Source Clock Delay (SCD): -0.702ns
|
|
Clock Pessimism Removal (CPR): -0.040ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock mlkem_clk_clk_pll rise edge)
|
|
0.000 0.000 r
|
|
clock source latency -1.848 -1.848
|
|
propagated clock network latency
|
|
1.147 -0.702
|
|
SLICE_X84Y157 FDCE 0.000 -0.702 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/qprod_s4_reg[14]/C
|
|
SLICE_X84Y157 FDCE (Prop_fdce_C_Q) 0.164 -0.538 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/qprod_s4_reg[14]/Q
|
|
net (fo=1, routed) 0.200 -0.337 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/qprod_s4[14]
|
|
SLICE_X83Y157 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5[15]_i_3/I1
|
|
SLICE_X83Y157 LUT2 (Prop_lut2_I1_O) 0.045 -0.292 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5[15]_i_3/O
|
|
net (fo=1, routed) 0.000 -0.292 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5[15]_i_3_n_0
|
|
SLICE_X83Y157 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[15]_i_1/S[2]
|
|
SLICE_X83Y157 CARRY4 (Prop_carry4_S[2]_O[2])
|
|
0.066 -0.226 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[15]_i_1/O[2]
|
|
net (fo=1, routed) 0.000 -0.226 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s50[14]
|
|
SLICE_X83Y157 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[14]/D
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock mlkem_clk_clk_pll rise edge)
|
|
0.000 0.000 r
|
|
clock source latency -1.947 -1.947
|
|
propagated clock network latency
|
|
1.469 -0.478
|
|
clock pessimism 0.040 -0.438
|
|
SLICE_X83Y157 FDCE (Hold_fdce_C_D) 0.105 -0.333 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[14]
|
|
-------------------------------------------------------------------
|
|
required time 0.333
|
|
arrival time -0.226
|
|
-------------------------------------------------------------------
|
|
slack 0.107
|
|
|
|
Slack (MET) : 0.107ns (arrival time - required time)
|
|
Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/qprod_s4_reg[14]/C
|
|
(rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns})
|
|
Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[14]/D
|
|
(rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns})
|
|
Path Group: mlkem_clk_clk_pll
|
|
Path Type: Hold (Min at Fast Process Corner)
|
|
Requirement: 0.000ns (mlkem_clk_clk_pll rise@0.000ns - mlkem_clk_clk_pll rise@0.000ns)
|
|
Data Path Delay: 0.475ns (logic 0.275ns (57.843%) route 0.200ns (42.157%))
|
|
Logic Levels: 2 (CARRY4=1 LUT2=1)
|
|
Clock Path Skew: 0.264ns (DCD - SCD - CPR)
|
|
Destination Clock Delay (DCD): -0.478ns
|
|
Source Clock Delay (SCD): -0.702ns
|
|
Clock Pessimism Removal (CPR): -0.040ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock mlkem_clk_clk_pll rise edge)
|
|
0.000 0.000 r
|
|
clock source latency -1.848 -1.848
|
|
propagated clock network latency
|
|
1.147 -0.702
|
|
SLICE_X84Y157 FDCE 0.000 -0.702 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/qprod_s4_reg[14]/C
|
|
SLICE_X84Y157 FDCE (Prop_fdce_C_Q) 0.164 -0.538 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/qprod_s4_reg[14]/Q
|
|
net (fo=1, routed) 0.200 -0.337 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/qprod_s4[14]
|
|
SLICE_X83Y157 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5[15]_i_3/I1
|
|
SLICE_X83Y157 LUT2 (Prop_lut2_I1_O) 0.045 -0.292 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5[15]_i_3/O
|
|
net (fo=1, routed) 0.000 -0.292 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5[15]_i_3_n_0
|
|
SLICE_X83Y157 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[15]_i_1/S[2]
|
|
SLICE_X83Y157 CARRY4 (Prop_carry4_S[2]_O[2])
|
|
0.066 -0.226 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[15]_i_1/O[2]
|
|
net (fo=1, routed) 0.000 -0.226 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s50[14]
|
|
SLICE_X83Y157 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[14]/D
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock mlkem_clk_clk_pll rise edge)
|
|
0.000 0.000 r
|
|
clock source latency -1.947 -1.947
|
|
propagated clock network latency
|
|
1.469 -0.478
|
|
clock pessimism 0.040 -0.438
|
|
SLICE_X83Y157 FDCE (Hold_fdce_C_D) 0.105 -0.333 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[14]
|
|
-------------------------------------------------------------------
|
|
required time 0.333
|
|
arrival time -0.226
|
|
-------------------------------------------------------------------
|
|
slack 0.107
|
|
|
|
Slack (MET) : 0.107ns (arrival time - required time)
|
|
Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/qprod_s4_reg[14]/C
|
|
(rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns})
|
|
Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[14]/D
|
|
(rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns})
|
|
Path Group: mlkem_clk_clk_pll
|
|
Path Type: Hold (Min at Fast Process Corner)
|
|
Requirement: 0.000ns (mlkem_clk_clk_pll rise@0.000ns - mlkem_clk_clk_pll rise@0.000ns)
|
|
Data Path Delay: 0.475ns (logic 0.275ns (57.843%) route 0.200ns (42.157%))
|
|
Logic Levels: 2 (CARRY4=1 LUT2=1)
|
|
Clock Path Skew: 0.264ns (DCD - SCD - CPR)
|
|
Destination Clock Delay (DCD): -0.478ns
|
|
Source Clock Delay (SCD): -0.702ns
|
|
Clock Pessimism Removal (CPR): -0.040ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock mlkem_clk_clk_pll rise edge)
|
|
0.000 0.000 r
|
|
clock source latency -1.848 -1.848
|
|
propagated clock network latency
|
|
1.147 -0.702
|
|
SLICE_X84Y157 FDCE 0.000 -0.702 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/qprod_s4_reg[14]/C
|
|
SLICE_X84Y157 FDCE (Prop_fdce_C_Q) 0.164 -0.538 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/qprod_s4_reg[14]/Q
|
|
net (fo=1, routed) 0.200 -0.337 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/qprod_s4[14]
|
|
SLICE_X83Y157 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5[15]_i_3/I1
|
|
SLICE_X83Y157 LUT2 (Prop_lut2_I1_O) 0.045 -0.292 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5[15]_i_3/O
|
|
net (fo=1, routed) 0.000 -0.292 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5[15]_i_3_n_0
|
|
SLICE_X83Y157 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[15]_i_1/S[2]
|
|
SLICE_X83Y157 CARRY4 (Prop_carry4_S[2]_O[2])
|
|
0.066 -0.226 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[15]_i_1/O[2]
|
|
net (fo=1, routed) 0.000 -0.226 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s50[14]
|
|
SLICE_X83Y157 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[14]/D
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock mlkem_clk_clk_pll rise edge)
|
|
0.000 0.000 r
|
|
clock source latency -1.947 -1.947
|
|
propagated clock network latency
|
|
1.469 -0.478
|
|
clock pessimism 0.040 -0.438
|
|
SLICE_X83Y157 FDCE (Hold_fdce_C_D) 0.105 -0.333 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[14]
|
|
-------------------------------------------------------------------
|
|
required time 0.333
|
|
arrival time -0.226
|
|
-------------------------------------------------------------------
|
|
slack 0.107
|
|
|
|
Slack (MET) : 0.107ns (arrival time - required time)
|
|
Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/qprod_s4_reg[14]/C
|
|
(rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns})
|
|
Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[14]/D
|
|
(rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns})
|
|
Path Group: mlkem_clk_clk_pll
|
|
Path Type: Hold (Min at Fast Process Corner)
|
|
Requirement: 0.000ns (mlkem_clk_clk_pll rise@0.000ns - mlkem_clk_clk_pll rise@0.000ns)
|
|
Data Path Delay: 0.475ns (logic 0.275ns (57.843%) route 0.200ns (42.157%))
|
|
Logic Levels: 2 (CARRY4=1 LUT2=1)
|
|
Clock Path Skew: 0.264ns (DCD - SCD - CPR)
|
|
Destination Clock Delay (DCD): -0.478ns
|
|
Source Clock Delay (SCD): -0.702ns
|
|
Clock Pessimism Removal (CPR): -0.040ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock mlkem_clk_clk_pll rise edge)
|
|
0.000 0.000 r
|
|
clock source latency -1.848 -1.848
|
|
propagated clock network latency
|
|
1.147 -0.702
|
|
SLICE_X84Y157 FDCE 0.000 -0.702 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/qprod_s4_reg[14]/C
|
|
SLICE_X84Y157 FDCE (Prop_fdce_C_Q) 0.164 -0.538 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/qprod_s4_reg[14]/Q
|
|
net (fo=1, routed) 0.200 -0.337 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/qprod_s4[14]
|
|
SLICE_X83Y157 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5[15]_i_3/I1
|
|
SLICE_X83Y157 LUT2 (Prop_lut2_I1_O) 0.045 -0.292 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5[15]_i_3/O
|
|
net (fo=1, routed) 0.000 -0.292 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5[15]_i_3_n_0
|
|
SLICE_X83Y157 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[15]_i_1/S[2]
|
|
SLICE_X83Y157 CARRY4 (Prop_carry4_S[2]_O[2])
|
|
0.066 -0.226 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[15]_i_1/O[2]
|
|
net (fo=1, routed) 0.000 -0.226 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s50[14]
|
|
SLICE_X83Y157 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[14]/D
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock mlkem_clk_clk_pll rise edge)
|
|
0.000 0.000 r
|
|
clock source latency -1.947 -1.947
|
|
propagated clock network latency
|
|
1.469 -0.478
|
|
clock pessimism 0.040 -0.438
|
|
SLICE_X83Y157 FDCE (Hold_fdce_C_D) 0.105 -0.333 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[14]
|
|
-------------------------------------------------------------------
|
|
required time 0.333
|
|
arrival time -0.226
|
|
-------------------------------------------------------------------
|
|
slack 0.107
|
|
|
|
Slack (MET) : 0.107ns (arrival time - required time)
|
|
Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/qprod_s4_reg[14]/C
|
|
(rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns})
|
|
Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[14]/D
|
|
(rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns})
|
|
Path Group: mlkem_clk_clk_pll
|
|
Path Type: Hold (Min at Fast Process Corner)
|
|
Requirement: 0.000ns (mlkem_clk_clk_pll rise@0.000ns - mlkem_clk_clk_pll rise@0.000ns)
|
|
Data Path Delay: 0.475ns (logic 0.275ns (57.843%) route 0.200ns (42.157%))
|
|
Logic Levels: 2 (CARRY4=1 LUT2=1)
|
|
Clock Path Skew: 0.264ns (DCD - SCD - CPR)
|
|
Destination Clock Delay (DCD): -0.478ns
|
|
Source Clock Delay (SCD): -0.702ns
|
|
Clock Pessimism Removal (CPR): -0.040ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock mlkem_clk_clk_pll rise edge)
|
|
0.000 0.000 r
|
|
clock source latency -1.848 -1.848
|
|
propagated clock network latency
|
|
1.147 -0.702
|
|
SLICE_X84Y157 FDCE 0.000 -0.702 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/qprod_s4_reg[14]/C
|
|
SLICE_X84Y157 FDCE (Prop_fdce_C_Q) 0.164 -0.538 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/qprod_s4_reg[14]/Q
|
|
net (fo=1, routed) 0.200 -0.337 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/qprod_s4[14]
|
|
SLICE_X83Y157 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5[15]_i_3/I1
|
|
SLICE_X83Y157 LUT2 (Prop_lut2_I1_O) 0.045 -0.292 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5[15]_i_3/O
|
|
net (fo=1, routed) 0.000 -0.292 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5[15]_i_3_n_0
|
|
SLICE_X83Y157 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[15]_i_1/S[2]
|
|
SLICE_X83Y157 CARRY4 (Prop_carry4_S[2]_O[2])
|
|
0.066 -0.226 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[15]_i_1/O[2]
|
|
net (fo=1, routed) 0.000 -0.226 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s50[14]
|
|
SLICE_X83Y157 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[14]/D
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock mlkem_clk_clk_pll rise edge)
|
|
0.000 0.000 r
|
|
clock source latency -1.947 -1.947
|
|
propagated clock network latency
|
|
1.469 -0.478
|
|
clock pessimism 0.040 -0.438
|
|
SLICE_X83Y157 FDCE (Hold_fdce_C_D) 0.105 -0.333 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[14]
|
|
-------------------------------------------------------------------
|
|
required time 0.333
|
|
arrival time -0.226
|
|
-------------------------------------------------------------------
|
|
slack 0.107
|
|
|
|
Slack (MET) : 0.107ns (arrival time - required time)
|
|
Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/qprod_s4_reg[14]/C
|
|
(rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns})
|
|
Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[14]/D
|
|
(rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns})
|
|
Path Group: mlkem_clk_clk_pll
|
|
Path Type: Hold (Min at Fast Process Corner)
|
|
Requirement: 0.000ns (mlkem_clk_clk_pll rise@0.000ns - mlkem_clk_clk_pll rise@0.000ns)
|
|
Data Path Delay: 0.475ns (logic 0.275ns (57.843%) route 0.200ns (42.157%))
|
|
Logic Levels: 2 (CARRY4=1 LUT2=1)
|
|
Clock Path Skew: 0.264ns (DCD - SCD - CPR)
|
|
Destination Clock Delay (DCD): -0.478ns
|
|
Source Clock Delay (SCD): -0.702ns
|
|
Clock Pessimism Removal (CPR): -0.040ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock mlkem_clk_clk_pll rise edge)
|
|
0.000 0.000 r
|
|
clock source latency -1.848 -1.848
|
|
propagated clock network latency
|
|
1.147 -0.702
|
|
SLICE_X84Y157 FDCE 0.000 -0.702 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/qprod_s4_reg[14]/C
|
|
SLICE_X84Y157 FDCE (Prop_fdce_C_Q) 0.164 -0.538 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/qprod_s4_reg[14]/Q
|
|
net (fo=1, routed) 0.200 -0.337 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/qprod_s4[14]
|
|
SLICE_X83Y157 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5[15]_i_3/I1
|
|
SLICE_X83Y157 LUT2 (Prop_lut2_I1_O) 0.045 -0.292 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5[15]_i_3/O
|
|
net (fo=1, routed) 0.000 -0.292 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5[15]_i_3_n_0
|
|
SLICE_X83Y157 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[15]_i_1/S[2]
|
|
SLICE_X83Y157 CARRY4 (Prop_carry4_S[2]_O[2])
|
|
0.066 -0.226 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[15]_i_1/O[2]
|
|
net (fo=1, routed) 0.000 -0.226 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s50[14]
|
|
SLICE_X83Y157 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[14]/D
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock mlkem_clk_clk_pll rise edge)
|
|
0.000 0.000 r
|
|
clock source latency -1.947 -1.947
|
|
propagated clock network latency
|
|
1.469 -0.478
|
|
clock pessimism 0.040 -0.438
|
|
SLICE_X83Y157 FDCE (Hold_fdce_C_D) 0.105 -0.333 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[14]
|
|
-------------------------------------------------------------------
|
|
required time 0.333
|
|
arrival time -0.226
|
|
-------------------------------------------------------------------
|
|
slack 0.107
|
|
|
|
Slack (MET) : 0.107ns (arrival time - required time)
|
|
Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/qprod_s4_reg[14]/C
|
|
(rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns})
|
|
Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[14]/D
|
|
(rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns})
|
|
Path Group: mlkem_clk_clk_pll
|
|
Path Type: Hold (Min at Fast Process Corner)
|
|
Requirement: 0.000ns (mlkem_clk_clk_pll rise@0.000ns - mlkem_clk_clk_pll rise@0.000ns)
|
|
Data Path Delay: 0.475ns (logic 0.275ns (57.843%) route 0.200ns (42.157%))
|
|
Logic Levels: 2 (CARRY4=1 LUT2=1)
|
|
Clock Path Skew: 0.264ns (DCD - SCD - CPR)
|
|
Destination Clock Delay (DCD): -0.478ns
|
|
Source Clock Delay (SCD): -0.702ns
|
|
Clock Pessimism Removal (CPR): -0.040ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock mlkem_clk_clk_pll rise edge)
|
|
0.000 0.000 r
|
|
clock source latency -1.848 -1.848
|
|
propagated clock network latency
|
|
1.147 -0.702
|
|
SLICE_X84Y157 FDCE 0.000 -0.702 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/qprod_s4_reg[14]/C
|
|
SLICE_X84Y157 FDCE (Prop_fdce_C_Q) 0.164 -0.538 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/qprod_s4_reg[14]/Q
|
|
net (fo=1, routed) 0.200 -0.337 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/qprod_s4[14]
|
|
SLICE_X83Y157 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5[15]_i_3/I1
|
|
SLICE_X83Y157 LUT2 (Prop_lut2_I1_O) 0.045 -0.292 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5[15]_i_3/O
|
|
net (fo=1, routed) 0.000 -0.292 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5[15]_i_3_n_0
|
|
SLICE_X83Y157 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[15]_i_1/S[2]
|
|
SLICE_X83Y157 CARRY4 (Prop_carry4_S[2]_O[2])
|
|
0.066 -0.226 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[15]_i_1/O[2]
|
|
net (fo=1, routed) 0.000 -0.226 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s50[14]
|
|
SLICE_X83Y157 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[14]/D
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock mlkem_clk_clk_pll rise edge)
|
|
0.000 0.000 r
|
|
clock source latency -1.947 -1.947
|
|
propagated clock network latency
|
|
1.469 -0.478
|
|
clock pessimism 0.040 -0.438
|
|
SLICE_X83Y157 FDCE (Hold_fdce_C_D) 0.105 -0.333 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[14]
|
|
-------------------------------------------------------------------
|
|
required time 0.333
|
|
arrival time -0.226
|
|
-------------------------------------------------------------------
|
|
slack 0.107
|
|
|
|
Slack (MET) : 0.107ns (arrival time - required time)
|
|
Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/qprod_s4_reg[18]/C
|
|
(rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns})
|
|
Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[18]/D
|
|
(rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns})
|
|
Path Group: mlkem_clk_clk_pll
|
|
Path Type: Hold (Min at Fast Process Corner)
|
|
Requirement: 0.000ns (mlkem_clk_clk_pll rise@0.000ns - mlkem_clk_clk_pll rise@0.000ns)
|
|
Data Path Delay: 0.475ns (logic 0.275ns (57.843%) route 0.200ns (42.157%))
|
|
Logic Levels: 2 (CARRY4=1 LUT2=1)
|
|
Clock Path Skew: 0.264ns (DCD - SCD - CPR)
|
|
Destination Clock Delay (DCD): -0.478ns
|
|
Source Clock Delay (SCD): -0.702ns
|
|
Clock Pessimism Removal (CPR): -0.040ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock mlkem_clk_clk_pll rise edge)
|
|
0.000 0.000 r
|
|
clock source latency -1.848 -1.848
|
|
propagated clock network latency
|
|
1.147 -0.702
|
|
SLICE_X84Y158 FDCE 0.000 -0.702 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/qprod_s4_reg[18]/C
|
|
SLICE_X84Y158 FDCE (Prop_fdce_C_Q) 0.164 -0.538 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/qprod_s4_reg[18]/Q
|
|
net (fo=1, routed) 0.200 -0.337 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/qprod_s4[18]
|
|
SLICE_X83Y158 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5[19]_i_3/I1
|
|
SLICE_X83Y158 LUT2 (Prop_lut2_I1_O) 0.045 -0.292 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5[19]_i_3/O
|
|
net (fo=1, routed) 0.000 -0.292 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5[19]_i_3_n_0
|
|
SLICE_X83Y158 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[19]_i_1/S[2]
|
|
SLICE_X83Y158 CARRY4 (Prop_carry4_S[2]_O[2])
|
|
0.066 -0.226 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[19]_i_1/O[2]
|
|
net (fo=1, routed) 0.000 -0.226 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s50[18]
|
|
SLICE_X83Y158 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[18]/D
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock mlkem_clk_clk_pll rise edge)
|
|
0.000 0.000 r
|
|
clock source latency -1.947 -1.947
|
|
propagated clock network latency
|
|
1.469 -0.478
|
|
clock pessimism 0.040 -0.438
|
|
SLICE_X83Y158 FDCE (Hold_fdce_C_D) 0.105 -0.333 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[18]
|
|
-------------------------------------------------------------------
|
|
required time 0.333
|
|
arrival time -0.226
|
|
-------------------------------------------------------------------
|
|
slack 0.107
|
|
|
|
Slack (MET) : 0.107ns (arrival time - required time)
|
|
Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/qprod_s4_reg[18]/C
|
|
(rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns})
|
|
Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[18]/D
|
|
(rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns})
|
|
Path Group: mlkem_clk_clk_pll
|
|
Path Type: Hold (Min at Fast Process Corner)
|
|
Requirement: 0.000ns (mlkem_clk_clk_pll rise@0.000ns - mlkem_clk_clk_pll rise@0.000ns)
|
|
Data Path Delay: 0.475ns (logic 0.275ns (57.843%) route 0.200ns (42.157%))
|
|
Logic Levels: 2 (CARRY4=1 LUT2=1)
|
|
Clock Path Skew: 0.264ns (DCD - SCD - CPR)
|
|
Destination Clock Delay (DCD): -0.478ns
|
|
Source Clock Delay (SCD): -0.702ns
|
|
Clock Pessimism Removal (CPR): -0.040ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock mlkem_clk_clk_pll rise edge)
|
|
0.000 0.000 r
|
|
clock source latency -1.848 -1.848
|
|
propagated clock network latency
|
|
1.147 -0.702
|
|
SLICE_X84Y158 FDCE 0.000 -0.702 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/qprod_s4_reg[18]/C
|
|
SLICE_X84Y158 FDCE (Prop_fdce_C_Q) 0.164 -0.538 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/qprod_s4_reg[18]/Q
|
|
net (fo=1, routed) 0.200 -0.337 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/qprod_s4[18]
|
|
SLICE_X83Y158 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5[19]_i_3/I1
|
|
SLICE_X83Y158 LUT2 (Prop_lut2_I1_O) 0.045 -0.292 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5[19]_i_3/O
|
|
net (fo=1, routed) 0.000 -0.292 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5[19]_i_3_n_0
|
|
SLICE_X83Y158 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[19]_i_1/S[2]
|
|
SLICE_X83Y158 CARRY4 (Prop_carry4_S[2]_O[2])
|
|
0.066 -0.226 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[19]_i_1/O[2]
|
|
net (fo=1, routed) 0.000 -0.226 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s50[18]
|
|
SLICE_X83Y158 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[18]/D
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock mlkem_clk_clk_pll rise edge)
|
|
0.000 0.000 r
|
|
clock source latency -1.947 -1.947
|
|
propagated clock network latency
|
|
1.469 -0.478
|
|
clock pessimism 0.040 -0.438
|
|
SLICE_X83Y158 FDCE (Hold_fdce_C_D) 0.105 -0.333 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[18]
|
|
-------------------------------------------------------------------
|
|
required time 0.333
|
|
arrival time -0.226
|
|
-------------------------------------------------------------------
|
|
slack 0.107
|
|
|
|
Slack (MET) : 0.107ns (arrival time - required time)
|
|
Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/qprod_s4_reg[18]/C
|
|
(rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns})
|
|
Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[18]/D
|
|
(rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns})
|
|
Path Group: mlkem_clk_clk_pll
|
|
Path Type: Hold (Min at Fast Process Corner)
|
|
Requirement: 0.000ns (mlkem_clk_clk_pll rise@0.000ns - mlkem_clk_clk_pll rise@0.000ns)
|
|
Data Path Delay: 0.475ns (logic 0.275ns (57.843%) route 0.200ns (42.157%))
|
|
Logic Levels: 2 (CARRY4=1 LUT2=1)
|
|
Clock Path Skew: 0.264ns (DCD - SCD - CPR)
|
|
Destination Clock Delay (DCD): -0.478ns
|
|
Source Clock Delay (SCD): -0.702ns
|
|
Clock Pessimism Removal (CPR): -0.040ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock mlkem_clk_clk_pll rise edge)
|
|
0.000 0.000 r
|
|
clock source latency -1.848 -1.848
|
|
propagated clock network latency
|
|
1.147 -0.702
|
|
SLICE_X84Y158 FDCE 0.000 -0.702 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/qprod_s4_reg[18]/C
|
|
SLICE_X84Y158 FDCE (Prop_fdce_C_Q) 0.164 -0.538 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/qprod_s4_reg[18]/Q
|
|
net (fo=1, routed) 0.200 -0.337 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/qprod_s4[18]
|
|
SLICE_X83Y158 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5[19]_i_3/I1
|
|
SLICE_X83Y158 LUT2 (Prop_lut2_I1_O) 0.045 -0.292 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5[19]_i_3/O
|
|
net (fo=1, routed) 0.000 -0.292 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5[19]_i_3_n_0
|
|
SLICE_X83Y158 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[19]_i_1/S[2]
|
|
SLICE_X83Y158 CARRY4 (Prop_carry4_S[2]_O[2])
|
|
0.066 -0.226 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[19]_i_1/O[2]
|
|
net (fo=1, routed) 0.000 -0.226 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s50[18]
|
|
SLICE_X83Y158 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[18]/D
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock mlkem_clk_clk_pll rise edge)
|
|
0.000 0.000 r
|
|
clock source latency -1.947 -1.947
|
|
propagated clock network latency
|
|
1.469 -0.478
|
|
clock pessimism 0.040 -0.438
|
|
SLICE_X83Y158 FDCE (Hold_fdce_C_D) 0.105 -0.333 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[18]
|
|
-------------------------------------------------------------------
|
|
required time 0.333
|
|
arrival time -0.226
|
|
-------------------------------------------------------------------
|
|
slack 0.107
|
|
|
|
Slack (MET) : 0.107ns (arrival time - required time)
|
|
Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/qprod_s4_reg[18]/C
|
|
(rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns})
|
|
Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[18]/D
|
|
(rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns})
|
|
Path Group: mlkem_clk_clk_pll
|
|
Path Type: Hold (Min at Fast Process Corner)
|
|
Requirement: 0.000ns (mlkem_clk_clk_pll rise@0.000ns - mlkem_clk_clk_pll rise@0.000ns)
|
|
Data Path Delay: 0.475ns (logic 0.275ns (57.843%) route 0.200ns (42.157%))
|
|
Logic Levels: 2 (CARRY4=1 LUT2=1)
|
|
Clock Path Skew: 0.264ns (DCD - SCD - CPR)
|
|
Destination Clock Delay (DCD): -0.478ns
|
|
Source Clock Delay (SCD): -0.702ns
|
|
Clock Pessimism Removal (CPR): -0.040ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock mlkem_clk_clk_pll rise edge)
|
|
0.000 0.000 r
|
|
clock source latency -1.848 -1.848
|
|
propagated clock network latency
|
|
1.147 -0.702
|
|
SLICE_X84Y158 FDCE 0.000 -0.702 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/qprod_s4_reg[18]/C
|
|
SLICE_X84Y158 FDCE (Prop_fdce_C_Q) 0.164 -0.538 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/qprod_s4_reg[18]/Q
|
|
net (fo=1, routed) 0.200 -0.337 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/qprod_s4[18]
|
|
SLICE_X83Y158 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5[19]_i_3/I1
|
|
SLICE_X83Y158 LUT2 (Prop_lut2_I1_O) 0.045 -0.292 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5[19]_i_3/O
|
|
net (fo=1, routed) 0.000 -0.292 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5[19]_i_3_n_0
|
|
SLICE_X83Y158 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[19]_i_1/S[2]
|
|
SLICE_X83Y158 CARRY4 (Prop_carry4_S[2]_O[2])
|
|
0.066 -0.226 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[19]_i_1/O[2]
|
|
net (fo=1, routed) 0.000 -0.226 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s50[18]
|
|
SLICE_X83Y158 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[18]/D
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock mlkem_clk_clk_pll rise edge)
|
|
0.000 0.000 r
|
|
clock source latency -1.947 -1.947
|
|
propagated clock network latency
|
|
1.469 -0.478
|
|
clock pessimism 0.040 -0.438
|
|
SLICE_X83Y158 FDCE (Hold_fdce_C_D) 0.105 -0.333 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[18]
|
|
-------------------------------------------------------------------
|
|
required time 0.333
|
|
arrival time -0.226
|
|
-------------------------------------------------------------------
|
|
slack 0.107
|
|
|
|
Slack (MET) : 0.107ns (arrival time - required time)
|
|
Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/qprod_s4_reg[18]/C
|
|
(rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns})
|
|
Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[18]/D
|
|
(rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns})
|
|
Path Group: mlkem_clk_clk_pll
|
|
Path Type: Hold (Min at Fast Process Corner)
|
|
Requirement: 0.000ns (mlkem_clk_clk_pll rise@0.000ns - mlkem_clk_clk_pll rise@0.000ns)
|
|
Data Path Delay: 0.475ns (logic 0.275ns (57.843%) route 0.200ns (42.157%))
|
|
Logic Levels: 2 (CARRY4=1 LUT2=1)
|
|
Clock Path Skew: 0.264ns (DCD - SCD - CPR)
|
|
Destination Clock Delay (DCD): -0.478ns
|
|
Source Clock Delay (SCD): -0.702ns
|
|
Clock Pessimism Removal (CPR): -0.040ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock mlkem_clk_clk_pll rise edge)
|
|
0.000 0.000 r
|
|
clock source latency -1.848 -1.848
|
|
propagated clock network latency
|
|
1.147 -0.702
|
|
SLICE_X84Y158 FDCE 0.000 -0.702 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/qprod_s4_reg[18]/C
|
|
SLICE_X84Y158 FDCE (Prop_fdce_C_Q) 0.164 -0.538 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/qprod_s4_reg[18]/Q
|
|
net (fo=1, routed) 0.200 -0.337 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/qprod_s4[18]
|
|
SLICE_X83Y158 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5[19]_i_3/I1
|
|
SLICE_X83Y158 LUT2 (Prop_lut2_I1_O) 0.045 -0.292 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5[19]_i_3/O
|
|
net (fo=1, routed) 0.000 -0.292 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5[19]_i_3_n_0
|
|
SLICE_X83Y158 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[19]_i_1/S[2]
|
|
SLICE_X83Y158 CARRY4 (Prop_carry4_S[2]_O[2])
|
|
0.066 -0.226 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[19]_i_1/O[2]
|
|
net (fo=1, routed) 0.000 -0.226 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s50[18]
|
|
SLICE_X83Y158 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[18]/D
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock mlkem_clk_clk_pll rise edge)
|
|
0.000 0.000 r
|
|
clock source latency -1.947 -1.947
|
|
propagated clock network latency
|
|
1.469 -0.478
|
|
clock pessimism 0.040 -0.438
|
|
SLICE_X83Y158 FDCE (Hold_fdce_C_D) 0.105 -0.333 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[18]
|
|
-------------------------------------------------------------------
|
|
required time 0.333
|
|
arrival time -0.226
|
|
-------------------------------------------------------------------
|
|
slack 0.107
|
|
|
|
Slack (MET) : 0.107ns (arrival time - required time)
|
|
Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/qprod_s4_reg[18]/C
|
|
(rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns})
|
|
Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[18]/D
|
|
(rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns})
|
|
Path Group: mlkem_clk_clk_pll
|
|
Path Type: Hold (Min at Fast Process Corner)
|
|
Requirement: 0.000ns (mlkem_clk_clk_pll rise@0.000ns - mlkem_clk_clk_pll rise@0.000ns)
|
|
Data Path Delay: 0.475ns (logic 0.275ns (57.843%) route 0.200ns (42.157%))
|
|
Logic Levels: 2 (CARRY4=1 LUT2=1)
|
|
Clock Path Skew: 0.264ns (DCD - SCD - CPR)
|
|
Destination Clock Delay (DCD): -0.478ns
|
|
Source Clock Delay (SCD): -0.702ns
|
|
Clock Pessimism Removal (CPR): -0.040ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock mlkem_clk_clk_pll rise edge)
|
|
0.000 0.000 r
|
|
clock source latency -1.848 -1.848
|
|
propagated clock network latency
|
|
1.147 -0.702
|
|
SLICE_X84Y158 FDCE 0.000 -0.702 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/qprod_s4_reg[18]/C
|
|
SLICE_X84Y158 FDCE (Prop_fdce_C_Q) 0.164 -0.538 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/qprod_s4_reg[18]/Q
|
|
net (fo=1, routed) 0.200 -0.337 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/qprod_s4[18]
|
|
SLICE_X83Y158 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5[19]_i_3/I1
|
|
SLICE_X83Y158 LUT2 (Prop_lut2_I1_O) 0.045 -0.292 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5[19]_i_3/O
|
|
net (fo=1, routed) 0.000 -0.292 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5[19]_i_3_n_0
|
|
SLICE_X83Y158 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[19]_i_1/S[2]
|
|
SLICE_X83Y158 CARRY4 (Prop_carry4_S[2]_O[2])
|
|
0.066 -0.226 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[19]_i_1/O[2]
|
|
net (fo=1, routed) 0.000 -0.226 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s50[18]
|
|
SLICE_X83Y158 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[18]/D
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock mlkem_clk_clk_pll rise edge)
|
|
0.000 0.000 r
|
|
clock source latency -1.947 -1.947
|
|
propagated clock network latency
|
|
1.469 -0.478
|
|
clock pessimism 0.040 -0.438
|
|
SLICE_X83Y158 FDCE (Hold_fdce_C_D) 0.105 -0.333 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[18]
|
|
-------------------------------------------------------------------
|
|
required time 0.333
|
|
arrival time -0.226
|
|
-------------------------------------------------------------------
|
|
slack 0.107
|
|
|
|
Slack (MET) : 0.107ns (arrival time - required time)
|
|
Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/qprod_s4_reg[18]/C
|
|
(rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns})
|
|
Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[18]/D
|
|
(rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns})
|
|
Path Group: mlkem_clk_clk_pll
|
|
Path Type: Hold (Min at Fast Process Corner)
|
|
Requirement: 0.000ns (mlkem_clk_clk_pll rise@0.000ns - mlkem_clk_clk_pll rise@0.000ns)
|
|
Data Path Delay: 0.475ns (logic 0.275ns (57.843%) route 0.200ns (42.157%))
|
|
Logic Levels: 2 (CARRY4=1 LUT2=1)
|
|
Clock Path Skew: 0.264ns (DCD - SCD - CPR)
|
|
Destination Clock Delay (DCD): -0.478ns
|
|
Source Clock Delay (SCD): -0.702ns
|
|
Clock Pessimism Removal (CPR): -0.040ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock mlkem_clk_clk_pll rise edge)
|
|
0.000 0.000 r
|
|
clock source latency -1.848 -1.848
|
|
propagated clock network latency
|
|
1.147 -0.702
|
|
SLICE_X84Y158 FDCE 0.000 -0.702 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/qprod_s4_reg[18]/C
|
|
SLICE_X84Y158 FDCE (Prop_fdce_C_Q) 0.164 -0.538 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/qprod_s4_reg[18]/Q
|
|
net (fo=1, routed) 0.200 -0.337 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/qprod_s4[18]
|
|
SLICE_X83Y158 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5[19]_i_3/I1
|
|
SLICE_X83Y158 LUT2 (Prop_lut2_I1_O) 0.045 -0.292 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5[19]_i_3/O
|
|
net (fo=1, routed) 0.000 -0.292 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5[19]_i_3_n_0
|
|
SLICE_X83Y158 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[19]_i_1/S[2]
|
|
SLICE_X83Y158 CARRY4 (Prop_carry4_S[2]_O[2])
|
|
0.066 -0.226 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[19]_i_1/O[2]
|
|
net (fo=1, routed) 0.000 -0.226 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s50[18]
|
|
SLICE_X83Y158 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[18]/D
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock mlkem_clk_clk_pll rise edge)
|
|
0.000 0.000 r
|
|
clock source latency -1.947 -1.947
|
|
propagated clock network latency
|
|
1.469 -0.478
|
|
clock pessimism 0.040 -0.438
|
|
SLICE_X83Y158 FDCE (Hold_fdce_C_D) 0.105 -0.333 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[18]
|
|
-------------------------------------------------------------------
|
|
required time 0.333
|
|
arrival time -0.226
|
|
-------------------------------------------------------------------
|
|
slack 0.107
|
|
|
|
Slack (MET) : 0.107ns (arrival time - required time)
|
|
Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/qprod_s4_reg[18]/C
|
|
(rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns})
|
|
Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[18]/D
|
|
(rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns})
|
|
Path Group: mlkem_clk_clk_pll
|
|
Path Type: Hold (Min at Fast Process Corner)
|
|
Requirement: 0.000ns (mlkem_clk_clk_pll rise@0.000ns - mlkem_clk_clk_pll rise@0.000ns)
|
|
Data Path Delay: 0.475ns (logic 0.275ns (57.843%) route 0.200ns (42.157%))
|
|
Logic Levels: 2 (CARRY4=1 LUT2=1)
|
|
Clock Path Skew: 0.264ns (DCD - SCD - CPR)
|
|
Destination Clock Delay (DCD): -0.478ns
|
|
Source Clock Delay (SCD): -0.702ns
|
|
Clock Pessimism Removal (CPR): -0.040ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock mlkem_clk_clk_pll rise edge)
|
|
0.000 0.000 r
|
|
clock source latency -1.848 -1.848
|
|
propagated clock network latency
|
|
1.147 -0.702
|
|
SLICE_X84Y158 FDCE 0.000 -0.702 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/qprod_s4_reg[18]/C
|
|
SLICE_X84Y158 FDCE (Prop_fdce_C_Q) 0.164 -0.538 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/qprod_s4_reg[18]/Q
|
|
net (fo=1, routed) 0.200 -0.337 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/qprod_s4[18]
|
|
SLICE_X83Y158 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5[19]_i_3/I1
|
|
SLICE_X83Y158 LUT2 (Prop_lut2_I1_O) 0.045 -0.292 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5[19]_i_3/O
|
|
net (fo=1, routed) 0.000 -0.292 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5[19]_i_3_n_0
|
|
SLICE_X83Y158 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[19]_i_1/S[2]
|
|
SLICE_X83Y158 CARRY4 (Prop_carry4_S[2]_O[2])
|
|
0.066 -0.226 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[19]_i_1/O[2]
|
|
net (fo=1, routed) 0.000 -0.226 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s50[18]
|
|
SLICE_X83Y158 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[18]/D
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock mlkem_clk_clk_pll rise edge)
|
|
0.000 0.000 r
|
|
clock source latency -1.947 -1.947
|
|
propagated clock network latency
|
|
1.469 -0.478
|
|
clock pessimism 0.040 -0.438
|
|
SLICE_X83Y158 FDCE (Hold_fdce_C_D) 0.105 -0.333 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[18]
|
|
-------------------------------------------------------------------
|
|
required time 0.333
|
|
arrival time -0.226
|
|
-------------------------------------------------------------------
|
|
slack 0.107
|
|
|
|
Slack (MET) : 0.107ns (arrival time - required time)
|
|
Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/qprod_s4_reg[22]/C
|
|
(rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns})
|
|
Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[22]/D
|
|
(rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns})
|
|
Path Group: mlkem_clk_clk_pll
|
|
Path Type: Hold (Min at Fast Process Corner)
|
|
Requirement: 0.000ns (mlkem_clk_clk_pll rise@0.000ns - mlkem_clk_clk_pll rise@0.000ns)
|
|
Data Path Delay: 0.475ns (logic 0.275ns (57.843%) route 0.200ns (42.157%))
|
|
Logic Levels: 2 (CARRY4=1 LUT2=1)
|
|
Clock Path Skew: 0.264ns (DCD - SCD - CPR)
|
|
Destination Clock Delay (DCD): -0.478ns
|
|
Source Clock Delay (SCD): -0.702ns
|
|
Clock Pessimism Removal (CPR): -0.040ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock mlkem_clk_clk_pll rise edge)
|
|
0.000 0.000 r
|
|
clock source latency -1.848 -1.848
|
|
propagated clock network latency
|
|
1.147 -0.702
|
|
SLICE_X84Y159 FDCE 0.000 -0.702 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/qprod_s4_reg[22]/C
|
|
SLICE_X84Y159 FDCE (Prop_fdce_C_Q) 0.164 -0.538 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/qprod_s4_reg[22]/Q
|
|
net (fo=1, routed) 0.200 -0.337 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/qprod_s4[22]
|
|
SLICE_X83Y159 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5[23]_i_3/I1
|
|
SLICE_X83Y159 LUT2 (Prop_lut2_I1_O) 0.045 -0.292 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5[23]_i_3/O
|
|
net (fo=1, routed) 0.000 -0.292 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5[23]_i_3_n_0
|
|
SLICE_X83Y159 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[23]_i_1/S[2]
|
|
SLICE_X83Y159 CARRY4 (Prop_carry4_S[2]_O[2])
|
|
0.066 -0.226 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[23]_i_1/O[2]
|
|
net (fo=1, routed) 0.000 -0.226 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s50[22]
|
|
SLICE_X83Y159 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[22]/D
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock mlkem_clk_clk_pll rise edge)
|
|
0.000 0.000 r
|
|
clock source latency -1.947 -1.947
|
|
propagated clock network latency
|
|
1.469 -0.478
|
|
clock pessimism 0.040 -0.438
|
|
SLICE_X83Y159 FDCE (Hold_fdce_C_D) 0.105 -0.333 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[22]
|
|
-------------------------------------------------------------------
|
|
required time 0.333
|
|
arrival time -0.226
|
|
-------------------------------------------------------------------
|
|
slack 0.107
|
|
|
|
Slack (MET) : 0.107ns (arrival time - required time)
|
|
Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/qprod_s4_reg[22]/C
|
|
(rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns})
|
|
Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[22]/D
|
|
(rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns})
|
|
Path Group: mlkem_clk_clk_pll
|
|
Path Type: Hold (Min at Fast Process Corner)
|
|
Requirement: 0.000ns (mlkem_clk_clk_pll rise@0.000ns - mlkem_clk_clk_pll rise@0.000ns)
|
|
Data Path Delay: 0.475ns (logic 0.275ns (57.843%) route 0.200ns (42.157%))
|
|
Logic Levels: 2 (CARRY4=1 LUT2=1)
|
|
Clock Path Skew: 0.264ns (DCD - SCD - CPR)
|
|
Destination Clock Delay (DCD): -0.478ns
|
|
Source Clock Delay (SCD): -0.702ns
|
|
Clock Pessimism Removal (CPR): -0.040ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock mlkem_clk_clk_pll rise edge)
|
|
0.000 0.000 r
|
|
clock source latency -1.848 -1.848
|
|
propagated clock network latency
|
|
1.147 -0.702
|
|
SLICE_X84Y159 FDCE 0.000 -0.702 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/qprod_s4_reg[22]/C
|
|
SLICE_X84Y159 FDCE (Prop_fdce_C_Q) 0.164 -0.538 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/qprod_s4_reg[22]/Q
|
|
net (fo=1, routed) 0.200 -0.337 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/qprod_s4[22]
|
|
SLICE_X83Y159 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5[23]_i_3/I1
|
|
SLICE_X83Y159 LUT2 (Prop_lut2_I1_O) 0.045 -0.292 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5[23]_i_3/O
|
|
net (fo=1, routed) 0.000 -0.292 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5[23]_i_3_n_0
|
|
SLICE_X83Y159 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[23]_i_1/S[2]
|
|
SLICE_X83Y159 CARRY4 (Prop_carry4_S[2]_O[2])
|
|
0.066 -0.226 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[23]_i_1/O[2]
|
|
net (fo=1, routed) 0.000 -0.226 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s50[22]
|
|
SLICE_X83Y159 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[22]/D
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock mlkem_clk_clk_pll rise edge)
|
|
0.000 0.000 r
|
|
clock source latency -1.947 -1.947
|
|
propagated clock network latency
|
|
1.469 -0.478
|
|
clock pessimism 0.040 -0.438
|
|
SLICE_X83Y159 FDCE (Hold_fdce_C_D) 0.105 -0.333 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[22]
|
|
-------------------------------------------------------------------
|
|
required time 0.333
|
|
arrival time -0.226
|
|
-------------------------------------------------------------------
|
|
slack 0.107
|
|
|
|
Slack (MET) : 0.107ns (arrival time - required time)
|
|
Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/qprod_s4_reg[22]/C
|
|
(rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns})
|
|
Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[22]/D
|
|
(rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns})
|
|
Path Group: mlkem_clk_clk_pll
|
|
Path Type: Hold (Min at Fast Process Corner)
|
|
Requirement: 0.000ns (mlkem_clk_clk_pll rise@0.000ns - mlkem_clk_clk_pll rise@0.000ns)
|
|
Data Path Delay: 0.475ns (logic 0.275ns (57.843%) route 0.200ns (42.157%))
|
|
Logic Levels: 2 (CARRY4=1 LUT2=1)
|
|
Clock Path Skew: 0.264ns (DCD - SCD - CPR)
|
|
Destination Clock Delay (DCD): -0.478ns
|
|
Source Clock Delay (SCD): -0.702ns
|
|
Clock Pessimism Removal (CPR): -0.040ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock mlkem_clk_clk_pll rise edge)
|
|
0.000 0.000 r
|
|
clock source latency -1.848 -1.848
|
|
propagated clock network latency
|
|
1.147 -0.702
|
|
SLICE_X84Y159 FDCE 0.000 -0.702 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/qprod_s4_reg[22]/C
|
|
SLICE_X84Y159 FDCE (Prop_fdce_C_Q) 0.164 -0.538 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/qprod_s4_reg[22]/Q
|
|
net (fo=1, routed) 0.200 -0.337 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/qprod_s4[22]
|
|
SLICE_X83Y159 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5[23]_i_3/I1
|
|
SLICE_X83Y159 LUT2 (Prop_lut2_I1_O) 0.045 -0.292 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5[23]_i_3/O
|
|
net (fo=1, routed) 0.000 -0.292 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5[23]_i_3_n_0
|
|
SLICE_X83Y159 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[23]_i_1/S[2]
|
|
SLICE_X83Y159 CARRY4 (Prop_carry4_S[2]_O[2])
|
|
0.066 -0.226 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[23]_i_1/O[2]
|
|
net (fo=1, routed) 0.000 -0.226 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s50[22]
|
|
SLICE_X83Y159 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[22]/D
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock mlkem_clk_clk_pll rise edge)
|
|
0.000 0.000 r
|
|
clock source latency -1.947 -1.947
|
|
propagated clock network latency
|
|
1.469 -0.478
|
|
clock pessimism 0.040 -0.438
|
|
SLICE_X83Y159 FDCE (Hold_fdce_C_D) 0.105 -0.333 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[22]
|
|
-------------------------------------------------------------------
|
|
required time 0.333
|
|
arrival time -0.226
|
|
-------------------------------------------------------------------
|
|
slack 0.107
|
|
|
|
Slack (MET) : 0.107ns (arrival time - required time)
|
|
Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/qprod_s4_reg[22]/C
|
|
(rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns})
|
|
Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[22]/D
|
|
(rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns})
|
|
Path Group: mlkem_clk_clk_pll
|
|
Path Type: Hold (Min at Fast Process Corner)
|
|
Requirement: 0.000ns (mlkem_clk_clk_pll rise@0.000ns - mlkem_clk_clk_pll rise@0.000ns)
|
|
Data Path Delay: 0.475ns (logic 0.275ns (57.843%) route 0.200ns (42.157%))
|
|
Logic Levels: 2 (CARRY4=1 LUT2=1)
|
|
Clock Path Skew: 0.264ns (DCD - SCD - CPR)
|
|
Destination Clock Delay (DCD): -0.478ns
|
|
Source Clock Delay (SCD): -0.702ns
|
|
Clock Pessimism Removal (CPR): -0.040ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock mlkem_clk_clk_pll rise edge)
|
|
0.000 0.000 r
|
|
clock source latency -1.848 -1.848
|
|
propagated clock network latency
|
|
1.147 -0.702
|
|
SLICE_X84Y159 FDCE 0.000 -0.702 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/qprod_s4_reg[22]/C
|
|
SLICE_X84Y159 FDCE (Prop_fdce_C_Q) 0.164 -0.538 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/qprod_s4_reg[22]/Q
|
|
net (fo=1, routed) 0.200 -0.337 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/qprod_s4[22]
|
|
SLICE_X83Y159 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5[23]_i_3/I1
|
|
SLICE_X83Y159 LUT2 (Prop_lut2_I1_O) 0.045 -0.292 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5[23]_i_3/O
|
|
net (fo=1, routed) 0.000 -0.292 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5[23]_i_3_n_0
|
|
SLICE_X83Y159 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[23]_i_1/S[2]
|
|
SLICE_X83Y159 CARRY4 (Prop_carry4_S[2]_O[2])
|
|
0.066 -0.226 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[23]_i_1/O[2]
|
|
net (fo=1, routed) 0.000 -0.226 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s50[22]
|
|
SLICE_X83Y159 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[22]/D
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock mlkem_clk_clk_pll rise edge)
|
|
0.000 0.000 r
|
|
clock source latency -1.947 -1.947
|
|
propagated clock network latency
|
|
1.469 -0.478
|
|
clock pessimism 0.040 -0.438
|
|
SLICE_X83Y159 FDCE (Hold_fdce_C_D) 0.105 -0.333 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[22]
|
|
-------------------------------------------------------------------
|
|
required time 0.333
|
|
arrival time -0.226
|
|
-------------------------------------------------------------------
|
|
slack 0.107
|
|
|
|
Slack (MET) : 0.107ns (arrival time - required time)
|
|
Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/qprod_s4_reg[22]/C
|
|
(rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns})
|
|
Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[22]/D
|
|
(rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns})
|
|
Path Group: mlkem_clk_clk_pll
|
|
Path Type: Hold (Min at Fast Process Corner)
|
|
Requirement: 0.000ns (mlkem_clk_clk_pll rise@0.000ns - mlkem_clk_clk_pll rise@0.000ns)
|
|
Data Path Delay: 0.475ns (logic 0.275ns (57.843%) route 0.200ns (42.157%))
|
|
Logic Levels: 2 (CARRY4=1 LUT2=1)
|
|
Clock Path Skew: 0.264ns (DCD - SCD - CPR)
|
|
Destination Clock Delay (DCD): -0.478ns
|
|
Source Clock Delay (SCD): -0.702ns
|
|
Clock Pessimism Removal (CPR): -0.040ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock mlkem_clk_clk_pll rise edge)
|
|
0.000 0.000 r
|
|
clock source latency -1.848 -1.848
|
|
propagated clock network latency
|
|
1.147 -0.702
|
|
SLICE_X84Y159 FDCE 0.000 -0.702 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/qprod_s4_reg[22]/C
|
|
SLICE_X84Y159 FDCE (Prop_fdce_C_Q) 0.164 -0.538 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/qprod_s4_reg[22]/Q
|
|
net (fo=1, routed) 0.200 -0.337 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/qprod_s4[22]
|
|
SLICE_X83Y159 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5[23]_i_3/I1
|
|
SLICE_X83Y159 LUT2 (Prop_lut2_I1_O) 0.045 -0.292 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5[23]_i_3/O
|
|
net (fo=1, routed) 0.000 -0.292 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5[23]_i_3_n_0
|
|
SLICE_X83Y159 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[23]_i_1/S[2]
|
|
SLICE_X83Y159 CARRY4 (Prop_carry4_S[2]_O[2])
|
|
0.066 -0.226 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[23]_i_1/O[2]
|
|
net (fo=1, routed) 0.000 -0.226 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s50[22]
|
|
SLICE_X83Y159 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[22]/D
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock mlkem_clk_clk_pll rise edge)
|
|
0.000 0.000 r
|
|
clock source latency -1.947 -1.947
|
|
propagated clock network latency
|
|
1.469 -0.478
|
|
clock pessimism 0.040 -0.438
|
|
SLICE_X83Y159 FDCE (Hold_fdce_C_D) 0.105 -0.333 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[22]
|
|
-------------------------------------------------------------------
|
|
required time 0.333
|
|
arrival time -0.226
|
|
-------------------------------------------------------------------
|
|
slack 0.107
|
|
|
|
Slack (MET) : 0.107ns (arrival time - required time)
|
|
Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/qprod_s4_reg[22]/C
|
|
(rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns})
|
|
Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[22]/D
|
|
(rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns})
|
|
Path Group: mlkem_clk_clk_pll
|
|
Path Type: Hold (Min at Fast Process Corner)
|
|
Requirement: 0.000ns (mlkem_clk_clk_pll rise@0.000ns - mlkem_clk_clk_pll rise@0.000ns)
|
|
Data Path Delay: 0.475ns (logic 0.275ns (57.843%) route 0.200ns (42.157%))
|
|
Logic Levels: 2 (CARRY4=1 LUT2=1)
|
|
Clock Path Skew: 0.264ns (DCD - SCD - CPR)
|
|
Destination Clock Delay (DCD): -0.478ns
|
|
Source Clock Delay (SCD): -0.702ns
|
|
Clock Pessimism Removal (CPR): -0.040ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock mlkem_clk_clk_pll rise edge)
|
|
0.000 0.000 r
|
|
clock source latency -1.848 -1.848
|
|
propagated clock network latency
|
|
1.147 -0.702
|
|
SLICE_X84Y159 FDCE 0.000 -0.702 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/qprod_s4_reg[22]/C
|
|
SLICE_X84Y159 FDCE (Prop_fdce_C_Q) 0.164 -0.538 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/qprod_s4_reg[22]/Q
|
|
net (fo=1, routed) 0.200 -0.337 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/qprod_s4[22]
|
|
SLICE_X83Y159 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5[23]_i_3/I1
|
|
SLICE_X83Y159 LUT2 (Prop_lut2_I1_O) 0.045 -0.292 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5[23]_i_3/O
|
|
net (fo=1, routed) 0.000 -0.292 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5[23]_i_3_n_0
|
|
SLICE_X83Y159 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[23]_i_1/S[2]
|
|
SLICE_X83Y159 CARRY4 (Prop_carry4_S[2]_O[2])
|
|
0.066 -0.226 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[23]_i_1/O[2]
|
|
net (fo=1, routed) 0.000 -0.226 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s50[22]
|
|
SLICE_X83Y159 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[22]/D
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock mlkem_clk_clk_pll rise edge)
|
|
0.000 0.000 r
|
|
clock source latency -1.947 -1.947
|
|
propagated clock network latency
|
|
1.469 -0.478
|
|
clock pessimism 0.040 -0.438
|
|
SLICE_X83Y159 FDCE (Hold_fdce_C_D) 0.105 -0.333 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[22]
|
|
-------------------------------------------------------------------
|
|
required time 0.333
|
|
arrival time -0.226
|
|
-------------------------------------------------------------------
|
|
slack 0.107
|
|
|
|
Slack (MET) : 0.107ns (arrival time - required time)
|
|
Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/qprod_s4_reg[22]/C
|
|
(rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns})
|
|
Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[22]/D
|
|
(rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns})
|
|
Path Group: mlkem_clk_clk_pll
|
|
Path Type: Hold (Min at Fast Process Corner)
|
|
Requirement: 0.000ns (mlkem_clk_clk_pll rise@0.000ns - mlkem_clk_clk_pll rise@0.000ns)
|
|
Data Path Delay: 0.475ns (logic 0.275ns (57.843%) route 0.200ns (42.157%))
|
|
Logic Levels: 2 (CARRY4=1 LUT2=1)
|
|
Clock Path Skew: 0.264ns (DCD - SCD - CPR)
|
|
Destination Clock Delay (DCD): -0.478ns
|
|
Source Clock Delay (SCD): -0.702ns
|
|
Clock Pessimism Removal (CPR): -0.040ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock mlkem_clk_clk_pll rise edge)
|
|
0.000 0.000 r
|
|
clock source latency -1.848 -1.848
|
|
propagated clock network latency
|
|
1.147 -0.702
|
|
SLICE_X84Y159 FDCE 0.000 -0.702 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/qprod_s4_reg[22]/C
|
|
SLICE_X84Y159 FDCE (Prop_fdce_C_Q) 0.164 -0.538 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/qprod_s4_reg[22]/Q
|
|
net (fo=1, routed) 0.200 -0.337 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/qprod_s4[22]
|
|
SLICE_X83Y159 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5[23]_i_3/I1
|
|
SLICE_X83Y159 LUT2 (Prop_lut2_I1_O) 0.045 -0.292 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5[23]_i_3/O
|
|
net (fo=1, routed) 0.000 -0.292 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5[23]_i_3_n_0
|
|
SLICE_X83Y159 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[23]_i_1/S[2]
|
|
SLICE_X83Y159 CARRY4 (Prop_carry4_S[2]_O[2])
|
|
0.066 -0.226 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[23]_i_1/O[2]
|
|
net (fo=1, routed) 0.000 -0.226 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s50[22]
|
|
SLICE_X83Y159 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[22]/D
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock mlkem_clk_clk_pll rise edge)
|
|
0.000 0.000 r
|
|
clock source latency -1.947 -1.947
|
|
propagated clock network latency
|
|
1.469 -0.478
|
|
clock pessimism 0.040 -0.438
|
|
SLICE_X83Y159 FDCE (Hold_fdce_C_D) 0.105 -0.333 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[22]
|
|
-------------------------------------------------------------------
|
|
required time 0.333
|
|
arrival time -0.226
|
|
-------------------------------------------------------------------
|
|
slack 0.107
|
|
|
|
Slack (MET) : 0.107ns (arrival time - required time)
|
|
Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/qprod_s4_reg[22]/C
|
|
(rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns})
|
|
Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[22]/D
|
|
(rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns})
|
|
Path Group: mlkem_clk_clk_pll
|
|
Path Type: Hold (Min at Fast Process Corner)
|
|
Requirement: 0.000ns (mlkem_clk_clk_pll rise@0.000ns - mlkem_clk_clk_pll rise@0.000ns)
|
|
Data Path Delay: 0.475ns (logic 0.275ns (57.843%) route 0.200ns (42.157%))
|
|
Logic Levels: 2 (CARRY4=1 LUT2=1)
|
|
Clock Path Skew: 0.264ns (DCD - SCD - CPR)
|
|
Destination Clock Delay (DCD): -0.478ns
|
|
Source Clock Delay (SCD): -0.702ns
|
|
Clock Pessimism Removal (CPR): -0.040ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock mlkem_clk_clk_pll rise edge)
|
|
0.000 0.000 r
|
|
clock source latency -1.848 -1.848
|
|
propagated clock network latency
|
|
1.147 -0.702
|
|
SLICE_X84Y159 FDCE 0.000 -0.702 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/qprod_s4_reg[22]/C
|
|
SLICE_X84Y159 FDCE (Prop_fdce_C_Q) 0.164 -0.538 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/qprod_s4_reg[22]/Q
|
|
net (fo=1, routed) 0.200 -0.337 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/qprod_s4[22]
|
|
SLICE_X83Y159 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5[23]_i_3/I1
|
|
SLICE_X83Y159 LUT2 (Prop_lut2_I1_O) 0.045 -0.292 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5[23]_i_3/O
|
|
net (fo=1, routed) 0.000 -0.292 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5[23]_i_3_n_0
|
|
SLICE_X83Y159 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[23]_i_1/S[2]
|
|
SLICE_X83Y159 CARRY4 (Prop_carry4_S[2]_O[2])
|
|
0.066 -0.226 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[23]_i_1/O[2]
|
|
net (fo=1, routed) 0.000 -0.226 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s50[22]
|
|
SLICE_X83Y159 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[22]/D
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock mlkem_clk_clk_pll rise edge)
|
|
0.000 0.000 r
|
|
clock source latency -1.947 -1.947
|
|
propagated clock network latency
|
|
1.469 -0.478
|
|
clock pessimism 0.040 -0.438
|
|
SLICE_X83Y159 FDCE (Hold_fdce_C_D) 0.105 -0.333 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[22]
|
|
-------------------------------------------------------------------
|
|
required time 0.333
|
|
arrival time -0.226
|
|
-------------------------------------------------------------------
|
|
slack 0.107
|
|
|
|
Slack (MET) : 0.107ns (arrival time - required time)
|
|
Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/wb_a_data_r_reg[8]/C
|
|
(rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns})
|
|
Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/cr_reg[240][8]/D
|
|
(rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns})
|
|
Path Group: mlkem_clk_clk_pll
|
|
Path Type: Hold (Min at Fast Process Corner)
|
|
Requirement: 0.000ns (mlkem_clk_clk_pll rise@0.000ns - mlkem_clk_clk_pll rise@0.000ns)
|
|
Data Path Delay: 0.508ns (logic 0.186ns (36.603%) route 0.322ns (63.397%))
|
|
Logic Levels: 1 (LUT6=1)
|
|
Clock Path Skew: 0.280ns (DCD - SCD - CPR)
|
|
Destination Clock Delay (DCD): -0.458ns
|
|
Source Clock Delay (SCD): -0.693ns
|
|
Clock Pessimism Removal (CPR): -0.045ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock mlkem_clk_clk_pll rise edge)
|
|
0.000 0.000 r
|
|
clock source latency -1.848 -1.848
|
|
propagated clock network latency
|
|
1.156 -0.693
|
|
SLICE_X89Y154 FDCE 0.000 -0.693 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/wb_a_data_r_reg[8]/C
|
|
SLICE_X89Y154 FDCE (Prop_fdce_C_Q) 0.141 -0.552 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/wb_a_data_r_reg[8]/Q
|
|
net (fo=234, routed) 0.322 -0.230 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/wb_a_data_r[8]
|
|
SLICE_X90Y147 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/cr[240][8]_i_1/I3
|
|
SLICE_X90Y147 LUT6 (Prop_lut6_I3_O) 0.045 -0.185 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/cr[240][8]_i_1/O
|
|
net (fo=1, routed) 0.000 -0.185 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/cr[240][8]_i_1_n_0
|
|
SLICE_X90Y147 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/cr_reg[240][8]/D
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock mlkem_clk_clk_pll rise edge)
|
|
0.000 0.000 r
|
|
clock source latency -1.947 -1.947
|
|
propagated clock network latency
|
|
1.489 -0.458
|
|
clock pessimism 0.045 -0.413
|
|
SLICE_X90Y147 FDCE (Hold_fdce_C_D) 0.121 -0.292 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/cr_reg[240][8]
|
|
-------------------------------------------------------------------
|
|
required time 0.292
|
|
arrival time -0.185
|
|
-------------------------------------------------------------------
|
|
slack 0.107
|
|
|
|
Slack (MET) : 0.107ns (arrival time - required time)
|
|
Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/wb_a_data_r_reg[8]/C
|
|
(rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns})
|
|
Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/cr_reg[240][8]/D
|
|
(rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns})
|
|
Path Group: mlkem_clk_clk_pll
|
|
Path Type: Hold (Min at Fast Process Corner)
|
|
Requirement: 0.000ns (mlkem_clk_clk_pll rise@0.000ns - mlkem_clk_clk_pll rise@0.000ns)
|
|
Data Path Delay: 0.508ns (logic 0.186ns (36.603%) route 0.322ns (63.397%))
|
|
Logic Levels: 1 (LUT6=1)
|
|
Clock Path Skew: 0.280ns (DCD - SCD - CPR)
|
|
Destination Clock Delay (DCD): -0.458ns
|
|
Source Clock Delay (SCD): -0.693ns
|
|
Clock Pessimism Removal (CPR): -0.045ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock mlkem_clk_clk_pll rise edge)
|
|
0.000 0.000 r
|
|
clock source latency -1.848 -1.848
|
|
propagated clock network latency
|
|
1.156 -0.693
|
|
SLICE_X89Y154 FDCE 0.000 -0.693 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/wb_a_data_r_reg[8]/C
|
|
SLICE_X89Y154 FDCE (Prop_fdce_C_Q) 0.141 -0.552 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/wb_a_data_r_reg[8]/Q
|
|
net (fo=234, routed) 0.322 -0.230 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/wb_a_data_r[8]
|
|
SLICE_X90Y147 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/cr[240][8]_i_1/I3
|
|
SLICE_X90Y147 LUT6 (Prop_lut6_I3_O) 0.045 -0.185 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/cr[240][8]_i_1/O
|
|
net (fo=1, routed) 0.000 -0.185 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/cr[240][8]_i_1_n_0
|
|
SLICE_X90Y147 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/cr_reg[240][8]/D
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock mlkem_clk_clk_pll rise edge)
|
|
0.000 0.000 r
|
|
clock source latency -1.947 -1.947
|
|
propagated clock network latency
|
|
1.489 -0.458
|
|
clock pessimism 0.045 -0.413
|
|
SLICE_X90Y147 FDCE (Hold_fdce_C_D) 0.121 -0.292 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/cr_reg[240][8]
|
|
-------------------------------------------------------------------
|
|
required time 0.292
|
|
arrival time -0.185
|
|
-------------------------------------------------------------------
|
|
slack 0.107
|
|
|
|
Slack (MET) : 0.108ns (arrival time - required time)
|
|
Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_12_17/RAMB_D1/CLK
|
|
(rising edge-triggered cell RAMD32 clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns})
|
|
Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[15]/D
|
|
(rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Path Group: sys_clk
|
|
Path Type: Hold (Min at Fast Process Corner)
|
|
Requirement: 0.000ns (sys_clk rise@0.000ns - mlkem_clk_clk_pll rise@0.000ns)
|
|
Data Path Delay: 0.707ns (logic 0.388ns (54.849%) route 0.319ns (45.151%))
|
|
Logic Levels: 0
|
|
Clock Path Skew: 0.333ns (DCD - SCD - CPR)
|
|
Destination Clock Delay (DCD): -0.392ns
|
|
Source Clock Delay (SCD): -0.626ns
|
|
Clock Pessimism Removal (CPR): -0.099ns
|
|
Clock Uncertainty: 0.197ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Discrete Jitter (DJ): 0.136ns
|
|
Phase Error (PE): 0.120ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock mlkem_clk_clk_pll rise edge)
|
|
0.000 0.000 r
|
|
clock source latency -1.848 -1.848
|
|
propagated clock network latency
|
|
1.222 -0.626
|
|
SLICE_X64Y76 RAMD32 0.000 -0.626 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_12_17/RAMB_D1/CLK
|
|
SLICE_X64Y76 RAMD32 (Prop_ramd32_CLK_O)
|
|
0.388 -0.238 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_12_17/RAMB_D1/O
|
|
net (fo=1, routed) 0.319 0.081 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port10__3[15]
|
|
SLICE_X57Y78 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[15]/D
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock sys_clk rise edge) 0.000 0.000 r
|
|
clock source latency -1.947 -1.947
|
|
propagated clock network latency
|
|
1.555 -0.392
|
|
clock pessimism 0.099 -0.293
|
|
clock uncertainty 0.197 -0.097
|
|
SLICE_X57Y78 FDRE (Hold_fdre_C_D) 0.070 -0.027 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[15]
|
|
-------------------------------------------------------------------
|
|
required time 0.027
|
|
arrival time 0.081
|
|
-------------------------------------------------------------------
|
|
slack 0.108
|
|
|
|
Slack (MET) : 0.108ns (arrival time - required time)
|
|
Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_12_17/RAMB_D1/CLK
|
|
(rising edge-triggered cell RAMD32 clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns})
|
|
Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[15]/D
|
|
(rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Path Group: sys_clk
|
|
Path Type: Hold (Min at Fast Process Corner)
|
|
Requirement: 0.000ns (sys_clk rise@0.000ns - mlkem_clk_clk_pll rise@0.000ns)
|
|
Data Path Delay: 0.707ns (logic 0.388ns (54.849%) route 0.319ns (45.151%))
|
|
Logic Levels: 0
|
|
Clock Path Skew: 0.333ns (DCD - SCD - CPR)
|
|
Destination Clock Delay (DCD): -0.392ns
|
|
Source Clock Delay (SCD): -0.626ns
|
|
Clock Pessimism Removal (CPR): -0.099ns
|
|
Clock Uncertainty: 0.197ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Discrete Jitter (DJ): 0.136ns
|
|
Phase Error (PE): 0.120ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock mlkem_clk_clk_pll rise edge)
|
|
0.000 0.000 r
|
|
clock source latency -1.848 -1.848
|
|
propagated clock network latency
|
|
1.222 -0.626
|
|
SLICE_X64Y76 RAMD32 0.000 -0.626 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_12_17/RAMB_D1/CLK
|
|
SLICE_X64Y76 RAMD32 (Prop_ramd32_CLK_O)
|
|
0.388 -0.238 f u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_12_17/RAMB_D1/O
|
|
net (fo=1, routed) 0.319 0.081 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port10__3[15]
|
|
SLICE_X57Y78 FDRE f u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[15]/D
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock sys_clk rise edge) 0.000 0.000 r
|
|
clock source latency -1.947 -1.947
|
|
propagated clock network latency
|
|
1.555 -0.392
|
|
clock pessimism 0.099 -0.293
|
|
clock uncertainty 0.197 -0.097
|
|
SLICE_X57Y78 FDRE (Hold_fdre_C_D) 0.070 -0.027 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[15]
|
|
-------------------------------------------------------------------
|
|
required time 0.027
|
|
arrival time 0.081
|
|
-------------------------------------------------------------------
|
|
slack 0.108
|
|
|
|
Slack (MET) : 0.108ns (arrival time - required time)
|
|
Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/ram_reg_0_3_30_35/RAMC/CLK
|
|
(rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/_zz_ram_port1_reg[34]/D
|
|
(rising edge-triggered cell FDRE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns})
|
|
Path Group: mlkem_clk_clk_pll
|
|
Path Type: Hold (Min at Fast Process Corner)
|
|
Requirement: 0.000ns (mlkem_clk_clk_pll rise@0.000ns - sys_clk rise@0.000ns)
|
|
Data Path Delay: 0.633ns (logic 0.390ns (61.631%) route 0.243ns (38.369%))
|
|
Logic Levels: 0
|
|
Clock Path Skew: 0.326ns (DCD - SCD - CPR)
|
|
Destination Clock Delay (DCD): -0.353ns
|
|
Source Clock Delay (SCD): -0.580ns
|
|
Clock Pessimism Removal (CPR): -0.099ns
|
|
Clock Uncertainty: 0.197ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Discrete Jitter (DJ): 0.136ns
|
|
Phase Error (PE): 0.120ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock sys_clk rise edge) 0.000 0.000 r
|
|
clock source latency -1.848 -1.848
|
|
propagated clock network latency
|
|
1.268 -0.580
|
|
SLICE_X22Y71 RAMD32 0.000 -0.580 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/ram_reg_0_3_30_35/RAMC/CLK
|
|
SLICE_X22Y71 RAMD32 (Prop_ramd32_CLK_O)
|
|
0.390 -0.190 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/ram_reg_0_3_30_35/RAMC/O
|
|
net (fo=1, routed) 0.243 0.052 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/_zz_ram_port10[34]
|
|
SLICE_X25Y70 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/_zz_ram_port1_reg[34]/D
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock mlkem_clk_clk_pll rise edge)
|
|
0.000 0.000 r
|
|
clock source latency -1.947 -1.947
|
|
propagated clock network latency
|
|
1.594 -0.353
|
|
clock pessimism 0.099 -0.254
|
|
clock uncertainty 0.197 -0.058
|
|
SLICE_X25Y70 FDRE (Hold_fdre_C_D) 0.002 -0.056 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/_zz_ram_port1_reg[34]
|
|
-------------------------------------------------------------------
|
|
required time 0.056
|
|
arrival time 0.052
|
|
-------------------------------------------------------------------
|
|
slack 0.108
|
|
|
|
Slack (MET) : 0.108ns (arrival time - required time)
|
|
Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/ram_reg_0_3_30_35/RAMC/CLK
|
|
(rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/_zz_ram_port1_reg[34]/D
|
|
(rising edge-triggered cell FDRE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns})
|
|
Path Group: mlkem_clk_clk_pll
|
|
Path Type: Hold (Min at Fast Process Corner)
|
|
Requirement: 0.000ns (mlkem_clk_clk_pll rise@0.000ns - sys_clk rise@0.000ns)
|
|
Data Path Delay: 0.633ns (logic 0.390ns (61.631%) route 0.243ns (38.369%))
|
|
Logic Levels: 0
|
|
Clock Path Skew: 0.326ns (DCD - SCD - CPR)
|
|
Destination Clock Delay (DCD): -0.353ns
|
|
Source Clock Delay (SCD): -0.580ns
|
|
Clock Pessimism Removal (CPR): -0.099ns
|
|
Clock Uncertainty: 0.197ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Discrete Jitter (DJ): 0.136ns
|
|
Phase Error (PE): 0.120ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock sys_clk rise edge) 0.000 0.000 r
|
|
clock source latency -1.848 -1.848
|
|
propagated clock network latency
|
|
1.268 -0.580
|
|
SLICE_X22Y71 RAMD32 0.000 -0.580 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/ram_reg_0_3_30_35/RAMC/CLK
|
|
SLICE_X22Y71 RAMD32 (Prop_ramd32_CLK_O)
|
|
0.390 -0.190 f u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/ram_reg_0_3_30_35/RAMC/O
|
|
net (fo=1, routed) 0.243 0.052 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/_zz_ram_port10[34]
|
|
SLICE_X25Y70 FDRE f u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/_zz_ram_port1_reg[34]/D
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock mlkem_clk_clk_pll rise edge)
|
|
0.000 0.000 r
|
|
clock source latency -1.947 -1.947
|
|
propagated clock network latency
|
|
1.594 -0.353
|
|
clock pessimism 0.099 -0.254
|
|
clock uncertainty 0.197 -0.058
|
|
SLICE_X25Y70 FDRE (Hold_fdre_C_D) 0.002 -0.056 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/_zz_ram_port1_reg[34]
|
|
-------------------------------------------------------------------
|
|
required time 0.056
|
|
arrival time 0.052
|
|
-------------------------------------------------------------------
|
|
slack 0.108
|
|
|
|
Slack (MET) : 0.108ns (arrival time - required time)
|
|
Source: u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/top_reg[2]/C
|
|
(rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Destination: u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/tfifo/ram_reg_0_15_0_5/RAMA/WADR2
|
|
(rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Path Group: sys_clk
|
|
Path Type: Hold (Min at Fast Process Corner)
|
|
Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns)
|
|
Data Path Delay: 0.379ns (logic 0.164ns (43.254%) route 0.215ns (56.746%))
|
|
Logic Levels: 0
|
|
Clock Path Skew: 0.017ns (DCD - SCD - CPR)
|
|
Destination Clock Delay (DCD): -0.310ns
|
|
Source Clock Delay (SCD): -0.543ns
|
|
Clock Pessimism Removal (CPR): 0.216ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock sys_clk rise edge) 0.000 0.000 r
|
|
clock source latency -1.848 -1.848
|
|
propagated clock network latency
|
|
1.305 -0.543
|
|
SLICE_X6Y62 FDRE 0.000 -0.543 r u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/top_reg[2]/C
|
|
SLICE_X6Y62 FDRE (Prop_fdre_C_Q) 0.164 -0.379 r u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/top_reg[2]/Q
|
|
net (fo=18, routed) 0.215 -0.164 u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/tfifo/ram_reg_0_15_0_5/ADDRD2
|
|
SLICE_X6Y61 RAMD32 r u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/tfifo/ram_reg_0_15_0_5/RAMA/WADR2
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock sys_clk rise edge) 0.000 0.000 r
|
|
clock source latency -1.947 -1.947
|
|
propagated clock network latency
|
|
1.637 -0.310
|
|
clock pessimism -0.216 -0.526
|
|
SLICE_X6Y61 RAMD32 (Hold_ramd32_CLK_WADR2)
|
|
0.254 -0.272 u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/tfifo/ram_reg_0_15_0_5/RAMA
|
|
-------------------------------------------------------------------
|
|
required time 0.272
|
|
arrival time -0.164
|
|
-------------------------------------------------------------------
|
|
slack 0.108
|
|
|
|
Slack (MET) : 0.108ns (arrival time - required time)
|
|
Source: u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/top_reg[2]/C
|
|
(rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Destination: u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/tfifo/ram_reg_0_15_0_5/RAMA/WADR2
|
|
(rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Path Group: sys_clk
|
|
Path Type: Hold (Min at Fast Process Corner)
|
|
Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns)
|
|
Data Path Delay: 0.379ns (logic 0.164ns (43.254%) route 0.215ns (56.746%))
|
|
Logic Levels: 0
|
|
Clock Path Skew: 0.017ns (DCD - SCD - CPR)
|
|
Destination Clock Delay (DCD): -0.310ns
|
|
Source Clock Delay (SCD): -0.543ns
|
|
Clock Pessimism Removal (CPR): 0.216ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock sys_clk rise edge) 0.000 0.000 r
|
|
clock source latency -1.848 -1.848
|
|
propagated clock network latency
|
|
1.305 -0.543
|
|
SLICE_X6Y62 FDRE 0.000 -0.543 r u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/top_reg[2]/C
|
|
SLICE_X6Y62 FDRE (Prop_fdre_C_Q) 0.164 -0.379 f u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/top_reg[2]/Q
|
|
net (fo=18, routed) 0.215 -0.164 u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/tfifo/ram_reg_0_15_0_5/ADDRD2
|
|
SLICE_X6Y61 RAMD32 f u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/tfifo/ram_reg_0_15_0_5/RAMA/WADR2
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock sys_clk rise edge) 0.000 0.000 r
|
|
clock source latency -1.947 -1.947
|
|
propagated clock network latency
|
|
1.637 -0.310
|
|
clock pessimism -0.216 -0.526
|
|
SLICE_X6Y61 RAMD32 (Hold_ramd32_CLK_WADR2)
|
|
0.254 -0.272 u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/tfifo/ram_reg_0_15_0_5/RAMA
|
|
-------------------------------------------------------------------
|
|
required time 0.272
|
|
arrival time -0.164
|
|
-------------------------------------------------------------------
|
|
slack 0.108
|
|
|
|
Slack (MET) : 0.108ns (arrival time - required time)
|
|
Source: u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/top_reg[2]/C
|
|
(rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Destination: u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/tfifo/ram_reg_0_15_0_5/RAMA_D1/WADR2
|
|
(rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Path Group: sys_clk
|
|
Path Type: Hold (Min at Fast Process Corner)
|
|
Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns)
|
|
Data Path Delay: 0.379ns (logic 0.164ns (43.254%) route 0.215ns (56.746%))
|
|
Logic Levels: 0
|
|
Clock Path Skew: 0.017ns (DCD - SCD - CPR)
|
|
Destination Clock Delay (DCD): -0.310ns
|
|
Source Clock Delay (SCD): -0.543ns
|
|
Clock Pessimism Removal (CPR): 0.216ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock sys_clk rise edge) 0.000 0.000 r
|
|
clock source latency -1.848 -1.848
|
|
propagated clock network latency
|
|
1.305 -0.543
|
|
SLICE_X6Y62 FDRE 0.000 -0.543 r u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/top_reg[2]/C
|
|
SLICE_X6Y62 FDRE (Prop_fdre_C_Q) 0.164 -0.379 r u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/top_reg[2]/Q
|
|
net (fo=18, routed) 0.215 -0.164 u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/tfifo/ram_reg_0_15_0_5/ADDRD2
|
|
SLICE_X6Y61 RAMD32 r u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/tfifo/ram_reg_0_15_0_5/RAMA_D1/WADR2
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock sys_clk rise edge) 0.000 0.000 r
|
|
clock source latency -1.947 -1.947
|
|
propagated clock network latency
|
|
1.637 -0.310
|
|
clock pessimism -0.216 -0.526
|
|
SLICE_X6Y61 RAMD32 (Hold_ramd32_CLK_WADR2)
|
|
0.254 -0.272 u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/tfifo/ram_reg_0_15_0_5/RAMA_D1
|
|
-------------------------------------------------------------------
|
|
required time 0.272
|
|
arrival time -0.164
|
|
-------------------------------------------------------------------
|
|
slack 0.108
|
|
|
|
Slack (MET) : 0.108ns (arrival time - required time)
|
|
Source: u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/top_reg[2]/C
|
|
(rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Destination: u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/tfifo/ram_reg_0_15_0_5/RAMA_D1/WADR2
|
|
(rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Path Group: sys_clk
|
|
Path Type: Hold (Min at Fast Process Corner)
|
|
Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns)
|
|
Data Path Delay: 0.379ns (logic 0.164ns (43.254%) route 0.215ns (56.746%))
|
|
Logic Levels: 0
|
|
Clock Path Skew: 0.017ns (DCD - SCD - CPR)
|
|
Destination Clock Delay (DCD): -0.310ns
|
|
Source Clock Delay (SCD): -0.543ns
|
|
Clock Pessimism Removal (CPR): 0.216ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock sys_clk rise edge) 0.000 0.000 r
|
|
clock source latency -1.848 -1.848
|
|
propagated clock network latency
|
|
1.305 -0.543
|
|
SLICE_X6Y62 FDRE 0.000 -0.543 r u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/top_reg[2]/C
|
|
SLICE_X6Y62 FDRE (Prop_fdre_C_Q) 0.164 -0.379 f u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/top_reg[2]/Q
|
|
net (fo=18, routed) 0.215 -0.164 u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/tfifo/ram_reg_0_15_0_5/ADDRD2
|
|
SLICE_X6Y61 RAMD32 f u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/tfifo/ram_reg_0_15_0_5/RAMA_D1/WADR2
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock sys_clk rise edge) 0.000 0.000 r
|
|
clock source latency -1.947 -1.947
|
|
propagated clock network latency
|
|
1.637 -0.310
|
|
clock pessimism -0.216 -0.526
|
|
SLICE_X6Y61 RAMD32 (Hold_ramd32_CLK_WADR2)
|
|
0.254 -0.272 u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/tfifo/ram_reg_0_15_0_5/RAMA_D1
|
|
-------------------------------------------------------------------
|
|
required time 0.272
|
|
arrival time -0.164
|
|
-------------------------------------------------------------------
|
|
slack 0.108
|
|
|
|
Slack (MET) : 0.108ns (arrival time - required time)
|
|
Source: u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/top_reg[2]/C
|
|
(rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Destination: u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/tfifo/ram_reg_0_15_0_5/RAMB/WADR2
|
|
(rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Path Group: sys_clk
|
|
Path Type: Hold (Min at Fast Process Corner)
|
|
Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns)
|
|
Data Path Delay: 0.379ns (logic 0.164ns (43.254%) route 0.215ns (56.746%))
|
|
Logic Levels: 0
|
|
Clock Path Skew: 0.017ns (DCD - SCD - CPR)
|
|
Destination Clock Delay (DCD): -0.310ns
|
|
Source Clock Delay (SCD): -0.543ns
|
|
Clock Pessimism Removal (CPR): 0.216ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock sys_clk rise edge) 0.000 0.000 r
|
|
clock source latency -1.848 -1.848
|
|
propagated clock network latency
|
|
1.305 -0.543
|
|
SLICE_X6Y62 FDRE 0.000 -0.543 r u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/top_reg[2]/C
|
|
SLICE_X6Y62 FDRE (Prop_fdre_C_Q) 0.164 -0.379 r u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/top_reg[2]/Q
|
|
net (fo=18, routed) 0.215 -0.164 u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/tfifo/ram_reg_0_15_0_5/ADDRD2
|
|
SLICE_X6Y61 RAMD32 r u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/tfifo/ram_reg_0_15_0_5/RAMB/WADR2
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock sys_clk rise edge) 0.000 0.000 r
|
|
clock source latency -1.947 -1.947
|
|
propagated clock network latency
|
|
1.637 -0.310
|
|
clock pessimism -0.216 -0.526
|
|
SLICE_X6Y61 RAMD32 (Hold_ramd32_CLK_WADR2)
|
|
0.254 -0.272 u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/tfifo/ram_reg_0_15_0_5/RAMB
|
|
-------------------------------------------------------------------
|
|
required time 0.272
|
|
arrival time -0.164
|
|
-------------------------------------------------------------------
|
|
slack 0.108
|
|
|
|
Slack (MET) : 0.108ns (arrival time - required time)
|
|
Source: u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/top_reg[2]/C
|
|
(rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Destination: u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/tfifo/ram_reg_0_15_0_5/RAMB/WADR2
|
|
(rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Path Group: sys_clk
|
|
Path Type: Hold (Min at Fast Process Corner)
|
|
Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns)
|
|
Data Path Delay: 0.379ns (logic 0.164ns (43.254%) route 0.215ns (56.746%))
|
|
Logic Levels: 0
|
|
Clock Path Skew: 0.017ns (DCD - SCD - CPR)
|
|
Destination Clock Delay (DCD): -0.310ns
|
|
Source Clock Delay (SCD): -0.543ns
|
|
Clock Pessimism Removal (CPR): 0.216ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock sys_clk rise edge) 0.000 0.000 r
|
|
clock source latency -1.848 -1.848
|
|
propagated clock network latency
|
|
1.305 -0.543
|
|
SLICE_X6Y62 FDRE 0.000 -0.543 r u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/top_reg[2]/C
|
|
SLICE_X6Y62 FDRE (Prop_fdre_C_Q) 0.164 -0.379 f u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/top_reg[2]/Q
|
|
net (fo=18, routed) 0.215 -0.164 u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/tfifo/ram_reg_0_15_0_5/ADDRD2
|
|
SLICE_X6Y61 RAMD32 f u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/tfifo/ram_reg_0_15_0_5/RAMB/WADR2
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock sys_clk rise edge) 0.000 0.000 r
|
|
clock source latency -1.947 -1.947
|
|
propagated clock network latency
|
|
1.637 -0.310
|
|
clock pessimism -0.216 -0.526
|
|
SLICE_X6Y61 RAMD32 (Hold_ramd32_CLK_WADR2)
|
|
0.254 -0.272 u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/tfifo/ram_reg_0_15_0_5/RAMB
|
|
-------------------------------------------------------------------
|
|
required time 0.272
|
|
arrival time -0.164
|
|
-------------------------------------------------------------------
|
|
slack 0.108
|
|
|
|
Slack (MET) : 0.108ns (arrival time - required time)
|
|
Source: u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/top_reg[2]/C
|
|
(rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Destination: u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/tfifo/ram_reg_0_15_0_5/RAMB_D1/WADR2
|
|
(rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Path Group: sys_clk
|
|
Path Type: Hold (Min at Fast Process Corner)
|
|
Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns)
|
|
Data Path Delay: 0.379ns (logic 0.164ns (43.254%) route 0.215ns (56.746%))
|
|
Logic Levels: 0
|
|
Clock Path Skew: 0.017ns (DCD - SCD - CPR)
|
|
Destination Clock Delay (DCD): -0.310ns
|
|
Source Clock Delay (SCD): -0.543ns
|
|
Clock Pessimism Removal (CPR): 0.216ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock sys_clk rise edge) 0.000 0.000 r
|
|
clock source latency -1.848 -1.848
|
|
propagated clock network latency
|
|
1.305 -0.543
|
|
SLICE_X6Y62 FDRE 0.000 -0.543 r u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/top_reg[2]/C
|
|
SLICE_X6Y62 FDRE (Prop_fdre_C_Q) 0.164 -0.379 r u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/top_reg[2]/Q
|
|
net (fo=18, routed) 0.215 -0.164 u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/tfifo/ram_reg_0_15_0_5/ADDRD2
|
|
SLICE_X6Y61 RAMD32 r u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/tfifo/ram_reg_0_15_0_5/RAMB_D1/WADR2
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock sys_clk rise edge) 0.000 0.000 r
|
|
clock source latency -1.947 -1.947
|
|
propagated clock network latency
|
|
1.637 -0.310
|
|
clock pessimism -0.216 -0.526
|
|
SLICE_X6Y61 RAMD32 (Hold_ramd32_CLK_WADR2)
|
|
0.254 -0.272 u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/tfifo/ram_reg_0_15_0_5/RAMB_D1
|
|
-------------------------------------------------------------------
|
|
required time 0.272
|
|
arrival time -0.164
|
|
-------------------------------------------------------------------
|
|
slack 0.108
|
|
|
|
Slack (MET) : 0.108ns (arrival time - required time)
|
|
Source: u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/top_reg[2]/C
|
|
(rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Destination: u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/tfifo/ram_reg_0_15_0_5/RAMB_D1/WADR2
|
|
(rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Path Group: sys_clk
|
|
Path Type: Hold (Min at Fast Process Corner)
|
|
Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns)
|
|
Data Path Delay: 0.379ns (logic 0.164ns (43.254%) route 0.215ns (56.746%))
|
|
Logic Levels: 0
|
|
Clock Path Skew: 0.017ns (DCD - SCD - CPR)
|
|
Destination Clock Delay (DCD): -0.310ns
|
|
Source Clock Delay (SCD): -0.543ns
|
|
Clock Pessimism Removal (CPR): 0.216ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock sys_clk rise edge) 0.000 0.000 r
|
|
clock source latency -1.848 -1.848
|
|
propagated clock network latency
|
|
1.305 -0.543
|
|
SLICE_X6Y62 FDRE 0.000 -0.543 r u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/top_reg[2]/C
|
|
SLICE_X6Y62 FDRE (Prop_fdre_C_Q) 0.164 -0.379 f u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/top_reg[2]/Q
|
|
net (fo=18, routed) 0.215 -0.164 u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/tfifo/ram_reg_0_15_0_5/ADDRD2
|
|
SLICE_X6Y61 RAMD32 f u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/tfifo/ram_reg_0_15_0_5/RAMB_D1/WADR2
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock sys_clk rise edge) 0.000 0.000 r
|
|
clock source latency -1.947 -1.947
|
|
propagated clock network latency
|
|
1.637 -0.310
|
|
clock pessimism -0.216 -0.526
|
|
SLICE_X6Y61 RAMD32 (Hold_ramd32_CLK_WADR2)
|
|
0.254 -0.272 u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/tfifo/ram_reg_0_15_0_5/RAMB_D1
|
|
-------------------------------------------------------------------
|
|
required time 0.272
|
|
arrival time -0.164
|
|
-------------------------------------------------------------------
|
|
slack 0.108
|
|
|
|
Slack (MET) : 0.108ns (arrival time - required time)
|
|
Source: u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/top_reg[2]/C
|
|
(rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Destination: u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/tfifo/ram_reg_0_15_0_5/RAMC/WADR2
|
|
(rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Path Group: sys_clk
|
|
Path Type: Hold (Min at Fast Process Corner)
|
|
Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns)
|
|
Data Path Delay: 0.379ns (logic 0.164ns (43.254%) route 0.215ns (56.746%))
|
|
Logic Levels: 0
|
|
Clock Path Skew: 0.017ns (DCD - SCD - CPR)
|
|
Destination Clock Delay (DCD): -0.310ns
|
|
Source Clock Delay (SCD): -0.543ns
|
|
Clock Pessimism Removal (CPR): 0.216ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock sys_clk rise edge) 0.000 0.000 r
|
|
clock source latency -1.848 -1.848
|
|
propagated clock network latency
|
|
1.305 -0.543
|
|
SLICE_X6Y62 FDRE 0.000 -0.543 r u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/top_reg[2]/C
|
|
SLICE_X6Y62 FDRE (Prop_fdre_C_Q) 0.164 -0.379 r u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/top_reg[2]/Q
|
|
net (fo=18, routed) 0.215 -0.164 u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/tfifo/ram_reg_0_15_0_5/ADDRD2
|
|
SLICE_X6Y61 RAMD32 r u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/tfifo/ram_reg_0_15_0_5/RAMC/WADR2
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock sys_clk rise edge) 0.000 0.000 r
|
|
clock source latency -1.947 -1.947
|
|
propagated clock network latency
|
|
1.637 -0.310
|
|
clock pessimism -0.216 -0.526
|
|
SLICE_X6Y61 RAMD32 (Hold_ramd32_CLK_WADR2)
|
|
0.254 -0.272 u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/tfifo/ram_reg_0_15_0_5/RAMC
|
|
-------------------------------------------------------------------
|
|
required time 0.272
|
|
arrival time -0.164
|
|
-------------------------------------------------------------------
|
|
slack 0.108
|
|
|
|
Slack (MET) : 0.108ns (arrival time - required time)
|
|
Source: u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/top_reg[2]/C
|
|
(rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Destination: u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/tfifo/ram_reg_0_15_0_5/RAMC/WADR2
|
|
(rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Path Group: sys_clk
|
|
Path Type: Hold (Min at Fast Process Corner)
|
|
Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns)
|
|
Data Path Delay: 0.379ns (logic 0.164ns (43.254%) route 0.215ns (56.746%))
|
|
Logic Levels: 0
|
|
Clock Path Skew: 0.017ns (DCD - SCD - CPR)
|
|
Destination Clock Delay (DCD): -0.310ns
|
|
Source Clock Delay (SCD): -0.543ns
|
|
Clock Pessimism Removal (CPR): 0.216ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock sys_clk rise edge) 0.000 0.000 r
|
|
clock source latency -1.848 -1.848
|
|
propagated clock network latency
|
|
1.305 -0.543
|
|
SLICE_X6Y62 FDRE 0.000 -0.543 r u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/top_reg[2]/C
|
|
SLICE_X6Y62 FDRE (Prop_fdre_C_Q) 0.164 -0.379 f u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/top_reg[2]/Q
|
|
net (fo=18, routed) 0.215 -0.164 u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/tfifo/ram_reg_0_15_0_5/ADDRD2
|
|
SLICE_X6Y61 RAMD32 f u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/tfifo/ram_reg_0_15_0_5/RAMC/WADR2
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock sys_clk rise edge) 0.000 0.000 r
|
|
clock source latency -1.947 -1.947
|
|
propagated clock network latency
|
|
1.637 -0.310
|
|
clock pessimism -0.216 -0.526
|
|
SLICE_X6Y61 RAMD32 (Hold_ramd32_CLK_WADR2)
|
|
0.254 -0.272 u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/tfifo/ram_reg_0_15_0_5/RAMC
|
|
-------------------------------------------------------------------
|
|
required time 0.272
|
|
arrival time -0.164
|
|
-------------------------------------------------------------------
|
|
slack 0.108
|
|
|
|
Slack (MET) : 0.108ns (arrival time - required time)
|
|
Source: u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/top_reg[2]/C
|
|
(rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Destination: u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/tfifo/ram_reg_0_15_0_5/RAMC_D1/WADR2
|
|
(rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Path Group: sys_clk
|
|
Path Type: Hold (Min at Fast Process Corner)
|
|
Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns)
|
|
Data Path Delay: 0.379ns (logic 0.164ns (43.254%) route 0.215ns (56.746%))
|
|
Logic Levels: 0
|
|
Clock Path Skew: 0.017ns (DCD - SCD - CPR)
|
|
Destination Clock Delay (DCD): -0.310ns
|
|
Source Clock Delay (SCD): -0.543ns
|
|
Clock Pessimism Removal (CPR): 0.216ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock sys_clk rise edge) 0.000 0.000 r
|
|
clock source latency -1.848 -1.848
|
|
propagated clock network latency
|
|
1.305 -0.543
|
|
SLICE_X6Y62 FDRE 0.000 -0.543 r u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/top_reg[2]/C
|
|
SLICE_X6Y62 FDRE (Prop_fdre_C_Q) 0.164 -0.379 r u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/top_reg[2]/Q
|
|
net (fo=18, routed) 0.215 -0.164 u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/tfifo/ram_reg_0_15_0_5/ADDRD2
|
|
SLICE_X6Y61 RAMD32 r u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/tfifo/ram_reg_0_15_0_5/RAMC_D1/WADR2
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock sys_clk rise edge) 0.000 0.000 r
|
|
clock source latency -1.947 -1.947
|
|
propagated clock network latency
|
|
1.637 -0.310
|
|
clock pessimism -0.216 -0.526
|
|
SLICE_X6Y61 RAMD32 (Hold_ramd32_CLK_WADR2)
|
|
0.254 -0.272 u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/tfifo/ram_reg_0_15_0_5/RAMC_D1
|
|
-------------------------------------------------------------------
|
|
required time 0.272
|
|
arrival time -0.164
|
|
-------------------------------------------------------------------
|
|
slack 0.108
|
|
|
|
Slack (MET) : 0.108ns (arrival time - required time)
|
|
Source: u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/top_reg[2]/C
|
|
(rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Destination: u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/tfifo/ram_reg_0_15_0_5/RAMC_D1/WADR2
|
|
(rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Path Group: sys_clk
|
|
Path Type: Hold (Min at Fast Process Corner)
|
|
Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns)
|
|
Data Path Delay: 0.379ns (logic 0.164ns (43.254%) route 0.215ns (56.746%))
|
|
Logic Levels: 0
|
|
Clock Path Skew: 0.017ns (DCD - SCD - CPR)
|
|
Destination Clock Delay (DCD): -0.310ns
|
|
Source Clock Delay (SCD): -0.543ns
|
|
Clock Pessimism Removal (CPR): 0.216ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock sys_clk rise edge) 0.000 0.000 r
|
|
clock source latency -1.848 -1.848
|
|
propagated clock network latency
|
|
1.305 -0.543
|
|
SLICE_X6Y62 FDRE 0.000 -0.543 r u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/top_reg[2]/C
|
|
SLICE_X6Y62 FDRE (Prop_fdre_C_Q) 0.164 -0.379 f u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/top_reg[2]/Q
|
|
net (fo=18, routed) 0.215 -0.164 u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/tfifo/ram_reg_0_15_0_5/ADDRD2
|
|
SLICE_X6Y61 RAMD32 f u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/tfifo/ram_reg_0_15_0_5/RAMC_D1/WADR2
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock sys_clk rise edge) 0.000 0.000 r
|
|
clock source latency -1.947 -1.947
|
|
propagated clock network latency
|
|
1.637 -0.310
|
|
clock pessimism -0.216 -0.526
|
|
SLICE_X6Y61 RAMD32 (Hold_ramd32_CLK_WADR2)
|
|
0.254 -0.272 u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/tfifo/ram_reg_0_15_0_5/RAMC_D1
|
|
-------------------------------------------------------------------
|
|
required time 0.272
|
|
arrival time -0.164
|
|
-------------------------------------------------------------------
|
|
slack 0.108
|
|
|
|
Slack (MET) : 0.108ns (arrival time - required time)
|
|
Source: u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/top_reg[2]/C
|
|
(rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Destination: u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/tfifo/ram_reg_0_15_0_5/RAMD/ADR2
|
|
(rising edge-triggered cell RAMS32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Path Group: sys_clk
|
|
Path Type: Hold (Min at Fast Process Corner)
|
|
Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns)
|
|
Data Path Delay: 0.379ns (logic 0.164ns (43.254%) route 0.215ns (56.746%))
|
|
Logic Levels: 0
|
|
Clock Path Skew: 0.017ns (DCD - SCD - CPR)
|
|
Destination Clock Delay (DCD): -0.310ns
|
|
Source Clock Delay (SCD): -0.543ns
|
|
Clock Pessimism Removal (CPR): 0.216ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock sys_clk rise edge) 0.000 0.000 r
|
|
clock source latency -1.848 -1.848
|
|
propagated clock network latency
|
|
1.305 -0.543
|
|
SLICE_X6Y62 FDRE 0.000 -0.543 r u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/top_reg[2]/C
|
|
SLICE_X6Y62 FDRE (Prop_fdre_C_Q) 0.164 -0.379 r u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/top_reg[2]/Q
|
|
net (fo=18, routed) 0.215 -0.164 u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/tfifo/ram_reg_0_15_0_5/ADDRD2
|
|
SLICE_X6Y61 RAMS32 r u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/tfifo/ram_reg_0_15_0_5/RAMD/ADR2
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock sys_clk rise edge) 0.000 0.000 r
|
|
clock source latency -1.947 -1.947
|
|
propagated clock network latency
|
|
1.637 -0.310
|
|
clock pessimism -0.216 -0.526
|
|
SLICE_X6Y61 RAMS32 (Hold_rams32_CLK_ADR2)
|
|
0.254 -0.272 u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/tfifo/ram_reg_0_15_0_5/RAMD
|
|
-------------------------------------------------------------------
|
|
required time 0.272
|
|
arrival time -0.164
|
|
-------------------------------------------------------------------
|
|
slack 0.108
|
|
|
|
Slack (MET) : 0.108ns (arrival time - required time)
|
|
Source: u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/top_reg[2]/C
|
|
(rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Destination: u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/tfifo/ram_reg_0_15_0_5/RAMD/ADR2
|
|
(rising edge-triggered cell RAMS32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Path Group: sys_clk
|
|
Path Type: Hold (Min at Fast Process Corner)
|
|
Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns)
|
|
Data Path Delay: 0.379ns (logic 0.164ns (43.254%) route 0.215ns (56.746%))
|
|
Logic Levels: 0
|
|
Clock Path Skew: 0.017ns (DCD - SCD - CPR)
|
|
Destination Clock Delay (DCD): -0.310ns
|
|
Source Clock Delay (SCD): -0.543ns
|
|
Clock Pessimism Removal (CPR): 0.216ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock sys_clk rise edge) 0.000 0.000 r
|
|
clock source latency -1.848 -1.848
|
|
propagated clock network latency
|
|
1.305 -0.543
|
|
SLICE_X6Y62 FDRE 0.000 -0.543 r u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/top_reg[2]/C
|
|
SLICE_X6Y62 FDRE (Prop_fdre_C_Q) 0.164 -0.379 f u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/top_reg[2]/Q
|
|
net (fo=18, routed) 0.215 -0.164 u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/tfifo/ram_reg_0_15_0_5/ADDRD2
|
|
SLICE_X6Y61 RAMS32 f u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/tfifo/ram_reg_0_15_0_5/RAMD/ADR2
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock sys_clk rise edge) 0.000 0.000 r
|
|
clock source latency -1.947 -1.947
|
|
propagated clock network latency
|
|
1.637 -0.310
|
|
clock pessimism -0.216 -0.526
|
|
SLICE_X6Y61 RAMS32 (Hold_rams32_CLK_ADR2)
|
|
0.254 -0.272 u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/tfifo/ram_reg_0_15_0_5/RAMD
|
|
-------------------------------------------------------------------
|
|
required time 0.272
|
|
arrival time -0.164
|
|
-------------------------------------------------------------------
|
|
slack 0.108
|
|
|
|
Slack (MET) : 0.108ns (arrival time - required time)
|
|
Source: u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/top_reg[2]/C
|
|
(rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Destination: u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/tfifo/ram_reg_0_15_0_5/RAMD_D1/ADR2
|
|
(rising edge-triggered cell RAMS32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Path Group: sys_clk
|
|
Path Type: Hold (Min at Fast Process Corner)
|
|
Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns)
|
|
Data Path Delay: 0.379ns (logic 0.164ns (43.254%) route 0.215ns (56.746%))
|
|
Logic Levels: 0
|
|
Clock Path Skew: 0.017ns (DCD - SCD - CPR)
|
|
Destination Clock Delay (DCD): -0.310ns
|
|
Source Clock Delay (SCD): -0.543ns
|
|
Clock Pessimism Removal (CPR): 0.216ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock sys_clk rise edge) 0.000 0.000 r
|
|
clock source latency -1.848 -1.848
|
|
propagated clock network latency
|
|
1.305 -0.543
|
|
SLICE_X6Y62 FDRE 0.000 -0.543 r u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/top_reg[2]/C
|
|
SLICE_X6Y62 FDRE (Prop_fdre_C_Q) 0.164 -0.379 r u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/top_reg[2]/Q
|
|
net (fo=18, routed) 0.215 -0.164 u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/tfifo/ram_reg_0_15_0_5/ADDRD2
|
|
SLICE_X6Y61 RAMS32 r u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/tfifo/ram_reg_0_15_0_5/RAMD_D1/ADR2
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock sys_clk rise edge) 0.000 0.000 r
|
|
clock source latency -1.947 -1.947
|
|
propagated clock network latency
|
|
1.637 -0.310
|
|
clock pessimism -0.216 -0.526
|
|
SLICE_X6Y61 RAMS32 (Hold_rams32_CLK_ADR2)
|
|
0.254 -0.272 u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/tfifo/ram_reg_0_15_0_5/RAMD_D1
|
|
-------------------------------------------------------------------
|
|
required time 0.272
|
|
arrival time -0.164
|
|
-------------------------------------------------------------------
|
|
slack 0.108
|
|
|
|
Slack (MET) : 0.108ns (arrival time - required time)
|
|
Source: u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/top_reg[2]/C
|
|
(rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Destination: u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/tfifo/ram_reg_0_15_0_5/RAMD_D1/ADR2
|
|
(rising edge-triggered cell RAMS32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Path Group: sys_clk
|
|
Path Type: Hold (Min at Fast Process Corner)
|
|
Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns)
|
|
Data Path Delay: 0.379ns (logic 0.164ns (43.254%) route 0.215ns (56.746%))
|
|
Logic Levels: 0
|
|
Clock Path Skew: 0.017ns (DCD - SCD - CPR)
|
|
Destination Clock Delay (DCD): -0.310ns
|
|
Source Clock Delay (SCD): -0.543ns
|
|
Clock Pessimism Removal (CPR): 0.216ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock sys_clk rise edge) 0.000 0.000 r
|
|
clock source latency -1.848 -1.848
|
|
propagated clock network latency
|
|
1.305 -0.543
|
|
SLICE_X6Y62 FDRE 0.000 -0.543 r u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/top_reg[2]/C
|
|
SLICE_X6Y62 FDRE (Prop_fdre_C_Q) 0.164 -0.379 f u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/top_reg[2]/Q
|
|
net (fo=18, routed) 0.215 -0.164 u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/tfifo/ram_reg_0_15_0_5/ADDRD2
|
|
SLICE_X6Y61 RAMS32 f u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/tfifo/ram_reg_0_15_0_5/RAMD_D1/ADR2
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock sys_clk rise edge) 0.000 0.000 r
|
|
clock source latency -1.947 -1.947
|
|
propagated clock network latency
|
|
1.637 -0.310
|
|
clock pessimism -0.216 -0.526
|
|
SLICE_X6Y61 RAMS32 (Hold_rams32_CLK_ADR2)
|
|
0.254 -0.272 u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/tfifo/ram_reg_0_15_0_5/RAMD_D1
|
|
-------------------------------------------------------------------
|
|
required time 0.272
|
|
arrival time -0.164
|
|
-------------------------------------------------------------------
|
|
slack 0.108
|
|
|
|
Slack (MET) : 0.108ns (arrival time - required time)
|
|
Source: u_matmul_axi_slave/mult_inst[1].u_mult/prod_reg[48]/C
|
|
(rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Destination: u_matmul_axi_slave/mult_inst[1].u_mult/p_reg[48]/D
|
|
(rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Path Group: sys_clk
|
|
Path Type: Hold (Min at Fast Process Corner)
|
|
Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns)
|
|
Data Path Delay: 0.509ns (logic 0.164ns (32.204%) route 0.345ns (67.796%))
|
|
Logic Levels: 0
|
|
Clock Path Skew: 0.335ns (DCD - SCD - CPR)
|
|
Destination Clock Delay (DCD): -0.338ns
|
|
Source Clock Delay (SCD): -0.633ns
|
|
Clock Pessimism Removal (CPR): -0.040ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock sys_clk rise edge) 0.000 0.000 r
|
|
clock source latency -1.848 -1.848
|
|
propagated clock network latency
|
|
1.215 -0.633
|
|
SLICE_X14Y102 FDRE 0.000 -0.633 r u_matmul_axi_slave/mult_inst[1].u_mult/prod_reg[48]/C
|
|
SLICE_X14Y102 FDRE (Prop_fdre_C_Q) 0.164 -0.469 r u_matmul_axi_slave/mult_inst[1].u_mult/prod_reg[48]/Q
|
|
net (fo=1, routed) 0.345 -0.124 u_matmul_axi_slave/mult_inst[1].u_mult/prod[48]
|
|
SLICE_X17Y92 FDRE r u_matmul_axi_slave/mult_inst[1].u_mult/p_reg[48]/D
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock sys_clk rise edge) 0.000 0.000 r
|
|
clock source latency -1.947 -1.947
|
|
propagated clock network latency
|
|
1.609 -0.338
|
|
clock pessimism 0.040 -0.298
|
|
SLICE_X17Y92 FDRE (Hold_fdre_C_D) 0.066 -0.232 u_matmul_axi_slave/mult_inst[1].u_mult/p_reg[48]
|
|
-------------------------------------------------------------------
|
|
required time 0.232
|
|
arrival time -0.124
|
|
-------------------------------------------------------------------
|
|
slack 0.108
|
|
|
|
Slack (MET) : 0.108ns (arrival time - required time)
|
|
Source: u_matmul_axi_slave/mult_inst[1].u_mult/prod_reg[48]/C
|
|
(rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Destination: u_matmul_axi_slave/mult_inst[1].u_mult/p_reg[48]/D
|
|
(rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Path Group: sys_clk
|
|
Path Type: Hold (Min at Fast Process Corner)
|
|
Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns)
|
|
Data Path Delay: 0.509ns (logic 0.164ns (32.204%) route 0.345ns (67.796%))
|
|
Logic Levels: 0
|
|
Clock Path Skew: 0.335ns (DCD - SCD - CPR)
|
|
Destination Clock Delay (DCD): -0.338ns
|
|
Source Clock Delay (SCD): -0.633ns
|
|
Clock Pessimism Removal (CPR): -0.040ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock sys_clk rise edge) 0.000 0.000 r
|
|
clock source latency -1.848 -1.848
|
|
propagated clock network latency
|
|
1.215 -0.633
|
|
SLICE_X14Y102 FDRE 0.000 -0.633 r u_matmul_axi_slave/mult_inst[1].u_mult/prod_reg[48]/C
|
|
SLICE_X14Y102 FDRE (Prop_fdre_C_Q) 0.164 -0.469 f u_matmul_axi_slave/mult_inst[1].u_mult/prod_reg[48]/Q
|
|
net (fo=1, routed) 0.345 -0.124 u_matmul_axi_slave/mult_inst[1].u_mult/prod[48]
|
|
SLICE_X17Y92 FDRE f u_matmul_axi_slave/mult_inst[1].u_mult/p_reg[48]/D
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock sys_clk rise edge) 0.000 0.000 r
|
|
clock source latency -1.947 -1.947
|
|
propagated clock network latency
|
|
1.609 -0.338
|
|
clock pessimism 0.040 -0.298
|
|
SLICE_X17Y92 FDRE (Hold_fdre_C_D) 0.066 -0.232 u_matmul_axi_slave/mult_inst[1].u_mult/p_reg[48]
|
|
-------------------------------------------------------------------
|
|
required time 0.232
|
|
arrival time -0.124
|
|
-------------------------------------------------------------------
|
|
slack 0.108
|
|
|
|
Slack (MET) : 0.110ns (arrival time - required time)
|
|
Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/qprod_s4_reg[24]/C
|
|
(rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns})
|
|
Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[24]/D
|
|
(rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns})
|
|
Path Group: mlkem_clk_clk_pll
|
|
Path Type: Hold (Min at Fast Process Corner)
|
|
Requirement: 0.000ns (mlkem_clk_clk_pll rise@0.000ns - mlkem_clk_clk_pll rise@0.000ns)
|
|
Data Path Delay: 0.478ns (logic 0.279ns (58.317%) route 0.199ns (41.683%))
|
|
Logic Levels: 2 (CARRY4=1 LUT1=1)
|
|
Clock Path Skew: 0.264ns (DCD - SCD - CPR)
|
|
Destination Clock Delay (DCD): -0.479ns
|
|
Source Clock Delay (SCD): -0.703ns
|
|
Clock Pessimism Removal (CPR): -0.040ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock mlkem_clk_clk_pll rise edge)
|
|
0.000 0.000 r
|
|
clock source latency -1.848 -1.848
|
|
propagated clock network latency
|
|
1.146 -0.703
|
|
SLICE_X84Y160 FDCE 0.000 -0.703 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/qprod_s4_reg[24]/C
|
|
SLICE_X84Y160 FDCE (Prop_fdce_C_Q) 0.164 -0.539 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/qprod_s4_reg[24]/Q
|
|
net (fo=1, routed) 0.199 -0.339 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/qprod_s4[24]
|
|
SLICE_X83Y160 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5[24]_i_2/I0
|
|
SLICE_X83Y160 LUT1 (Prop_lut1_I0_O) 0.045 -0.294 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5[24]_i_2/O
|
|
net (fo=1, routed) 0.000 -0.294 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5[24]_i_2_n_0
|
|
SLICE_X83Y160 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[24]_i_1/S[0]
|
|
SLICE_X83Y160 CARRY4 (Prop_carry4_S[0]_O[0])
|
|
0.070 -0.224 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[24]_i_1/O[0]
|
|
net (fo=1, routed) 0.000 -0.224 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s50[24]
|
|
SLICE_X83Y160 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[24]/D
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock mlkem_clk_clk_pll rise edge)
|
|
0.000 0.000 r
|
|
clock source latency -1.947 -1.947
|
|
propagated clock network latency
|
|
1.468 -0.479
|
|
clock pessimism 0.040 -0.439
|
|
SLICE_X83Y160 FDCE (Hold_fdce_C_D) 0.105 -0.334 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[24]
|
|
-------------------------------------------------------------------
|
|
required time 0.334
|
|
arrival time -0.224
|
|
-------------------------------------------------------------------
|
|
slack 0.110
|
|
|
|
Slack (MET) : 0.110ns (arrival time - required time)
|
|
Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/qprod_s4_reg[24]/C
|
|
(rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns})
|
|
Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[24]/D
|
|
(rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns})
|
|
Path Group: mlkem_clk_clk_pll
|
|
Path Type: Hold (Min at Fast Process Corner)
|
|
Requirement: 0.000ns (mlkem_clk_clk_pll rise@0.000ns - mlkem_clk_clk_pll rise@0.000ns)
|
|
Data Path Delay: 0.478ns (logic 0.279ns (58.317%) route 0.199ns (41.683%))
|
|
Logic Levels: 2 (CARRY4=1 LUT1=1)
|
|
Clock Path Skew: 0.264ns (DCD - SCD - CPR)
|
|
Destination Clock Delay (DCD): -0.479ns
|
|
Source Clock Delay (SCD): -0.703ns
|
|
Clock Pessimism Removal (CPR): -0.040ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock mlkem_clk_clk_pll rise edge)
|
|
0.000 0.000 r
|
|
clock source latency -1.848 -1.848
|
|
propagated clock network latency
|
|
1.146 -0.703
|
|
SLICE_X84Y160 FDCE 0.000 -0.703 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/qprod_s4_reg[24]/C
|
|
SLICE_X84Y160 FDCE (Prop_fdce_C_Q) 0.164 -0.539 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/qprod_s4_reg[24]/Q
|
|
net (fo=1, routed) 0.199 -0.339 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/qprod_s4[24]
|
|
SLICE_X83Y160 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5[24]_i_2/I0
|
|
SLICE_X83Y160 LUT1 (Prop_lut1_I0_O) 0.045 -0.294 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5[24]_i_2/O
|
|
net (fo=1, routed) 0.000 -0.294 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5[24]_i_2_n_0
|
|
SLICE_X83Y160 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[24]_i_1/S[0]
|
|
SLICE_X83Y160 CARRY4 (Prop_carry4_S[0]_O[0])
|
|
0.070 -0.224 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[24]_i_1/O[0]
|
|
net (fo=1, routed) 0.000 -0.224 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s50[24]
|
|
SLICE_X83Y160 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[24]/D
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock mlkem_clk_clk_pll rise edge)
|
|
0.000 0.000 r
|
|
clock source latency -1.947 -1.947
|
|
propagated clock network latency
|
|
1.468 -0.479
|
|
clock pessimism 0.040 -0.439
|
|
SLICE_X83Y160 FDCE (Hold_fdce_C_D) 0.105 -0.334 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[24]
|
|
-------------------------------------------------------------------
|
|
required time 0.334
|
|
arrival time -0.224
|
|
-------------------------------------------------------------------
|
|
slack 0.110
|
|
|
|
Slack (MET) : 0.110ns (arrival time - required time)
|
|
Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/qprod_s4_reg[24]/C
|
|
(rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns})
|
|
Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[24]/D
|
|
(rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns})
|
|
Path Group: mlkem_clk_clk_pll
|
|
Path Type: Hold (Min at Fast Process Corner)
|
|
Requirement: 0.000ns (mlkem_clk_clk_pll rise@0.000ns - mlkem_clk_clk_pll rise@0.000ns)
|
|
Data Path Delay: 0.478ns (logic 0.279ns (58.317%) route 0.199ns (41.683%))
|
|
Logic Levels: 2 (CARRY4=1 LUT1=1)
|
|
Clock Path Skew: 0.264ns (DCD - SCD - CPR)
|
|
Destination Clock Delay (DCD): -0.479ns
|
|
Source Clock Delay (SCD): -0.703ns
|
|
Clock Pessimism Removal (CPR): -0.040ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock mlkem_clk_clk_pll rise edge)
|
|
0.000 0.000 r
|
|
clock source latency -1.848 -1.848
|
|
propagated clock network latency
|
|
1.146 -0.703
|
|
SLICE_X84Y160 FDCE 0.000 -0.703 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/qprod_s4_reg[24]/C
|
|
SLICE_X84Y160 FDCE (Prop_fdce_C_Q) 0.164 -0.539 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/qprod_s4_reg[24]/Q
|
|
net (fo=1, routed) 0.199 -0.339 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/qprod_s4[24]
|
|
SLICE_X83Y160 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5[24]_i_2/I0
|
|
SLICE_X83Y160 LUT1 (Prop_lut1_I0_O) 0.045 -0.294 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5[24]_i_2/O
|
|
net (fo=1, routed) 0.000 -0.294 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5[24]_i_2_n_0
|
|
SLICE_X83Y160 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[24]_i_1/S[0]
|
|
SLICE_X83Y160 CARRY4 (Prop_carry4_S[0]_O[0])
|
|
0.070 -0.224 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[24]_i_1/O[0]
|
|
net (fo=1, routed) 0.000 -0.224 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s50[24]
|
|
SLICE_X83Y160 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[24]/D
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock mlkem_clk_clk_pll rise edge)
|
|
0.000 0.000 r
|
|
clock source latency -1.947 -1.947
|
|
propagated clock network latency
|
|
1.468 -0.479
|
|
clock pessimism 0.040 -0.439
|
|
SLICE_X83Y160 FDCE (Hold_fdce_C_D) 0.105 -0.334 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[24]
|
|
-------------------------------------------------------------------
|
|
required time 0.334
|
|
arrival time -0.224
|
|
-------------------------------------------------------------------
|
|
slack 0.110
|
|
|
|
Slack (MET) : 0.110ns (arrival time - required time)
|
|
Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/qprod_s4_reg[24]/C
|
|
(rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns})
|
|
Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[24]/D
|
|
(rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns})
|
|
Path Group: mlkem_clk_clk_pll
|
|
Path Type: Hold (Min at Fast Process Corner)
|
|
Requirement: 0.000ns (mlkem_clk_clk_pll rise@0.000ns - mlkem_clk_clk_pll rise@0.000ns)
|
|
Data Path Delay: 0.478ns (logic 0.279ns (58.317%) route 0.199ns (41.683%))
|
|
Logic Levels: 2 (CARRY4=1 LUT1=1)
|
|
Clock Path Skew: 0.264ns (DCD - SCD - CPR)
|
|
Destination Clock Delay (DCD): -0.479ns
|
|
Source Clock Delay (SCD): -0.703ns
|
|
Clock Pessimism Removal (CPR): -0.040ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock mlkem_clk_clk_pll rise edge)
|
|
0.000 0.000 r
|
|
clock source latency -1.848 -1.848
|
|
propagated clock network latency
|
|
1.146 -0.703
|
|
SLICE_X84Y160 FDCE 0.000 -0.703 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/qprod_s4_reg[24]/C
|
|
SLICE_X84Y160 FDCE (Prop_fdce_C_Q) 0.164 -0.539 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/qprod_s4_reg[24]/Q
|
|
net (fo=1, routed) 0.199 -0.339 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/qprod_s4[24]
|
|
SLICE_X83Y160 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5[24]_i_2/I0
|
|
SLICE_X83Y160 LUT1 (Prop_lut1_I0_O) 0.045 -0.294 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5[24]_i_2/O
|
|
net (fo=1, routed) 0.000 -0.294 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5[24]_i_2_n_0
|
|
SLICE_X83Y160 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[24]_i_1/S[0]
|
|
SLICE_X83Y160 CARRY4 (Prop_carry4_S[0]_O[0])
|
|
0.070 -0.224 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[24]_i_1/O[0]
|
|
net (fo=1, routed) 0.000 -0.224 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s50[24]
|
|
SLICE_X83Y160 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[24]/D
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock mlkem_clk_clk_pll rise edge)
|
|
0.000 0.000 r
|
|
clock source latency -1.947 -1.947
|
|
propagated clock network latency
|
|
1.468 -0.479
|
|
clock pessimism 0.040 -0.439
|
|
SLICE_X83Y160 FDCE (Hold_fdce_C_D) 0.105 -0.334 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[24]
|
|
-------------------------------------------------------------------
|
|
required time 0.334
|
|
arrival time -0.224
|
|
-------------------------------------------------------------------
|
|
slack 0.110
|
|
|
|
Slack (MET) : 0.110ns (arrival time - required time)
|
|
Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/qprod_s4_reg[12]/C
|
|
(rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns})
|
|
Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[12]/D
|
|
(rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns})
|
|
Path Group: mlkem_clk_clk_pll
|
|
Path Type: Hold (Min at Fast Process Corner)
|
|
Requirement: 0.000ns (mlkem_clk_clk_pll rise@0.000ns - mlkem_clk_clk_pll rise@0.000ns)
|
|
Data Path Delay: 0.478ns (logic 0.279ns (58.317%) route 0.199ns (41.683%))
|
|
Logic Levels: 2 (CARRY4=1 LUT2=1)
|
|
Clock Path Skew: 0.264ns (DCD - SCD - CPR)
|
|
Destination Clock Delay (DCD): -0.478ns
|
|
Source Clock Delay (SCD): -0.702ns
|
|
Clock Pessimism Removal (CPR): -0.040ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock mlkem_clk_clk_pll rise edge)
|
|
0.000 0.000 r
|
|
clock source latency -1.848 -1.848
|
|
propagated clock network latency
|
|
1.147 -0.702
|
|
SLICE_X84Y157 FDCE 0.000 -0.702 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/qprod_s4_reg[12]/C
|
|
SLICE_X84Y157 FDCE (Prop_fdce_C_Q) 0.164 -0.538 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/qprod_s4_reg[12]/Q
|
|
net (fo=1, routed) 0.199 -0.338 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/qprod_s4[12]
|
|
SLICE_X83Y157 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5[15]_i_5/I1
|
|
SLICE_X83Y157 LUT2 (Prop_lut2_I1_O) 0.045 -0.293 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5[15]_i_5/O
|
|
net (fo=1, routed) 0.000 -0.293 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5[15]_i_5_n_0
|
|
SLICE_X83Y157 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[15]_i_1/S[0]
|
|
SLICE_X83Y157 CARRY4 (Prop_carry4_S[0]_O[0])
|
|
0.070 -0.223 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[15]_i_1/O[0]
|
|
net (fo=1, routed) 0.000 -0.223 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s50[12]
|
|
SLICE_X83Y157 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[12]/D
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock mlkem_clk_clk_pll rise edge)
|
|
0.000 0.000 r
|
|
clock source latency -1.947 -1.947
|
|
propagated clock network latency
|
|
1.469 -0.478
|
|
clock pessimism 0.040 -0.438
|
|
SLICE_X83Y157 FDCE (Hold_fdce_C_D) 0.105 -0.333 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[12]
|
|
-------------------------------------------------------------------
|
|
required time 0.333
|
|
arrival time -0.223
|
|
-------------------------------------------------------------------
|
|
slack 0.110
|
|
|
|
Slack (MET) : 0.110ns (arrival time - required time)
|
|
Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/qprod_s4_reg[12]/C
|
|
(rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns})
|
|
Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[12]/D
|
|
(rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns})
|
|
Path Group: mlkem_clk_clk_pll
|
|
Path Type: Hold (Min at Fast Process Corner)
|
|
Requirement: 0.000ns (mlkem_clk_clk_pll rise@0.000ns - mlkem_clk_clk_pll rise@0.000ns)
|
|
Data Path Delay: 0.478ns (logic 0.279ns (58.317%) route 0.199ns (41.683%))
|
|
Logic Levels: 2 (CARRY4=1 LUT2=1)
|
|
Clock Path Skew: 0.264ns (DCD - SCD - CPR)
|
|
Destination Clock Delay (DCD): -0.478ns
|
|
Source Clock Delay (SCD): -0.702ns
|
|
Clock Pessimism Removal (CPR): -0.040ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock mlkem_clk_clk_pll rise edge)
|
|
0.000 0.000 r
|
|
clock source latency -1.848 -1.848
|
|
propagated clock network latency
|
|
1.147 -0.702
|
|
SLICE_X84Y157 FDCE 0.000 -0.702 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/qprod_s4_reg[12]/C
|
|
SLICE_X84Y157 FDCE (Prop_fdce_C_Q) 0.164 -0.538 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/qprod_s4_reg[12]/Q
|
|
net (fo=1, routed) 0.199 -0.338 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/qprod_s4[12]
|
|
SLICE_X83Y157 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5[15]_i_5/I1
|
|
SLICE_X83Y157 LUT2 (Prop_lut2_I1_O) 0.045 -0.293 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5[15]_i_5/O
|
|
net (fo=1, routed) 0.000 -0.293 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5[15]_i_5_n_0
|
|
SLICE_X83Y157 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[15]_i_1/S[0]
|
|
SLICE_X83Y157 CARRY4 (Prop_carry4_S[0]_O[0])
|
|
0.070 -0.223 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[15]_i_1/O[0]
|
|
net (fo=1, routed) 0.000 -0.223 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s50[12]
|
|
SLICE_X83Y157 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[12]/D
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock mlkem_clk_clk_pll rise edge)
|
|
0.000 0.000 r
|
|
clock source latency -1.947 -1.947
|
|
propagated clock network latency
|
|
1.469 -0.478
|
|
clock pessimism 0.040 -0.438
|
|
SLICE_X83Y157 FDCE (Hold_fdce_C_D) 0.105 -0.333 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[12]
|
|
-------------------------------------------------------------------
|
|
required time 0.333
|
|
arrival time -0.223
|
|
-------------------------------------------------------------------
|
|
slack 0.110
|
|
|
|
Slack (MET) : 0.110ns (arrival time - required time)
|
|
Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/qprod_s4_reg[12]/C
|
|
(rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns})
|
|
Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[12]/D
|
|
(rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns})
|
|
Path Group: mlkem_clk_clk_pll
|
|
Path Type: Hold (Min at Fast Process Corner)
|
|
Requirement: 0.000ns (mlkem_clk_clk_pll rise@0.000ns - mlkem_clk_clk_pll rise@0.000ns)
|
|
Data Path Delay: 0.478ns (logic 0.279ns (58.317%) route 0.199ns (41.683%))
|
|
Logic Levels: 2 (CARRY4=1 LUT2=1)
|
|
Clock Path Skew: 0.264ns (DCD - SCD - CPR)
|
|
Destination Clock Delay (DCD): -0.478ns
|
|
Source Clock Delay (SCD): -0.702ns
|
|
Clock Pessimism Removal (CPR): -0.040ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock mlkem_clk_clk_pll rise edge)
|
|
0.000 0.000 r
|
|
clock source latency -1.848 -1.848
|
|
propagated clock network latency
|
|
1.147 -0.702
|
|
SLICE_X84Y157 FDCE 0.000 -0.702 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/qprod_s4_reg[12]/C
|
|
SLICE_X84Y157 FDCE (Prop_fdce_C_Q) 0.164 -0.538 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/qprod_s4_reg[12]/Q
|
|
net (fo=1, routed) 0.199 -0.338 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/qprod_s4[12]
|
|
SLICE_X83Y157 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5[15]_i_5/I1
|
|
SLICE_X83Y157 LUT2 (Prop_lut2_I1_O) 0.045 -0.293 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5[15]_i_5/O
|
|
net (fo=1, routed) 0.000 -0.293 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5[15]_i_5_n_0
|
|
SLICE_X83Y157 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[15]_i_1/S[0]
|
|
SLICE_X83Y157 CARRY4 (Prop_carry4_S[0]_O[0])
|
|
0.070 -0.223 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[15]_i_1/O[0]
|
|
net (fo=1, routed) 0.000 -0.223 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s50[12]
|
|
SLICE_X83Y157 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[12]/D
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock mlkem_clk_clk_pll rise edge)
|
|
0.000 0.000 r
|
|
clock source latency -1.947 -1.947
|
|
propagated clock network latency
|
|
1.469 -0.478
|
|
clock pessimism 0.040 -0.438
|
|
SLICE_X83Y157 FDCE (Hold_fdce_C_D) 0.105 -0.333 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[12]
|
|
-------------------------------------------------------------------
|
|
required time 0.333
|
|
arrival time -0.223
|
|
-------------------------------------------------------------------
|
|
slack 0.110
|
|
|
|
Slack (MET) : 0.110ns (arrival time - required time)
|
|
Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/qprod_s4_reg[12]/C
|
|
(rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns})
|
|
Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[12]/D
|
|
(rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns})
|
|
Path Group: mlkem_clk_clk_pll
|
|
Path Type: Hold (Min at Fast Process Corner)
|
|
Requirement: 0.000ns (mlkem_clk_clk_pll rise@0.000ns - mlkem_clk_clk_pll rise@0.000ns)
|
|
Data Path Delay: 0.478ns (logic 0.279ns (58.317%) route 0.199ns (41.683%))
|
|
Logic Levels: 2 (CARRY4=1 LUT2=1)
|
|
Clock Path Skew: 0.264ns (DCD - SCD - CPR)
|
|
Destination Clock Delay (DCD): -0.478ns
|
|
Source Clock Delay (SCD): -0.702ns
|
|
Clock Pessimism Removal (CPR): -0.040ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock mlkem_clk_clk_pll rise edge)
|
|
0.000 0.000 r
|
|
clock source latency -1.848 -1.848
|
|
propagated clock network latency
|
|
1.147 -0.702
|
|
SLICE_X84Y157 FDCE 0.000 -0.702 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/qprod_s4_reg[12]/C
|
|
SLICE_X84Y157 FDCE (Prop_fdce_C_Q) 0.164 -0.538 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/qprod_s4_reg[12]/Q
|
|
net (fo=1, routed) 0.199 -0.338 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/qprod_s4[12]
|
|
SLICE_X83Y157 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5[15]_i_5/I1
|
|
SLICE_X83Y157 LUT2 (Prop_lut2_I1_O) 0.045 -0.293 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5[15]_i_5/O
|
|
net (fo=1, routed) 0.000 -0.293 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5[15]_i_5_n_0
|
|
SLICE_X83Y157 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[15]_i_1/S[0]
|
|
SLICE_X83Y157 CARRY4 (Prop_carry4_S[0]_O[0])
|
|
0.070 -0.223 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[15]_i_1/O[0]
|
|
net (fo=1, routed) 0.000 -0.223 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s50[12]
|
|
SLICE_X83Y157 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[12]/D
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock mlkem_clk_clk_pll rise edge)
|
|
0.000 0.000 r
|
|
clock source latency -1.947 -1.947
|
|
propagated clock network latency
|
|
1.469 -0.478
|
|
clock pessimism 0.040 -0.438
|
|
SLICE_X83Y157 FDCE (Hold_fdce_C_D) 0.105 -0.333 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[12]
|
|
-------------------------------------------------------------------
|
|
required time 0.333
|
|
arrival time -0.223
|
|
-------------------------------------------------------------------
|
|
slack 0.110
|
|
|
|
Slack (MET) : 0.110ns (arrival time - required time)
|
|
Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/qprod_s4_reg[12]/C
|
|
(rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns})
|
|
Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[12]/D
|
|
(rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns})
|
|
Path Group: mlkem_clk_clk_pll
|
|
Path Type: Hold (Min at Fast Process Corner)
|
|
Requirement: 0.000ns (mlkem_clk_clk_pll rise@0.000ns - mlkem_clk_clk_pll rise@0.000ns)
|
|
Data Path Delay: 0.478ns (logic 0.279ns (58.317%) route 0.199ns (41.683%))
|
|
Logic Levels: 2 (CARRY4=1 LUT2=1)
|
|
Clock Path Skew: 0.264ns (DCD - SCD - CPR)
|
|
Destination Clock Delay (DCD): -0.478ns
|
|
Source Clock Delay (SCD): -0.702ns
|
|
Clock Pessimism Removal (CPR): -0.040ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock mlkem_clk_clk_pll rise edge)
|
|
0.000 0.000 r
|
|
clock source latency -1.848 -1.848
|
|
propagated clock network latency
|
|
1.147 -0.702
|
|
SLICE_X84Y157 FDCE 0.000 -0.702 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/qprod_s4_reg[12]/C
|
|
SLICE_X84Y157 FDCE (Prop_fdce_C_Q) 0.164 -0.538 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/qprod_s4_reg[12]/Q
|
|
net (fo=1, routed) 0.199 -0.338 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/qprod_s4[12]
|
|
SLICE_X83Y157 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5[15]_i_5/I1
|
|
SLICE_X83Y157 LUT2 (Prop_lut2_I1_O) 0.045 -0.293 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5[15]_i_5/O
|
|
net (fo=1, routed) 0.000 -0.293 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5[15]_i_5_n_0
|
|
SLICE_X83Y157 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[15]_i_1/S[0]
|
|
SLICE_X83Y157 CARRY4 (Prop_carry4_S[0]_O[0])
|
|
0.070 -0.223 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[15]_i_1/O[0]
|
|
net (fo=1, routed) 0.000 -0.223 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s50[12]
|
|
SLICE_X83Y157 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[12]/D
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock mlkem_clk_clk_pll rise edge)
|
|
0.000 0.000 r
|
|
clock source latency -1.947 -1.947
|
|
propagated clock network latency
|
|
1.469 -0.478
|
|
clock pessimism 0.040 -0.438
|
|
SLICE_X83Y157 FDCE (Hold_fdce_C_D) 0.105 -0.333 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[12]
|
|
-------------------------------------------------------------------
|
|
required time 0.333
|
|
arrival time -0.223
|
|
-------------------------------------------------------------------
|
|
slack 0.110
|
|
|
|
Slack (MET) : 0.110ns (arrival time - required time)
|
|
Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/qprod_s4_reg[12]/C
|
|
(rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns})
|
|
Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[12]/D
|
|
(rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns})
|
|
Path Group: mlkem_clk_clk_pll
|
|
Path Type: Hold (Min at Fast Process Corner)
|
|
Requirement: 0.000ns (mlkem_clk_clk_pll rise@0.000ns - mlkem_clk_clk_pll rise@0.000ns)
|
|
Data Path Delay: 0.478ns (logic 0.279ns (58.317%) route 0.199ns (41.683%))
|
|
Logic Levels: 2 (CARRY4=1 LUT2=1)
|
|
Clock Path Skew: 0.264ns (DCD - SCD - CPR)
|
|
Destination Clock Delay (DCD): -0.478ns
|
|
Source Clock Delay (SCD): -0.702ns
|
|
Clock Pessimism Removal (CPR): -0.040ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock mlkem_clk_clk_pll rise edge)
|
|
0.000 0.000 r
|
|
clock source latency -1.848 -1.848
|
|
propagated clock network latency
|
|
1.147 -0.702
|
|
SLICE_X84Y157 FDCE 0.000 -0.702 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/qprod_s4_reg[12]/C
|
|
SLICE_X84Y157 FDCE (Prop_fdce_C_Q) 0.164 -0.538 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/qprod_s4_reg[12]/Q
|
|
net (fo=1, routed) 0.199 -0.338 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/qprod_s4[12]
|
|
SLICE_X83Y157 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5[15]_i_5/I1
|
|
SLICE_X83Y157 LUT2 (Prop_lut2_I1_O) 0.045 -0.293 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5[15]_i_5/O
|
|
net (fo=1, routed) 0.000 -0.293 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5[15]_i_5_n_0
|
|
SLICE_X83Y157 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[15]_i_1/S[0]
|
|
SLICE_X83Y157 CARRY4 (Prop_carry4_S[0]_O[0])
|
|
0.070 -0.223 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[15]_i_1/O[0]
|
|
net (fo=1, routed) 0.000 -0.223 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s50[12]
|
|
SLICE_X83Y157 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[12]/D
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock mlkem_clk_clk_pll rise edge)
|
|
0.000 0.000 r
|
|
clock source latency -1.947 -1.947
|
|
propagated clock network latency
|
|
1.469 -0.478
|
|
clock pessimism 0.040 -0.438
|
|
SLICE_X83Y157 FDCE (Hold_fdce_C_D) 0.105 -0.333 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[12]
|
|
-------------------------------------------------------------------
|
|
required time 0.333
|
|
arrival time -0.223
|
|
-------------------------------------------------------------------
|
|
slack 0.110
|
|
|
|
Slack (MET) : 0.110ns (arrival time - required time)
|
|
Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/qprod_s4_reg[12]/C
|
|
(rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns})
|
|
Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[12]/D
|
|
(rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns})
|
|
Path Group: mlkem_clk_clk_pll
|
|
Path Type: Hold (Min at Fast Process Corner)
|
|
Requirement: 0.000ns (mlkem_clk_clk_pll rise@0.000ns - mlkem_clk_clk_pll rise@0.000ns)
|
|
Data Path Delay: 0.478ns (logic 0.279ns (58.317%) route 0.199ns (41.683%))
|
|
Logic Levels: 2 (CARRY4=1 LUT2=1)
|
|
Clock Path Skew: 0.264ns (DCD - SCD - CPR)
|
|
Destination Clock Delay (DCD): -0.478ns
|
|
Source Clock Delay (SCD): -0.702ns
|
|
Clock Pessimism Removal (CPR): -0.040ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock mlkem_clk_clk_pll rise edge)
|
|
0.000 0.000 r
|
|
clock source latency -1.848 -1.848
|
|
propagated clock network latency
|
|
1.147 -0.702
|
|
SLICE_X84Y157 FDCE 0.000 -0.702 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/qprod_s4_reg[12]/C
|
|
SLICE_X84Y157 FDCE (Prop_fdce_C_Q) 0.164 -0.538 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/qprod_s4_reg[12]/Q
|
|
net (fo=1, routed) 0.199 -0.338 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/qprod_s4[12]
|
|
SLICE_X83Y157 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5[15]_i_5/I1
|
|
SLICE_X83Y157 LUT2 (Prop_lut2_I1_O) 0.045 -0.293 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5[15]_i_5/O
|
|
net (fo=1, routed) 0.000 -0.293 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5[15]_i_5_n_0
|
|
SLICE_X83Y157 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[15]_i_1/S[0]
|
|
SLICE_X83Y157 CARRY4 (Prop_carry4_S[0]_O[0])
|
|
0.070 -0.223 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[15]_i_1/O[0]
|
|
net (fo=1, routed) 0.000 -0.223 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s50[12]
|
|
SLICE_X83Y157 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[12]/D
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock mlkem_clk_clk_pll rise edge)
|
|
0.000 0.000 r
|
|
clock source latency -1.947 -1.947
|
|
propagated clock network latency
|
|
1.469 -0.478
|
|
clock pessimism 0.040 -0.438
|
|
SLICE_X83Y157 FDCE (Hold_fdce_C_D) 0.105 -0.333 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[12]
|
|
-------------------------------------------------------------------
|
|
required time 0.333
|
|
arrival time -0.223
|
|
-------------------------------------------------------------------
|
|
slack 0.110
|
|
|
|
Slack (MET) : 0.110ns (arrival time - required time)
|
|
Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/qprod_s4_reg[12]/C
|
|
(rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns})
|
|
Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[12]/D
|
|
(rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns})
|
|
Path Group: mlkem_clk_clk_pll
|
|
Path Type: Hold (Min at Fast Process Corner)
|
|
Requirement: 0.000ns (mlkem_clk_clk_pll rise@0.000ns - mlkem_clk_clk_pll rise@0.000ns)
|
|
Data Path Delay: 0.478ns (logic 0.279ns (58.317%) route 0.199ns (41.683%))
|
|
Logic Levels: 2 (CARRY4=1 LUT2=1)
|
|
Clock Path Skew: 0.264ns (DCD - SCD - CPR)
|
|
Destination Clock Delay (DCD): -0.478ns
|
|
Source Clock Delay (SCD): -0.702ns
|
|
Clock Pessimism Removal (CPR): -0.040ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock mlkem_clk_clk_pll rise edge)
|
|
0.000 0.000 r
|
|
clock source latency -1.848 -1.848
|
|
propagated clock network latency
|
|
1.147 -0.702
|
|
SLICE_X84Y157 FDCE 0.000 -0.702 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/qprod_s4_reg[12]/C
|
|
SLICE_X84Y157 FDCE (Prop_fdce_C_Q) 0.164 -0.538 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/qprod_s4_reg[12]/Q
|
|
net (fo=1, routed) 0.199 -0.338 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/qprod_s4[12]
|
|
SLICE_X83Y157 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5[15]_i_5/I1
|
|
SLICE_X83Y157 LUT2 (Prop_lut2_I1_O) 0.045 -0.293 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5[15]_i_5/O
|
|
net (fo=1, routed) 0.000 -0.293 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5[15]_i_5_n_0
|
|
SLICE_X83Y157 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[15]_i_1/S[0]
|
|
SLICE_X83Y157 CARRY4 (Prop_carry4_S[0]_O[0])
|
|
0.070 -0.223 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[15]_i_1/O[0]
|
|
net (fo=1, routed) 0.000 -0.223 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s50[12]
|
|
SLICE_X83Y157 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[12]/D
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock mlkem_clk_clk_pll rise edge)
|
|
0.000 0.000 r
|
|
clock source latency -1.947 -1.947
|
|
propagated clock network latency
|
|
1.469 -0.478
|
|
clock pessimism 0.040 -0.438
|
|
SLICE_X83Y157 FDCE (Hold_fdce_C_D) 0.105 -0.333 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[12]
|
|
-------------------------------------------------------------------
|
|
required time 0.333
|
|
arrival time -0.223
|
|
-------------------------------------------------------------------
|
|
slack 0.110
|
|
|
|
Slack (MET) : 0.110ns (arrival time - required time)
|
|
Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/qprod_s4_reg[16]/C
|
|
(rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns})
|
|
Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[16]/D
|
|
(rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns})
|
|
Path Group: mlkem_clk_clk_pll
|
|
Path Type: Hold (Min at Fast Process Corner)
|
|
Requirement: 0.000ns (mlkem_clk_clk_pll rise@0.000ns - mlkem_clk_clk_pll rise@0.000ns)
|
|
Data Path Delay: 0.478ns (logic 0.279ns (58.317%) route 0.199ns (41.683%))
|
|
Logic Levels: 2 (CARRY4=1 LUT2=1)
|
|
Clock Path Skew: 0.264ns (DCD - SCD - CPR)
|
|
Destination Clock Delay (DCD): -0.478ns
|
|
Source Clock Delay (SCD): -0.702ns
|
|
Clock Pessimism Removal (CPR): -0.040ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock mlkem_clk_clk_pll rise edge)
|
|
0.000 0.000 r
|
|
clock source latency -1.848 -1.848
|
|
propagated clock network latency
|
|
1.147 -0.702
|
|
SLICE_X84Y158 FDCE 0.000 -0.702 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/qprod_s4_reg[16]/C
|
|
SLICE_X84Y158 FDCE (Prop_fdce_C_Q) 0.164 -0.538 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/qprod_s4_reg[16]/Q
|
|
net (fo=1, routed) 0.199 -0.338 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/qprod_s4[16]
|
|
SLICE_X83Y158 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5[19]_i_5/I1
|
|
SLICE_X83Y158 LUT2 (Prop_lut2_I1_O) 0.045 -0.293 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5[19]_i_5/O
|
|
net (fo=1, routed) 0.000 -0.293 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5[19]_i_5_n_0
|
|
SLICE_X83Y158 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[19]_i_1/S[0]
|
|
SLICE_X83Y158 CARRY4 (Prop_carry4_S[0]_O[0])
|
|
0.070 -0.223 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[19]_i_1/O[0]
|
|
net (fo=1, routed) 0.000 -0.223 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s50[16]
|
|
SLICE_X83Y158 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[16]/D
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock mlkem_clk_clk_pll rise edge)
|
|
0.000 0.000 r
|
|
clock source latency -1.947 -1.947
|
|
propagated clock network latency
|
|
1.469 -0.478
|
|
clock pessimism 0.040 -0.438
|
|
SLICE_X83Y158 FDCE (Hold_fdce_C_D) 0.105 -0.333 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[16]
|
|
-------------------------------------------------------------------
|
|
required time 0.333
|
|
arrival time -0.223
|
|
-------------------------------------------------------------------
|
|
slack 0.110
|
|
|
|
Slack (MET) : 0.110ns (arrival time - required time)
|
|
Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/qprod_s4_reg[16]/C
|
|
(rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns})
|
|
Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[16]/D
|
|
(rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns})
|
|
Path Group: mlkem_clk_clk_pll
|
|
Path Type: Hold (Min at Fast Process Corner)
|
|
Requirement: 0.000ns (mlkem_clk_clk_pll rise@0.000ns - mlkem_clk_clk_pll rise@0.000ns)
|
|
Data Path Delay: 0.478ns (logic 0.279ns (58.317%) route 0.199ns (41.683%))
|
|
Logic Levels: 2 (CARRY4=1 LUT2=1)
|
|
Clock Path Skew: 0.264ns (DCD - SCD - CPR)
|
|
Destination Clock Delay (DCD): -0.478ns
|
|
Source Clock Delay (SCD): -0.702ns
|
|
Clock Pessimism Removal (CPR): -0.040ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock mlkem_clk_clk_pll rise edge)
|
|
0.000 0.000 r
|
|
clock source latency -1.848 -1.848
|
|
propagated clock network latency
|
|
1.147 -0.702
|
|
SLICE_X84Y158 FDCE 0.000 -0.702 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/qprod_s4_reg[16]/C
|
|
SLICE_X84Y158 FDCE (Prop_fdce_C_Q) 0.164 -0.538 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/qprod_s4_reg[16]/Q
|
|
net (fo=1, routed) 0.199 -0.338 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/qprod_s4[16]
|
|
SLICE_X83Y158 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5[19]_i_5/I1
|
|
SLICE_X83Y158 LUT2 (Prop_lut2_I1_O) 0.045 -0.293 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5[19]_i_5/O
|
|
net (fo=1, routed) 0.000 -0.293 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5[19]_i_5_n_0
|
|
SLICE_X83Y158 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[19]_i_1/S[0]
|
|
SLICE_X83Y158 CARRY4 (Prop_carry4_S[0]_O[0])
|
|
0.070 -0.223 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[19]_i_1/O[0]
|
|
net (fo=1, routed) 0.000 -0.223 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s50[16]
|
|
SLICE_X83Y158 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[16]/D
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock mlkem_clk_clk_pll rise edge)
|
|
0.000 0.000 r
|
|
clock source latency -1.947 -1.947
|
|
propagated clock network latency
|
|
1.469 -0.478
|
|
clock pessimism 0.040 -0.438
|
|
SLICE_X83Y158 FDCE (Hold_fdce_C_D) 0.105 -0.333 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[16]
|
|
-------------------------------------------------------------------
|
|
required time 0.333
|
|
arrival time -0.223
|
|
-------------------------------------------------------------------
|
|
slack 0.110
|
|
|
|
Slack (MET) : 0.110ns (arrival time - required time)
|
|
Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/qprod_s4_reg[16]/C
|
|
(rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns})
|
|
Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[16]/D
|
|
(rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns})
|
|
Path Group: mlkem_clk_clk_pll
|
|
Path Type: Hold (Min at Fast Process Corner)
|
|
Requirement: 0.000ns (mlkem_clk_clk_pll rise@0.000ns - mlkem_clk_clk_pll rise@0.000ns)
|
|
Data Path Delay: 0.478ns (logic 0.279ns (58.317%) route 0.199ns (41.683%))
|
|
Logic Levels: 2 (CARRY4=1 LUT2=1)
|
|
Clock Path Skew: 0.264ns (DCD - SCD - CPR)
|
|
Destination Clock Delay (DCD): -0.478ns
|
|
Source Clock Delay (SCD): -0.702ns
|
|
Clock Pessimism Removal (CPR): -0.040ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock mlkem_clk_clk_pll rise edge)
|
|
0.000 0.000 r
|
|
clock source latency -1.848 -1.848
|
|
propagated clock network latency
|
|
1.147 -0.702
|
|
SLICE_X84Y158 FDCE 0.000 -0.702 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/qprod_s4_reg[16]/C
|
|
SLICE_X84Y158 FDCE (Prop_fdce_C_Q) 0.164 -0.538 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/qprod_s4_reg[16]/Q
|
|
net (fo=1, routed) 0.199 -0.338 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/qprod_s4[16]
|
|
SLICE_X83Y158 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5[19]_i_5/I1
|
|
SLICE_X83Y158 LUT2 (Prop_lut2_I1_O) 0.045 -0.293 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5[19]_i_5/O
|
|
net (fo=1, routed) 0.000 -0.293 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5[19]_i_5_n_0
|
|
SLICE_X83Y158 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[19]_i_1/S[0]
|
|
SLICE_X83Y158 CARRY4 (Prop_carry4_S[0]_O[0])
|
|
0.070 -0.223 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[19]_i_1/O[0]
|
|
net (fo=1, routed) 0.000 -0.223 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s50[16]
|
|
SLICE_X83Y158 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[16]/D
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock mlkem_clk_clk_pll rise edge)
|
|
0.000 0.000 r
|
|
clock source latency -1.947 -1.947
|
|
propagated clock network latency
|
|
1.469 -0.478
|
|
clock pessimism 0.040 -0.438
|
|
SLICE_X83Y158 FDCE (Hold_fdce_C_D) 0.105 -0.333 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[16]
|
|
-------------------------------------------------------------------
|
|
required time 0.333
|
|
arrival time -0.223
|
|
-------------------------------------------------------------------
|
|
slack 0.110
|
|
|
|
Slack (MET) : 0.110ns (arrival time - required time)
|
|
Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/qprod_s4_reg[16]/C
|
|
(rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns})
|
|
Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[16]/D
|
|
(rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns})
|
|
Path Group: mlkem_clk_clk_pll
|
|
Path Type: Hold (Min at Fast Process Corner)
|
|
Requirement: 0.000ns (mlkem_clk_clk_pll rise@0.000ns - mlkem_clk_clk_pll rise@0.000ns)
|
|
Data Path Delay: 0.478ns (logic 0.279ns (58.317%) route 0.199ns (41.683%))
|
|
Logic Levels: 2 (CARRY4=1 LUT2=1)
|
|
Clock Path Skew: 0.264ns (DCD - SCD - CPR)
|
|
Destination Clock Delay (DCD): -0.478ns
|
|
Source Clock Delay (SCD): -0.702ns
|
|
Clock Pessimism Removal (CPR): -0.040ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock mlkem_clk_clk_pll rise edge)
|
|
0.000 0.000 r
|
|
clock source latency -1.848 -1.848
|
|
propagated clock network latency
|
|
1.147 -0.702
|
|
SLICE_X84Y158 FDCE 0.000 -0.702 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/qprod_s4_reg[16]/C
|
|
SLICE_X84Y158 FDCE (Prop_fdce_C_Q) 0.164 -0.538 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/qprod_s4_reg[16]/Q
|
|
net (fo=1, routed) 0.199 -0.338 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/qprod_s4[16]
|
|
SLICE_X83Y158 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5[19]_i_5/I1
|
|
SLICE_X83Y158 LUT2 (Prop_lut2_I1_O) 0.045 -0.293 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5[19]_i_5/O
|
|
net (fo=1, routed) 0.000 -0.293 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5[19]_i_5_n_0
|
|
SLICE_X83Y158 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[19]_i_1/S[0]
|
|
SLICE_X83Y158 CARRY4 (Prop_carry4_S[0]_O[0])
|
|
0.070 -0.223 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[19]_i_1/O[0]
|
|
net (fo=1, routed) 0.000 -0.223 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s50[16]
|
|
SLICE_X83Y158 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[16]/D
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock mlkem_clk_clk_pll rise edge)
|
|
0.000 0.000 r
|
|
clock source latency -1.947 -1.947
|
|
propagated clock network latency
|
|
1.469 -0.478
|
|
clock pessimism 0.040 -0.438
|
|
SLICE_X83Y158 FDCE (Hold_fdce_C_D) 0.105 -0.333 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[16]
|
|
-------------------------------------------------------------------
|
|
required time 0.333
|
|
arrival time -0.223
|
|
-------------------------------------------------------------------
|
|
slack 0.110
|
|
|
|
Slack (MET) : 0.110ns (arrival time - required time)
|
|
Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/qprod_s4_reg[16]/C
|
|
(rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns})
|
|
Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[16]/D
|
|
(rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns})
|
|
Path Group: mlkem_clk_clk_pll
|
|
Path Type: Hold (Min at Fast Process Corner)
|
|
Requirement: 0.000ns (mlkem_clk_clk_pll rise@0.000ns - mlkem_clk_clk_pll rise@0.000ns)
|
|
Data Path Delay: 0.478ns (logic 0.279ns (58.317%) route 0.199ns (41.683%))
|
|
Logic Levels: 2 (CARRY4=1 LUT2=1)
|
|
Clock Path Skew: 0.264ns (DCD - SCD - CPR)
|
|
Destination Clock Delay (DCD): -0.478ns
|
|
Source Clock Delay (SCD): -0.702ns
|
|
Clock Pessimism Removal (CPR): -0.040ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock mlkem_clk_clk_pll rise edge)
|
|
0.000 0.000 r
|
|
clock source latency -1.848 -1.848
|
|
propagated clock network latency
|
|
1.147 -0.702
|
|
SLICE_X84Y158 FDCE 0.000 -0.702 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/qprod_s4_reg[16]/C
|
|
SLICE_X84Y158 FDCE (Prop_fdce_C_Q) 0.164 -0.538 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/qprod_s4_reg[16]/Q
|
|
net (fo=1, routed) 0.199 -0.338 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/qprod_s4[16]
|
|
SLICE_X83Y158 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5[19]_i_5/I1
|
|
SLICE_X83Y158 LUT2 (Prop_lut2_I1_O) 0.045 -0.293 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5[19]_i_5/O
|
|
net (fo=1, routed) 0.000 -0.293 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5[19]_i_5_n_0
|
|
SLICE_X83Y158 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[19]_i_1/S[0]
|
|
SLICE_X83Y158 CARRY4 (Prop_carry4_S[0]_O[0])
|
|
0.070 -0.223 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[19]_i_1/O[0]
|
|
net (fo=1, routed) 0.000 -0.223 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s50[16]
|
|
SLICE_X83Y158 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[16]/D
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock mlkem_clk_clk_pll rise edge)
|
|
0.000 0.000 r
|
|
clock source latency -1.947 -1.947
|
|
propagated clock network latency
|
|
1.469 -0.478
|
|
clock pessimism 0.040 -0.438
|
|
SLICE_X83Y158 FDCE (Hold_fdce_C_D) 0.105 -0.333 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[16]
|
|
-------------------------------------------------------------------
|
|
required time 0.333
|
|
arrival time -0.223
|
|
-------------------------------------------------------------------
|
|
slack 0.110
|
|
|
|
Slack (MET) : 0.110ns (arrival time - required time)
|
|
Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/qprod_s4_reg[16]/C
|
|
(rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns})
|
|
Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[16]/D
|
|
(rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns})
|
|
Path Group: mlkem_clk_clk_pll
|
|
Path Type: Hold (Min at Fast Process Corner)
|
|
Requirement: 0.000ns (mlkem_clk_clk_pll rise@0.000ns - mlkem_clk_clk_pll rise@0.000ns)
|
|
Data Path Delay: 0.478ns (logic 0.279ns (58.317%) route 0.199ns (41.683%))
|
|
Logic Levels: 2 (CARRY4=1 LUT2=1)
|
|
Clock Path Skew: 0.264ns (DCD - SCD - CPR)
|
|
Destination Clock Delay (DCD): -0.478ns
|
|
Source Clock Delay (SCD): -0.702ns
|
|
Clock Pessimism Removal (CPR): -0.040ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock mlkem_clk_clk_pll rise edge)
|
|
0.000 0.000 r
|
|
clock source latency -1.848 -1.848
|
|
propagated clock network latency
|
|
1.147 -0.702
|
|
SLICE_X84Y158 FDCE 0.000 -0.702 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/qprod_s4_reg[16]/C
|
|
SLICE_X84Y158 FDCE (Prop_fdce_C_Q) 0.164 -0.538 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/qprod_s4_reg[16]/Q
|
|
net (fo=1, routed) 0.199 -0.338 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/qprod_s4[16]
|
|
SLICE_X83Y158 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5[19]_i_5/I1
|
|
SLICE_X83Y158 LUT2 (Prop_lut2_I1_O) 0.045 -0.293 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5[19]_i_5/O
|
|
net (fo=1, routed) 0.000 -0.293 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5[19]_i_5_n_0
|
|
SLICE_X83Y158 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[19]_i_1/S[0]
|
|
SLICE_X83Y158 CARRY4 (Prop_carry4_S[0]_O[0])
|
|
0.070 -0.223 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[19]_i_1/O[0]
|
|
net (fo=1, routed) 0.000 -0.223 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s50[16]
|
|
SLICE_X83Y158 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[16]/D
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock mlkem_clk_clk_pll rise edge)
|
|
0.000 0.000 r
|
|
clock source latency -1.947 -1.947
|
|
propagated clock network latency
|
|
1.469 -0.478
|
|
clock pessimism 0.040 -0.438
|
|
SLICE_X83Y158 FDCE (Hold_fdce_C_D) 0.105 -0.333 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[16]
|
|
-------------------------------------------------------------------
|
|
required time 0.333
|
|
arrival time -0.223
|
|
-------------------------------------------------------------------
|
|
slack 0.110
|
|
|
|
Slack (MET) : 0.110ns (arrival time - required time)
|
|
Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/qprod_s4_reg[16]/C
|
|
(rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns})
|
|
Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[16]/D
|
|
(rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns})
|
|
Path Group: mlkem_clk_clk_pll
|
|
Path Type: Hold (Min at Fast Process Corner)
|
|
Requirement: 0.000ns (mlkem_clk_clk_pll rise@0.000ns - mlkem_clk_clk_pll rise@0.000ns)
|
|
Data Path Delay: 0.478ns (logic 0.279ns (58.317%) route 0.199ns (41.683%))
|
|
Logic Levels: 2 (CARRY4=1 LUT2=1)
|
|
Clock Path Skew: 0.264ns (DCD - SCD - CPR)
|
|
Destination Clock Delay (DCD): -0.478ns
|
|
Source Clock Delay (SCD): -0.702ns
|
|
Clock Pessimism Removal (CPR): -0.040ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock mlkem_clk_clk_pll rise edge)
|
|
0.000 0.000 r
|
|
clock source latency -1.848 -1.848
|
|
propagated clock network latency
|
|
1.147 -0.702
|
|
SLICE_X84Y158 FDCE 0.000 -0.702 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/qprod_s4_reg[16]/C
|
|
SLICE_X84Y158 FDCE (Prop_fdce_C_Q) 0.164 -0.538 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/qprod_s4_reg[16]/Q
|
|
net (fo=1, routed) 0.199 -0.338 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/qprod_s4[16]
|
|
SLICE_X83Y158 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5[19]_i_5/I1
|
|
SLICE_X83Y158 LUT2 (Prop_lut2_I1_O) 0.045 -0.293 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5[19]_i_5/O
|
|
net (fo=1, routed) 0.000 -0.293 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5[19]_i_5_n_0
|
|
SLICE_X83Y158 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[19]_i_1/S[0]
|
|
SLICE_X83Y158 CARRY4 (Prop_carry4_S[0]_O[0])
|
|
0.070 -0.223 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[19]_i_1/O[0]
|
|
net (fo=1, routed) 0.000 -0.223 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s50[16]
|
|
SLICE_X83Y158 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[16]/D
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock mlkem_clk_clk_pll rise edge)
|
|
0.000 0.000 r
|
|
clock source latency -1.947 -1.947
|
|
propagated clock network latency
|
|
1.469 -0.478
|
|
clock pessimism 0.040 -0.438
|
|
SLICE_X83Y158 FDCE (Hold_fdce_C_D) 0.105 -0.333 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[16]
|
|
-------------------------------------------------------------------
|
|
required time 0.333
|
|
arrival time -0.223
|
|
-------------------------------------------------------------------
|
|
slack 0.110
|
|
|
|
Slack (MET) : 0.110ns (arrival time - required time)
|
|
Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/qprod_s4_reg[16]/C
|
|
(rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns})
|
|
Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[16]/D
|
|
(rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns})
|
|
Path Group: mlkem_clk_clk_pll
|
|
Path Type: Hold (Min at Fast Process Corner)
|
|
Requirement: 0.000ns (mlkem_clk_clk_pll rise@0.000ns - mlkem_clk_clk_pll rise@0.000ns)
|
|
Data Path Delay: 0.478ns (logic 0.279ns (58.317%) route 0.199ns (41.683%))
|
|
Logic Levels: 2 (CARRY4=1 LUT2=1)
|
|
Clock Path Skew: 0.264ns (DCD - SCD - CPR)
|
|
Destination Clock Delay (DCD): -0.478ns
|
|
Source Clock Delay (SCD): -0.702ns
|
|
Clock Pessimism Removal (CPR): -0.040ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock mlkem_clk_clk_pll rise edge)
|
|
0.000 0.000 r
|
|
clock source latency -1.848 -1.848
|
|
propagated clock network latency
|
|
1.147 -0.702
|
|
SLICE_X84Y158 FDCE 0.000 -0.702 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/qprod_s4_reg[16]/C
|
|
SLICE_X84Y158 FDCE (Prop_fdce_C_Q) 0.164 -0.538 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/qprod_s4_reg[16]/Q
|
|
net (fo=1, routed) 0.199 -0.338 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/qprod_s4[16]
|
|
SLICE_X83Y158 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5[19]_i_5/I1
|
|
SLICE_X83Y158 LUT2 (Prop_lut2_I1_O) 0.045 -0.293 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5[19]_i_5/O
|
|
net (fo=1, routed) 0.000 -0.293 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5[19]_i_5_n_0
|
|
SLICE_X83Y158 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[19]_i_1/S[0]
|
|
SLICE_X83Y158 CARRY4 (Prop_carry4_S[0]_O[0])
|
|
0.070 -0.223 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[19]_i_1/O[0]
|
|
net (fo=1, routed) 0.000 -0.223 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s50[16]
|
|
SLICE_X83Y158 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[16]/D
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock mlkem_clk_clk_pll rise edge)
|
|
0.000 0.000 r
|
|
clock source latency -1.947 -1.947
|
|
propagated clock network latency
|
|
1.469 -0.478
|
|
clock pessimism 0.040 -0.438
|
|
SLICE_X83Y158 FDCE (Hold_fdce_C_D) 0.105 -0.333 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[16]
|
|
-------------------------------------------------------------------
|
|
required time 0.333
|
|
arrival time -0.223
|
|
-------------------------------------------------------------------
|
|
slack 0.110
|
|
|
|
Slack (MET) : 0.110ns (arrival time - required time)
|
|
Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/qprod_s4_reg[20]/C
|
|
(rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns})
|
|
Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[20]/D
|
|
(rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns})
|
|
Path Group: mlkem_clk_clk_pll
|
|
Path Type: Hold (Min at Fast Process Corner)
|
|
Requirement: 0.000ns (mlkem_clk_clk_pll rise@0.000ns - mlkem_clk_clk_pll rise@0.000ns)
|
|
Data Path Delay: 0.478ns (logic 0.279ns (58.317%) route 0.199ns (41.683%))
|
|
Logic Levels: 2 (CARRY4=1 LUT2=1)
|
|
Clock Path Skew: 0.264ns (DCD - SCD - CPR)
|
|
Destination Clock Delay (DCD): -0.478ns
|
|
Source Clock Delay (SCD): -0.702ns
|
|
Clock Pessimism Removal (CPR): -0.040ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock mlkem_clk_clk_pll rise edge)
|
|
0.000 0.000 r
|
|
clock source latency -1.848 -1.848
|
|
propagated clock network latency
|
|
1.147 -0.702
|
|
SLICE_X84Y159 FDCE 0.000 -0.702 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/qprod_s4_reg[20]/C
|
|
SLICE_X84Y159 FDCE (Prop_fdce_C_Q) 0.164 -0.538 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/qprod_s4_reg[20]/Q
|
|
net (fo=1, routed) 0.199 -0.338 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/qprod_s4[20]
|
|
SLICE_X83Y159 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5[23]_i_5/I1
|
|
SLICE_X83Y159 LUT2 (Prop_lut2_I1_O) 0.045 -0.293 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5[23]_i_5/O
|
|
net (fo=1, routed) 0.000 -0.293 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5[23]_i_5_n_0
|
|
SLICE_X83Y159 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[23]_i_1/S[0]
|
|
SLICE_X83Y159 CARRY4 (Prop_carry4_S[0]_O[0])
|
|
0.070 -0.223 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[23]_i_1/O[0]
|
|
net (fo=1, routed) 0.000 -0.223 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s50[20]
|
|
SLICE_X83Y159 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[20]/D
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock mlkem_clk_clk_pll rise edge)
|
|
0.000 0.000 r
|
|
clock source latency -1.947 -1.947
|
|
propagated clock network latency
|
|
1.469 -0.478
|
|
clock pessimism 0.040 -0.438
|
|
SLICE_X83Y159 FDCE (Hold_fdce_C_D) 0.105 -0.333 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[20]
|
|
-------------------------------------------------------------------
|
|
required time 0.333
|
|
arrival time -0.223
|
|
-------------------------------------------------------------------
|
|
slack 0.110
|
|
|
|
Slack (MET) : 0.110ns (arrival time - required time)
|
|
Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/qprod_s4_reg[20]/C
|
|
(rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns})
|
|
Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[20]/D
|
|
(rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns})
|
|
Path Group: mlkem_clk_clk_pll
|
|
Path Type: Hold (Min at Fast Process Corner)
|
|
Requirement: 0.000ns (mlkem_clk_clk_pll rise@0.000ns - mlkem_clk_clk_pll rise@0.000ns)
|
|
Data Path Delay: 0.478ns (logic 0.279ns (58.317%) route 0.199ns (41.683%))
|
|
Logic Levels: 2 (CARRY4=1 LUT2=1)
|
|
Clock Path Skew: 0.264ns (DCD - SCD - CPR)
|
|
Destination Clock Delay (DCD): -0.478ns
|
|
Source Clock Delay (SCD): -0.702ns
|
|
Clock Pessimism Removal (CPR): -0.040ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock mlkem_clk_clk_pll rise edge)
|
|
0.000 0.000 r
|
|
clock source latency -1.848 -1.848
|
|
propagated clock network latency
|
|
1.147 -0.702
|
|
SLICE_X84Y159 FDCE 0.000 -0.702 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/qprod_s4_reg[20]/C
|
|
SLICE_X84Y159 FDCE (Prop_fdce_C_Q) 0.164 -0.538 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/qprod_s4_reg[20]/Q
|
|
net (fo=1, routed) 0.199 -0.338 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/qprod_s4[20]
|
|
SLICE_X83Y159 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5[23]_i_5/I1
|
|
SLICE_X83Y159 LUT2 (Prop_lut2_I1_O) 0.045 -0.293 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5[23]_i_5/O
|
|
net (fo=1, routed) 0.000 -0.293 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5[23]_i_5_n_0
|
|
SLICE_X83Y159 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[23]_i_1/S[0]
|
|
SLICE_X83Y159 CARRY4 (Prop_carry4_S[0]_O[0])
|
|
0.070 -0.223 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[23]_i_1/O[0]
|
|
net (fo=1, routed) 0.000 -0.223 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s50[20]
|
|
SLICE_X83Y159 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[20]/D
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock mlkem_clk_clk_pll rise edge)
|
|
0.000 0.000 r
|
|
clock source latency -1.947 -1.947
|
|
propagated clock network latency
|
|
1.469 -0.478
|
|
clock pessimism 0.040 -0.438
|
|
SLICE_X83Y159 FDCE (Hold_fdce_C_D) 0.105 -0.333 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[20]
|
|
-------------------------------------------------------------------
|
|
required time 0.333
|
|
arrival time -0.223
|
|
-------------------------------------------------------------------
|
|
slack 0.110
|
|
|
|
Slack (MET) : 0.110ns (arrival time - required time)
|
|
Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/qprod_s4_reg[20]/C
|
|
(rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns})
|
|
Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[20]/D
|
|
(rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns})
|
|
Path Group: mlkem_clk_clk_pll
|
|
Path Type: Hold (Min at Fast Process Corner)
|
|
Requirement: 0.000ns (mlkem_clk_clk_pll rise@0.000ns - mlkem_clk_clk_pll rise@0.000ns)
|
|
Data Path Delay: 0.478ns (logic 0.279ns (58.317%) route 0.199ns (41.683%))
|
|
Logic Levels: 2 (CARRY4=1 LUT2=1)
|
|
Clock Path Skew: 0.264ns (DCD - SCD - CPR)
|
|
Destination Clock Delay (DCD): -0.478ns
|
|
Source Clock Delay (SCD): -0.702ns
|
|
Clock Pessimism Removal (CPR): -0.040ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock mlkem_clk_clk_pll rise edge)
|
|
0.000 0.000 r
|
|
clock source latency -1.848 -1.848
|
|
propagated clock network latency
|
|
1.147 -0.702
|
|
SLICE_X84Y159 FDCE 0.000 -0.702 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/qprod_s4_reg[20]/C
|
|
SLICE_X84Y159 FDCE (Prop_fdce_C_Q) 0.164 -0.538 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/qprod_s4_reg[20]/Q
|
|
net (fo=1, routed) 0.199 -0.338 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/qprod_s4[20]
|
|
SLICE_X83Y159 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5[23]_i_5/I1
|
|
SLICE_X83Y159 LUT2 (Prop_lut2_I1_O) 0.045 -0.293 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5[23]_i_5/O
|
|
net (fo=1, routed) 0.000 -0.293 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5[23]_i_5_n_0
|
|
SLICE_X83Y159 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[23]_i_1/S[0]
|
|
SLICE_X83Y159 CARRY4 (Prop_carry4_S[0]_O[0])
|
|
0.070 -0.223 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[23]_i_1/O[0]
|
|
net (fo=1, routed) 0.000 -0.223 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s50[20]
|
|
SLICE_X83Y159 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[20]/D
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock mlkem_clk_clk_pll rise edge)
|
|
0.000 0.000 r
|
|
clock source latency -1.947 -1.947
|
|
propagated clock network latency
|
|
1.469 -0.478
|
|
clock pessimism 0.040 -0.438
|
|
SLICE_X83Y159 FDCE (Hold_fdce_C_D) 0.105 -0.333 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[20]
|
|
-------------------------------------------------------------------
|
|
required time 0.333
|
|
arrival time -0.223
|
|
-------------------------------------------------------------------
|
|
slack 0.110
|
|
|
|
Slack (MET) : 0.110ns (arrival time - required time)
|
|
Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/qprod_s4_reg[20]/C
|
|
(rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns})
|
|
Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[20]/D
|
|
(rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns})
|
|
Path Group: mlkem_clk_clk_pll
|
|
Path Type: Hold (Min at Fast Process Corner)
|
|
Requirement: 0.000ns (mlkem_clk_clk_pll rise@0.000ns - mlkem_clk_clk_pll rise@0.000ns)
|
|
Data Path Delay: 0.478ns (logic 0.279ns (58.317%) route 0.199ns (41.683%))
|
|
Logic Levels: 2 (CARRY4=1 LUT2=1)
|
|
Clock Path Skew: 0.264ns (DCD - SCD - CPR)
|
|
Destination Clock Delay (DCD): -0.478ns
|
|
Source Clock Delay (SCD): -0.702ns
|
|
Clock Pessimism Removal (CPR): -0.040ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock mlkem_clk_clk_pll rise edge)
|
|
0.000 0.000 r
|
|
clock source latency -1.848 -1.848
|
|
propagated clock network latency
|
|
1.147 -0.702
|
|
SLICE_X84Y159 FDCE 0.000 -0.702 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/qprod_s4_reg[20]/C
|
|
SLICE_X84Y159 FDCE (Prop_fdce_C_Q) 0.164 -0.538 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/qprod_s4_reg[20]/Q
|
|
net (fo=1, routed) 0.199 -0.338 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/qprod_s4[20]
|
|
SLICE_X83Y159 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5[23]_i_5/I1
|
|
SLICE_X83Y159 LUT2 (Prop_lut2_I1_O) 0.045 -0.293 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5[23]_i_5/O
|
|
net (fo=1, routed) 0.000 -0.293 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5[23]_i_5_n_0
|
|
SLICE_X83Y159 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[23]_i_1/S[0]
|
|
SLICE_X83Y159 CARRY4 (Prop_carry4_S[0]_O[0])
|
|
0.070 -0.223 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[23]_i_1/O[0]
|
|
net (fo=1, routed) 0.000 -0.223 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s50[20]
|
|
SLICE_X83Y159 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[20]/D
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock mlkem_clk_clk_pll rise edge)
|
|
0.000 0.000 r
|
|
clock source latency -1.947 -1.947
|
|
propagated clock network latency
|
|
1.469 -0.478
|
|
clock pessimism 0.040 -0.438
|
|
SLICE_X83Y159 FDCE (Hold_fdce_C_D) 0.105 -0.333 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[20]
|
|
-------------------------------------------------------------------
|
|
required time 0.333
|
|
arrival time -0.223
|
|
-------------------------------------------------------------------
|
|
slack 0.110
|
|
|
|
Slack (MET) : 0.110ns (arrival time - required time)
|
|
Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/qprod_s4_reg[20]/C
|
|
(rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns})
|
|
Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[20]/D
|
|
(rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns})
|
|
Path Group: mlkem_clk_clk_pll
|
|
Path Type: Hold (Min at Fast Process Corner)
|
|
Requirement: 0.000ns (mlkem_clk_clk_pll rise@0.000ns - mlkem_clk_clk_pll rise@0.000ns)
|
|
Data Path Delay: 0.478ns (logic 0.279ns (58.317%) route 0.199ns (41.683%))
|
|
Logic Levels: 2 (CARRY4=1 LUT2=1)
|
|
Clock Path Skew: 0.264ns (DCD - SCD - CPR)
|
|
Destination Clock Delay (DCD): -0.478ns
|
|
Source Clock Delay (SCD): -0.702ns
|
|
Clock Pessimism Removal (CPR): -0.040ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock mlkem_clk_clk_pll rise edge)
|
|
0.000 0.000 r
|
|
clock source latency -1.848 -1.848
|
|
propagated clock network latency
|
|
1.147 -0.702
|
|
SLICE_X84Y159 FDCE 0.000 -0.702 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/qprod_s4_reg[20]/C
|
|
SLICE_X84Y159 FDCE (Prop_fdce_C_Q) 0.164 -0.538 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/qprod_s4_reg[20]/Q
|
|
net (fo=1, routed) 0.199 -0.338 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/qprod_s4[20]
|
|
SLICE_X83Y159 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5[23]_i_5/I1
|
|
SLICE_X83Y159 LUT2 (Prop_lut2_I1_O) 0.045 -0.293 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5[23]_i_5/O
|
|
net (fo=1, routed) 0.000 -0.293 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5[23]_i_5_n_0
|
|
SLICE_X83Y159 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[23]_i_1/S[0]
|
|
SLICE_X83Y159 CARRY4 (Prop_carry4_S[0]_O[0])
|
|
0.070 -0.223 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[23]_i_1/O[0]
|
|
net (fo=1, routed) 0.000 -0.223 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s50[20]
|
|
SLICE_X83Y159 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[20]/D
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock mlkem_clk_clk_pll rise edge)
|
|
0.000 0.000 r
|
|
clock source latency -1.947 -1.947
|
|
propagated clock network latency
|
|
1.469 -0.478
|
|
clock pessimism 0.040 -0.438
|
|
SLICE_X83Y159 FDCE (Hold_fdce_C_D) 0.105 -0.333 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[20]
|
|
-------------------------------------------------------------------
|
|
required time 0.333
|
|
arrival time -0.223
|
|
-------------------------------------------------------------------
|
|
slack 0.110
|
|
|
|
Slack (MET) : 0.110ns (arrival time - required time)
|
|
Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/qprod_s4_reg[20]/C
|
|
(rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns})
|
|
Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[20]/D
|
|
(rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns})
|
|
Path Group: mlkem_clk_clk_pll
|
|
Path Type: Hold (Min at Fast Process Corner)
|
|
Requirement: 0.000ns (mlkem_clk_clk_pll rise@0.000ns - mlkem_clk_clk_pll rise@0.000ns)
|
|
Data Path Delay: 0.478ns (logic 0.279ns (58.317%) route 0.199ns (41.683%))
|
|
Logic Levels: 2 (CARRY4=1 LUT2=1)
|
|
Clock Path Skew: 0.264ns (DCD - SCD - CPR)
|
|
Destination Clock Delay (DCD): -0.478ns
|
|
Source Clock Delay (SCD): -0.702ns
|
|
Clock Pessimism Removal (CPR): -0.040ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock mlkem_clk_clk_pll rise edge)
|
|
0.000 0.000 r
|
|
clock source latency -1.848 -1.848
|
|
propagated clock network latency
|
|
1.147 -0.702
|
|
SLICE_X84Y159 FDCE 0.000 -0.702 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/qprod_s4_reg[20]/C
|
|
SLICE_X84Y159 FDCE (Prop_fdce_C_Q) 0.164 -0.538 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/qprod_s4_reg[20]/Q
|
|
net (fo=1, routed) 0.199 -0.338 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/qprod_s4[20]
|
|
SLICE_X83Y159 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5[23]_i_5/I1
|
|
SLICE_X83Y159 LUT2 (Prop_lut2_I1_O) 0.045 -0.293 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5[23]_i_5/O
|
|
net (fo=1, routed) 0.000 -0.293 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5[23]_i_5_n_0
|
|
SLICE_X83Y159 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[23]_i_1/S[0]
|
|
SLICE_X83Y159 CARRY4 (Prop_carry4_S[0]_O[0])
|
|
0.070 -0.223 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[23]_i_1/O[0]
|
|
net (fo=1, routed) 0.000 -0.223 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s50[20]
|
|
SLICE_X83Y159 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[20]/D
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock mlkem_clk_clk_pll rise edge)
|
|
0.000 0.000 r
|
|
clock source latency -1.947 -1.947
|
|
propagated clock network latency
|
|
1.469 -0.478
|
|
clock pessimism 0.040 -0.438
|
|
SLICE_X83Y159 FDCE (Hold_fdce_C_D) 0.105 -0.333 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[20]
|
|
-------------------------------------------------------------------
|
|
required time 0.333
|
|
arrival time -0.223
|
|
-------------------------------------------------------------------
|
|
slack 0.110
|
|
|
|
Slack (MET) : 0.110ns (arrival time - required time)
|
|
Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/qprod_s4_reg[20]/C
|
|
(rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns})
|
|
Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[20]/D
|
|
(rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns})
|
|
Path Group: mlkem_clk_clk_pll
|
|
Path Type: Hold (Min at Fast Process Corner)
|
|
Requirement: 0.000ns (mlkem_clk_clk_pll rise@0.000ns - mlkem_clk_clk_pll rise@0.000ns)
|
|
Data Path Delay: 0.478ns (logic 0.279ns (58.317%) route 0.199ns (41.683%))
|
|
Logic Levels: 2 (CARRY4=1 LUT2=1)
|
|
Clock Path Skew: 0.264ns (DCD - SCD - CPR)
|
|
Destination Clock Delay (DCD): -0.478ns
|
|
Source Clock Delay (SCD): -0.702ns
|
|
Clock Pessimism Removal (CPR): -0.040ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock mlkem_clk_clk_pll rise edge)
|
|
0.000 0.000 r
|
|
clock source latency -1.848 -1.848
|
|
propagated clock network latency
|
|
1.147 -0.702
|
|
SLICE_X84Y159 FDCE 0.000 -0.702 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/qprod_s4_reg[20]/C
|
|
SLICE_X84Y159 FDCE (Prop_fdce_C_Q) 0.164 -0.538 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/qprod_s4_reg[20]/Q
|
|
net (fo=1, routed) 0.199 -0.338 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/qprod_s4[20]
|
|
SLICE_X83Y159 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5[23]_i_5/I1
|
|
SLICE_X83Y159 LUT2 (Prop_lut2_I1_O) 0.045 -0.293 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5[23]_i_5/O
|
|
net (fo=1, routed) 0.000 -0.293 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5[23]_i_5_n_0
|
|
SLICE_X83Y159 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[23]_i_1/S[0]
|
|
SLICE_X83Y159 CARRY4 (Prop_carry4_S[0]_O[0])
|
|
0.070 -0.223 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[23]_i_1/O[0]
|
|
net (fo=1, routed) 0.000 -0.223 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s50[20]
|
|
SLICE_X83Y159 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[20]/D
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock mlkem_clk_clk_pll rise edge)
|
|
0.000 0.000 r
|
|
clock source latency -1.947 -1.947
|
|
propagated clock network latency
|
|
1.469 -0.478
|
|
clock pessimism 0.040 -0.438
|
|
SLICE_X83Y159 FDCE (Hold_fdce_C_D) 0.105 -0.333 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[20]
|
|
-------------------------------------------------------------------
|
|
required time 0.333
|
|
arrival time -0.223
|
|
-------------------------------------------------------------------
|
|
slack 0.110
|
|
|
|
Slack (MET) : 0.110ns (arrival time - required time)
|
|
Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/qprod_s4_reg[20]/C
|
|
(rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns})
|
|
Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[20]/D
|
|
(rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns})
|
|
Path Group: mlkem_clk_clk_pll
|
|
Path Type: Hold (Min at Fast Process Corner)
|
|
Requirement: 0.000ns (mlkem_clk_clk_pll rise@0.000ns - mlkem_clk_clk_pll rise@0.000ns)
|
|
Data Path Delay: 0.478ns (logic 0.279ns (58.317%) route 0.199ns (41.683%))
|
|
Logic Levels: 2 (CARRY4=1 LUT2=1)
|
|
Clock Path Skew: 0.264ns (DCD - SCD - CPR)
|
|
Destination Clock Delay (DCD): -0.478ns
|
|
Source Clock Delay (SCD): -0.702ns
|
|
Clock Pessimism Removal (CPR): -0.040ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock mlkem_clk_clk_pll rise edge)
|
|
0.000 0.000 r
|
|
clock source latency -1.848 -1.848
|
|
propagated clock network latency
|
|
1.147 -0.702
|
|
SLICE_X84Y159 FDCE 0.000 -0.702 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/qprod_s4_reg[20]/C
|
|
SLICE_X84Y159 FDCE (Prop_fdce_C_Q) 0.164 -0.538 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/qprod_s4_reg[20]/Q
|
|
net (fo=1, routed) 0.199 -0.338 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/qprod_s4[20]
|
|
SLICE_X83Y159 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5[23]_i_5/I1
|
|
SLICE_X83Y159 LUT2 (Prop_lut2_I1_O) 0.045 -0.293 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5[23]_i_5/O
|
|
net (fo=1, routed) 0.000 -0.293 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5[23]_i_5_n_0
|
|
SLICE_X83Y159 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[23]_i_1/S[0]
|
|
SLICE_X83Y159 CARRY4 (Prop_carry4_S[0]_O[0])
|
|
0.070 -0.223 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[23]_i_1/O[0]
|
|
net (fo=1, routed) 0.000 -0.223 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s50[20]
|
|
SLICE_X83Y159 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[20]/D
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock mlkem_clk_clk_pll rise edge)
|
|
0.000 0.000 r
|
|
clock source latency -1.947 -1.947
|
|
propagated clock network latency
|
|
1.469 -0.478
|
|
clock pessimism 0.040 -0.438
|
|
SLICE_X83Y159 FDCE (Hold_fdce_C_D) 0.105 -0.333 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[20]
|
|
-------------------------------------------------------------------
|
|
required time 0.333
|
|
arrival time -0.223
|
|
-------------------------------------------------------------------
|
|
slack 0.110
|
|
|
|
Slack (MET) : 0.110ns (arrival time - required time)
|
|
Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/qprod_s4_reg[8]/C
|
|
(rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns})
|
|
Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[8]/D
|
|
(rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns})
|
|
Path Group: mlkem_clk_clk_pll
|
|
Path Type: Hold (Min at Fast Process Corner)
|
|
Requirement: 0.000ns (mlkem_clk_clk_pll rise@0.000ns - mlkem_clk_clk_pll rise@0.000ns)
|
|
Data Path Delay: 0.478ns (logic 0.279ns (58.317%) route 0.199ns (41.683%))
|
|
Logic Levels: 2 (CARRY4=1 LUT2=1)
|
|
Clock Path Skew: 0.264ns (DCD - SCD - CPR)
|
|
Destination Clock Delay (DCD): -0.477ns
|
|
Source Clock Delay (SCD): -0.701ns
|
|
Clock Pessimism Removal (CPR): -0.040ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock mlkem_clk_clk_pll rise edge)
|
|
0.000 0.000 r
|
|
clock source latency -1.848 -1.848
|
|
propagated clock network latency
|
|
1.148 -0.701
|
|
SLICE_X84Y156 FDCE 0.000 -0.701 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/qprod_s4_reg[8]/C
|
|
SLICE_X84Y156 FDCE (Prop_fdce_C_Q) 0.164 -0.537 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/qprod_s4_reg[8]/Q
|
|
net (fo=1, routed) 0.199 -0.337 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/qprod_s4[8]
|
|
SLICE_X83Y156 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5[11]_i_5/I1
|
|
SLICE_X83Y156 LUT2 (Prop_lut2_I1_O) 0.045 -0.292 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5[11]_i_5/O
|
|
net (fo=1, routed) 0.000 -0.292 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5[11]_i_5_n_0
|
|
SLICE_X83Y156 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[11]_i_1/S[0]
|
|
SLICE_X83Y156 CARRY4 (Prop_carry4_S[0]_O[0])
|
|
0.070 -0.222 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[11]_i_1/O[0]
|
|
net (fo=1, routed) 0.000 -0.222 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s50[8]
|
|
SLICE_X83Y156 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[8]/D
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock mlkem_clk_clk_pll rise edge)
|
|
0.000 0.000 r
|
|
clock source latency -1.947 -1.947
|
|
propagated clock network latency
|
|
1.470 -0.477
|
|
clock pessimism 0.040 -0.437
|
|
SLICE_X83Y156 FDCE (Hold_fdce_C_D) 0.105 -0.332 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[8]
|
|
-------------------------------------------------------------------
|
|
required time 0.332
|
|
arrival time -0.222
|
|
-------------------------------------------------------------------
|
|
slack 0.110
|
|
|
|
Slack (MET) : 0.110ns (arrival time - required time)
|
|
Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/qprod_s4_reg[8]/C
|
|
(rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns})
|
|
Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[8]/D
|
|
(rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns})
|
|
Path Group: mlkem_clk_clk_pll
|
|
Path Type: Hold (Min at Fast Process Corner)
|
|
Requirement: 0.000ns (mlkem_clk_clk_pll rise@0.000ns - mlkem_clk_clk_pll rise@0.000ns)
|
|
Data Path Delay: 0.478ns (logic 0.279ns (58.317%) route 0.199ns (41.683%))
|
|
Logic Levels: 2 (CARRY4=1 LUT2=1)
|
|
Clock Path Skew: 0.264ns (DCD - SCD - CPR)
|
|
Destination Clock Delay (DCD): -0.477ns
|
|
Source Clock Delay (SCD): -0.701ns
|
|
Clock Pessimism Removal (CPR): -0.040ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock mlkem_clk_clk_pll rise edge)
|
|
0.000 0.000 r
|
|
clock source latency -1.848 -1.848
|
|
propagated clock network latency
|
|
1.148 -0.701
|
|
SLICE_X84Y156 FDCE 0.000 -0.701 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/qprod_s4_reg[8]/C
|
|
SLICE_X84Y156 FDCE (Prop_fdce_C_Q) 0.164 -0.537 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/qprod_s4_reg[8]/Q
|
|
net (fo=1, routed) 0.199 -0.337 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/qprod_s4[8]
|
|
SLICE_X83Y156 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5[11]_i_5/I1
|
|
SLICE_X83Y156 LUT2 (Prop_lut2_I1_O) 0.045 -0.292 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5[11]_i_5/O
|
|
net (fo=1, routed) 0.000 -0.292 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5[11]_i_5_n_0
|
|
SLICE_X83Y156 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[11]_i_1/S[0]
|
|
SLICE_X83Y156 CARRY4 (Prop_carry4_S[0]_O[0])
|
|
0.070 -0.222 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[11]_i_1/O[0]
|
|
net (fo=1, routed) 0.000 -0.222 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s50[8]
|
|
SLICE_X83Y156 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[8]/D
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock mlkem_clk_clk_pll rise edge)
|
|
0.000 0.000 r
|
|
clock source latency -1.947 -1.947
|
|
propagated clock network latency
|
|
1.470 -0.477
|
|
clock pessimism 0.040 -0.437
|
|
SLICE_X83Y156 FDCE (Hold_fdce_C_D) 0.105 -0.332 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[8]
|
|
-------------------------------------------------------------------
|
|
required time 0.332
|
|
arrival time -0.222
|
|
-------------------------------------------------------------------
|
|
slack 0.110
|
|
|
|
Slack (MET) : 0.110ns (arrival time - required time)
|
|
Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/qprod_s4_reg[8]/C
|
|
(rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns})
|
|
Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[8]/D
|
|
(rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns})
|
|
Path Group: mlkem_clk_clk_pll
|
|
Path Type: Hold (Min at Fast Process Corner)
|
|
Requirement: 0.000ns (mlkem_clk_clk_pll rise@0.000ns - mlkem_clk_clk_pll rise@0.000ns)
|
|
Data Path Delay: 0.478ns (logic 0.279ns (58.317%) route 0.199ns (41.683%))
|
|
Logic Levels: 2 (CARRY4=1 LUT2=1)
|
|
Clock Path Skew: 0.264ns (DCD - SCD - CPR)
|
|
Destination Clock Delay (DCD): -0.477ns
|
|
Source Clock Delay (SCD): -0.701ns
|
|
Clock Pessimism Removal (CPR): -0.040ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock mlkem_clk_clk_pll rise edge)
|
|
0.000 0.000 r
|
|
clock source latency -1.848 -1.848
|
|
propagated clock network latency
|
|
1.148 -0.701
|
|
SLICE_X84Y156 FDCE 0.000 -0.701 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/qprod_s4_reg[8]/C
|
|
SLICE_X84Y156 FDCE (Prop_fdce_C_Q) 0.164 -0.537 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/qprod_s4_reg[8]/Q
|
|
net (fo=1, routed) 0.199 -0.337 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/qprod_s4[8]
|
|
SLICE_X83Y156 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5[11]_i_5/I1
|
|
SLICE_X83Y156 LUT2 (Prop_lut2_I1_O) 0.045 -0.292 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5[11]_i_5/O
|
|
net (fo=1, routed) 0.000 -0.292 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5[11]_i_5_n_0
|
|
SLICE_X83Y156 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[11]_i_1/S[0]
|
|
SLICE_X83Y156 CARRY4 (Prop_carry4_S[0]_O[0])
|
|
0.070 -0.222 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[11]_i_1/O[0]
|
|
net (fo=1, routed) 0.000 -0.222 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s50[8]
|
|
SLICE_X83Y156 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[8]/D
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock mlkem_clk_clk_pll rise edge)
|
|
0.000 0.000 r
|
|
clock source latency -1.947 -1.947
|
|
propagated clock network latency
|
|
1.470 -0.477
|
|
clock pessimism 0.040 -0.437
|
|
SLICE_X83Y156 FDCE (Hold_fdce_C_D) 0.105 -0.332 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[8]
|
|
-------------------------------------------------------------------
|
|
required time 0.332
|
|
arrival time -0.222
|
|
-------------------------------------------------------------------
|
|
slack 0.110
|
|
|
|
Slack (MET) : 0.110ns (arrival time - required time)
|
|
Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/qprod_s4_reg[8]/C
|
|
(rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns})
|
|
Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[8]/D
|
|
(rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns})
|
|
Path Group: mlkem_clk_clk_pll
|
|
Path Type: Hold (Min at Fast Process Corner)
|
|
Requirement: 0.000ns (mlkem_clk_clk_pll rise@0.000ns - mlkem_clk_clk_pll rise@0.000ns)
|
|
Data Path Delay: 0.478ns (logic 0.279ns (58.317%) route 0.199ns (41.683%))
|
|
Logic Levels: 2 (CARRY4=1 LUT2=1)
|
|
Clock Path Skew: 0.264ns (DCD - SCD - CPR)
|
|
Destination Clock Delay (DCD): -0.477ns
|
|
Source Clock Delay (SCD): -0.701ns
|
|
Clock Pessimism Removal (CPR): -0.040ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock mlkem_clk_clk_pll rise edge)
|
|
0.000 0.000 r
|
|
clock source latency -1.848 -1.848
|
|
propagated clock network latency
|
|
1.148 -0.701
|
|
SLICE_X84Y156 FDCE 0.000 -0.701 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/qprod_s4_reg[8]/C
|
|
SLICE_X84Y156 FDCE (Prop_fdce_C_Q) 0.164 -0.537 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/qprod_s4_reg[8]/Q
|
|
net (fo=1, routed) 0.199 -0.337 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/qprod_s4[8]
|
|
SLICE_X83Y156 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5[11]_i_5/I1
|
|
SLICE_X83Y156 LUT2 (Prop_lut2_I1_O) 0.045 -0.292 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5[11]_i_5/O
|
|
net (fo=1, routed) 0.000 -0.292 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5[11]_i_5_n_0
|
|
SLICE_X83Y156 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[11]_i_1/S[0]
|
|
SLICE_X83Y156 CARRY4 (Prop_carry4_S[0]_O[0])
|
|
0.070 -0.222 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[11]_i_1/O[0]
|
|
net (fo=1, routed) 0.000 -0.222 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s50[8]
|
|
SLICE_X83Y156 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[8]/D
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock mlkem_clk_clk_pll rise edge)
|
|
0.000 0.000 r
|
|
clock source latency -1.947 -1.947
|
|
propagated clock network latency
|
|
1.470 -0.477
|
|
clock pessimism 0.040 -0.437
|
|
SLICE_X83Y156 FDCE (Hold_fdce_C_D) 0.105 -0.332 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[8]
|
|
-------------------------------------------------------------------
|
|
required time 0.332
|
|
arrival time -0.222
|
|
-------------------------------------------------------------------
|
|
slack 0.110
|
|
|
|
Slack (MET) : 0.110ns (arrival time - required time)
|
|
Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/qprod_s4_reg[8]/C
|
|
(rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns})
|
|
Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[8]/D
|
|
(rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns})
|
|
Path Group: mlkem_clk_clk_pll
|
|
Path Type: Hold (Min at Fast Process Corner)
|
|
Requirement: 0.000ns (mlkem_clk_clk_pll rise@0.000ns - mlkem_clk_clk_pll rise@0.000ns)
|
|
Data Path Delay: 0.478ns (logic 0.279ns (58.317%) route 0.199ns (41.683%))
|
|
Logic Levels: 2 (CARRY4=1 LUT2=1)
|
|
Clock Path Skew: 0.264ns (DCD - SCD - CPR)
|
|
Destination Clock Delay (DCD): -0.477ns
|
|
Source Clock Delay (SCD): -0.701ns
|
|
Clock Pessimism Removal (CPR): -0.040ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock mlkem_clk_clk_pll rise edge)
|
|
0.000 0.000 r
|
|
clock source latency -1.848 -1.848
|
|
propagated clock network latency
|
|
1.148 -0.701
|
|
SLICE_X84Y156 FDCE 0.000 -0.701 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/qprod_s4_reg[8]/C
|
|
SLICE_X84Y156 FDCE (Prop_fdce_C_Q) 0.164 -0.537 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/qprod_s4_reg[8]/Q
|
|
net (fo=1, routed) 0.199 -0.337 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/qprod_s4[8]
|
|
SLICE_X83Y156 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5[11]_i_5/I1
|
|
SLICE_X83Y156 LUT2 (Prop_lut2_I1_O) 0.045 -0.292 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5[11]_i_5/O
|
|
net (fo=1, routed) 0.000 -0.292 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5[11]_i_5_n_0
|
|
SLICE_X83Y156 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[11]_i_1/S[0]
|
|
SLICE_X83Y156 CARRY4 (Prop_carry4_S[0]_O[0])
|
|
0.070 -0.222 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[11]_i_1/O[0]
|
|
net (fo=1, routed) 0.000 -0.222 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s50[8]
|
|
SLICE_X83Y156 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[8]/D
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock mlkem_clk_clk_pll rise edge)
|
|
0.000 0.000 r
|
|
clock source latency -1.947 -1.947
|
|
propagated clock network latency
|
|
1.470 -0.477
|
|
clock pessimism 0.040 -0.437
|
|
SLICE_X83Y156 FDCE (Hold_fdce_C_D) 0.105 -0.332 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[8]
|
|
-------------------------------------------------------------------
|
|
required time 0.332
|
|
arrival time -0.222
|
|
-------------------------------------------------------------------
|
|
slack 0.110
|
|
|
|
Slack (MET) : 0.110ns (arrival time - required time)
|
|
Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/qprod_s4_reg[8]/C
|
|
(rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns})
|
|
Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[8]/D
|
|
(rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns})
|
|
Path Group: mlkem_clk_clk_pll
|
|
Path Type: Hold (Min at Fast Process Corner)
|
|
Requirement: 0.000ns (mlkem_clk_clk_pll rise@0.000ns - mlkem_clk_clk_pll rise@0.000ns)
|
|
Data Path Delay: 0.478ns (logic 0.279ns (58.317%) route 0.199ns (41.683%))
|
|
Logic Levels: 2 (CARRY4=1 LUT2=1)
|
|
Clock Path Skew: 0.264ns (DCD - SCD - CPR)
|
|
Destination Clock Delay (DCD): -0.477ns
|
|
Source Clock Delay (SCD): -0.701ns
|
|
Clock Pessimism Removal (CPR): -0.040ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock mlkem_clk_clk_pll rise edge)
|
|
0.000 0.000 r
|
|
clock source latency -1.848 -1.848
|
|
propagated clock network latency
|
|
1.148 -0.701
|
|
SLICE_X84Y156 FDCE 0.000 -0.701 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/qprod_s4_reg[8]/C
|
|
SLICE_X84Y156 FDCE (Prop_fdce_C_Q) 0.164 -0.537 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/qprod_s4_reg[8]/Q
|
|
net (fo=1, routed) 0.199 -0.337 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/qprod_s4[8]
|
|
SLICE_X83Y156 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5[11]_i_5/I1
|
|
SLICE_X83Y156 LUT2 (Prop_lut2_I1_O) 0.045 -0.292 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5[11]_i_5/O
|
|
net (fo=1, routed) 0.000 -0.292 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5[11]_i_5_n_0
|
|
SLICE_X83Y156 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[11]_i_1/S[0]
|
|
SLICE_X83Y156 CARRY4 (Prop_carry4_S[0]_O[0])
|
|
0.070 -0.222 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[11]_i_1/O[0]
|
|
net (fo=1, routed) 0.000 -0.222 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s50[8]
|
|
SLICE_X83Y156 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[8]/D
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock mlkem_clk_clk_pll rise edge)
|
|
0.000 0.000 r
|
|
clock source latency -1.947 -1.947
|
|
propagated clock network latency
|
|
1.470 -0.477
|
|
clock pessimism 0.040 -0.437
|
|
SLICE_X83Y156 FDCE (Hold_fdce_C_D) 0.105 -0.332 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[8]
|
|
-------------------------------------------------------------------
|
|
required time 0.332
|
|
arrival time -0.222
|
|
-------------------------------------------------------------------
|
|
slack 0.110
|
|
|
|
Slack (MET) : 0.117ns (arrival time - required time)
|
|
Source: u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdRouteFork_translated_fifo/fifo/logic_ptr_push_reg[0]/C
|
|
(rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Destination: axi4WriteOnlyArbiter_4/cmdRouteFork_translated_fifo/fifo/logic_ram_reg_0_3_0_0/DP/WADR0
|
|
(rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Path Group: sys_clk
|
|
Path Type: Hold (Min at Fast Process Corner)
|
|
Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns)
|
|
Data Path Delay: 0.463ns (logic 0.164ns (35.436%) route 0.299ns (64.564%))
|
|
Logic Levels: 0
|
|
Clock Path Skew: 0.036ns (DCD - SCD - CPR)
|
|
Destination Clock Delay (DCD): -0.322ns
|
|
Source Clock Delay (SCD): -0.550ns
|
|
Clock Pessimism Removal (CPR): 0.192ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock sys_clk rise edge) 0.000 0.000 r
|
|
clock source latency -1.848 -1.848
|
|
propagated clock network latency
|
|
1.298 -0.550
|
|
SLICE_X2Y75 FDCE 0.000 -0.550 r u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdRouteFork_translated_fifo/fifo/logic_ptr_push_reg[0]/C
|
|
SLICE_X2Y75 FDCE (Prop_fdce_C_Q) 0.164 -0.386 r u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdRouteFork_translated_fifo/fifo/logic_ptr_push_reg[0]/Q
|
|
net (fo=8, routed) 0.299 -0.088 axi4WriteOnlyArbiter_4/cmdRouteFork_translated_fifo/fifo/logic_ram_reg_0_3_0_0/A0
|
|
SLICE_X2Y74 RAMD32 r axi4WriteOnlyArbiter_4/cmdRouteFork_translated_fifo/fifo/logic_ram_reg_0_3_0_0/DP/WADR0
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock sys_clk rise edge) 0.000 0.000 r
|
|
clock source latency -1.947 -1.947
|
|
propagated clock network latency
|
|
1.625 -0.322
|
|
clock pessimism -0.192 -0.514
|
|
SLICE_X2Y74 RAMD32 (Hold_ramd32_CLK_WADR0)
|
|
0.310 -0.204 axi4WriteOnlyArbiter_4/cmdRouteFork_translated_fifo/fifo/logic_ram_reg_0_3_0_0/DP
|
|
-------------------------------------------------------------------
|
|
required time 0.204
|
|
arrival time -0.088
|
|
-------------------------------------------------------------------
|
|
slack 0.117
|
|
|
|
Slack (MET) : 0.117ns (arrival time - required time)
|
|
Source: u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdRouteFork_translated_fifo/fifo/logic_ptr_push_reg[0]/C
|
|
(rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Destination: axi4WriteOnlyArbiter_4/cmdRouteFork_translated_fifo/fifo/logic_ram_reg_0_3_0_0/DP/WADR0
|
|
(rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Path Group: sys_clk
|
|
Path Type: Hold (Min at Fast Process Corner)
|
|
Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns)
|
|
Data Path Delay: 0.463ns (logic 0.164ns (35.436%) route 0.299ns (64.564%))
|
|
Logic Levels: 0
|
|
Clock Path Skew: 0.036ns (DCD - SCD - CPR)
|
|
Destination Clock Delay (DCD): -0.322ns
|
|
Source Clock Delay (SCD): -0.550ns
|
|
Clock Pessimism Removal (CPR): 0.192ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock sys_clk rise edge) 0.000 0.000 r
|
|
clock source latency -1.848 -1.848
|
|
propagated clock network latency
|
|
1.298 -0.550
|
|
SLICE_X2Y75 FDCE 0.000 -0.550 r u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdRouteFork_translated_fifo/fifo/logic_ptr_push_reg[0]/C
|
|
SLICE_X2Y75 FDCE (Prop_fdce_C_Q) 0.164 -0.386 f u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdRouteFork_translated_fifo/fifo/logic_ptr_push_reg[0]/Q
|
|
net (fo=8, routed) 0.299 -0.088 axi4WriteOnlyArbiter_4/cmdRouteFork_translated_fifo/fifo/logic_ram_reg_0_3_0_0/A0
|
|
SLICE_X2Y74 RAMD32 f axi4WriteOnlyArbiter_4/cmdRouteFork_translated_fifo/fifo/logic_ram_reg_0_3_0_0/DP/WADR0
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock sys_clk rise edge) 0.000 0.000 r
|
|
clock source latency -1.947 -1.947
|
|
propagated clock network latency
|
|
1.625 -0.322
|
|
clock pessimism -0.192 -0.514
|
|
SLICE_X2Y74 RAMD32 (Hold_ramd32_CLK_WADR0)
|
|
0.310 -0.204 axi4WriteOnlyArbiter_4/cmdRouteFork_translated_fifo/fifo/logic_ram_reg_0_3_0_0/DP
|
|
-------------------------------------------------------------------
|
|
required time 0.204
|
|
arrival time -0.088
|
|
-------------------------------------------------------------------
|
|
slack 0.117
|
|
|
|
Slack (MET) : 0.117ns (arrival time - required time)
|
|
Source: u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdRouteFork_translated_fifo/fifo/logic_ptr_push_reg[0]/C
|
|
(rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Destination: axi4WriteOnlyArbiter_4/cmdRouteFork_translated_fifo/fifo/logic_ram_reg_0_3_0_0/SP/WADR0
|
|
(rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Path Group: sys_clk
|
|
Path Type: Hold (Min at Fast Process Corner)
|
|
Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns)
|
|
Data Path Delay: 0.463ns (logic 0.164ns (35.436%) route 0.299ns (64.564%))
|
|
Logic Levels: 0
|
|
Clock Path Skew: 0.036ns (DCD - SCD - CPR)
|
|
Destination Clock Delay (DCD): -0.322ns
|
|
Source Clock Delay (SCD): -0.550ns
|
|
Clock Pessimism Removal (CPR): 0.192ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock sys_clk rise edge) 0.000 0.000 r
|
|
clock source latency -1.848 -1.848
|
|
propagated clock network latency
|
|
1.298 -0.550
|
|
SLICE_X2Y75 FDCE 0.000 -0.550 r u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdRouteFork_translated_fifo/fifo/logic_ptr_push_reg[0]/C
|
|
SLICE_X2Y75 FDCE (Prop_fdce_C_Q) 0.164 -0.386 r u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdRouteFork_translated_fifo/fifo/logic_ptr_push_reg[0]/Q
|
|
net (fo=8, routed) 0.299 -0.088 axi4WriteOnlyArbiter_4/cmdRouteFork_translated_fifo/fifo/logic_ram_reg_0_3_0_0/A0
|
|
SLICE_X2Y74 RAMD32 r axi4WriteOnlyArbiter_4/cmdRouteFork_translated_fifo/fifo/logic_ram_reg_0_3_0_0/SP/WADR0
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock sys_clk rise edge) 0.000 0.000 r
|
|
clock source latency -1.947 -1.947
|
|
propagated clock network latency
|
|
1.625 -0.322
|
|
clock pessimism -0.192 -0.514
|
|
SLICE_X2Y74 RAMD32 (Hold_ramd32_CLK_WADR0)
|
|
0.310 -0.204 axi4WriteOnlyArbiter_4/cmdRouteFork_translated_fifo/fifo/logic_ram_reg_0_3_0_0/SP
|
|
-------------------------------------------------------------------
|
|
required time 0.204
|
|
arrival time -0.088
|
|
-------------------------------------------------------------------
|
|
slack 0.117
|
|
|
|
Slack (MET) : 0.117ns (arrival time - required time)
|
|
Source: u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdRouteFork_translated_fifo/fifo/logic_ptr_push_reg[0]/C
|
|
(rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Destination: axi4WriteOnlyArbiter_4/cmdRouteFork_translated_fifo/fifo/logic_ram_reg_0_3_0_0/SP/WADR0
|
|
(rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Path Group: sys_clk
|
|
Path Type: Hold (Min at Fast Process Corner)
|
|
Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns)
|
|
Data Path Delay: 0.463ns (logic 0.164ns (35.436%) route 0.299ns (64.564%))
|
|
Logic Levels: 0
|
|
Clock Path Skew: 0.036ns (DCD - SCD - CPR)
|
|
Destination Clock Delay (DCD): -0.322ns
|
|
Source Clock Delay (SCD): -0.550ns
|
|
Clock Pessimism Removal (CPR): 0.192ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock sys_clk rise edge) 0.000 0.000 r
|
|
clock source latency -1.848 -1.848
|
|
propagated clock network latency
|
|
1.298 -0.550
|
|
SLICE_X2Y75 FDCE 0.000 -0.550 r u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdRouteFork_translated_fifo/fifo/logic_ptr_push_reg[0]/C
|
|
SLICE_X2Y75 FDCE (Prop_fdce_C_Q) 0.164 -0.386 f u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdRouteFork_translated_fifo/fifo/logic_ptr_push_reg[0]/Q
|
|
net (fo=8, routed) 0.299 -0.088 axi4WriteOnlyArbiter_4/cmdRouteFork_translated_fifo/fifo/logic_ram_reg_0_3_0_0/A0
|
|
SLICE_X2Y74 RAMD32 f axi4WriteOnlyArbiter_4/cmdRouteFork_translated_fifo/fifo/logic_ram_reg_0_3_0_0/SP/WADR0
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock sys_clk rise edge) 0.000 0.000 r
|
|
clock source latency -1.947 -1.947
|
|
propagated clock network latency
|
|
1.625 -0.322
|
|
clock pessimism -0.192 -0.514
|
|
SLICE_X2Y74 RAMD32 (Hold_ramd32_CLK_WADR0)
|
|
0.310 -0.204 axi4WriteOnlyArbiter_4/cmdRouteFork_translated_fifo/fifo/logic_ram_reg_0_3_0_0/SP
|
|
-------------------------------------------------------------------
|
|
required time 0.204
|
|
arrival time -0.088
|
|
-------------------------------------------------------------------
|
|
slack 0.117
|
|
|
|
Slack (MET) : 0.117ns (arrival time - required time)
|
|
Source: u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdRouteFork_translated_fifo/fifo/logic_ptr_push_reg[1]/C
|
|
(rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Destination: axi4WriteOnlyArbiter_4/cmdRouteFork_translated_fifo/fifo/logic_ram_reg_0_3_0_0/DP/WADR1
|
|
(rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Path Group: sys_clk
|
|
Path Type: Hold (Min at Fast Process Corner)
|
|
Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns)
|
|
Data Path Delay: 0.462ns (logic 0.164ns (35.508%) route 0.298ns (64.492%))
|
|
Logic Levels: 0
|
|
Clock Path Skew: 0.036ns (DCD - SCD - CPR)
|
|
Destination Clock Delay (DCD): -0.322ns
|
|
Source Clock Delay (SCD): -0.550ns
|
|
Clock Pessimism Removal (CPR): 0.192ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock sys_clk rise edge) 0.000 0.000 r
|
|
clock source latency -1.848 -1.848
|
|
propagated clock network latency
|
|
1.298 -0.550
|
|
SLICE_X2Y75 FDCE 0.000 -0.550 r u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdRouteFork_translated_fifo/fifo/logic_ptr_push_reg[1]/C
|
|
SLICE_X2Y75 FDCE (Prop_fdce_C_Q) 0.164 -0.386 r u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdRouteFork_translated_fifo/fifo/logic_ptr_push_reg[1]/Q
|
|
net (fo=7, routed) 0.298 -0.089 axi4WriteOnlyArbiter_4/cmdRouteFork_translated_fifo/fifo/logic_ram_reg_0_3_0_0/A1
|
|
SLICE_X2Y74 RAMD32 r axi4WriteOnlyArbiter_4/cmdRouteFork_translated_fifo/fifo/logic_ram_reg_0_3_0_0/DP/WADR1
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock sys_clk rise edge) 0.000 0.000 r
|
|
clock source latency -1.947 -1.947
|
|
propagated clock network latency
|
|
1.625 -0.322
|
|
clock pessimism -0.192 -0.514
|
|
SLICE_X2Y74 RAMD32 (Hold_ramd32_CLK_WADR1)
|
|
0.309 -0.205 axi4WriteOnlyArbiter_4/cmdRouteFork_translated_fifo/fifo/logic_ram_reg_0_3_0_0/DP
|
|
-------------------------------------------------------------------
|
|
required time 0.205
|
|
arrival time -0.089
|
|
-------------------------------------------------------------------
|
|
slack 0.117
|
|
|
|
Slack (MET) : 0.117ns (arrival time - required time)
|
|
Source: u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdRouteFork_translated_fifo/fifo/logic_ptr_push_reg[1]/C
|
|
(rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Destination: axi4WriteOnlyArbiter_4/cmdRouteFork_translated_fifo/fifo/logic_ram_reg_0_3_0_0/DP/WADR1
|
|
(rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Path Group: sys_clk
|
|
Path Type: Hold (Min at Fast Process Corner)
|
|
Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns)
|
|
Data Path Delay: 0.462ns (logic 0.164ns (35.508%) route 0.298ns (64.492%))
|
|
Logic Levels: 0
|
|
Clock Path Skew: 0.036ns (DCD - SCD - CPR)
|
|
Destination Clock Delay (DCD): -0.322ns
|
|
Source Clock Delay (SCD): -0.550ns
|
|
Clock Pessimism Removal (CPR): 0.192ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock sys_clk rise edge) 0.000 0.000 r
|
|
clock source latency -1.848 -1.848
|
|
propagated clock network latency
|
|
1.298 -0.550
|
|
SLICE_X2Y75 FDCE 0.000 -0.550 r u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdRouteFork_translated_fifo/fifo/logic_ptr_push_reg[1]/C
|
|
SLICE_X2Y75 FDCE (Prop_fdce_C_Q) 0.164 -0.386 f u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdRouteFork_translated_fifo/fifo/logic_ptr_push_reg[1]/Q
|
|
net (fo=7, routed) 0.298 -0.089 axi4WriteOnlyArbiter_4/cmdRouteFork_translated_fifo/fifo/logic_ram_reg_0_3_0_0/A1
|
|
SLICE_X2Y74 RAMD32 f axi4WriteOnlyArbiter_4/cmdRouteFork_translated_fifo/fifo/logic_ram_reg_0_3_0_0/DP/WADR1
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock sys_clk rise edge) 0.000 0.000 r
|
|
clock source latency -1.947 -1.947
|
|
propagated clock network latency
|
|
1.625 -0.322
|
|
clock pessimism -0.192 -0.514
|
|
SLICE_X2Y74 RAMD32 (Hold_ramd32_CLK_WADR1)
|
|
0.309 -0.205 axi4WriteOnlyArbiter_4/cmdRouteFork_translated_fifo/fifo/logic_ram_reg_0_3_0_0/DP
|
|
-------------------------------------------------------------------
|
|
required time 0.205
|
|
arrival time -0.089
|
|
-------------------------------------------------------------------
|
|
slack 0.117
|
|
|
|
Slack (MET) : 0.117ns (arrival time - required time)
|
|
Source: u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdRouteFork_translated_fifo/fifo/logic_ptr_push_reg[1]/C
|
|
(rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Destination: axi4WriteOnlyArbiter_4/cmdRouteFork_translated_fifo/fifo/logic_ram_reg_0_3_0_0/SP/WADR1
|
|
(rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Path Group: sys_clk
|
|
Path Type: Hold (Min at Fast Process Corner)
|
|
Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns)
|
|
Data Path Delay: 0.462ns (logic 0.164ns (35.508%) route 0.298ns (64.492%))
|
|
Logic Levels: 0
|
|
Clock Path Skew: 0.036ns (DCD - SCD - CPR)
|
|
Destination Clock Delay (DCD): -0.322ns
|
|
Source Clock Delay (SCD): -0.550ns
|
|
Clock Pessimism Removal (CPR): 0.192ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock sys_clk rise edge) 0.000 0.000 r
|
|
clock source latency -1.848 -1.848
|
|
propagated clock network latency
|
|
1.298 -0.550
|
|
SLICE_X2Y75 FDCE 0.000 -0.550 r u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdRouteFork_translated_fifo/fifo/logic_ptr_push_reg[1]/C
|
|
SLICE_X2Y75 FDCE (Prop_fdce_C_Q) 0.164 -0.386 r u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdRouteFork_translated_fifo/fifo/logic_ptr_push_reg[1]/Q
|
|
net (fo=7, routed) 0.298 -0.089 axi4WriteOnlyArbiter_4/cmdRouteFork_translated_fifo/fifo/logic_ram_reg_0_3_0_0/A1
|
|
SLICE_X2Y74 RAMD32 r axi4WriteOnlyArbiter_4/cmdRouteFork_translated_fifo/fifo/logic_ram_reg_0_3_0_0/SP/WADR1
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock sys_clk rise edge) 0.000 0.000 r
|
|
clock source latency -1.947 -1.947
|
|
propagated clock network latency
|
|
1.625 -0.322
|
|
clock pessimism -0.192 -0.514
|
|
SLICE_X2Y74 RAMD32 (Hold_ramd32_CLK_WADR1)
|
|
0.309 -0.205 axi4WriteOnlyArbiter_4/cmdRouteFork_translated_fifo/fifo/logic_ram_reg_0_3_0_0/SP
|
|
-------------------------------------------------------------------
|
|
required time 0.205
|
|
arrival time -0.089
|
|
-------------------------------------------------------------------
|
|
slack 0.117
|
|
|
|
Slack (MET) : 0.117ns (arrival time - required time)
|
|
Source: u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdRouteFork_translated_fifo/fifo/logic_ptr_push_reg[1]/C
|
|
(rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Destination: axi4WriteOnlyArbiter_4/cmdRouteFork_translated_fifo/fifo/logic_ram_reg_0_3_0_0/SP/WADR1
|
|
(rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Path Group: sys_clk
|
|
Path Type: Hold (Min at Fast Process Corner)
|
|
Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns)
|
|
Data Path Delay: 0.462ns (logic 0.164ns (35.508%) route 0.298ns (64.492%))
|
|
Logic Levels: 0
|
|
Clock Path Skew: 0.036ns (DCD - SCD - CPR)
|
|
Destination Clock Delay (DCD): -0.322ns
|
|
Source Clock Delay (SCD): -0.550ns
|
|
Clock Pessimism Removal (CPR): 0.192ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock sys_clk rise edge) 0.000 0.000 r
|
|
clock source latency -1.848 -1.848
|
|
propagated clock network latency
|
|
1.298 -0.550
|
|
SLICE_X2Y75 FDCE 0.000 -0.550 r u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdRouteFork_translated_fifo/fifo/logic_ptr_push_reg[1]/C
|
|
SLICE_X2Y75 FDCE (Prop_fdce_C_Q) 0.164 -0.386 f u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdRouteFork_translated_fifo/fifo/logic_ptr_push_reg[1]/Q
|
|
net (fo=7, routed) 0.298 -0.089 axi4WriteOnlyArbiter_4/cmdRouteFork_translated_fifo/fifo/logic_ram_reg_0_3_0_0/A1
|
|
SLICE_X2Y74 RAMD32 f axi4WriteOnlyArbiter_4/cmdRouteFork_translated_fifo/fifo/logic_ram_reg_0_3_0_0/SP/WADR1
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock sys_clk rise edge) 0.000 0.000 r
|
|
clock source latency -1.947 -1.947
|
|
propagated clock network latency
|
|
1.625 -0.322
|
|
clock pessimism -0.192 -0.514
|
|
SLICE_X2Y74 RAMD32 (Hold_ramd32_CLK_WADR1)
|
|
0.309 -0.205 axi4WriteOnlyArbiter_4/cmdRouteFork_translated_fifo/fifo/logic_ram_reg_0_3_0_0/SP
|
|
-------------------------------------------------------------------
|
|
required time 0.205
|
|
arrival time -0.089
|
|
-------------------------------------------------------------------
|
|
slack 0.117
|
|
|
|
Slack (MET) : 0.117ns (arrival time - required time)
|
|
Source: u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/top_reg[0]/C
|
|
(rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Destination: u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/tfifo/ram_reg_0_15_0_5/RAMA/WADR0
|
|
(rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Path Group: sys_clk
|
|
Path Type: Hold (Min at Fast Process Corner)
|
|
Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns)
|
|
Data Path Delay: 0.444ns (logic 0.164ns (36.916%) route 0.280ns (63.084%))
|
|
Logic Levels: 0
|
|
Clock Path Skew: 0.017ns (DCD - SCD - CPR)
|
|
Destination Clock Delay (DCD): -0.310ns
|
|
Source Clock Delay (SCD): -0.543ns
|
|
Clock Pessimism Removal (CPR): 0.216ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock sys_clk rise edge) 0.000 0.000 r
|
|
clock source latency -1.848 -1.848
|
|
propagated clock network latency
|
|
1.305 -0.543
|
|
SLICE_X6Y62 FDRE 0.000 -0.543 r u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/top_reg[0]/C
|
|
SLICE_X6Y62 FDRE (Prop_fdre_C_Q) 0.164 -0.379 r u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/top_reg[0]/Q
|
|
net (fo=20, routed) 0.280 -0.099 u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/tfifo/ram_reg_0_15_0_5/ADDRD0
|
|
SLICE_X6Y61 RAMD32 r u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/tfifo/ram_reg_0_15_0_5/RAMA/WADR0
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock sys_clk rise edge) 0.000 0.000 r
|
|
clock source latency -1.947 -1.947
|
|
propagated clock network latency
|
|
1.637 -0.310
|
|
clock pessimism -0.216 -0.526
|
|
SLICE_X6Y61 RAMD32 (Hold_ramd32_CLK_WADR0)
|
|
0.310 -0.216 u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/tfifo/ram_reg_0_15_0_5/RAMA
|
|
-------------------------------------------------------------------
|
|
required time 0.216
|
|
arrival time -0.099
|
|
-------------------------------------------------------------------
|
|
slack 0.117
|
|
|
|
Slack (MET) : 0.117ns (arrival time - required time)
|
|
Source: u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/top_reg[0]/C
|
|
(rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Destination: u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/tfifo/ram_reg_0_15_0_5/RAMA/WADR0
|
|
(rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Path Group: sys_clk
|
|
Path Type: Hold (Min at Fast Process Corner)
|
|
Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns)
|
|
Data Path Delay: 0.444ns (logic 0.164ns (36.916%) route 0.280ns (63.084%))
|
|
Logic Levels: 0
|
|
Clock Path Skew: 0.017ns (DCD - SCD - CPR)
|
|
Destination Clock Delay (DCD): -0.310ns
|
|
Source Clock Delay (SCD): -0.543ns
|
|
Clock Pessimism Removal (CPR): 0.216ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock sys_clk rise edge) 0.000 0.000 r
|
|
clock source latency -1.848 -1.848
|
|
propagated clock network latency
|
|
1.305 -0.543
|
|
SLICE_X6Y62 FDRE 0.000 -0.543 r u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/top_reg[0]/C
|
|
SLICE_X6Y62 FDRE (Prop_fdre_C_Q) 0.164 -0.379 f u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/top_reg[0]/Q
|
|
net (fo=20, routed) 0.280 -0.099 u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/tfifo/ram_reg_0_15_0_5/ADDRD0
|
|
SLICE_X6Y61 RAMD32 f u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/tfifo/ram_reg_0_15_0_5/RAMA/WADR0
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock sys_clk rise edge) 0.000 0.000 r
|
|
clock source latency -1.947 -1.947
|
|
propagated clock network latency
|
|
1.637 -0.310
|
|
clock pessimism -0.216 -0.526
|
|
SLICE_X6Y61 RAMD32 (Hold_ramd32_CLK_WADR0)
|
|
0.310 -0.216 u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/tfifo/ram_reg_0_15_0_5/RAMA
|
|
-------------------------------------------------------------------
|
|
required time 0.216
|
|
arrival time -0.099
|
|
-------------------------------------------------------------------
|
|
slack 0.117
|
|
|
|
Slack (MET) : 0.117ns (arrival time - required time)
|
|
Source: u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/top_reg[0]/C
|
|
(rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Destination: u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/tfifo/ram_reg_0_15_0_5/RAMA_D1/WADR0
|
|
(rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Path Group: sys_clk
|
|
Path Type: Hold (Min at Fast Process Corner)
|
|
Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns)
|
|
Data Path Delay: 0.444ns (logic 0.164ns (36.916%) route 0.280ns (63.084%))
|
|
Logic Levels: 0
|
|
Clock Path Skew: 0.017ns (DCD - SCD - CPR)
|
|
Destination Clock Delay (DCD): -0.310ns
|
|
Source Clock Delay (SCD): -0.543ns
|
|
Clock Pessimism Removal (CPR): 0.216ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock sys_clk rise edge) 0.000 0.000 r
|
|
clock source latency -1.848 -1.848
|
|
propagated clock network latency
|
|
1.305 -0.543
|
|
SLICE_X6Y62 FDRE 0.000 -0.543 r u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/top_reg[0]/C
|
|
SLICE_X6Y62 FDRE (Prop_fdre_C_Q) 0.164 -0.379 r u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/top_reg[0]/Q
|
|
net (fo=20, routed) 0.280 -0.099 u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/tfifo/ram_reg_0_15_0_5/ADDRD0
|
|
SLICE_X6Y61 RAMD32 r u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/tfifo/ram_reg_0_15_0_5/RAMA_D1/WADR0
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock sys_clk rise edge) 0.000 0.000 r
|
|
clock source latency -1.947 -1.947
|
|
propagated clock network latency
|
|
1.637 -0.310
|
|
clock pessimism -0.216 -0.526
|
|
SLICE_X6Y61 RAMD32 (Hold_ramd32_CLK_WADR0)
|
|
0.310 -0.216 u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/tfifo/ram_reg_0_15_0_5/RAMA_D1
|
|
-------------------------------------------------------------------
|
|
required time 0.216
|
|
arrival time -0.099
|
|
-------------------------------------------------------------------
|
|
slack 0.117
|
|
|
|
Slack (MET) : 0.117ns (arrival time - required time)
|
|
Source: u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/top_reg[0]/C
|
|
(rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Destination: u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/tfifo/ram_reg_0_15_0_5/RAMA_D1/WADR0
|
|
(rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Path Group: sys_clk
|
|
Path Type: Hold (Min at Fast Process Corner)
|
|
Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns)
|
|
Data Path Delay: 0.444ns (logic 0.164ns (36.916%) route 0.280ns (63.084%))
|
|
Logic Levels: 0
|
|
Clock Path Skew: 0.017ns (DCD - SCD - CPR)
|
|
Destination Clock Delay (DCD): -0.310ns
|
|
Source Clock Delay (SCD): -0.543ns
|
|
Clock Pessimism Removal (CPR): 0.216ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock sys_clk rise edge) 0.000 0.000 r
|
|
clock source latency -1.848 -1.848
|
|
propagated clock network latency
|
|
1.305 -0.543
|
|
SLICE_X6Y62 FDRE 0.000 -0.543 r u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/top_reg[0]/C
|
|
SLICE_X6Y62 FDRE (Prop_fdre_C_Q) 0.164 -0.379 f u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/top_reg[0]/Q
|
|
net (fo=20, routed) 0.280 -0.099 u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/tfifo/ram_reg_0_15_0_5/ADDRD0
|
|
SLICE_X6Y61 RAMD32 f u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/tfifo/ram_reg_0_15_0_5/RAMA_D1/WADR0
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock sys_clk rise edge) 0.000 0.000 r
|
|
clock source latency -1.947 -1.947
|
|
propagated clock network latency
|
|
1.637 -0.310
|
|
clock pessimism -0.216 -0.526
|
|
SLICE_X6Y61 RAMD32 (Hold_ramd32_CLK_WADR0)
|
|
0.310 -0.216 u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/tfifo/ram_reg_0_15_0_5/RAMA_D1
|
|
-------------------------------------------------------------------
|
|
required time 0.216
|
|
arrival time -0.099
|
|
-------------------------------------------------------------------
|
|
slack 0.117
|
|
|
|
Slack (MET) : 0.117ns (arrival time - required time)
|
|
Source: u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/top_reg[0]/C
|
|
(rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Destination: u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/tfifo/ram_reg_0_15_0_5/RAMB/WADR0
|
|
(rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Path Group: sys_clk
|
|
Path Type: Hold (Min at Fast Process Corner)
|
|
Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns)
|
|
Data Path Delay: 0.444ns (logic 0.164ns (36.916%) route 0.280ns (63.084%))
|
|
Logic Levels: 0
|
|
Clock Path Skew: 0.017ns (DCD - SCD - CPR)
|
|
Destination Clock Delay (DCD): -0.310ns
|
|
Source Clock Delay (SCD): -0.543ns
|
|
Clock Pessimism Removal (CPR): 0.216ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock sys_clk rise edge) 0.000 0.000 r
|
|
clock source latency -1.848 -1.848
|
|
propagated clock network latency
|
|
1.305 -0.543
|
|
SLICE_X6Y62 FDRE 0.000 -0.543 r u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/top_reg[0]/C
|
|
SLICE_X6Y62 FDRE (Prop_fdre_C_Q) 0.164 -0.379 r u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/top_reg[0]/Q
|
|
net (fo=20, routed) 0.280 -0.099 u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/tfifo/ram_reg_0_15_0_5/ADDRD0
|
|
SLICE_X6Y61 RAMD32 r u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/tfifo/ram_reg_0_15_0_5/RAMB/WADR0
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock sys_clk rise edge) 0.000 0.000 r
|
|
clock source latency -1.947 -1.947
|
|
propagated clock network latency
|
|
1.637 -0.310
|
|
clock pessimism -0.216 -0.526
|
|
SLICE_X6Y61 RAMD32 (Hold_ramd32_CLK_WADR0)
|
|
0.310 -0.216 u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/tfifo/ram_reg_0_15_0_5/RAMB
|
|
-------------------------------------------------------------------
|
|
required time 0.216
|
|
arrival time -0.099
|
|
-------------------------------------------------------------------
|
|
slack 0.117
|
|
|
|
Slack (MET) : 0.117ns (arrival time - required time)
|
|
Source: u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/top_reg[0]/C
|
|
(rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Destination: u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/tfifo/ram_reg_0_15_0_5/RAMB/WADR0
|
|
(rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Path Group: sys_clk
|
|
Path Type: Hold (Min at Fast Process Corner)
|
|
Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns)
|
|
Data Path Delay: 0.444ns (logic 0.164ns (36.916%) route 0.280ns (63.084%))
|
|
Logic Levels: 0
|
|
Clock Path Skew: 0.017ns (DCD - SCD - CPR)
|
|
Destination Clock Delay (DCD): -0.310ns
|
|
Source Clock Delay (SCD): -0.543ns
|
|
Clock Pessimism Removal (CPR): 0.216ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock sys_clk rise edge) 0.000 0.000 r
|
|
clock source latency -1.848 -1.848
|
|
propagated clock network latency
|
|
1.305 -0.543
|
|
SLICE_X6Y62 FDRE 0.000 -0.543 r u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/top_reg[0]/C
|
|
SLICE_X6Y62 FDRE (Prop_fdre_C_Q) 0.164 -0.379 f u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/top_reg[0]/Q
|
|
net (fo=20, routed) 0.280 -0.099 u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/tfifo/ram_reg_0_15_0_5/ADDRD0
|
|
SLICE_X6Y61 RAMD32 f u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/tfifo/ram_reg_0_15_0_5/RAMB/WADR0
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock sys_clk rise edge) 0.000 0.000 r
|
|
clock source latency -1.947 -1.947
|
|
propagated clock network latency
|
|
1.637 -0.310
|
|
clock pessimism -0.216 -0.526
|
|
SLICE_X6Y61 RAMD32 (Hold_ramd32_CLK_WADR0)
|
|
0.310 -0.216 u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/tfifo/ram_reg_0_15_0_5/RAMB
|
|
-------------------------------------------------------------------
|
|
required time 0.216
|
|
arrival time -0.099
|
|
-------------------------------------------------------------------
|
|
slack 0.117
|
|
|
|
Slack (MET) : 0.117ns (arrival time - required time)
|
|
Source: u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/top_reg[0]/C
|
|
(rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Destination: u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/tfifo/ram_reg_0_15_0_5/RAMB_D1/WADR0
|
|
(rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Path Group: sys_clk
|
|
Path Type: Hold (Min at Fast Process Corner)
|
|
Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns)
|
|
Data Path Delay: 0.444ns (logic 0.164ns (36.916%) route 0.280ns (63.084%))
|
|
Logic Levels: 0
|
|
Clock Path Skew: 0.017ns (DCD - SCD - CPR)
|
|
Destination Clock Delay (DCD): -0.310ns
|
|
Source Clock Delay (SCD): -0.543ns
|
|
Clock Pessimism Removal (CPR): 0.216ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock sys_clk rise edge) 0.000 0.000 r
|
|
clock source latency -1.848 -1.848
|
|
propagated clock network latency
|
|
1.305 -0.543
|
|
SLICE_X6Y62 FDRE 0.000 -0.543 r u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/top_reg[0]/C
|
|
SLICE_X6Y62 FDRE (Prop_fdre_C_Q) 0.164 -0.379 r u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/top_reg[0]/Q
|
|
net (fo=20, routed) 0.280 -0.099 u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/tfifo/ram_reg_0_15_0_5/ADDRD0
|
|
SLICE_X6Y61 RAMD32 r u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/tfifo/ram_reg_0_15_0_5/RAMB_D1/WADR0
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock sys_clk rise edge) 0.000 0.000 r
|
|
clock source latency -1.947 -1.947
|
|
propagated clock network latency
|
|
1.637 -0.310
|
|
clock pessimism -0.216 -0.526
|
|
SLICE_X6Y61 RAMD32 (Hold_ramd32_CLK_WADR0)
|
|
0.310 -0.216 u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/tfifo/ram_reg_0_15_0_5/RAMB_D1
|
|
-------------------------------------------------------------------
|
|
required time 0.216
|
|
arrival time -0.099
|
|
-------------------------------------------------------------------
|
|
slack 0.117
|
|
|
|
Slack (MET) : 0.117ns (arrival time - required time)
|
|
Source: u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/top_reg[0]/C
|
|
(rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Destination: u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/tfifo/ram_reg_0_15_0_5/RAMB_D1/WADR0
|
|
(rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Path Group: sys_clk
|
|
Path Type: Hold (Min at Fast Process Corner)
|
|
Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns)
|
|
Data Path Delay: 0.444ns (logic 0.164ns (36.916%) route 0.280ns (63.084%))
|
|
Logic Levels: 0
|
|
Clock Path Skew: 0.017ns (DCD - SCD - CPR)
|
|
Destination Clock Delay (DCD): -0.310ns
|
|
Source Clock Delay (SCD): -0.543ns
|
|
Clock Pessimism Removal (CPR): 0.216ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock sys_clk rise edge) 0.000 0.000 r
|
|
clock source latency -1.848 -1.848
|
|
propagated clock network latency
|
|
1.305 -0.543
|
|
SLICE_X6Y62 FDRE 0.000 -0.543 r u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/top_reg[0]/C
|
|
SLICE_X6Y62 FDRE (Prop_fdre_C_Q) 0.164 -0.379 f u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/top_reg[0]/Q
|
|
net (fo=20, routed) 0.280 -0.099 u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/tfifo/ram_reg_0_15_0_5/ADDRD0
|
|
SLICE_X6Y61 RAMD32 f u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/tfifo/ram_reg_0_15_0_5/RAMB_D1/WADR0
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock sys_clk rise edge) 0.000 0.000 r
|
|
clock source latency -1.947 -1.947
|
|
propagated clock network latency
|
|
1.637 -0.310
|
|
clock pessimism -0.216 -0.526
|
|
SLICE_X6Y61 RAMD32 (Hold_ramd32_CLK_WADR0)
|
|
0.310 -0.216 u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/tfifo/ram_reg_0_15_0_5/RAMB_D1
|
|
-------------------------------------------------------------------
|
|
required time 0.216
|
|
arrival time -0.099
|
|
-------------------------------------------------------------------
|
|
slack 0.117
|
|
|
|
Slack (MET) : 0.117ns (arrival time - required time)
|
|
Source: u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/top_reg[0]/C
|
|
(rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Destination: u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/tfifo/ram_reg_0_15_0_5/RAMC/WADR0
|
|
(rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Path Group: sys_clk
|
|
Path Type: Hold (Min at Fast Process Corner)
|
|
Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns)
|
|
Data Path Delay: 0.444ns (logic 0.164ns (36.916%) route 0.280ns (63.084%))
|
|
Logic Levels: 0
|
|
Clock Path Skew: 0.017ns (DCD - SCD - CPR)
|
|
Destination Clock Delay (DCD): -0.310ns
|
|
Source Clock Delay (SCD): -0.543ns
|
|
Clock Pessimism Removal (CPR): 0.216ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock sys_clk rise edge) 0.000 0.000 r
|
|
clock source latency -1.848 -1.848
|
|
propagated clock network latency
|
|
1.305 -0.543
|
|
SLICE_X6Y62 FDRE 0.000 -0.543 r u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/top_reg[0]/C
|
|
SLICE_X6Y62 FDRE (Prop_fdre_C_Q) 0.164 -0.379 r u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/top_reg[0]/Q
|
|
net (fo=20, routed) 0.280 -0.099 u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/tfifo/ram_reg_0_15_0_5/ADDRD0
|
|
SLICE_X6Y61 RAMD32 r u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/tfifo/ram_reg_0_15_0_5/RAMC/WADR0
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock sys_clk rise edge) 0.000 0.000 r
|
|
clock source latency -1.947 -1.947
|
|
propagated clock network latency
|
|
1.637 -0.310
|
|
clock pessimism -0.216 -0.526
|
|
SLICE_X6Y61 RAMD32 (Hold_ramd32_CLK_WADR0)
|
|
0.310 -0.216 u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/tfifo/ram_reg_0_15_0_5/RAMC
|
|
-------------------------------------------------------------------
|
|
required time 0.216
|
|
arrival time -0.099
|
|
-------------------------------------------------------------------
|
|
slack 0.117
|
|
|
|
Slack (MET) : 0.117ns (arrival time - required time)
|
|
Source: u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/top_reg[0]/C
|
|
(rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Destination: u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/tfifo/ram_reg_0_15_0_5/RAMC/WADR0
|
|
(rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Path Group: sys_clk
|
|
Path Type: Hold (Min at Fast Process Corner)
|
|
Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns)
|
|
Data Path Delay: 0.444ns (logic 0.164ns (36.916%) route 0.280ns (63.084%))
|
|
Logic Levels: 0
|
|
Clock Path Skew: 0.017ns (DCD - SCD - CPR)
|
|
Destination Clock Delay (DCD): -0.310ns
|
|
Source Clock Delay (SCD): -0.543ns
|
|
Clock Pessimism Removal (CPR): 0.216ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock sys_clk rise edge) 0.000 0.000 r
|
|
clock source latency -1.848 -1.848
|
|
propagated clock network latency
|
|
1.305 -0.543
|
|
SLICE_X6Y62 FDRE 0.000 -0.543 r u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/top_reg[0]/C
|
|
SLICE_X6Y62 FDRE (Prop_fdre_C_Q) 0.164 -0.379 f u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/top_reg[0]/Q
|
|
net (fo=20, routed) 0.280 -0.099 u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/tfifo/ram_reg_0_15_0_5/ADDRD0
|
|
SLICE_X6Y61 RAMD32 f u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/tfifo/ram_reg_0_15_0_5/RAMC/WADR0
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock sys_clk rise edge) 0.000 0.000 r
|
|
clock source latency -1.947 -1.947
|
|
propagated clock network latency
|
|
1.637 -0.310
|
|
clock pessimism -0.216 -0.526
|
|
SLICE_X6Y61 RAMD32 (Hold_ramd32_CLK_WADR0)
|
|
0.310 -0.216 u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/tfifo/ram_reg_0_15_0_5/RAMC
|
|
-------------------------------------------------------------------
|
|
required time 0.216
|
|
arrival time -0.099
|
|
-------------------------------------------------------------------
|
|
slack 0.117
|
|
|
|
Slack (MET) : 0.117ns (arrival time - required time)
|
|
Source: u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/top_reg[0]/C
|
|
(rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Destination: u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/tfifo/ram_reg_0_15_0_5/RAMC_D1/WADR0
|
|
(rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Path Group: sys_clk
|
|
Path Type: Hold (Min at Fast Process Corner)
|
|
Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns)
|
|
Data Path Delay: 0.444ns (logic 0.164ns (36.916%) route 0.280ns (63.084%))
|
|
Logic Levels: 0
|
|
Clock Path Skew: 0.017ns (DCD - SCD - CPR)
|
|
Destination Clock Delay (DCD): -0.310ns
|
|
Source Clock Delay (SCD): -0.543ns
|
|
Clock Pessimism Removal (CPR): 0.216ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock sys_clk rise edge) 0.000 0.000 r
|
|
clock source latency -1.848 -1.848
|
|
propagated clock network latency
|
|
1.305 -0.543
|
|
SLICE_X6Y62 FDRE 0.000 -0.543 r u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/top_reg[0]/C
|
|
SLICE_X6Y62 FDRE (Prop_fdre_C_Q) 0.164 -0.379 r u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/top_reg[0]/Q
|
|
net (fo=20, routed) 0.280 -0.099 u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/tfifo/ram_reg_0_15_0_5/ADDRD0
|
|
SLICE_X6Y61 RAMD32 r u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/tfifo/ram_reg_0_15_0_5/RAMC_D1/WADR0
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock sys_clk rise edge) 0.000 0.000 r
|
|
clock source latency -1.947 -1.947
|
|
propagated clock network latency
|
|
1.637 -0.310
|
|
clock pessimism -0.216 -0.526
|
|
SLICE_X6Y61 RAMD32 (Hold_ramd32_CLK_WADR0)
|
|
0.310 -0.216 u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/tfifo/ram_reg_0_15_0_5/RAMC_D1
|
|
-------------------------------------------------------------------
|
|
required time 0.216
|
|
arrival time -0.099
|
|
-------------------------------------------------------------------
|
|
slack 0.117
|
|
|
|
Slack (MET) : 0.117ns (arrival time - required time)
|
|
Source: u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/top_reg[0]/C
|
|
(rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Destination: u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/tfifo/ram_reg_0_15_0_5/RAMC_D1/WADR0
|
|
(rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Path Group: sys_clk
|
|
Path Type: Hold (Min at Fast Process Corner)
|
|
Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns)
|
|
Data Path Delay: 0.444ns (logic 0.164ns (36.916%) route 0.280ns (63.084%))
|
|
Logic Levels: 0
|
|
Clock Path Skew: 0.017ns (DCD - SCD - CPR)
|
|
Destination Clock Delay (DCD): -0.310ns
|
|
Source Clock Delay (SCD): -0.543ns
|
|
Clock Pessimism Removal (CPR): 0.216ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock sys_clk rise edge) 0.000 0.000 r
|
|
clock source latency -1.848 -1.848
|
|
propagated clock network latency
|
|
1.305 -0.543
|
|
SLICE_X6Y62 FDRE 0.000 -0.543 r u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/top_reg[0]/C
|
|
SLICE_X6Y62 FDRE (Prop_fdre_C_Q) 0.164 -0.379 f u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/top_reg[0]/Q
|
|
net (fo=20, routed) 0.280 -0.099 u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/tfifo/ram_reg_0_15_0_5/ADDRD0
|
|
SLICE_X6Y61 RAMD32 f u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/tfifo/ram_reg_0_15_0_5/RAMC_D1/WADR0
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock sys_clk rise edge) 0.000 0.000 r
|
|
clock source latency -1.947 -1.947
|
|
propagated clock network latency
|
|
1.637 -0.310
|
|
clock pessimism -0.216 -0.526
|
|
SLICE_X6Y61 RAMD32 (Hold_ramd32_CLK_WADR0)
|
|
0.310 -0.216 u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/tfifo/ram_reg_0_15_0_5/RAMC_D1
|
|
-------------------------------------------------------------------
|
|
required time 0.216
|
|
arrival time -0.099
|
|
-------------------------------------------------------------------
|
|
slack 0.117
|
|
|
|
Slack (MET) : 0.117ns (arrival time - required time)
|
|
Source: u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/top_reg[0]/C
|
|
(rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Destination: u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/tfifo/ram_reg_0_15_0_5/RAMD/ADR0
|
|
(rising edge-triggered cell RAMS32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Path Group: sys_clk
|
|
Path Type: Hold (Min at Fast Process Corner)
|
|
Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns)
|
|
Data Path Delay: 0.444ns (logic 0.164ns (36.916%) route 0.280ns (63.084%))
|
|
Logic Levels: 0
|
|
Clock Path Skew: 0.017ns (DCD - SCD - CPR)
|
|
Destination Clock Delay (DCD): -0.310ns
|
|
Source Clock Delay (SCD): -0.543ns
|
|
Clock Pessimism Removal (CPR): 0.216ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock sys_clk rise edge) 0.000 0.000 r
|
|
clock source latency -1.848 -1.848
|
|
propagated clock network latency
|
|
1.305 -0.543
|
|
SLICE_X6Y62 FDRE 0.000 -0.543 r u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/top_reg[0]/C
|
|
SLICE_X6Y62 FDRE (Prop_fdre_C_Q) 0.164 -0.379 r u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/top_reg[0]/Q
|
|
net (fo=20, routed) 0.280 -0.099 u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/tfifo/ram_reg_0_15_0_5/ADDRD0
|
|
SLICE_X6Y61 RAMS32 r u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/tfifo/ram_reg_0_15_0_5/RAMD/ADR0
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock sys_clk rise edge) 0.000 0.000 r
|
|
clock source latency -1.947 -1.947
|
|
propagated clock network latency
|
|
1.637 -0.310
|
|
clock pessimism -0.216 -0.526
|
|
SLICE_X6Y61 RAMS32 (Hold_rams32_CLK_ADR0)
|
|
0.310 -0.216 u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/tfifo/ram_reg_0_15_0_5/RAMD
|
|
-------------------------------------------------------------------
|
|
required time 0.216
|
|
arrival time -0.099
|
|
-------------------------------------------------------------------
|
|
slack 0.117
|
|
|
|
Slack (MET) : 0.117ns (arrival time - required time)
|
|
Source: u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/top_reg[0]/C
|
|
(rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Destination: u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/tfifo/ram_reg_0_15_0_5/RAMD/ADR0
|
|
(rising edge-triggered cell RAMS32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Path Group: sys_clk
|
|
Path Type: Hold (Min at Fast Process Corner)
|
|
Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns)
|
|
Data Path Delay: 0.444ns (logic 0.164ns (36.916%) route 0.280ns (63.084%))
|
|
Logic Levels: 0
|
|
Clock Path Skew: 0.017ns (DCD - SCD - CPR)
|
|
Destination Clock Delay (DCD): -0.310ns
|
|
Source Clock Delay (SCD): -0.543ns
|
|
Clock Pessimism Removal (CPR): 0.216ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock sys_clk rise edge) 0.000 0.000 r
|
|
clock source latency -1.848 -1.848
|
|
propagated clock network latency
|
|
1.305 -0.543
|
|
SLICE_X6Y62 FDRE 0.000 -0.543 r u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/top_reg[0]/C
|
|
SLICE_X6Y62 FDRE (Prop_fdre_C_Q) 0.164 -0.379 f u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/top_reg[0]/Q
|
|
net (fo=20, routed) 0.280 -0.099 u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/tfifo/ram_reg_0_15_0_5/ADDRD0
|
|
SLICE_X6Y61 RAMS32 f u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/tfifo/ram_reg_0_15_0_5/RAMD/ADR0
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock sys_clk rise edge) 0.000 0.000 r
|
|
clock source latency -1.947 -1.947
|
|
propagated clock network latency
|
|
1.637 -0.310
|
|
clock pessimism -0.216 -0.526
|
|
SLICE_X6Y61 RAMS32 (Hold_rams32_CLK_ADR0)
|
|
0.310 -0.216 u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/tfifo/ram_reg_0_15_0_5/RAMD
|
|
-------------------------------------------------------------------
|
|
required time 0.216
|
|
arrival time -0.099
|
|
-------------------------------------------------------------------
|
|
slack 0.117
|
|
|
|
Slack (MET) : 0.117ns (arrival time - required time)
|
|
Source: u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/top_reg[0]/C
|
|
(rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Destination: u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/tfifo/ram_reg_0_15_0_5/RAMD_D1/ADR0
|
|
(rising edge-triggered cell RAMS32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Path Group: sys_clk
|
|
Path Type: Hold (Min at Fast Process Corner)
|
|
Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns)
|
|
Data Path Delay: 0.444ns (logic 0.164ns (36.916%) route 0.280ns (63.084%))
|
|
Logic Levels: 0
|
|
Clock Path Skew: 0.017ns (DCD - SCD - CPR)
|
|
Destination Clock Delay (DCD): -0.310ns
|
|
Source Clock Delay (SCD): -0.543ns
|
|
Clock Pessimism Removal (CPR): 0.216ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock sys_clk rise edge) 0.000 0.000 r
|
|
clock source latency -1.848 -1.848
|
|
propagated clock network latency
|
|
1.305 -0.543
|
|
SLICE_X6Y62 FDRE 0.000 -0.543 r u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/top_reg[0]/C
|
|
SLICE_X6Y62 FDRE (Prop_fdre_C_Q) 0.164 -0.379 r u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/top_reg[0]/Q
|
|
net (fo=20, routed) 0.280 -0.099 u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/tfifo/ram_reg_0_15_0_5/ADDRD0
|
|
SLICE_X6Y61 RAMS32 r u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/tfifo/ram_reg_0_15_0_5/RAMD_D1/ADR0
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock sys_clk rise edge) 0.000 0.000 r
|
|
clock source latency -1.947 -1.947
|
|
propagated clock network latency
|
|
1.637 -0.310
|
|
clock pessimism -0.216 -0.526
|
|
SLICE_X6Y61 RAMS32 (Hold_rams32_CLK_ADR0)
|
|
0.310 -0.216 u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/tfifo/ram_reg_0_15_0_5/RAMD_D1
|
|
-------------------------------------------------------------------
|
|
required time 0.216
|
|
arrival time -0.099
|
|
-------------------------------------------------------------------
|
|
slack 0.117
|
|
|
|
Slack (MET) : 0.117ns (arrival time - required time)
|
|
Source: u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/top_reg[0]/C
|
|
(rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Destination: u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/tfifo/ram_reg_0_15_0_5/RAMD_D1/ADR0
|
|
(rising edge-triggered cell RAMS32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Path Group: sys_clk
|
|
Path Type: Hold (Min at Fast Process Corner)
|
|
Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns)
|
|
Data Path Delay: 0.444ns (logic 0.164ns (36.916%) route 0.280ns (63.084%))
|
|
Logic Levels: 0
|
|
Clock Path Skew: 0.017ns (DCD - SCD - CPR)
|
|
Destination Clock Delay (DCD): -0.310ns
|
|
Source Clock Delay (SCD): -0.543ns
|
|
Clock Pessimism Removal (CPR): 0.216ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock sys_clk rise edge) 0.000 0.000 r
|
|
clock source latency -1.848 -1.848
|
|
propagated clock network latency
|
|
1.305 -0.543
|
|
SLICE_X6Y62 FDRE 0.000 -0.543 r u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/top_reg[0]/C
|
|
SLICE_X6Y62 FDRE (Prop_fdre_C_Q) 0.164 -0.379 f u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/top_reg[0]/Q
|
|
net (fo=20, routed) 0.280 -0.099 u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/tfifo/ram_reg_0_15_0_5/ADDRD0
|
|
SLICE_X6Y61 RAMS32 f u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/tfifo/ram_reg_0_15_0_5/RAMD_D1/ADR0
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock sys_clk rise edge) 0.000 0.000 r
|
|
clock source latency -1.947 -1.947
|
|
propagated clock network latency
|
|
1.637 -0.310
|
|
clock pessimism -0.216 -0.526
|
|
SLICE_X6Y61 RAMS32 (Hold_rams32_CLK_ADR0)
|
|
0.310 -0.216 u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/tfifo/ram_reg_0_15_0_5/RAMD_D1
|
|
-------------------------------------------------------------------
|
|
required time 0.216
|
|
arrival time -0.099
|
|
-------------------------------------------------------------------
|
|
slack 0.117
|
|
|
|
Slack (MET) : 0.118ns (arrival time - required time)
|
|
Source: u_cpu/axi_bridge/wdata_reg[15]/C
|
|
(rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns})
|
|
Destination: u_Axi_CDC/wFifo/ram_reg_0_7_12_17/RAMB_D1/I
|
|
(rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns})
|
|
Path Group: cpu_clk
|
|
Path Type: Hold (Min at Fast Process Corner)
|
|
Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns)
|
|
Data Path Delay: 0.257ns (logic 0.141ns (54.812%) route 0.116ns (45.188%))
|
|
Logic Levels: 0
|
|
Clock Path Skew: 0.015ns (DCD - SCD - CPR)
|
|
Destination Clock Delay (DCD): -0.232ns
|
|
Source Clock Delay (SCD): -0.467ns
|
|
Clock Pessimism Removal (CPR): 0.220ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock cpu_clk rise edge) 0.000 0.000 r
|
|
clock source latency -1.848 -1.848
|
|
propagated clock network latency
|
|
1.382 -0.467
|
|
SLICE_X7Y48 FDRE 0.000 -0.467 r u_cpu/axi_bridge/wdata_reg[15]/C
|
|
SLICE_X7Y48 FDRE (Prop_fdre_C_Q) 0.141 -0.326 r u_cpu/axi_bridge/wdata_reg[15]/Q
|
|
net (fo=1, routed) 0.116 -0.210 u_Axi_CDC/wFifo/ram_reg_0_7_12_17/DIB1
|
|
SLICE_X6Y46 RAMD32 r u_Axi_CDC/wFifo/ram_reg_0_7_12_17/RAMB_D1/I
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock cpu_clk rise edge) 0.000 0.000 r
|
|
clock source latency -1.947 -1.947
|
|
propagated clock network latency
|
|
1.715 -0.232
|
|
clock pessimism -0.220 -0.452
|
|
SLICE_X6Y46 RAMD32 (Hold_ramd32_CLK_I)
|
|
0.124 -0.328 u_Axi_CDC/wFifo/ram_reg_0_7_12_17/RAMB_D1
|
|
-------------------------------------------------------------------
|
|
required time 0.328
|
|
arrival time -0.210
|
|
-------------------------------------------------------------------
|
|
slack 0.118
|
|
|
|
Slack (MET) : 0.118ns (arrival time - required time)
|
|
Source: u_cpu/axi_bridge/wdata_reg[15]/C
|
|
(rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns})
|
|
Destination: u_Axi_CDC/wFifo/ram_reg_0_7_12_17/RAMB_D1/I
|
|
(rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns})
|
|
Path Group: cpu_clk
|
|
Path Type: Hold (Min at Fast Process Corner)
|
|
Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns)
|
|
Data Path Delay: 0.257ns (logic 0.141ns (54.812%) route 0.116ns (45.188%))
|
|
Logic Levels: 0
|
|
Clock Path Skew: 0.015ns (DCD - SCD - CPR)
|
|
Destination Clock Delay (DCD): -0.232ns
|
|
Source Clock Delay (SCD): -0.467ns
|
|
Clock Pessimism Removal (CPR): 0.220ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock cpu_clk rise edge) 0.000 0.000 r
|
|
clock source latency -1.848 -1.848
|
|
propagated clock network latency
|
|
1.382 -0.467
|
|
SLICE_X7Y48 FDRE 0.000 -0.467 r u_cpu/axi_bridge/wdata_reg[15]/C
|
|
SLICE_X7Y48 FDRE (Prop_fdre_C_Q) 0.141 -0.326 f u_cpu/axi_bridge/wdata_reg[15]/Q
|
|
net (fo=1, routed) 0.116 -0.210 u_Axi_CDC/wFifo/ram_reg_0_7_12_17/DIB1
|
|
SLICE_X6Y46 RAMD32 f u_Axi_CDC/wFifo/ram_reg_0_7_12_17/RAMB_D1/I
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock cpu_clk rise edge) 0.000 0.000 r
|
|
clock source latency -1.947 -1.947
|
|
propagated clock network latency
|
|
1.715 -0.232
|
|
clock pessimism -0.220 -0.452
|
|
SLICE_X6Y46 RAMD32 (Hold_ramd32_CLK_I)
|
|
0.124 -0.328 u_Axi_CDC/wFifo/ram_reg_0_7_12_17/RAMB_D1
|
|
-------------------------------------------------------------------
|
|
required time 0.328
|
|
arrival time -0.210
|
|
-------------------------------------------------------------------
|
|
slack 0.118
|
|
|
|
Slack (MET) : 0.121ns (arrival time - required time)
|
|
Source: u_cpu/u_csr/csr_tlbelo1_reg[3]/C
|
|
(rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns})
|
|
Destination: u_cpu/addr_trans/tlb_entry/tlb_plv1_reg_r3_0_31_1_1/SP/I
|
|
(rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns})
|
|
Path Group: cpu_clk
|
|
Path Type: Hold (Min at Fast Process Corner)
|
|
Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns)
|
|
Data Path Delay: 0.261ns (logic 0.141ns (54.075%) route 0.120ns (45.925%))
|
|
Logic Levels: 0
|
|
Clock Path Skew: 0.016ns (DCD - SCD - CPR)
|
|
Destination Clock Delay (DCD): -0.275ns
|
|
Source Clock Delay (SCD): -0.509ns
|
|
Clock Pessimism Removal (CPR): 0.218ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock cpu_clk rise edge) 0.000 0.000 r
|
|
clock source latency -1.848 -1.848
|
|
propagated clock network latency
|
|
1.340 -0.509
|
|
SLICE_X39Y39 FDRE 0.000 -0.509 r u_cpu/u_csr/csr_tlbelo1_reg[3]/C
|
|
SLICE_X39Y39 FDRE (Prop_fdre_C_Q) 0.141 -0.368 r u_cpu/u_csr/csr_tlbelo1_reg[3]/Q
|
|
net (fo=7, routed) 0.120 -0.248 u_cpu/addr_trans/tlb_entry/tlb_plv1_reg_r3_0_31_1_1/D
|
|
SLICE_X40Y39 RAMD32 r u_cpu/addr_trans/tlb_entry/tlb_plv1_reg_r3_0_31_1_1/SP/I
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock cpu_clk rise edge) 0.000 0.000 r
|
|
clock source latency -1.947 -1.947
|
|
propagated clock network latency
|
|
1.672 -0.275
|
|
clock pessimism -0.218 -0.493
|
|
SLICE_X40Y39 RAMD32 (Hold_ramd32_CLK_I)
|
|
0.124 -0.369 u_cpu/addr_trans/tlb_entry/tlb_plv1_reg_r3_0_31_1_1/SP
|
|
-------------------------------------------------------------------
|
|
required time 0.369
|
|
arrival time -0.248
|
|
-------------------------------------------------------------------
|
|
slack 0.121
|
|
|
|
Slack (MET) : 0.121ns (arrival time - required time)
|
|
Source: u_cpu/u_csr/csr_tlbelo1_reg[3]/C
|
|
(rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns})
|
|
Destination: u_cpu/addr_trans/tlb_entry/tlb_plv1_reg_r3_0_31_1_1/SP/I
|
|
(rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns})
|
|
Path Group: cpu_clk
|
|
Path Type: Hold (Min at Fast Process Corner)
|
|
Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns)
|
|
Data Path Delay: 0.261ns (logic 0.141ns (54.075%) route 0.120ns (45.925%))
|
|
Logic Levels: 0
|
|
Clock Path Skew: 0.016ns (DCD - SCD - CPR)
|
|
Destination Clock Delay (DCD): -0.275ns
|
|
Source Clock Delay (SCD): -0.509ns
|
|
Clock Pessimism Removal (CPR): 0.218ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock cpu_clk rise edge) 0.000 0.000 r
|
|
clock source latency -1.848 -1.848
|
|
propagated clock network latency
|
|
1.340 -0.509
|
|
SLICE_X39Y39 FDRE 0.000 -0.509 r u_cpu/u_csr/csr_tlbelo1_reg[3]/C
|
|
SLICE_X39Y39 FDRE (Prop_fdre_C_Q) 0.141 -0.368 f u_cpu/u_csr/csr_tlbelo1_reg[3]/Q
|
|
net (fo=7, routed) 0.120 -0.248 u_cpu/addr_trans/tlb_entry/tlb_plv1_reg_r3_0_31_1_1/D
|
|
SLICE_X40Y39 RAMD32 f u_cpu/addr_trans/tlb_entry/tlb_plv1_reg_r3_0_31_1_1/SP/I
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock cpu_clk rise edge) 0.000 0.000 r
|
|
clock source latency -1.947 -1.947
|
|
propagated clock network latency
|
|
1.672 -0.275
|
|
clock pessimism -0.218 -0.493
|
|
SLICE_X40Y39 RAMD32 (Hold_ramd32_CLK_I)
|
|
0.124 -0.369 u_cpu/addr_trans/tlb_entry/tlb_plv1_reg_r3_0_31_1_1/SP
|
|
-------------------------------------------------------------------
|
|
required time 0.369
|
|
arrival time -0.248
|
|
-------------------------------------------------------------------
|
|
slack 0.121
|
|
|
|
Slack (MET) : 0.121ns (arrival time - required time)
|
|
Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_18_23/RAMB_D1/CLK
|
|
(rising edge-triggered cell RAMD32 clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns})
|
|
Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[21]/D
|
|
(rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Path Group: sys_clk
|
|
Path Type: Hold (Min at Fast Process Corner)
|
|
Requirement: 0.000ns (sys_clk rise@0.000ns - mlkem_clk_clk_pll rise@0.000ns)
|
|
Data Path Delay: 0.723ns (logic 0.388ns (53.631%) route 0.335ns (46.369%))
|
|
Logic Levels: 0
|
|
Clock Path Skew: 0.334ns (DCD - SCD - CPR)
|
|
Destination Clock Delay (DCD): -0.392ns
|
|
Source Clock Delay (SCD): -0.627ns
|
|
Clock Pessimism Removal (CPR): -0.099ns
|
|
Clock Uncertainty: 0.197ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Discrete Jitter (DJ): 0.136ns
|
|
Phase Error (PE): 0.120ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock mlkem_clk_clk_pll rise edge)
|
|
0.000 0.000 r
|
|
clock source latency -1.848 -1.848
|
|
propagated clock network latency
|
|
1.221 -0.627
|
|
SLICE_X64Y75 RAMD32 0.000 -0.627 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_18_23/RAMB_D1/CLK
|
|
SLICE_X64Y75 RAMD32 (Prop_ramd32_CLK_O)
|
|
0.388 -0.239 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_18_23/RAMB_D1/O
|
|
net (fo=1, routed) 0.335 0.096 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port10__3[21]
|
|
SLICE_X57Y78 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[21]/D
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock sys_clk rise edge) 0.000 0.000 r
|
|
clock source latency -1.947 -1.947
|
|
propagated clock network latency
|
|
1.555 -0.392
|
|
clock pessimism 0.099 -0.293
|
|
clock uncertainty 0.197 -0.097
|
|
SLICE_X57Y78 FDRE (Hold_fdre_C_D) 0.072 -0.025 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[21]
|
|
-------------------------------------------------------------------
|
|
required time 0.025
|
|
arrival time 0.096
|
|
-------------------------------------------------------------------
|
|
slack 0.121
|
|
|
|
Slack (MET) : 0.121ns (arrival time - required time)
|
|
Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_18_23/RAMB_D1/CLK
|
|
(rising edge-triggered cell RAMD32 clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns})
|
|
Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[21]/D
|
|
(rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Path Group: sys_clk
|
|
Path Type: Hold (Min at Fast Process Corner)
|
|
Requirement: 0.000ns (sys_clk rise@0.000ns - mlkem_clk_clk_pll rise@0.000ns)
|
|
Data Path Delay: 0.723ns (logic 0.388ns (53.631%) route 0.335ns (46.369%))
|
|
Logic Levels: 0
|
|
Clock Path Skew: 0.334ns (DCD - SCD - CPR)
|
|
Destination Clock Delay (DCD): -0.392ns
|
|
Source Clock Delay (SCD): -0.627ns
|
|
Clock Pessimism Removal (CPR): -0.099ns
|
|
Clock Uncertainty: 0.197ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Discrete Jitter (DJ): 0.136ns
|
|
Phase Error (PE): 0.120ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock mlkem_clk_clk_pll rise edge)
|
|
0.000 0.000 r
|
|
clock source latency -1.848 -1.848
|
|
propagated clock network latency
|
|
1.221 -0.627
|
|
SLICE_X64Y75 RAMD32 0.000 -0.627 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_18_23/RAMB_D1/CLK
|
|
SLICE_X64Y75 RAMD32 (Prop_ramd32_CLK_O)
|
|
0.388 -0.239 f u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_18_23/RAMB_D1/O
|
|
net (fo=1, routed) 0.335 0.096 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port10__3[21]
|
|
SLICE_X57Y78 FDRE f u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[21]/D
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock sys_clk rise edge) 0.000 0.000 r
|
|
clock source latency -1.947 -1.947
|
|
propagated clock network latency
|
|
1.555 -0.392
|
|
clock pessimism 0.099 -0.293
|
|
clock uncertainty 0.197 -0.097
|
|
SLICE_X57Y78 FDRE (Hold_fdre_C_D) 0.072 -0.025 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[21]
|
|
-------------------------------------------------------------------
|
|
required time 0.025
|
|
arrival time 0.096
|
|
-------------------------------------------------------------------
|
|
slack 0.121
|
|
|
|
Slack (MET) : 0.121ns (arrival time - required time)
|
|
Source: u_Axi_CDC/arFifo/pushToPopGray_buffercc/buffers_0_reg[2]/C
|
|
(rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Destination: u_Axi_CDC/arFifo/pushToPopGray_buffercc/buffers_1_reg[2]/D
|
|
(rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Path Group: sys_clk
|
|
Path Type: Hold (Min at Fast Process Corner)
|
|
Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns)
|
|
Data Path Delay: 0.197ns (logic 0.141ns (71.611%) route 0.056ns (28.389%))
|
|
Logic Levels: 0
|
|
Clock Path Skew: 0.000ns (DCD - SCD - CPR)
|
|
Destination Clock Delay (DCD): -0.344ns
|
|
Source Clock Delay (SCD): -0.572ns
|
|
Clock Pessimism Removal (CPR): 0.228ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock sys_clk rise edge) 0.000 0.000 r
|
|
clock source latency -1.848 -1.848
|
|
propagated clock network latency
|
|
1.276 -0.572
|
|
SLICE_X15Y66 FDCE 0.000 -0.572 r u_Axi_CDC/arFifo/pushToPopGray_buffercc/buffers_0_reg[2]/C
|
|
SLICE_X15Y66 FDCE (Prop_fdce_C_Q) 0.141 -0.431 r u_Axi_CDC/arFifo/pushToPopGray_buffercc/buffers_0_reg[2]/Q
|
|
net (fo=1, routed) 0.056 -0.375 u_Axi_CDC/arFifo/pushToPopGray_buffercc/buffers_0[2]
|
|
SLICE_X15Y66 FDCE r u_Axi_CDC/arFifo/pushToPopGray_buffercc/buffers_1_reg[2]/D
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock sys_clk rise edge) 0.000 0.000 r
|
|
clock source latency -1.947 -1.947
|
|
propagated clock network latency
|
|
1.603 -0.344
|
|
clock pessimism -0.228 -0.572
|
|
SLICE_X15Y66 FDCE (Hold_fdce_C_D) 0.076 -0.496 u_Axi_CDC/arFifo/pushToPopGray_buffercc/buffers_1_reg[2]
|
|
-------------------------------------------------------------------
|
|
required time 0.496
|
|
arrival time -0.375
|
|
-------------------------------------------------------------------
|
|
slack 0.121
|
|
|
|
Slack (MET) : 0.121ns (arrival time - required time)
|
|
Source: u_Axi_CDC/arFifo/pushToPopGray_buffercc/buffers_0_reg[2]/C
|
|
(rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Destination: u_Axi_CDC/arFifo/pushToPopGray_buffercc/buffers_1_reg[2]/D
|
|
(rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Path Group: sys_clk
|
|
Path Type: Hold (Min at Fast Process Corner)
|
|
Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns)
|
|
Data Path Delay: 0.197ns (logic 0.141ns (71.611%) route 0.056ns (28.389%))
|
|
Logic Levels: 0
|
|
Clock Path Skew: 0.000ns (DCD - SCD - CPR)
|
|
Destination Clock Delay (DCD): -0.344ns
|
|
Source Clock Delay (SCD): -0.572ns
|
|
Clock Pessimism Removal (CPR): 0.228ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock sys_clk rise edge) 0.000 0.000 r
|
|
clock source latency -1.848 -1.848
|
|
propagated clock network latency
|
|
1.276 -0.572
|
|
SLICE_X15Y66 FDCE 0.000 -0.572 r u_Axi_CDC/arFifo/pushToPopGray_buffercc/buffers_0_reg[2]/C
|
|
SLICE_X15Y66 FDCE (Prop_fdce_C_Q) 0.141 -0.431 f u_Axi_CDC/arFifo/pushToPopGray_buffercc/buffers_0_reg[2]/Q
|
|
net (fo=1, routed) 0.056 -0.375 u_Axi_CDC/arFifo/pushToPopGray_buffercc/buffers_0[2]
|
|
SLICE_X15Y66 FDCE f u_Axi_CDC/arFifo/pushToPopGray_buffercc/buffers_1_reg[2]/D
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock sys_clk rise edge) 0.000 0.000 r
|
|
clock source latency -1.947 -1.947
|
|
propagated clock network latency
|
|
1.603 -0.344
|
|
clock pessimism -0.228 -0.572
|
|
SLICE_X15Y66 FDCE (Hold_fdce_C_D) 0.076 -0.496 u_Axi_CDC/arFifo/pushToPopGray_buffercc/buffers_1_reg[2]
|
|
-------------------------------------------------------------------
|
|
required time 0.496
|
|
arrival time -0.375
|
|
-------------------------------------------------------------------
|
|
slack 0.121
|
|
|
|
Slack (MET) : 0.121ns (arrival time - required time)
|
|
Source: u_Axi_CDC/awFifo/pushToPopGray_buffercc/buffers_0_reg[2]/C
|
|
(rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Destination: u_Axi_CDC/awFifo/pushToPopGray_buffercc/buffers_1_reg[2]/D
|
|
(rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Path Group: sys_clk
|
|
Path Type: Hold (Min at Fast Process Corner)
|
|
Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns)
|
|
Data Path Delay: 0.197ns (logic 0.141ns (71.611%) route 0.056ns (28.389%))
|
|
Logic Levels: 0
|
|
Clock Path Skew: 0.000ns (DCD - SCD - CPR)
|
|
Destination Clock Delay (DCD): -0.348ns
|
|
Source Clock Delay (SCD): -0.576ns
|
|
Clock Pessimism Removal (CPR): 0.228ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock sys_clk rise edge) 0.000 0.000 r
|
|
clock source latency -1.848 -1.848
|
|
propagated clock network latency
|
|
1.272 -0.576
|
|
SLICE_X15Y70 FDCE 0.000 -0.576 r u_Axi_CDC/awFifo/pushToPopGray_buffercc/buffers_0_reg[2]/C
|
|
SLICE_X15Y70 FDCE (Prop_fdce_C_Q) 0.141 -0.435 r u_Axi_CDC/awFifo/pushToPopGray_buffercc/buffers_0_reg[2]/Q
|
|
net (fo=1, routed) 0.056 -0.379 u_Axi_CDC/awFifo/pushToPopGray_buffercc/buffers_0[2]
|
|
SLICE_X15Y70 FDCE r u_Axi_CDC/awFifo/pushToPopGray_buffercc/buffers_1_reg[2]/D
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock sys_clk rise edge) 0.000 0.000 r
|
|
clock source latency -1.947 -1.947
|
|
propagated clock network latency
|
|
1.599 -0.348
|
|
clock pessimism -0.228 -0.576
|
|
SLICE_X15Y70 FDCE (Hold_fdce_C_D) 0.076 -0.500 u_Axi_CDC/awFifo/pushToPopGray_buffercc/buffers_1_reg[2]
|
|
-------------------------------------------------------------------
|
|
required time 0.500
|
|
arrival time -0.379
|
|
-------------------------------------------------------------------
|
|
slack 0.121
|
|
|
|
Slack (MET) : 0.121ns (arrival time - required time)
|
|
Source: u_Axi_CDC/awFifo/pushToPopGray_buffercc/buffers_0_reg[2]/C
|
|
(rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Destination: u_Axi_CDC/awFifo/pushToPopGray_buffercc/buffers_1_reg[2]/D
|
|
(rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Path Group: sys_clk
|
|
Path Type: Hold (Min at Fast Process Corner)
|
|
Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns)
|
|
Data Path Delay: 0.197ns (logic 0.141ns (71.611%) route 0.056ns (28.389%))
|
|
Logic Levels: 0
|
|
Clock Path Skew: 0.000ns (DCD - SCD - CPR)
|
|
Destination Clock Delay (DCD): -0.348ns
|
|
Source Clock Delay (SCD): -0.576ns
|
|
Clock Pessimism Removal (CPR): 0.228ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock sys_clk rise edge) 0.000 0.000 r
|
|
clock source latency -1.848 -1.848
|
|
propagated clock network latency
|
|
1.272 -0.576
|
|
SLICE_X15Y70 FDCE 0.000 -0.576 r u_Axi_CDC/awFifo/pushToPopGray_buffercc/buffers_0_reg[2]/C
|
|
SLICE_X15Y70 FDCE (Prop_fdce_C_Q) 0.141 -0.435 f u_Axi_CDC/awFifo/pushToPopGray_buffercc/buffers_0_reg[2]/Q
|
|
net (fo=1, routed) 0.056 -0.379 u_Axi_CDC/awFifo/pushToPopGray_buffercc/buffers_0[2]
|
|
SLICE_X15Y70 FDCE f u_Axi_CDC/awFifo/pushToPopGray_buffercc/buffers_1_reg[2]/D
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock sys_clk rise edge) 0.000 0.000 r
|
|
clock source latency -1.947 -1.947
|
|
propagated clock network latency
|
|
1.599 -0.348
|
|
clock pessimism -0.228 -0.576
|
|
SLICE_X15Y70 FDCE (Hold_fdce_C_D) 0.076 -0.500 u_Axi_CDC/awFifo/pushToPopGray_buffercc/buffers_1_reg[2]
|
|
-------------------------------------------------------------------
|
|
required time 0.500
|
|
arrival time -0.379
|
|
-------------------------------------------------------------------
|
|
slack 0.121
|
|
|
|
Slack (MET) : 0.121ns (arrival time - required time)
|
|
Source: u_Axi_CDC/bFifo/popToPushGray_buffercc/buffers_0_reg[2]/C
|
|
(rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Destination: u_Axi_CDC/bFifo/popToPushGray_buffercc/buffers_1_reg[2]/D
|
|
(rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Path Group: sys_clk
|
|
Path Type: Hold (Min at Fast Process Corner)
|
|
Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns)
|
|
Data Path Delay: 0.197ns (logic 0.141ns (71.611%) route 0.056ns (28.389%))
|
|
Logic Levels: 0
|
|
Clock Path Skew: 0.000ns (DCD - SCD - CPR)
|
|
Destination Clock Delay (DCD): -0.338ns
|
|
Source Clock Delay (SCD): -0.568ns
|
|
Clock Pessimism Removal (CPR): 0.230ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock sys_clk rise edge) 0.000 0.000 r
|
|
clock source latency -1.848 -1.848
|
|
propagated clock network latency
|
|
1.280 -0.568
|
|
SLICE_X17Y59 FDCE 0.000 -0.568 r u_Axi_CDC/bFifo/popToPushGray_buffercc/buffers_0_reg[2]/C
|
|
SLICE_X17Y59 FDCE (Prop_fdce_C_Q) 0.141 -0.427 r u_Axi_CDC/bFifo/popToPushGray_buffercc/buffers_0_reg[2]/Q
|
|
net (fo=1, routed) 0.056 -0.371 u_Axi_CDC/bFifo/popToPushGray_buffercc/buffers_0[2]
|
|
SLICE_X17Y59 FDCE r u_Axi_CDC/bFifo/popToPushGray_buffercc/buffers_1_reg[2]/D
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock sys_clk rise edge) 0.000 0.000 r
|
|
clock source latency -1.947 -1.947
|
|
propagated clock network latency
|
|
1.609 -0.338
|
|
clock pessimism -0.230 -0.568
|
|
SLICE_X17Y59 FDCE (Hold_fdce_C_D) 0.076 -0.492 u_Axi_CDC/bFifo/popToPushGray_buffercc/buffers_1_reg[2]
|
|
-------------------------------------------------------------------
|
|
required time 0.492
|
|
arrival time -0.371
|
|
-------------------------------------------------------------------
|
|
slack 0.121
|
|
|
|
Slack (MET) : 0.121ns (arrival time - required time)
|
|
Source: u_Axi_CDC/bFifo/popToPushGray_buffercc/buffers_0_reg[2]/C
|
|
(rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Destination: u_Axi_CDC/bFifo/popToPushGray_buffercc/buffers_1_reg[2]/D
|
|
(rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Path Group: sys_clk
|
|
Path Type: Hold (Min at Fast Process Corner)
|
|
Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns)
|
|
Data Path Delay: 0.197ns (logic 0.141ns (71.611%) route 0.056ns (28.389%))
|
|
Logic Levels: 0
|
|
Clock Path Skew: 0.000ns (DCD - SCD - CPR)
|
|
Destination Clock Delay (DCD): -0.338ns
|
|
Source Clock Delay (SCD): -0.568ns
|
|
Clock Pessimism Removal (CPR): 0.230ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock sys_clk rise edge) 0.000 0.000 r
|
|
clock source latency -1.848 -1.848
|
|
propagated clock network latency
|
|
1.280 -0.568
|
|
SLICE_X17Y59 FDCE 0.000 -0.568 r u_Axi_CDC/bFifo/popToPushGray_buffercc/buffers_0_reg[2]/C
|
|
SLICE_X17Y59 FDCE (Prop_fdce_C_Q) 0.141 -0.427 f u_Axi_CDC/bFifo/popToPushGray_buffercc/buffers_0_reg[2]/Q
|
|
net (fo=1, routed) 0.056 -0.371 u_Axi_CDC/bFifo/popToPushGray_buffercc/buffers_0[2]
|
|
SLICE_X17Y59 FDCE f u_Axi_CDC/bFifo/popToPushGray_buffercc/buffers_1_reg[2]/D
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock sys_clk rise edge) 0.000 0.000 r
|
|
clock source latency -1.947 -1.947
|
|
propagated clock network latency
|
|
1.609 -0.338
|
|
clock pessimism -0.230 -0.568
|
|
SLICE_X17Y59 FDCE (Hold_fdce_C_D) 0.076 -0.492 u_Axi_CDC/bFifo/popToPushGray_buffercc/buffers_1_reg[2]
|
|
-------------------------------------------------------------------
|
|
required time 0.492
|
|
arrival time -0.371
|
|
-------------------------------------------------------------------
|
|
slack 0.121
|
|
|
|
Slack (MET) : 0.121ns (arrival time - required time)
|
|
Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/popToPushGray_buffercc/buffers_0_reg[2]/C
|
|
(rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/popToPushGray_buffercc/buffers_1_reg[2]/D
|
|
(rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Path Group: sys_clk
|
|
Path Type: Hold (Min at Fast Process Corner)
|
|
Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns)
|
|
Data Path Delay: 0.197ns (logic 0.141ns (71.611%) route 0.056ns (28.389%))
|
|
Logic Levels: 0
|
|
Clock Path Skew: 0.000ns (DCD - SCD - CPR)
|
|
Destination Clock Delay (DCD): -0.354ns
|
|
Source Clock Delay (SCD): -0.582ns
|
|
Clock Pessimism Removal (CPR): 0.228ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock sys_clk rise edge) 0.000 0.000 r
|
|
clock source latency -1.848 -1.848
|
|
propagated clock network latency
|
|
1.266 -0.582
|
|
SLICE_X27Y78 FDCE 0.000 -0.582 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/popToPushGray_buffercc/buffers_0_reg[2]/C
|
|
SLICE_X27Y78 FDCE (Prop_fdce_C_Q) 0.141 -0.441 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/popToPushGray_buffercc/buffers_0_reg[2]/Q
|
|
net (fo=1, routed) 0.056 -0.385 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/popToPushGray_buffercc/buffers_0[2]
|
|
SLICE_X27Y78 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/popToPushGray_buffercc/buffers_1_reg[2]/D
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock sys_clk rise edge) 0.000 0.000 r
|
|
clock source latency -1.947 -1.947
|
|
propagated clock network latency
|
|
1.593 -0.354
|
|
clock pessimism -0.228 -0.582
|
|
SLICE_X27Y78 FDCE (Hold_fdce_C_D) 0.076 -0.506 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/popToPushGray_buffercc/buffers_1_reg[2]
|
|
-------------------------------------------------------------------
|
|
required time 0.506
|
|
arrival time -0.385
|
|
-------------------------------------------------------------------
|
|
slack 0.121
|
|
|
|
Slack (MET) : 0.121ns (arrival time - required time)
|
|
Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/popToPushGray_buffercc/buffers_0_reg[2]/C
|
|
(rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/popToPushGray_buffercc/buffers_1_reg[2]/D
|
|
(rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Path Group: sys_clk
|
|
Path Type: Hold (Min at Fast Process Corner)
|
|
Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns)
|
|
Data Path Delay: 0.197ns (logic 0.141ns (71.611%) route 0.056ns (28.389%))
|
|
Logic Levels: 0
|
|
Clock Path Skew: 0.000ns (DCD - SCD - CPR)
|
|
Destination Clock Delay (DCD): -0.354ns
|
|
Source Clock Delay (SCD): -0.582ns
|
|
Clock Pessimism Removal (CPR): 0.228ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock sys_clk rise edge) 0.000 0.000 r
|
|
clock source latency -1.848 -1.848
|
|
propagated clock network latency
|
|
1.266 -0.582
|
|
SLICE_X27Y78 FDCE 0.000 -0.582 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/popToPushGray_buffercc/buffers_0_reg[2]/C
|
|
SLICE_X27Y78 FDCE (Prop_fdce_C_Q) 0.141 -0.441 f u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/popToPushGray_buffercc/buffers_0_reg[2]/Q
|
|
net (fo=1, routed) 0.056 -0.385 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/popToPushGray_buffercc/buffers_0[2]
|
|
SLICE_X27Y78 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/popToPushGray_buffercc/buffers_1_reg[2]/D
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock sys_clk rise edge) 0.000 0.000 r
|
|
clock source latency -1.947 -1.947
|
|
propagated clock network latency
|
|
1.593 -0.354
|
|
clock pessimism -0.228 -0.582
|
|
SLICE_X27Y78 FDCE (Hold_fdce_C_D) 0.076 -0.506 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/popToPushGray_buffercc/buffers_1_reg[2]
|
|
-------------------------------------------------------------------
|
|
required time 0.506
|
|
arrival time -0.385
|
|
-------------------------------------------------------------------
|
|
slack 0.121
|
|
|
|
Slack (MET) : 0.121ns (arrival time - required time)
|
|
Source: u_Axi_CDC/awFifo/popToPushGray_buffercc/buffers_0_reg[2]/C
|
|
(rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns})
|
|
Destination: u_Axi_CDC/awFifo/popToPushGray_buffercc/buffers_1_reg[2]/D
|
|
(rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns})
|
|
Path Group: cpu_clk
|
|
Path Type: Hold (Min at Fast Process Corner)
|
|
Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns)
|
|
Data Path Delay: 0.197ns (logic 0.141ns (71.611%) route 0.056ns (28.389%))
|
|
Logic Levels: 0
|
|
Clock Path Skew: 0.000ns (DCD - SCD - CPR)
|
|
Destination Clock Delay (DCD): -0.347ns
|
|
Source Clock Delay (SCD): -0.575ns
|
|
Clock Pessimism Removal (CPR): 0.228ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock cpu_clk rise edge) 0.000 0.000 r
|
|
clock source latency -1.848 -1.848
|
|
propagated clock network latency
|
|
1.273 -0.575
|
|
SLICE_X15Y69 FDCE 0.000 -0.575 r u_Axi_CDC/awFifo/popToPushGray_buffercc/buffers_0_reg[2]/C
|
|
SLICE_X15Y69 FDCE (Prop_fdce_C_Q) 0.141 -0.434 r u_Axi_CDC/awFifo/popToPushGray_buffercc/buffers_0_reg[2]/Q
|
|
net (fo=1, routed) 0.056 -0.378 u_Axi_CDC/awFifo/popToPushGray_buffercc/buffers_0[2]
|
|
SLICE_X15Y69 FDCE r u_Axi_CDC/awFifo/popToPushGray_buffercc/buffers_1_reg[2]/D
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock cpu_clk rise edge) 0.000 0.000 r
|
|
clock source latency -1.947 -1.947
|
|
propagated clock network latency
|
|
1.600 -0.347
|
|
clock pessimism -0.228 -0.575
|
|
SLICE_X15Y69 FDCE (Hold_fdce_C_D) 0.076 -0.499 u_Axi_CDC/awFifo/popToPushGray_buffercc/buffers_1_reg[2]
|
|
-------------------------------------------------------------------
|
|
required time 0.499
|
|
arrival time -0.378
|
|
-------------------------------------------------------------------
|
|
slack 0.121
|
|
|
|
Slack (MET) : 0.121ns (arrival time - required time)
|
|
Source: u_Axi_CDC/awFifo/popToPushGray_buffercc/buffers_0_reg[2]/C
|
|
(rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns})
|
|
Destination: u_Axi_CDC/awFifo/popToPushGray_buffercc/buffers_1_reg[2]/D
|
|
(rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns})
|
|
Path Group: cpu_clk
|
|
Path Type: Hold (Min at Fast Process Corner)
|
|
Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns)
|
|
Data Path Delay: 0.197ns (logic 0.141ns (71.611%) route 0.056ns (28.389%))
|
|
Logic Levels: 0
|
|
Clock Path Skew: 0.000ns (DCD - SCD - CPR)
|
|
Destination Clock Delay (DCD): -0.347ns
|
|
Source Clock Delay (SCD): -0.575ns
|
|
Clock Pessimism Removal (CPR): 0.228ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock cpu_clk rise edge) 0.000 0.000 r
|
|
clock source latency -1.848 -1.848
|
|
propagated clock network latency
|
|
1.273 -0.575
|
|
SLICE_X15Y69 FDCE 0.000 -0.575 r u_Axi_CDC/awFifo/popToPushGray_buffercc/buffers_0_reg[2]/C
|
|
SLICE_X15Y69 FDCE (Prop_fdce_C_Q) 0.141 -0.434 f u_Axi_CDC/awFifo/popToPushGray_buffercc/buffers_0_reg[2]/Q
|
|
net (fo=1, routed) 0.056 -0.378 u_Axi_CDC/awFifo/popToPushGray_buffercc/buffers_0[2]
|
|
SLICE_X15Y69 FDCE f u_Axi_CDC/awFifo/popToPushGray_buffercc/buffers_1_reg[2]/D
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock cpu_clk rise edge) 0.000 0.000 r
|
|
clock source latency -1.947 -1.947
|
|
propagated clock network latency
|
|
1.600 -0.347
|
|
clock pessimism -0.228 -0.575
|
|
SLICE_X15Y69 FDCE (Hold_fdce_C_D) 0.076 -0.499 u_Axi_CDC/awFifo/popToPushGray_buffercc/buffers_1_reg[2]
|
|
-------------------------------------------------------------------
|
|
required time 0.499
|
|
arrival time -0.378
|
|
-------------------------------------------------------------------
|
|
slack 0.121
|
|
|
|
Slack (MET) : 0.121ns (arrival time - required time)
|
|
Source: u_Axi_CDC/bFifo/pushToPopGray_buffercc/buffers_0_reg[2]/C
|
|
(rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns})
|
|
Destination: u_Axi_CDC/bFifo/pushToPopGray_buffercc/buffers_1_reg[2]/D
|
|
(rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns})
|
|
Path Group: cpu_clk
|
|
Path Type: Hold (Min at Fast Process Corner)
|
|
Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns)
|
|
Data Path Delay: 0.197ns (logic 0.141ns (71.611%) route 0.056ns (28.389%))
|
|
Logic Levels: 0
|
|
Clock Path Skew: 0.000ns (DCD - SCD - CPR)
|
|
Destination Clock Delay (DCD): -0.338ns
|
|
Source Clock Delay (SCD): -0.568ns
|
|
Clock Pessimism Removal (CPR): 0.230ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock cpu_clk rise edge) 0.000 0.000 r
|
|
clock source latency -1.848 -1.848
|
|
propagated clock network latency
|
|
1.280 -0.568
|
|
SLICE_X19Y59 FDCE 0.000 -0.568 r u_Axi_CDC/bFifo/pushToPopGray_buffercc/buffers_0_reg[2]/C
|
|
SLICE_X19Y59 FDCE (Prop_fdce_C_Q) 0.141 -0.427 r u_Axi_CDC/bFifo/pushToPopGray_buffercc/buffers_0_reg[2]/Q
|
|
net (fo=1, routed) 0.056 -0.371 u_Axi_CDC/bFifo/pushToPopGray_buffercc/buffers_0[2]
|
|
SLICE_X19Y59 FDCE r u_Axi_CDC/bFifo/pushToPopGray_buffercc/buffers_1_reg[2]/D
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock cpu_clk rise edge) 0.000 0.000 r
|
|
clock source latency -1.947 -1.947
|
|
propagated clock network latency
|
|
1.609 -0.338
|
|
clock pessimism -0.230 -0.568
|
|
SLICE_X19Y59 FDCE (Hold_fdce_C_D) 0.076 -0.492 u_Axi_CDC/bFifo/pushToPopGray_buffercc/buffers_1_reg[2]
|
|
-------------------------------------------------------------------
|
|
required time 0.492
|
|
arrival time -0.371
|
|
-------------------------------------------------------------------
|
|
slack 0.121
|
|
|
|
Slack (MET) : 0.121ns (arrival time - required time)
|
|
Source: u_Axi_CDC/bFifo/pushToPopGray_buffercc/buffers_0_reg[2]/C
|
|
(rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns})
|
|
Destination: u_Axi_CDC/bFifo/pushToPopGray_buffercc/buffers_1_reg[2]/D
|
|
(rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns})
|
|
Path Group: cpu_clk
|
|
Path Type: Hold (Min at Fast Process Corner)
|
|
Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns)
|
|
Data Path Delay: 0.197ns (logic 0.141ns (71.611%) route 0.056ns (28.389%))
|
|
Logic Levels: 0
|
|
Clock Path Skew: 0.000ns (DCD - SCD - CPR)
|
|
Destination Clock Delay (DCD): -0.338ns
|
|
Source Clock Delay (SCD): -0.568ns
|
|
Clock Pessimism Removal (CPR): 0.230ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock cpu_clk rise edge) 0.000 0.000 r
|
|
clock source latency -1.848 -1.848
|
|
propagated clock network latency
|
|
1.280 -0.568
|
|
SLICE_X19Y59 FDCE 0.000 -0.568 r u_Axi_CDC/bFifo/pushToPopGray_buffercc/buffers_0_reg[2]/C
|
|
SLICE_X19Y59 FDCE (Prop_fdce_C_Q) 0.141 -0.427 f u_Axi_CDC/bFifo/pushToPopGray_buffercc/buffers_0_reg[2]/Q
|
|
net (fo=1, routed) 0.056 -0.371 u_Axi_CDC/bFifo/pushToPopGray_buffercc/buffers_0[2]
|
|
SLICE_X19Y59 FDCE f u_Axi_CDC/bFifo/pushToPopGray_buffercc/buffers_1_reg[2]/D
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock cpu_clk rise edge) 0.000 0.000 r
|
|
clock source latency -1.947 -1.947
|
|
propagated clock network latency
|
|
1.609 -0.338
|
|
clock pessimism -0.230 -0.568
|
|
SLICE_X19Y59 FDCE (Hold_fdce_C_D) 0.076 -0.492 u_Axi_CDC/bFifo/pushToPopGray_buffercc/buffers_1_reg[2]
|
|
-------------------------------------------------------------------
|
|
required time 0.492
|
|
arrival time -0.371
|
|
-------------------------------------------------------------------
|
|
slack 0.121
|
|
|
|
Slack (MET) : 0.121ns (arrival time - required time)
|
|
Source: u_Axi_CDC/rFifo/pushToPopGray_buffercc/buffers_0_reg[2]/C
|
|
(rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns})
|
|
Destination: u_Axi_CDC/rFifo/pushToPopGray_buffercc/buffers_1_reg[2]/D
|
|
(rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns})
|
|
Path Group: cpu_clk
|
|
Path Type: Hold (Min at Fast Process Corner)
|
|
Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns)
|
|
Data Path Delay: 0.197ns (logic 0.141ns (71.611%) route 0.056ns (28.389%))
|
|
Logic Levels: 0
|
|
Clock Path Skew: 0.000ns (DCD - SCD - CPR)
|
|
Destination Clock Delay (DCD): -0.323ns
|
|
Source Clock Delay (SCD): -0.552ns
|
|
Clock Pessimism Removal (CPR): 0.229ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock cpu_clk rise edge) 0.000 0.000 r
|
|
clock source latency -1.848 -1.848
|
|
propagated clock network latency
|
|
1.296 -0.552
|
|
SLICE_X5Y76 FDCE 0.000 -0.552 r u_Axi_CDC/rFifo/pushToPopGray_buffercc/buffers_0_reg[2]/C
|
|
SLICE_X5Y76 FDCE (Prop_fdce_C_Q) 0.141 -0.411 r u_Axi_CDC/rFifo/pushToPopGray_buffercc/buffers_0_reg[2]/Q
|
|
net (fo=1, routed) 0.056 -0.355 u_Axi_CDC/rFifo/pushToPopGray_buffercc/buffers_0[2]
|
|
SLICE_X5Y76 FDCE r u_Axi_CDC/rFifo/pushToPopGray_buffercc/buffers_1_reg[2]/D
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock cpu_clk rise edge) 0.000 0.000 r
|
|
clock source latency -1.947 -1.947
|
|
propagated clock network latency
|
|
1.624 -0.323
|
|
clock pessimism -0.229 -0.552
|
|
SLICE_X5Y76 FDCE (Hold_fdce_C_D) 0.076 -0.476 u_Axi_CDC/rFifo/pushToPopGray_buffercc/buffers_1_reg[2]
|
|
-------------------------------------------------------------------
|
|
required time 0.476
|
|
arrival time -0.355
|
|
-------------------------------------------------------------------
|
|
slack 0.121
|
|
|
|
Slack (MET) : 0.121ns (arrival time - required time)
|
|
Source: u_Axi_CDC/rFifo/pushToPopGray_buffercc/buffers_0_reg[2]/C
|
|
(rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns})
|
|
Destination: u_Axi_CDC/rFifo/pushToPopGray_buffercc/buffers_1_reg[2]/D
|
|
(rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns})
|
|
Path Group: cpu_clk
|
|
Path Type: Hold (Min at Fast Process Corner)
|
|
Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns)
|
|
Data Path Delay: 0.197ns (logic 0.141ns (71.611%) route 0.056ns (28.389%))
|
|
Logic Levels: 0
|
|
Clock Path Skew: 0.000ns (DCD - SCD - CPR)
|
|
Destination Clock Delay (DCD): -0.323ns
|
|
Source Clock Delay (SCD): -0.552ns
|
|
Clock Pessimism Removal (CPR): 0.229ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock cpu_clk rise edge) 0.000 0.000 r
|
|
clock source latency -1.848 -1.848
|
|
propagated clock network latency
|
|
1.296 -0.552
|
|
SLICE_X5Y76 FDCE 0.000 -0.552 r u_Axi_CDC/rFifo/pushToPopGray_buffercc/buffers_0_reg[2]/C
|
|
SLICE_X5Y76 FDCE (Prop_fdce_C_Q) 0.141 -0.411 f u_Axi_CDC/rFifo/pushToPopGray_buffercc/buffers_0_reg[2]/Q
|
|
net (fo=1, routed) 0.056 -0.355 u_Axi_CDC/rFifo/pushToPopGray_buffercc/buffers_0[2]
|
|
SLICE_X5Y76 FDCE f u_Axi_CDC/rFifo/pushToPopGray_buffercc/buffers_1_reg[2]/D
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock cpu_clk rise edge) 0.000 0.000 r
|
|
clock source latency -1.947 -1.947
|
|
propagated clock network latency
|
|
1.624 -0.323
|
|
clock pessimism -0.229 -0.552
|
|
SLICE_X5Y76 FDCE (Hold_fdce_C_D) 0.076 -0.476 u_Axi_CDC/rFifo/pushToPopGray_buffercc/buffers_1_reg[2]
|
|
-------------------------------------------------------------------
|
|
required time 0.476
|
|
arrival time -0.355
|
|
-------------------------------------------------------------------
|
|
slack 0.121
|
|
|
|
Slack (MET) : 0.121ns (arrival time - required time)
|
|
Source: u_cpu/u_csr/csr_tlbelo0_reg[10]/C
|
|
(rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns})
|
|
Destination: u_cpu/addr_trans/tlb_entry/tlb_ppn0_reg_r3_0_31_0_5/RAMB/I
|
|
(rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns})
|
|
Path Group: cpu_clk
|
|
Path Type: Hold (Min at Fast Process Corner)
|
|
Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns)
|
|
Data Path Delay: 0.281ns (logic 0.141ns (50.124%) route 0.140ns (49.876%))
|
|
Logic Levels: 0
|
|
Clock Path Skew: 0.014ns (DCD - SCD - CPR)
|
|
Destination Clock Delay (DCD): -0.309ns
|
|
Source Clock Delay (SCD): -0.540ns
|
|
Clock Pessimism Removal (CPR): 0.217ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock cpu_clk rise edge) 0.000 0.000 r
|
|
clock source latency -1.848 -1.848
|
|
propagated clock network latency
|
|
1.309 -0.540
|
|
SLICE_X45Y36 FDRE 0.000 -0.540 r u_cpu/u_csr/csr_tlbelo0_reg[10]/C
|
|
SLICE_X45Y36 FDRE (Prop_fdre_C_Q) 0.141 -0.399 r u_cpu/u_csr/csr_tlbelo0_reg[10]/Q
|
|
net (fo=4, routed) 0.140 -0.258 u_cpu/addr_trans/tlb_entry/tlb_ppn0_reg_r3_0_31_0_5/DIB0
|
|
SLICE_X44Y34 RAMD32 r u_cpu/addr_trans/tlb_entry/tlb_ppn0_reg_r3_0_31_0_5/RAMB/I
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock cpu_clk rise edge) 0.000 0.000 r
|
|
clock source latency -1.947 -1.947
|
|
propagated clock network latency
|
|
1.638 -0.309
|
|
clock pessimism -0.217 -0.526
|
|
SLICE_X44Y34 RAMD32 (Hold_ramd32_CLK_I)
|
|
0.146 -0.380 u_cpu/addr_trans/tlb_entry/tlb_ppn0_reg_r3_0_31_0_5/RAMB
|
|
-------------------------------------------------------------------
|
|
required time 0.380
|
|
arrival time -0.258
|
|
-------------------------------------------------------------------
|
|
slack 0.121
|
|
|
|
Slack (MET) : 0.121ns (arrival time - required time)
|
|
Source: u_cpu/u_csr/csr_tlbelo0_reg[10]/C
|
|
(rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns})
|
|
Destination: u_cpu/addr_trans/tlb_entry/tlb_ppn0_reg_r3_0_31_0_5/RAMB/I
|
|
(rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns})
|
|
Path Group: cpu_clk
|
|
Path Type: Hold (Min at Fast Process Corner)
|
|
Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns)
|
|
Data Path Delay: 0.281ns (logic 0.141ns (50.124%) route 0.140ns (49.876%))
|
|
Logic Levels: 0
|
|
Clock Path Skew: 0.014ns (DCD - SCD - CPR)
|
|
Destination Clock Delay (DCD): -0.309ns
|
|
Source Clock Delay (SCD): -0.540ns
|
|
Clock Pessimism Removal (CPR): 0.217ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock cpu_clk rise edge) 0.000 0.000 r
|
|
clock source latency -1.848 -1.848
|
|
propagated clock network latency
|
|
1.309 -0.540
|
|
SLICE_X45Y36 FDRE 0.000 -0.540 r u_cpu/u_csr/csr_tlbelo0_reg[10]/C
|
|
SLICE_X45Y36 FDRE (Prop_fdre_C_Q) 0.141 -0.399 f u_cpu/u_csr/csr_tlbelo0_reg[10]/Q
|
|
net (fo=4, routed) 0.140 -0.258 u_cpu/addr_trans/tlb_entry/tlb_ppn0_reg_r3_0_31_0_5/DIB0
|
|
SLICE_X44Y34 RAMD32 f u_cpu/addr_trans/tlb_entry/tlb_ppn0_reg_r3_0_31_0_5/RAMB/I
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock cpu_clk rise edge) 0.000 0.000 r
|
|
clock source latency -1.947 -1.947
|
|
propagated clock network latency
|
|
1.638 -0.309
|
|
clock pessimism -0.217 -0.526
|
|
SLICE_X44Y34 RAMD32 (Hold_ramd32_CLK_I)
|
|
0.146 -0.380 u_cpu/addr_trans/tlb_entry/tlb_ppn0_reg_r3_0_31_0_5/RAMB
|
|
-------------------------------------------------------------------
|
|
required time 0.380
|
|
arrival time -0.258
|
|
-------------------------------------------------------------------
|
|
slack 0.121
|
|
|
|
Slack (MET) : 0.122ns (arrival time - required time)
|
|
Source: u_Axi_CDC/arFifo/pushToPopGray_buffercc/buffers_0_reg[0]/C
|
|
(rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Destination: u_Axi_CDC/arFifo/pushToPopGray_buffercc/buffers_1_reg[0]/D
|
|
(rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Path Group: sys_clk
|
|
Path Type: Hold (Min at Fast Process Corner)
|
|
Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns)
|
|
Data Path Delay: 0.197ns (logic 0.141ns (71.611%) route 0.056ns (28.389%))
|
|
Logic Levels: 0
|
|
Clock Path Skew: 0.000ns (DCD - SCD - CPR)
|
|
Destination Clock Delay (DCD): -0.344ns
|
|
Source Clock Delay (SCD): -0.572ns
|
|
Clock Pessimism Removal (CPR): 0.228ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock sys_clk rise edge) 0.000 0.000 r
|
|
clock source latency -1.848 -1.848
|
|
propagated clock network latency
|
|
1.276 -0.572
|
|
SLICE_X15Y66 FDCE 0.000 -0.572 r u_Axi_CDC/arFifo/pushToPopGray_buffercc/buffers_0_reg[0]/C
|
|
SLICE_X15Y66 FDCE (Prop_fdce_C_Q) 0.141 -0.431 r u_Axi_CDC/arFifo/pushToPopGray_buffercc/buffers_0_reg[0]/Q
|
|
net (fo=1, routed) 0.056 -0.375 u_Axi_CDC/arFifo/pushToPopGray_buffercc/buffers_0[0]
|
|
SLICE_X15Y66 FDCE r u_Axi_CDC/arFifo/pushToPopGray_buffercc/buffers_1_reg[0]/D
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock sys_clk rise edge) 0.000 0.000 r
|
|
clock source latency -1.947 -1.947
|
|
propagated clock network latency
|
|
1.603 -0.344
|
|
clock pessimism -0.228 -0.572
|
|
SLICE_X15Y66 FDCE (Hold_fdce_C_D) 0.075 -0.497 u_Axi_CDC/arFifo/pushToPopGray_buffercc/buffers_1_reg[0]
|
|
-------------------------------------------------------------------
|
|
required time 0.497
|
|
arrival time -0.375
|
|
-------------------------------------------------------------------
|
|
slack 0.122
|
|
|
|
Slack (MET) : 0.122ns (arrival time - required time)
|
|
Source: u_Axi_CDC/arFifo/pushToPopGray_buffercc/buffers_0_reg[0]/C
|
|
(rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Destination: u_Axi_CDC/arFifo/pushToPopGray_buffercc/buffers_1_reg[0]/D
|
|
(rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Path Group: sys_clk
|
|
Path Type: Hold (Min at Fast Process Corner)
|
|
Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns)
|
|
Data Path Delay: 0.197ns (logic 0.141ns (71.611%) route 0.056ns (28.389%))
|
|
Logic Levels: 0
|
|
Clock Path Skew: 0.000ns (DCD - SCD - CPR)
|
|
Destination Clock Delay (DCD): -0.344ns
|
|
Source Clock Delay (SCD): -0.572ns
|
|
Clock Pessimism Removal (CPR): 0.228ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock sys_clk rise edge) 0.000 0.000 r
|
|
clock source latency -1.848 -1.848
|
|
propagated clock network latency
|
|
1.276 -0.572
|
|
SLICE_X15Y66 FDCE 0.000 -0.572 r u_Axi_CDC/arFifo/pushToPopGray_buffercc/buffers_0_reg[0]/C
|
|
SLICE_X15Y66 FDCE (Prop_fdce_C_Q) 0.141 -0.431 f u_Axi_CDC/arFifo/pushToPopGray_buffercc/buffers_0_reg[0]/Q
|
|
net (fo=1, routed) 0.056 -0.375 u_Axi_CDC/arFifo/pushToPopGray_buffercc/buffers_0[0]
|
|
SLICE_X15Y66 FDCE f u_Axi_CDC/arFifo/pushToPopGray_buffercc/buffers_1_reg[0]/D
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock sys_clk rise edge) 0.000 0.000 r
|
|
clock source latency -1.947 -1.947
|
|
propagated clock network latency
|
|
1.603 -0.344
|
|
clock pessimism -0.228 -0.572
|
|
SLICE_X15Y66 FDCE (Hold_fdce_C_D) 0.075 -0.497 u_Axi_CDC/arFifo/pushToPopGray_buffercc/buffers_1_reg[0]
|
|
-------------------------------------------------------------------
|
|
required time 0.497
|
|
arrival time -0.375
|
|
-------------------------------------------------------------------
|
|
slack 0.122
|
|
|
|
Slack (MET) : 0.122ns (arrival time - required time)
|
|
Source: u_Axi_CDC/awFifo/bufferCC_12/buffers_0_reg/C
|
|
(rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Destination: u_Axi_CDC/awFifo/bufferCC_12/buffers_1_reg/D
|
|
(rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Path Group: sys_clk
|
|
Path Type: Hold (Min at Fast Process Corner)
|
|
Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns)
|
|
Data Path Delay: 0.197ns (logic 0.141ns (71.611%) route 0.056ns (28.389%))
|
|
Logic Levels: 0
|
|
Clock Path Skew: 0.000ns (DCD - SCD - CPR)
|
|
Destination Clock Delay (DCD): -0.309ns
|
|
Source Clock Delay (SCD): -0.541ns
|
|
Clock Pessimism Removal (CPR): 0.232ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock sys_clk rise edge) 0.000 0.000 r
|
|
clock source latency -1.848 -1.848
|
|
propagated clock network latency
|
|
1.307 -0.541
|
|
SLICE_X7Y59 FDCE 0.000 -0.541 r u_Axi_CDC/awFifo/bufferCC_12/buffers_0_reg/C
|
|
SLICE_X7Y59 FDCE (Prop_fdce_C_Q) 0.141 -0.400 r u_Axi_CDC/awFifo/bufferCC_12/buffers_0_reg/Q
|
|
net (fo=1, routed) 0.056 -0.344 u_Axi_CDC/awFifo/bufferCC_12/buffers_0
|
|
SLICE_X7Y59 FDCE r u_Axi_CDC/awFifo/bufferCC_12/buffers_1_reg/D
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock sys_clk rise edge) 0.000 0.000 r
|
|
clock source latency -1.947 -1.947
|
|
propagated clock network latency
|
|
1.638 -0.309
|
|
clock pessimism -0.232 -0.541
|
|
SLICE_X7Y59 FDCE (Hold_fdce_C_D) 0.075 -0.466 u_Axi_CDC/awFifo/bufferCC_12/buffers_1_reg
|
|
-------------------------------------------------------------------
|
|
required time 0.466
|
|
arrival time -0.344
|
|
-------------------------------------------------------------------
|
|
slack 0.122
|
|
|
|
Slack (MET) : 0.122ns (arrival time - required time)
|
|
Source: u_Axi_CDC/awFifo/bufferCC_12/buffers_0_reg/C
|
|
(rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Destination: u_Axi_CDC/awFifo/bufferCC_12/buffers_1_reg/D
|
|
(rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Path Group: sys_clk
|
|
Path Type: Hold (Min at Fast Process Corner)
|
|
Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns)
|
|
Data Path Delay: 0.197ns (logic 0.141ns (71.611%) route 0.056ns (28.389%))
|
|
Logic Levels: 0
|
|
Clock Path Skew: 0.000ns (DCD - SCD - CPR)
|
|
Destination Clock Delay (DCD): -0.309ns
|
|
Source Clock Delay (SCD): -0.541ns
|
|
Clock Pessimism Removal (CPR): 0.232ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock sys_clk rise edge) 0.000 0.000 r
|
|
clock source latency -1.848 -1.848
|
|
propagated clock network latency
|
|
1.307 -0.541
|
|
SLICE_X7Y59 FDCE 0.000 -0.541 r u_Axi_CDC/awFifo/bufferCC_12/buffers_0_reg/C
|
|
SLICE_X7Y59 FDCE (Prop_fdce_C_Q) 0.141 -0.400 f u_Axi_CDC/awFifo/bufferCC_12/buffers_0_reg/Q
|
|
net (fo=1, routed) 0.056 -0.344 u_Axi_CDC/awFifo/bufferCC_12/buffers_0
|
|
SLICE_X7Y59 FDCE f u_Axi_CDC/awFifo/bufferCC_12/buffers_1_reg/D
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock sys_clk rise edge) 0.000 0.000 r
|
|
clock source latency -1.947 -1.947
|
|
propagated clock network latency
|
|
1.638 -0.309
|
|
clock pessimism -0.232 -0.541
|
|
SLICE_X7Y59 FDCE (Hold_fdce_C_D) 0.075 -0.466 u_Axi_CDC/awFifo/bufferCC_12/buffers_1_reg
|
|
-------------------------------------------------------------------
|
|
required time 0.466
|
|
arrival time -0.344
|
|
-------------------------------------------------------------------
|
|
slack 0.122
|
|
|
|
Slack (MET) : 0.122ns (arrival time - required time)
|
|
Source: u_Axi_CDC/bFifo/popToPushGray_buffercc/buffers_0_reg[0]/C
|
|
(rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Destination: u_Axi_CDC/bFifo/popToPushGray_buffercc/buffers_1_reg[0]/D
|
|
(rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Path Group: sys_clk
|
|
Path Type: Hold (Min at Fast Process Corner)
|
|
Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns)
|
|
Data Path Delay: 0.197ns (logic 0.141ns (71.611%) route 0.056ns (28.389%))
|
|
Logic Levels: 0
|
|
Clock Path Skew: 0.000ns (DCD - SCD - CPR)
|
|
Destination Clock Delay (DCD): -0.338ns
|
|
Source Clock Delay (SCD): -0.568ns
|
|
Clock Pessimism Removal (CPR): 0.230ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock sys_clk rise edge) 0.000 0.000 r
|
|
clock source latency -1.848 -1.848
|
|
propagated clock network latency
|
|
1.280 -0.568
|
|
SLICE_X17Y59 FDCE 0.000 -0.568 r u_Axi_CDC/bFifo/popToPushGray_buffercc/buffers_0_reg[0]/C
|
|
SLICE_X17Y59 FDCE (Prop_fdce_C_Q) 0.141 -0.427 r u_Axi_CDC/bFifo/popToPushGray_buffercc/buffers_0_reg[0]/Q
|
|
net (fo=1, routed) 0.056 -0.371 u_Axi_CDC/bFifo/popToPushGray_buffercc/buffers_0[0]
|
|
SLICE_X17Y59 FDCE r u_Axi_CDC/bFifo/popToPushGray_buffercc/buffers_1_reg[0]/D
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock sys_clk rise edge) 0.000 0.000 r
|
|
clock source latency -1.947 -1.947
|
|
propagated clock network latency
|
|
1.609 -0.338
|
|
clock pessimism -0.230 -0.568
|
|
SLICE_X17Y59 FDCE (Hold_fdce_C_D) 0.075 -0.493 u_Axi_CDC/bFifo/popToPushGray_buffercc/buffers_1_reg[0]
|
|
-------------------------------------------------------------------
|
|
required time 0.493
|
|
arrival time -0.371
|
|
-------------------------------------------------------------------
|
|
slack 0.122
|
|
|
|
Slack (MET) : 0.122ns (arrival time - required time)
|
|
Source: u_Axi_CDC/bFifo/popToPushGray_buffercc/buffers_0_reg[0]/C
|
|
(rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Destination: u_Axi_CDC/bFifo/popToPushGray_buffercc/buffers_1_reg[0]/D
|
|
(rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Path Group: sys_clk
|
|
Path Type: Hold (Min at Fast Process Corner)
|
|
Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns)
|
|
Data Path Delay: 0.197ns (logic 0.141ns (71.611%) route 0.056ns (28.389%))
|
|
Logic Levels: 0
|
|
Clock Path Skew: 0.000ns (DCD - SCD - CPR)
|
|
Destination Clock Delay (DCD): -0.338ns
|
|
Source Clock Delay (SCD): -0.568ns
|
|
Clock Pessimism Removal (CPR): 0.230ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock sys_clk rise edge) 0.000 0.000 r
|
|
clock source latency -1.848 -1.848
|
|
propagated clock network latency
|
|
1.280 -0.568
|
|
SLICE_X17Y59 FDCE 0.000 -0.568 r u_Axi_CDC/bFifo/popToPushGray_buffercc/buffers_0_reg[0]/C
|
|
SLICE_X17Y59 FDCE (Prop_fdce_C_Q) 0.141 -0.427 f u_Axi_CDC/bFifo/popToPushGray_buffercc/buffers_0_reg[0]/Q
|
|
net (fo=1, routed) 0.056 -0.371 u_Axi_CDC/bFifo/popToPushGray_buffercc/buffers_0[0]
|
|
SLICE_X17Y59 FDCE f u_Axi_CDC/bFifo/popToPushGray_buffercc/buffers_1_reg[0]/D
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock sys_clk rise edge) 0.000 0.000 r
|
|
clock source latency -1.947 -1.947
|
|
propagated clock network latency
|
|
1.609 -0.338
|
|
clock pessimism -0.230 -0.568
|
|
SLICE_X17Y59 FDCE (Hold_fdce_C_D) 0.075 -0.493 u_Axi_CDC/bFifo/popToPushGray_buffercc/buffers_1_reg[0]
|
|
-------------------------------------------------------------------
|
|
required time 0.493
|
|
arrival time -0.371
|
|
-------------------------------------------------------------------
|
|
slack 0.122
|
|
|
|
Slack (MET) : 0.122ns (arrival time - required time)
|
|
Source: u_axi_uart_controller/uart0/regs/i_uart_sync_flops/flop_0_reg[0]/C
|
|
(rising edge-triggered cell FDSE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Destination: u_axi_uart_controller/uart0/regs/i_uart_sync_flops/sync_dat_o_reg[0]/D
|
|
(rising edge-triggered cell FDSE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Path Group: sys_clk
|
|
Path Type: Hold (Min at Fast Process Corner)
|
|
Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns)
|
|
Data Path Delay: 0.197ns (logic 0.141ns (71.611%) route 0.056ns (28.389%))
|
|
Logic Levels: 0
|
|
Clock Path Skew: 0.000ns (DCD - SCD - CPR)
|
|
Destination Clock Delay (DCD): -0.308ns
|
|
Source Clock Delay (SCD): -0.539ns
|
|
Clock Pessimism Removal (CPR): 0.231ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock sys_clk rise edge) 0.000 0.000 r
|
|
clock source latency -1.848 -1.848
|
|
propagated clock network latency
|
|
1.309 -0.539
|
|
SLICE_X1Y61 FDSE 0.000 -0.539 r u_axi_uart_controller/uart0/regs/i_uart_sync_flops/flop_0_reg[0]/C
|
|
SLICE_X1Y61 FDSE (Prop_fdse_C_Q) 0.141 -0.398 r u_axi_uart_controller/uart0/regs/i_uart_sync_flops/flop_0_reg[0]/Q
|
|
net (fo=1, routed) 0.056 -0.342 u_axi_uart_controller/uart0/regs/i_uart_sync_flops/flop_0
|
|
SLICE_X1Y61 FDSE r u_axi_uart_controller/uart0/regs/i_uart_sync_flops/sync_dat_o_reg[0]/D
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock sys_clk rise edge) 0.000 0.000 r
|
|
clock source latency -1.947 -1.947
|
|
propagated clock network latency
|
|
1.639 -0.308
|
|
clock pessimism -0.231 -0.539
|
|
SLICE_X1Y61 FDSE (Hold_fdse_C_D) 0.075 -0.464 u_axi_uart_controller/uart0/regs/i_uart_sync_flops/sync_dat_o_reg[0]
|
|
-------------------------------------------------------------------
|
|
required time 0.464
|
|
arrival time -0.342
|
|
-------------------------------------------------------------------
|
|
slack 0.122
|
|
|
|
Slack (MET) : 0.122ns (arrival time - required time)
|
|
Source: u_axi_uart_controller/uart0/regs/i_uart_sync_flops/flop_0_reg[0]/C
|
|
(rising edge-triggered cell FDSE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Destination: u_axi_uart_controller/uart0/regs/i_uart_sync_flops/sync_dat_o_reg[0]/D
|
|
(rising edge-triggered cell FDSE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Path Group: sys_clk
|
|
Path Type: Hold (Min at Fast Process Corner)
|
|
Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns)
|
|
Data Path Delay: 0.197ns (logic 0.141ns (71.611%) route 0.056ns (28.389%))
|
|
Logic Levels: 0
|
|
Clock Path Skew: 0.000ns (DCD - SCD - CPR)
|
|
Destination Clock Delay (DCD): -0.308ns
|
|
Source Clock Delay (SCD): -0.539ns
|
|
Clock Pessimism Removal (CPR): 0.231ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock sys_clk rise edge) 0.000 0.000 r
|
|
clock source latency -1.848 -1.848
|
|
propagated clock network latency
|
|
1.309 -0.539
|
|
SLICE_X1Y61 FDSE 0.000 -0.539 r u_axi_uart_controller/uart0/regs/i_uart_sync_flops/flop_0_reg[0]/C
|
|
SLICE_X1Y61 FDSE (Prop_fdse_C_Q) 0.141 -0.398 f u_axi_uart_controller/uart0/regs/i_uart_sync_flops/flop_0_reg[0]/Q
|
|
net (fo=1, routed) 0.056 -0.342 u_axi_uart_controller/uart0/regs/i_uart_sync_flops/flop_0
|
|
SLICE_X1Y61 FDSE f u_axi_uart_controller/uart0/regs/i_uart_sync_flops/sync_dat_o_reg[0]/D
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock sys_clk rise edge) 0.000 0.000 r
|
|
clock source latency -1.947 -1.947
|
|
propagated clock network latency
|
|
1.639 -0.308
|
|
clock pessimism -0.231 -0.539
|
|
SLICE_X1Y61 FDSE (Hold_fdse_C_D) 0.075 -0.464 u_axi_uart_controller/uart0/regs/i_uart_sync_flops/sync_dat_o_reg[0]
|
|
-------------------------------------------------------------------
|
|
required time 0.464
|
|
arrival time -0.342
|
|
-------------------------------------------------------------------
|
|
slack 0.122
|
|
|
|
Slack (MET) : 0.122ns (arrival time - required time)
|
|
Source: u_fft_mlkem_axi_slave/mlkem_intr_sync_reg[0]/C
|
|
(rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Destination: u_fft_mlkem_axi_slave/mlkem_intr_sync_reg[1]/D
|
|
(rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Path Group: sys_clk
|
|
Path Type: Hold (Min at Fast Process Corner)
|
|
Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns)
|
|
Data Path Delay: 0.197ns (logic 0.141ns (71.611%) route 0.056ns (28.389%))
|
|
Logic Levels: 0
|
|
Clock Path Skew: 0.000ns (DCD - SCD - CPR)
|
|
Destination Clock Delay (DCD): -0.374ns
|
|
Source Clock Delay (SCD): -0.603ns
|
|
Clock Pessimism Removal (CPR): 0.229ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock sys_clk rise edge) 0.000 0.000 r
|
|
clock source latency -1.848 -1.848
|
|
propagated clock network latency
|
|
1.245 -0.603
|
|
SLICE_X117Y61 FDCE 0.000 -0.603 r u_fft_mlkem_axi_slave/mlkem_intr_sync_reg[0]/C
|
|
SLICE_X117Y61 FDCE (Prop_fdce_C_Q) 0.141 -0.462 r u_fft_mlkem_axi_slave/mlkem_intr_sync_reg[0]/Q
|
|
net (fo=1, routed) 0.056 -0.406 u_fft_mlkem_axi_slave/mlkem_intr_sync[0]
|
|
SLICE_X117Y61 FDCE r u_fft_mlkem_axi_slave/mlkem_intr_sync_reg[1]/D
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock sys_clk rise edge) 0.000 0.000 r
|
|
clock source latency -1.947 -1.947
|
|
propagated clock network latency
|
|
1.573 -0.374
|
|
clock pessimism -0.229 -0.603
|
|
SLICE_X117Y61 FDCE (Hold_fdce_C_D) 0.075 -0.528 u_fft_mlkem_axi_slave/mlkem_intr_sync_reg[1]
|
|
-------------------------------------------------------------------
|
|
required time 0.528
|
|
arrival time -0.406
|
|
-------------------------------------------------------------------
|
|
slack 0.122
|
|
|
|
Slack (MET) : 0.122ns (arrival time - required time)
|
|
Source: u_fft_mlkem_axi_slave/mlkem_intr_sync_reg[0]/C
|
|
(rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Destination: u_fft_mlkem_axi_slave/mlkem_intr_sync_reg[1]/D
|
|
(rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Path Group: sys_clk
|
|
Path Type: Hold (Min at Fast Process Corner)
|
|
Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns)
|
|
Data Path Delay: 0.197ns (logic 0.141ns (71.611%) route 0.056ns (28.389%))
|
|
Logic Levels: 0
|
|
Clock Path Skew: 0.000ns (DCD - SCD - CPR)
|
|
Destination Clock Delay (DCD): -0.374ns
|
|
Source Clock Delay (SCD): -0.603ns
|
|
Clock Pessimism Removal (CPR): 0.229ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock sys_clk rise edge) 0.000 0.000 r
|
|
clock source latency -1.848 -1.848
|
|
propagated clock network latency
|
|
1.245 -0.603
|
|
SLICE_X117Y61 FDCE 0.000 -0.603 r u_fft_mlkem_axi_slave/mlkem_intr_sync_reg[0]/C
|
|
SLICE_X117Y61 FDCE (Prop_fdce_C_Q) 0.141 -0.462 f u_fft_mlkem_axi_slave/mlkem_intr_sync_reg[0]/Q
|
|
net (fo=1, routed) 0.056 -0.406 u_fft_mlkem_axi_slave/mlkem_intr_sync[0]
|
|
SLICE_X117Y61 FDCE f u_fft_mlkem_axi_slave/mlkem_intr_sync_reg[1]/D
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock sys_clk rise edge) 0.000 0.000 r
|
|
clock source latency -1.947 -1.947
|
|
propagated clock network latency
|
|
1.573 -0.374
|
|
clock pessimism -0.229 -0.603
|
|
SLICE_X117Y61 FDCE (Hold_fdce_C_D) 0.075 -0.528 u_fft_mlkem_axi_slave/mlkem_intr_sync_reg[1]
|
|
-------------------------------------------------------------------
|
|
required time 0.528
|
|
arrival time -0.406
|
|
-------------------------------------------------------------------
|
|
slack 0.122
|
|
|
|
Slack (MET) : 0.122ns (arrival time - required time)
|
|
Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/popToPushGray_buffercc/buffers_0_reg[0]/C
|
|
(rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/popToPushGray_buffercc/buffers_1_reg[0]/D
|
|
(rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Path Group: sys_clk
|
|
Path Type: Hold (Min at Fast Process Corner)
|
|
Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns)
|
|
Data Path Delay: 0.197ns (logic 0.141ns (71.611%) route 0.056ns (28.389%))
|
|
Logic Levels: 0
|
|
Clock Path Skew: 0.000ns (DCD - SCD - CPR)
|
|
Destination Clock Delay (DCD): -0.354ns
|
|
Source Clock Delay (SCD): -0.582ns
|
|
Clock Pessimism Removal (CPR): 0.228ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock sys_clk rise edge) 0.000 0.000 r
|
|
clock source latency -1.848 -1.848
|
|
propagated clock network latency
|
|
1.266 -0.582
|
|
SLICE_X27Y78 FDCE 0.000 -0.582 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/popToPushGray_buffercc/buffers_0_reg[0]/C
|
|
SLICE_X27Y78 FDCE (Prop_fdce_C_Q) 0.141 -0.441 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/popToPushGray_buffercc/buffers_0_reg[0]/Q
|
|
net (fo=1, routed) 0.056 -0.385 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/popToPushGray_buffercc/buffers_0[0]
|
|
SLICE_X27Y78 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/popToPushGray_buffercc/buffers_1_reg[0]/D
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock sys_clk rise edge) 0.000 0.000 r
|
|
clock source latency -1.947 -1.947
|
|
propagated clock network latency
|
|
1.593 -0.354
|
|
clock pessimism -0.228 -0.582
|
|
SLICE_X27Y78 FDCE (Hold_fdce_C_D) 0.075 -0.507 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/popToPushGray_buffercc/buffers_1_reg[0]
|
|
-------------------------------------------------------------------
|
|
required time 0.507
|
|
arrival time -0.385
|
|
-------------------------------------------------------------------
|
|
slack 0.122
|
|
|
|
Slack (MET) : 0.122ns (arrival time - required time)
|
|
Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/popToPushGray_buffercc/buffers_0_reg[0]/C
|
|
(rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/popToPushGray_buffercc/buffers_1_reg[0]/D
|
|
(rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Path Group: sys_clk
|
|
Path Type: Hold (Min at Fast Process Corner)
|
|
Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns)
|
|
Data Path Delay: 0.197ns (logic 0.141ns (71.611%) route 0.056ns (28.389%))
|
|
Logic Levels: 0
|
|
Clock Path Skew: 0.000ns (DCD - SCD - CPR)
|
|
Destination Clock Delay (DCD): -0.354ns
|
|
Source Clock Delay (SCD): -0.582ns
|
|
Clock Pessimism Removal (CPR): 0.228ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock sys_clk rise edge) 0.000 0.000 r
|
|
clock source latency -1.848 -1.848
|
|
propagated clock network latency
|
|
1.266 -0.582
|
|
SLICE_X27Y78 FDCE 0.000 -0.582 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/popToPushGray_buffercc/buffers_0_reg[0]/C
|
|
SLICE_X27Y78 FDCE (Prop_fdce_C_Q) 0.141 -0.441 f u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/popToPushGray_buffercc/buffers_0_reg[0]/Q
|
|
net (fo=1, routed) 0.056 -0.385 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/popToPushGray_buffercc/buffers_0[0]
|
|
SLICE_X27Y78 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/popToPushGray_buffercc/buffers_1_reg[0]/D
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock sys_clk rise edge) 0.000 0.000 r
|
|
clock source latency -1.947 -1.947
|
|
propagated clock network latency
|
|
1.593 -0.354
|
|
clock pessimism -0.228 -0.582
|
|
SLICE_X27Y78 FDCE (Hold_fdce_C_D) 0.075 -0.507 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/popToPushGray_buffercc/buffers_1_reg[0]
|
|
-------------------------------------------------------------------
|
|
required time 0.507
|
|
arrival time -0.385
|
|
-------------------------------------------------------------------
|
|
slack 0.122
|
|
|
|
Slack (MET) : 0.122ns (arrival time - required time)
|
|
Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/popToPushGray_buffercc/buffers_0_reg[1]/C
|
|
(rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/popToPushGray_buffercc/buffers_1_reg[1]/D
|
|
(rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Path Group: sys_clk
|
|
Path Type: Hold (Min at Fast Process Corner)
|
|
Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns)
|
|
Data Path Delay: 0.197ns (logic 0.141ns (71.611%) route 0.056ns (28.389%))
|
|
Logic Levels: 0
|
|
Clock Path Skew: 0.000ns (DCD - SCD - CPR)
|
|
Destination Clock Delay (DCD): -0.360ns
|
|
Source Clock Delay (SCD): -0.587ns
|
|
Clock Pessimism Removal (CPR): 0.227ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock sys_clk rise edge) 0.000 0.000 r
|
|
clock source latency -1.848 -1.848
|
|
propagated clock network latency
|
|
1.261 -0.587
|
|
SLICE_X29Y74 FDCE 0.000 -0.587 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/popToPushGray_buffercc/buffers_0_reg[1]/C
|
|
SLICE_X29Y74 FDCE (Prop_fdce_C_Q) 0.141 -0.446 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/popToPushGray_buffercc/buffers_0_reg[1]/Q
|
|
net (fo=1, routed) 0.056 -0.390 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/popToPushGray_buffercc/buffers_0[1]
|
|
SLICE_X29Y74 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/popToPushGray_buffercc/buffers_1_reg[1]/D
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock sys_clk rise edge) 0.000 0.000 r
|
|
clock source latency -1.947 -1.947
|
|
propagated clock network latency
|
|
1.587 -0.360
|
|
clock pessimism -0.227 -0.587
|
|
SLICE_X29Y74 FDCE (Hold_fdce_C_D) 0.075 -0.512 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/popToPushGray_buffercc/buffers_1_reg[1]
|
|
-------------------------------------------------------------------
|
|
required time 0.512
|
|
arrival time -0.390
|
|
-------------------------------------------------------------------
|
|
slack 0.122
|
|
|
|
Slack (MET) : 0.122ns (arrival time - required time)
|
|
Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/popToPushGray_buffercc/buffers_0_reg[1]/C
|
|
(rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/popToPushGray_buffercc/buffers_1_reg[1]/D
|
|
(rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Path Group: sys_clk
|
|
Path Type: Hold (Min at Fast Process Corner)
|
|
Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns)
|
|
Data Path Delay: 0.197ns (logic 0.141ns (71.611%) route 0.056ns (28.389%))
|
|
Logic Levels: 0
|
|
Clock Path Skew: 0.000ns (DCD - SCD - CPR)
|
|
Destination Clock Delay (DCD): -0.360ns
|
|
Source Clock Delay (SCD): -0.587ns
|
|
Clock Pessimism Removal (CPR): 0.227ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock sys_clk rise edge) 0.000 0.000 r
|
|
clock source latency -1.848 -1.848
|
|
propagated clock network latency
|
|
1.261 -0.587
|
|
SLICE_X29Y74 FDCE 0.000 -0.587 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/popToPushGray_buffercc/buffers_0_reg[1]/C
|
|
SLICE_X29Y74 FDCE (Prop_fdce_C_Q) 0.141 -0.446 f u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/popToPushGray_buffercc/buffers_0_reg[1]/Q
|
|
net (fo=1, routed) 0.056 -0.390 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/popToPushGray_buffercc/buffers_0[1]
|
|
SLICE_X29Y74 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/popToPushGray_buffercc/buffers_1_reg[1]/D
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock sys_clk rise edge) 0.000 0.000 r
|
|
clock source latency -1.947 -1.947
|
|
propagated clock network latency
|
|
1.587 -0.360
|
|
clock pessimism -0.227 -0.587
|
|
SLICE_X29Y74 FDCE (Hold_fdce_C_D) 0.075 -0.512 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/popToPushGray_buffercc/buffers_1_reg[1]
|
|
-------------------------------------------------------------------
|
|
required time 0.512
|
|
arrival time -0.390
|
|
-------------------------------------------------------------------
|
|
slack 0.122
|
|
|
|
Slack (MET) : 0.122ns (arrival time - required time)
|
|
Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/buffers_0_reg/C
|
|
(rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/buffers_1_reg/D
|
|
(rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Path Group: sys_clk
|
|
Path Type: Hold (Min at Fast Process Corner)
|
|
Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns)
|
|
Data Path Delay: 0.197ns (logic 0.141ns (71.611%) route 0.056ns (28.389%))
|
|
Logic Levels: 0
|
|
Clock Path Skew: 0.000ns (DCD - SCD - CPR)
|
|
Destination Clock Delay (DCD): -0.341ns
|
|
Source Clock Delay (SCD): -0.570ns
|
|
Clock Pessimism Removal (CPR): 0.229ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock sys_clk rise edge) 0.000 0.000 r
|
|
clock source latency -1.848 -1.848
|
|
propagated clock network latency
|
|
1.278 -0.570
|
|
SLICE_X13Y87 FDCE 0.000 -0.570 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/buffers_0_reg/C
|
|
SLICE_X13Y87 FDCE (Prop_fdce_C_Q) 0.141 -0.429 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/buffers_0_reg/Q
|
|
net (fo=1, routed) 0.056 -0.373 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/buffers_0
|
|
SLICE_X13Y87 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/buffers_1_reg/D
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock sys_clk rise edge) 0.000 0.000 r
|
|
clock source latency -1.947 -1.947
|
|
propagated clock network latency
|
|
1.606 -0.341
|
|
clock pessimism -0.229 -0.570
|
|
SLICE_X13Y87 FDCE (Hold_fdce_C_D) 0.075 -0.495 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/buffers_1_reg
|
|
-------------------------------------------------------------------
|
|
required time 0.495
|
|
arrival time -0.373
|
|
-------------------------------------------------------------------
|
|
slack 0.122
|
|
|
|
Slack (MET) : 0.122ns (arrival time - required time)
|
|
Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/buffers_0_reg/C
|
|
(rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/buffers_1_reg/D
|
|
(rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Path Group: sys_clk
|
|
Path Type: Hold (Min at Fast Process Corner)
|
|
Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns)
|
|
Data Path Delay: 0.197ns (logic 0.141ns (71.611%) route 0.056ns (28.389%))
|
|
Logic Levels: 0
|
|
Clock Path Skew: 0.000ns (DCD - SCD - CPR)
|
|
Destination Clock Delay (DCD): -0.341ns
|
|
Source Clock Delay (SCD): -0.570ns
|
|
Clock Pessimism Removal (CPR): 0.229ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock sys_clk rise edge) 0.000 0.000 r
|
|
clock source latency -1.848 -1.848
|
|
propagated clock network latency
|
|
1.278 -0.570
|
|
SLICE_X13Y87 FDCE 0.000 -0.570 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/buffers_0_reg/C
|
|
SLICE_X13Y87 FDCE (Prop_fdce_C_Q) 0.141 -0.429 f u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/buffers_0_reg/Q
|
|
net (fo=1, routed) 0.056 -0.373 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/buffers_0
|
|
SLICE_X13Y87 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/buffers_1_reg/D
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock sys_clk rise edge) 0.000 0.000 r
|
|
clock source latency -1.947 -1.947
|
|
propagated clock network latency
|
|
1.606 -0.341
|
|
clock pessimism -0.229 -0.570
|
|
SLICE_X13Y87 FDCE (Hold_fdce_C_D) 0.075 -0.495 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/buffers_1_reg
|
|
-------------------------------------------------------------------
|
|
required time 0.495
|
|
arrival time -0.373
|
|
-------------------------------------------------------------------
|
|
slack 0.122
|
|
|
|
Slack (MET) : 0.122ns (arrival time - required time)
|
|
Source: u_Axi_CDC/awFifo/popToPushGray_buffercc/buffers_0_reg[0]/C
|
|
(rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns})
|
|
Destination: u_Axi_CDC/awFifo/popToPushGray_buffercc/buffers_1_reg[0]/D
|
|
(rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns})
|
|
Path Group: cpu_clk
|
|
Path Type: Hold (Min at Fast Process Corner)
|
|
Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns)
|
|
Data Path Delay: 0.197ns (logic 0.141ns (71.611%) route 0.056ns (28.389%))
|
|
Logic Levels: 0
|
|
Clock Path Skew: 0.000ns (DCD - SCD - CPR)
|
|
Destination Clock Delay (DCD): -0.347ns
|
|
Source Clock Delay (SCD): -0.575ns
|
|
Clock Pessimism Removal (CPR): 0.228ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock cpu_clk rise edge) 0.000 0.000 r
|
|
clock source latency -1.848 -1.848
|
|
propagated clock network latency
|
|
1.273 -0.575
|
|
SLICE_X15Y69 FDCE 0.000 -0.575 r u_Axi_CDC/awFifo/popToPushGray_buffercc/buffers_0_reg[0]/C
|
|
SLICE_X15Y69 FDCE (Prop_fdce_C_Q) 0.141 -0.434 r u_Axi_CDC/awFifo/popToPushGray_buffercc/buffers_0_reg[0]/Q
|
|
net (fo=1, routed) 0.056 -0.378 u_Axi_CDC/awFifo/popToPushGray_buffercc/buffers_0[0]
|
|
SLICE_X15Y69 FDCE r u_Axi_CDC/awFifo/popToPushGray_buffercc/buffers_1_reg[0]/D
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock cpu_clk rise edge) 0.000 0.000 r
|
|
clock source latency -1.947 -1.947
|
|
propagated clock network latency
|
|
1.600 -0.347
|
|
clock pessimism -0.228 -0.575
|
|
SLICE_X15Y69 FDCE (Hold_fdce_C_D) 0.075 -0.500 u_Axi_CDC/awFifo/popToPushGray_buffercc/buffers_1_reg[0]
|
|
-------------------------------------------------------------------
|
|
required time 0.500
|
|
arrival time -0.378
|
|
-------------------------------------------------------------------
|
|
slack 0.122
|
|
|
|
Slack (MET) : 0.122ns (arrival time - required time)
|
|
Source: u_Axi_CDC/awFifo/popToPushGray_buffercc/buffers_0_reg[0]/C
|
|
(rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns})
|
|
Destination: u_Axi_CDC/awFifo/popToPushGray_buffercc/buffers_1_reg[0]/D
|
|
(rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns})
|
|
Path Group: cpu_clk
|
|
Path Type: Hold (Min at Fast Process Corner)
|
|
Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns)
|
|
Data Path Delay: 0.197ns (logic 0.141ns (71.611%) route 0.056ns (28.389%))
|
|
Logic Levels: 0
|
|
Clock Path Skew: 0.000ns (DCD - SCD - CPR)
|
|
Destination Clock Delay (DCD): -0.347ns
|
|
Source Clock Delay (SCD): -0.575ns
|
|
Clock Pessimism Removal (CPR): 0.228ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock cpu_clk rise edge) 0.000 0.000 r
|
|
clock source latency -1.848 -1.848
|
|
propagated clock network latency
|
|
1.273 -0.575
|
|
SLICE_X15Y69 FDCE 0.000 -0.575 r u_Axi_CDC/awFifo/popToPushGray_buffercc/buffers_0_reg[0]/C
|
|
SLICE_X15Y69 FDCE (Prop_fdce_C_Q) 0.141 -0.434 f u_Axi_CDC/awFifo/popToPushGray_buffercc/buffers_0_reg[0]/Q
|
|
net (fo=1, routed) 0.056 -0.378 u_Axi_CDC/awFifo/popToPushGray_buffercc/buffers_0[0]
|
|
SLICE_X15Y69 FDCE f u_Axi_CDC/awFifo/popToPushGray_buffercc/buffers_1_reg[0]/D
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock cpu_clk rise edge) 0.000 0.000 r
|
|
clock source latency -1.947 -1.947
|
|
propagated clock network latency
|
|
1.600 -0.347
|
|
clock pessimism -0.228 -0.575
|
|
SLICE_X15Y69 FDCE (Hold_fdce_C_D) 0.075 -0.500 u_Axi_CDC/awFifo/popToPushGray_buffercc/buffers_1_reg[0]
|
|
-------------------------------------------------------------------
|
|
required time 0.500
|
|
arrival time -0.378
|
|
-------------------------------------------------------------------
|
|
slack 0.122
|
|
|
|
Slack (MET) : 0.122ns (arrival time - required time)
|
|
Source: u_Axi_CDC/bFifo/pushToPopGray_buffercc/buffers_0_reg[0]/C
|
|
(rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns})
|
|
Destination: u_Axi_CDC/bFifo/pushToPopGray_buffercc/buffers_1_reg[0]/D
|
|
(rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns})
|
|
Path Group: cpu_clk
|
|
Path Type: Hold (Min at Fast Process Corner)
|
|
Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns)
|
|
Data Path Delay: 0.197ns (logic 0.141ns (71.611%) route 0.056ns (28.389%))
|
|
Logic Levels: 0
|
|
Clock Path Skew: 0.000ns (DCD - SCD - CPR)
|
|
Destination Clock Delay (DCD): -0.338ns
|
|
Source Clock Delay (SCD): -0.568ns
|
|
Clock Pessimism Removal (CPR): 0.230ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock cpu_clk rise edge) 0.000 0.000 r
|
|
clock source latency -1.848 -1.848
|
|
propagated clock network latency
|
|
1.280 -0.568
|
|
SLICE_X19Y59 FDCE 0.000 -0.568 r u_Axi_CDC/bFifo/pushToPopGray_buffercc/buffers_0_reg[0]/C
|
|
SLICE_X19Y59 FDCE (Prop_fdce_C_Q) 0.141 -0.427 r u_Axi_CDC/bFifo/pushToPopGray_buffercc/buffers_0_reg[0]/Q
|
|
net (fo=1, routed) 0.056 -0.371 u_Axi_CDC/bFifo/pushToPopGray_buffercc/buffers_0[0]
|
|
SLICE_X19Y59 FDCE r u_Axi_CDC/bFifo/pushToPopGray_buffercc/buffers_1_reg[0]/D
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock cpu_clk rise edge) 0.000 0.000 r
|
|
clock source latency -1.947 -1.947
|
|
propagated clock network latency
|
|
1.609 -0.338
|
|
clock pessimism -0.230 -0.568
|
|
SLICE_X19Y59 FDCE (Hold_fdce_C_D) 0.075 -0.493 u_Axi_CDC/bFifo/pushToPopGray_buffercc/buffers_1_reg[0]
|
|
-------------------------------------------------------------------
|
|
required time 0.493
|
|
arrival time -0.371
|
|
-------------------------------------------------------------------
|
|
slack 0.122
|
|
|
|
Slack (MET) : 0.122ns (arrival time - required time)
|
|
Source: u_Axi_CDC/bFifo/pushToPopGray_buffercc/buffers_0_reg[0]/C
|
|
(rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns})
|
|
Destination: u_Axi_CDC/bFifo/pushToPopGray_buffercc/buffers_1_reg[0]/D
|
|
(rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns})
|
|
Path Group: cpu_clk
|
|
Path Type: Hold (Min at Fast Process Corner)
|
|
Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns)
|
|
Data Path Delay: 0.197ns (logic 0.141ns (71.611%) route 0.056ns (28.389%))
|
|
Logic Levels: 0
|
|
Clock Path Skew: 0.000ns (DCD - SCD - CPR)
|
|
Destination Clock Delay (DCD): -0.338ns
|
|
Source Clock Delay (SCD): -0.568ns
|
|
Clock Pessimism Removal (CPR): 0.230ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock cpu_clk rise edge) 0.000 0.000 r
|
|
clock source latency -1.848 -1.848
|
|
propagated clock network latency
|
|
1.280 -0.568
|
|
SLICE_X19Y59 FDCE 0.000 -0.568 r u_Axi_CDC/bFifo/pushToPopGray_buffercc/buffers_0_reg[0]/C
|
|
SLICE_X19Y59 FDCE (Prop_fdce_C_Q) 0.141 -0.427 f u_Axi_CDC/bFifo/pushToPopGray_buffercc/buffers_0_reg[0]/Q
|
|
net (fo=1, routed) 0.056 -0.371 u_Axi_CDC/bFifo/pushToPopGray_buffercc/buffers_0[0]
|
|
SLICE_X19Y59 FDCE f u_Axi_CDC/bFifo/pushToPopGray_buffercc/buffers_1_reg[0]/D
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock cpu_clk rise edge) 0.000 0.000 r
|
|
clock source latency -1.947 -1.947
|
|
propagated clock network latency
|
|
1.609 -0.338
|
|
clock pessimism -0.230 -0.568
|
|
SLICE_X19Y59 FDCE (Hold_fdce_C_D) 0.075 -0.493 u_Axi_CDC/bFifo/pushToPopGray_buffercc/buffers_1_reg[0]
|
|
-------------------------------------------------------------------
|
|
required time 0.493
|
|
arrival time -0.371
|
|
-------------------------------------------------------------------
|
|
slack 0.122
|
|
|
|
Slack (MET) : 0.122ns (arrival time - required time)
|
|
Source: u_Axi_CDC/rFifo/pushToPopGray_buffercc/buffers_0_reg[0]/C
|
|
(rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns})
|
|
Destination: u_Axi_CDC/rFifo/pushToPopGray_buffercc/buffers_1_reg[0]/D
|
|
(rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns})
|
|
Path Group: cpu_clk
|
|
Path Type: Hold (Min at Fast Process Corner)
|
|
Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns)
|
|
Data Path Delay: 0.197ns (logic 0.141ns (71.611%) route 0.056ns (28.389%))
|
|
Logic Levels: 0
|
|
Clock Path Skew: 0.000ns (DCD - SCD - CPR)
|
|
Destination Clock Delay (DCD): -0.323ns
|
|
Source Clock Delay (SCD): -0.552ns
|
|
Clock Pessimism Removal (CPR): 0.229ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock cpu_clk rise edge) 0.000 0.000 r
|
|
clock source latency -1.848 -1.848
|
|
propagated clock network latency
|
|
1.296 -0.552
|
|
SLICE_X5Y76 FDCE 0.000 -0.552 r u_Axi_CDC/rFifo/pushToPopGray_buffercc/buffers_0_reg[0]/C
|
|
SLICE_X5Y76 FDCE (Prop_fdce_C_Q) 0.141 -0.411 r u_Axi_CDC/rFifo/pushToPopGray_buffercc/buffers_0_reg[0]/Q
|
|
net (fo=1, routed) 0.056 -0.355 u_Axi_CDC/rFifo/pushToPopGray_buffercc/buffers_0[0]
|
|
SLICE_X5Y76 FDCE r u_Axi_CDC/rFifo/pushToPopGray_buffercc/buffers_1_reg[0]/D
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock cpu_clk rise edge) 0.000 0.000 r
|
|
clock source latency -1.947 -1.947
|
|
propagated clock network latency
|
|
1.624 -0.323
|
|
clock pessimism -0.229 -0.552
|
|
SLICE_X5Y76 FDCE (Hold_fdce_C_D) 0.075 -0.477 u_Axi_CDC/rFifo/pushToPopGray_buffercc/buffers_1_reg[0]
|
|
-------------------------------------------------------------------
|
|
required time 0.477
|
|
arrival time -0.355
|
|
-------------------------------------------------------------------
|
|
slack 0.122
|
|
|
|
Slack (MET) : 0.122ns (arrival time - required time)
|
|
Source: u_Axi_CDC/rFifo/pushToPopGray_buffercc/buffers_0_reg[0]/C
|
|
(rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns})
|
|
Destination: u_Axi_CDC/rFifo/pushToPopGray_buffercc/buffers_1_reg[0]/D
|
|
(rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns})
|
|
Path Group: cpu_clk
|
|
Path Type: Hold (Min at Fast Process Corner)
|
|
Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns)
|
|
Data Path Delay: 0.197ns (logic 0.141ns (71.611%) route 0.056ns (28.389%))
|
|
Logic Levels: 0
|
|
Clock Path Skew: 0.000ns (DCD - SCD - CPR)
|
|
Destination Clock Delay (DCD): -0.323ns
|
|
Source Clock Delay (SCD): -0.552ns
|
|
Clock Pessimism Removal (CPR): 0.229ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock cpu_clk rise edge) 0.000 0.000 r
|
|
clock source latency -1.848 -1.848
|
|
propagated clock network latency
|
|
1.296 -0.552
|
|
SLICE_X5Y76 FDCE 0.000 -0.552 r u_Axi_CDC/rFifo/pushToPopGray_buffercc/buffers_0_reg[0]/C
|
|
SLICE_X5Y76 FDCE (Prop_fdce_C_Q) 0.141 -0.411 f u_Axi_CDC/rFifo/pushToPopGray_buffercc/buffers_0_reg[0]/Q
|
|
net (fo=1, routed) 0.056 -0.355 u_Axi_CDC/rFifo/pushToPopGray_buffercc/buffers_0[0]
|
|
SLICE_X5Y76 FDCE f u_Axi_CDC/rFifo/pushToPopGray_buffercc/buffers_1_reg[0]/D
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock cpu_clk rise edge) 0.000 0.000 r
|
|
clock source latency -1.947 -1.947
|
|
propagated clock network latency
|
|
1.624 -0.323
|
|
clock pessimism -0.229 -0.552
|
|
SLICE_X5Y76 FDCE (Hold_fdce_C_D) 0.075 -0.477 u_Axi_CDC/rFifo/pushToPopGray_buffercc/buffers_1_reg[0]
|
|
-------------------------------------------------------------------
|
|
required time 0.477
|
|
arrival time -0.355
|
|
-------------------------------------------------------------------
|
|
slack 0.122
|
|
|
|
Slack (MET) : 0.122ns (arrival time - required time)
|
|
Source: u_Axi_CDC/rFifo/pushToPopGray_buffercc/buffers_0_reg[3]/C
|
|
(rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns})
|
|
Destination: u_Axi_CDC/rFifo/pushToPopGray_buffercc/buffers_1_reg[3]/D
|
|
(rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns})
|
|
Path Group: cpu_clk
|
|
Path Type: Hold (Min at Fast Process Corner)
|
|
Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns)
|
|
Data Path Delay: 0.197ns (logic 0.141ns (71.611%) route 0.056ns (28.389%))
|
|
Logic Levels: 0
|
|
Clock Path Skew: 0.000ns (DCD - SCD - CPR)
|
|
Destination Clock Delay (DCD): -0.324ns
|
|
Source Clock Delay (SCD): -0.553ns
|
|
Clock Pessimism Removal (CPR): 0.229ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock cpu_clk rise edge) 0.000 0.000 r
|
|
clock source latency -1.848 -1.848
|
|
propagated clock network latency
|
|
1.295 -0.553
|
|
SLICE_X5Y75 FDCE 0.000 -0.553 r u_Axi_CDC/rFifo/pushToPopGray_buffercc/buffers_0_reg[3]/C
|
|
SLICE_X5Y75 FDCE (Prop_fdce_C_Q) 0.141 -0.412 r u_Axi_CDC/rFifo/pushToPopGray_buffercc/buffers_0_reg[3]/Q
|
|
net (fo=1, routed) 0.056 -0.356 u_Axi_CDC/rFifo/pushToPopGray_buffercc/buffers_0[3]
|
|
SLICE_X5Y75 FDCE r u_Axi_CDC/rFifo/pushToPopGray_buffercc/buffers_1_reg[3]/D
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock cpu_clk rise edge) 0.000 0.000 r
|
|
clock source latency -1.947 -1.947
|
|
propagated clock network latency
|
|
1.623 -0.324
|
|
clock pessimism -0.229 -0.553
|
|
SLICE_X5Y75 FDCE (Hold_fdce_C_D) 0.075 -0.478 u_Axi_CDC/rFifo/pushToPopGray_buffercc/buffers_1_reg[3]
|
|
-------------------------------------------------------------------
|
|
required time 0.478
|
|
arrival time -0.356
|
|
-------------------------------------------------------------------
|
|
slack 0.122
|
|
|
|
Slack (MET) : 0.122ns (arrival time - required time)
|
|
Source: u_Axi_CDC/rFifo/pushToPopGray_buffercc/buffers_0_reg[3]/C
|
|
(rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns})
|
|
Destination: u_Axi_CDC/rFifo/pushToPopGray_buffercc/buffers_1_reg[3]/D
|
|
(rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns})
|
|
Path Group: cpu_clk
|
|
Path Type: Hold (Min at Fast Process Corner)
|
|
Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns)
|
|
Data Path Delay: 0.197ns (logic 0.141ns (71.611%) route 0.056ns (28.389%))
|
|
Logic Levels: 0
|
|
Clock Path Skew: 0.000ns (DCD - SCD - CPR)
|
|
Destination Clock Delay (DCD): -0.324ns
|
|
Source Clock Delay (SCD): -0.553ns
|
|
Clock Pessimism Removal (CPR): 0.229ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock cpu_clk rise edge) 0.000 0.000 r
|
|
clock source latency -1.848 -1.848
|
|
propagated clock network latency
|
|
1.295 -0.553
|
|
SLICE_X5Y75 FDCE 0.000 -0.553 r u_Axi_CDC/rFifo/pushToPopGray_buffercc/buffers_0_reg[3]/C
|
|
SLICE_X5Y75 FDCE (Prop_fdce_C_Q) 0.141 -0.412 f u_Axi_CDC/rFifo/pushToPopGray_buffercc/buffers_0_reg[3]/Q
|
|
net (fo=1, routed) 0.056 -0.356 u_Axi_CDC/rFifo/pushToPopGray_buffercc/buffers_0[3]
|
|
SLICE_X5Y75 FDCE f u_Axi_CDC/rFifo/pushToPopGray_buffercc/buffers_1_reg[3]/D
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock cpu_clk rise edge) 0.000 0.000 r
|
|
clock source latency -1.947 -1.947
|
|
propagated clock network latency
|
|
1.623 -0.324
|
|
clock pessimism -0.229 -0.553
|
|
SLICE_X5Y75 FDCE (Hold_fdce_C_D) 0.075 -0.478 u_Axi_CDC/rFifo/pushToPopGray_buffercc/buffers_1_reg[3]
|
|
-------------------------------------------------------------------
|
|
required time 0.478
|
|
arrival time -0.356
|
|
-------------------------------------------------------------------
|
|
slack 0.122
|
|
|
|
Slack (MET) : 0.123ns (arrival time - required time)
|
|
Source: u_cpu/u_csr/csr_tlbelo0_reg[12]/C
|
|
(rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns})
|
|
Destination: u_cpu/addr_trans/tlb_entry/tlb_ppn0_reg_r3_0_31_0_5/RAMC/I
|
|
(rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns})
|
|
Path Group: cpu_clk
|
|
Path Type: Hold (Min at Fast Process Corner)
|
|
Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns)
|
|
Data Path Delay: 0.280ns (logic 0.141ns (50.404%) route 0.139ns (49.596%))
|
|
Logic Levels: 0
|
|
Clock Path Skew: 0.013ns (DCD - SCD - CPR)
|
|
Destination Clock Delay (DCD): -0.309ns
|
|
Source Clock Delay (SCD): -0.540ns
|
|
Clock Pessimism Removal (CPR): 0.218ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock cpu_clk rise edge) 0.000 0.000 r
|
|
clock source latency -1.848 -1.848
|
|
propagated clock network latency
|
|
1.309 -0.540
|
|
SLICE_X45Y34 FDRE 0.000 -0.540 r u_cpu/u_csr/csr_tlbelo0_reg[12]/C
|
|
SLICE_X45Y34 FDRE (Prop_fdre_C_Q) 0.141 -0.399 r u_cpu/u_csr/csr_tlbelo0_reg[12]/Q
|
|
net (fo=4, routed) 0.139 -0.260 u_cpu/addr_trans/tlb_entry/tlb_ppn0_reg_r3_0_31_0_5/DIC0
|
|
SLICE_X44Y34 RAMD32 r u_cpu/addr_trans/tlb_entry/tlb_ppn0_reg_r3_0_31_0_5/RAMC/I
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock cpu_clk rise edge) 0.000 0.000 r
|
|
clock source latency -1.947 -1.947
|
|
propagated clock network latency
|
|
1.638 -0.309
|
|
clock pessimism -0.218 -0.527
|
|
SLICE_X44Y34 RAMD32 (Hold_ramd32_CLK_I)
|
|
0.144 -0.383 u_cpu/addr_trans/tlb_entry/tlb_ppn0_reg_r3_0_31_0_5/RAMC
|
|
-------------------------------------------------------------------
|
|
required time 0.383
|
|
arrival time -0.260
|
|
-------------------------------------------------------------------
|
|
slack 0.123
|
|
|
|
Slack (MET) : 0.123ns (arrival time - required time)
|
|
Source: u_cpu/u_csr/csr_tlbelo0_reg[12]/C
|
|
(rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns})
|
|
Destination: u_cpu/addr_trans/tlb_entry/tlb_ppn0_reg_r3_0_31_0_5/RAMC/I
|
|
(rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns})
|
|
Path Group: cpu_clk
|
|
Path Type: Hold (Min at Fast Process Corner)
|
|
Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns)
|
|
Data Path Delay: 0.280ns (logic 0.141ns (50.404%) route 0.139ns (49.596%))
|
|
Logic Levels: 0
|
|
Clock Path Skew: 0.013ns (DCD - SCD - CPR)
|
|
Destination Clock Delay (DCD): -0.309ns
|
|
Source Clock Delay (SCD): -0.540ns
|
|
Clock Pessimism Removal (CPR): 0.218ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock cpu_clk rise edge) 0.000 0.000 r
|
|
clock source latency -1.848 -1.848
|
|
propagated clock network latency
|
|
1.309 -0.540
|
|
SLICE_X45Y34 FDRE 0.000 -0.540 r u_cpu/u_csr/csr_tlbelo0_reg[12]/C
|
|
SLICE_X45Y34 FDRE (Prop_fdre_C_Q) 0.141 -0.399 f u_cpu/u_csr/csr_tlbelo0_reg[12]/Q
|
|
net (fo=4, routed) 0.139 -0.260 u_cpu/addr_trans/tlb_entry/tlb_ppn0_reg_r3_0_31_0_5/DIC0
|
|
SLICE_X44Y34 RAMD32 f u_cpu/addr_trans/tlb_entry/tlb_ppn0_reg_r3_0_31_0_5/RAMC/I
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock cpu_clk rise edge) 0.000 0.000 r
|
|
clock source latency -1.947 -1.947
|
|
propagated clock network latency
|
|
1.638 -0.309
|
|
clock pessimism -0.218 -0.527
|
|
SLICE_X44Y34 RAMD32 (Hold_ramd32_CLK_I)
|
|
0.144 -0.383 u_cpu/addr_trans/tlb_entry/tlb_ppn0_reg_r3_0_31_0_5/RAMC
|
|
-------------------------------------------------------------------
|
|
required time 0.383
|
|
arrival time -0.260
|
|
-------------------------------------------------------------------
|
|
slack 0.123
|
|
|
|
Slack (MET) : 0.124ns (arrival time - required time)
|
|
Source: u_cpu/u_csr/csr_tlbelo0_reg[16]/C
|
|
(rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns})
|
|
Destination: u_cpu/addr_trans/tlb_entry/tlb_ppn0_reg_r3_0_31_6_11/RAMB/I
|
|
(rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns})
|
|
Path Group: cpu_clk
|
|
Path Type: Hold (Min at Fast Process Corner)
|
|
Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns)
|
|
Data Path Delay: 0.284ns (logic 0.141ns (49.682%) route 0.143ns (50.318%))
|
|
Logic Levels: 0
|
|
Clock Path Skew: 0.014ns (DCD - SCD - CPR)
|
|
Destination Clock Delay (DCD): -0.310ns
|
|
Source Clock Delay (SCD): -0.541ns
|
|
Clock Pessimism Removal (CPR): 0.217ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock cpu_clk rise edge) 0.000 0.000 r
|
|
clock source latency -1.848 -1.848
|
|
propagated clock network latency
|
|
1.308 -0.541
|
|
SLICE_X47Y36 FDRE 0.000 -0.541 r u_cpu/u_csr/csr_tlbelo0_reg[16]/C
|
|
SLICE_X47Y36 FDRE (Prop_fdre_C_Q) 0.141 -0.400 r u_cpu/u_csr/csr_tlbelo0_reg[16]/Q
|
|
net (fo=4, routed) 0.143 -0.257 u_cpu/addr_trans/tlb_entry/tlb_ppn0_reg_r3_0_31_6_11/DIB0
|
|
SLICE_X46Y34 RAMD32 r u_cpu/addr_trans/tlb_entry/tlb_ppn0_reg_r3_0_31_6_11/RAMB/I
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock cpu_clk rise edge) 0.000 0.000 r
|
|
clock source latency -1.947 -1.947
|
|
propagated clock network latency
|
|
1.637 -0.310
|
|
clock pessimism -0.217 -0.527
|
|
SLICE_X46Y34 RAMD32 (Hold_ramd32_CLK_I)
|
|
0.146 -0.381 u_cpu/addr_trans/tlb_entry/tlb_ppn0_reg_r3_0_31_6_11/RAMB
|
|
-------------------------------------------------------------------
|
|
required time 0.381
|
|
arrival time -0.257
|
|
-------------------------------------------------------------------
|
|
slack 0.124
|
|
|
|
Slack (MET) : 0.124ns (arrival time - required time)
|
|
Source: u_cpu/u_csr/csr_tlbelo0_reg[16]/C
|
|
(rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns})
|
|
Destination: u_cpu/addr_trans/tlb_entry/tlb_ppn0_reg_r3_0_31_6_11/RAMB/I
|
|
(rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns})
|
|
Path Group: cpu_clk
|
|
Path Type: Hold (Min at Fast Process Corner)
|
|
Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns)
|
|
Data Path Delay: 0.284ns (logic 0.141ns (49.682%) route 0.143ns (50.318%))
|
|
Logic Levels: 0
|
|
Clock Path Skew: 0.014ns (DCD - SCD - CPR)
|
|
Destination Clock Delay (DCD): -0.310ns
|
|
Source Clock Delay (SCD): -0.541ns
|
|
Clock Pessimism Removal (CPR): 0.217ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock cpu_clk rise edge) 0.000 0.000 r
|
|
clock source latency -1.848 -1.848
|
|
propagated clock network latency
|
|
1.308 -0.541
|
|
SLICE_X47Y36 FDRE 0.000 -0.541 r u_cpu/u_csr/csr_tlbelo0_reg[16]/C
|
|
SLICE_X47Y36 FDRE (Prop_fdre_C_Q) 0.141 -0.400 f u_cpu/u_csr/csr_tlbelo0_reg[16]/Q
|
|
net (fo=4, routed) 0.143 -0.257 u_cpu/addr_trans/tlb_entry/tlb_ppn0_reg_r3_0_31_6_11/DIB0
|
|
SLICE_X46Y34 RAMD32 f u_cpu/addr_trans/tlb_entry/tlb_ppn0_reg_r3_0_31_6_11/RAMB/I
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock cpu_clk rise edge) 0.000 0.000 r
|
|
clock source latency -1.947 -1.947
|
|
propagated clock network latency
|
|
1.637 -0.310
|
|
clock pessimism -0.217 -0.527
|
|
SLICE_X46Y34 RAMD32 (Hold_ramd32_CLK_I)
|
|
0.146 -0.381 u_cpu/addr_trans/tlb_entry/tlb_ppn0_reg_r3_0_31_6_11/RAMB
|
|
-------------------------------------------------------------------
|
|
required time 0.381
|
|
arrival time -0.257
|
|
-------------------------------------------------------------------
|
|
slack 0.124
|
|
|
|
Slack (MET) : 0.124ns (arrival time - required time)
|
|
Source: u_cpu/axi_bridge/wdata_reg[22]/C
|
|
(rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns})
|
|
Destination: u_Axi_CDC/wFifo/ram_reg_0_7_18_23/RAMC/I
|
|
(rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns})
|
|
Path Group: cpu_clk
|
|
Path Type: Hold (Min at Fast Process Corner)
|
|
Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns)
|
|
Data Path Delay: 0.310ns (logic 0.141ns (45.479%) route 0.169ns (54.521%))
|
|
Logic Levels: 0
|
|
Clock Path Skew: 0.042ns (DCD - SCD - CPR)
|
|
Destination Clock Delay (DCD): -0.229ns
|
|
Source Clock Delay (SCD): -0.467ns
|
|
Clock Pessimism Removal (CPR): 0.196ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock cpu_clk rise edge) 0.000 0.000 r
|
|
clock source latency -1.848 -1.848
|
|
propagated clock network latency
|
|
1.382 -0.467
|
|
SLICE_X5Y47 FDRE 0.000 -0.467 r u_cpu/axi_bridge/wdata_reg[22]/C
|
|
SLICE_X5Y47 FDRE (Prop_fdre_C_Q) 0.141 -0.326 r u_cpu/axi_bridge/wdata_reg[22]/Q
|
|
net (fo=1, routed) 0.169 -0.157 u_Axi_CDC/wFifo/ram_reg_0_7_18_23/DIC0
|
|
SLICE_X2Y48 RAMD32 r u_Axi_CDC/wFifo/ram_reg_0_7_18_23/RAMC/I
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock cpu_clk rise edge) 0.000 0.000 r
|
|
clock source latency -1.947 -1.947
|
|
propagated clock network latency
|
|
1.718 -0.229
|
|
clock pessimism -0.196 -0.425
|
|
SLICE_X2Y48 RAMD32 (Hold_ramd32_CLK_I)
|
|
0.144 -0.281 u_Axi_CDC/wFifo/ram_reg_0_7_18_23/RAMC
|
|
-------------------------------------------------------------------
|
|
required time 0.281
|
|
arrival time -0.157
|
|
-------------------------------------------------------------------
|
|
slack 0.124
|
|
|
|
Slack (MET) : 0.124ns (arrival time - required time)
|
|
Source: u_cpu/axi_bridge/wdata_reg[22]/C
|
|
(rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns})
|
|
Destination: u_Axi_CDC/wFifo/ram_reg_0_7_18_23/RAMC/I
|
|
(rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns})
|
|
Path Group: cpu_clk
|
|
Path Type: Hold (Min at Fast Process Corner)
|
|
Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns)
|
|
Data Path Delay: 0.310ns (logic 0.141ns (45.479%) route 0.169ns (54.521%))
|
|
Logic Levels: 0
|
|
Clock Path Skew: 0.042ns (DCD - SCD - CPR)
|
|
Destination Clock Delay (DCD): -0.229ns
|
|
Source Clock Delay (SCD): -0.467ns
|
|
Clock Pessimism Removal (CPR): 0.196ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock cpu_clk rise edge) 0.000 0.000 r
|
|
clock source latency -1.848 -1.848
|
|
propagated clock network latency
|
|
1.382 -0.467
|
|
SLICE_X5Y47 FDRE 0.000 -0.467 r u_cpu/axi_bridge/wdata_reg[22]/C
|
|
SLICE_X5Y47 FDRE (Prop_fdre_C_Q) 0.141 -0.326 f u_cpu/axi_bridge/wdata_reg[22]/Q
|
|
net (fo=1, routed) 0.169 -0.157 u_Axi_CDC/wFifo/ram_reg_0_7_18_23/DIC0
|
|
SLICE_X2Y48 RAMD32 f u_Axi_CDC/wFifo/ram_reg_0_7_18_23/RAMC/I
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock cpu_clk rise edge) 0.000 0.000 r
|
|
clock source latency -1.947 -1.947
|
|
propagated clock network latency
|
|
1.718 -0.229
|
|
clock pessimism -0.196 -0.425
|
|
SLICE_X2Y48 RAMD32 (Hold_ramd32_CLK_I)
|
|
0.144 -0.281 u_Axi_CDC/wFifo/ram_reg_0_7_18_23/RAMC
|
|
-------------------------------------------------------------------
|
|
required time 0.281
|
|
arrival time -0.157
|
|
-------------------------------------------------------------------
|
|
slack 0.124
|
|
|
|
Slack (MET) : 0.125ns (arrival time - required time)
|
|
Source: u_cpu/u_csr/csr_tlbelo1_reg[3]/C
|
|
(rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns})
|
|
Destination: u_cpu/addr_trans/tlb_entry/tlb_plv1_reg_r3_0_31_1_1/DP/I
|
|
(rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns})
|
|
Path Group: cpu_clk
|
|
Path Type: Hold (Min at Fast Process Corner)
|
|
Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns)
|
|
Data Path Delay: 0.261ns (logic 0.141ns (54.075%) route 0.120ns (45.925%))
|
|
Logic Levels: 0
|
|
Clock Path Skew: 0.016ns (DCD - SCD - CPR)
|
|
Destination Clock Delay (DCD): -0.275ns
|
|
Source Clock Delay (SCD): -0.509ns
|
|
Clock Pessimism Removal (CPR): 0.218ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock cpu_clk rise edge) 0.000 0.000 r
|
|
clock source latency -1.848 -1.848
|
|
propagated clock network latency
|
|
1.340 -0.509
|
|
SLICE_X39Y39 FDRE 0.000 -0.509 r u_cpu/u_csr/csr_tlbelo1_reg[3]/C
|
|
SLICE_X39Y39 FDRE (Prop_fdre_C_Q) 0.141 -0.368 r u_cpu/u_csr/csr_tlbelo1_reg[3]/Q
|
|
net (fo=7, routed) 0.120 -0.248 u_cpu/addr_trans/tlb_entry/tlb_plv1_reg_r3_0_31_1_1/D
|
|
SLICE_X40Y39 RAMD32 r u_cpu/addr_trans/tlb_entry/tlb_plv1_reg_r3_0_31_1_1/DP/I
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock cpu_clk rise edge) 0.000 0.000 r
|
|
clock source latency -1.947 -1.947
|
|
propagated clock network latency
|
|
1.672 -0.275
|
|
clock pessimism -0.218 -0.493
|
|
SLICE_X40Y39 RAMD32 (Hold_ramd32_CLK_I)
|
|
0.120 -0.373 u_cpu/addr_trans/tlb_entry/tlb_plv1_reg_r3_0_31_1_1/DP
|
|
-------------------------------------------------------------------
|
|
required time 0.373
|
|
arrival time -0.248
|
|
-------------------------------------------------------------------
|
|
slack 0.125
|
|
|
|
Slack (MET) : 0.125ns (arrival time - required time)
|
|
Source: u_cpu/u_csr/csr_tlbelo1_reg[3]/C
|
|
(rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns})
|
|
Destination: u_cpu/addr_trans/tlb_entry/tlb_plv1_reg_r3_0_31_1_1/DP/I
|
|
(rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns})
|
|
Path Group: cpu_clk
|
|
Path Type: Hold (Min at Fast Process Corner)
|
|
Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns)
|
|
Data Path Delay: 0.261ns (logic 0.141ns (54.075%) route 0.120ns (45.925%))
|
|
Logic Levels: 0
|
|
Clock Path Skew: 0.016ns (DCD - SCD - CPR)
|
|
Destination Clock Delay (DCD): -0.275ns
|
|
Source Clock Delay (SCD): -0.509ns
|
|
Clock Pessimism Removal (CPR): 0.218ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock cpu_clk rise edge) 0.000 0.000 r
|
|
clock source latency -1.848 -1.848
|
|
propagated clock network latency
|
|
1.340 -0.509
|
|
SLICE_X39Y39 FDRE 0.000 -0.509 r u_cpu/u_csr/csr_tlbelo1_reg[3]/C
|
|
SLICE_X39Y39 FDRE (Prop_fdre_C_Q) 0.141 -0.368 f u_cpu/u_csr/csr_tlbelo1_reg[3]/Q
|
|
net (fo=7, routed) 0.120 -0.248 u_cpu/addr_trans/tlb_entry/tlb_plv1_reg_r3_0_31_1_1/D
|
|
SLICE_X40Y39 RAMD32 f u_cpu/addr_trans/tlb_entry/tlb_plv1_reg_r3_0_31_1_1/DP/I
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock cpu_clk rise edge) 0.000 0.000 r
|
|
clock source latency -1.947 -1.947
|
|
propagated clock network latency
|
|
1.672 -0.275
|
|
clock pessimism -0.218 -0.493
|
|
SLICE_X40Y39 RAMD32 (Hold_ramd32_CLK_I)
|
|
0.120 -0.373 u_cpu/addr_trans/tlb_entry/tlb_plv1_reg_r3_0_31_1_1/DP
|
|
-------------------------------------------------------------------
|
|
required time 0.373
|
|
arrival time -0.248
|
|
-------------------------------------------------------------------
|
|
slack 0.125
|
|
|
|
Slack (MET) : 0.126ns (arrival time - required time)
|
|
Source: u_Axi_CDC/awFifo/popToPushGray_buffercc/buffers_0_reg[1]/C
|
|
(rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns})
|
|
Destination: u_Axi_CDC/awFifo/popToPushGray_buffercc/buffers_1_reg[1]/D
|
|
(rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns})
|
|
Path Group: cpu_clk
|
|
Path Type: Hold (Min at Fast Process Corner)
|
|
Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns)
|
|
Data Path Delay: 0.197ns (logic 0.141ns (71.611%) route 0.056ns (28.389%))
|
|
Logic Levels: 0
|
|
Clock Path Skew: 0.000ns (DCD - SCD - CPR)
|
|
Destination Clock Delay (DCD): -0.347ns
|
|
Source Clock Delay (SCD): -0.575ns
|
|
Clock Pessimism Removal (CPR): 0.228ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock cpu_clk rise edge) 0.000 0.000 r
|
|
clock source latency -1.848 -1.848
|
|
propagated clock network latency
|
|
1.273 -0.575
|
|
SLICE_X15Y69 FDCE 0.000 -0.575 r u_Axi_CDC/awFifo/popToPushGray_buffercc/buffers_0_reg[1]/C
|
|
SLICE_X15Y69 FDCE (Prop_fdce_C_Q) 0.141 -0.434 r u_Axi_CDC/awFifo/popToPushGray_buffercc/buffers_0_reg[1]/Q
|
|
net (fo=1, routed) 0.056 -0.378 u_Axi_CDC/awFifo/popToPushGray_buffercc/buffers_0[1]
|
|
SLICE_X15Y69 FDCE r u_Axi_CDC/awFifo/popToPushGray_buffercc/buffers_1_reg[1]/D
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock cpu_clk rise edge) 0.000 0.000 r
|
|
clock source latency -1.947 -1.947
|
|
propagated clock network latency
|
|
1.600 -0.347
|
|
clock pessimism -0.228 -0.575
|
|
SLICE_X15Y69 FDCE (Hold_fdce_C_D) 0.071 -0.504 u_Axi_CDC/awFifo/popToPushGray_buffercc/buffers_1_reg[1]
|
|
-------------------------------------------------------------------
|
|
required time 0.504
|
|
arrival time -0.378
|
|
-------------------------------------------------------------------
|
|
slack 0.126
|
|
|
|
Slack (MET) : 0.126ns (arrival time - required time)
|
|
Source: u_Axi_CDC/awFifo/popToPushGray_buffercc/buffers_0_reg[1]/C
|
|
(rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns})
|
|
Destination: u_Axi_CDC/awFifo/popToPushGray_buffercc/buffers_1_reg[1]/D
|
|
(rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns})
|
|
Path Group: cpu_clk
|
|
Path Type: Hold (Min at Fast Process Corner)
|
|
Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns)
|
|
Data Path Delay: 0.197ns (logic 0.141ns (71.611%) route 0.056ns (28.389%))
|
|
Logic Levels: 0
|
|
Clock Path Skew: 0.000ns (DCD - SCD - CPR)
|
|
Destination Clock Delay (DCD): -0.347ns
|
|
Source Clock Delay (SCD): -0.575ns
|
|
Clock Pessimism Removal (CPR): 0.228ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock cpu_clk rise edge) 0.000 0.000 r
|
|
clock source latency -1.848 -1.848
|
|
propagated clock network latency
|
|
1.273 -0.575
|
|
SLICE_X15Y69 FDCE 0.000 -0.575 r u_Axi_CDC/awFifo/popToPushGray_buffercc/buffers_0_reg[1]/C
|
|
SLICE_X15Y69 FDCE (Prop_fdce_C_Q) 0.141 -0.434 f u_Axi_CDC/awFifo/popToPushGray_buffercc/buffers_0_reg[1]/Q
|
|
net (fo=1, routed) 0.056 -0.378 u_Axi_CDC/awFifo/popToPushGray_buffercc/buffers_0[1]
|
|
SLICE_X15Y69 FDCE f u_Axi_CDC/awFifo/popToPushGray_buffercc/buffers_1_reg[1]/D
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock cpu_clk rise edge) 0.000 0.000 r
|
|
clock source latency -1.947 -1.947
|
|
propagated clock network latency
|
|
1.600 -0.347
|
|
clock pessimism -0.228 -0.575
|
|
SLICE_X15Y69 FDCE (Hold_fdce_C_D) 0.071 -0.504 u_Axi_CDC/awFifo/popToPushGray_buffercc/buffers_1_reg[1]
|
|
-------------------------------------------------------------------
|
|
required time 0.504
|
|
arrival time -0.378
|
|
-------------------------------------------------------------------
|
|
slack 0.126
|
|
|
|
Slack (MET) : 0.126ns (arrival time - required time)
|
|
Source: u_Axi_CDC/bFifo/pushToPopGray_buffercc/buffers_0_reg[1]/C
|
|
(rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns})
|
|
Destination: u_Axi_CDC/bFifo/pushToPopGray_buffercc/buffers_1_reg[1]/D
|
|
(rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns})
|
|
Path Group: cpu_clk
|
|
Path Type: Hold (Min at Fast Process Corner)
|
|
Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns)
|
|
Data Path Delay: 0.197ns (logic 0.141ns (71.611%) route 0.056ns (28.389%))
|
|
Logic Levels: 0
|
|
Clock Path Skew: 0.000ns (DCD - SCD - CPR)
|
|
Destination Clock Delay (DCD): -0.338ns
|
|
Source Clock Delay (SCD): -0.568ns
|
|
Clock Pessimism Removal (CPR): 0.230ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock cpu_clk rise edge) 0.000 0.000 r
|
|
clock source latency -1.848 -1.848
|
|
propagated clock network latency
|
|
1.280 -0.568
|
|
SLICE_X19Y59 FDCE 0.000 -0.568 r u_Axi_CDC/bFifo/pushToPopGray_buffercc/buffers_0_reg[1]/C
|
|
SLICE_X19Y59 FDCE (Prop_fdce_C_Q) 0.141 -0.427 r u_Axi_CDC/bFifo/pushToPopGray_buffercc/buffers_0_reg[1]/Q
|
|
net (fo=1, routed) 0.056 -0.371 u_Axi_CDC/bFifo/pushToPopGray_buffercc/buffers_0[1]
|
|
SLICE_X19Y59 FDCE r u_Axi_CDC/bFifo/pushToPopGray_buffercc/buffers_1_reg[1]/D
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock cpu_clk rise edge) 0.000 0.000 r
|
|
clock source latency -1.947 -1.947
|
|
propagated clock network latency
|
|
1.609 -0.338
|
|
clock pessimism -0.230 -0.568
|
|
SLICE_X19Y59 FDCE (Hold_fdce_C_D) 0.071 -0.497 u_Axi_CDC/bFifo/pushToPopGray_buffercc/buffers_1_reg[1]
|
|
-------------------------------------------------------------------
|
|
required time 0.497
|
|
arrival time -0.371
|
|
-------------------------------------------------------------------
|
|
slack 0.126
|
|
|
|
Slack (MET) : 0.126ns (arrival time - required time)
|
|
Source: u_Axi_CDC/bFifo/pushToPopGray_buffercc/buffers_0_reg[1]/C
|
|
(rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns})
|
|
Destination: u_Axi_CDC/bFifo/pushToPopGray_buffercc/buffers_1_reg[1]/D
|
|
(rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns})
|
|
Path Group: cpu_clk
|
|
Path Type: Hold (Min at Fast Process Corner)
|
|
Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns)
|
|
Data Path Delay: 0.197ns (logic 0.141ns (71.611%) route 0.056ns (28.389%))
|
|
Logic Levels: 0
|
|
Clock Path Skew: 0.000ns (DCD - SCD - CPR)
|
|
Destination Clock Delay (DCD): -0.338ns
|
|
Source Clock Delay (SCD): -0.568ns
|
|
Clock Pessimism Removal (CPR): 0.230ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock cpu_clk rise edge) 0.000 0.000 r
|
|
clock source latency -1.848 -1.848
|
|
propagated clock network latency
|
|
1.280 -0.568
|
|
SLICE_X19Y59 FDCE 0.000 -0.568 r u_Axi_CDC/bFifo/pushToPopGray_buffercc/buffers_0_reg[1]/C
|
|
SLICE_X19Y59 FDCE (Prop_fdce_C_Q) 0.141 -0.427 f u_Axi_CDC/bFifo/pushToPopGray_buffercc/buffers_0_reg[1]/Q
|
|
net (fo=1, routed) 0.056 -0.371 u_Axi_CDC/bFifo/pushToPopGray_buffercc/buffers_0[1]
|
|
SLICE_X19Y59 FDCE f u_Axi_CDC/bFifo/pushToPopGray_buffercc/buffers_1_reg[1]/D
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock cpu_clk rise edge) 0.000 0.000 r
|
|
clock source latency -1.947 -1.947
|
|
propagated clock network latency
|
|
1.609 -0.338
|
|
clock pessimism -0.230 -0.568
|
|
SLICE_X19Y59 FDCE (Hold_fdce_C_D) 0.071 -0.497 u_Axi_CDC/bFifo/pushToPopGray_buffercc/buffers_1_reg[1]
|
|
-------------------------------------------------------------------
|
|
required time 0.497
|
|
arrival time -0.371
|
|
-------------------------------------------------------------------
|
|
slack 0.126
|
|
|
|
Slack (MET) : 0.126ns (arrival time - required time)
|
|
Source: u_Axi_CDC/rFifo/pushToPopGray_buffercc/buffers_0_reg[1]/C
|
|
(rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns})
|
|
Destination: u_Axi_CDC/rFifo/pushToPopGray_buffercc/buffers_1_reg[1]/D
|
|
(rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns})
|
|
Path Group: cpu_clk
|
|
Path Type: Hold (Min at Fast Process Corner)
|
|
Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns)
|
|
Data Path Delay: 0.197ns (logic 0.141ns (71.611%) route 0.056ns (28.389%))
|
|
Logic Levels: 0
|
|
Clock Path Skew: 0.000ns (DCD - SCD - CPR)
|
|
Destination Clock Delay (DCD): -0.323ns
|
|
Source Clock Delay (SCD): -0.552ns
|
|
Clock Pessimism Removal (CPR): 0.229ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock cpu_clk rise edge) 0.000 0.000 r
|
|
clock source latency -1.848 -1.848
|
|
propagated clock network latency
|
|
1.296 -0.552
|
|
SLICE_X5Y76 FDCE 0.000 -0.552 r u_Axi_CDC/rFifo/pushToPopGray_buffercc/buffers_0_reg[1]/C
|
|
SLICE_X5Y76 FDCE (Prop_fdce_C_Q) 0.141 -0.411 r u_Axi_CDC/rFifo/pushToPopGray_buffercc/buffers_0_reg[1]/Q
|
|
net (fo=1, routed) 0.056 -0.355 u_Axi_CDC/rFifo/pushToPopGray_buffercc/buffers_0[1]
|
|
SLICE_X5Y76 FDCE r u_Axi_CDC/rFifo/pushToPopGray_buffercc/buffers_1_reg[1]/D
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock cpu_clk rise edge) 0.000 0.000 r
|
|
clock source latency -1.947 -1.947
|
|
propagated clock network latency
|
|
1.624 -0.323
|
|
clock pessimism -0.229 -0.552
|
|
SLICE_X5Y76 FDCE (Hold_fdce_C_D) 0.071 -0.481 u_Axi_CDC/rFifo/pushToPopGray_buffercc/buffers_1_reg[1]
|
|
-------------------------------------------------------------------
|
|
required time 0.481
|
|
arrival time -0.355
|
|
-------------------------------------------------------------------
|
|
slack 0.126
|
|
|
|
Slack (MET) : 0.126ns (arrival time - required time)
|
|
Source: u_Axi_CDC/rFifo/pushToPopGray_buffercc/buffers_0_reg[1]/C
|
|
(rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns})
|
|
Destination: u_Axi_CDC/rFifo/pushToPopGray_buffercc/buffers_1_reg[1]/D
|
|
(rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns})
|
|
Path Group: cpu_clk
|
|
Path Type: Hold (Min at Fast Process Corner)
|
|
Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns)
|
|
Data Path Delay: 0.197ns (logic 0.141ns (71.611%) route 0.056ns (28.389%))
|
|
Logic Levels: 0
|
|
Clock Path Skew: 0.000ns (DCD - SCD - CPR)
|
|
Destination Clock Delay (DCD): -0.323ns
|
|
Source Clock Delay (SCD): -0.552ns
|
|
Clock Pessimism Removal (CPR): 0.229ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock cpu_clk rise edge) 0.000 0.000 r
|
|
clock source latency -1.848 -1.848
|
|
propagated clock network latency
|
|
1.296 -0.552
|
|
SLICE_X5Y76 FDCE 0.000 -0.552 r u_Axi_CDC/rFifo/pushToPopGray_buffercc/buffers_0_reg[1]/C
|
|
SLICE_X5Y76 FDCE (Prop_fdce_C_Q) 0.141 -0.411 f u_Axi_CDC/rFifo/pushToPopGray_buffercc/buffers_0_reg[1]/Q
|
|
net (fo=1, routed) 0.056 -0.355 u_Axi_CDC/rFifo/pushToPopGray_buffercc/buffers_0[1]
|
|
SLICE_X5Y76 FDCE f u_Axi_CDC/rFifo/pushToPopGray_buffercc/buffers_1_reg[1]/D
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock cpu_clk rise edge) 0.000 0.000 r
|
|
clock source latency -1.947 -1.947
|
|
propagated clock network latency
|
|
1.624 -0.323
|
|
clock pessimism -0.229 -0.552
|
|
SLICE_X5Y76 FDCE (Hold_fdce_C_D) 0.071 -0.481 u_Axi_CDC/rFifo/pushToPopGray_buffercc/buffers_1_reg[1]
|
|
-------------------------------------------------------------------
|
|
required time 0.481
|
|
arrival time -0.355
|
|
-------------------------------------------------------------------
|
|
slack 0.126
|
|
|
|
Slack (MET) : 0.128ns (arrival time - required time)
|
|
Source: u_Axi_CDC/wFifo/popToPushGray_buffercc/buffers_0_reg[1]/C
|
|
(rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns})
|
|
Destination: u_Axi_CDC/wFifo/popToPushGray_buffercc/buffers_1_reg[1]/D
|
|
(rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns})
|
|
Path Group: cpu_clk
|
|
Path Type: Hold (Min at Fast Process Corner)
|
|
Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns)
|
|
Data Path Delay: 0.199ns (logic 0.141ns (70.953%) route 0.058ns (29.047%))
|
|
Logic Levels: 0
|
|
Clock Path Skew: 0.000ns (DCD - SCD - CPR)
|
|
Destination Clock Delay (DCD): -0.229ns
|
|
Source Clock Delay (SCD): -0.465ns
|
|
Clock Pessimism Removal (CPR): 0.236ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock cpu_clk rise edge) 0.000 0.000 r
|
|
clock source latency -1.848 -1.848
|
|
propagated clock network latency
|
|
1.384 -0.465
|
|
SLICE_X0Y49 FDCE 0.000 -0.465 r u_Axi_CDC/wFifo/popToPushGray_buffercc/buffers_0_reg[1]/C
|
|
SLICE_X0Y49 FDCE (Prop_fdce_C_Q) 0.141 -0.324 r u_Axi_CDC/wFifo/popToPushGray_buffercc/buffers_0_reg[1]/Q
|
|
net (fo=1, routed) 0.058 -0.266 u_Axi_CDC/wFifo/popToPushGray_buffercc/buffers_0[1]
|
|
SLICE_X0Y49 FDCE r u_Axi_CDC/wFifo/popToPushGray_buffercc/buffers_1_reg[1]/D
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock cpu_clk rise edge) 0.000 0.000 r
|
|
clock source latency -1.947 -1.947
|
|
propagated clock network latency
|
|
1.718 -0.229
|
|
clock pessimism -0.236 -0.465
|
|
SLICE_X0Y49 FDCE (Hold_fdce_C_D) 0.071 -0.394 u_Axi_CDC/wFifo/popToPushGray_buffercc/buffers_1_reg[1]
|
|
-------------------------------------------------------------------
|
|
required time 0.394
|
|
arrival time -0.266
|
|
-------------------------------------------------------------------
|
|
slack 0.128
|
|
|
|
Slack (MET) : 0.128ns (arrival time - required time)
|
|
Source: u_Axi_CDC/wFifo/popToPushGray_buffercc/buffers_0_reg[1]/C
|
|
(rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns})
|
|
Destination: u_Axi_CDC/wFifo/popToPushGray_buffercc/buffers_1_reg[1]/D
|
|
(rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns})
|
|
Path Group: cpu_clk
|
|
Path Type: Hold (Min at Fast Process Corner)
|
|
Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns)
|
|
Data Path Delay: 0.199ns (logic 0.141ns (70.953%) route 0.058ns (29.047%))
|
|
Logic Levels: 0
|
|
Clock Path Skew: 0.000ns (DCD - SCD - CPR)
|
|
Destination Clock Delay (DCD): -0.229ns
|
|
Source Clock Delay (SCD): -0.465ns
|
|
Clock Pessimism Removal (CPR): 0.236ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock cpu_clk rise edge) 0.000 0.000 r
|
|
clock source latency -1.848 -1.848
|
|
propagated clock network latency
|
|
1.384 -0.465
|
|
SLICE_X0Y49 FDCE 0.000 -0.465 r u_Axi_CDC/wFifo/popToPushGray_buffercc/buffers_0_reg[1]/C
|
|
SLICE_X0Y49 FDCE (Prop_fdce_C_Q) 0.141 -0.324 f u_Axi_CDC/wFifo/popToPushGray_buffercc/buffers_0_reg[1]/Q
|
|
net (fo=1, routed) 0.058 -0.266 u_Axi_CDC/wFifo/popToPushGray_buffercc/buffers_0[1]
|
|
SLICE_X0Y49 FDCE f u_Axi_CDC/wFifo/popToPushGray_buffercc/buffers_1_reg[1]/D
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock cpu_clk rise edge) 0.000 0.000 r
|
|
clock source latency -1.947 -1.947
|
|
propagated clock network latency
|
|
1.718 -0.229
|
|
clock pessimism -0.236 -0.465
|
|
SLICE_X0Y49 FDCE (Hold_fdce_C_D) 0.071 -0.394 u_Axi_CDC/wFifo/popToPushGray_buffercc/buffers_1_reg[1]
|
|
-------------------------------------------------------------------
|
|
required time 0.394
|
|
arrival time -0.266
|
|
-------------------------------------------------------------------
|
|
slack 0.128
|
|
|
|
Slack (MET) : 0.128ns (arrival time - required time)
|
|
Source: u_cpu/u_csr/csr_tlbelo1_reg[15]/C
|
|
(rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns})
|
|
Destination: u_cpu/addr_trans/tlb_entry/tlb_ppn1_reg_r1_0_31_6_11/RAMA_D1/I
|
|
(rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns})
|
|
Path Group: cpu_clk
|
|
Path Type: Hold (Min at Fast Process Corner)
|
|
Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns)
|
|
Data Path Delay: 0.265ns (logic 0.141ns (53.167%) route 0.124ns (46.833%))
|
|
Logic Levels: 0
|
|
Clock Path Skew: 0.017ns (DCD - SCD - CPR)
|
|
Destination Clock Delay (DCD): -0.275ns
|
|
Source Clock Delay (SCD): -0.510ns
|
|
Clock Pessimism Removal (CPR): 0.218ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock cpu_clk rise edge) 0.000 0.000 r
|
|
clock source latency -1.848 -1.848
|
|
propagated clock network latency
|
|
1.339 -0.510
|
|
SLICE_X41Y37 FDRE 0.000 -0.510 r u_cpu/u_csr/csr_tlbelo1_reg[15]/C
|
|
SLICE_X41Y37 FDRE (Prop_fdre_C_Q) 0.141 -0.369 r u_cpu/u_csr/csr_tlbelo1_reg[15]/Q
|
|
net (fo=4, routed) 0.124 -0.245 u_cpu/addr_trans/tlb_entry/tlb_ppn1_reg_r1_0_31_6_11/DIA1
|
|
SLICE_X40Y38 RAMD32 r u_cpu/addr_trans/tlb_entry/tlb_ppn1_reg_r1_0_31_6_11/RAMA_D1/I
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock cpu_clk rise edge) 0.000 0.000 r
|
|
clock source latency -1.947 -1.947
|
|
propagated clock network latency
|
|
1.672 -0.275
|
|
clock pessimism -0.218 -0.493
|
|
SLICE_X40Y38 RAMD32 (Hold_ramd32_CLK_I)
|
|
0.120 -0.373 u_cpu/addr_trans/tlb_entry/tlb_ppn1_reg_r1_0_31_6_11/RAMA_D1
|
|
-------------------------------------------------------------------
|
|
required time 0.373
|
|
arrival time -0.245
|
|
-------------------------------------------------------------------
|
|
slack 0.128
|
|
|
|
Slack (MET) : 0.128ns (arrival time - required time)
|
|
Source: u_cpu/u_csr/csr_tlbelo1_reg[15]/C
|
|
(rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns})
|
|
Destination: u_cpu/addr_trans/tlb_entry/tlb_ppn1_reg_r1_0_31_6_11/RAMA_D1/I
|
|
(rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns})
|
|
Path Group: cpu_clk
|
|
Path Type: Hold (Min at Fast Process Corner)
|
|
Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns)
|
|
Data Path Delay: 0.265ns (logic 0.141ns (53.167%) route 0.124ns (46.833%))
|
|
Logic Levels: 0
|
|
Clock Path Skew: 0.017ns (DCD - SCD - CPR)
|
|
Destination Clock Delay (DCD): -0.275ns
|
|
Source Clock Delay (SCD): -0.510ns
|
|
Clock Pessimism Removal (CPR): 0.218ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock cpu_clk rise edge) 0.000 0.000 r
|
|
clock source latency -1.848 -1.848
|
|
propagated clock network latency
|
|
1.339 -0.510
|
|
SLICE_X41Y37 FDRE 0.000 -0.510 r u_cpu/u_csr/csr_tlbelo1_reg[15]/C
|
|
SLICE_X41Y37 FDRE (Prop_fdre_C_Q) 0.141 -0.369 f u_cpu/u_csr/csr_tlbelo1_reg[15]/Q
|
|
net (fo=4, routed) 0.124 -0.245 u_cpu/addr_trans/tlb_entry/tlb_ppn1_reg_r1_0_31_6_11/DIA1
|
|
SLICE_X40Y38 RAMD32 f u_cpu/addr_trans/tlb_entry/tlb_ppn1_reg_r1_0_31_6_11/RAMA_D1/I
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock cpu_clk rise edge) 0.000 0.000 r
|
|
clock source latency -1.947 -1.947
|
|
propagated clock network latency
|
|
1.672 -0.275
|
|
clock pessimism -0.218 -0.493
|
|
SLICE_X40Y38 RAMD32 (Hold_ramd32_CLK_I)
|
|
0.120 -0.373 u_cpu/addr_trans/tlb_entry/tlb_ppn1_reg_r1_0_31_6_11/RAMA_D1
|
|
-------------------------------------------------------------------
|
|
required time 0.373
|
|
arrival time -0.245
|
|
-------------------------------------------------------------------
|
|
slack 0.128
|
|
|
|
Slack (MET) : 0.128ns (arrival time - required time)
|
|
Source: u_cpu/u_csr/csr_tlbelo1_reg[27]/C
|
|
(rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns})
|
|
Destination: u_cpu/addr_trans/tlb_entry/tlb_ppn1_reg_r1_0_31_18_19/RAMA_D1/I
|
|
(rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns})
|
|
Path Group: cpu_clk
|
|
Path Type: Hold (Min at Fast Process Corner)
|
|
Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns)
|
|
Data Path Delay: 0.263ns (logic 0.141ns (53.571%) route 0.122ns (46.429%))
|
|
Logic Levels: 0
|
|
Clock Path Skew: 0.015ns (DCD - SCD - CPR)
|
|
Destination Clock Delay (DCD): -0.309ns
|
|
Source Clock Delay (SCD): -0.541ns
|
|
Clock Pessimism Removal (CPR): 0.217ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock cpu_clk rise edge) 0.000 0.000 r
|
|
clock source latency -1.848 -1.848
|
|
propagated clock network latency
|
|
1.308 -0.541
|
|
SLICE_X47Y35 FDRE 0.000 -0.541 r u_cpu/u_csr/csr_tlbelo1_reg[27]/C
|
|
SLICE_X47Y35 FDRE (Prop_fdre_C_Q) 0.141 -0.400 r u_cpu/u_csr/csr_tlbelo1_reg[27]/Q
|
|
net (fo=4, routed) 0.122 -0.278 u_cpu/addr_trans/tlb_entry/tlb_ppn1_reg_r1_0_31_18_19/DIA1
|
|
SLICE_X46Y36 RAMD32 r u_cpu/addr_trans/tlb_entry/tlb_ppn1_reg_r1_0_31_18_19/RAMA_D1/I
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock cpu_clk rise edge) 0.000 0.000 r
|
|
clock source latency -1.947 -1.947
|
|
propagated clock network latency
|
|
1.638 -0.309
|
|
clock pessimism -0.217 -0.526
|
|
SLICE_X46Y36 RAMD32 (Hold_ramd32_CLK_I)
|
|
0.120 -0.406 u_cpu/addr_trans/tlb_entry/tlb_ppn1_reg_r1_0_31_18_19/RAMA_D1
|
|
-------------------------------------------------------------------
|
|
required time 0.406
|
|
arrival time -0.278
|
|
-------------------------------------------------------------------
|
|
slack 0.128
|
|
|
|
Slack (MET) : 0.128ns (arrival time - required time)
|
|
Source: u_cpu/u_csr/csr_tlbelo1_reg[27]/C
|
|
(rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns})
|
|
Destination: u_cpu/addr_trans/tlb_entry/tlb_ppn1_reg_r1_0_31_18_19/RAMA_D1/I
|
|
(rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns})
|
|
Path Group: cpu_clk
|
|
Path Type: Hold (Min at Fast Process Corner)
|
|
Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns)
|
|
Data Path Delay: 0.263ns (logic 0.141ns (53.571%) route 0.122ns (46.429%))
|
|
Logic Levels: 0
|
|
Clock Path Skew: 0.015ns (DCD - SCD - CPR)
|
|
Destination Clock Delay (DCD): -0.309ns
|
|
Source Clock Delay (SCD): -0.541ns
|
|
Clock Pessimism Removal (CPR): 0.217ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock cpu_clk rise edge) 0.000 0.000 r
|
|
clock source latency -1.848 -1.848
|
|
propagated clock network latency
|
|
1.308 -0.541
|
|
SLICE_X47Y35 FDRE 0.000 -0.541 r u_cpu/u_csr/csr_tlbelo1_reg[27]/C
|
|
SLICE_X47Y35 FDRE (Prop_fdre_C_Q) 0.141 -0.400 f u_cpu/u_csr/csr_tlbelo1_reg[27]/Q
|
|
net (fo=4, routed) 0.122 -0.278 u_cpu/addr_trans/tlb_entry/tlb_ppn1_reg_r1_0_31_18_19/DIA1
|
|
SLICE_X46Y36 RAMD32 f u_cpu/addr_trans/tlb_entry/tlb_ppn1_reg_r1_0_31_18_19/RAMA_D1/I
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock cpu_clk rise edge) 0.000 0.000 r
|
|
clock source latency -1.947 -1.947
|
|
propagated clock network latency
|
|
1.638 -0.309
|
|
clock pessimism -0.217 -0.526
|
|
SLICE_X46Y36 RAMD32 (Hold_ramd32_CLK_I)
|
|
0.120 -0.406 u_cpu/addr_trans/tlb_entry/tlb_ppn1_reg_r1_0_31_18_19/RAMA_D1
|
|
-------------------------------------------------------------------
|
|
required time 0.406
|
|
arrival time -0.278
|
|
-------------------------------------------------------------------
|
|
slack 0.128
|
|
|
|
Slack (MET) : 0.131ns (arrival time - required time)
|
|
Source: u_Axi_CDC/bFifo/bufferCC_12/buffers_0_reg/C
|
|
(rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns})
|
|
Destination: u_Axi_CDC/bFifo/bufferCC_12/buffers_1_reg/D
|
|
(rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns})
|
|
Path Group: cpu_clk
|
|
Path Type: Hold (Min at Fast Process Corner)
|
|
Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns)
|
|
Data Path Delay: 0.206ns (logic 0.141ns (68.336%) route 0.065ns (31.664%))
|
|
Logic Levels: 0
|
|
Clock Path Skew: 0.000ns (DCD - SCD - CPR)
|
|
Destination Clock Delay (DCD): -0.345ns
|
|
Source Clock Delay (SCD): -0.575ns
|
|
Clock Pessimism Removal (CPR): 0.230ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock cpu_clk rise edge) 0.000 0.000 r
|
|
clock source latency -1.848 -1.848
|
|
propagated clock network latency
|
|
1.273 -0.575
|
|
SLICE_X30Y58 FDCE 0.000 -0.575 r u_Axi_CDC/bFifo/bufferCC_12/buffers_0_reg/C
|
|
SLICE_X30Y58 FDCE (Prop_fdce_C_Q) 0.141 -0.434 r u_Axi_CDC/bFifo/bufferCC_12/buffers_0_reg/Q
|
|
net (fo=1, routed) 0.065 -0.369 u_Axi_CDC/bFifo/bufferCC_12/buffers_0
|
|
SLICE_X30Y58 FDCE r u_Axi_CDC/bFifo/bufferCC_12/buffers_1_reg/D
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock cpu_clk rise edge) 0.000 0.000 r
|
|
clock source latency -1.947 -1.947
|
|
propagated clock network latency
|
|
1.602 -0.345
|
|
clock pessimism -0.230 -0.575
|
|
SLICE_X30Y58 FDCE (Hold_fdce_C_D) 0.075 -0.500 u_Axi_CDC/bFifo/bufferCC_12/buffers_1_reg
|
|
-------------------------------------------------------------------
|
|
required time 0.500
|
|
arrival time -0.369
|
|
-------------------------------------------------------------------
|
|
slack 0.131
|
|
|
|
Slack (MET) : 0.131ns (arrival time - required time)
|
|
Source: u_Axi_CDC/bFifo/bufferCC_12/buffers_0_reg/C
|
|
(rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns})
|
|
Destination: u_Axi_CDC/bFifo/bufferCC_12/buffers_1_reg/D
|
|
(rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns})
|
|
Path Group: cpu_clk
|
|
Path Type: Hold (Min at Fast Process Corner)
|
|
Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns)
|
|
Data Path Delay: 0.206ns (logic 0.141ns (68.336%) route 0.065ns (31.664%))
|
|
Logic Levels: 0
|
|
Clock Path Skew: 0.000ns (DCD - SCD - CPR)
|
|
Destination Clock Delay (DCD): -0.345ns
|
|
Source Clock Delay (SCD): -0.575ns
|
|
Clock Pessimism Removal (CPR): 0.230ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock cpu_clk rise edge) 0.000 0.000 r
|
|
clock source latency -1.848 -1.848
|
|
propagated clock network latency
|
|
1.273 -0.575
|
|
SLICE_X30Y58 FDCE 0.000 -0.575 r u_Axi_CDC/bFifo/bufferCC_12/buffers_0_reg/C
|
|
SLICE_X30Y58 FDCE (Prop_fdce_C_Q) 0.141 -0.434 f u_Axi_CDC/bFifo/bufferCC_12/buffers_0_reg/Q
|
|
net (fo=1, routed) 0.065 -0.369 u_Axi_CDC/bFifo/bufferCC_12/buffers_0
|
|
SLICE_X30Y58 FDCE f u_Axi_CDC/bFifo/bufferCC_12/buffers_1_reg/D
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock cpu_clk rise edge) 0.000 0.000 r
|
|
clock source latency -1.947 -1.947
|
|
propagated clock network latency
|
|
1.602 -0.345
|
|
clock pessimism -0.230 -0.575
|
|
SLICE_X30Y58 FDCE (Hold_fdce_C_D) 0.075 -0.500 u_Axi_CDC/bFifo/bufferCC_12/buffers_1_reg
|
|
-------------------------------------------------------------------
|
|
required time 0.500
|
|
arrival time -0.369
|
|
-------------------------------------------------------------------
|
|
slack 0.131
|
|
|
|
Slack (MET) : 0.131ns (arrival time - required time)
|
|
Source: u_Axi_CDC/wFifo/popToPushGray_buffercc/buffers_0_reg[0]/C
|
|
(rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns})
|
|
Destination: u_Axi_CDC/wFifo/popToPushGray_buffercc/buffers_1_reg[0]/D
|
|
(rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns})
|
|
Path Group: cpu_clk
|
|
Path Type: Hold (Min at Fast Process Corner)
|
|
Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns)
|
|
Data Path Delay: 0.206ns (logic 0.141ns (68.336%) route 0.065ns (31.664%))
|
|
Logic Levels: 0
|
|
Clock Path Skew: 0.000ns (DCD - SCD - CPR)
|
|
Destination Clock Delay (DCD): -0.229ns
|
|
Source Clock Delay (SCD): -0.465ns
|
|
Clock Pessimism Removal (CPR): 0.236ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock cpu_clk rise edge) 0.000 0.000 r
|
|
clock source latency -1.848 -1.848
|
|
propagated clock network latency
|
|
1.384 -0.465
|
|
SLICE_X0Y49 FDCE 0.000 -0.465 r u_Axi_CDC/wFifo/popToPushGray_buffercc/buffers_0_reg[0]/C
|
|
SLICE_X0Y49 FDCE (Prop_fdce_C_Q) 0.141 -0.324 r u_Axi_CDC/wFifo/popToPushGray_buffercc/buffers_0_reg[0]/Q
|
|
net (fo=1, routed) 0.065 -0.258 u_Axi_CDC/wFifo/popToPushGray_buffercc/buffers_0[0]
|
|
SLICE_X0Y49 FDCE r u_Axi_CDC/wFifo/popToPushGray_buffercc/buffers_1_reg[0]/D
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock cpu_clk rise edge) 0.000 0.000 r
|
|
clock source latency -1.947 -1.947
|
|
propagated clock network latency
|
|
1.718 -0.229
|
|
clock pessimism -0.236 -0.465
|
|
SLICE_X0Y49 FDCE (Hold_fdce_C_D) 0.075 -0.390 u_Axi_CDC/wFifo/popToPushGray_buffercc/buffers_1_reg[0]
|
|
-------------------------------------------------------------------
|
|
required time 0.390
|
|
arrival time -0.258
|
|
-------------------------------------------------------------------
|
|
slack 0.131
|
|
|
|
Slack (MET) : 0.131ns (arrival time - required time)
|
|
Source: u_Axi_CDC/wFifo/popToPushGray_buffercc/buffers_0_reg[0]/C
|
|
(rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns})
|
|
Destination: u_Axi_CDC/wFifo/popToPushGray_buffercc/buffers_1_reg[0]/D
|
|
(rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns})
|
|
Path Group: cpu_clk
|
|
Path Type: Hold (Min at Fast Process Corner)
|
|
Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns)
|
|
Data Path Delay: 0.206ns (logic 0.141ns (68.336%) route 0.065ns (31.664%))
|
|
Logic Levels: 0
|
|
Clock Path Skew: 0.000ns (DCD - SCD - CPR)
|
|
Destination Clock Delay (DCD): -0.229ns
|
|
Source Clock Delay (SCD): -0.465ns
|
|
Clock Pessimism Removal (CPR): 0.236ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock cpu_clk rise edge) 0.000 0.000 r
|
|
clock source latency -1.848 -1.848
|
|
propagated clock network latency
|
|
1.384 -0.465
|
|
SLICE_X0Y49 FDCE 0.000 -0.465 r u_Axi_CDC/wFifo/popToPushGray_buffercc/buffers_0_reg[0]/C
|
|
SLICE_X0Y49 FDCE (Prop_fdce_C_Q) 0.141 -0.324 f u_Axi_CDC/wFifo/popToPushGray_buffercc/buffers_0_reg[0]/Q
|
|
net (fo=1, routed) 0.065 -0.258 u_Axi_CDC/wFifo/popToPushGray_buffercc/buffers_0[0]
|
|
SLICE_X0Y49 FDCE f u_Axi_CDC/wFifo/popToPushGray_buffercc/buffers_1_reg[0]/D
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock cpu_clk rise edge) 0.000 0.000 r
|
|
clock source latency -1.947 -1.947
|
|
propagated clock network latency
|
|
1.718 -0.229
|
|
clock pessimism -0.236 -0.465
|
|
SLICE_X0Y49 FDCE (Hold_fdce_C_D) 0.075 -0.390 u_Axi_CDC/wFifo/popToPushGray_buffercc/buffers_1_reg[0]
|
|
-------------------------------------------------------------------
|
|
required time 0.390
|
|
arrival time -0.258
|
|
-------------------------------------------------------------------
|
|
slack 0.131
|
|
|
|
Slack (MET) : 0.132ns (arrival time - required time)
|
|
Source: u_cpu/u_csr/csr_tlbelo0_reg[20]/C
|
|
(rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns})
|
|
Destination: u_cpu/addr_trans/tlb_entry/tlb_ppn0_reg_r3_0_31_12_17/RAMA/I
|
|
(rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns})
|
|
Path Group: cpu_clk
|
|
Path Type: Hold (Min at Fast Process Corner)
|
|
Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns)
|
|
Data Path Delay: 0.294ns (logic 0.141ns (47.970%) route 0.153ns (52.030%))
|
|
Logic Levels: 0
|
|
Clock Path Skew: 0.015ns (DCD - SCD - CPR)
|
|
Destination Clock Delay (DCD): -0.310ns
|
|
Source Clock Delay (SCD): -0.542ns
|
|
Clock Pessimism Removal (CPR): 0.217ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock cpu_clk rise edge) 0.000 0.000 r
|
|
clock source latency -1.848 -1.848
|
|
propagated clock network latency
|
|
1.307 -0.542
|
|
SLICE_X43Y32 FDRE 0.000 -0.542 r u_cpu/u_csr/csr_tlbelo0_reg[20]/C
|
|
SLICE_X43Y32 FDRE (Prop_fdre_C_Q) 0.141 -0.401 r u_cpu/u_csr/csr_tlbelo0_reg[20]/Q
|
|
net (fo=4, routed) 0.153 -0.248 u_cpu/addr_trans/tlb_entry/tlb_ppn0_reg_r3_0_31_12_17/DIA0
|
|
SLICE_X42Y33 RAMD32 r u_cpu/addr_trans/tlb_entry/tlb_ppn0_reg_r3_0_31_12_17/RAMA/I
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock cpu_clk rise edge) 0.000 0.000 r
|
|
clock source latency -1.947 -1.947
|
|
propagated clock network latency
|
|
1.637 -0.310
|
|
clock pessimism -0.217 -0.527
|
|
SLICE_X42Y33 RAMD32 (Hold_ramd32_CLK_I)
|
|
0.147 -0.380 u_cpu/addr_trans/tlb_entry/tlb_ppn0_reg_r3_0_31_12_17/RAMA
|
|
-------------------------------------------------------------------
|
|
required time 0.380
|
|
arrival time -0.248
|
|
-------------------------------------------------------------------
|
|
slack 0.132
|
|
|
|
Slack (MET) : 0.132ns (arrival time - required time)
|
|
Source: u_cpu/u_csr/csr_tlbelo0_reg[20]/C
|
|
(rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns})
|
|
Destination: u_cpu/addr_trans/tlb_entry/tlb_ppn0_reg_r3_0_31_12_17/RAMA/I
|
|
(rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns})
|
|
Path Group: cpu_clk
|
|
Path Type: Hold (Min at Fast Process Corner)
|
|
Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns)
|
|
Data Path Delay: 0.294ns (logic 0.141ns (47.970%) route 0.153ns (52.030%))
|
|
Logic Levels: 0
|
|
Clock Path Skew: 0.015ns (DCD - SCD - CPR)
|
|
Destination Clock Delay (DCD): -0.310ns
|
|
Source Clock Delay (SCD): -0.542ns
|
|
Clock Pessimism Removal (CPR): 0.217ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock cpu_clk rise edge) 0.000 0.000 r
|
|
clock source latency -1.848 -1.848
|
|
propagated clock network latency
|
|
1.307 -0.542
|
|
SLICE_X43Y32 FDRE 0.000 -0.542 r u_cpu/u_csr/csr_tlbelo0_reg[20]/C
|
|
SLICE_X43Y32 FDRE (Prop_fdre_C_Q) 0.141 -0.401 f u_cpu/u_csr/csr_tlbelo0_reg[20]/Q
|
|
net (fo=4, routed) 0.153 -0.248 u_cpu/addr_trans/tlb_entry/tlb_ppn0_reg_r3_0_31_12_17/DIA0
|
|
SLICE_X42Y33 RAMD32 f u_cpu/addr_trans/tlb_entry/tlb_ppn0_reg_r3_0_31_12_17/RAMA/I
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock cpu_clk rise edge) 0.000 0.000 r
|
|
clock source latency -1.947 -1.947
|
|
propagated clock network latency
|
|
1.637 -0.310
|
|
clock pessimism -0.217 -0.527
|
|
SLICE_X42Y33 RAMD32 (Hold_ramd32_CLK_I)
|
|
0.147 -0.380 u_cpu/addr_trans/tlb_entry/tlb_ppn0_reg_r3_0_31_12_17/RAMA
|
|
-------------------------------------------------------------------
|
|
required time 0.380
|
|
arrival time -0.248
|
|
-------------------------------------------------------------------
|
|
slack 0.132
|
|
|
|
Slack (MET) : 0.133ns (arrival time - required time)
|
|
Source: u_cpu/axi_bridge/wdata_reg[0]/C
|
|
(rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns})
|
|
Destination: u_Axi_CDC/wFifo/ram_reg_0_7_0_5/RAMA/I
|
|
(rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns})
|
|
Path Group: cpu_clk
|
|
Path Type: Hold (Min at Fast Process Corner)
|
|
Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns)
|
|
Data Path Delay: 0.296ns (logic 0.141ns (47.613%) route 0.155ns (52.387%))
|
|
Logic Levels: 0
|
|
Clock Path Skew: 0.016ns (DCD - SCD - CPR)
|
|
Destination Clock Delay (DCD): -0.232ns
|
|
Source Clock Delay (SCD): -0.468ns
|
|
Clock Pessimism Removal (CPR): 0.220ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock cpu_clk rise edge) 0.000 0.000 r
|
|
clock source latency -1.848 -1.848
|
|
propagated clock network latency
|
|
1.381 -0.468
|
|
SLICE_X5Y45 FDRE 0.000 -0.468 r u_cpu/axi_bridge/wdata_reg[0]/C
|
|
SLICE_X5Y45 FDRE (Prop_fdre_C_Q) 0.141 -0.327 r u_cpu/axi_bridge/wdata_reg[0]/Q
|
|
net (fo=1, routed) 0.155 -0.172 u_Axi_CDC/wFifo/ram_reg_0_7_0_5/DIA0
|
|
SLICE_X6Y45 RAMD32 r u_Axi_CDC/wFifo/ram_reg_0_7_0_5/RAMA/I
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock cpu_clk rise edge) 0.000 0.000 r
|
|
clock source latency -1.947 -1.947
|
|
propagated clock network latency
|
|
1.715 -0.232
|
|
clock pessimism -0.220 -0.452
|
|
SLICE_X6Y45 RAMD32 (Hold_ramd32_CLK_I)
|
|
0.147 -0.305 u_Axi_CDC/wFifo/ram_reg_0_7_0_5/RAMA
|
|
-------------------------------------------------------------------
|
|
required time 0.305
|
|
arrival time -0.172
|
|
-------------------------------------------------------------------
|
|
slack 0.133
|
|
|
|
Slack (MET) : 0.133ns (arrival time - required time)
|
|
Source: u_cpu/axi_bridge/wdata_reg[0]/C
|
|
(rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns})
|
|
Destination: u_Axi_CDC/wFifo/ram_reg_0_7_0_5/RAMA/I
|
|
(rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns})
|
|
Path Group: cpu_clk
|
|
Path Type: Hold (Min at Fast Process Corner)
|
|
Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns)
|
|
Data Path Delay: 0.296ns (logic 0.141ns (47.613%) route 0.155ns (52.387%))
|
|
Logic Levels: 0
|
|
Clock Path Skew: 0.016ns (DCD - SCD - CPR)
|
|
Destination Clock Delay (DCD): -0.232ns
|
|
Source Clock Delay (SCD): -0.468ns
|
|
Clock Pessimism Removal (CPR): 0.220ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock cpu_clk rise edge) 0.000 0.000 r
|
|
clock source latency -1.848 -1.848
|
|
propagated clock network latency
|
|
1.381 -0.468
|
|
SLICE_X5Y45 FDRE 0.000 -0.468 r u_cpu/axi_bridge/wdata_reg[0]/C
|
|
SLICE_X5Y45 FDRE (Prop_fdre_C_Q) 0.141 -0.327 f u_cpu/axi_bridge/wdata_reg[0]/Q
|
|
net (fo=1, routed) 0.155 -0.172 u_Axi_CDC/wFifo/ram_reg_0_7_0_5/DIA0
|
|
SLICE_X6Y45 RAMD32 f u_Axi_CDC/wFifo/ram_reg_0_7_0_5/RAMA/I
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock cpu_clk rise edge) 0.000 0.000 r
|
|
clock source latency -1.947 -1.947
|
|
propagated clock network latency
|
|
1.715 -0.232
|
|
clock pessimism -0.220 -0.452
|
|
SLICE_X6Y45 RAMD32 (Hold_ramd32_CLK_I)
|
|
0.147 -0.305 u_Axi_CDC/wFifo/ram_reg_0_7_0_5/RAMA
|
|
-------------------------------------------------------------------
|
|
required time 0.305
|
|
arrival time -0.172
|
|
-------------------------------------------------------------------
|
|
slack 0.133
|
|
|
|
Slack (MET) : 0.134ns (arrival time - required time)
|
|
Source: u_cpu/u_csr/csr_tlbelo1_reg[2]/C
|
|
(rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns})
|
|
Destination: u_cpu/addr_trans/tlb_entry/tlb_plv1_reg_r2_0_31_0_0/DP/I
|
|
(rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns})
|
|
Path Group: cpu_clk
|
|
Path Type: Hold (Min at Fast Process Corner)
|
|
Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns)
|
|
Data Path Delay: 0.264ns (logic 0.141ns (53.394%) route 0.123ns (46.606%))
|
|
Logic Levels: 0
|
|
Clock Path Skew: 0.016ns (DCD - SCD - CPR)
|
|
Destination Clock Delay (DCD): -0.275ns
|
|
Source Clock Delay (SCD): -0.509ns
|
|
Clock Pessimism Removal (CPR): 0.218ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock cpu_clk rise edge) 0.000 0.000 r
|
|
clock source latency -1.848 -1.848
|
|
propagated clock network latency
|
|
1.340 -0.509
|
|
SLICE_X39Y39 FDRE 0.000 -0.509 r u_cpu/u_csr/csr_tlbelo1_reg[2]/C
|
|
SLICE_X39Y39 FDRE (Prop_fdre_C_Q) 0.141 -0.368 r u_cpu/u_csr/csr_tlbelo1_reg[2]/Q
|
|
net (fo=7, routed) 0.123 -0.245 u_cpu/addr_trans/tlb_entry/tlb_plv1_reg_r2_0_31_0_0/D
|
|
SLICE_X40Y39 RAMD32 r u_cpu/addr_trans/tlb_entry/tlb_plv1_reg_r2_0_31_0_0/DP/I
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock cpu_clk rise edge) 0.000 0.000 r
|
|
clock source latency -1.947 -1.947
|
|
propagated clock network latency
|
|
1.672 -0.275
|
|
clock pessimism -0.218 -0.493
|
|
SLICE_X40Y39 RAMD32 (Hold_ramd32_CLK_I)
|
|
0.114 -0.379 u_cpu/addr_trans/tlb_entry/tlb_plv1_reg_r2_0_31_0_0/DP
|
|
-------------------------------------------------------------------
|
|
required time 0.379
|
|
arrival time -0.245
|
|
-------------------------------------------------------------------
|
|
slack 0.134
|
|
|
|
Slack (MET) : 0.134ns (arrival time - required time)
|
|
Source: u_cpu/u_csr/csr_tlbelo1_reg[2]/C
|
|
(rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns})
|
|
Destination: u_cpu/addr_trans/tlb_entry/tlb_plv1_reg_r2_0_31_0_0/DP/I
|
|
(rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns})
|
|
Path Group: cpu_clk
|
|
Path Type: Hold (Min at Fast Process Corner)
|
|
Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns)
|
|
Data Path Delay: 0.264ns (logic 0.141ns (53.394%) route 0.123ns (46.606%))
|
|
Logic Levels: 0
|
|
Clock Path Skew: 0.016ns (DCD - SCD - CPR)
|
|
Destination Clock Delay (DCD): -0.275ns
|
|
Source Clock Delay (SCD): -0.509ns
|
|
Clock Pessimism Removal (CPR): 0.218ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock cpu_clk rise edge) 0.000 0.000 r
|
|
clock source latency -1.848 -1.848
|
|
propagated clock network latency
|
|
1.340 -0.509
|
|
SLICE_X39Y39 FDRE 0.000 -0.509 r u_cpu/u_csr/csr_tlbelo1_reg[2]/C
|
|
SLICE_X39Y39 FDRE (Prop_fdre_C_Q) 0.141 -0.368 f u_cpu/u_csr/csr_tlbelo1_reg[2]/Q
|
|
net (fo=7, routed) 0.123 -0.245 u_cpu/addr_trans/tlb_entry/tlb_plv1_reg_r2_0_31_0_0/D
|
|
SLICE_X40Y39 RAMD32 f u_cpu/addr_trans/tlb_entry/tlb_plv1_reg_r2_0_31_0_0/DP/I
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock cpu_clk rise edge) 0.000 0.000 r
|
|
clock source latency -1.947 -1.947
|
|
propagated clock network latency
|
|
1.672 -0.275
|
|
clock pessimism -0.218 -0.493
|
|
SLICE_X40Y39 RAMD32 (Hold_ramd32_CLK_I)
|
|
0.114 -0.379 u_cpu/addr_trans/tlb_entry/tlb_plv1_reg_r2_0_31_0_0/DP
|
|
-------------------------------------------------------------------
|
|
required time 0.379
|
|
arrival time -0.245
|
|
-------------------------------------------------------------------
|
|
slack 0.134
|
|
|
|
Slack (MET) : 0.135ns (arrival time - required time)
|
|
Source: u_cpu/axi_bridge/araddr_reg[2]/C
|
|
(rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns})
|
|
Destination: u_Axi_CDC/arFifo/ram_reg_0_3_0_5/RAMB/I
|
|
(rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns})
|
|
Path Group: cpu_clk
|
|
Path Type: Hold (Min at Fast Process Corner)
|
|
Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns)
|
|
Data Path Delay: 0.469ns (logic 0.141ns (30.053%) route 0.328ns (69.947%))
|
|
Logic Levels: 0
|
|
Clock Path Skew: 0.188ns (DCD - SCD - CPR)
|
|
Destination Clock Delay (DCD): -0.348ns
|
|
Source Clock Delay (SCD): -0.500ns
|
|
Clock Pessimism Removal (CPR): -0.037ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock cpu_clk rise edge) 0.000 0.000 r
|
|
clock source latency -1.848 -1.848
|
|
propagated clock network latency
|
|
1.349 -0.500
|
|
SLICE_X28Y48 FDRE 0.000 -0.500 r u_cpu/axi_bridge/araddr_reg[2]/C
|
|
SLICE_X28Y48 FDRE (Prop_fdre_C_Q) 0.141 -0.359 r u_cpu/axi_bridge/araddr_reg[2]/Q
|
|
net (fo=1, routed) 0.328 -0.031 u_Axi_CDC/arFifo/ram_reg_0_3_0_5/DIB0
|
|
SLICE_X36Y59 RAMD32 r u_Axi_CDC/arFifo/ram_reg_0_3_0_5/RAMB/I
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock cpu_clk rise edge) 0.000 0.000 r
|
|
clock source latency -1.947 -1.947
|
|
propagated clock network latency
|
|
1.599 -0.348
|
|
clock pessimism 0.037 -0.311
|
|
SLICE_X36Y59 RAMD32 (Hold_ramd32_CLK_I)
|
|
0.146 -0.165 u_Axi_CDC/arFifo/ram_reg_0_3_0_5/RAMB
|
|
-------------------------------------------------------------------
|
|
required time 0.165
|
|
arrival time -0.031
|
|
-------------------------------------------------------------------
|
|
slack 0.135
|
|
|
|
Slack (MET) : 0.135ns (arrival time - required time)
|
|
Source: u_cpu/axi_bridge/araddr_reg[2]/C
|
|
(rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns})
|
|
Destination: u_Axi_CDC/arFifo/ram_reg_0_3_0_5/RAMB/I
|
|
(rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns})
|
|
Path Group: cpu_clk
|
|
Path Type: Hold (Min at Fast Process Corner)
|
|
Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns)
|
|
Data Path Delay: 0.469ns (logic 0.141ns (30.053%) route 0.328ns (69.947%))
|
|
Logic Levels: 0
|
|
Clock Path Skew: 0.188ns (DCD - SCD - CPR)
|
|
Destination Clock Delay (DCD): -0.348ns
|
|
Source Clock Delay (SCD): -0.500ns
|
|
Clock Pessimism Removal (CPR): -0.037ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock cpu_clk rise edge) 0.000 0.000 r
|
|
clock source latency -1.848 -1.848
|
|
propagated clock network latency
|
|
1.349 -0.500
|
|
SLICE_X28Y48 FDRE 0.000 -0.500 r u_cpu/axi_bridge/araddr_reg[2]/C
|
|
SLICE_X28Y48 FDRE (Prop_fdre_C_Q) 0.141 -0.359 f u_cpu/axi_bridge/araddr_reg[2]/Q
|
|
net (fo=1, routed) 0.328 -0.031 u_Axi_CDC/arFifo/ram_reg_0_3_0_5/DIB0
|
|
SLICE_X36Y59 RAMD32 f u_Axi_CDC/arFifo/ram_reg_0_3_0_5/RAMB/I
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock cpu_clk rise edge) 0.000 0.000 r
|
|
clock source latency -1.947 -1.947
|
|
propagated clock network latency
|
|
1.599 -0.348
|
|
clock pessimism 0.037 -0.311
|
|
SLICE_X36Y59 RAMD32 (Hold_ramd32_CLK_I)
|
|
0.146 -0.165 u_Axi_CDC/arFifo/ram_reg_0_3_0_5/RAMB
|
|
-------------------------------------------------------------------
|
|
required time 0.165
|
|
arrival time -0.031
|
|
-------------------------------------------------------------------
|
|
slack 0.135
|
|
|
|
Slack (MET) : 0.135ns (arrival time - required time)
|
|
Source: u_cpu/axi_bridge/wdata_reg[12]/C
|
|
(rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns})
|
|
Destination: u_Axi_CDC/wFifo/ram_reg_0_7_12_17/RAMA/I
|
|
(rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns})
|
|
Path Group: cpu_clk
|
|
Path Type: Hold (Min at Fast Process Corner)
|
|
Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns)
|
|
Data Path Delay: 0.298ns (logic 0.141ns (47.334%) route 0.157ns (52.666%))
|
|
Logic Levels: 0
|
|
Clock Path Skew: 0.016ns (DCD - SCD - CPR)
|
|
Destination Clock Delay (DCD): -0.232ns
|
|
Source Clock Delay (SCD): -0.468ns
|
|
Clock Pessimism Removal (CPR): 0.220ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock cpu_clk rise edge) 0.000 0.000 r
|
|
clock source latency -1.848 -1.848
|
|
propagated clock network latency
|
|
1.381 -0.468
|
|
SLICE_X5Y45 FDRE 0.000 -0.468 r u_cpu/axi_bridge/wdata_reg[12]/C
|
|
SLICE_X5Y45 FDRE (Prop_fdre_C_Q) 0.141 -0.327 r u_cpu/axi_bridge/wdata_reg[12]/Q
|
|
net (fo=1, routed) 0.157 -0.170 u_Axi_CDC/wFifo/ram_reg_0_7_12_17/DIA0
|
|
SLICE_X6Y46 RAMD32 r u_Axi_CDC/wFifo/ram_reg_0_7_12_17/RAMA/I
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock cpu_clk rise edge) 0.000 0.000 r
|
|
clock source latency -1.947 -1.947
|
|
propagated clock network latency
|
|
1.715 -0.232
|
|
clock pessimism -0.220 -0.452
|
|
SLICE_X6Y46 RAMD32 (Hold_ramd32_CLK_I)
|
|
0.147 -0.305 u_Axi_CDC/wFifo/ram_reg_0_7_12_17/RAMA
|
|
-------------------------------------------------------------------
|
|
required time 0.305
|
|
arrival time -0.170
|
|
-------------------------------------------------------------------
|
|
slack 0.135
|
|
|
|
Slack (MET) : 0.135ns (arrival time - required time)
|
|
Source: u_cpu/axi_bridge/wdata_reg[12]/C
|
|
(rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns})
|
|
Destination: u_Axi_CDC/wFifo/ram_reg_0_7_12_17/RAMA/I
|
|
(rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns})
|
|
Path Group: cpu_clk
|
|
Path Type: Hold (Min at Fast Process Corner)
|
|
Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns)
|
|
Data Path Delay: 0.298ns (logic 0.141ns (47.334%) route 0.157ns (52.666%))
|
|
Logic Levels: 0
|
|
Clock Path Skew: 0.016ns (DCD - SCD - CPR)
|
|
Destination Clock Delay (DCD): -0.232ns
|
|
Source Clock Delay (SCD): -0.468ns
|
|
Clock Pessimism Removal (CPR): 0.220ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock cpu_clk rise edge) 0.000 0.000 r
|
|
clock source latency -1.848 -1.848
|
|
propagated clock network latency
|
|
1.381 -0.468
|
|
SLICE_X5Y45 FDRE 0.000 -0.468 r u_cpu/axi_bridge/wdata_reg[12]/C
|
|
SLICE_X5Y45 FDRE (Prop_fdre_C_Q) 0.141 -0.327 f u_cpu/axi_bridge/wdata_reg[12]/Q
|
|
net (fo=1, routed) 0.157 -0.170 u_Axi_CDC/wFifo/ram_reg_0_7_12_17/DIA0
|
|
SLICE_X6Y46 RAMD32 f u_Axi_CDC/wFifo/ram_reg_0_7_12_17/RAMA/I
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock cpu_clk rise edge) 0.000 0.000 r
|
|
clock source latency -1.947 -1.947
|
|
propagated clock network latency
|
|
1.715 -0.232
|
|
clock pessimism -0.220 -0.452
|
|
SLICE_X6Y46 RAMD32 (Hold_ramd32_CLK_I)
|
|
0.147 -0.305 u_Axi_CDC/wFifo/ram_reg_0_7_12_17/RAMA
|
|
-------------------------------------------------------------------
|
|
required time 0.305
|
|
arrival time -0.170
|
|
-------------------------------------------------------------------
|
|
slack 0.135
|
|
|
|
Slack (MET) : 0.136ns (arrival time - required time)
|
|
Source: u_cpu/u_csr/csr_tlbelo1_reg[12]/C
|
|
(rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns})
|
|
Destination: u_cpu/addr_trans/tlb_entry/tlb_ppn1_reg_r3_0_31_0_5/RAMC/I
|
|
(rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns})
|
|
Path Group: cpu_clk
|
|
Path Type: Hold (Min at Fast Process Corner)
|
|
Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns)
|
|
Data Path Delay: 0.294ns (logic 0.164ns (55.832%) route 0.130ns (44.168%))
|
|
Logic Levels: 0
|
|
Clock Path Skew: 0.014ns (DCD - SCD - CPR)
|
|
Destination Clock Delay (DCD): -0.312ns
|
|
Source Clock Delay (SCD): -0.543ns
|
|
Clock Pessimism Removal (CPR): 0.217ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock cpu_clk rise edge) 0.000 0.000 r
|
|
clock source latency -1.848 -1.848
|
|
propagated clock network latency
|
|
1.306 -0.543
|
|
SLICE_X48Y32 FDRE 0.000 -0.543 r u_cpu/u_csr/csr_tlbelo1_reg[12]/C
|
|
SLICE_X48Y32 FDRE (Prop_fdre_C_Q) 0.164 -0.379 r u_cpu/u_csr/csr_tlbelo1_reg[12]/Q
|
|
net (fo=4, routed) 0.130 -0.249 u_cpu/addr_trans/tlb_entry/tlb_ppn1_reg_r3_0_31_0_5/DIC0
|
|
SLICE_X46Y32 RAMD32 r u_cpu/addr_trans/tlb_entry/tlb_ppn1_reg_r3_0_31_0_5/RAMC/I
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock cpu_clk rise edge) 0.000 0.000 r
|
|
clock source latency -1.947 -1.947
|
|
propagated clock network latency
|
|
1.635 -0.312
|
|
clock pessimism -0.217 -0.529
|
|
SLICE_X46Y32 RAMD32 (Hold_ramd32_CLK_I)
|
|
0.144 -0.385 u_cpu/addr_trans/tlb_entry/tlb_ppn1_reg_r3_0_31_0_5/RAMC
|
|
-------------------------------------------------------------------
|
|
required time 0.385
|
|
arrival time -0.249
|
|
-------------------------------------------------------------------
|
|
slack 0.136
|
|
|
|
Slack (MET) : 0.136ns (arrival time - required time)
|
|
Source: u_cpu/u_csr/csr_tlbelo1_reg[12]/C
|
|
(rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns})
|
|
Destination: u_cpu/addr_trans/tlb_entry/tlb_ppn1_reg_r3_0_31_0_5/RAMC/I
|
|
(rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns})
|
|
Path Group: cpu_clk
|
|
Path Type: Hold (Min at Fast Process Corner)
|
|
Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns)
|
|
Data Path Delay: 0.294ns (logic 0.164ns (55.832%) route 0.130ns (44.168%))
|
|
Logic Levels: 0
|
|
Clock Path Skew: 0.014ns (DCD - SCD - CPR)
|
|
Destination Clock Delay (DCD): -0.312ns
|
|
Source Clock Delay (SCD): -0.543ns
|
|
Clock Pessimism Removal (CPR): 0.217ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock cpu_clk rise edge) 0.000 0.000 r
|
|
clock source latency -1.848 -1.848
|
|
propagated clock network latency
|
|
1.306 -0.543
|
|
SLICE_X48Y32 FDRE 0.000 -0.543 r u_cpu/u_csr/csr_tlbelo1_reg[12]/C
|
|
SLICE_X48Y32 FDRE (Prop_fdre_C_Q) 0.164 -0.379 f u_cpu/u_csr/csr_tlbelo1_reg[12]/Q
|
|
net (fo=4, routed) 0.130 -0.249 u_cpu/addr_trans/tlb_entry/tlb_ppn1_reg_r3_0_31_0_5/DIC0
|
|
SLICE_X46Y32 RAMD32 f u_cpu/addr_trans/tlb_entry/tlb_ppn1_reg_r3_0_31_0_5/RAMC/I
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock cpu_clk rise edge) 0.000 0.000 r
|
|
clock source latency -1.947 -1.947
|
|
propagated clock network latency
|
|
1.635 -0.312
|
|
clock pessimism -0.217 -0.529
|
|
SLICE_X46Y32 RAMD32 (Hold_ramd32_CLK_I)
|
|
0.144 -0.385 u_cpu/addr_trans/tlb_entry/tlb_ppn1_reg_r3_0_31_0_5/RAMC
|
|
-------------------------------------------------------------------
|
|
required time 0.385
|
|
arrival time -0.249
|
|
-------------------------------------------------------------------
|
|
slack 0.136
|
|
|
|
Slack (MET) : 0.136ns (arrival time - required time)
|
|
Source: u_cpu/axi_bridge/araddr_reg[0]/C
|
|
(rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns})
|
|
Destination: u_Axi_CDC/arFifo/ram_reg_0_3_0_5/RAMA/I
|
|
(rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns})
|
|
Path Group: cpu_clk
|
|
Path Type: Hold (Min at Fast Process Corner)
|
|
Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns)
|
|
Data Path Delay: 0.472ns (logic 0.141ns (29.890%) route 0.331ns (70.110%))
|
|
Logic Levels: 0
|
|
Clock Path Skew: 0.188ns (DCD - SCD - CPR)
|
|
Destination Clock Delay (DCD): -0.348ns
|
|
Source Clock Delay (SCD): -0.500ns
|
|
Clock Pessimism Removal (CPR): -0.037ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock cpu_clk rise edge) 0.000 0.000 r
|
|
clock source latency -1.848 -1.848
|
|
propagated clock network latency
|
|
1.349 -0.500
|
|
SLICE_X29Y48 FDRE 0.000 -0.500 r u_cpu/axi_bridge/araddr_reg[0]/C
|
|
SLICE_X29Y48 FDRE (Prop_fdre_C_Q) 0.141 -0.359 r u_cpu/axi_bridge/araddr_reg[0]/Q
|
|
net (fo=1, routed) 0.331 -0.028 u_Axi_CDC/arFifo/ram_reg_0_3_0_5/DIA0
|
|
SLICE_X36Y59 RAMD32 r u_Axi_CDC/arFifo/ram_reg_0_3_0_5/RAMA/I
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock cpu_clk rise edge) 0.000 0.000 r
|
|
clock source latency -1.947 -1.947
|
|
propagated clock network latency
|
|
1.599 -0.348
|
|
clock pessimism 0.037 -0.311
|
|
SLICE_X36Y59 RAMD32 (Hold_ramd32_CLK_I)
|
|
0.147 -0.164 u_Axi_CDC/arFifo/ram_reg_0_3_0_5/RAMA
|
|
-------------------------------------------------------------------
|
|
required time 0.164
|
|
arrival time -0.028
|
|
-------------------------------------------------------------------
|
|
slack 0.136
|
|
|
|
Slack (MET) : 0.136ns (arrival time - required time)
|
|
Source: u_cpu/axi_bridge/araddr_reg[0]/C
|
|
(rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns})
|
|
Destination: u_Axi_CDC/arFifo/ram_reg_0_3_0_5/RAMA/I
|
|
(rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns})
|
|
Path Group: cpu_clk
|
|
Path Type: Hold (Min at Fast Process Corner)
|
|
Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns)
|
|
Data Path Delay: 0.472ns (logic 0.141ns (29.890%) route 0.331ns (70.110%))
|
|
Logic Levels: 0
|
|
Clock Path Skew: 0.188ns (DCD - SCD - CPR)
|
|
Destination Clock Delay (DCD): -0.348ns
|
|
Source Clock Delay (SCD): -0.500ns
|
|
Clock Pessimism Removal (CPR): -0.037ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock cpu_clk rise edge) 0.000 0.000 r
|
|
clock source latency -1.848 -1.848
|
|
propagated clock network latency
|
|
1.349 -0.500
|
|
SLICE_X29Y48 FDRE 0.000 -0.500 r u_cpu/axi_bridge/araddr_reg[0]/C
|
|
SLICE_X29Y48 FDRE (Prop_fdre_C_Q) 0.141 -0.359 f u_cpu/axi_bridge/araddr_reg[0]/Q
|
|
net (fo=1, routed) 0.331 -0.028 u_Axi_CDC/arFifo/ram_reg_0_3_0_5/DIA0
|
|
SLICE_X36Y59 RAMD32 f u_Axi_CDC/arFifo/ram_reg_0_3_0_5/RAMA/I
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock cpu_clk rise edge) 0.000 0.000 r
|
|
clock source latency -1.947 -1.947
|
|
propagated clock network latency
|
|
1.599 -0.348
|
|
clock pessimism 0.037 -0.311
|
|
SLICE_X36Y59 RAMD32 (Hold_ramd32_CLK_I)
|
|
0.147 -0.164 u_Axi_CDC/arFifo/ram_reg_0_3_0_5/RAMA
|
|
-------------------------------------------------------------------
|
|
required time 0.164
|
|
arrival time -0.028
|
|
-------------------------------------------------------------------
|
|
slack 0.136
|
|
|
|
Slack (MET) : 0.137ns (arrival time - required time)
|
|
Source: u_cpu/u_csr/csr_tlbelo1_reg[11]/C
|
|
(rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns})
|
|
Destination: u_cpu/addr_trans/tlb_entry/tlb_ppn1_reg_r3_0_31_0_5/RAMB_D1/I
|
|
(rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns})
|
|
Path Group: cpu_clk
|
|
Path Type: Hold (Min at Fast Process Corner)
|
|
Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns)
|
|
Data Path Delay: 0.275ns (logic 0.164ns (59.651%) route 0.111ns (40.349%))
|
|
Logic Levels: 0
|
|
Clock Path Skew: 0.014ns (DCD - SCD - CPR)
|
|
Destination Clock Delay (DCD): -0.312ns
|
|
Source Clock Delay (SCD): -0.543ns
|
|
Clock Pessimism Removal (CPR): 0.217ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock cpu_clk rise edge) 0.000 0.000 r
|
|
clock source latency -1.848 -1.848
|
|
propagated clock network latency
|
|
1.306 -0.543
|
|
SLICE_X48Y32 FDRE 0.000 -0.543 r u_cpu/u_csr/csr_tlbelo1_reg[11]/C
|
|
SLICE_X48Y32 FDRE (Prop_fdre_C_Q) 0.164 -0.379 r u_cpu/u_csr/csr_tlbelo1_reg[11]/Q
|
|
net (fo=4, routed) 0.111 -0.268 u_cpu/addr_trans/tlb_entry/tlb_ppn1_reg_r3_0_31_0_5/DIB1
|
|
SLICE_X46Y32 RAMD32 r u_cpu/addr_trans/tlb_entry/tlb_ppn1_reg_r3_0_31_0_5/RAMB_D1/I
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock cpu_clk rise edge) 0.000 0.000 r
|
|
clock source latency -1.947 -1.947
|
|
propagated clock network latency
|
|
1.635 -0.312
|
|
clock pessimism -0.217 -0.529
|
|
SLICE_X46Y32 RAMD32 (Hold_ramd32_CLK_I)
|
|
0.124 -0.405 u_cpu/addr_trans/tlb_entry/tlb_ppn1_reg_r3_0_31_0_5/RAMB_D1
|
|
-------------------------------------------------------------------
|
|
required time 0.405
|
|
arrival time -0.268
|
|
-------------------------------------------------------------------
|
|
slack 0.137
|
|
|
|
Slack (MET) : 0.137ns (arrival time - required time)
|
|
Source: u_cpu/u_csr/csr_tlbelo1_reg[11]/C
|
|
(rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns})
|
|
Destination: u_cpu/addr_trans/tlb_entry/tlb_ppn1_reg_r3_0_31_0_5/RAMB_D1/I
|
|
(rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns})
|
|
Path Group: cpu_clk
|
|
Path Type: Hold (Min at Fast Process Corner)
|
|
Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns)
|
|
Data Path Delay: 0.275ns (logic 0.164ns (59.651%) route 0.111ns (40.349%))
|
|
Logic Levels: 0
|
|
Clock Path Skew: 0.014ns (DCD - SCD - CPR)
|
|
Destination Clock Delay (DCD): -0.312ns
|
|
Source Clock Delay (SCD): -0.543ns
|
|
Clock Pessimism Removal (CPR): 0.217ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock cpu_clk rise edge) 0.000 0.000 r
|
|
clock source latency -1.848 -1.848
|
|
propagated clock network latency
|
|
1.306 -0.543
|
|
SLICE_X48Y32 FDRE 0.000 -0.543 r u_cpu/u_csr/csr_tlbelo1_reg[11]/C
|
|
SLICE_X48Y32 FDRE (Prop_fdre_C_Q) 0.164 -0.379 f u_cpu/u_csr/csr_tlbelo1_reg[11]/Q
|
|
net (fo=4, routed) 0.111 -0.268 u_cpu/addr_trans/tlb_entry/tlb_ppn1_reg_r3_0_31_0_5/DIB1
|
|
SLICE_X46Y32 RAMD32 f u_cpu/addr_trans/tlb_entry/tlb_ppn1_reg_r3_0_31_0_5/RAMB_D1/I
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock cpu_clk rise edge) 0.000 0.000 r
|
|
clock source latency -1.947 -1.947
|
|
propagated clock network latency
|
|
1.635 -0.312
|
|
clock pessimism -0.217 -0.529
|
|
SLICE_X46Y32 RAMD32 (Hold_ramd32_CLK_I)
|
|
0.124 -0.405 u_cpu/addr_trans/tlb_entry/tlb_ppn1_reg_r3_0_31_0_5/RAMB_D1
|
|
-------------------------------------------------------------------
|
|
required time 0.405
|
|
arrival time -0.268
|
|
-------------------------------------------------------------------
|
|
slack 0.137
|
|
|
|
Slack (MET) : 0.138ns (arrival time - required time)
|
|
Source: u_cpu/axi_bridge/wdata_reg[28]/C
|
|
(rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns})
|
|
Destination: u_Axi_CDC/wFifo/ram_reg_0_7_24_29/RAMC/I
|
|
(rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns})
|
|
Path Group: cpu_clk
|
|
Path Type: Hold (Min at Fast Process Corner)
|
|
Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns)
|
|
Data Path Delay: 0.244ns (logic 0.128ns (52.542%) route 0.116ns (47.458%))
|
|
Logic Levels: 0
|
|
Clock Path Skew: 0.016ns (DCD - SCD - CPR)
|
|
Destination Clock Delay (DCD): -0.229ns
|
|
Source Clock Delay (SCD): -0.465ns
|
|
Clock Pessimism Removal (CPR): 0.220ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock cpu_clk rise edge) 0.000 0.000 r
|
|
clock source latency -1.848 -1.848
|
|
propagated clock network latency
|
|
1.384 -0.465
|
|
SLICE_X3Y48 FDRE 0.000 -0.465 r u_cpu/axi_bridge/wdata_reg[28]/C
|
|
SLICE_X3Y48 FDRE (Prop_fdre_C_Q) 0.128 -0.337 r u_cpu/axi_bridge/wdata_reg[28]/Q
|
|
net (fo=1, routed) 0.116 -0.221 u_Axi_CDC/wFifo/ram_reg_0_7_24_29/DIC0
|
|
SLICE_X2Y49 RAMD32 r u_Axi_CDC/wFifo/ram_reg_0_7_24_29/RAMC/I
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock cpu_clk rise edge) 0.000 0.000 r
|
|
clock source latency -1.947 -1.947
|
|
propagated clock network latency
|
|
1.718 -0.229
|
|
clock pessimism -0.220 -0.449
|
|
SLICE_X2Y49 RAMD32 (Hold_ramd32_CLK_I)
|
|
0.090 -0.359 u_Axi_CDC/wFifo/ram_reg_0_7_24_29/RAMC
|
|
-------------------------------------------------------------------
|
|
required time 0.359
|
|
arrival time -0.221
|
|
-------------------------------------------------------------------
|
|
slack 0.138
|
|
|
|
Slack (MET) : 0.138ns (arrival time - required time)
|
|
Source: u_cpu/axi_bridge/wdata_reg[28]/C
|
|
(rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns})
|
|
Destination: u_Axi_CDC/wFifo/ram_reg_0_7_24_29/RAMC/I
|
|
(rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns})
|
|
Path Group: cpu_clk
|
|
Path Type: Hold (Min at Fast Process Corner)
|
|
Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns)
|
|
Data Path Delay: 0.244ns (logic 0.128ns (52.542%) route 0.116ns (47.458%))
|
|
Logic Levels: 0
|
|
Clock Path Skew: 0.016ns (DCD - SCD - CPR)
|
|
Destination Clock Delay (DCD): -0.229ns
|
|
Source Clock Delay (SCD): -0.465ns
|
|
Clock Pessimism Removal (CPR): 0.220ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock cpu_clk rise edge) 0.000 0.000 r
|
|
clock source latency -1.848 -1.848
|
|
propagated clock network latency
|
|
1.384 -0.465
|
|
SLICE_X3Y48 FDRE 0.000 -0.465 r u_cpu/axi_bridge/wdata_reg[28]/C
|
|
SLICE_X3Y48 FDRE (Prop_fdre_C_Q) 0.128 -0.337 f u_cpu/axi_bridge/wdata_reg[28]/Q
|
|
net (fo=1, routed) 0.116 -0.221 u_Axi_CDC/wFifo/ram_reg_0_7_24_29/DIC0
|
|
SLICE_X2Y49 RAMD32 f u_Axi_CDC/wFifo/ram_reg_0_7_24_29/RAMC/I
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock cpu_clk rise edge) 0.000 0.000 r
|
|
clock source latency -1.947 -1.947
|
|
propagated clock network latency
|
|
1.718 -0.229
|
|
clock pessimism -0.220 -0.449
|
|
SLICE_X2Y49 RAMD32 (Hold_ramd32_CLK_I)
|
|
0.090 -0.359 u_Axi_CDC/wFifo/ram_reg_0_7_24_29/RAMC
|
|
-------------------------------------------------------------------
|
|
required time 0.359
|
|
arrival time -0.221
|
|
-------------------------------------------------------------------
|
|
slack 0.138
|
|
|
|
Slack (MET) : 0.139ns (arrival time - required time)
|
|
Source: u_cpu/icache/lfsr/r_lfsr_reg[6]/C
|
|
(rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns})
|
|
Destination: u_cpu/icache/lfsr/r_lfsr_reg[7]/D
|
|
(rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns})
|
|
Path Group: cpu_clk
|
|
Path Type: Hold (Min at Fast Process Corner)
|
|
Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns)
|
|
Data Path Delay: 0.210ns (logic 0.141ns (67.004%) route 0.069ns (32.996%))
|
|
Logic Levels: 0
|
|
Clock Path Skew: 0.000ns (DCD - SCD - CPR)
|
|
Destination Clock Delay (DCD): -0.232ns
|
|
Source Clock Delay (SCD): -0.468ns
|
|
Clock Pessimism Removal (CPR): 0.236ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock cpu_clk rise edge) 0.000 0.000 r
|
|
clock source latency -1.848 -1.848
|
|
propagated clock network latency
|
|
1.381 -0.468
|
|
SLICE_X5Y43 FDRE 0.000 -0.468 r u_cpu/icache/lfsr/r_lfsr_reg[6]/C
|
|
SLICE_X5Y43 FDRE (Prop_fdre_C_Q) 0.141 -0.327 r u_cpu/icache/lfsr/r_lfsr_reg[6]/Q
|
|
net (fo=2, routed) 0.069 -0.257 u_cpu/icache/lfsr/Q[0]
|
|
SLICE_X5Y43 FDRE r u_cpu/icache/lfsr/r_lfsr_reg[7]/D
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock cpu_clk rise edge) 0.000 0.000 r
|
|
clock source latency -1.947 -1.947
|
|
propagated clock network latency
|
|
1.715 -0.232
|
|
clock pessimism -0.236 -0.468
|
|
SLICE_X5Y43 FDRE (Hold_fdre_C_D) 0.071 -0.397 u_cpu/icache/lfsr/r_lfsr_reg[7]
|
|
-------------------------------------------------------------------
|
|
required time 0.397
|
|
arrival time -0.257
|
|
-------------------------------------------------------------------
|
|
slack 0.139
|
|
|
|
Slack (MET) : 0.139ns (arrival time - required time)
|
|
Source: u_cpu/icache/lfsr/r_lfsr_reg[6]/C
|
|
(rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns})
|
|
Destination: u_cpu/icache/lfsr/r_lfsr_reg[7]/D
|
|
(rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns})
|
|
Path Group: cpu_clk
|
|
Path Type: Hold (Min at Fast Process Corner)
|
|
Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns)
|
|
Data Path Delay: 0.210ns (logic 0.141ns (67.004%) route 0.069ns (32.996%))
|
|
Logic Levels: 0
|
|
Clock Path Skew: 0.000ns (DCD - SCD - CPR)
|
|
Destination Clock Delay (DCD): -0.232ns
|
|
Source Clock Delay (SCD): -0.468ns
|
|
Clock Pessimism Removal (CPR): 0.236ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock cpu_clk rise edge) 0.000 0.000 r
|
|
clock source latency -1.848 -1.848
|
|
propagated clock network latency
|
|
1.381 -0.468
|
|
SLICE_X5Y43 FDRE 0.000 -0.468 r u_cpu/icache/lfsr/r_lfsr_reg[6]/C
|
|
SLICE_X5Y43 FDRE (Prop_fdre_C_Q) 0.141 -0.327 f u_cpu/icache/lfsr/r_lfsr_reg[6]/Q
|
|
net (fo=2, routed) 0.069 -0.257 u_cpu/icache/lfsr/Q[0]
|
|
SLICE_X5Y43 FDRE f u_cpu/icache/lfsr/r_lfsr_reg[7]/D
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock cpu_clk rise edge) 0.000 0.000 r
|
|
clock source latency -1.947 -1.947
|
|
propagated clock network latency
|
|
1.715 -0.232
|
|
clock pessimism -0.236 -0.468
|
|
SLICE_X5Y43 FDRE (Hold_fdre_C_D) 0.071 -0.397 u_cpu/icache/lfsr/r_lfsr_reg[7]
|
|
-------------------------------------------------------------------
|
|
required time 0.397
|
|
arrival time -0.257
|
|
-------------------------------------------------------------------
|
|
slack 0.139
|
|
|
|
Slack (MET) : 0.140ns (arrival time - required time)
|
|
Source: u_cpu/u_csr/csr_tlbelo0_reg[11]/C
|
|
(rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns})
|
|
Destination: u_cpu/addr_trans/tlb_entry/tlb_ppn0_reg_r1_0_31_0_5/RAMB_D1/I
|
|
(rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns})
|
|
Path Group: cpu_clk
|
|
Path Type: Hold (Min at Fast Process Corner)
|
|
Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns)
|
|
Data Path Delay: 0.280ns (logic 0.141ns (50.435%) route 0.139ns (49.565%))
|
|
Logic Levels: 0
|
|
Clock Path Skew: 0.016ns (DCD - SCD - CPR)
|
|
Destination Clock Delay (DCD): -0.307ns
|
|
Source Clock Delay (SCD): -0.540ns
|
|
Clock Pessimism Removal (CPR): 0.217ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock cpu_clk rise edge) 0.000 0.000 r
|
|
clock source latency -1.848 -1.848
|
|
propagated clock network latency
|
|
1.309 -0.540
|
|
SLICE_X45Y36 FDRE 0.000 -0.540 r u_cpu/u_csr/csr_tlbelo0_reg[11]/C
|
|
SLICE_X45Y36 FDRE (Prop_fdre_C_Q) 0.141 -0.399 r u_cpu/u_csr/csr_tlbelo0_reg[11]/Q
|
|
net (fo=4, routed) 0.139 -0.260 u_cpu/addr_trans/tlb_entry/tlb_ppn0_reg_r1_0_31_0_5/DIB1
|
|
SLICE_X44Y37 RAMD32 r u_cpu/addr_trans/tlb_entry/tlb_ppn0_reg_r1_0_31_0_5/RAMB_D1/I
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock cpu_clk rise edge) 0.000 0.000 r
|
|
clock source latency -1.947 -1.947
|
|
propagated clock network latency
|
|
1.640 -0.307
|
|
clock pessimism -0.217 -0.524
|
|
SLICE_X44Y37 RAMD32 (Hold_ramd32_CLK_I)
|
|
0.124 -0.400 u_cpu/addr_trans/tlb_entry/tlb_ppn0_reg_r1_0_31_0_5/RAMB_D1
|
|
-------------------------------------------------------------------
|
|
required time 0.400
|
|
arrival time -0.260
|
|
-------------------------------------------------------------------
|
|
slack 0.140
|
|
|
|
Slack (MET) : 0.140ns (arrival time - required time)
|
|
Source: u_cpu/u_csr/csr_tlbelo0_reg[11]/C
|
|
(rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns})
|
|
Destination: u_cpu/addr_trans/tlb_entry/tlb_ppn0_reg_r1_0_31_0_5/RAMB_D1/I
|
|
(rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns})
|
|
Path Group: cpu_clk
|
|
Path Type: Hold (Min at Fast Process Corner)
|
|
Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns)
|
|
Data Path Delay: 0.280ns (logic 0.141ns (50.435%) route 0.139ns (49.565%))
|
|
Logic Levels: 0
|
|
Clock Path Skew: 0.016ns (DCD - SCD - CPR)
|
|
Destination Clock Delay (DCD): -0.307ns
|
|
Source Clock Delay (SCD): -0.540ns
|
|
Clock Pessimism Removal (CPR): 0.217ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock cpu_clk rise edge) 0.000 0.000 r
|
|
clock source latency -1.848 -1.848
|
|
propagated clock network latency
|
|
1.309 -0.540
|
|
SLICE_X45Y36 FDRE 0.000 -0.540 r u_cpu/u_csr/csr_tlbelo0_reg[11]/C
|
|
SLICE_X45Y36 FDRE (Prop_fdre_C_Q) 0.141 -0.399 f u_cpu/u_csr/csr_tlbelo0_reg[11]/Q
|
|
net (fo=4, routed) 0.139 -0.260 u_cpu/addr_trans/tlb_entry/tlb_ppn0_reg_r1_0_31_0_5/DIB1
|
|
SLICE_X44Y37 RAMD32 f u_cpu/addr_trans/tlb_entry/tlb_ppn0_reg_r1_0_31_0_5/RAMB_D1/I
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock cpu_clk rise edge) 0.000 0.000 r
|
|
clock source latency -1.947 -1.947
|
|
propagated clock network latency
|
|
1.640 -0.307
|
|
clock pessimism -0.217 -0.524
|
|
SLICE_X44Y37 RAMD32 (Hold_ramd32_CLK_I)
|
|
0.124 -0.400 u_cpu/addr_trans/tlb_entry/tlb_ppn0_reg_r1_0_31_0_5/RAMB_D1
|
|
-------------------------------------------------------------------
|
|
required time 0.400
|
|
arrival time -0.260
|
|
-------------------------------------------------------------------
|
|
slack 0.140
|
|
|
|
Slack (MET) : 0.140ns (arrival time - required time)
|
|
Source: u_cpu/wb_stage/ms_to_ws_bus_r_reg[238]/C
|
|
(rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns})
|
|
Destination: u_cpu/u_csr/lladdr_reg[16]/D
|
|
(rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns})
|
|
Path Group: cpu_clk
|
|
Path Type: Hold (Min at Fast Process Corner)
|
|
Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns)
|
|
Data Path Delay: 0.200ns (logic 0.141ns (70.330%) route 0.059ns (29.670%))
|
|
Logic Levels: 0
|
|
Clock Path Skew: 0.013ns (DCD - SCD - CPR)
|
|
Destination Clock Delay (DCD): -0.268ns
|
|
Source Clock Delay (SCD): -0.502ns
|
|
Clock Pessimism Removal (CPR): 0.221ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock cpu_clk rise edge) 0.000 0.000 r
|
|
clock source latency -1.848 -1.848
|
|
propagated clock network latency
|
|
1.347 -0.502
|
|
SLICE_X31Y41 FDRE 0.000 -0.502 r u_cpu/wb_stage/ms_to_ws_bus_r_reg[238]/C
|
|
SLICE_X31Y41 FDRE (Prop_fdre_C_Q) 0.141 -0.361 r u_cpu/wb_stage/ms_to_ws_bus_r_reg[238]/Q
|
|
net (fo=1, routed) 0.059 -0.301 u_cpu/u_csr/ws_lladdr[16]
|
|
SLICE_X30Y41 FDRE r u_cpu/u_csr/lladdr_reg[16]/D
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock cpu_clk rise edge) 0.000 0.000 r
|
|
clock source latency -1.947 -1.947
|
|
propagated clock network latency
|
|
1.679 -0.268
|
|
clock pessimism -0.221 -0.489
|
|
SLICE_X30Y41 FDRE (Hold_fdre_C_D) 0.047 -0.442 u_cpu/u_csr/lladdr_reg[16]
|
|
-------------------------------------------------------------------
|
|
required time 0.442
|
|
arrival time -0.301
|
|
-------------------------------------------------------------------
|
|
slack 0.140
|
|
|
|
Slack (MET) : 0.140ns (arrival time - required time)
|
|
Source: u_cpu/wb_stage/ms_to_ws_bus_r_reg[238]/C
|
|
(rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns})
|
|
Destination: u_cpu/u_csr/lladdr_reg[16]/D
|
|
(rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns})
|
|
Path Group: cpu_clk
|
|
Path Type: Hold (Min at Fast Process Corner)
|
|
Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns)
|
|
Data Path Delay: 0.200ns (logic 0.141ns (70.330%) route 0.059ns (29.670%))
|
|
Logic Levels: 0
|
|
Clock Path Skew: 0.013ns (DCD - SCD - CPR)
|
|
Destination Clock Delay (DCD): -0.268ns
|
|
Source Clock Delay (SCD): -0.502ns
|
|
Clock Pessimism Removal (CPR): 0.221ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock cpu_clk rise edge) 0.000 0.000 r
|
|
clock source latency -1.848 -1.848
|
|
propagated clock network latency
|
|
1.347 -0.502
|
|
SLICE_X31Y41 FDRE 0.000 -0.502 r u_cpu/wb_stage/ms_to_ws_bus_r_reg[238]/C
|
|
SLICE_X31Y41 FDRE (Prop_fdre_C_Q) 0.141 -0.361 f u_cpu/wb_stage/ms_to_ws_bus_r_reg[238]/Q
|
|
net (fo=1, routed) 0.059 -0.301 u_cpu/u_csr/ws_lladdr[16]
|
|
SLICE_X30Y41 FDRE f u_cpu/u_csr/lladdr_reg[16]/D
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock cpu_clk rise edge) 0.000 0.000 r
|
|
clock source latency -1.947 -1.947
|
|
propagated clock network latency
|
|
1.679 -0.268
|
|
clock pessimism -0.221 -0.489
|
|
SLICE_X30Y41 FDRE (Hold_fdre_C_D) 0.047 -0.442 u_cpu/u_csr/lladdr_reg[16]
|
|
-------------------------------------------------------------------
|
|
required time 0.442
|
|
arrival time -0.301
|
|
-------------------------------------------------------------------
|
|
slack 0.140
|
|
|
|
Slack (MET) : 0.143ns (arrival time - required time)
|
|
Source: u_cpu/wb_stage/ms_to_ws_bus_r_reg[231]/C
|
|
(rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns})
|
|
Destination: u_cpu/u_csr/lladdr_reg[9]/D
|
|
(rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns})
|
|
Path Group: cpu_clk
|
|
Path Type: Hold (Min at Fast Process Corner)
|
|
Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns)
|
|
Data Path Delay: 0.260ns (logic 0.141ns (54.241%) route 0.119ns (45.759%))
|
|
Logic Levels: 0
|
|
Clock Path Skew: 0.039ns (DCD - SCD - CPR)
|
|
Destination Clock Delay (DCD): -0.269ns
|
|
Source Clock Delay (SCD): -0.504ns
|
|
Clock Pessimism Removal (CPR): 0.196ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock cpu_clk rise edge) 0.000 0.000 r
|
|
clock source latency -1.848 -1.848
|
|
propagated clock network latency
|
|
1.345 -0.504
|
|
SLICE_X32Y40 FDRE 0.000 -0.504 r u_cpu/wb_stage/ms_to_ws_bus_r_reg[231]/C
|
|
SLICE_X32Y40 FDRE (Prop_fdre_C_Q) 0.141 -0.363 r u_cpu/wb_stage/ms_to_ws_bus_r_reg[231]/Q
|
|
net (fo=1, routed) 0.119 -0.244 u_cpu/u_csr/ws_lladdr[9]
|
|
SLICE_X31Y39 FDRE r u_cpu/u_csr/lladdr_reg[9]/D
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock cpu_clk rise edge) 0.000 0.000 r
|
|
clock source latency -1.947 -1.947
|
|
propagated clock network latency
|
|
1.678 -0.269
|
|
clock pessimism -0.196 -0.465
|
|
SLICE_X31Y39 FDRE (Hold_fdre_C_D) 0.078 -0.387 u_cpu/u_csr/lladdr_reg[9]
|
|
-------------------------------------------------------------------
|
|
required time 0.387
|
|
arrival time -0.244
|
|
-------------------------------------------------------------------
|
|
slack 0.143
|
|
|
|
Slack (MET) : 0.143ns (arrival time - required time)
|
|
Source: u_cpu/wb_stage/ms_to_ws_bus_r_reg[231]/C
|
|
(rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns})
|
|
Destination: u_cpu/u_csr/lladdr_reg[9]/D
|
|
(rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns})
|
|
Path Group: cpu_clk
|
|
Path Type: Hold (Min at Fast Process Corner)
|
|
Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns)
|
|
Data Path Delay: 0.260ns (logic 0.141ns (54.241%) route 0.119ns (45.759%))
|
|
Logic Levels: 0
|
|
Clock Path Skew: 0.039ns (DCD - SCD - CPR)
|
|
Destination Clock Delay (DCD): -0.269ns
|
|
Source Clock Delay (SCD): -0.504ns
|
|
Clock Pessimism Removal (CPR): 0.196ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock cpu_clk rise edge) 0.000 0.000 r
|
|
clock source latency -1.848 -1.848
|
|
propagated clock network latency
|
|
1.345 -0.504
|
|
SLICE_X32Y40 FDRE 0.000 -0.504 r u_cpu/wb_stage/ms_to_ws_bus_r_reg[231]/C
|
|
SLICE_X32Y40 FDRE (Prop_fdre_C_Q) 0.141 -0.363 f u_cpu/wb_stage/ms_to_ws_bus_r_reg[231]/Q
|
|
net (fo=1, routed) 0.119 -0.244 u_cpu/u_csr/ws_lladdr[9]
|
|
SLICE_X31Y39 FDRE f u_cpu/u_csr/lladdr_reg[9]/D
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock cpu_clk rise edge) 0.000 0.000 r
|
|
clock source latency -1.947 -1.947
|
|
propagated clock network latency
|
|
1.678 -0.269
|
|
clock pessimism -0.196 -0.465
|
|
SLICE_X31Y39 FDRE (Hold_fdre_C_D) 0.078 -0.387 u_cpu/u_csr/lladdr_reg[9]
|
|
-------------------------------------------------------------------
|
|
required time 0.387
|
|
arrival time -0.244
|
|
-------------------------------------------------------------------
|
|
slack 0.143
|
|
|
|
Slack (MET) : 0.148ns (arrival time - required time)
|
|
Source: u_cpu/mem_stage/es_to_ms_bus_r_reg[89]/C
|
|
(rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns})
|
|
Destination: u_cpu/wb_stage/ms_to_ws_bus_r_reg[82]/D
|
|
(rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns})
|
|
Path Group: cpu_clk
|
|
Path Type: Hold (Min at Fast Process Corner)
|
|
Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns)
|
|
Data Path Delay: 0.254ns (logic 0.141ns (55.548%) route 0.113ns (44.452%))
|
|
Logic Levels: 0
|
|
Clock Path Skew: 0.035ns (DCD - SCD - CPR)
|
|
Destination Clock Delay (DCD): -0.282ns
|
|
Source Clock Delay (SCD): -0.513ns
|
|
Clock Pessimism Removal (CPR): 0.196ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock cpu_clk rise edge) 0.000 0.000 r
|
|
clock source latency -1.848 -1.848
|
|
propagated clock network latency
|
|
1.336 -0.513
|
|
SLICE_X27Y26 FDRE 0.000 -0.513 r u_cpu/mem_stage/es_to_ms_bus_r_reg[89]/C
|
|
SLICE_X27Y26 FDRE (Prop_fdre_C_Q) 0.141 -0.372 r u_cpu/mem_stage/es_to_ms_bus_r_reg[89]/Q
|
|
net (fo=1, routed) 0.113 -0.259 u_cpu/wb_stage/ms_to_ws_bus[46]
|
|
SLICE_X28Y26 FDRE r u_cpu/wb_stage/ms_to_ws_bus_r_reg[82]/D
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock cpu_clk rise edge) 0.000 0.000 r
|
|
clock source latency -1.947 -1.947
|
|
propagated clock network latency
|
|
1.665 -0.282
|
|
clock pessimism -0.196 -0.478
|
|
SLICE_X28Y26 FDRE (Hold_fdre_C_D) 0.071 -0.407 u_cpu/wb_stage/ms_to_ws_bus_r_reg[82]
|
|
-------------------------------------------------------------------
|
|
required time 0.407
|
|
arrival time -0.259
|
|
-------------------------------------------------------------------
|
|
slack 0.148
|
|
|
|
Slack (MET) : 0.148ns (arrival time - required time)
|
|
Source: u_cpu/mem_stage/es_to_ms_bus_r_reg[89]/C
|
|
(rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns})
|
|
Destination: u_cpu/wb_stage/ms_to_ws_bus_r_reg[82]/D
|
|
(rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns})
|
|
Path Group: cpu_clk
|
|
Path Type: Hold (Min at Fast Process Corner)
|
|
Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns)
|
|
Data Path Delay: 0.254ns (logic 0.141ns (55.548%) route 0.113ns (44.452%))
|
|
Logic Levels: 0
|
|
Clock Path Skew: 0.035ns (DCD - SCD - CPR)
|
|
Destination Clock Delay (DCD): -0.282ns
|
|
Source Clock Delay (SCD): -0.513ns
|
|
Clock Pessimism Removal (CPR): 0.196ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock cpu_clk rise edge) 0.000 0.000 r
|
|
clock source latency -1.848 -1.848
|
|
propagated clock network latency
|
|
1.336 -0.513
|
|
SLICE_X27Y26 FDRE 0.000 -0.513 r u_cpu/mem_stage/es_to_ms_bus_r_reg[89]/C
|
|
SLICE_X27Y26 FDRE (Prop_fdre_C_Q) 0.141 -0.372 f u_cpu/mem_stage/es_to_ms_bus_r_reg[89]/Q
|
|
net (fo=1, routed) 0.113 -0.259 u_cpu/wb_stage/ms_to_ws_bus[46]
|
|
SLICE_X28Y26 FDRE f u_cpu/wb_stage/ms_to_ws_bus_r_reg[82]/D
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock cpu_clk rise edge) 0.000 0.000 r
|
|
clock source latency -1.947 -1.947
|
|
propagated clock network latency
|
|
1.665 -0.282
|
|
clock pessimism -0.196 -0.478
|
|
SLICE_X28Y26 FDRE (Hold_fdre_C_D) 0.071 -0.407 u_cpu/wb_stage/ms_to_ws_bus_r_reg[82]
|
|
-------------------------------------------------------------------
|
|
required time 0.407
|
|
arrival time -0.259
|
|
-------------------------------------------------------------------
|
|
slack 0.148
|
|
|
|
Slack (MET) : 0.148ns (arrival time - required time)
|
|
Source: u_Axi_CDC/wFifo/pushCC_pushPtr_reg[0]/C
|
|
(rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns})
|
|
Destination: u_Axi_CDC/wFifo/ram_reg_0_7_24_29/RAMA/WADR0
|
|
(rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns})
|
|
Path Group: cpu_clk
|
|
Path Type: Hold (Min at Fast Process Corner)
|
|
Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns)
|
|
Data Path Delay: 0.471ns (logic 0.141ns (29.919%) route 0.330ns (70.081%))
|
|
Logic Levels: 0
|
|
Clock Path Skew: 0.013ns (DCD - SCD - CPR)
|
|
Destination Clock Delay (DCD): -0.229ns
|
|
Source Clock Delay (SCD): -0.465ns
|
|
Clock Pessimism Removal (CPR): 0.223ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock cpu_clk rise edge) 0.000 0.000 r
|
|
clock source latency -1.848 -1.848
|
|
propagated clock network latency
|
|
1.384 -0.465
|
|
SLICE_X3Y49 FDCE 0.000 -0.465 r u_Axi_CDC/wFifo/pushCC_pushPtr_reg[0]/C
|
|
SLICE_X3Y49 FDCE (Prop_fdce_C_Q) 0.141 -0.324 r u_Axi_CDC/wFifo/pushCC_pushPtr_reg[0]/Q
|
|
net (fo=62, routed) 0.330 0.007 u_Axi_CDC/wFifo/ram_reg_0_7_24_29/ADDRD0
|
|
SLICE_X2Y49 RAMD32 r u_Axi_CDC/wFifo/ram_reg_0_7_24_29/RAMA/WADR0
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock cpu_clk rise edge) 0.000 0.000 r
|
|
clock source latency -1.947 -1.947
|
|
propagated clock network latency
|
|
1.718 -0.229
|
|
clock pessimism -0.223 -0.452
|
|
SLICE_X2Y49 RAMD32 (Hold_ramd32_CLK_WADR0)
|
|
0.310 -0.142 u_Axi_CDC/wFifo/ram_reg_0_7_24_29/RAMA
|
|
-------------------------------------------------------------------
|
|
required time 0.142
|
|
arrival time 0.007
|
|
-------------------------------------------------------------------
|
|
slack 0.148
|
|
|
|
Slack (MET) : 0.148ns (arrival time - required time)
|
|
Source: u_Axi_CDC/wFifo/pushCC_pushPtr_reg[0]/C
|
|
(rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns})
|
|
Destination: u_Axi_CDC/wFifo/ram_reg_0_7_24_29/RAMA/WADR0
|
|
(rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns})
|
|
Path Group: cpu_clk
|
|
Path Type: Hold (Min at Fast Process Corner)
|
|
Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns)
|
|
Data Path Delay: 0.471ns (logic 0.141ns (29.919%) route 0.330ns (70.081%))
|
|
Logic Levels: 0
|
|
Clock Path Skew: 0.013ns (DCD - SCD - CPR)
|
|
Destination Clock Delay (DCD): -0.229ns
|
|
Source Clock Delay (SCD): -0.465ns
|
|
Clock Pessimism Removal (CPR): 0.223ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock cpu_clk rise edge) 0.000 0.000 r
|
|
clock source latency -1.848 -1.848
|
|
propagated clock network latency
|
|
1.384 -0.465
|
|
SLICE_X3Y49 FDCE 0.000 -0.465 r u_Axi_CDC/wFifo/pushCC_pushPtr_reg[0]/C
|
|
SLICE_X3Y49 FDCE (Prop_fdce_C_Q) 0.141 -0.324 f u_Axi_CDC/wFifo/pushCC_pushPtr_reg[0]/Q
|
|
net (fo=62, routed) 0.330 0.007 u_Axi_CDC/wFifo/ram_reg_0_7_24_29/ADDRD0
|
|
SLICE_X2Y49 RAMD32 f u_Axi_CDC/wFifo/ram_reg_0_7_24_29/RAMA/WADR0
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock cpu_clk rise edge) 0.000 0.000 r
|
|
clock source latency -1.947 -1.947
|
|
propagated clock network latency
|
|
1.718 -0.229
|
|
clock pessimism -0.223 -0.452
|
|
SLICE_X2Y49 RAMD32 (Hold_ramd32_CLK_WADR0)
|
|
0.310 -0.142 u_Axi_CDC/wFifo/ram_reg_0_7_24_29/RAMA
|
|
-------------------------------------------------------------------
|
|
required time 0.142
|
|
arrival time 0.007
|
|
-------------------------------------------------------------------
|
|
slack 0.148
|
|
|
|
Slack (MET) : 0.148ns (arrival time - required time)
|
|
Source: u_Axi_CDC/wFifo/pushCC_pushPtr_reg[0]/C
|
|
(rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns})
|
|
Destination: u_Axi_CDC/wFifo/ram_reg_0_7_24_29/RAMA_D1/WADR0
|
|
(rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns})
|
|
Path Group: cpu_clk
|
|
Path Type: Hold (Min at Fast Process Corner)
|
|
Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns)
|
|
Data Path Delay: 0.471ns (logic 0.141ns (29.919%) route 0.330ns (70.081%))
|
|
Logic Levels: 0
|
|
Clock Path Skew: 0.013ns (DCD - SCD - CPR)
|
|
Destination Clock Delay (DCD): -0.229ns
|
|
Source Clock Delay (SCD): -0.465ns
|
|
Clock Pessimism Removal (CPR): 0.223ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock cpu_clk rise edge) 0.000 0.000 r
|
|
clock source latency -1.848 -1.848
|
|
propagated clock network latency
|
|
1.384 -0.465
|
|
SLICE_X3Y49 FDCE 0.000 -0.465 r u_Axi_CDC/wFifo/pushCC_pushPtr_reg[0]/C
|
|
SLICE_X3Y49 FDCE (Prop_fdce_C_Q) 0.141 -0.324 r u_Axi_CDC/wFifo/pushCC_pushPtr_reg[0]/Q
|
|
net (fo=62, routed) 0.330 0.007 u_Axi_CDC/wFifo/ram_reg_0_7_24_29/ADDRD0
|
|
SLICE_X2Y49 RAMD32 r u_Axi_CDC/wFifo/ram_reg_0_7_24_29/RAMA_D1/WADR0
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock cpu_clk rise edge) 0.000 0.000 r
|
|
clock source latency -1.947 -1.947
|
|
propagated clock network latency
|
|
1.718 -0.229
|
|
clock pessimism -0.223 -0.452
|
|
SLICE_X2Y49 RAMD32 (Hold_ramd32_CLK_WADR0)
|
|
0.310 -0.142 u_Axi_CDC/wFifo/ram_reg_0_7_24_29/RAMA_D1
|
|
-------------------------------------------------------------------
|
|
required time 0.142
|
|
arrival time 0.007
|
|
-------------------------------------------------------------------
|
|
slack 0.148
|
|
|
|
Slack (MET) : 0.148ns (arrival time - required time)
|
|
Source: u_Axi_CDC/wFifo/pushCC_pushPtr_reg[0]/C
|
|
(rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns})
|
|
Destination: u_Axi_CDC/wFifo/ram_reg_0_7_24_29/RAMA_D1/WADR0
|
|
(rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns})
|
|
Path Group: cpu_clk
|
|
Path Type: Hold (Min at Fast Process Corner)
|
|
Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns)
|
|
Data Path Delay: 0.471ns (logic 0.141ns (29.919%) route 0.330ns (70.081%))
|
|
Logic Levels: 0
|
|
Clock Path Skew: 0.013ns (DCD - SCD - CPR)
|
|
Destination Clock Delay (DCD): -0.229ns
|
|
Source Clock Delay (SCD): -0.465ns
|
|
Clock Pessimism Removal (CPR): 0.223ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock cpu_clk rise edge) 0.000 0.000 r
|
|
clock source latency -1.848 -1.848
|
|
propagated clock network latency
|
|
1.384 -0.465
|
|
SLICE_X3Y49 FDCE 0.000 -0.465 r u_Axi_CDC/wFifo/pushCC_pushPtr_reg[0]/C
|
|
SLICE_X3Y49 FDCE (Prop_fdce_C_Q) 0.141 -0.324 f u_Axi_CDC/wFifo/pushCC_pushPtr_reg[0]/Q
|
|
net (fo=62, routed) 0.330 0.007 u_Axi_CDC/wFifo/ram_reg_0_7_24_29/ADDRD0
|
|
SLICE_X2Y49 RAMD32 f u_Axi_CDC/wFifo/ram_reg_0_7_24_29/RAMA_D1/WADR0
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock cpu_clk rise edge) 0.000 0.000 r
|
|
clock source latency -1.947 -1.947
|
|
propagated clock network latency
|
|
1.718 -0.229
|
|
clock pessimism -0.223 -0.452
|
|
SLICE_X2Y49 RAMD32 (Hold_ramd32_CLK_WADR0)
|
|
0.310 -0.142 u_Axi_CDC/wFifo/ram_reg_0_7_24_29/RAMA_D1
|
|
-------------------------------------------------------------------
|
|
required time 0.142
|
|
arrival time 0.007
|
|
-------------------------------------------------------------------
|
|
slack 0.148
|
|
|
|
Slack (MET) : 0.148ns (arrival time - required time)
|
|
Source: u_Axi_CDC/wFifo/pushCC_pushPtr_reg[0]/C
|
|
(rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns})
|
|
Destination: u_Axi_CDC/wFifo/ram_reg_0_7_24_29/RAMB/WADR0
|
|
(rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns})
|
|
Path Group: cpu_clk
|
|
Path Type: Hold (Min at Fast Process Corner)
|
|
Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns)
|
|
Data Path Delay: 0.471ns (logic 0.141ns (29.919%) route 0.330ns (70.081%))
|
|
Logic Levels: 0
|
|
Clock Path Skew: 0.013ns (DCD - SCD - CPR)
|
|
Destination Clock Delay (DCD): -0.229ns
|
|
Source Clock Delay (SCD): -0.465ns
|
|
Clock Pessimism Removal (CPR): 0.223ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock cpu_clk rise edge) 0.000 0.000 r
|
|
clock source latency -1.848 -1.848
|
|
propagated clock network latency
|
|
1.384 -0.465
|
|
SLICE_X3Y49 FDCE 0.000 -0.465 r u_Axi_CDC/wFifo/pushCC_pushPtr_reg[0]/C
|
|
SLICE_X3Y49 FDCE (Prop_fdce_C_Q) 0.141 -0.324 r u_Axi_CDC/wFifo/pushCC_pushPtr_reg[0]/Q
|
|
net (fo=62, routed) 0.330 0.007 u_Axi_CDC/wFifo/ram_reg_0_7_24_29/ADDRD0
|
|
SLICE_X2Y49 RAMD32 r u_Axi_CDC/wFifo/ram_reg_0_7_24_29/RAMB/WADR0
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock cpu_clk rise edge) 0.000 0.000 r
|
|
clock source latency -1.947 -1.947
|
|
propagated clock network latency
|
|
1.718 -0.229
|
|
clock pessimism -0.223 -0.452
|
|
SLICE_X2Y49 RAMD32 (Hold_ramd32_CLK_WADR0)
|
|
0.310 -0.142 u_Axi_CDC/wFifo/ram_reg_0_7_24_29/RAMB
|
|
-------------------------------------------------------------------
|
|
required time 0.142
|
|
arrival time 0.007
|
|
-------------------------------------------------------------------
|
|
slack 0.148
|
|
|
|
Slack (MET) : 0.148ns (arrival time - required time)
|
|
Source: u_Axi_CDC/wFifo/pushCC_pushPtr_reg[0]/C
|
|
(rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns})
|
|
Destination: u_Axi_CDC/wFifo/ram_reg_0_7_24_29/RAMB/WADR0
|
|
(rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns})
|
|
Path Group: cpu_clk
|
|
Path Type: Hold (Min at Fast Process Corner)
|
|
Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns)
|
|
Data Path Delay: 0.471ns (logic 0.141ns (29.919%) route 0.330ns (70.081%))
|
|
Logic Levels: 0
|
|
Clock Path Skew: 0.013ns (DCD - SCD - CPR)
|
|
Destination Clock Delay (DCD): -0.229ns
|
|
Source Clock Delay (SCD): -0.465ns
|
|
Clock Pessimism Removal (CPR): 0.223ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock cpu_clk rise edge) 0.000 0.000 r
|
|
clock source latency -1.848 -1.848
|
|
propagated clock network latency
|
|
1.384 -0.465
|
|
SLICE_X3Y49 FDCE 0.000 -0.465 r u_Axi_CDC/wFifo/pushCC_pushPtr_reg[0]/C
|
|
SLICE_X3Y49 FDCE (Prop_fdce_C_Q) 0.141 -0.324 f u_Axi_CDC/wFifo/pushCC_pushPtr_reg[0]/Q
|
|
net (fo=62, routed) 0.330 0.007 u_Axi_CDC/wFifo/ram_reg_0_7_24_29/ADDRD0
|
|
SLICE_X2Y49 RAMD32 f u_Axi_CDC/wFifo/ram_reg_0_7_24_29/RAMB/WADR0
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock cpu_clk rise edge) 0.000 0.000 r
|
|
clock source latency -1.947 -1.947
|
|
propagated clock network latency
|
|
1.718 -0.229
|
|
clock pessimism -0.223 -0.452
|
|
SLICE_X2Y49 RAMD32 (Hold_ramd32_CLK_WADR0)
|
|
0.310 -0.142 u_Axi_CDC/wFifo/ram_reg_0_7_24_29/RAMB
|
|
-------------------------------------------------------------------
|
|
required time 0.142
|
|
arrival time 0.007
|
|
-------------------------------------------------------------------
|
|
slack 0.148
|
|
|
|
Slack (MET) : 0.479ns (arrival time - required time)
|
|
Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/buffers_1_reg/C
|
|
(rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/popCC_ptrToPush_reg[0]/CLR
|
|
(removal check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Path Group: **async_default**
|
|
Path Type: Removal (Min at Fast Process Corner)
|
|
Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns)
|
|
Data Path Delay: 0.427ns (logic 0.227ns (53.157%) route 0.200ns (46.843%))
|
|
Logic Levels: 1 (LUT1=1)
|
|
Clock Path Skew: 0.015ns (DCD - SCD - CPR)
|
|
Destination Clock Delay (DCD): -0.341ns
|
|
Source Clock Delay (SCD): -0.570ns
|
|
Clock Pessimism Removal (CPR): 0.214ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock sys_clk rise edge) 0.000 0.000 r
|
|
clock source latency -1.848 -1.848
|
|
propagated clock network latency
|
|
1.278 -0.570
|
|
SLICE_X13Y87 FDCE 0.000 -0.570 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/buffers_1_reg/C
|
|
SLICE_X13Y87 FDCE (Prop_fdce_C_Q) 0.128 -0.442 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/buffers_1_reg/Q
|
|
net (fo=1, routed) 0.053 -0.389 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/buffers_1
|
|
SLICE_X13Y87 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/popCC_popPtr[2]_i_2__2/I0
|
|
SLICE_X13Y87 LUT1 (Prop_lut1_I0_O) 0.099 -0.290 f u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/popCC_popPtr[2]_i_2__2/O
|
|
net (fo=30, routed) 0.147 -0.143 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/buffers_0_reg[3]
|
|
SLICE_X14Y87 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/popCC_ptrToPush_reg[0]/CLR
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock sys_clk rise edge) 0.000 0.000 r
|
|
clock source latency -1.947 -1.947
|
|
propagated clock network latency
|
|
1.606 -0.341
|
|
clock pessimism -0.214 -0.555
|
|
SLICE_X14Y87 FDCE (Remov_fdce_C_CLR) -0.067 -0.622 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/popCC_ptrToPush_reg[0]
|
|
-------------------------------------------------------------------
|
|
required time 0.622
|
|
arrival time -0.143
|
|
-------------------------------------------------------------------
|
|
slack 0.479
|
|
|
|
Slack (MET) : 0.479ns (arrival time - required time)
|
|
Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/buffers_1_reg/C
|
|
(rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/popCC_ptrToPush_reg[1]/CLR
|
|
(removal check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Path Group: **async_default**
|
|
Path Type: Removal (Min at Fast Process Corner)
|
|
Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns)
|
|
Data Path Delay: 0.427ns (logic 0.227ns (53.157%) route 0.200ns (46.843%))
|
|
Logic Levels: 1 (LUT1=1)
|
|
Clock Path Skew: 0.015ns (DCD - SCD - CPR)
|
|
Destination Clock Delay (DCD): -0.341ns
|
|
Source Clock Delay (SCD): -0.570ns
|
|
Clock Pessimism Removal (CPR): 0.214ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock sys_clk rise edge) 0.000 0.000 r
|
|
clock source latency -1.848 -1.848
|
|
propagated clock network latency
|
|
1.278 -0.570
|
|
SLICE_X13Y87 FDCE 0.000 -0.570 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/buffers_1_reg/C
|
|
SLICE_X13Y87 FDCE (Prop_fdce_C_Q) 0.128 -0.442 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/buffers_1_reg/Q
|
|
net (fo=1, routed) 0.053 -0.389 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/buffers_1
|
|
SLICE_X13Y87 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/popCC_popPtr[2]_i_2__2/I0
|
|
SLICE_X13Y87 LUT1 (Prop_lut1_I0_O) 0.099 -0.290 f u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/popCC_popPtr[2]_i_2__2/O
|
|
net (fo=30, routed) 0.147 -0.143 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/buffers_0_reg[3]
|
|
SLICE_X14Y87 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/popCC_ptrToPush_reg[1]/CLR
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock sys_clk rise edge) 0.000 0.000 r
|
|
clock source latency -1.947 -1.947
|
|
propagated clock network latency
|
|
1.606 -0.341
|
|
clock pessimism -0.214 -0.555
|
|
SLICE_X14Y87 FDCE (Remov_fdce_C_CLR) -0.067 -0.622 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/popCC_ptrToPush_reg[1]
|
|
-------------------------------------------------------------------
|
|
required time 0.622
|
|
arrival time -0.143
|
|
-------------------------------------------------------------------
|
|
slack 0.479
|
|
|
|
Slack (MET) : 0.479ns (arrival time - required time)
|
|
Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/buffers_1_reg/C
|
|
(rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/popCC_ptrToPush_reg[2]/CLR
|
|
(removal check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Path Group: **async_default**
|
|
Path Type: Removal (Min at Fast Process Corner)
|
|
Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns)
|
|
Data Path Delay: 0.427ns (logic 0.227ns (53.157%) route 0.200ns (46.843%))
|
|
Logic Levels: 1 (LUT1=1)
|
|
Clock Path Skew: 0.015ns (DCD - SCD - CPR)
|
|
Destination Clock Delay (DCD): -0.341ns
|
|
Source Clock Delay (SCD): -0.570ns
|
|
Clock Pessimism Removal (CPR): 0.214ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock sys_clk rise edge) 0.000 0.000 r
|
|
clock source latency -1.848 -1.848
|
|
propagated clock network latency
|
|
1.278 -0.570
|
|
SLICE_X13Y87 FDCE 0.000 -0.570 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/buffers_1_reg/C
|
|
SLICE_X13Y87 FDCE (Prop_fdce_C_Q) 0.128 -0.442 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/buffers_1_reg/Q
|
|
net (fo=1, routed) 0.053 -0.389 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/buffers_1
|
|
SLICE_X13Y87 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/popCC_popPtr[2]_i_2__2/I0
|
|
SLICE_X13Y87 LUT1 (Prop_lut1_I0_O) 0.099 -0.290 f u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/popCC_popPtr[2]_i_2__2/O
|
|
net (fo=30, routed) 0.147 -0.143 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/buffers_0_reg[3]
|
|
SLICE_X14Y87 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/popCC_ptrToPush_reg[2]/CLR
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock sys_clk rise edge) 0.000 0.000 r
|
|
clock source latency -1.947 -1.947
|
|
propagated clock network latency
|
|
1.606 -0.341
|
|
clock pessimism -0.214 -0.555
|
|
SLICE_X14Y87 FDCE (Remov_fdce_C_CLR) -0.067 -0.622 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/popCC_ptrToPush_reg[2]
|
|
-------------------------------------------------------------------
|
|
required time 0.622
|
|
arrival time -0.143
|
|
-------------------------------------------------------------------
|
|
slack 0.479
|
|
|
|
Slack (MET) : 0.504ns (arrival time - required time)
|
|
Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/buffers_1_reg/C
|
|
(rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/pushToPopGray_buffercc/buffers_0_reg[2]/CLR
|
|
(removal check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Path Group: **async_default**
|
|
Path Type: Removal (Min at Fast Process Corner)
|
|
Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns)
|
|
Data Path Delay: 0.427ns (logic 0.227ns (53.157%) route 0.200ns (46.843%))
|
|
Logic Levels: 1 (LUT1=1)
|
|
Clock Path Skew: 0.015ns (DCD - SCD - CPR)
|
|
Destination Clock Delay (DCD): -0.341ns
|
|
Source Clock Delay (SCD): -0.570ns
|
|
Clock Pessimism Removal (CPR): 0.214ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock sys_clk rise edge) 0.000 0.000 r
|
|
clock source latency -1.848 -1.848
|
|
propagated clock network latency
|
|
1.278 -0.570
|
|
SLICE_X13Y87 FDCE 0.000 -0.570 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/buffers_1_reg/C
|
|
SLICE_X13Y87 FDCE (Prop_fdce_C_Q) 0.128 -0.442 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/buffers_1_reg/Q
|
|
net (fo=1, routed) 0.053 -0.389 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/buffers_1
|
|
SLICE_X13Y87 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/popCC_popPtr[2]_i_2__2/I0
|
|
SLICE_X13Y87 LUT1 (Prop_lut1_I0_O) 0.099 -0.290 f u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/popCC_popPtr[2]_i_2__2/O
|
|
net (fo=30, routed) 0.147 -0.143 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/pushToPopGray_buffercc/buffers_0_reg[3]_0
|
|
SLICE_X15Y87 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/pushToPopGray_buffercc/buffers_0_reg[2]/CLR
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock sys_clk rise edge) 0.000 0.000 r
|
|
clock source latency -1.947 -1.947
|
|
propagated clock network latency
|
|
1.606 -0.341
|
|
clock pessimism -0.214 -0.555
|
|
SLICE_X15Y87 FDCE (Remov_fdce_C_CLR) -0.092 -0.647 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/pushToPopGray_buffercc/buffers_0_reg[2]
|
|
-------------------------------------------------------------------
|
|
required time 0.647
|
|
arrival time -0.143
|
|
-------------------------------------------------------------------
|
|
slack 0.504
|
|
|
|
Slack (MET) : 0.504ns (arrival time - required time)
|
|
Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/buffers_1_reg/C
|
|
(rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/pushToPopGray_buffercc/buffers_0_reg[3]/CLR
|
|
(removal check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Path Group: **async_default**
|
|
Path Type: Removal (Min at Fast Process Corner)
|
|
Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns)
|
|
Data Path Delay: 0.427ns (logic 0.227ns (53.157%) route 0.200ns (46.843%))
|
|
Logic Levels: 1 (LUT1=1)
|
|
Clock Path Skew: 0.015ns (DCD - SCD - CPR)
|
|
Destination Clock Delay (DCD): -0.341ns
|
|
Source Clock Delay (SCD): -0.570ns
|
|
Clock Pessimism Removal (CPR): 0.214ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock sys_clk rise edge) 0.000 0.000 r
|
|
clock source latency -1.848 -1.848
|
|
propagated clock network latency
|
|
1.278 -0.570
|
|
SLICE_X13Y87 FDCE 0.000 -0.570 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/buffers_1_reg/C
|
|
SLICE_X13Y87 FDCE (Prop_fdce_C_Q) 0.128 -0.442 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/buffers_1_reg/Q
|
|
net (fo=1, routed) 0.053 -0.389 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/buffers_1
|
|
SLICE_X13Y87 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/popCC_popPtr[2]_i_2__2/I0
|
|
SLICE_X13Y87 LUT1 (Prop_lut1_I0_O) 0.099 -0.290 f u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/popCC_popPtr[2]_i_2__2/O
|
|
net (fo=30, routed) 0.147 -0.143 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/pushToPopGray_buffercc/buffers_0_reg[3]_0
|
|
SLICE_X15Y87 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/pushToPopGray_buffercc/buffers_0_reg[3]/CLR
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock sys_clk rise edge) 0.000 0.000 r
|
|
clock source latency -1.947 -1.947
|
|
propagated clock network latency
|
|
1.606 -0.341
|
|
clock pessimism -0.214 -0.555
|
|
SLICE_X15Y87 FDCE (Remov_fdce_C_CLR) -0.092 -0.647 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/pushToPopGray_buffercc/buffers_0_reg[3]
|
|
-------------------------------------------------------------------
|
|
required time 0.647
|
|
arrival time -0.143
|
|
-------------------------------------------------------------------
|
|
slack 0.504
|
|
|
|
Slack (MET) : 0.504ns (arrival time - required time)
|
|
Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/buffers_1_reg/C
|
|
(rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/pushToPopGray_buffercc/buffers_1_reg[2]/CLR
|
|
(removal check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Path Group: **async_default**
|
|
Path Type: Removal (Min at Fast Process Corner)
|
|
Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns)
|
|
Data Path Delay: 0.427ns (logic 0.227ns (53.157%) route 0.200ns (46.843%))
|
|
Logic Levels: 1 (LUT1=1)
|
|
Clock Path Skew: 0.015ns (DCD - SCD - CPR)
|
|
Destination Clock Delay (DCD): -0.341ns
|
|
Source Clock Delay (SCD): -0.570ns
|
|
Clock Pessimism Removal (CPR): 0.214ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock sys_clk rise edge) 0.000 0.000 r
|
|
clock source latency -1.848 -1.848
|
|
propagated clock network latency
|
|
1.278 -0.570
|
|
SLICE_X13Y87 FDCE 0.000 -0.570 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/buffers_1_reg/C
|
|
SLICE_X13Y87 FDCE (Prop_fdce_C_Q) 0.128 -0.442 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/buffers_1_reg/Q
|
|
net (fo=1, routed) 0.053 -0.389 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/buffers_1
|
|
SLICE_X13Y87 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/popCC_popPtr[2]_i_2__2/I0
|
|
SLICE_X13Y87 LUT1 (Prop_lut1_I0_O) 0.099 -0.290 f u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/popCC_popPtr[2]_i_2__2/O
|
|
net (fo=30, routed) 0.147 -0.143 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/pushToPopGray_buffercc/buffers_0_reg[3]_0
|
|
SLICE_X15Y87 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/pushToPopGray_buffercc/buffers_1_reg[2]/CLR
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock sys_clk rise edge) 0.000 0.000 r
|
|
clock source latency -1.947 -1.947
|
|
propagated clock network latency
|
|
1.606 -0.341
|
|
clock pessimism -0.214 -0.555
|
|
SLICE_X15Y87 FDCE (Remov_fdce_C_CLR) -0.092 -0.647 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/pushToPopGray_buffercc/buffers_1_reg[2]
|
|
-------------------------------------------------------------------
|
|
required time 0.647
|
|
arrival time -0.143
|
|
-------------------------------------------------------------------
|
|
slack 0.504
|
|
|
|
Slack (MET) : 0.504ns (arrival time - required time)
|
|
Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/buffers_1_reg/C
|
|
(rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/pushToPopGray_buffercc/buffers_1_reg[3]/CLR
|
|
(removal check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Path Group: **async_default**
|
|
Path Type: Removal (Min at Fast Process Corner)
|
|
Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns)
|
|
Data Path Delay: 0.427ns (logic 0.227ns (53.157%) route 0.200ns (46.843%))
|
|
Logic Levels: 1 (LUT1=1)
|
|
Clock Path Skew: 0.015ns (DCD - SCD - CPR)
|
|
Destination Clock Delay (DCD): -0.341ns
|
|
Source Clock Delay (SCD): -0.570ns
|
|
Clock Pessimism Removal (CPR): 0.214ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock sys_clk rise edge) 0.000 0.000 r
|
|
clock source latency -1.848 -1.848
|
|
propagated clock network latency
|
|
1.278 -0.570
|
|
SLICE_X13Y87 FDCE 0.000 -0.570 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/buffers_1_reg/C
|
|
SLICE_X13Y87 FDCE (Prop_fdce_C_Q) 0.128 -0.442 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/buffers_1_reg/Q
|
|
net (fo=1, routed) 0.053 -0.389 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/buffers_1
|
|
SLICE_X13Y87 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/popCC_popPtr[2]_i_2__2/I0
|
|
SLICE_X13Y87 LUT1 (Prop_lut1_I0_O) 0.099 -0.290 f u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/popCC_popPtr[2]_i_2__2/O
|
|
net (fo=30, routed) 0.147 -0.143 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/pushToPopGray_buffercc/buffers_0_reg[3]_0
|
|
SLICE_X15Y87 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/pushToPopGray_buffercc/buffers_1_reg[3]/CLR
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock sys_clk rise edge) 0.000 0.000 r
|
|
clock source latency -1.947 -1.947
|
|
propagated clock network latency
|
|
1.606 -0.341
|
|
clock pessimism -0.214 -0.555
|
|
SLICE_X15Y87 FDCE (Remov_fdce_C_CLR) -0.092 -0.647 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/pushToPopGray_buffercc/buffers_1_reg[3]
|
|
-------------------------------------------------------------------
|
|
required time 0.647
|
|
arrival time -0.143
|
|
-------------------------------------------------------------------
|
|
slack 0.504
|
|
|
|
Slack (MET) : 0.524ns (arrival time - required time)
|
|
Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/buffers_1_reg/C
|
|
(rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/popCC_ptrToPush_reg[3]/CLR
|
|
(removal check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Path Group: **async_default**
|
|
Path Type: Removal (Min at Fast Process Corner)
|
|
Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns)
|
|
Data Path Delay: 0.468ns (logic 0.227ns (48.556%) route 0.241ns (51.444%))
|
|
Logic Levels: 1 (LUT1=1)
|
|
Clock Path Skew: 0.036ns (DCD - SCD - CPR)
|
|
Destination Clock Delay (DCD): -0.342ns
|
|
Source Clock Delay (SCD): -0.570ns
|
|
Clock Pessimism Removal (CPR): 0.192ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock sys_clk rise edge) 0.000 0.000 r
|
|
clock source latency -1.848 -1.848
|
|
propagated clock network latency
|
|
1.278 -0.570
|
|
SLICE_X13Y87 FDCE 0.000 -0.570 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/buffers_1_reg/C
|
|
SLICE_X13Y87 FDCE (Prop_fdce_C_Q) 0.128 -0.442 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/buffers_1_reg/Q
|
|
net (fo=1, routed) 0.053 -0.389 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/buffers_1
|
|
SLICE_X13Y87 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/popCC_popPtr[2]_i_2__2/I0
|
|
SLICE_X13Y87 LUT1 (Prop_lut1_I0_O) 0.099 -0.290 f u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/popCC_popPtr[2]_i_2__2/O
|
|
net (fo=30, routed) 0.187 -0.103 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/buffers_0_reg[3]
|
|
SLICE_X17Y86 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/popCC_ptrToPush_reg[3]/CLR
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock sys_clk rise edge) 0.000 0.000 r
|
|
clock source latency -1.947 -1.947
|
|
propagated clock network latency
|
|
1.605 -0.342
|
|
clock pessimism -0.192 -0.534
|
|
SLICE_X17Y86 FDCE (Remov_fdce_C_CLR) -0.092 -0.626 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/popCC_ptrToPush_reg[3]
|
|
-------------------------------------------------------------------
|
|
required time 0.626
|
|
arrival time -0.103
|
|
-------------------------------------------------------------------
|
|
slack 0.524
|
|
|
|
Slack (MET) : 0.548ns (arrival time - required time)
|
|
Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/buffers_1_reg/C
|
|
(rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/popCC_popPtr_reg[1]/CLR
|
|
(removal check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Path Group: **async_default**
|
|
Path Type: Removal (Min at Fast Process Corner)
|
|
Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns)
|
|
Data Path Delay: 0.470ns (logic 0.227ns (48.316%) route 0.243ns (51.684%))
|
|
Logic Levels: 1 (LUT1=1)
|
|
Clock Path Skew: 0.014ns (DCD - SCD - CPR)
|
|
Destination Clock Delay (DCD): -0.342ns
|
|
Source Clock Delay (SCD): -0.570ns
|
|
Clock Pessimism Removal (CPR): 0.214ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock sys_clk rise edge) 0.000 0.000 r
|
|
clock source latency -1.848 -1.848
|
|
propagated clock network latency
|
|
1.278 -0.570
|
|
SLICE_X13Y87 FDCE 0.000 -0.570 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/buffers_1_reg/C
|
|
SLICE_X13Y87 FDCE (Prop_fdce_C_Q) 0.128 -0.442 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/buffers_1_reg/Q
|
|
net (fo=1, routed) 0.053 -0.389 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/buffers_1
|
|
SLICE_X13Y87 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/popCC_popPtr[2]_i_2__2/I0
|
|
SLICE_X13Y87 LUT1 (Prop_lut1_I0_O) 0.099 -0.290 f u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/popCC_popPtr[2]_i_2__2/O
|
|
net (fo=30, routed) 0.189 -0.101 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/buffers_0_reg[3]
|
|
SLICE_X15Y85 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/popCC_popPtr_reg[1]/CLR
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock sys_clk rise edge) 0.000 0.000 r
|
|
clock source latency -1.947 -1.947
|
|
propagated clock network latency
|
|
1.605 -0.342
|
|
clock pessimism -0.214 -0.556
|
|
SLICE_X15Y85 FDCE (Remov_fdce_C_CLR) -0.092 -0.648 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/popCC_popPtr_reg[1]
|
|
-------------------------------------------------------------------
|
|
required time 0.648
|
|
arrival time -0.101
|
|
-------------------------------------------------------------------
|
|
slack 0.548
|
|
|
|
Slack (MET) : 0.558ns (arrival time - required time)
|
|
Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/buffers_1_reg/C
|
|
(rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/popCC_addressGen_rValid_reg/CLR
|
|
(removal check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Path Group: **async_default**
|
|
Path Type: Removal (Min at Fast Process Corner)
|
|
Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns)
|
|
Data Path Delay: 0.508ns (logic 0.227ns (44.714%) route 0.281ns (55.286%))
|
|
Logic Levels: 1 (LUT1=1)
|
|
Clock Path Skew: 0.017ns (DCD - SCD - CPR)
|
|
Destination Clock Delay (DCD): -0.339ns
|
|
Source Clock Delay (SCD): -0.570ns
|
|
Clock Pessimism Removal (CPR): 0.214ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock sys_clk rise edge) 0.000 0.000 r
|
|
clock source latency -1.848 -1.848
|
|
propagated clock network latency
|
|
1.278 -0.570
|
|
SLICE_X13Y87 FDCE 0.000 -0.570 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/buffers_1_reg/C
|
|
SLICE_X13Y87 FDCE (Prop_fdce_C_Q) 0.128 -0.442 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/buffers_1_reg/Q
|
|
net (fo=1, routed) 0.053 -0.389 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/buffers_1
|
|
SLICE_X13Y87 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/popCC_popPtr[2]_i_2__2/I0
|
|
SLICE_X13Y87 LUT1 (Prop_lut1_I0_O) 0.099 -0.290 f u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/popCC_popPtr[2]_i_2__2/O
|
|
net (fo=30, routed) 0.227 -0.063 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/buffers_0_reg[3]
|
|
SLICE_X14Y88 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/popCC_addressGen_rValid_reg/CLR
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock sys_clk rise edge) 0.000 0.000 r
|
|
clock source latency -1.947 -1.947
|
|
propagated clock network latency
|
|
1.608 -0.339
|
|
clock pessimism -0.214 -0.553
|
|
SLICE_X14Y88 FDCE (Remov_fdce_C_CLR) -0.067 -0.620 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/popCC_addressGen_rValid_reg
|
|
-------------------------------------------------------------------
|
|
required time 0.620
|
|
arrival time -0.063
|
|
-------------------------------------------------------------------
|
|
slack 0.558
|
|
|
|
Slack (MET) : 0.583ns (arrival time - required time)
|
|
Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/buffers_1_reg/C
|
|
(rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/pushToPopGray_buffercc/buffers_0_reg[0]/CLR
|
|
(removal check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Path Group: **async_default**
|
|
Path Type: Removal (Min at Fast Process Corner)
|
|
Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns)
|
|
Data Path Delay: 0.508ns (logic 0.227ns (44.714%) route 0.281ns (55.286%))
|
|
Logic Levels: 1 (LUT1=1)
|
|
Clock Path Skew: 0.017ns (DCD - SCD - CPR)
|
|
Destination Clock Delay (DCD): -0.339ns
|
|
Source Clock Delay (SCD): -0.570ns
|
|
Clock Pessimism Removal (CPR): 0.214ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock sys_clk rise edge) 0.000 0.000 r
|
|
clock source latency -1.848 -1.848
|
|
propagated clock network latency
|
|
1.278 -0.570
|
|
SLICE_X13Y87 FDCE 0.000 -0.570 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/buffers_1_reg/C
|
|
SLICE_X13Y87 FDCE (Prop_fdce_C_Q) 0.128 -0.442 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/buffers_1_reg/Q
|
|
net (fo=1, routed) 0.053 -0.389 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/buffers_1
|
|
SLICE_X13Y87 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/popCC_popPtr[2]_i_2__2/I0
|
|
SLICE_X13Y87 LUT1 (Prop_lut1_I0_O) 0.099 -0.290 f u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/popCC_popPtr[2]_i_2__2/O
|
|
net (fo=30, routed) 0.227 -0.063 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/pushToPopGray_buffercc/buffers_0_reg[3]_0
|
|
SLICE_X15Y88 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/pushToPopGray_buffercc/buffers_0_reg[0]/CLR
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock sys_clk rise edge) 0.000 0.000 r
|
|
clock source latency -1.947 -1.947
|
|
propagated clock network latency
|
|
1.608 -0.339
|
|
clock pessimism -0.214 -0.553
|
|
SLICE_X15Y88 FDCE (Remov_fdce_C_CLR) -0.092 -0.645 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/pushToPopGray_buffercc/buffers_0_reg[0]
|
|
-------------------------------------------------------------------
|
|
required time 0.645
|
|
arrival time -0.063
|
|
-------------------------------------------------------------------
|
|
slack 0.583
|
|
|
|
Slack (MET) : 0.583ns (arrival time - required time)
|
|
Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/buffers_1_reg/C
|
|
(rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/pushToPopGray_buffercc/buffers_0_reg[1]/CLR
|
|
(removal check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Path Group: **async_default**
|
|
Path Type: Removal (Min at Fast Process Corner)
|
|
Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns)
|
|
Data Path Delay: 0.508ns (logic 0.227ns (44.714%) route 0.281ns (55.286%))
|
|
Logic Levels: 1 (LUT1=1)
|
|
Clock Path Skew: 0.017ns (DCD - SCD - CPR)
|
|
Destination Clock Delay (DCD): -0.339ns
|
|
Source Clock Delay (SCD): -0.570ns
|
|
Clock Pessimism Removal (CPR): 0.214ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock sys_clk rise edge) 0.000 0.000 r
|
|
clock source latency -1.848 -1.848
|
|
propagated clock network latency
|
|
1.278 -0.570
|
|
SLICE_X13Y87 FDCE 0.000 -0.570 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/buffers_1_reg/C
|
|
SLICE_X13Y87 FDCE (Prop_fdce_C_Q) 0.128 -0.442 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/buffers_1_reg/Q
|
|
net (fo=1, routed) 0.053 -0.389 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/buffers_1
|
|
SLICE_X13Y87 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/popCC_popPtr[2]_i_2__2/I0
|
|
SLICE_X13Y87 LUT1 (Prop_lut1_I0_O) 0.099 -0.290 f u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/popCC_popPtr[2]_i_2__2/O
|
|
net (fo=30, routed) 0.227 -0.063 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/pushToPopGray_buffercc/buffers_0_reg[3]_0
|
|
SLICE_X15Y88 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/pushToPopGray_buffercc/buffers_0_reg[1]/CLR
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock sys_clk rise edge) 0.000 0.000 r
|
|
clock source latency -1.947 -1.947
|
|
propagated clock network latency
|
|
1.608 -0.339
|
|
clock pessimism -0.214 -0.553
|
|
SLICE_X15Y88 FDCE (Remov_fdce_C_CLR) -0.092 -0.645 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/pushToPopGray_buffercc/buffers_0_reg[1]
|
|
-------------------------------------------------------------------
|
|
required time 0.645
|
|
arrival time -0.063
|
|
-------------------------------------------------------------------
|
|
slack 0.583
|
|
|
|
Slack (MET) : 0.583ns (arrival time - required time)
|
|
Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/buffers_1_reg/C
|
|
(rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/pushToPopGray_buffercc/buffers_1_reg[0]/CLR
|
|
(removal check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Path Group: **async_default**
|
|
Path Type: Removal (Min at Fast Process Corner)
|
|
Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns)
|
|
Data Path Delay: 0.508ns (logic 0.227ns (44.714%) route 0.281ns (55.286%))
|
|
Logic Levels: 1 (LUT1=1)
|
|
Clock Path Skew: 0.017ns (DCD - SCD - CPR)
|
|
Destination Clock Delay (DCD): -0.339ns
|
|
Source Clock Delay (SCD): -0.570ns
|
|
Clock Pessimism Removal (CPR): 0.214ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock sys_clk rise edge) 0.000 0.000 r
|
|
clock source latency -1.848 -1.848
|
|
propagated clock network latency
|
|
1.278 -0.570
|
|
SLICE_X13Y87 FDCE 0.000 -0.570 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/buffers_1_reg/C
|
|
SLICE_X13Y87 FDCE (Prop_fdce_C_Q) 0.128 -0.442 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/buffers_1_reg/Q
|
|
net (fo=1, routed) 0.053 -0.389 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/buffers_1
|
|
SLICE_X13Y87 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/popCC_popPtr[2]_i_2__2/I0
|
|
SLICE_X13Y87 LUT1 (Prop_lut1_I0_O) 0.099 -0.290 f u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/popCC_popPtr[2]_i_2__2/O
|
|
net (fo=30, routed) 0.227 -0.063 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/pushToPopGray_buffercc/buffers_0_reg[3]_0
|
|
SLICE_X15Y88 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/pushToPopGray_buffercc/buffers_1_reg[0]/CLR
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock sys_clk rise edge) 0.000 0.000 r
|
|
clock source latency -1.947 -1.947
|
|
propagated clock network latency
|
|
1.608 -0.339
|
|
clock pessimism -0.214 -0.553
|
|
SLICE_X15Y88 FDCE (Remov_fdce_C_CLR) -0.092 -0.645 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/pushToPopGray_buffercc/buffers_1_reg[0]
|
|
-------------------------------------------------------------------
|
|
required time 0.645
|
|
arrival time -0.063
|
|
-------------------------------------------------------------------
|
|
slack 0.583
|
|
|
|
Slack (MET) : 0.583ns (arrival time - required time)
|
|
Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/buffers_1_reg/C
|
|
(rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/pushToPopGray_buffercc/buffers_1_reg[1]/CLR
|
|
(removal check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Path Group: **async_default**
|
|
Path Type: Removal (Min at Fast Process Corner)
|
|
Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns)
|
|
Data Path Delay: 0.508ns (logic 0.227ns (44.714%) route 0.281ns (55.286%))
|
|
Logic Levels: 1 (LUT1=1)
|
|
Clock Path Skew: 0.017ns (DCD - SCD - CPR)
|
|
Destination Clock Delay (DCD): -0.339ns
|
|
Source Clock Delay (SCD): -0.570ns
|
|
Clock Pessimism Removal (CPR): 0.214ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock sys_clk rise edge) 0.000 0.000 r
|
|
clock source latency -1.848 -1.848
|
|
propagated clock network latency
|
|
1.278 -0.570
|
|
SLICE_X13Y87 FDCE 0.000 -0.570 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/buffers_1_reg/C
|
|
SLICE_X13Y87 FDCE (Prop_fdce_C_Q) 0.128 -0.442 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/buffers_1_reg/Q
|
|
net (fo=1, routed) 0.053 -0.389 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/buffers_1
|
|
SLICE_X13Y87 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/popCC_popPtr[2]_i_2__2/I0
|
|
SLICE_X13Y87 LUT1 (Prop_lut1_I0_O) 0.099 -0.290 f u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/popCC_popPtr[2]_i_2__2/O
|
|
net (fo=30, routed) 0.227 -0.063 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/pushToPopGray_buffercc/buffers_0_reg[3]_0
|
|
SLICE_X15Y88 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/pushToPopGray_buffercc/buffers_1_reg[1]/CLR
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock sys_clk rise edge) 0.000 0.000 r
|
|
clock source latency -1.947 -1.947
|
|
propagated clock network latency
|
|
1.608 -0.339
|
|
clock pessimism -0.214 -0.553
|
|
SLICE_X15Y88 FDCE (Remov_fdce_C_CLR) -0.092 -0.645 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/pushToPopGray_buffercc/buffers_1_reg[1]
|
|
-------------------------------------------------------------------
|
|
required time 0.645
|
|
arrival time -0.063
|
|
-------------------------------------------------------------------
|
|
slack 0.583
|
|
|
|
Slack (MET) : 0.613ns (arrival time - required time)
|
|
Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/buffers_1_reg/C
|
|
(rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns})
|
|
Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/popCC_popPtr_reg[2]/CLR
|
|
(removal check against rising-edge clock mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns})
|
|
Path Group: **async_default**
|
|
Path Type: Removal (Min at Fast Process Corner)
|
|
Requirement: 0.000ns (mlkem_clk_clk_pll rise@0.000ns - mlkem_clk_clk_pll rise@0.000ns)
|
|
Data Path Delay: 0.555ns (logic 0.227ns (40.925%) route 0.328ns (59.075%))
|
|
Logic Levels: 1 (LUT1=1)
|
|
Clock Path Skew: 0.034ns (DCD - SCD - CPR)
|
|
Destination Clock Delay (DCD): -0.355ns
|
|
Source Clock Delay (SCD): -0.581ns
|
|
Clock Pessimism Removal (CPR): 0.192ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock mlkem_clk_clk_pll rise edge)
|
|
0.000 0.000 r
|
|
clock source latency -1.848 -1.848
|
|
propagated clock network latency
|
|
1.267 -0.581
|
|
SLICE_X25Y79 FDCE 0.000 -0.581 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/buffers_1_reg/C
|
|
SLICE_X25Y79 FDCE (Prop_fdce_C_Q) 0.128 -0.453 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/buffers_1_reg/Q
|
|
net (fo=1, routed) 0.139 -0.314 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/buffers_1
|
|
SLICE_X25Y79 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/popCC_popPtr[2]_i_2__1/I0
|
|
SLICE_X25Y79 LUT1 (Prop_lut1_I0_O) 0.099 -0.215 f u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/popCC_popPtr[2]_i_2__1/O
|
|
net (fo=43, routed) 0.188 -0.027 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/buffers_0_reg[2]
|
|
SLICE_X28Y79 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/popCC_popPtr_reg[2]/CLR
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock mlkem_clk_clk_pll rise edge)
|
|
0.000 0.000 r
|
|
clock source latency -1.947 -1.947
|
|
propagated clock network latency
|
|
1.592 -0.355
|
|
clock pessimism -0.192 -0.547
|
|
SLICE_X28Y79 FDCE (Remov_fdce_C_CLR) -0.092 -0.639 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/popCC_popPtr_reg[2]
|
|
-------------------------------------------------------------------
|
|
required time 0.639
|
|
arrival time -0.027
|
|
-------------------------------------------------------------------
|
|
slack 0.613
|
|
|
|
Slack (MET) : 0.613ns (arrival time - required time)
|
|
Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/buffers_1_reg/C
|
|
(rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns})
|
|
Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/popCC_ptrToPush_reg[1]/CLR
|
|
(removal check against rising-edge clock mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns})
|
|
Path Group: **async_default**
|
|
Path Type: Removal (Min at Fast Process Corner)
|
|
Requirement: 0.000ns (mlkem_clk_clk_pll rise@0.000ns - mlkem_clk_clk_pll rise@0.000ns)
|
|
Data Path Delay: 0.555ns (logic 0.227ns (40.925%) route 0.328ns (59.075%))
|
|
Logic Levels: 1 (LUT1=1)
|
|
Clock Path Skew: 0.034ns (DCD - SCD - CPR)
|
|
Destination Clock Delay (DCD): -0.355ns
|
|
Source Clock Delay (SCD): -0.581ns
|
|
Clock Pessimism Removal (CPR): 0.192ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock mlkem_clk_clk_pll rise edge)
|
|
0.000 0.000 r
|
|
clock source latency -1.848 -1.848
|
|
propagated clock network latency
|
|
1.267 -0.581
|
|
SLICE_X25Y79 FDCE 0.000 -0.581 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/buffers_1_reg/C
|
|
SLICE_X25Y79 FDCE (Prop_fdce_C_Q) 0.128 -0.453 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/buffers_1_reg/Q
|
|
net (fo=1, routed) 0.139 -0.314 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/buffers_1
|
|
SLICE_X25Y79 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/popCC_popPtr[2]_i_2__1/I0
|
|
SLICE_X25Y79 LUT1 (Prop_lut1_I0_O) 0.099 -0.215 f u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/popCC_popPtr[2]_i_2__1/O
|
|
net (fo=43, routed) 0.188 -0.027 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/buffers_0_reg[2]
|
|
SLICE_X28Y79 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/popCC_ptrToPush_reg[1]/CLR
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock mlkem_clk_clk_pll rise edge)
|
|
0.000 0.000 r
|
|
clock source latency -1.947 -1.947
|
|
propagated clock network latency
|
|
1.592 -0.355
|
|
clock pessimism -0.192 -0.547
|
|
SLICE_X28Y79 FDCE (Remov_fdce_C_CLR) -0.092 -0.639 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/popCC_ptrToPush_reg[1]
|
|
-------------------------------------------------------------------
|
|
required time 0.639
|
|
arrival time -0.027
|
|
-------------------------------------------------------------------
|
|
slack 0.613
|
|
|
|
Slack (MET) : 0.613ns (arrival time - required time)
|
|
Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/buffers_1_reg/C
|
|
(rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns})
|
|
Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/popCC_ptrToPush_reg[2]/CLR
|
|
(removal check against rising-edge clock mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns})
|
|
Path Group: **async_default**
|
|
Path Type: Removal (Min at Fast Process Corner)
|
|
Requirement: 0.000ns (mlkem_clk_clk_pll rise@0.000ns - mlkem_clk_clk_pll rise@0.000ns)
|
|
Data Path Delay: 0.555ns (logic 0.227ns (40.925%) route 0.328ns (59.075%))
|
|
Logic Levels: 1 (LUT1=1)
|
|
Clock Path Skew: 0.034ns (DCD - SCD - CPR)
|
|
Destination Clock Delay (DCD): -0.355ns
|
|
Source Clock Delay (SCD): -0.581ns
|
|
Clock Pessimism Removal (CPR): 0.192ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock mlkem_clk_clk_pll rise edge)
|
|
0.000 0.000 r
|
|
clock source latency -1.848 -1.848
|
|
propagated clock network latency
|
|
1.267 -0.581
|
|
SLICE_X25Y79 FDCE 0.000 -0.581 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/buffers_1_reg/C
|
|
SLICE_X25Y79 FDCE (Prop_fdce_C_Q) 0.128 -0.453 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/buffers_1_reg/Q
|
|
net (fo=1, routed) 0.139 -0.314 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/buffers_1
|
|
SLICE_X25Y79 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/popCC_popPtr[2]_i_2__1/I0
|
|
SLICE_X25Y79 LUT1 (Prop_lut1_I0_O) 0.099 -0.215 f u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/popCC_popPtr[2]_i_2__1/O
|
|
net (fo=43, routed) 0.188 -0.027 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/buffers_0_reg[2]
|
|
SLICE_X28Y79 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/popCC_ptrToPush_reg[2]/CLR
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock mlkem_clk_clk_pll rise edge)
|
|
0.000 0.000 r
|
|
clock source latency -1.947 -1.947
|
|
propagated clock network latency
|
|
1.592 -0.355
|
|
clock pessimism -0.192 -0.547
|
|
SLICE_X28Y79 FDCE (Remov_fdce_C_CLR) -0.092 -0.639 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/popCC_ptrToPush_reg[2]
|
|
-------------------------------------------------------------------
|
|
required time 0.639
|
|
arrival time -0.027
|
|
-------------------------------------------------------------------
|
|
slack 0.613
|
|
|
|
Slack (MET) : 0.629ns (arrival time - required time)
|
|
Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/buffers_1_reg/C
|
|
(rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns})
|
|
Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/pushToPopGray_buffercc/buffers_0_reg[0]/CLR
|
|
(removal check against rising-edge clock mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns})
|
|
Path Group: **async_default**
|
|
Path Type: Removal (Min at Fast Process Corner)
|
|
Requirement: 0.000ns (mlkem_clk_clk_pll rise@0.000ns - mlkem_clk_clk_pll rise@0.000ns)
|
|
Data Path Delay: 0.551ns (logic 0.227ns (41.209%) route 0.324ns (58.791%))
|
|
Logic Levels: 1 (LUT1=1)
|
|
Clock Path Skew: 0.014ns (DCD - SCD - CPR)
|
|
Destination Clock Delay (DCD): -0.353ns
|
|
Source Clock Delay (SCD): -0.581ns
|
|
Clock Pessimism Removal (CPR): 0.214ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock mlkem_clk_clk_pll rise edge)
|
|
0.000 0.000 r
|
|
clock source latency -1.848 -1.848
|
|
propagated clock network latency
|
|
1.267 -0.581
|
|
SLICE_X25Y79 FDCE 0.000 -0.581 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/buffers_1_reg/C
|
|
SLICE_X25Y79 FDCE (Prop_fdce_C_Q) 0.128 -0.453 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/buffers_1_reg/Q
|
|
net (fo=1, routed) 0.139 -0.314 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/buffers_1
|
|
SLICE_X25Y79 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/popCC_popPtr[2]_i_2__1/I0
|
|
SLICE_X25Y79 LUT1 (Prop_lut1_I0_O) 0.099 -0.215 f u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/popCC_popPtr[2]_i_2__1/O
|
|
net (fo=43, routed) 0.184 -0.031 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/pushToPopGray_buffercc/buffers_0_reg[2]_1
|
|
SLICE_X27Y79 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/pushToPopGray_buffercc/buffers_0_reg[0]/CLR
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock mlkem_clk_clk_pll rise edge)
|
|
0.000 0.000 r
|
|
clock source latency -1.947 -1.947
|
|
propagated clock network latency
|
|
1.594 -0.353
|
|
clock pessimism -0.214 -0.567
|
|
SLICE_X27Y79 FDCE (Remov_fdce_C_CLR) -0.092 -0.659 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/pushToPopGray_buffercc/buffers_0_reg[0]
|
|
-------------------------------------------------------------------
|
|
required time 0.659
|
|
arrival time -0.031
|
|
-------------------------------------------------------------------
|
|
slack 0.629
|
|
|
|
Slack (MET) : 0.629ns (arrival time - required time)
|
|
Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/buffers_1_reg/C
|
|
(rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns})
|
|
Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/pushToPopGray_buffercc/buffers_0_reg[1]/CLR
|
|
(removal check against rising-edge clock mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns})
|
|
Path Group: **async_default**
|
|
Path Type: Removal (Min at Fast Process Corner)
|
|
Requirement: 0.000ns (mlkem_clk_clk_pll rise@0.000ns - mlkem_clk_clk_pll rise@0.000ns)
|
|
Data Path Delay: 0.551ns (logic 0.227ns (41.209%) route 0.324ns (58.791%))
|
|
Logic Levels: 1 (LUT1=1)
|
|
Clock Path Skew: 0.014ns (DCD - SCD - CPR)
|
|
Destination Clock Delay (DCD): -0.353ns
|
|
Source Clock Delay (SCD): -0.581ns
|
|
Clock Pessimism Removal (CPR): 0.214ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock mlkem_clk_clk_pll rise edge)
|
|
0.000 0.000 r
|
|
clock source latency -1.848 -1.848
|
|
propagated clock network latency
|
|
1.267 -0.581
|
|
SLICE_X25Y79 FDCE 0.000 -0.581 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/buffers_1_reg/C
|
|
SLICE_X25Y79 FDCE (Prop_fdce_C_Q) 0.128 -0.453 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/buffers_1_reg/Q
|
|
net (fo=1, routed) 0.139 -0.314 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/buffers_1
|
|
SLICE_X25Y79 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/popCC_popPtr[2]_i_2__1/I0
|
|
SLICE_X25Y79 LUT1 (Prop_lut1_I0_O) 0.099 -0.215 f u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/popCC_popPtr[2]_i_2__1/O
|
|
net (fo=43, routed) 0.184 -0.031 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/pushToPopGray_buffercc/buffers_0_reg[2]_1
|
|
SLICE_X27Y79 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/pushToPopGray_buffercc/buffers_0_reg[1]/CLR
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock mlkem_clk_clk_pll rise edge)
|
|
0.000 0.000 r
|
|
clock source latency -1.947 -1.947
|
|
propagated clock network latency
|
|
1.594 -0.353
|
|
clock pessimism -0.214 -0.567
|
|
SLICE_X27Y79 FDCE (Remov_fdce_C_CLR) -0.092 -0.659 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/pushToPopGray_buffercc/buffers_0_reg[1]
|
|
-------------------------------------------------------------------
|
|
required time 0.659
|
|
arrival time -0.031
|
|
-------------------------------------------------------------------
|
|
slack 0.629
|
|
|
|
Slack (MET) : 0.629ns (arrival time - required time)
|
|
Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/buffers_1_reg/C
|
|
(rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns})
|
|
Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/pushToPopGray_buffercc/buffers_0_reg[2]/CLR
|
|
(removal check against rising-edge clock mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns})
|
|
Path Group: **async_default**
|
|
Path Type: Removal (Min at Fast Process Corner)
|
|
Requirement: 0.000ns (mlkem_clk_clk_pll rise@0.000ns - mlkem_clk_clk_pll rise@0.000ns)
|
|
Data Path Delay: 0.551ns (logic 0.227ns (41.209%) route 0.324ns (58.791%))
|
|
Logic Levels: 1 (LUT1=1)
|
|
Clock Path Skew: 0.014ns (DCD - SCD - CPR)
|
|
Destination Clock Delay (DCD): -0.353ns
|
|
Source Clock Delay (SCD): -0.581ns
|
|
Clock Pessimism Removal (CPR): 0.214ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock mlkem_clk_clk_pll rise edge)
|
|
0.000 0.000 r
|
|
clock source latency -1.848 -1.848
|
|
propagated clock network latency
|
|
1.267 -0.581
|
|
SLICE_X25Y79 FDCE 0.000 -0.581 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/buffers_1_reg/C
|
|
SLICE_X25Y79 FDCE (Prop_fdce_C_Q) 0.128 -0.453 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/buffers_1_reg/Q
|
|
net (fo=1, routed) 0.139 -0.314 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/buffers_1
|
|
SLICE_X25Y79 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/popCC_popPtr[2]_i_2__1/I0
|
|
SLICE_X25Y79 LUT1 (Prop_lut1_I0_O) 0.099 -0.215 f u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/popCC_popPtr[2]_i_2__1/O
|
|
net (fo=43, routed) 0.184 -0.031 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/pushToPopGray_buffercc/buffers_0_reg[2]_1
|
|
SLICE_X27Y79 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/pushToPopGray_buffercc/buffers_0_reg[2]/CLR
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock mlkem_clk_clk_pll rise edge)
|
|
0.000 0.000 r
|
|
clock source latency -1.947 -1.947
|
|
propagated clock network latency
|
|
1.594 -0.353
|
|
clock pessimism -0.214 -0.567
|
|
SLICE_X27Y79 FDCE (Remov_fdce_C_CLR) -0.092 -0.659 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/pushToPopGray_buffercc/buffers_0_reg[2]
|
|
-------------------------------------------------------------------
|
|
required time 0.659
|
|
arrival time -0.031
|
|
-------------------------------------------------------------------
|
|
slack 0.629
|
|
|
|
Slack (MET) : 0.629ns (arrival time - required time)
|
|
Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/buffers_1_reg/C
|
|
(rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns})
|
|
Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/pushToPopGray_buffercc/buffers_1_reg[0]/CLR
|
|
(removal check against rising-edge clock mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns})
|
|
Path Group: **async_default**
|
|
Path Type: Removal (Min at Fast Process Corner)
|
|
Requirement: 0.000ns (mlkem_clk_clk_pll rise@0.000ns - mlkem_clk_clk_pll rise@0.000ns)
|
|
Data Path Delay: 0.551ns (logic 0.227ns (41.209%) route 0.324ns (58.791%))
|
|
Logic Levels: 1 (LUT1=1)
|
|
Clock Path Skew: 0.014ns (DCD - SCD - CPR)
|
|
Destination Clock Delay (DCD): -0.353ns
|
|
Source Clock Delay (SCD): -0.581ns
|
|
Clock Pessimism Removal (CPR): 0.214ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock mlkem_clk_clk_pll rise edge)
|
|
0.000 0.000 r
|
|
clock source latency -1.848 -1.848
|
|
propagated clock network latency
|
|
1.267 -0.581
|
|
SLICE_X25Y79 FDCE 0.000 -0.581 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/buffers_1_reg/C
|
|
SLICE_X25Y79 FDCE (Prop_fdce_C_Q) 0.128 -0.453 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/buffers_1_reg/Q
|
|
net (fo=1, routed) 0.139 -0.314 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/buffers_1
|
|
SLICE_X25Y79 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/popCC_popPtr[2]_i_2__1/I0
|
|
SLICE_X25Y79 LUT1 (Prop_lut1_I0_O) 0.099 -0.215 f u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/popCC_popPtr[2]_i_2__1/O
|
|
net (fo=43, routed) 0.184 -0.031 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/pushToPopGray_buffercc/buffers_0_reg[2]_1
|
|
SLICE_X27Y79 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/pushToPopGray_buffercc/buffers_1_reg[0]/CLR
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock mlkem_clk_clk_pll rise edge)
|
|
0.000 0.000 r
|
|
clock source latency -1.947 -1.947
|
|
propagated clock network latency
|
|
1.594 -0.353
|
|
clock pessimism -0.214 -0.567
|
|
SLICE_X27Y79 FDCE (Remov_fdce_C_CLR) -0.092 -0.659 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/pushToPopGray_buffercc/buffers_1_reg[0]
|
|
-------------------------------------------------------------------
|
|
required time 0.659
|
|
arrival time -0.031
|
|
-------------------------------------------------------------------
|
|
slack 0.629
|
|
|
|
Slack (MET) : 0.629ns (arrival time - required time)
|
|
Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/buffers_1_reg/C
|
|
(rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns})
|
|
Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/pushToPopGray_buffercc/buffers_1_reg[1]/CLR
|
|
(removal check against rising-edge clock mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns})
|
|
Path Group: **async_default**
|
|
Path Type: Removal (Min at Fast Process Corner)
|
|
Requirement: 0.000ns (mlkem_clk_clk_pll rise@0.000ns - mlkem_clk_clk_pll rise@0.000ns)
|
|
Data Path Delay: 0.551ns (logic 0.227ns (41.209%) route 0.324ns (58.791%))
|
|
Logic Levels: 1 (LUT1=1)
|
|
Clock Path Skew: 0.014ns (DCD - SCD - CPR)
|
|
Destination Clock Delay (DCD): -0.353ns
|
|
Source Clock Delay (SCD): -0.581ns
|
|
Clock Pessimism Removal (CPR): 0.214ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock mlkem_clk_clk_pll rise edge)
|
|
0.000 0.000 r
|
|
clock source latency -1.848 -1.848
|
|
propagated clock network latency
|
|
1.267 -0.581
|
|
SLICE_X25Y79 FDCE 0.000 -0.581 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/buffers_1_reg/C
|
|
SLICE_X25Y79 FDCE (Prop_fdce_C_Q) 0.128 -0.453 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/buffers_1_reg/Q
|
|
net (fo=1, routed) 0.139 -0.314 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/buffers_1
|
|
SLICE_X25Y79 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/popCC_popPtr[2]_i_2__1/I0
|
|
SLICE_X25Y79 LUT1 (Prop_lut1_I0_O) 0.099 -0.215 f u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/popCC_popPtr[2]_i_2__1/O
|
|
net (fo=43, routed) 0.184 -0.031 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/pushToPopGray_buffercc/buffers_0_reg[2]_1
|
|
SLICE_X27Y79 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/pushToPopGray_buffercc/buffers_1_reg[1]/CLR
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock mlkem_clk_clk_pll rise edge)
|
|
0.000 0.000 r
|
|
clock source latency -1.947 -1.947
|
|
propagated clock network latency
|
|
1.594 -0.353
|
|
clock pessimism -0.214 -0.567
|
|
SLICE_X27Y79 FDCE (Remov_fdce_C_CLR) -0.092 -0.659 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/pushToPopGray_buffercc/buffers_1_reg[1]
|
|
-------------------------------------------------------------------
|
|
required time 0.659
|
|
arrival time -0.031
|
|
-------------------------------------------------------------------
|
|
slack 0.629
|
|
|
|
Slack (MET) : 0.629ns (arrival time - required time)
|
|
Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/buffers_1_reg/C
|
|
(rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns})
|
|
Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/pushToPopGray_buffercc/buffers_1_reg[2]/CLR
|
|
(removal check against rising-edge clock mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns})
|
|
Path Group: **async_default**
|
|
Path Type: Removal (Min at Fast Process Corner)
|
|
Requirement: 0.000ns (mlkem_clk_clk_pll rise@0.000ns - mlkem_clk_clk_pll rise@0.000ns)
|
|
Data Path Delay: 0.551ns (logic 0.227ns (41.209%) route 0.324ns (58.791%))
|
|
Logic Levels: 1 (LUT1=1)
|
|
Clock Path Skew: 0.014ns (DCD - SCD - CPR)
|
|
Destination Clock Delay (DCD): -0.353ns
|
|
Source Clock Delay (SCD): -0.581ns
|
|
Clock Pessimism Removal (CPR): 0.214ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock mlkem_clk_clk_pll rise edge)
|
|
0.000 0.000 r
|
|
clock source latency -1.848 -1.848
|
|
propagated clock network latency
|
|
1.267 -0.581
|
|
SLICE_X25Y79 FDCE 0.000 -0.581 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/buffers_1_reg/C
|
|
SLICE_X25Y79 FDCE (Prop_fdce_C_Q) 0.128 -0.453 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/buffers_1_reg/Q
|
|
net (fo=1, routed) 0.139 -0.314 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/buffers_1
|
|
SLICE_X25Y79 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/popCC_popPtr[2]_i_2__1/I0
|
|
SLICE_X25Y79 LUT1 (Prop_lut1_I0_O) 0.099 -0.215 f u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/popCC_popPtr[2]_i_2__1/O
|
|
net (fo=43, routed) 0.184 -0.031 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/pushToPopGray_buffercc/buffers_0_reg[2]_1
|
|
SLICE_X27Y79 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/pushToPopGray_buffercc/buffers_1_reg[2]/CLR
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock mlkem_clk_clk_pll rise edge)
|
|
0.000 0.000 r
|
|
clock source latency -1.947 -1.947
|
|
propagated clock network latency
|
|
1.594 -0.353
|
|
clock pessimism -0.214 -0.567
|
|
SLICE_X27Y79 FDCE (Remov_fdce_C_CLR) -0.092 -0.659 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/pushToPopGray_buffercc/buffers_1_reg[2]
|
|
-------------------------------------------------------------------
|
|
required time 0.659
|
|
arrival time -0.031
|
|
-------------------------------------------------------------------
|
|
slack 0.629
|
|
|
|
Slack (MET) : 0.650ns (arrival time - required time)
|
|
Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/buffers_1_reg/C
|
|
(rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/popCC_popPtr_reg[3]/CLR
|
|
(removal check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Path Group: **async_default**
|
|
Path Type: Removal (Min at Fast Process Corner)
|
|
Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns)
|
|
Data Path Delay: 0.622ns (logic 0.227ns (36.501%) route 0.395ns (63.499%))
|
|
Logic Levels: 1 (LUT1=1)
|
|
Clock Path Skew: 0.039ns (DCD - SCD - CPR)
|
|
Destination Clock Delay (DCD): -0.339ns
|
|
Source Clock Delay (SCD): -0.570ns
|
|
Clock Pessimism Removal (CPR): 0.192ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock sys_clk rise edge) 0.000 0.000 r
|
|
clock source latency -1.848 -1.848
|
|
propagated clock network latency
|
|
1.278 -0.570
|
|
SLICE_X13Y87 FDCE 0.000 -0.570 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/buffers_1_reg/C
|
|
SLICE_X13Y87 FDCE (Prop_fdce_C_Q) 0.128 -0.442 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/buffers_1_reg/Q
|
|
net (fo=1, routed) 0.053 -0.389 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/buffers_1
|
|
SLICE_X13Y87 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/popCC_popPtr[2]_i_2__2/I0
|
|
SLICE_X13Y87 LUT1 (Prop_lut1_I0_O) 0.099 -0.290 f u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/popCC_popPtr[2]_i_2__2/O
|
|
net (fo=30, routed) 0.341 0.052 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/buffers_0_reg[3]
|
|
SLICE_X16Y88 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/popCC_popPtr_reg[3]/CLR
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock sys_clk rise edge) 0.000 0.000 r
|
|
clock source latency -1.947 -1.947
|
|
propagated clock network latency
|
|
1.608 -0.339
|
|
clock pessimism -0.192 -0.531
|
|
SLICE_X16Y88 FDCE (Remov_fdce_C_CLR) -0.067 -0.598 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/popCC_popPtr_reg[3]
|
|
-------------------------------------------------------------------
|
|
required time 0.598
|
|
arrival time 0.052
|
|
-------------------------------------------------------------------
|
|
slack 0.650
|
|
|
|
Slack (MET) : 0.651ns (arrival time - required time)
|
|
Source: pll_clk.u_rst_cpu/delay_reg[1]/C
|
|
(rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns})
|
|
Destination: u_Axi_CDC/wFifo/popToPushGray_buffercc/buffers_0_reg[2]/CLR
|
|
(removal check against rising-edge clock cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns})
|
|
Path Group: **async_default**
|
|
Path Type: Removal (Min at Fast Process Corner)
|
|
Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns)
|
|
Data Path Delay: 0.779ns (logic 0.186ns (23.880%) route 0.593ns (76.120%))
|
|
Logic Levels: 1 (LUT1=1)
|
|
Clock Path Skew: 0.194ns (DCD - SCD - CPR)
|
|
Destination Clock Delay (DCD): -0.307ns
|
|
Source Clock Delay (SCD): -0.465ns
|
|
Clock Pessimism Removal (CPR): -0.037ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock cpu_clk rise edge) 0.000 0.000 r
|
|
clock source latency -1.848 -1.848
|
|
propagated clock network latency
|
|
1.384 -0.465
|
|
SLICE_X0Y48 FDCE 0.000 -0.465 r pll_clk.u_rst_cpu/delay_reg[1]/C
|
|
SLICE_X0Y48 FDCE (Prop_fdce_C_Q) 0.141 -0.324 r pll_clk.u_rst_cpu/delay_reg[1]/Q
|
|
net (fo=1, routed) 0.221 -0.103 pll_clk.u_rst_cpu/cpu_resetn
|
|
SLICE_X0Y48 r pll_clk.u_rst_cpu/reset_i_1/I0
|
|
SLICE_X0Y48 LUT1 (Prop_lut1_I0_O) 0.045 -0.058 f pll_clk.u_rst_cpu/reset_i_1/O
|
|
net (fo=40, routed) 0.372 0.314 u_Axi_CDC/wFifo/popToPushGray_buffercc/p_0_in
|
|
SLICE_X6Y50 FDCE f u_Axi_CDC/wFifo/popToPushGray_buffercc/buffers_0_reg[2]/CLR
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock cpu_clk rise edge) 0.000 0.000 r
|
|
clock source latency -1.947 -1.947
|
|
propagated clock network latency
|
|
1.640 -0.307
|
|
clock pessimism 0.037 -0.270
|
|
SLICE_X6Y50 FDCE (Remov_fdce_C_CLR) -0.067 -0.337 u_Axi_CDC/wFifo/popToPushGray_buffercc/buffers_0_reg[2]
|
|
-------------------------------------------------------------------
|
|
required time 0.337
|
|
arrival time 0.314
|
|
-------------------------------------------------------------------
|
|
slack 0.651
|
|
|
|
Slack (MET) : 0.651ns (arrival time - required time)
|
|
Source: pll_clk.u_rst_cpu/delay_reg[1]/C
|
|
(rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns})
|
|
Destination: u_Axi_CDC/wFifo/popToPushGray_buffercc/buffers_0_reg[3]/CLR
|
|
(removal check against rising-edge clock cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns})
|
|
Path Group: **async_default**
|
|
Path Type: Removal (Min at Fast Process Corner)
|
|
Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns)
|
|
Data Path Delay: 0.779ns (logic 0.186ns (23.880%) route 0.593ns (76.120%))
|
|
Logic Levels: 1 (LUT1=1)
|
|
Clock Path Skew: 0.194ns (DCD - SCD - CPR)
|
|
Destination Clock Delay (DCD): -0.307ns
|
|
Source Clock Delay (SCD): -0.465ns
|
|
Clock Pessimism Removal (CPR): -0.037ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock cpu_clk rise edge) 0.000 0.000 r
|
|
clock source latency -1.848 -1.848
|
|
propagated clock network latency
|
|
1.384 -0.465
|
|
SLICE_X0Y48 FDCE 0.000 -0.465 r pll_clk.u_rst_cpu/delay_reg[1]/C
|
|
SLICE_X0Y48 FDCE (Prop_fdce_C_Q) 0.141 -0.324 r pll_clk.u_rst_cpu/delay_reg[1]/Q
|
|
net (fo=1, routed) 0.221 -0.103 pll_clk.u_rst_cpu/cpu_resetn
|
|
SLICE_X0Y48 r pll_clk.u_rst_cpu/reset_i_1/I0
|
|
SLICE_X0Y48 LUT1 (Prop_lut1_I0_O) 0.045 -0.058 f pll_clk.u_rst_cpu/reset_i_1/O
|
|
net (fo=40, routed) 0.372 0.314 u_Axi_CDC/wFifo/popToPushGray_buffercc/p_0_in
|
|
SLICE_X6Y50 FDCE f u_Axi_CDC/wFifo/popToPushGray_buffercc/buffers_0_reg[3]/CLR
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock cpu_clk rise edge) 0.000 0.000 r
|
|
clock source latency -1.947 -1.947
|
|
propagated clock network latency
|
|
1.640 -0.307
|
|
clock pessimism 0.037 -0.270
|
|
SLICE_X6Y50 FDCE (Remov_fdce_C_CLR) -0.067 -0.337 u_Axi_CDC/wFifo/popToPushGray_buffercc/buffers_0_reg[3]
|
|
-------------------------------------------------------------------
|
|
required time 0.337
|
|
arrival time 0.314
|
|
-------------------------------------------------------------------
|
|
slack 0.651
|
|
|
|
Slack (MET) : 0.651ns (arrival time - required time)
|
|
Source: pll_clk.u_rst_cpu/delay_reg[1]/C
|
|
(rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns})
|
|
Destination: u_Axi_CDC/wFifo/popToPushGray_buffercc/buffers_1_reg[2]/CLR
|
|
(removal check against rising-edge clock cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns})
|
|
Path Group: **async_default**
|
|
Path Type: Removal (Min at Fast Process Corner)
|
|
Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns)
|
|
Data Path Delay: 0.779ns (logic 0.186ns (23.880%) route 0.593ns (76.120%))
|
|
Logic Levels: 1 (LUT1=1)
|
|
Clock Path Skew: 0.194ns (DCD - SCD - CPR)
|
|
Destination Clock Delay (DCD): -0.307ns
|
|
Source Clock Delay (SCD): -0.465ns
|
|
Clock Pessimism Removal (CPR): -0.037ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock cpu_clk rise edge) 0.000 0.000 r
|
|
clock source latency -1.848 -1.848
|
|
propagated clock network latency
|
|
1.384 -0.465
|
|
SLICE_X0Y48 FDCE 0.000 -0.465 r pll_clk.u_rst_cpu/delay_reg[1]/C
|
|
SLICE_X0Y48 FDCE (Prop_fdce_C_Q) 0.141 -0.324 r pll_clk.u_rst_cpu/delay_reg[1]/Q
|
|
net (fo=1, routed) 0.221 -0.103 pll_clk.u_rst_cpu/cpu_resetn
|
|
SLICE_X0Y48 r pll_clk.u_rst_cpu/reset_i_1/I0
|
|
SLICE_X0Y48 LUT1 (Prop_lut1_I0_O) 0.045 -0.058 f pll_clk.u_rst_cpu/reset_i_1/O
|
|
net (fo=40, routed) 0.372 0.314 u_Axi_CDC/wFifo/popToPushGray_buffercc/p_0_in
|
|
SLICE_X6Y50 FDCE f u_Axi_CDC/wFifo/popToPushGray_buffercc/buffers_1_reg[2]/CLR
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock cpu_clk rise edge) 0.000 0.000 r
|
|
clock source latency -1.947 -1.947
|
|
propagated clock network latency
|
|
1.640 -0.307
|
|
clock pessimism 0.037 -0.270
|
|
SLICE_X6Y50 FDCE (Remov_fdce_C_CLR) -0.067 -0.337 u_Axi_CDC/wFifo/popToPushGray_buffercc/buffers_1_reg[2]
|
|
-------------------------------------------------------------------
|
|
required time 0.337
|
|
arrival time 0.314
|
|
-------------------------------------------------------------------
|
|
slack 0.651
|
|
|
|
Slack (MET) : 0.651ns (arrival time - required time)
|
|
Source: pll_clk.u_rst_cpu/delay_reg[1]/C
|
|
(rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns})
|
|
Destination: u_Axi_CDC/wFifo/popToPushGray_buffercc/buffers_1_reg[3]/CLR
|
|
(removal check against rising-edge clock cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns})
|
|
Path Group: **async_default**
|
|
Path Type: Removal (Min at Fast Process Corner)
|
|
Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns)
|
|
Data Path Delay: 0.779ns (logic 0.186ns (23.880%) route 0.593ns (76.120%))
|
|
Logic Levels: 1 (LUT1=1)
|
|
Clock Path Skew: 0.194ns (DCD - SCD - CPR)
|
|
Destination Clock Delay (DCD): -0.307ns
|
|
Source Clock Delay (SCD): -0.465ns
|
|
Clock Pessimism Removal (CPR): -0.037ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock cpu_clk rise edge) 0.000 0.000 r
|
|
clock source latency -1.848 -1.848
|
|
propagated clock network latency
|
|
1.384 -0.465
|
|
SLICE_X0Y48 FDCE 0.000 -0.465 r pll_clk.u_rst_cpu/delay_reg[1]/C
|
|
SLICE_X0Y48 FDCE (Prop_fdce_C_Q) 0.141 -0.324 r pll_clk.u_rst_cpu/delay_reg[1]/Q
|
|
net (fo=1, routed) 0.221 -0.103 pll_clk.u_rst_cpu/cpu_resetn
|
|
SLICE_X0Y48 r pll_clk.u_rst_cpu/reset_i_1/I0
|
|
SLICE_X0Y48 LUT1 (Prop_lut1_I0_O) 0.045 -0.058 f pll_clk.u_rst_cpu/reset_i_1/O
|
|
net (fo=40, routed) 0.372 0.314 u_Axi_CDC/wFifo/popToPushGray_buffercc/p_0_in
|
|
SLICE_X6Y50 FDCE f u_Axi_CDC/wFifo/popToPushGray_buffercc/buffers_1_reg[3]/CLR
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock cpu_clk rise edge) 0.000 0.000 r
|
|
clock source latency -1.947 -1.947
|
|
propagated clock network latency
|
|
1.640 -0.307
|
|
clock pessimism 0.037 -0.270
|
|
SLICE_X6Y50 FDCE (Remov_fdce_C_CLR) -0.067 -0.337 u_Axi_CDC/wFifo/popToPushGray_buffercc/buffers_1_reg[3]
|
|
-------------------------------------------------------------------
|
|
required time 0.337
|
|
arrival time 0.314
|
|
-------------------------------------------------------------------
|
|
slack 0.651
|
|
|
|
Slack (MET) : 0.703ns (arrival time - required time)
|
|
Source: pll_clk.u_rst_cpu/delay_reg[1]/C
|
|
(rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns})
|
|
Destination: u_Axi_CDC/wFifo/popToPushGray_buffercc/buffers_0_reg[0]/CLR
|
|
(removal check against rising-edge clock cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns})
|
|
Path Group: **async_default**
|
|
Path Type: Removal (Min at Fast Process Corner)
|
|
Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns)
|
|
Data Path Delay: 0.627ns (logic 0.186ns (29.656%) route 0.441ns (70.344%))
|
|
Logic Levels: 1 (LUT1=1)
|
|
Clock Path Skew: 0.016ns (DCD - SCD - CPR)
|
|
Destination Clock Delay (DCD): -0.229ns
|
|
Source Clock Delay (SCD): -0.465ns
|
|
Clock Pessimism Removal (CPR): 0.220ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock cpu_clk rise edge) 0.000 0.000 r
|
|
clock source latency -1.848 -1.848
|
|
propagated clock network latency
|
|
1.384 -0.465
|
|
SLICE_X0Y48 FDCE 0.000 -0.465 r pll_clk.u_rst_cpu/delay_reg[1]/C
|
|
SLICE_X0Y48 FDCE (Prop_fdce_C_Q) 0.141 -0.324 r pll_clk.u_rst_cpu/delay_reg[1]/Q
|
|
net (fo=1, routed) 0.221 -0.103 pll_clk.u_rst_cpu/cpu_resetn
|
|
SLICE_X0Y48 r pll_clk.u_rst_cpu/reset_i_1/I0
|
|
SLICE_X0Y48 LUT1 (Prop_lut1_I0_O) 0.045 -0.058 f pll_clk.u_rst_cpu/reset_i_1/O
|
|
net (fo=40, routed) 0.220 0.162 u_Axi_CDC/wFifo/popToPushGray_buffercc/p_0_in
|
|
SLICE_X0Y49 FDCE f u_Axi_CDC/wFifo/popToPushGray_buffercc/buffers_0_reg[0]/CLR
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock cpu_clk rise edge) 0.000 0.000 r
|
|
clock source latency -1.947 -1.947
|
|
propagated clock network latency
|
|
1.718 -0.229
|
|
clock pessimism -0.220 -0.449
|
|
SLICE_X0Y49 FDCE (Remov_fdce_C_CLR) -0.092 -0.541 u_Axi_CDC/wFifo/popToPushGray_buffercc/buffers_0_reg[0]
|
|
-------------------------------------------------------------------
|
|
required time 0.541
|
|
arrival time 0.162
|
|
-------------------------------------------------------------------
|
|
slack 0.703
|
|
|
|
Slack (MET) : 0.703ns (arrival time - required time)
|
|
Source: pll_clk.u_rst_cpu/delay_reg[1]/C
|
|
(rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns})
|
|
Destination: u_Axi_CDC/wFifo/popToPushGray_buffercc/buffers_0_reg[1]/CLR
|
|
(removal check against rising-edge clock cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns})
|
|
Path Group: **async_default**
|
|
Path Type: Removal (Min at Fast Process Corner)
|
|
Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns)
|
|
Data Path Delay: 0.627ns (logic 0.186ns (29.656%) route 0.441ns (70.344%))
|
|
Logic Levels: 1 (LUT1=1)
|
|
Clock Path Skew: 0.016ns (DCD - SCD - CPR)
|
|
Destination Clock Delay (DCD): -0.229ns
|
|
Source Clock Delay (SCD): -0.465ns
|
|
Clock Pessimism Removal (CPR): 0.220ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock cpu_clk rise edge) 0.000 0.000 r
|
|
clock source latency -1.848 -1.848
|
|
propagated clock network latency
|
|
1.384 -0.465
|
|
SLICE_X0Y48 FDCE 0.000 -0.465 r pll_clk.u_rst_cpu/delay_reg[1]/C
|
|
SLICE_X0Y48 FDCE (Prop_fdce_C_Q) 0.141 -0.324 r pll_clk.u_rst_cpu/delay_reg[1]/Q
|
|
net (fo=1, routed) 0.221 -0.103 pll_clk.u_rst_cpu/cpu_resetn
|
|
SLICE_X0Y48 r pll_clk.u_rst_cpu/reset_i_1/I0
|
|
SLICE_X0Y48 LUT1 (Prop_lut1_I0_O) 0.045 -0.058 f pll_clk.u_rst_cpu/reset_i_1/O
|
|
net (fo=40, routed) 0.220 0.162 u_Axi_CDC/wFifo/popToPushGray_buffercc/p_0_in
|
|
SLICE_X0Y49 FDCE f u_Axi_CDC/wFifo/popToPushGray_buffercc/buffers_0_reg[1]/CLR
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock cpu_clk rise edge) 0.000 0.000 r
|
|
clock source latency -1.947 -1.947
|
|
propagated clock network latency
|
|
1.718 -0.229
|
|
clock pessimism -0.220 -0.449
|
|
SLICE_X0Y49 FDCE (Remov_fdce_C_CLR) -0.092 -0.541 u_Axi_CDC/wFifo/popToPushGray_buffercc/buffers_0_reg[1]
|
|
-------------------------------------------------------------------
|
|
required time 0.541
|
|
arrival time 0.162
|
|
-------------------------------------------------------------------
|
|
slack 0.703
|
|
|
|
Slack (MET) : 0.703ns (arrival time - required time)
|
|
Source: pll_clk.u_rst_cpu/delay_reg[1]/C
|
|
(rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns})
|
|
Destination: u_Axi_CDC/wFifo/popToPushGray_buffercc/buffers_1_reg[0]/CLR
|
|
(removal check against rising-edge clock cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns})
|
|
Path Group: **async_default**
|
|
Path Type: Removal (Min at Fast Process Corner)
|
|
Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns)
|
|
Data Path Delay: 0.627ns (logic 0.186ns (29.656%) route 0.441ns (70.344%))
|
|
Logic Levels: 1 (LUT1=1)
|
|
Clock Path Skew: 0.016ns (DCD - SCD - CPR)
|
|
Destination Clock Delay (DCD): -0.229ns
|
|
Source Clock Delay (SCD): -0.465ns
|
|
Clock Pessimism Removal (CPR): 0.220ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock cpu_clk rise edge) 0.000 0.000 r
|
|
clock source latency -1.848 -1.848
|
|
propagated clock network latency
|
|
1.384 -0.465
|
|
SLICE_X0Y48 FDCE 0.000 -0.465 r pll_clk.u_rst_cpu/delay_reg[1]/C
|
|
SLICE_X0Y48 FDCE (Prop_fdce_C_Q) 0.141 -0.324 r pll_clk.u_rst_cpu/delay_reg[1]/Q
|
|
net (fo=1, routed) 0.221 -0.103 pll_clk.u_rst_cpu/cpu_resetn
|
|
SLICE_X0Y48 r pll_clk.u_rst_cpu/reset_i_1/I0
|
|
SLICE_X0Y48 LUT1 (Prop_lut1_I0_O) 0.045 -0.058 f pll_clk.u_rst_cpu/reset_i_1/O
|
|
net (fo=40, routed) 0.220 0.162 u_Axi_CDC/wFifo/popToPushGray_buffercc/p_0_in
|
|
SLICE_X0Y49 FDCE f u_Axi_CDC/wFifo/popToPushGray_buffercc/buffers_1_reg[0]/CLR
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock cpu_clk rise edge) 0.000 0.000 r
|
|
clock source latency -1.947 -1.947
|
|
propagated clock network latency
|
|
1.718 -0.229
|
|
clock pessimism -0.220 -0.449
|
|
SLICE_X0Y49 FDCE (Remov_fdce_C_CLR) -0.092 -0.541 u_Axi_CDC/wFifo/popToPushGray_buffercc/buffers_1_reg[0]
|
|
-------------------------------------------------------------------
|
|
required time 0.541
|
|
arrival time 0.162
|
|
-------------------------------------------------------------------
|
|
slack 0.703
|
|
|
|
Slack (MET) : 0.703ns (arrival time - required time)
|
|
Source: pll_clk.u_rst_cpu/delay_reg[1]/C
|
|
(rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns})
|
|
Destination: u_Axi_CDC/wFifo/popToPushGray_buffercc/buffers_1_reg[1]/CLR
|
|
(removal check against rising-edge clock cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns})
|
|
Path Group: **async_default**
|
|
Path Type: Removal (Min at Fast Process Corner)
|
|
Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns)
|
|
Data Path Delay: 0.627ns (logic 0.186ns (29.656%) route 0.441ns (70.344%))
|
|
Logic Levels: 1 (LUT1=1)
|
|
Clock Path Skew: 0.016ns (DCD - SCD - CPR)
|
|
Destination Clock Delay (DCD): -0.229ns
|
|
Source Clock Delay (SCD): -0.465ns
|
|
Clock Pessimism Removal (CPR): 0.220ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock cpu_clk rise edge) 0.000 0.000 r
|
|
clock source latency -1.848 -1.848
|
|
propagated clock network latency
|
|
1.384 -0.465
|
|
SLICE_X0Y48 FDCE 0.000 -0.465 r pll_clk.u_rst_cpu/delay_reg[1]/C
|
|
SLICE_X0Y48 FDCE (Prop_fdce_C_Q) 0.141 -0.324 r pll_clk.u_rst_cpu/delay_reg[1]/Q
|
|
net (fo=1, routed) 0.221 -0.103 pll_clk.u_rst_cpu/cpu_resetn
|
|
SLICE_X0Y48 r pll_clk.u_rst_cpu/reset_i_1/I0
|
|
SLICE_X0Y48 LUT1 (Prop_lut1_I0_O) 0.045 -0.058 f pll_clk.u_rst_cpu/reset_i_1/O
|
|
net (fo=40, routed) 0.220 0.162 u_Axi_CDC/wFifo/popToPushGray_buffercc/p_0_in
|
|
SLICE_X0Y49 FDCE f u_Axi_CDC/wFifo/popToPushGray_buffercc/buffers_1_reg[1]/CLR
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock cpu_clk rise edge) 0.000 0.000 r
|
|
clock source latency -1.947 -1.947
|
|
propagated clock network latency
|
|
1.718 -0.229
|
|
clock pessimism -0.220 -0.449
|
|
SLICE_X0Y49 FDCE (Remov_fdce_C_CLR) -0.092 -0.541 u_Axi_CDC/wFifo/popToPushGray_buffercc/buffers_1_reg[1]
|
|
-------------------------------------------------------------------
|
|
required time 0.541
|
|
arrival time 0.162
|
|
-------------------------------------------------------------------
|
|
slack 0.703
|
|
|
|
Slack (MET) : 0.728ns (arrival time - required time)
|
|
Source: pll_clk.u_rst_mlkem/delay_reg[1]/C
|
|
(rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns})
|
|
Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/stream_wdata_reg[14]/CLR
|
|
(removal check against rising-edge clock mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns})
|
|
Path Group: **async_default**
|
|
Path Type: Removal (Min at Fast Process Corner)
|
|
Requirement: 0.000ns (mlkem_clk_clk_pll rise@0.000ns - mlkem_clk_clk_pll rise@0.000ns)
|
|
Data Path Delay: 0.695ns (logic 0.186ns (26.771%) route 0.509ns (73.229%))
|
|
Logic Levels: 1 (LUT1=1)
|
|
Clock Path Skew: 0.034ns (DCD - SCD - CPR)
|
|
Destination Clock Delay (DCD): -0.381ns
|
|
Source Clock Delay (SCD): -0.607ns
|
|
Clock Pessimism Removal (CPR): 0.192ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock mlkem_clk_clk_pll rise edge)
|
|
0.000 0.000 r
|
|
clock source latency -1.848 -1.848
|
|
propagated clock network latency
|
|
1.241 -0.607
|
|
SLICE_X118Y67 FDCE 0.000 -0.607 r pll_clk.u_rst_mlkem/delay_reg[1]/C
|
|
SLICE_X118Y67 FDCE (Prop_fdce_C_Q) 0.141 -0.466 r pll_clk.u_rst_mlkem/delay_reg[1]/Q
|
|
net (fo=4, routed) 0.297 -0.169 pll_clk.u_rst_mlkem/Q[0]
|
|
SLICE_X118Y67 r pll_clk.u_rst_mlkem/rdb_addr[11]_i_2/I0
|
|
SLICE_X118Y67 LUT1 (Prop_lut1_I0_O) 0.045 -0.124 f pll_clk.u_rst_mlkem/rdb_addr[11]_i_2/O
|
|
net (fo=1069, routed) 0.211 0.087 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/pre_addr_l_reg[2]_rep__1_0
|
|
SLICE_X120Y68 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/stream_wdata_reg[14]/CLR
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock mlkem_clk_clk_pll rise edge)
|
|
0.000 0.000 r
|
|
clock source latency -1.947 -1.947
|
|
propagated clock network latency
|
|
1.566 -0.381
|
|
clock pessimism -0.192 -0.573
|
|
SLICE_X120Y68 FDCE (Remov_fdce_C_CLR) -0.067 -0.640 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/stream_wdata_reg[14]
|
|
-------------------------------------------------------------------
|
|
required time 0.640
|
|
arrival time 0.087
|
|
-------------------------------------------------------------------
|
|
slack 0.728
|
|
|
|
Slack (MET) : 0.728ns (arrival time - required time)
|
|
Source: pll_clk.u_rst_mlkem/delay_reg[1]/C
|
|
(rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns})
|
|
Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/stream_wdata_reg[22]/CLR
|
|
(removal check against rising-edge clock mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns})
|
|
Path Group: **async_default**
|
|
Path Type: Removal (Min at Fast Process Corner)
|
|
Requirement: 0.000ns (mlkem_clk_clk_pll rise@0.000ns - mlkem_clk_clk_pll rise@0.000ns)
|
|
Data Path Delay: 0.695ns (logic 0.186ns (26.771%) route 0.509ns (73.229%))
|
|
Logic Levels: 1 (LUT1=1)
|
|
Clock Path Skew: 0.034ns (DCD - SCD - CPR)
|
|
Destination Clock Delay (DCD): -0.381ns
|
|
Source Clock Delay (SCD): -0.607ns
|
|
Clock Pessimism Removal (CPR): 0.192ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock mlkem_clk_clk_pll rise edge)
|
|
0.000 0.000 r
|
|
clock source latency -1.848 -1.848
|
|
propagated clock network latency
|
|
1.241 -0.607
|
|
SLICE_X118Y67 FDCE 0.000 -0.607 r pll_clk.u_rst_mlkem/delay_reg[1]/C
|
|
SLICE_X118Y67 FDCE (Prop_fdce_C_Q) 0.141 -0.466 r pll_clk.u_rst_mlkem/delay_reg[1]/Q
|
|
net (fo=4, routed) 0.297 -0.169 pll_clk.u_rst_mlkem/Q[0]
|
|
SLICE_X118Y67 r pll_clk.u_rst_mlkem/rdb_addr[11]_i_2/I0
|
|
SLICE_X118Y67 LUT1 (Prop_lut1_I0_O) 0.045 -0.124 f pll_clk.u_rst_mlkem/rdb_addr[11]_i_2/O
|
|
net (fo=1069, routed) 0.211 0.087 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/pre_addr_l_reg[2]_rep__1_0
|
|
SLICE_X120Y68 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/stream_wdata_reg[22]/CLR
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock mlkem_clk_clk_pll rise edge)
|
|
0.000 0.000 r
|
|
clock source latency -1.947 -1.947
|
|
propagated clock network latency
|
|
1.566 -0.381
|
|
clock pessimism -0.192 -0.573
|
|
SLICE_X120Y68 FDCE (Remov_fdce_C_CLR) -0.067 -0.640 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/stream_wdata_reg[22]
|
|
-------------------------------------------------------------------
|
|
required time 0.640
|
|
arrival time 0.087
|
|
-------------------------------------------------------------------
|
|
slack 0.728
|
|
|
|
Slack (MET) : 0.728ns (arrival time - required time)
|
|
Source: pll_clk.u_rst_mlkem/delay_reg[1]/C
|
|
(rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns})
|
|
Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/stream_wdata_reg[6]/CLR
|
|
(removal check against rising-edge clock mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns})
|
|
Path Group: **async_default**
|
|
Path Type: Removal (Min at Fast Process Corner)
|
|
Requirement: 0.000ns (mlkem_clk_clk_pll rise@0.000ns - mlkem_clk_clk_pll rise@0.000ns)
|
|
Data Path Delay: 0.695ns (logic 0.186ns (26.771%) route 0.509ns (73.229%))
|
|
Logic Levels: 1 (LUT1=1)
|
|
Clock Path Skew: 0.034ns (DCD - SCD - CPR)
|
|
Destination Clock Delay (DCD): -0.381ns
|
|
Source Clock Delay (SCD): -0.607ns
|
|
Clock Pessimism Removal (CPR): 0.192ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock mlkem_clk_clk_pll rise edge)
|
|
0.000 0.000 r
|
|
clock source latency -1.848 -1.848
|
|
propagated clock network latency
|
|
1.241 -0.607
|
|
SLICE_X118Y67 FDCE 0.000 -0.607 r pll_clk.u_rst_mlkem/delay_reg[1]/C
|
|
SLICE_X118Y67 FDCE (Prop_fdce_C_Q) 0.141 -0.466 r pll_clk.u_rst_mlkem/delay_reg[1]/Q
|
|
net (fo=4, routed) 0.297 -0.169 pll_clk.u_rst_mlkem/Q[0]
|
|
SLICE_X118Y67 r pll_clk.u_rst_mlkem/rdb_addr[11]_i_2/I0
|
|
SLICE_X118Y67 LUT1 (Prop_lut1_I0_O) 0.045 -0.124 f pll_clk.u_rst_mlkem/rdb_addr[11]_i_2/O
|
|
net (fo=1069, routed) 0.211 0.087 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/pre_addr_l_reg[2]_rep__1_0
|
|
SLICE_X120Y68 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/stream_wdata_reg[6]/CLR
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock mlkem_clk_clk_pll rise edge)
|
|
0.000 0.000 r
|
|
clock source latency -1.947 -1.947
|
|
propagated clock network latency
|
|
1.566 -0.381
|
|
clock pessimism -0.192 -0.573
|
|
SLICE_X120Y68 FDCE (Remov_fdce_C_CLR) -0.067 -0.640 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/stream_wdata_reg[6]
|
|
-------------------------------------------------------------------
|
|
required time 0.640
|
|
arrival time 0.087
|
|
-------------------------------------------------------------------
|
|
slack 0.728
|
|
|
|
Slack (MET) : 0.741ns (arrival time - required time)
|
|
Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/buffers_1_reg/C
|
|
(rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns})
|
|
Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/popCC_addressGen_rValid_reg/CLR
|
|
(removal check against rising-edge clock mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns})
|
|
Path Group: **async_default**
|
|
Path Type: Removal (Min at Fast Process Corner)
|
|
Requirement: 0.000ns (mlkem_clk_clk_pll rise@0.000ns - mlkem_clk_clk_pll rise@0.000ns)
|
|
Data Path Delay: 0.682ns (logic 0.227ns (33.271%) route 0.455ns (66.729%))
|
|
Logic Levels: 1 (LUT1=1)
|
|
Clock Path Skew: 0.033ns (DCD - SCD - CPR)
|
|
Destination Clock Delay (DCD): -0.356ns
|
|
Source Clock Delay (SCD): -0.581ns
|
|
Clock Pessimism Removal (CPR): 0.192ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock mlkem_clk_clk_pll rise edge)
|
|
0.000 0.000 r
|
|
clock source latency -1.848 -1.848
|
|
propagated clock network latency
|
|
1.267 -0.581
|
|
SLICE_X25Y79 FDCE 0.000 -0.581 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/buffers_1_reg/C
|
|
SLICE_X25Y79 FDCE (Prop_fdce_C_Q) 0.128 -0.453 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/buffers_1_reg/Q
|
|
net (fo=1, routed) 0.139 -0.314 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/buffers_1
|
|
SLICE_X25Y79 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/popCC_popPtr[2]_i_2__1/I0
|
|
SLICE_X25Y79 LUT1 (Prop_lut1_I0_O) 0.099 -0.215 f u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/popCC_popPtr[2]_i_2__1/O
|
|
net (fo=43, routed) 0.316 0.101 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/buffers_0_reg[2]
|
|
SLICE_X30Y78 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/popCC_addressGen_rValid_reg/CLR
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock mlkem_clk_clk_pll rise edge)
|
|
0.000 0.000 r
|
|
clock source latency -1.947 -1.947
|
|
propagated clock network latency
|
|
1.591 -0.356
|
|
clock pessimism -0.192 -0.548
|
|
SLICE_X30Y78 FDCE (Remov_fdce_C_CLR) -0.092 -0.640 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/popCC_addressGen_rValid_reg
|
|
-------------------------------------------------------------------
|
|
required time 0.640
|
|
arrival time 0.101
|
|
-------------------------------------------------------------------
|
|
slack 0.741
|
|
|
|
Slack (MET) : 0.741ns (arrival time - required time)
|
|
Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/buffers_1_reg/C
|
|
(rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns})
|
|
Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/popCC_popPtr_reg[0]/CLR
|
|
(removal check against rising-edge clock mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns})
|
|
Path Group: **async_default**
|
|
Path Type: Removal (Min at Fast Process Corner)
|
|
Requirement: 0.000ns (mlkem_clk_clk_pll rise@0.000ns - mlkem_clk_clk_pll rise@0.000ns)
|
|
Data Path Delay: 0.682ns (logic 0.227ns (33.271%) route 0.455ns (66.729%))
|
|
Logic Levels: 1 (LUT1=1)
|
|
Clock Path Skew: 0.033ns (DCD - SCD - CPR)
|
|
Destination Clock Delay (DCD): -0.356ns
|
|
Source Clock Delay (SCD): -0.581ns
|
|
Clock Pessimism Removal (CPR): 0.192ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock mlkem_clk_clk_pll rise edge)
|
|
0.000 0.000 r
|
|
clock source latency -1.848 -1.848
|
|
propagated clock network latency
|
|
1.267 -0.581
|
|
SLICE_X25Y79 FDCE 0.000 -0.581 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/buffers_1_reg/C
|
|
SLICE_X25Y79 FDCE (Prop_fdce_C_Q) 0.128 -0.453 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/buffers_1_reg/Q
|
|
net (fo=1, routed) 0.139 -0.314 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/buffers_1
|
|
SLICE_X25Y79 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/popCC_popPtr[2]_i_2__1/I0
|
|
SLICE_X25Y79 LUT1 (Prop_lut1_I0_O) 0.099 -0.215 f u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/popCC_popPtr[2]_i_2__1/O
|
|
net (fo=43, routed) 0.316 0.101 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/buffers_0_reg[2]
|
|
SLICE_X30Y78 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/popCC_popPtr_reg[0]/CLR
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock mlkem_clk_clk_pll rise edge)
|
|
0.000 0.000 r
|
|
clock source latency -1.947 -1.947
|
|
propagated clock network latency
|
|
1.591 -0.356
|
|
clock pessimism -0.192 -0.548
|
|
SLICE_X30Y78 FDCE (Remov_fdce_C_CLR) -0.092 -0.640 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/popCC_popPtr_reg[0]
|
|
-------------------------------------------------------------------
|
|
required time 0.640
|
|
arrival time 0.101
|
|
-------------------------------------------------------------------
|
|
slack 0.741
|
|
|
|
Slack (MET) : 0.741ns (arrival time - required time)
|
|
Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/buffers_1_reg/C
|
|
(rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns})
|
|
Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/popCC_popPtr_reg[1]/CLR
|
|
(removal check against rising-edge clock mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns})
|
|
Path Group: **async_default**
|
|
Path Type: Removal (Min at Fast Process Corner)
|
|
Requirement: 0.000ns (mlkem_clk_clk_pll rise@0.000ns - mlkem_clk_clk_pll rise@0.000ns)
|
|
Data Path Delay: 0.682ns (logic 0.227ns (33.271%) route 0.455ns (66.729%))
|
|
Logic Levels: 1 (LUT1=1)
|
|
Clock Path Skew: 0.033ns (DCD - SCD - CPR)
|
|
Destination Clock Delay (DCD): -0.356ns
|
|
Source Clock Delay (SCD): -0.581ns
|
|
Clock Pessimism Removal (CPR): 0.192ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock mlkem_clk_clk_pll rise edge)
|
|
0.000 0.000 r
|
|
clock source latency -1.848 -1.848
|
|
propagated clock network latency
|
|
1.267 -0.581
|
|
SLICE_X25Y79 FDCE 0.000 -0.581 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/buffers_1_reg/C
|
|
SLICE_X25Y79 FDCE (Prop_fdce_C_Q) 0.128 -0.453 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/buffers_1_reg/Q
|
|
net (fo=1, routed) 0.139 -0.314 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/buffers_1
|
|
SLICE_X25Y79 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/popCC_popPtr[2]_i_2__1/I0
|
|
SLICE_X25Y79 LUT1 (Prop_lut1_I0_O) 0.099 -0.215 f u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/popCC_popPtr[2]_i_2__1/O
|
|
net (fo=43, routed) 0.316 0.101 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/buffers_0_reg[2]
|
|
SLICE_X30Y78 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/popCC_popPtr_reg[1]/CLR
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock mlkem_clk_clk_pll rise edge)
|
|
0.000 0.000 r
|
|
clock source latency -1.947 -1.947
|
|
propagated clock network latency
|
|
1.591 -0.356
|
|
clock pessimism -0.192 -0.548
|
|
SLICE_X30Y78 FDCE (Remov_fdce_C_CLR) -0.092 -0.640 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/popCC_popPtr_reg[1]
|
|
-------------------------------------------------------------------
|
|
required time 0.640
|
|
arrival time 0.101
|
|
-------------------------------------------------------------------
|
|
slack 0.741
|
|
|
|
Slack (MET) : 0.741ns (arrival time - required time)
|
|
Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/buffers_1_reg/C
|
|
(rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns})
|
|
Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/popCC_ptrToPush_reg[0]/CLR
|
|
(removal check against rising-edge clock mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns})
|
|
Path Group: **async_default**
|
|
Path Type: Removal (Min at Fast Process Corner)
|
|
Requirement: 0.000ns (mlkem_clk_clk_pll rise@0.000ns - mlkem_clk_clk_pll rise@0.000ns)
|
|
Data Path Delay: 0.682ns (logic 0.227ns (33.271%) route 0.455ns (66.729%))
|
|
Logic Levels: 1 (LUT1=1)
|
|
Clock Path Skew: 0.033ns (DCD - SCD - CPR)
|
|
Destination Clock Delay (DCD): -0.356ns
|
|
Source Clock Delay (SCD): -0.581ns
|
|
Clock Pessimism Removal (CPR): 0.192ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock mlkem_clk_clk_pll rise edge)
|
|
0.000 0.000 r
|
|
clock source latency -1.848 -1.848
|
|
propagated clock network latency
|
|
1.267 -0.581
|
|
SLICE_X25Y79 FDCE 0.000 -0.581 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/buffers_1_reg/C
|
|
SLICE_X25Y79 FDCE (Prop_fdce_C_Q) 0.128 -0.453 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/buffers_1_reg/Q
|
|
net (fo=1, routed) 0.139 -0.314 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/buffers_1
|
|
SLICE_X25Y79 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/popCC_popPtr[2]_i_2__1/I0
|
|
SLICE_X25Y79 LUT1 (Prop_lut1_I0_O) 0.099 -0.215 f u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/popCC_popPtr[2]_i_2__1/O
|
|
net (fo=43, routed) 0.316 0.101 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/buffers_0_reg[2]
|
|
SLICE_X30Y78 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/popCC_ptrToPush_reg[0]/CLR
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock mlkem_clk_clk_pll rise edge)
|
|
0.000 0.000 r
|
|
clock source latency -1.947 -1.947
|
|
propagated clock network latency
|
|
1.591 -0.356
|
|
clock pessimism -0.192 -0.548
|
|
SLICE_X30Y78 FDCE (Remov_fdce_C_CLR) -0.092 -0.640 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/popCC_ptrToPush_reg[0]
|
|
-------------------------------------------------------------------
|
|
required time 0.640
|
|
arrival time 0.101
|
|
-------------------------------------------------------------------
|
|
slack 0.741
|
|
|
|
Slack (MET) : 0.753ns (arrival time - required time)
|
|
Source: pll_clk.u_rst_mlkem/delay_reg[1]/C
|
|
(rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns})
|
|
Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/stream_byte_addr_reg[10]/CLR
|
|
(removal check against rising-edge clock mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns})
|
|
Path Group: **async_default**
|
|
Path Type: Removal (Min at Fast Process Corner)
|
|
Requirement: 0.000ns (mlkem_clk_clk_pll rise@0.000ns - mlkem_clk_clk_pll rise@0.000ns)
|
|
Data Path Delay: 0.695ns (logic 0.186ns (26.771%) route 0.509ns (73.229%))
|
|
Logic Levels: 1 (LUT1=1)
|
|
Clock Path Skew: 0.034ns (DCD - SCD - CPR)
|
|
Destination Clock Delay (DCD): -0.381ns
|
|
Source Clock Delay (SCD): -0.607ns
|
|
Clock Pessimism Removal (CPR): 0.192ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock mlkem_clk_clk_pll rise edge)
|
|
0.000 0.000 r
|
|
clock source latency -1.848 -1.848
|
|
propagated clock network latency
|
|
1.241 -0.607
|
|
SLICE_X118Y67 FDCE 0.000 -0.607 r pll_clk.u_rst_mlkem/delay_reg[1]/C
|
|
SLICE_X118Y67 FDCE (Prop_fdce_C_Q) 0.141 -0.466 r pll_clk.u_rst_mlkem/delay_reg[1]/Q
|
|
net (fo=4, routed) 0.297 -0.169 pll_clk.u_rst_mlkem/Q[0]
|
|
SLICE_X118Y67 r pll_clk.u_rst_mlkem/rdb_addr[11]_i_2/I0
|
|
SLICE_X118Y67 LUT1 (Prop_lut1_I0_O) 0.045 -0.124 f pll_clk.u_rst_mlkem/rdb_addr[11]_i_2/O
|
|
net (fo=1069, routed) 0.211 0.087 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/pre_addr_l_reg[2]_rep__1_0
|
|
SLICE_X121Y68 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/stream_byte_addr_reg[10]/CLR
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock mlkem_clk_clk_pll rise edge)
|
|
0.000 0.000 r
|
|
clock source latency -1.947 -1.947
|
|
propagated clock network latency
|
|
1.566 -0.381
|
|
clock pessimism -0.192 -0.573
|
|
SLICE_X121Y68 FDCE (Remov_fdce_C_CLR) -0.092 -0.665 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/stream_byte_addr_reg[10]
|
|
-------------------------------------------------------------------
|
|
required time 0.665
|
|
arrival time 0.087
|
|
-------------------------------------------------------------------
|
|
slack 0.753
|
|
|
|
Slack (MET) : 0.753ns (arrival time - required time)
|
|
Source: pll_clk.u_rst_mlkem/delay_reg[1]/C
|
|
(rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns})
|
|
Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/stream_byte_addr_reg[11]/CLR
|
|
(removal check against rising-edge clock mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns})
|
|
Path Group: **async_default**
|
|
Path Type: Removal (Min at Fast Process Corner)
|
|
Requirement: 0.000ns (mlkem_clk_clk_pll rise@0.000ns - mlkem_clk_clk_pll rise@0.000ns)
|
|
Data Path Delay: 0.695ns (logic 0.186ns (26.771%) route 0.509ns (73.229%))
|
|
Logic Levels: 1 (LUT1=1)
|
|
Clock Path Skew: 0.034ns (DCD - SCD - CPR)
|
|
Destination Clock Delay (DCD): -0.381ns
|
|
Source Clock Delay (SCD): -0.607ns
|
|
Clock Pessimism Removal (CPR): 0.192ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock mlkem_clk_clk_pll rise edge)
|
|
0.000 0.000 r
|
|
clock source latency -1.848 -1.848
|
|
propagated clock network latency
|
|
1.241 -0.607
|
|
SLICE_X118Y67 FDCE 0.000 -0.607 r pll_clk.u_rst_mlkem/delay_reg[1]/C
|
|
SLICE_X118Y67 FDCE (Prop_fdce_C_Q) 0.141 -0.466 r pll_clk.u_rst_mlkem/delay_reg[1]/Q
|
|
net (fo=4, routed) 0.297 -0.169 pll_clk.u_rst_mlkem/Q[0]
|
|
SLICE_X118Y67 r pll_clk.u_rst_mlkem/rdb_addr[11]_i_2/I0
|
|
SLICE_X118Y67 LUT1 (Prop_lut1_I0_O) 0.045 -0.124 f pll_clk.u_rst_mlkem/rdb_addr[11]_i_2/O
|
|
net (fo=1069, routed) 0.211 0.087 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/pre_addr_l_reg[2]_rep__1_0
|
|
SLICE_X121Y68 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/stream_byte_addr_reg[11]/CLR
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock mlkem_clk_clk_pll rise edge)
|
|
0.000 0.000 r
|
|
clock source latency -1.947 -1.947
|
|
propagated clock network latency
|
|
1.566 -0.381
|
|
clock pessimism -0.192 -0.573
|
|
SLICE_X121Y68 FDCE (Remov_fdce_C_CLR) -0.092 -0.665 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/stream_byte_addr_reg[11]
|
|
-------------------------------------------------------------------
|
|
required time 0.665
|
|
arrival time 0.087
|
|
-------------------------------------------------------------------
|
|
slack 0.753
|
|
|
|
Slack (MET) : 0.753ns (arrival time - required time)
|
|
Source: pll_clk.u_rst_mlkem/delay_reg[1]/C
|
|
(rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns})
|
|
Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/stream_byte_addr_reg[8]/CLR
|
|
(removal check against rising-edge clock mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns})
|
|
Path Group: **async_default**
|
|
Path Type: Removal (Min at Fast Process Corner)
|
|
Requirement: 0.000ns (mlkem_clk_clk_pll rise@0.000ns - mlkem_clk_clk_pll rise@0.000ns)
|
|
Data Path Delay: 0.695ns (logic 0.186ns (26.771%) route 0.509ns (73.229%))
|
|
Logic Levels: 1 (LUT1=1)
|
|
Clock Path Skew: 0.034ns (DCD - SCD - CPR)
|
|
Destination Clock Delay (DCD): -0.381ns
|
|
Source Clock Delay (SCD): -0.607ns
|
|
Clock Pessimism Removal (CPR): 0.192ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock mlkem_clk_clk_pll rise edge)
|
|
0.000 0.000 r
|
|
clock source latency -1.848 -1.848
|
|
propagated clock network latency
|
|
1.241 -0.607
|
|
SLICE_X118Y67 FDCE 0.000 -0.607 r pll_clk.u_rst_mlkem/delay_reg[1]/C
|
|
SLICE_X118Y67 FDCE (Prop_fdce_C_Q) 0.141 -0.466 r pll_clk.u_rst_mlkem/delay_reg[1]/Q
|
|
net (fo=4, routed) 0.297 -0.169 pll_clk.u_rst_mlkem/Q[0]
|
|
SLICE_X118Y67 r pll_clk.u_rst_mlkem/rdb_addr[11]_i_2/I0
|
|
SLICE_X118Y67 LUT1 (Prop_lut1_I0_O) 0.045 -0.124 f pll_clk.u_rst_mlkem/rdb_addr[11]_i_2/O
|
|
net (fo=1069, routed) 0.211 0.087 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/pre_addr_l_reg[2]_rep__1_0
|
|
SLICE_X121Y68 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/stream_byte_addr_reg[8]/CLR
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock mlkem_clk_clk_pll rise edge)
|
|
0.000 0.000 r
|
|
clock source latency -1.947 -1.947
|
|
propagated clock network latency
|
|
1.566 -0.381
|
|
clock pessimism -0.192 -0.573
|
|
SLICE_X121Y68 FDCE (Remov_fdce_C_CLR) -0.092 -0.665 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/stream_byte_addr_reg[8]
|
|
-------------------------------------------------------------------
|
|
required time 0.665
|
|
arrival time 0.087
|
|
-------------------------------------------------------------------
|
|
slack 0.753
|
|
|
|
Slack (MET) : 0.753ns (arrival time - required time)
|
|
Source: pll_clk.u_rst_mlkem/delay_reg[1]/C
|
|
(rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns})
|
|
Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/stream_byte_addr_reg[9]/CLR
|
|
(removal check against rising-edge clock mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns})
|
|
Path Group: **async_default**
|
|
Path Type: Removal (Min at Fast Process Corner)
|
|
Requirement: 0.000ns (mlkem_clk_clk_pll rise@0.000ns - mlkem_clk_clk_pll rise@0.000ns)
|
|
Data Path Delay: 0.695ns (logic 0.186ns (26.771%) route 0.509ns (73.229%))
|
|
Logic Levels: 1 (LUT1=1)
|
|
Clock Path Skew: 0.034ns (DCD - SCD - CPR)
|
|
Destination Clock Delay (DCD): -0.381ns
|
|
Source Clock Delay (SCD): -0.607ns
|
|
Clock Pessimism Removal (CPR): 0.192ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock mlkem_clk_clk_pll rise edge)
|
|
0.000 0.000 r
|
|
clock source latency -1.848 -1.848
|
|
propagated clock network latency
|
|
1.241 -0.607
|
|
SLICE_X118Y67 FDCE 0.000 -0.607 r pll_clk.u_rst_mlkem/delay_reg[1]/C
|
|
SLICE_X118Y67 FDCE (Prop_fdce_C_Q) 0.141 -0.466 r pll_clk.u_rst_mlkem/delay_reg[1]/Q
|
|
net (fo=4, routed) 0.297 -0.169 pll_clk.u_rst_mlkem/Q[0]
|
|
SLICE_X118Y67 r pll_clk.u_rst_mlkem/rdb_addr[11]_i_2/I0
|
|
SLICE_X118Y67 LUT1 (Prop_lut1_I0_O) 0.045 -0.124 f pll_clk.u_rst_mlkem/rdb_addr[11]_i_2/O
|
|
net (fo=1069, routed) 0.211 0.087 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/pre_addr_l_reg[2]_rep__1_0
|
|
SLICE_X121Y68 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/stream_byte_addr_reg[9]/CLR
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock mlkem_clk_clk_pll rise edge)
|
|
0.000 0.000 r
|
|
clock source latency -1.947 -1.947
|
|
propagated clock network latency
|
|
1.566 -0.381
|
|
clock pessimism -0.192 -0.573
|
|
SLICE_X121Y68 FDCE (Remov_fdce_C_CLR) -0.092 -0.665 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/stream_byte_addr_reg[9]
|
|
-------------------------------------------------------------------
|
|
required time 0.665
|
|
arrival time 0.087
|
|
-------------------------------------------------------------------
|
|
slack 0.753
|
|
|
|
Slack (MET) : 0.772ns (arrival time - required time)
|
|
Source: pll_clk.u_rst_mlkem/delay_reg[1]/C
|
|
(rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns})
|
|
Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/stream_wdata_reg[0]/CLR
|
|
(removal check against rising-edge clock mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns})
|
|
Path Group: **async_default**
|
|
Path Type: Removal (Min at Fast Process Corner)
|
|
Requirement: 0.000ns (mlkem_clk_clk_pll rise@0.000ns - mlkem_clk_clk_pll rise@0.000ns)
|
|
Data Path Delay: 0.692ns (logic 0.186ns (26.887%) route 0.506ns (73.113%))
|
|
Logic Levels: 1 (LUT1=1)
|
|
Clock Path Skew: 0.012ns (DCD - SCD - CPR)
|
|
Destination Clock Delay (DCD): -0.382ns
|
|
Source Clock Delay (SCD): -0.607ns
|
|
Clock Pessimism Removal (CPR): 0.213ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock mlkem_clk_clk_pll rise edge)
|
|
0.000 0.000 r
|
|
clock source latency -1.848 -1.848
|
|
propagated clock network latency
|
|
1.241 -0.607
|
|
SLICE_X118Y67 FDCE 0.000 -0.607 r pll_clk.u_rst_mlkem/delay_reg[1]/C
|
|
SLICE_X118Y67 FDCE (Prop_fdce_C_Q) 0.141 -0.466 r pll_clk.u_rst_mlkem/delay_reg[1]/Q
|
|
net (fo=4, routed) 0.297 -0.169 pll_clk.u_rst_mlkem/Q[0]
|
|
SLICE_X118Y67 r pll_clk.u_rst_mlkem/rdb_addr[11]_i_2/I0
|
|
SLICE_X118Y67 LUT1 (Prop_lut1_I0_O) 0.045 -0.124 f pll_clk.u_rst_mlkem/rdb_addr[11]_i_2/O
|
|
net (fo=1069, routed) 0.208 0.084 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/pre_addr_l_reg[2]_rep__1_0
|
|
SLICE_X119Y69 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/stream_wdata_reg[0]/CLR
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock mlkem_clk_clk_pll rise edge)
|
|
0.000 0.000 r
|
|
clock source latency -1.947 -1.947
|
|
propagated clock network latency
|
|
1.565 -0.382
|
|
clock pessimism -0.213 -0.595
|
|
SLICE_X119Y69 FDCE (Remov_fdce_C_CLR) -0.092 -0.687 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/stream_wdata_reg[0]
|
|
-------------------------------------------------------------------
|
|
required time 0.687
|
|
arrival time 0.084
|
|
-------------------------------------------------------------------
|
|
slack 0.772
|
|
|
|
Slack (MET) : 0.772ns (arrival time - required time)
|
|
Source: pll_clk.u_rst_mlkem/delay_reg[1]/C
|
|
(rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns})
|
|
Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/stream_wdata_reg[12]/CLR
|
|
(removal check against rising-edge clock mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns})
|
|
Path Group: **async_default**
|
|
Path Type: Removal (Min at Fast Process Corner)
|
|
Requirement: 0.000ns (mlkem_clk_clk_pll rise@0.000ns - mlkem_clk_clk_pll rise@0.000ns)
|
|
Data Path Delay: 0.692ns (logic 0.186ns (26.887%) route 0.506ns (73.113%))
|
|
Logic Levels: 1 (LUT1=1)
|
|
Clock Path Skew: 0.012ns (DCD - SCD - CPR)
|
|
Destination Clock Delay (DCD): -0.382ns
|
|
Source Clock Delay (SCD): -0.607ns
|
|
Clock Pessimism Removal (CPR): 0.213ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock mlkem_clk_clk_pll rise edge)
|
|
0.000 0.000 r
|
|
clock source latency -1.848 -1.848
|
|
propagated clock network latency
|
|
1.241 -0.607
|
|
SLICE_X118Y67 FDCE 0.000 -0.607 r pll_clk.u_rst_mlkem/delay_reg[1]/C
|
|
SLICE_X118Y67 FDCE (Prop_fdce_C_Q) 0.141 -0.466 r pll_clk.u_rst_mlkem/delay_reg[1]/Q
|
|
net (fo=4, routed) 0.297 -0.169 pll_clk.u_rst_mlkem/Q[0]
|
|
SLICE_X118Y67 r pll_clk.u_rst_mlkem/rdb_addr[11]_i_2/I0
|
|
SLICE_X118Y67 LUT1 (Prop_lut1_I0_O) 0.045 -0.124 f pll_clk.u_rst_mlkem/rdb_addr[11]_i_2/O
|
|
net (fo=1069, routed) 0.208 0.084 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/pre_addr_l_reg[2]_rep__1_0
|
|
SLICE_X119Y69 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/stream_wdata_reg[12]/CLR
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock mlkem_clk_clk_pll rise edge)
|
|
0.000 0.000 r
|
|
clock source latency -1.947 -1.947
|
|
propagated clock network latency
|
|
1.565 -0.382
|
|
clock pessimism -0.213 -0.595
|
|
SLICE_X119Y69 FDCE (Remov_fdce_C_CLR) -0.092 -0.687 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/stream_wdata_reg[12]
|
|
-------------------------------------------------------------------
|
|
required time 0.687
|
|
arrival time 0.084
|
|
-------------------------------------------------------------------
|
|
slack 0.772
|
|
|
|
Slack (MET) : 0.772ns (arrival time - required time)
|
|
Source: pll_clk.u_rst_mlkem/delay_reg[1]/C
|
|
(rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns})
|
|
Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/stream_wdata_reg[16]/CLR
|
|
(removal check against rising-edge clock mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns})
|
|
Path Group: **async_default**
|
|
Path Type: Removal (Min at Fast Process Corner)
|
|
Requirement: 0.000ns (mlkem_clk_clk_pll rise@0.000ns - mlkem_clk_clk_pll rise@0.000ns)
|
|
Data Path Delay: 0.692ns (logic 0.186ns (26.887%) route 0.506ns (73.113%))
|
|
Logic Levels: 1 (LUT1=1)
|
|
Clock Path Skew: 0.012ns (DCD - SCD - CPR)
|
|
Destination Clock Delay (DCD): -0.382ns
|
|
Source Clock Delay (SCD): -0.607ns
|
|
Clock Pessimism Removal (CPR): 0.213ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock mlkem_clk_clk_pll rise edge)
|
|
0.000 0.000 r
|
|
clock source latency -1.848 -1.848
|
|
propagated clock network latency
|
|
1.241 -0.607
|
|
SLICE_X118Y67 FDCE 0.000 -0.607 r pll_clk.u_rst_mlkem/delay_reg[1]/C
|
|
SLICE_X118Y67 FDCE (Prop_fdce_C_Q) 0.141 -0.466 r pll_clk.u_rst_mlkem/delay_reg[1]/Q
|
|
net (fo=4, routed) 0.297 -0.169 pll_clk.u_rst_mlkem/Q[0]
|
|
SLICE_X118Y67 r pll_clk.u_rst_mlkem/rdb_addr[11]_i_2/I0
|
|
SLICE_X118Y67 LUT1 (Prop_lut1_I0_O) 0.045 -0.124 f pll_clk.u_rst_mlkem/rdb_addr[11]_i_2/O
|
|
net (fo=1069, routed) 0.208 0.084 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/pre_addr_l_reg[2]_rep__1_0
|
|
SLICE_X119Y69 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/stream_wdata_reg[16]/CLR
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock mlkem_clk_clk_pll rise edge)
|
|
0.000 0.000 r
|
|
clock source latency -1.947 -1.947
|
|
propagated clock network latency
|
|
1.565 -0.382
|
|
clock pessimism -0.213 -0.595
|
|
SLICE_X119Y69 FDCE (Remov_fdce_C_CLR) -0.092 -0.687 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/stream_wdata_reg[16]
|
|
-------------------------------------------------------------------
|
|
required time 0.687
|
|
arrival time 0.084
|
|
-------------------------------------------------------------------
|
|
slack 0.772
|
|
|
|
Slack (MET) : 0.772ns (arrival time - required time)
|
|
Source: pll_clk.u_rst_mlkem/delay_reg[1]/C
|
|
(rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns})
|
|
Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/stream_wdata_reg[20]/CLR
|
|
(removal check against rising-edge clock mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns})
|
|
Path Group: **async_default**
|
|
Path Type: Removal (Min at Fast Process Corner)
|
|
Requirement: 0.000ns (mlkem_clk_clk_pll rise@0.000ns - mlkem_clk_clk_pll rise@0.000ns)
|
|
Data Path Delay: 0.692ns (logic 0.186ns (26.887%) route 0.506ns (73.113%))
|
|
Logic Levels: 1 (LUT1=1)
|
|
Clock Path Skew: 0.012ns (DCD - SCD - CPR)
|
|
Destination Clock Delay (DCD): -0.382ns
|
|
Source Clock Delay (SCD): -0.607ns
|
|
Clock Pessimism Removal (CPR): 0.213ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock mlkem_clk_clk_pll rise edge)
|
|
0.000 0.000 r
|
|
clock source latency -1.848 -1.848
|
|
propagated clock network latency
|
|
1.241 -0.607
|
|
SLICE_X118Y67 FDCE 0.000 -0.607 r pll_clk.u_rst_mlkem/delay_reg[1]/C
|
|
SLICE_X118Y67 FDCE (Prop_fdce_C_Q) 0.141 -0.466 r pll_clk.u_rst_mlkem/delay_reg[1]/Q
|
|
net (fo=4, routed) 0.297 -0.169 pll_clk.u_rst_mlkem/Q[0]
|
|
SLICE_X118Y67 r pll_clk.u_rst_mlkem/rdb_addr[11]_i_2/I0
|
|
SLICE_X118Y67 LUT1 (Prop_lut1_I0_O) 0.045 -0.124 f pll_clk.u_rst_mlkem/rdb_addr[11]_i_2/O
|
|
net (fo=1069, routed) 0.208 0.084 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/pre_addr_l_reg[2]_rep__1_0
|
|
SLICE_X119Y69 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/stream_wdata_reg[20]/CLR
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock mlkem_clk_clk_pll rise edge)
|
|
0.000 0.000 r
|
|
clock source latency -1.947 -1.947
|
|
propagated clock network latency
|
|
1.565 -0.382
|
|
clock pessimism -0.213 -0.595
|
|
SLICE_X119Y69 FDCE (Remov_fdce_C_CLR) -0.092 -0.687 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/stream_wdata_reg[20]
|
|
-------------------------------------------------------------------
|
|
required time 0.687
|
|
arrival time 0.084
|
|
-------------------------------------------------------------------
|
|
slack 0.772
|
|
|
|
Slack (MET) : 0.772ns (arrival time - required time)
|
|
Source: pll_clk.u_rst_mlkem/delay_reg[1]/C
|
|
(rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns})
|
|
Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/stream_wdata_reg[24]/CLR
|
|
(removal check against rising-edge clock mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns})
|
|
Path Group: **async_default**
|
|
Path Type: Removal (Min at Fast Process Corner)
|
|
Requirement: 0.000ns (mlkem_clk_clk_pll rise@0.000ns - mlkem_clk_clk_pll rise@0.000ns)
|
|
Data Path Delay: 0.692ns (logic 0.186ns (26.887%) route 0.506ns (73.113%))
|
|
Logic Levels: 1 (LUT1=1)
|
|
Clock Path Skew: 0.012ns (DCD - SCD - CPR)
|
|
Destination Clock Delay (DCD): -0.382ns
|
|
Source Clock Delay (SCD): -0.607ns
|
|
Clock Pessimism Removal (CPR): 0.213ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock mlkem_clk_clk_pll rise edge)
|
|
0.000 0.000 r
|
|
clock source latency -1.848 -1.848
|
|
propagated clock network latency
|
|
1.241 -0.607
|
|
SLICE_X118Y67 FDCE 0.000 -0.607 r pll_clk.u_rst_mlkem/delay_reg[1]/C
|
|
SLICE_X118Y67 FDCE (Prop_fdce_C_Q) 0.141 -0.466 r pll_clk.u_rst_mlkem/delay_reg[1]/Q
|
|
net (fo=4, routed) 0.297 -0.169 pll_clk.u_rst_mlkem/Q[0]
|
|
SLICE_X118Y67 r pll_clk.u_rst_mlkem/rdb_addr[11]_i_2/I0
|
|
SLICE_X118Y67 LUT1 (Prop_lut1_I0_O) 0.045 -0.124 f pll_clk.u_rst_mlkem/rdb_addr[11]_i_2/O
|
|
net (fo=1069, routed) 0.208 0.084 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/pre_addr_l_reg[2]_rep__1_0
|
|
SLICE_X119Y69 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/stream_wdata_reg[24]/CLR
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock mlkem_clk_clk_pll rise edge)
|
|
0.000 0.000 r
|
|
clock source latency -1.947 -1.947
|
|
propagated clock network latency
|
|
1.565 -0.382
|
|
clock pessimism -0.213 -0.595
|
|
SLICE_X119Y69 FDCE (Remov_fdce_C_CLR) -0.092 -0.687 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/stream_wdata_reg[24]
|
|
-------------------------------------------------------------------
|
|
required time 0.687
|
|
arrival time 0.084
|
|
-------------------------------------------------------------------
|
|
slack 0.772
|
|
|
|
Slack (MET) : 0.772ns (arrival time - required time)
|
|
Source: pll_clk.u_rst_mlkem/delay_reg[1]/C
|
|
(rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns})
|
|
Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/stream_wdata_reg[8]/CLR
|
|
(removal check against rising-edge clock mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns})
|
|
Path Group: **async_default**
|
|
Path Type: Removal (Min at Fast Process Corner)
|
|
Requirement: 0.000ns (mlkem_clk_clk_pll rise@0.000ns - mlkem_clk_clk_pll rise@0.000ns)
|
|
Data Path Delay: 0.692ns (logic 0.186ns (26.887%) route 0.506ns (73.113%))
|
|
Logic Levels: 1 (LUT1=1)
|
|
Clock Path Skew: 0.012ns (DCD - SCD - CPR)
|
|
Destination Clock Delay (DCD): -0.382ns
|
|
Source Clock Delay (SCD): -0.607ns
|
|
Clock Pessimism Removal (CPR): 0.213ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock mlkem_clk_clk_pll rise edge)
|
|
0.000 0.000 r
|
|
clock source latency -1.848 -1.848
|
|
propagated clock network latency
|
|
1.241 -0.607
|
|
SLICE_X118Y67 FDCE 0.000 -0.607 r pll_clk.u_rst_mlkem/delay_reg[1]/C
|
|
SLICE_X118Y67 FDCE (Prop_fdce_C_Q) 0.141 -0.466 r pll_clk.u_rst_mlkem/delay_reg[1]/Q
|
|
net (fo=4, routed) 0.297 -0.169 pll_clk.u_rst_mlkem/Q[0]
|
|
SLICE_X118Y67 r pll_clk.u_rst_mlkem/rdb_addr[11]_i_2/I0
|
|
SLICE_X118Y67 LUT1 (Prop_lut1_I0_O) 0.045 -0.124 f pll_clk.u_rst_mlkem/rdb_addr[11]_i_2/O
|
|
net (fo=1069, routed) 0.208 0.084 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/pre_addr_l_reg[2]_rep__1_0
|
|
SLICE_X119Y69 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/stream_wdata_reg[8]/CLR
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock mlkem_clk_clk_pll rise edge)
|
|
0.000 0.000 r
|
|
clock source latency -1.947 -1.947
|
|
propagated clock network latency
|
|
1.565 -0.382
|
|
clock pessimism -0.213 -0.595
|
|
SLICE_X119Y69 FDCE (Remov_fdce_C_CLR) -0.092 -0.687 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/stream_wdata_reg[8]
|
|
-------------------------------------------------------------------
|
|
required time 0.687
|
|
arrival time 0.084
|
|
-------------------------------------------------------------------
|
|
slack 0.772
|
|
|
|
Slack (MET) : 0.776ns (arrival time - required time)
|
|
Source: pll_clk.u_rst_mlkem/delay_reg[1]/C
|
|
(rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns})
|
|
Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/pre_byte_l_reg[0]/CLR
|
|
(removal check against rising-edge clock mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns})
|
|
Path Group: **async_default**
|
|
Path Type: Removal (Min at Fast Process Corner)
|
|
Requirement: 0.000ns (mlkem_clk_clk_pll rise@0.000ns - mlkem_clk_clk_pll rise@0.000ns)
|
|
Data Path Delay: 0.696ns (logic 0.186ns (26.719%) route 0.510ns (73.281%))
|
|
Logic Levels: 1 (LUT1=1)
|
|
Clock Path Skew: 0.012ns (DCD - SCD - CPR)
|
|
Destination Clock Delay (DCD): -0.382ns
|
|
Source Clock Delay (SCD): -0.607ns
|
|
Clock Pessimism Removal (CPR): 0.213ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock mlkem_clk_clk_pll rise edge)
|
|
0.000 0.000 r
|
|
clock source latency -1.848 -1.848
|
|
propagated clock network latency
|
|
1.241 -0.607
|
|
SLICE_X118Y67 FDCE 0.000 -0.607 r pll_clk.u_rst_mlkem/delay_reg[1]/C
|
|
SLICE_X118Y67 FDCE (Prop_fdce_C_Q) 0.141 -0.466 r pll_clk.u_rst_mlkem/delay_reg[1]/Q
|
|
net (fo=4, routed) 0.297 -0.169 pll_clk.u_rst_mlkem/Q[0]
|
|
SLICE_X118Y67 r pll_clk.u_rst_mlkem/rdb_addr[11]_i_2/I0
|
|
SLICE_X118Y67 LUT1 (Prop_lut1_I0_O) 0.045 -0.124 f pll_clk.u_rst_mlkem/rdb_addr[11]_i_2/O
|
|
net (fo=1069, routed) 0.213 0.089 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/pre_addr_l_reg[2]_rep__1_0
|
|
SLICE_X118Y69 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/pre_byte_l_reg[0]/CLR
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock mlkem_clk_clk_pll rise edge)
|
|
0.000 0.000 r
|
|
clock source latency -1.947 -1.947
|
|
propagated clock network latency
|
|
1.565 -0.382
|
|
clock pessimism -0.213 -0.595
|
|
SLICE_X118Y69 FDCE (Remov_fdce_C_CLR) -0.092 -0.687 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/pre_byte_l_reg[0]
|
|
-------------------------------------------------------------------
|
|
required time 0.687
|
|
arrival time 0.089
|
|
-------------------------------------------------------------------
|
|
slack 0.776
|
|
|
|
Slack (MET) : 0.776ns (arrival time - required time)
|
|
Source: pll_clk.u_rst_mlkem/delay_reg[1]/C
|
|
(rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns})
|
|
Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/pre_byte_l_reg[4]/CLR
|
|
(removal check against rising-edge clock mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns})
|
|
Path Group: **async_default**
|
|
Path Type: Removal (Min at Fast Process Corner)
|
|
Requirement: 0.000ns (mlkem_clk_clk_pll rise@0.000ns - mlkem_clk_clk_pll rise@0.000ns)
|
|
Data Path Delay: 0.696ns (logic 0.186ns (26.719%) route 0.510ns (73.281%))
|
|
Logic Levels: 1 (LUT1=1)
|
|
Clock Path Skew: 0.012ns (DCD - SCD - CPR)
|
|
Destination Clock Delay (DCD): -0.382ns
|
|
Source Clock Delay (SCD): -0.607ns
|
|
Clock Pessimism Removal (CPR): 0.213ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock mlkem_clk_clk_pll rise edge)
|
|
0.000 0.000 r
|
|
clock source latency -1.848 -1.848
|
|
propagated clock network latency
|
|
1.241 -0.607
|
|
SLICE_X118Y67 FDCE 0.000 -0.607 r pll_clk.u_rst_mlkem/delay_reg[1]/C
|
|
SLICE_X118Y67 FDCE (Prop_fdce_C_Q) 0.141 -0.466 r pll_clk.u_rst_mlkem/delay_reg[1]/Q
|
|
net (fo=4, routed) 0.297 -0.169 pll_clk.u_rst_mlkem/Q[0]
|
|
SLICE_X118Y67 r pll_clk.u_rst_mlkem/rdb_addr[11]_i_2/I0
|
|
SLICE_X118Y67 LUT1 (Prop_lut1_I0_O) 0.045 -0.124 f pll_clk.u_rst_mlkem/rdb_addr[11]_i_2/O
|
|
net (fo=1069, routed) 0.213 0.089 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/pre_addr_l_reg[2]_rep__1_0
|
|
SLICE_X118Y69 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/pre_byte_l_reg[4]/CLR
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock mlkem_clk_clk_pll rise edge)
|
|
0.000 0.000 r
|
|
clock source latency -1.947 -1.947
|
|
propagated clock network latency
|
|
1.565 -0.382
|
|
clock pessimism -0.213 -0.595
|
|
SLICE_X118Y69 FDCE (Remov_fdce_C_CLR) -0.092 -0.687 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/pre_byte_l_reg[4]
|
|
-------------------------------------------------------------------
|
|
required time 0.687
|
|
arrival time 0.089
|
|
-------------------------------------------------------------------
|
|
slack 0.776
|
|
|
|
Slack (MET) : 0.799ns (arrival time - required time)
|
|
Source: pll_clk.u_rst_mlkem/delay_reg[1]/C
|
|
(rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns})
|
|
Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/pre_addr_l_reg[10]/CLR
|
|
(removal check against rising-edge clock mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns})
|
|
Path Group: **async_default**
|
|
Path Type: Removal (Min at Fast Process Corner)
|
|
Requirement: 0.000ns (mlkem_clk_clk_pll rise@0.000ns - mlkem_clk_clk_pll rise@0.000ns)
|
|
Data Path Delay: 0.741ns (logic 0.186ns (25.097%) route 0.555ns (74.903%))
|
|
Logic Levels: 1 (LUT1=1)
|
|
Clock Path Skew: 0.034ns (DCD - SCD - CPR)
|
|
Destination Clock Delay (DCD): -0.381ns
|
|
Source Clock Delay (SCD): -0.607ns
|
|
Clock Pessimism Removal (CPR): 0.192ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock mlkem_clk_clk_pll rise edge)
|
|
0.000 0.000 r
|
|
clock source latency -1.848 -1.848
|
|
propagated clock network latency
|
|
1.241 -0.607
|
|
SLICE_X118Y67 FDCE 0.000 -0.607 r pll_clk.u_rst_mlkem/delay_reg[1]/C
|
|
SLICE_X118Y67 FDCE (Prop_fdce_C_Q) 0.141 -0.466 r pll_clk.u_rst_mlkem/delay_reg[1]/Q
|
|
net (fo=4, routed) 0.297 -0.169 pll_clk.u_rst_mlkem/Q[0]
|
|
SLICE_X118Y67 r pll_clk.u_rst_mlkem/rdb_addr[11]_i_2/I0
|
|
SLICE_X118Y67 LUT1 (Prop_lut1_I0_O) 0.045 -0.124 f pll_clk.u_rst_mlkem/rdb_addr[11]_i_2/O
|
|
net (fo=1069, routed) 0.258 0.134 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/pre_addr_l_reg[2]_rep__1_0
|
|
SLICE_X123Y68 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/pre_addr_l_reg[10]/CLR
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock mlkem_clk_clk_pll rise edge)
|
|
0.000 0.000 r
|
|
clock source latency -1.947 -1.947
|
|
propagated clock network latency
|
|
1.566 -0.381
|
|
clock pessimism -0.192 -0.573
|
|
SLICE_X123Y68 FDCE (Remov_fdce_C_CLR) -0.092 -0.665 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/pre_addr_l_reg[10]
|
|
-------------------------------------------------------------------
|
|
required time 0.665
|
|
arrival time 0.134
|
|
-------------------------------------------------------------------
|
|
slack 0.799
|
|
|
|
Slack (MET) : 0.799ns (arrival time - required time)
|
|
Source: pll_clk.u_rst_mlkem/delay_reg[1]/C
|
|
(rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns})
|
|
Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/pre_addr_l_reg[11]/CLR
|
|
(removal check against rising-edge clock mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns})
|
|
Path Group: **async_default**
|
|
Path Type: Removal (Min at Fast Process Corner)
|
|
Requirement: 0.000ns (mlkem_clk_clk_pll rise@0.000ns - mlkem_clk_clk_pll rise@0.000ns)
|
|
Data Path Delay: 0.741ns (logic 0.186ns (25.097%) route 0.555ns (74.903%))
|
|
Logic Levels: 1 (LUT1=1)
|
|
Clock Path Skew: 0.034ns (DCD - SCD - CPR)
|
|
Destination Clock Delay (DCD): -0.381ns
|
|
Source Clock Delay (SCD): -0.607ns
|
|
Clock Pessimism Removal (CPR): 0.192ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock mlkem_clk_clk_pll rise edge)
|
|
0.000 0.000 r
|
|
clock source latency -1.848 -1.848
|
|
propagated clock network latency
|
|
1.241 -0.607
|
|
SLICE_X118Y67 FDCE 0.000 -0.607 r pll_clk.u_rst_mlkem/delay_reg[1]/C
|
|
SLICE_X118Y67 FDCE (Prop_fdce_C_Q) 0.141 -0.466 r pll_clk.u_rst_mlkem/delay_reg[1]/Q
|
|
net (fo=4, routed) 0.297 -0.169 pll_clk.u_rst_mlkem/Q[0]
|
|
SLICE_X118Y67 r pll_clk.u_rst_mlkem/rdb_addr[11]_i_2/I0
|
|
SLICE_X118Y67 LUT1 (Prop_lut1_I0_O) 0.045 -0.124 f pll_clk.u_rst_mlkem/rdb_addr[11]_i_2/O
|
|
net (fo=1069, routed) 0.258 0.134 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/pre_addr_l_reg[2]_rep__1_0
|
|
SLICE_X123Y68 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/pre_addr_l_reg[11]/CLR
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock mlkem_clk_clk_pll rise edge)
|
|
0.000 0.000 r
|
|
clock source latency -1.947 -1.947
|
|
propagated clock network latency
|
|
1.566 -0.381
|
|
clock pessimism -0.192 -0.573
|
|
SLICE_X123Y68 FDCE (Remov_fdce_C_CLR) -0.092 -0.665 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/pre_addr_l_reg[11]
|
|
-------------------------------------------------------------------
|
|
required time 0.665
|
|
arrival time 0.134
|
|
-------------------------------------------------------------------
|
|
slack 0.799
|
|
|
|
Slack (MET) : 0.799ns (arrival time - required time)
|
|
Source: pll_clk.u_rst_mlkem/delay_reg[1]/C
|
|
(rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns})
|
|
Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/pre_addr_l_reg[8]/CLR
|
|
(removal check against rising-edge clock mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns})
|
|
Path Group: **async_default**
|
|
Path Type: Removal (Min at Fast Process Corner)
|
|
Requirement: 0.000ns (mlkem_clk_clk_pll rise@0.000ns - mlkem_clk_clk_pll rise@0.000ns)
|
|
Data Path Delay: 0.741ns (logic 0.186ns (25.097%) route 0.555ns (74.903%))
|
|
Logic Levels: 1 (LUT1=1)
|
|
Clock Path Skew: 0.034ns (DCD - SCD - CPR)
|
|
Destination Clock Delay (DCD): -0.381ns
|
|
Source Clock Delay (SCD): -0.607ns
|
|
Clock Pessimism Removal (CPR): 0.192ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock mlkem_clk_clk_pll rise edge)
|
|
0.000 0.000 r
|
|
clock source latency -1.848 -1.848
|
|
propagated clock network latency
|
|
1.241 -0.607
|
|
SLICE_X118Y67 FDCE 0.000 -0.607 r pll_clk.u_rst_mlkem/delay_reg[1]/C
|
|
SLICE_X118Y67 FDCE (Prop_fdce_C_Q) 0.141 -0.466 r pll_clk.u_rst_mlkem/delay_reg[1]/Q
|
|
net (fo=4, routed) 0.297 -0.169 pll_clk.u_rst_mlkem/Q[0]
|
|
SLICE_X118Y67 r pll_clk.u_rst_mlkem/rdb_addr[11]_i_2/I0
|
|
SLICE_X118Y67 LUT1 (Prop_lut1_I0_O) 0.045 -0.124 f pll_clk.u_rst_mlkem/rdb_addr[11]_i_2/O
|
|
net (fo=1069, routed) 0.258 0.134 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/pre_addr_l_reg[2]_rep__1_0
|
|
SLICE_X123Y68 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/pre_addr_l_reg[8]/CLR
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock mlkem_clk_clk_pll rise edge)
|
|
0.000 0.000 r
|
|
clock source latency -1.947 -1.947
|
|
propagated clock network latency
|
|
1.566 -0.381
|
|
clock pessimism -0.192 -0.573
|
|
SLICE_X123Y68 FDCE (Remov_fdce_C_CLR) -0.092 -0.665 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/pre_addr_l_reg[8]
|
|
-------------------------------------------------------------------
|
|
required time 0.665
|
|
arrival time 0.134
|
|
-------------------------------------------------------------------
|
|
slack 0.799
|
|
|
|
Slack (MET) : 0.799ns (arrival time - required time)
|
|
Source: pll_clk.u_rst_mlkem/delay_reg[1]/C
|
|
(rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns})
|
|
Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/pre_addr_l_reg[9]/CLR
|
|
(removal check against rising-edge clock mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns})
|
|
Path Group: **async_default**
|
|
Path Type: Removal (Min at Fast Process Corner)
|
|
Requirement: 0.000ns (mlkem_clk_clk_pll rise@0.000ns - mlkem_clk_clk_pll rise@0.000ns)
|
|
Data Path Delay: 0.741ns (logic 0.186ns (25.097%) route 0.555ns (74.903%))
|
|
Logic Levels: 1 (LUT1=1)
|
|
Clock Path Skew: 0.034ns (DCD - SCD - CPR)
|
|
Destination Clock Delay (DCD): -0.381ns
|
|
Source Clock Delay (SCD): -0.607ns
|
|
Clock Pessimism Removal (CPR): 0.192ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock mlkem_clk_clk_pll rise edge)
|
|
0.000 0.000 r
|
|
clock source latency -1.848 -1.848
|
|
propagated clock network latency
|
|
1.241 -0.607
|
|
SLICE_X118Y67 FDCE 0.000 -0.607 r pll_clk.u_rst_mlkem/delay_reg[1]/C
|
|
SLICE_X118Y67 FDCE (Prop_fdce_C_Q) 0.141 -0.466 r pll_clk.u_rst_mlkem/delay_reg[1]/Q
|
|
net (fo=4, routed) 0.297 -0.169 pll_clk.u_rst_mlkem/Q[0]
|
|
SLICE_X118Y67 r pll_clk.u_rst_mlkem/rdb_addr[11]_i_2/I0
|
|
SLICE_X118Y67 LUT1 (Prop_lut1_I0_O) 0.045 -0.124 f pll_clk.u_rst_mlkem/rdb_addr[11]_i_2/O
|
|
net (fo=1069, routed) 0.258 0.134 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/pre_addr_l_reg[2]_rep__1_0
|
|
SLICE_X123Y68 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/pre_addr_l_reg[9]/CLR
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock mlkem_clk_clk_pll rise edge)
|
|
0.000 0.000 r
|
|
clock source latency -1.947 -1.947
|
|
propagated clock network latency
|
|
1.566 -0.381
|
|
clock pessimism -0.192 -0.573
|
|
SLICE_X123Y68 FDCE (Remov_fdce_C_CLR) -0.092 -0.665 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/pre_addr_l_reg[9]
|
|
-------------------------------------------------------------------
|
|
required time 0.665
|
|
arrival time 0.134
|
|
-------------------------------------------------------------------
|
|
slack 0.799
|
|
|
|
Slack (MET) : 0.799ns (arrival time - required time)
|
|
Source: pll_clk.u_rst_mlkem/delay_reg[1]/C
|
|
(rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns})
|
|
Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/stream_wdata_reg[11]/CLR
|
|
(removal check against rising-edge clock mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns})
|
|
Path Group: **async_default**
|
|
Path Type: Removal (Min at Fast Process Corner)
|
|
Requirement: 0.000ns (mlkem_clk_clk_pll rise@0.000ns - mlkem_clk_clk_pll rise@0.000ns)
|
|
Data Path Delay: 0.765ns (logic 0.186ns (24.299%) route 0.579ns (75.701%))
|
|
Logic Levels: 1 (LUT1=1)
|
|
Clock Path Skew: 0.033ns (DCD - SCD - CPR)
|
|
Destination Clock Delay (DCD): -0.382ns
|
|
Source Clock Delay (SCD): -0.607ns
|
|
Clock Pessimism Removal (CPR): 0.192ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock mlkem_clk_clk_pll rise edge)
|
|
0.000 0.000 r
|
|
clock source latency -1.848 -1.848
|
|
propagated clock network latency
|
|
1.241 -0.607
|
|
SLICE_X118Y67 FDCE 0.000 -0.607 r pll_clk.u_rst_mlkem/delay_reg[1]/C
|
|
SLICE_X118Y67 FDCE (Prop_fdce_C_Q) 0.141 -0.466 r pll_clk.u_rst_mlkem/delay_reg[1]/Q
|
|
net (fo=4, routed) 0.297 -0.169 pll_clk.u_rst_mlkem/Q[0]
|
|
SLICE_X118Y67 r pll_clk.u_rst_mlkem/rdb_addr[11]_i_2/I0
|
|
SLICE_X118Y67 LUT1 (Prop_lut1_I0_O) 0.045 -0.124 f pll_clk.u_rst_mlkem/rdb_addr[11]_i_2/O
|
|
net (fo=1069, routed) 0.282 0.158 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/pre_addr_l_reg[2]_rep__1_0
|
|
SLICE_X120Y69 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/stream_wdata_reg[11]/CLR
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock mlkem_clk_clk_pll rise edge)
|
|
0.000 0.000 r
|
|
clock source latency -1.947 -1.947
|
|
propagated clock network latency
|
|
1.565 -0.382
|
|
clock pessimism -0.192 -0.574
|
|
SLICE_X120Y69 FDCE (Remov_fdce_C_CLR) -0.067 -0.641 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/stream_wdata_reg[11]
|
|
-------------------------------------------------------------------
|
|
required time 0.641
|
|
arrival time 0.158
|
|
-------------------------------------------------------------------
|
|
slack 0.799
|
|
|
|
Slack (MET) : 0.799ns (arrival time - required time)
|
|
Source: pll_clk.u_rst_mlkem/delay_reg[1]/C
|
|
(rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns})
|
|
Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/stream_wdata_reg[19]/CLR
|
|
(removal check against rising-edge clock mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns})
|
|
Path Group: **async_default**
|
|
Path Type: Removal (Min at Fast Process Corner)
|
|
Requirement: 0.000ns (mlkem_clk_clk_pll rise@0.000ns - mlkem_clk_clk_pll rise@0.000ns)
|
|
Data Path Delay: 0.765ns (logic 0.186ns (24.299%) route 0.579ns (75.701%))
|
|
Logic Levels: 1 (LUT1=1)
|
|
Clock Path Skew: 0.033ns (DCD - SCD - CPR)
|
|
Destination Clock Delay (DCD): -0.382ns
|
|
Source Clock Delay (SCD): -0.607ns
|
|
Clock Pessimism Removal (CPR): 0.192ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock mlkem_clk_clk_pll rise edge)
|
|
0.000 0.000 r
|
|
clock source latency -1.848 -1.848
|
|
propagated clock network latency
|
|
1.241 -0.607
|
|
SLICE_X118Y67 FDCE 0.000 -0.607 r pll_clk.u_rst_mlkem/delay_reg[1]/C
|
|
SLICE_X118Y67 FDCE (Prop_fdce_C_Q) 0.141 -0.466 r pll_clk.u_rst_mlkem/delay_reg[1]/Q
|
|
net (fo=4, routed) 0.297 -0.169 pll_clk.u_rst_mlkem/Q[0]
|
|
SLICE_X118Y67 r pll_clk.u_rst_mlkem/rdb_addr[11]_i_2/I0
|
|
SLICE_X118Y67 LUT1 (Prop_lut1_I0_O) 0.045 -0.124 f pll_clk.u_rst_mlkem/rdb_addr[11]_i_2/O
|
|
net (fo=1069, routed) 0.282 0.158 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/pre_addr_l_reg[2]_rep__1_0
|
|
SLICE_X120Y69 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/stream_wdata_reg[19]/CLR
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock mlkem_clk_clk_pll rise edge)
|
|
0.000 0.000 r
|
|
clock source latency -1.947 -1.947
|
|
propagated clock network latency
|
|
1.565 -0.382
|
|
clock pessimism -0.192 -0.574
|
|
SLICE_X120Y69 FDCE (Remov_fdce_C_CLR) -0.067 -0.641 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/stream_wdata_reg[19]
|
|
-------------------------------------------------------------------
|
|
required time 0.641
|
|
arrival time 0.158
|
|
-------------------------------------------------------------------
|
|
slack 0.799
|
|
|
|
Slack (MET) : 0.799ns (arrival time - required time)
|
|
Source: pll_clk.u_rst_mlkem/delay_reg[1]/C
|
|
(rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns})
|
|
Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/stream_wdata_reg[27]/CLR
|
|
(removal check against rising-edge clock mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns})
|
|
Path Group: **async_default**
|
|
Path Type: Removal (Min at Fast Process Corner)
|
|
Requirement: 0.000ns (mlkem_clk_clk_pll rise@0.000ns - mlkem_clk_clk_pll rise@0.000ns)
|
|
Data Path Delay: 0.765ns (logic 0.186ns (24.299%) route 0.579ns (75.701%))
|
|
Logic Levels: 1 (LUT1=1)
|
|
Clock Path Skew: 0.033ns (DCD - SCD - CPR)
|
|
Destination Clock Delay (DCD): -0.382ns
|
|
Source Clock Delay (SCD): -0.607ns
|
|
Clock Pessimism Removal (CPR): 0.192ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock mlkem_clk_clk_pll rise edge)
|
|
0.000 0.000 r
|
|
clock source latency -1.848 -1.848
|
|
propagated clock network latency
|
|
1.241 -0.607
|
|
SLICE_X118Y67 FDCE 0.000 -0.607 r pll_clk.u_rst_mlkem/delay_reg[1]/C
|
|
SLICE_X118Y67 FDCE (Prop_fdce_C_Q) 0.141 -0.466 r pll_clk.u_rst_mlkem/delay_reg[1]/Q
|
|
net (fo=4, routed) 0.297 -0.169 pll_clk.u_rst_mlkem/Q[0]
|
|
SLICE_X118Y67 r pll_clk.u_rst_mlkem/rdb_addr[11]_i_2/I0
|
|
SLICE_X118Y67 LUT1 (Prop_lut1_I0_O) 0.045 -0.124 f pll_clk.u_rst_mlkem/rdb_addr[11]_i_2/O
|
|
net (fo=1069, routed) 0.282 0.158 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/pre_addr_l_reg[2]_rep__1_0
|
|
SLICE_X120Y69 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/stream_wdata_reg[27]/CLR
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock mlkem_clk_clk_pll rise edge)
|
|
0.000 0.000 r
|
|
clock source latency -1.947 -1.947
|
|
propagated clock network latency
|
|
1.565 -0.382
|
|
clock pessimism -0.192 -0.574
|
|
SLICE_X120Y69 FDCE (Remov_fdce_C_CLR) -0.067 -0.641 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/stream_wdata_reg[27]
|
|
-------------------------------------------------------------------
|
|
required time 0.641
|
|
arrival time 0.158
|
|
-------------------------------------------------------------------
|
|
slack 0.799
|
|
|
|
Slack (MET) : 0.799ns (arrival time - required time)
|
|
Source: pll_clk.u_rst_mlkem/delay_reg[1]/C
|
|
(rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns})
|
|
Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/stream_wdata_reg[28]/CLR
|
|
(removal check against rising-edge clock mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns})
|
|
Path Group: **async_default**
|
|
Path Type: Removal (Min at Fast Process Corner)
|
|
Requirement: 0.000ns (mlkem_clk_clk_pll rise@0.000ns - mlkem_clk_clk_pll rise@0.000ns)
|
|
Data Path Delay: 0.765ns (logic 0.186ns (24.299%) route 0.579ns (75.701%))
|
|
Logic Levels: 1 (LUT1=1)
|
|
Clock Path Skew: 0.033ns (DCD - SCD - CPR)
|
|
Destination Clock Delay (DCD): -0.382ns
|
|
Source Clock Delay (SCD): -0.607ns
|
|
Clock Pessimism Removal (CPR): 0.192ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock mlkem_clk_clk_pll rise edge)
|
|
0.000 0.000 r
|
|
clock source latency -1.848 -1.848
|
|
propagated clock network latency
|
|
1.241 -0.607
|
|
SLICE_X118Y67 FDCE 0.000 -0.607 r pll_clk.u_rst_mlkem/delay_reg[1]/C
|
|
SLICE_X118Y67 FDCE (Prop_fdce_C_Q) 0.141 -0.466 r pll_clk.u_rst_mlkem/delay_reg[1]/Q
|
|
net (fo=4, routed) 0.297 -0.169 pll_clk.u_rst_mlkem/Q[0]
|
|
SLICE_X118Y67 r pll_clk.u_rst_mlkem/rdb_addr[11]_i_2/I0
|
|
SLICE_X118Y67 LUT1 (Prop_lut1_I0_O) 0.045 -0.124 f pll_clk.u_rst_mlkem/rdb_addr[11]_i_2/O
|
|
net (fo=1069, routed) 0.282 0.158 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/pre_addr_l_reg[2]_rep__1_0
|
|
SLICE_X120Y69 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/stream_wdata_reg[28]/CLR
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock mlkem_clk_clk_pll rise edge)
|
|
0.000 0.000 r
|
|
clock source latency -1.947 -1.947
|
|
propagated clock network latency
|
|
1.565 -0.382
|
|
clock pessimism -0.192 -0.574
|
|
SLICE_X120Y69 FDCE (Remov_fdce_C_CLR) -0.067 -0.641 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/stream_wdata_reg[28]
|
|
-------------------------------------------------------------------
|
|
required time 0.641
|
|
arrival time 0.158
|
|
-------------------------------------------------------------------
|
|
slack 0.799
|
|
|
|
Slack (MET) : 0.799ns (arrival time - required time)
|
|
Source: pll_clk.u_rst_mlkem/delay_reg[1]/C
|
|
(rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns})
|
|
Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/stream_wdata_reg[30]/CLR
|
|
(removal check against rising-edge clock mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns})
|
|
Path Group: **async_default**
|
|
Path Type: Removal (Min at Fast Process Corner)
|
|
Requirement: 0.000ns (mlkem_clk_clk_pll rise@0.000ns - mlkem_clk_clk_pll rise@0.000ns)
|
|
Data Path Delay: 0.765ns (logic 0.186ns (24.299%) route 0.579ns (75.701%))
|
|
Logic Levels: 1 (LUT1=1)
|
|
Clock Path Skew: 0.033ns (DCD - SCD - CPR)
|
|
Destination Clock Delay (DCD): -0.382ns
|
|
Source Clock Delay (SCD): -0.607ns
|
|
Clock Pessimism Removal (CPR): 0.192ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock mlkem_clk_clk_pll rise edge)
|
|
0.000 0.000 r
|
|
clock source latency -1.848 -1.848
|
|
propagated clock network latency
|
|
1.241 -0.607
|
|
SLICE_X118Y67 FDCE 0.000 -0.607 r pll_clk.u_rst_mlkem/delay_reg[1]/C
|
|
SLICE_X118Y67 FDCE (Prop_fdce_C_Q) 0.141 -0.466 r pll_clk.u_rst_mlkem/delay_reg[1]/Q
|
|
net (fo=4, routed) 0.297 -0.169 pll_clk.u_rst_mlkem/Q[0]
|
|
SLICE_X118Y67 r pll_clk.u_rst_mlkem/rdb_addr[11]_i_2/I0
|
|
SLICE_X118Y67 LUT1 (Prop_lut1_I0_O) 0.045 -0.124 f pll_clk.u_rst_mlkem/rdb_addr[11]_i_2/O
|
|
net (fo=1069, routed) 0.282 0.158 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/pre_addr_l_reg[2]_rep__1_0
|
|
SLICE_X120Y69 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/stream_wdata_reg[30]/CLR
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock mlkem_clk_clk_pll rise edge)
|
|
0.000 0.000 r
|
|
clock source latency -1.947 -1.947
|
|
propagated clock network latency
|
|
1.565 -0.382
|
|
clock pessimism -0.192 -0.574
|
|
SLICE_X120Y69 FDCE (Remov_fdce_C_CLR) -0.067 -0.641 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/stream_wdata_reg[30]
|
|
-------------------------------------------------------------------
|
|
required time 0.641
|
|
arrival time 0.158
|
|
-------------------------------------------------------------------
|
|
slack 0.799
|
|
|
|
Slack (MET) : 0.799ns (arrival time - required time)
|
|
Source: pll_clk.u_rst_mlkem/delay_reg[1]/C
|
|
(rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns})
|
|
Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/stream_wdata_reg[3]/CLR
|
|
(removal check against rising-edge clock mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns})
|
|
Path Group: **async_default**
|
|
Path Type: Removal (Min at Fast Process Corner)
|
|
Requirement: 0.000ns (mlkem_clk_clk_pll rise@0.000ns - mlkem_clk_clk_pll rise@0.000ns)
|
|
Data Path Delay: 0.765ns (logic 0.186ns (24.299%) route 0.579ns (75.701%))
|
|
Logic Levels: 1 (LUT1=1)
|
|
Clock Path Skew: 0.033ns (DCD - SCD - CPR)
|
|
Destination Clock Delay (DCD): -0.382ns
|
|
Source Clock Delay (SCD): -0.607ns
|
|
Clock Pessimism Removal (CPR): 0.192ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock mlkem_clk_clk_pll rise edge)
|
|
0.000 0.000 r
|
|
clock source latency -1.848 -1.848
|
|
propagated clock network latency
|
|
1.241 -0.607
|
|
SLICE_X118Y67 FDCE 0.000 -0.607 r pll_clk.u_rst_mlkem/delay_reg[1]/C
|
|
SLICE_X118Y67 FDCE (Prop_fdce_C_Q) 0.141 -0.466 r pll_clk.u_rst_mlkem/delay_reg[1]/Q
|
|
net (fo=4, routed) 0.297 -0.169 pll_clk.u_rst_mlkem/Q[0]
|
|
SLICE_X118Y67 r pll_clk.u_rst_mlkem/rdb_addr[11]_i_2/I0
|
|
SLICE_X118Y67 LUT1 (Prop_lut1_I0_O) 0.045 -0.124 f pll_clk.u_rst_mlkem/rdb_addr[11]_i_2/O
|
|
net (fo=1069, routed) 0.282 0.158 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/pre_addr_l_reg[2]_rep__1_0
|
|
SLICE_X120Y69 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/stream_wdata_reg[3]/CLR
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock mlkem_clk_clk_pll rise edge)
|
|
0.000 0.000 r
|
|
clock source latency -1.947 -1.947
|
|
propagated clock network latency
|
|
1.565 -0.382
|
|
clock pessimism -0.192 -0.574
|
|
SLICE_X120Y69 FDCE (Remov_fdce_C_CLR) -0.067 -0.641 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/stream_wdata_reg[3]
|
|
-------------------------------------------------------------------
|
|
required time 0.641
|
|
arrival time 0.158
|
|
-------------------------------------------------------------------
|
|
slack 0.799
|
|
|
|
Slack (MET) : 0.799ns (arrival time - required time)
|
|
Source: pll_clk.u_rst_mlkem/delay_reg[1]/C
|
|
(rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns})
|
|
Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/stream_wdata_reg[4]/CLR
|
|
(removal check against rising-edge clock mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns})
|
|
Path Group: **async_default**
|
|
Path Type: Removal (Min at Fast Process Corner)
|
|
Requirement: 0.000ns (mlkem_clk_clk_pll rise@0.000ns - mlkem_clk_clk_pll rise@0.000ns)
|
|
Data Path Delay: 0.765ns (logic 0.186ns (24.299%) route 0.579ns (75.701%))
|
|
Logic Levels: 1 (LUT1=1)
|
|
Clock Path Skew: 0.033ns (DCD - SCD - CPR)
|
|
Destination Clock Delay (DCD): -0.382ns
|
|
Source Clock Delay (SCD): -0.607ns
|
|
Clock Pessimism Removal (CPR): 0.192ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock mlkem_clk_clk_pll rise edge)
|
|
0.000 0.000 r
|
|
clock source latency -1.848 -1.848
|
|
propagated clock network latency
|
|
1.241 -0.607
|
|
SLICE_X118Y67 FDCE 0.000 -0.607 r pll_clk.u_rst_mlkem/delay_reg[1]/C
|
|
SLICE_X118Y67 FDCE (Prop_fdce_C_Q) 0.141 -0.466 r pll_clk.u_rst_mlkem/delay_reg[1]/Q
|
|
net (fo=4, routed) 0.297 -0.169 pll_clk.u_rst_mlkem/Q[0]
|
|
SLICE_X118Y67 r pll_clk.u_rst_mlkem/rdb_addr[11]_i_2/I0
|
|
SLICE_X118Y67 LUT1 (Prop_lut1_I0_O) 0.045 -0.124 f pll_clk.u_rst_mlkem/rdb_addr[11]_i_2/O
|
|
net (fo=1069, routed) 0.282 0.158 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/pre_addr_l_reg[2]_rep__1_0
|
|
SLICE_X120Y69 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/stream_wdata_reg[4]/CLR
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock mlkem_clk_clk_pll rise edge)
|
|
0.000 0.000 r
|
|
clock source latency -1.947 -1.947
|
|
propagated clock network latency
|
|
1.565 -0.382
|
|
clock pessimism -0.192 -0.574
|
|
SLICE_X120Y69 FDCE (Remov_fdce_C_CLR) -0.067 -0.641 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/stream_wdata_reg[4]
|
|
-------------------------------------------------------------------
|
|
required time 0.641
|
|
arrival time 0.158
|
|
-------------------------------------------------------------------
|
|
slack 0.799
|
|
|
|
Slack (MET) : 0.800ns (arrival time - required time)
|
|
Source: u_Axi_CDC/awFifo/bufferCC_12/buffers_1_reg/C
|
|
(rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Destination: u_Axi_CDC/wFifo/popCC_ptrToPush_reg[0]/CLR
|
|
(removal check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Path Group: **async_default**
|
|
Path Type: Removal (Min at Fast Process Corner)
|
|
Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns)
|
|
Data Path Delay: 1.055ns (logic 0.227ns (21.508%) route 0.828ns (78.492%))
|
|
Logic Levels: 1 (LUT1=1)
|
|
Clock Path Skew: 0.347ns (DCD - SCD - CPR)
|
|
Destination Clock Delay (DCD): -0.231ns
|
|
Source Clock Delay (SCD): -0.541ns
|
|
Clock Pessimism Removal (CPR): -0.037ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock sys_clk rise edge) 0.000 0.000 r
|
|
clock source latency -1.848 -1.848
|
|
propagated clock network latency
|
|
1.307 -0.541
|
|
SLICE_X7Y59 FDCE 0.000 -0.541 r u_Axi_CDC/awFifo/bufferCC_12/buffers_1_reg/C
|
|
SLICE_X7Y59 FDCE (Prop_fdce_C_Q) 0.128 -0.413 r u_Axi_CDC/awFifo/bufferCC_12/buffers_1_reg/Q
|
|
net (fo=1, routed) 0.283 -0.131 u_Axi_CDC/awFifo/bufferCC_12/buffers_1
|
|
SLICE_X7Y59 r u_Axi_CDC/awFifo/bufferCC_12/popCC_popPtr[2]_i_2/I0
|
|
SLICE_X7Y59 LUT1 (Prop_lut1_I0_O) 0.099 -0.032 f u_Axi_CDC/awFifo/bufferCC_12/popCC_popPtr[2]_i_2/O
|
|
net (fo=43, routed) 0.546 0.514 u_Axi_CDC/wFifo/buffers_0_reg[3]
|
|
SLICE_X5Y49 FDCE f u_Axi_CDC/wFifo/popCC_ptrToPush_reg[0]/CLR
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock sys_clk rise edge) 0.000 0.000 r
|
|
clock source latency -1.947 -1.947
|
|
propagated clock network latency
|
|
1.716 -0.231
|
|
clock pessimism 0.037 -0.194
|
|
SLICE_X5Y49 FDCE (Remov_fdce_C_CLR) -0.092 -0.286 u_Axi_CDC/wFifo/popCC_ptrToPush_reg[0]
|
|
-------------------------------------------------------------------
|
|
required time 0.286
|
|
arrival time 0.514
|
|
-------------------------------------------------------------------
|
|
slack 0.800
|
|
|
|
Slack (MET) : 0.800ns (arrival time - required time)
|
|
Source: u_Axi_CDC/awFifo/bufferCC_12/buffers_1_reg/C
|
|
(rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Destination: u_Axi_CDC/wFifo/popCC_ptrToPush_reg[1]/CLR
|
|
(removal check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Path Group: **async_default**
|
|
Path Type: Removal (Min at Fast Process Corner)
|
|
Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns)
|
|
Data Path Delay: 1.055ns (logic 0.227ns (21.508%) route 0.828ns (78.492%))
|
|
Logic Levels: 1 (LUT1=1)
|
|
Clock Path Skew: 0.347ns (DCD - SCD - CPR)
|
|
Destination Clock Delay (DCD): -0.231ns
|
|
Source Clock Delay (SCD): -0.541ns
|
|
Clock Pessimism Removal (CPR): -0.037ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock sys_clk rise edge) 0.000 0.000 r
|
|
clock source latency -1.848 -1.848
|
|
propagated clock network latency
|
|
1.307 -0.541
|
|
SLICE_X7Y59 FDCE 0.000 -0.541 r u_Axi_CDC/awFifo/bufferCC_12/buffers_1_reg/C
|
|
SLICE_X7Y59 FDCE (Prop_fdce_C_Q) 0.128 -0.413 r u_Axi_CDC/awFifo/bufferCC_12/buffers_1_reg/Q
|
|
net (fo=1, routed) 0.283 -0.131 u_Axi_CDC/awFifo/bufferCC_12/buffers_1
|
|
SLICE_X7Y59 r u_Axi_CDC/awFifo/bufferCC_12/popCC_popPtr[2]_i_2/I0
|
|
SLICE_X7Y59 LUT1 (Prop_lut1_I0_O) 0.099 -0.032 f u_Axi_CDC/awFifo/bufferCC_12/popCC_popPtr[2]_i_2/O
|
|
net (fo=43, routed) 0.546 0.514 u_Axi_CDC/wFifo/buffers_0_reg[3]
|
|
SLICE_X5Y49 FDCE f u_Axi_CDC/wFifo/popCC_ptrToPush_reg[1]/CLR
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock sys_clk rise edge) 0.000 0.000 r
|
|
clock source latency -1.947 -1.947
|
|
propagated clock network latency
|
|
1.716 -0.231
|
|
clock pessimism 0.037 -0.194
|
|
SLICE_X5Y49 FDCE (Remov_fdce_C_CLR) -0.092 -0.286 u_Axi_CDC/wFifo/popCC_ptrToPush_reg[1]
|
|
-------------------------------------------------------------------
|
|
required time 0.286
|
|
arrival time 0.514
|
|
-------------------------------------------------------------------
|
|
slack 0.800
|
|
|
|
Slack (MET) : 0.800ns (arrival time - required time)
|
|
Source: u_Axi_CDC/awFifo/bufferCC_12/buffers_1_reg/C
|
|
(rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Destination: u_Axi_CDC/wFifo/popCC_ptrToPush_reg[2]/CLR
|
|
(removal check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Path Group: **async_default**
|
|
Path Type: Removal (Min at Fast Process Corner)
|
|
Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns)
|
|
Data Path Delay: 1.055ns (logic 0.227ns (21.508%) route 0.828ns (78.492%))
|
|
Logic Levels: 1 (LUT1=1)
|
|
Clock Path Skew: 0.347ns (DCD - SCD - CPR)
|
|
Destination Clock Delay (DCD): -0.231ns
|
|
Source Clock Delay (SCD): -0.541ns
|
|
Clock Pessimism Removal (CPR): -0.037ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock sys_clk rise edge) 0.000 0.000 r
|
|
clock source latency -1.848 -1.848
|
|
propagated clock network latency
|
|
1.307 -0.541
|
|
SLICE_X7Y59 FDCE 0.000 -0.541 r u_Axi_CDC/awFifo/bufferCC_12/buffers_1_reg/C
|
|
SLICE_X7Y59 FDCE (Prop_fdce_C_Q) 0.128 -0.413 r u_Axi_CDC/awFifo/bufferCC_12/buffers_1_reg/Q
|
|
net (fo=1, routed) 0.283 -0.131 u_Axi_CDC/awFifo/bufferCC_12/buffers_1
|
|
SLICE_X7Y59 r u_Axi_CDC/awFifo/bufferCC_12/popCC_popPtr[2]_i_2/I0
|
|
SLICE_X7Y59 LUT1 (Prop_lut1_I0_O) 0.099 -0.032 f u_Axi_CDC/awFifo/bufferCC_12/popCC_popPtr[2]_i_2/O
|
|
net (fo=43, routed) 0.546 0.514 u_Axi_CDC/wFifo/buffers_0_reg[3]
|
|
SLICE_X5Y49 FDCE f u_Axi_CDC/wFifo/popCC_ptrToPush_reg[2]/CLR
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock sys_clk rise edge) 0.000 0.000 r
|
|
clock source latency -1.947 -1.947
|
|
propagated clock network latency
|
|
1.716 -0.231
|
|
clock pessimism 0.037 -0.194
|
|
SLICE_X5Y49 FDCE (Remov_fdce_C_CLR) -0.092 -0.286 u_Axi_CDC/wFifo/popCC_ptrToPush_reg[2]
|
|
-------------------------------------------------------------------
|
|
required time 0.286
|
|
arrival time 0.514
|
|
-------------------------------------------------------------------
|
|
slack 0.800
|
|
|
|
Slack (MET) : 0.800ns (arrival time - required time)
|
|
Source: u_Axi_CDC/awFifo/bufferCC_12/buffers_1_reg/C
|
|
(rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Destination: u_Axi_CDC/wFifo/popCC_ptrToPush_reg[3]/CLR
|
|
(removal check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Path Group: **async_default**
|
|
Path Type: Removal (Min at Fast Process Corner)
|
|
Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns)
|
|
Data Path Delay: 1.055ns (logic 0.227ns (21.508%) route 0.828ns (78.492%))
|
|
Logic Levels: 1 (LUT1=1)
|
|
Clock Path Skew: 0.347ns (DCD - SCD - CPR)
|
|
Destination Clock Delay (DCD): -0.231ns
|
|
Source Clock Delay (SCD): -0.541ns
|
|
Clock Pessimism Removal (CPR): -0.037ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock sys_clk rise edge) 0.000 0.000 r
|
|
clock source latency -1.848 -1.848
|
|
propagated clock network latency
|
|
1.307 -0.541
|
|
SLICE_X7Y59 FDCE 0.000 -0.541 r u_Axi_CDC/awFifo/bufferCC_12/buffers_1_reg/C
|
|
SLICE_X7Y59 FDCE (Prop_fdce_C_Q) 0.128 -0.413 r u_Axi_CDC/awFifo/bufferCC_12/buffers_1_reg/Q
|
|
net (fo=1, routed) 0.283 -0.131 u_Axi_CDC/awFifo/bufferCC_12/buffers_1
|
|
SLICE_X7Y59 r u_Axi_CDC/awFifo/bufferCC_12/popCC_popPtr[2]_i_2/I0
|
|
SLICE_X7Y59 LUT1 (Prop_lut1_I0_O) 0.099 -0.032 f u_Axi_CDC/awFifo/bufferCC_12/popCC_popPtr[2]_i_2/O
|
|
net (fo=43, routed) 0.546 0.514 u_Axi_CDC/wFifo/buffers_0_reg[3]
|
|
SLICE_X5Y49 FDCE f u_Axi_CDC/wFifo/popCC_ptrToPush_reg[3]/CLR
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock sys_clk rise edge) 0.000 0.000 r
|
|
clock source latency -1.947 -1.947
|
|
propagated clock network latency
|
|
1.716 -0.231
|
|
clock pessimism 0.037 -0.194
|
|
SLICE_X5Y49 FDCE (Remov_fdce_C_CLR) -0.092 -0.286 u_Axi_CDC/wFifo/popCC_ptrToPush_reg[3]
|
|
-------------------------------------------------------------------
|
|
required time 0.286
|
|
arrival time 0.514
|
|
-------------------------------------------------------------------
|
|
slack 0.800
|
|
|
|
Slack (MET) : 0.805ns (arrival time - required time)
|
|
Source: u_Axi_CDC/awFifo/bufferCC_12/buffers_1_reg/C
|
|
(rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Destination: u_Axi_CDC/wFifo/pushToPopGray_buffercc/buffers_0_reg[0]/CLR
|
|
(removal check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Path Group: **async_default**
|
|
Path Type: Removal (Min at Fast Process Corner)
|
|
Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns)
|
|
Data Path Delay: 1.060ns (logic 0.227ns (21.419%) route 0.833ns (78.581%))
|
|
Logic Levels: 1 (LUT1=1)
|
|
Clock Path Skew: 0.347ns (DCD - SCD - CPR)
|
|
Destination Clock Delay (DCD): -0.231ns
|
|
Source Clock Delay (SCD): -0.541ns
|
|
Clock Pessimism Removal (CPR): -0.037ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock sys_clk rise edge) 0.000 0.000 r
|
|
clock source latency -1.848 -1.848
|
|
propagated clock network latency
|
|
1.307 -0.541
|
|
SLICE_X7Y59 FDCE 0.000 -0.541 r u_Axi_CDC/awFifo/bufferCC_12/buffers_1_reg/C
|
|
SLICE_X7Y59 FDCE (Prop_fdce_C_Q) 0.128 -0.413 r u_Axi_CDC/awFifo/bufferCC_12/buffers_1_reg/Q
|
|
net (fo=1, routed) 0.283 -0.131 u_Axi_CDC/awFifo/bufferCC_12/buffers_1
|
|
SLICE_X7Y59 r u_Axi_CDC/awFifo/bufferCC_12/popCC_popPtr[2]_i_2/I0
|
|
SLICE_X7Y59 LUT1 (Prop_lut1_I0_O) 0.099 -0.032 f u_Axi_CDC/awFifo/bufferCC_12/popCC_popPtr[2]_i_2/O
|
|
net (fo=43, routed) 0.550 0.518 u_Axi_CDC/wFifo/pushToPopGray_buffercc/buffers_0_reg[3]_0
|
|
SLICE_X4Y49 FDCE f u_Axi_CDC/wFifo/pushToPopGray_buffercc/buffers_0_reg[0]/CLR
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock sys_clk rise edge) 0.000 0.000 r
|
|
clock source latency -1.947 -1.947
|
|
propagated clock network latency
|
|
1.716 -0.231
|
|
clock pessimism 0.037 -0.194
|
|
SLICE_X4Y49 FDCE (Remov_fdce_C_CLR) -0.092 -0.286 u_Axi_CDC/wFifo/pushToPopGray_buffercc/buffers_0_reg[0]
|
|
-------------------------------------------------------------------
|
|
required time 0.286
|
|
arrival time 0.518
|
|
-------------------------------------------------------------------
|
|
slack 0.805
|
|
|
|
Slack (MET) : 0.805ns (arrival time - required time)
|
|
Source: u_Axi_CDC/awFifo/bufferCC_12/buffers_1_reg/C
|
|
(rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Destination: u_Axi_CDC/wFifo/pushToPopGray_buffercc/buffers_0_reg[1]/CLR
|
|
(removal check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Path Group: **async_default**
|
|
Path Type: Removal (Min at Fast Process Corner)
|
|
Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns)
|
|
Data Path Delay: 1.060ns (logic 0.227ns (21.419%) route 0.833ns (78.581%))
|
|
Logic Levels: 1 (LUT1=1)
|
|
Clock Path Skew: 0.347ns (DCD - SCD - CPR)
|
|
Destination Clock Delay (DCD): -0.231ns
|
|
Source Clock Delay (SCD): -0.541ns
|
|
Clock Pessimism Removal (CPR): -0.037ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock sys_clk rise edge) 0.000 0.000 r
|
|
clock source latency -1.848 -1.848
|
|
propagated clock network latency
|
|
1.307 -0.541
|
|
SLICE_X7Y59 FDCE 0.000 -0.541 r u_Axi_CDC/awFifo/bufferCC_12/buffers_1_reg/C
|
|
SLICE_X7Y59 FDCE (Prop_fdce_C_Q) 0.128 -0.413 r u_Axi_CDC/awFifo/bufferCC_12/buffers_1_reg/Q
|
|
net (fo=1, routed) 0.283 -0.131 u_Axi_CDC/awFifo/bufferCC_12/buffers_1
|
|
SLICE_X7Y59 r u_Axi_CDC/awFifo/bufferCC_12/popCC_popPtr[2]_i_2/I0
|
|
SLICE_X7Y59 LUT1 (Prop_lut1_I0_O) 0.099 -0.032 f u_Axi_CDC/awFifo/bufferCC_12/popCC_popPtr[2]_i_2/O
|
|
net (fo=43, routed) 0.550 0.518 u_Axi_CDC/wFifo/pushToPopGray_buffercc/buffers_0_reg[3]_0
|
|
SLICE_X4Y49 FDCE f u_Axi_CDC/wFifo/pushToPopGray_buffercc/buffers_0_reg[1]/CLR
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock sys_clk rise edge) 0.000 0.000 r
|
|
clock source latency -1.947 -1.947
|
|
propagated clock network latency
|
|
1.716 -0.231
|
|
clock pessimism 0.037 -0.194
|
|
SLICE_X4Y49 FDCE (Remov_fdce_C_CLR) -0.092 -0.286 u_Axi_CDC/wFifo/pushToPopGray_buffercc/buffers_0_reg[1]
|
|
-------------------------------------------------------------------
|
|
required time 0.286
|
|
arrival time 0.518
|
|
-------------------------------------------------------------------
|
|
slack 0.805
|
|
|
|
Slack (MET) : 0.805ns (arrival time - required time)
|
|
Source: u_Axi_CDC/awFifo/bufferCC_12/buffers_1_reg/C
|
|
(rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Destination: u_Axi_CDC/wFifo/pushToPopGray_buffercc/buffers_0_reg[2]/CLR
|
|
(removal check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Path Group: **async_default**
|
|
Path Type: Removal (Min at Fast Process Corner)
|
|
Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns)
|
|
Data Path Delay: 1.060ns (logic 0.227ns (21.419%) route 0.833ns (78.581%))
|
|
Logic Levels: 1 (LUT1=1)
|
|
Clock Path Skew: 0.347ns (DCD - SCD - CPR)
|
|
Destination Clock Delay (DCD): -0.231ns
|
|
Source Clock Delay (SCD): -0.541ns
|
|
Clock Pessimism Removal (CPR): -0.037ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock sys_clk rise edge) 0.000 0.000 r
|
|
clock source latency -1.848 -1.848
|
|
propagated clock network latency
|
|
1.307 -0.541
|
|
SLICE_X7Y59 FDCE 0.000 -0.541 r u_Axi_CDC/awFifo/bufferCC_12/buffers_1_reg/C
|
|
SLICE_X7Y59 FDCE (Prop_fdce_C_Q) 0.128 -0.413 r u_Axi_CDC/awFifo/bufferCC_12/buffers_1_reg/Q
|
|
net (fo=1, routed) 0.283 -0.131 u_Axi_CDC/awFifo/bufferCC_12/buffers_1
|
|
SLICE_X7Y59 r u_Axi_CDC/awFifo/bufferCC_12/popCC_popPtr[2]_i_2/I0
|
|
SLICE_X7Y59 LUT1 (Prop_lut1_I0_O) 0.099 -0.032 f u_Axi_CDC/awFifo/bufferCC_12/popCC_popPtr[2]_i_2/O
|
|
net (fo=43, routed) 0.550 0.518 u_Axi_CDC/wFifo/pushToPopGray_buffercc/buffers_0_reg[3]_0
|
|
SLICE_X4Y49 FDCE f u_Axi_CDC/wFifo/pushToPopGray_buffercc/buffers_0_reg[2]/CLR
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock sys_clk rise edge) 0.000 0.000 r
|
|
clock source latency -1.947 -1.947
|
|
propagated clock network latency
|
|
1.716 -0.231
|
|
clock pessimism 0.037 -0.194
|
|
SLICE_X4Y49 FDCE (Remov_fdce_C_CLR) -0.092 -0.286 u_Axi_CDC/wFifo/pushToPopGray_buffercc/buffers_0_reg[2]
|
|
-------------------------------------------------------------------
|
|
required time 0.286
|
|
arrival time 0.518
|
|
-------------------------------------------------------------------
|
|
slack 0.805
|
|
|
|
Slack (MET) : 0.805ns (arrival time - required time)
|
|
Source: u_Axi_CDC/awFifo/bufferCC_12/buffers_1_reg/C
|
|
(rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Destination: u_Axi_CDC/wFifo/pushToPopGray_buffercc/buffers_0_reg[3]/CLR
|
|
(removal check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Path Group: **async_default**
|
|
Path Type: Removal (Min at Fast Process Corner)
|
|
Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns)
|
|
Data Path Delay: 1.060ns (logic 0.227ns (21.419%) route 0.833ns (78.581%))
|
|
Logic Levels: 1 (LUT1=1)
|
|
Clock Path Skew: 0.347ns (DCD - SCD - CPR)
|
|
Destination Clock Delay (DCD): -0.231ns
|
|
Source Clock Delay (SCD): -0.541ns
|
|
Clock Pessimism Removal (CPR): -0.037ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock sys_clk rise edge) 0.000 0.000 r
|
|
clock source latency -1.848 -1.848
|
|
propagated clock network latency
|
|
1.307 -0.541
|
|
SLICE_X7Y59 FDCE 0.000 -0.541 r u_Axi_CDC/awFifo/bufferCC_12/buffers_1_reg/C
|
|
SLICE_X7Y59 FDCE (Prop_fdce_C_Q) 0.128 -0.413 r u_Axi_CDC/awFifo/bufferCC_12/buffers_1_reg/Q
|
|
net (fo=1, routed) 0.283 -0.131 u_Axi_CDC/awFifo/bufferCC_12/buffers_1
|
|
SLICE_X7Y59 r u_Axi_CDC/awFifo/bufferCC_12/popCC_popPtr[2]_i_2/I0
|
|
SLICE_X7Y59 LUT1 (Prop_lut1_I0_O) 0.099 -0.032 f u_Axi_CDC/awFifo/bufferCC_12/popCC_popPtr[2]_i_2/O
|
|
net (fo=43, routed) 0.550 0.518 u_Axi_CDC/wFifo/pushToPopGray_buffercc/buffers_0_reg[3]_0
|
|
SLICE_X4Y49 FDCE f u_Axi_CDC/wFifo/pushToPopGray_buffercc/buffers_0_reg[3]/CLR
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock sys_clk rise edge) 0.000 0.000 r
|
|
clock source latency -1.947 -1.947
|
|
propagated clock network latency
|
|
1.716 -0.231
|
|
clock pessimism 0.037 -0.194
|
|
SLICE_X4Y49 FDCE (Remov_fdce_C_CLR) -0.092 -0.286 u_Axi_CDC/wFifo/pushToPopGray_buffercc/buffers_0_reg[3]
|
|
-------------------------------------------------------------------
|
|
required time 0.286
|
|
arrival time 0.518
|
|
-------------------------------------------------------------------
|
|
slack 0.805
|
|
|
|
Slack (MET) : 0.805ns (arrival time - required time)
|
|
Source: u_Axi_CDC/awFifo/bufferCC_12/buffers_1_reg/C
|
|
(rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Destination: u_Axi_CDC/wFifo/pushToPopGray_buffercc/buffers_1_reg[0]/CLR
|
|
(removal check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Path Group: **async_default**
|
|
Path Type: Removal (Min at Fast Process Corner)
|
|
Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns)
|
|
Data Path Delay: 1.060ns (logic 0.227ns (21.419%) route 0.833ns (78.581%))
|
|
Logic Levels: 1 (LUT1=1)
|
|
Clock Path Skew: 0.347ns (DCD - SCD - CPR)
|
|
Destination Clock Delay (DCD): -0.231ns
|
|
Source Clock Delay (SCD): -0.541ns
|
|
Clock Pessimism Removal (CPR): -0.037ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock sys_clk rise edge) 0.000 0.000 r
|
|
clock source latency -1.848 -1.848
|
|
propagated clock network latency
|
|
1.307 -0.541
|
|
SLICE_X7Y59 FDCE 0.000 -0.541 r u_Axi_CDC/awFifo/bufferCC_12/buffers_1_reg/C
|
|
SLICE_X7Y59 FDCE (Prop_fdce_C_Q) 0.128 -0.413 r u_Axi_CDC/awFifo/bufferCC_12/buffers_1_reg/Q
|
|
net (fo=1, routed) 0.283 -0.131 u_Axi_CDC/awFifo/bufferCC_12/buffers_1
|
|
SLICE_X7Y59 r u_Axi_CDC/awFifo/bufferCC_12/popCC_popPtr[2]_i_2/I0
|
|
SLICE_X7Y59 LUT1 (Prop_lut1_I0_O) 0.099 -0.032 f u_Axi_CDC/awFifo/bufferCC_12/popCC_popPtr[2]_i_2/O
|
|
net (fo=43, routed) 0.550 0.518 u_Axi_CDC/wFifo/pushToPopGray_buffercc/buffers_0_reg[3]_0
|
|
SLICE_X4Y49 FDCE f u_Axi_CDC/wFifo/pushToPopGray_buffercc/buffers_1_reg[0]/CLR
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock sys_clk rise edge) 0.000 0.000 r
|
|
clock source latency -1.947 -1.947
|
|
propagated clock network latency
|
|
1.716 -0.231
|
|
clock pessimism 0.037 -0.194
|
|
SLICE_X4Y49 FDCE (Remov_fdce_C_CLR) -0.092 -0.286 u_Axi_CDC/wFifo/pushToPopGray_buffercc/buffers_1_reg[0]
|
|
-------------------------------------------------------------------
|
|
required time 0.286
|
|
arrival time 0.518
|
|
-------------------------------------------------------------------
|
|
slack 0.805
|
|
|
|
Slack (MET) : 0.805ns (arrival time - required time)
|
|
Source: u_Axi_CDC/awFifo/bufferCC_12/buffers_1_reg/C
|
|
(rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Destination: u_Axi_CDC/wFifo/pushToPopGray_buffercc/buffers_1_reg[1]/CLR
|
|
(removal check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Path Group: **async_default**
|
|
Path Type: Removal (Min at Fast Process Corner)
|
|
Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns)
|
|
Data Path Delay: 1.060ns (logic 0.227ns (21.419%) route 0.833ns (78.581%))
|
|
Logic Levels: 1 (LUT1=1)
|
|
Clock Path Skew: 0.347ns (DCD - SCD - CPR)
|
|
Destination Clock Delay (DCD): -0.231ns
|
|
Source Clock Delay (SCD): -0.541ns
|
|
Clock Pessimism Removal (CPR): -0.037ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock sys_clk rise edge) 0.000 0.000 r
|
|
clock source latency -1.848 -1.848
|
|
propagated clock network latency
|
|
1.307 -0.541
|
|
SLICE_X7Y59 FDCE 0.000 -0.541 r u_Axi_CDC/awFifo/bufferCC_12/buffers_1_reg/C
|
|
SLICE_X7Y59 FDCE (Prop_fdce_C_Q) 0.128 -0.413 r u_Axi_CDC/awFifo/bufferCC_12/buffers_1_reg/Q
|
|
net (fo=1, routed) 0.283 -0.131 u_Axi_CDC/awFifo/bufferCC_12/buffers_1
|
|
SLICE_X7Y59 r u_Axi_CDC/awFifo/bufferCC_12/popCC_popPtr[2]_i_2/I0
|
|
SLICE_X7Y59 LUT1 (Prop_lut1_I0_O) 0.099 -0.032 f u_Axi_CDC/awFifo/bufferCC_12/popCC_popPtr[2]_i_2/O
|
|
net (fo=43, routed) 0.550 0.518 u_Axi_CDC/wFifo/pushToPopGray_buffercc/buffers_0_reg[3]_0
|
|
SLICE_X4Y49 FDCE f u_Axi_CDC/wFifo/pushToPopGray_buffercc/buffers_1_reg[1]/CLR
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock sys_clk rise edge) 0.000 0.000 r
|
|
clock source latency -1.947 -1.947
|
|
propagated clock network latency
|
|
1.716 -0.231
|
|
clock pessimism 0.037 -0.194
|
|
SLICE_X4Y49 FDCE (Remov_fdce_C_CLR) -0.092 -0.286 u_Axi_CDC/wFifo/pushToPopGray_buffercc/buffers_1_reg[1]
|
|
-------------------------------------------------------------------
|
|
required time 0.286
|
|
arrival time 0.518
|
|
-------------------------------------------------------------------
|
|
slack 0.805
|
|
|
|
Slack (MET) : 0.805ns (arrival time - required time)
|
|
Source: u_Axi_CDC/awFifo/bufferCC_12/buffers_1_reg/C
|
|
(rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Destination: u_Axi_CDC/wFifo/pushToPopGray_buffercc/buffers_1_reg[2]/CLR
|
|
(removal check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Path Group: **async_default**
|
|
Path Type: Removal (Min at Fast Process Corner)
|
|
Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns)
|
|
Data Path Delay: 1.060ns (logic 0.227ns (21.419%) route 0.833ns (78.581%))
|
|
Logic Levels: 1 (LUT1=1)
|
|
Clock Path Skew: 0.347ns (DCD - SCD - CPR)
|
|
Destination Clock Delay (DCD): -0.231ns
|
|
Source Clock Delay (SCD): -0.541ns
|
|
Clock Pessimism Removal (CPR): -0.037ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock sys_clk rise edge) 0.000 0.000 r
|
|
clock source latency -1.848 -1.848
|
|
propagated clock network latency
|
|
1.307 -0.541
|
|
SLICE_X7Y59 FDCE 0.000 -0.541 r u_Axi_CDC/awFifo/bufferCC_12/buffers_1_reg/C
|
|
SLICE_X7Y59 FDCE (Prop_fdce_C_Q) 0.128 -0.413 r u_Axi_CDC/awFifo/bufferCC_12/buffers_1_reg/Q
|
|
net (fo=1, routed) 0.283 -0.131 u_Axi_CDC/awFifo/bufferCC_12/buffers_1
|
|
SLICE_X7Y59 r u_Axi_CDC/awFifo/bufferCC_12/popCC_popPtr[2]_i_2/I0
|
|
SLICE_X7Y59 LUT1 (Prop_lut1_I0_O) 0.099 -0.032 f u_Axi_CDC/awFifo/bufferCC_12/popCC_popPtr[2]_i_2/O
|
|
net (fo=43, routed) 0.550 0.518 u_Axi_CDC/wFifo/pushToPopGray_buffercc/buffers_0_reg[3]_0
|
|
SLICE_X4Y49 FDCE f u_Axi_CDC/wFifo/pushToPopGray_buffercc/buffers_1_reg[2]/CLR
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock sys_clk rise edge) 0.000 0.000 r
|
|
clock source latency -1.947 -1.947
|
|
propagated clock network latency
|
|
1.716 -0.231
|
|
clock pessimism 0.037 -0.194
|
|
SLICE_X4Y49 FDCE (Remov_fdce_C_CLR) -0.092 -0.286 u_Axi_CDC/wFifo/pushToPopGray_buffercc/buffers_1_reg[2]
|
|
-------------------------------------------------------------------
|
|
required time 0.286
|
|
arrival time 0.518
|
|
-------------------------------------------------------------------
|
|
slack 0.805
|
|
|
|
Slack (MET) : 0.805ns (arrival time - required time)
|
|
Source: u_Axi_CDC/awFifo/bufferCC_12/buffers_1_reg/C
|
|
(rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Destination: u_Axi_CDC/wFifo/pushToPopGray_buffercc/buffers_1_reg[3]/CLR
|
|
(removal check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Path Group: **async_default**
|
|
Path Type: Removal (Min at Fast Process Corner)
|
|
Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns)
|
|
Data Path Delay: 1.060ns (logic 0.227ns (21.419%) route 0.833ns (78.581%))
|
|
Logic Levels: 1 (LUT1=1)
|
|
Clock Path Skew: 0.347ns (DCD - SCD - CPR)
|
|
Destination Clock Delay (DCD): -0.231ns
|
|
Source Clock Delay (SCD): -0.541ns
|
|
Clock Pessimism Removal (CPR): -0.037ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock sys_clk rise edge) 0.000 0.000 r
|
|
clock source latency -1.848 -1.848
|
|
propagated clock network latency
|
|
1.307 -0.541
|
|
SLICE_X7Y59 FDCE 0.000 -0.541 r u_Axi_CDC/awFifo/bufferCC_12/buffers_1_reg/C
|
|
SLICE_X7Y59 FDCE (Prop_fdce_C_Q) 0.128 -0.413 r u_Axi_CDC/awFifo/bufferCC_12/buffers_1_reg/Q
|
|
net (fo=1, routed) 0.283 -0.131 u_Axi_CDC/awFifo/bufferCC_12/buffers_1
|
|
SLICE_X7Y59 r u_Axi_CDC/awFifo/bufferCC_12/popCC_popPtr[2]_i_2/I0
|
|
SLICE_X7Y59 LUT1 (Prop_lut1_I0_O) 0.099 -0.032 f u_Axi_CDC/awFifo/bufferCC_12/popCC_popPtr[2]_i_2/O
|
|
net (fo=43, routed) 0.550 0.518 u_Axi_CDC/wFifo/pushToPopGray_buffercc/buffers_0_reg[3]_0
|
|
SLICE_X4Y49 FDCE f u_Axi_CDC/wFifo/pushToPopGray_buffercc/buffers_1_reg[3]/CLR
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock sys_clk rise edge) 0.000 0.000 r
|
|
clock source latency -1.947 -1.947
|
|
propagated clock network latency
|
|
1.716 -0.231
|
|
clock pessimism 0.037 -0.194
|
|
SLICE_X4Y49 FDCE (Remov_fdce_C_CLR) -0.092 -0.286 u_Axi_CDC/wFifo/pushToPopGray_buffercc/buffers_1_reg[3]
|
|
-------------------------------------------------------------------
|
|
required time 0.286
|
|
arrival time 0.518
|
|
-------------------------------------------------------------------
|
|
slack 0.805
|
|
|
|
Slack (MET) : 0.824ns (arrival time - required time)
|
|
Source: pll_clk.u_rst_mlkem/delay_reg[1]/C
|
|
(rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns})
|
|
Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/stream_lane_reg[0]/CLR
|
|
(removal check against rising-edge clock mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns})
|
|
Path Group: **async_default**
|
|
Path Type: Removal (Min at Fast Process Corner)
|
|
Requirement: 0.000ns (mlkem_clk_clk_pll rise@0.000ns - mlkem_clk_clk_pll rise@0.000ns)
|
|
Data Path Delay: 0.765ns (logic 0.186ns (24.299%) route 0.579ns (75.701%))
|
|
Logic Levels: 1 (LUT1=1)
|
|
Clock Path Skew: 0.033ns (DCD - SCD - CPR)
|
|
Destination Clock Delay (DCD): -0.382ns
|
|
Source Clock Delay (SCD): -0.607ns
|
|
Clock Pessimism Removal (CPR): 0.192ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock mlkem_clk_clk_pll rise edge)
|
|
0.000 0.000 r
|
|
clock source latency -1.848 -1.848
|
|
propagated clock network latency
|
|
1.241 -0.607
|
|
SLICE_X118Y67 FDCE 0.000 -0.607 r pll_clk.u_rst_mlkem/delay_reg[1]/C
|
|
SLICE_X118Y67 FDCE (Prop_fdce_C_Q) 0.141 -0.466 r pll_clk.u_rst_mlkem/delay_reg[1]/Q
|
|
net (fo=4, routed) 0.297 -0.169 pll_clk.u_rst_mlkem/Q[0]
|
|
SLICE_X118Y67 r pll_clk.u_rst_mlkem/rdb_addr[11]_i_2/I0
|
|
SLICE_X118Y67 LUT1 (Prop_lut1_I0_O) 0.045 -0.124 f pll_clk.u_rst_mlkem/rdb_addr[11]_i_2/O
|
|
net (fo=1069, routed) 0.282 0.158 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/pre_addr_l_reg[2]_rep__1_0
|
|
SLICE_X121Y69 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/stream_lane_reg[0]/CLR
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock mlkem_clk_clk_pll rise edge)
|
|
0.000 0.000 r
|
|
clock source latency -1.947 -1.947
|
|
propagated clock network latency
|
|
1.565 -0.382
|
|
clock pessimism -0.192 -0.574
|
|
SLICE_X121Y69 FDCE (Remov_fdce_C_CLR) -0.092 -0.666 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/stream_lane_reg[0]
|
|
-------------------------------------------------------------------
|
|
required time 0.666
|
|
arrival time 0.158
|
|
-------------------------------------------------------------------
|
|
slack 0.824
|
|
|
|
Slack (MET) : 0.827ns (arrival time - required time)
|
|
Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/buffers_1_reg/C
|
|
(rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns})
|
|
Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/popCC_ptrToPush_reg[1]/CLR
|
|
(removal check against rising-edge clock mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns})
|
|
Path Group: **async_default**
|
|
Path Type: Removal (Min at Fast Process Corner)
|
|
Requirement: 0.000ns (mlkem_clk_clk_pll rise@0.000ns - mlkem_clk_clk_pll rise@0.000ns)
|
|
Data Path Delay: 0.764ns (logic 0.227ns (29.725%) route 0.537ns (70.275%))
|
|
Logic Levels: 1 (LUT1=1)
|
|
Clock Path Skew: 0.029ns (DCD - SCD - CPR)
|
|
Destination Clock Delay (DCD): -0.360ns
|
|
Source Clock Delay (SCD): -0.581ns
|
|
Clock Pessimism Removal (CPR): 0.192ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock mlkem_clk_clk_pll rise edge)
|
|
0.000 0.000 r
|
|
clock source latency -1.848 -1.848
|
|
propagated clock network latency
|
|
1.267 -0.581
|
|
SLICE_X25Y79 FDCE 0.000 -0.581 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/buffers_1_reg/C
|
|
SLICE_X25Y79 FDCE (Prop_fdce_C_Q) 0.128 -0.453 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/buffers_1_reg/Q
|
|
net (fo=1, routed) 0.139 -0.314 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/buffers_1
|
|
SLICE_X25Y79 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/popCC_popPtr[2]_i_2__1/I0
|
|
SLICE_X25Y79 LUT1 (Prop_lut1_I0_O) 0.099 -0.215 f u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/popCC_popPtr[2]_i_2__1/O
|
|
net (fo=43, routed) 0.397 0.182 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/buffers_1_reg
|
|
SLICE_X31Y74 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/popCC_ptrToPush_reg[1]/CLR
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock mlkem_clk_clk_pll rise edge)
|
|
0.000 0.000 r
|
|
clock source latency -1.947 -1.947
|
|
propagated clock network latency
|
|
1.587 -0.360
|
|
clock pessimism -0.192 -0.552
|
|
SLICE_X31Y74 FDCE (Remov_fdce_C_CLR) -0.092 -0.644 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/popCC_ptrToPush_reg[1]
|
|
-------------------------------------------------------------------
|
|
required time 0.644
|
|
arrival time 0.182
|
|
-------------------------------------------------------------------
|
|
slack 0.827
|
|
|
|
Slack (MET) : 0.827ns (arrival time - required time)
|
|
Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/buffers_1_reg/C
|
|
(rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns})
|
|
Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/popCC_ptrToPush_reg[2]/CLR
|
|
(removal check against rising-edge clock mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns})
|
|
Path Group: **async_default**
|
|
Path Type: Removal (Min at Fast Process Corner)
|
|
Requirement: 0.000ns (mlkem_clk_clk_pll rise@0.000ns - mlkem_clk_clk_pll rise@0.000ns)
|
|
Data Path Delay: 0.764ns (logic 0.227ns (29.725%) route 0.537ns (70.275%))
|
|
Logic Levels: 1 (LUT1=1)
|
|
Clock Path Skew: 0.029ns (DCD - SCD - CPR)
|
|
Destination Clock Delay (DCD): -0.360ns
|
|
Source Clock Delay (SCD): -0.581ns
|
|
Clock Pessimism Removal (CPR): 0.192ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock mlkem_clk_clk_pll rise edge)
|
|
0.000 0.000 r
|
|
clock source latency -1.848 -1.848
|
|
propagated clock network latency
|
|
1.267 -0.581
|
|
SLICE_X25Y79 FDCE 0.000 -0.581 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/buffers_1_reg/C
|
|
SLICE_X25Y79 FDCE (Prop_fdce_C_Q) 0.128 -0.453 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/buffers_1_reg/Q
|
|
net (fo=1, routed) 0.139 -0.314 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/buffers_1
|
|
SLICE_X25Y79 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/popCC_popPtr[2]_i_2__1/I0
|
|
SLICE_X25Y79 LUT1 (Prop_lut1_I0_O) 0.099 -0.215 f u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/popCC_popPtr[2]_i_2__1/O
|
|
net (fo=43, routed) 0.397 0.182 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/buffers_1_reg
|
|
SLICE_X31Y74 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/popCC_ptrToPush_reg[2]/CLR
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock mlkem_clk_clk_pll rise edge)
|
|
0.000 0.000 r
|
|
clock source latency -1.947 -1.947
|
|
propagated clock network latency
|
|
1.587 -0.360
|
|
clock pessimism -0.192 -0.552
|
|
SLICE_X31Y74 FDCE (Remov_fdce_C_CLR) -0.092 -0.644 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/popCC_ptrToPush_reg[2]
|
|
-------------------------------------------------------------------
|
|
required time 0.644
|
|
arrival time 0.182
|
|
-------------------------------------------------------------------
|
|
slack 0.827
|
|
|
|
Slack (MET) : 0.827ns (arrival time - required time)
|
|
Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/buffers_1_reg/C
|
|
(rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns})
|
|
Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/pushToPopGray_buffercc/buffers_0_reg[1]/CLR
|
|
(removal check against rising-edge clock mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns})
|
|
Path Group: **async_default**
|
|
Path Type: Removal (Min at Fast Process Corner)
|
|
Requirement: 0.000ns (mlkem_clk_clk_pll rise@0.000ns - mlkem_clk_clk_pll rise@0.000ns)
|
|
Data Path Delay: 0.764ns (logic 0.227ns (29.725%) route 0.537ns (70.275%))
|
|
Logic Levels: 1 (LUT1=1)
|
|
Clock Path Skew: 0.029ns (DCD - SCD - CPR)
|
|
Destination Clock Delay (DCD): -0.360ns
|
|
Source Clock Delay (SCD): -0.581ns
|
|
Clock Pessimism Removal (CPR): 0.192ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock mlkem_clk_clk_pll rise edge)
|
|
0.000 0.000 r
|
|
clock source latency -1.848 -1.848
|
|
propagated clock network latency
|
|
1.267 -0.581
|
|
SLICE_X25Y79 FDCE 0.000 -0.581 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/buffers_1_reg/C
|
|
SLICE_X25Y79 FDCE (Prop_fdce_C_Q) 0.128 -0.453 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/buffers_1_reg/Q
|
|
net (fo=1, routed) 0.139 -0.314 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/buffers_1
|
|
SLICE_X25Y79 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/popCC_popPtr[2]_i_2__1/I0
|
|
SLICE_X25Y79 LUT1 (Prop_lut1_I0_O) 0.099 -0.215 f u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/popCC_popPtr[2]_i_2__1/O
|
|
net (fo=43, routed) 0.397 0.182 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/pushToPopGray_buffercc/buffers_0_reg[2]_1
|
|
SLICE_X31Y74 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/pushToPopGray_buffercc/buffers_0_reg[1]/CLR
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock mlkem_clk_clk_pll rise edge)
|
|
0.000 0.000 r
|
|
clock source latency -1.947 -1.947
|
|
propagated clock network latency
|
|
1.587 -0.360
|
|
clock pessimism -0.192 -0.552
|
|
SLICE_X31Y74 FDCE (Remov_fdce_C_CLR) -0.092 -0.644 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/pushToPopGray_buffercc/buffers_0_reg[1]
|
|
-------------------------------------------------------------------
|
|
required time 0.644
|
|
arrival time 0.182
|
|
-------------------------------------------------------------------
|
|
slack 0.827
|
|
|
|
Slack (MET) : 0.827ns (arrival time - required time)
|
|
Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/buffers_1_reg/C
|
|
(rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns})
|
|
Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/pushToPopGray_buffercc/buffers_0_reg[2]/CLR
|
|
(removal check against rising-edge clock mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns})
|
|
Path Group: **async_default**
|
|
Path Type: Removal (Min at Fast Process Corner)
|
|
Requirement: 0.000ns (mlkem_clk_clk_pll rise@0.000ns - mlkem_clk_clk_pll rise@0.000ns)
|
|
Data Path Delay: 0.764ns (logic 0.227ns (29.725%) route 0.537ns (70.275%))
|
|
Logic Levels: 1 (LUT1=1)
|
|
Clock Path Skew: 0.029ns (DCD - SCD - CPR)
|
|
Destination Clock Delay (DCD): -0.360ns
|
|
Source Clock Delay (SCD): -0.581ns
|
|
Clock Pessimism Removal (CPR): 0.192ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock mlkem_clk_clk_pll rise edge)
|
|
0.000 0.000 r
|
|
clock source latency -1.848 -1.848
|
|
propagated clock network latency
|
|
1.267 -0.581
|
|
SLICE_X25Y79 FDCE 0.000 -0.581 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/buffers_1_reg/C
|
|
SLICE_X25Y79 FDCE (Prop_fdce_C_Q) 0.128 -0.453 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/buffers_1_reg/Q
|
|
net (fo=1, routed) 0.139 -0.314 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/buffers_1
|
|
SLICE_X25Y79 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/popCC_popPtr[2]_i_2__1/I0
|
|
SLICE_X25Y79 LUT1 (Prop_lut1_I0_O) 0.099 -0.215 f u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/popCC_popPtr[2]_i_2__1/O
|
|
net (fo=43, routed) 0.397 0.182 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/pushToPopGray_buffercc/buffers_0_reg[2]_1
|
|
SLICE_X31Y74 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/pushToPopGray_buffercc/buffers_0_reg[2]/CLR
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock mlkem_clk_clk_pll rise edge)
|
|
0.000 0.000 r
|
|
clock source latency -1.947 -1.947
|
|
propagated clock network latency
|
|
1.587 -0.360
|
|
clock pessimism -0.192 -0.552
|
|
SLICE_X31Y74 FDCE (Remov_fdce_C_CLR) -0.092 -0.644 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/pushToPopGray_buffercc/buffers_0_reg[2]
|
|
-------------------------------------------------------------------
|
|
required time 0.644
|
|
arrival time 0.182
|
|
-------------------------------------------------------------------
|
|
slack 0.827
|
|
|
|
Slack (MET) : 0.827ns (arrival time - required time)
|
|
Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/buffers_1_reg/C
|
|
(rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns})
|
|
Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/pushToPopGray_buffercc/buffers_1_reg[1]/CLR
|
|
(removal check against rising-edge clock mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns})
|
|
Path Group: **async_default**
|
|
Path Type: Removal (Min at Fast Process Corner)
|
|
Requirement: 0.000ns (mlkem_clk_clk_pll rise@0.000ns - mlkem_clk_clk_pll rise@0.000ns)
|
|
Data Path Delay: 0.764ns (logic 0.227ns (29.725%) route 0.537ns (70.275%))
|
|
Logic Levels: 1 (LUT1=1)
|
|
Clock Path Skew: 0.029ns (DCD - SCD - CPR)
|
|
Destination Clock Delay (DCD): -0.360ns
|
|
Source Clock Delay (SCD): -0.581ns
|
|
Clock Pessimism Removal (CPR): 0.192ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock mlkem_clk_clk_pll rise edge)
|
|
0.000 0.000 r
|
|
clock source latency -1.848 -1.848
|
|
propagated clock network latency
|
|
1.267 -0.581
|
|
SLICE_X25Y79 FDCE 0.000 -0.581 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/buffers_1_reg/C
|
|
SLICE_X25Y79 FDCE (Prop_fdce_C_Q) 0.128 -0.453 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/buffers_1_reg/Q
|
|
net (fo=1, routed) 0.139 -0.314 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/buffers_1
|
|
SLICE_X25Y79 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/popCC_popPtr[2]_i_2__1/I0
|
|
SLICE_X25Y79 LUT1 (Prop_lut1_I0_O) 0.099 -0.215 f u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/popCC_popPtr[2]_i_2__1/O
|
|
net (fo=43, routed) 0.397 0.182 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/pushToPopGray_buffercc/buffers_0_reg[2]_1
|
|
SLICE_X31Y74 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/pushToPopGray_buffercc/buffers_1_reg[1]/CLR
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock mlkem_clk_clk_pll rise edge)
|
|
0.000 0.000 r
|
|
clock source latency -1.947 -1.947
|
|
propagated clock network latency
|
|
1.587 -0.360
|
|
clock pessimism -0.192 -0.552
|
|
SLICE_X31Y74 FDCE (Remov_fdce_C_CLR) -0.092 -0.644 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/pushToPopGray_buffercc/buffers_1_reg[1]
|
|
-------------------------------------------------------------------
|
|
required time 0.644
|
|
arrival time 0.182
|
|
-------------------------------------------------------------------
|
|
slack 0.827
|
|
|
|
Slack (MET) : 0.827ns (arrival time - required time)
|
|
Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/buffers_1_reg/C
|
|
(rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns})
|
|
Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/pushToPopGray_buffercc/buffers_1_reg[2]/CLR
|
|
(removal check against rising-edge clock mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns})
|
|
Path Group: **async_default**
|
|
Path Type: Removal (Min at Fast Process Corner)
|
|
Requirement: 0.000ns (mlkem_clk_clk_pll rise@0.000ns - mlkem_clk_clk_pll rise@0.000ns)
|
|
Data Path Delay: 0.764ns (logic 0.227ns (29.725%) route 0.537ns (70.275%))
|
|
Logic Levels: 1 (LUT1=1)
|
|
Clock Path Skew: 0.029ns (DCD - SCD - CPR)
|
|
Destination Clock Delay (DCD): -0.360ns
|
|
Source Clock Delay (SCD): -0.581ns
|
|
Clock Pessimism Removal (CPR): 0.192ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock mlkem_clk_clk_pll rise edge)
|
|
0.000 0.000 r
|
|
clock source latency -1.848 -1.848
|
|
propagated clock network latency
|
|
1.267 -0.581
|
|
SLICE_X25Y79 FDCE 0.000 -0.581 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/buffers_1_reg/C
|
|
SLICE_X25Y79 FDCE (Prop_fdce_C_Q) 0.128 -0.453 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/buffers_1_reg/Q
|
|
net (fo=1, routed) 0.139 -0.314 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/buffers_1
|
|
SLICE_X25Y79 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/popCC_popPtr[2]_i_2__1/I0
|
|
SLICE_X25Y79 LUT1 (Prop_lut1_I0_O) 0.099 -0.215 f u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/popCC_popPtr[2]_i_2__1/O
|
|
net (fo=43, routed) 0.397 0.182 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/pushToPopGray_buffercc/buffers_0_reg[2]_1
|
|
SLICE_X31Y74 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/pushToPopGray_buffercc/buffers_1_reg[2]/CLR
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock mlkem_clk_clk_pll rise edge)
|
|
0.000 0.000 r
|
|
clock source latency -1.947 -1.947
|
|
propagated clock network latency
|
|
1.587 -0.360
|
|
clock pessimism -0.192 -0.552
|
|
SLICE_X31Y74 FDCE (Remov_fdce_C_CLR) -0.092 -0.644 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/pushToPopGray_buffercc/buffers_1_reg[2]
|
|
-------------------------------------------------------------------
|
|
required time 0.644
|
|
arrival time 0.182
|
|
-------------------------------------------------------------------
|
|
slack 0.827
|
|
|
|
Slack (MET) : 0.859ns (arrival time - required time)
|
|
Source: u_Axi_CDC/awFifo/bufferCC_12/buffers_1_reg/C
|
|
(rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Destination: u_Axi_CDC/wFifo/popCC_popPtr_reg[0]/CLR
|
|
(removal check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Path Group: **async_default**
|
|
Path Type: Removal (Min at Fast Process Corner)
|
|
Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns)
|
|
Data Path Delay: 1.114ns (logic 0.227ns (20.373%) route 0.887ns (79.627%))
|
|
Logic Levels: 1 (LUT1=1)
|
|
Clock Path Skew: 0.347ns (DCD - SCD - CPR)
|
|
Destination Clock Delay (DCD): -0.231ns
|
|
Source Clock Delay (SCD): -0.541ns
|
|
Clock Pessimism Removal (CPR): -0.037ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock sys_clk rise edge) 0.000 0.000 r
|
|
clock source latency -1.848 -1.848
|
|
propagated clock network latency
|
|
1.307 -0.541
|
|
SLICE_X7Y59 FDCE 0.000 -0.541 r u_Axi_CDC/awFifo/bufferCC_12/buffers_1_reg/C
|
|
SLICE_X7Y59 FDCE (Prop_fdce_C_Q) 0.128 -0.413 r u_Axi_CDC/awFifo/bufferCC_12/buffers_1_reg/Q
|
|
net (fo=1, routed) 0.283 -0.131 u_Axi_CDC/awFifo/bufferCC_12/buffers_1
|
|
SLICE_X7Y59 r u_Axi_CDC/awFifo/bufferCC_12/popCC_popPtr[2]_i_2/I0
|
|
SLICE_X7Y59 LUT1 (Prop_lut1_I0_O) 0.099 -0.032 f u_Axi_CDC/awFifo/bufferCC_12/popCC_popPtr[2]_i_2/O
|
|
net (fo=43, routed) 0.605 0.573 u_Axi_CDC/wFifo/buffers_0_reg[3]
|
|
SLICE_X4Y48 FDCE f u_Axi_CDC/wFifo/popCC_popPtr_reg[0]/CLR
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock sys_clk rise edge) 0.000 0.000 r
|
|
clock source latency -1.947 -1.947
|
|
propagated clock network latency
|
|
1.716 -0.231
|
|
clock pessimism 0.037 -0.194
|
|
SLICE_X4Y48 FDCE (Remov_fdce_C_CLR) -0.092 -0.286 u_Axi_CDC/wFifo/popCC_popPtr_reg[0]
|
|
-------------------------------------------------------------------
|
|
required time 0.286
|
|
arrival time 0.573
|
|
-------------------------------------------------------------------
|
|
slack 0.859
|
|
|
|
Slack (MET) : 0.859ns (arrival time - required time)
|
|
Source: u_Axi_CDC/awFifo/bufferCC_12/buffers_1_reg/C
|
|
(rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Destination: u_Axi_CDC/wFifo/popCC_popPtr_reg[1]/CLR
|
|
(removal check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Path Group: **async_default**
|
|
Path Type: Removal (Min at Fast Process Corner)
|
|
Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns)
|
|
Data Path Delay: 1.114ns (logic 0.227ns (20.373%) route 0.887ns (79.627%))
|
|
Logic Levels: 1 (LUT1=1)
|
|
Clock Path Skew: 0.347ns (DCD - SCD - CPR)
|
|
Destination Clock Delay (DCD): -0.231ns
|
|
Source Clock Delay (SCD): -0.541ns
|
|
Clock Pessimism Removal (CPR): -0.037ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock sys_clk rise edge) 0.000 0.000 r
|
|
clock source latency -1.848 -1.848
|
|
propagated clock network latency
|
|
1.307 -0.541
|
|
SLICE_X7Y59 FDCE 0.000 -0.541 r u_Axi_CDC/awFifo/bufferCC_12/buffers_1_reg/C
|
|
SLICE_X7Y59 FDCE (Prop_fdce_C_Q) 0.128 -0.413 r u_Axi_CDC/awFifo/bufferCC_12/buffers_1_reg/Q
|
|
net (fo=1, routed) 0.283 -0.131 u_Axi_CDC/awFifo/bufferCC_12/buffers_1
|
|
SLICE_X7Y59 r u_Axi_CDC/awFifo/bufferCC_12/popCC_popPtr[2]_i_2/I0
|
|
SLICE_X7Y59 LUT1 (Prop_lut1_I0_O) 0.099 -0.032 f u_Axi_CDC/awFifo/bufferCC_12/popCC_popPtr[2]_i_2/O
|
|
net (fo=43, routed) 0.605 0.573 u_Axi_CDC/wFifo/buffers_0_reg[3]
|
|
SLICE_X4Y48 FDCE f u_Axi_CDC/wFifo/popCC_popPtr_reg[1]/CLR
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock sys_clk rise edge) 0.000 0.000 r
|
|
clock source latency -1.947 -1.947
|
|
propagated clock network latency
|
|
1.716 -0.231
|
|
clock pessimism 0.037 -0.194
|
|
SLICE_X4Y48 FDCE (Remov_fdce_C_CLR) -0.092 -0.286 u_Axi_CDC/wFifo/popCC_popPtr_reg[1]
|
|
-------------------------------------------------------------------
|
|
required time 0.286
|
|
arrival time 0.573
|
|
-------------------------------------------------------------------
|
|
slack 0.859
|
|
|
|
Slack (MET) : 0.859ns (arrival time - required time)
|
|
Source: u_Axi_CDC/awFifo/bufferCC_12/buffers_1_reg/C
|
|
(rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Destination: u_Axi_CDC/wFifo/popCC_popPtr_reg[2]/CLR
|
|
(removal check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Path Group: **async_default**
|
|
Path Type: Removal (Min at Fast Process Corner)
|
|
Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns)
|
|
Data Path Delay: 1.114ns (logic 0.227ns (20.373%) route 0.887ns (79.627%))
|
|
Logic Levels: 1 (LUT1=1)
|
|
Clock Path Skew: 0.347ns (DCD - SCD - CPR)
|
|
Destination Clock Delay (DCD): -0.231ns
|
|
Source Clock Delay (SCD): -0.541ns
|
|
Clock Pessimism Removal (CPR): -0.037ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock sys_clk rise edge) 0.000 0.000 r
|
|
clock source latency -1.848 -1.848
|
|
propagated clock network latency
|
|
1.307 -0.541
|
|
SLICE_X7Y59 FDCE 0.000 -0.541 r u_Axi_CDC/awFifo/bufferCC_12/buffers_1_reg/C
|
|
SLICE_X7Y59 FDCE (Prop_fdce_C_Q) 0.128 -0.413 r u_Axi_CDC/awFifo/bufferCC_12/buffers_1_reg/Q
|
|
net (fo=1, routed) 0.283 -0.131 u_Axi_CDC/awFifo/bufferCC_12/buffers_1
|
|
SLICE_X7Y59 r u_Axi_CDC/awFifo/bufferCC_12/popCC_popPtr[2]_i_2/I0
|
|
SLICE_X7Y59 LUT1 (Prop_lut1_I0_O) 0.099 -0.032 f u_Axi_CDC/awFifo/bufferCC_12/popCC_popPtr[2]_i_2/O
|
|
net (fo=43, routed) 0.605 0.573 u_Axi_CDC/wFifo/buffers_0_reg[3]
|
|
SLICE_X4Y48 FDCE f u_Axi_CDC/wFifo/popCC_popPtr_reg[2]/CLR
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock sys_clk rise edge) 0.000 0.000 r
|
|
clock source latency -1.947 -1.947
|
|
propagated clock network latency
|
|
1.716 -0.231
|
|
clock pessimism 0.037 -0.194
|
|
SLICE_X4Y48 FDCE (Remov_fdce_C_CLR) -0.092 -0.286 u_Axi_CDC/wFifo/popCC_popPtr_reg[2]
|
|
-------------------------------------------------------------------
|
|
required time 0.286
|
|
arrival time 0.573
|
|
-------------------------------------------------------------------
|
|
slack 0.859
|
|
|
|
Slack (MET) : 0.859ns (arrival time - required time)
|
|
Source: u_Axi_CDC/awFifo/bufferCC_12/buffers_1_reg/C
|
|
(rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Destination: u_Axi_CDC/wFifo/popCC_popPtr_reg[3]/CLR
|
|
(removal check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns})
|
|
Path Group: **async_default**
|
|
Path Type: Removal (Min at Fast Process Corner)
|
|
Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns)
|
|
Data Path Delay: 1.114ns (logic 0.227ns (20.373%) route 0.887ns (79.627%))
|
|
Logic Levels: 1 (LUT1=1)
|
|
Clock Path Skew: 0.347ns (DCD - SCD - CPR)
|
|
Destination Clock Delay (DCD): -0.231ns
|
|
Source Clock Delay (SCD): -0.541ns
|
|
Clock Pessimism Removal (CPR): -0.037ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock sys_clk rise edge) 0.000 0.000 r
|
|
clock source latency -1.848 -1.848
|
|
propagated clock network latency
|
|
1.307 -0.541
|
|
SLICE_X7Y59 FDCE 0.000 -0.541 r u_Axi_CDC/awFifo/bufferCC_12/buffers_1_reg/C
|
|
SLICE_X7Y59 FDCE (Prop_fdce_C_Q) 0.128 -0.413 r u_Axi_CDC/awFifo/bufferCC_12/buffers_1_reg/Q
|
|
net (fo=1, routed) 0.283 -0.131 u_Axi_CDC/awFifo/bufferCC_12/buffers_1
|
|
SLICE_X7Y59 r u_Axi_CDC/awFifo/bufferCC_12/popCC_popPtr[2]_i_2/I0
|
|
SLICE_X7Y59 LUT1 (Prop_lut1_I0_O) 0.099 -0.032 f u_Axi_CDC/awFifo/bufferCC_12/popCC_popPtr[2]_i_2/O
|
|
net (fo=43, routed) 0.605 0.573 u_Axi_CDC/wFifo/buffers_0_reg[3]
|
|
SLICE_X4Y48 FDCE f u_Axi_CDC/wFifo/popCC_popPtr_reg[3]/CLR
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock sys_clk rise edge) 0.000 0.000 r
|
|
clock source latency -1.947 -1.947
|
|
propagated clock network latency
|
|
1.716 -0.231
|
|
clock pessimism 0.037 -0.194
|
|
SLICE_X4Y48 FDCE (Remov_fdce_C_CLR) -0.092 -0.286 u_Axi_CDC/wFifo/popCC_popPtr_reg[3]
|
|
-------------------------------------------------------------------
|
|
required time 0.286
|
|
arrival time 0.573
|
|
-------------------------------------------------------------------
|
|
slack 0.859
|
|
|
|
Slack (MET) : 0.860ns (arrival time - required time)
|
|
Source: pll_clk.u_rst_mlkem/delay_reg[1]/C
|
|
(rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns})
|
|
Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/start_sync_reg[0]/CLR
|
|
(removal check against rising-edge clock mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns})
|
|
Path Group: **async_default**
|
|
Path Type: Removal (Min at Fast Process Corner)
|
|
Requirement: 0.000ns (mlkem_clk_clk_pll rise@0.000ns - mlkem_clk_clk_pll rise@0.000ns)
|
|
Data Path Delay: 0.779ns (logic 0.186ns (23.870%) route 0.593ns (76.130%))
|
|
Logic Levels: 1 (LUT1=1)
|
|
Clock Path Skew: 0.011ns (DCD - SCD - CPR)
|
|
Destination Clock Delay (DCD): -0.383ns
|
|
Source Clock Delay (SCD): -0.607ns
|
|
Clock Pessimism Removal (CPR): 0.213ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock mlkem_clk_clk_pll rise edge)
|
|
0.000 0.000 r
|
|
clock source latency -1.848 -1.848
|
|
propagated clock network latency
|
|
1.241 -0.607
|
|
SLICE_X118Y67 FDCE 0.000 -0.607 r pll_clk.u_rst_mlkem/delay_reg[1]/C
|
|
SLICE_X118Y67 FDCE (Prop_fdce_C_Q) 0.141 -0.466 r pll_clk.u_rst_mlkem/delay_reg[1]/Q
|
|
net (fo=4, routed) 0.297 -0.169 pll_clk.u_rst_mlkem/Q[0]
|
|
SLICE_X118Y67 r pll_clk.u_rst_mlkem/rdb_addr[11]_i_2/I0
|
|
SLICE_X118Y67 LUT1 (Prop_lut1_I0_O) 0.045 -0.124 f pll_clk.u_rst_mlkem/rdb_addr[11]_i_2/O
|
|
net (fo=1069, routed) 0.296 0.172 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/pre_addr_l_reg[2]_rep__1_0
|
|
SLICE_X118Y70 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/start_sync_reg[0]/CLR
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock mlkem_clk_clk_pll rise edge)
|
|
0.000 0.000 r
|
|
clock source latency -1.947 -1.947
|
|
propagated clock network latency
|
|
1.564 -0.383
|
|
clock pessimism -0.213 -0.596
|
|
SLICE_X118Y70 FDCE (Remov_fdce_C_CLR) -0.092 -0.688 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/start_sync_reg[0]
|
|
-------------------------------------------------------------------
|
|
required time 0.688
|
|
arrival time 0.172
|
|
-------------------------------------------------------------------
|
|
slack 0.860
|
|
|
|
Slack (MET) : 0.860ns (arrival time - required time)
|
|
Source: pll_clk.u_rst_mlkem/delay_reg[1]/C
|
|
(rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns})
|
|
Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/start_tg_reg/CLR
|
|
(removal check against rising-edge clock mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns})
|
|
Path Group: **async_default**
|
|
Path Type: Removal (Min at Fast Process Corner)
|
|
Requirement: 0.000ns (mlkem_clk_clk_pll rise@0.000ns - mlkem_clk_clk_pll rise@0.000ns)
|
|
Data Path Delay: 0.779ns (logic 0.186ns (23.870%) route 0.593ns (76.130%))
|
|
Logic Levels: 1 (LUT1=1)
|
|
Clock Path Skew: 0.011ns (DCD - SCD - CPR)
|
|
Destination Clock Delay (DCD): -0.383ns
|
|
Source Clock Delay (SCD): -0.607ns
|
|
Clock Pessimism Removal (CPR): 0.213ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock mlkem_clk_clk_pll rise edge)
|
|
0.000 0.000 r
|
|
clock source latency -1.848 -1.848
|
|
propagated clock network latency
|
|
1.241 -0.607
|
|
SLICE_X118Y67 FDCE 0.000 -0.607 r pll_clk.u_rst_mlkem/delay_reg[1]/C
|
|
SLICE_X118Y67 FDCE (Prop_fdce_C_Q) 0.141 -0.466 r pll_clk.u_rst_mlkem/delay_reg[1]/Q
|
|
net (fo=4, routed) 0.297 -0.169 pll_clk.u_rst_mlkem/Q[0]
|
|
SLICE_X118Y67 r pll_clk.u_rst_mlkem/rdb_addr[11]_i_2/I0
|
|
SLICE_X118Y67 LUT1 (Prop_lut1_I0_O) 0.045 -0.124 f pll_clk.u_rst_mlkem/rdb_addr[11]_i_2/O
|
|
net (fo=1069, routed) 0.296 0.172 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/pre_addr_l_reg[2]_rep__1_0
|
|
SLICE_X118Y70 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/start_tg_reg/CLR
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock mlkem_clk_clk_pll rise edge)
|
|
0.000 0.000 r
|
|
clock source latency -1.947 -1.947
|
|
propagated clock network latency
|
|
1.564 -0.383
|
|
clock pessimism -0.213 -0.596
|
|
SLICE_X118Y70 FDCE (Remov_fdce_C_CLR) -0.092 -0.688 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/start_tg_reg
|
|
-------------------------------------------------------------------
|
|
required time 0.688
|
|
arrival time 0.172
|
|
-------------------------------------------------------------------
|
|
slack 0.860
|
|
|
|
Slack (MET) : 0.868ns (arrival time - required time)
|
|
Source: pll_clk.u_rst_mlkem/delay_reg[1]/C
|
|
(rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns})
|
|
Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/stream_wstrb_reg[0]/CLR
|
|
(removal check against rising-edge clock mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns})
|
|
Path Group: **async_default**
|
|
Path Type: Removal (Min at Fast Process Corner)
|
|
Requirement: 0.000ns (mlkem_clk_clk_pll rise@0.000ns - mlkem_clk_clk_pll rise@0.000ns)
|
|
Data Path Delay: 0.809ns (logic 0.186ns (22.998%) route 0.623ns (77.002%))
|
|
Logic Levels: 1 (LUT1=1)
|
|
Clock Path Skew: 0.033ns (DCD - SCD - CPR)
|
|
Destination Clock Delay (DCD): -0.382ns
|
|
Source Clock Delay (SCD): -0.607ns
|
|
Clock Pessimism Removal (CPR): 0.192ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock mlkem_clk_clk_pll rise edge)
|
|
0.000 0.000 r
|
|
clock source latency -1.848 -1.848
|
|
propagated clock network latency
|
|
1.241 -0.607
|
|
SLICE_X118Y67 FDCE 0.000 -0.607 r pll_clk.u_rst_mlkem/delay_reg[1]/C
|
|
SLICE_X118Y67 FDCE (Prop_fdce_C_Q) 0.141 -0.466 r pll_clk.u_rst_mlkem/delay_reg[1]/Q
|
|
net (fo=4, routed) 0.297 -0.169 pll_clk.u_rst_mlkem/Q[0]
|
|
SLICE_X118Y67 r pll_clk.u_rst_mlkem/rdb_addr[11]_i_2/I0
|
|
SLICE_X118Y67 LUT1 (Prop_lut1_I0_O) 0.045 -0.124 f pll_clk.u_rst_mlkem/rdb_addr[11]_i_2/O
|
|
net (fo=1069, routed) 0.325 0.201 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/pre_addr_l_reg[2]_rep__1_0
|
|
SLICE_X122Y69 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/stream_wstrb_reg[0]/CLR
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock mlkem_clk_clk_pll rise edge)
|
|
0.000 0.000 r
|
|
clock source latency -1.947 -1.947
|
|
propagated clock network latency
|
|
1.565 -0.382
|
|
clock pessimism -0.192 -0.574
|
|
SLICE_X122Y69 FDCE (Remov_fdce_C_CLR) -0.092 -0.666 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/stream_wstrb_reg[0]
|
|
-------------------------------------------------------------------
|
|
required time 0.666
|
|
arrival time 0.201
|
|
-------------------------------------------------------------------
|
|
slack 0.868
|
|
|
|
Slack (MET) : 0.868ns (arrival time - required time)
|
|
Source: pll_clk.u_rst_mlkem/delay_reg[1]/C
|
|
(rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns})
|
|
Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/stream_wstrb_reg[1]/CLR
|
|
(removal check against rising-edge clock mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns})
|
|
Path Group: **async_default**
|
|
Path Type: Removal (Min at Fast Process Corner)
|
|
Requirement: 0.000ns (mlkem_clk_clk_pll rise@0.000ns - mlkem_clk_clk_pll rise@0.000ns)
|
|
Data Path Delay: 0.809ns (logic 0.186ns (22.998%) route 0.623ns (77.002%))
|
|
Logic Levels: 1 (LUT1=1)
|
|
Clock Path Skew: 0.033ns (DCD - SCD - CPR)
|
|
Destination Clock Delay (DCD): -0.382ns
|
|
Source Clock Delay (SCD): -0.607ns
|
|
Clock Pessimism Removal (CPR): 0.192ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock mlkem_clk_clk_pll rise edge)
|
|
0.000 0.000 r
|
|
clock source latency -1.848 -1.848
|
|
propagated clock network latency
|
|
1.241 -0.607
|
|
SLICE_X118Y67 FDCE 0.000 -0.607 r pll_clk.u_rst_mlkem/delay_reg[1]/C
|
|
SLICE_X118Y67 FDCE (Prop_fdce_C_Q) 0.141 -0.466 r pll_clk.u_rst_mlkem/delay_reg[1]/Q
|
|
net (fo=4, routed) 0.297 -0.169 pll_clk.u_rst_mlkem/Q[0]
|
|
SLICE_X118Y67 r pll_clk.u_rst_mlkem/rdb_addr[11]_i_2/I0
|
|
SLICE_X118Y67 LUT1 (Prop_lut1_I0_O) 0.045 -0.124 f pll_clk.u_rst_mlkem/rdb_addr[11]_i_2/O
|
|
net (fo=1069, routed) 0.325 0.201 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/pre_addr_l_reg[2]_rep__1_0
|
|
SLICE_X122Y69 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/stream_wstrb_reg[1]/CLR
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock mlkem_clk_clk_pll rise edge)
|
|
0.000 0.000 r
|
|
clock source latency -1.947 -1.947
|
|
propagated clock network latency
|
|
1.565 -0.382
|
|
clock pessimism -0.192 -0.574
|
|
SLICE_X122Y69 FDCE (Remov_fdce_C_CLR) -0.092 -0.666 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/stream_wstrb_reg[1]
|
|
-------------------------------------------------------------------
|
|
required time 0.666
|
|
arrival time 0.201
|
|
-------------------------------------------------------------------
|
|
slack 0.868
|
|
|
|
Slack (MET) : 0.868ns (arrival time - required time)
|
|
Source: pll_clk.u_rst_mlkem/delay_reg[1]/C
|
|
(rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns})
|
|
Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/stream_wstrb_reg[2]/CLR
|
|
(removal check against rising-edge clock mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns})
|
|
Path Group: **async_default**
|
|
Path Type: Removal (Min at Fast Process Corner)
|
|
Requirement: 0.000ns (mlkem_clk_clk_pll rise@0.000ns - mlkem_clk_clk_pll rise@0.000ns)
|
|
Data Path Delay: 0.809ns (logic 0.186ns (22.998%) route 0.623ns (77.002%))
|
|
Logic Levels: 1 (LUT1=1)
|
|
Clock Path Skew: 0.033ns (DCD - SCD - CPR)
|
|
Destination Clock Delay (DCD): -0.382ns
|
|
Source Clock Delay (SCD): -0.607ns
|
|
Clock Pessimism Removal (CPR): 0.192ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock mlkem_clk_clk_pll rise edge)
|
|
0.000 0.000 r
|
|
clock source latency -1.848 -1.848
|
|
propagated clock network latency
|
|
1.241 -0.607
|
|
SLICE_X118Y67 FDCE 0.000 -0.607 r pll_clk.u_rst_mlkem/delay_reg[1]/C
|
|
SLICE_X118Y67 FDCE (Prop_fdce_C_Q) 0.141 -0.466 r pll_clk.u_rst_mlkem/delay_reg[1]/Q
|
|
net (fo=4, routed) 0.297 -0.169 pll_clk.u_rst_mlkem/Q[0]
|
|
SLICE_X118Y67 r pll_clk.u_rst_mlkem/rdb_addr[11]_i_2/I0
|
|
SLICE_X118Y67 LUT1 (Prop_lut1_I0_O) 0.045 -0.124 f pll_clk.u_rst_mlkem/rdb_addr[11]_i_2/O
|
|
net (fo=1069, routed) 0.325 0.201 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/pre_addr_l_reg[2]_rep__1_0
|
|
SLICE_X122Y69 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/stream_wstrb_reg[2]/CLR
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock mlkem_clk_clk_pll rise edge)
|
|
0.000 0.000 r
|
|
clock source latency -1.947 -1.947
|
|
propagated clock network latency
|
|
1.565 -0.382
|
|
clock pessimism -0.192 -0.574
|
|
SLICE_X122Y69 FDCE (Remov_fdce_C_CLR) -0.092 -0.666 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/stream_wstrb_reg[2]
|
|
-------------------------------------------------------------------
|
|
required time 0.666
|
|
arrival time 0.201
|
|
-------------------------------------------------------------------
|
|
slack 0.868
|
|
|
|
Slack (MET) : 0.868ns (arrival time - required time)
|
|
Source: pll_clk.u_rst_mlkem/delay_reg[1]/C
|
|
(rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns})
|
|
Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/stream_wstrb_reg[3]/CLR
|
|
(removal check against rising-edge clock mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns})
|
|
Path Group: **async_default**
|
|
Path Type: Removal (Min at Fast Process Corner)
|
|
Requirement: 0.000ns (mlkem_clk_clk_pll rise@0.000ns - mlkem_clk_clk_pll rise@0.000ns)
|
|
Data Path Delay: 0.809ns (logic 0.186ns (22.998%) route 0.623ns (77.002%))
|
|
Logic Levels: 1 (LUT1=1)
|
|
Clock Path Skew: 0.033ns (DCD - SCD - CPR)
|
|
Destination Clock Delay (DCD): -0.382ns
|
|
Source Clock Delay (SCD): -0.607ns
|
|
Clock Pessimism Removal (CPR): 0.192ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock mlkem_clk_clk_pll rise edge)
|
|
0.000 0.000 r
|
|
clock source latency -1.848 -1.848
|
|
propagated clock network latency
|
|
1.241 -0.607
|
|
SLICE_X118Y67 FDCE 0.000 -0.607 r pll_clk.u_rst_mlkem/delay_reg[1]/C
|
|
SLICE_X118Y67 FDCE (Prop_fdce_C_Q) 0.141 -0.466 r pll_clk.u_rst_mlkem/delay_reg[1]/Q
|
|
net (fo=4, routed) 0.297 -0.169 pll_clk.u_rst_mlkem/Q[0]
|
|
SLICE_X118Y67 r pll_clk.u_rst_mlkem/rdb_addr[11]_i_2/I0
|
|
SLICE_X118Y67 LUT1 (Prop_lut1_I0_O) 0.045 -0.124 f pll_clk.u_rst_mlkem/rdb_addr[11]_i_2/O
|
|
net (fo=1069, routed) 0.325 0.201 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/pre_addr_l_reg[2]_rep__1_0
|
|
SLICE_X122Y69 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/stream_wstrb_reg[3]/CLR
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock mlkem_clk_clk_pll rise edge)
|
|
0.000 0.000 r
|
|
clock source latency -1.947 -1.947
|
|
propagated clock network latency
|
|
1.565 -0.382
|
|
clock pessimism -0.192 -0.574
|
|
SLICE_X122Y69 FDCE (Remov_fdce_C_CLR) -0.092 -0.666 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/stream_wstrb_reg[3]
|
|
-------------------------------------------------------------------
|
|
required time 0.666
|
|
arrival time 0.201
|
|
-------------------------------------------------------------------
|
|
slack 0.868
|
|
|
|
Slack (MET) : 0.881ns (arrival time - required time)
|
|
Source: pll_clk.u_rst_mlkem/delay_reg[1]/C
|
|
(rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns})
|
|
Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/stream_lane_reg[1]/CLR
|
|
(removal check against rising-edge clock mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns})
|
|
Path Group: **async_default**
|
|
Path Type: Removal (Min at Fast Process Corner)
|
|
Requirement: 0.000ns (mlkem_clk_clk_pll rise@0.000ns - mlkem_clk_clk_pll rise@0.000ns)
|
|
Data Path Delay: 0.846ns (logic 0.186ns (21.984%) route 0.660ns (78.016%))
|
|
Logic Levels: 1 (LUT1=1)
|
|
Clock Path Skew: 0.032ns (DCD - SCD - CPR)
|
|
Destination Clock Delay (DCD): -0.383ns
|
|
Source Clock Delay (SCD): -0.607ns
|
|
Clock Pessimism Removal (CPR): 0.192ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock mlkem_clk_clk_pll rise edge)
|
|
0.000 0.000 r
|
|
clock source latency -1.848 -1.848
|
|
propagated clock network latency
|
|
1.241 -0.607
|
|
SLICE_X118Y67 FDCE 0.000 -0.607 r pll_clk.u_rst_mlkem/delay_reg[1]/C
|
|
SLICE_X118Y67 FDCE (Prop_fdce_C_Q) 0.141 -0.466 r pll_clk.u_rst_mlkem/delay_reg[1]/Q
|
|
net (fo=4, routed) 0.297 -0.169 pll_clk.u_rst_mlkem/Q[0]
|
|
SLICE_X118Y67 r pll_clk.u_rst_mlkem/rdb_addr[11]_i_2/I0
|
|
SLICE_X118Y67 LUT1 (Prop_lut1_I0_O) 0.045 -0.124 f pll_clk.u_rst_mlkem/rdb_addr[11]_i_2/O
|
|
net (fo=1069, routed) 0.363 0.239 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/pre_addr_l_reg[2]_rep__1_0
|
|
SLICE_X120Y70 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/stream_lane_reg[1]/CLR
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock mlkem_clk_clk_pll rise edge)
|
|
0.000 0.000 r
|
|
clock source latency -1.947 -1.947
|
|
propagated clock network latency
|
|
1.564 -0.383
|
|
clock pessimism -0.192 -0.575
|
|
SLICE_X120Y70 FDCE (Remov_fdce_C_CLR) -0.067 -0.642 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/stream_lane_reg[1]
|
|
-------------------------------------------------------------------
|
|
required time 0.642
|
|
arrival time 0.239
|
|
-------------------------------------------------------------------
|
|
slack 0.881
|
|
|
|
Slack (MET) : 0.881ns (arrival time - required time)
|
|
Source: pll_clk.u_rst_mlkem/delay_reg[1]/C
|
|
(rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns})
|
|
Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/stream_lane_reg[2]/CLR
|
|
(removal check against rising-edge clock mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns})
|
|
Path Group: **async_default**
|
|
Path Type: Removal (Min at Fast Process Corner)
|
|
Requirement: 0.000ns (mlkem_clk_clk_pll rise@0.000ns - mlkem_clk_clk_pll rise@0.000ns)
|
|
Data Path Delay: 0.846ns (logic 0.186ns (21.984%) route 0.660ns (78.016%))
|
|
Logic Levels: 1 (LUT1=1)
|
|
Clock Path Skew: 0.032ns (DCD - SCD - CPR)
|
|
Destination Clock Delay (DCD): -0.383ns
|
|
Source Clock Delay (SCD): -0.607ns
|
|
Clock Pessimism Removal (CPR): 0.192ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock mlkem_clk_clk_pll rise edge)
|
|
0.000 0.000 r
|
|
clock source latency -1.848 -1.848
|
|
propagated clock network latency
|
|
1.241 -0.607
|
|
SLICE_X118Y67 FDCE 0.000 -0.607 r pll_clk.u_rst_mlkem/delay_reg[1]/C
|
|
SLICE_X118Y67 FDCE (Prop_fdce_C_Q) 0.141 -0.466 r pll_clk.u_rst_mlkem/delay_reg[1]/Q
|
|
net (fo=4, routed) 0.297 -0.169 pll_clk.u_rst_mlkem/Q[0]
|
|
SLICE_X118Y67 r pll_clk.u_rst_mlkem/rdb_addr[11]_i_2/I0
|
|
SLICE_X118Y67 LUT1 (Prop_lut1_I0_O) 0.045 -0.124 f pll_clk.u_rst_mlkem/rdb_addr[11]_i_2/O
|
|
net (fo=1069, routed) 0.363 0.239 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/pre_addr_l_reg[2]_rep__1_0
|
|
SLICE_X120Y70 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/stream_lane_reg[2]/CLR
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock mlkem_clk_clk_pll rise edge)
|
|
0.000 0.000 r
|
|
clock source latency -1.947 -1.947
|
|
propagated clock network latency
|
|
1.564 -0.383
|
|
clock pessimism -0.192 -0.575
|
|
SLICE_X120Y70 FDCE (Remov_fdce_C_CLR) -0.067 -0.642 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/stream_lane_reg[2]
|
|
-------------------------------------------------------------------
|
|
required time 0.642
|
|
arrival time 0.239
|
|
-------------------------------------------------------------------
|
|
slack 0.881
|
|
|
|
Slack (MET) : 0.885ns (arrival time - required time)
|
|
Source: u_Axi_CDC/bFifo/bufferCC_12/buffers_1_reg/C
|
|
(rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns})
|
|
Destination: u_Axi_CDC/bFifo/popCC_popPtr_reg[0]/CLR
|
|
(removal check against rising-edge clock cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns})
|
|
Path Group: **async_default**
|
|
Path Type: Removal (Min at Fast Process Corner)
|
|
Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns)
|
|
Data Path Delay: 0.838ns (logic 0.227ns (27.080%) route 0.611ns (72.920%))
|
|
Logic Levels: 1 (LUT1=1)
|
|
Clock Path Skew: 0.045ns (DCD - SCD - CPR)
|
|
Destination Clock Delay (DCD): -0.338ns
|
|
Source Clock Delay (SCD): -0.575ns
|
|
Clock Pessimism Removal (CPR): 0.192ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock cpu_clk rise edge) 0.000 0.000 r
|
|
clock source latency -1.848 -1.848
|
|
propagated clock network latency
|
|
1.273 -0.575
|
|
SLICE_X30Y58 FDCE 0.000 -0.575 r u_Axi_CDC/bFifo/bufferCC_12/buffers_1_reg/C
|
|
SLICE_X30Y58 FDCE (Prop_fdce_C_Q) 0.128 -0.447 r u_Axi_CDC/bFifo/bufferCC_12/buffers_1_reg/Q
|
|
net (fo=1, routed) 0.207 -0.241 u_Axi_CDC/bFifo/bufferCC_12/buffers_1
|
|
SLICE_X28Y58 r u_Axi_CDC/bFifo/bufferCC_12/popCC_popPtr[2]_i_2__0/I0
|
|
SLICE_X28Y58 LUT1 (Prop_lut1_I0_O) 0.099 -0.142 f u_Axi_CDC/bFifo/bufferCC_12/popCC_popPtr[2]_i_2__0/O
|
|
net (fo=30, routed) 0.404 0.263 u_Axi_CDC/bFifo/buffers_1_reg
|
|
SLICE_X19Y58 FDCE f u_Axi_CDC/bFifo/popCC_popPtr_reg[0]/CLR
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock cpu_clk rise edge) 0.000 0.000 r
|
|
clock source latency -1.947 -1.947
|
|
propagated clock network latency
|
|
1.609 -0.338
|
|
clock pessimism -0.192 -0.530
|
|
SLICE_X19Y58 FDCE (Remov_fdce_C_CLR) -0.092 -0.622 u_Axi_CDC/bFifo/popCC_popPtr_reg[0]
|
|
-------------------------------------------------------------------
|
|
required time 0.622
|
|
arrival time 0.263
|
|
-------------------------------------------------------------------
|
|
slack 0.885
|
|
|
|
Slack (MET) : 0.885ns (arrival time - required time)
|
|
Source: u_Axi_CDC/bFifo/bufferCC_12/buffers_1_reg/C
|
|
(rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns})
|
|
Destination: u_Axi_CDC/bFifo/popCC_popPtr_reg[1]/CLR
|
|
(removal check against rising-edge clock cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns})
|
|
Path Group: **async_default**
|
|
Path Type: Removal (Min at Fast Process Corner)
|
|
Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns)
|
|
Data Path Delay: 0.838ns (logic 0.227ns (27.080%) route 0.611ns (72.920%))
|
|
Logic Levels: 1 (LUT1=1)
|
|
Clock Path Skew: 0.045ns (DCD - SCD - CPR)
|
|
Destination Clock Delay (DCD): -0.338ns
|
|
Source Clock Delay (SCD): -0.575ns
|
|
Clock Pessimism Removal (CPR): 0.192ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock cpu_clk rise edge) 0.000 0.000 r
|
|
clock source latency -1.848 -1.848
|
|
propagated clock network latency
|
|
1.273 -0.575
|
|
SLICE_X30Y58 FDCE 0.000 -0.575 r u_Axi_CDC/bFifo/bufferCC_12/buffers_1_reg/C
|
|
SLICE_X30Y58 FDCE (Prop_fdce_C_Q) 0.128 -0.447 r u_Axi_CDC/bFifo/bufferCC_12/buffers_1_reg/Q
|
|
net (fo=1, routed) 0.207 -0.241 u_Axi_CDC/bFifo/bufferCC_12/buffers_1
|
|
SLICE_X28Y58 r u_Axi_CDC/bFifo/bufferCC_12/popCC_popPtr[2]_i_2__0/I0
|
|
SLICE_X28Y58 LUT1 (Prop_lut1_I0_O) 0.099 -0.142 f u_Axi_CDC/bFifo/bufferCC_12/popCC_popPtr[2]_i_2__0/O
|
|
net (fo=30, routed) 0.404 0.263 u_Axi_CDC/bFifo/buffers_1_reg
|
|
SLICE_X19Y58 FDCE f u_Axi_CDC/bFifo/popCC_popPtr_reg[1]/CLR
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock cpu_clk rise edge) 0.000 0.000 r
|
|
clock source latency -1.947 -1.947
|
|
propagated clock network latency
|
|
1.609 -0.338
|
|
clock pessimism -0.192 -0.530
|
|
SLICE_X19Y58 FDCE (Remov_fdce_C_CLR) -0.092 -0.622 u_Axi_CDC/bFifo/popCC_popPtr_reg[1]
|
|
-------------------------------------------------------------------
|
|
required time 0.622
|
|
arrival time 0.263
|
|
-------------------------------------------------------------------
|
|
slack 0.885
|
|
|
|
Slack (MET) : 0.885ns (arrival time - required time)
|
|
Source: u_Axi_CDC/bFifo/bufferCC_12/buffers_1_reg/C
|
|
(rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns})
|
|
Destination: u_Axi_CDC/bFifo/popCC_ptrToPush_reg[0]/CLR
|
|
(removal check against rising-edge clock cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns})
|
|
Path Group: **async_default**
|
|
Path Type: Removal (Min at Fast Process Corner)
|
|
Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns)
|
|
Data Path Delay: 0.838ns (logic 0.227ns (27.080%) route 0.611ns (72.920%))
|
|
Logic Levels: 1 (LUT1=1)
|
|
Clock Path Skew: 0.045ns (DCD - SCD - CPR)
|
|
Destination Clock Delay (DCD): -0.338ns
|
|
Source Clock Delay (SCD): -0.575ns
|
|
Clock Pessimism Removal (CPR): 0.192ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock cpu_clk rise edge) 0.000 0.000 r
|
|
clock source latency -1.848 -1.848
|
|
propagated clock network latency
|
|
1.273 -0.575
|
|
SLICE_X30Y58 FDCE 0.000 -0.575 r u_Axi_CDC/bFifo/bufferCC_12/buffers_1_reg/C
|
|
SLICE_X30Y58 FDCE (Prop_fdce_C_Q) 0.128 -0.447 r u_Axi_CDC/bFifo/bufferCC_12/buffers_1_reg/Q
|
|
net (fo=1, routed) 0.207 -0.241 u_Axi_CDC/bFifo/bufferCC_12/buffers_1
|
|
SLICE_X28Y58 r u_Axi_CDC/bFifo/bufferCC_12/popCC_popPtr[2]_i_2__0/I0
|
|
SLICE_X28Y58 LUT1 (Prop_lut1_I0_O) 0.099 -0.142 f u_Axi_CDC/bFifo/bufferCC_12/popCC_popPtr[2]_i_2__0/O
|
|
net (fo=30, routed) 0.404 0.263 u_Axi_CDC/bFifo/buffers_1_reg
|
|
SLICE_X19Y58 FDCE f u_Axi_CDC/bFifo/popCC_ptrToPush_reg[0]/CLR
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock cpu_clk rise edge) 0.000 0.000 r
|
|
clock source latency -1.947 -1.947
|
|
propagated clock network latency
|
|
1.609 -0.338
|
|
clock pessimism -0.192 -0.530
|
|
SLICE_X19Y58 FDCE (Remov_fdce_C_CLR) -0.092 -0.622 u_Axi_CDC/bFifo/popCC_ptrToPush_reg[0]
|
|
-------------------------------------------------------------------
|
|
required time 0.622
|
|
arrival time 0.263
|
|
-------------------------------------------------------------------
|
|
slack 0.885
|
|
|
|
Slack (MET) : 0.906ns (arrival time - required time)
|
|
Source: pll_clk.u_rst_mlkem/delay_reg[1]/C
|
|
(rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns})
|
|
Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/stream_wdata_reg[13]/CLR
|
|
(removal check against rising-edge clock mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns})
|
|
Path Group: **async_default**
|
|
Path Type: Removal (Min at Fast Process Corner)
|
|
Requirement: 0.000ns (mlkem_clk_clk_pll rise@0.000ns - mlkem_clk_clk_pll rise@0.000ns)
|
|
Data Path Delay: 0.846ns (logic 0.186ns (21.984%) route 0.660ns (78.016%))
|
|
Logic Levels: 1 (LUT1=1)
|
|
Clock Path Skew: 0.032ns (DCD - SCD - CPR)
|
|
Destination Clock Delay (DCD): -0.383ns
|
|
Source Clock Delay (SCD): -0.607ns
|
|
Clock Pessimism Removal (CPR): 0.192ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock mlkem_clk_clk_pll rise edge)
|
|
0.000 0.000 r
|
|
clock source latency -1.848 -1.848
|
|
propagated clock network latency
|
|
1.241 -0.607
|
|
SLICE_X118Y67 FDCE 0.000 -0.607 r pll_clk.u_rst_mlkem/delay_reg[1]/C
|
|
SLICE_X118Y67 FDCE (Prop_fdce_C_Q) 0.141 -0.466 r pll_clk.u_rst_mlkem/delay_reg[1]/Q
|
|
net (fo=4, routed) 0.297 -0.169 pll_clk.u_rst_mlkem/Q[0]
|
|
SLICE_X118Y67 r pll_clk.u_rst_mlkem/rdb_addr[11]_i_2/I0
|
|
SLICE_X118Y67 LUT1 (Prop_lut1_I0_O) 0.045 -0.124 f pll_clk.u_rst_mlkem/rdb_addr[11]_i_2/O
|
|
net (fo=1069, routed) 0.363 0.239 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/pre_addr_l_reg[2]_rep__1_0
|
|
SLICE_X121Y70 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/stream_wdata_reg[13]/CLR
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock mlkem_clk_clk_pll rise edge)
|
|
0.000 0.000 r
|
|
clock source latency -1.947 -1.947
|
|
propagated clock network latency
|
|
1.564 -0.383
|
|
clock pessimism -0.192 -0.575
|
|
SLICE_X121Y70 FDCE (Remov_fdce_C_CLR) -0.092 -0.667 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/stream_wdata_reg[13]
|
|
-------------------------------------------------------------------
|
|
required time 0.667
|
|
arrival time 0.239
|
|
-------------------------------------------------------------------
|
|
slack 0.906
|
|
|
|
Slack (MET) : 0.906ns (arrival time - required time)
|
|
Source: pll_clk.u_rst_mlkem/delay_reg[1]/C
|
|
(rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns})
|
|
Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/stream_wdata_reg[21]/CLR
|
|
(removal check against rising-edge clock mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns})
|
|
Path Group: **async_default**
|
|
Path Type: Removal (Min at Fast Process Corner)
|
|
Requirement: 0.000ns (mlkem_clk_clk_pll rise@0.000ns - mlkem_clk_clk_pll rise@0.000ns)
|
|
Data Path Delay: 0.846ns (logic 0.186ns (21.984%) route 0.660ns (78.016%))
|
|
Logic Levels: 1 (LUT1=1)
|
|
Clock Path Skew: 0.032ns (DCD - SCD - CPR)
|
|
Destination Clock Delay (DCD): -0.383ns
|
|
Source Clock Delay (SCD): -0.607ns
|
|
Clock Pessimism Removal (CPR): 0.192ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock mlkem_clk_clk_pll rise edge)
|
|
0.000 0.000 r
|
|
clock source latency -1.848 -1.848
|
|
propagated clock network latency
|
|
1.241 -0.607
|
|
SLICE_X118Y67 FDCE 0.000 -0.607 r pll_clk.u_rst_mlkem/delay_reg[1]/C
|
|
SLICE_X118Y67 FDCE (Prop_fdce_C_Q) 0.141 -0.466 r pll_clk.u_rst_mlkem/delay_reg[1]/Q
|
|
net (fo=4, routed) 0.297 -0.169 pll_clk.u_rst_mlkem/Q[0]
|
|
SLICE_X118Y67 r pll_clk.u_rst_mlkem/rdb_addr[11]_i_2/I0
|
|
SLICE_X118Y67 LUT1 (Prop_lut1_I0_O) 0.045 -0.124 f pll_clk.u_rst_mlkem/rdb_addr[11]_i_2/O
|
|
net (fo=1069, routed) 0.363 0.239 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/pre_addr_l_reg[2]_rep__1_0
|
|
SLICE_X121Y70 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/stream_wdata_reg[21]/CLR
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock mlkem_clk_clk_pll rise edge)
|
|
0.000 0.000 r
|
|
clock source latency -1.947 -1.947
|
|
propagated clock network latency
|
|
1.564 -0.383
|
|
clock pessimism -0.192 -0.575
|
|
SLICE_X121Y70 FDCE (Remov_fdce_C_CLR) -0.092 -0.667 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/stream_wdata_reg[21]
|
|
-------------------------------------------------------------------
|
|
required time 0.667
|
|
arrival time 0.239
|
|
-------------------------------------------------------------------
|
|
slack 0.906
|
|
|
|
Slack (MET) : 0.906ns (arrival time - required time)
|
|
Source: pll_clk.u_rst_mlkem/delay_reg[1]/C
|
|
(rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns})
|
|
Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/stream_wdata_reg[29]/CLR
|
|
(removal check against rising-edge clock mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns})
|
|
Path Group: **async_default**
|
|
Path Type: Removal (Min at Fast Process Corner)
|
|
Requirement: 0.000ns (mlkem_clk_clk_pll rise@0.000ns - mlkem_clk_clk_pll rise@0.000ns)
|
|
Data Path Delay: 0.846ns (logic 0.186ns (21.984%) route 0.660ns (78.016%))
|
|
Logic Levels: 1 (LUT1=1)
|
|
Clock Path Skew: 0.032ns (DCD - SCD - CPR)
|
|
Destination Clock Delay (DCD): -0.383ns
|
|
Source Clock Delay (SCD): -0.607ns
|
|
Clock Pessimism Removal (CPR): 0.192ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock mlkem_clk_clk_pll rise edge)
|
|
0.000 0.000 r
|
|
clock source latency -1.848 -1.848
|
|
propagated clock network latency
|
|
1.241 -0.607
|
|
SLICE_X118Y67 FDCE 0.000 -0.607 r pll_clk.u_rst_mlkem/delay_reg[1]/C
|
|
SLICE_X118Y67 FDCE (Prop_fdce_C_Q) 0.141 -0.466 r pll_clk.u_rst_mlkem/delay_reg[1]/Q
|
|
net (fo=4, routed) 0.297 -0.169 pll_clk.u_rst_mlkem/Q[0]
|
|
SLICE_X118Y67 r pll_clk.u_rst_mlkem/rdb_addr[11]_i_2/I0
|
|
SLICE_X118Y67 LUT1 (Prop_lut1_I0_O) 0.045 -0.124 f pll_clk.u_rst_mlkem/rdb_addr[11]_i_2/O
|
|
net (fo=1069, routed) 0.363 0.239 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/pre_addr_l_reg[2]_rep__1_0
|
|
SLICE_X121Y70 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/stream_wdata_reg[29]/CLR
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock mlkem_clk_clk_pll rise edge)
|
|
0.000 0.000 r
|
|
clock source latency -1.947 -1.947
|
|
propagated clock network latency
|
|
1.564 -0.383
|
|
clock pessimism -0.192 -0.575
|
|
SLICE_X121Y70 FDCE (Remov_fdce_C_CLR) -0.092 -0.667 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/stream_wdata_reg[29]
|
|
-------------------------------------------------------------------
|
|
required time 0.667
|
|
arrival time 0.239
|
|
-------------------------------------------------------------------
|
|
slack 0.906
|
|
|
|
Slack (MET) : 0.906ns (arrival time - required time)
|
|
Source: pll_clk.u_rst_mlkem/delay_reg[1]/C
|
|
(rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns})
|
|
Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/stream_wdata_reg[5]/CLR
|
|
(removal check against rising-edge clock mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns})
|
|
Path Group: **async_default**
|
|
Path Type: Removal (Min at Fast Process Corner)
|
|
Requirement: 0.000ns (mlkem_clk_clk_pll rise@0.000ns - mlkem_clk_clk_pll rise@0.000ns)
|
|
Data Path Delay: 0.846ns (logic 0.186ns (21.984%) route 0.660ns (78.016%))
|
|
Logic Levels: 1 (LUT1=1)
|
|
Clock Path Skew: 0.032ns (DCD - SCD - CPR)
|
|
Destination Clock Delay (DCD): -0.383ns
|
|
Source Clock Delay (SCD): -0.607ns
|
|
Clock Pessimism Removal (CPR): 0.192ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock mlkem_clk_clk_pll rise edge)
|
|
0.000 0.000 r
|
|
clock source latency -1.848 -1.848
|
|
propagated clock network latency
|
|
1.241 -0.607
|
|
SLICE_X118Y67 FDCE 0.000 -0.607 r pll_clk.u_rst_mlkem/delay_reg[1]/C
|
|
SLICE_X118Y67 FDCE (Prop_fdce_C_Q) 0.141 -0.466 r pll_clk.u_rst_mlkem/delay_reg[1]/Q
|
|
net (fo=4, routed) 0.297 -0.169 pll_clk.u_rst_mlkem/Q[0]
|
|
SLICE_X118Y67 r pll_clk.u_rst_mlkem/rdb_addr[11]_i_2/I0
|
|
SLICE_X118Y67 LUT1 (Prop_lut1_I0_O) 0.045 -0.124 f pll_clk.u_rst_mlkem/rdb_addr[11]_i_2/O
|
|
net (fo=1069, routed) 0.363 0.239 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/pre_addr_l_reg[2]_rep__1_0
|
|
SLICE_X121Y70 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/stream_wdata_reg[5]/CLR
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock mlkem_clk_clk_pll rise edge)
|
|
0.000 0.000 r
|
|
clock source latency -1.947 -1.947
|
|
propagated clock network latency
|
|
1.564 -0.383
|
|
clock pessimism -0.192 -0.575
|
|
SLICE_X121Y70 FDCE (Remov_fdce_C_CLR) -0.092 -0.667 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/stream_wdata_reg[5]
|
|
-------------------------------------------------------------------
|
|
required time 0.667
|
|
arrival time 0.239
|
|
-------------------------------------------------------------------
|
|
slack 0.906
|
|
|
|
|
|
|
|
|