260 lines
9.3 KiB
Verilog
260 lines
9.3 KiB
Verilog
/*------------------------------------------------------------------------------
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--------------------------------------------------------------------------------
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Copyright (c) 2016, Loongson Technology Corporation Limited.
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All rights reserved.
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Redistribution and use in source and binary forms, with or without modification,
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are permitted provided that the following conditions are met:
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1. Redistributions of source code must retain the above copyright notice, this
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list of conditions and the following disclaimer.
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2. Redistributions in binary form must reproduce the above copyright notice,
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this list of conditions and the following disclaimer in the documentation and/or
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other materials provided with the distribution.
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3. Neither the name of Loongson Technology Corporation Limited nor the names of
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its contributors may be used to endorse or promote products derived from this
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software without specific prior written permission.
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THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
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ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
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WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
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DISCLAIMED. IN NO EVENT SHALL LOONGSON TECHNOLOGY CORPORATION LIMITED BE LIABLE
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TO ANY PARTY FOR DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
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CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE
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GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF
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THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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--------------------------------------------------------------------------------
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------------------------------------------------------------------------------*/
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module axi_wrap_ram_sp_external (
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input aclk,
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input aresetn,
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//ar
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input [4 :0] axi_arid ,
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input [31:0] axi_araddr ,
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input [7 :0] axi_arlen ,
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input [2 :0] axi_arsize ,
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input [1 :0] axi_arburst,
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input axi_arlock ,
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input [3 :0] axi_arcache,
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input [2 :0] axi_arprot ,
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input axi_arvalid,
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output axi_arready,
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//r
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output [4 :0] axi_rid ,
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output [31:0] axi_rdata ,
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output [1 :0] axi_rresp ,
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output axi_rlast ,
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output axi_rvalid ,
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input axi_rready ,
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//aw
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input [4 :0] axi_awid ,
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input [31:0] axi_awaddr ,
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input [7 :0] axi_awlen ,
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input [2 :0] axi_awsize ,
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input [1 :0] axi_awburst,
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input axi_awlock ,
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input [3 :0] axi_awcache,
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input [2 :0] axi_awprot ,
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input axi_awvalid,
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output axi_awready,
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//w
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input [31:0] axi_wdata ,
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input [3 :0] axi_wstrb ,
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input axi_wlast ,
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input axi_wvalid ,
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output axi_wready ,
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//b
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output [4 :0] axi_bid ,
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output [1 :0] axi_bresp ,
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output axi_bvalid ,
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input axi_bready ,
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//BaseRAM信号
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inout [31:0] base_ram_data, //BaseRAM数据，低8位与CPLD串口控制器共享
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output [19:0] base_ram_addr, //BaseRAM地址
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output [ 3:0] base_ram_be_n, //BaseRAM字节使能，低有效。如果不使用字节使能，请保持为0
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output base_ram_ce_n, //BaseRAM片选，低有效
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output base_ram_oe_n, //BaseRAM读使能，低有效
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output base_ram_we_n, //BaseRAM写使能，低有效
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//ExtRAM信号
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inout [31:0] ext_ram_data, //ExtRAM数据
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output [19:0] ext_ram_addr, //ExtRAM地址
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output [ 3:0] ext_ram_be_n, //ExtRAM字节使能，低有效。如果不使用字节使能，请保持为0
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output ext_ram_ce_n, //ExtRAM片选，低有效
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output ext_ram_oe_n, //ExtRAM读使能，低有效
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output ext_ram_we_n //ExtRAM写使能，低有效
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);
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//ram axi
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//ar
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wire [4 :0] ram_arid ;
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wire [31:0] ram_araddr ;
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wire [7 :0] ram_arlen ;
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wire [2 :0] ram_arsize ;
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wire [1 :0] ram_arburst;
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wire ram_arlock ;
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wire [3 :0] ram_arcache;
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wire [2 :0] ram_arprot ;
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wire ram_arvalid;
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wire ram_arready;
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//r
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wire [4 :0] ram_rid ;
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wire [31:0] ram_rdata ;
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wire [1 :0] ram_rresp ;
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wire ram_rlast ;
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wire ram_rvalid ;
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wire ram_rready ;
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//aw
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wire [4 :0] ram_awid ;
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wire [31:0] ram_awaddr ;
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wire [7 :0] ram_awlen ;
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wire [2 :0] ram_awsize ;
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wire [1 :0] ram_awburst;
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wire ram_awlock ;
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wire [3 :0] ram_awcache;
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wire [2 :0] ram_awprot ;
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wire ram_awvalid;
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wire ram_awready;
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//w
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wire [31:0] ram_wdata ;
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wire [3 :0] ram_wstrb ;
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wire ram_wlast ;
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wire ram_wvalid ;
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wire ram_wready ;
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//b
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wire [4 :0] ram_bid ;
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wire [1 :0] ram_bresp ;
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wire ram_bvalid ;
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wire ram_bready ;
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//sram signal
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wire [31:0] soc_sram_addr;
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wire soc_sram_cs;
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wire soc_sram_we;
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wire [3:0] soc_sram_be;
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wire [31:0] soc_sram_wdata;
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wire [31:0] soc_sram_rdata;
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//ar
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assign ram_arid = axi_arid ;
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assign ram_araddr = axi_araddr ;
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assign ram_arlen = axi_arlen ;
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assign ram_arsize = axi_arsize ;
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assign ram_arburst = axi_arburst;
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assign ram_arlock = axi_arlock ;
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assign ram_arcache = axi_arcache;
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assign ram_arprot = axi_arprot ;
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assign ram_arvalid = axi_arvalid;
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assign axi_arready = ram_arready;
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//r
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assign axi_rid = axi_rvalid ? ram_rid : 5'd0 ;
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assign axi_rdata = axi_rvalid ? ram_rdata : 32'd0 ;
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assign axi_rresp = axi_rvalid ? ram_rresp : 2'd0 ;
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assign axi_rlast = axi_rvalid ? ram_rlast : 1'd0 ;
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assign axi_rvalid = ram_rvalid;
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assign ram_rready = axi_rready;
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//aw
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assign ram_awid = axi_awid ;
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assign ram_awaddr = axi_awaddr ;
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assign ram_awlen = axi_awlen ;
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assign ram_awsize = axi_awsize ;
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assign ram_awburst = axi_awburst;
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assign ram_awlock = axi_awlock ;
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assign ram_awcache = axi_awcache;
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assign ram_awprot = axi_awprot ;
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assign ram_awvalid = axi_awvalid;
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assign axi_awready = ram_awready;
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//w
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assign ram_wdata = axi_wdata ;
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assign ram_wstrb = axi_wstrb ;
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assign ram_wlast = axi_wlast ;
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assign ram_wvalid = axi_wvalid ;
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assign axi_wready = ram_wready ;
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//b
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assign axi_bid = axi_bvalid ? ram_bid : 5'd0 ;
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assign axi_bresp = axi_bvalid ? ram_bresp : 2'd0 ;
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assign axi_bvalid = ram_bvalid ;
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assign ram_bready = axi_bready ;
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axi2sram_sp_external #(
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.AXI_ID_WIDTH ( 5 ),
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.AXI_ADDR_WIDTH ( 32 ),
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.AXI_DATA_WIDTH ( 32 ))
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u_axi_sram_sp (
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.clk ( aclk ),
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.resetn ( aresetn ),
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.s_araddr ( ram_araddr ),
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.s_arburst ( ram_arburst ),
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.s_arcache ( ram_arcache ),
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.s_arid ( ram_arid ),
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.s_arlen ( ram_arlen ),
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.s_arlock ( ram_arlock ),
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.s_arprot ( ram_arprot ),
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.s_arsize ( ram_arsize ),
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.s_arvalid ( ram_arvalid ),
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.s_awaddr ( ram_awaddr ),
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.s_awburst ( ram_awburst ),
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.s_awcache ( ram_awcache ),
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.s_awid ( ram_awid ),
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.s_awlen ( ram_awlen ),
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.s_awlock ( ram_awlock ),
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.s_awprot ( ram_awprot ),
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.s_awsize ( ram_awsize ),
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.s_awvalid ( ram_awvalid ),
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.s_bready ( ram_bready ),
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.s_rready ( ram_rready ),
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.s_wdata ( ram_wdata ),
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.s_wlast ( ram_wlast ),
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.s_wstrb ( ram_wstrb ),
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.s_wvalid ( ram_wvalid ),
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.s_arready ( ram_arready ),
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.s_awready ( ram_awready ),
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.s_bid ( ram_bid ),
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.s_bresp ( ram_bresp ),
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.s_bvalid ( ram_bvalid ),
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.s_rdata ( ram_rdata ),
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.s_rid ( ram_rid ),
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.s_rlast ( ram_rlast ),
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.s_rresp ( ram_rresp ),
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.s_rvalid ( ram_rvalid ),
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.s_wready ( ram_wready ),
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.req_o ( soc_sram_cs ),
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.we_o ( soc_sram_we ),
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.addr_o ( soc_sram_addr ),
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.be_o ( soc_sram_be ),
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.data_o ( soc_sram_wdata ),
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.data_i ( soc_sram_rdata )
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);
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wire choose_sram = soc_sram_addr[22];//1:ExtRAM 0:BaseRAM
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wire [3:0] be_out = soc_sram_we ? soc_sram_be : 4'b1111;
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assign base_ram_addr = soc_sram_addr[21:2];
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assign base_ram_be_n = choose_sram ? 4'b1111 : ~be_out;
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assign base_ram_ce_n = ~(soc_sram_cs & (~choose_sram));
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assign base_ram_oe_n = soc_sram_we | choose_sram;
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assign base_ram_we_n = ~(soc_sram_we & (~choose_sram));
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assign base_ram_data = ((~choose_sram) & soc_sram_cs & soc_sram_we) ? soc_sram_wdata : 32'hzzzzzzzz;
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assign ext_ram_addr = soc_sram_addr[21:2];
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assign ext_ram_be_n = choose_sram ? ~be_out : 4'b1111;
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assign ext_ram_ce_n = choose_sram ? ~soc_sram_cs : 1'b1;
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assign ext_ram_oe_n = choose_sram ? soc_sram_we : 1'b1;
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assign ext_ram_we_n = choose_sram ? ~soc_sram_we : 1'b1;
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assign ext_ram_data = ((choose_sram) & soc_sram_cs & soc_sram_we) ? soc_sram_wdata : 32'hzzzzzzzz;
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assign soc_sram_rdata = choose_sram ? ext_ram_data : base_ram_data;
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endmodule
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