254 lines
37 KiB
Plaintext
254 lines
37 KiB
Plaintext
Copyright 1986-2019 Xilinx, Inc. All Rights Reserved.
|
|
---------------------------------------------------------------------------------------------------------------------------------------------------------
|
|
| Tool Version : Vivado v.2019.2 (lin64) Build 2708876 Wed Nov 6 21:39:14 MST 2019
|
|
| Date : Fri Jul 10 04:14:48 2026
|
|
| Host : fedora running 64-bit unknown
|
|
| Command : report_utilization -hierarchical -file /home/fallensigh/Dev/ciciec2026_loongson_regional/fpga/vivado_reports_nodsp/utilization_hier.rpt
|
|
| Design : soc_top
|
|
| Device : 7a200tfbg676-1
|
|
| Design State : Routed
|
|
---------------------------------------------------------------------------------------------------------------------------------------------------------
|
|
|
|
Utilization Design Information
|
|
|
|
Table of Contents
|
|
-----------------
|
|
1. Utilization by Hierarchy
|
|
|
|
1. Utilization by Hierarchy
|
|
---------------------------
|
|
|
|
+------------------------------------------+------------------------------+------------+------------+---------+------+-------+--------+--------+--------------+
|
|
| Instance | Module | Total LUTs | Logic LUTs | LUTRAMs | SRLs | FFs | RAMB36 | RAMB18 | DSP48 Blocks |
|
|
+------------------------------------------+------------------------------+------------+------------+---------+------+-------+--------+--------+--------------+
|
|
| soc_top | (top) | 71196 | 69453 | 628 | 1115 | 39690 | 10 | 31 | 0 |
|
|
| (soc_top) | (top) | 868 | 812 | 56 | 0 | 4 | 0 | 0 | 0 |
|
|
| pll_clk.u_clk_pll | clk_pll | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
|
|
| inst | clk_pll_clk_pll_clk_wiz | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
|
|
| pll_clk.u_rst_cpu | rst_sync | 1 | 1 | 0 | 0 | 2 | 0 | 0 | 0 |
|
|
| pll_clk.u_rst_sys | rst_sync_0 | 3 | 3 | 0 | 0 | 2 | 0 | 0 | 0 |
|
|
| u_AxiCrossbar_2x8 | AxiCrossbar_2x8 | 357 | 357 | 0 | 0 | 151 | 0 | 0 | 0 |
|
|
| (u_AxiCrossbar_2x8) | AxiCrossbar_2x8 | 8 | 8 | 0 | 0 | 24 | 0 | 0 | 0 |
|
|
| axi4ReadOnlyArbiter_4 | Axi4ReadOnlyArbiter | 19 | 19 | 0 | 0 | 3 | 0 | 0 | 0 |
|
|
| cmdArbiter | StreamArbiter_7_64 | 19 | 19 | 0 | 0 | 3 | 0 | 0 | 0 |
|
|
| axi4ReadOnlyArbiter_5 | Axi4ReadOnlyArbiter_47 | 5 | 5 | 0 | 0 | 2 | 0 | 0 | 0 |
|
|
| cmdArbiter | StreamArbiter_7_63 | 5 | 5 | 0 | 0 | 2 | 0 | 0 | 0 |
|
|
| axi4ReadOnlyArbiter_6 | Axi4ReadOnlyArbiter_48 | 12 | 12 | 0 | 0 | 3 | 0 | 0 | 0 |
|
|
| cmdArbiter | StreamArbiter_7_62 | 12 | 12 | 0 | 0 | 3 | 0 | 0 | 0 |
|
|
| axi4ReadOnlyArbiter_7 | Axi4ReadOnlyArbiter_49 | 13 | 13 | 0 | 0 | 3 | 0 | 0 | 0 |
|
|
| cmdArbiter | StreamArbiter_7_61 | 13 | 13 | 0 | 0 | 3 | 0 | 0 | 0 |
|
|
| axi4WriteOnlyArbiter_4 | Axi4WriteOnlyArbiter | 30 | 30 | 0 | 0 | 11 | 0 | 0 | 0 |
|
|
| (axi4WriteOnlyArbiter_4) | Axi4WriteOnlyArbiter | 0 | 0 | 0 | 0 | 2 | 0 | 0 | 0 |
|
|
| cmdArbiter | StreamArbiter_7_58 | 24 | 24 | 0 | 0 | 3 | 0 | 0 | 0 |
|
|
| cmdRouteFork_translated_fifo | StreamFifoLowLatency_3_59 | 7 | 7 | 0 | 0 | 6 | 0 | 0 | 0 |
|
|
| fifo | StreamFifo_3_60 | 7 | 7 | 0 | 0 | 6 | 0 | 0 | 0 |
|
|
| axi4WriteOnlyArbiter_5 | Axi4WriteOnlyArbiter_1 | 15 | 15 | 0 | 0 | 9 | 0 | 0 | 0 |
|
|
| cmdArbiter | StreamArbiter_7_55 | 7 | 7 | 0 | 0 | 3 | 0 | 0 | 0 |
|
|
| cmdRouteFork_translated_fifo | StreamFifoLowLatency_3_56 | 8 | 8 | 0 | 0 | 6 | 0 | 0 | 0 |
|
|
| fifo | StreamFifo_3_57 | 8 | 8 | 0 | 0 | 6 | 0 | 0 | 0 |
|
|
| axi4WriteOnlyArbiter_6 | Axi4WriteOnlyArbiter_2 | 26 | 26 | 0 | 0 | 11 | 0 | 0 | 0 |
|
|
| (axi4WriteOnlyArbiter_6) | Axi4WriteOnlyArbiter_2 | 0 | 0 | 0 | 0 | 2 | 0 | 0 | 0 |
|
|
| cmdArbiter | StreamArbiter_7_52 | 16 | 16 | 0 | 0 | 3 | 0 | 0 | 0 |
|
|
| cmdRouteFork_translated_fifo | StreamFifoLowLatency_3_53 | 10 | 10 | 0 | 0 | 6 | 0 | 0 | 0 |
|
|
| fifo | StreamFifo_3_54 | 10 | 10 | 0 | 0 | 6 | 0 | 0 | 0 |
|
|
| axi4WriteOnlyArbiter_7 | Axi4WriteOnlyArbiter_3 | 27 | 27 | 0 | 0 | 11 | 0 | 0 | 0 |
|
|
| (axi4WriteOnlyArbiter_7) | Axi4WriteOnlyArbiter_3 | 0 | 0 | 0 | 0 | 2 | 0 | 0 | 0 |
|
|
| cmdArbiter | StreamArbiter_7 | 18 | 18 | 0 | 0 | 3 | 0 | 0 | 0 |
|
|
| cmdRouteFork_translated_fifo | StreamFifoLowLatency_3 | 9 | 9 | 0 | 0 | 6 | 0 | 0 | 0 |
|
|
| fifo | StreamFifo_3 | 9 | 9 | 0 | 0 | 6 | 0 | 0 | 0 |
|
|
| axiIn_0_readOnly_decoder | Axi4ReadOnlyDecoder | 89 | 89 | 0 | 0 | 25 | 0 | 0 | 0 |
|
|
| (axiIn_0_readOnly_decoder) | Axi4ReadOnlyDecoder | 73 | 73 | 0 | 0 | 12 | 0 | 0 | 0 |
|
|
| errorSlave | Axi4ReadOnlyErrorSlave_1_51 | 16 | 16 | 0 | 0 | 13 | 0 | 0 | 0 |
|
|
| axiIn_0_writeOnly_decoder | Axi4WriteOnlyDecoder | 36 | 36 | 0 | 0 | 18 | 0 | 0 | 0 |
|
|
| (axiIn_0_writeOnly_decoder) | Axi4WriteOnlyDecoder | 16 | 16 | 0 | 0 | 16 | 0 | 0 | 0 |
|
|
| errorSlave | Axi4WriteOnlyErrorSlave_1_50 | 20 | 20 | 0 | 0 | 2 | 0 | 0 | 0 |
|
|
| axiIn_1_readOnly_decoder | Axi4ReadOnlyDecoder_1 | 55 | 55 | 0 | 0 | 17 | 0 | 0 | 0 |
|
|
| (axiIn_1_readOnly_decoder) | Axi4ReadOnlyDecoder_1 | 41 | 41 | 0 | 0 | 8 | 0 | 0 | 0 |
|
|
| errorSlave | Axi4ReadOnlyErrorSlave_1 | 15 | 15 | 0 | 0 | 9 | 0 | 0 | 0 |
|
|
| axiIn_1_writeOnly_decoder | Axi4WriteOnlyDecoder_1 | 23 | 23 | 0 | 0 | 14 | 0 | 0 | 0 |
|
|
| (axiIn_1_writeOnly_decoder) | Axi4WriteOnlyDecoder_1 | 18 | 18 | 0 | 0 | 12 | 0 | 0 | 0 |
|
|
| errorSlave | Axi4WriteOnlyErrorSlave_1 | 5 | 5 | 0 | 0 | 2 | 0 | 0 | 0 |
|
|
| u_Axi_CDC | Axi_CDC | 407 | 279 | 128 | 0 | 309 | 0 | 0 | 0 |
|
|
| arFifo | StreamFifoCC_3 | 180 | 144 | 36 | 0 | 73 | 0 | 0 | 0 |
|
|
| (arFifo) | StreamFifoCC_3 | 174 | 138 | 36 | 0 | 61 | 0 | 0 | 0 |
|
|
| popToPushGray_buffercc | BufferCC_9_45 | 1 | 1 | 0 | 0 | 6 | 0 | 0 | 0 |
|
|
| pushToPopGray_buffercc | BufferCC_11_46 | 5 | 5 | 0 | 0 | 6 | 0 | 0 | 0 |
|
|
| awFifo | StreamFifoCC | 101 | 65 | 36 | 0 | 75 | 0 | 0 | 0 |
|
|
| (awFifo) | StreamFifoCC | 94 | 58 | 36 | 0 | 61 | 0 | 0 | 0 |
|
|
| bufferCC_12 | BufferCC_10 | 1 | 1 | 0 | 0 | 2 | 0 | 0 | 0 |
|
|
| popToPushGray_buffercc | BufferCC_9 | 2 | 2 | 0 | 0 | 6 | 0 | 0 | 0 |
|
|
| pushToPopGray_buffercc | BufferCC_11 | 4 | 4 | 0 | 0 | 6 | 0 | 0 | 0 |
|
|
| bFifo | StreamFifoCC_2 | 14 | 14 | 0 | 0 | 26 | 0 | 0 | 0 |
|
|
| (bFifo) | StreamFifoCC_2 | 7 | 7 | 0 | 0 | 12 | 0 | 0 | 0 |
|
|
| bufferCC_12 | BufferCC_5 | 1 | 1 | 0 | 0 | 2 | 0 | 0 | 0 |
|
|
| popToPushGray_buffercc | BufferCC_4 | 2 | 2 | 0 | 0 | 6 | 0 | 0 | 0 |
|
|
| pushToPopGray_buffercc | BufferCC_6 | 4 | 4 | 0 | 0 | 6 | 0 | 0 | 0 |
|
|
| rFifo | StreamFifoCC_4 | 46 | 18 | 28 | 0 | 66 | 0 | 0 | 0 |
|
|
| (rFifo) | StreamFifoCC_4 | 41 | 13 | 28 | 0 | 50 | 0 | 0 | 0 |
|
|
| popToPushGray_buffercc | BufferCC | 4 | 4 | 0 | 0 | 8 | 0 | 0 | 0 |
|
|
| pushToPopGray_buffercc | BufferCC_1 | 2 | 2 | 0 | 0 | 8 | 0 | 0 | 0 |
|
|
| wFifo | StreamFifoCC_1 | 66 | 38 | 28 | 0 | 69 | 0 | 0 | 0 |
|
|
| (wFifo) | StreamFifoCC_1 | 62 | 34 | 28 | 0 | 53 | 0 | 0 | 0 |
|
|
| popToPushGray_buffercc | BufferCC_7 | 3 | 3 | 0 | 0 | 8 | 0 | 0 | 0 |
|
|
| pushToPopGray_buffercc | BufferCC_8 | 2 | 2 | 0 | 0 | 8 | 0 | 0 | 0 |
|
|
| u_axi_axil_adapter | axi_axil_adapter | 1338 | 1338 | 0 | 0 | 161 | 0 | 0 | 0 |
|
|
| axi_axil_adapter_rd_inst | axi_axil_adapter_rd | 635 | 635 | 0 | 0 | 81 | 0 | 0 | 0 |
|
|
| axi_axil_adapter_wr_inst | axi_axil_adapter_wr | 703 | 703 | 0 | 0 | 80 | 0 | 0 | 0 |
|
|
| u_axi_dvi | axi_dvi | 284 | 284 | 0 | 0 | 211 | 0 | 0 | 0 |
|
|
| u_axi_ram | axi_wrap_ram_sp_external | 354 | 354 | 0 | 0 | 78 | 0 | 0 | 0 |
|
|
| u_axi_sram_sp | axi2sram_sp_external | 354 | 354 | 0 | 0 | 78 | 0 | 0 | 0 |
|
|
| u_axi_uart_controller | axi_uart_controller | 683 | 667 | 16 | 0 | 457 | 0 | 0 | 0 |
|
|
| AA_axi2apb_bridge_cpu | axi2apb_bridge | 250 | 250 | 0 | 0 | 120 | 0 | 0 | 0 |
|
|
| uart0 | UART_TOP | 433 | 417 | 16 | 0 | 337 | 0 | 0 | 0 |
|
|
| regs | uart_regs | 433 | 417 | 16 | 0 | 337 | 0 | 0 | 0 |
|
|
| (regs) | uart_regs | 118 | 118 | 0 | 0 | 155 | 0 | 0 | 0 |
|
|
| i_uart_sync_flops | uart_sync_flops | 3 | 3 | 0 | 0 | 2 | 0 | 0 | 0 |
|
|
| receiver | uart_receiver | 229 | 221 | 8 | 0 | 124 | 0 | 0 | 0 |
|
|
| (receiver) | uart_receiver | 68 | 68 | 0 | 0 | 54 | 0 | 0 | 0 |
|
|
| fifo_rx | uart_rfifo | 161 | 153 | 8 | 0 | 70 | 0 | 0 | 0 |
|
|
| (fifo_rx) | uart_rfifo | 143 | 143 | 0 | 0 | 62 | 0 | 0 | 0 |
|
|
| rfifo | raminfr_44 | 19 | 11 | 8 | 0 | 8 | 0 | 0 | 0 |
|
|
| transmitter | uart_transmitter | 83 | 75 | 8 | 0 | 56 | 0 | 0 | 0 |
|
|
| (transmitter) | uart_transmitter | 41 | 41 | 0 | 0 | 35 | 0 | 0 | 0 |
|
|
| fifo_tx | uart_tfifo | 43 | 35 | 8 | 0 | 21 | 0 | 0 | 0 |
|
|
| (fifo_tx) | uart_tfifo | 24 | 24 | 0 | 0 | 13 | 0 | 0 | 0 |
|
|
| tfifo | raminfr | 19 | 11 | 8 | 0 | 8 | 0 | 0 | 0 |
|
|
| u_cdma_matmul_bridge | cdma_matmul_bridge | 247 | 247 | 0 | 0 | 578 | 0 | 0 | 0 |
|
|
| u_confreg | confreg | 390 | 390 | 0 | 0 | 476 | 0 | 0 | 0 |
|
|
| (u_confreg) | confreg | 230 | 230 | 0 | 0 | 399 | 0 | 0 | 0 |
|
|
| u_digitaltube_controller | digitaltube_controller | 16 | 16 | 0 | 0 | 24 | 0 | 0 | 0 |
|
|
| u_int_ctrl | int_ctrl | 144 | 144 | 0 | 0 | 53 | 0 | 0 | 0 |
|
|
| u_cpu | core_top | 8553 | 8301 | 252 | 0 | 5591 | 0 | 20 | 0 |
|
|
| (u_cpu) | core_top | 519 | 519 | 0 | 0 | 1 | 0 | 0 | 0 |
|
|
| addr_trans | addr_trans | 2249 | 2109 | 140 | 0 | 1244 | 0 | 0 | 0 |
|
|
| (addr_trans) | addr_trans | 0 | 0 | 0 | 0 | 40 | 0 | 0 | 0 |
|
|
| tlb_entry | tlb_entry | 2249 | 2109 | 140 | 0 | 1204 | 0 | 0 | 0 |
|
|
| axi_bridge | axi_bridge | 39 | 39 | 0 | 0 | 214 | 0 | 0 | 0 |
|
|
| btb | btb | 1046 | 966 | 80 | 0 | 1611 | 0 | 0 | 0 |
|
|
| (btb) | btb | 1043 | 963 | 80 | 0 | 1611 | 0 | 0 | 0 |
|
|
| dec_btb_add_entry | decoder_5_32 | 3 | 3 | 0 | 0 | 0 | 0 | 0 | 0 |
|
|
| dcache | dcache | 553 | 521 | 32 | 0 | 146 | 0 | 10 | 0 |
|
|
| (dcache) | dcache | 87 | 55 | 32 | 0 | 138 | 0 | 0 | 0 |
|
|
| data_ram_way[0].data_ram_bank[0].u | data_bank_sram_33 | 49 | 49 | 0 | 0 | 0 | 0 | 1 | 0 |
|
|
| data_ram_way[0].data_ram_bank[1].u | data_bank_sram_34 | 17 | 17 | 0 | 0 | 0 | 0 | 1 | 0 |
|
|
| data_ram_way[0].data_ram_bank[2].u | data_bank_sram_35 | 49 | 49 | 0 | 0 | 0 | 0 | 1 | 0 |
|
|
| data_ram_way[0].data_ram_bank[3].u | data_bank_sram_36 | 51 | 51 | 0 | 0 | 0 | 0 | 1 | 0 |
|
|
| data_ram_way[1].data_ram_bank[0].u | data_bank_sram_37 | 17 | 17 | 0 | 0 | 0 | 0 | 1 | 0 |
|
|
| data_ram_way[1].data_ram_bank[1].u | data_bank_sram_38 | 49 | 49 | 0 | 0 | 0 | 0 | 1 | 0 |
|
|
| data_ram_way[1].data_ram_bank[2].u | data_bank_sram_39 | 81 | 81 | 0 | 0 | 0 | 0 | 1 | 0 |
|
|
| data_ram_way[1].data_ram_bank[3].u | data_bank_sram_40 | 54 | 54 | 0 | 0 | 0 | 0 | 1 | 0 |
|
|
| lfsr | lfsr_41 | 2 | 2 | 0 | 0 | 8 | 0 | 0 | 0 |
|
|
| tagv_ram_way[0].u | tagv_sram_42 | 62 | 62 | 0 | 0 | 0 | 0 | 1 | 0 |
|
|
| tagv_ram_way[1].u | tagv_sram_43 | 41 | 41 | 0 | 0 | 0 | 0 | 1 | 0 |
|
|
| exe_stage | exe_stage | 664 | 664 | 0 | 0 | 233 | 0 | 0 | 0 |
|
|
| (exe_stage) | exe_stage | 633 | 633 | 0 | 0 | 233 | 0 | 0 | 0 |
|
|
| u_alu | alu | 33 | 33 | 0 | 0 | 0 | 0 | 0 | 0 |
|
|
| icache | icache | 235 | 235 | 0 | 0 | 55 | 0 | 10 | 0 |
|
|
| (icache) | icache | 12 | 12 | 0 | 0 | 47 | 0 | 0 | 0 |
|
|
| data_ram_way[0].data_ram_bank[0].u | data_bank_sram | 4 | 4 | 0 | 0 | 0 | 0 | 1 | 0 |
|
|
| data_ram_way[0].data_ram_bank[1].u | data_bank_sram_25 | 3 | 3 | 0 | 0 | 0 | 0 | 1 | 0 |
|
|
| data_ram_way[0].data_ram_bank[2].u | data_bank_sram_26 | 67 | 67 | 0 | 0 | 0 | 0 | 1 | 0 |
|
|
| data_ram_way[0].data_ram_bank[3].u | data_bank_sram_27 | 3 | 3 | 0 | 0 | 0 | 0 | 1 | 0 |
|
|
| data_ram_way[1].data_ram_bank[0].u | data_bank_sram_28 | 3 | 3 | 0 | 0 | 0 | 0 | 1 | 0 |
|
|
| data_ram_way[1].data_ram_bank[1].u | data_bank_sram_29 | 3 | 3 | 0 | 0 | 0 | 0 | 1 | 0 |
|
|
| data_ram_way[1].data_ram_bank[2].u | data_bank_sram_30 | 35 | 35 | 0 | 0 | 0 | 0 | 1 | 0 |
|
|
| data_ram_way[1].data_ram_bank[3].u | data_bank_sram_31 | 4 | 4 | 0 | 0 | 0 | 0 | 1 | 0 |
|
|
| lfsr | lfsr | 2 | 2 | 0 | 0 | 8 | 0 | 0 | 0 |
|
|
| tagv_ram_way[0].u | tagv_sram | 15 | 15 | 0 | 0 | 0 | 0 | 1 | 0 |
|
|
| tagv_ram_way[1].u | tagv_sram_32 | 88 | 88 | 0 | 0 | 0 | 0 | 1 | 0 |
|
|
| id_stage | id_stage | 1050 | 1050 | 0 | 0 | 108 | 0 | 0 | 0 |
|
|
| if_stage | if_stage | 134 | 134 | 0 | 0 | 173 | 0 | 0 | 0 |
|
|
| mem_stage | mem_stage | 117 | 117 | 0 | 0 | 211 | 0 | 0 | 0 |
|
|
| u_csr | csr | 200 | 200 | 0 | 0 | 663 | 0 | 0 | 0 |
|
|
| u_div | div | 142 | 142 | 0 | 0 | 107 | 0 | 0 | 0 |
|
|
| u_mul | mul | 934 | 934 | 0 | 0 | 592 | 0 | 0 | 0 |
|
|
| wb_stage | wb_stage | 681 | 681 | 0 | 0 | 233 | 0 | 0 | 0 |
|
|
| u_fft_mlkem_axi_slave | fft_mlkem_axi_slave | 45975 | 44866 | 0 | 1109 | 26955 | 10 | 10 | 0 |
|
|
| (u_fft_mlkem_axi_slave) | fft_mlkem_axi_slave | 0 | 0 | 0 | 0 | 4 | 0 | 0 | 0 |
|
|
| u_fft_controller | fft_controller | 6949 | 5909 | 0 | 1040 | 1083 | 8 | 4 | 0 |
|
|
| (u_fft_controller) | fft_controller | 118 | 118 | 0 | 0 | 100 | 0 | 0 | 0 |
|
|
| u_FFT | FFT | 6783 | 5743 | 0 | 1040 | 983 | 8 | 0 | 0 |
|
|
| SU1 | SdfUnit | 2145 | 1377 | 0 | 768 | 197 | 2 | 0 | 0 |
|
|
| (SU1) | SdfUnit | 39 | 39 | 0 | 0 | 133 | 0 | 0 | 0 |
|
|
| BF1 | Butterfly_21 | 16 | 16 | 0 | 0 | 0 | 0 | 0 | 0 |
|
|
| BF2 | Butterfly__parameterized0_22 | 32 | 32 | 0 | 0 | 0 | 0 | 0 | 0 |
|
|
| DB1 | DelayBuffer | 624 | 112 | 0 | 512 | 32 | 0 | 0 | 0 |
|
|
| DB2 | DelayBuffer__parameterized0 | 320 | 64 | 0 | 256 | 32 | 0 | 0 | 0 |
|
|
| MU | Multiply_23 | 611 | 611 | 0 | 0 | 0 | 0 | 0 | 0 |
|
|
| TW | Twiddle_24 | 543 | 543 | 0 | 0 | 0 | 2 | 0 | 0 |
|
|
| SU2 | SdfUnit__parameterized0 | 1566 | 1374 | 0 | 192 | 197 | 2 | 0 | 0 |
|
|
| (SU2) | SdfUnit__parameterized0 | 38 | 38 | 0 | 0 | 133 | 0 | 0 | 0 |
|
|
| BF1 | Butterfly_17 | 16 | 16 | 0 | 0 | 0 | 0 | 0 | 0 |
|
|
| BF2 | Butterfly__parameterized0_18 | 32 | 32 | 0 | 0 | 0 | 0 | 0 | 0 |
|
|
| DB1 | DelayBuffer__parameterized1 | 240 | 112 | 0 | 128 | 32 | 0 | 0 | 0 |
|
|
| DB2 | DelayBuffer__parameterized2 | 128 | 64 | 0 | 64 | 32 | 0 | 0 | 0 |
|
|
| MU | Multiply_19 | 611 | 611 | 0 | 0 | 0 | 0 | 0 | 0 |
|
|
| TW | Twiddle_20 | 541 | 541 | 0 | 0 | 0 | 2 | 0 | 0 |
|
|
| SU3 | SdfUnit__parameterized1 | 1416 | 1368 | 0 | 48 | 197 | 2 | 0 | 0 |
|
|
| (SU3) | SdfUnit__parameterized1 | 35 | 35 | 0 | 0 | 133 | 0 | 0 | 0 |
|
|
| BF1 | Butterfly_13 | 16 | 16 | 0 | 0 | 0 | 0 | 0 | 0 |
|
|
| BF2 | Butterfly__parameterized0_14 | 32 | 32 | 0 | 0 | 0 | 0 | 0 | 0 |
|
|
| DB1 | DelayBuffer__parameterized3 | 144 | 112 | 0 | 32 | 32 | 0 | 0 | 0 |
|
|
| DB2 | DelayBuffer__parameterized4 | 80 | 64 | 0 | 16 | 32 | 0 | 0 | 0 |
|
|
| MU | Multiply_15 | 610 | 610 | 0 | 0 | 0 | 0 | 0 | 0 |
|
|
| TW | Twiddle_16 | 539 | 539 | 0 | 0 | 0 | 2 | 0 | 0 |
|
|
| SU4 | SdfUnit__parameterized2 | 1398 | 1366 | 0 | 32 | 197 | 2 | 0 | 0 |
|
|
| (SU4) | SdfUnit__parameterized2 | 34 | 34 | 0 | 0 | 133 | 0 | 0 | 0 |
|
|
| BF1 | Butterfly_11 | 16 | 16 | 0 | 0 | 0 | 0 | 0 | 0 |
|
|
| BF2 | Butterfly__parameterized0_12 | 32 | 32 | 0 | 0 | 0 | 0 | 0 | 0 |
|
|
| DB1 | DelayBuffer__parameterized5 | 128 | 112 | 0 | 16 | 32 | 0 | 0 | 0 |
|
|
| DB2 | DelayBuffer__parameterized6 | 80 | 64 | 0 | 16 | 32 | 0 | 0 | 0 |
|
|
| MU | Multiply | 612 | 612 | 0 | 0 | 0 | 0 | 0 | 0 |
|
|
| TW | Twiddle | 536 | 536 | 0 | 0 | 0 | 2 | 0 | 0 |
|
|
| SU5 | SdfUnit__parameterized3 | 258 | 258 | 0 | 0 | 195 | 0 | 0 | 0 |
|
|
| (SU5) | SdfUnit__parameterized3 | 34 | 34 | 0 | 0 | 99 | 0 | 0 | 0 |
|
|
| BF1 | Butterfly | 16 | 16 | 0 | 0 | 0 | 0 | 0 | 0 |
|
|
| BF2 | Butterfly__parameterized0 | 32 | 32 | 0 | 0 | 0 | 0 | 0 | 0 |
|
|
| DB1 | DelayBuffer__parameterized7 | 112 | 112 | 0 | 0 | 64 | 0 | 0 | 0 |
|
|
| DB2 | DelayBuffer__parameterized8 | 64 | 64 | 0 | 0 | 32 | 0 | 0 | 0 |
|
|
| u_in0 | my_bram0 | 3 | 3 | 0 | 0 | 0 | 0 | 1 | 0 |
|
|
| u_in1 | my_bram0_8 | 2 | 2 | 0 | 0 | 0 | 0 | 1 | 0 |
|
|
| u_out0 | my_bram0_9 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 |
|
|
| u_out1 | my_bram0_10 | 45 | 45 | 0 | 0 | 0 | 0 | 1 | 0 |
|
|
| u_mlkem_axi_slave | mlkem_axi_slave | 39029 | 38960 | 0 | 69 | 25868 | 2 | 6 | 0 |
|
|
| (u_mlkem_axi_slave) | mlkem_axi_slave | 1332 | 1332 | 0 | 0 | 1060 | 0 | 0 | 0 |
|
|
| u_mlkem | mlkem_top | 37700 | 37631 | 0 | 69 | 24808 | 2 | 6 | 0 |
|
|
| (u_mlkem) | mlkem_top | 2754 | 2754 | 0 | 0 | 4949 | 0 | 0 | 0 |
|
|
| u_bank_a | sd_bram__parameterized0 | 51 | 51 | 0 | 0 | 0 | 1 | 1 | 0 |
|
|
| u_bank_se | sd_bram__parameterized1 | 70 | 70 | 0 | 0 | 0 | 1 | 0 | 0 |
|
|
| u_bank_t | sd_bram__parameterized2 | 683 | 683 | 0 | 0 | 0 | 0 | 1 | 0 |
|
|
| u_c_in_bram | sd_bram | 1312 | 1312 | 0 | 0 | 0 | 0 | 1 | 0 |
|
|
| u_cbd | sample_cbd_sync_shared | 2753 | 2753 | 0 | 0 | 3186 | 0 | 0 | 0 |
|
|
| u_comp | comp_decomp_sync | 465 | 464 | 0 | 1 | 323 | 0 | 0 | 0 |
|
|
| u_ct_bram | sd_bram_4 | 12 | 12 | 0 | 0 | 0 | 0 | 1 | 0 |
|
|
| u_dkp_bram | sd_bram_5 | 82 | 82 | 0 | 0 | 0 | 0 | 1 | 0 |
|
|
| u_ek_bram | sd_bram_6 | 2006 | 2006 | 0 | 0 | 0 | 0 | 1 | 0 |
|
|
| u_keccak | keccak_core | 5271 | 5271 | 0 | 0 | 1606 | 0 | 0 | 0 |
|
|
| u_ntt | ntt_core | 9893 | 9850 | 0 | 43 | 3869 | 0 | 0 | 0 |
|
|
| (u_ntt) | ntt_core | 7376 | 7360 | 0 | 16 | 3366 | 0 | 0 | 0 |
|
|
| u_bf | butterfly_unit_pipe | 2256 | 2230 | 0 | 26 | 286 | 0 | 0 | 0 |
|
|
| (u_bf) | butterfly_unit_pipe | 58 | 33 | 0 | 25 | 75 | 0 | 0 | 0 |
|
|
| u_barrett | barrett_mul_pipe_7 | 2198 | 2197 | 0 | 1 | 211 | 0 | 0 | 0 |
|
|
| u_scl | barrett_mul_pipe | 263 | 262 | 0 | 1 | 217 | 0 | 0 | 0 |
|
|
| u_pmul | poly_mul_sync | 8281 | 8256 | 0 | 25 | 6818 | 0 | 0 | 0 |
|
|
| (u_pmul) | poly_mul_sync | 6834 | 6834 | 0 | 0 | 6355 | 0 | 0 | 0 |
|
|
| u_bc | basecase_mul_pipe | 1447 | 1422 | 0 | 25 | 463 | 0 | 0 | 0 |
|
|
| u_sha3 | sha3_top_shared | 1975 | 1975 | 0 | 0 | 2388 | 0 | 0 | 0 |
|
|
| u_snt | sample_ntt_sync_shared | 2108 | 2108 | 0 | 0 | 1669 | 0 | 0 | 0 |
|
|
| u_matmul_axi_slave | matmul_axi_slave | 10204 | 10022 | 176 | 6 | 3239 | 0 | 0 | 0 |
|
|
| (u_matmul_axi_slave) | matmul_axi_slave | 6085 | 5903 | 176 | 6 | 2471 | 0 | 0 | 0 |
|
|
| mult_inst[0].u_mult | pipelined_mult_32x32 | 1061 | 1061 | 0 | 0 | 192 | 0 | 0 | 0 |
|
|
| mult_inst[1].u_mult | pipelined_mult_32x32_1 | 998 | 998 | 0 | 0 | 192 | 0 | 0 | 0 |
|
|
| mult_inst[2].u_mult | pipelined_mult_32x32_2 | 1063 | 1063 | 0 | 0 | 192 | 0 | 0 | 0 |
|
|
| mult_inst[3].u_mult | pipelined_mult_32x32_3 | 997 | 997 | 0 | 0 | 192 | 0 | 0 | 0 |
|
|
| u_snix_axil_cdma_mux_8ch | snix_axil_cdma_mux | 1558 | 1558 | 0 | 0 | 1476 | 0 | 1 | 0 |
|
|
| (u_snix_axil_cdma_mux_8ch) | snix_axil_cdma_mux | 587 | 587 | 0 | 0 | 1180 | 0 | 0 | 0 |
|
|
| u_core_engine | snix_axi_mm2mm | 974 | 974 | 0 | 0 | 296 | 0 | 1 | 0 |
|
|
| (u_core_engine) | snix_axi_mm2mm | 700 | 700 | 0 | 0 | 243 | 0 | 0 | 0 |
|
|
| axis_fifo_u0 | snix_axis_fifo | 274 | 274 | 0 | 0 | 53 | 0 | 1 | 0 |
|
|
| u_fifo | snix_sync_fifo | 274 | 274 | 0 | 0 | 53 | 0 | 1 | 0 |
|
|
+------------------------------------------+------------------------------+------------+------------+---------+------+-------+--------+--------+--------------+
|
|
* Note: The sum of lower-level cells may be larger than their parent cells total, due to cross-hierarchy LUT combining
|
|
|
|
|