69 lines
2.4 KiB
Plaintext
69 lines
2.4 KiB
Plaintext
Copyright 1986-2019 Xilinx, Inc. All Rights Reserved.
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| Tool Version : Vivado v.2019.2 (lin64) Build 2708876 Wed Nov 6 21:39:14 MST 2019
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| Date : Fri Jul 10 04:14:54 2026
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| Host : fedora running 64-bit unknown
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| Command : report_clocks -file /home/fallensigh/Dev/ciciec2026_loongson_regional/fpga/vivado_reports_nodsp/clocks.rpt
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| Design : soc_top
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| Device : 7a200t-fbg676
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| Speed File : -1 PRODUCTION 1.23 2018-06-13
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Clock Report
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Attributes
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P: Propagated
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G: Generated
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A: Auto-derived
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R: Renamed
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V: Virtual
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I: Inverted
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S: Pin phase-shifted with Latency mode
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Clock Period(ns) Waveform(ns) Attributes Sources
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clk 20.000 {0.000 10.000} P {clk}
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clkfbout_clk_pll 20.000 {0.000 10.000} P,G,A {pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKFBOUT}
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cpu_clk 30.323 {0.000 15.161} P,G,A,R {pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0}
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sys_clk 20.000 {0.000 10.000} P,G,A,R {pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1}
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====================================================
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Generated Clocks
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Generated Clock : clkfbout_clk_pll
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Master Source : pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1
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Master Clock : clk
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Multiply By : 1
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Generated Sources : {pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKFBOUT}
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Generated Clock : cpu_clk
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Master Source : pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1
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Master Clock : clk
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Edges : {1 2 3}
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Edge Shifts(ns) : {0.000 5.161 10.323}
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Generated Sources : {pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0}
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Generated Clock : sys_clk
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Master Source : pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1
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Master Clock : clk
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Multiply By : 1
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Generated Sources : {pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1}
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User Uncertainty
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User Jitter
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Clock Jitter(ns)
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clk 0.200
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