26 lines
1.9 KiB
Plaintext
26 lines
1.9 KiB
Plaintext
Copyright 1986-2019 Xilinx, Inc. All Rights Reserved.
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| Tool Version : Vivado v.2019.2 (lin64) Build 2708876 Wed Nov 6 21:39:14 MST 2019
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| Date : Fri Jul 10 04:14:55 2026
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| Host : fedora running 64-bit unknown
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| Command : report_clock_interaction -file /home/fallensigh/Dev/ciciec2026_loongson_regional/fpga/vivado_reports_nodsp/clock_interaction.rpt
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| Design : soc_top
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| Device : 7a200t-fbg676
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| Speed File : -1 PRODUCTION 1.23 2018-06-13
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Clock Interaction Report
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Clock Interaction Table
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-----------------------
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WNS TNS Failing TNS Total WNS Path Clock-Pair Inter-Clock
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From Clock To Clock Clock Edges WNS(ns) TNS(ns) Endpoints Endpoints Requirement(ns) Classification Constraints
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---------------- ---------------- ----------- ------- ------- ----------- ----------- --------------- ------------------- -------------------
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cpu_clk cpu_clk rise - rise 1.51 0.00 0 17264 30.32 Clean Timed
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cpu_clk sys_clk 0 154 Ignored Asynchronous Groups
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sys_clk cpu_clk 0 59 Ignored Asynchronous Groups
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sys_clk sys_clk rise - rise 0.15 0.00 0 96069 20.00 Clean Timed
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