Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. -------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- | Tool Version : Vivado v.2019.2 (lin64) Build 2708876 Wed Nov 6 21:39:14 MST 2019 | Date : Wed Jul 8 02:57:56 2026 | Host : fedora running 64-bit unknown | Command : report_timing_summary -delay_type min -report_unconstrained -check_timing_verbose -max_paths 50 -file /home/fallensigh/vivado_reports_withdsp/timing_summary_hold_full.rpt | Design : soc_top | Device : 7a200t-fbg676 | Speed File : -1 PRODUCTION 1.23 2018-06-13 -------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- Timing Summary Report ------------------------------------------------------------------------------------------------ | Timer Settings | -------------- ------------------------------------------------------------------------------------------------ Enable Multi Corner Analysis : Yes Enable Pessimism Removal : Yes Pessimism Removal Resolution : Nearest Common Node Enable Input Delay Default Clock : No Enable Preset / Clear Arcs : No Disable Flight Delays : No Ignore I/O Paths : No Timing Early Launch at Borrowing Latches : No Borrow Time for Max Delay Exceptions : Yes Merge Timing Exceptions : Yes Corner Analyze Analyze Name Max Paths Min Paths ------ --------- --------- Slow Yes Yes Fast Yes Yes check_timing report Table of Contents ----------------- 1. checking no_clock 2. checking constant_clock 3. checking pulse_width_clock 4. checking unconstrained_internal_endpoints 5. checking no_input_delay 6. checking no_output_delay 7. checking multiple_clock 8. checking generated_clocks 9. checking loops 10. checking partial_input_delay 11. checking partial_output_delay 12. checking latch_loops 1. checking no_clock -------------------- There are 0 register/latch pins with no clock. 2. checking constant_clock -------------------------- There are 0 register/latch pins with constant_clock. 3. checking pulse_width_clock ----------------------------- There are 0 register/latch pins which need pulse_width check 4. checking unconstrained_internal_endpoints -------------------------------------------- There are 0 pins that are not constrained for maximum delay. There are 0 pins that are not constrained for maximum delay due to constant clock. 5. checking no_input_delay -------------------------- There are 38 input ports with no input delay specified. (HIGH) UART_RX UART_TX dip_sw[0] dip_sw[10] dip_sw[11] dip_sw[12] dip_sw[13] dip_sw[14] dip_sw[15] dip_sw[16] dip_sw[17] dip_sw[18] dip_sw[19] dip_sw[1] dip_sw[20] dip_sw[21] dip_sw[22] dip_sw[23] dip_sw[24] dip_sw[25] dip_sw[26] dip_sw[27] dip_sw[28] dip_sw[29] dip_sw[2] dip_sw[30] dip_sw[31] dip_sw[3] dip_sw[4] dip_sw[5] dip_sw[6] dip_sw[7] dip_sw[8] dip_sw[9] touch_btn[0] touch_btn[1] touch_btn[2] touch_btn[3] There are 0 input ports with no input delay but user has a false path constraint. 6. checking no_output_delay --------------------------- There are 40 ports with no output delay specified. (HIGH) UART_RX UART_TX dpy0[0] dpy0[1] dpy0[2] dpy0[3] dpy0[4] dpy0[5] dpy0[6] dpy0[7] dpy1[0] dpy1[1] dpy1[2] dpy1[3] dpy1[4] dpy1[5] dpy1[6] dpy1[7] leds[0] leds[10] leds[11] leds[12] leds[13] leds[14] leds[15] leds[1] leds[2] leds[3] leds[4] leds[5] leds[6] leds[7] leds[8] leds[9] video_de video_hsync video_red[0] video_red[1] video_red[2] video_vsync There are 0 ports with no output delay but user has a false path constraint There are 0 ports with no output delay but with a timing clock defined on it or propagating through it 7. checking multiple_clock -------------------------- There are 0 register/latch pins with multiple clocks. 8. checking generated_clocks ---------------------------- There are 0 generated clocks that are not connected to a clock source. 9. checking loops ----------------- There are 0 combinational loops in the design. 10. checking partial_input_delay -------------------------------- There are 0 input ports with partial input delay specified. 11. checking partial_output_delay --------------------------------- There are 0 ports with partial output delay specified. 12. checking latch_loops ------------------------ There are 0 combinational latch loops in the design through latch input ------------------------------------------------------------------------------------------------ | Design Timing Summary | --------------------- ------------------------------------------------------------------------------------------------ WHS(ns) THS(ns) THS Failing Endpoints THS Total Endpoints WPWS(ns) TPWS(ns) TPWS Failing Endpoints TPWS Total Endpoints ------- ------- --------------------- ------------------- -------- -------- ---------------------- -------------------- 0.022 0.000 0 115919 7.000 0.000 0 41847 All user specified timing constraints are met. ------------------------------------------------------------------------------------------------ | Clock Summary | ------------- ------------------------------------------------------------------------------------------------ Clock Waveform(ns) Period(ns) Frequency(MHz) ----- ------------ ---------- -------------- clk {0.000 10.000} 20.000 50.000 clkfbout_clk_pll {0.000 10.000} 20.000 50.000 cpu_clk {0.000 15.161} 30.323 32.979 mlkem_clk_clk_pll {0.000 20.000} 40.000 25.000 sys_clk {0.000 10.000} 20.000 50.000 ------------------------------------------------------------------------------------------------ | Intra Clock Table | ----------------- ------------------------------------------------------------------------------------------------ Clock WHS(ns) THS(ns) THS Failing Endpoints THS Total Endpoints WPWS(ns) TPWS(ns) TPWS Failing Endpoints TPWS Total Endpoints ----- ------- ------- --------------------- ------------------- -------- -------- ---------------------- -------------------- clk 7.000 0.000 0 1 clkfbout_clk_pll 17.845 0.000 0 3 cpu_clk 0.061 0.000 0 17197 13.911 0.000 0 6486 mlkem_clk_clk_pll 0.035 0.000 0 49560 18.750 0.000 0 25777 sys_clk 0.045 0.000 0 22846 8.750 0.000 0 9580 ------------------------------------------------------------------------------------------------ | Inter Clock Table | ----------------- ------------------------------------------------------------------------------------------------ From Clock To Clock WHS(ns) THS(ns) THS Failing Endpoints THS Total Endpoints ---------- -------- ------- ------- --------------------- ------------------- sys_clk mlkem_clk_clk_pll 0.022 0.000 0 108 mlkem_clk_clk_pll sys_clk 0.035 0.000 0 59 ------------------------------------------------------------------------------------------------ | Other Path Groups Table | ----------------------- ------------------------------------------------------------------------------------------------ Path Group From Clock To Clock WHS(ns) THS(ns) THS Failing Endpoints THS Total Endpoints ---------- ---------- -------- ------- ------- --------------------- ------------------- **async_default** cpu_clk cpu_clk 0.746 0.000 0 67 **async_default** mlkem_clk_clk_pll mlkem_clk_clk_pll 0.518 0.000 0 25322 **async_default** sys_clk mlkem_clk_clk_pll 4.195 0.000 0 4 **async_default** mlkem_clk_clk_pll sys_clk 0.445 0.000 0 2 **async_default** sys_clk sys_clk 0.798 0.000 0 886 ------------------------------------------------------------------------------------------------ | User Ignored Path Table | ----------------------- ------------------------------------------------------------------------------------------------ Path Group From Clock To Clock ---------- ---------- -------- (none) sys_clk cpu_clk (none) cpu_clk sys_clk ------------------------------------------------------------------------------------------------ | Unconstrained Path Table | ------------------------ ------------------------------------------------------------------------------------------------ Path Group From Clock To Clock ---------- ---------- -------- (none) clkfbout_clk_pll (none) sys_clk (none) sys_clk ------------------------------------------------------------------------------------------------ | Timing Details | -------------- ------------------------------------------------------------------------------------------------ --------------------------------------------------------------------------------------------------- From Clock: clk To Clock: clk Setup : NA Failing Endpoints, Worst Slack NA , Total Violation NA Hold : NA Failing Endpoints, Worst Slack NA , Total Violation NA PW : 0 Failing Endpoints, Worst Slack 7.000ns, Total Violation 0.000ns --------------------------------------------------------------------------------------------------- Pulse Width Checks -------------------------------------------------------------------------------------- Clock Name: clk Waveform(ns): { 0.000 10.000 } Period(ns): 20.000 Sources: { clk } Check Type Corner Lib Pin Reference Pin Required(ns) Actual(ns) Slack(ns) Location Pin Min Period n/a PLLE2_ADV/CLKIN1 n/a 1.249 20.000 18.751 PLLE2_ADV_X0Y3 pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1 Max Period n/a PLLE2_ADV/CLKIN1 n/a 52.633 20.000 32.633 PLLE2_ADV_X0Y3 pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1 Low Pulse Width Slow PLLE2_ADV/CLKIN1 n/a 3.000 10.000 7.000 PLLE2_ADV_X0Y3 pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1 Low Pulse Width Fast PLLE2_ADV/CLKIN1 n/a 3.000 10.000 7.000 PLLE2_ADV_X0Y3 pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1 High Pulse Width Fast PLLE2_ADV/CLKIN1 n/a 3.000 10.000 7.000 PLLE2_ADV_X0Y3 pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1 High Pulse Width Slow PLLE2_ADV/CLKIN1 n/a 3.000 10.000 7.000 PLLE2_ADV_X0Y3 pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1 --------------------------------------------------------------------------------------------------- From Clock: clkfbout_clk_pll To Clock: clkfbout_clk_pll Setup : NA Failing Endpoints, Worst Slack NA , Total Violation NA Hold : NA Failing Endpoints, Worst Slack NA , Total Violation NA PW : 0 Failing Endpoints, Worst Slack 17.845ns, Total Violation 0.000ns --------------------------------------------------------------------------------------------------- Pulse Width Checks -------------------------------------------------------------------------------------- Clock Name: clkfbout_clk_pll Waveform(ns): { 0.000 10.000 } Period(ns): 20.000 Sources: { pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKFBOUT } Check Type Corner Lib Pin Reference Pin Required(ns) Actual(ns) Slack(ns) Location Pin Min Period n/a BUFG/I n/a 2.155 20.000 17.845 BUFGCTRL_X0Y19 pll_clk.u_clk_pll/inst/clkf_buf/I Min Period n/a PLLE2_ADV/CLKFBOUT n/a 1.249 20.000 18.751 PLLE2_ADV_X0Y3 pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKFBOUT Min Period n/a PLLE2_ADV/CLKFBIN n/a 1.249 20.000 18.751 PLLE2_ADV_X0Y3 pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKFBIN Max Period n/a PLLE2_ADV/CLKFBIN n/a 52.633 20.000 32.633 PLLE2_ADV_X0Y3 pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKFBIN Max Period n/a PLLE2_ADV/CLKFBOUT n/a 160.000 20.000 140.000 PLLE2_ADV_X0Y3 pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKFBOUT --------------------------------------------------------------------------------------------------- From Clock: cpu_clk To Clock: cpu_clk Setup : NA Failing Endpoints, Worst Slack NA , Total Violation NA Hold : 0 Failing Endpoints, Worst Slack 0.061ns, Total Violation 0.000ns PW : 0 Failing Endpoints, Worst Slack 13.911ns, Total Violation 0.000ns --------------------------------------------------------------------------------------------------- Min Delay Paths -------------------------------------------------------------------------------------- Slack (MET) : 0.061ns (arrival time - required time) Source: u_cpu/u_csr/csr_tlbelo1_reg[14]/C (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Destination: u_cpu/addr_trans/tlb_entry/tlb_ppn1_reg_r3_0_31_6_11/RAMA/I (rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Path Group: cpu_clk Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) Data Path Delay: 0.221ns (logic 0.141ns (63.734%) route 0.080ns (36.266%)) Logic Levels: 0 Clock Path Skew: 0.013ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.275ns Source Clock Delay (SCD): -0.508ns Clock Pessimism Removal (CPR): 0.220ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 0.755 -0.508 u_cpu/u_csr/cpu_clk SLICE_X23Y28 FDRE r u_cpu/u_csr/csr_tlbelo1_reg[14]/C ------------------------------------------------------------------- ------------------- SLICE_X23Y28 FDRE (Prop_fdre_C_Q) 0.141 -0.367 r u_cpu/u_csr/csr_tlbelo1_reg[14]/Q net (fo=4, routed) 0.080 -0.287 u_cpu/addr_trans/tlb_entry/tlb_ppn1_reg_r3_0_31_6_11/DIA0 SLICE_X22Y28 RAMD32 r u_cpu/addr_trans/tlb_entry/tlb_ppn1_reg_r3_0_31_6_11/RAMA/I ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 1.033 -0.275 u_cpu/addr_trans/tlb_entry/tlb_ppn1_reg_r3_0_31_6_11/WCLK SLICE_X22Y28 RAMD32 r u_cpu/addr_trans/tlb_entry/tlb_ppn1_reg_r3_0_31_6_11/RAMA/CLK clock pessimism -0.220 -0.495 SLICE_X22Y28 RAMD32 (Hold_ramd32_CLK_I) 0.147 -0.348 u_cpu/addr_trans/tlb_entry/tlb_ppn1_reg_r3_0_31_6_11/RAMA ------------------------------------------------------------------- required time 0.348 arrival time -0.287 ------------------------------------------------------------------- slack 0.061 Slack (MET) : 0.076ns (arrival time - required time) Source: u_cpu/u_csr/csr_tlbelo1_reg[26]/C (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Destination: u_cpu/addr_trans/tlb_entry/tlb_ppn1_reg_r3_0_31_18_19/RAMA/I (rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Path Group: cpu_clk Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) Data Path Delay: 0.236ns (logic 0.141ns (59.832%) route 0.095ns (40.168%)) Logic Levels: 0 Clock Path Skew: 0.013ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.279ns Source Clock Delay (SCD): -0.511ns Clock Pessimism Removal (CPR): 0.219ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 0.752 -0.511 u_cpu/u_csr/cpu_clk SLICE_X23Y25 FDRE r u_cpu/u_csr/csr_tlbelo1_reg[26]/C ------------------------------------------------------------------- ------------------- SLICE_X23Y25 FDRE (Prop_fdre_C_Q) 0.141 -0.370 r u_cpu/u_csr/csr_tlbelo1_reg[26]/Q net (fo=4, routed) 0.095 -0.275 u_cpu/addr_trans/tlb_entry/tlb_ppn1_reg_r3_0_31_18_19/DIA0 SLICE_X22Y25 RAMD32 r u_cpu/addr_trans/tlb_entry/tlb_ppn1_reg_r3_0_31_18_19/RAMA/I ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 1.029 -0.279 u_cpu/addr_trans/tlb_entry/tlb_ppn1_reg_r3_0_31_18_19/WCLK SLICE_X22Y25 RAMD32 r u_cpu/addr_trans/tlb_entry/tlb_ppn1_reg_r3_0_31_18_19/RAMA/CLK clock pessimism -0.219 -0.498 SLICE_X22Y25 RAMD32 (Hold_ramd32_CLK_I) 0.147 -0.351 u_cpu/addr_trans/tlb_entry/tlb_ppn1_reg_r3_0_31_18_19/RAMA ------------------------------------------------------------------- required time 0.351 arrival time -0.275 ------------------------------------------------------------------- slack 0.076 Slack (MET) : 0.095ns (arrival time - required time) Source: u_cpu/wb_stage/ms_to_ws_bus_r_reg[66]/C (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Destination: u_regfile/rf_reg_r2_0_31_30_31/RAMA/WADR2 (rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Path Group: cpu_clk Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) Data Path Delay: 0.363ns (logic 0.141ns (38.849%) route 0.222ns (61.151%)) Logic Levels: 0 Clock Path Skew: 0.014ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.269ns Source Clock Delay (SCD): -0.501ns Clock Pessimism Removal (CPR): 0.218ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 0.762 -0.501 u_cpu/wb_stage/cpu_clk SLICE_X13Y17 FDRE r u_cpu/wb_stage/ms_to_ws_bus_r_reg[66]/C ------------------------------------------------------------------- ------------------- SLICE_X13Y17 FDRE (Prop_fdre_C_Q) 0.141 -0.360 r u_cpu/wb_stage/ms_to_ws_bus_r_reg[66]/Q net (fo=194, routed) 0.222 -0.138 u_regfile/rf_reg_r2_0_31_30_31/ADDRD2 SLICE_X14Y17 RAMD32 r u_regfile/rf_reg_r2_0_31_30_31/RAMA/WADR2 ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 1.039 -0.269 u_regfile/rf_reg_r2_0_31_30_31/WCLK SLICE_X14Y17 RAMD32 r u_regfile/rf_reg_r2_0_31_30_31/RAMA/CLK clock pessimism -0.218 -0.487 SLICE_X14Y17 RAMD32 (Hold_ramd32_CLK_WADR2) 0.254 -0.233 u_regfile/rf_reg_r2_0_31_30_31/RAMA ------------------------------------------------------------------- required time 0.233 arrival time -0.138 ------------------------------------------------------------------- slack 0.095 Slack (MET) : 0.095ns (arrival time - required time) Source: u_cpu/wb_stage/ms_to_ws_bus_r_reg[66]/C (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Destination: u_regfile/rf_reg_r2_0_31_30_31/RAMA_D1/WADR2 (rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Path Group: cpu_clk Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) Data Path Delay: 0.363ns (logic 0.141ns (38.849%) route 0.222ns (61.151%)) Logic Levels: 0 Clock Path Skew: 0.014ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.269ns Source Clock Delay (SCD): -0.501ns Clock Pessimism Removal (CPR): 0.218ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 0.762 -0.501 u_cpu/wb_stage/cpu_clk SLICE_X13Y17 FDRE r u_cpu/wb_stage/ms_to_ws_bus_r_reg[66]/C ------------------------------------------------------------------- ------------------- SLICE_X13Y17 FDRE (Prop_fdre_C_Q) 0.141 -0.360 r u_cpu/wb_stage/ms_to_ws_bus_r_reg[66]/Q net (fo=194, routed) 0.222 -0.138 u_regfile/rf_reg_r2_0_31_30_31/ADDRD2 SLICE_X14Y17 RAMD32 r u_regfile/rf_reg_r2_0_31_30_31/RAMA_D1/WADR2 ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 1.039 -0.269 u_regfile/rf_reg_r2_0_31_30_31/WCLK SLICE_X14Y17 RAMD32 r u_regfile/rf_reg_r2_0_31_30_31/RAMA_D1/CLK clock pessimism -0.218 -0.487 SLICE_X14Y17 RAMD32 (Hold_ramd32_CLK_WADR2) 0.254 -0.233 u_regfile/rf_reg_r2_0_31_30_31/RAMA_D1 ------------------------------------------------------------------- required time 0.233 arrival time -0.138 ------------------------------------------------------------------- slack 0.095 Slack (MET) : 0.095ns (arrival time - required time) Source: u_cpu/wb_stage/ms_to_ws_bus_r_reg[66]/C (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Destination: u_regfile/rf_reg_r2_0_31_30_31/RAMB/WADR2 (rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Path Group: cpu_clk Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) Data Path Delay: 0.363ns (logic 0.141ns (38.849%) route 0.222ns (61.151%)) Logic Levels: 0 Clock Path Skew: 0.014ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.269ns Source Clock Delay (SCD): -0.501ns Clock Pessimism Removal (CPR): 0.218ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 0.762 -0.501 u_cpu/wb_stage/cpu_clk SLICE_X13Y17 FDRE r u_cpu/wb_stage/ms_to_ws_bus_r_reg[66]/C ------------------------------------------------------------------- ------------------- SLICE_X13Y17 FDRE (Prop_fdre_C_Q) 0.141 -0.360 r u_cpu/wb_stage/ms_to_ws_bus_r_reg[66]/Q net (fo=194, routed) 0.222 -0.138 u_regfile/rf_reg_r2_0_31_30_31/ADDRD2 SLICE_X14Y17 RAMD32 r u_regfile/rf_reg_r2_0_31_30_31/RAMB/WADR2 ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 1.039 -0.269 u_regfile/rf_reg_r2_0_31_30_31/WCLK SLICE_X14Y17 RAMD32 r u_regfile/rf_reg_r2_0_31_30_31/RAMB/CLK clock pessimism -0.218 -0.487 SLICE_X14Y17 RAMD32 (Hold_ramd32_CLK_WADR2) 0.254 -0.233 u_regfile/rf_reg_r2_0_31_30_31/RAMB ------------------------------------------------------------------- required time 0.233 arrival time -0.138 ------------------------------------------------------------------- slack 0.095 Slack (MET) : 0.095ns (arrival time - required time) Source: u_cpu/wb_stage/ms_to_ws_bus_r_reg[66]/C (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Destination: u_regfile/rf_reg_r2_0_31_30_31/RAMB_D1/WADR2 (rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Path Group: cpu_clk Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) Data Path Delay: 0.363ns (logic 0.141ns (38.849%) route 0.222ns (61.151%)) Logic Levels: 0 Clock Path Skew: 0.014ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.269ns Source Clock Delay (SCD): -0.501ns Clock Pessimism Removal (CPR): 0.218ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 0.762 -0.501 u_cpu/wb_stage/cpu_clk SLICE_X13Y17 FDRE r u_cpu/wb_stage/ms_to_ws_bus_r_reg[66]/C ------------------------------------------------------------------- ------------------- SLICE_X13Y17 FDRE (Prop_fdre_C_Q) 0.141 -0.360 r u_cpu/wb_stage/ms_to_ws_bus_r_reg[66]/Q net (fo=194, routed) 0.222 -0.138 u_regfile/rf_reg_r2_0_31_30_31/ADDRD2 SLICE_X14Y17 RAMD32 r u_regfile/rf_reg_r2_0_31_30_31/RAMB_D1/WADR2 ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 1.039 -0.269 u_regfile/rf_reg_r2_0_31_30_31/WCLK SLICE_X14Y17 RAMD32 r u_regfile/rf_reg_r2_0_31_30_31/RAMB_D1/CLK clock pessimism -0.218 -0.487 SLICE_X14Y17 RAMD32 (Hold_ramd32_CLK_WADR2) 0.254 -0.233 u_regfile/rf_reg_r2_0_31_30_31/RAMB_D1 ------------------------------------------------------------------- required time 0.233 arrival time -0.138 ------------------------------------------------------------------- slack 0.095 Slack (MET) : 0.095ns (arrival time - required time) Source: u_cpu/wb_stage/ms_to_ws_bus_r_reg[66]/C (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Destination: u_regfile/rf_reg_r2_0_31_30_31/RAMC/WADR2 (rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Path Group: cpu_clk Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) Data Path Delay: 0.363ns (logic 0.141ns (38.849%) route 0.222ns (61.151%)) Logic Levels: 0 Clock Path Skew: 0.014ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.269ns Source Clock Delay (SCD): -0.501ns Clock Pessimism Removal (CPR): 0.218ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 0.762 -0.501 u_cpu/wb_stage/cpu_clk SLICE_X13Y17 FDRE r u_cpu/wb_stage/ms_to_ws_bus_r_reg[66]/C ------------------------------------------------------------------- ------------------- SLICE_X13Y17 FDRE (Prop_fdre_C_Q) 0.141 -0.360 r u_cpu/wb_stage/ms_to_ws_bus_r_reg[66]/Q net (fo=194, routed) 0.222 -0.138 u_regfile/rf_reg_r2_0_31_30_31/ADDRD2 SLICE_X14Y17 RAMD32 r u_regfile/rf_reg_r2_0_31_30_31/RAMC/WADR2 ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 1.039 -0.269 u_regfile/rf_reg_r2_0_31_30_31/WCLK SLICE_X14Y17 RAMD32 r u_regfile/rf_reg_r2_0_31_30_31/RAMC/CLK clock pessimism -0.218 -0.487 SLICE_X14Y17 RAMD32 (Hold_ramd32_CLK_WADR2) 0.254 -0.233 u_regfile/rf_reg_r2_0_31_30_31/RAMC ------------------------------------------------------------------- required time 0.233 arrival time -0.138 ------------------------------------------------------------------- slack 0.095 Slack (MET) : 0.095ns (arrival time - required time) Source: u_cpu/wb_stage/ms_to_ws_bus_r_reg[66]/C (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Destination: u_regfile/rf_reg_r2_0_31_30_31/RAMC_D1/WADR2 (rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Path Group: cpu_clk Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) Data Path Delay: 0.363ns (logic 0.141ns (38.849%) route 0.222ns (61.151%)) Logic Levels: 0 Clock Path Skew: 0.014ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.269ns Source Clock Delay (SCD): -0.501ns Clock Pessimism Removal (CPR): 0.218ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 0.762 -0.501 u_cpu/wb_stage/cpu_clk SLICE_X13Y17 FDRE r u_cpu/wb_stage/ms_to_ws_bus_r_reg[66]/C ------------------------------------------------------------------- ------------------- SLICE_X13Y17 FDRE (Prop_fdre_C_Q) 0.141 -0.360 r u_cpu/wb_stage/ms_to_ws_bus_r_reg[66]/Q net (fo=194, routed) 0.222 -0.138 u_regfile/rf_reg_r2_0_31_30_31/ADDRD2 SLICE_X14Y17 RAMD32 r u_regfile/rf_reg_r2_0_31_30_31/RAMC_D1/WADR2 ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 1.039 -0.269 u_regfile/rf_reg_r2_0_31_30_31/WCLK SLICE_X14Y17 RAMD32 r u_regfile/rf_reg_r2_0_31_30_31/RAMC_D1/CLK clock pessimism -0.218 -0.487 SLICE_X14Y17 RAMD32 (Hold_ramd32_CLK_WADR2) 0.254 -0.233 u_regfile/rf_reg_r2_0_31_30_31/RAMC_D1 ------------------------------------------------------------------- required time 0.233 arrival time -0.138 ------------------------------------------------------------------- slack 0.095 Slack (MET) : 0.095ns (arrival time - required time) Source: u_cpu/wb_stage/ms_to_ws_bus_r_reg[66]/C (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Destination: u_regfile/rf_reg_r2_0_31_30_31/RAMD/ADR2 (rising edge-triggered cell RAMS32 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Path Group: cpu_clk Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) Data Path Delay: 0.363ns (logic 0.141ns (38.849%) route 0.222ns (61.151%)) Logic Levels: 0 Clock Path Skew: 0.014ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.269ns Source Clock Delay (SCD): -0.501ns Clock Pessimism Removal (CPR): 0.218ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 0.762 -0.501 u_cpu/wb_stage/cpu_clk SLICE_X13Y17 FDRE r u_cpu/wb_stage/ms_to_ws_bus_r_reg[66]/C ------------------------------------------------------------------- ------------------- SLICE_X13Y17 FDRE (Prop_fdre_C_Q) 0.141 -0.360 r u_cpu/wb_stage/ms_to_ws_bus_r_reg[66]/Q net (fo=194, routed) 0.222 -0.138 u_regfile/rf_reg_r2_0_31_30_31/ADDRD2 SLICE_X14Y17 RAMS32 r u_regfile/rf_reg_r2_0_31_30_31/RAMD/ADR2 ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 1.039 -0.269 u_regfile/rf_reg_r2_0_31_30_31/WCLK SLICE_X14Y17 RAMS32 r u_regfile/rf_reg_r2_0_31_30_31/RAMD/CLK clock pessimism -0.218 -0.487 SLICE_X14Y17 RAMS32 (Hold_rams32_CLK_ADR2) 0.254 -0.233 u_regfile/rf_reg_r2_0_31_30_31/RAMD ------------------------------------------------------------------- required time 0.233 arrival time -0.138 ------------------------------------------------------------------- slack 0.095 Slack (MET) : 0.095ns (arrival time - required time) Source: u_cpu/wb_stage/ms_to_ws_bus_r_reg[66]/C (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Destination: u_regfile/rf_reg_r2_0_31_30_31/RAMD_D1/ADR2 (rising edge-triggered cell RAMS32 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Path Group: cpu_clk Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) Data Path Delay: 0.363ns (logic 0.141ns (38.849%) route 0.222ns (61.151%)) Logic Levels: 0 Clock Path Skew: 0.014ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.269ns Source Clock Delay (SCD): -0.501ns Clock Pessimism Removal (CPR): 0.218ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 0.762 -0.501 u_cpu/wb_stage/cpu_clk SLICE_X13Y17 FDRE r u_cpu/wb_stage/ms_to_ws_bus_r_reg[66]/C ------------------------------------------------------------------- ------------------- SLICE_X13Y17 FDRE (Prop_fdre_C_Q) 0.141 -0.360 r u_cpu/wb_stage/ms_to_ws_bus_r_reg[66]/Q net (fo=194, routed) 0.222 -0.138 u_regfile/rf_reg_r2_0_31_30_31/ADDRD2 SLICE_X14Y17 RAMS32 r u_regfile/rf_reg_r2_0_31_30_31/RAMD_D1/ADR2 ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 1.039 -0.269 u_regfile/rf_reg_r2_0_31_30_31/WCLK SLICE_X14Y17 RAMS32 r u_regfile/rf_reg_r2_0_31_30_31/RAMD_D1/CLK clock pessimism -0.218 -0.487 SLICE_X14Y17 RAMS32 (Hold_rams32_CLK_ADR2) 0.254 -0.233 u_regfile/rf_reg_r2_0_31_30_31/RAMD_D1 ------------------------------------------------------------------- required time 0.233 arrival time -0.138 ------------------------------------------------------------------- slack 0.095 Slack (MET) : 0.095ns (arrival time - required time) Source: u_cpu/axi_bridge/awaddr_reg[0]/C (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Destination: u_Axi_CDC/awFifo/ram_reg_0_3_0_5/RAMA/I (rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Path Group: cpu_clk Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) Data Path Delay: 0.257ns (logic 0.141ns (54.812%) route 0.116ns (45.188%)) Logic Levels: 0 Clock Path Skew: 0.015ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.339ns Source Clock Delay (SCD): -0.568ns Clock Pessimism Removal (CPR): 0.214ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 0.694 -0.568 u_cpu/axi_bridge/cpu_clk SLICE_X17Y58 FDRE r u_cpu/axi_bridge/awaddr_reg[0]/C ------------------------------------------------------------------- ------------------- SLICE_X17Y58 FDRE (Prop_fdre_C_Q) 0.141 -0.427 r u_cpu/axi_bridge/awaddr_reg[0]/Q net (fo=1, routed) 0.116 -0.311 u_Axi_CDC/awFifo/ram_reg_0_3_0_5/DIA0 SLICE_X16Y60 RAMD32 r u_Axi_CDC/awFifo/ram_reg_0_3_0_5/RAMA/I ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 0.969 -0.339 u_Axi_CDC/awFifo/ram_reg_0_3_0_5/WCLK SLICE_X16Y60 RAMD32 r u_Axi_CDC/awFifo/ram_reg_0_3_0_5/RAMA/CLK clock pessimism -0.214 -0.553 SLICE_X16Y60 RAMD32 (Hold_ramd32_CLK_I) 0.147 -0.406 u_Axi_CDC/awFifo/ram_reg_0_3_0_5/RAMA ------------------------------------------------------------------- required time 0.406 arrival time -0.311 ------------------------------------------------------------------- slack 0.095 Slack (MET) : 0.097ns (arrival time - required time) Source: u_cpu/axi_bridge/wstrb_reg[2]/C (rising edge-triggered cell FDSE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Destination: u_Axi_CDC/wFifo/ram_reg_0_7_30_35/RAMC/I (rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Path Group: cpu_clk Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) Data Path Delay: 0.257ns (logic 0.141ns (54.812%) route 0.116ns (45.188%)) Logic Levels: 0 Clock Path Skew: 0.016ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.336ns Source Clock Delay (SCD): -0.567ns Clock Pessimism Removal (CPR): 0.215ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 0.695 -0.567 u_cpu/axi_bridge/cpu_clk SLICE_X11Y54 FDSE r u_cpu/axi_bridge/wstrb_reg[2]/C ------------------------------------------------------------------- ------------------- SLICE_X11Y54 FDSE (Prop_fdse_C_Q) 0.141 -0.426 r u_cpu/axi_bridge/wstrb_reg[2]/Q net (fo=1, routed) 0.116 -0.310 u_Axi_CDC/wFifo/ram_reg_0_7_30_35/DIC0 SLICE_X10Y56 RAMD32 r u_Axi_CDC/wFifo/ram_reg_0_7_30_35/RAMC/I ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 0.972 -0.336 u_Axi_CDC/wFifo/ram_reg_0_7_30_35/WCLK SLICE_X10Y56 RAMD32 r u_Axi_CDC/wFifo/ram_reg_0_7_30_35/RAMC/CLK clock pessimism -0.215 -0.551 SLICE_X10Y56 RAMD32 (Hold_ramd32_CLK_I) 0.144 -0.407 u_Axi_CDC/wFifo/ram_reg_0_7_30_35/RAMC ------------------------------------------------------------------- required time 0.407 arrival time -0.310 ------------------------------------------------------------------- slack 0.097 Slack (MET) : 0.098ns (arrival time - required time) Source: u_cpu/btb/ras_ptr_reg[1]/C (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Destination: u_cpu/btb/ras_reg_0_7_18_23/RAMA/WADR1 (rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Path Group: cpu_clk Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) Data Path Delay: 0.443ns (logic 0.141ns (31.821%) route 0.302ns (68.179%)) Logic Levels: 0 Clock Path Skew: 0.036ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.309ns Source Clock Delay (SCD): -0.541ns Clock Pessimism Removal (CPR): 0.196ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 0.722 -0.541 u_cpu/btb/cpu_clk SLICE_X50Y13 FDRE r u_cpu/btb/ras_ptr_reg[1]/C ------------------------------------------------------------------- ------------------- SLICE_X50Y13 FDRE (Prop_fdre_C_Q) 0.141 -0.400 r u_cpu/btb/ras_ptr_reg[1]/Q net (fo=46, routed) 0.302 -0.098 u_cpu/btb/ras_reg_0_7_18_23/ADDRD1 SLICE_X46Y13 RAMD32 r u_cpu/btb/ras_reg_0_7_18_23/RAMA/WADR1 ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 0.999 -0.309 u_cpu/btb/ras_reg_0_7_18_23/WCLK SLICE_X46Y13 RAMD32 r u_cpu/btb/ras_reg_0_7_18_23/RAMA/CLK clock pessimism -0.196 -0.505 SLICE_X46Y13 RAMD32 (Hold_ramd32_CLK_WADR1) 0.309 -0.196 u_cpu/btb/ras_reg_0_7_18_23/RAMA ------------------------------------------------------------------- required time 0.196 arrival time -0.098 ------------------------------------------------------------------- slack 0.098 Slack (MET) : 0.098ns (arrival time - required time) Source: u_cpu/btb/ras_ptr_reg[1]/C (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Destination: u_cpu/btb/ras_reg_0_7_18_23/RAMA_D1/WADR1 (rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Path Group: cpu_clk Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) Data Path Delay: 0.443ns (logic 0.141ns (31.821%) route 0.302ns (68.179%)) Logic Levels: 0 Clock Path Skew: 0.036ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.309ns Source Clock Delay (SCD): -0.541ns Clock Pessimism Removal (CPR): 0.196ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 0.722 -0.541 u_cpu/btb/cpu_clk SLICE_X50Y13 FDRE r u_cpu/btb/ras_ptr_reg[1]/C ------------------------------------------------------------------- ------------------- SLICE_X50Y13 FDRE (Prop_fdre_C_Q) 0.141 -0.400 r u_cpu/btb/ras_ptr_reg[1]/Q net (fo=46, routed) 0.302 -0.098 u_cpu/btb/ras_reg_0_7_18_23/ADDRD1 SLICE_X46Y13 RAMD32 r u_cpu/btb/ras_reg_0_7_18_23/RAMA_D1/WADR1 ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 0.999 -0.309 u_cpu/btb/ras_reg_0_7_18_23/WCLK SLICE_X46Y13 RAMD32 r u_cpu/btb/ras_reg_0_7_18_23/RAMA_D1/CLK clock pessimism -0.196 -0.505 SLICE_X46Y13 RAMD32 (Hold_ramd32_CLK_WADR1) 0.309 -0.196 u_cpu/btb/ras_reg_0_7_18_23/RAMA_D1 ------------------------------------------------------------------- required time 0.196 arrival time -0.098 ------------------------------------------------------------------- slack 0.098 Slack (MET) : 0.098ns (arrival time - required time) Source: u_cpu/btb/ras_ptr_reg[1]/C (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Destination: u_cpu/btb/ras_reg_0_7_18_23/RAMB/WADR1 (rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Path Group: cpu_clk Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) Data Path Delay: 0.443ns (logic 0.141ns (31.821%) route 0.302ns (68.179%)) Logic Levels: 0 Clock Path Skew: 0.036ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.309ns Source Clock Delay (SCD): -0.541ns Clock Pessimism Removal (CPR): 0.196ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 0.722 -0.541 u_cpu/btb/cpu_clk SLICE_X50Y13 FDRE r u_cpu/btb/ras_ptr_reg[1]/C ------------------------------------------------------------------- ------------------- SLICE_X50Y13 FDRE (Prop_fdre_C_Q) 0.141 -0.400 r u_cpu/btb/ras_ptr_reg[1]/Q net (fo=46, routed) 0.302 -0.098 u_cpu/btb/ras_reg_0_7_18_23/ADDRD1 SLICE_X46Y13 RAMD32 r u_cpu/btb/ras_reg_0_7_18_23/RAMB/WADR1 ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 0.999 -0.309 u_cpu/btb/ras_reg_0_7_18_23/WCLK SLICE_X46Y13 RAMD32 r u_cpu/btb/ras_reg_0_7_18_23/RAMB/CLK clock pessimism -0.196 -0.505 SLICE_X46Y13 RAMD32 (Hold_ramd32_CLK_WADR1) 0.309 -0.196 u_cpu/btb/ras_reg_0_7_18_23/RAMB ------------------------------------------------------------------- required time 0.196 arrival time -0.098 ------------------------------------------------------------------- slack 0.098 Slack (MET) : 0.098ns (arrival time - required time) Source: u_cpu/btb/ras_ptr_reg[1]/C (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Destination: u_cpu/btb/ras_reg_0_7_18_23/RAMB_D1/WADR1 (rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Path Group: cpu_clk Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) Data Path Delay: 0.443ns (logic 0.141ns (31.821%) route 0.302ns (68.179%)) Logic Levels: 0 Clock Path Skew: 0.036ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.309ns Source Clock Delay (SCD): -0.541ns Clock Pessimism Removal (CPR): 0.196ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 0.722 -0.541 u_cpu/btb/cpu_clk SLICE_X50Y13 FDRE r u_cpu/btb/ras_ptr_reg[1]/C ------------------------------------------------------------------- ------------------- SLICE_X50Y13 FDRE (Prop_fdre_C_Q) 0.141 -0.400 r u_cpu/btb/ras_ptr_reg[1]/Q net (fo=46, routed) 0.302 -0.098 u_cpu/btb/ras_reg_0_7_18_23/ADDRD1 SLICE_X46Y13 RAMD32 r u_cpu/btb/ras_reg_0_7_18_23/RAMB_D1/WADR1 ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 0.999 -0.309 u_cpu/btb/ras_reg_0_7_18_23/WCLK SLICE_X46Y13 RAMD32 r u_cpu/btb/ras_reg_0_7_18_23/RAMB_D1/CLK clock pessimism -0.196 -0.505 SLICE_X46Y13 RAMD32 (Hold_ramd32_CLK_WADR1) 0.309 -0.196 u_cpu/btb/ras_reg_0_7_18_23/RAMB_D1 ------------------------------------------------------------------- required time 0.196 arrival time -0.098 ------------------------------------------------------------------- slack 0.098 Slack (MET) : 0.098ns (arrival time - required time) Source: u_cpu/btb/ras_ptr_reg[1]/C (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Destination: u_cpu/btb/ras_reg_0_7_18_23/RAMC/WADR1 (rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Path Group: cpu_clk Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) Data Path Delay: 0.443ns (logic 0.141ns (31.821%) route 0.302ns (68.179%)) Logic Levels: 0 Clock Path Skew: 0.036ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.309ns Source Clock Delay (SCD): -0.541ns Clock Pessimism Removal (CPR): 0.196ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 0.722 -0.541 u_cpu/btb/cpu_clk SLICE_X50Y13 FDRE r u_cpu/btb/ras_ptr_reg[1]/C ------------------------------------------------------------------- ------------------- SLICE_X50Y13 FDRE (Prop_fdre_C_Q) 0.141 -0.400 r u_cpu/btb/ras_ptr_reg[1]/Q net (fo=46, routed) 0.302 -0.098 u_cpu/btb/ras_reg_0_7_18_23/ADDRD1 SLICE_X46Y13 RAMD32 r u_cpu/btb/ras_reg_0_7_18_23/RAMC/WADR1 ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 0.999 -0.309 u_cpu/btb/ras_reg_0_7_18_23/WCLK SLICE_X46Y13 RAMD32 r u_cpu/btb/ras_reg_0_7_18_23/RAMC/CLK clock pessimism -0.196 -0.505 SLICE_X46Y13 RAMD32 (Hold_ramd32_CLK_WADR1) 0.309 -0.196 u_cpu/btb/ras_reg_0_7_18_23/RAMC ------------------------------------------------------------------- required time 0.196 arrival time -0.098 ------------------------------------------------------------------- slack 0.098 Slack (MET) : 0.098ns (arrival time - required time) Source: u_cpu/btb/ras_ptr_reg[1]/C (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Destination: u_cpu/btb/ras_reg_0_7_18_23/RAMC_D1/WADR1 (rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Path Group: cpu_clk Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) Data Path Delay: 0.443ns (logic 0.141ns (31.821%) route 0.302ns (68.179%)) Logic Levels: 0 Clock Path Skew: 0.036ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.309ns Source Clock Delay (SCD): -0.541ns Clock Pessimism Removal (CPR): 0.196ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 0.722 -0.541 u_cpu/btb/cpu_clk SLICE_X50Y13 FDRE r u_cpu/btb/ras_ptr_reg[1]/C ------------------------------------------------------------------- ------------------- SLICE_X50Y13 FDRE (Prop_fdre_C_Q) 0.141 -0.400 r u_cpu/btb/ras_ptr_reg[1]/Q net (fo=46, routed) 0.302 -0.098 u_cpu/btb/ras_reg_0_7_18_23/ADDRD1 SLICE_X46Y13 RAMD32 r u_cpu/btb/ras_reg_0_7_18_23/RAMC_D1/WADR1 ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 0.999 -0.309 u_cpu/btb/ras_reg_0_7_18_23/WCLK SLICE_X46Y13 RAMD32 r u_cpu/btb/ras_reg_0_7_18_23/RAMC_D1/CLK clock pessimism -0.196 -0.505 SLICE_X46Y13 RAMD32 (Hold_ramd32_CLK_WADR1) 0.309 -0.196 u_cpu/btb/ras_reg_0_7_18_23/RAMC_D1 ------------------------------------------------------------------- required time 0.196 arrival time -0.098 ------------------------------------------------------------------- slack 0.098 Slack (MET) : 0.098ns (arrival time - required time) Source: u_cpu/btb/ras_ptr_reg[1]/C (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Destination: u_cpu/btb/ras_reg_0_7_18_23/RAMD/ADR1 (rising edge-triggered cell RAMS32 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Path Group: cpu_clk Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) Data Path Delay: 0.443ns (logic 0.141ns (31.821%) route 0.302ns (68.179%)) Logic Levels: 0 Clock Path Skew: 0.036ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.309ns Source Clock Delay (SCD): -0.541ns Clock Pessimism Removal (CPR): 0.196ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 0.722 -0.541 u_cpu/btb/cpu_clk SLICE_X50Y13 FDRE r u_cpu/btb/ras_ptr_reg[1]/C ------------------------------------------------------------------- ------------------- SLICE_X50Y13 FDRE (Prop_fdre_C_Q) 0.141 -0.400 r u_cpu/btb/ras_ptr_reg[1]/Q net (fo=46, routed) 0.302 -0.098 u_cpu/btb/ras_reg_0_7_18_23/ADDRD1 SLICE_X46Y13 RAMS32 r u_cpu/btb/ras_reg_0_7_18_23/RAMD/ADR1 ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 0.999 -0.309 u_cpu/btb/ras_reg_0_7_18_23/WCLK SLICE_X46Y13 RAMS32 r u_cpu/btb/ras_reg_0_7_18_23/RAMD/CLK clock pessimism -0.196 -0.505 SLICE_X46Y13 RAMS32 (Hold_rams32_CLK_ADR1) 0.309 -0.196 u_cpu/btb/ras_reg_0_7_18_23/RAMD ------------------------------------------------------------------- required time 0.196 arrival time -0.098 ------------------------------------------------------------------- slack 0.098 Slack (MET) : 0.098ns (arrival time - required time) Source: u_cpu/btb/ras_ptr_reg[1]/C (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Destination: u_cpu/btb/ras_reg_0_7_18_23/RAMD_D1/ADR1 (rising edge-triggered cell RAMS32 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Path Group: cpu_clk Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) Data Path Delay: 0.443ns (logic 0.141ns (31.821%) route 0.302ns (68.179%)) Logic Levels: 0 Clock Path Skew: 0.036ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.309ns Source Clock Delay (SCD): -0.541ns Clock Pessimism Removal (CPR): 0.196ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 0.722 -0.541 u_cpu/btb/cpu_clk SLICE_X50Y13 FDRE r u_cpu/btb/ras_ptr_reg[1]/C ------------------------------------------------------------------- ------------------- SLICE_X50Y13 FDRE (Prop_fdre_C_Q) 0.141 -0.400 r u_cpu/btb/ras_ptr_reg[1]/Q net (fo=46, routed) 0.302 -0.098 u_cpu/btb/ras_reg_0_7_18_23/ADDRD1 SLICE_X46Y13 RAMS32 r u_cpu/btb/ras_reg_0_7_18_23/RAMD_D1/ADR1 ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 0.999 -0.309 u_cpu/btb/ras_reg_0_7_18_23/WCLK SLICE_X46Y13 RAMS32 r u_cpu/btb/ras_reg_0_7_18_23/RAMD_D1/CLK clock pessimism -0.196 -0.505 SLICE_X46Y13 RAMS32 (Hold_rams32_CLK_ADR1) 0.309 -0.196 u_cpu/btb/ras_reg_0_7_18_23/RAMD_D1 ------------------------------------------------------------------- required time 0.196 arrival time -0.098 ------------------------------------------------------------------- slack 0.098 Slack (MET) : 0.098ns (arrival time - required time) Source: u_cpu/u_csr/csr_asid_reg[4]/C (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Destination: u_cpu/addr_trans/tlb_entry/tlb_asid_reg[24][4]/D (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Path Group: cpu_clk Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) Data Path Delay: 0.367ns (logic 0.141ns (38.455%) route 0.226ns (61.545%)) Logic Levels: 0 Clock Path Skew: 0.196ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.344ns Source Clock Delay (SCD): -0.504ns Clock Pessimism Removal (CPR): -0.037ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 0.759 -0.504 u_cpu/u_csr/cpu_clk SLICE_X37Y48 FDRE r u_cpu/u_csr/csr_asid_reg[4]/C ------------------------------------------------------------------- ------------------- SLICE_X37Y48 FDRE (Prop_fdre_C_Q) 0.141 -0.363 r u_cpu/u_csr/csr_asid_reg[4]/Q net (fo=35, routed) 0.226 -0.137 u_cpu/addr_trans/tlb_entry/s1_asid_r_reg[9]_0[4] SLICE_X33Y51 FDRE r u_cpu/addr_trans/tlb_entry/tlb_asid_reg[24][4]/D ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 0.964 -0.344 u_cpu/addr_trans/tlb_entry/cpu_clk SLICE_X33Y51 FDRE r u_cpu/addr_trans/tlb_entry/tlb_asid_reg[24][4]/C clock pessimism 0.037 -0.307 SLICE_X33Y51 FDRE (Hold_fdre_C_D) 0.072 -0.235 u_cpu/addr_trans/tlb_entry/tlb_asid_reg[24][4] ------------------------------------------------------------------- required time 0.235 arrival time -0.137 ------------------------------------------------------------------- slack 0.098 Slack (MET) : 0.100ns (arrival time - required time) Source: u_cpu/wb_stage/ms_to_ws_bus_r_reg[65]/C (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Destination: u_regfile/rf_reg_r2_0_31_30_31/RAMA/WADR1 (rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Path Group: cpu_clk Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) Data Path Delay: 0.423ns (logic 0.141ns (33.296%) route 0.282ns (66.704%)) Logic Levels: 0 Clock Path Skew: 0.014ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.269ns Source Clock Delay (SCD): -0.501ns Clock Pessimism Removal (CPR): 0.218ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 0.762 -0.501 u_cpu/wb_stage/cpu_clk SLICE_X13Y17 FDRE r u_cpu/wb_stage/ms_to_ws_bus_r_reg[65]/C ------------------------------------------------------------------- ------------------- SLICE_X13Y17 FDRE (Prop_fdre_C_Q) 0.141 -0.360 r u_cpu/wb_stage/ms_to_ws_bus_r_reg[65]/Q net (fo=194, routed) 0.282 -0.077 u_regfile/rf_reg_r2_0_31_30_31/ADDRD1 SLICE_X14Y17 RAMD32 r u_regfile/rf_reg_r2_0_31_30_31/RAMA/WADR1 ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 1.039 -0.269 u_regfile/rf_reg_r2_0_31_30_31/WCLK SLICE_X14Y17 RAMD32 r u_regfile/rf_reg_r2_0_31_30_31/RAMA/CLK clock pessimism -0.218 -0.487 SLICE_X14Y17 RAMD32 (Hold_ramd32_CLK_WADR1) 0.309 -0.178 u_regfile/rf_reg_r2_0_31_30_31/RAMA ------------------------------------------------------------------- required time 0.178 arrival time -0.077 ------------------------------------------------------------------- slack 0.100 Slack (MET) : 0.100ns (arrival time - required time) Source: u_cpu/wb_stage/ms_to_ws_bus_r_reg[65]/C (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Destination: u_regfile/rf_reg_r2_0_31_30_31/RAMA_D1/WADR1 (rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Path Group: cpu_clk Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) Data Path Delay: 0.423ns (logic 0.141ns (33.296%) route 0.282ns (66.704%)) Logic Levels: 0 Clock Path Skew: 0.014ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.269ns Source Clock Delay (SCD): -0.501ns Clock Pessimism Removal (CPR): 0.218ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 0.762 -0.501 u_cpu/wb_stage/cpu_clk SLICE_X13Y17 FDRE r u_cpu/wb_stage/ms_to_ws_bus_r_reg[65]/C ------------------------------------------------------------------- ------------------- SLICE_X13Y17 FDRE (Prop_fdre_C_Q) 0.141 -0.360 r u_cpu/wb_stage/ms_to_ws_bus_r_reg[65]/Q net (fo=194, routed) 0.282 -0.077 u_regfile/rf_reg_r2_0_31_30_31/ADDRD1 SLICE_X14Y17 RAMD32 r u_regfile/rf_reg_r2_0_31_30_31/RAMA_D1/WADR1 ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 1.039 -0.269 u_regfile/rf_reg_r2_0_31_30_31/WCLK SLICE_X14Y17 RAMD32 r u_regfile/rf_reg_r2_0_31_30_31/RAMA_D1/CLK clock pessimism -0.218 -0.487 SLICE_X14Y17 RAMD32 (Hold_ramd32_CLK_WADR1) 0.309 -0.178 u_regfile/rf_reg_r2_0_31_30_31/RAMA_D1 ------------------------------------------------------------------- required time 0.178 arrival time -0.077 ------------------------------------------------------------------- slack 0.100 Slack (MET) : 0.100ns (arrival time - required time) Source: u_cpu/wb_stage/ms_to_ws_bus_r_reg[65]/C (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Destination: u_regfile/rf_reg_r2_0_31_30_31/RAMB/WADR1 (rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Path Group: cpu_clk Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) Data Path Delay: 0.423ns (logic 0.141ns (33.296%) route 0.282ns (66.704%)) Logic Levels: 0 Clock Path Skew: 0.014ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.269ns Source Clock Delay (SCD): -0.501ns Clock Pessimism Removal (CPR): 0.218ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 0.762 -0.501 u_cpu/wb_stage/cpu_clk SLICE_X13Y17 FDRE r u_cpu/wb_stage/ms_to_ws_bus_r_reg[65]/C ------------------------------------------------------------------- ------------------- SLICE_X13Y17 FDRE (Prop_fdre_C_Q) 0.141 -0.360 r u_cpu/wb_stage/ms_to_ws_bus_r_reg[65]/Q net (fo=194, routed) 0.282 -0.077 u_regfile/rf_reg_r2_0_31_30_31/ADDRD1 SLICE_X14Y17 RAMD32 r u_regfile/rf_reg_r2_0_31_30_31/RAMB/WADR1 ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 1.039 -0.269 u_regfile/rf_reg_r2_0_31_30_31/WCLK SLICE_X14Y17 RAMD32 r u_regfile/rf_reg_r2_0_31_30_31/RAMB/CLK clock pessimism -0.218 -0.487 SLICE_X14Y17 RAMD32 (Hold_ramd32_CLK_WADR1) 0.309 -0.178 u_regfile/rf_reg_r2_0_31_30_31/RAMB ------------------------------------------------------------------- required time 0.178 arrival time -0.077 ------------------------------------------------------------------- slack 0.100 Slack (MET) : 0.100ns (arrival time - required time) Source: u_cpu/wb_stage/ms_to_ws_bus_r_reg[65]/C (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Destination: u_regfile/rf_reg_r2_0_31_30_31/RAMB_D1/WADR1 (rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Path Group: cpu_clk Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) Data Path Delay: 0.423ns (logic 0.141ns (33.296%) route 0.282ns (66.704%)) Logic Levels: 0 Clock Path Skew: 0.014ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.269ns Source Clock Delay (SCD): -0.501ns Clock Pessimism Removal (CPR): 0.218ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 0.762 -0.501 u_cpu/wb_stage/cpu_clk SLICE_X13Y17 FDRE r u_cpu/wb_stage/ms_to_ws_bus_r_reg[65]/C ------------------------------------------------------------------- ------------------- SLICE_X13Y17 FDRE (Prop_fdre_C_Q) 0.141 -0.360 r u_cpu/wb_stage/ms_to_ws_bus_r_reg[65]/Q net (fo=194, routed) 0.282 -0.077 u_regfile/rf_reg_r2_0_31_30_31/ADDRD1 SLICE_X14Y17 RAMD32 r u_regfile/rf_reg_r2_0_31_30_31/RAMB_D1/WADR1 ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 1.039 -0.269 u_regfile/rf_reg_r2_0_31_30_31/WCLK SLICE_X14Y17 RAMD32 r u_regfile/rf_reg_r2_0_31_30_31/RAMB_D1/CLK clock pessimism -0.218 -0.487 SLICE_X14Y17 RAMD32 (Hold_ramd32_CLK_WADR1) 0.309 -0.178 u_regfile/rf_reg_r2_0_31_30_31/RAMB_D1 ------------------------------------------------------------------- required time 0.178 arrival time -0.077 ------------------------------------------------------------------- slack 0.100 Slack (MET) : 0.100ns (arrival time - required time) Source: u_cpu/wb_stage/ms_to_ws_bus_r_reg[65]/C (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Destination: u_regfile/rf_reg_r2_0_31_30_31/RAMC/WADR1 (rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Path Group: cpu_clk Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) Data Path Delay: 0.423ns (logic 0.141ns (33.296%) route 0.282ns (66.704%)) Logic Levels: 0 Clock Path Skew: 0.014ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.269ns Source Clock Delay (SCD): -0.501ns Clock Pessimism Removal (CPR): 0.218ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 0.762 -0.501 u_cpu/wb_stage/cpu_clk SLICE_X13Y17 FDRE r u_cpu/wb_stage/ms_to_ws_bus_r_reg[65]/C ------------------------------------------------------------------- ------------------- SLICE_X13Y17 FDRE (Prop_fdre_C_Q) 0.141 -0.360 r u_cpu/wb_stage/ms_to_ws_bus_r_reg[65]/Q net (fo=194, routed) 0.282 -0.077 u_regfile/rf_reg_r2_0_31_30_31/ADDRD1 SLICE_X14Y17 RAMD32 r u_regfile/rf_reg_r2_0_31_30_31/RAMC/WADR1 ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 1.039 -0.269 u_regfile/rf_reg_r2_0_31_30_31/WCLK SLICE_X14Y17 RAMD32 r u_regfile/rf_reg_r2_0_31_30_31/RAMC/CLK clock pessimism -0.218 -0.487 SLICE_X14Y17 RAMD32 (Hold_ramd32_CLK_WADR1) 0.309 -0.178 u_regfile/rf_reg_r2_0_31_30_31/RAMC ------------------------------------------------------------------- required time 0.178 arrival time -0.077 ------------------------------------------------------------------- slack 0.100 Slack (MET) : 0.100ns (arrival time - required time) Source: u_cpu/wb_stage/ms_to_ws_bus_r_reg[65]/C (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Destination: u_regfile/rf_reg_r2_0_31_30_31/RAMC_D1/WADR1 (rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Path Group: cpu_clk Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) Data Path Delay: 0.423ns (logic 0.141ns (33.296%) route 0.282ns (66.704%)) Logic Levels: 0 Clock Path Skew: 0.014ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.269ns Source Clock Delay (SCD): -0.501ns Clock Pessimism Removal (CPR): 0.218ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 0.762 -0.501 u_cpu/wb_stage/cpu_clk SLICE_X13Y17 FDRE r u_cpu/wb_stage/ms_to_ws_bus_r_reg[65]/C ------------------------------------------------------------------- ------------------- SLICE_X13Y17 FDRE (Prop_fdre_C_Q) 0.141 -0.360 r u_cpu/wb_stage/ms_to_ws_bus_r_reg[65]/Q net (fo=194, routed) 0.282 -0.077 u_regfile/rf_reg_r2_0_31_30_31/ADDRD1 SLICE_X14Y17 RAMD32 r u_regfile/rf_reg_r2_0_31_30_31/RAMC_D1/WADR1 ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 1.039 -0.269 u_regfile/rf_reg_r2_0_31_30_31/WCLK SLICE_X14Y17 RAMD32 r u_regfile/rf_reg_r2_0_31_30_31/RAMC_D1/CLK clock pessimism -0.218 -0.487 SLICE_X14Y17 RAMD32 (Hold_ramd32_CLK_WADR1) 0.309 -0.178 u_regfile/rf_reg_r2_0_31_30_31/RAMC_D1 ------------------------------------------------------------------- required time 0.178 arrival time -0.077 ------------------------------------------------------------------- slack 0.100 Slack (MET) : 0.100ns (arrival time - required time) Source: u_cpu/wb_stage/ms_to_ws_bus_r_reg[65]/C (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Destination: u_regfile/rf_reg_r2_0_31_30_31/RAMD/ADR1 (rising edge-triggered cell RAMS32 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Path Group: cpu_clk Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) Data Path Delay: 0.423ns (logic 0.141ns (33.296%) route 0.282ns (66.704%)) Logic Levels: 0 Clock Path Skew: 0.014ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.269ns Source Clock Delay (SCD): -0.501ns Clock Pessimism Removal (CPR): 0.218ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 0.762 -0.501 u_cpu/wb_stage/cpu_clk SLICE_X13Y17 FDRE r u_cpu/wb_stage/ms_to_ws_bus_r_reg[65]/C ------------------------------------------------------------------- ------------------- SLICE_X13Y17 FDRE (Prop_fdre_C_Q) 0.141 -0.360 r u_cpu/wb_stage/ms_to_ws_bus_r_reg[65]/Q net (fo=194, routed) 0.282 -0.077 u_regfile/rf_reg_r2_0_31_30_31/ADDRD1 SLICE_X14Y17 RAMS32 r u_regfile/rf_reg_r2_0_31_30_31/RAMD/ADR1 ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 1.039 -0.269 u_regfile/rf_reg_r2_0_31_30_31/WCLK SLICE_X14Y17 RAMS32 r u_regfile/rf_reg_r2_0_31_30_31/RAMD/CLK clock pessimism -0.218 -0.487 SLICE_X14Y17 RAMS32 (Hold_rams32_CLK_ADR1) 0.309 -0.178 u_regfile/rf_reg_r2_0_31_30_31/RAMD ------------------------------------------------------------------- required time 0.178 arrival time -0.077 ------------------------------------------------------------------- slack 0.100 Slack (MET) : 0.100ns (arrival time - required time) Source: u_cpu/wb_stage/ms_to_ws_bus_r_reg[65]/C (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Destination: u_regfile/rf_reg_r2_0_31_30_31/RAMD_D1/ADR1 (rising edge-triggered cell RAMS32 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Path Group: cpu_clk Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) Data Path Delay: 0.423ns (logic 0.141ns (33.296%) route 0.282ns (66.704%)) Logic Levels: 0 Clock Path Skew: 0.014ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.269ns Source Clock Delay (SCD): -0.501ns Clock Pessimism Removal (CPR): 0.218ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 0.762 -0.501 u_cpu/wb_stage/cpu_clk SLICE_X13Y17 FDRE r u_cpu/wb_stage/ms_to_ws_bus_r_reg[65]/C ------------------------------------------------------------------- ------------------- SLICE_X13Y17 FDRE (Prop_fdre_C_Q) 0.141 -0.360 r u_cpu/wb_stage/ms_to_ws_bus_r_reg[65]/Q net (fo=194, routed) 0.282 -0.077 u_regfile/rf_reg_r2_0_31_30_31/ADDRD1 SLICE_X14Y17 RAMS32 r u_regfile/rf_reg_r2_0_31_30_31/RAMD_D1/ADR1 ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 1.039 -0.269 u_regfile/rf_reg_r2_0_31_30_31/WCLK SLICE_X14Y17 RAMS32 r u_regfile/rf_reg_r2_0_31_30_31/RAMD_D1/CLK clock pessimism -0.218 -0.487 SLICE_X14Y17 RAMS32 (Hold_rams32_CLK_ADR1) 0.309 -0.178 u_regfile/rf_reg_r2_0_31_30_31/RAMD_D1 ------------------------------------------------------------------- required time 0.178 arrival time -0.077 ------------------------------------------------------------------- slack 0.100 Slack (MET) : 0.105ns (arrival time - required time) Source: u_cpu/u_csr/csr_tlbelo1_reg[10]/C (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Destination: u_cpu/addr_trans/tlb_entry/tlb_ppn1_reg_r1_0_31_0_5/RAMB/I (rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Path Group: cpu_clk Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) Data Path Delay: 0.265ns (logic 0.141ns (53.280%) route 0.124ns (46.720%)) Logic Levels: 0 Clock Path Skew: 0.014ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.277ns Source Clock Delay (SCD): -0.510ns Clock Pessimism Removal (CPR): 0.219ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 0.753 -0.510 u_cpu/u_csr/cpu_clk SLICE_X19Y24 FDRE r u_cpu/u_csr/csr_tlbelo1_reg[10]/C ------------------------------------------------------------------- ------------------- SLICE_X19Y24 FDRE (Prop_fdre_C_Q) 0.141 -0.369 r u_cpu/u_csr/csr_tlbelo1_reg[10]/Q net (fo=4, routed) 0.124 -0.245 u_cpu/addr_trans/tlb_entry/tlb_ppn1_reg_r1_0_31_0_5/DIB0 SLICE_X16Y23 RAMD32 r u_cpu/addr_trans/tlb_entry/tlb_ppn1_reg_r1_0_31_0_5/RAMB/I ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 1.031 -0.277 u_cpu/addr_trans/tlb_entry/tlb_ppn1_reg_r1_0_31_0_5/WCLK SLICE_X16Y23 RAMD32 r u_cpu/addr_trans/tlb_entry/tlb_ppn1_reg_r1_0_31_0_5/RAMB/CLK clock pessimism -0.219 -0.496 SLICE_X16Y23 RAMD32 (Hold_ramd32_CLK_I) 0.146 -0.350 u_cpu/addr_trans/tlb_entry/tlb_ppn1_reg_r1_0_31_0_5/RAMB ------------------------------------------------------------------- required time 0.350 arrival time -0.245 ------------------------------------------------------------------- slack 0.105 Slack (MET) : 0.105ns (arrival time - required time) Source: u_cpu/wb_stage/ms_to_ws_bus_r_reg[50]/C (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Destination: u_regfile/rf_reg_r2_0_31_18_23/RAMA/I (rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Path Group: cpu_clk Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) Data Path Delay: 0.265ns (logic 0.141ns (53.192%) route 0.124ns (46.808%)) Logic Levels: 0 Clock Path Skew: 0.013ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.272ns Source Clock Delay (SCD): -0.503ns Clock Pessimism Removal (CPR): 0.218ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 0.760 -0.503 u_cpu/wb_stage/cpu_clk SLICE_X13Y19 FDRE r u_cpu/wb_stage/ms_to_ws_bus_r_reg[50]/C ------------------------------------------------------------------- ------------------- SLICE_X13Y19 FDRE (Prop_fdre_C_Q) 0.141 -0.362 r u_cpu/wb_stage/ms_to_ws_bus_r_reg[50]/Q net (fo=6, routed) 0.124 -0.238 u_regfile/rf_reg_r2_0_31_18_23/DIA0 SLICE_X14Y20 RAMD32 r u_regfile/rf_reg_r2_0_31_18_23/RAMA/I ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 1.036 -0.272 u_regfile/rf_reg_r2_0_31_18_23/WCLK SLICE_X14Y20 RAMD32 r u_regfile/rf_reg_r2_0_31_18_23/RAMA/CLK clock pessimism -0.218 -0.490 SLICE_X14Y20 RAMD32 (Hold_ramd32_CLK_I) 0.147 -0.343 u_regfile/rf_reg_r2_0_31_18_23/RAMA ------------------------------------------------------------------- required time 0.343 arrival time -0.238 ------------------------------------------------------------------- slack 0.105 Slack (MET) : 0.113ns (arrival time - required time) Source: u_cpu/u_csr/csr_tlbelo1_reg[4]/C (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Destination: u_cpu/addr_trans/tlb_entry/tlb_mat1_reg_r3_0_31_0_0/SP/I (rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Path Group: cpu_clk Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) Data Path Delay: 0.273ns (logic 0.141ns (51.636%) route 0.132ns (48.364%)) Logic Levels: 0 Clock Path Skew: 0.014ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.273ns Source Clock Delay (SCD): -0.505ns Clock Pessimism Removal (CPR): 0.218ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 0.758 -0.505 u_cpu/u_csr/cpu_clk SLICE_X15Y27 FDRE r u_cpu/u_csr/csr_tlbelo1_reg[4]/C ------------------------------------------------------------------- ------------------- SLICE_X15Y27 FDRE (Prop_fdre_C_Q) 0.141 -0.364 r u_cpu/u_csr/csr_tlbelo1_reg[4]/Q net (fo=7, routed) 0.132 -0.232 u_cpu/addr_trans/tlb_entry/tlb_mat1_reg_r3_0_31_0_0/D SLICE_X14Y28 RAMD32 r u_cpu/addr_trans/tlb_entry/tlb_mat1_reg_r3_0_31_0_0/SP/I ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 1.035 -0.273 u_cpu/addr_trans/tlb_entry/tlb_mat1_reg_r3_0_31_0_0/WCLK SLICE_X14Y28 RAMD32 r u_cpu/addr_trans/tlb_entry/tlb_mat1_reg_r3_0_31_0_0/SP/CLK clock pessimism -0.218 -0.491 SLICE_X14Y28 RAMD32 (Hold_ramd32_CLK_I) 0.146 -0.345 u_cpu/addr_trans/tlb_entry/tlb_mat1_reg_r3_0_31_0_0/SP ------------------------------------------------------------------- required time 0.345 arrival time -0.232 ------------------------------------------------------------------- slack 0.113 Slack (MET) : 0.116ns (arrival time - required time) Source: u_cpu/u_csr/csr_tlbelo1_reg[5]/C (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Destination: u_cpu/addr_trans/tlb_entry/tlb_mat1_reg_r2_0_31_1_1/SP/I (rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Path Group: cpu_clk Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) Data Path Delay: 0.274ns (logic 0.141ns (51.492%) route 0.133ns (48.508%)) Logic Levels: 0 Clock Path Skew: 0.014ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.273ns Source Clock Delay (SCD): -0.505ns Clock Pessimism Removal (CPR): 0.218ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 0.758 -0.505 u_cpu/u_csr/cpu_clk SLICE_X15Y27 FDRE r u_cpu/u_csr/csr_tlbelo1_reg[5]/C ------------------------------------------------------------------- ------------------- SLICE_X15Y27 FDRE (Prop_fdre_C_Q) 0.141 -0.364 r u_cpu/u_csr/csr_tlbelo1_reg[5]/Q net (fo=7, routed) 0.133 -0.231 u_cpu/addr_trans/tlb_entry/tlb_mat1_reg_r2_0_31_1_1/D SLICE_X14Y28 RAMD32 r u_cpu/addr_trans/tlb_entry/tlb_mat1_reg_r2_0_31_1_1/SP/I ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 1.035 -0.273 u_cpu/addr_trans/tlb_entry/tlb_mat1_reg_r2_0_31_1_1/WCLK SLICE_X14Y28 RAMD32 r u_cpu/addr_trans/tlb_entry/tlb_mat1_reg_r2_0_31_1_1/SP/CLK clock pessimism -0.218 -0.491 SLICE_X14Y28 RAMD32 (Hold_ramd32_CLK_I) 0.144 -0.347 u_cpu/addr_trans/tlb_entry/tlb_mat1_reg_r2_0_31_1_1/SP ------------------------------------------------------------------- required time 0.347 arrival time -0.231 ------------------------------------------------------------------- slack 0.116 Slack (MET) : 0.116ns (arrival time - required time) Source: u_cpu/u_csr/csr_tlbelo1_reg[24]/C (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Destination: u_cpu/addr_trans/tlb_entry/tlb_ppn1_reg_r3_0_31_12_17/RAMC/I (rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Path Group: cpu_clk Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) Data Path Delay: 0.273ns (logic 0.141ns (51.645%) route 0.132ns (48.355%)) Logic Levels: 0 Clock Path Skew: 0.013ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.275ns Source Clock Delay (SCD): -0.507ns Clock Pessimism Removal (CPR): 0.219ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 0.756 -0.507 u_cpu/u_csr/cpu_clk SLICE_X19Y27 FDRE r u_cpu/u_csr/csr_tlbelo1_reg[24]/C ------------------------------------------------------------------- ------------------- SLICE_X19Y27 FDRE (Prop_fdre_C_Q) 0.141 -0.366 r u_cpu/u_csr/csr_tlbelo1_reg[24]/Q net (fo=4, routed) 0.132 -0.234 u_cpu/addr_trans/tlb_entry/tlb_ppn1_reg_r3_0_31_12_17/DIC0 SLICE_X18Y27 RAMD32 r u_cpu/addr_trans/tlb_entry/tlb_ppn1_reg_r3_0_31_12_17/RAMC/I ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 1.033 -0.275 u_cpu/addr_trans/tlb_entry/tlb_ppn1_reg_r3_0_31_12_17/WCLK SLICE_X18Y27 RAMD32 r u_cpu/addr_trans/tlb_entry/tlb_ppn1_reg_r3_0_31_12_17/RAMC/CLK clock pessimism -0.219 -0.494 SLICE_X18Y27 RAMD32 (Hold_ramd32_CLK_I) 0.144 -0.350 u_cpu/addr_trans/tlb_entry/tlb_ppn1_reg_r3_0_31_12_17/RAMC ------------------------------------------------------------------- required time 0.350 arrival time -0.234 ------------------------------------------------------------------- slack 0.116 Slack (MET) : 0.116ns (arrival time - required time) Source: u_cpu/wb_stage/ms_to_ws_bus_r_reg[40]/C (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Destination: u_regfile/rf_reg_r1_0_31_6_11/RAMB/I (rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Path Group: cpu_clk Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) Data Path Delay: 0.275ns (logic 0.141ns (51.258%) route 0.134ns (48.742%)) Logic Levels: 0 Clock Path Skew: 0.013ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.270ns Source Clock Delay (SCD): -0.502ns Clock Pessimism Removal (CPR): 0.219ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 0.761 -0.502 u_cpu/wb_stage/cpu_clk SLICE_X19Y16 FDRE r u_cpu/wb_stage/ms_to_ws_bus_r_reg[40]/C ------------------------------------------------------------------- ------------------- SLICE_X19Y16 FDRE (Prop_fdre_C_Q) 0.141 -0.361 r u_cpu/wb_stage/ms_to_ws_bus_r_reg[40]/Q net (fo=6, routed) 0.134 -0.227 u_regfile/rf_reg_r1_0_31_6_11/DIB0 SLICE_X18Y17 RAMD32 r u_regfile/rf_reg_r1_0_31_6_11/RAMB/I ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 1.038 -0.270 u_regfile/rf_reg_r1_0_31_6_11/WCLK SLICE_X18Y17 RAMD32 r u_regfile/rf_reg_r1_0_31_6_11/RAMB/CLK clock pessimism -0.219 -0.489 SLICE_X18Y17 RAMD32 (Hold_ramd32_CLK_I) 0.146 -0.343 u_regfile/rf_reg_r1_0_31_6_11/RAMB ------------------------------------------------------------------- required time 0.343 arrival time -0.227 ------------------------------------------------------------------- slack 0.116 Slack (MET) : 0.117ns (arrival time - required time) Source: u_cpu/axi_bridge/wstrb_reg[1]/C (rising edge-triggered cell FDSE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Destination: u_Axi_CDC/wFifo/ram_reg_0_7_30_35/RAMB_D1/I (rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Path Group: cpu_clk Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) Data Path Delay: 0.257ns (logic 0.141ns (54.812%) route 0.116ns (45.188%)) Logic Levels: 0 Clock Path Skew: 0.016ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.336ns Source Clock Delay (SCD): -0.567ns Clock Pessimism Removal (CPR): 0.215ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 0.695 -0.567 u_cpu/axi_bridge/cpu_clk SLICE_X11Y54 FDSE r u_cpu/axi_bridge/wstrb_reg[1]/C ------------------------------------------------------------------- ------------------- SLICE_X11Y54 FDSE (Prop_fdse_C_Q) 0.141 -0.426 r u_cpu/axi_bridge/wstrb_reg[1]/Q net (fo=1, routed) 0.116 -0.310 u_Axi_CDC/wFifo/ram_reg_0_7_30_35/DIB1 SLICE_X10Y56 RAMD32 r u_Axi_CDC/wFifo/ram_reg_0_7_30_35/RAMB_D1/I ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 0.972 -0.336 u_Axi_CDC/wFifo/ram_reg_0_7_30_35/WCLK SLICE_X10Y56 RAMD32 r u_Axi_CDC/wFifo/ram_reg_0_7_30_35/RAMB_D1/CLK clock pessimism -0.215 -0.551 SLICE_X10Y56 RAMD32 (Hold_ramd32_CLK_I) 0.124 -0.427 u_Axi_CDC/wFifo/ram_reg_0_7_30_35/RAMB_D1 ------------------------------------------------------------------- required time 0.427 arrival time -0.310 ------------------------------------------------------------------- slack 0.117 Slack (MET) : 0.118ns (arrival time - required time) Source: u_cpu/u_csr/csr_tlbelo1_reg[22]/C (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Destination: u_cpu/addr_trans/tlb_entry/tlb_ppn1_reg_r2_0_31_12_17/RAMB/I (rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Path Group: cpu_clk Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) Data Path Delay: 0.278ns (logic 0.141ns (50.687%) route 0.137ns (49.313%)) Logic Levels: 0 Clock Path Skew: 0.014ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.274ns Source Clock Delay (SCD): -0.507ns Clock Pessimism Removal (CPR): 0.219ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 0.756 -0.507 u_cpu/u_csr/cpu_clk SLICE_X17Y27 FDRE r u_cpu/u_csr/csr_tlbelo1_reg[22]/C ------------------------------------------------------------------- ------------------- SLICE_X17Y27 FDRE (Prop_fdre_C_Q) 0.141 -0.366 r u_cpu/u_csr/csr_tlbelo1_reg[22]/Q net (fo=4, routed) 0.137 -0.229 u_cpu/addr_trans/tlb_entry/tlb_ppn1_reg_r2_0_31_12_17/DIB0 SLICE_X18Y28 RAMD32 r u_cpu/addr_trans/tlb_entry/tlb_ppn1_reg_r2_0_31_12_17/RAMB/I ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 1.034 -0.274 u_cpu/addr_trans/tlb_entry/tlb_ppn1_reg_r2_0_31_12_17/WCLK SLICE_X18Y28 RAMD32 r u_cpu/addr_trans/tlb_entry/tlb_ppn1_reg_r2_0_31_12_17/RAMB/CLK clock pessimism -0.219 -0.493 SLICE_X18Y28 RAMD32 (Hold_ramd32_CLK_I) 0.146 -0.347 u_cpu/addr_trans/tlb_entry/tlb_ppn1_reg_r2_0_31_12_17/RAMB ------------------------------------------------------------------- required time 0.347 arrival time -0.229 ------------------------------------------------------------------- slack 0.118 Slack (MET) : 0.121ns (arrival time - required time) Source: u_Axi_CDC/bFifo/pushToPopGray_buffercc/buffers_0_reg[2]/C (rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Destination: u_Axi_CDC/bFifo/pushToPopGray_buffercc/buffers_1_reg[2]/D (rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Path Group: cpu_clk Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) Data Path Delay: 0.197ns (logic 0.141ns (71.611%) route 0.056ns (28.389%)) Logic Levels: 0 Clock Path Skew: 0.000ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.341ns Source Clock Delay (SCD): -0.570ns Clock Pessimism Removal (CPR): 0.229ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 0.692 -0.570 u_Axi_CDC/bFifo/pushToPopGray_buffercc/cpu_clk SLICE_X15Y62 FDCE r u_Axi_CDC/bFifo/pushToPopGray_buffercc/buffers_0_reg[2]/C ------------------------------------------------------------------- ------------------- SLICE_X15Y62 FDCE (Prop_fdce_C_Q) 0.141 -0.429 r u_Axi_CDC/bFifo/pushToPopGray_buffercc/buffers_0_reg[2]/Q net (fo=1, routed) 0.056 -0.373 u_Axi_CDC/bFifo/pushToPopGray_buffercc/buffers_0[2] SLICE_X15Y62 FDCE r u_Axi_CDC/bFifo/pushToPopGray_buffercc/buffers_1_reg[2]/D ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 0.967 -0.341 u_Axi_CDC/bFifo/pushToPopGray_buffercc/cpu_clk SLICE_X15Y62 FDCE r u_Axi_CDC/bFifo/pushToPopGray_buffercc/buffers_1_reg[2]/C clock pessimism -0.229 -0.570 SLICE_X15Y62 FDCE (Hold_fdce_C_D) 0.076 -0.494 u_Axi_CDC/bFifo/pushToPopGray_buffercc/buffers_1_reg[2] ------------------------------------------------------------------- required time 0.494 arrival time -0.373 ------------------------------------------------------------------- slack 0.121 Slack (MET) : 0.121ns (arrival time - required time) Source: u_cpu/wb_stage/ms_to_ws_bus_r_reg[64]/C (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Destination: u_regfile/rf_reg_r1_0_31_24_29/RAMA/WADR0 (rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Path Group: cpu_clk Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) Data Path Delay: 0.444ns (logic 0.141ns (31.736%) route 0.303ns (68.264%)) Logic Levels: 0 Clock Path Skew: 0.013ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.270ns Source Clock Delay (SCD): -0.501ns Clock Pessimism Removal (CPR): 0.218ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 0.762 -0.501 u_cpu/wb_stage/cpu_clk SLICE_X13Y17 FDRE r u_cpu/wb_stage/ms_to_ws_bus_r_reg[64]/C ------------------------------------------------------------------- ------------------- SLICE_X13Y17 FDRE (Prop_fdre_C_Q) 0.141 -0.360 r u_cpu/wb_stage/ms_to_ws_bus_r_reg[64]/Q net (fo=164, routed) 0.303 -0.056 u_regfile/rf_reg_r1_0_31_24_29/ADDRD0 SLICE_X14Y18 RAMD32 r u_regfile/rf_reg_r1_0_31_24_29/RAMA/WADR0 ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 1.038 -0.270 u_regfile/rf_reg_r1_0_31_24_29/WCLK SLICE_X14Y18 RAMD32 r u_regfile/rf_reg_r1_0_31_24_29/RAMA/CLK clock pessimism -0.218 -0.488 SLICE_X14Y18 RAMD32 (Hold_ramd32_CLK_WADR0) 0.310 -0.178 u_regfile/rf_reg_r1_0_31_24_29/RAMA ------------------------------------------------------------------- required time 0.178 arrival time -0.056 ------------------------------------------------------------------- slack 0.121 Slack (MET) : 0.121ns (arrival time - required time) Source: u_cpu/wb_stage/ms_to_ws_bus_r_reg[64]/C (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Destination: u_regfile/rf_reg_r1_0_31_24_29/RAMA_D1/WADR0 (rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Path Group: cpu_clk Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) Data Path Delay: 0.444ns (logic 0.141ns (31.736%) route 0.303ns (68.264%)) Logic Levels: 0 Clock Path Skew: 0.013ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.270ns Source Clock Delay (SCD): -0.501ns Clock Pessimism Removal (CPR): 0.218ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 0.762 -0.501 u_cpu/wb_stage/cpu_clk SLICE_X13Y17 FDRE r u_cpu/wb_stage/ms_to_ws_bus_r_reg[64]/C ------------------------------------------------------------------- ------------------- SLICE_X13Y17 FDRE (Prop_fdre_C_Q) 0.141 -0.360 r u_cpu/wb_stage/ms_to_ws_bus_r_reg[64]/Q net (fo=164, routed) 0.303 -0.056 u_regfile/rf_reg_r1_0_31_24_29/ADDRD0 SLICE_X14Y18 RAMD32 r u_regfile/rf_reg_r1_0_31_24_29/RAMA_D1/WADR0 ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 1.038 -0.270 u_regfile/rf_reg_r1_0_31_24_29/WCLK SLICE_X14Y18 RAMD32 r u_regfile/rf_reg_r1_0_31_24_29/RAMA_D1/CLK clock pessimism -0.218 -0.488 SLICE_X14Y18 RAMD32 (Hold_ramd32_CLK_WADR0) 0.310 -0.178 u_regfile/rf_reg_r1_0_31_24_29/RAMA_D1 ------------------------------------------------------------------- required time 0.178 arrival time -0.056 ------------------------------------------------------------------- slack 0.121 Slack (MET) : 0.121ns (arrival time - required time) Source: u_cpu/wb_stage/ms_to_ws_bus_r_reg[64]/C (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Destination: u_regfile/rf_reg_r1_0_31_24_29/RAMB/WADR0 (rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Path Group: cpu_clk Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) Data Path Delay: 0.444ns (logic 0.141ns (31.736%) route 0.303ns (68.264%)) Logic Levels: 0 Clock Path Skew: 0.013ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.270ns Source Clock Delay (SCD): -0.501ns Clock Pessimism Removal (CPR): 0.218ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 0.762 -0.501 u_cpu/wb_stage/cpu_clk SLICE_X13Y17 FDRE r u_cpu/wb_stage/ms_to_ws_bus_r_reg[64]/C ------------------------------------------------------------------- ------------------- SLICE_X13Y17 FDRE (Prop_fdre_C_Q) 0.141 -0.360 r u_cpu/wb_stage/ms_to_ws_bus_r_reg[64]/Q net (fo=164, routed) 0.303 -0.056 u_regfile/rf_reg_r1_0_31_24_29/ADDRD0 SLICE_X14Y18 RAMD32 r u_regfile/rf_reg_r1_0_31_24_29/RAMB/WADR0 ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 1.038 -0.270 u_regfile/rf_reg_r1_0_31_24_29/WCLK SLICE_X14Y18 RAMD32 r u_regfile/rf_reg_r1_0_31_24_29/RAMB/CLK clock pessimism -0.218 -0.488 SLICE_X14Y18 RAMD32 (Hold_ramd32_CLK_WADR0) 0.310 -0.178 u_regfile/rf_reg_r1_0_31_24_29/RAMB ------------------------------------------------------------------- required time 0.178 arrival time -0.056 ------------------------------------------------------------------- slack 0.121 Slack (MET) : 0.121ns (arrival time - required time) Source: u_cpu/wb_stage/ms_to_ws_bus_r_reg[64]/C (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Destination: u_regfile/rf_reg_r1_0_31_24_29/RAMB_D1/WADR0 (rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Path Group: cpu_clk Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) Data Path Delay: 0.444ns (logic 0.141ns (31.736%) route 0.303ns (68.264%)) Logic Levels: 0 Clock Path Skew: 0.013ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.270ns Source Clock Delay (SCD): -0.501ns Clock Pessimism Removal (CPR): 0.218ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 0.762 -0.501 u_cpu/wb_stage/cpu_clk SLICE_X13Y17 FDRE r u_cpu/wb_stage/ms_to_ws_bus_r_reg[64]/C ------------------------------------------------------------------- ------------------- SLICE_X13Y17 FDRE (Prop_fdre_C_Q) 0.141 -0.360 r u_cpu/wb_stage/ms_to_ws_bus_r_reg[64]/Q net (fo=164, routed) 0.303 -0.056 u_regfile/rf_reg_r1_0_31_24_29/ADDRD0 SLICE_X14Y18 RAMD32 r u_regfile/rf_reg_r1_0_31_24_29/RAMB_D1/WADR0 ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 1.038 -0.270 u_regfile/rf_reg_r1_0_31_24_29/WCLK SLICE_X14Y18 RAMD32 r u_regfile/rf_reg_r1_0_31_24_29/RAMB_D1/CLK clock pessimism -0.218 -0.488 SLICE_X14Y18 RAMD32 (Hold_ramd32_CLK_WADR0) 0.310 -0.178 u_regfile/rf_reg_r1_0_31_24_29/RAMB_D1 ------------------------------------------------------------------- required time 0.178 arrival time -0.056 ------------------------------------------------------------------- slack 0.121 Slack (MET) : 0.121ns (arrival time - required time) Source: u_cpu/wb_stage/ms_to_ws_bus_r_reg[64]/C (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Destination: u_regfile/rf_reg_r1_0_31_24_29/RAMC/WADR0 (rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Path Group: cpu_clk Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) Data Path Delay: 0.444ns (logic 0.141ns (31.736%) route 0.303ns (68.264%)) Logic Levels: 0 Clock Path Skew: 0.013ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.270ns Source Clock Delay (SCD): -0.501ns Clock Pessimism Removal (CPR): 0.218ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 0.762 -0.501 u_cpu/wb_stage/cpu_clk SLICE_X13Y17 FDRE r u_cpu/wb_stage/ms_to_ws_bus_r_reg[64]/C ------------------------------------------------------------------- ------------------- SLICE_X13Y17 FDRE (Prop_fdre_C_Q) 0.141 -0.360 r u_cpu/wb_stage/ms_to_ws_bus_r_reg[64]/Q net (fo=164, routed) 0.303 -0.056 u_regfile/rf_reg_r1_0_31_24_29/ADDRD0 SLICE_X14Y18 RAMD32 r u_regfile/rf_reg_r1_0_31_24_29/RAMC/WADR0 ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 1.038 -0.270 u_regfile/rf_reg_r1_0_31_24_29/WCLK SLICE_X14Y18 RAMD32 r u_regfile/rf_reg_r1_0_31_24_29/RAMC/CLK clock pessimism -0.218 -0.488 SLICE_X14Y18 RAMD32 (Hold_ramd32_CLK_WADR0) 0.310 -0.178 u_regfile/rf_reg_r1_0_31_24_29/RAMC ------------------------------------------------------------------- required time 0.178 arrival time -0.056 ------------------------------------------------------------------- slack 0.121 Slack (MET) : 0.121ns (arrival time - required time) Source: u_cpu/wb_stage/ms_to_ws_bus_r_reg[64]/C (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Destination: u_regfile/rf_reg_r1_0_31_24_29/RAMC_D1/WADR0 (rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Path Group: cpu_clk Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) Data Path Delay: 0.444ns (logic 0.141ns (31.736%) route 0.303ns (68.264%)) Logic Levels: 0 Clock Path Skew: 0.013ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.270ns Source Clock Delay (SCD): -0.501ns Clock Pessimism Removal (CPR): 0.218ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 0.762 -0.501 u_cpu/wb_stage/cpu_clk SLICE_X13Y17 FDRE r u_cpu/wb_stage/ms_to_ws_bus_r_reg[64]/C ------------------------------------------------------------------- ------------------- SLICE_X13Y17 FDRE (Prop_fdre_C_Q) 0.141 -0.360 r u_cpu/wb_stage/ms_to_ws_bus_r_reg[64]/Q net (fo=164, routed) 0.303 -0.056 u_regfile/rf_reg_r1_0_31_24_29/ADDRD0 SLICE_X14Y18 RAMD32 r u_regfile/rf_reg_r1_0_31_24_29/RAMC_D1/WADR0 ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 1.038 -0.270 u_regfile/rf_reg_r1_0_31_24_29/WCLK SLICE_X14Y18 RAMD32 r u_regfile/rf_reg_r1_0_31_24_29/RAMC_D1/CLK clock pessimism -0.218 -0.488 SLICE_X14Y18 RAMD32 (Hold_ramd32_CLK_WADR0) 0.310 -0.178 u_regfile/rf_reg_r1_0_31_24_29/RAMC_D1 ------------------------------------------------------------------- required time 0.178 arrival time -0.056 ------------------------------------------------------------------- slack 0.121 Slack (MET) : 0.121ns (arrival time - required time) Source: u_cpu/wb_stage/ms_to_ws_bus_r_reg[64]/C (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Destination: u_regfile/rf_reg_r1_0_31_24_29/RAMD/ADR0 (rising edge-triggered cell RAMS32 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Path Group: cpu_clk Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) Data Path Delay: 0.444ns (logic 0.141ns (31.736%) route 0.303ns (68.264%)) Logic Levels: 0 Clock Path Skew: 0.013ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.270ns Source Clock Delay (SCD): -0.501ns Clock Pessimism Removal (CPR): 0.218ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 0.762 -0.501 u_cpu/wb_stage/cpu_clk SLICE_X13Y17 FDRE r u_cpu/wb_stage/ms_to_ws_bus_r_reg[64]/C ------------------------------------------------------------------- ------------------- SLICE_X13Y17 FDRE (Prop_fdre_C_Q) 0.141 -0.360 r u_cpu/wb_stage/ms_to_ws_bus_r_reg[64]/Q net (fo=164, routed) 0.303 -0.056 u_regfile/rf_reg_r1_0_31_24_29/ADDRD0 SLICE_X14Y18 RAMS32 r u_regfile/rf_reg_r1_0_31_24_29/RAMD/ADR0 ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 1.038 -0.270 u_regfile/rf_reg_r1_0_31_24_29/WCLK SLICE_X14Y18 RAMS32 r u_regfile/rf_reg_r1_0_31_24_29/RAMD/CLK clock pessimism -0.218 -0.488 SLICE_X14Y18 RAMS32 (Hold_rams32_CLK_ADR0) 0.310 -0.178 u_regfile/rf_reg_r1_0_31_24_29/RAMD ------------------------------------------------------------------- required time 0.178 arrival time -0.056 ------------------------------------------------------------------- slack 0.121 Slack (MET) : 0.121ns (arrival time - required time) Source: u_cpu/wb_stage/ms_to_ws_bus_r_reg[64]/C (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Destination: u_regfile/rf_reg_r1_0_31_24_29/RAMD_D1/ADR0 (rising edge-triggered cell RAMS32 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Path Group: cpu_clk Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) Data Path Delay: 0.444ns (logic 0.141ns (31.736%) route 0.303ns (68.264%)) Logic Levels: 0 Clock Path Skew: 0.013ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.270ns Source Clock Delay (SCD): -0.501ns Clock Pessimism Removal (CPR): 0.218ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 0.762 -0.501 u_cpu/wb_stage/cpu_clk SLICE_X13Y17 FDRE r u_cpu/wb_stage/ms_to_ws_bus_r_reg[64]/C ------------------------------------------------------------------- ------------------- SLICE_X13Y17 FDRE (Prop_fdre_C_Q) 0.141 -0.360 r u_cpu/wb_stage/ms_to_ws_bus_r_reg[64]/Q net (fo=164, routed) 0.303 -0.056 u_regfile/rf_reg_r1_0_31_24_29/ADDRD0 SLICE_X14Y18 RAMS32 r u_regfile/rf_reg_r1_0_31_24_29/RAMD_D1/ADR0 ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 1.038 -0.270 u_regfile/rf_reg_r1_0_31_24_29/WCLK SLICE_X14Y18 RAMS32 r u_regfile/rf_reg_r1_0_31_24_29/RAMD_D1/CLK clock pessimism -0.218 -0.488 SLICE_X14Y18 RAMS32 (Hold_rams32_CLK_ADR0) 0.310 -0.178 u_regfile/rf_reg_r1_0_31_24_29/RAMD_D1 ------------------------------------------------------------------- required time 0.178 arrival time -0.056 ------------------------------------------------------------------- slack 0.121 Slack (MET) : 0.122ns (arrival time - required time) Source: u_Axi_CDC/bFifo/pushToPopGray_buffercc/buffers_0_reg[0]/C (rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Destination: u_Axi_CDC/bFifo/pushToPopGray_buffercc/buffers_1_reg[0]/D (rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Path Group: cpu_clk Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) Data Path Delay: 0.197ns (logic 0.141ns (71.611%) route 0.056ns (28.389%)) Logic Levels: 0 Clock Path Skew: 0.000ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.341ns Source Clock Delay (SCD): -0.570ns Clock Pessimism Removal (CPR): 0.229ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 0.692 -0.570 u_Axi_CDC/bFifo/pushToPopGray_buffercc/cpu_clk SLICE_X15Y62 FDCE r u_Axi_CDC/bFifo/pushToPopGray_buffercc/buffers_0_reg[0]/C ------------------------------------------------------------------- ------------------- SLICE_X15Y62 FDCE (Prop_fdce_C_Q) 0.141 -0.429 r u_Axi_CDC/bFifo/pushToPopGray_buffercc/buffers_0_reg[0]/Q net (fo=1, routed) 0.056 -0.373 u_Axi_CDC/bFifo/pushToPopGray_buffercc/buffers_0[0] SLICE_X15Y62 FDCE r u_Axi_CDC/bFifo/pushToPopGray_buffercc/buffers_1_reg[0]/D ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 0.967 -0.341 u_Axi_CDC/bFifo/pushToPopGray_buffercc/cpu_clk SLICE_X15Y62 FDCE r u_Axi_CDC/bFifo/pushToPopGray_buffercc/buffers_1_reg[0]/C clock pessimism -0.229 -0.570 SLICE_X15Y62 FDCE (Hold_fdce_C_D) 0.075 -0.495 u_Axi_CDC/bFifo/pushToPopGray_buffercc/buffers_1_reg[0] ------------------------------------------------------------------- required time 0.495 arrival time -0.373 ------------------------------------------------------------------- slack 0.122 Slack (MET) : 0.122ns (arrival time - required time) Source: u_Axi_CDC/wFifo/popToPushGray_buffercc/buffers_0_reg[0]/C (rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Destination: u_Axi_CDC/wFifo/popToPushGray_buffercc/buffers_1_reg[0]/D (rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Path Group: cpu_clk Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) Data Path Delay: 0.197ns (logic 0.141ns (71.611%) route 0.056ns (28.389%)) Logic Levels: 0 Clock Path Skew: 0.000ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.337ns Source Clock Delay (SCD): -0.568ns Clock Pessimism Removal (CPR): 0.231ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 0.694 -0.568 u_Axi_CDC/wFifo/popToPushGray_buffercc/cpu_clk SLICE_X9Y59 FDCE r u_Axi_CDC/wFifo/popToPushGray_buffercc/buffers_0_reg[0]/C ------------------------------------------------------------------- ------------------- SLICE_X9Y59 FDCE (Prop_fdce_C_Q) 0.141 -0.427 r u_Axi_CDC/wFifo/popToPushGray_buffercc/buffers_0_reg[0]/Q net (fo=1, routed) 0.056 -0.371 u_Axi_CDC/wFifo/popToPushGray_buffercc/buffers_0[0] SLICE_X9Y59 FDCE r u_Axi_CDC/wFifo/popToPushGray_buffercc/buffers_1_reg[0]/D ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 0.971 -0.337 u_Axi_CDC/wFifo/popToPushGray_buffercc/cpu_clk SLICE_X9Y59 FDCE r u_Axi_CDC/wFifo/popToPushGray_buffercc/buffers_1_reg[0]/C clock pessimism -0.231 -0.568 SLICE_X9Y59 FDCE (Hold_fdce_C_D) 0.075 -0.493 u_Axi_CDC/wFifo/popToPushGray_buffercc/buffers_1_reg[0] ------------------------------------------------------------------- required time 0.493 arrival time -0.371 ------------------------------------------------------------------- slack 0.122 Slack (MET) : 0.122ns (arrival time - required time) Source: u_cpu/axi_bridge/awaddr_reg[1]/C (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Destination: u_Axi_CDC/awFifo/ram_reg_0_3_0_5/RAMA_D1/I (rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Path Group: cpu_clk Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) Data Path Delay: 0.257ns (logic 0.141ns (54.812%) route 0.116ns (45.188%)) Logic Levels: 0 Clock Path Skew: 0.015ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.339ns Source Clock Delay (SCD): -0.568ns Clock Pessimism Removal (CPR): 0.214ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 0.694 -0.568 u_cpu/axi_bridge/cpu_clk SLICE_X17Y58 FDRE r u_cpu/axi_bridge/awaddr_reg[1]/C ------------------------------------------------------------------- ------------------- SLICE_X17Y58 FDRE (Prop_fdre_C_Q) 0.141 -0.427 r u_cpu/axi_bridge/awaddr_reg[1]/Q net (fo=1, routed) 0.116 -0.311 u_Axi_CDC/awFifo/ram_reg_0_3_0_5/DIA1 SLICE_X16Y60 RAMD32 r u_Axi_CDC/awFifo/ram_reg_0_3_0_5/RAMA_D1/I ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 0.969 -0.339 u_Axi_CDC/awFifo/ram_reg_0_3_0_5/WCLK SLICE_X16Y60 RAMD32 r u_Axi_CDC/awFifo/ram_reg_0_3_0_5/RAMA_D1/CLK clock pessimism -0.214 -0.553 SLICE_X16Y60 RAMD32 (Hold_ramd32_CLK_I) 0.120 -0.433 u_Axi_CDC/awFifo/ram_reg_0_3_0_5/RAMA_D1 ------------------------------------------------------------------- required time 0.433 arrival time -0.311 ------------------------------------------------------------------- slack 0.122 Slack (MET) : 0.123ns (arrival time - required time) Source: u_cpu/u_csr/csr_tlbelo1_reg[12]/C (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Destination: u_cpu/addr_trans/tlb_entry/tlb_ppn1_reg_r3_0_31_0_5/RAMC/I (rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Path Group: cpu_clk Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) Data Path Delay: 0.303ns (logic 0.141ns (46.480%) route 0.162ns (53.520%)) Logic Levels: 0 Clock Path Skew: 0.036ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.278ns Source Clock Delay (SCD): -0.510ns Clock Pessimism Removal (CPR): 0.196ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 0.753 -0.510 u_cpu/u_csr/cpu_clk SLICE_X19Y24 FDRE r u_cpu/u_csr/csr_tlbelo1_reg[12]/C ------------------------------------------------------------------- ------------------- SLICE_X19Y24 FDRE (Prop_fdre_C_Q) 0.141 -0.369 r u_cpu/u_csr/csr_tlbelo1_reg[12]/Q net (fo=4, routed) 0.162 -0.206 u_cpu/addr_trans/tlb_entry/tlb_ppn1_reg_r3_0_31_0_5/DIC0 SLICE_X18Y25 RAMD32 r u_cpu/addr_trans/tlb_entry/tlb_ppn1_reg_r3_0_31_0_5/RAMC/I ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 1.030 -0.278 u_cpu/addr_trans/tlb_entry/tlb_ppn1_reg_r3_0_31_0_5/WCLK SLICE_X18Y25 RAMD32 r u_cpu/addr_trans/tlb_entry/tlb_ppn1_reg_r3_0_31_0_5/RAMC/CLK clock pessimism -0.196 -0.474 SLICE_X18Y25 RAMD32 (Hold_ramd32_CLK_I) 0.144 -0.330 u_cpu/addr_trans/tlb_entry/tlb_ppn1_reg_r3_0_31_0_5/RAMC ------------------------------------------------------------------- required time 0.330 arrival time -0.206 ------------------------------------------------------------------- slack 0.123 Pulse Width Checks -------------------------------------------------------------------------------------- Clock Name: cpu_clk Waveform(ns): { 0.000 15.161 } Period(ns): 30.323 Sources: { pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 } Check Type Corner Lib Pin Reference Pin Required(ns) Actual(ns) Slack(ns) Location Pin Min Period n/a RAMB18E1/CLKARDCLK n/a 2.944 30.323 27.379 RAMB18_X0Y9 u_cpu/dcache/data_ram_way[0].data_ram_bank[0].u/mem_reg_reg/CLKARDCLK Min Period n/a RAMB18E1/CLKBWRCLK n/a 2.944 30.323 27.379 RAMB18_X0Y9 u_cpu/dcache/data_ram_way[0].data_ram_bank[0].u/mem_reg_reg/CLKBWRCLK Min Period n/a RAMB18E1/CLKARDCLK n/a 2.944 30.323 27.379 RAMB18_X0Y5 u_cpu/dcache/data_ram_way[0].data_ram_bank[1].u/mem_reg_reg/CLKARDCLK Min Period n/a RAMB18E1/CLKBWRCLK n/a 2.944 30.323 27.379 RAMB18_X0Y5 u_cpu/dcache/data_ram_way[0].data_ram_bank[1].u/mem_reg_reg/CLKBWRCLK Min Period n/a RAMB18E1/CLKARDCLK n/a 2.944 30.323 27.379 RAMB18_X0Y10 u_cpu/dcache/data_ram_way[0].data_ram_bank[2].u/mem_reg_reg/CLKARDCLK Min Period n/a RAMB18E1/CLKBWRCLK n/a 2.944 30.323 27.379 RAMB18_X0Y10 u_cpu/dcache/data_ram_way[0].data_ram_bank[2].u/mem_reg_reg/CLKBWRCLK Min Period n/a RAMB18E1/CLKARDCLK n/a 2.944 30.323 27.379 RAMB18_X0Y7 u_cpu/dcache/data_ram_way[0].data_ram_bank[3].u/mem_reg_reg/CLKARDCLK Min Period n/a RAMB18E1/CLKBWRCLK n/a 2.944 30.323 27.379 RAMB18_X0Y7 u_cpu/dcache/data_ram_way[0].data_ram_bank[3].u/mem_reg_reg/CLKBWRCLK Min Period n/a RAMB18E1/CLKARDCLK n/a 2.944 30.323 27.379 RAMB18_X0Y4 u_cpu/dcache/data_ram_way[1].data_ram_bank[0].u/mem_reg_reg/CLKARDCLK Min Period n/a RAMB18E1/CLKBWRCLK n/a 2.944 30.323 27.379 RAMB18_X0Y4 u_cpu/dcache/data_ram_way[1].data_ram_bank[0].u/mem_reg_reg/CLKBWRCLK Min Period n/a RAMB18E1/CLKARDCLK n/a 2.944 30.323 27.379 RAMB18_X0Y8 u_cpu/dcache/data_ram_way[1].data_ram_bank[1].u/mem_reg_reg/CLKARDCLK Min Period n/a RAMB18E1/CLKBWRCLK n/a 2.944 30.323 27.379 RAMB18_X0Y8 u_cpu/dcache/data_ram_way[1].data_ram_bank[1].u/mem_reg_reg/CLKBWRCLK Min Period n/a RAMB18E1/CLKARDCLK n/a 2.944 30.323 27.379 RAMB18_X0Y6 u_cpu/dcache/data_ram_way[1].data_ram_bank[2].u/mem_reg_reg/CLKARDCLK Min Period n/a RAMB18E1/CLKBWRCLK n/a 2.944 30.323 27.379 RAMB18_X0Y6 u_cpu/dcache/data_ram_way[1].data_ram_bank[2].u/mem_reg_reg/CLKBWRCLK Min Period n/a RAMB18E1/CLKARDCLK n/a 2.944 30.323 27.379 RAMB18_X0Y11 u_cpu/dcache/data_ram_way[1].data_ram_bank[3].u/mem_reg_reg/CLKARDCLK Min Period n/a RAMB18E1/CLKBWRCLK n/a 2.944 30.323 27.379 RAMB18_X0Y11 u_cpu/dcache/data_ram_way[1].data_ram_bank[3].u/mem_reg_reg/CLKBWRCLK Min Period n/a RAMB18E1/CLKARDCLK n/a 2.944 30.323 27.379 RAMB18_X1Y0 u_cpu/icache/data_ram_way[0].data_ram_bank[0].u/mem_reg_reg/CLKARDCLK Min Period n/a RAMB18E1/CLKBWRCLK n/a 2.944 30.323 27.379 RAMB18_X1Y0 u_cpu/icache/data_ram_way[0].data_ram_bank[0].u/mem_reg_reg/CLKBWRCLK Min Period n/a RAMB18E1/CLKARDCLK n/a 2.944 30.323 27.379 RAMB18_X1Y1 u_cpu/icache/data_ram_way[0].data_ram_bank[1].u/mem_reg_reg/CLKARDCLK Min Period n/a RAMB18E1/CLKBWRCLK n/a 2.944 30.323 27.379 RAMB18_X1Y1 u_cpu/icache/data_ram_way[0].data_ram_bank[1].u/mem_reg_reg/CLKBWRCLK Min Period n/a RAMB18E1/CLKARDCLK n/a 2.944 30.323 27.379 RAMB18_X1Y2 u_cpu/icache/data_ram_way[0].data_ram_bank[2].u/mem_reg_reg/CLKARDCLK Min Period n/a RAMB18E1/CLKBWRCLK n/a 2.944 30.323 27.379 RAMB18_X1Y2 u_cpu/icache/data_ram_way[0].data_ram_bank[2].u/mem_reg_reg/CLKBWRCLK Min Period n/a RAMB18E1/CLKARDCLK n/a 2.944 30.323 27.379 RAMB18_X1Y3 u_cpu/icache/data_ram_way[0].data_ram_bank[3].u/mem_reg_reg/CLKARDCLK Min Period n/a RAMB18E1/CLKBWRCLK n/a 2.944 30.323 27.379 RAMB18_X1Y3 u_cpu/icache/data_ram_way[0].data_ram_bank[3].u/mem_reg_reg/CLKBWRCLK Min Period n/a RAMB18E1/CLKARDCLK n/a 2.944 30.323 27.379 RAMB18_X0Y2 u_cpu/icache/data_ram_way[1].data_ram_bank[0].u/mem_reg_reg/CLKARDCLK Min Period n/a RAMB18E1/CLKBWRCLK n/a 2.944 30.323 27.379 RAMB18_X0Y2 u_cpu/icache/data_ram_way[1].data_ram_bank[0].u/mem_reg_reg/CLKBWRCLK Min Period n/a RAMB18E1/CLKARDCLK n/a 2.944 30.323 27.379 RAMB18_X0Y0 u_cpu/icache/data_ram_way[1].data_ram_bank[1].u/mem_reg_reg/CLKARDCLK Min Period n/a RAMB18E1/CLKBWRCLK n/a 2.944 30.323 27.379 RAMB18_X0Y0 u_cpu/icache/data_ram_way[1].data_ram_bank[1].u/mem_reg_reg/CLKBWRCLK Min Period n/a RAMB18E1/CLKARDCLK n/a 2.944 30.323 27.379 RAMB18_X0Y1 u_cpu/icache/data_ram_way[1].data_ram_bank[2].u/mem_reg_reg/CLKARDCLK Min Period n/a RAMB18E1/CLKBWRCLK n/a 2.944 30.323 27.379 RAMB18_X0Y1 u_cpu/icache/data_ram_way[1].data_ram_bank[2].u/mem_reg_reg/CLKBWRCLK Min Period n/a RAMB18E1/CLKARDCLK n/a 2.944 30.323 27.379 RAMB18_X0Y3 u_cpu/icache/data_ram_way[1].data_ram_bank[3].u/mem_reg_reg/CLKARDCLK Min Period n/a RAMB18E1/CLKBWRCLK n/a 2.944 30.323 27.379 RAMB18_X0Y3 u_cpu/icache/data_ram_way[1].data_ram_bank[3].u/mem_reg_reg/CLKBWRCLK Min Period n/a RAMB18E1/CLKARDCLK n/a 2.576 30.323 27.747 RAMB18_X1Y5 u_cpu/dcache/tagv_ram_way[0].u/mem_reg_reg/CLKARDCLK Min Period n/a RAMB18E1/CLKBWRCLK n/a 2.576 30.323 27.747 RAMB18_X1Y5 u_cpu/dcache/tagv_ram_way[0].u/mem_reg_reg/CLKBWRCLK Min Period n/a RAMB18E1/CLKARDCLK n/a 2.576 30.323 27.747 RAMB18_X1Y4 u_cpu/dcache/tagv_ram_way[1].u/mem_reg_reg/CLKARDCLK Min Period n/a RAMB18E1/CLKBWRCLK n/a 2.576 30.323 27.747 RAMB18_X1Y4 u_cpu/dcache/tagv_ram_way[1].u/mem_reg_reg/CLKBWRCLK Min Period n/a RAMB18E1/CLKARDCLK n/a 2.576 30.323 27.747 RAMB18_X1Y7 u_cpu/icache/tagv_ram_way[0].u/mem_reg_reg/CLKARDCLK Min Period n/a RAMB18E1/CLKBWRCLK n/a 2.576 30.323 27.747 RAMB18_X1Y7 u_cpu/icache/tagv_ram_way[0].u/mem_reg_reg/CLKBWRCLK Min Period n/a RAMB18E1/CLKARDCLK n/a 2.576 30.323 27.747 RAMB18_X1Y6 u_cpu/icache/tagv_ram_way[1].u/mem_reg_reg/CLKARDCLK Min Period n/a RAMB18E1/CLKBWRCLK n/a 2.576 30.323 27.747 RAMB18_X1Y6 u_cpu/icache/tagv_ram_way[1].u/mem_reg_reg/CLKBWRCLK Min Period n/a BUFG/I n/a 2.155 30.323 28.167 BUFGCTRL_X0Y18 pll_clk.u_clk_pll/inst/clkout1_buf/I Min Period n/a PLLE2_ADV/CLKOUT0 n/a 1.249 30.323 29.074 PLLE2_ADV_X0Y3 pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 Min Period n/a FDCE/C n/a 1.000 30.323 29.323 SLICE_X6Y63 pll_clk.u_rst_cpu/delay_reg[0]/C Min Period n/a FDCE/C n/a 1.000 30.323 29.323 SLICE_X6Y63 pll_clk.u_rst_cpu/delay_reg[1]/C Min Period n/a FDCE/C n/a 1.000 30.323 29.323 SLICE_X18Y64 u_Axi_CDC/arFifo/popToPushGray_buffercc/buffers_0_reg[0]/C Min Period n/a FDCE/C n/a 1.000 30.323 29.323 SLICE_X18Y64 u_Axi_CDC/arFifo/popToPushGray_buffercc/buffers_0_reg[1]/C Min Period n/a FDCE/C n/a 1.000 30.323 29.323 SLICE_X18Y64 u_Axi_CDC/arFifo/popToPushGray_buffercc/buffers_0_reg[2]/C Min Period n/a FDCE/C n/a 1.000 30.323 29.323 SLICE_X18Y64 u_Axi_CDC/arFifo/popToPushGray_buffercc/buffers_1_reg[0]/C Min Period n/a FDCE/C n/a 1.000 30.323 29.323 SLICE_X18Y64 u_Axi_CDC/arFifo/popToPushGray_buffercc/buffers_1_reg[1]/C Min Period n/a FDCE/C n/a 1.000 30.323 29.323 SLICE_X18Y64 u_Axi_CDC/arFifo/popToPushGray_buffercc/buffers_1_reg[2]/C Max Period n/a PLLE2_ADV/CLKOUT0 n/a 160.000 30.323 129.677 PLLE2_ADV_X0Y3 pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 Low Pulse Width Fast RAMD32/CLK n/a 1.250 15.161 13.911 SLICE_X16Y18 u_regfile/rf_reg_r2_0_31_24_29/RAMA/CLK Low Pulse Width Fast RAMD32/CLK n/a 1.250 15.161 13.911 SLICE_X16Y18 u_regfile/rf_reg_r2_0_31_24_29/RAMA_D1/CLK Low Pulse Width Fast RAMD32/CLK n/a 1.250 15.161 13.911 SLICE_X16Y18 u_regfile/rf_reg_r2_0_31_24_29/RAMB/CLK Low Pulse Width Fast RAMD32/CLK n/a 1.250 15.161 13.911 SLICE_X16Y18 u_regfile/rf_reg_r2_0_31_24_29/RAMB_D1/CLK Low Pulse Width Fast RAMD32/CLK n/a 1.250 15.161 13.911 SLICE_X16Y18 u_regfile/rf_reg_r2_0_31_24_29/RAMC/CLK Low Pulse Width Fast RAMD32/CLK n/a 1.250 15.161 13.911 SLICE_X16Y18 u_regfile/rf_reg_r2_0_31_24_29/RAMC_D1/CLK Low Pulse Width Fast RAMS32/CLK n/a 1.250 15.161 13.911 SLICE_X16Y18 u_regfile/rf_reg_r2_0_31_24_29/RAMD/CLK Low Pulse Width Fast RAMS32/CLK n/a 1.250 15.161 13.911 SLICE_X16Y18 u_regfile/rf_reg_r2_0_31_24_29/RAMD_D1/CLK Low Pulse Width Fast RAMD32/CLK n/a 1.250 15.161 13.911 SLICE_X18Y16 u_regfile/rf_reg_r2_0_31_6_11/RAMA/CLK Low Pulse Width Fast RAMD32/CLK n/a 1.250 15.161 13.911 SLICE_X18Y16 u_regfile/rf_reg_r2_0_31_6_11/RAMA_D1/CLK Low Pulse Width Fast RAMD32/CLK n/a 1.250 15.161 13.911 SLICE_X18Y16 u_regfile/rf_reg_r2_0_31_6_11/RAMB/CLK Low Pulse Width Fast RAMD32/CLK n/a 1.250 15.161 13.911 SLICE_X18Y16 u_regfile/rf_reg_r2_0_31_6_11/RAMB_D1/CLK Low Pulse Width Fast RAMD32/CLK n/a 1.250 15.161 13.911 SLICE_X18Y16 u_regfile/rf_reg_r2_0_31_6_11/RAMC/CLK Low Pulse Width Fast RAMD32/CLK n/a 1.250 15.161 13.911 SLICE_X18Y16 u_regfile/rf_reg_r2_0_31_6_11/RAMC_D1/CLK Low Pulse Width Fast RAMS32/CLK n/a 1.250 15.161 13.911 SLICE_X18Y16 u_regfile/rf_reg_r2_0_31_6_11/RAMD/CLK Low Pulse Width Fast RAMS32/CLK n/a 1.250 15.161 13.911 SLICE_X18Y16 u_regfile/rf_reg_r2_0_31_6_11/RAMD_D1/CLK Low Pulse Width Slow RAMD32/CLK n/a 1.250 15.161 13.911 SLICE_X20Y59 u_Axi_CDC/awFifo/ram_reg_0_3_12_17/RAMA/CLK Low Pulse Width Slow RAMD32/CLK n/a 1.250 15.161 13.911 SLICE_X20Y59 u_Axi_CDC/awFifo/ram_reg_0_3_12_17/RAMA_D1/CLK Low Pulse Width Slow RAMD32/CLK n/a 1.250 15.161 13.911 SLICE_X20Y59 u_Axi_CDC/awFifo/ram_reg_0_3_12_17/RAMB/CLK Low Pulse Width Slow RAMD32/CLK n/a 1.250 15.161 13.911 SLICE_X20Y59 u_Axi_CDC/awFifo/ram_reg_0_3_12_17/RAMB_D1/CLK Low Pulse Width Slow RAMD32/CLK n/a 1.250 15.161 13.911 SLICE_X20Y59 u_Axi_CDC/awFifo/ram_reg_0_3_12_17/RAMC/CLK Low Pulse Width Slow RAMD32/CLK n/a 1.250 15.161 13.911 SLICE_X20Y59 u_Axi_CDC/awFifo/ram_reg_0_3_12_17/RAMC_D1/CLK Low Pulse Width Slow RAMS32/CLK n/a 1.250 15.161 13.911 SLICE_X20Y59 u_Axi_CDC/awFifo/ram_reg_0_3_12_17/RAMD/CLK Low Pulse Width Slow RAMS32/CLK n/a 1.250 15.161 13.911 SLICE_X20Y59 u_Axi_CDC/awFifo/ram_reg_0_3_12_17/RAMD_D1/CLK Low Pulse Width Slow RAMD32/CLK n/a 1.250 15.161 13.911 SLICE_X6Y57 u_Axi_CDC/wFifo/ram_reg_0_7_24_29/RAMA/CLK Low Pulse Width Slow RAMD32/CLK n/a 1.250 15.161 13.911 SLICE_X6Y57 u_Axi_CDC/wFifo/ram_reg_0_7_24_29/RAMA_D1/CLK Low Pulse Width Slow RAMD32/CLK n/a 1.250 15.161 13.911 SLICE_X6Y57 u_Axi_CDC/wFifo/ram_reg_0_7_24_29/RAMB/CLK Low Pulse Width Slow RAMD32/CLK n/a 1.250 15.161 13.911 SLICE_X6Y57 u_Axi_CDC/wFifo/ram_reg_0_7_24_29/RAMB_D1/CLK Low Pulse Width Slow RAMD32/CLK n/a 1.250 15.161 13.911 SLICE_X6Y57 u_Axi_CDC/wFifo/ram_reg_0_7_24_29/RAMC/CLK Low Pulse Width Slow RAMD32/CLK n/a 1.250 15.161 13.911 SLICE_X6Y57 u_Axi_CDC/wFifo/ram_reg_0_7_24_29/RAMC_D1/CLK Low Pulse Width Slow RAMS32/CLK n/a 1.250 15.161 13.911 SLICE_X6Y57 u_Axi_CDC/wFifo/ram_reg_0_7_24_29/RAMD/CLK Low Pulse Width Slow RAMS32/CLK n/a 1.250 15.161 13.911 SLICE_X6Y57 u_Axi_CDC/wFifo/ram_reg_0_7_24_29/RAMD_D1/CLK Low Pulse Width Slow RAMD32/CLK n/a 1.250 15.161 13.911 SLICE_X10Y56 u_Axi_CDC/wFifo/ram_reg_0_7_30_35/RAMA/CLK Low Pulse Width Slow RAMD32/CLK n/a 1.250 15.161 13.911 SLICE_X10Y56 u_Axi_CDC/wFifo/ram_reg_0_7_30_35/RAMA_D1/CLK Low Pulse Width Slow RAMD32/CLK n/a 1.250 15.161 13.911 SLICE_X10Y56 u_Axi_CDC/wFifo/ram_reg_0_7_30_35/RAMB/CLK Low Pulse Width Slow RAMD32/CLK n/a 1.250 15.161 13.911 SLICE_X10Y56 u_Axi_CDC/wFifo/ram_reg_0_7_30_35/RAMB_D1/CLK Low Pulse Width Slow RAMD32/CLK n/a 1.250 15.161 13.911 SLICE_X10Y56 u_Axi_CDC/wFifo/ram_reg_0_7_30_35/RAMC/CLK Low Pulse Width Slow RAMD32/CLK n/a 1.250 15.161 13.911 SLICE_X10Y56 u_Axi_CDC/wFifo/ram_reg_0_7_30_35/RAMC_D1/CLK Low Pulse Width Slow RAMS32/CLK n/a 1.250 15.161 13.911 SLICE_X10Y56 u_Axi_CDC/wFifo/ram_reg_0_7_30_35/RAMD/CLK Low Pulse Width Slow RAMS32/CLK n/a 1.250 15.161 13.911 SLICE_X10Y56 u_Axi_CDC/wFifo/ram_reg_0_7_30_35/RAMD_D1/CLK Low Pulse Width Slow RAMD32/CLK n/a 1.250 15.161 13.911 SLICE_X10Y57 u_Axi_CDC/wFifo/ram_reg_0_7_36_36/RAMA/CLK Low Pulse Width Slow RAMD32/CLK n/a 1.250 15.161 13.911 SLICE_X10Y57 u_Axi_CDC/wFifo/ram_reg_0_7_36_36/RAMA_D1/CLK Low Pulse Width Slow RAMD32/CLK n/a 1.250 15.161 13.911 SLICE_X10Y57 u_Axi_CDC/wFifo/ram_reg_0_7_36_36/RAMB/CLK Low Pulse Width Slow RAMD32/CLK n/a 1.250 15.161 13.911 SLICE_X10Y57 u_Axi_CDC/wFifo/ram_reg_0_7_36_36/RAMB_D1/CLK Low Pulse Width Slow RAMD32/CLK n/a 1.250 15.161 13.911 SLICE_X10Y57 u_Axi_CDC/wFifo/ram_reg_0_7_36_36/RAMC/CLK Low Pulse Width Slow RAMD32/CLK n/a 1.250 15.161 13.911 SLICE_X10Y57 u_Axi_CDC/wFifo/ram_reg_0_7_36_36/RAMC_D1/CLK Low Pulse Width Slow RAMS32/CLK n/a 1.250 15.161 13.911 SLICE_X10Y57 u_Axi_CDC/wFifo/ram_reg_0_7_36_36/RAMD/CLK Low Pulse Width Slow RAMS32/CLK n/a 1.250 15.161 13.911 SLICE_X10Y57 u_Axi_CDC/wFifo/ram_reg_0_7_36_36/RAMD_D1/CLK Low Pulse Width Fast RAMD32/CLK n/a 1.250 15.161 13.911 SLICE_X16Y29 u_cpu/addr_trans/tlb_entry/tlb_mat0_reg_r1_0_31_0_0/DP/CLK Low Pulse Width Fast RAMD32/CLK n/a 1.250 15.161 13.911 SLICE_X16Y29 u_cpu/addr_trans/tlb_entry/tlb_mat0_reg_r1_0_31_0_0/SP/CLK High Pulse Width Fast RAMD32/CLK n/a 1.250 15.161 13.911 SLICE_X16Y19 u_regfile/rf_reg_r1_0_31_30_31/RAMA/CLK High Pulse Width Fast RAMD32/CLK n/a 1.250 15.161 13.911 SLICE_X16Y19 u_regfile/rf_reg_r1_0_31_30_31/RAMA_D1/CLK High Pulse Width Fast RAMD32/CLK n/a 1.250 15.161 13.911 SLICE_X16Y19 u_regfile/rf_reg_r1_0_31_30_31/RAMB/CLK High Pulse Width Fast RAMD32/CLK n/a 1.250 15.161 13.911 SLICE_X16Y19 u_regfile/rf_reg_r1_0_31_30_31/RAMB_D1/CLK High Pulse Width Fast RAMD32/CLK n/a 1.250 15.161 13.911 SLICE_X16Y19 u_regfile/rf_reg_r1_0_31_30_31/RAMC/CLK High Pulse Width Fast RAMD32/CLK n/a 1.250 15.161 13.911 SLICE_X16Y19 u_regfile/rf_reg_r1_0_31_30_31/RAMC_D1/CLK High Pulse Width Fast RAMS32/CLK n/a 1.250 15.161 13.911 SLICE_X16Y19 u_regfile/rf_reg_r1_0_31_30_31/RAMD/CLK High Pulse Width Fast RAMS32/CLK n/a 1.250 15.161 13.911 SLICE_X16Y19 u_regfile/rf_reg_r1_0_31_30_31/RAMD_D1/CLK High Pulse Width Fast RAMD32/CLK n/a 1.250 15.161 13.911 SLICE_X22Y61 u_Axi_CDC/arFifo/ram_reg_0_3_12_17/RAMA/CLK High Pulse Width Fast RAMD32/CLK n/a 1.250 15.161 13.911 SLICE_X22Y61 u_Axi_CDC/arFifo/ram_reg_0_3_12_17/RAMA_D1/CLK High Pulse Width Fast RAMD32/CLK n/a 1.250 15.161 13.911 SLICE_X22Y61 u_Axi_CDC/arFifo/ram_reg_0_3_12_17/RAMB/CLK High Pulse Width Fast RAMD32/CLK n/a 1.250 15.161 13.911 SLICE_X22Y61 u_Axi_CDC/arFifo/ram_reg_0_3_12_17/RAMB_D1/CLK High Pulse Width Fast RAMD32/CLK n/a 1.250 15.161 13.911 SLICE_X22Y61 u_Axi_CDC/arFifo/ram_reg_0_3_12_17/RAMC/CLK High Pulse Width Fast RAMD32/CLK n/a 1.250 15.161 13.911 SLICE_X22Y61 u_Axi_CDC/arFifo/ram_reg_0_3_12_17/RAMC_D1/CLK High Pulse Width Fast RAMS32/CLK n/a 1.250 15.161 13.911 SLICE_X22Y61 u_Axi_CDC/arFifo/ram_reg_0_3_12_17/RAMD/CLK High Pulse Width Fast RAMS32/CLK n/a 1.250 15.161 13.911 SLICE_X22Y61 u_Axi_CDC/arFifo/ram_reg_0_3_12_17/RAMD_D1/CLK High Pulse Width Fast RAMD32/CLK n/a 1.250 15.161 13.911 SLICE_X22Y64 u_Axi_CDC/arFifo/ram_reg_0_3_18_23/RAMA/CLK High Pulse Width Fast RAMD32/CLK n/a 1.250 15.161 13.911 SLICE_X22Y64 u_Axi_CDC/arFifo/ram_reg_0_3_18_23/RAMA_D1/CLK High Pulse Width Fast RAMD32/CLK n/a 1.250 15.161 13.911 SLICE_X22Y64 u_Axi_CDC/arFifo/ram_reg_0_3_18_23/RAMB/CLK High Pulse Width Fast RAMD32/CLK n/a 1.250 15.161 13.911 SLICE_X22Y64 u_Axi_CDC/arFifo/ram_reg_0_3_18_23/RAMB_D1/CLK High Pulse Width Fast RAMD32/CLK n/a 1.250 15.161 13.911 SLICE_X22Y64 u_Axi_CDC/arFifo/ram_reg_0_3_18_23/RAMC/CLK High Pulse Width Fast RAMD32/CLK n/a 1.250 15.161 13.911 SLICE_X22Y64 u_Axi_CDC/arFifo/ram_reg_0_3_18_23/RAMC_D1/CLK High Pulse Width Fast RAMS32/CLK n/a 1.250 15.161 13.911 SLICE_X22Y64 u_Axi_CDC/arFifo/ram_reg_0_3_18_23/RAMD/CLK High Pulse Width Fast RAMS32/CLK n/a 1.250 15.161 13.911 SLICE_X22Y64 u_Axi_CDC/arFifo/ram_reg_0_3_18_23/RAMD_D1/CLK High Pulse Width Fast RAMD32/CLK n/a 1.250 15.161 13.911 SLICE_X22Y65 u_Axi_CDC/arFifo/ram_reg_0_3_24_29/RAMA/CLK High Pulse Width Fast RAMD32/CLK n/a 1.250 15.161 13.911 SLICE_X22Y65 u_Axi_CDC/arFifo/ram_reg_0_3_24_29/RAMA_D1/CLK High Pulse Width Fast RAMD32/CLK n/a 1.250 15.161 13.911 SLICE_X22Y65 u_Axi_CDC/arFifo/ram_reg_0_3_24_29/RAMB/CLK High Pulse Width Fast RAMD32/CLK n/a 1.250 15.161 13.911 SLICE_X22Y65 u_Axi_CDC/arFifo/ram_reg_0_3_24_29/RAMB_D1/CLK High Pulse Width Fast RAMD32/CLK n/a 1.250 15.161 13.911 SLICE_X22Y65 u_Axi_CDC/arFifo/ram_reg_0_3_24_29/RAMC/CLK High Pulse Width Fast RAMD32/CLK n/a 1.250 15.161 13.911 SLICE_X22Y65 u_Axi_CDC/arFifo/ram_reg_0_3_24_29/RAMC_D1/CLK High Pulse Width Fast RAMS32/CLK n/a 1.250 15.161 13.911 SLICE_X22Y65 u_Axi_CDC/arFifo/ram_reg_0_3_24_29/RAMD/CLK High Pulse Width Fast RAMS32/CLK n/a 1.250 15.161 13.911 SLICE_X22Y65 u_Axi_CDC/arFifo/ram_reg_0_3_24_29/RAMD_D1/CLK High Pulse Width Fast RAMD32/CLK n/a 1.250 15.161 13.911 SLICE_X36Y67 u_Axi_CDC/arFifo/ram_reg_0_3_30_35/RAMA/CLK High Pulse Width Fast RAMD32/CLK n/a 1.250 15.161 13.911 SLICE_X36Y67 u_Axi_CDC/arFifo/ram_reg_0_3_30_35/RAMA_D1/CLK High Pulse Width Fast RAMD32/CLK n/a 1.250 15.161 13.911 SLICE_X36Y67 u_Axi_CDC/arFifo/ram_reg_0_3_30_35/RAMB/CLK High Pulse Width Fast RAMD32/CLK n/a 1.250 15.161 13.911 SLICE_X36Y67 u_Axi_CDC/arFifo/ram_reg_0_3_30_35/RAMB_D1/CLK High Pulse Width Fast RAMD32/CLK n/a 1.250 15.161 13.911 SLICE_X36Y67 u_Axi_CDC/arFifo/ram_reg_0_3_30_35/RAMC/CLK High Pulse Width Fast RAMD32/CLK n/a 1.250 15.161 13.911 SLICE_X36Y67 u_Axi_CDC/arFifo/ram_reg_0_3_30_35/RAMC_D1/CLK High Pulse Width Fast RAMS32/CLK n/a 1.250 15.161 13.911 SLICE_X36Y67 u_Axi_CDC/arFifo/ram_reg_0_3_30_35/RAMD/CLK High Pulse Width Fast RAMS32/CLK n/a 1.250 15.161 13.911 SLICE_X36Y67 u_Axi_CDC/arFifo/ram_reg_0_3_30_35/RAMD_D1/CLK High Pulse Width Fast RAMD32/CLK n/a 1.250 15.161 13.911 SLICE_X22Y66 u_Axi_CDC/arFifo/ram_reg_0_3_42_47/RAMA/CLK High Pulse Width Fast RAMD32/CLK n/a 1.250 15.161 13.911 SLICE_X22Y66 u_Axi_CDC/arFifo/ram_reg_0_3_42_47/RAMA_D1/CLK High Pulse Width Fast RAMD32/CLK n/a 1.250 15.161 13.911 SLICE_X22Y66 u_Axi_CDC/arFifo/ram_reg_0_3_42_47/RAMB/CLK High Pulse Width Fast RAMD32/CLK n/a 1.250 15.161 13.911 SLICE_X22Y66 u_Axi_CDC/arFifo/ram_reg_0_3_42_47/RAMB_D1/CLK High Pulse Width Fast RAMD32/CLK n/a 1.250 15.161 13.911 SLICE_X22Y66 u_Axi_CDC/arFifo/ram_reg_0_3_42_47/RAMC/CLK High Pulse Width Fast RAMD32/CLK n/a 1.250 15.161 13.911 SLICE_X22Y66 u_Axi_CDC/arFifo/ram_reg_0_3_42_47/RAMC_D1/CLK High Pulse Width Fast RAMS32/CLK n/a 1.250 15.161 13.911 SLICE_X22Y66 u_Axi_CDC/arFifo/ram_reg_0_3_42_47/RAMD/CLK High Pulse Width Fast RAMS32/CLK n/a 1.250 15.161 13.911 SLICE_X22Y66 u_Axi_CDC/arFifo/ram_reg_0_3_42_47/RAMD_D1/CLK High Pulse Width Fast RAMD32/CLK n/a 1.250 15.161 13.911 SLICE_X36Y68 u_Axi_CDC/arFifo/ram_reg_0_3_48_53/RAMA/CLK High Pulse Width Fast RAMD32/CLK n/a 1.250 15.161 13.911 SLICE_X36Y68 u_Axi_CDC/arFifo/ram_reg_0_3_48_53/RAMA_D1/CLK --------------------------------------------------------------------------------------------------- From Clock: mlkem_clk_clk_pll To Clock: mlkem_clk_clk_pll Setup : NA Failing Endpoints, Worst Slack NA , Total Violation NA Hold : 0 Failing Endpoints, Worst Slack 0.035ns, Total Violation 0.000ns PW : 0 Failing Endpoints, Worst Slack 18.750ns, Total Violation 0.000ns --------------------------------------------------------------------------------------------------- Min Delay Paths -------------------------------------------------------------------------------------- Slack (MET) : 0.035ns (arrival time - required time) Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_snt/d2_r_reg[9]/C (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_snt/coeff_o_r_reg[9]/D (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) Path Group: mlkem_clk_clk_pll Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (mlkem_clk_clk_pll rise@0.000ns - mlkem_clk_clk_pll rise@0.000ns) Data Path Delay: 0.445ns (logic 0.249ns (55.966%) route 0.196ns (44.034%)) Logic Levels: 1 (LUT3=1) Clock Path Skew: 0.279ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.449ns Source Clock Delay (SCD): -0.683ns Clock Pessimism Removal (CPR): -0.045ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock mlkem_clk_clk_pll rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout3_buf/O net (fo=25775, routed) 0.580 -0.683 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_snt/mlkem_clk SLICE_X60Y150 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_snt/d2_r_reg[9]/C ------------------------------------------------------------------- ------------------- SLICE_X60Y150 FDCE (Prop_fdce_C_Q) 0.148 -0.535 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_snt/d2_r_reg[9]/Q net (fo=1, routed) 0.196 -0.339 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_snt/d2_r[9] SLICE_X56Y149 LUT3 (Prop_lut3_I0_O) 0.101 -0.238 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_snt/coeff_o_r[9]_i_1/O net (fo=1, routed) 0.000 -0.238 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_snt/p_0_in[9] SLICE_X56Y149 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_snt/coeff_o_r_reg[9]/D ------------------------------------------------------------------- ------------------- (clock mlkem_clk_clk_pll rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout3_buf/O net (fo=25775, routed) 0.859 -0.449 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_snt/mlkem_clk SLICE_X56Y149 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_snt/coeff_o_r_reg[9]/C clock pessimism 0.045 -0.404 SLICE_X56Y149 FDCE (Hold_fdce_C_D) 0.131 -0.273 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_snt/coeff_o_r_reg[9] ------------------------------------------------------------------- required time 0.273 arrival time -0.238 ------------------------------------------------------------------- slack 0.035 Slack (MET) : 0.065ns (arrival time - required time) Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/_zz_ram_port1_reg[9]/C (rising edge-triggered cell FDRE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/w_addr_reg[9]/D (rising edge-triggered cell FDRE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) Path Group: mlkem_clk_clk_pll Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (mlkem_clk_clk_pll rise@0.000ns - mlkem_clk_clk_pll rise@0.000ns) Data Path Delay: 0.385ns (logic 0.186ns (48.253%) route 0.199ns (51.747%)) Logic Levels: 1 (LUT4=1) Clock Path Skew: 0.199ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.457ns Source Clock Delay (SCD): -0.616ns Clock Pessimism Removal (CPR): -0.040ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock mlkem_clk_clk_pll rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout3_buf/O net (fo=25775, routed) 0.646 -0.616 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/mlkem_clk SLICE_X69Y93 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/_zz_ram_port1_reg[9]/C ------------------------------------------------------------------- ------------------- SLICE_X69Y93 FDRE (Prop_fdre_C_Q) 0.141 -0.475 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/_zz_ram_port1_reg[9]/Q net (fo=1, routed) 0.199 -0.276 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/w_burst_reg[1]_1[9] SLICE_X70Y100 LUT4 (Prop_lut4_I0_O) 0.045 -0.231 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/w_addr[9]_i_1/O net (fo=1, routed) 0.000 -0.231 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/w_addr[9] SLICE_X70Y100 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/w_addr_reg[9]/D ------------------------------------------------------------------- ------------------- (clock mlkem_clk_clk_pll rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout3_buf/O net (fo=25775, routed) 0.851 -0.457 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/mlkem_clk SLICE_X70Y100 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/w_addr_reg[9]/C clock pessimism 0.040 -0.417 SLICE_X70Y100 FDRE (Hold_fdre_C_D) 0.121 -0.296 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/w_addr_reg[9] ------------------------------------------------------------------- required time 0.296 arrival time -0.231 ------------------------------------------------------------------- slack 0.065 Slack (MET) : 0.075ns (arrival time - required time) Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_widx_reg[0]/C (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_widx_reg[3]/D (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) Path Group: mlkem_clk_clk_pll Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (mlkem_clk_clk_pll rise@0.000ns - mlkem_clk_clk_pll rise@0.000ns) Data Path Delay: 0.459ns (logic 0.187ns (40.764%) route 0.272ns (59.236%)) Logic Levels: 1 (LUT5=1) Clock Path Skew: 0.277ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.448ns Source Clock Delay (SCD): -0.680ns Clock Pessimism Removal (CPR): -0.045ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock mlkem_clk_clk_pll rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout3_buf/O net (fo=25775, routed) 0.583 -0.680 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mlkem_clk SLICE_X45Y150 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_widx_reg[0]/C ------------------------------------------------------------------- ------------------- SLICE_X45Y150 FDCE (Prop_fdce_C_Q) 0.141 -0.539 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_widx_reg[0]/Q net (fo=8, routed) 0.272 -0.267 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_widx_reg[7][0] SLICE_X45Y149 LUT5 (Prop_lut5_I1_O) 0.046 -0.221 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_widx[3]_i_1/O net (fo=1, routed) 0.000 -0.221 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_widx[3] SLICE_X45Y149 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_widx_reg[3]/D ------------------------------------------------------------------- ------------------- (clock mlkem_clk_clk_pll rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout3_buf/O net (fo=25775, routed) 0.860 -0.448 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mlkem_clk SLICE_X45Y149 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_widx_reg[3]/C clock pessimism 0.045 -0.403 SLICE_X45Y149 FDCE (Hold_fdce_C_D) 0.107 -0.296 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_widx_reg[3] ------------------------------------------------------------------- required time 0.296 arrival time -0.221 ------------------------------------------------------------------- slack 0.075 Slack (MET) : 0.089ns (arrival time - required time) Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dec_dc_done_reg/C (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dec_cidx_reg[0]/D (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) Path Group: mlkem_clk_clk_pll Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (mlkem_clk_clk_pll rise@0.000ns - mlkem_clk_clk_pll rise@0.000ns) Data Path Delay: 0.446ns (logic 0.186ns (41.696%) route 0.260ns (58.304%)) Logic Levels: 1 (LUT6=1) Clock Path Skew: 0.266ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.423ns Source Clock Delay (SCD): -0.644ns Clock Pessimism Removal (CPR): -0.045ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock mlkem_clk_clk_pll rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout3_buf/O net (fo=25775, routed) 0.619 -0.644 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mlkem_clk SLICE_X38Y148 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dec_dc_done_reg/C ------------------------------------------------------------------- ------------------- SLICE_X38Y148 FDCE (Prop_fdce_C_Q) 0.141 -0.503 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dec_dc_done_reg/Q net (fo=11, routed) 0.260 -0.243 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/dec_dc_done_reg_0 SLICE_X38Y151 LUT6 (Prop_lut6_I1_O) 0.045 -0.198 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/dec_cidx[0]_i_1/O net (fo=1, routed) 0.000 -0.198 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dec_cidx0_out[0] SLICE_X38Y151 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dec_cidx_reg[0]/D ------------------------------------------------------------------- ------------------- (clock mlkem_clk_clk_pll rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout3_buf/O net (fo=25775, routed) 0.885 -0.423 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mlkem_clk SLICE_X38Y151 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dec_cidx_reg[0]/C clock pessimism 0.045 -0.378 SLICE_X38Y151 FDCE (Hold_fdce_C_D) 0.091 -0.287 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dec_cidx_reg[0] ------------------------------------------------------------------- required time 0.287 arrival time -0.198 ------------------------------------------------------------------- slack 0.089 Slack (MET) : 0.090ns (arrival time - required time) Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_widx_reg[0]/C (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_widx_reg[2]/D (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) Path Group: mlkem_clk_clk_pll Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (mlkem_clk_clk_pll rise@0.000ns - mlkem_clk_clk_pll rise@0.000ns) Data Path Delay: 0.458ns (logic 0.186ns (40.635%) route 0.272ns (59.365%)) Logic Levels: 1 (LUT4=1) Clock Path Skew: 0.277ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.448ns Source Clock Delay (SCD): -0.680ns Clock Pessimism Removal (CPR): -0.045ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock mlkem_clk_clk_pll rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout3_buf/O net (fo=25775, routed) 0.583 -0.680 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mlkem_clk SLICE_X45Y150 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_widx_reg[0]/C ------------------------------------------------------------------- ------------------- SLICE_X45Y150 FDCE (Prop_fdce_C_Q) 0.141 -0.539 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_widx_reg[0]/Q net (fo=8, routed) 0.272 -0.267 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_widx_reg[7][0] SLICE_X45Y149 LUT4 (Prop_lut4_I2_O) 0.045 -0.222 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_widx[2]_i_1/O net (fo=1, routed) 0.000 -0.222 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_widx[2] SLICE_X45Y149 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_widx_reg[2]/D ------------------------------------------------------------------- ------------------- (clock mlkem_clk_clk_pll rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout3_buf/O net (fo=25775, routed) 0.860 -0.448 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mlkem_clk SLICE_X45Y149 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_widx_reg[2]/C clock pessimism 0.045 -0.403 SLICE_X45Y149 FDCE (Hold_fdce_C_D) 0.091 -0.312 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_widx_reg[2] ------------------------------------------------------------------- required time 0.312 arrival time -0.222 ------------------------------------------------------------------- slack 0.090 Slack (MET) : 0.100ns (arrival time - required time) Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_scl/valid_sr_reg_c_3/C (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_scl/valid_sr_reg_c_4/D (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) Path Group: mlkem_clk_clk_pll Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (mlkem_clk_clk_pll rise@0.000ns - mlkem_clk_clk_pll rise@0.000ns) Data Path Delay: 0.380ns (logic 0.128ns (33.677%) route 0.252ns (66.323%)) Logic Levels: 0 Clock Path Skew: 0.264ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.481ns Source Clock Delay (SCD): -0.705ns Clock Pessimism Removal (CPR): -0.040ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock mlkem_clk_clk_pll rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout3_buf/O net (fo=25775, routed) 0.558 -0.705 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_scl/mlkem_clk SLICE_X86Y165 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_scl/valid_sr_reg_c_3/C ------------------------------------------------------------------- ------------------- SLICE_X86Y165 FDCE (Prop_fdce_C_Q) 0.128 -0.577 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_scl/valid_sr_reg_c_3/Q net (fo=27, routed) 0.252 -0.325 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_scl/valid_sr_reg_c_3_0 SLICE_X81Y165 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_scl/valid_sr_reg_c_4/D ------------------------------------------------------------------- ------------------- (clock mlkem_clk_clk_pll rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout3_buf/O net (fo=25775, routed) 0.826 -0.481 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_scl/mlkem_clk SLICE_X81Y165 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_scl/valid_sr_reg_c_4/C clock pessimism 0.040 -0.441 SLICE_X81Y165 FDCE (Hold_fdce_C_D) 0.016 -0.425 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_scl/valid_sr_reg_c_4 ------------------------------------------------------------------- required time 0.425 arrival time -0.325 ------------------------------------------------------------------- slack 0.100 Slack (MET) : 0.101ns (arrival time - required time) Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/s_axi_rid_reg[0]/C (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_30_35/RAMB/I (rising edge-triggered cell RAMD32 clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) Path Group: mlkem_clk_clk_pll Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (mlkem_clk_clk_pll rise@0.000ns - mlkem_clk_clk_pll rise@0.000ns) Data Path Delay: 0.263ns (logic 0.164ns (62.300%) route 0.099ns (37.700%)) Logic Levels: 0 Clock Path Skew: 0.016ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.380ns Source Clock Delay (SCD): -0.608ns Clock Pessimism Removal (CPR): 0.212ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock mlkem_clk_clk_pll rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout3_buf/O net (fo=25775, routed) 0.654 -0.608 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/mlkem_clk SLICE_X48Y94 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/s_axi_rid_reg[0]/C ------------------------------------------------------------------- ------------------- SLICE_X48Y94 FDCE (Prop_fdce_C_Q) 0.164 -0.444 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/s_axi_rid_reg[0]/Q net (fo=1, routed) 0.099 -0.345 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_30_35/DIB0 SLICE_X46Y93 RAMD32 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_30_35/RAMB/I ------------------------------------------------------------------- ------------------- (clock mlkem_clk_clk_pll rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout3_buf/O net (fo=25775, routed) 0.928 -0.380 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_30_35/WCLK SLICE_X46Y93 RAMD32 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_30_35/RAMB/CLK clock pessimism -0.212 -0.592 SLICE_X46Y93 RAMD32 (Hold_ramd32_CLK_I) 0.146 -0.446 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_30_35/RAMB ------------------------------------------------------------------- required time 0.446 arrival time -0.345 ------------------------------------------------------------------- slack 0.101 Slack (MET) : 0.103ns (arrival time - required time) Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/s_axi_rid_reg[2]/C (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_30_35/RAMC/I (rising edge-triggered cell RAMD32 clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) Path Group: mlkem_clk_clk_pll Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (mlkem_clk_clk_pll rise@0.000ns - mlkem_clk_clk_pll rise@0.000ns) Data Path Delay: 0.263ns (logic 0.164ns (62.300%) route 0.099ns (37.700%)) Logic Levels: 0 Clock Path Skew: 0.016ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.380ns Source Clock Delay (SCD): -0.608ns Clock Pessimism Removal (CPR): 0.212ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock mlkem_clk_clk_pll rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout3_buf/O net (fo=25775, routed) 0.654 -0.608 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/mlkem_clk SLICE_X48Y94 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/s_axi_rid_reg[2]/C ------------------------------------------------------------------- ------------------- SLICE_X48Y94 FDCE (Prop_fdce_C_Q) 0.164 -0.444 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/s_axi_rid_reg[2]/Q net (fo=1, routed) 0.099 -0.345 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_30_35/DIC0 SLICE_X46Y93 RAMD32 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_30_35/RAMC/I ------------------------------------------------------------------- ------------------- (clock mlkem_clk_clk_pll rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout3_buf/O net (fo=25775, routed) 0.928 -0.380 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_30_35/WCLK SLICE_X46Y93 RAMD32 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_30_35/RAMC/CLK clock pessimism -0.212 -0.592 SLICE_X46Y93 RAMD32 (Hold_ramd32_CLK_I) 0.144 -0.448 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_30_35/RAMC ------------------------------------------------------------------- required time 0.448 arrival time -0.345 ------------------------------------------------------------------- slack 0.103 Slack (MET) : 0.104ns (arrival time - required time) Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/wb_a_data_r_reg[10]/C (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/cr_reg[118][10]/D (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) Path Group: mlkem_clk_clk_pll Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (mlkem_clk_clk_pll rise@0.000ns - mlkem_clk_clk_pll rise@0.000ns) Data Path Delay: 0.458ns (logic 0.186ns (40.603%) route 0.272ns (59.397%)) Logic Levels: 1 (LUT6=1) Clock Path Skew: 0.263ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.488ns Source Clock Delay (SCD): -0.711ns Clock Pessimism Removal (CPR): -0.040ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock mlkem_clk_clk_pll rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout3_buf/O net (fo=25775, routed) 0.552 -0.711 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/mlkem_clk SLICE_X87Y171 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/wb_a_data_r_reg[10]/C ------------------------------------------------------------------- ------------------- SLICE_X87Y171 FDCE (Prop_fdce_C_Q) 0.141 -0.570 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/wb_a_data_r_reg[10]/Q net (fo=231, routed) 0.272 -0.298 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/wb_a_data_r[10] SLICE_X83Y170 LUT6 (Prop_lut6_I2_O) 0.045 -0.253 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/cr[118][10]_i_1/O net (fo=1, routed) 0.000 -0.253 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/cr[118][10]_i_1_n_0 SLICE_X83Y170 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/cr_reg[118][10]/D ------------------------------------------------------------------- ------------------- (clock mlkem_clk_clk_pll rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout3_buf/O net (fo=25775, routed) 0.820 -0.488 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/mlkem_clk SLICE_X83Y170 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/cr_reg[118][10]/C clock pessimism 0.040 -0.448 SLICE_X83Y170 FDCE (Hold_fdce_C_D) 0.091 -0.357 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/cr_reg[118][10] ------------------------------------------------------------------- required time 0.357 arrival time -0.253 ------------------------------------------------------------------- slack 0.104 Slack (MET) : 0.106ns (arrival time - required time) Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/perm_done_reg_rep__17/C (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/squeeze_buf_reg[845]/D (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) Path Group: mlkem_clk_clk_pll Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (mlkem_clk_clk_pll rise@0.000ns - mlkem_clk_clk_pll rise@0.000ns) Data Path Delay: 0.494ns (logic 0.186ns (37.665%) route 0.308ns (62.335%)) Logic Levels: 1 (LUT4=1) Clock Path Skew: 0.267ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.475ns Source Clock Delay (SCD): -0.702ns Clock Pessimism Removal (CPR): -0.040ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock mlkem_clk_clk_pll rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout3_buf/O net (fo=25775, routed) 0.561 -0.702 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/mlkem_clk SLICE_X79Y158 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/perm_done_reg_rep__17/C ------------------------------------------------------------------- ------------------- SLICE_X79Y158 FDCE (Prop_fdce_C_Q) 0.141 -0.561 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/perm_done_reg_rep__17/Q net (fo=118, routed) 0.308 -0.253 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/squeeze_buf_reg[35] SLICE_X84Y152 LUT4 (Prop_lut4_I2_O) 0.045 -0.208 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/squeeze_buf[845]_i_1/O net (fo=1, routed) 0.000 -0.208 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/squeeze_buf_reg[845]_0 SLICE_X84Y152 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/squeeze_buf_reg[845]/D ------------------------------------------------------------------- ------------------- (clock mlkem_clk_clk_pll rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout3_buf/O net (fo=25775, routed) 0.833 -0.475 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/mlkem_clk SLICE_X84Y152 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/squeeze_buf_reg[845]/C clock pessimism 0.040 -0.435 SLICE_X84Y152 FDCE (Hold_fdce_C_D) 0.121 -0.314 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/squeeze_buf_reg[845] ------------------------------------------------------------------- required time 0.314 arrival time -0.208 ------------------------------------------------------------------- slack 0.106 Slack (MET) : 0.106ns (arrival time - required time) Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_snt/d1_r_reg[6]/C (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_snt/coeff_o_r_reg[6]/D (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) Path Group: mlkem_clk_clk_pll Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (mlkem_clk_clk_pll rise@0.000ns - mlkem_clk_clk_pll rise@0.000ns) Data Path Delay: 0.240ns (logic 0.186ns (77.466%) route 0.054ns (22.534%)) Logic Levels: 1 (LUT3=1) Clock Path Skew: 0.013ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.449ns Source Clock Delay (SCD): -0.675ns Clock Pessimism Removal (CPR): 0.213ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock mlkem_clk_clk_pll rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout3_buf/O net (fo=25775, routed) 0.588 -0.675 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_snt/mlkem_clk SLICE_X57Y149 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_snt/d1_r_reg[6]/C ------------------------------------------------------------------- ------------------- SLICE_X57Y149 FDCE (Prop_fdce_C_Q) 0.141 -0.534 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_snt/d1_r_reg[6]/Q net (fo=1, routed) 0.054 -0.480 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_snt/d1_r[6] SLICE_X56Y149 LUT3 (Prop_lut3_I1_O) 0.045 -0.435 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_snt/coeff_o_r[6]_i_1/O net (fo=1, routed) 0.000 -0.435 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_snt/p_0_in[6] SLICE_X56Y149 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_snt/coeff_o_r_reg[6]/D ------------------------------------------------------------------- ------------------- (clock mlkem_clk_clk_pll rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout3_buf/O net (fo=25775, routed) 0.859 -0.449 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_snt/mlkem_clk SLICE_X56Y149 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_snt/coeff_o_r_reg[6]/C clock pessimism -0.213 -0.662 SLICE_X56Y149 FDCE (Hold_fdce_C_D) 0.121 -0.541 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_snt/coeff_o_r_reg[6] ------------------------------------------------------------------- required time 0.541 arrival time -0.435 ------------------------------------------------------------------- slack 0.106 Slack (MET) : 0.116ns (arrival time - required time) Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/perm_done_reg_rep__15/C (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/squeeze_buf_reg[963]/D (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) Path Group: mlkem_clk_clk_pll Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (mlkem_clk_clk_pll rise@0.000ns - mlkem_clk_clk_pll rise@0.000ns) Data Path Delay: 0.515ns (logic 0.186ns (36.124%) route 0.329ns (63.876%)) Logic Levels: 1 (LUT4=1) Clock Path Skew: 0.278ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.469ns Source Clock Delay (SCD): -0.702ns Clock Pessimism Removal (CPR): -0.045ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock mlkem_clk_clk_pll rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout3_buf/O net (fo=25775, routed) 0.561 -0.702 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/mlkem_clk SLICE_X79Y158 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/perm_done_reg_rep__15/C ------------------------------------------------------------------- ------------------- SLICE_X79Y158 FDCE (Prop_fdce_C_Q) 0.141 -0.561 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/perm_done_reg_rep__15/Q net (fo=118, routed) 0.329 -0.232 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/squeeze_buf_reg[707] SLICE_X80Y146 LUT4 (Prop_lut4_I2_O) 0.045 -0.187 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/squeeze_buf[963]_i_1/O net (fo=1, routed) 0.000 -0.187 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/squeeze_buf_reg[963]_0 SLICE_X80Y146 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/squeeze_buf_reg[963]/D ------------------------------------------------------------------- ------------------- (clock mlkem_clk_clk_pll rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout3_buf/O net (fo=25775, routed) 0.839 -0.469 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/mlkem_clk SLICE_X80Y146 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/squeeze_buf_reg[963]/C clock pessimism 0.045 -0.424 SLICE_X80Y146 FDCE (Hold_fdce_C_D) 0.121 -0.303 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/squeeze_buf_reg[963] ------------------------------------------------------------------- required time 0.303 arrival time -0.187 ------------------------------------------------------------------- slack 0.116 Slack (MET) : 0.119ns (arrival time - required time) Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/rdb_ack_tg_reg/C (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/rdb_ack_sync_reg[0]/D (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) Path Group: mlkem_clk_clk_pll Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (mlkem_clk_clk_pll rise@0.000ns - mlkem_clk_clk_pll rise@0.000ns) Data Path Delay: 0.522ns (logic 0.164ns (31.430%) route 0.358ns (68.570%)) Logic Levels: 0 Clock Path Skew: 0.333ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.383ns Source Clock Delay (SCD): -0.676ns Clock Pessimism Removal (CPR): -0.040ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock mlkem_clk_clk_pll rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout3_buf/O net (fo=25775, routed) 0.587 -0.676 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/mlkem_clk SLICE_X56Y105 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/rdb_ack_tg_reg/C ------------------------------------------------------------------- ------------------- SLICE_X56Y105 FDCE (Prop_fdce_C_Q) 0.164 -0.512 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/rdb_ack_tg_reg/Q net (fo=2, routed) 0.358 -0.154 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/rdb_ack_tg_reg_n_0 SLICE_X63Y99 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/rdb_ack_sync_reg[0]/D ------------------------------------------------------------------- ------------------- (clock mlkem_clk_clk_pll rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout3_buf/O net (fo=25775, routed) 0.925 -0.383 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/mlkem_clk SLICE_X63Y99 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/rdb_ack_sync_reg[0]/C clock pessimism 0.040 -0.343 SLICE_X63Y99 FDCE (Hold_fdce_C_D) 0.070 -0.273 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/rdb_ack_sync_reg[0] ------------------------------------------------------------------- required time 0.273 arrival time -0.154 ------------------------------------------------------------------- slack 0.119 Slack (MET) : 0.119ns (arrival time - required time) Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/p_s2_reg[1]/C (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/p_s3_reg[1]/D (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) Path Group: mlkem_clk_clk_pll Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (mlkem_clk_clk_pll rise@0.000ns - mlkem_clk_clk_pll rise@0.000ns) Data Path Delay: 0.197ns (logic 0.141ns (71.611%) route 0.056ns (28.389%)) Logic Levels: 0 Clock Path Skew: 0.000ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.465ns Source Clock Delay (SCD): -0.691ns Clock Pessimism Removal (CPR): 0.226ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock mlkem_clk_clk_pll rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout3_buf/O net (fo=25775, routed) 0.572 -0.691 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/mlkem_clk SLICE_X67Y161 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/p_s2_reg[1]/C ------------------------------------------------------------------- ------------------- SLICE_X67Y161 FDCE (Prop_fdce_C_Q) 0.141 -0.550 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/p_s2_reg[1]/Q net (fo=1, routed) 0.056 -0.494 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/p_s2[1] SLICE_X67Y161 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/p_s3_reg[1]/D ------------------------------------------------------------------- ------------------- (clock mlkem_clk_clk_pll rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout3_buf/O net (fo=25775, routed) 0.843 -0.465 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/mlkem_clk SLICE_X67Y161 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/p_s3_reg[1]/C clock pessimism -0.226 -0.691 SLICE_X67Y161 FDCE (Hold_fdce_C_D) 0.078 -0.613 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/p_s3_reg[1] ------------------------------------------------------------------- required time 0.613 arrival time -0.494 ------------------------------------------------------------------- slack 0.119 Slack (MET) : 0.119ns (arrival time - required time) Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/popToPushGray_buffercc/buffers_0_reg[3]/C (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/popToPushGray_buffercc/buffers_1_reg[3]/D (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) Path Group: mlkem_clk_clk_pll Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (mlkem_clk_clk_pll rise@0.000ns - mlkem_clk_clk_pll rise@0.000ns) Data Path Delay: 0.197ns (logic 0.141ns (71.611%) route 0.056ns (28.389%)) Logic Levels: 0 Clock Path Skew: 0.000ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.387ns Source Clock Delay (SCD): -0.616ns Clock Pessimism Removal (CPR): 0.229ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock mlkem_clk_clk_pll rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout3_buf/O net (fo=25775, routed) 0.646 -0.616 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/popToPushGray_buffercc/mlkem_clk SLICE_X67Y95 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/popToPushGray_buffercc/buffers_0_reg[3]/C ------------------------------------------------------------------- ------------------- SLICE_X67Y95 FDCE (Prop_fdce_C_Q) 0.141 -0.475 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/popToPushGray_buffercc/buffers_0_reg[3]/Q net (fo=1, routed) 0.056 -0.419 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/popToPushGray_buffercc/buffers_0[3] SLICE_X67Y95 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/popToPushGray_buffercc/buffers_1_reg[3]/D ------------------------------------------------------------------- ------------------- (clock mlkem_clk_clk_pll rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout3_buf/O net (fo=25775, routed) 0.921 -0.387 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/popToPushGray_buffercc/mlkem_clk SLICE_X67Y95 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/popToPushGray_buffercc/buffers_1_reg[3]/C clock pessimism -0.229 -0.616 SLICE_X67Y95 FDCE (Hold_fdce_C_D) 0.078 -0.538 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/popToPushGray_buffercc/buffers_1_reg[3] ------------------------------------------------------------------- required time 0.538 arrival time -0.419 ------------------------------------------------------------------- slack 0.119 Slack (MET) : 0.121ns (arrival time - required time) Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/p_s2_reg[16]/C (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/p_s3_reg[16]/D (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) Path Group: mlkem_clk_clk_pll Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (mlkem_clk_clk_pll rise@0.000ns - mlkem_clk_clk_pll rise@0.000ns) Data Path Delay: 0.197ns (logic 0.141ns (71.611%) route 0.056ns (28.389%)) Logic Levels: 0 Clock Path Skew: 0.000ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.465ns Source Clock Delay (SCD): -0.691ns Clock Pessimism Removal (CPR): 0.226ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock mlkem_clk_clk_pll rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout3_buf/O net (fo=25775, routed) 0.572 -0.691 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/mlkem_clk SLICE_X67Y161 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/p_s2_reg[16]/C ------------------------------------------------------------------- ------------------- SLICE_X67Y161 FDCE (Prop_fdce_C_Q) 0.141 -0.550 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/p_s2_reg[16]/Q net (fo=1, routed) 0.056 -0.494 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/p_s2[16] SLICE_X67Y161 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/p_s3_reg[16]/D ------------------------------------------------------------------- ------------------- (clock mlkem_clk_clk_pll rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout3_buf/O net (fo=25775, routed) 0.843 -0.465 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/mlkem_clk SLICE_X67Y161 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/p_s3_reg[16]/C clock pessimism -0.226 -0.691 SLICE_X67Y161 FDCE (Hold_fdce_C_D) 0.076 -0.615 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/p_s3_reg[16] ------------------------------------------------------------------- required time 0.615 arrival time -0.494 ------------------------------------------------------------------- slack 0.121 Slack (MET) : 0.121ns (arrival time - required time) Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/pushToPopGray_buffercc/buffers_0_reg[2]/C (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/pushToPopGray_buffercc/buffers_1_reg[2]/D (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) Path Group: mlkem_clk_clk_pll Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (mlkem_clk_clk_pll rise@0.000ns - mlkem_clk_clk_pll rise@0.000ns) Data Path Delay: 0.197ns (logic 0.141ns (71.611%) route 0.056ns (28.389%)) Logic Levels: 0 Clock Path Skew: 0.000ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.388ns Source Clock Delay (SCD): -0.617ns Clock Pessimism Removal (CPR): 0.229ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock mlkem_clk_clk_pll rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout3_buf/O net (fo=25775, routed) 0.645 -0.617 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/pushToPopGray_buffercc/mlkem_clk SLICE_X69Y91 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/pushToPopGray_buffercc/buffers_0_reg[2]/C ------------------------------------------------------------------- ------------------- SLICE_X69Y91 FDCE (Prop_fdce_C_Q) 0.141 -0.476 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/pushToPopGray_buffercc/buffers_0_reg[2]/Q net (fo=1, routed) 0.056 -0.420 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/pushToPopGray_buffercc/buffers_0[2] SLICE_X69Y91 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/pushToPopGray_buffercc/buffers_1_reg[2]/D ------------------------------------------------------------------- ------------------- (clock mlkem_clk_clk_pll rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout3_buf/O net (fo=25775, routed) 0.920 -0.388 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/pushToPopGray_buffercc/mlkem_clk SLICE_X69Y91 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/pushToPopGray_buffercc/buffers_1_reg[2]/C clock pessimism -0.229 -0.617 SLICE_X69Y91 FDCE (Hold_fdce_C_D) 0.076 -0.541 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/pushToPopGray_buffercc/buffers_1_reg[2] ------------------------------------------------------------------- required time 0.541 arrival time -0.420 ------------------------------------------------------------------- slack 0.121 Slack (MET) : 0.121ns (arrival time - required time) Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/pushToPopGray_buffercc/buffers_0_reg[2]/C (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/pushToPopGray_buffercc/buffers_1_reg[2]/D (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) Path Group: mlkem_clk_clk_pll Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (mlkem_clk_clk_pll rise@0.000ns - mlkem_clk_clk_pll rise@0.000ns) Data Path Delay: 0.197ns (logic 0.141ns (71.611%) route 0.056ns (28.389%)) Logic Levels: 0 Clock Path Skew: 0.000ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.388ns Source Clock Delay (SCD): -0.617ns Clock Pessimism Removal (CPR): 0.229ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock mlkem_clk_clk_pll rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout3_buf/O net (fo=25775, routed) 0.645 -0.617 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/pushToPopGray_buffercc/mlkem_clk SLICE_X73Y93 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/pushToPopGray_buffercc/buffers_0_reg[2]/C ------------------------------------------------------------------- ------------------- SLICE_X73Y93 FDCE (Prop_fdce_C_Q) 0.141 -0.476 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/pushToPopGray_buffercc/buffers_0_reg[2]/Q net (fo=1, routed) 0.056 -0.420 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/pushToPopGray_buffercc/buffers_0[2] SLICE_X73Y93 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/pushToPopGray_buffercc/buffers_1_reg[2]/D ------------------------------------------------------------------- ------------------- (clock mlkem_clk_clk_pll rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout3_buf/O net (fo=25775, routed) 0.920 -0.388 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/pushToPopGray_buffercc/mlkem_clk SLICE_X73Y93 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/pushToPopGray_buffercc/buffers_1_reg[2]/C clock pessimism -0.229 -0.617 SLICE_X73Y93 FDCE (Hold_fdce_C_D) 0.076 -0.541 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/pushToPopGray_buffercc/buffers_1_reg[2] ------------------------------------------------------------------- required time 0.541 arrival time -0.420 ------------------------------------------------------------------- slack 0.121 Slack (MET) : 0.121ns (arrival time - required time) Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/popToPushGray_buffercc/buffers_0_reg[2]/C (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/popToPushGray_buffercc/buffers_1_reg[2]/D (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) Path Group: mlkem_clk_clk_pll Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (mlkem_clk_clk_pll rise@0.000ns - mlkem_clk_clk_pll rise@0.000ns) Data Path Delay: 0.197ns (logic 0.141ns (71.611%) route 0.056ns (28.389%)) Logic Levels: 0 Clock Path Skew: 0.000ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.387ns Source Clock Delay (SCD): -0.616ns Clock Pessimism Removal (CPR): 0.229ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock mlkem_clk_clk_pll rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout3_buf/O net (fo=25775, routed) 0.646 -0.616 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/popToPushGray_buffercc/mlkem_clk SLICE_X67Y96 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/popToPushGray_buffercc/buffers_0_reg[2]/C ------------------------------------------------------------------- ------------------- SLICE_X67Y96 FDCE (Prop_fdce_C_Q) 0.141 -0.475 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/popToPushGray_buffercc/buffers_0_reg[2]/Q net (fo=1, routed) 0.056 -0.419 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/popToPushGray_buffercc/buffers_0[2] SLICE_X67Y96 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/popToPushGray_buffercc/buffers_1_reg[2]/D ------------------------------------------------------------------- ------------------- (clock mlkem_clk_clk_pll rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout3_buf/O net (fo=25775, routed) 0.921 -0.387 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/popToPushGray_buffercc/mlkem_clk SLICE_X67Y96 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/popToPushGray_buffercc/buffers_1_reg[2]/C clock pessimism -0.229 -0.616 SLICE_X67Y96 FDCE (Hold_fdce_C_D) 0.076 -0.540 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/popToPushGray_buffercc/buffers_1_reg[2] ------------------------------------------------------------------- required time 0.540 arrival time -0.419 ------------------------------------------------------------------- slack 0.121 Slack (MET) : 0.121ns (arrival time - required time) Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/popToPushGray_buffercc/buffers_0_reg[2]/C (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/popToPushGray_buffercc/buffers_1_reg[2]/D (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) Path Group: mlkem_clk_clk_pll Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (mlkem_clk_clk_pll rise@0.000ns - mlkem_clk_clk_pll rise@0.000ns) Data Path Delay: 0.197ns (logic 0.141ns (71.611%) route 0.056ns (28.389%)) Logic Levels: 0 Clock Path Skew: 0.000ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.387ns Source Clock Delay (SCD): -0.616ns Clock Pessimism Removal (CPR): 0.229ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock mlkem_clk_clk_pll rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout3_buf/O net (fo=25775, routed) 0.646 -0.616 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/popToPushGray_buffercc/mlkem_clk SLICE_X67Y95 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/popToPushGray_buffercc/buffers_0_reg[2]/C ------------------------------------------------------------------- ------------------- SLICE_X67Y95 FDCE (Prop_fdce_C_Q) 0.141 -0.475 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/popToPushGray_buffercc/buffers_0_reg[2]/Q net (fo=1, routed) 0.056 -0.419 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/popToPushGray_buffercc/buffers_0[2] SLICE_X67Y95 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/popToPushGray_buffercc/buffers_1_reg[2]/D ------------------------------------------------------------------- ------------------- (clock mlkem_clk_clk_pll rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout3_buf/O net (fo=25775, routed) 0.921 -0.387 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/popToPushGray_buffercc/mlkem_clk SLICE_X67Y95 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/popToPushGray_buffercc/buffers_1_reg[2]/C clock pessimism -0.229 -0.616 SLICE_X67Y95 FDCE (Hold_fdce_C_D) 0.076 -0.540 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/popToPushGray_buffercc/buffers_1_reg[2] ------------------------------------------------------------------- required time 0.540 arrival time -0.419 ------------------------------------------------------------------- slack 0.121 Slack (MET) : 0.121ns (arrival time - required time) Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/pushToPopGray_buffercc/buffers_0_reg[2]/C (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/pushToPopGray_buffercc/buffers_1_reg[2]/D (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) Path Group: mlkem_clk_clk_pll Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (mlkem_clk_clk_pll rise@0.000ns - mlkem_clk_clk_pll rise@0.000ns) Data Path Delay: 0.197ns (logic 0.141ns (71.611%) route 0.056ns (28.389%)) Logic Levels: 0 Clock Path Skew: 0.000ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.388ns Source Clock Delay (SCD): -0.617ns Clock Pessimism Removal (CPR): 0.229ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock mlkem_clk_clk_pll rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout3_buf/O net (fo=25775, routed) 0.645 -0.617 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/pushToPopGray_buffercc/mlkem_clk SLICE_X71Y95 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/pushToPopGray_buffercc/buffers_0_reg[2]/C ------------------------------------------------------------------- ------------------- SLICE_X71Y95 FDCE (Prop_fdce_C_Q) 0.141 -0.476 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/pushToPopGray_buffercc/buffers_0_reg[2]/Q net (fo=1, routed) 0.056 -0.420 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/pushToPopGray_buffercc/buffers_0[2] SLICE_X71Y95 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/pushToPopGray_buffercc/buffers_1_reg[2]/D ------------------------------------------------------------------- ------------------- (clock mlkem_clk_clk_pll rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout3_buf/O net (fo=25775, routed) 0.920 -0.388 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/pushToPopGray_buffercc/mlkem_clk SLICE_X71Y95 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/pushToPopGray_buffercc/buffers_1_reg[2]/C clock pessimism -0.229 -0.617 SLICE_X71Y95 FDCE (Hold_fdce_C_D) 0.076 -0.541 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/pushToPopGray_buffercc/buffers_1_reg[2] ------------------------------------------------------------------- required time 0.541 arrival time -0.420 ------------------------------------------------------------------- slack 0.121 Slack (MET) : 0.121ns (arrival time - required time) Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/w_id_reg[0]/C (rising edge-triggered cell FDRE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/ram_reg_0_3_0_5/RAMA/I (rising edge-triggered cell RAMD32 clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) Path Group: mlkem_clk_clk_pll Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (mlkem_clk_clk_pll rise@0.000ns - mlkem_clk_clk_pll rise@0.000ns) Data Path Delay: 0.284ns (logic 0.141ns (49.624%) route 0.143ns (50.376%)) Logic Levels: 0 Clock Path Skew: 0.016ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.385ns Source Clock Delay (SCD): -0.614ns Clock Pessimism Removal (CPR): 0.213ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock mlkem_clk_clk_pll rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout3_buf/O net (fo=25775, routed) 0.648 -0.614 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/mlkem_clk SLICE_X65Y96 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/w_id_reg[0]/C ------------------------------------------------------------------- ------------------- SLICE_X65Y96 FDRE (Prop_fdre_C_Q) 0.141 -0.473 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/w_id_reg[0]/Q net (fo=1, routed) 0.143 -0.330 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/ram_reg_0_3_0_5/DIA0 SLICE_X64Y95 RAMD32 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/ram_reg_0_3_0_5/RAMA/I ------------------------------------------------------------------- ------------------- (clock mlkem_clk_clk_pll rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout3_buf/O net (fo=25775, routed) 0.923 -0.385 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/ram_reg_0_3_0_5/WCLK SLICE_X64Y95 RAMD32 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/ram_reg_0_3_0_5/RAMA/CLK clock pessimism -0.213 -0.598 SLICE_X64Y95 RAMD32 (Hold_ramd32_CLK_I) 0.147 -0.451 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/ram_reg_0_3_0_5/RAMA ------------------------------------------------------------------- required time 0.451 arrival time -0.330 ------------------------------------------------------------------- slack 0.121 Slack (MET) : 0.122ns (arrival time - required time) Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/pushToPopGray_buffercc/buffers_0_reg[0]/C (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/pushToPopGray_buffercc/buffers_1_reg[0]/D (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) Path Group: mlkem_clk_clk_pll Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (mlkem_clk_clk_pll rise@0.000ns - mlkem_clk_clk_pll rise@0.000ns) Data Path Delay: 0.197ns (logic 0.141ns (71.611%) route 0.056ns (28.389%)) Logic Levels: 0 Clock Path Skew: 0.000ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.388ns Source Clock Delay (SCD): -0.617ns Clock Pessimism Removal (CPR): 0.229ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock mlkem_clk_clk_pll rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout3_buf/O net (fo=25775, routed) 0.645 -0.617 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/pushToPopGray_buffercc/mlkem_clk SLICE_X69Y91 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/pushToPopGray_buffercc/buffers_0_reg[0]/C ------------------------------------------------------------------- ------------------- SLICE_X69Y91 FDCE (Prop_fdce_C_Q) 0.141 -0.476 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/pushToPopGray_buffercc/buffers_0_reg[0]/Q net (fo=1, routed) 0.056 -0.420 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/pushToPopGray_buffercc/buffers_0[0] SLICE_X69Y91 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/pushToPopGray_buffercc/buffers_1_reg[0]/D ------------------------------------------------------------------- ------------------- (clock mlkem_clk_clk_pll rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout3_buf/O net (fo=25775, routed) 0.920 -0.388 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/pushToPopGray_buffercc/mlkem_clk SLICE_X69Y91 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/pushToPopGray_buffercc/buffers_1_reg[0]/C clock pessimism -0.229 -0.617 SLICE_X69Y91 FDCE (Hold_fdce_C_D) 0.075 -0.542 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/pushToPopGray_buffercc/buffers_1_reg[0] ------------------------------------------------------------------- required time 0.542 arrival time -0.420 ------------------------------------------------------------------- slack 0.122 Slack (MET) : 0.122ns (arrival time - required time) Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/pushToPopGray_buffercc/buffers_0_reg[0]/C (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/pushToPopGray_buffercc/buffers_1_reg[0]/D (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) Path Group: mlkem_clk_clk_pll Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (mlkem_clk_clk_pll rise@0.000ns - mlkem_clk_clk_pll rise@0.000ns) Data Path Delay: 0.197ns (logic 0.141ns (71.611%) route 0.056ns (28.389%)) Logic Levels: 0 Clock Path Skew: 0.000ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.388ns Source Clock Delay (SCD): -0.617ns Clock Pessimism Removal (CPR): 0.229ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock mlkem_clk_clk_pll rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout3_buf/O net (fo=25775, routed) 0.645 -0.617 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/pushToPopGray_buffercc/mlkem_clk SLICE_X73Y93 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/pushToPopGray_buffercc/buffers_0_reg[0]/C ------------------------------------------------------------------- ------------------- SLICE_X73Y93 FDCE (Prop_fdce_C_Q) 0.141 -0.476 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/pushToPopGray_buffercc/buffers_0_reg[0]/Q net (fo=1, routed) 0.056 -0.420 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/pushToPopGray_buffercc/buffers_0[0] SLICE_X73Y93 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/pushToPopGray_buffercc/buffers_1_reg[0]/D ------------------------------------------------------------------- ------------------- (clock mlkem_clk_clk_pll rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout3_buf/O net (fo=25775, routed) 0.920 -0.388 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/pushToPopGray_buffercc/mlkem_clk SLICE_X73Y93 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/pushToPopGray_buffercc/buffers_1_reg[0]/C clock pessimism -0.229 -0.617 SLICE_X73Y93 FDCE (Hold_fdce_C_D) 0.075 -0.542 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/pushToPopGray_buffercc/buffers_1_reg[0] ------------------------------------------------------------------- required time 0.542 arrival time -0.420 ------------------------------------------------------------------- slack 0.122 Slack (MET) : 0.122ns (arrival time - required time) Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/popToPushGray_buffercc/buffers_0_reg[0]/C (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/popToPushGray_buffercc/buffers_1_reg[0]/D (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) Path Group: mlkem_clk_clk_pll Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (mlkem_clk_clk_pll rise@0.000ns - mlkem_clk_clk_pll rise@0.000ns) Data Path Delay: 0.197ns (logic 0.141ns (71.611%) route 0.056ns (28.389%)) Logic Levels: 0 Clock Path Skew: 0.000ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.387ns Source Clock Delay (SCD): -0.616ns Clock Pessimism Removal (CPR): 0.229ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock mlkem_clk_clk_pll rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout3_buf/O net (fo=25775, routed) 0.646 -0.616 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/popToPushGray_buffercc/mlkem_clk SLICE_X67Y96 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/popToPushGray_buffercc/buffers_0_reg[0]/C ------------------------------------------------------------------- ------------------- SLICE_X67Y96 FDCE (Prop_fdce_C_Q) 0.141 -0.475 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/popToPushGray_buffercc/buffers_0_reg[0]/Q net (fo=1, routed) 0.056 -0.419 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/popToPushGray_buffercc/buffers_0[0] SLICE_X67Y96 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/popToPushGray_buffercc/buffers_1_reg[0]/D ------------------------------------------------------------------- ------------------- (clock mlkem_clk_clk_pll rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout3_buf/O net (fo=25775, routed) 0.921 -0.387 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/popToPushGray_buffercc/mlkem_clk SLICE_X67Y96 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/popToPushGray_buffercc/buffers_1_reg[0]/C clock pessimism -0.229 -0.616 SLICE_X67Y96 FDCE (Hold_fdce_C_D) 0.075 -0.541 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/popToPushGray_buffercc/buffers_1_reg[0] ------------------------------------------------------------------- required time 0.541 arrival time -0.419 ------------------------------------------------------------------- slack 0.122 Slack (MET) : 0.122ns (arrival time - required time) Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/popToPushGray_buffercc/buffers_0_reg[0]/C (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/popToPushGray_buffercc/buffers_1_reg[0]/D (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) Path Group: mlkem_clk_clk_pll Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (mlkem_clk_clk_pll rise@0.000ns - mlkem_clk_clk_pll rise@0.000ns) Data Path Delay: 0.197ns (logic 0.141ns (71.611%) route 0.056ns (28.389%)) Logic Levels: 0 Clock Path Skew: 0.000ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.387ns Source Clock Delay (SCD): -0.616ns Clock Pessimism Removal (CPR): 0.229ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock mlkem_clk_clk_pll rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout3_buf/O net (fo=25775, routed) 0.646 -0.616 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/popToPushGray_buffercc/mlkem_clk SLICE_X67Y95 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/popToPushGray_buffercc/buffers_0_reg[0]/C ------------------------------------------------------------------- ------------------- SLICE_X67Y95 FDCE (Prop_fdce_C_Q) 0.141 -0.475 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/popToPushGray_buffercc/buffers_0_reg[0]/Q net (fo=1, routed) 0.056 -0.419 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/popToPushGray_buffercc/buffers_0[0] SLICE_X67Y95 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/popToPushGray_buffercc/buffers_1_reg[0]/D ------------------------------------------------------------------- ------------------- (clock mlkem_clk_clk_pll rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout3_buf/O net (fo=25775, routed) 0.921 -0.387 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/popToPushGray_buffercc/mlkem_clk SLICE_X67Y95 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/popToPushGray_buffercc/buffers_1_reg[0]/C clock pessimism -0.229 -0.616 SLICE_X67Y95 FDCE (Hold_fdce_C_D) 0.075 -0.541 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/popToPushGray_buffercc/buffers_1_reg[0] ------------------------------------------------------------------- required time 0.541 arrival time -0.419 ------------------------------------------------------------------- slack 0.122 Slack (MET) : 0.122ns (arrival time - required time) Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/pushToPopGray_buffercc/buffers_0_reg[0]/C (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/pushToPopGray_buffercc/buffers_1_reg[0]/D (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) Path Group: mlkem_clk_clk_pll Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (mlkem_clk_clk_pll rise@0.000ns - mlkem_clk_clk_pll rise@0.000ns) Data Path Delay: 0.197ns (logic 0.141ns (71.611%) route 0.056ns (28.389%)) Logic Levels: 0 Clock Path Skew: 0.000ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.388ns Source Clock Delay (SCD): -0.617ns Clock Pessimism Removal (CPR): 0.229ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock mlkem_clk_clk_pll rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout3_buf/O net (fo=25775, routed) 0.645 -0.617 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/pushToPopGray_buffercc/mlkem_clk SLICE_X71Y95 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/pushToPopGray_buffercc/buffers_0_reg[0]/C ------------------------------------------------------------------- ------------------- SLICE_X71Y95 FDCE (Prop_fdce_C_Q) 0.141 -0.476 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/pushToPopGray_buffercc/buffers_0_reg[0]/Q net (fo=1, routed) 0.056 -0.420 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/pushToPopGray_buffercc/buffers_0[0] SLICE_X71Y95 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/pushToPopGray_buffercc/buffers_1_reg[0]/D ------------------------------------------------------------------- ------------------- (clock mlkem_clk_clk_pll rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout3_buf/O net (fo=25775, routed) 0.920 -0.388 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/pushToPopGray_buffercc/mlkem_clk SLICE_X71Y95 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/pushToPopGray_buffercc/buffers_1_reg[0]/C clock pessimism -0.229 -0.617 SLICE_X71Y95 FDCE (Hold_fdce_C_D) 0.075 -0.542 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/pushToPopGray_buffercc/buffers_1_reg[0] ------------------------------------------------------------------- required time 0.542 arrival time -0.420 ------------------------------------------------------------------- slack 0.122 Slack (MET) : 0.123ns (arrival time - required time) Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/s_axi_rid_reg[1]/C (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_30_35/RAMB_D1/I (rising edge-triggered cell RAMD32 clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) Path Group: mlkem_clk_clk_pll Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (mlkem_clk_clk_pll rise@0.000ns - mlkem_clk_clk_pll rise@0.000ns) Data Path Delay: 0.263ns (logic 0.164ns (62.300%) route 0.099ns (37.700%)) Logic Levels: 0 Clock Path Skew: 0.016ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.380ns Source Clock Delay (SCD): -0.608ns Clock Pessimism Removal (CPR): 0.212ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock mlkem_clk_clk_pll rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout3_buf/O net (fo=25775, routed) 0.654 -0.608 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/mlkem_clk SLICE_X48Y94 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/s_axi_rid_reg[1]/C ------------------------------------------------------------------- ------------------- SLICE_X48Y94 FDCE (Prop_fdce_C_Q) 0.164 -0.444 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/s_axi_rid_reg[1]/Q net (fo=1, routed) 0.099 -0.345 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_30_35/DIB1 SLICE_X46Y93 RAMD32 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_30_35/RAMB_D1/I ------------------------------------------------------------------- ------------------- (clock mlkem_clk_clk_pll rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout3_buf/O net (fo=25775, routed) 0.928 -0.380 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_30_35/WCLK SLICE_X46Y93 RAMD32 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_30_35/RAMB_D1/CLK clock pessimism -0.212 -0.592 SLICE_X46Y93 RAMD32 (Hold_ramd32_CLK_I) 0.124 -0.468 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_30_35/RAMB_D1 ------------------------------------------------------------------- required time 0.468 arrival time -0.345 ------------------------------------------------------------------- slack 0.123 Slack (MET) : 0.125ns (arrival time - required time) Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/perm_done_reg_rep__16/C (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/squeeze_buf_reg[833]/D (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) Path Group: mlkem_clk_clk_pll Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (mlkem_clk_clk_pll rise@0.000ns - mlkem_clk_clk_pll rise@0.000ns) Data Path Delay: 0.483ns (logic 0.186ns (38.497%) route 0.297ns (61.503%)) Logic Levels: 1 (LUT4=1) Clock Path Skew: 0.266ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.476ns Source Clock Delay (SCD): -0.702ns Clock Pessimism Removal (CPR): -0.040ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock mlkem_clk_clk_pll rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout3_buf/O net (fo=25775, routed) 0.561 -0.702 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/mlkem_clk SLICE_X79Y158 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/perm_done_reg_rep__16/C ------------------------------------------------------------------- ------------------- SLICE_X79Y158 FDCE (Prop_fdce_C_Q) 0.141 -0.561 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/perm_done_reg_rep__16/Q net (fo=118, routed) 0.297 -0.264 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/squeeze_buf_reg[304] SLICE_X85Y156 LUT4 (Prop_lut4_I2_O) 0.045 -0.219 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/squeeze_buf[833]_i_1/O net (fo=1, routed) 0.000 -0.219 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/squeeze_buf_reg[833]_0 SLICE_X85Y156 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/squeeze_buf_reg[833]/D ------------------------------------------------------------------- ------------------- (clock mlkem_clk_clk_pll rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout3_buf/O net (fo=25775, routed) 0.831 -0.476 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/mlkem_clk SLICE_X85Y156 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/squeeze_buf_reg[833]/C clock pessimism 0.040 -0.436 SLICE_X85Y156 FDCE (Hold_fdce_C_D) 0.092 -0.344 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/squeeze_buf_reg[833] ------------------------------------------------------------------- required time 0.344 arrival time -0.219 ------------------------------------------------------------------- slack 0.125 Slack (MET) : 0.126ns (arrival time - required time) Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/pushToPopGray_buffercc/buffers_0_reg[1]/C (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/pushToPopGray_buffercc/buffers_1_reg[1]/D (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) Path Group: mlkem_clk_clk_pll Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (mlkem_clk_clk_pll rise@0.000ns - mlkem_clk_clk_pll rise@0.000ns) Data Path Delay: 0.197ns (logic 0.141ns (71.611%) route 0.056ns (28.389%)) Logic Levels: 0 Clock Path Skew: 0.000ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.388ns Source Clock Delay (SCD): -0.617ns Clock Pessimism Removal (CPR): 0.229ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock mlkem_clk_clk_pll rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout3_buf/O net (fo=25775, routed) 0.645 -0.617 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/pushToPopGray_buffercc/mlkem_clk SLICE_X69Y91 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/pushToPopGray_buffercc/buffers_0_reg[1]/C ------------------------------------------------------------------- ------------------- SLICE_X69Y91 FDCE (Prop_fdce_C_Q) 0.141 -0.476 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/pushToPopGray_buffercc/buffers_0_reg[1]/Q net (fo=1, routed) 0.056 -0.420 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/pushToPopGray_buffercc/buffers_0[1] SLICE_X69Y91 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/pushToPopGray_buffercc/buffers_1_reg[1]/D ------------------------------------------------------------------- ------------------- (clock mlkem_clk_clk_pll rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout3_buf/O net (fo=25775, routed) 0.920 -0.388 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/pushToPopGray_buffercc/mlkem_clk SLICE_X69Y91 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/pushToPopGray_buffercc/buffers_1_reg[1]/C clock pessimism -0.229 -0.617 SLICE_X69Y91 FDCE (Hold_fdce_C_D) 0.071 -0.546 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/pushToPopGray_buffercc/buffers_1_reg[1] ------------------------------------------------------------------- required time 0.546 arrival time -0.420 ------------------------------------------------------------------- slack 0.126 Slack (MET) : 0.126ns (arrival time - required time) Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/pushToPopGray_buffercc/buffers_0_reg[1]/C (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/pushToPopGray_buffercc/buffers_1_reg[1]/D (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) Path Group: mlkem_clk_clk_pll Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (mlkem_clk_clk_pll rise@0.000ns - mlkem_clk_clk_pll rise@0.000ns) Data Path Delay: 0.197ns (logic 0.141ns (71.611%) route 0.056ns (28.389%)) Logic Levels: 0 Clock Path Skew: 0.000ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.388ns Source Clock Delay (SCD): -0.617ns Clock Pessimism Removal (CPR): 0.229ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock mlkem_clk_clk_pll rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout3_buf/O net (fo=25775, routed) 0.645 -0.617 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/pushToPopGray_buffercc/mlkem_clk SLICE_X73Y93 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/pushToPopGray_buffercc/buffers_0_reg[1]/C ------------------------------------------------------------------- ------------------- SLICE_X73Y93 FDCE (Prop_fdce_C_Q) 0.141 -0.476 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/pushToPopGray_buffercc/buffers_0_reg[1]/Q net (fo=1, routed) 0.056 -0.420 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/pushToPopGray_buffercc/buffers_0[1] SLICE_X73Y93 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/pushToPopGray_buffercc/buffers_1_reg[1]/D ------------------------------------------------------------------- ------------------- (clock mlkem_clk_clk_pll rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout3_buf/O net (fo=25775, routed) 0.920 -0.388 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/pushToPopGray_buffercc/mlkem_clk SLICE_X73Y93 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/pushToPopGray_buffercc/buffers_1_reg[1]/C clock pessimism -0.229 -0.617 SLICE_X73Y93 FDCE (Hold_fdce_C_D) 0.071 -0.546 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/pushToPopGray_buffercc/buffers_1_reg[1] ------------------------------------------------------------------- required time 0.546 arrival time -0.420 ------------------------------------------------------------------- slack 0.126 Slack (MET) : 0.126ns (arrival time - required time) Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/popToPushGray_buffercc/buffers_0_reg[1]/C (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/popToPushGray_buffercc/buffers_1_reg[1]/D (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) Path Group: mlkem_clk_clk_pll Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (mlkem_clk_clk_pll rise@0.000ns - mlkem_clk_clk_pll rise@0.000ns) Data Path Delay: 0.197ns (logic 0.141ns (71.611%) route 0.056ns (28.389%)) Logic Levels: 0 Clock Path Skew: 0.000ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.387ns Source Clock Delay (SCD): -0.616ns Clock Pessimism Removal (CPR): 0.229ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock mlkem_clk_clk_pll rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout3_buf/O net (fo=25775, routed) 0.646 -0.616 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/popToPushGray_buffercc/mlkem_clk SLICE_X67Y96 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/popToPushGray_buffercc/buffers_0_reg[1]/C ------------------------------------------------------------------- ------------------- SLICE_X67Y96 FDCE (Prop_fdce_C_Q) 0.141 -0.475 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/popToPushGray_buffercc/buffers_0_reg[1]/Q net (fo=1, routed) 0.056 -0.419 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/popToPushGray_buffercc/buffers_0[1] SLICE_X67Y96 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/popToPushGray_buffercc/buffers_1_reg[1]/D ------------------------------------------------------------------- ------------------- (clock mlkem_clk_clk_pll rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout3_buf/O net (fo=25775, routed) 0.921 -0.387 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/popToPushGray_buffercc/mlkem_clk SLICE_X67Y96 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/popToPushGray_buffercc/buffers_1_reg[1]/C clock pessimism -0.229 -0.616 SLICE_X67Y96 FDCE (Hold_fdce_C_D) 0.071 -0.545 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/popToPushGray_buffercc/buffers_1_reg[1] ------------------------------------------------------------------- required time 0.545 arrival time -0.419 ------------------------------------------------------------------- slack 0.126 Slack (MET) : 0.126ns (arrival time - required time) Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/popToPushGray_buffercc/buffers_0_reg[1]/C (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/popToPushGray_buffercc/buffers_1_reg[1]/D (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) Path Group: mlkem_clk_clk_pll Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (mlkem_clk_clk_pll rise@0.000ns - mlkem_clk_clk_pll rise@0.000ns) Data Path Delay: 0.197ns (logic 0.141ns (71.611%) route 0.056ns (28.389%)) Logic Levels: 0 Clock Path Skew: 0.000ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.387ns Source Clock Delay (SCD): -0.616ns Clock Pessimism Removal (CPR): 0.229ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock mlkem_clk_clk_pll rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout3_buf/O net (fo=25775, routed) 0.646 -0.616 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/popToPushGray_buffercc/mlkem_clk SLICE_X67Y95 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/popToPushGray_buffercc/buffers_0_reg[1]/C ------------------------------------------------------------------- ------------------- SLICE_X67Y95 FDCE (Prop_fdce_C_Q) 0.141 -0.475 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/popToPushGray_buffercc/buffers_0_reg[1]/Q net (fo=1, routed) 0.056 -0.419 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/popToPushGray_buffercc/buffers_0[1] SLICE_X67Y95 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/popToPushGray_buffercc/buffers_1_reg[1]/D ------------------------------------------------------------------- ------------------- (clock mlkem_clk_clk_pll rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout3_buf/O net (fo=25775, routed) 0.921 -0.387 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/popToPushGray_buffercc/mlkem_clk SLICE_X67Y95 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/popToPushGray_buffercc/buffers_1_reg[1]/C clock pessimism -0.229 -0.616 SLICE_X67Y95 FDCE (Hold_fdce_C_D) 0.071 -0.545 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/popToPushGray_buffercc/buffers_1_reg[1] ------------------------------------------------------------------- required time 0.545 arrival time -0.419 ------------------------------------------------------------------- slack 0.126 Slack (MET) : 0.126ns (arrival time - required time) Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/pushToPopGray_buffercc/buffers_0_reg[1]/C (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/pushToPopGray_buffercc/buffers_1_reg[1]/D (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) Path Group: mlkem_clk_clk_pll Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (mlkem_clk_clk_pll rise@0.000ns - mlkem_clk_clk_pll rise@0.000ns) Data Path Delay: 0.197ns (logic 0.141ns (71.611%) route 0.056ns (28.389%)) Logic Levels: 0 Clock Path Skew: 0.000ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.388ns Source Clock Delay (SCD): -0.617ns Clock Pessimism Removal (CPR): 0.229ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock mlkem_clk_clk_pll rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout3_buf/O net (fo=25775, routed) 0.645 -0.617 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/pushToPopGray_buffercc/mlkem_clk SLICE_X71Y95 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/pushToPopGray_buffercc/buffers_0_reg[1]/C ------------------------------------------------------------------- ------------------- SLICE_X71Y95 FDCE (Prop_fdce_C_Q) 0.141 -0.476 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/pushToPopGray_buffercc/buffers_0_reg[1]/Q net (fo=1, routed) 0.056 -0.420 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/pushToPopGray_buffercc/buffers_0[1] SLICE_X71Y95 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/pushToPopGray_buffercc/buffers_1_reg[1]/D ------------------------------------------------------------------- ------------------- (clock mlkem_clk_clk_pll rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout3_buf/O net (fo=25775, routed) 0.920 -0.388 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/pushToPopGray_buffercc/mlkem_clk SLICE_X71Y95 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/pushToPopGray_buffercc/buffers_1_reg[1]/C clock pessimism -0.229 -0.617 SLICE_X71Y95 FDCE (Hold_fdce_C_D) 0.071 -0.546 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/pushToPopGray_buffercc/buffers_1_reg[1] ------------------------------------------------------------------- required time 0.546 arrival time -0.420 ------------------------------------------------------------------- slack 0.126 Slack (MET) : 0.128ns (arrival time - required time) Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/c_widx_reg[4]/C (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_se/mem_reg/ADDRARDADDR[8] (rising edge-triggered cell RAMB36E1 clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) Path Group: mlkem_clk_clk_pll Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (mlkem_clk_clk_pll rise@0.000ns - mlkem_clk_clk_pll rise@0.000ns) Data Path Delay: 0.617ns (logic 0.209ns (33.847%) route 0.408ns (66.153%)) Logic Levels: 1 (LUT5=1) Clock Path Skew: 0.306ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.413ns Source Clock Delay (SCD): -0.674ns Clock Pessimism Removal (CPR): -0.045ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock mlkem_clk_clk_pll rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout3_buf/O net (fo=25775, routed) 0.589 -0.674 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mlkem_clk SLICE_X42Y149 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/c_widx_reg[4]/C ------------------------------------------------------------------- ------------------- SLICE_X42Y149 FDCE (Prop_fdce_C_Q) 0.164 -0.510 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/c_widx_reg[4]/Q net (fo=5, routed) 0.197 -0.313 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/mem_reg_4[1] SLICE_X42Y150 LUT5 (Prop_lut5_I1_O) 0.045 -0.268 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/mem_reg_i_8/O net (fo=1, routed) 0.211 -0.056 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_se/ADDRARDADDR[4] RAMB36_X2Y30 RAMB36E1 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_se/mem_reg/ADDRARDADDR[8] ------------------------------------------------------------------- ------------------- (clock mlkem_clk_clk_pll rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout3_buf/O net (fo=25775, routed) 0.895 -0.413 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_se/mlkem_clk RAMB36_X2Y30 RAMB36E1 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_se/mem_reg/CLKARDCLK clock pessimism 0.045 -0.368 RAMB36_X2Y30 RAMB36E1 (Hold_ramb36e1_CLKARDCLK_ADDRARDADDR[8]) 0.183 -0.185 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_se/mem_reg ------------------------------------------------------------------- required time 0.185 arrival time -0.056 ------------------------------------------------------------------- slack 0.128 Slack (MET) : 0.130ns (arrival time - required time) Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/b_out_r_reg[1]/C (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/wb_b_data_r_reg[1]/D (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) Path Group: mlkem_clk_clk_pll Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (mlkem_clk_clk_pll rise@0.000ns - mlkem_clk_clk_pll rise@0.000ns) Data Path Delay: 0.228ns (logic 0.141ns (61.814%) route 0.087ns (38.186%)) Logic Levels: 0 Clock Path Skew: 0.013ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.475ns Source Clock Delay (SCD): -0.699ns Clock Pessimism Removal (CPR): 0.211ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock mlkem_clk_clk_pll rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout3_buf/O net (fo=25775, routed) 0.564 -0.699 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/mlkem_clk SLICE_X77Y166 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/b_out_r_reg[1]/C ------------------------------------------------------------------- ------------------- SLICE_X77Y166 FDCE (Prop_fdce_C_Q) 0.141 -0.558 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/b_out_r_reg[1]/Q net (fo=1, routed) 0.087 -0.471 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/bf_b_out[1] SLICE_X76Y166 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/wb_b_data_r_reg[1]/D ------------------------------------------------------------------- ------------------- (clock mlkem_clk_clk_pll rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout3_buf/O net (fo=25775, routed) 0.833 -0.475 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/mlkem_clk SLICE_X76Y166 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/wb_b_data_r_reg[1]/C clock pessimism -0.211 -0.686 SLICE_X76Y166 FDCE (Hold_fdce_C_D) 0.085 -0.601 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/wb_b_data_r_reg[1] ------------------------------------------------------------------- required time 0.601 arrival time -0.471 ------------------------------------------------------------------- slack 0.130 Slack (MET) : 0.134ns (arrival time - required time) Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_scl/p_s2_reg[19]/C (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_scl/p_s3_reg[19]/D (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) Path Group: mlkem_clk_clk_pll Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (mlkem_clk_clk_pll rise@0.000ns - mlkem_clk_clk_pll rise@0.000ns) Data Path Delay: 0.232ns (logic 0.141ns (60.749%) route 0.091ns (39.251%)) Logic Levels: 0 Clock Path Skew: 0.013ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.456ns Source Clock Delay (SCD): -0.681ns Clock Pessimism Removal (CPR): 0.212ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock mlkem_clk_clk_pll rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout3_buf/O net (fo=25775, routed) 0.582 -0.681 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_scl/mlkem_clk SLICE_X53Y153 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_scl/p_s2_reg[19]/C ------------------------------------------------------------------- ------------------- SLICE_X53Y153 FDCE (Prop_fdce_C_Q) 0.141 -0.540 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_scl/p_s2_reg[19]/Q net (fo=1, routed) 0.091 -0.449 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_scl/p_s2[19] SLICE_X52Y153 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_scl/p_s3_reg[19]/D ------------------------------------------------------------------- ------------------- (clock mlkem_clk_clk_pll rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout3_buf/O net (fo=25775, routed) 0.851 -0.456 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_scl/mlkem_clk SLICE_X52Y153 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_scl/p_s3_reg[19]/C clock pessimism -0.212 -0.668 SLICE_X52Y153 FDCE (Hold_fdce_C_D) 0.085 -0.583 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_scl/p_s3_reg[19] ------------------------------------------------------------------- required time 0.583 arrival time -0.449 ------------------------------------------------------------------- slack 0.134 Slack (MET) : 0.136ns (arrival time - required time) Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/w_id_reg[4]/C (rising edge-triggered cell FDRE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/ram_reg_0_3_0_5/RAMC/I (rising edge-triggered cell RAMD32 clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) Path Group: mlkem_clk_clk_pll Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (mlkem_clk_clk_pll rise@0.000ns - mlkem_clk_clk_pll rise@0.000ns) Data Path Delay: 0.242ns (logic 0.128ns (52.976%) route 0.114ns (47.024%)) Logic Levels: 0 Clock Path Skew: 0.016ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.385ns Source Clock Delay (SCD): -0.614ns Clock Pessimism Removal (CPR): 0.213ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock mlkem_clk_clk_pll rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout3_buf/O net (fo=25775, routed) 0.648 -0.614 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/mlkem_clk SLICE_X65Y96 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/w_id_reg[4]/C ------------------------------------------------------------------- ------------------- SLICE_X65Y96 FDRE (Prop_fdre_C_Q) 0.128 -0.486 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/w_id_reg[4]/Q net (fo=1, routed) 0.114 -0.373 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/ram_reg_0_3_0_5/DIC0 SLICE_X64Y95 RAMD32 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/ram_reg_0_3_0_5/RAMC/I ------------------------------------------------------------------- ------------------- (clock mlkem_clk_clk_pll rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout3_buf/O net (fo=25775, routed) 0.923 -0.385 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/ram_reg_0_3_0_5/WCLK SLICE_X64Y95 RAMD32 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/ram_reg_0_3_0_5/RAMC/CLK clock pessimism -0.213 -0.598 SLICE_X64Y95 RAMD32 (Hold_ramd32_CLK_I) 0.090 -0.508 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/ram_reg_0_3_0_5/RAMC ------------------------------------------------------------------- required time 0.508 arrival time -0.373 ------------------------------------------------------------------- slack 0.136 Slack (MET) : 0.136ns (arrival time - required time) Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/cd_coeff_reg[8]/C (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/coeff_s0_reg[8]/D (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) Path Group: mlkem_clk_clk_pll Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (mlkem_clk_clk_pll rise@0.000ns - mlkem_clk_clk_pll rise@0.000ns) Data Path Delay: 0.280ns (logic 0.189ns (67.475%) route 0.091ns (32.525%)) Logic Levels: 1 (LUT3=1) Clock Path Skew: 0.013ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.424ns Source Clock Delay (SCD): -0.651ns Clock Pessimism Removal (CPR): 0.214ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock mlkem_clk_clk_pll rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout3_buf/O net (fo=25775, routed) 0.612 -0.651 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mlkem_clk SLICE_X41Y156 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/cd_coeff_reg[8]/C ------------------------------------------------------------------- ------------------- SLICE_X41Y156 FDCE (Prop_fdce_C_Q) 0.141 -0.510 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/cd_coeff_reg[8]/Q net (fo=1, routed) 0.091 -0.419 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/coeff_s0_reg[11]_1[8] SLICE_X40Y156 LUT3 (Prop_lut3_I2_O) 0.048 -0.371 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/coeff_s0[8]_i_1/O net (fo=1, routed) 0.000 -0.371 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/cd_in_mux[8] SLICE_X40Y156 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/coeff_s0_reg[8]/D ------------------------------------------------------------------- ------------------- (clock mlkem_clk_clk_pll rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout3_buf/O net (fo=25775, routed) 0.884 -0.424 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/mlkem_clk SLICE_X40Y156 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/coeff_s0_reg[8]/C clock pessimism -0.214 -0.638 SLICE_X40Y156 FDCE (Hold_fdce_C_D) 0.131 -0.507 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/coeff_s0_reg[8] ------------------------------------------------------------------- required time 0.507 arrival time -0.371 ------------------------------------------------------------------- slack 0.136 Slack (MET) : 0.139ns (arrival time - required time) Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/bf_inflight_reg[2]/C (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/bf_inflight_reg[4]/D (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) Path Group: mlkem_clk_clk_pll Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (mlkem_clk_clk_pll rise@0.000ns - mlkem_clk_clk_pll rise@0.000ns) Data Path Delay: 0.273ns (logic 0.186ns (68.080%) route 0.087ns (31.920%)) Logic Levels: 1 (LUT5=1) Clock Path Skew: 0.013ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.470ns Source Clock Delay (SCD): -0.696ns Clock Pessimism Removal (CPR): 0.213ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock mlkem_clk_clk_pll rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout3_buf/O net (fo=25775, routed) 0.567 -0.696 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/mlkem_clk SLICE_X77Y160 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/bf_inflight_reg[2]/C ------------------------------------------------------------------- ------------------- SLICE_X77Y160 FDCE (Prop_fdce_C_Q) 0.141 -0.555 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/bf_inflight_reg[2]/Q net (fo=6, routed) 0.087 -0.468 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/bf_inflight_reg_n_0_[2] SLICE_X76Y160 LUT5 (Prop_lut5_I2_O) 0.045 -0.423 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/bf_inflight[4]_i_2/O net (fo=1, routed) 0.000 -0.423 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/bf_inflight[4] SLICE_X76Y160 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/bf_inflight_reg[4]/D ------------------------------------------------------------------- ------------------- (clock mlkem_clk_clk_pll rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout3_buf/O net (fo=25775, routed) 0.838 -0.470 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/mlkem_clk SLICE_X76Y160 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/bf_inflight_reg[4]/C clock pessimism -0.213 -0.683 SLICE_X76Y160 FDCE (Hold_fdce_C_D) 0.121 -0.562 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/bf_inflight_reg[4] ------------------------------------------------------------------- required time 0.562 arrival time -0.423 ------------------------------------------------------------------- slack 0.139 Slack (MET) : 0.139ns (arrival time - required time) Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/j_reg[0]_rep__10/C (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/j_reg[0]_rep__8/D (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) Path Group: mlkem_clk_clk_pll Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (mlkem_clk_clk_pll rise@0.000ns - mlkem_clk_clk_pll rise@0.000ns) Data Path Delay: 0.493ns (logic 0.186ns (37.717%) route 0.307ns (62.283%)) Logic Levels: 1 (LUT6=1) Clock Path Skew: 0.262ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.483ns Source Clock Delay (SCD): -0.705ns Clock Pessimism Removal (CPR): -0.040ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock mlkem_clk_clk_pll rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout3_buf/O net (fo=25775, routed) 0.558 -0.705 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/mlkem_clk SLICE_X85Y164 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/j_reg[0]_rep__10/C ------------------------------------------------------------------- ------------------- SLICE_X85Y164 FDCE (Prop_fdce_C_Q) 0.141 -0.564 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/j_reg[0]_rep__10/Q net (fo=26, routed) 0.307 -0.257 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/j_reg[0]_rep__10_n_0 SLICE_X83Y165 LUT6 (Prop_lut6_I2_O) 0.045 -0.212 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/j[0]_rep_i_1__8/O net (fo=1, routed) 0.000 -0.212 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/j[0]_rep_i_1__8_n_0 SLICE_X83Y165 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/j_reg[0]_rep__8/D ------------------------------------------------------------------- ------------------- (clock mlkem_clk_clk_pll rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout3_buf/O net (fo=25775, routed) 0.825 -0.483 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/mlkem_clk SLICE_X83Y165 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/j_reg[0]_rep__8/C clock pessimism 0.040 -0.443 SLICE_X83Y165 FDCE (Hold_fdce_C_D) 0.092 -0.351 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/j_reg[0]_rep__8 ------------------------------------------------------------------- required time 0.351 arrival time -0.212 ------------------------------------------------------------------- slack 0.139 Slack (MET) : 0.140ns (arrival time - required time) Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/e_rho_reg[4]/C (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/e_done_reg/D (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) Path Group: mlkem_clk_clk_pll Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (mlkem_clk_clk_pll rise@0.000ns - mlkem_clk_clk_pll rise@0.000ns) Data Path Delay: 0.274ns (logic 0.186ns (67.773%) route 0.088ns (32.227%)) Logic Levels: 1 (LUT6=1) Clock Path Skew: 0.013ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.434ns Source Clock Delay (SCD): -0.658ns Clock Pessimism Removal (CPR): 0.211ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock mlkem_clk_clk_pll rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout3_buf/O net (fo=25775, routed) 0.605 -0.658 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mlkem_clk SLICE_X41Y125 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/e_rho_reg[4]/C ------------------------------------------------------------------- ------------------- SLICE_X41Y125 FDCE (Prop_fdce_C_Q) 0.141 -0.517 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/e_rho_reg[4]/Q net (fo=68, routed) 0.088 -0.429 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_sha3/e_done_reg_0[1] SLICE_X40Y125 LUT6 (Prop_lut6_I2_O) 0.045 -0.384 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_sha3/e_done_i_1/O net (fo=1, routed) 0.000 -0.384 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_sha3_n_870 SLICE_X40Y125 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/e_done_reg/D ------------------------------------------------------------------- ------------------- (clock mlkem_clk_clk_pll rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout3_buf/O net (fo=25775, routed) 0.874 -0.434 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mlkem_clk SLICE_X40Y125 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/e_done_reg/C clock pessimism -0.211 -0.645 SLICE_X40Y125 FDCE (Hold_fdce_C_D) 0.121 -0.524 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/e_done_reg ------------------------------------------------------------------- required time 0.524 arrival time -0.384 ------------------------------------------------------------------- slack 0.140 Slack (MET) : 0.141ns (arrival time - required time) Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/n_widx_reg[1]/C (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/n_widx_reg[3]/D (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) Path Group: mlkem_clk_clk_pll Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (mlkem_clk_clk_pll rise@0.000ns - mlkem_clk_clk_pll rise@0.000ns) Data Path Delay: 0.514ns (logic 0.225ns (43.781%) route 0.289ns (56.219%)) Logic Levels: 1 (LUT5=1) Clock Path Skew: 0.266ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.423ns Source Clock Delay (SCD): -0.644ns Clock Pessimism Removal (CPR): -0.045ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock mlkem_clk_clk_pll rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout3_buf/O net (fo=25775, routed) 0.619 -0.644 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mlkem_clk SLICE_X39Y149 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/n_widx_reg[1]/C ------------------------------------------------------------------- ------------------- SLICE_X39Y149 FDCE (Prop_fdce_C_Q) 0.128 -0.516 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/n_widx_reg[1]/Q net (fo=7, routed) 0.289 -0.227 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/n_widx_reg[7][1] SLICE_X38Y150 LUT5 (Prop_lut5_I2_O) 0.097 -0.130 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/n_widx[3]_i_1/O net (fo=1, routed) 0.000 -0.130 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/n_widx0_out[3] SLICE_X38Y150 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/n_widx_reg[3]/D ------------------------------------------------------------------- ------------------- (clock mlkem_clk_clk_pll rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout3_buf/O net (fo=25775, routed) 0.885 -0.423 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mlkem_clk SLICE_X38Y150 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/n_widx_reg[3]/C clock pessimism 0.045 -0.378 SLICE_X38Y150 FDCE (Hold_fdce_C_D) 0.107 -0.271 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/n_widx_reg[3] ------------------------------------------------------------------- required time 0.271 arrival time -0.130 ------------------------------------------------------------------- slack 0.141 Slack (MET) : 0.141ns (arrival time - required time) Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/j_reg[0]_rep__10/C (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/j_reg[0]_rep__0/D (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) Path Group: mlkem_clk_clk_pll Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (mlkem_clk_clk_pll rise@0.000ns - mlkem_clk_clk_pll rise@0.000ns) Data Path Delay: 0.494ns (logic 0.186ns (37.641%) route 0.308ns (62.359%)) Logic Levels: 1 (LUT6=1) Clock Path Skew: 0.262ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.483ns Source Clock Delay (SCD): -0.705ns Clock Pessimism Removal (CPR): -0.040ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock mlkem_clk_clk_pll rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout3_buf/O net (fo=25775, routed) 0.558 -0.705 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/mlkem_clk SLICE_X85Y164 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/j_reg[0]_rep__10/C ------------------------------------------------------------------- ------------------- SLICE_X85Y164 FDCE (Prop_fdce_C_Q) 0.141 -0.564 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/j_reg[0]_rep__10/Q net (fo=26, routed) 0.308 -0.256 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/j_reg[0]_rep__10_n_0 SLICE_X83Y165 LUT6 (Prop_lut6_I2_O) 0.045 -0.211 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/j[0]_rep_i_1__0/O net (fo=1, routed) 0.000 -0.211 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/j[0]_rep_i_1__0_n_0 SLICE_X83Y165 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/j_reg[0]_rep__0/D ------------------------------------------------------------------- ------------------- (clock mlkem_clk_clk_pll rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout3_buf/O net (fo=25775, routed) 0.825 -0.483 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/mlkem_clk SLICE_X83Y165 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/j_reg[0]_rep__0/C clock pessimism 0.040 -0.443 SLICE_X83Y165 FDCE (Hold_fdce_C_D) 0.091 -0.352 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/j_reg[0]_rep__0 ------------------------------------------------------------------- required time 0.352 arrival time -0.211 ------------------------------------------------------------------- slack 0.141 Slack (MET) : 0.141ns (arrival time - required time) Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/pushCC_pushPtr_reg[2]/C (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_0_5/RAMA/WADR2 (rising edge-triggered cell RAMD32 clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) Path Group: mlkem_clk_clk_pll Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (mlkem_clk_clk_pll rise@0.000ns - mlkem_clk_clk_pll rise@0.000ns) Data Path Delay: 0.380ns (logic 0.148ns (38.900%) route 0.232ns (61.100%)) Logic Levels: 0 Clock Path Skew: 0.038ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.384ns Source Clock Delay (SCD): -0.614ns Clock Pessimism Removal (CPR): 0.192ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock mlkem_clk_clk_pll rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout3_buf/O net (fo=25775, routed) 0.648 -0.614 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/mlkem_clk SLICE_X64Y93 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/pushCC_pushPtr_reg[2]/C ------------------------------------------------------------------- ------------------- SLICE_X64Y93 FDCE (Prop_fdce_C_Q) 0.148 -0.466 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/pushCC_pushPtr_reg[2]/Q net (fo=60, routed) 0.232 -0.234 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_0_5/ADDRD2 SLICE_X62Y93 RAMD32 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_0_5/RAMA/WADR2 ------------------------------------------------------------------- ------------------- (clock mlkem_clk_clk_pll rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout3_buf/O net (fo=25775, routed) 0.924 -0.384 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_0_5/WCLK SLICE_X62Y93 RAMD32 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_0_5/RAMA/CLK clock pessimism -0.192 -0.576 SLICE_X62Y93 RAMD32 (Hold_ramd32_CLK_WADR2) 0.201 -0.375 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_0_5/RAMA ------------------------------------------------------------------- required time 0.375 arrival time -0.234 ------------------------------------------------------------------- slack 0.141 Slack (MET) : 0.141ns (arrival time - required time) Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/pushCC_pushPtr_reg[2]/C (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_0_5/RAMA_D1/WADR2 (rising edge-triggered cell RAMD32 clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) Path Group: mlkem_clk_clk_pll Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (mlkem_clk_clk_pll rise@0.000ns - mlkem_clk_clk_pll rise@0.000ns) Data Path Delay: 0.380ns (logic 0.148ns (38.900%) route 0.232ns (61.100%)) Logic Levels: 0 Clock Path Skew: 0.038ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.384ns Source Clock Delay (SCD): -0.614ns Clock Pessimism Removal (CPR): 0.192ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock mlkem_clk_clk_pll rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout3_buf/O net (fo=25775, routed) 0.648 -0.614 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/mlkem_clk SLICE_X64Y93 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/pushCC_pushPtr_reg[2]/C ------------------------------------------------------------------- ------------------- SLICE_X64Y93 FDCE (Prop_fdce_C_Q) 0.148 -0.466 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/pushCC_pushPtr_reg[2]/Q net (fo=60, routed) 0.232 -0.234 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_0_5/ADDRD2 SLICE_X62Y93 RAMD32 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_0_5/RAMA_D1/WADR2 ------------------------------------------------------------------- ------------------- (clock mlkem_clk_clk_pll rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout3_buf/O net (fo=25775, routed) 0.924 -0.384 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_0_5/WCLK SLICE_X62Y93 RAMD32 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_0_5/RAMA_D1/CLK clock pessimism -0.192 -0.576 SLICE_X62Y93 RAMD32 (Hold_ramd32_CLK_WADR2) 0.201 -0.375 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_0_5/RAMA_D1 ------------------------------------------------------------------- required time 0.375 arrival time -0.234 ------------------------------------------------------------------- slack 0.141 Slack (MET) : 0.141ns (arrival time - required time) Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/pushCC_pushPtr_reg[2]/C (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_0_5/RAMB/WADR2 (rising edge-triggered cell RAMD32 clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) Path Group: mlkem_clk_clk_pll Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (mlkem_clk_clk_pll rise@0.000ns - mlkem_clk_clk_pll rise@0.000ns) Data Path Delay: 0.380ns (logic 0.148ns (38.900%) route 0.232ns (61.100%)) Logic Levels: 0 Clock Path Skew: 0.038ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.384ns Source Clock Delay (SCD): -0.614ns Clock Pessimism Removal (CPR): 0.192ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock mlkem_clk_clk_pll rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout3_buf/O net (fo=25775, routed) 0.648 -0.614 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/mlkem_clk SLICE_X64Y93 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/pushCC_pushPtr_reg[2]/C ------------------------------------------------------------------- ------------------- SLICE_X64Y93 FDCE (Prop_fdce_C_Q) 0.148 -0.466 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/pushCC_pushPtr_reg[2]/Q net (fo=60, routed) 0.232 -0.234 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_0_5/ADDRD2 SLICE_X62Y93 RAMD32 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_0_5/RAMB/WADR2 ------------------------------------------------------------------- ------------------- (clock mlkem_clk_clk_pll rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout3_buf/O net (fo=25775, routed) 0.924 -0.384 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_0_5/WCLK SLICE_X62Y93 RAMD32 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_0_5/RAMB/CLK clock pessimism -0.192 -0.576 SLICE_X62Y93 RAMD32 (Hold_ramd32_CLK_WADR2) 0.201 -0.375 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_0_5/RAMB ------------------------------------------------------------------- required time 0.375 arrival time -0.234 ------------------------------------------------------------------- slack 0.141 Slack (MET) : 0.141ns (arrival time - required time) Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/pushCC_pushPtr_reg[2]/C (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_0_5/RAMB_D1/WADR2 (rising edge-triggered cell RAMD32 clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) Path Group: mlkem_clk_clk_pll Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (mlkem_clk_clk_pll rise@0.000ns - mlkem_clk_clk_pll rise@0.000ns) Data Path Delay: 0.380ns (logic 0.148ns (38.900%) route 0.232ns (61.100%)) Logic Levels: 0 Clock Path Skew: 0.038ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.384ns Source Clock Delay (SCD): -0.614ns Clock Pessimism Removal (CPR): 0.192ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock mlkem_clk_clk_pll rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout3_buf/O net (fo=25775, routed) 0.648 -0.614 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/mlkem_clk SLICE_X64Y93 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/pushCC_pushPtr_reg[2]/C ------------------------------------------------------------------- ------------------- SLICE_X64Y93 FDCE (Prop_fdce_C_Q) 0.148 -0.466 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/pushCC_pushPtr_reg[2]/Q net (fo=60, routed) 0.232 -0.234 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_0_5/ADDRD2 SLICE_X62Y93 RAMD32 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_0_5/RAMB_D1/WADR2 ------------------------------------------------------------------- ------------------- (clock mlkem_clk_clk_pll rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout3_buf/O net (fo=25775, routed) 0.924 -0.384 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_0_5/WCLK SLICE_X62Y93 RAMD32 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_0_5/RAMB_D1/CLK clock pessimism -0.192 -0.576 SLICE_X62Y93 RAMD32 (Hold_ramd32_CLK_WADR2) 0.201 -0.375 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_0_5/RAMB_D1 ------------------------------------------------------------------- required time 0.375 arrival time -0.234 ------------------------------------------------------------------- slack 0.141 Slack (MET) : 0.141ns (arrival time - required time) Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/pushCC_pushPtr_reg[2]/C (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_0_5/RAMC/WADR2 (rising edge-triggered cell RAMD32 clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) Path Group: mlkem_clk_clk_pll Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (mlkem_clk_clk_pll rise@0.000ns - mlkem_clk_clk_pll rise@0.000ns) Data Path Delay: 0.380ns (logic 0.148ns (38.900%) route 0.232ns (61.100%)) Logic Levels: 0 Clock Path Skew: 0.038ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.384ns Source Clock Delay (SCD): -0.614ns Clock Pessimism Removal (CPR): 0.192ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock mlkem_clk_clk_pll rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout3_buf/O net (fo=25775, routed) 0.648 -0.614 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/mlkem_clk SLICE_X64Y93 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/pushCC_pushPtr_reg[2]/C ------------------------------------------------------------------- ------------------- SLICE_X64Y93 FDCE (Prop_fdce_C_Q) 0.148 -0.466 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/pushCC_pushPtr_reg[2]/Q net (fo=60, routed) 0.232 -0.234 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_0_5/ADDRD2 SLICE_X62Y93 RAMD32 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_0_5/RAMC/WADR2 ------------------------------------------------------------------- ------------------- (clock mlkem_clk_clk_pll rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout3_buf/O net (fo=25775, routed) 0.924 -0.384 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_0_5/WCLK SLICE_X62Y93 RAMD32 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_0_5/RAMC/CLK clock pessimism -0.192 -0.576 SLICE_X62Y93 RAMD32 (Hold_ramd32_CLK_WADR2) 0.201 -0.375 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_0_5/RAMC ------------------------------------------------------------------- required time 0.375 arrival time -0.234 ------------------------------------------------------------------- slack 0.141 Slack (MET) : 0.141ns (arrival time - required time) Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/pushCC_pushPtr_reg[2]/C (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_0_5/RAMC_D1/WADR2 (rising edge-triggered cell RAMD32 clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) Path Group: mlkem_clk_clk_pll Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (mlkem_clk_clk_pll rise@0.000ns - mlkem_clk_clk_pll rise@0.000ns) Data Path Delay: 0.380ns (logic 0.148ns (38.900%) route 0.232ns (61.100%)) Logic Levels: 0 Clock Path Skew: 0.038ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.384ns Source Clock Delay (SCD): -0.614ns Clock Pessimism Removal (CPR): 0.192ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock mlkem_clk_clk_pll rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout3_buf/O net (fo=25775, routed) 0.648 -0.614 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/mlkem_clk SLICE_X64Y93 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/pushCC_pushPtr_reg[2]/C ------------------------------------------------------------------- ------------------- SLICE_X64Y93 FDCE (Prop_fdce_C_Q) 0.148 -0.466 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/pushCC_pushPtr_reg[2]/Q net (fo=60, routed) 0.232 -0.234 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_0_5/ADDRD2 SLICE_X62Y93 RAMD32 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_0_5/RAMC_D1/WADR2 ------------------------------------------------------------------- ------------------- (clock mlkem_clk_clk_pll rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout3_buf/O net (fo=25775, routed) 0.924 -0.384 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_0_5/WCLK SLICE_X62Y93 RAMD32 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_0_5/RAMC_D1/CLK clock pessimism -0.192 -0.576 SLICE_X62Y93 RAMD32 (Hold_ramd32_CLK_WADR2) 0.201 -0.375 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_0_5/RAMC_D1 ------------------------------------------------------------------- required time 0.375 arrival time -0.234 ------------------------------------------------------------------- slack 0.141 Pulse Width Checks -------------------------------------------------------------------------------------- Clock Name: mlkem_clk_clk_pll Waveform(ns): { 0.000 20.000 } Period(ns): 40.000 Sources: { pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 } Check Type Corner Lib Pin Reference Pin Required(ns) Actual(ns) Slack(ns) Location Pin Min Period n/a RAMB18E1/CLKARDCLK n/a 2.944 40.000 37.056 RAMB18_X2Y52 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ct_bram/mem_reg/CLKARDCLK Min Period n/a RAMB18E1/CLKARDCLK n/a 2.944 40.000 37.056 RAMB18_X2Y49 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_dkp_bram/mem_reg/CLKARDCLK Min Period n/a RAMB18E1/CLKARDCLK n/a 2.944 40.000 37.056 RAMB18_X2Y50 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/mem_reg/CLKARDCLK Min Period n/a RAMB36E1/CLKARDCLK n/a 2.944 40.000 37.056 RAMB36_X2Y28 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_a/mem_reg_0/CLKARDCLK Min Period n/a RAMB18E1/CLKARDCLK n/a 2.944 40.000 37.056 RAMB18_X2Y58 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_a/mem_reg_1/CLKARDCLK Min Period n/a RAMB36E1/CLKARDCLK n/a 2.944 40.000 37.056 RAMB36_X2Y30 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_se/mem_reg/CLKARDCLK Min Period n/a RAMB18E1/CLKARDCLK n/a 2.944 40.000 37.056 RAMB18_X2Y59 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg/CLKARDCLK Min Period n/a RAMB18E1/CLKARDCLK n/a 2.944 40.000 37.056 RAMB18_X3Y48 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_c_in_bram/mem_reg/CLKARDCLK Min Period n/a RAMB18E1/CLKBWRCLK n/a 2.576 40.000 37.424 RAMB18_X2Y52 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ct_bram/mem_reg/CLKBWRCLK Min Period n/a RAMB18E1/CLKBWRCLK n/a 2.576 40.000 37.424 RAMB18_X2Y49 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_dkp_bram/mem_reg/CLKBWRCLK Min Period n/a RAMB18E1/CLKBWRCLK n/a 2.576 40.000 37.424 RAMB18_X2Y50 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/mem_reg/CLKBWRCLK Min Period n/a RAMB36E1/CLKBWRCLK n/a 2.576 40.000 37.424 RAMB36_X2Y28 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_a/mem_reg_0/CLKBWRCLK Min Period n/a RAMB18E1/CLKBWRCLK n/a 2.576 40.000 37.424 RAMB18_X2Y58 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_a/mem_reg_1/CLKBWRCLK Min Period n/a RAMB36E1/CLKBWRCLK n/a 2.576 40.000 37.424 RAMB36_X2Y30 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_se/mem_reg/CLKBWRCLK Min Period n/a RAMB18E1/CLKBWRCLK n/a 2.576 40.000 37.424 RAMB18_X2Y59 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg/CLKBWRCLK Min Period n/a RAMB18E1/CLKBWRCLK n/a 2.576 40.000 37.424 RAMB18_X3Y48 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_c_in_bram/mem_reg/CLKBWRCLK Min Period n/a BUFG/I n/a 2.155 40.000 37.845 BUFGCTRL_X0Y17 pll_clk.u_clk_pll/inst/clkout3_buf/I Min Period n/a DSP48E1/CLK n/a 2.154 40.000 37.846 DSP48_X1Y62 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/comp_qprod_est_s20/CLK Min Period n/a DSP48E1/CLK n/a 2.154 40.000 37.846 DSP48_X8Y61 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/u_bc/barrett_q_return0/CLK Min Period n/a DSP48E1/CLK n/a 2.154 40.000 37.846 DSP48_X7Y71 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/u_bc/p0__3/CLK Min Period n/a DSP48E1/CLK n/a 2.154 40.000 37.846 DSP48_X8Y68 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/u_bc/p0/CLK Min Period n/a DSP48E1/CLK n/a 2.154 40.000 37.846 DSP48_X4Y64 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/qprod_s40/CLK Min Period n/a DSP48E1/CLK n/a 2.154 40.000 37.846 DSP48_X8Y66 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/u_bc/p0__0/CLK Min Period n/a DSP48E1/CLK n/a 2.154 40.000 37.846 DSP48_X7Y64 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/u_bc/p0__1/CLK Min Period n/a DSP48E1/CLK n/a 2.154 40.000 37.846 DSP48_X7Y69 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/u_bc/p0__2/CLK Min Period n/a DSP48E1/CLK n/a 2.154 40.000 37.846 DSP48_X1Y65 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/decomp_round_next/CLK Min Period n/a DSP48E1/CLK n/a 2.154 40.000 37.846 DSP48_X3Y65 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/tk_s20/CLK Min Period n/a DSP48E1/CLK n/a 2.154 40.000 37.846 DSP48_X2Y64 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_scl/p_s10/CLK Min Period n/a DSP48E1/CLK n/a 2.154 40.000 37.846 DSP48_X2Y60 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_scl/qprod_s40/CLK Min Period n/a DSP48E1/CLK n/a 2.154 40.000 37.846 DSP48_X2Y62 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_scl/tk_s20/CLK Min Period n/a DSP48E1/CLK n/a 2.154 40.000 37.846 DSP48_X8Y67 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/u_bc/barrett_q0_return0/CLK Min Period n/a DSP48E1/CLK n/a 2.154 40.000 37.846 DSP48_X7Y70 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/u_bc/barrett_q1_return0/CLK Min Period n/a DSP48E1/CLK n/a 2.154 40.000 37.846 DSP48_X7Y68 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/u_bc/barrett_q2_return0/CLK Min Period n/a DSP48E1/CLK n/a 2.154 40.000 37.846 DSP48_X8Y64 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/u_bc/barrett_q3_return0/CLK Min Period n/a DSP48E1/CLK n/a 2.154 40.000 37.846 DSP48_X1Y64 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/comp_q_mul_q_s40/CLK Min Period n/a DSP48E1/CLK n/a 2.154 40.000 37.846 DSP48_X3Y64 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/p_s10/CLK Min Period n/a PLLE2_ADV/CLKOUT2 n/a 1.249 40.000 38.751 PLLE2_ADV_X0Y3 pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 Min Period n/a FDCE/C n/a 1.000 40.000 39.000 SLICE_X70Y163 _i_1/C Min Period n/a FDRE/C n/a 1.000 40.000 39.000 SLICE_X60Y163 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_scl/valid_sr_reg[5]_u_fft_mlkem_axi_slave_u_mlkem_axi_slave_u_mlkem_u_ntt_u_scl_valid_sr_reg_c_4/C Min Period n/a FDCE/C n/a 1.000 40.000 39.000 SLICE_X62Y163 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_scl/valid_sr_reg[6]/C Min Period n/a FDCE/C n/a 1.000 40.000 39.000 SLICE_X155Y163 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_scl/valid_sr_reg_c/C Min Period n/a FDCE/C n/a 1.000 40.000 39.000 SLICE_X145Y163 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_scl/valid_sr_reg_c_0/C Min Period n/a FDCE/C n/a 1.000 40.000 39.000 SLICE_X121Y164 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_scl/valid_sr_reg_c_1/C Min Period n/a FDCE/C n/a 1.000 40.000 39.000 SLICE_X86Y164 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_scl/valid_sr_reg_c_2/C Min Period n/a FDCE/C n/a 1.000 40.000 39.000 SLICE_X86Y165 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_scl/valid_sr_reg_c_3/C Min Period n/a FDCE/C n/a 1.000 40.000 39.000 SLICE_X81Y165 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_scl/valid_sr_reg_c_4/C Min Period n/a FDCE/C n/a 1.000 40.000 39.000 SLICE_X59Y158 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/valid_o_r_reg/C Min Period n/a FDRE/C n/a 1.000 40.000 39.000 SLICE_X80Y166 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/wa_d6_reg[0]_u_fft_mlkem_axi_slave_u_mlkem_axi_slave_u_mlkem_u_ntt_u_scl_valid_sr_reg_c_4/C Min Period n/a FDRE/C n/a 1.000 40.000 39.000 SLICE_X72Y166 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/wa_d6_reg[1]_u_fft_mlkem_axi_slave_u_mlkem_axi_slave_u_mlkem_u_ntt_u_scl_valid_sr_reg_c_4/C Min Period n/a FDRE/C n/a 1.000 40.000 39.000 SLICE_X60Y163 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/wa_d6_reg[2]_u_fft_mlkem_axi_slave_u_mlkem_axi_slave_u_mlkem_u_ntt_u_scl_valid_sr_reg_c_4/C Max Period n/a PLLE2_ADV/CLKOUT2 n/a 160.000 40.000 120.000 PLLE2_ADV_X0Y3 pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 Low Pulse Width Fast RAMD32/CLK n/a 1.250 20.000 18.750 SLICE_X64Y95 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/ram_reg_0_3_0_5/RAMA/CLK Low Pulse Width Fast RAMD32/CLK n/a 1.250 20.000 18.750 SLICE_X64Y95 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/ram_reg_0_3_0_5/RAMA_D1/CLK Low Pulse Width Fast RAMD32/CLK n/a 1.250 20.000 18.750 SLICE_X64Y95 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/ram_reg_0_3_0_5/RAMB/CLK Low Pulse Width Fast RAMD32/CLK n/a 1.250 20.000 18.750 SLICE_X64Y95 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/ram_reg_0_3_0_5/RAMB_D1/CLK Low Pulse Width Fast RAMD32/CLK n/a 1.250 20.000 18.750 SLICE_X64Y95 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/ram_reg_0_3_0_5/RAMC/CLK Low Pulse Width Fast RAMD32/CLK n/a 1.250 20.000 18.750 SLICE_X64Y95 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/ram_reg_0_3_0_5/RAMC_D1/CLK Low Pulse Width Fast RAMS32/CLK n/a 1.250 20.000 18.750 SLICE_X64Y95 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/ram_reg_0_3_0_5/RAMD/CLK Low Pulse Width Fast RAMS32/CLK n/a 1.250 20.000 18.750 SLICE_X64Y95 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/ram_reg_0_3_0_5/RAMD_D1/CLK Low Pulse Width Slow RAMD32/CLK n/a 1.250 20.000 18.750 SLICE_X62Y93 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_0_5/RAMA/CLK Low Pulse Width Slow RAMD32/CLK n/a 1.250 20.000 18.750 SLICE_X62Y93 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_0_5/RAMA_D1/CLK Low Pulse Width Slow RAMD32/CLK n/a 1.250 20.000 18.750 SLICE_X62Y93 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_0_5/RAMB/CLK Low Pulse Width Slow RAMD32/CLK n/a 1.250 20.000 18.750 SLICE_X62Y93 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_0_5/RAMB_D1/CLK Low Pulse Width Slow RAMD32/CLK n/a 1.250 20.000 18.750 SLICE_X62Y93 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_0_5/RAMC/CLK Low Pulse Width Slow RAMD32/CLK n/a 1.250 20.000 18.750 SLICE_X62Y93 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_0_5/RAMC_D1/CLK Low Pulse Width Slow RAMS32/CLK n/a 1.250 20.000 18.750 SLICE_X62Y93 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_0_5/RAMD/CLK Low Pulse Width Slow RAMS32/CLK n/a 1.250 20.000 18.750 SLICE_X62Y93 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_0_5/RAMD_D1/CLK Low Pulse Width Slow RAMD32/CLK n/a 1.250 20.000 18.750 SLICE_X62Y94 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_12_17/RAMA/CLK Low Pulse Width Slow RAMD32/CLK n/a 1.250 20.000 18.750 SLICE_X62Y94 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_12_17/RAMA_D1/CLK Low Pulse Width Slow RAMD32/CLK n/a 1.250 20.000 18.750 SLICE_X62Y94 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_12_17/RAMB/CLK Low Pulse Width Slow RAMD32/CLK n/a 1.250 20.000 18.750 SLICE_X62Y94 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_12_17/RAMB_D1/CLK Low Pulse Width Slow RAMD32/CLK n/a 1.250 20.000 18.750 SLICE_X62Y94 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_12_17/RAMC/CLK Low Pulse Width Slow RAMD32/CLK n/a 1.250 20.000 18.750 SLICE_X62Y94 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_12_17/RAMC_D1/CLK Low Pulse Width Slow RAMS32/CLK n/a 1.250 20.000 18.750 SLICE_X62Y94 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_12_17/RAMD/CLK Low Pulse Width Slow RAMS32/CLK n/a 1.250 20.000 18.750 SLICE_X62Y94 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_12_17/RAMD_D1/CLK Low Pulse Width Slow RAMD32/CLK n/a 1.250 20.000 18.750 SLICE_X56Y93 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_18_23/RAMA/CLK Low Pulse Width Slow RAMD32/CLK n/a 1.250 20.000 18.750 SLICE_X56Y93 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_18_23/RAMA_D1/CLK Low Pulse Width Slow RAMD32/CLK n/a 1.250 20.000 18.750 SLICE_X56Y93 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_18_23/RAMB/CLK Low Pulse Width Slow RAMD32/CLK n/a 1.250 20.000 18.750 SLICE_X56Y93 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_18_23/RAMB_D1/CLK Low Pulse Width Slow RAMD32/CLK n/a 1.250 20.000 18.750 SLICE_X56Y93 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_18_23/RAMC/CLK Low Pulse Width Slow RAMD32/CLK n/a 1.250 20.000 18.750 SLICE_X56Y93 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_18_23/RAMC_D1/CLK Low Pulse Width Slow RAMS32/CLK n/a 1.250 20.000 18.750 SLICE_X56Y93 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_18_23/RAMD/CLK Low Pulse Width Slow RAMS32/CLK n/a 1.250 20.000 18.750 SLICE_X56Y93 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_18_23/RAMD_D1/CLK Low Pulse Width Slow RAMD32/CLK n/a 1.250 20.000 18.750 SLICE_X56Y94 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_24_29/RAMA/CLK Low Pulse Width Slow RAMD32/CLK n/a 1.250 20.000 18.750 SLICE_X56Y94 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_24_29/RAMA_D1/CLK Low Pulse Width Slow RAMD32/CLK n/a 1.250 20.000 18.750 SLICE_X56Y94 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_24_29/RAMB/CLK Low Pulse Width Slow RAMD32/CLK n/a 1.250 20.000 18.750 SLICE_X56Y94 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_24_29/RAMB_D1/CLK Low Pulse Width Slow RAMD32/CLK n/a 1.250 20.000 18.750 SLICE_X56Y94 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_24_29/RAMC/CLK Low Pulse Width Slow RAMD32/CLK n/a 1.250 20.000 18.750 SLICE_X56Y94 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_24_29/RAMC_D1/CLK Low Pulse Width Slow RAMS32/CLK n/a 1.250 20.000 18.750 SLICE_X56Y94 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_24_29/RAMD/CLK Low Pulse Width Slow RAMS32/CLK n/a 1.250 20.000 18.750 SLICE_X56Y94 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_24_29/RAMD_D1/CLK Low Pulse Width Slow RAMD32/CLK n/a 1.250 20.000 18.750 SLICE_X46Y93 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_30_35/RAMA/CLK Low Pulse Width Slow RAMD32/CLK n/a 1.250 20.000 18.750 SLICE_X46Y93 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_30_35/RAMA_D1/CLK Low Pulse Width Slow RAMD32/CLK n/a 1.250 20.000 18.750 SLICE_X46Y93 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_30_35/RAMB/CLK Low Pulse Width Slow RAMD32/CLK n/a 1.250 20.000 18.750 SLICE_X46Y93 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_30_35/RAMB_D1/CLK Low Pulse Width Slow RAMD32/CLK n/a 1.250 20.000 18.750 SLICE_X46Y93 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_30_35/RAMC/CLK Low Pulse Width Slow RAMD32/CLK n/a 1.250 20.000 18.750 SLICE_X46Y93 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_30_35/RAMC_D1/CLK Low Pulse Width Slow RAMS32/CLK n/a 1.250 20.000 18.750 SLICE_X46Y93 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_30_35/RAMD/CLK Low Pulse Width Slow RAMS32/CLK n/a 1.250 20.000 18.750 SLICE_X46Y93 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_30_35/RAMD_D1/CLK Low Pulse Width Slow RAMD32/CLK n/a 1.250 20.000 18.750 SLICE_X48Y93 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_36_39/RAMA/CLK Low Pulse Width Slow RAMD32/CLK n/a 1.250 20.000 18.750 SLICE_X48Y93 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_36_39/RAMA_D1/CLK High Pulse Width Slow RAMD32/CLK n/a 1.250 20.000 18.750 SLICE_X64Y95 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/ram_reg_0_3_0_5/RAMA/CLK High Pulse Width Fast RAMD32/CLK n/a 1.250 20.000 18.750 SLICE_X64Y95 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/ram_reg_0_3_0_5/RAMA/CLK High Pulse Width Slow RAMD32/CLK n/a 1.250 20.000 18.750 SLICE_X64Y95 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/ram_reg_0_3_0_5/RAMA_D1/CLK High Pulse Width Fast RAMD32/CLK n/a 1.250 20.000 18.750 SLICE_X64Y95 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/ram_reg_0_3_0_5/RAMA_D1/CLK High Pulse Width Slow RAMD32/CLK n/a 1.250 20.000 18.750 SLICE_X64Y95 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/ram_reg_0_3_0_5/RAMB/CLK High Pulse Width Fast RAMD32/CLK n/a 1.250 20.000 18.750 SLICE_X64Y95 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/ram_reg_0_3_0_5/RAMB/CLK High Pulse Width Slow RAMD32/CLK n/a 1.250 20.000 18.750 SLICE_X64Y95 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/ram_reg_0_3_0_5/RAMB_D1/CLK High Pulse Width Fast RAMD32/CLK n/a 1.250 20.000 18.750 SLICE_X64Y95 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/ram_reg_0_3_0_5/RAMB_D1/CLK High Pulse Width Slow RAMD32/CLK n/a 1.250 20.000 18.750 SLICE_X64Y95 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/ram_reg_0_3_0_5/RAMC/CLK High Pulse Width Fast RAMD32/CLK n/a 1.250 20.000 18.750 SLICE_X64Y95 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/ram_reg_0_3_0_5/RAMC/CLK High Pulse Width Slow RAMD32/CLK n/a 1.250 20.000 18.750 SLICE_X64Y95 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/ram_reg_0_3_0_5/RAMC_D1/CLK High Pulse Width Fast RAMD32/CLK n/a 1.250 20.000 18.750 SLICE_X64Y95 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/ram_reg_0_3_0_5/RAMC_D1/CLK High Pulse Width Slow RAMS32/CLK n/a 1.250 20.000 18.750 SLICE_X64Y95 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/ram_reg_0_3_0_5/RAMD/CLK High Pulse Width Fast RAMS32/CLK n/a 1.250 20.000 18.750 SLICE_X64Y95 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/ram_reg_0_3_0_5/RAMD/CLK High Pulse Width Slow RAMS32/CLK n/a 1.250 20.000 18.750 SLICE_X64Y95 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/ram_reg_0_3_0_5/RAMD_D1/CLK High Pulse Width Fast RAMS32/CLK n/a 1.250 20.000 18.750 SLICE_X64Y95 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/ram_reg_0_3_0_5/RAMD_D1/CLK High Pulse Width Slow RAMD32/CLK n/a 1.250 20.000 18.750 SLICE_X62Y93 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_0_5/RAMA/CLK High Pulse Width Fast RAMD32/CLK n/a 1.250 20.000 18.750 SLICE_X62Y93 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_0_5/RAMA/CLK High Pulse Width Slow RAMD32/CLK n/a 1.250 20.000 18.750 SLICE_X62Y93 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_0_5/RAMA_D1/CLK High Pulse Width Fast RAMD32/CLK n/a 1.250 20.000 18.750 SLICE_X62Y93 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_0_5/RAMA_D1/CLK High Pulse Width Slow RAMD32/CLK n/a 1.250 20.000 18.750 SLICE_X62Y93 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_0_5/RAMB/CLK High Pulse Width Fast RAMD32/CLK n/a 1.250 20.000 18.750 SLICE_X62Y93 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_0_5/RAMB/CLK High Pulse Width Slow RAMD32/CLK n/a 1.250 20.000 18.750 SLICE_X62Y93 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_0_5/RAMB_D1/CLK High Pulse Width Fast RAMD32/CLK n/a 1.250 20.000 18.750 SLICE_X62Y93 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_0_5/RAMB_D1/CLK High Pulse Width Slow RAMD32/CLK n/a 1.250 20.000 18.750 SLICE_X62Y93 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_0_5/RAMC/CLK High Pulse Width Fast RAMD32/CLK n/a 1.250 20.000 18.750 SLICE_X62Y93 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_0_5/RAMC/CLK High Pulse Width Slow RAMD32/CLK n/a 1.250 20.000 18.750 SLICE_X62Y93 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_0_5/RAMC_D1/CLK High Pulse Width Fast RAMD32/CLK n/a 1.250 20.000 18.750 SLICE_X62Y93 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_0_5/RAMC_D1/CLK High Pulse Width Slow RAMS32/CLK n/a 1.250 20.000 18.750 SLICE_X62Y93 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_0_5/RAMD/CLK High Pulse Width Fast RAMS32/CLK n/a 1.250 20.000 18.750 SLICE_X62Y93 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_0_5/RAMD/CLK High Pulse Width Slow RAMS32/CLK n/a 1.250 20.000 18.750 SLICE_X62Y93 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_0_5/RAMD_D1/CLK High Pulse Width Fast RAMS32/CLK n/a 1.250 20.000 18.750 SLICE_X62Y93 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_0_5/RAMD_D1/CLK High Pulse Width Slow RAMD32/CLK n/a 1.250 20.000 18.750 SLICE_X62Y94 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_12_17/RAMA/CLK High Pulse Width Fast RAMD32/CLK n/a 1.250 20.000 18.750 SLICE_X62Y94 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_12_17/RAMA/CLK High Pulse Width Slow RAMD32/CLK n/a 1.250 20.000 18.750 SLICE_X62Y94 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_12_17/RAMA_D1/CLK High Pulse Width Fast RAMD32/CLK n/a 1.250 20.000 18.750 SLICE_X62Y94 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_12_17/RAMA_D1/CLK High Pulse Width Slow RAMD32/CLK n/a 1.250 20.000 18.750 SLICE_X62Y94 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_12_17/RAMB/CLK High Pulse Width Fast RAMD32/CLK n/a 1.250 20.000 18.750 SLICE_X62Y94 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_12_17/RAMB/CLK High Pulse Width Slow RAMD32/CLK n/a 1.250 20.000 18.750 SLICE_X62Y94 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_12_17/RAMB_D1/CLK High Pulse Width Fast RAMD32/CLK n/a 1.250 20.000 18.750 SLICE_X62Y94 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_12_17/RAMB_D1/CLK High Pulse Width Slow RAMD32/CLK n/a 1.250 20.000 18.750 SLICE_X62Y94 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_12_17/RAMC/CLK High Pulse Width Fast RAMD32/CLK n/a 1.250 20.000 18.750 SLICE_X62Y94 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_12_17/RAMC/CLK High Pulse Width Slow RAMD32/CLK n/a 1.250 20.000 18.750 SLICE_X62Y94 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_12_17/RAMC_D1/CLK High Pulse Width Fast RAMD32/CLK n/a 1.250 20.000 18.750 SLICE_X62Y94 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_12_17/RAMC_D1/CLK High Pulse Width Slow RAMS32/CLK n/a 1.250 20.000 18.750 SLICE_X62Y94 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_12_17/RAMD/CLK High Pulse Width Fast RAMS32/CLK n/a 1.250 20.000 18.750 SLICE_X62Y94 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_12_17/RAMD/CLK High Pulse Width Slow RAMS32/CLK n/a 1.250 20.000 18.750 SLICE_X62Y94 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_12_17/RAMD_D1/CLK High Pulse Width Fast RAMS32/CLK n/a 1.250 20.000 18.750 SLICE_X62Y94 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_12_17/RAMD_D1/CLK High Pulse Width Slow RAMD32/CLK n/a 1.250 20.000 18.750 SLICE_X56Y93 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_18_23/RAMA/CLK High Pulse Width Fast RAMD32/CLK n/a 1.250 20.000 18.750 SLICE_X56Y93 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_18_23/RAMA/CLK --------------------------------------------------------------------------------------------------- From Clock: sys_clk To Clock: sys_clk Setup : NA Failing Endpoints, Worst Slack NA , Total Violation NA Hold : 0 Failing Endpoints, Worst Slack 0.045ns, Total Violation 0.000ns PW : 0 Failing Endpoints, Worst Slack 8.750ns, Total Violation 0.000ns --------------------------------------------------------------------------------------------------- Min Delay Paths -------------------------------------------------------------------------------------- Slack (MET) : 0.045ns (arrival time - required time) Source: u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_7/cmdRouteFork_translated_fifo/fifo/logic_ptr_push_reg[0]/C (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: axi4WriteOnlyArbiter_7/cmdRouteFork_translated_fifo/fifo/logic_ram_reg_0_3_0_0/DP/WADR0 (rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: sys_clk Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) Data Path Delay: 0.368ns (logic 0.141ns (38.293%) route 0.227ns (61.707%)) Logic Levels: 0 Clock Path Skew: 0.013ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.354ns Source Clock Delay (SCD): -0.582ns Clock Pessimism Removal (CPR): 0.215ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9603, routed) 0.680 -0.582 u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_7/cmdRouteFork_translated_fifo/fifo/sys_clk SLICE_X41Y84 FDCE r u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_7/cmdRouteFork_translated_fifo/fifo/logic_ptr_push_reg[0]/C ------------------------------------------------------------------- ------------------- SLICE_X41Y84 FDCE (Prop_fdce_C_Q) 0.141 -0.441 r u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_7/cmdRouteFork_translated_fifo/fifo/logic_ptr_push_reg[0]/Q net (fo=8, routed) 0.227 -0.214 axi4WriteOnlyArbiter_7/cmdRouteFork_translated_fifo/fifo/logic_ram_reg_0_3_0_0/A0 SLICE_X40Y84 RAMD32 r axi4WriteOnlyArbiter_7/cmdRouteFork_translated_fifo/fifo/logic_ram_reg_0_3_0_0/DP/WADR0 ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9603, routed) 0.954 -0.354 axi4WriteOnlyArbiter_7/cmdRouteFork_translated_fifo/fifo/logic_ram_reg_0_3_0_0/WCLK SLICE_X40Y84 RAMD32 r axi4WriteOnlyArbiter_7/cmdRouteFork_translated_fifo/fifo/logic_ram_reg_0_3_0_0/DP/CLK clock pessimism -0.215 -0.569 SLICE_X40Y84 RAMD32 (Hold_ramd32_CLK_WADR0) 0.310 -0.259 axi4WriteOnlyArbiter_7/cmdRouteFork_translated_fifo/fifo/logic_ram_reg_0_3_0_0/DP ------------------------------------------------------------------- required time 0.259 arrival time -0.214 ------------------------------------------------------------------- slack 0.045 Slack (MET) : 0.045ns (arrival time - required time) Source: u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_7/cmdRouteFork_translated_fifo/fifo/logic_ptr_push_reg[0]/C (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: axi4WriteOnlyArbiter_7/cmdRouteFork_translated_fifo/fifo/logic_ram_reg_0_3_0_0/SP/WADR0 (rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: sys_clk Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) Data Path Delay: 0.368ns (logic 0.141ns (38.293%) route 0.227ns (61.707%)) Logic Levels: 0 Clock Path Skew: 0.013ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.354ns Source Clock Delay (SCD): -0.582ns Clock Pessimism Removal (CPR): 0.215ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9603, routed) 0.680 -0.582 u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_7/cmdRouteFork_translated_fifo/fifo/sys_clk SLICE_X41Y84 FDCE r u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_7/cmdRouteFork_translated_fifo/fifo/logic_ptr_push_reg[0]/C ------------------------------------------------------------------- ------------------- SLICE_X41Y84 FDCE (Prop_fdce_C_Q) 0.141 -0.441 r u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_7/cmdRouteFork_translated_fifo/fifo/logic_ptr_push_reg[0]/Q net (fo=8, routed) 0.227 -0.214 axi4WriteOnlyArbiter_7/cmdRouteFork_translated_fifo/fifo/logic_ram_reg_0_3_0_0/A0 SLICE_X40Y84 RAMD32 r axi4WriteOnlyArbiter_7/cmdRouteFork_translated_fifo/fifo/logic_ram_reg_0_3_0_0/SP/WADR0 ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9603, routed) 0.954 -0.354 axi4WriteOnlyArbiter_7/cmdRouteFork_translated_fifo/fifo/logic_ram_reg_0_3_0_0/WCLK SLICE_X40Y84 RAMD32 r axi4WriteOnlyArbiter_7/cmdRouteFork_translated_fifo/fifo/logic_ram_reg_0_3_0_0/SP/CLK clock pessimism -0.215 -0.569 SLICE_X40Y84 RAMD32 (Hold_ramd32_CLK_WADR0) 0.310 -0.259 axi4WriteOnlyArbiter_7/cmdRouteFork_translated_fifo/fifo/logic_ram_reg_0_3_0_0/SP ------------------------------------------------------------------- required time 0.259 arrival time -0.214 ------------------------------------------------------------------- slack 0.045 Slack (MET) : 0.054ns (arrival time - required time) Source: u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU2/DB1/buf_im_reg[127][12]__0/C (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU2/bf1_do_re_reg[12]/D (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: sys_clk Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) Data Path Delay: 0.412ns (logic 0.209ns (50.735%) route 0.203ns (49.265%)) Logic Levels: 1 (LUT6=1) Clock Path Skew: 0.266ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.403ns Source Clock Delay (SCD): -0.632ns Clock Pessimism Removal (CPR): -0.037ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9603, routed) 0.630 -0.632 u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU2/DB1/sys_clk SLICE_X84Y65 FDRE r u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU2/DB1/buf_im_reg[127][12]__0/C ------------------------------------------------------------------- ------------------- SLICE_X84Y65 FDRE (Prop_fdre_C_Q) 0.164 -0.468 r u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU2/DB1/buf_im_reg[127][12]__0/Q net (fo=6, routed) 0.203 -0.265 u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU2/DB1/buf_im_reg[127][14]__0_0[12] SLICE_X81Y62 LUT6 (Prop_lut6_I3_O) 0.045 -0.220 r u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU2/DB1/bf1_do_re[12]_i_1__1/O net (fo=1, routed) 0.000 -0.220 u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU2/bf1_sp_re[12] SLICE_X81Y62 FDRE r u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU2/bf1_do_re_reg[12]/D ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9603, routed) 0.905 -0.403 u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU2/sys_clk SLICE_X81Y62 FDRE r u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU2/bf1_do_re_reg[12]/C clock pessimism 0.037 -0.366 SLICE_X81Y62 FDRE (Hold_fdre_C_D) 0.092 -0.274 u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU2/bf1_do_re_reg[12] ------------------------------------------------------------------- required time 0.274 arrival time -0.220 ------------------------------------------------------------------- slack 0.054 Slack (MET) : 0.069ns (arrival time - required time) Source: u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdRouteFork_translated_fifo/fifo/logic_ptr_push_reg[1]/C (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: axi4WriteOnlyArbiter_4/cmdRouteFork_translated_fifo/fifo/logic_ram_reg_0_3_0_0/DP/WADR1 (rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: sys_clk Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) Data Path Delay: 0.391ns (logic 0.141ns (36.049%) route 0.250ns (63.951%)) Logic Levels: 0 Clock Path Skew: 0.013ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.323ns Source Clock Delay (SCD): -0.552ns Clock Pessimism Removal (CPR): 0.216ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9603, routed) 0.710 -0.552 u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdRouteFork_translated_fifo/fifo/sys_clk SLICE_X4Y73 FDCE r u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdRouteFork_translated_fifo/fifo/logic_ptr_push_reg[1]/C ------------------------------------------------------------------- ------------------- SLICE_X4Y73 FDCE (Prop_fdce_C_Q) 0.141 -0.411 r u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdRouteFork_translated_fifo/fifo/logic_ptr_push_reg[1]/Q net (fo=7, routed) 0.250 -0.161 axi4WriteOnlyArbiter_4/cmdRouteFork_translated_fifo/fifo/logic_ram_reg_0_3_0_0/A1 SLICE_X6Y73 RAMD32 r axi4WriteOnlyArbiter_4/cmdRouteFork_translated_fifo/fifo/logic_ram_reg_0_3_0_0/DP/WADR1 ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9603, routed) 0.985 -0.323 axi4WriteOnlyArbiter_4/cmdRouteFork_translated_fifo/fifo/logic_ram_reg_0_3_0_0/WCLK SLICE_X6Y73 RAMD32 r axi4WriteOnlyArbiter_4/cmdRouteFork_translated_fifo/fifo/logic_ram_reg_0_3_0_0/DP/CLK clock pessimism -0.216 -0.539 SLICE_X6Y73 RAMD32 (Hold_ramd32_CLK_WADR1) 0.309 -0.230 axi4WriteOnlyArbiter_4/cmdRouteFork_translated_fifo/fifo/logic_ram_reg_0_3_0_0/DP ------------------------------------------------------------------- required time 0.230 arrival time -0.161 ------------------------------------------------------------------- slack 0.069 Slack (MET) : 0.069ns (arrival time - required time) Source: u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdRouteFork_translated_fifo/fifo/logic_ptr_push_reg[1]/C (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: axi4WriteOnlyArbiter_4/cmdRouteFork_translated_fifo/fifo/logic_ram_reg_0_3_0_0/SP/WADR1 (rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: sys_clk Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) Data Path Delay: 0.391ns (logic 0.141ns (36.049%) route 0.250ns (63.951%)) Logic Levels: 0 Clock Path Skew: 0.013ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.323ns Source Clock Delay (SCD): -0.552ns Clock Pessimism Removal (CPR): 0.216ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9603, routed) 0.710 -0.552 u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdRouteFork_translated_fifo/fifo/sys_clk SLICE_X4Y73 FDCE r u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdRouteFork_translated_fifo/fifo/logic_ptr_push_reg[1]/C ------------------------------------------------------------------- ------------------- SLICE_X4Y73 FDCE (Prop_fdce_C_Q) 0.141 -0.411 r u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdRouteFork_translated_fifo/fifo/logic_ptr_push_reg[1]/Q net (fo=7, routed) 0.250 -0.161 axi4WriteOnlyArbiter_4/cmdRouteFork_translated_fifo/fifo/logic_ram_reg_0_3_0_0/A1 SLICE_X6Y73 RAMD32 r axi4WriteOnlyArbiter_4/cmdRouteFork_translated_fifo/fifo/logic_ram_reg_0_3_0_0/SP/WADR1 ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9603, routed) 0.985 -0.323 axi4WriteOnlyArbiter_4/cmdRouteFork_translated_fifo/fifo/logic_ram_reg_0_3_0_0/WCLK SLICE_X6Y73 RAMD32 r axi4WriteOnlyArbiter_4/cmdRouteFork_translated_fifo/fifo/logic_ram_reg_0_3_0_0/SP/CLK clock pessimism -0.216 -0.539 SLICE_X6Y73 RAMD32 (Hold_ramd32_CLK_WADR1) 0.309 -0.230 axi4WriteOnlyArbiter_4/cmdRouteFork_translated_fifo/fifo/logic_ram_reg_0_3_0_0/SP ------------------------------------------------------------------- required time 0.230 arrival time -0.161 ------------------------------------------------------------------- slack 0.069 Slack (MET) : 0.081ns (arrival time - required time) Source: u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/bf2_sp_en_reg/C (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/bf2_do_en_reg/D (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: sys_clk Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) Data Path Delay: 0.418ns (logic 0.141ns (33.715%) route 0.277ns (66.285%)) Logic Levels: 0 Clock Path Skew: 0.267ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.402ns Source Clock Delay (SCD): -0.632ns Clock Pessimism Removal (CPR): -0.037ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9603, routed) 0.630 -0.632 u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/sys_clk SLICE_X81Y64 FDCE r u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/bf2_sp_en_reg/C ------------------------------------------------------------------- ------------------- SLICE_X81Y64 FDCE (Prop_fdce_C_Q) 0.141 -0.491 r u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/bf2_sp_en_reg/Q net (fo=12, routed) 0.277 -0.214 u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/bf2_sp_en SLICE_X87Y61 FDCE r u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/bf2_do_en_reg/D ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9603, routed) 0.906 -0.402 u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/sys_clk SLICE_X87Y61 FDCE r u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/bf2_do_en_reg/C clock pessimism 0.037 -0.365 SLICE_X87Y61 FDCE (Hold_fdce_C_D) 0.070 -0.295 u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/bf2_do_en_reg ------------------------------------------------------------------- required time 0.295 arrival time -0.214 ------------------------------------------------------------------- slack 0.081 Slack (MET) : 0.084ns (arrival time - required time) Source: u_axi_uart_controller/uart0/regs/receiver/rf_data_in_reg[7]/C (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: u_axi_uart_controller/uart0/regs/receiver/fifo_rx/rfifo/ram_reg_0_15_0_5/RAMC/I (rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: sys_clk Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) Data Path Delay: 0.187ns (logic 0.128ns (68.397%) route 0.059ns (31.603%)) Logic Levels: 0 Clock Path Skew: 0.013ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.380ns Source Clock Delay (SCD): -0.609ns Clock Pessimism Removal (CPR): 0.216ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9603, routed) 0.653 -0.609 u_axi_uart_controller/uart0/regs/receiver/sys_clk SLICE_X43Y59 FDRE r u_axi_uart_controller/uart0/regs/receiver/rf_data_in_reg[7]/C ------------------------------------------------------------------- ------------------- SLICE_X43Y59 FDRE (Prop_fdre_C_Q) 0.128 -0.481 r u_axi_uart_controller/uart0/regs/receiver/rf_data_in_reg[7]/Q net (fo=1, routed) 0.059 -0.422 u_axi_uart_controller/uart0/regs/receiver/fifo_rx/rfifo/ram_reg_0_15_0_5/DIC0 SLICE_X42Y59 RAMD32 r u_axi_uart_controller/uart0/regs/receiver/fifo_rx/rfifo/ram_reg_0_15_0_5/RAMC/I ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9603, routed) 0.928 -0.380 u_axi_uart_controller/uart0/regs/receiver/fifo_rx/rfifo/ram_reg_0_15_0_5/WCLK SLICE_X42Y59 RAMD32 r u_axi_uart_controller/uart0/regs/receiver/fifo_rx/rfifo/ram_reg_0_15_0_5/RAMC/CLK clock pessimism -0.216 -0.596 SLICE_X42Y59 RAMD32 (Hold_ramd32_CLK_I) 0.090 -0.506 u_axi_uart_controller/uart0/regs/receiver/fifo_rx/rfifo/ram_reg_0_15_0_5/RAMC ------------------------------------------------------------------- required time 0.506 arrival time -0.422 ------------------------------------------------------------------- slack 0.084 Slack (MET) : 0.094ns (arrival time - required time) Source: u_axi_uart_controller/uart0/regs/receiver/rf_data_in_reg[9]/C (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: u_axi_uart_controller/uart0/regs/receiver/fifo_rx/rfifo/ram_reg_0_15_6_7/RAMA/I (rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: sys_clk Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) Data Path Delay: 0.254ns (logic 0.141ns (55.511%) route 0.113ns (44.489%)) Logic Levels: 0 Clock Path Skew: 0.013ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.380ns Source Clock Delay (SCD): -0.609ns Clock Pessimism Removal (CPR): 0.216ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9603, routed) 0.653 -0.609 u_axi_uart_controller/uart0/regs/receiver/sys_clk SLICE_X45Y59 FDRE r u_axi_uart_controller/uart0/regs/receiver/rf_data_in_reg[9]/C ------------------------------------------------------------------- ------------------- SLICE_X45Y59 FDRE (Prop_fdre_C_Q) 0.141 -0.468 r u_axi_uart_controller/uart0/regs/receiver/rf_data_in_reg[9]/Q net (fo=1, routed) 0.113 -0.355 u_axi_uart_controller/uart0/regs/receiver/fifo_rx/rfifo/ram_reg_0_15_6_7/DIA0 SLICE_X44Y59 RAMD32 r u_axi_uart_controller/uart0/regs/receiver/fifo_rx/rfifo/ram_reg_0_15_6_7/RAMA/I ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9603, routed) 0.928 -0.380 u_axi_uart_controller/uart0/regs/receiver/fifo_rx/rfifo/ram_reg_0_15_6_7/WCLK SLICE_X44Y59 RAMD32 r u_axi_uart_controller/uart0/regs/receiver/fifo_rx/rfifo/ram_reg_0_15_6_7/RAMA/CLK clock pessimism -0.216 -0.596 SLICE_X44Y59 RAMD32 (Hold_ramd32_CLK_I) 0.147 -0.449 u_axi_uart_controller/uart0/regs/receiver/fifo_rx/rfifo/ram_reg_0_15_6_7/RAMA ------------------------------------------------------------------- required time 0.449 arrival time -0.355 ------------------------------------------------------------------- slack 0.094 Slack (MET) : 0.094ns (arrival time - required time) Source: u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_6/cmdRouteFork_translated_fifo/fifo/logic_ptr_push_reg[1]/C (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: axi4WriteOnlyArbiter_6/cmdRouteFork_translated_fifo/fifo/logic_ram_reg_0_3_0_0/DP/WADR1 (rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: sys_clk Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) Data Path Delay: 0.417ns (logic 0.141ns (33.777%) route 0.276ns (66.223%)) Logic Levels: 0 Clock Path Skew: 0.014ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.385ns Source Clock Delay (SCD): -0.612ns Clock Pessimism Removal (CPR): 0.213ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9603, routed) 0.650 -0.612 u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_6/cmdRouteFork_translated_fifo/fifo/sys_clk SLICE_X43Y85 FDCE r u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_6/cmdRouteFork_translated_fifo/fifo/logic_ptr_push_reg[1]/C ------------------------------------------------------------------- ------------------- SLICE_X43Y85 FDCE (Prop_fdce_C_Q) 0.141 -0.471 r u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_6/cmdRouteFork_translated_fifo/fifo/logic_ptr_push_reg[1]/Q net (fo=7, routed) 0.276 -0.195 axi4WriteOnlyArbiter_6/cmdRouteFork_translated_fifo/fifo/logic_ram_reg_0_3_0_0/A1 SLICE_X42Y84 RAMD32 r axi4WriteOnlyArbiter_6/cmdRouteFork_translated_fifo/fifo/logic_ram_reg_0_3_0_0/DP/WADR1 ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9603, routed) 0.923 -0.385 axi4WriteOnlyArbiter_6/cmdRouteFork_translated_fifo/fifo/logic_ram_reg_0_3_0_0/WCLK SLICE_X42Y84 RAMD32 r axi4WriteOnlyArbiter_6/cmdRouteFork_translated_fifo/fifo/logic_ram_reg_0_3_0_0/DP/CLK clock pessimism -0.213 -0.598 SLICE_X42Y84 RAMD32 (Hold_ramd32_CLK_WADR1) 0.309 -0.289 axi4WriteOnlyArbiter_6/cmdRouteFork_translated_fifo/fifo/logic_ram_reg_0_3_0_0/DP ------------------------------------------------------------------- required time 0.289 arrival time -0.195 ------------------------------------------------------------------- slack 0.094 Slack (MET) : 0.094ns (arrival time - required time) Source: u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_6/cmdRouteFork_translated_fifo/fifo/logic_ptr_push_reg[1]/C (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: axi4WriteOnlyArbiter_6/cmdRouteFork_translated_fifo/fifo/logic_ram_reg_0_3_0_0/SP/WADR1 (rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: sys_clk Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) Data Path Delay: 0.417ns (logic 0.141ns (33.777%) route 0.276ns (66.223%)) Logic Levels: 0 Clock Path Skew: 0.014ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.385ns Source Clock Delay (SCD): -0.612ns Clock Pessimism Removal (CPR): 0.213ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9603, routed) 0.650 -0.612 u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_6/cmdRouteFork_translated_fifo/fifo/sys_clk SLICE_X43Y85 FDCE r u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_6/cmdRouteFork_translated_fifo/fifo/logic_ptr_push_reg[1]/C ------------------------------------------------------------------- ------------------- SLICE_X43Y85 FDCE (Prop_fdce_C_Q) 0.141 -0.471 r u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_6/cmdRouteFork_translated_fifo/fifo/logic_ptr_push_reg[1]/Q net (fo=7, routed) 0.276 -0.195 axi4WriteOnlyArbiter_6/cmdRouteFork_translated_fifo/fifo/logic_ram_reg_0_3_0_0/A1 SLICE_X42Y84 RAMD32 r axi4WriteOnlyArbiter_6/cmdRouteFork_translated_fifo/fifo/logic_ram_reg_0_3_0_0/SP/WADR1 ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9603, routed) 0.923 -0.385 axi4WriteOnlyArbiter_6/cmdRouteFork_translated_fifo/fifo/logic_ram_reg_0_3_0_0/WCLK SLICE_X42Y84 RAMD32 r axi4WriteOnlyArbiter_6/cmdRouteFork_translated_fifo/fifo/logic_ram_reg_0_3_0_0/SP/CLK clock pessimism -0.213 -0.598 SLICE_X42Y84 RAMD32 (Hold_ramd32_CLK_WADR1) 0.309 -0.289 axi4WriteOnlyArbiter_6/cmdRouteFork_translated_fifo/fifo/logic_ram_reg_0_3_0_0/SP ------------------------------------------------------------------- required time 0.289 arrival time -0.195 ------------------------------------------------------------------- slack 0.094 Slack (MET) : 0.096ns (arrival time - required time) Source: u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_7/cmdRouteFork_translated_fifo/fifo/logic_ptr_push_reg[1]/C (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: axi4WriteOnlyArbiter_7/cmdRouteFork_translated_fifo/fifo/logic_ram_reg_0_3_0_0/DP/WADR1 (rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: sys_clk Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) Data Path Delay: 0.364ns (logic 0.128ns (35.129%) route 0.236ns (64.871%)) Logic Levels: 0 Clock Path Skew: 0.013ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.354ns Source Clock Delay (SCD): -0.582ns Clock Pessimism Removal (CPR): 0.215ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9603, routed) 0.680 -0.582 u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_7/cmdRouteFork_translated_fifo/fifo/sys_clk SLICE_X41Y84 FDCE r u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_7/cmdRouteFork_translated_fifo/fifo/logic_ptr_push_reg[1]/C ------------------------------------------------------------------- ------------------- SLICE_X41Y84 FDCE (Prop_fdce_C_Q) 0.128 -0.454 r u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_7/cmdRouteFork_translated_fifo/fifo/logic_ptr_push_reg[1]/Q net (fo=7, routed) 0.236 -0.218 axi4WriteOnlyArbiter_7/cmdRouteFork_translated_fifo/fifo/logic_ram_reg_0_3_0_0/A1 SLICE_X40Y84 RAMD32 r axi4WriteOnlyArbiter_7/cmdRouteFork_translated_fifo/fifo/logic_ram_reg_0_3_0_0/DP/WADR1 ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9603, routed) 0.954 -0.354 axi4WriteOnlyArbiter_7/cmdRouteFork_translated_fifo/fifo/logic_ram_reg_0_3_0_0/WCLK SLICE_X40Y84 RAMD32 r axi4WriteOnlyArbiter_7/cmdRouteFork_translated_fifo/fifo/logic_ram_reg_0_3_0_0/DP/CLK clock pessimism -0.215 -0.569 SLICE_X40Y84 RAMD32 (Hold_ramd32_CLK_WADR1) 0.255 -0.314 axi4WriteOnlyArbiter_7/cmdRouteFork_translated_fifo/fifo/logic_ram_reg_0_3_0_0/DP ------------------------------------------------------------------- required time 0.314 arrival time -0.218 ------------------------------------------------------------------- slack 0.096 Slack (MET) : 0.096ns (arrival time - required time) Source: u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_7/cmdRouteFork_translated_fifo/fifo/logic_ptr_push_reg[1]/C (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: axi4WriteOnlyArbiter_7/cmdRouteFork_translated_fifo/fifo/logic_ram_reg_0_3_0_0/SP/WADR1 (rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: sys_clk Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) Data Path Delay: 0.364ns (logic 0.128ns (35.129%) route 0.236ns (64.871%)) Logic Levels: 0 Clock Path Skew: 0.013ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.354ns Source Clock Delay (SCD): -0.582ns Clock Pessimism Removal (CPR): 0.215ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9603, routed) 0.680 -0.582 u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_7/cmdRouteFork_translated_fifo/fifo/sys_clk SLICE_X41Y84 FDCE r u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_7/cmdRouteFork_translated_fifo/fifo/logic_ptr_push_reg[1]/C ------------------------------------------------------------------- ------------------- SLICE_X41Y84 FDCE (Prop_fdce_C_Q) 0.128 -0.454 r u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_7/cmdRouteFork_translated_fifo/fifo/logic_ptr_push_reg[1]/Q net (fo=7, routed) 0.236 -0.218 axi4WriteOnlyArbiter_7/cmdRouteFork_translated_fifo/fifo/logic_ram_reg_0_3_0_0/A1 SLICE_X40Y84 RAMD32 r axi4WriteOnlyArbiter_7/cmdRouteFork_translated_fifo/fifo/logic_ram_reg_0_3_0_0/SP/WADR1 ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9603, routed) 0.954 -0.354 axi4WriteOnlyArbiter_7/cmdRouteFork_translated_fifo/fifo/logic_ram_reg_0_3_0_0/WCLK SLICE_X40Y84 RAMD32 r axi4WriteOnlyArbiter_7/cmdRouteFork_translated_fifo/fifo/logic_ram_reg_0_3_0_0/SP/CLK clock pessimism -0.215 -0.569 SLICE_X40Y84 RAMD32 (Hold_ramd32_CLK_WADR1) 0.255 -0.314 axi4WriteOnlyArbiter_7/cmdRouteFork_translated_fifo/fifo/logic_ram_reg_0_3_0_0/SP ------------------------------------------------------------------- required time 0.314 arrival time -0.218 ------------------------------------------------------------------- slack 0.096 Slack (MET) : 0.101ns (arrival time - required time) Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/pushCC_pushPtr_reg[0]/C (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_0_5/RAMA/WADR0 (rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: sys_clk Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) Data Path Delay: 0.424ns (logic 0.141ns (33.251%) route 0.283ns (66.749%)) Logic Levels: 0 Clock Path Skew: 0.013ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.388ns Source Clock Delay (SCD): -0.614ns Clock Pessimism Removal (CPR): 0.213ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9603, routed) 0.648 -0.614 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/sys_clk SLICE_X49Y82 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/pushCC_pushPtr_reg[0]/C ------------------------------------------------------------------- ------------------- SLICE_X49Y82 FDCE (Prop_fdce_C_Q) 0.141 -0.473 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/pushCC_pushPtr_reg[0]/Q net (fo=60, routed) 0.283 -0.190 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_0_5/ADDRD0 SLICE_X48Y82 RAMD32 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_0_5/RAMA/WADR0 ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9603, routed) 0.920 -0.388 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_0_5/WCLK SLICE_X48Y82 RAMD32 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_0_5/RAMA/CLK clock pessimism -0.213 -0.601 SLICE_X48Y82 RAMD32 (Hold_ramd32_CLK_WADR0) 0.310 -0.291 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_0_5/RAMA ------------------------------------------------------------------- required time 0.291 arrival time -0.190 ------------------------------------------------------------------- slack 0.101 Slack (MET) : 0.101ns (arrival time - required time) Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/pushCC_pushPtr_reg[0]/C (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_0_5/RAMA_D1/WADR0 (rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: sys_clk Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) Data Path Delay: 0.424ns (logic 0.141ns (33.251%) route 0.283ns (66.749%)) Logic Levels: 0 Clock Path Skew: 0.013ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.388ns Source Clock Delay (SCD): -0.614ns Clock Pessimism Removal (CPR): 0.213ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9603, routed) 0.648 -0.614 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/sys_clk SLICE_X49Y82 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/pushCC_pushPtr_reg[0]/C ------------------------------------------------------------------- ------------------- SLICE_X49Y82 FDCE (Prop_fdce_C_Q) 0.141 -0.473 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/pushCC_pushPtr_reg[0]/Q net (fo=60, routed) 0.283 -0.190 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_0_5/ADDRD0 SLICE_X48Y82 RAMD32 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_0_5/RAMA_D1/WADR0 ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9603, routed) 0.920 -0.388 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_0_5/WCLK SLICE_X48Y82 RAMD32 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_0_5/RAMA_D1/CLK clock pessimism -0.213 -0.601 SLICE_X48Y82 RAMD32 (Hold_ramd32_CLK_WADR0) 0.310 -0.291 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_0_5/RAMA_D1 ------------------------------------------------------------------- required time 0.291 arrival time -0.190 ------------------------------------------------------------------- slack 0.101 Slack (MET) : 0.101ns (arrival time - required time) Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/pushCC_pushPtr_reg[0]/C (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_0_5/RAMB/WADR0 (rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: sys_clk Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) Data Path Delay: 0.424ns (logic 0.141ns (33.251%) route 0.283ns (66.749%)) Logic Levels: 0 Clock Path Skew: 0.013ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.388ns Source Clock Delay (SCD): -0.614ns Clock Pessimism Removal (CPR): 0.213ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9603, routed) 0.648 -0.614 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/sys_clk SLICE_X49Y82 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/pushCC_pushPtr_reg[0]/C ------------------------------------------------------------------- ------------------- SLICE_X49Y82 FDCE (Prop_fdce_C_Q) 0.141 -0.473 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/pushCC_pushPtr_reg[0]/Q net (fo=60, routed) 0.283 -0.190 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_0_5/ADDRD0 SLICE_X48Y82 RAMD32 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_0_5/RAMB/WADR0 ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9603, routed) 0.920 -0.388 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_0_5/WCLK SLICE_X48Y82 RAMD32 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_0_5/RAMB/CLK clock pessimism -0.213 -0.601 SLICE_X48Y82 RAMD32 (Hold_ramd32_CLK_WADR0) 0.310 -0.291 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_0_5/RAMB ------------------------------------------------------------------- required time 0.291 arrival time -0.190 ------------------------------------------------------------------- slack 0.101 Slack (MET) : 0.101ns (arrival time - required time) Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/pushCC_pushPtr_reg[0]/C (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_0_5/RAMB_D1/WADR0 (rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: sys_clk Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) Data Path Delay: 0.424ns (logic 0.141ns (33.251%) route 0.283ns (66.749%)) Logic Levels: 0 Clock Path Skew: 0.013ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.388ns Source Clock Delay (SCD): -0.614ns Clock Pessimism Removal (CPR): 0.213ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9603, routed) 0.648 -0.614 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/sys_clk SLICE_X49Y82 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/pushCC_pushPtr_reg[0]/C ------------------------------------------------------------------- ------------------- SLICE_X49Y82 FDCE (Prop_fdce_C_Q) 0.141 -0.473 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/pushCC_pushPtr_reg[0]/Q net (fo=60, routed) 0.283 -0.190 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_0_5/ADDRD0 SLICE_X48Y82 RAMD32 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_0_5/RAMB_D1/WADR0 ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9603, routed) 0.920 -0.388 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_0_5/WCLK SLICE_X48Y82 RAMD32 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_0_5/RAMB_D1/CLK clock pessimism -0.213 -0.601 SLICE_X48Y82 RAMD32 (Hold_ramd32_CLK_WADR0) 0.310 -0.291 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_0_5/RAMB_D1 ------------------------------------------------------------------- required time 0.291 arrival time -0.190 ------------------------------------------------------------------- slack 0.101 Slack (MET) : 0.101ns (arrival time - required time) Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/pushCC_pushPtr_reg[0]/C (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_0_5/RAMC/WADR0 (rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: sys_clk Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) Data Path Delay: 0.424ns (logic 0.141ns (33.251%) route 0.283ns (66.749%)) Logic Levels: 0 Clock Path Skew: 0.013ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.388ns Source Clock Delay (SCD): -0.614ns Clock Pessimism Removal (CPR): 0.213ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9603, routed) 0.648 -0.614 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/sys_clk SLICE_X49Y82 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/pushCC_pushPtr_reg[0]/C ------------------------------------------------------------------- ------------------- SLICE_X49Y82 FDCE (Prop_fdce_C_Q) 0.141 -0.473 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/pushCC_pushPtr_reg[0]/Q net (fo=60, routed) 0.283 -0.190 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_0_5/ADDRD0 SLICE_X48Y82 RAMD32 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_0_5/RAMC/WADR0 ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9603, routed) 0.920 -0.388 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_0_5/WCLK SLICE_X48Y82 RAMD32 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_0_5/RAMC/CLK clock pessimism -0.213 -0.601 SLICE_X48Y82 RAMD32 (Hold_ramd32_CLK_WADR0) 0.310 -0.291 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_0_5/RAMC ------------------------------------------------------------------- required time 0.291 arrival time -0.190 ------------------------------------------------------------------- slack 0.101 Slack (MET) : 0.101ns (arrival time - required time) Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/pushCC_pushPtr_reg[0]/C (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_0_5/RAMC_D1/WADR0 (rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: sys_clk Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) Data Path Delay: 0.424ns (logic 0.141ns (33.251%) route 0.283ns (66.749%)) Logic Levels: 0 Clock Path Skew: 0.013ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.388ns Source Clock Delay (SCD): -0.614ns Clock Pessimism Removal (CPR): 0.213ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9603, routed) 0.648 -0.614 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/sys_clk SLICE_X49Y82 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/pushCC_pushPtr_reg[0]/C ------------------------------------------------------------------- ------------------- SLICE_X49Y82 FDCE (Prop_fdce_C_Q) 0.141 -0.473 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/pushCC_pushPtr_reg[0]/Q net (fo=60, routed) 0.283 -0.190 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_0_5/ADDRD0 SLICE_X48Y82 RAMD32 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_0_5/RAMC_D1/WADR0 ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9603, routed) 0.920 -0.388 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_0_5/WCLK SLICE_X48Y82 RAMD32 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_0_5/RAMC_D1/CLK clock pessimism -0.213 -0.601 SLICE_X48Y82 RAMD32 (Hold_ramd32_CLK_WADR0) 0.310 -0.291 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_0_5/RAMC_D1 ------------------------------------------------------------------- required time 0.291 arrival time -0.190 ------------------------------------------------------------------- slack 0.101 Slack (MET) : 0.101ns (arrival time - required time) Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/pushCC_pushPtr_reg[0]/C (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_0_5/RAMD/ADR0 (rising edge-triggered cell RAMS32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: sys_clk Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) Data Path Delay: 0.424ns (logic 0.141ns (33.251%) route 0.283ns (66.749%)) Logic Levels: 0 Clock Path Skew: 0.013ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.388ns Source Clock Delay (SCD): -0.614ns Clock Pessimism Removal (CPR): 0.213ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9603, routed) 0.648 -0.614 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/sys_clk SLICE_X49Y82 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/pushCC_pushPtr_reg[0]/C ------------------------------------------------------------------- ------------------- SLICE_X49Y82 FDCE (Prop_fdce_C_Q) 0.141 -0.473 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/pushCC_pushPtr_reg[0]/Q net (fo=60, routed) 0.283 -0.190 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_0_5/ADDRD0 SLICE_X48Y82 RAMS32 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_0_5/RAMD/ADR0 ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9603, routed) 0.920 -0.388 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_0_5/WCLK SLICE_X48Y82 RAMS32 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_0_5/RAMD/CLK clock pessimism -0.213 -0.601 SLICE_X48Y82 RAMS32 (Hold_rams32_CLK_ADR0) 0.310 -0.291 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_0_5/RAMD ------------------------------------------------------------------- required time 0.291 arrival time -0.190 ------------------------------------------------------------------- slack 0.101 Slack (MET) : 0.101ns (arrival time - required time) Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/pushCC_pushPtr_reg[0]/C (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_0_5/RAMD_D1/ADR0 (rising edge-triggered cell RAMS32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: sys_clk Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) Data Path Delay: 0.424ns (logic 0.141ns (33.251%) route 0.283ns (66.749%)) Logic Levels: 0 Clock Path Skew: 0.013ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.388ns Source Clock Delay (SCD): -0.614ns Clock Pessimism Removal (CPR): 0.213ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9603, routed) 0.648 -0.614 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/sys_clk SLICE_X49Y82 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/pushCC_pushPtr_reg[0]/C ------------------------------------------------------------------- ------------------- SLICE_X49Y82 FDCE (Prop_fdce_C_Q) 0.141 -0.473 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/pushCC_pushPtr_reg[0]/Q net (fo=60, routed) 0.283 -0.190 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_0_5/ADDRD0 SLICE_X48Y82 RAMS32 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_0_5/RAMD_D1/ADR0 ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9603, routed) 0.920 -0.388 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_0_5/WCLK SLICE_X48Y82 RAMS32 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_0_5/RAMD_D1/CLK clock pessimism -0.213 -0.601 SLICE_X48Y82 RAMS32 (Hold_rams32_CLK_ADR0) 0.310 -0.291 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_0_5/RAMD_D1 ------------------------------------------------------------------- required time 0.291 arrival time -0.190 ------------------------------------------------------------------- slack 0.101 Slack (MET) : 0.104ns (arrival time - required time) Source: u_cdma_matmul_bridge/bank_dst_addr_reg[0][9]/C (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: u_cdma_matmul_bridge/cdma_wr_req_dst_reg[9]/D (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: sys_clk Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) Data Path Delay: 0.238ns (logic 0.186ns (78.117%) route 0.052ns (21.883%)) Logic Levels: 1 (LUT6=1) Clock Path Skew: 0.013ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.385ns Source Clock Delay (SCD): -0.612ns Clock Pessimism Removal (CPR): 0.214ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9603, routed) 0.650 -0.612 u_cdma_matmul_bridge/sys_clk SLICE_X49Y85 FDRE r u_cdma_matmul_bridge/bank_dst_addr_reg[0][9]/C ------------------------------------------------------------------- ------------------- SLICE_X49Y85 FDRE (Prop_fdre_C_Q) 0.141 -0.471 r u_cdma_matmul_bridge/bank_dst_addr_reg[0][9]/Q net (fo=1, routed) 0.052 -0.419 u_cdma_matmul_bridge/bank_dst_addr_reg[0]_3[9] SLICE_X48Y85 LUT6 (Prop_lut6_I5_O) 0.045 -0.374 r u_cdma_matmul_bridge/cdma_wr_req_dst[9]_i_1/O net (fo=1, routed) 0.000 -0.374 u_cdma_matmul_bridge/cdma_wr_req_dst[9]_i_1_n_0 SLICE_X48Y85 FDRE r u_cdma_matmul_bridge/cdma_wr_req_dst_reg[9]/D ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9603, routed) 0.923 -0.385 u_cdma_matmul_bridge/sys_clk SLICE_X48Y85 FDRE r u_cdma_matmul_bridge/cdma_wr_req_dst_reg[9]/C clock pessimism -0.214 -0.599 SLICE_X48Y85 FDRE (Hold_fdre_C_D) 0.121 -0.478 u_cdma_matmul_bridge/cdma_wr_req_dst_reg[9] ------------------------------------------------------------------- required time 0.478 arrival time -0.374 ------------------------------------------------------------------- slack 0.104 Slack (MET) : 0.105ns (arrival time - required time) Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/pushCC_pushPtr_reg[0]/C (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_6_11/RAMA/WADR0 (rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: sys_clk Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) Data Path Delay: 0.430ns (logic 0.141ns (32.783%) route 0.289ns (67.217%)) Logic Levels: 0 Clock Path Skew: 0.015ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.387ns Source Clock Delay (SCD): -0.614ns Clock Pessimism Removal (CPR): 0.212ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9603, routed) 0.648 -0.614 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/sys_clk SLICE_X49Y82 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/pushCC_pushPtr_reg[0]/C ------------------------------------------------------------------- ------------------- SLICE_X49Y82 FDCE (Prop_fdce_C_Q) 0.141 -0.473 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/pushCC_pushPtr_reg[0]/Q net (fo=60, routed) 0.289 -0.184 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_6_11/ADDRD0 SLICE_X48Y83 RAMD32 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_6_11/RAMA/WADR0 ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9603, routed) 0.921 -0.387 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_6_11/WCLK SLICE_X48Y83 RAMD32 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_6_11/RAMA/CLK clock pessimism -0.212 -0.599 SLICE_X48Y83 RAMD32 (Hold_ramd32_CLK_WADR0) 0.310 -0.289 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_6_11/RAMA ------------------------------------------------------------------- required time 0.289 arrival time -0.184 ------------------------------------------------------------------- slack 0.105 Slack (MET) : 0.105ns (arrival time - required time) Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/pushCC_pushPtr_reg[0]/C (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_6_11/RAMA_D1/WADR0 (rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: sys_clk Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) Data Path Delay: 0.430ns (logic 0.141ns (32.783%) route 0.289ns (67.217%)) Logic Levels: 0 Clock Path Skew: 0.015ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.387ns Source Clock Delay (SCD): -0.614ns Clock Pessimism Removal (CPR): 0.212ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9603, routed) 0.648 -0.614 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/sys_clk SLICE_X49Y82 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/pushCC_pushPtr_reg[0]/C ------------------------------------------------------------------- ------------------- SLICE_X49Y82 FDCE (Prop_fdce_C_Q) 0.141 -0.473 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/pushCC_pushPtr_reg[0]/Q net (fo=60, routed) 0.289 -0.184 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_6_11/ADDRD0 SLICE_X48Y83 RAMD32 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_6_11/RAMA_D1/WADR0 ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9603, routed) 0.921 -0.387 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_6_11/WCLK SLICE_X48Y83 RAMD32 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_6_11/RAMA_D1/CLK clock pessimism -0.212 -0.599 SLICE_X48Y83 RAMD32 (Hold_ramd32_CLK_WADR0) 0.310 -0.289 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_6_11/RAMA_D1 ------------------------------------------------------------------- required time 0.289 arrival time -0.184 ------------------------------------------------------------------- slack 0.105 Slack (MET) : 0.105ns (arrival time - required time) Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/pushCC_pushPtr_reg[0]/C (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_6_11/RAMB/WADR0 (rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: sys_clk Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) Data Path Delay: 0.430ns (logic 0.141ns (32.783%) route 0.289ns (67.217%)) Logic Levels: 0 Clock Path Skew: 0.015ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.387ns Source Clock Delay (SCD): -0.614ns Clock Pessimism Removal (CPR): 0.212ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9603, routed) 0.648 -0.614 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/sys_clk SLICE_X49Y82 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/pushCC_pushPtr_reg[0]/C ------------------------------------------------------------------- ------------------- SLICE_X49Y82 FDCE (Prop_fdce_C_Q) 0.141 -0.473 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/pushCC_pushPtr_reg[0]/Q net (fo=60, routed) 0.289 -0.184 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_6_11/ADDRD0 SLICE_X48Y83 RAMD32 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_6_11/RAMB/WADR0 ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9603, routed) 0.921 -0.387 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_6_11/WCLK SLICE_X48Y83 RAMD32 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_6_11/RAMB/CLK clock pessimism -0.212 -0.599 SLICE_X48Y83 RAMD32 (Hold_ramd32_CLK_WADR0) 0.310 -0.289 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_6_11/RAMB ------------------------------------------------------------------- required time 0.289 arrival time -0.184 ------------------------------------------------------------------- slack 0.105 Slack (MET) : 0.105ns (arrival time - required time) Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/pushCC_pushPtr_reg[0]/C (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_6_11/RAMB_D1/WADR0 (rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: sys_clk Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) Data Path Delay: 0.430ns (logic 0.141ns (32.783%) route 0.289ns (67.217%)) Logic Levels: 0 Clock Path Skew: 0.015ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.387ns Source Clock Delay (SCD): -0.614ns Clock Pessimism Removal (CPR): 0.212ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9603, routed) 0.648 -0.614 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/sys_clk SLICE_X49Y82 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/pushCC_pushPtr_reg[0]/C ------------------------------------------------------------------- ------------------- SLICE_X49Y82 FDCE (Prop_fdce_C_Q) 0.141 -0.473 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/pushCC_pushPtr_reg[0]/Q net (fo=60, routed) 0.289 -0.184 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_6_11/ADDRD0 SLICE_X48Y83 RAMD32 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_6_11/RAMB_D1/WADR0 ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9603, routed) 0.921 -0.387 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_6_11/WCLK SLICE_X48Y83 RAMD32 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_6_11/RAMB_D1/CLK clock pessimism -0.212 -0.599 SLICE_X48Y83 RAMD32 (Hold_ramd32_CLK_WADR0) 0.310 -0.289 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_6_11/RAMB_D1 ------------------------------------------------------------------- required time 0.289 arrival time -0.184 ------------------------------------------------------------------- slack 0.105 Slack (MET) : 0.105ns (arrival time - required time) Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/pushCC_pushPtr_reg[0]/C (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_6_11/RAMC/WADR0 (rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: sys_clk Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) Data Path Delay: 0.430ns (logic 0.141ns (32.783%) route 0.289ns (67.217%)) Logic Levels: 0 Clock Path Skew: 0.015ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.387ns Source Clock Delay (SCD): -0.614ns Clock Pessimism Removal (CPR): 0.212ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9603, routed) 0.648 -0.614 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/sys_clk SLICE_X49Y82 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/pushCC_pushPtr_reg[0]/C ------------------------------------------------------------------- ------------------- SLICE_X49Y82 FDCE (Prop_fdce_C_Q) 0.141 -0.473 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/pushCC_pushPtr_reg[0]/Q net (fo=60, routed) 0.289 -0.184 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_6_11/ADDRD0 SLICE_X48Y83 RAMD32 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_6_11/RAMC/WADR0 ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9603, routed) 0.921 -0.387 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_6_11/WCLK SLICE_X48Y83 RAMD32 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_6_11/RAMC/CLK clock pessimism -0.212 -0.599 SLICE_X48Y83 RAMD32 (Hold_ramd32_CLK_WADR0) 0.310 -0.289 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_6_11/RAMC ------------------------------------------------------------------- required time 0.289 arrival time -0.184 ------------------------------------------------------------------- slack 0.105 Slack (MET) : 0.105ns (arrival time - required time) Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/pushCC_pushPtr_reg[0]/C (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_6_11/RAMC_D1/WADR0 (rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: sys_clk Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) Data Path Delay: 0.430ns (logic 0.141ns (32.783%) route 0.289ns (67.217%)) Logic Levels: 0 Clock Path Skew: 0.015ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.387ns Source Clock Delay (SCD): -0.614ns Clock Pessimism Removal (CPR): 0.212ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9603, routed) 0.648 -0.614 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/sys_clk SLICE_X49Y82 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/pushCC_pushPtr_reg[0]/C ------------------------------------------------------------------- ------------------- SLICE_X49Y82 FDCE (Prop_fdce_C_Q) 0.141 -0.473 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/pushCC_pushPtr_reg[0]/Q net (fo=60, routed) 0.289 -0.184 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_6_11/ADDRD0 SLICE_X48Y83 RAMD32 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_6_11/RAMC_D1/WADR0 ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9603, routed) 0.921 -0.387 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_6_11/WCLK SLICE_X48Y83 RAMD32 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_6_11/RAMC_D1/CLK clock pessimism -0.212 -0.599 SLICE_X48Y83 RAMD32 (Hold_ramd32_CLK_WADR0) 0.310 -0.289 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_6_11/RAMC_D1 ------------------------------------------------------------------- required time 0.289 arrival time -0.184 ------------------------------------------------------------------- slack 0.105 Slack (MET) : 0.105ns (arrival time - required time) Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/pushCC_pushPtr_reg[0]/C (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_6_11/RAMD/ADR0 (rising edge-triggered cell RAMS32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: sys_clk Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) Data Path Delay: 0.430ns (logic 0.141ns (32.783%) route 0.289ns (67.217%)) Logic Levels: 0 Clock Path Skew: 0.015ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.387ns Source Clock Delay (SCD): -0.614ns Clock Pessimism Removal (CPR): 0.212ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9603, routed) 0.648 -0.614 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/sys_clk SLICE_X49Y82 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/pushCC_pushPtr_reg[0]/C ------------------------------------------------------------------- ------------------- SLICE_X49Y82 FDCE (Prop_fdce_C_Q) 0.141 -0.473 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/pushCC_pushPtr_reg[0]/Q net (fo=60, routed) 0.289 -0.184 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_6_11/ADDRD0 SLICE_X48Y83 RAMS32 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_6_11/RAMD/ADR0 ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9603, routed) 0.921 -0.387 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_6_11/WCLK SLICE_X48Y83 RAMS32 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_6_11/RAMD/CLK clock pessimism -0.212 -0.599 SLICE_X48Y83 RAMS32 (Hold_rams32_CLK_ADR0) 0.310 -0.289 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_6_11/RAMD ------------------------------------------------------------------- required time 0.289 arrival time -0.184 ------------------------------------------------------------------- slack 0.105 Slack (MET) : 0.105ns (arrival time - required time) Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/pushCC_pushPtr_reg[0]/C (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_6_11/RAMD_D1/ADR0 (rising edge-triggered cell RAMS32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: sys_clk Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) Data Path Delay: 0.430ns (logic 0.141ns (32.783%) route 0.289ns (67.217%)) Logic Levels: 0 Clock Path Skew: 0.015ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.387ns Source Clock Delay (SCD): -0.614ns Clock Pessimism Removal (CPR): 0.212ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9603, routed) 0.648 -0.614 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/sys_clk SLICE_X49Y82 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/pushCC_pushPtr_reg[0]/C ------------------------------------------------------------------- ------------------- SLICE_X49Y82 FDCE (Prop_fdce_C_Q) 0.141 -0.473 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/pushCC_pushPtr_reg[0]/Q net (fo=60, routed) 0.289 -0.184 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_6_11/ADDRD0 SLICE_X48Y83 RAMS32 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_6_11/RAMD_D1/ADR0 ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9603, routed) 0.921 -0.387 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_6_11/WCLK SLICE_X48Y83 RAMS32 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_6_11/RAMD_D1/CLK clock pessimism -0.212 -0.599 SLICE_X48Y83 RAMS32 (Hold_rams32_CLK_ADR0) 0.310 -0.289 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_6_11/RAMD_D1 ------------------------------------------------------------------- required time 0.289 arrival time -0.184 ------------------------------------------------------------------- slack 0.105 Slack (MET) : 0.110ns (arrival time - required time) Source: u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU4/DB1/buf_im_reg[7][10]__0/C (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU4/bf1_do_im_reg[10]/D (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: sys_clk Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) Data Path Delay: 0.394ns (logic 0.209ns (53.059%) route 0.185ns (46.941%)) Logic Levels: 1 (LUT6=1) Clock Path Skew: 0.193ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.379ns Source Clock Delay (SCD): -0.536ns Clock Pessimism Removal (CPR): -0.037ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9603, routed) 0.727 -0.536 u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU4/DB1/sys_clk SLICE_X46Y48 FDRE r u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU4/DB1/buf_im_reg[7][10]__0/C ------------------------------------------------------------------- ------------------- SLICE_X46Y48 FDRE (Prop_fdre_C_Q) 0.164 -0.372 r u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU4/DB1/buf_im_reg[7][10]__0/Q net (fo=6, routed) 0.185 -0.187 u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU4/DB1/buf_im_reg[7][14]__0_0[10] SLICE_X47Y52 LUT6 (Prop_lut6_I2_O) 0.045 -0.142 r u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU4/DB1/bf1_do_im[10]_i_1__3/O net (fo=1, routed) 0.000 -0.142 u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU4/bf1_sp_im[10] SLICE_X47Y52 FDRE r u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU4/bf1_do_im_reg[10]/D ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9603, routed) 0.929 -0.379 u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU4/sys_clk SLICE_X47Y52 FDRE r u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU4/bf1_do_im_reg[10]/C clock pessimism 0.037 -0.342 SLICE_X47Y52 FDRE (Hold_fdre_C_D) 0.091 -0.251 u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU4/bf1_do_im_reg[10] ------------------------------------------------------------------- required time 0.251 arrival time -0.142 ------------------------------------------------------------------- slack 0.110 Slack (MET) : 0.112ns (arrival time - required time) Source: u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU2/DB1/buf_re_reg[127][11]__0/C (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU2/bf1_do_re_reg[11]/D (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: sys_clk Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) Data Path Delay: 0.470ns (logic 0.209ns (44.512%) route 0.261ns (55.488%)) Logic Levels: 1 (LUT6=1) Clock Path Skew: 0.266ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.403ns Source Clock Delay (SCD): -0.632ns Clock Pessimism Removal (CPR): -0.037ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9603, routed) 0.630 -0.632 u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU2/DB1/sys_clk SLICE_X84Y63 FDRE r u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU2/DB1/buf_re_reg[127][11]__0/C ------------------------------------------------------------------- ------------------- SLICE_X84Y63 FDRE (Prop_fdre_C_Q) 0.164 -0.468 r u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU2/DB1/buf_re_reg[127][11]__0/Q net (fo=6, routed) 0.261 -0.208 u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU2/DB1/buf_re_reg[127][14]__0_0[11] SLICE_X81Y62 LUT6 (Prop_lut6_I2_O) 0.045 -0.163 r u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU2/DB1/bf1_do_re[11]_i_1__1/O net (fo=1, routed) 0.000 -0.163 u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU2/bf1_sp_re[11] SLICE_X81Y62 FDRE r u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU2/bf1_do_re_reg[11]/D ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9603, routed) 0.905 -0.403 u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU2/sys_clk SLICE_X81Y62 FDRE r u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU2/bf1_do_re_reg[11]/C clock pessimism 0.037 -0.366 SLICE_X81Y62 FDRE (Hold_fdre_C_D) 0.092 -0.274 u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU2/bf1_do_re_reg[11] ------------------------------------------------------------------- required time 0.274 arrival time -0.163 ------------------------------------------------------------------- slack 0.112 Slack (MET) : 0.112ns (arrival time - required time) Source: u_matmul_axi_slave/m_in_a_reg[2]__1/C (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: u_matmul_axi_slave/mult_inst[2].u_mult/prod0/B[13] (rising edge-triggered cell DSP48E1 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: sys_clk Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) Data Path Delay: 0.624ns (logic 0.164ns (26.291%) route 0.460ns (73.709%)) Logic Levels: 0 Clock Path Skew: 0.430ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.250ns Source Clock Delay (SCD): -0.639ns Clock Pessimism Removal (CPR): -0.040ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9603, routed) 0.624 -0.639 u_matmul_axi_slave/sys_clk SLICE_X22Y110 FDRE r u_matmul_axi_slave/m_in_a_reg[2]__1/C ------------------------------------------------------------------- ------------------- SLICE_X22Y110 FDRE (Prop_fdre_C_Q) 0.164 -0.475 r u_matmul_axi_slave/m_in_a_reg[2]__1/Q net (fo=2, routed) 0.460 -0.015 u_matmul_axi_slave/mult_inst[2].u_mult/Q[13] DSP48_X1Y36 DSP48E1 r u_matmul_axi_slave/mult_inst[2].u_mult/prod0/B[13] ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9603, routed) 1.058 -0.250 u_matmul_axi_slave/mult_inst[2].u_mult/sys_clk DSP48_X1Y36 DSP48E1 r u_matmul_axi_slave/mult_inst[2].u_mult/prod0/CLK clock pessimism 0.040 -0.209 DSP48_X1Y36 DSP48E1 (Hold_dsp48e1_CLK_B[13]) 0.082 -0.127 u_matmul_axi_slave/mult_inst[2].u_mult/prod0 ------------------------------------------------------------------- required time 0.127 arrival time -0.015 ------------------------------------------------------------------- slack 0.112 Slack (MET) : 0.116ns (arrival time - required time) Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/pushCC_pushPtr_reg[0]/C (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/ram_reg_0_3_0_5/RAMA/WADR0 (rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: sys_clk Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) Data Path Delay: 0.441ns (logic 0.164ns (37.151%) route 0.277ns (62.849%)) Logic Levels: 0 Clock Path Skew: 0.015ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.381ns Source Clock Delay (SCD): -0.608ns Clock Pessimism Removal (CPR): 0.212ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9603, routed) 0.654 -0.608 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/sys_clk SLICE_X52Y93 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/pushCC_pushPtr_reg[0]/C ------------------------------------------------------------------- ------------------- SLICE_X52Y93 FDCE (Prop_fdce_C_Q) 0.164 -0.444 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/pushCC_pushPtr_reg[0]/Q net (fo=52, routed) 0.277 -0.167 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/ram_reg_0_3_0_5/ADDRD0 SLICE_X52Y91 RAMD32 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/ram_reg_0_3_0_5/RAMA/WADR0 ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9603, routed) 0.927 -0.381 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/ram_reg_0_3_0_5/WCLK SLICE_X52Y91 RAMD32 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/ram_reg_0_3_0_5/RAMA/CLK clock pessimism -0.212 -0.593 SLICE_X52Y91 RAMD32 (Hold_ramd32_CLK_WADR0) 0.310 -0.283 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/ram_reg_0_3_0_5/RAMA ------------------------------------------------------------------- required time 0.283 arrival time -0.167 ------------------------------------------------------------------- slack 0.116 Slack (MET) : 0.116ns (arrival time - required time) Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/pushCC_pushPtr_reg[0]/C (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/ram_reg_0_3_0_5/RAMA_D1/WADR0 (rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: sys_clk Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) Data Path Delay: 0.441ns (logic 0.164ns (37.151%) route 0.277ns (62.849%)) Logic Levels: 0 Clock Path Skew: 0.015ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.381ns Source Clock Delay (SCD): -0.608ns Clock Pessimism Removal (CPR): 0.212ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9603, routed) 0.654 -0.608 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/sys_clk SLICE_X52Y93 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/pushCC_pushPtr_reg[0]/C ------------------------------------------------------------------- ------------------- SLICE_X52Y93 FDCE (Prop_fdce_C_Q) 0.164 -0.444 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/pushCC_pushPtr_reg[0]/Q net (fo=52, routed) 0.277 -0.167 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/ram_reg_0_3_0_5/ADDRD0 SLICE_X52Y91 RAMD32 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/ram_reg_0_3_0_5/RAMA_D1/WADR0 ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9603, routed) 0.927 -0.381 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/ram_reg_0_3_0_5/WCLK SLICE_X52Y91 RAMD32 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/ram_reg_0_3_0_5/RAMA_D1/CLK clock pessimism -0.212 -0.593 SLICE_X52Y91 RAMD32 (Hold_ramd32_CLK_WADR0) 0.310 -0.283 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/ram_reg_0_3_0_5/RAMA_D1 ------------------------------------------------------------------- required time 0.283 arrival time -0.167 ------------------------------------------------------------------- slack 0.116 Slack (MET) : 0.116ns (arrival time - required time) Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/pushCC_pushPtr_reg[0]/C (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/ram_reg_0_3_0_5/RAMB/WADR0 (rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: sys_clk Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) Data Path Delay: 0.441ns (logic 0.164ns (37.151%) route 0.277ns (62.849%)) Logic Levels: 0 Clock Path Skew: 0.015ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.381ns Source Clock Delay (SCD): -0.608ns Clock Pessimism Removal (CPR): 0.212ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9603, routed) 0.654 -0.608 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/sys_clk SLICE_X52Y93 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/pushCC_pushPtr_reg[0]/C ------------------------------------------------------------------- ------------------- SLICE_X52Y93 FDCE (Prop_fdce_C_Q) 0.164 -0.444 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/pushCC_pushPtr_reg[0]/Q net (fo=52, routed) 0.277 -0.167 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/ram_reg_0_3_0_5/ADDRD0 SLICE_X52Y91 RAMD32 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/ram_reg_0_3_0_5/RAMB/WADR0 ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9603, routed) 0.927 -0.381 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/ram_reg_0_3_0_5/WCLK SLICE_X52Y91 RAMD32 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/ram_reg_0_3_0_5/RAMB/CLK clock pessimism -0.212 -0.593 SLICE_X52Y91 RAMD32 (Hold_ramd32_CLK_WADR0) 0.310 -0.283 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/ram_reg_0_3_0_5/RAMB ------------------------------------------------------------------- required time 0.283 arrival time -0.167 ------------------------------------------------------------------- slack 0.116 Slack (MET) : 0.116ns (arrival time - required time) Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/pushCC_pushPtr_reg[0]/C (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/ram_reg_0_3_0_5/RAMB_D1/WADR0 (rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: sys_clk Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) Data Path Delay: 0.441ns (logic 0.164ns (37.151%) route 0.277ns (62.849%)) Logic Levels: 0 Clock Path Skew: 0.015ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.381ns Source Clock Delay (SCD): -0.608ns Clock Pessimism Removal (CPR): 0.212ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9603, routed) 0.654 -0.608 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/sys_clk SLICE_X52Y93 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/pushCC_pushPtr_reg[0]/C ------------------------------------------------------------------- ------------------- SLICE_X52Y93 FDCE (Prop_fdce_C_Q) 0.164 -0.444 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/pushCC_pushPtr_reg[0]/Q net (fo=52, routed) 0.277 -0.167 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/ram_reg_0_3_0_5/ADDRD0 SLICE_X52Y91 RAMD32 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/ram_reg_0_3_0_5/RAMB_D1/WADR0 ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9603, routed) 0.927 -0.381 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/ram_reg_0_3_0_5/WCLK SLICE_X52Y91 RAMD32 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/ram_reg_0_3_0_5/RAMB_D1/CLK clock pessimism -0.212 -0.593 SLICE_X52Y91 RAMD32 (Hold_ramd32_CLK_WADR0) 0.310 -0.283 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/ram_reg_0_3_0_5/RAMB_D1 ------------------------------------------------------------------- required time 0.283 arrival time -0.167 ------------------------------------------------------------------- slack 0.116 Slack (MET) : 0.116ns (arrival time - required time) Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/pushCC_pushPtr_reg[0]/C (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/ram_reg_0_3_0_5/RAMC/WADR0 (rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: sys_clk Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) Data Path Delay: 0.441ns (logic 0.164ns (37.151%) route 0.277ns (62.849%)) Logic Levels: 0 Clock Path Skew: 0.015ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.381ns Source Clock Delay (SCD): -0.608ns Clock Pessimism Removal (CPR): 0.212ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9603, routed) 0.654 -0.608 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/sys_clk SLICE_X52Y93 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/pushCC_pushPtr_reg[0]/C ------------------------------------------------------------------- ------------------- SLICE_X52Y93 FDCE (Prop_fdce_C_Q) 0.164 -0.444 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/pushCC_pushPtr_reg[0]/Q net (fo=52, routed) 0.277 -0.167 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/ram_reg_0_3_0_5/ADDRD0 SLICE_X52Y91 RAMD32 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/ram_reg_0_3_0_5/RAMC/WADR0 ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9603, routed) 0.927 -0.381 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/ram_reg_0_3_0_5/WCLK SLICE_X52Y91 RAMD32 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/ram_reg_0_3_0_5/RAMC/CLK clock pessimism -0.212 -0.593 SLICE_X52Y91 RAMD32 (Hold_ramd32_CLK_WADR0) 0.310 -0.283 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/ram_reg_0_3_0_5/RAMC ------------------------------------------------------------------- required time 0.283 arrival time -0.167 ------------------------------------------------------------------- slack 0.116 Slack (MET) : 0.116ns (arrival time - required time) Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/pushCC_pushPtr_reg[0]/C (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/ram_reg_0_3_0_5/RAMC_D1/WADR0 (rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: sys_clk Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) Data Path Delay: 0.441ns (logic 0.164ns (37.151%) route 0.277ns (62.849%)) Logic Levels: 0 Clock Path Skew: 0.015ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.381ns Source Clock Delay (SCD): -0.608ns Clock Pessimism Removal (CPR): 0.212ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9603, routed) 0.654 -0.608 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/sys_clk SLICE_X52Y93 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/pushCC_pushPtr_reg[0]/C ------------------------------------------------------------------- ------------------- SLICE_X52Y93 FDCE (Prop_fdce_C_Q) 0.164 -0.444 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/pushCC_pushPtr_reg[0]/Q net (fo=52, routed) 0.277 -0.167 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/ram_reg_0_3_0_5/ADDRD0 SLICE_X52Y91 RAMD32 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/ram_reg_0_3_0_5/RAMC_D1/WADR0 ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9603, routed) 0.927 -0.381 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/ram_reg_0_3_0_5/WCLK SLICE_X52Y91 RAMD32 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/ram_reg_0_3_0_5/RAMC_D1/CLK clock pessimism -0.212 -0.593 SLICE_X52Y91 RAMD32 (Hold_ramd32_CLK_WADR0) 0.310 -0.283 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/ram_reg_0_3_0_5/RAMC_D1 ------------------------------------------------------------------- required time 0.283 arrival time -0.167 ------------------------------------------------------------------- slack 0.116 Slack (MET) : 0.116ns (arrival time - required time) Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/pushCC_pushPtr_reg[0]/C (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/ram_reg_0_3_0_5/RAMD/ADR0 (rising edge-triggered cell RAMS32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: sys_clk Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) Data Path Delay: 0.441ns (logic 0.164ns (37.151%) route 0.277ns (62.849%)) Logic Levels: 0 Clock Path Skew: 0.015ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.381ns Source Clock Delay (SCD): -0.608ns Clock Pessimism Removal (CPR): 0.212ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9603, routed) 0.654 -0.608 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/sys_clk SLICE_X52Y93 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/pushCC_pushPtr_reg[0]/C ------------------------------------------------------------------- ------------------- SLICE_X52Y93 FDCE (Prop_fdce_C_Q) 0.164 -0.444 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/pushCC_pushPtr_reg[0]/Q net (fo=52, routed) 0.277 -0.167 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/ram_reg_0_3_0_5/ADDRD0 SLICE_X52Y91 RAMS32 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/ram_reg_0_3_0_5/RAMD/ADR0 ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9603, routed) 0.927 -0.381 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/ram_reg_0_3_0_5/WCLK SLICE_X52Y91 RAMS32 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/ram_reg_0_3_0_5/RAMD/CLK clock pessimism -0.212 -0.593 SLICE_X52Y91 RAMS32 (Hold_rams32_CLK_ADR0) 0.310 -0.283 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/ram_reg_0_3_0_5/RAMD ------------------------------------------------------------------- required time 0.283 arrival time -0.167 ------------------------------------------------------------------- slack 0.116 Slack (MET) : 0.116ns (arrival time - required time) Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/pushCC_pushPtr_reg[0]/C (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/ram_reg_0_3_0_5/RAMD_D1/ADR0 (rising edge-triggered cell RAMS32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: sys_clk Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) Data Path Delay: 0.441ns (logic 0.164ns (37.151%) route 0.277ns (62.849%)) Logic Levels: 0 Clock Path Skew: 0.015ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.381ns Source Clock Delay (SCD): -0.608ns Clock Pessimism Removal (CPR): 0.212ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9603, routed) 0.654 -0.608 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/sys_clk SLICE_X52Y93 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/pushCC_pushPtr_reg[0]/C ------------------------------------------------------------------- ------------------- SLICE_X52Y93 FDCE (Prop_fdce_C_Q) 0.164 -0.444 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/pushCC_pushPtr_reg[0]/Q net (fo=52, routed) 0.277 -0.167 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/ram_reg_0_3_0_5/ADDRD0 SLICE_X52Y91 RAMS32 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/ram_reg_0_3_0_5/RAMD_D1/ADR0 ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9603, routed) 0.927 -0.381 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/ram_reg_0_3_0_5/WCLK SLICE_X52Y91 RAMS32 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/ram_reg_0_3_0_5/RAMD_D1/CLK clock pessimism -0.212 -0.593 SLICE_X52Y91 RAMS32 (Hold_rams32_CLK_ADR0) 0.310 -0.283 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/ram_reg_0_3_0_5/RAMD_D1 ------------------------------------------------------------------- required time 0.283 arrival time -0.167 ------------------------------------------------------------------- slack 0.116 Slack (MET) : 0.117ns (arrival time - required time) Source: u_matmul_axi_slave/m_in_b_reg[2]__4/C (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: u_matmul_axi_slave/mult_inst[2].u_mult/prod_reg__0/B[10] (rising edge-triggered cell DSP48E1 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: sys_clk Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) Data Path Delay: 0.627ns (logic 0.141ns (22.484%) route 0.486ns (77.516%)) Logic Levels: 0 Clock Path Skew: 0.429ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.247ns Source Clock Delay (SCD): -0.635ns Clock Pessimism Removal (CPR): -0.040ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9603, routed) 0.628 -0.635 u_matmul_axi_slave/sys_clk SLICE_X11Y108 FDRE r u_matmul_axi_slave/m_in_b_reg[2]__4/C ------------------------------------------------------------------- ------------------- SLICE_X11Y108 FDRE (Prop_fdre_C_Q) 0.141 -0.494 r u_matmul_axi_slave/m_in_b_reg[2]__4/Q net (fo=2, routed) 0.486 -0.008 u_matmul_axi_slave/mult_inst[2].u_mult/prod_reg__0_0[10] DSP48_X0Y37 DSP48E1 r u_matmul_axi_slave/mult_inst[2].u_mult/prod_reg__0/B[10] ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9603, routed) 1.061 -0.247 u_matmul_axi_slave/mult_inst[2].u_mult/sys_clk DSP48_X0Y37 DSP48E1 r u_matmul_axi_slave/mult_inst[2].u_mult/prod_reg__0/CLK clock pessimism 0.040 -0.206 DSP48_X0Y37 DSP48E1 (Hold_dsp48e1_CLK_B[10]) 0.082 -0.124 u_matmul_axi_slave/mult_inst[2].u_mult/prod_reg__0 ------------------------------------------------------------------- required time 0.124 arrival time -0.008 ------------------------------------------------------------------- slack 0.117 Slack (MET) : 0.118ns (arrival time - required time) Source: u_matmul_axi_slave/m_in_a_reg[1]__1/C (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: u_matmul_axi_slave/mult_inst[1].u_mult/prod0/B[13] (rising edge-triggered cell DSP48E1 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: sys_clk Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) Data Path Delay: 0.631ns (logic 0.141ns (22.343%) route 0.490ns (77.657%)) Logic Levels: 0 Clock Path Skew: 0.432ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.249ns Source Clock Delay (SCD): -0.640ns Clock Pessimism Removal (CPR): -0.040ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9603, routed) 0.623 -0.640 u_matmul_axi_slave/sys_clk SLICE_X23Y112 FDRE r u_matmul_axi_slave/m_in_a_reg[1]__1/C ------------------------------------------------------------------- ------------------- SLICE_X23Y112 FDRE (Prop_fdre_C_Q) 0.141 -0.499 r u_matmul_axi_slave/m_in_a_reg[1]__1/Q net (fo=2, routed) 0.490 -0.009 u_matmul_axi_slave/mult_inst[1].u_mult/Q[13] DSP48_X1Y38 DSP48E1 r u_matmul_axi_slave/mult_inst[1].u_mult/prod0/B[13] ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9603, routed) 1.059 -0.249 u_matmul_axi_slave/mult_inst[1].u_mult/sys_clk DSP48_X1Y38 DSP48E1 r u_matmul_axi_slave/mult_inst[1].u_mult/prod0/CLK clock pessimism 0.040 -0.208 DSP48_X1Y38 DSP48E1 (Hold_dsp48e1_CLK_B[13]) 0.082 -0.126 u_matmul_axi_slave/mult_inst[1].u_mult/prod0 ------------------------------------------------------------------- required time 0.126 arrival time -0.009 ------------------------------------------------------------------- slack 0.118 Slack (MET) : 0.120ns (arrival time - required time) Source: u_Axi_CDC/rFifo/pushCC_pushPtr_reg[0]/C (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: u_Axi_CDC/rFifo/ram_reg_0_7_30_35/RAMA/WADR0 (rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: sys_clk Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) Data Path Delay: 0.465ns (logic 0.164ns (35.259%) route 0.301ns (64.741%)) Logic Levels: 0 Clock Path Skew: 0.035ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.348ns Source Clock Delay (SCD): -0.575ns Clock Pessimism Removal (CPR): 0.192ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9603, routed) 0.687 -0.575 u_Axi_CDC/rFifo/sys_clk SLICE_X14Y69 FDCE r u_Axi_CDC/rFifo/pushCC_pushPtr_reg[0]/C ------------------------------------------------------------------- ------------------- SLICE_X14Y69 FDCE (Prop_fdce_C_Q) 0.164 -0.411 r u_Axi_CDC/rFifo/pushCC_pushPtr_reg[0]/Q net (fo=62, routed) 0.301 -0.110 u_Axi_CDC/rFifo/ram_reg_0_7_30_35/ADDRD0 SLICE_X16Y70 RAMD32 r u_Axi_CDC/rFifo/ram_reg_0_7_30_35/RAMA/WADR0 ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9603, routed) 0.960 -0.348 u_Axi_CDC/rFifo/ram_reg_0_7_30_35/WCLK SLICE_X16Y70 RAMD32 r u_Axi_CDC/rFifo/ram_reg_0_7_30_35/RAMA/CLK clock pessimism -0.192 -0.540 SLICE_X16Y70 RAMD32 (Hold_ramd32_CLK_WADR0) 0.310 -0.230 u_Axi_CDC/rFifo/ram_reg_0_7_30_35/RAMA ------------------------------------------------------------------- required time 0.230 arrival time -0.110 ------------------------------------------------------------------- slack 0.120 Slack (MET) : 0.120ns (arrival time - required time) Source: u_Axi_CDC/rFifo/pushCC_pushPtr_reg[0]/C (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: u_Axi_CDC/rFifo/ram_reg_0_7_30_35/RAMA_D1/WADR0 (rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: sys_clk Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) Data Path Delay: 0.465ns (logic 0.164ns (35.259%) route 0.301ns (64.741%)) Logic Levels: 0 Clock Path Skew: 0.035ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.348ns Source Clock Delay (SCD): -0.575ns Clock Pessimism Removal (CPR): 0.192ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9603, routed) 0.687 -0.575 u_Axi_CDC/rFifo/sys_clk SLICE_X14Y69 FDCE r u_Axi_CDC/rFifo/pushCC_pushPtr_reg[0]/C ------------------------------------------------------------------- ------------------- SLICE_X14Y69 FDCE (Prop_fdce_C_Q) 0.164 -0.411 r u_Axi_CDC/rFifo/pushCC_pushPtr_reg[0]/Q net (fo=62, routed) 0.301 -0.110 u_Axi_CDC/rFifo/ram_reg_0_7_30_35/ADDRD0 SLICE_X16Y70 RAMD32 r u_Axi_CDC/rFifo/ram_reg_0_7_30_35/RAMA_D1/WADR0 ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9603, routed) 0.960 -0.348 u_Axi_CDC/rFifo/ram_reg_0_7_30_35/WCLK SLICE_X16Y70 RAMD32 r u_Axi_CDC/rFifo/ram_reg_0_7_30_35/RAMA_D1/CLK clock pessimism -0.192 -0.540 SLICE_X16Y70 RAMD32 (Hold_ramd32_CLK_WADR0) 0.310 -0.230 u_Axi_CDC/rFifo/ram_reg_0_7_30_35/RAMA_D1 ------------------------------------------------------------------- required time 0.230 arrival time -0.110 ------------------------------------------------------------------- slack 0.120 Slack (MET) : 0.120ns (arrival time - required time) Source: u_Axi_CDC/rFifo/pushCC_pushPtr_reg[0]/C (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: u_Axi_CDC/rFifo/ram_reg_0_7_30_35/RAMB/WADR0 (rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: sys_clk Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) Data Path Delay: 0.465ns (logic 0.164ns (35.259%) route 0.301ns (64.741%)) Logic Levels: 0 Clock Path Skew: 0.035ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.348ns Source Clock Delay (SCD): -0.575ns Clock Pessimism Removal (CPR): 0.192ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9603, routed) 0.687 -0.575 u_Axi_CDC/rFifo/sys_clk SLICE_X14Y69 FDCE r u_Axi_CDC/rFifo/pushCC_pushPtr_reg[0]/C ------------------------------------------------------------------- ------------------- SLICE_X14Y69 FDCE (Prop_fdce_C_Q) 0.164 -0.411 r u_Axi_CDC/rFifo/pushCC_pushPtr_reg[0]/Q net (fo=62, routed) 0.301 -0.110 u_Axi_CDC/rFifo/ram_reg_0_7_30_35/ADDRD0 SLICE_X16Y70 RAMD32 r u_Axi_CDC/rFifo/ram_reg_0_7_30_35/RAMB/WADR0 ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9603, routed) 0.960 -0.348 u_Axi_CDC/rFifo/ram_reg_0_7_30_35/WCLK SLICE_X16Y70 RAMD32 r u_Axi_CDC/rFifo/ram_reg_0_7_30_35/RAMB/CLK clock pessimism -0.192 -0.540 SLICE_X16Y70 RAMD32 (Hold_ramd32_CLK_WADR0) 0.310 -0.230 u_Axi_CDC/rFifo/ram_reg_0_7_30_35/RAMB ------------------------------------------------------------------- required time 0.230 arrival time -0.110 ------------------------------------------------------------------- slack 0.120 Slack (MET) : 0.120ns (arrival time - required time) Source: u_Axi_CDC/rFifo/pushCC_pushPtr_reg[0]/C (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: u_Axi_CDC/rFifo/ram_reg_0_7_30_35/RAMB_D1/WADR0 (rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: sys_clk Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) Data Path Delay: 0.465ns (logic 0.164ns (35.259%) route 0.301ns (64.741%)) Logic Levels: 0 Clock Path Skew: 0.035ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.348ns Source Clock Delay (SCD): -0.575ns Clock Pessimism Removal (CPR): 0.192ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9603, routed) 0.687 -0.575 u_Axi_CDC/rFifo/sys_clk SLICE_X14Y69 FDCE r u_Axi_CDC/rFifo/pushCC_pushPtr_reg[0]/C ------------------------------------------------------------------- ------------------- SLICE_X14Y69 FDCE (Prop_fdce_C_Q) 0.164 -0.411 r u_Axi_CDC/rFifo/pushCC_pushPtr_reg[0]/Q net (fo=62, routed) 0.301 -0.110 u_Axi_CDC/rFifo/ram_reg_0_7_30_35/ADDRD0 SLICE_X16Y70 RAMD32 r u_Axi_CDC/rFifo/ram_reg_0_7_30_35/RAMB_D1/WADR0 ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9603, routed) 0.960 -0.348 u_Axi_CDC/rFifo/ram_reg_0_7_30_35/WCLK SLICE_X16Y70 RAMD32 r u_Axi_CDC/rFifo/ram_reg_0_7_30_35/RAMB_D1/CLK clock pessimism -0.192 -0.540 SLICE_X16Y70 RAMD32 (Hold_ramd32_CLK_WADR0) 0.310 -0.230 u_Axi_CDC/rFifo/ram_reg_0_7_30_35/RAMB_D1 ------------------------------------------------------------------- required time 0.230 arrival time -0.110 ------------------------------------------------------------------- slack 0.120 Slack (MET) : 0.120ns (arrival time - required time) Source: u_Axi_CDC/rFifo/pushCC_pushPtr_reg[0]/C (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: u_Axi_CDC/rFifo/ram_reg_0_7_30_35/RAMC/WADR0 (rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: sys_clk Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) Data Path Delay: 0.465ns (logic 0.164ns (35.259%) route 0.301ns (64.741%)) Logic Levels: 0 Clock Path Skew: 0.035ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.348ns Source Clock Delay (SCD): -0.575ns Clock Pessimism Removal (CPR): 0.192ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9603, routed) 0.687 -0.575 u_Axi_CDC/rFifo/sys_clk SLICE_X14Y69 FDCE r u_Axi_CDC/rFifo/pushCC_pushPtr_reg[0]/C ------------------------------------------------------------------- ------------------- SLICE_X14Y69 FDCE (Prop_fdce_C_Q) 0.164 -0.411 r u_Axi_CDC/rFifo/pushCC_pushPtr_reg[0]/Q net (fo=62, routed) 0.301 -0.110 u_Axi_CDC/rFifo/ram_reg_0_7_30_35/ADDRD0 SLICE_X16Y70 RAMD32 r u_Axi_CDC/rFifo/ram_reg_0_7_30_35/RAMC/WADR0 ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9603, routed) 0.960 -0.348 u_Axi_CDC/rFifo/ram_reg_0_7_30_35/WCLK SLICE_X16Y70 RAMD32 r u_Axi_CDC/rFifo/ram_reg_0_7_30_35/RAMC/CLK clock pessimism -0.192 -0.540 SLICE_X16Y70 RAMD32 (Hold_ramd32_CLK_WADR0) 0.310 -0.230 u_Axi_CDC/rFifo/ram_reg_0_7_30_35/RAMC ------------------------------------------------------------------- required time 0.230 arrival time -0.110 ------------------------------------------------------------------- slack 0.120 Slack (MET) : 0.120ns (arrival time - required time) Source: u_Axi_CDC/rFifo/pushCC_pushPtr_reg[0]/C (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: u_Axi_CDC/rFifo/ram_reg_0_7_30_35/RAMC_D1/WADR0 (rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: sys_clk Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) Data Path Delay: 0.465ns (logic 0.164ns (35.259%) route 0.301ns (64.741%)) Logic Levels: 0 Clock Path Skew: 0.035ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.348ns Source Clock Delay (SCD): -0.575ns Clock Pessimism Removal (CPR): 0.192ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9603, routed) 0.687 -0.575 u_Axi_CDC/rFifo/sys_clk SLICE_X14Y69 FDCE r u_Axi_CDC/rFifo/pushCC_pushPtr_reg[0]/C ------------------------------------------------------------------- ------------------- SLICE_X14Y69 FDCE (Prop_fdce_C_Q) 0.164 -0.411 r u_Axi_CDC/rFifo/pushCC_pushPtr_reg[0]/Q net (fo=62, routed) 0.301 -0.110 u_Axi_CDC/rFifo/ram_reg_0_7_30_35/ADDRD0 SLICE_X16Y70 RAMD32 r u_Axi_CDC/rFifo/ram_reg_0_7_30_35/RAMC_D1/WADR0 ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9603, routed) 0.960 -0.348 u_Axi_CDC/rFifo/ram_reg_0_7_30_35/WCLK SLICE_X16Y70 RAMD32 r u_Axi_CDC/rFifo/ram_reg_0_7_30_35/RAMC_D1/CLK clock pessimism -0.192 -0.540 SLICE_X16Y70 RAMD32 (Hold_ramd32_CLK_WADR0) 0.310 -0.230 u_Axi_CDC/rFifo/ram_reg_0_7_30_35/RAMC_D1 ------------------------------------------------------------------- required time 0.230 arrival time -0.110 ------------------------------------------------------------------- slack 0.120 Slack (MET) : 0.120ns (arrival time - required time) Source: u_Axi_CDC/rFifo/pushCC_pushPtr_reg[0]/C (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: u_Axi_CDC/rFifo/ram_reg_0_7_30_35/RAMD/ADR0 (rising edge-triggered cell RAMS32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: sys_clk Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) Data Path Delay: 0.465ns (logic 0.164ns (35.259%) route 0.301ns (64.741%)) Logic Levels: 0 Clock Path Skew: 0.035ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.348ns Source Clock Delay (SCD): -0.575ns Clock Pessimism Removal (CPR): 0.192ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9603, routed) 0.687 -0.575 u_Axi_CDC/rFifo/sys_clk SLICE_X14Y69 FDCE r u_Axi_CDC/rFifo/pushCC_pushPtr_reg[0]/C ------------------------------------------------------------------- ------------------- SLICE_X14Y69 FDCE (Prop_fdce_C_Q) 0.164 -0.411 r u_Axi_CDC/rFifo/pushCC_pushPtr_reg[0]/Q net (fo=62, routed) 0.301 -0.110 u_Axi_CDC/rFifo/ram_reg_0_7_30_35/ADDRD0 SLICE_X16Y70 RAMS32 r u_Axi_CDC/rFifo/ram_reg_0_7_30_35/RAMD/ADR0 ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9603, routed) 0.960 -0.348 u_Axi_CDC/rFifo/ram_reg_0_7_30_35/WCLK SLICE_X16Y70 RAMS32 r u_Axi_CDC/rFifo/ram_reg_0_7_30_35/RAMD/CLK clock pessimism -0.192 -0.540 SLICE_X16Y70 RAMS32 (Hold_rams32_CLK_ADR0) 0.310 -0.230 u_Axi_CDC/rFifo/ram_reg_0_7_30_35/RAMD ------------------------------------------------------------------- required time 0.230 arrival time -0.110 ------------------------------------------------------------------- slack 0.120 Slack (MET) : 0.120ns (arrival time - required time) Source: u_Axi_CDC/rFifo/pushCC_pushPtr_reg[0]/C (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: u_Axi_CDC/rFifo/ram_reg_0_7_30_35/RAMD_D1/ADR0 (rising edge-triggered cell RAMS32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: sys_clk Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) Data Path Delay: 0.465ns (logic 0.164ns (35.259%) route 0.301ns (64.741%)) Logic Levels: 0 Clock Path Skew: 0.035ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.348ns Source Clock Delay (SCD): -0.575ns Clock Pessimism Removal (CPR): 0.192ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9603, routed) 0.687 -0.575 u_Axi_CDC/rFifo/sys_clk SLICE_X14Y69 FDCE r u_Axi_CDC/rFifo/pushCC_pushPtr_reg[0]/C ------------------------------------------------------------------- ------------------- SLICE_X14Y69 FDCE (Prop_fdce_C_Q) 0.164 -0.411 r u_Axi_CDC/rFifo/pushCC_pushPtr_reg[0]/Q net (fo=62, routed) 0.301 -0.110 u_Axi_CDC/rFifo/ram_reg_0_7_30_35/ADDRD0 SLICE_X16Y70 RAMS32 r u_Axi_CDC/rFifo/ram_reg_0_7_30_35/RAMD_D1/ADR0 ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9603, routed) 0.960 -0.348 u_Axi_CDC/rFifo/ram_reg_0_7_30_35/WCLK SLICE_X16Y70 RAMS32 r u_Axi_CDC/rFifo/ram_reg_0_7_30_35/RAMD_D1/CLK clock pessimism -0.192 -0.540 SLICE_X16Y70 RAMS32 (Hold_rams32_CLK_ADR0) 0.310 -0.230 u_Axi_CDC/rFifo/ram_reg_0_7_30_35/RAMD_D1 ------------------------------------------------------------------- required time 0.230 arrival time -0.110 ------------------------------------------------------------------- slack 0.120 Pulse Width Checks -------------------------------------------------------------------------------------- Clock Name: sys_clk Waveform(ns): { 0.000 10.000 } Period(ns): 20.000 Sources: { pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 } Check Type Corner Lib Pin Reference Pin Required(ns) Actual(ns) Slack(ns) Location Pin Min Period n/a DSP48E1/CLK n/a 3.884 20.000 16.116 DSP48_X1Y35 u_matmul_axi_slave/mult_inst[0].u_mult/prod_reg/CLK Min Period n/a DSP48E1/CLK n/a 3.884 20.000 16.116 DSP48_X0Y35 u_matmul_axi_slave/mult_inst[3].u_mult/prod_reg/CLK Min Period n/a DSP48E1/CLK n/a 3.884 20.000 16.116 DSP48_X1Y37 u_matmul_axi_slave/mult_inst[2].u_mult/prod_reg/CLK Min Period n/a DSP48E1/CLK n/a 3.884 20.000 16.116 DSP48_X1Y39 u_matmul_axi_slave/mult_inst[1].u_mult/prod_reg/CLK Min Period n/a DSP48E1/CLK n/a 3.687 20.000 16.313 DSP48_X0Y39 u_matmul_axi_slave/mult_inst[1].u_mult/prod_reg__0/CLK Min Period n/a DSP48E1/CLK n/a 3.687 20.000 16.313 DSP48_X1Y33 u_matmul_axi_slave/mult_inst[0].u_mult/prod_reg__0/CLK Min Period n/a DSP48E1/CLK n/a 3.687 20.000 16.313 DSP48_X0Y33 u_matmul_axi_slave/mult_inst[3].u_mult/prod_reg__0/CLK Min Period n/a DSP48E1/CLK n/a 3.687 20.000 16.313 DSP48_X0Y37 u_matmul_axi_slave/mult_inst[2].u_mult/prod_reg__0/CLK Min Period n/a RAMB18E1/CLKARDCLK n/a 2.944 20.000 17.056 RAMB18_X3Y34 u_fft_mlkem_axi_slave/u_fft_controller/u_in0/ram_reg/CLKARDCLK Min Period n/a RAMB18E1/CLKARDCLK n/a 2.944 20.000 17.056 RAMB18_X3Y35 u_fft_mlkem_axi_slave/u_fft_controller/u_in1/ram_reg/CLKARDCLK Min Period n/a RAMB18E1/CLKARDCLK n/a 2.944 20.000 17.056 RAMB18_X3Y24 u_fft_mlkem_axi_slave/u_fft_controller/u_out0/ram_reg/CLKARDCLK Min Period n/a RAMB18E1/CLKARDCLK n/a 2.944 20.000 17.056 RAMB18_X3Y25 u_fft_mlkem_axi_slave/u_fft_controller/u_out1/ram_reg/CLKARDCLK Min Period n/a RAMB18E1/CLKARDCLK n/a 2.944 20.000 17.056 RAMB18_X1Y32 u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/mem_reg/CLKARDCLK Min Period n/a RAMB18E1/CLKBWRCLK n/a 2.944 20.000 17.056 RAMB18_X1Y32 u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/mem_reg/CLKBWRCLK Min Period n/a RAMB36E1/CLKARDCLK n/a 2.576 20.000 17.424 RAMB36_X4Y13 u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/TW/ff_im_reg/CLKARDCLK Min Period n/a RAMB36E1/CLKARDCLK n/a 2.576 20.000 17.424 RAMB36_X3Y13 u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/TW/ff_re_reg/CLKARDCLK Min Period n/a RAMB36E1/CLKARDCLK n/a 2.576 20.000 17.424 RAMB36_X3Y10 u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU2/TW/ff_im_reg/CLKARDCLK Min Period n/a RAMB36E1/CLKBWRCLK n/a 2.576 20.000 17.424 RAMB36_X3Y10 u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU2/TW/ff_im_reg/CLKBWRCLK Min Period n/a RAMB36E1/CLKARDCLK n/a 2.576 20.000 17.424 RAMB36_X7Y5 u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU4/TW/ff_im_reg/CLKARDCLK Min Period n/a RAMB36E1/CLKARDCLK n/a 2.576 20.000 17.424 RAMB36_X3Y11 u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU2/TW/ff_re_reg/CLKARDCLK Min Period n/a RAMB36E1/CLKBWRCLK n/a 2.576 20.000 17.424 RAMB36_X3Y11 u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU2/TW/ff_re_reg/CLKBWRCLK Min Period n/a RAMB36E1/CLKARDCLK n/a 2.576 20.000 17.424 RAMB36_X7Y6 u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU4/TW/ff_re_reg/CLKARDCLK Min Period n/a RAMB18E1/CLKBWRCLK n/a 2.576 20.000 17.424 RAMB18_X3Y34 u_fft_mlkem_axi_slave/u_fft_controller/u_in0/ram_reg/CLKBWRCLK Min Period n/a RAMB18E1/CLKBWRCLK n/a 2.576 20.000 17.424 RAMB18_X3Y35 u_fft_mlkem_axi_slave/u_fft_controller/u_in1/ram_reg/CLKBWRCLK Min Period n/a RAMB18E1/CLKBWRCLK n/a 2.576 20.000 17.424 RAMB18_X3Y24 u_fft_mlkem_axi_slave/u_fft_controller/u_out0/ram_reg/CLKBWRCLK Min Period n/a RAMB18E1/CLKBWRCLK n/a 2.576 20.000 17.424 RAMB18_X3Y25 u_fft_mlkem_axi_slave/u_fft_controller/u_out1/ram_reg/CLKBWRCLK Min Period n/a BUFG/I n/a 2.155 20.000 17.845 BUFGCTRL_X0Y16 pll_clk.u_clk_pll/inst/clkout2_buf/I Min Period n/a PLLE2_ADV/CLKOUT1 n/a 1.249 20.000 18.751 PLLE2_ADV_X0Y3 pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 Min Period n/a FDRE/C n/a 1.000 20.000 19.000 SLICE_X21Y108 u_matmul_axi_slave/mult_inst[0].u_mult/prod0__18/C Min Period n/a FDRE/C n/a 1.000 20.000 19.000 SLICE_X25Y95 u_matmul_axi_slave/mult_inst[0].u_mult/prod0__19/C Min Period n/a FDRE/C n/a 1.000 20.000 19.000 SLICE_X45Y111 u_matmul_axi_slave/mult_inst[0].u_mult/prod0__2/C Min Period n/a FDRE/C n/a 1.000 20.000 19.000 SLICE_X43Y98 u_matmul_axi_slave/mult_inst[0].u_mult/prod0__20/C Min Period n/a FDRE/C n/a 1.000 20.000 19.000 SLICE_X19Y95 u_matmul_axi_slave/mult_inst[1].u_mult/prod_reg[0]/C Min Period n/a FDRE/C n/a 1.000 20.000 19.000 SLICE_X16Y76 u_matmul_axi_slave/mult_inst[1].u_mult/prod_reg[0]__0/C Min Period n/a FDRE/C n/a 1.000 20.000 19.000 SLICE_X22Y96 u_matmul_axi_slave/mult_inst[1].u_mult/prod_reg[10]/C Min Period n/a FDRE/C n/a 1.000 20.000 19.000 SLICE_X14Y93 u_matmul_axi_slave/mult_inst[1].u_mult/prod_reg[10]__0/C Min Period n/a FDRE/C n/a 1.000 20.000 19.000 SLICE_X19Y95 u_matmul_axi_slave/mult_inst[1].u_mult/prod_reg[11]/C Min Period n/a FDRE/C n/a 1.000 20.000 19.000 SLICE_X13Y90 u_matmul_axi_slave/mult_inst[1].u_mult/prod_reg[11]__0/C Min Period n/a FDRE/C n/a 1.000 20.000 19.000 SLICE_X21Y94 u_matmul_axi_slave/mult_inst[1].u_mult/prod_reg[12]/C Min Period n/a FDRE/C n/a 1.000 20.000 19.000 SLICE_X12Y84 u_matmul_axi_slave/mult_inst[1].u_mult/prod_reg[12]__0/C Min Period n/a FDRE/C n/a 1.000 20.000 19.000 SLICE_X22Y96 u_matmul_axi_slave/mult_inst[1].u_mult/prod_reg[13]/C Min Period n/a FDRE/C n/a 1.000 20.000 19.000 SLICE_X14Y93 u_matmul_axi_slave/mult_inst[1].u_mult/prod_reg[13]__0/C Min Period n/a FDRE/C n/a 1.000 20.000 19.000 SLICE_X19Y98 u_matmul_axi_slave/mult_inst[1].u_mult/prod_reg[14]/C Min Period n/a FDRE/C n/a 1.000 20.000 19.000 SLICE_X13Y91 u_matmul_axi_slave/mult_inst[1].u_mult/prod_reg[14]__0/C Min Period n/a FDRE/C n/a 1.000 20.000 19.000 SLICE_X22Y96 u_matmul_axi_slave/mult_inst[1].u_mult/prod_reg[15]/C Min Period n/a FDRE/C n/a 1.000 20.000 19.000 SLICE_X13Y91 u_matmul_axi_slave/mult_inst[1].u_mult/prod_reg[15]__0/C Min Period n/a FDRE/C n/a 1.000 20.000 19.000 SLICE_X22Y96 u_matmul_axi_slave/mult_inst[1].u_mult/prod_reg[16]/C Min Period n/a FDRE/C n/a 1.000 20.000 19.000 SLICE_X14Y91 u_matmul_axi_slave/mult_inst[1].u_mult/prod_reg[16]__0/C Min Period n/a FDRE/C n/a 1.000 20.000 19.000 SLICE_X18Y94 u_matmul_axi_slave/mult_inst[1].u_mult/prod_reg[1]/C Min Period n/a FDRE/C n/a 1.000 20.000 19.000 SLICE_X13Y81 u_matmul_axi_slave/mult_inst[1].u_mult/prod_reg[1]__0/C Max Period n/a PLLE2_ADV/CLKOUT1 n/a 160.000 20.000 140.000 PLLE2_ADV_X0Y3 pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 Low Pulse Width Fast RAMD32/CLK n/a 1.250 10.000 8.750 SLICE_X22Y70 axi4WriteOnlyArbiter_5/cmdRouteFork_translated_fifo/fifo/logic_ram_reg_0_3_0_0/DP/CLK Low Pulse Width Fast RAMD32/CLK n/a 1.250 10.000 8.750 SLICE_X22Y70 axi4WriteOnlyArbiter_5/cmdRouteFork_translated_fifo/fifo/logic_ram_reg_0_3_0_0/SP/CLK Low Pulse Width Slow RAMD32/CLK n/a 1.250 10.000 8.750 SLICE_X40Y84 axi4WriteOnlyArbiter_7/cmdRouteFork_translated_fifo/fifo/logic_ram_reg_0_3_0_0/DP/CLK Low Pulse Width Slow RAMD32/CLK n/a 1.250 10.000 8.750 SLICE_X40Y84 axi4WriteOnlyArbiter_7/cmdRouteFork_translated_fifo/fifo/logic_ram_reg_0_3_0_0/SP/CLK Low Pulse Width Fast RAMD32/CLK n/a 1.250 10.000 8.750 SLICE_X48Y82 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_0_5/RAMA/CLK Low Pulse Width Fast RAMD32/CLK n/a 1.250 10.000 8.750 SLICE_X48Y82 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_0_5/RAMA_D1/CLK Low Pulse Width Fast RAMD32/CLK n/a 1.250 10.000 8.750 SLICE_X48Y82 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_0_5/RAMB/CLK Low Pulse Width Fast RAMD32/CLK n/a 1.250 10.000 8.750 SLICE_X48Y82 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_0_5/RAMB_D1/CLK Low Pulse Width Fast RAMD32/CLK n/a 1.250 10.000 8.750 SLICE_X48Y82 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_0_5/RAMC/CLK Low Pulse Width Fast RAMD32/CLK n/a 1.250 10.000 8.750 SLICE_X48Y82 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_0_5/RAMC_D1/CLK Low Pulse Width Fast RAMS32/CLK n/a 1.250 10.000 8.750 SLICE_X48Y82 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_0_5/RAMD/CLK Low Pulse Width Fast RAMS32/CLK n/a 1.250 10.000 8.750 SLICE_X48Y82 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_0_5/RAMD_D1/CLK Low Pulse Width Fast RAMD32/CLK n/a 1.250 10.000 8.750 SLICE_X48Y80 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_12_17/RAMA/CLK Low Pulse Width Fast RAMD32/CLK n/a 1.250 10.000 8.750 SLICE_X48Y80 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_12_17/RAMA_D1/CLK Low Pulse Width Fast RAMD32/CLK n/a 1.250 10.000 8.750 SLICE_X48Y80 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_12_17/RAMB/CLK Low Pulse Width Fast RAMD32/CLK n/a 1.250 10.000 8.750 SLICE_X48Y80 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_12_17/RAMB_D1/CLK Low Pulse Width Fast RAMD32/CLK n/a 1.250 10.000 8.750 SLICE_X48Y80 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_12_17/RAMC/CLK Low Pulse Width Fast RAMD32/CLK n/a 1.250 10.000 8.750 SLICE_X48Y80 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_12_17/RAMC_D1/CLK Low Pulse Width Fast RAMS32/CLK n/a 1.250 10.000 8.750 SLICE_X48Y80 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_12_17/RAMD/CLK Low Pulse Width Fast RAMS32/CLK n/a 1.250 10.000 8.750 SLICE_X48Y80 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_12_17/RAMD_D1/CLK Low Pulse Width Fast RAMD32/CLK n/a 1.250 10.000 8.750 SLICE_X42Y80 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_30_35/RAMA/CLK Low Pulse Width Fast RAMD32/CLK n/a 1.250 10.000 8.750 SLICE_X42Y80 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_30_35/RAMA_D1/CLK Low Pulse Width Fast RAMD32/CLK n/a 1.250 10.000 8.750 SLICE_X42Y80 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_30_35/RAMB/CLK Low Pulse Width Fast RAMD32/CLK n/a 1.250 10.000 8.750 SLICE_X42Y80 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_30_35/RAMB_D1/CLK Low Pulse Width Fast RAMD32/CLK n/a 1.250 10.000 8.750 SLICE_X42Y80 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_30_35/RAMC/CLK Low Pulse Width Fast RAMD32/CLK n/a 1.250 10.000 8.750 SLICE_X42Y80 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_30_35/RAMC_D1/CLK Low Pulse Width Fast RAMS32/CLK n/a 1.250 10.000 8.750 SLICE_X42Y80 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_30_35/RAMD/CLK Low Pulse Width Fast RAMS32/CLK n/a 1.250 10.000 8.750 SLICE_X42Y80 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_30_35/RAMD_D1/CLK Low Pulse Width Fast RAMD32/CLK n/a 1.250 10.000 8.750 SLICE_X46Y80 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_42_47/RAMA/CLK Low Pulse Width Fast RAMD32/CLK n/a 1.250 10.000 8.750 SLICE_X46Y80 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_42_47/RAMA_D1/CLK Low Pulse Width Fast RAMD32/CLK n/a 1.250 10.000 8.750 SLICE_X46Y80 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_42_47/RAMB/CLK Low Pulse Width Fast RAMD32/CLK n/a 1.250 10.000 8.750 SLICE_X46Y80 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_42_47/RAMB_D1/CLK Low Pulse Width Fast RAMD32/CLK n/a 1.250 10.000 8.750 SLICE_X46Y80 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_42_47/RAMC/CLK Low Pulse Width Fast RAMD32/CLK n/a 1.250 10.000 8.750 SLICE_X46Y80 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_42_47/RAMC_D1/CLK Low Pulse Width Fast RAMS32/CLK n/a 1.250 10.000 8.750 SLICE_X46Y80 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_42_47/RAMD/CLK Low Pulse Width Fast RAMS32/CLK n/a 1.250 10.000 8.750 SLICE_X46Y80 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_42_47/RAMD_D1/CLK Low Pulse Width Slow RAMD32/CLK n/a 1.250 10.000 8.750 SLICE_X42Y81 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_48_53/RAMA/CLK Low Pulse Width Fast RAMD32/CLK n/a 1.250 10.000 8.750 SLICE_X42Y81 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_48_53/RAMA/CLK Low Pulse Width Slow RAMD32/CLK n/a 1.250 10.000 8.750 SLICE_X42Y81 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_48_53/RAMA_D1/CLK Low Pulse Width Fast RAMD32/CLK n/a 1.250 10.000 8.750 SLICE_X42Y81 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_48_53/RAMA_D1/CLK Low Pulse Width Slow RAMD32/CLK n/a 1.250 10.000 8.750 SLICE_X42Y81 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_48_53/RAMB/CLK Low Pulse Width Fast RAMD32/CLK n/a 1.250 10.000 8.750 SLICE_X42Y81 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_48_53/RAMB/CLK Low Pulse Width Slow RAMD32/CLK n/a 1.250 10.000 8.750 SLICE_X42Y81 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_48_53/RAMB_D1/CLK Low Pulse Width Fast RAMD32/CLK n/a 1.250 10.000 8.750 SLICE_X42Y81 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_48_53/RAMB_D1/CLK Low Pulse Width Slow RAMD32/CLK n/a 1.250 10.000 8.750 SLICE_X42Y81 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_48_53/RAMC/CLK Low Pulse Width Fast RAMD32/CLK n/a 1.250 10.000 8.750 SLICE_X42Y81 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_48_53/RAMC/CLK Low Pulse Width Slow RAMD32/CLK n/a 1.250 10.000 8.750 SLICE_X42Y81 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_48_53/RAMC_D1/CLK Low Pulse Width Fast RAMD32/CLK n/a 1.250 10.000 8.750 SLICE_X42Y81 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_48_53/RAMC_D1/CLK Low Pulse Width Slow RAMS32/CLK n/a 1.250 10.000 8.750 SLICE_X42Y81 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_48_53/RAMD/CLK Low Pulse Width Fast RAMS32/CLK n/a 1.250 10.000 8.750 SLICE_X42Y81 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_48_53/RAMD/CLK High Pulse Width Slow RAMD32/CLK n/a 1.250 10.000 8.750 SLICE_X48Y82 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_0_5/RAMA/CLK High Pulse Width Slow RAMD32/CLK n/a 1.250 10.000 8.750 SLICE_X48Y82 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_0_5/RAMA_D1/CLK High Pulse Width Slow RAMD32/CLK n/a 1.250 10.000 8.750 SLICE_X48Y82 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_0_5/RAMB/CLK High Pulse Width Slow RAMD32/CLK n/a 1.250 10.000 8.750 SLICE_X48Y82 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_0_5/RAMB_D1/CLK High Pulse Width Slow RAMD32/CLK n/a 1.250 10.000 8.750 SLICE_X48Y82 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_0_5/RAMC/CLK High Pulse Width Slow RAMD32/CLK n/a 1.250 10.000 8.750 SLICE_X48Y82 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_0_5/RAMC_D1/CLK High Pulse Width Slow RAMS32/CLK n/a 1.250 10.000 8.750 SLICE_X48Y82 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_0_5/RAMD/CLK High Pulse Width Slow RAMS32/CLK n/a 1.250 10.000 8.750 SLICE_X48Y82 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_0_5/RAMD_D1/CLK High Pulse Width Fast RAMD32/CLK n/a 1.250 10.000 8.750 SLICE_X46Y83 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_36_41/RAMA/CLK High Pulse Width Fast RAMD32/CLK n/a 1.250 10.000 8.750 SLICE_X46Y83 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_36_41/RAMA_D1/CLK High Pulse Width Fast RAMD32/CLK n/a 1.250 10.000 8.750 SLICE_X46Y83 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_36_41/RAMB/CLK High Pulse Width Fast RAMD32/CLK n/a 1.250 10.000 8.750 SLICE_X46Y83 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_36_41/RAMB_D1/CLK High Pulse Width Fast RAMD32/CLK n/a 1.250 10.000 8.750 SLICE_X46Y83 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_36_41/RAMC/CLK High Pulse Width Fast RAMD32/CLK n/a 1.250 10.000 8.750 SLICE_X46Y83 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_36_41/RAMC_D1/CLK High Pulse Width Fast RAMS32/CLK n/a 1.250 10.000 8.750 SLICE_X46Y83 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_36_41/RAMD/CLK High Pulse Width Fast RAMS32/CLK n/a 1.250 10.000 8.750 SLICE_X46Y83 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_36_41/RAMD_D1/CLK High Pulse Width Fast RAMD32/CLK n/a 1.250 10.000 8.750 SLICE_X48Y83 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_6_11/RAMA/CLK High Pulse Width Fast RAMD32/CLK n/a 1.250 10.000 8.750 SLICE_X48Y83 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_6_11/RAMA_D1/CLK High Pulse Width Fast RAMD32/CLK n/a 1.250 10.000 8.750 SLICE_X48Y83 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_6_11/RAMB/CLK High Pulse Width Fast RAMD32/CLK n/a 1.250 10.000 8.750 SLICE_X48Y83 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_6_11/RAMB_D1/CLK High Pulse Width Fast RAMD32/CLK n/a 1.250 10.000 8.750 SLICE_X48Y83 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_6_11/RAMC/CLK High Pulse Width Fast RAMD32/CLK n/a 1.250 10.000 8.750 SLICE_X48Y83 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_6_11/RAMC_D1/CLK High Pulse Width Fast RAMS32/CLK n/a 1.250 10.000 8.750 SLICE_X48Y83 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_6_11/RAMD/CLK High Pulse Width Fast RAMS32/CLK n/a 1.250 10.000 8.750 SLICE_X48Y83 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_6_11/RAMD_D1/CLK High Pulse Width Fast RAMD32/CLK n/a 1.250 10.000 8.750 SLICE_X12Y70 u_Axi_CDC/rFifo/ram_reg_0_7_0_5/RAMA/CLK High Pulse Width Fast RAMD32/CLK n/a 1.250 10.000 8.750 SLICE_X12Y70 u_Axi_CDC/rFifo/ram_reg_0_7_0_5/RAMA_D1/CLK High Pulse Width Fast RAMD32/CLK n/a 1.250 10.000 8.750 SLICE_X12Y70 u_Axi_CDC/rFifo/ram_reg_0_7_0_5/RAMB/CLK High Pulse Width Fast RAMD32/CLK n/a 1.250 10.000 8.750 SLICE_X12Y70 u_Axi_CDC/rFifo/ram_reg_0_7_0_5/RAMB_D1/CLK High Pulse Width Fast RAMD32/CLK n/a 1.250 10.000 8.750 SLICE_X12Y70 u_Axi_CDC/rFifo/ram_reg_0_7_0_5/RAMC/CLK High Pulse Width Fast RAMD32/CLK n/a 1.250 10.000 8.750 SLICE_X12Y70 u_Axi_CDC/rFifo/ram_reg_0_7_0_5/RAMC_D1/CLK High Pulse Width Fast RAMS32/CLK n/a 1.250 10.000 8.750 SLICE_X12Y70 u_Axi_CDC/rFifo/ram_reg_0_7_0_5/RAMD/CLK High Pulse Width Fast RAMS32/CLK n/a 1.250 10.000 8.750 SLICE_X12Y70 u_Axi_CDC/rFifo/ram_reg_0_7_0_5/RAMD_D1/CLK High Pulse Width Fast RAMD32/CLK n/a 1.250 10.000 8.750 SLICE_X14Y70 u_Axi_CDC/rFifo/ram_reg_0_7_12_17/RAMA/CLK High Pulse Width Fast RAMD32/CLK n/a 1.250 10.000 8.750 SLICE_X14Y70 u_Axi_CDC/rFifo/ram_reg_0_7_12_17/RAMA_D1/CLK High Pulse Width Fast RAMD32/CLK n/a 1.250 10.000 8.750 SLICE_X14Y70 u_Axi_CDC/rFifo/ram_reg_0_7_12_17/RAMB/CLK High Pulse Width Fast RAMD32/CLK n/a 1.250 10.000 8.750 SLICE_X14Y70 u_Axi_CDC/rFifo/ram_reg_0_7_12_17/RAMB_D1/CLK High Pulse Width Fast RAMD32/CLK n/a 1.250 10.000 8.750 SLICE_X14Y70 u_Axi_CDC/rFifo/ram_reg_0_7_12_17/RAMC/CLK High Pulse Width Fast RAMD32/CLK n/a 1.250 10.000 8.750 SLICE_X14Y70 u_Axi_CDC/rFifo/ram_reg_0_7_12_17/RAMC_D1/CLK High Pulse Width Fast RAMS32/CLK n/a 1.250 10.000 8.750 SLICE_X14Y70 u_Axi_CDC/rFifo/ram_reg_0_7_12_17/RAMD/CLK High Pulse Width Fast RAMS32/CLK n/a 1.250 10.000 8.750 SLICE_X14Y70 u_Axi_CDC/rFifo/ram_reg_0_7_12_17/RAMD_D1/CLK High Pulse Width Fast RAMD32/CLK n/a 1.250 10.000 8.750 SLICE_X10Y71 u_Axi_CDC/rFifo/ram_reg_0_7_24_29/RAMA/CLK High Pulse Width Fast RAMD32/CLK n/a 1.250 10.000 8.750 SLICE_X10Y71 u_Axi_CDC/rFifo/ram_reg_0_7_24_29/RAMA_D1/CLK High Pulse Width Fast RAMD32/CLK n/a 1.250 10.000 8.750 SLICE_X10Y71 u_Axi_CDC/rFifo/ram_reg_0_7_24_29/RAMB/CLK High Pulse Width Fast RAMD32/CLK n/a 1.250 10.000 8.750 SLICE_X10Y71 u_Axi_CDC/rFifo/ram_reg_0_7_24_29/RAMB_D1/CLK High Pulse Width Fast RAMD32/CLK n/a 1.250 10.000 8.750 SLICE_X10Y71 u_Axi_CDC/rFifo/ram_reg_0_7_24_29/RAMC/CLK High Pulse Width Fast RAMD32/CLK n/a 1.250 10.000 8.750 SLICE_X10Y71 u_Axi_CDC/rFifo/ram_reg_0_7_24_29/RAMC_D1/CLK High Pulse Width Fast RAMS32/CLK n/a 1.250 10.000 8.750 SLICE_X10Y71 u_Axi_CDC/rFifo/ram_reg_0_7_24_29/RAMD/CLK High Pulse Width Fast RAMS32/CLK n/a 1.250 10.000 8.750 SLICE_X10Y71 u_Axi_CDC/rFifo/ram_reg_0_7_24_29/RAMD_D1/CLK High Pulse Width Fast RAMD32/CLK n/a 1.250 10.000 8.750 SLICE_X16Y70 u_Axi_CDC/rFifo/ram_reg_0_7_30_35/RAMA/CLK High Pulse Width Fast RAMD32/CLK n/a 1.250 10.000 8.750 SLICE_X16Y70 u_Axi_CDC/rFifo/ram_reg_0_7_30_35/RAMA_D1/CLK --------------------------------------------------------------------------------------------------- From Clock: sys_clk To Clock: mlkem_clk_clk_pll Setup : NA Failing Endpoints, Worst Slack NA , Total Violation NA Hold : 0 Failing Endpoints, Worst Slack 0.022ns, Total Violation 0.000ns --------------------------------------------------------------------------------------------------- Min Delay Paths -------------------------------------------------------------------------------------- Slack (MET) : 0.022ns (arrival time - required time) Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/ram_reg_0_7_6_11/RAMA/CLK (rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/_zz_ram_port1_reg[6]/D (rising edge-triggered cell FDRE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) Path Group: mlkem_clk_clk_pll Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (mlkem_clk_clk_pll rise@0.000ns - sys_clk rise@0.000ns) Data Path Delay: 0.551ns (logic 0.492ns (89.293%) route 0.059ns (10.707%)) Logic Levels: 0 Clock Path Skew: 0.328ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.381ns Source Clock Delay (SCD): -0.610ns Clock Pessimism Removal (CPR): -0.099ns Clock Uncertainty: 0.197ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.136ns Phase Error (PE): 0.120ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9603, routed) 0.652 -0.610 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/ram_reg_0_7_6_11/WCLK SLICE_X60Y98 RAMD32 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/ram_reg_0_7_6_11/RAMA/CLK ------------------------------------------------------------------- ------------------- SLICE_X60Y98 RAMD32 (Prop_ramd32_CLK_O) 0.492 -0.118 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/ram_reg_0_7_6_11/RAMA/O net (fo=1, routed) 0.059 -0.059 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/_zz_ram_port10__0[6] SLICE_X61Y98 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/_zz_ram_port1_reg[6]/D ------------------------------------------------------------------- ------------------- (clock mlkem_clk_clk_pll rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout3_buf/O net (fo=25775, routed) 0.927 -0.381 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/mlkem_clk SLICE_X61Y98 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/_zz_ram_port1_reg[6]/C clock pessimism 0.099 -0.282 clock uncertainty 0.197 -0.086 SLICE_X61Y98 FDRE (Hold_fdre_C_D) 0.004 -0.082 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/_zz_ram_port1_reg[6] ------------------------------------------------------------------- required time 0.082 arrival time -0.059 ------------------------------------------------------------------- slack 0.022 Slack (MET) : 0.044ns (arrival time - required time) Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/ram_reg_0_7_18_23/RAMC/CLK (rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/_zz_ram_port1_reg[22]/D (rising edge-triggered cell FDRE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) Path Group: mlkem_clk_clk_pll Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (mlkem_clk_clk_pll rise@0.000ns - sys_clk rise@0.000ns) Data Path Delay: 0.564ns (logic 0.390ns (69.198%) route 0.174ns (30.802%)) Logic Levels: 0 Clock Path Skew: 0.328ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.379ns Source Clock Delay (SCD): -0.608ns Clock Pessimism Removal (CPR): -0.099ns Clock Uncertainty: 0.197ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.136ns Phase Error (PE): 0.120ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9603, routed) 0.654 -0.608 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/ram_reg_0_7_18_23/WCLK SLICE_X52Y95 RAMD32 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/ram_reg_0_7_18_23/RAMC/CLK ------------------------------------------------------------------- ------------------- SLICE_X52Y95 RAMD32 (Prop_ramd32_CLK_O) 0.390 -0.218 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/ram_reg_0_7_18_23/RAMC/O net (fo=1, routed) 0.174 -0.045 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/_zz_ram_port10__0[22] SLICE_X52Y97 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/_zz_ram_port1_reg[22]/D ------------------------------------------------------------------- ------------------- (clock mlkem_clk_clk_pll rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout3_buf/O net (fo=25775, routed) 0.929 -0.379 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/mlkem_clk SLICE_X52Y97 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/_zz_ram_port1_reg[22]/C clock pessimism 0.099 -0.280 clock uncertainty 0.197 -0.084 SLICE_X52Y97 FDRE (Hold_fdre_C_D) -0.005 -0.089 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/_zz_ram_port1_reg[22] ------------------------------------------------------------------- required time 0.089 arrival time -0.045 ------------------------------------------------------------------- slack 0.044 Slack (MET) : 0.047ns (arrival time - required time) Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/ram_reg_0_7_30_35/RAMB/CLK (rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/_zz_ram_port1_reg[32]/D (rising edge-triggered cell FDRE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) Path Group: mlkem_clk_clk_pll Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (mlkem_clk_clk_pll rise@0.000ns - sys_clk rise@0.000ns) Data Path Delay: 0.569ns (logic 0.394ns (69.239%) route 0.175ns (30.761%)) Logic Levels: 0 Clock Path Skew: 0.328ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.379ns Source Clock Delay (SCD): -0.608ns Clock Pessimism Removal (CPR): -0.099ns Clock Uncertainty: 0.197ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.136ns Phase Error (PE): 0.120ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9603, routed) 0.654 -0.608 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/ram_reg_0_7_30_35/WCLK SLICE_X52Y96 RAMD32 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/ram_reg_0_7_30_35/RAMB/CLK ------------------------------------------------------------------- ------------------- SLICE_X52Y96 RAMD32 (Prop_ramd32_CLK_O) 0.394 -0.214 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/ram_reg_0_7_30_35/RAMB/O net (fo=1, routed) 0.175 -0.039 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/_zz_ram_port10__0[32] SLICE_X54Y98 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/_zz_ram_port1_reg[32]/D ------------------------------------------------------------------- ------------------- (clock mlkem_clk_clk_pll rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout3_buf/O net (fo=25775, routed) 0.929 -0.379 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/mlkem_clk SLICE_X54Y98 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/_zz_ram_port1_reg[32]/C clock pessimism 0.099 -0.280 clock uncertainty 0.197 -0.084 SLICE_X54Y98 FDRE (Hold_fdre_C_D) -0.003 -0.087 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/_zz_ram_port1_reg[32] ------------------------------------------------------------------- required time 0.087 arrival time -0.039 ------------------------------------------------------------------- slack 0.047 Slack (MET) : 0.049ns (arrival time - required time) Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/ram_reg_0_7_12_17/RAMB/CLK (rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/_zz_ram_port1_reg[14]/D (rising edge-triggered cell FDRE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) Path Group: mlkem_clk_clk_pll Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (mlkem_clk_clk_pll rise@0.000ns - sys_clk rise@0.000ns) Data Path Delay: 0.568ns (logic 0.394ns (69.353%) route 0.174ns (30.647%)) Logic Levels: 0 Clock Path Skew: 0.329ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.381ns Source Clock Delay (SCD): -0.611ns Clock Pessimism Removal (CPR): -0.099ns Clock Uncertainty: 0.197ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.136ns Phase Error (PE): 0.120ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9603, routed) 0.651 -0.611 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/ram_reg_0_7_12_17/WCLK SLICE_X60Y96 RAMD32 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/ram_reg_0_7_12_17/RAMB/CLK ------------------------------------------------------------------- ------------------- SLICE_X60Y96 RAMD32 (Prop_ramd32_CLK_O) 0.394 -0.217 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/ram_reg_0_7_12_17/RAMB/O net (fo=1, routed) 0.174 -0.043 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/_zz_ram_port10__0[14] SLICE_X61Y99 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/_zz_ram_port1_reg[14]/D ------------------------------------------------------------------- ------------------- (clock mlkem_clk_clk_pll rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout3_buf/O net (fo=25775, routed) 0.927 -0.381 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/mlkem_clk SLICE_X61Y99 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/_zz_ram_port1_reg[14]/C clock pessimism 0.099 -0.282 clock uncertainty 0.197 -0.086 SLICE_X61Y99 FDRE (Hold_fdre_C_D) -0.007 -0.093 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/_zz_ram_port1_reg[14] ------------------------------------------------------------------- required time 0.093 arrival time -0.043 ------------------------------------------------------------------- slack 0.049 Slack (MET) : 0.054ns (arrival time - required time) Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/ram_reg_0_7_24_29/RAMB/CLK (rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/_zz_ram_port1_reg[26]/D (rising edge-triggered cell FDRE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) Path Group: mlkem_clk_clk_pll Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (mlkem_clk_clk_pll rise@0.000ns - sys_clk rise@0.000ns) Data Path Delay: 0.574ns (logic 0.394ns (68.584%) route 0.180ns (31.416%)) Logic Levels: 0 Clock Path Skew: 0.327ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.379ns Source Clock Delay (SCD): -0.607ns Clock Pessimism Removal (CPR): -0.099ns Clock Uncertainty: 0.197ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.136ns Phase Error (PE): 0.120ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9603, routed) 0.655 -0.607 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/ram_reg_0_7_24_29/WCLK SLICE_X52Y98 RAMD32 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/ram_reg_0_7_24_29/RAMB/CLK ------------------------------------------------------------------- ------------------- SLICE_X52Y98 RAMD32 (Prop_ramd32_CLK_O) 0.394 -0.213 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/ram_reg_0_7_24_29/RAMB/O net (fo=1, routed) 0.180 -0.033 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/_zz_ram_port10__0[26] SLICE_X54Y98 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/_zz_ram_port1_reg[26]/D ------------------------------------------------------------------- ------------------- (clock mlkem_clk_clk_pll rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout3_buf/O net (fo=25775, routed) 0.929 -0.379 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/mlkem_clk SLICE_X54Y98 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/_zz_ram_port1_reg[26]/C clock pessimism 0.099 -0.280 clock uncertainty 0.197 -0.084 SLICE_X54Y98 FDRE (Hold_fdre_C_D) -0.003 -0.087 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/_zz_ram_port1_reg[26] ------------------------------------------------------------------- required time 0.087 arrival time -0.033 ------------------------------------------------------------------- slack 0.054 Slack (MET) : 0.054ns (arrival time - required time) Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/ram_reg_0_7_6_11/RAMA_D1/CLK (rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/_zz_ram_port1_reg[7]/D (rising edge-triggered cell FDRE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) Path Group: mlkem_clk_clk_pll Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (mlkem_clk_clk_pll rise@0.000ns - sys_clk rise@0.000ns) Data Path Delay: 0.651ns (logic 0.478ns (73.473%) route 0.173ns (26.527%)) Logic Levels: 0 Clock Path Skew: 0.328ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.381ns Source Clock Delay (SCD): -0.610ns Clock Pessimism Removal (CPR): -0.099ns Clock Uncertainty: 0.197ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.136ns Phase Error (PE): 0.120ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9603, routed) 0.652 -0.610 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/ram_reg_0_7_6_11/WCLK SLICE_X60Y98 RAMD32 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/ram_reg_0_7_6_11/RAMA_D1/CLK ------------------------------------------------------------------- ------------------- SLICE_X60Y98 RAMD32 (Prop_ramd32_CLK_O) 0.478 -0.132 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/ram_reg_0_7_6_11/RAMA_D1/O net (fo=1, routed) 0.173 0.040 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/_zz_ram_port10__0[7] SLICE_X61Y98 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/_zz_ram_port1_reg[7]/D ------------------------------------------------------------------- ------------------- (clock mlkem_clk_clk_pll rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout3_buf/O net (fo=25775, routed) 0.927 -0.381 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/mlkem_clk SLICE_X61Y98 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/_zz_ram_port1_reg[7]/C clock pessimism 0.099 -0.282 clock uncertainty 0.197 -0.086 SLICE_X61Y98 FDRE (Hold_fdre_C_D) 0.072 -0.014 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/_zz_ram_port1_reg[7] ------------------------------------------------------------------- required time 0.014 arrival time 0.040 ------------------------------------------------------------------- slack 0.054 Slack (MET) : 0.056ns (arrival time - required time) Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/ram_reg_0_7_0_5/RAMB/CLK (rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/_zz_ram_port1_reg[2]/D (rising edge-triggered cell FDRE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) Path Group: mlkem_clk_clk_pll Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (mlkem_clk_clk_pll rise@0.000ns - sys_clk rise@0.000ns) Data Path Delay: 0.575ns (logic 0.394ns (68.577%) route 0.181ns (31.423%)) Logic Levels: 0 Clock Path Skew: 0.329ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.381ns Source Clock Delay (SCD): -0.611ns Clock Pessimism Removal (CPR): -0.099ns Clock Uncertainty: 0.197ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.136ns Phase Error (PE): 0.120ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9603, routed) 0.651 -0.611 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/ram_reg_0_7_0_5/WCLK SLICE_X60Y95 RAMD32 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/ram_reg_0_7_0_5/RAMB/CLK ------------------------------------------------------------------- ------------------- SLICE_X60Y95 RAMD32 (Prop_ramd32_CLK_O) 0.394 -0.217 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/ram_reg_0_7_0_5/RAMB/O net (fo=1, routed) 0.181 -0.037 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/_zz_ram_port10__0[2] SLICE_X61Y97 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/_zz_ram_port1_reg[2]/D ------------------------------------------------------------------- ------------------- (clock mlkem_clk_clk_pll rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout3_buf/O net (fo=25775, routed) 0.927 -0.381 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/mlkem_clk SLICE_X61Y97 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/_zz_ram_port1_reg[2]/C clock pessimism 0.099 -0.282 clock uncertainty 0.197 -0.086 SLICE_X61Y97 FDRE (Hold_fdre_C_D) -0.007 -0.093 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/_zz_ram_port1_reg[2] ------------------------------------------------------------------- required time 0.093 arrival time -0.037 ------------------------------------------------------------------- slack 0.056 Slack (MET) : 0.065ns (arrival time - required time) Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/ram_reg_0_7_30_35/RAMC/CLK (rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/_zz_ram_port1_reg[34]/D (rising edge-triggered cell FDRE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) Path Group: mlkem_clk_clk_pll Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (mlkem_clk_clk_pll rise@0.000ns - sys_clk rise@0.000ns) Data Path Delay: 0.591ns (logic 0.390ns (65.936%) route 0.201ns (34.064%)) Logic Levels: 0 Clock Path Skew: 0.328ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.379ns Source Clock Delay (SCD): -0.608ns Clock Pessimism Removal (CPR): -0.099ns Clock Uncertainty: 0.197ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.136ns Phase Error (PE): 0.120ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9603, routed) 0.654 -0.608 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/ram_reg_0_7_30_35/WCLK SLICE_X52Y96 RAMD32 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/ram_reg_0_7_30_35/RAMC/CLK ------------------------------------------------------------------- ------------------- SLICE_X52Y96 RAMD32 (Prop_ramd32_CLK_O) 0.390 -0.218 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/ram_reg_0_7_30_35/RAMC/O net (fo=1, routed) 0.201 -0.017 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/_zz_ram_port10__0[34] SLICE_X53Y97 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/_zz_ram_port1_reg[34]/D ------------------------------------------------------------------- ------------------- (clock mlkem_clk_clk_pll rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout3_buf/O net (fo=25775, routed) 0.929 -0.379 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/mlkem_clk SLICE_X53Y97 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/_zz_ram_port1_reg[34]/C clock pessimism 0.099 -0.280 clock uncertainty 0.197 -0.084 SLICE_X53Y97 FDRE (Hold_fdre_C_D) 0.002 -0.082 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/_zz_ram_port1_reg[34] ------------------------------------------------------------------- required time 0.082 arrival time -0.017 ------------------------------------------------------------------- slack 0.065 Slack (MET) : 0.071ns (arrival time - required time) Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/ram_reg_0_7_18_23/RAMB/CLK (rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/_zz_ram_port1_reg[20]/D (rising edge-triggered cell FDRE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) Path Group: mlkem_clk_clk_pll Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (mlkem_clk_clk_pll rise@0.000ns - sys_clk rise@0.000ns) Data Path Delay: 0.575ns (logic 0.394ns (68.577%) route 0.181ns (31.423%)) Logic Levels: 0 Clock Path Skew: 0.328ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.379ns Source Clock Delay (SCD): -0.608ns Clock Pessimism Removal (CPR): -0.099ns Clock Uncertainty: 0.197ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.136ns Phase Error (PE): 0.120ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9603, routed) 0.654 -0.608 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/ram_reg_0_7_18_23/WCLK SLICE_X52Y95 RAMD32 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/ram_reg_0_7_18_23/RAMB/CLK ------------------------------------------------------------------- ------------------- SLICE_X52Y95 RAMD32 (Prop_ramd32_CLK_O) 0.394 -0.214 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/ram_reg_0_7_18_23/RAMB/O net (fo=1, routed) 0.181 -0.034 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/_zz_ram_port10__0[20] SLICE_X52Y97 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/_zz_ram_port1_reg[20]/D ------------------------------------------------------------------- ------------------- (clock mlkem_clk_clk_pll rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout3_buf/O net (fo=25775, routed) 0.929 -0.379 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/mlkem_clk SLICE_X52Y97 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/_zz_ram_port1_reg[20]/C clock pessimism 0.099 -0.280 clock uncertainty 0.197 -0.084 SLICE_X52Y97 FDRE (Hold_fdre_C_D) -0.021 -0.105 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/_zz_ram_port1_reg[20] ------------------------------------------------------------------- required time 0.105 arrival time -0.034 ------------------------------------------------------------------- slack 0.071 Slack (MET) : 0.101ns (arrival time - required time) Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/ram_reg_0_7_12_17/RAMA/CLK (rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/_zz_ram_port1_reg[12]/D (rising edge-triggered cell FDRE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) Path Group: mlkem_clk_clk_pll Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (mlkem_clk_clk_pll rise@0.000ns - sys_clk rise@0.000ns) Data Path Delay: 0.607ns (logic 0.492ns (81.071%) route 0.115ns (18.929%)) Logic Levels: 0 Clock Path Skew: 0.329ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.381ns Source Clock Delay (SCD): -0.611ns Clock Pessimism Removal (CPR): -0.099ns Clock Uncertainty: 0.197ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.136ns Phase Error (PE): 0.120ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9603, routed) 0.651 -0.611 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/ram_reg_0_7_12_17/WCLK SLICE_X60Y96 RAMD32 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/ram_reg_0_7_12_17/RAMA/CLK ------------------------------------------------------------------- ------------------- SLICE_X60Y96 RAMD32 (Prop_ramd32_CLK_O) 0.492 -0.119 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/ram_reg_0_7_12_17/RAMA/O net (fo=1, routed) 0.115 -0.004 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/_zz_ram_port10__0[12] SLICE_X61Y98 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/_zz_ram_port1_reg[12]/D ------------------------------------------------------------------- ------------------- (clock mlkem_clk_clk_pll rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout3_buf/O net (fo=25775, routed) 0.927 -0.381 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/mlkem_clk SLICE_X61Y98 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/_zz_ram_port1_reg[12]/C clock pessimism 0.099 -0.282 clock uncertainty 0.197 -0.086 SLICE_X61Y98 FDRE (Hold_fdre_C_D) -0.020 -0.106 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/_zz_ram_port1_reg[12] ------------------------------------------------------------------- required time 0.106 arrival time -0.004 ------------------------------------------------------------------- slack 0.101 Slack (MET) : 0.115ns (arrival time - required time) Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/ram_reg_0_7_24_29/RAMA_D1/CLK (rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/_zz_ram_port1_reg[25]/D (rising edge-triggered cell FDRE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) Path Group: mlkem_clk_clk_pll Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (mlkem_clk_clk_pll rise@0.000ns - sys_clk rise@0.000ns) Data Path Delay: 0.708ns (logic 0.478ns (67.468%) route 0.230ns (32.532%)) Logic Levels: 0 Clock Path Skew: 0.327ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.379ns Source Clock Delay (SCD): -0.607ns Clock Pessimism Removal (CPR): -0.099ns Clock Uncertainty: 0.197ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.136ns Phase Error (PE): 0.120ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9603, routed) 0.655 -0.607 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/ram_reg_0_7_24_29/WCLK SLICE_X52Y98 RAMD32 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/ram_reg_0_7_24_29/RAMA_D1/CLK ------------------------------------------------------------------- ------------------- SLICE_X52Y98 RAMD32 (Prop_ramd32_CLK_O) 0.478 -0.129 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/ram_reg_0_7_24_29/RAMA_D1/O net (fo=1, routed) 0.230 0.101 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/_zz_ram_port10__0[25] SLICE_X55Y98 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/_zz_ram_port1_reg[25]/D ------------------------------------------------------------------- ------------------- (clock mlkem_clk_clk_pll rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout3_buf/O net (fo=25775, routed) 0.929 -0.379 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/mlkem_clk SLICE_X55Y98 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/_zz_ram_port1_reg[25]/C clock pessimism 0.099 -0.280 clock uncertainty 0.197 -0.084 SLICE_X55Y98 FDRE (Hold_fdre_C_D) 0.070 -0.014 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/_zz_ram_port1_reg[25] ------------------------------------------------------------------- required time 0.014 arrival time 0.101 ------------------------------------------------------------------- slack 0.115 Slack (MET) : 0.117ns (arrival time - required time) Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_0_5/RAMB_D1/CLK (rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/_zz_ram_port1_reg[3]/D (rising edge-triggered cell FDRE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) Path Group: mlkem_clk_clk_pll Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (mlkem_clk_clk_pll rise@0.000ns - sys_clk rise@0.000ns) Data Path Delay: 0.712ns (logic 0.388ns (54.475%) route 0.324ns (45.525%)) Logic Levels: 0 Clock Path Skew: 0.333ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.380ns Source Clock Delay (SCD): -0.614ns Clock Pessimism Removal (CPR): -0.099ns Clock Uncertainty: 0.197ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.136ns Phase Error (PE): 0.120ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9603, routed) 0.648 -0.614 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_0_5/WCLK SLICE_X48Y82 RAMD32 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_0_5/RAMB_D1/CLK ------------------------------------------------------------------- ------------------- SLICE_X48Y82 RAMD32 (Prop_ramd32_CLK_O) 0.388 -0.226 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_0_5/RAMB_D1/O net (fo=1, routed) 0.324 0.098 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/_zz_ram_port10__2[3] SLICE_X51Y94 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/_zz_ram_port1_reg[3]/D ------------------------------------------------------------------- ------------------- (clock mlkem_clk_clk_pll rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout3_buf/O net (fo=25775, routed) 0.928 -0.380 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/mlkem_clk SLICE_X51Y94 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/_zz_ram_port1_reg[3]/C clock pessimism 0.099 -0.281 clock uncertainty 0.197 -0.085 SLICE_X51Y94 FDRE (Hold_fdre_C_D) 0.066 -0.019 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/_zz_ram_port1_reg[3] ------------------------------------------------------------------- required time 0.019 arrival time 0.098 ------------------------------------------------------------------- slack 0.117 Slack (MET) : 0.120ns (arrival time - required time) Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/ram_reg_0_7_24_29/RAMA/CLK (rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/_zz_ram_port1_reg[24]/D (rising edge-triggered cell FDRE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) Path Group: mlkem_clk_clk_pll Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (mlkem_clk_clk_pll rise@0.000ns - sys_clk rise@0.000ns) Data Path Delay: 0.633ns (logic 0.492ns (77.772%) route 0.141ns (22.228%)) Logic Levels: 0 Clock Path Skew: 0.327ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.379ns Source Clock Delay (SCD): -0.607ns Clock Pessimism Removal (CPR): -0.099ns Clock Uncertainty: 0.197ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.136ns Phase Error (PE): 0.120ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9603, routed) 0.655 -0.607 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/ram_reg_0_7_24_29/WCLK SLICE_X52Y98 RAMD32 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/ram_reg_0_7_24_29/RAMA/CLK ------------------------------------------------------------------- ------------------- SLICE_X52Y98 RAMD32 (Prop_ramd32_CLK_O) 0.492 -0.115 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/ram_reg_0_7_24_29/RAMA/O net (fo=1, routed) 0.141 0.025 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/_zz_ram_port10__0[24] SLICE_X53Y99 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/_zz_ram_port1_reg[24]/D ------------------------------------------------------------------- ------------------- (clock mlkem_clk_clk_pll rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout3_buf/O net (fo=25775, routed) 0.929 -0.379 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/mlkem_clk SLICE_X53Y99 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/_zz_ram_port1_reg[24]/C clock pessimism 0.099 -0.280 clock uncertainty 0.197 -0.084 SLICE_X53Y99 FDRE (Hold_fdre_C_D) -0.011 -0.095 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/_zz_ram_port1_reg[24] ------------------------------------------------------------------- required time 0.095 arrival time 0.025 ------------------------------------------------------------------- slack 0.120 Slack (MET) : 0.126ns (arrival time - required time) Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/ram_reg_0_7_18_23/RAMB_D1/CLK (rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/_zz_ram_port1_reg[21]/D (rising edge-triggered cell FDRE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) Path Group: mlkem_clk_clk_pll Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (mlkem_clk_clk_pll rise@0.000ns - sys_clk rise@0.000ns) Data Path Delay: 0.709ns (logic 0.388ns (54.687%) route 0.321ns (45.313%)) Logic Levels: 0 Clock Path Skew: 0.328ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.379ns Source Clock Delay (SCD): -0.608ns Clock Pessimism Removal (CPR): -0.099ns Clock Uncertainty: 0.197ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.136ns Phase Error (PE): 0.120ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9603, routed) 0.654 -0.608 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/ram_reg_0_7_18_23/WCLK SLICE_X52Y95 RAMD32 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/ram_reg_0_7_18_23/RAMB_D1/CLK ------------------------------------------------------------------- ------------------- SLICE_X52Y95 RAMD32 (Prop_ramd32_CLK_O) 0.388 -0.220 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/ram_reg_0_7_18_23/RAMB_D1/O net (fo=1, routed) 0.321 0.101 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/_zz_ram_port10__0[21] SLICE_X53Y99 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/_zz_ram_port1_reg[21]/D ------------------------------------------------------------------- ------------------- (clock mlkem_clk_clk_pll rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout3_buf/O net (fo=25775, routed) 0.929 -0.379 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/mlkem_clk SLICE_X53Y99 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/_zz_ram_port1_reg[21]/C clock pessimism 0.099 -0.280 clock uncertainty 0.197 -0.084 SLICE_X53Y99 FDRE (Hold_fdre_C_D) 0.059 -0.025 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/_zz_ram_port1_reg[21] ------------------------------------------------------------------- required time 0.025 arrival time 0.101 ------------------------------------------------------------------- slack 0.126 Slack (MET) : 0.126ns (arrival time - required time) Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_6_11/RAMB_D1/CLK (rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/_zz_ram_port1_reg[9]/D (rising edge-triggered cell FDRE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) Path Group: mlkem_clk_clk_pll Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (mlkem_clk_clk_pll rise@0.000ns - sys_clk rise@0.000ns) Data Path Delay: 0.727ns (logic 0.388ns (53.370%) route 0.339ns (46.630%)) Logic Levels: 0 Clock Path Skew: 0.332ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.380ns Source Clock Delay (SCD): -0.613ns Clock Pessimism Removal (CPR): -0.099ns Clock Uncertainty: 0.197ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.136ns Phase Error (PE): 0.120ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9603, routed) 0.649 -0.613 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_6_11/WCLK SLICE_X48Y83 RAMD32 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_6_11/RAMB_D1/CLK ------------------------------------------------------------------- ------------------- SLICE_X48Y83 RAMD32 (Prop_ramd32_CLK_O) 0.388 -0.225 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_6_11/RAMB_D1/O net (fo=1, routed) 0.339 0.114 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/_zz_ram_port10__2[9] SLICE_X50Y94 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/_zz_ram_port1_reg[9]/D ------------------------------------------------------------------- ------------------- (clock mlkem_clk_clk_pll rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout3_buf/O net (fo=25775, routed) 0.928 -0.380 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/mlkem_clk SLICE_X50Y94 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/_zz_ram_port1_reg[9]/C clock pessimism 0.099 -0.281 clock uncertainty 0.197 -0.085 SLICE_X50Y94 FDRE (Hold_fdre_C_D) 0.072 -0.013 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/_zz_ram_port1_reg[9] ------------------------------------------------------------------- required time 0.013 arrival time 0.114 ------------------------------------------------------------------- slack 0.126 Slack (MET) : 0.130ns (arrival time - required time) Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/ram_reg_0_7_30_35/RAMA_D1/CLK (rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/_zz_ram_port1_reg[31]/D (rising edge-triggered cell FDRE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) Path Group: mlkem_clk_clk_pll Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (mlkem_clk_clk_pll rise@0.000ns - sys_clk rise@0.000ns) Data Path Delay: 0.721ns (logic 0.478ns (66.314%) route 0.243ns (33.686%)) Logic Levels: 0 Clock Path Skew: 0.328ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.379ns Source Clock Delay (SCD): -0.608ns Clock Pessimism Removal (CPR): -0.099ns Clock Uncertainty: 0.197ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.136ns Phase Error (PE): 0.120ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9603, routed) 0.654 -0.608 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/ram_reg_0_7_30_35/WCLK SLICE_X52Y96 RAMD32 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/ram_reg_0_7_30_35/RAMA_D1/CLK ------------------------------------------------------------------- ------------------- SLICE_X52Y96 RAMD32 (Prop_ramd32_CLK_O) 0.478 -0.130 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/ram_reg_0_7_30_35/RAMA_D1/O net (fo=1, routed) 0.243 0.112 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/_zz_ram_port10__0[31] SLICE_X53Y98 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/_zz_ram_port1_reg[31]/D ------------------------------------------------------------------- ------------------- (clock mlkem_clk_clk_pll rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout3_buf/O net (fo=25775, routed) 0.929 -0.379 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/mlkem_clk SLICE_X53Y98 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/_zz_ram_port1_reg[31]/C clock pessimism 0.099 -0.280 clock uncertainty 0.197 -0.084 SLICE_X53Y98 FDRE (Hold_fdre_C_D) 0.066 -0.018 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/_zz_ram_port1_reg[31] ------------------------------------------------------------------- required time 0.018 arrival time 0.112 ------------------------------------------------------------------- slack 0.130 Slack (MET) : 0.138ns (arrival time - required time) Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/pushCC_pushPtrGray_reg[1]/C (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/pushToPopGray_buffercc/buffers_0_reg[1]/D (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) Path Group: mlkem_clk_clk_pll Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (mlkem_clk_clk_pll rise@0.000ns - sys_clk rise@0.000ns) Data Path Delay: 0.706ns (logic 0.141ns (19.966%) route 0.565ns (80.034%)) Logic Levels: 0 Clock Path Skew: 0.325ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.388ns Source Clock Delay (SCD): -0.614ns Clock Pessimism Removal (CPR): -0.099ns Clock Uncertainty: 0.197ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.136ns Phase Error (PE): 0.120ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9603, routed) 0.648 -0.614 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/sys_clk SLICE_X49Y82 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/pushCC_pushPtrGray_reg[1]/C ------------------------------------------------------------------- ------------------- SLICE_X49Y82 FDCE (Prop_fdce_C_Q) 0.141 -0.473 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/pushCC_pushPtrGray_reg[1]/Q net (fo=2, routed) 0.565 0.092 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/pushToPopGray_buffercc/Q[1] SLICE_X69Y91 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/pushToPopGray_buffercc/buffers_0_reg[1]/D ------------------------------------------------------------------- ------------------- (clock mlkem_clk_clk_pll rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout3_buf/O net (fo=25775, routed) 0.920 -0.388 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/pushToPopGray_buffercc/mlkem_clk SLICE_X69Y91 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/pushToPopGray_buffercc/buffers_0_reg[1]/C clock pessimism 0.099 -0.289 clock uncertainty 0.197 -0.093 SLICE_X69Y91 FDCE (Hold_fdce_C_D) 0.047 -0.046 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/pushToPopGray_buffercc/buffers_0_reg[1] ------------------------------------------------------------------- required time 0.046 arrival time 0.092 ------------------------------------------------------------------- slack 0.138 Slack (MET) : 0.140ns (arrival time - required time) Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/ram_reg_0_7_0_5/RAMA_D1/CLK (rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/_zz_ram_port1_reg[1]/D (rising edge-triggered cell FDRE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) Path Group: mlkem_clk_clk_pll Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (mlkem_clk_clk_pll rise@0.000ns - sys_clk rise@0.000ns) Data Path Delay: 0.735ns (logic 0.478ns (64.996%) route 0.257ns (35.004%)) Logic Levels: 0 Clock Path Skew: 0.329ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.381ns Source Clock Delay (SCD): -0.611ns Clock Pessimism Removal (CPR): -0.099ns Clock Uncertainty: 0.197ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.136ns Phase Error (PE): 0.120ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9603, routed) 0.651 -0.611 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/ram_reg_0_7_0_5/WCLK SLICE_X60Y95 RAMD32 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/ram_reg_0_7_0_5/RAMA_D1/CLK ------------------------------------------------------------------- ------------------- SLICE_X60Y95 RAMD32 (Prop_ramd32_CLK_O) 0.478 -0.133 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/ram_reg_0_7_0_5/RAMA_D1/O net (fo=1, routed) 0.257 0.124 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/_zz_ram_port10__0[1] SLICE_X61Y97 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/_zz_ram_port1_reg[1]/D ------------------------------------------------------------------- ------------------- (clock mlkem_clk_clk_pll rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout3_buf/O net (fo=25775, routed) 0.927 -0.381 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/mlkem_clk SLICE_X61Y97 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/_zz_ram_port1_reg[1]/C clock pessimism 0.099 -0.282 clock uncertainty 0.197 -0.086 SLICE_X61Y97 FDRE (Hold_fdre_C_D) 0.070 -0.016 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/_zz_ram_port1_reg[1] ------------------------------------------------------------------- required time 0.016 arrival time 0.124 ------------------------------------------------------------------- slack 0.140 Slack (MET) : 0.142ns (arrival time - required time) Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_6_11/RAMB/CLK (rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/_zz_ram_port1_reg[8]/D (rising edge-triggered cell FDRE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) Path Group: mlkem_clk_clk_pll Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (mlkem_clk_clk_pll rise@0.000ns - sys_clk rise@0.000ns) Data Path Delay: 0.667ns (logic 0.394ns (59.045%) route 0.273ns (40.955%)) Logic Levels: 0 Clock Path Skew: 0.332ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.380ns Source Clock Delay (SCD): -0.613ns Clock Pessimism Removal (CPR): -0.099ns Clock Uncertainty: 0.197ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.136ns Phase Error (PE): 0.120ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9603, routed) 0.649 -0.613 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_6_11/WCLK SLICE_X48Y83 RAMD32 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_6_11/RAMB/CLK ------------------------------------------------------------------- ------------------- SLICE_X48Y83 RAMD32 (Prop_ramd32_CLK_O) 0.394 -0.219 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_6_11/RAMB/O net (fo=1, routed) 0.273 0.054 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/_zz_ram_port10__2[8] SLICE_X50Y94 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/_zz_ram_port1_reg[8]/D ------------------------------------------------------------------- ------------------- (clock mlkem_clk_clk_pll rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout3_buf/O net (fo=25775, routed) 0.928 -0.380 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/mlkem_clk SLICE_X50Y94 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/_zz_ram_port1_reg[8]/C clock pessimism 0.099 -0.281 clock uncertainty 0.197 -0.085 SLICE_X50Y94 FDRE (Hold_fdre_C_D) -0.003 -0.088 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/_zz_ram_port1_reg[8] ------------------------------------------------------------------- required time 0.088 arrival time 0.054 ------------------------------------------------------------------- slack 0.142 Slack (MET) : 0.143ns (arrival time - required time) Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/ram_reg_0_7_30_35/RAMA/CLK (rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/_zz_ram_port1_reg[30]/D (rising edge-triggered cell FDRE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) Path Group: mlkem_clk_clk_pll Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (mlkem_clk_clk_pll rise@0.000ns - sys_clk rise@0.000ns) Data Path Delay: 0.668ns (logic 0.492ns (73.684%) route 0.176ns (26.316%)) Logic Levels: 0 Clock Path Skew: 0.328ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.379ns Source Clock Delay (SCD): -0.608ns Clock Pessimism Removal (CPR): -0.099ns Clock Uncertainty: 0.197ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.136ns Phase Error (PE): 0.120ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9603, routed) 0.654 -0.608 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/ram_reg_0_7_30_35/WCLK SLICE_X52Y96 RAMD32 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/ram_reg_0_7_30_35/RAMA/CLK ------------------------------------------------------------------- ------------------- SLICE_X52Y96 RAMD32 (Prop_ramd32_CLK_O) 0.492 -0.116 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/ram_reg_0_7_30_35/RAMA/O net (fo=1, routed) 0.176 0.059 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/_zz_ram_port10__0[30] SLICE_X53Y97 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/_zz_ram_port1_reg[30]/D ------------------------------------------------------------------- ------------------- (clock mlkem_clk_clk_pll rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout3_buf/O net (fo=25775, routed) 0.929 -0.379 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/mlkem_clk SLICE_X53Y97 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/_zz_ram_port1_reg[30]/C clock pessimism 0.099 -0.280 clock uncertainty 0.197 -0.084 SLICE_X53Y97 FDRE (Hold_fdre_C_D) 0.000 -0.084 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/_zz_ram_port1_reg[30] ------------------------------------------------------------------- required time 0.084 arrival time 0.059 ------------------------------------------------------------------- slack 0.143 Slack (MET) : 0.149ns (arrival time - required time) Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/ram_reg_0_7_30_35/RAMB_D1/CLK (rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/_zz_ram_port1_reg[33]/D (rising edge-triggered cell FDRE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) Path Group: mlkem_clk_clk_pll Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (mlkem_clk_clk_pll rise@0.000ns - sys_clk rise@0.000ns) Data Path Delay: 0.746ns (logic 0.388ns (52.040%) route 0.358ns (47.960%)) Logic Levels: 0 Clock Path Skew: 0.328ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.379ns Source Clock Delay (SCD): -0.608ns Clock Pessimism Removal (CPR): -0.099ns Clock Uncertainty: 0.197ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.136ns Phase Error (PE): 0.120ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9603, routed) 0.654 -0.608 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/ram_reg_0_7_30_35/WCLK SLICE_X52Y96 RAMD32 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/ram_reg_0_7_30_35/RAMB_D1/CLK ------------------------------------------------------------------- ------------------- SLICE_X52Y96 RAMD32 (Prop_ramd32_CLK_O) 0.388 -0.220 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/ram_reg_0_7_30_35/RAMB_D1/O net (fo=1, routed) 0.358 0.137 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/_zz_ram_port10__0[33] SLICE_X54Y98 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/_zz_ram_port1_reg[33]/D ------------------------------------------------------------------- ------------------- (clock mlkem_clk_clk_pll rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout3_buf/O net (fo=25775, routed) 0.929 -0.379 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/mlkem_clk SLICE_X54Y98 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/_zz_ram_port1_reg[33]/C clock pessimism 0.099 -0.280 clock uncertainty 0.197 -0.084 SLICE_X54Y98 FDRE (Hold_fdre_C_D) 0.072 -0.012 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/_zz_ram_port1_reg[33] ------------------------------------------------------------------- required time 0.012 arrival time 0.137 ------------------------------------------------------------------- slack 0.149 Slack (MET) : 0.150ns (arrival time - required time) Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/pushCC_pushPtrGray_reg[2]/C (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/pushToPopGray_buffercc/buffers_0_reg[2]/D (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) Path Group: mlkem_clk_clk_pll Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (mlkem_clk_clk_pll rise@0.000ns - sys_clk rise@0.000ns) Data Path Delay: 0.665ns (logic 0.128ns (19.253%) route 0.537ns (80.747%)) Logic Levels: 0 Clock Path Skew: 0.325ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.388ns Source Clock Delay (SCD): -0.614ns Clock Pessimism Removal (CPR): -0.099ns Clock Uncertainty: 0.197ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.136ns Phase Error (PE): 0.120ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9603, routed) 0.648 -0.614 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/sys_clk SLICE_X49Y82 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/pushCC_pushPtrGray_reg[2]/C ------------------------------------------------------------------- ------------------- SLICE_X49Y82 FDCE (Prop_fdce_C_Q) 0.128 -0.486 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/pushCC_pushPtrGray_reg[2]/Q net (fo=4, routed) 0.537 0.050 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/pushToPopGray_buffercc/buffers_0_reg[2]_0 SLICE_X69Y91 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/pushToPopGray_buffercc/buffers_0_reg[2]/D ------------------------------------------------------------------- ------------------- (clock mlkem_clk_clk_pll rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout3_buf/O net (fo=25775, routed) 0.920 -0.388 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/pushToPopGray_buffercc/mlkem_clk SLICE_X69Y91 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/pushToPopGray_buffercc/buffers_0_reg[2]/C clock pessimism 0.099 -0.289 clock uncertainty 0.197 -0.093 SLICE_X69Y91 FDCE (Hold_fdce_C_D) -0.007 -0.100 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/pushToPopGray_buffercc/buffers_0_reg[2] ------------------------------------------------------------------- required time 0.100 arrival time 0.050 ------------------------------------------------------------------- slack 0.150 Slack (MET) : 0.161ns (arrival time - required time) Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/pushCC_pushPtrGray_reg[0]/C (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/pushToPopGray_buffercc/buffers_0_reg[0]/D (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) Path Group: mlkem_clk_clk_pll Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (mlkem_clk_clk_pll rise@0.000ns - sys_clk rise@0.000ns) Data Path Delay: 0.729ns (logic 0.141ns (19.353%) route 0.588ns (80.647%)) Logic Levels: 0 Clock Path Skew: 0.325ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.388ns Source Clock Delay (SCD): -0.614ns Clock Pessimism Removal (CPR): -0.099ns Clock Uncertainty: 0.197ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.136ns Phase Error (PE): 0.120ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9603, routed) 0.648 -0.614 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/sys_clk SLICE_X49Y82 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/pushCC_pushPtrGray_reg[0]/C ------------------------------------------------------------------- ------------------- SLICE_X49Y82 FDCE (Prop_fdce_C_Q) 0.141 -0.473 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/pushCC_pushPtrGray_reg[0]/Q net (fo=2, routed) 0.588 0.114 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/pushToPopGray_buffercc/Q[0] SLICE_X69Y91 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/pushToPopGray_buffercc/buffers_0_reg[0]/D ------------------------------------------------------------------- ------------------- (clock mlkem_clk_clk_pll rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout3_buf/O net (fo=25775, routed) 0.920 -0.388 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/pushToPopGray_buffercc/mlkem_clk SLICE_X69Y91 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/pushToPopGray_buffercc/buffers_0_reg[0]/C clock pessimism 0.099 -0.289 clock uncertainty 0.197 -0.093 SLICE_X69Y91 FDCE (Hold_fdce_C_D) 0.046 -0.047 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/pushToPopGray_buffercc/buffers_0_reg[0] ------------------------------------------------------------------- required time 0.047 arrival time 0.114 ------------------------------------------------------------------- slack 0.161 Slack (MET) : 0.164ns (arrival time - required time) Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/popCC_ptrToPush_reg[2]/C (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/popToPushGray_buffercc/buffers_0_reg[2]/D (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) Path Group: mlkem_clk_clk_pll Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (mlkem_clk_clk_pll rise@0.000ns - sys_clk rise@0.000ns) Data Path Delay: 0.681ns (logic 0.128ns (18.783%) route 0.553ns (81.217%)) Logic Levels: 0 Clock Path Skew: 0.328ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.387ns Source Clock Delay (SCD): -0.616ns Clock Pessimism Removal (CPR): -0.099ns Clock Uncertainty: 0.197ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.136ns Phase Error (PE): 0.120ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9603, routed) 0.646 -0.616 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/sys_clk SLICE_X67Y94 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/popCC_ptrToPush_reg[2]/C ------------------------------------------------------------------- ------------------- SLICE_X67Y94 FDCE (Prop_fdce_C_Q) 0.128 -0.488 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/popCC_ptrToPush_reg[2]/Q net (fo=1, routed) 0.553 0.065 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/popToPushGray_buffercc/Q[2] SLICE_X67Y95 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/popToPushGray_buffercc/buffers_0_reg[2]/D ------------------------------------------------------------------- ------------------- (clock mlkem_clk_clk_pll rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout3_buf/O net (fo=25775, routed) 0.921 -0.387 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/popToPushGray_buffercc/mlkem_clk SLICE_X67Y95 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/popToPushGray_buffercc/buffers_0_reg[2]/C clock pessimism 0.099 -0.288 clock uncertainty 0.197 -0.092 SLICE_X67Y95 FDCE (Hold_fdce_C_D) -0.007 -0.099 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/popToPushGray_buffercc/buffers_0_reg[2] ------------------------------------------------------------------- required time 0.099 arrival time 0.065 ------------------------------------------------------------------- slack 0.164 Slack (MET) : 0.164ns (arrival time - required time) Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/popCC_ptrToPush_reg[1]/C (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/popToPushGray_buffercc/buffers_0_reg[1]/D (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) Path Group: mlkem_clk_clk_pll Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (mlkem_clk_clk_pll rise@0.000ns - sys_clk rise@0.000ns) Data Path Delay: 0.736ns (logic 0.141ns (19.154%) route 0.595ns (80.846%)) Logic Levels: 0 Clock Path Skew: 0.328ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.387ns Source Clock Delay (SCD): -0.616ns Clock Pessimism Removal (CPR): -0.099ns Clock Uncertainty: 0.197ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.136ns Phase Error (PE): 0.120ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9603, routed) 0.646 -0.616 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/sys_clk SLICE_X67Y94 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/popCC_ptrToPush_reg[1]/C ------------------------------------------------------------------- ------------------- SLICE_X67Y94 FDCE (Prop_fdce_C_Q) 0.141 -0.475 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/popCC_ptrToPush_reg[1]/Q net (fo=1, routed) 0.595 0.120 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/popToPushGray_buffercc/Q[1] SLICE_X67Y95 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/popToPushGray_buffercc/buffers_0_reg[1]/D ------------------------------------------------------------------- ------------------- (clock mlkem_clk_clk_pll rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout3_buf/O net (fo=25775, routed) 0.921 -0.387 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/popToPushGray_buffercc/mlkem_clk SLICE_X67Y95 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/popToPushGray_buffercc/buffers_0_reg[1]/C clock pessimism 0.099 -0.288 clock uncertainty 0.197 -0.092 SLICE_X67Y95 FDCE (Hold_fdce_C_D) 0.047 -0.045 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/popToPushGray_buffercc/buffers_0_reg[1] ------------------------------------------------------------------- required time 0.045 arrival time 0.120 ------------------------------------------------------------------- slack 0.164 Slack (MET) : 0.179ns (arrival time - required time) Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/popCC_ptrToPush_reg[0]/C (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/popToPushGray_buffercc/buffers_0_reg[0]/D (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) Path Group: mlkem_clk_clk_pll Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (mlkem_clk_clk_pll rise@0.000ns - sys_clk rise@0.000ns) Data Path Delay: 0.750ns (logic 0.141ns (18.805%) route 0.609ns (81.195%)) Logic Levels: 0 Clock Path Skew: 0.328ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.387ns Source Clock Delay (SCD): -0.616ns Clock Pessimism Removal (CPR): -0.099ns Clock Uncertainty: 0.197ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.136ns Phase Error (PE): 0.120ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9603, routed) 0.646 -0.616 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/sys_clk SLICE_X67Y94 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/popCC_ptrToPush_reg[0]/C ------------------------------------------------------------------- ------------------- SLICE_X67Y94 FDCE (Prop_fdce_C_Q) 0.141 -0.475 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/popCC_ptrToPush_reg[0]/Q net (fo=1, routed) 0.609 0.133 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/popToPushGray_buffercc/Q[0] SLICE_X67Y95 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/popToPushGray_buffercc/buffers_0_reg[0]/D ------------------------------------------------------------------- ------------------- (clock mlkem_clk_clk_pll rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout3_buf/O net (fo=25775, routed) 0.921 -0.387 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/popToPushGray_buffercc/mlkem_clk SLICE_X67Y95 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/popToPushGray_buffercc/buffers_0_reg[0]/C clock pessimism 0.099 -0.288 clock uncertainty 0.197 -0.092 SLICE_X67Y95 FDCE (Hold_fdce_C_D) 0.046 -0.046 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/popToPushGray_buffercc/buffers_0_reg[0] ------------------------------------------------------------------- required time 0.046 arrival time 0.133 ------------------------------------------------------------------- slack 0.179 Slack (MET) : 0.181ns (arrival time - required time) Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/pushCC_pushPtrGray_reg[1]/C (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/pushToPopGray_buffercc/buffers_0_reg[1]/D (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) Path Group: mlkem_clk_clk_pll Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (mlkem_clk_clk_pll rise@0.000ns - sys_clk rise@0.000ns) Data Path Delay: 0.744ns (logic 0.141ns (18.948%) route 0.603ns (81.052%)) Logic Levels: 0 Clock Path Skew: 0.319ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.388ns Source Clock Delay (SCD): -0.608ns Clock Pessimism Removal (CPR): -0.099ns Clock Uncertainty: 0.197ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.136ns Phase Error (PE): 0.120ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9603, routed) 0.654 -0.608 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/sys_clk SLICE_X53Y93 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/pushCC_pushPtrGray_reg[1]/C ------------------------------------------------------------------- ------------------- SLICE_X53Y93 FDCE (Prop_fdce_C_Q) 0.141 -0.467 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/pushCC_pushPtrGray_reg[1]/Q net (fo=2, routed) 0.603 0.136 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/pushToPopGray_buffercc/Q[1] SLICE_X73Y93 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/pushToPopGray_buffercc/buffers_0_reg[1]/D ------------------------------------------------------------------- ------------------- (clock mlkem_clk_clk_pll rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout3_buf/O net (fo=25775, routed) 0.920 -0.388 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/pushToPopGray_buffercc/mlkem_clk SLICE_X73Y93 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/pushToPopGray_buffercc/buffers_0_reg[1]/C clock pessimism 0.099 -0.289 clock uncertainty 0.197 -0.093 SLICE_X73Y93 FDCE (Hold_fdce_C_D) 0.047 -0.046 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/pushToPopGray_buffercc/buffers_0_reg[1] ------------------------------------------------------------------- required time 0.046 arrival time 0.136 ------------------------------------------------------------------- slack 0.181 Slack (MET) : 0.182ns (arrival time - required time) Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/pushCC_pushPtrGray_reg[1]/C (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/pushToPopGray_buffercc/buffers_0_reg[1]/D (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) Path Group: mlkem_clk_clk_pll Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (mlkem_clk_clk_pll rise@0.000ns - sys_clk rise@0.000ns) Data Path Delay: 0.749ns (logic 0.164ns (21.888%) route 0.585ns (78.112%)) Logic Levels: 0 Clock Path Skew: 0.324ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.388ns Source Clock Delay (SCD): -0.613ns Clock Pessimism Removal (CPR): -0.099ns Clock Uncertainty: 0.197ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.136ns Phase Error (PE): 0.120ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9603, routed) 0.649 -0.613 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/sys_clk SLICE_X62Y96 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/pushCC_pushPtrGray_reg[1]/C ------------------------------------------------------------------- ------------------- SLICE_X62Y96 FDCE (Prop_fdce_C_Q) 0.164 -0.449 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/pushCC_pushPtrGray_reg[1]/Q net (fo=2, routed) 0.585 0.136 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/pushToPopGray_buffercc/D[1] SLICE_X71Y95 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/pushToPopGray_buffercc/buffers_0_reg[1]/D ------------------------------------------------------------------- ------------------- (clock mlkem_clk_clk_pll rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout3_buf/O net (fo=25775, routed) 0.920 -0.388 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/pushToPopGray_buffercc/mlkem_clk SLICE_X71Y95 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/pushToPopGray_buffercc/buffers_0_reg[1]/C clock pessimism 0.099 -0.289 clock uncertainty 0.197 -0.093 SLICE_X71Y95 FDCE (Hold_fdce_C_D) 0.047 -0.046 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/pushToPopGray_buffercc/buffers_0_reg[1] ------------------------------------------------------------------- required time 0.046 arrival time 0.136 ------------------------------------------------------------------- slack 0.182 Slack (MET) : 0.187ns (arrival time - required time) Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/ram_reg_0_7_18_23/RAMC_D1/CLK (rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/_zz_ram_port1_reg[23]/D (rising edge-triggered cell FDRE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) Path Group: mlkem_clk_clk_pll Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (mlkem_clk_clk_pll rise@0.000ns - sys_clk rise@0.000ns) Data Path Delay: 0.782ns (logic 0.386ns (49.382%) route 0.396ns (50.618%)) Logic Levels: 0 Clock Path Skew: 0.328ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.379ns Source Clock Delay (SCD): -0.608ns Clock Pessimism Removal (CPR): -0.099ns Clock Uncertainty: 0.197ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.136ns Phase Error (PE): 0.120ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9603, routed) 0.654 -0.608 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/ram_reg_0_7_18_23/WCLK SLICE_X52Y95 RAMD32 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/ram_reg_0_7_18_23/RAMC_D1/CLK ------------------------------------------------------------------- ------------------- SLICE_X52Y95 RAMD32 (Prop_ramd32_CLK_O) 0.386 -0.222 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/ram_reg_0_7_18_23/RAMC_D1/O net (fo=1, routed) 0.396 0.173 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/_zz_ram_port10__0[23] SLICE_X53Y97 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/_zz_ram_port1_reg[23]/D ------------------------------------------------------------------- ------------------- (clock mlkem_clk_clk_pll rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout3_buf/O net (fo=25775, routed) 0.929 -0.379 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/mlkem_clk SLICE_X53Y97 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/_zz_ram_port1_reg[23]/C clock pessimism 0.099 -0.280 clock uncertainty 0.197 -0.084 SLICE_X53Y97 FDRE (Hold_fdre_C_D) 0.070 -0.014 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/_zz_ram_port1_reg[23] ------------------------------------------------------------------- required time 0.014 arrival time 0.173 ------------------------------------------------------------------- slack 0.187 Slack (MET) : 0.188ns (arrival time - required time) Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/ram_reg_0_7_18_23/RAMA_D1/CLK (rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/_zz_ram_port1_reg[19]/D (rising edge-triggered cell FDRE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) Path Group: mlkem_clk_clk_pll Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (mlkem_clk_clk_pll rise@0.000ns - sys_clk rise@0.000ns) Data Path Delay: 0.772ns (logic 0.478ns (61.920%) route 0.294ns (38.080%)) Logic Levels: 0 Clock Path Skew: 0.328ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.379ns Source Clock Delay (SCD): -0.608ns Clock Pessimism Removal (CPR): -0.099ns Clock Uncertainty: 0.197ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.136ns Phase Error (PE): 0.120ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9603, routed) 0.654 -0.608 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/ram_reg_0_7_18_23/WCLK SLICE_X52Y95 RAMD32 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/ram_reg_0_7_18_23/RAMA_D1/CLK ------------------------------------------------------------------- ------------------- SLICE_X52Y95 RAMD32 (Prop_ramd32_CLK_O) 0.478 -0.130 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/ram_reg_0_7_18_23/RAMA_D1/O net (fo=1, routed) 0.294 0.164 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/_zz_ram_port10__0[19] SLICE_X52Y97 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/_zz_ram_port1_reg[19]/D ------------------------------------------------------------------- ------------------- (clock mlkem_clk_clk_pll rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout3_buf/O net (fo=25775, routed) 0.929 -0.379 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/mlkem_clk SLICE_X52Y97 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/_zz_ram_port1_reg[19]/C clock pessimism 0.099 -0.280 clock uncertainty 0.197 -0.084 SLICE_X52Y97 FDRE (Hold_fdre_C_D) 0.059 -0.025 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/_zz_ram_port1_reg[19] ------------------------------------------------------------------- required time 0.025 arrival time 0.164 ------------------------------------------------------------------- slack 0.188 Slack (MET) : 0.190ns (arrival time - required time) Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_30_35/RAMB_D1/CLK (rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/_zz_ram_port1_reg[33]/D (rising edge-triggered cell FDRE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) Path Group: mlkem_clk_clk_pll Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (mlkem_clk_clk_pll rise@0.000ns - sys_clk rise@0.000ns) Data Path Delay: 0.788ns (logic 0.388ns (49.257%) route 0.400ns (50.743%)) Logic Levels: 0 Clock Path Skew: 0.335ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.380ns Source Clock Delay (SCD): -0.616ns Clock Pessimism Removal (CPR): -0.099ns Clock Uncertainty: 0.197ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.136ns Phase Error (PE): 0.120ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9603, routed) 0.646 -0.616 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_30_35/WCLK SLICE_X42Y80 RAMD32 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_30_35/RAMB_D1/CLK ------------------------------------------------------------------- ------------------- SLICE_X42Y80 RAMD32 (Prop_ramd32_CLK_O) 0.388 -0.228 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_30_35/RAMB_D1/O net (fo=1, routed) 0.400 0.171 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/_zz_ram_port10__2[33] SLICE_X47Y94 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/_zz_ram_port1_reg[33]/D ------------------------------------------------------------------- ------------------- (clock mlkem_clk_clk_pll rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout3_buf/O net (fo=25775, routed) 0.928 -0.380 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/mlkem_clk SLICE_X47Y94 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/_zz_ram_port1_reg[33]/C clock pessimism 0.099 -0.281 clock uncertainty 0.197 -0.085 SLICE_X47Y94 FDRE (Hold_fdre_C_D) 0.066 -0.019 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/_zz_ram_port1_reg[33] ------------------------------------------------------------------- required time 0.019 arrival time 0.171 ------------------------------------------------------------------- slack 0.190 Slack (MET) : 0.191ns (arrival time - required time) Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/pushCC_pushPtrGray_reg[0]/C (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/pushToPopGray_buffercc/buffers_0_reg[0]/D (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) Path Group: mlkem_clk_clk_pll Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (mlkem_clk_clk_pll rise@0.000ns - sys_clk rise@0.000ns) Data Path Delay: 0.753ns (logic 0.141ns (18.737%) route 0.612ns (81.263%)) Logic Levels: 0 Clock Path Skew: 0.319ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.388ns Source Clock Delay (SCD): -0.608ns Clock Pessimism Removal (CPR): -0.099ns Clock Uncertainty: 0.197ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.136ns Phase Error (PE): 0.120ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9603, routed) 0.654 -0.608 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/sys_clk SLICE_X53Y93 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/pushCC_pushPtrGray_reg[0]/C ------------------------------------------------------------------- ------------------- SLICE_X53Y93 FDCE (Prop_fdce_C_Q) 0.141 -0.467 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/pushCC_pushPtrGray_reg[0]/Q net (fo=2, routed) 0.612 0.144 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/pushToPopGray_buffercc/Q[0] SLICE_X73Y93 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/pushToPopGray_buffercc/buffers_0_reg[0]/D ------------------------------------------------------------------- ------------------- (clock mlkem_clk_clk_pll rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout3_buf/O net (fo=25775, routed) 0.920 -0.388 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/pushToPopGray_buffercc/mlkem_clk SLICE_X73Y93 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/pushToPopGray_buffercc/buffers_0_reg[0]/C clock pessimism 0.099 -0.289 clock uncertainty 0.197 -0.093 SLICE_X73Y93 FDCE (Hold_fdce_C_D) 0.046 -0.047 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/pushToPopGray_buffercc/buffers_0_reg[0] ------------------------------------------------------------------- required time 0.047 arrival time 0.144 ------------------------------------------------------------------- slack 0.191 Slack (MET) : 0.194ns (arrival time - required time) Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/ram_reg_0_3_0_5/RAMC_D1/CLK (rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/_zz_ram_port1_reg[5]/D (rising edge-triggered cell FDRE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) Path Group: mlkem_clk_clk_pll Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (mlkem_clk_clk_pll rise@0.000ns - sys_clk rise@0.000ns) Data Path Delay: 0.780ns (logic 0.386ns (49.472%) route 0.394ns (50.528%)) Logic Levels: 0 Clock Path Skew: 0.320ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.388ns Source Clock Delay (SCD): -0.609ns Clock Pessimism Removal (CPR): -0.099ns Clock Uncertainty: 0.197ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.136ns Phase Error (PE): 0.120ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9603, routed) 0.653 -0.609 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/ram_reg_0_3_0_5/WCLK SLICE_X52Y91 RAMD32 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/ram_reg_0_3_0_5/RAMC_D1/CLK ------------------------------------------------------------------- ------------------- SLICE_X52Y91 RAMD32 (Prop_ramd32_CLK_O) 0.386 -0.223 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/ram_reg_0_3_0_5/RAMC_D1/O net (fo=1, routed) 0.394 0.171 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/_zz_ram_port10[5] SLICE_X67Y92 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/_zz_ram_port1_reg[5]/D ------------------------------------------------------------------- ------------------- (clock mlkem_clk_clk_pll rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout3_buf/O net (fo=25775, routed) 0.920 -0.388 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/mlkem_clk SLICE_X67Y92 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/_zz_ram_port1_reg[5]/C clock pessimism 0.099 -0.289 clock uncertainty 0.197 -0.093 SLICE_X67Y92 FDRE (Hold_fdre_C_D) 0.070 -0.023 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/_zz_ram_port1_reg[5] ------------------------------------------------------------------- required time 0.023 arrival time 0.171 ------------------------------------------------------------------- slack 0.194 Slack (MET) : 0.198ns (arrival time - required time) Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/ram_reg_0_3_0_5/RAMB_D1/CLK (rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/_zz_ram_port1_reg[3]/D (rising edge-triggered cell FDRE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) Path Group: mlkem_clk_clk_pll Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (mlkem_clk_clk_pll rise@0.000ns - sys_clk rise@0.000ns) Data Path Delay: 0.785ns (logic 0.388ns (49.430%) route 0.397ns (50.570%)) Logic Levels: 0 Clock Path Skew: 0.320ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.388ns Source Clock Delay (SCD): -0.609ns Clock Pessimism Removal (CPR): -0.099ns Clock Uncertainty: 0.197ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.136ns Phase Error (PE): 0.120ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9603, routed) 0.653 -0.609 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/ram_reg_0_3_0_5/WCLK SLICE_X52Y91 RAMD32 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/ram_reg_0_3_0_5/RAMB_D1/CLK ------------------------------------------------------------------- ------------------- SLICE_X52Y91 RAMD32 (Prop_ramd32_CLK_O) 0.388 -0.221 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/ram_reg_0_3_0_5/RAMB_D1/O net (fo=1, routed) 0.397 0.176 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/_zz_ram_port10[3] SLICE_X67Y92 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/_zz_ram_port1_reg[3]/D ------------------------------------------------------------------- ------------------- (clock mlkem_clk_clk_pll rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout3_buf/O net (fo=25775, routed) 0.920 -0.388 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/mlkem_clk SLICE_X67Y92 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/_zz_ram_port1_reg[3]/C clock pessimism 0.099 -0.289 clock uncertainty 0.197 -0.093 SLICE_X67Y92 FDRE (Hold_fdre_C_D) 0.070 -0.023 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/_zz_ram_port1_reg[3] ------------------------------------------------------------------- required time 0.023 arrival time 0.176 ------------------------------------------------------------------- slack 0.198 Slack (MET) : 0.199ns (arrival time - required time) Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/ram_reg_0_7_24_29/RAMC_D1/CLK (rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/_zz_ram_port1_reg[29]/D (rising edge-triggered cell FDRE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) Path Group: mlkem_clk_clk_pll Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (mlkem_clk_clk_pll rise@0.000ns - sys_clk rise@0.000ns) Data Path Delay: 0.788ns (logic 0.386ns (48.958%) route 0.402ns (51.041%)) Logic Levels: 0 Clock Path Skew: 0.327ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.379ns Source Clock Delay (SCD): -0.607ns Clock Pessimism Removal (CPR): -0.099ns Clock Uncertainty: 0.197ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.136ns Phase Error (PE): 0.120ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9603, routed) 0.655 -0.607 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/ram_reg_0_7_24_29/WCLK SLICE_X52Y98 RAMD32 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/ram_reg_0_7_24_29/RAMC_D1/CLK ------------------------------------------------------------------- ------------------- SLICE_X52Y98 RAMD32 (Prop_ramd32_CLK_O) 0.386 -0.221 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/ram_reg_0_7_24_29/RAMC_D1/O net (fo=1, routed) 0.402 0.181 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/_zz_ram_port10__0[29] SLICE_X54Y98 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/_zz_ram_port1_reg[29]/D ------------------------------------------------------------------- ------------------- (clock mlkem_clk_clk_pll rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout3_buf/O net (fo=25775, routed) 0.929 -0.379 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/mlkem_clk SLICE_X54Y98 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/_zz_ram_port1_reg[29]/C clock pessimism 0.099 -0.280 clock uncertainty 0.197 -0.084 SLICE_X54Y98 FDRE (Hold_fdre_C_D) 0.066 -0.018 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/_zz_ram_port1_reg[29] ------------------------------------------------------------------- required time 0.018 arrival time 0.181 ------------------------------------------------------------------- slack 0.199 Slack (MET) : 0.203ns (arrival time - required time) Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/popCC_ptrToPush_reg[0]/C (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/popToPushGray_buffercc/buffers_0_reg[0]/D (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) Path Group: mlkem_clk_clk_pll Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (mlkem_clk_clk_pll rise@0.000ns - sys_clk rise@0.000ns) Data Path Delay: 0.771ns (logic 0.141ns (18.278%) route 0.630ns (81.722%)) Logic Levels: 0 Clock Path Skew: 0.326ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.387ns Source Clock Delay (SCD): -0.614ns Clock Pessimism Removal (CPR): -0.099ns Clock Uncertainty: 0.197ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.136ns Phase Error (PE): 0.120ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9603, routed) 0.648 -0.614 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/sys_clk SLICE_X65Y95 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/popCC_ptrToPush_reg[0]/C ------------------------------------------------------------------- ------------------- SLICE_X65Y95 FDCE (Prop_fdce_C_Q) 0.141 -0.473 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/popCC_ptrToPush_reg[0]/Q net (fo=2, routed) 0.630 0.157 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/popToPushGray_buffercc/D[0] SLICE_X67Y96 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/popToPushGray_buffercc/buffers_0_reg[0]/D ------------------------------------------------------------------- ------------------- (clock mlkem_clk_clk_pll rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout3_buf/O net (fo=25775, routed) 0.921 -0.387 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/popToPushGray_buffercc/mlkem_clk SLICE_X67Y96 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/popToPushGray_buffercc/buffers_0_reg[0]/C clock pessimism 0.099 -0.288 clock uncertainty 0.197 -0.092 SLICE_X67Y96 FDCE (Hold_fdce_C_D) 0.046 -0.046 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/popToPushGray_buffercc/buffers_0_reg[0] ------------------------------------------------------------------- required time 0.046 arrival time 0.157 ------------------------------------------------------------------- slack 0.203 Slack (MET) : 0.203ns (arrival time - required time) Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/ram_reg_0_7_0_5/RAMA/CLK (rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/_zz_ram_port1_reg[0]/D (rising edge-triggered cell FDRE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) Path Group: mlkem_clk_clk_pll Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (mlkem_clk_clk_pll rise@0.000ns - sys_clk rise@0.000ns) Data Path Delay: 0.721ns (logic 0.492ns (68.193%) route 0.229ns (31.807%)) Logic Levels: 0 Clock Path Skew: 0.329ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.381ns Source Clock Delay (SCD): -0.611ns Clock Pessimism Removal (CPR): -0.099ns Clock Uncertainty: 0.197ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.136ns Phase Error (PE): 0.120ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9603, routed) 0.651 -0.611 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/ram_reg_0_7_0_5/WCLK SLICE_X60Y95 RAMD32 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/ram_reg_0_7_0_5/RAMA/CLK ------------------------------------------------------------------- ------------------- SLICE_X60Y95 RAMD32 (Prop_ramd32_CLK_O) 0.492 -0.119 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/ram_reg_0_7_0_5/RAMA/O net (fo=1, routed) 0.229 0.110 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/_zz_ram_port10__0[0] SLICE_X60Y99 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/_zz_ram_port1_reg[0]/D ------------------------------------------------------------------- ------------------- (clock mlkem_clk_clk_pll rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout3_buf/O net (fo=25775, routed) 0.927 -0.381 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/mlkem_clk SLICE_X60Y99 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/_zz_ram_port1_reg[0]/C clock pessimism 0.099 -0.282 clock uncertainty 0.197 -0.086 SLICE_X60Y99 FDRE (Hold_fdre_C_D) -0.007 -0.093 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/_zz_ram_port1_reg[0] ------------------------------------------------------------------- required time 0.093 arrival time 0.110 ------------------------------------------------------------------- slack 0.203 Slack (MET) : 0.210ns (arrival time - required time) Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/popCC_ptrToPush_reg[3]/C (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/popToPushGray_buffercc/buffers_0_reg[3]/D (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) Path Group: mlkem_clk_clk_pll Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (mlkem_clk_clk_pll rise@0.000ns - sys_clk rise@0.000ns) Data Path Delay: 0.781ns (logic 0.141ns (18.045%) route 0.640ns (81.955%)) Logic Levels: 0 Clock Path Skew: 0.328ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.387ns Source Clock Delay (SCD): -0.616ns Clock Pessimism Removal (CPR): -0.099ns Clock Uncertainty: 0.197ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.136ns Phase Error (PE): 0.120ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9603, routed) 0.646 -0.616 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/sys_clk SLICE_X67Y94 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/popCC_ptrToPush_reg[3]/C ------------------------------------------------------------------- ------------------- SLICE_X67Y94 FDCE (Prop_fdce_C_Q) 0.141 -0.475 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/popCC_ptrToPush_reg[3]/Q net (fo=1, routed) 0.640 0.165 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/popToPushGray_buffercc/Q[3] SLICE_X67Y95 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/popToPushGray_buffercc/buffers_0_reg[3]/D ------------------------------------------------------------------- ------------------- (clock mlkem_clk_clk_pll rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout3_buf/O net (fo=25775, routed) 0.921 -0.387 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/popToPushGray_buffercc/mlkem_clk SLICE_X67Y95 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/popToPushGray_buffercc/buffers_0_reg[3]/C clock pessimism 0.099 -0.288 clock uncertainty 0.197 -0.092 SLICE_X67Y95 FDCE (Hold_fdce_C_D) 0.047 -0.045 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/popToPushGray_buffercc/buffers_0_reg[3] ------------------------------------------------------------------- required time 0.045 arrival time 0.165 ------------------------------------------------------------------- slack 0.210 Slack (MET) : 0.217ns (arrival time - required time) Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_0_5/RAMB/CLK (rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/_zz_ram_port1_reg[2]/D (rising edge-triggered cell FDRE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) Path Group: mlkem_clk_clk_pll Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (mlkem_clk_clk_pll rise@0.000ns - sys_clk rise@0.000ns) Data Path Delay: 0.744ns (logic 0.394ns (52.947%) route 0.350ns (47.053%)) Logic Levels: 0 Clock Path Skew: 0.333ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.380ns Source Clock Delay (SCD): -0.614ns Clock Pessimism Removal (CPR): -0.099ns Clock Uncertainty: 0.197ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.136ns Phase Error (PE): 0.120ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9603, routed) 0.648 -0.614 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_0_5/WCLK SLICE_X48Y82 RAMD32 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_0_5/RAMB/CLK ------------------------------------------------------------------- ------------------- SLICE_X48Y82 RAMD32 (Prop_ramd32_CLK_O) 0.394 -0.220 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_0_5/RAMB/O net (fo=1, routed) 0.350 0.130 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/_zz_ram_port10__2[2] SLICE_X51Y94 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/_zz_ram_port1_reg[2]/D ------------------------------------------------------------------- ------------------- (clock mlkem_clk_clk_pll rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout3_buf/O net (fo=25775, routed) 0.928 -0.380 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/mlkem_clk SLICE_X51Y94 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/_zz_ram_port1_reg[2]/C clock pessimism 0.099 -0.281 clock uncertainty 0.197 -0.085 SLICE_X51Y94 FDRE (Hold_fdre_C_D) -0.003 -0.088 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/_zz_ram_port1_reg[2] ------------------------------------------------------------------- required time 0.088 arrival time 0.130 ------------------------------------------------------------------- slack 0.217 Slack (MET) : 0.219ns (arrival time - required time) Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/ram_reg_0_7_12_17/RAMC/CLK (rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/_zz_ram_port1_reg[16]/D (rising edge-triggered cell FDRE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) Path Group: mlkem_clk_clk_pll Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (mlkem_clk_clk_pll rise@0.000ns - sys_clk rise@0.000ns) Data Path Delay: 0.728ns (logic 0.390ns (53.543%) route 0.338ns (46.457%)) Logic Levels: 0 Clock Path Skew: 0.329ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.381ns Source Clock Delay (SCD): -0.611ns Clock Pessimism Removal (CPR): -0.099ns Clock Uncertainty: 0.197ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.136ns Phase Error (PE): 0.120ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9603, routed) 0.651 -0.611 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/ram_reg_0_7_12_17/WCLK SLICE_X60Y96 RAMD32 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/ram_reg_0_7_12_17/RAMC/CLK ------------------------------------------------------------------- ------------------- SLICE_X60Y96 RAMD32 (Prop_ramd32_CLK_O) 0.390 -0.221 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/ram_reg_0_7_12_17/RAMC/O net (fo=1, routed) 0.338 0.117 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/_zz_ram_port10__0[16] SLICE_X60Y97 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/_zz_ram_port1_reg[16]/D ------------------------------------------------------------------- ------------------- (clock mlkem_clk_clk_pll rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout3_buf/O net (fo=25775, routed) 0.927 -0.381 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/mlkem_clk SLICE_X60Y97 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/_zz_ram_port1_reg[16]/C clock pessimism 0.099 -0.282 clock uncertainty 0.197 -0.086 SLICE_X60Y97 FDRE (Hold_fdre_C_D) -0.016 -0.102 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/_zz_ram_port1_reg[16] ------------------------------------------------------------------- required time 0.102 arrival time 0.117 ------------------------------------------------------------------- slack 0.219 Slack (MET) : 0.220ns (arrival time - required time) Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/ram_reg_0_7_6_11/RAMC/CLK (rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/_zz_ram_port1_reg[10]/D (rising edge-triggered cell FDRE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) Path Group: mlkem_clk_clk_pll Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (mlkem_clk_clk_pll rise@0.000ns - sys_clk rise@0.000ns) Data Path Delay: 0.728ns (logic 0.390ns (53.543%) route 0.338ns (46.457%)) Logic Levels: 0 Clock Path Skew: 0.328ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.381ns Source Clock Delay (SCD): -0.610ns Clock Pessimism Removal (CPR): -0.099ns Clock Uncertainty: 0.197ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.136ns Phase Error (PE): 0.120ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9603, routed) 0.652 -0.610 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/ram_reg_0_7_6_11/WCLK SLICE_X60Y98 RAMD32 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/ram_reg_0_7_6_11/RAMC/CLK ------------------------------------------------------------------- ------------------- SLICE_X60Y98 RAMD32 (Prop_ramd32_CLK_O) 0.390 -0.220 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/ram_reg_0_7_6_11/RAMC/O net (fo=1, routed) 0.338 0.118 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/_zz_ram_port10__0[10] SLICE_X60Y99 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/_zz_ram_port1_reg[10]/D ------------------------------------------------------------------- ------------------- (clock mlkem_clk_clk_pll rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout3_buf/O net (fo=25775, routed) 0.927 -0.381 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/mlkem_clk SLICE_X60Y99 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/_zz_ram_port1_reg[10]/C clock pessimism 0.099 -0.282 clock uncertainty 0.197 -0.086 SLICE_X60Y99 FDRE (Hold_fdre_C_D) -0.016 -0.102 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/_zz_ram_port1_reg[10] ------------------------------------------------------------------- required time 0.102 arrival time 0.118 ------------------------------------------------------------------- slack 0.220 Slack (MET) : 0.220ns (arrival time - required time) Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/pushCC_pushPtrGray_reg[2]/C (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/pushToPopGray_buffercc/buffers_0_reg[2]/D (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) Path Group: mlkem_clk_clk_pll Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (mlkem_clk_clk_pll rise@0.000ns - sys_clk rise@0.000ns) Data Path Delay: 0.788ns (logic 0.164ns (20.816%) route 0.624ns (79.184%)) Logic Levels: 0 Clock Path Skew: 0.324ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.388ns Source Clock Delay (SCD): -0.613ns Clock Pessimism Removal (CPR): -0.099ns Clock Uncertainty: 0.197ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.136ns Phase Error (PE): 0.120ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9603, routed) 0.649 -0.613 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/sys_clk SLICE_X62Y96 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/pushCC_pushPtrGray_reg[2]/C ------------------------------------------------------------------- ------------------- SLICE_X62Y96 FDCE (Prop_fdce_C_Q) 0.164 -0.449 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/pushCC_pushPtrGray_reg[2]/Q net (fo=2, routed) 0.624 0.174 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/pushToPopGray_buffercc/D[2] SLICE_X71Y95 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/pushToPopGray_buffercc/buffers_0_reg[2]/D ------------------------------------------------------------------- ------------------- (clock mlkem_clk_clk_pll rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout3_buf/O net (fo=25775, routed) 0.920 -0.388 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/pushToPopGray_buffercc/mlkem_clk SLICE_X71Y95 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/pushToPopGray_buffercc/buffers_0_reg[2]/C clock pessimism 0.099 -0.289 clock uncertainty 0.197 -0.093 SLICE_X71Y95 FDCE (Hold_fdce_C_D) 0.047 -0.046 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/pushToPopGray_buffercc/buffers_0_reg[2] ------------------------------------------------------------------- required time 0.046 arrival time 0.174 ------------------------------------------------------------------- slack 0.220 Slack (MET) : 0.226ns (arrival time - required time) Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/pushCC_pushPtrGray_reg[2]/C (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/pushToPopGray_buffercc/buffers_0_reg[2]/D (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) Path Group: mlkem_clk_clk_pll Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (mlkem_clk_clk_pll rise@0.000ns - sys_clk rise@0.000ns) Data Path Delay: 0.735ns (logic 0.128ns (17.411%) route 0.607ns (82.589%)) Logic Levels: 0 Clock Path Skew: 0.319ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.388ns Source Clock Delay (SCD): -0.608ns Clock Pessimism Removal (CPR): -0.099ns Clock Uncertainty: 0.197ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.136ns Phase Error (PE): 0.120ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9603, routed) 0.654 -0.608 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/sys_clk SLICE_X53Y93 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/pushCC_pushPtrGray_reg[2]/C ------------------------------------------------------------------- ------------------- SLICE_X53Y93 FDCE (Prop_fdce_C_Q) 0.128 -0.480 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/pushCC_pushPtrGray_reg[2]/Q net (fo=4, routed) 0.607 0.127 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/pushToPopGray_buffercc/buffers_0_reg[2]_0 SLICE_X73Y93 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/pushToPopGray_buffercc/buffers_0_reg[2]/D ------------------------------------------------------------------- ------------------- (clock mlkem_clk_clk_pll rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout3_buf/O net (fo=25775, routed) 0.920 -0.388 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/pushToPopGray_buffercc/mlkem_clk SLICE_X73Y93 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/pushToPopGray_buffercc/buffers_0_reg[2]/C clock pessimism 0.099 -0.289 clock uncertainty 0.197 -0.093 SLICE_X73Y93 FDCE (Hold_fdce_C_D) -0.007 -0.100 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/pushToPopGray_buffercc/buffers_0_reg[2] ------------------------------------------------------------------- required time 0.100 arrival time 0.127 ------------------------------------------------------------------- slack 0.226 Slack (MET) : 0.235ns (arrival time - required time) Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_12_17/RAMB_D1/CLK (rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/_zz_ram_port1_reg[15]/D (rising edge-triggered cell FDRE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) Path Group: mlkem_clk_clk_pll Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (mlkem_clk_clk_pll rise@0.000ns - sys_clk rise@0.000ns) Data Path Delay: 0.842ns (logic 0.388ns (46.104%) route 0.454ns (53.896%)) Logic Levels: 0 Clock Path Skew: 0.335ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.380ns Source Clock Delay (SCD): -0.616ns Clock Pessimism Removal (CPR): -0.099ns Clock Uncertainty: 0.197ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.136ns Phase Error (PE): 0.120ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9603, routed) 0.646 -0.616 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_12_17/WCLK SLICE_X48Y80 RAMD32 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_12_17/RAMB_D1/CLK ------------------------------------------------------------------- ------------------- SLICE_X48Y80 RAMD32 (Prop_ramd32_CLK_O) 0.388 -0.228 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_12_17/RAMB_D1/O net (fo=1, routed) 0.454 0.225 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/_zz_ram_port10__2[15] SLICE_X53Y96 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/_zz_ram_port1_reg[15]/D ------------------------------------------------------------------- ------------------- (clock mlkem_clk_clk_pll rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout3_buf/O net (fo=25775, routed) 0.928 -0.380 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/mlkem_clk SLICE_X53Y96 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/_zz_ram_port1_reg[15]/C clock pessimism 0.099 -0.281 clock uncertainty 0.197 -0.085 SLICE_X53Y96 FDRE (Hold_fdre_C_D) 0.075 -0.010 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/_zz_ram_port1_reg[15] ------------------------------------------------------------------- required time 0.010 arrival time 0.225 ------------------------------------------------------------------- slack 0.235 Slack (MET) : 0.236ns (arrival time - required time) Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/ram_reg_0_7_24_29/RAMB_D1/CLK (rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/_zz_ram_port1_reg[27]/D (rising edge-triggered cell FDRE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) Path Group: mlkem_clk_clk_pll Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (mlkem_clk_clk_pll rise@0.000ns - sys_clk rise@0.000ns) Data Path Delay: 0.817ns (logic 0.388ns (47.470%) route 0.429ns (52.530%)) Logic Levels: 0 Clock Path Skew: 0.327ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.379ns Source Clock Delay (SCD): -0.607ns Clock Pessimism Removal (CPR): -0.099ns Clock Uncertainty: 0.197ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.136ns Phase Error (PE): 0.120ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9603, routed) 0.655 -0.607 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/ram_reg_0_7_24_29/WCLK SLICE_X52Y98 RAMD32 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/ram_reg_0_7_24_29/RAMB_D1/CLK ------------------------------------------------------------------- ------------------- SLICE_X52Y98 RAMD32 (Prop_ramd32_CLK_O) 0.388 -0.219 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/ram_reg_0_7_24_29/RAMB_D1/O net (fo=1, routed) 0.429 0.210 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/_zz_ram_port10__0[27] SLICE_X53Y99 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/_zz_ram_port1_reg[27]/D ------------------------------------------------------------------- ------------------- (clock mlkem_clk_clk_pll rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout3_buf/O net (fo=25775, routed) 0.929 -0.379 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/mlkem_clk SLICE_X53Y99 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/_zz_ram_port1_reg[27]/C clock pessimism 0.099 -0.280 clock uncertainty 0.197 -0.084 SLICE_X53Y99 FDRE (Hold_fdre_C_D) 0.058 -0.026 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/_zz_ram_port1_reg[27] ------------------------------------------------------------------- required time 0.026 arrival time 0.210 ------------------------------------------------------------------- slack 0.236 Slack (MET) : 0.240ns (arrival time - required time) Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/ram_reg_0_7_6_11/RAMB_D1/CLK (rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/_zz_ram_port1_reg[9]/D (rising edge-triggered cell FDRE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) Path Group: mlkem_clk_clk_pll Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (mlkem_clk_clk_pll rise@0.000ns - sys_clk rise@0.000ns) Data Path Delay: 0.839ns (logic 0.388ns (46.230%) route 0.451ns (53.770%)) Logic Levels: 0 Clock Path Skew: 0.328ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.381ns Source Clock Delay (SCD): -0.610ns Clock Pessimism Removal (CPR): -0.099ns Clock Uncertainty: 0.197ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.136ns Phase Error (PE): 0.120ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9603, routed) 0.652 -0.610 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/ram_reg_0_7_6_11/WCLK SLICE_X60Y98 RAMD32 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/ram_reg_0_7_6_11/RAMB_D1/CLK ------------------------------------------------------------------- ------------------- SLICE_X60Y98 RAMD32 (Prop_ramd32_CLK_O) 0.388 -0.222 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/ram_reg_0_7_6_11/RAMB_D1/O net (fo=1, routed) 0.451 0.229 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/_zz_ram_port10__0[9] SLICE_X61Y98 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/_zz_ram_port1_reg[9]/D ------------------------------------------------------------------- ------------------- (clock mlkem_clk_clk_pll rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout3_buf/O net (fo=25775, routed) 0.927 -0.381 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/mlkem_clk SLICE_X61Y98 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/_zz_ram_port1_reg[9]/C clock pessimism 0.099 -0.282 clock uncertainty 0.197 -0.086 SLICE_X61Y98 FDRE (Hold_fdre_C_D) 0.075 -0.011 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/_zz_ram_port1_reg[9] ------------------------------------------------------------------- required time 0.011 arrival time 0.229 ------------------------------------------------------------------- slack 0.240 Slack (MET) : 0.242ns (arrival time - required time) Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/pushCC_pushPtrGray_reg[3]/C (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/pushToPopGray_buffercc/buffers_0_reg[3]/D (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) Path Group: mlkem_clk_clk_pll Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (mlkem_clk_clk_pll rise@0.000ns - sys_clk rise@0.000ns) Data Path Delay: 0.768ns (logic 0.148ns (19.265%) route 0.620ns (80.735%)) Logic Levels: 0 Clock Path Skew: 0.325ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.387ns Source Clock Delay (SCD): -0.613ns Clock Pessimism Removal (CPR): -0.099ns Clock Uncertainty: 0.197ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.136ns Phase Error (PE): 0.120ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9603, routed) 0.649 -0.613 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/sys_clk SLICE_X62Y96 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/pushCC_pushPtrGray_reg[3]/C ------------------------------------------------------------------- ------------------- SLICE_X62Y96 FDCE (Prop_fdce_C_Q) 0.148 -0.465 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/pushCC_pushPtrGray_reg[3]/Q net (fo=4, routed) 0.620 0.155 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/pushToPopGray_buffercc/D[3] SLICE_X72Y97 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/pushToPopGray_buffercc/buffers_0_reg[3]/D ------------------------------------------------------------------- ------------------- (clock mlkem_clk_clk_pll rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout3_buf/O net (fo=25775, routed) 0.921 -0.387 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/pushToPopGray_buffercc/mlkem_clk SLICE_X72Y97 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/pushToPopGray_buffercc/buffers_0_reg[3]/C clock pessimism 0.099 -0.288 clock uncertainty 0.197 -0.092 SLICE_X72Y97 FDCE (Hold_fdce_C_D) 0.005 -0.087 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/pushToPopGray_buffercc/buffers_0_reg[3] ------------------------------------------------------------------- required time 0.087 arrival time 0.155 ------------------------------------------------------------------- slack 0.242 Slack (MET) : 0.243ns (arrival time - required time) Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_30_35/RAMC_D1/CLK (rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/_zz_ram_port1_reg[35]/D (rising edge-triggered cell FDRE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) Path Group: mlkem_clk_clk_pll Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (mlkem_clk_clk_pll rise@0.000ns - sys_clk rise@0.000ns) Data Path Delay: 0.847ns (logic 0.386ns (45.578%) route 0.461ns (54.422%)) Logic Levels: 0 Clock Path Skew: 0.335ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.380ns Source Clock Delay (SCD): -0.616ns Clock Pessimism Removal (CPR): -0.099ns Clock Uncertainty: 0.197ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.136ns Phase Error (PE): 0.120ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9603, routed) 0.646 -0.616 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_30_35/WCLK SLICE_X42Y80 RAMD32 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_30_35/RAMC_D1/CLK ------------------------------------------------------------------- ------------------- SLICE_X42Y80 RAMD32 (Prop_ramd32_CLK_O) 0.386 -0.230 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_30_35/RAMC_D1/O net (fo=1, routed) 0.461 0.231 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/_zz_ram_port10__2[35] SLICE_X47Y94 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/_zz_ram_port1_reg[35]/D ------------------------------------------------------------------- ------------------- (clock mlkem_clk_clk_pll rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout3_buf/O net (fo=25775, routed) 0.928 -0.380 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/mlkem_clk SLICE_X47Y94 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/_zz_ram_port1_reg[35]/C clock pessimism 0.099 -0.281 clock uncertainty 0.197 -0.085 SLICE_X47Y94 FDRE (Hold_fdre_C_D) 0.072 -0.013 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/_zz_ram_port1_reg[35] ------------------------------------------------------------------- required time 0.013 arrival time 0.231 ------------------------------------------------------------------- slack 0.243 Slack (MET) : 0.246ns (arrival time - required time) Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/ram_reg_0_7_6_11/RAMC_D1/CLK (rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/_zz_ram_port1_reg[11]/D (rising edge-triggered cell FDRE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) Path Group: mlkem_clk_clk_pll Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (mlkem_clk_clk_pll rise@0.000ns - sys_clk rise@0.000ns) Data Path Delay: 0.840ns (logic 0.386ns (45.933%) route 0.454ns (54.067%)) Logic Levels: 0 Clock Path Skew: 0.328ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.381ns Source Clock Delay (SCD): -0.610ns Clock Pessimism Removal (CPR): -0.099ns Clock Uncertainty: 0.197ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.136ns Phase Error (PE): 0.120ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9603, routed) 0.652 -0.610 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/ram_reg_0_7_6_11/WCLK SLICE_X60Y98 RAMD32 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/ram_reg_0_7_6_11/RAMC_D1/CLK ------------------------------------------------------------------- ------------------- SLICE_X60Y98 RAMD32 (Prop_ramd32_CLK_O) 0.386 -0.224 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/ram_reg_0_7_6_11/RAMC_D1/O net (fo=1, routed) 0.454 0.230 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/_zz_ram_port10__0[11] SLICE_X61Y99 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/_zz_ram_port1_reg[11]/D ------------------------------------------------------------------- ------------------- (clock mlkem_clk_clk_pll rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout3_buf/O net (fo=25775, routed) 0.927 -0.381 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/mlkem_clk SLICE_X61Y99 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/_zz_ram_port1_reg[11]/C clock pessimism 0.099 -0.282 clock uncertainty 0.197 -0.086 SLICE_X61Y99 FDRE (Hold_fdre_C_D) 0.070 -0.016 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/_zz_ram_port1_reg[11] ------------------------------------------------------------------- required time 0.016 arrival time 0.230 ------------------------------------------------------------------- slack 0.246 Slack (MET) : 0.247ns (arrival time - required time) Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_0_5/RAMC_D1/CLK (rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/_zz_ram_port1_reg[5]/D (rising edge-triggered cell FDRE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) Path Group: mlkem_clk_clk_pll Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (mlkem_clk_clk_pll rise@0.000ns - sys_clk rise@0.000ns) Data Path Delay: 0.840ns (logic 0.386ns (45.968%) route 0.454ns (54.032%)) Logic Levels: 0 Clock Path Skew: 0.333ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.380ns Source Clock Delay (SCD): -0.614ns Clock Pessimism Removal (CPR): -0.099ns Clock Uncertainty: 0.197ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.136ns Phase Error (PE): 0.120ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9603, routed) 0.648 -0.614 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_0_5/WCLK SLICE_X48Y82 RAMD32 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_0_5/RAMC_D1/CLK ------------------------------------------------------------------- ------------------- SLICE_X48Y82 RAMD32 (Prop_ramd32_CLK_O) 0.386 -0.228 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_0_5/RAMC_D1/O net (fo=1, routed) 0.454 0.225 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/_zz_ram_port10__2[5] SLICE_X50Y96 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/_zz_ram_port1_reg[5]/D ------------------------------------------------------------------- ------------------- (clock mlkem_clk_clk_pll rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout3_buf/O net (fo=25775, routed) 0.928 -0.380 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/mlkem_clk SLICE_X50Y96 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/_zz_ram_port1_reg[5]/C clock pessimism 0.099 -0.281 clock uncertainty 0.197 -0.085 SLICE_X50Y96 FDRE (Hold_fdre_C_D) 0.063 -0.022 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/_zz_ram_port1_reg[5] ------------------------------------------------------------------- required time 0.022 arrival time 0.225 ------------------------------------------------------------------- slack 0.247 --------------------------------------------------------------------------------------------------- From Clock: mlkem_clk_clk_pll To Clock: sys_clk Setup : NA Failing Endpoints, Worst Slack NA , Total Violation NA Hold : 0 Failing Endpoints, Worst Slack 0.035ns, Total Violation 0.000ns --------------------------------------------------------------------------------------------------- Min Delay Paths -------------------------------------------------------------------------------------- Slack (MET) : 0.035ns (arrival time - required time) Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_24_29/RAMB/CLK (rising edge-triggered cell RAMD32 clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[26]/D (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: sys_clk Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (sys_clk rise@0.000ns - mlkem_clk_clk_pll rise@0.000ns) Data Path Delay: 0.558ns (logic 0.394ns (70.668%) route 0.164ns (29.332%)) Logic Levels: 0 Clock Path Skew: 0.328ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.380ns Source Clock Delay (SCD): -0.609ns Clock Pessimism Removal (CPR): -0.099ns Clock Uncertainty: 0.197ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.136ns Phase Error (PE): 0.120ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock mlkem_clk_clk_pll rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout3_buf/O net (fo=25775, routed) 0.653 -0.609 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_24_29/WCLK SLICE_X56Y94 RAMD32 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_24_29/RAMB/CLK ------------------------------------------------------------------- ------------------- SLICE_X56Y94 RAMD32 (Prop_ramd32_CLK_O) 0.394 -0.215 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_24_29/RAMB/O net (fo=1, routed) 0.164 -0.052 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port10__3[26] SLICE_X55Y93 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[26]/D ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9603, routed) 0.928 -0.380 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/sys_clk SLICE_X55Y93 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[26]/C clock pessimism 0.099 -0.281 clock uncertainty 0.197 -0.085 SLICE_X55Y93 FDRE (Hold_fdre_C_D) -0.002 -0.087 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[26] ------------------------------------------------------------------- required time 0.087 arrival time -0.052 ------------------------------------------------------------------- slack 0.035 Slack (MET) : 0.036ns (arrival time - required time) Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_36_39/RAMB_D1/CLK (rising edge-triggered cell RAMD32 clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[39]/D (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: sys_clk Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (sys_clk rise@0.000ns - mlkem_clk_clk_pll rise@0.000ns) Data Path Delay: 0.627ns (logic 0.388ns (61.845%) route 0.239ns (38.155%)) Logic Levels: 0 Clock Path Skew: 0.325ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.382ns Source Clock Delay (SCD): -0.608ns Clock Pessimism Removal (CPR): -0.099ns Clock Uncertainty: 0.197ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.136ns Phase Error (PE): 0.120ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock mlkem_clk_clk_pll rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout3_buf/O net (fo=25775, routed) 0.654 -0.608 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_36_39/WCLK SLICE_X48Y93 RAMD32 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_36_39/RAMB_D1/CLK ------------------------------------------------------------------- ------------------- SLICE_X48Y93 RAMD32 (Prop_ramd32_CLK_O) 0.388 -0.220 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_36_39/RAMB_D1/O net (fo=1, routed) 0.239 0.019 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port10__3[39] SLICE_X47Y88 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[39]/D ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9603, routed) 0.926 -0.382 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/sys_clk SLICE_X47Y88 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[39]/C clock pessimism 0.099 -0.283 clock uncertainty 0.197 -0.087 SLICE_X47Y88 FDRE (Hold_fdre_C_D) 0.070 -0.017 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[39] ------------------------------------------------------------------- required time 0.017 arrival time 0.019 ------------------------------------------------------------------- slack 0.036 Slack (MET) : 0.044ns (arrival time - required time) Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_12_17/RAMC/CLK (rising edge-triggered cell RAMD32 clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[16]/D (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: sys_clk Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (sys_clk rise@0.000ns - mlkem_clk_clk_pll rise@0.000ns) Data Path Delay: 0.562ns (logic 0.390ns (69.355%) route 0.172ns (30.645%)) Logic Levels: 0 Clock Path Skew: 0.327ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.385ns Source Clock Delay (SCD): -0.613ns Clock Pessimism Removal (CPR): -0.099ns Clock Uncertainty: 0.197ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.136ns Phase Error (PE): 0.120ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock mlkem_clk_clk_pll rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout3_buf/O net (fo=25775, routed) 0.649 -0.613 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_12_17/WCLK SLICE_X62Y94 RAMD32 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_12_17/RAMC/CLK ------------------------------------------------------------------- ------------------- SLICE_X62Y94 RAMD32 (Prop_ramd32_CLK_O) 0.390 -0.223 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_12_17/RAMC/O net (fo=1, routed) 0.172 -0.051 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port10__3[16] SLICE_X62Y92 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[16]/D ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9603, routed) 0.923 -0.385 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/sys_clk SLICE_X62Y92 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[16]/C clock pessimism 0.099 -0.286 clock uncertainty 0.197 -0.090 SLICE_X62Y92 FDRE (Hold_fdre_C_D) -0.005 -0.095 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[16] ------------------------------------------------------------------- required time 0.095 arrival time -0.051 ------------------------------------------------------------------- slack 0.044 Slack (MET) : 0.048ns (arrival time - required time) Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_18_23/RAMA_D1/CLK (rising edge-triggered cell RAMD32 clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[19]/D (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: sys_clk Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (sys_clk rise@0.000ns - mlkem_clk_clk_pll rise@0.000ns) Data Path Delay: 0.623ns (logic 0.478ns (76.671%) route 0.145ns (23.329%)) Logic Levels: 0 Clock Path Skew: 0.327ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.381ns Source Clock Delay (SCD): -0.609ns Clock Pessimism Removal (CPR): -0.099ns Clock Uncertainty: 0.197ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.136ns Phase Error (PE): 0.120ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock mlkem_clk_clk_pll rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout3_buf/O net (fo=25775, routed) 0.653 -0.609 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_18_23/WCLK SLICE_X56Y93 RAMD32 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_18_23/RAMA_D1/CLK ------------------------------------------------------------------- ------------------- SLICE_X56Y93 RAMD32 (Prop_ramd32_CLK_O) 0.478 -0.131 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_18_23/RAMA_D1/O net (fo=1, routed) 0.145 0.014 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port10__3[19] SLICE_X56Y92 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[19]/D ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9603, routed) 0.927 -0.381 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/sys_clk SLICE_X56Y92 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[19]/C clock pessimism 0.099 -0.282 clock uncertainty 0.197 -0.086 SLICE_X56Y92 FDRE (Hold_fdre_C_D) 0.052 -0.034 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[19] ------------------------------------------------------------------- required time 0.034 arrival time 0.014 ------------------------------------------------------------------- slack 0.048 Slack (MET) : 0.061ns (arrival time - required time) Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_24_29/RAMA_D1/CLK (rising edge-triggered cell RAMD32 clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[25]/D (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: sys_clk Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (sys_clk rise@0.000ns - mlkem_clk_clk_pll rise@0.000ns) Data Path Delay: 0.647ns (logic 0.478ns (73.858%) route 0.169ns (26.142%)) Logic Levels: 0 Clock Path Skew: 0.327ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.381ns Source Clock Delay (SCD): -0.609ns Clock Pessimism Removal (CPR): -0.099ns Clock Uncertainty: 0.197ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.136ns Phase Error (PE): 0.120ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock mlkem_clk_clk_pll rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout3_buf/O net (fo=25775, routed) 0.653 -0.609 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_24_29/WCLK SLICE_X56Y94 RAMD32 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_24_29/RAMA_D1/CLK ------------------------------------------------------------------- ------------------- SLICE_X56Y94 RAMD32 (Prop_ramd32_CLK_O) 0.478 -0.131 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_24_29/RAMA_D1/O net (fo=1, routed) 0.169 0.038 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port10__3[25] SLICE_X56Y92 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[25]/D ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9603, routed) 0.927 -0.381 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/sys_clk SLICE_X56Y92 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[25]/C clock pessimism 0.099 -0.282 clock uncertainty 0.197 -0.086 SLICE_X56Y92 FDRE (Hold_fdre_C_D) 0.063 -0.023 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[25] ------------------------------------------------------------------- required time 0.023 arrival time 0.038 ------------------------------------------------------------------- slack 0.061 Slack (MET) : 0.068ns (arrival time - required time) Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_36_39/RAMA/CLK (rising edge-triggered cell RAMD32 clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[36]/D (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: sys_clk Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (sys_clk rise@0.000ns - mlkem_clk_clk_pll rise@0.000ns) Data Path Delay: 0.595ns (logic 0.492ns (82.730%) route 0.103ns (17.270%)) Logic Levels: 0 Clock Path Skew: 0.326ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.381ns Source Clock Delay (SCD): -0.608ns Clock Pessimism Removal (CPR): -0.099ns Clock Uncertainty: 0.197ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.136ns Phase Error (PE): 0.120ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock mlkem_clk_clk_pll rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout3_buf/O net (fo=25775, routed) 0.654 -0.608 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_36_39/WCLK SLICE_X48Y93 RAMD32 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_36_39/RAMA/CLK ------------------------------------------------------------------- ------------------- SLICE_X48Y93 RAMD32 (Prop_ramd32_CLK_O) 0.492 -0.116 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_36_39/RAMA/O net (fo=1, routed) 0.103 -0.014 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port10__3[36] SLICE_X47Y92 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[36]/D ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9603, routed) 0.927 -0.381 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/sys_clk SLICE_X47Y92 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[36]/C clock pessimism 0.099 -0.282 clock uncertainty 0.197 -0.086 SLICE_X47Y92 FDRE (Hold_fdre_C_D) 0.004 -0.082 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[36] ------------------------------------------------------------------- required time 0.082 arrival time -0.014 ------------------------------------------------------------------- slack 0.068 Slack (MET) : 0.075ns (arrival time - required time) Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_0_5/RAMA_D1/CLK (rising edge-triggered cell RAMD32 clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[1]/D (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: sys_clk Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (sys_clk rise@0.000ns - mlkem_clk_clk_pll rise@0.000ns) Data Path Delay: 0.650ns (logic 0.478ns (73.492%) route 0.172ns (26.508%)) Logic Levels: 0 Clock Path Skew: 0.327ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.385ns Source Clock Delay (SCD): -0.613ns Clock Pessimism Removal (CPR): -0.099ns Clock Uncertainty: 0.197ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.136ns Phase Error (PE): 0.120ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock mlkem_clk_clk_pll rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout3_buf/O net (fo=25775, routed) 0.649 -0.613 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_0_5/WCLK SLICE_X62Y93 RAMD32 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_0_5/RAMA_D1/CLK ------------------------------------------------------------------- ------------------- SLICE_X62Y93 RAMD32 (Prop_ramd32_CLK_O) 0.478 -0.135 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_0_5/RAMA_D1/O net (fo=1, routed) 0.172 0.037 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port10__3[1] SLICE_X62Y90 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[1]/D ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9603, routed) 0.923 -0.385 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/sys_clk SLICE_X62Y90 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[1]/C clock pessimism 0.099 -0.286 clock uncertainty 0.197 -0.090 SLICE_X62Y90 FDRE (Hold_fdre_C_D) 0.052 -0.038 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[1] ------------------------------------------------------------------- required time 0.038 arrival time 0.037 ------------------------------------------------------------------- slack 0.075 Slack (MET) : 0.076ns (arrival time - required time) Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_12_17/RAMA_D1/CLK (rising edge-triggered cell RAMD32 clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[13]/D (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: sys_clk Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (sys_clk rise@0.000ns - mlkem_clk_clk_pll rise@0.000ns) Data Path Delay: 0.675ns (logic 0.478ns (70.764%) route 0.197ns (29.236%)) Logic Levels: 0 Clock Path Skew: 0.327ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.385ns Source Clock Delay (SCD): -0.613ns Clock Pessimism Removal (CPR): -0.099ns Clock Uncertainty: 0.197ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.136ns Phase Error (PE): 0.120ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock mlkem_clk_clk_pll rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout3_buf/O net (fo=25775, routed) 0.649 -0.613 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_12_17/WCLK SLICE_X62Y94 RAMD32 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_12_17/RAMA_D1/CLK ------------------------------------------------------------------- ------------------- SLICE_X62Y94 RAMD32 (Prop_ramd32_CLK_O) 0.478 -0.135 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_12_17/RAMA_D1/O net (fo=1, routed) 0.197 0.062 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port10__3[13] SLICE_X62Y92 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[13]/D ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9603, routed) 0.923 -0.385 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/sys_clk SLICE_X62Y92 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[13]/C clock pessimism 0.099 -0.286 clock uncertainty 0.197 -0.090 SLICE_X62Y92 FDRE (Hold_fdre_C_D) 0.076 -0.014 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[13] ------------------------------------------------------------------- required time 0.014 arrival time 0.062 ------------------------------------------------------------------- slack 0.076 Slack (MET) : 0.117ns (arrival time - required time) Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_0_5/RAMB/CLK (rising edge-triggered cell RAMD32 clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[2]/D (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: sys_clk Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (sys_clk rise@0.000ns - mlkem_clk_clk_pll rise@0.000ns) Data Path Delay: 0.631ns (logic 0.394ns (62.467%) route 0.237ns (37.533%)) Logic Levels: 0 Clock Path Skew: 0.327ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.385ns Source Clock Delay (SCD): -0.613ns Clock Pessimism Removal (CPR): -0.099ns Clock Uncertainty: 0.197ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.136ns Phase Error (PE): 0.120ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock mlkem_clk_clk_pll rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout3_buf/O net (fo=25775, routed) 0.649 -0.613 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_0_5/WCLK SLICE_X62Y93 RAMD32 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_0_5/RAMB/CLK ------------------------------------------------------------------- ------------------- SLICE_X62Y93 RAMD32 (Prop_ramd32_CLK_O) 0.394 -0.219 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_0_5/RAMB/O net (fo=1, routed) 0.237 0.017 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port10__3[2] SLICE_X62Y90 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[2]/D ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9603, routed) 0.923 -0.385 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/sys_clk SLICE_X62Y90 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[2]/C clock pessimism 0.099 -0.286 clock uncertainty 0.197 -0.090 SLICE_X62Y90 FDRE (Hold_fdre_C_D) -0.010 -0.100 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[2] ------------------------------------------------------------------- required time 0.100 arrival time 0.017 ------------------------------------------------------------------- slack 0.117 Slack (MET) : 0.119ns (arrival time - required time) Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_6_11/RAMA_D1/CLK (rising edge-triggered cell RAMD32 clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[7]/D (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: sys_clk Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (sys_clk rise@0.000ns - mlkem_clk_clk_pll rise@0.000ns) Data Path Delay: 0.708ns (logic 0.478ns (67.522%) route 0.230ns (32.478%)) Logic Levels: 0 Clock Path Skew: 0.328ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.385ns Source Clock Delay (SCD): -0.614ns Clock Pessimism Removal (CPR): -0.099ns Clock Uncertainty: 0.197ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.136ns Phase Error (PE): 0.120ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock mlkem_clk_clk_pll rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout3_buf/O net (fo=25775, routed) 0.648 -0.614 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_6_11/WCLK SLICE_X64Y94 RAMD32 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_6_11/RAMA_D1/CLK ------------------------------------------------------------------- ------------------- SLICE_X64Y94 RAMD32 (Prop_ramd32_CLK_O) 0.478 -0.136 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_6_11/RAMA_D1/O net (fo=1, routed) 0.230 0.094 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port10__3[7] SLICE_X62Y92 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[7]/D ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9603, routed) 0.923 -0.385 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/sys_clk SLICE_X62Y92 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[7]/C clock pessimism 0.099 -0.286 clock uncertainty 0.197 -0.090 SLICE_X62Y92 FDRE (Hold_fdre_C_D) 0.064 -0.026 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[7] ------------------------------------------------------------------- required time 0.026 arrival time 0.094 ------------------------------------------------------------------- slack 0.119 Slack (MET) : 0.120ns (arrival time - required time) Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_0_5/RAMB_D1/CLK (rising edge-triggered cell RAMD32 clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[3]/D (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: sys_clk Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (sys_clk rise@0.000ns - mlkem_clk_clk_pll rise@0.000ns) Data Path Delay: 0.700ns (logic 0.388ns (55.416%) route 0.312ns (44.584%)) Logic Levels: 0 Clock Path Skew: 0.321ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.391ns Source Clock Delay (SCD): -0.613ns Clock Pessimism Removal (CPR): -0.099ns Clock Uncertainty: 0.197ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.136ns Phase Error (PE): 0.120ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock mlkem_clk_clk_pll rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout3_buf/O net (fo=25775, routed) 0.649 -0.613 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_0_5/WCLK SLICE_X62Y93 RAMD32 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_0_5/RAMB_D1/CLK ------------------------------------------------------------------- ------------------- SLICE_X62Y93 RAMD32 (Prop_ramd32_CLK_O) 0.388 -0.225 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_0_5/RAMB_D1/O net (fo=1, routed) 0.312 0.087 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port10__3[3] SLICE_X62Y83 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[3]/D ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9603, routed) 0.917 -0.391 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/sys_clk SLICE_X62Y83 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[3]/C clock pessimism 0.099 -0.292 clock uncertainty 0.197 -0.096 SLICE_X62Y83 FDRE (Hold_fdre_C_D) 0.063 -0.033 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[3] ------------------------------------------------------------------- required time 0.033 arrival time 0.087 ------------------------------------------------------------------- slack 0.120 Slack (MET) : 0.121ns (arrival time - required time) Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_6_11/RAMB/CLK (rising edge-triggered cell RAMD32 clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[8]/D (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: sys_clk Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (sys_clk rise@0.000ns - mlkem_clk_clk_pll rise@0.000ns) Data Path Delay: 0.636ns (logic 0.394ns (61.991%) route 0.242ns (38.009%)) Logic Levels: 0 Clock Path Skew: 0.328ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.385ns Source Clock Delay (SCD): -0.614ns Clock Pessimism Removal (CPR): -0.099ns Clock Uncertainty: 0.197ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.136ns Phase Error (PE): 0.120ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock mlkem_clk_clk_pll rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout3_buf/O net (fo=25775, routed) 0.648 -0.614 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_6_11/WCLK SLICE_X64Y94 RAMD32 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_6_11/RAMB/CLK ------------------------------------------------------------------- ------------------- SLICE_X64Y94 RAMD32 (Prop_ramd32_CLK_O) 0.394 -0.220 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_6_11/RAMB/O net (fo=1, routed) 0.242 0.021 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port10__3[8] SLICE_X62Y90 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[8]/D ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9603, routed) 0.923 -0.385 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/sys_clk SLICE_X62Y90 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[8]/C clock pessimism 0.099 -0.286 clock uncertainty 0.197 -0.090 SLICE_X62Y90 FDRE (Hold_fdre_C_D) -0.010 -0.100 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[8] ------------------------------------------------------------------- required time 0.100 arrival time 0.021 ------------------------------------------------------------------- slack 0.121 Slack (MET) : 0.123ns (arrival time - required time) Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_30_35/RAMC_D1/CLK (rising edge-triggered cell RAMD32 clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[35]/D (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: sys_clk Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (sys_clk rise@0.000ns - mlkem_clk_clk_pll rise@0.000ns) Data Path Delay: 0.718ns (logic 0.386ns (53.777%) route 0.332ns (46.223%)) Logic Levels: 0 Clock Path Skew: 0.326ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.381ns Source Clock Delay (SCD): -0.608ns Clock Pessimism Removal (CPR): -0.099ns Clock Uncertainty: 0.197ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.136ns Phase Error (PE): 0.120ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock mlkem_clk_clk_pll rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout3_buf/O net (fo=25775, routed) 0.654 -0.608 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_30_35/WCLK SLICE_X46Y93 RAMD32 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_30_35/RAMC_D1/CLK ------------------------------------------------------------------- ------------------- SLICE_X46Y93 RAMD32 (Prop_ramd32_CLK_O) 0.386 -0.222 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_30_35/RAMC_D1/O net (fo=1, routed) 0.332 0.109 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port10__3[35] SLICE_X43Y88 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[35]/D ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9603, routed) 0.927 -0.381 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/sys_clk SLICE_X43Y88 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[35]/C clock pessimism 0.099 -0.282 clock uncertainty 0.197 -0.086 SLICE_X43Y88 FDRE (Hold_fdre_C_D) 0.072 -0.014 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[35] ------------------------------------------------------------------- required time 0.014 arrival time 0.109 ------------------------------------------------------------------- slack 0.123 Slack (MET) : 0.133ns (arrival time - required time) Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_36_39/RAMB/CLK (rising edge-triggered cell RAMD32 clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[38]/D (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: sys_clk Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (sys_clk rise@0.000ns - mlkem_clk_clk_pll rise@0.000ns) Data Path Delay: 0.659ns (logic 0.394ns (59.812%) route 0.265ns (40.188%)) Logic Levels: 0 Clock Path Skew: 0.326ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.381ns Source Clock Delay (SCD): -0.608ns Clock Pessimism Removal (CPR): -0.099ns Clock Uncertainty: 0.197ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.136ns Phase Error (PE): 0.120ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock mlkem_clk_clk_pll rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout3_buf/O net (fo=25775, routed) 0.654 -0.608 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_36_39/WCLK SLICE_X48Y93 RAMD32 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_36_39/RAMB/CLK ------------------------------------------------------------------- ------------------- SLICE_X48Y93 RAMD32 (Prop_ramd32_CLK_O) 0.394 -0.214 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_36_39/RAMB/O net (fo=1, routed) 0.265 0.050 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port10__3[38] SLICE_X43Y88 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[38]/D ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9603, routed) 0.927 -0.381 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/sys_clk SLICE_X43Y88 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[38]/C clock pessimism 0.099 -0.282 clock uncertainty 0.197 -0.086 SLICE_X43Y88 FDRE (Hold_fdre_C_D) 0.003 -0.083 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[38] ------------------------------------------------------------------- required time 0.083 arrival time 0.050 ------------------------------------------------------------------- slack 0.133 Slack (MET) : 0.146ns (arrival time - required time) Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_30_35/RAMC/CLK (rising edge-triggered cell RAMD32 clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[34]/D (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: sys_clk Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (sys_clk rise@0.000ns - mlkem_clk_clk_pll rise@0.000ns) Data Path Delay: 0.647ns (logic 0.390ns (60.239%) route 0.257ns (39.761%)) Logic Levels: 0 Clock Path Skew: 0.326ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.381ns Source Clock Delay (SCD): -0.608ns Clock Pessimism Removal (CPR): -0.099ns Clock Uncertainty: 0.197ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.136ns Phase Error (PE): 0.120ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock mlkem_clk_clk_pll rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout3_buf/O net (fo=25775, routed) 0.654 -0.608 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_30_35/WCLK SLICE_X46Y93 RAMD32 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_30_35/RAMC/CLK ------------------------------------------------------------------- ------------------- SLICE_X46Y93 RAMD32 (Prop_ramd32_CLK_O) 0.390 -0.218 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_30_35/RAMC/O net (fo=1, routed) 0.257 0.039 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port10__3[34] SLICE_X43Y88 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[34]/D ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9603, routed) 0.927 -0.381 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/sys_clk SLICE_X43Y88 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[34]/C clock pessimism 0.099 -0.282 clock uncertainty 0.197 -0.086 SLICE_X43Y88 FDRE (Hold_fdre_C_D) -0.021 -0.107 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[34] ------------------------------------------------------------------- required time 0.107 arrival time 0.039 ------------------------------------------------------------------- slack 0.146 Slack (MET) : 0.149ns (arrival time - required time) Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_18_23/RAMA/CLK (rising edge-triggered cell RAMD32 clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[18]/D (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: sys_clk Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (sys_clk rise@0.000ns - mlkem_clk_clk_pll rise@0.000ns) Data Path Delay: 0.666ns (logic 0.492ns (73.905%) route 0.174ns (26.095%)) Logic Levels: 0 Clock Path Skew: 0.327ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.381ns Source Clock Delay (SCD): -0.609ns Clock Pessimism Removal (CPR): -0.099ns Clock Uncertainty: 0.197ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.136ns Phase Error (PE): 0.120ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock mlkem_clk_clk_pll rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout3_buf/O net (fo=25775, routed) 0.653 -0.609 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_18_23/WCLK SLICE_X56Y93 RAMD32 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_18_23/RAMA/CLK ------------------------------------------------------------------- ------------------- SLICE_X56Y93 RAMD32 (Prop_ramd32_CLK_O) 0.492 -0.117 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_18_23/RAMA/O net (fo=1, routed) 0.174 0.056 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port10__3[18] SLICE_X56Y92 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[18]/D ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9603, routed) 0.927 -0.381 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/sys_clk SLICE_X56Y92 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[18]/C clock pessimism 0.099 -0.282 clock uncertainty 0.197 -0.086 SLICE_X56Y92 FDRE (Hold_fdre_C_D) -0.007 -0.093 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[18] ------------------------------------------------------------------- required time 0.093 arrival time 0.056 ------------------------------------------------------------------- slack 0.149 Slack (MET) : 0.155ns (arrival time - required time) Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_30_35/RAMB/CLK (rising edge-triggered cell RAMD32 clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[32]/D (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: sys_clk Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (sys_clk rise@0.000ns - mlkem_clk_clk_pll rise@0.000ns) Data Path Delay: 0.675ns (logic 0.394ns (58.378%) route 0.281ns (41.622%)) Logic Levels: 0 Clock Path Skew: 0.326ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.381ns Source Clock Delay (SCD): -0.608ns Clock Pessimism Removal (CPR): -0.099ns Clock Uncertainty: 0.197ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.136ns Phase Error (PE): 0.120ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock mlkem_clk_clk_pll rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout3_buf/O net (fo=25775, routed) 0.654 -0.608 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_30_35/WCLK SLICE_X46Y93 RAMD32 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_30_35/RAMB/CLK ------------------------------------------------------------------- ------------------- SLICE_X46Y93 RAMD32 (Prop_ramd32_CLK_O) 0.394 -0.214 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_30_35/RAMB/O net (fo=1, routed) 0.281 0.067 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port10__3[32] SLICE_X43Y88 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[32]/D ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9603, routed) 0.927 -0.381 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/sys_clk SLICE_X43Y88 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[32]/C clock pessimism 0.099 -0.282 clock uncertainty 0.197 -0.086 SLICE_X43Y88 FDRE (Hold_fdre_C_D) -0.003 -0.089 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[32] ------------------------------------------------------------------- required time 0.089 arrival time 0.067 ------------------------------------------------------------------- slack 0.155 Slack (MET) : 0.157ns (arrival time - required time) Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_12_17/RAMC_D1/CLK (rising edge-triggered cell RAMD32 clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[17]/D (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: sys_clk Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (sys_clk rise@0.000ns - mlkem_clk_clk_pll rise@0.000ns) Data Path Delay: 0.755ns (logic 0.386ns (51.148%) route 0.369ns (48.852%)) Logic Levels: 0 Clock Path Skew: 0.331ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.381ns Source Clock Delay (SCD): -0.613ns Clock Pessimism Removal (CPR): -0.099ns Clock Uncertainty: 0.197ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.136ns Phase Error (PE): 0.120ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock mlkem_clk_clk_pll rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout3_buf/O net (fo=25775, routed) 0.649 -0.613 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_12_17/WCLK SLICE_X62Y94 RAMD32 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_12_17/RAMC_D1/CLK ------------------------------------------------------------------- ------------------- SLICE_X62Y94 RAMD32 (Prop_ramd32_CLK_O) 0.386 -0.227 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_12_17/RAMC_D1/O net (fo=1, routed) 0.369 0.141 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port10__3[17] SLICE_X53Y92 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[17]/D ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9603, routed) 0.927 -0.381 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/sys_clk SLICE_X53Y92 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[17]/C clock pessimism 0.099 -0.282 clock uncertainty 0.197 -0.086 SLICE_X53Y92 FDRE (Hold_fdre_C_D) 0.070 -0.016 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[17] ------------------------------------------------------------------- required time 0.016 arrival time 0.141 ------------------------------------------------------------------- slack 0.157 Slack (MET) : 0.160ns (arrival time - required time) Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/popCC_ptrToPush_reg[2]/C (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/popToPushGray_buffercc/buffers_0_reg[2]/D (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: sys_clk Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (sys_clk rise@0.000ns - mlkem_clk_clk_pll rise@0.000ns) Data Path Delay: 0.679ns (logic 0.128ns (18.854%) route 0.551ns (81.146%)) Logic Levels: 0 Clock Path Skew: 0.329ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.387ns Source Clock Delay (SCD): -0.617ns Clock Pessimism Removal (CPR): -0.099ns Clock Uncertainty: 0.197ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.136ns Phase Error (PE): 0.120ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock mlkem_clk_clk_pll rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout3_buf/O net (fo=25775, routed) 0.645 -0.617 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/mlkem_clk SLICE_X73Y96 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/popCC_ptrToPush_reg[2]/C ------------------------------------------------------------------- ------------------- SLICE_X73Y96 FDCE (Prop_fdce_C_Q) 0.128 -0.489 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/popCC_ptrToPush_reg[2]/Q net (fo=1, routed) 0.551 0.062 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/popToPushGray_buffercc/Q[2] SLICE_X73Y97 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/popToPushGray_buffercc/buffers_0_reg[2]/D ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9603, routed) 0.921 -0.387 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/popToPushGray_buffercc/sys_clk SLICE_X73Y97 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/popToPushGray_buffercc/buffers_0_reg[2]/C clock pessimism 0.099 -0.288 clock uncertainty 0.197 -0.092 SLICE_X73Y97 FDCE (Hold_fdce_C_D) -0.007 -0.099 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/popToPushGray_buffercc/buffers_0_reg[2] ------------------------------------------------------------------- required time 0.099 arrival time 0.062 ------------------------------------------------------------------- slack 0.160 Slack (MET) : 0.165ns (arrival time - required time) Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_6_11/RAMB_D1/CLK (rising edge-triggered cell RAMD32 clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[9]/D (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: sys_clk Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (sys_clk rise@0.000ns - mlkem_clk_clk_pll rise@0.000ns) Data Path Delay: 0.747ns (logic 0.388ns (51.964%) route 0.359ns (48.036%)) Logic Levels: 0 Clock Path Skew: 0.324ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.389ns Source Clock Delay (SCD): -0.614ns Clock Pessimism Removal (CPR): -0.099ns Clock Uncertainty: 0.197ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.136ns Phase Error (PE): 0.120ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock mlkem_clk_clk_pll rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout3_buf/O net (fo=25775, routed) 0.648 -0.614 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_6_11/WCLK SLICE_X64Y94 RAMD32 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_6_11/RAMB_D1/CLK ------------------------------------------------------------------- ------------------- SLICE_X64Y94 RAMD32 (Prop_ramd32_CLK_O) 0.388 -0.226 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_6_11/RAMB_D1/O net (fo=1, routed) 0.359 0.132 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port10__3[9] SLICE_X65Y87 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[9]/D ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9603, routed) 0.919 -0.389 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/sys_clk SLICE_X65Y87 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[9]/C clock pessimism 0.099 -0.290 clock uncertainty 0.197 -0.094 SLICE_X65Y87 FDRE (Hold_fdre_C_D) 0.061 -0.033 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[9] ------------------------------------------------------------------- required time 0.033 arrival time 0.132 ------------------------------------------------------------------- slack 0.165 Slack (MET) : 0.166ns (arrival time - required time) Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/popCC_ptrToPush_reg[3]/C (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/popToPushGray_buffercc/buffers_0_reg[3]/D (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: sys_clk Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (sys_clk rise@0.000ns - mlkem_clk_clk_pll rise@0.000ns) Data Path Delay: 0.767ns (logic 0.141ns (18.386%) route 0.626ns (81.614%)) Logic Levels: 0 Clock Path Skew: 0.328ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.388ns Source Clock Delay (SCD): -0.617ns Clock Pessimism Removal (CPR): -0.099ns Clock Uncertainty: 0.197ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.136ns Phase Error (PE): 0.120ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock mlkem_clk_clk_pll rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout3_buf/O net (fo=25775, routed) 0.645 -0.617 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/mlkem_clk SLICE_X73Y96 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/popCC_ptrToPush_reg[3]/C ------------------------------------------------------------------- ------------------- SLICE_X73Y96 FDCE (Prop_fdce_C_Q) 0.141 -0.476 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/popCC_ptrToPush_reg[3]/Q net (fo=1, routed) 0.626 0.150 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/popToPushGray_buffercc/Q[3] SLICE_X72Y96 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/popToPushGray_buffercc/buffers_0_reg[3]/D ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9603, routed) 0.920 -0.388 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/popToPushGray_buffercc/sys_clk SLICE_X72Y96 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/popToPushGray_buffercc/buffers_0_reg[3]/C clock pessimism 0.099 -0.289 clock uncertainty 0.197 -0.093 SLICE_X72Y96 FDCE (Hold_fdce_C_D) 0.076 -0.017 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/popToPushGray_buffercc/buffers_0_reg[3] ------------------------------------------------------------------- required time 0.017 arrival time 0.150 ------------------------------------------------------------------- slack 0.166 Slack (MET) : 0.167ns (arrival time - required time) Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_0_5/RAMC/CLK (rising edge-triggered cell RAMD32 clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[4]/D (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: sys_clk Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (sys_clk rise@0.000ns - mlkem_clk_clk_pll rise@0.000ns) Data Path Delay: 0.683ns (logic 0.390ns (57.099%) route 0.293ns (42.901%)) Logic Levels: 0 Clock Path Skew: 0.327ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.385ns Source Clock Delay (SCD): -0.613ns Clock Pessimism Removal (CPR): -0.099ns Clock Uncertainty: 0.197ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.136ns Phase Error (PE): 0.120ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock mlkem_clk_clk_pll rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout3_buf/O net (fo=25775, routed) 0.649 -0.613 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_0_5/WCLK SLICE_X62Y93 RAMD32 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_0_5/RAMC/CLK ------------------------------------------------------------------- ------------------- SLICE_X62Y93 RAMD32 (Prop_ramd32_CLK_O) 0.390 -0.223 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_0_5/RAMC/O net (fo=1, routed) 0.293 0.070 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port10__3[4] SLICE_X62Y92 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[4]/D ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9603, routed) 0.923 -0.385 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/sys_clk SLICE_X62Y92 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[4]/C clock pessimism 0.099 -0.286 clock uncertainty 0.197 -0.090 SLICE_X62Y92 FDRE (Hold_fdre_C_D) -0.008 -0.098 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[4] ------------------------------------------------------------------- required time 0.098 arrival time 0.070 ------------------------------------------------------------------- slack 0.167 Slack (MET) : 0.168ns (arrival time - required time) Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_18_23/RAMB/CLK (rising edge-triggered cell RAMD32 clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[20]/D (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: sys_clk Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (sys_clk rise@0.000ns - mlkem_clk_clk_pll rise@0.000ns) Data Path Delay: 0.665ns (logic 0.394ns (59.212%) route 0.271ns (40.788%)) Logic Levels: 0 Clock Path Skew: 0.328ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.380ns Source Clock Delay (SCD): -0.609ns Clock Pessimism Removal (CPR): -0.099ns Clock Uncertainty: 0.197ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.136ns Phase Error (PE): 0.120ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock mlkem_clk_clk_pll rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout3_buf/O net (fo=25775, routed) 0.653 -0.609 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_18_23/WCLK SLICE_X56Y93 RAMD32 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_18_23/RAMB/CLK ------------------------------------------------------------------- ------------------- SLICE_X56Y93 RAMD32 (Prop_ramd32_CLK_O) 0.394 -0.215 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_18_23/RAMB/O net (fo=1, routed) 0.271 0.056 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port10__3[20] SLICE_X55Y93 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[20]/D ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9603, routed) 0.928 -0.380 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/sys_clk SLICE_X55Y93 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[20]/C clock pessimism 0.099 -0.281 clock uncertainty 0.197 -0.085 SLICE_X55Y93 FDRE (Hold_fdre_C_D) -0.027 -0.112 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[20] ------------------------------------------------------------------- required time 0.112 arrival time 0.056 ------------------------------------------------------------------- slack 0.168 Slack (MET) : 0.169ns (arrival time - required time) Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/popCC_ptrToPush_reg[1]/C (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/popToPushGray_buffercc/buffers_0_reg[1]/D (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: sys_clk Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (sys_clk rise@0.000ns - mlkem_clk_clk_pll rise@0.000ns) Data Path Delay: 0.741ns (logic 0.141ns (19.027%) route 0.600ns (80.973%)) Logic Levels: 0 Clock Path Skew: 0.328ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.388ns Source Clock Delay (SCD): -0.617ns Clock Pessimism Removal (CPR): -0.099ns Clock Uncertainty: 0.197ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.136ns Phase Error (PE): 0.120ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock mlkem_clk_clk_pll rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout3_buf/O net (fo=25775, routed) 0.645 -0.617 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/mlkem_clk SLICE_X73Y95 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/popCC_ptrToPush_reg[1]/C ------------------------------------------------------------------- ------------------- SLICE_X73Y95 FDCE (Prop_fdce_C_Q) 0.141 -0.476 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/popCC_ptrToPush_reg[1]/Q net (fo=2, routed) 0.600 0.124 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/popToPushGray_buffercc/D[1] SLICE_X73Y94 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/popToPushGray_buffercc/buffers_0_reg[1]/D ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9603, routed) 0.920 -0.388 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/popToPushGray_buffercc/sys_clk SLICE_X73Y94 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/popToPushGray_buffercc/buffers_0_reg[1]/C clock pessimism 0.099 -0.289 clock uncertainty 0.197 -0.093 SLICE_X73Y94 FDCE (Hold_fdce_C_D) 0.047 -0.046 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/popToPushGray_buffercc/buffers_0_reg[1] ------------------------------------------------------------------- required time 0.046 arrival time 0.124 ------------------------------------------------------------------- slack 0.169 Slack (MET) : 0.171ns (arrival time - required time) Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_6_11/RAMC_D1/CLK (rising edge-triggered cell RAMD32 clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[11]/D (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: sys_clk Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (sys_clk rise@0.000ns - mlkem_clk_clk_pll rise@0.000ns) Data Path Delay: 0.771ns (logic 0.386ns (50.090%) route 0.385ns (49.910%)) Logic Levels: 0 Clock Path Skew: 0.328ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.385ns Source Clock Delay (SCD): -0.614ns Clock Pessimism Removal (CPR): -0.099ns Clock Uncertainty: 0.197ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.136ns Phase Error (PE): 0.120ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock mlkem_clk_clk_pll rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout3_buf/O net (fo=25775, routed) 0.648 -0.614 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_6_11/WCLK SLICE_X64Y94 RAMD32 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_6_11/RAMC_D1/CLK ------------------------------------------------------------------- ------------------- SLICE_X64Y94 RAMD32 (Prop_ramd32_CLK_O) 0.386 -0.228 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_6_11/RAMC_D1/O net (fo=1, routed) 0.385 0.156 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port10__3[11] SLICE_X62Y92 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[11]/D ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9603, routed) 0.923 -0.385 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/sys_clk SLICE_X62Y92 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[11]/C clock pessimism 0.099 -0.286 clock uncertainty 0.197 -0.090 SLICE_X62Y92 FDRE (Hold_fdre_C_D) 0.075 -0.015 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[11] ------------------------------------------------------------------- required time 0.015 arrival time 0.156 ------------------------------------------------------------------- slack 0.171 Slack (MET) : 0.172ns (arrival time - required time) Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_18_23/RAMC/CLK (rising edge-triggered cell RAMD32 clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[22]/D (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: sys_clk Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (sys_clk rise@0.000ns - mlkem_clk_clk_pll rise@0.000ns) Data Path Delay: 0.676ns (logic 0.390ns (57.707%) route 0.286ns (42.293%)) Logic Levels: 0 Clock Path Skew: 0.328ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.380ns Source Clock Delay (SCD): -0.609ns Clock Pessimism Removal (CPR): -0.099ns Clock Uncertainty: 0.197ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.136ns Phase Error (PE): 0.120ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock mlkem_clk_clk_pll rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout3_buf/O net (fo=25775, routed) 0.653 -0.609 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_18_23/WCLK SLICE_X56Y93 RAMD32 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_18_23/RAMC/CLK ------------------------------------------------------------------- ------------------- SLICE_X56Y93 RAMD32 (Prop_ramd32_CLK_O) 0.390 -0.219 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_18_23/RAMC/O net (fo=1, routed) 0.286 0.066 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port10__3[22] SLICE_X55Y93 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[22]/D ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9603, routed) 0.928 -0.380 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/sys_clk SLICE_X55Y93 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[22]/C clock pessimism 0.099 -0.281 clock uncertainty 0.197 -0.085 SLICE_X55Y93 FDRE (Hold_fdre_C_D) -0.021 -0.106 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[22] ------------------------------------------------------------------- required time 0.106 arrival time 0.066 ------------------------------------------------------------------- slack 0.172 Slack (MET) : 0.174ns (arrival time - required time) Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_6_11/RAMC/CLK (rising edge-triggered cell RAMD32 clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[10]/D (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: sys_clk Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (sys_clk rise@0.000ns - mlkem_clk_clk_pll rise@0.000ns) Data Path Delay: 0.690ns (logic 0.390ns (56.526%) route 0.300ns (43.474%)) Logic Levels: 0 Clock Path Skew: 0.324ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.389ns Source Clock Delay (SCD): -0.614ns Clock Pessimism Removal (CPR): -0.099ns Clock Uncertainty: 0.197ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.136ns Phase Error (PE): 0.120ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock mlkem_clk_clk_pll rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout3_buf/O net (fo=25775, routed) 0.648 -0.614 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_6_11/WCLK SLICE_X64Y94 RAMD32 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_6_11/RAMC/CLK ------------------------------------------------------------------- ------------------- SLICE_X64Y94 RAMD32 (Prop_ramd32_CLK_O) 0.390 -0.224 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_6_11/RAMC/O net (fo=1, routed) 0.300 0.076 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port10__3[10] SLICE_X65Y87 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[10]/D ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9603, routed) 0.919 -0.389 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/sys_clk SLICE_X65Y87 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[10]/C clock pessimism 0.099 -0.290 clock uncertainty 0.197 -0.094 SLICE_X65Y87 FDRE (Hold_fdre_C_D) -0.005 -0.099 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[10] ------------------------------------------------------------------- required time 0.099 arrival time 0.076 ------------------------------------------------------------------- slack 0.174 Slack (MET) : 0.175ns (arrival time - required time) Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_24_29/RAMC_D1/CLK (rising edge-triggered cell RAMD32 clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[29]/D (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: sys_clk Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (sys_clk rise@0.000ns - mlkem_clk_clk_pll rise@0.000ns) Data Path Delay: 0.777ns (logic 0.386ns (49.658%) route 0.391ns (50.342%)) Logic Levels: 0 Clock Path Skew: 0.328ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.380ns Source Clock Delay (SCD): -0.609ns Clock Pessimism Removal (CPR): -0.099ns Clock Uncertainty: 0.197ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.136ns Phase Error (PE): 0.120ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock mlkem_clk_clk_pll rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout3_buf/O net (fo=25775, routed) 0.653 -0.609 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_24_29/WCLK SLICE_X56Y94 RAMD32 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_24_29/RAMC_D1/CLK ------------------------------------------------------------------- ------------------- SLICE_X56Y94 RAMD32 (Prop_ramd32_CLK_O) 0.386 -0.223 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_24_29/RAMC_D1/O net (fo=1, routed) 0.391 0.168 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port10__3[29] SLICE_X55Y93 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[29]/D ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9603, routed) 0.928 -0.380 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/sys_clk SLICE_X55Y93 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[29]/C clock pessimism 0.099 -0.281 clock uncertainty 0.197 -0.085 SLICE_X55Y93 FDRE (Hold_fdre_C_D) 0.078 -0.007 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[29] ------------------------------------------------------------------- required time 0.007 arrival time 0.168 ------------------------------------------------------------------- slack 0.175 Slack (MET) : 0.179ns (arrival time - required time) Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_24_29/RAMA/CLK (rising edge-triggered cell RAMD32 clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[24]/D (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: sys_clk Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (sys_clk rise@0.000ns - mlkem_clk_clk_pll rise@0.000ns) Data Path Delay: 0.713ns (logic 0.492ns (69.023%) route 0.221ns (30.977%)) Logic Levels: 0 Clock Path Skew: 0.328ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.380ns Source Clock Delay (SCD): -0.609ns Clock Pessimism Removal (CPR): -0.099ns Clock Uncertainty: 0.197ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.136ns Phase Error (PE): 0.120ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock mlkem_clk_clk_pll rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout3_buf/O net (fo=25775, routed) 0.653 -0.609 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_24_29/WCLK SLICE_X56Y94 RAMD32 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_24_29/RAMA/CLK ------------------------------------------------------------------- ------------------- SLICE_X56Y94 RAMD32 (Prop_ramd32_CLK_O) 0.492 -0.117 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_24_29/RAMA/O net (fo=1, routed) 0.221 0.103 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port10__3[24] SLICE_X55Y93 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[24]/D ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9603, routed) 0.928 -0.380 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/sys_clk SLICE_X55Y93 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[24]/C clock pessimism 0.099 -0.281 clock uncertainty 0.197 -0.085 SLICE_X55Y93 FDRE (Hold_fdre_C_D) 0.009 -0.076 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[24] ------------------------------------------------------------------- required time 0.076 arrival time 0.103 ------------------------------------------------------------------- slack 0.179 Slack (MET) : 0.180ns (arrival time - required time) Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_30_35/RAMB_D1/CLK (rising edge-triggered cell RAMD32 clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[33]/D (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: sys_clk Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (sys_clk rise@0.000ns - mlkem_clk_clk_pll rise@0.000ns) Data Path Delay: 0.769ns (logic 0.388ns (50.475%) route 0.381ns (49.525%)) Logic Levels: 0 Clock Path Skew: 0.326ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.381ns Source Clock Delay (SCD): -0.608ns Clock Pessimism Removal (CPR): -0.099ns Clock Uncertainty: 0.197ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.136ns Phase Error (PE): 0.120ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock mlkem_clk_clk_pll rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout3_buf/O net (fo=25775, routed) 0.654 -0.608 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_30_35/WCLK SLICE_X46Y93 RAMD32 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_30_35/RAMB_D1/CLK ------------------------------------------------------------------- ------------------- SLICE_X46Y93 RAMD32 (Prop_ramd32_CLK_O) 0.388 -0.220 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_30_35/RAMB_D1/O net (fo=1, routed) 0.381 0.160 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port10__3[33] SLICE_X43Y88 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[33]/D ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9603, routed) 0.927 -0.381 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/sys_clk SLICE_X43Y88 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[33]/C clock pessimism 0.099 -0.282 clock uncertainty 0.197 -0.086 SLICE_X43Y88 FDRE (Hold_fdre_C_D) 0.066 -0.020 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[33] ------------------------------------------------------------------- required time 0.020 arrival time 0.160 ------------------------------------------------------------------- slack 0.180 Slack (MET) : 0.184ns (arrival time - required time) Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/popCC_ptrToPush_reg[0]/C (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/popToPushGray_buffercc/buffers_0_reg[0]/D (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: sys_clk Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (sys_clk rise@0.000ns - mlkem_clk_clk_pll rise@0.000ns) Data Path Delay: 0.784ns (logic 0.141ns (17.983%) route 0.643ns (82.017%)) Logic Levels: 0 Clock Path Skew: 0.328ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.389ns Source Clock Delay (SCD): -0.618ns Clock Pessimism Removal (CPR): -0.099ns Clock Uncertainty: 0.197ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.136ns Phase Error (PE): 0.120ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock mlkem_clk_clk_pll rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout3_buf/O net (fo=25775, routed) 0.644 -0.618 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/mlkem_clk SLICE_X71Y91 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/popCC_ptrToPush_reg[0]/C ------------------------------------------------------------------- ------------------- SLICE_X71Y91 FDCE (Prop_fdce_C_Q) 0.141 -0.477 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/popCC_ptrToPush_reg[0]/Q net (fo=2, routed) 0.643 0.166 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/popToPushGray_buffercc/D[0] SLICE_X70Y91 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/popToPushGray_buffercc/buffers_0_reg[0]/D ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9603, routed) 0.919 -0.389 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/popToPushGray_buffercc/sys_clk SLICE_X70Y91 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/popToPushGray_buffercc/buffers_0_reg[0]/C clock pessimism 0.099 -0.290 clock uncertainty 0.197 -0.094 SLICE_X70Y91 FDCE (Hold_fdce_C_D) 0.075 -0.019 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/popToPushGray_buffercc/buffers_0_reg[0] ------------------------------------------------------------------- required time 0.019 arrival time 0.166 ------------------------------------------------------------------- slack 0.184 Slack (MET) : 0.186ns (arrival time - required time) Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/popCC_ptrToPush_reg[0]/C (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/popToPushGray_buffercc/buffers_0_reg[0]/D (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: sys_clk Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (sys_clk rise@0.000ns - mlkem_clk_clk_pll rise@0.000ns) Data Path Delay: 0.757ns (logic 0.141ns (18.627%) route 0.616ns (81.373%)) Logic Levels: 0 Clock Path Skew: 0.328ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.388ns Source Clock Delay (SCD): -0.617ns Clock Pessimism Removal (CPR): -0.099ns Clock Uncertainty: 0.197ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.136ns Phase Error (PE): 0.120ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock mlkem_clk_clk_pll rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout3_buf/O net (fo=25775, routed) 0.645 -0.617 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/mlkem_clk SLICE_X73Y95 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/popCC_ptrToPush_reg[0]/C ------------------------------------------------------------------- ------------------- SLICE_X73Y95 FDCE (Prop_fdce_C_Q) 0.141 -0.476 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/popCC_ptrToPush_reg[0]/Q net (fo=2, routed) 0.616 0.140 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/popToPushGray_buffercc/D[0] SLICE_X73Y94 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/popToPushGray_buffercc/buffers_0_reg[0]/D ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9603, routed) 0.920 -0.388 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/popToPushGray_buffercc/sys_clk SLICE_X73Y94 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/popToPushGray_buffercc/buffers_0_reg[0]/C clock pessimism 0.099 -0.289 clock uncertainty 0.197 -0.093 SLICE_X73Y94 FDCE (Hold_fdce_C_D) 0.046 -0.047 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/popToPushGray_buffercc/buffers_0_reg[0] ------------------------------------------------------------------- required time 0.047 arrival time 0.140 ------------------------------------------------------------------- slack 0.186 Slack (MET) : 0.189ns (arrival time - required time) Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_36_39/RAMA_D1/CLK (rising edge-triggered cell RAMD32 clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[37]/D (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: sys_clk Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (sys_clk rise@0.000ns - mlkem_clk_clk_pll rise@0.000ns) Data Path Delay: 0.783ns (logic 0.478ns (61.013%) route 0.305ns (38.987%)) Logic Levels: 0 Clock Path Skew: 0.326ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.381ns Source Clock Delay (SCD): -0.608ns Clock Pessimism Removal (CPR): -0.099ns Clock Uncertainty: 0.197ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.136ns Phase Error (PE): 0.120ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock mlkem_clk_clk_pll rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout3_buf/O net (fo=25775, routed) 0.654 -0.608 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_36_39/WCLK SLICE_X48Y93 RAMD32 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_36_39/RAMA_D1/CLK ------------------------------------------------------------------- ------------------- SLICE_X48Y93 RAMD32 (Prop_ramd32_CLK_O) 0.478 -0.130 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_36_39/RAMA_D1/O net (fo=1, routed) 0.305 0.175 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port10__3[37] SLICE_X47Y92 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[37]/D ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9603, routed) 0.927 -0.381 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/sys_clk SLICE_X47Y92 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[37]/C clock pessimism 0.099 -0.282 clock uncertainty 0.197 -0.086 SLICE_X47Y92 FDRE (Hold_fdre_C_D) 0.072 -0.014 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[37] ------------------------------------------------------------------- required time 0.014 arrival time 0.175 ------------------------------------------------------------------- slack 0.189 Slack (MET) : 0.190ns (arrival time - required time) Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/ram_reg_0_3_0_5/RAMC/CLK (rising edge-triggered cell RAMD32 clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/_zz_ram_port1_reg[4]/D (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: sys_clk Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (sys_clk rise@0.000ns - mlkem_clk_clk_pll rise@0.000ns) Data Path Delay: 0.721ns (logic 0.390ns (54.079%) route 0.331ns (45.921%)) Logic Levels: 0 Clock Path Skew: 0.333ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.380ns Source Clock Delay (SCD): -0.614ns Clock Pessimism Removal (CPR): -0.099ns Clock Uncertainty: 0.197ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.136ns Phase Error (PE): 0.120ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock mlkem_clk_clk_pll rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout3_buf/O net (fo=25775, routed) 0.648 -0.614 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/ram_reg_0_3_0_5/WCLK SLICE_X64Y95 RAMD32 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/ram_reg_0_3_0_5/RAMC/CLK ------------------------------------------------------------------- ------------------- SLICE_X64Y95 RAMD32 (Prop_ramd32_CLK_O) 0.390 -0.224 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/ram_reg_0_3_0_5/RAMC/O net (fo=1, routed) 0.331 0.107 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/_zz_ram_port10__1[4] SLICE_X57Y95 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/_zz_ram_port1_reg[4]/D ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9603, routed) 0.928 -0.380 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/sys_clk SLICE_X57Y95 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/_zz_ram_port1_reg[4]/C clock pessimism 0.099 -0.281 clock uncertainty 0.197 -0.085 SLICE_X57Y95 FDRE (Hold_fdre_C_D) 0.002 -0.083 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/_zz_ram_port1_reg[4] ------------------------------------------------------------------- required time 0.083 arrival time 0.107 ------------------------------------------------------------------- slack 0.190 Slack (MET) : 0.196ns (arrival time - required time) Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/pushCC_pushPtrGray_reg[0]/C (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/pushToPopGray_buffercc/buffers_0_reg[0]/D (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: sys_clk Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (sys_clk rise@0.000ns - mlkem_clk_clk_pll rise@0.000ns) Data Path Delay: 0.795ns (logic 0.164ns (20.617%) route 0.631ns (79.383%)) Logic Levels: 0 Clock Path Skew: 0.328ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.387ns Source Clock Delay (SCD): -0.616ns Clock Pessimism Removal (CPR): -0.099ns Clock Uncertainty: 0.197ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.136ns Phase Error (PE): 0.120ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock mlkem_clk_clk_pll rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout3_buf/O net (fo=25775, routed) 0.646 -0.616 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/mlkem_clk SLICE_X66Y95 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/pushCC_pushPtrGray_reg[0]/C ------------------------------------------------------------------- ------------------- SLICE_X66Y95 FDCE (Prop_fdce_C_Q) 0.164 -0.452 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/pushCC_pushPtrGray_reg[0]/Q net (fo=2, routed) 0.631 0.179 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/pushToPopGray_buffercc/Q[0] SLICE_X66Y96 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/pushToPopGray_buffercc/buffers_0_reg[0]/D ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9603, routed) 0.921 -0.387 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/pushToPopGray_buffercc/sys_clk SLICE_X66Y96 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/pushToPopGray_buffercc/buffers_0_reg[0]/C clock pessimism 0.099 -0.288 clock uncertainty 0.197 -0.092 SLICE_X66Y96 FDCE (Hold_fdce_C_D) 0.075 -0.017 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/pushToPopGray_buffercc/buffers_0_reg[0] ------------------------------------------------------------------- required time 0.017 arrival time 0.179 ------------------------------------------------------------------- slack 0.196 Slack (MET) : 0.198ns (arrival time - required time) Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/pushCC_pushPtrGray_reg[3]/C (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/pushToPopGray_buffercc/buffers_0_reg[3]/D (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: sys_clk Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (sys_clk rise@0.000ns - mlkem_clk_clk_pll rise@0.000ns) Data Path Delay: 0.714ns (logic 0.128ns (17.925%) route 0.586ns (82.076%)) Logic Levels: 0 Clock Path Skew: 0.326ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.386ns Source Clock Delay (SCD): -0.613ns Clock Pessimism Removal (CPR): -0.099ns Clock Uncertainty: 0.197ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.136ns Phase Error (PE): 0.120ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock mlkem_clk_clk_pll rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout3_buf/O net (fo=25775, routed) 0.649 -0.613 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/mlkem_clk SLICE_X63Y93 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/pushCC_pushPtrGray_reg[3]/C ------------------------------------------------------------------- ------------------- SLICE_X63Y93 FDCE (Prop_fdce_C_Q) 0.128 -0.485 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/pushCC_pushPtrGray_reg[3]/Q net (fo=5, routed) 0.586 0.101 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/pushToPopGray_buffercc/D[3] SLICE_X65Y92 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/pushToPopGray_buffercc/buffers_0_reg[3]/D ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9603, routed) 0.922 -0.386 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/pushToPopGray_buffercc/sys_clk SLICE_X65Y92 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/pushToPopGray_buffercc/buffers_0_reg[3]/C clock pessimism 0.099 -0.287 clock uncertainty 0.197 -0.091 SLICE_X65Y92 FDCE (Hold_fdce_C_D) -0.007 -0.098 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/pushToPopGray_buffercc/buffers_0_reg[3] ------------------------------------------------------------------- required time 0.098 arrival time 0.101 ------------------------------------------------------------------- slack 0.198 Slack (MET) : 0.203ns (arrival time - required time) Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/popCC_ptrToPush_reg[2]/C (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/popToPushGray_buffercc/buffers_0_reg[2]/D (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: sys_clk Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (sys_clk rise@0.000ns - mlkem_clk_clk_pll rise@0.000ns) Data Path Delay: 0.774ns (logic 0.141ns (18.218%) route 0.633ns (81.782%)) Logic Levels: 0 Clock Path Skew: 0.328ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.389ns Source Clock Delay (SCD): -0.618ns Clock Pessimism Removal (CPR): -0.099ns Clock Uncertainty: 0.197ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.136ns Phase Error (PE): 0.120ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock mlkem_clk_clk_pll rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout3_buf/O net (fo=25775, routed) 0.644 -0.618 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/mlkem_clk SLICE_X71Y92 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/popCC_ptrToPush_reg[2]/C ------------------------------------------------------------------- ------------------- SLICE_X71Y92 FDCE (Prop_fdce_C_Q) 0.141 -0.477 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/popCC_ptrToPush_reg[2]/Q net (fo=2, routed) 0.633 0.156 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/popToPushGray_buffercc/D[2] SLICE_X73Y92 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/popToPushGray_buffercc/buffers_0_reg[2]/D ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9603, routed) 0.919 -0.389 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/popToPushGray_buffercc/sys_clk SLICE_X73Y92 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/popToPushGray_buffercc/buffers_0_reg[2]/C clock pessimism 0.099 -0.290 clock uncertainty 0.197 -0.094 SLICE_X73Y92 FDCE (Hold_fdce_C_D) 0.046 -0.048 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/popToPushGray_buffercc/buffers_0_reg[2] ------------------------------------------------------------------- required time 0.048 arrival time 0.156 ------------------------------------------------------------------- slack 0.203 Slack (MET) : 0.206ns (arrival time - required time) Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/popCC_ptrToPush_reg[0]/C (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/popToPushGray_buffercc/buffers_0_reg[0]/D (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: sys_clk Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (sys_clk rise@0.000ns - mlkem_clk_clk_pll rise@0.000ns) Data Path Delay: 0.820ns (logic 0.141ns (17.204%) route 0.679ns (82.796%)) Logic Levels: 0 Clock Path Skew: 0.328ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.388ns Source Clock Delay (SCD): -0.617ns Clock Pessimism Removal (CPR): -0.099ns Clock Uncertainty: 0.197ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.136ns Phase Error (PE): 0.120ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock mlkem_clk_clk_pll rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout3_buf/O net (fo=25775, routed) 0.645 -0.617 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/mlkem_clk SLICE_X73Y96 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/popCC_ptrToPush_reg[0]/C ------------------------------------------------------------------- ------------------- SLICE_X73Y96 FDCE (Prop_fdce_C_Q) 0.141 -0.476 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/popCC_ptrToPush_reg[0]/Q net (fo=1, routed) 0.679 0.202 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/popToPushGray_buffercc/Q[0] SLICE_X72Y96 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/popToPushGray_buffercc/buffers_0_reg[0]/D ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9603, routed) 0.920 -0.388 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/popToPushGray_buffercc/sys_clk SLICE_X72Y96 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/popToPushGray_buffercc/buffers_0_reg[0]/C clock pessimism 0.099 -0.289 clock uncertainty 0.197 -0.093 SLICE_X72Y96 FDCE (Hold_fdce_C_D) 0.089 -0.004 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/popToPushGray_buffercc/buffers_0_reg[0] ------------------------------------------------------------------- required time 0.004 arrival time 0.202 ------------------------------------------------------------------- slack 0.206 Slack (MET) : 0.210ns (arrival time - required time) Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/pushCC_pushPtrGray_reg[2]/C (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/pushToPopGray_buffercc/buffers_0_reg[2]/D (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: sys_clk Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (sys_clk rise@0.000ns - mlkem_clk_clk_pll rise@0.000ns) Data Path Delay: 0.757ns (logic 0.148ns (19.543%) route 0.609ns (80.457%)) Logic Levels: 0 Clock Path Skew: 0.328ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.387ns Source Clock Delay (SCD): -0.616ns Clock Pessimism Removal (CPR): -0.099ns Clock Uncertainty: 0.197ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.136ns Phase Error (PE): 0.120ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock mlkem_clk_clk_pll rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout3_buf/O net (fo=25775, routed) 0.646 -0.616 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/mlkem_clk SLICE_X66Y95 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/pushCC_pushPtrGray_reg[2]/C ------------------------------------------------------------------- ------------------- SLICE_X66Y95 FDCE (Prop_fdce_C_Q) 0.148 -0.468 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/pushCC_pushPtrGray_reg[2]/Q net (fo=4, routed) 0.609 0.141 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/pushToPopGray_buffercc/buffers_0_reg[2]_0 SLICE_X66Y96 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/pushToPopGray_buffercc/buffers_0_reg[2]/D ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9603, routed) 0.921 -0.387 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/pushToPopGray_buffercc/sys_clk SLICE_X66Y96 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/pushToPopGray_buffercc/buffers_0_reg[2]/C clock pessimism 0.099 -0.288 clock uncertainty 0.197 -0.092 SLICE_X66Y96 FDCE (Hold_fdce_C_D) 0.023 -0.069 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/pushToPopGray_buffercc/buffers_0_reg[2] ------------------------------------------------------------------- required time 0.069 arrival time 0.141 ------------------------------------------------------------------- slack 0.210 Slack (MET) : 0.212ns (arrival time - required time) Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/pushCC_pushPtrGray_reg[2]/C (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/pushToPopGray_buffercc/buffers_0_reg[2]/D (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: sys_clk Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (sys_clk rise@0.000ns - mlkem_clk_clk_pll rise@0.000ns) Data Path Delay: 0.781ns (logic 0.141ns (18.051%) route 0.640ns (81.949%)) Logic Levels: 0 Clock Path Skew: 0.326ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.386ns Source Clock Delay (SCD): -0.613ns Clock Pessimism Removal (CPR): -0.099ns Clock Uncertainty: 0.197ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.136ns Phase Error (PE): 0.120ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock mlkem_clk_clk_pll rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout3_buf/O net (fo=25775, routed) 0.649 -0.613 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/mlkem_clk SLICE_X63Y93 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/pushCC_pushPtrGray_reg[2]/C ------------------------------------------------------------------- ------------------- SLICE_X63Y93 FDCE (Prop_fdce_C_Q) 0.141 -0.472 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/pushCC_pushPtrGray_reg[2]/Q net (fo=3, routed) 0.640 0.168 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/pushToPopGray_buffercc/D[2] SLICE_X65Y92 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/pushToPopGray_buffercc/buffers_0_reg[2]/D ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9603, routed) 0.922 -0.386 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/pushToPopGray_buffercc/sys_clk SLICE_X65Y92 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/pushToPopGray_buffercc/buffers_0_reg[2]/C clock pessimism 0.099 -0.287 clock uncertainty 0.197 -0.091 SLICE_X65Y92 FDCE (Hold_fdce_C_D) 0.046 -0.045 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/pushToPopGray_buffercc/buffers_0_reg[2] ------------------------------------------------------------------- required time 0.045 arrival time 0.168 ------------------------------------------------------------------- slack 0.212 Slack (MET) : 0.223ns (arrival time - required time) Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_30_35/RAMA/CLK (rising edge-triggered cell RAMD32 clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[30]/D (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: sys_clk Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (sys_clk rise@0.000ns - mlkem_clk_clk_pll rise@0.000ns) Data Path Delay: 0.740ns (logic 0.492ns (66.478%) route 0.248ns (33.522%)) Logic Levels: 0 Clock Path Skew: 0.327ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.380ns Source Clock Delay (SCD): -0.608ns Clock Pessimism Removal (CPR): -0.099ns Clock Uncertainty: 0.197ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.136ns Phase Error (PE): 0.120ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock mlkem_clk_clk_pll rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout3_buf/O net (fo=25775, routed) 0.654 -0.608 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_30_35/WCLK SLICE_X46Y93 RAMD32 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_30_35/RAMA/CLK ------------------------------------------------------------------- ------------------- SLICE_X46Y93 RAMD32 (Prop_ramd32_CLK_O) 0.492 -0.116 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_30_35/RAMA/O net (fo=1, routed) 0.248 0.132 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port10__3[30] SLICE_X44Y92 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[30]/D ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9603, routed) 0.928 -0.380 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/sys_clk SLICE_X44Y92 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[30]/C clock pessimism 0.099 -0.281 clock uncertainty 0.197 -0.085 SLICE_X44Y92 FDRE (Hold_fdre_C_D) -0.007 -0.092 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[30] ------------------------------------------------------------------- required time 0.092 arrival time 0.132 ------------------------------------------------------------------- slack 0.223 Slack (MET) : 0.224ns (arrival time - required time) Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/popCC_ptrToPush_reg[2]/C (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/popToPushGray_buffercc/buffers_0_reg[2]/D (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: sys_clk Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (sys_clk rise@0.000ns - mlkem_clk_clk_pll rise@0.000ns) Data Path Delay: 0.796ns (logic 0.141ns (17.715%) route 0.655ns (82.285%)) Logic Levels: 0 Clock Path Skew: 0.328ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.388ns Source Clock Delay (SCD): -0.617ns Clock Pessimism Removal (CPR): -0.099ns Clock Uncertainty: 0.197ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.136ns Phase Error (PE): 0.120ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock mlkem_clk_clk_pll rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout3_buf/O net (fo=25775, routed) 0.645 -0.617 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/mlkem_clk SLICE_X73Y95 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/popCC_ptrToPush_reg[2]/C ------------------------------------------------------------------- ------------------- SLICE_X73Y95 FDCE (Prop_fdce_C_Q) 0.141 -0.476 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/popCC_ptrToPush_reg[2]/Q net (fo=2, routed) 0.655 0.179 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/popToPushGray_buffercc/D[2] SLICE_X73Y94 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/popToPushGray_buffercc/buffers_0_reg[2]/D ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9603, routed) 0.920 -0.388 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/popToPushGray_buffercc/sys_clk SLICE_X73Y94 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/popToPushGray_buffercc/buffers_0_reg[2]/C clock pessimism 0.099 -0.289 clock uncertainty 0.197 -0.093 SLICE_X73Y94 FDCE (Hold_fdce_C_D) 0.047 -0.046 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/popToPushGray_buffercc/buffers_0_reg[2] ------------------------------------------------------------------- required time 0.046 arrival time 0.179 ------------------------------------------------------------------- slack 0.224 Slack (MET) : 0.225ns (arrival time - required time) Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/popCC_ptrToPush_reg[1]/C (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/popToPushGray_buffercc/buffers_0_reg[1]/D (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: sys_clk Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (sys_clk rise@0.000ns - mlkem_clk_clk_pll rise@0.000ns) Data Path Delay: 0.796ns (logic 0.141ns (17.709%) route 0.655ns (82.291%)) Logic Levels: 0 Clock Path Skew: 0.329ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.387ns Source Clock Delay (SCD): -0.617ns Clock Pessimism Removal (CPR): -0.099ns Clock Uncertainty: 0.197ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.136ns Phase Error (PE): 0.120ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock mlkem_clk_clk_pll rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout3_buf/O net (fo=25775, routed) 0.645 -0.617 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/mlkem_clk SLICE_X73Y96 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/popCC_ptrToPush_reg[1]/C ------------------------------------------------------------------- ------------------- SLICE_X73Y96 FDCE (Prop_fdce_C_Q) 0.141 -0.476 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/popCC_ptrToPush_reg[1]/Q net (fo=1, routed) 0.655 0.179 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/popToPushGray_buffercc/Q[1] SLICE_X73Y97 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/popToPushGray_buffercc/buffers_0_reg[1]/D ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9603, routed) 0.921 -0.387 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/popToPushGray_buffercc/sys_clk SLICE_X73Y97 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/popToPushGray_buffercc/buffers_0_reg[1]/C clock pessimism 0.099 -0.288 clock uncertainty 0.197 -0.092 SLICE_X73Y97 FDCE (Hold_fdce_C_D) 0.046 -0.046 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/popToPushGray_buffercc/buffers_0_reg[1] ------------------------------------------------------------------- required time 0.046 arrival time 0.179 ------------------------------------------------------------------- slack 0.225 Slack (MET) : 0.232ns (arrival time - required time) Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_12_17/RAMA/CLK (rising edge-triggered cell RAMD32 clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[12]/D (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: sys_clk Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (sys_clk rise@0.000ns - mlkem_clk_clk_pll rise@0.000ns) Data Path Delay: 0.749ns (logic 0.492ns (65.718%) route 0.257ns (34.282%)) Logic Levels: 0 Clock Path Skew: 0.327ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.385ns Source Clock Delay (SCD): -0.613ns Clock Pessimism Removal (CPR): -0.099ns Clock Uncertainty: 0.197ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.136ns Phase Error (PE): 0.120ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock mlkem_clk_clk_pll rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout3_buf/O net (fo=25775, routed) 0.649 -0.613 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_12_17/WCLK SLICE_X62Y94 RAMD32 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_12_17/RAMA/CLK ------------------------------------------------------------------- ------------------- SLICE_X62Y94 RAMD32 (Prop_ramd32_CLK_O) 0.492 -0.121 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_12_17/RAMA/O net (fo=1, routed) 0.257 0.135 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port10__3[12] SLICE_X62Y90 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[12]/D ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9603, routed) 0.923 -0.385 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/sys_clk SLICE_X62Y90 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[12]/C clock pessimism 0.099 -0.286 clock uncertainty 0.197 -0.090 SLICE_X62Y90 FDRE (Hold_fdre_C_D) -0.007 -0.097 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[12] ------------------------------------------------------------------- required time 0.097 arrival time 0.135 ------------------------------------------------------------------- slack 0.232 Slack (MET) : 0.237ns (arrival time - required time) Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/popCC_ptrToPush_reg[1]/C (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/popToPushGray_buffercc/buffers_0_reg[1]/D (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: sys_clk Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (sys_clk rise@0.000ns - mlkem_clk_clk_pll rise@0.000ns) Data Path Delay: 0.838ns (logic 0.141ns (16.825%) route 0.697ns (83.175%)) Logic Levels: 0 Clock Path Skew: 0.328ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.389ns Source Clock Delay (SCD): -0.618ns Clock Pessimism Removal (CPR): -0.099ns Clock Uncertainty: 0.197ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.136ns Phase Error (PE): 0.120ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock mlkem_clk_clk_pll rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout3_buf/O net (fo=25775, routed) 0.644 -0.618 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/mlkem_clk SLICE_X71Y91 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/popCC_ptrToPush_reg[1]/C ------------------------------------------------------------------- ------------------- SLICE_X71Y91 FDCE (Prop_fdce_C_Q) 0.141 -0.477 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/popCC_ptrToPush_reg[1]/Q net (fo=2, routed) 0.697 0.220 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/popToPushGray_buffercc/D[1] SLICE_X70Y91 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/popToPushGray_buffercc/buffers_0_reg[1]/D ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9603, routed) 0.919 -0.389 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/popToPushGray_buffercc/sys_clk SLICE_X70Y91 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/popToPushGray_buffercc/buffers_0_reg[1]/C clock pessimism 0.099 -0.290 clock uncertainty 0.197 -0.094 SLICE_X70Y91 FDCE (Hold_fdce_C_D) 0.076 -0.018 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/popToPushGray_buffercc/buffers_0_reg[1] ------------------------------------------------------------------- required time 0.018 arrival time 0.220 ------------------------------------------------------------------- slack 0.237 Slack (MET) : 0.241ns (arrival time - required time) Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_12_17/RAMB_D1/CLK (rising edge-triggered cell RAMD32 clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[15]/D (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: sys_clk Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (sys_clk rise@0.000ns - mlkem_clk_clk_pll rise@0.000ns) Data Path Delay: 0.841ns (logic 0.388ns (46.144%) route 0.453ns (53.856%)) Logic Levels: 0 Clock Path Skew: 0.327ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.385ns Source Clock Delay (SCD): -0.613ns Clock Pessimism Removal (CPR): -0.099ns Clock Uncertainty: 0.197ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.136ns Phase Error (PE): 0.120ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock mlkem_clk_clk_pll rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout3_buf/O net (fo=25775, routed) 0.649 -0.613 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_12_17/WCLK SLICE_X62Y94 RAMD32 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_12_17/RAMB_D1/CLK ------------------------------------------------------------------- ------------------- SLICE_X62Y94 RAMD32 (Prop_ramd32_CLK_O) 0.388 -0.225 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_12_17/RAMB_D1/O net (fo=1, routed) 0.453 0.227 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port10__3[15] SLICE_X62Y92 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[15]/D ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9603, routed) 0.923 -0.385 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/sys_clk SLICE_X62Y92 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[15]/C clock pessimism 0.099 -0.286 clock uncertainty 0.197 -0.090 SLICE_X62Y92 FDRE (Hold_fdre_C_D) 0.076 -0.014 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[15] ------------------------------------------------------------------- required time 0.014 arrival time 0.227 ------------------------------------------------------------------- slack 0.241 Slack (MET) : 0.248ns (arrival time - required time) Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/pushCC_pushPtrGray_reg[1]/C (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/pushToPopGray_buffercc/buffers_0_reg[1]/D (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: sys_clk Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (sys_clk rise@0.000ns - mlkem_clk_clk_pll rise@0.000ns) Data Path Delay: 0.849ns (logic 0.164ns (19.319%) route 0.685ns (80.681%)) Logic Levels: 0 Clock Path Skew: 0.328ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.387ns Source Clock Delay (SCD): -0.616ns Clock Pessimism Removal (CPR): -0.099ns Clock Uncertainty: 0.197ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.136ns Phase Error (PE): 0.120ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock mlkem_clk_clk_pll rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout3_buf/O net (fo=25775, routed) 0.646 -0.616 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/mlkem_clk SLICE_X66Y95 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/pushCC_pushPtrGray_reg[1]/C ------------------------------------------------------------------- ------------------- SLICE_X66Y95 FDCE (Prop_fdce_C_Q) 0.164 -0.452 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/pushCC_pushPtrGray_reg[1]/Q net (fo=2, routed) 0.685 0.233 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/pushToPopGray_buffercc/Q[1] SLICE_X66Y96 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/pushToPopGray_buffercc/buffers_0_reg[1]/D ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9603, routed) 0.921 -0.387 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/pushToPopGray_buffercc/sys_clk SLICE_X66Y96 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/pushToPopGray_buffercc/buffers_0_reg[1]/C clock pessimism 0.099 -0.288 clock uncertainty 0.197 -0.092 SLICE_X66Y96 FDCE (Hold_fdce_C_D) 0.076 -0.016 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/pushToPopGray_buffercc/buffers_0_reg[1] ------------------------------------------------------------------- required time 0.016 arrival time 0.233 ------------------------------------------------------------------- slack 0.248 Slack (MET) : 0.249ns (arrival time - required time) Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/done_sync_reg[1]/C (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) Destination: u_fft_mlkem_axi_slave/mlkem_intr_sync_reg[0]/D (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: sys_clk Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (sys_clk rise@0.000ns - mlkem_clk_clk_pll rise@0.000ns) Data Path Delay: 0.860ns (logic 0.148ns (17.206%) route 0.712ns (82.794%)) Logic Levels: 0 Clock Path Skew: 0.394ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.382ns Source Clock Delay (SCD): -0.677ns Clock Pessimism Removal (CPR): -0.099ns Clock Uncertainty: 0.197ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.136ns Phase Error (PE): 0.120ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock mlkem_clk_clk_pll rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout3_buf/O net (fo=25775, routed) 0.586 -0.677 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/mlkem_clk SLICE_X60Y102 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/done_sync_reg[1]/C ------------------------------------------------------------------- ------------------- SLICE_X60Y102 FDCE (Prop_fdce_C_Q) 0.148 -0.529 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/done_sync_reg[1]/Q net (fo=2, routed) 0.712 0.183 u_fft_mlkem_axi_slave/mlkem_intr_m SLICE_X60Y93 FDCE r u_fft_mlkem_axi_slave/mlkem_intr_sync_reg[0]/D ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9603, routed) 0.926 -0.382 u_fft_mlkem_axi_slave/sys_clk SLICE_X60Y93 FDCE r u_fft_mlkem_axi_slave/mlkem_intr_sync_reg[0]/C clock pessimism 0.099 -0.283 clock uncertainty 0.197 -0.087 SLICE_X60Y93 FDCE (Hold_fdce_C_D) 0.021 -0.066 u_fft_mlkem_axi_slave/mlkem_intr_sync_reg[0] ------------------------------------------------------------------- required time 0.066 arrival time 0.183 ------------------------------------------------------------------- slack 0.249 Slack (MET) : 0.251ns (arrival time - required time) Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_30_35/RAMA_D1/CLK (rising edge-triggered cell RAMD32 clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[31]/D (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: sys_clk Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (sys_clk rise@0.000ns - mlkem_clk_clk_pll rise@0.000ns) Data Path Delay: 0.840ns (logic 0.478ns (56.936%) route 0.362ns (43.064%)) Logic Levels: 0 Clock Path Skew: 0.326ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.381ns Source Clock Delay (SCD): -0.608ns Clock Pessimism Removal (CPR): -0.099ns Clock Uncertainty: 0.197ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.136ns Phase Error (PE): 0.120ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock mlkem_clk_clk_pll rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout3_buf/O net (fo=25775, routed) 0.654 -0.608 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_30_35/WCLK SLICE_X46Y93 RAMD32 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_30_35/RAMA_D1/CLK ------------------------------------------------------------------- ------------------- SLICE_X46Y93 RAMD32 (Prop_ramd32_CLK_O) 0.478 -0.130 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_30_35/RAMA_D1/O net (fo=1, routed) 0.362 0.231 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port10__3[31] SLICE_X47Y92 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[31]/D ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9603, routed) 0.927 -0.381 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/sys_clk SLICE_X47Y92 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[31]/C clock pessimism 0.099 -0.282 clock uncertainty 0.197 -0.086 SLICE_X47Y92 FDRE (Hold_fdre_C_D) 0.066 -0.020 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[31] ------------------------------------------------------------------- required time 0.020 arrival time 0.231 ------------------------------------------------------------------- slack 0.251 Slack (MET) : 0.259ns (arrival time - required time) Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/pushCC_pushPtrGray_reg[0]/C (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/pushToPopGray_buffercc/buffers_0_reg[0]/D (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: sys_clk Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (sys_clk rise@0.000ns - mlkem_clk_clk_pll rise@0.000ns) Data Path Delay: 0.829ns (logic 0.164ns (19.771%) route 0.665ns (80.229%)) Logic Levels: 0 Clock Path Skew: 0.328ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.385ns Source Clock Delay (SCD): -0.614ns Clock Pessimism Removal (CPR): -0.099ns Clock Uncertainty: 0.197ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.136ns Phase Error (PE): 0.120ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock mlkem_clk_clk_pll rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout3_buf/O net (fo=25775, routed) 0.648 -0.614 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/mlkem_clk SLICE_X64Y93 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/pushCC_pushPtrGray_reg[0]/C ------------------------------------------------------------------- ------------------- SLICE_X64Y93 FDCE (Prop_fdce_C_Q) 0.164 -0.450 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/pushCC_pushPtrGray_reg[0]/Q net (fo=2, routed) 0.665 0.215 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/pushToPopGray_buffercc/D[0] SLICE_X65Y94 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/pushToPopGray_buffercc/buffers_0_reg[0]/D ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9603, routed) 0.923 -0.385 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/pushToPopGray_buffercc/sys_clk SLICE_X65Y94 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/pushToPopGray_buffercc/buffers_0_reg[0]/C clock pessimism 0.099 -0.286 clock uncertainty 0.197 -0.090 SLICE_X65Y94 FDCE (Hold_fdce_C_D) 0.046 -0.044 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/pushToPopGray_buffercc/buffers_0_reg[0] ------------------------------------------------------------------- required time 0.044 arrival time 0.215 ------------------------------------------------------------------- slack 0.259 --------------------------------------------------------------------------------------------------- Path Group: **async_default** From Clock: cpu_clk To Clock: cpu_clk Setup : NA Failing Endpoints, Worst Slack NA , Total Violation NA Hold : 0 Failing Endpoints, Worst Slack 0.746ns, Total Violation 0.000ns --------------------------------------------------------------------------------------------------- Min Delay Paths -------------------------------------------------------------------------------------- Slack (MET) : 0.746ns (arrival time - required time) Source: pll_clk.u_rst_cpu/delay_reg[1]/C (rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Destination: u_Axi_CDC/wFifo/popToPushGray_buffercc/buffers_0_reg[1]/CLR (removal check against rising-edge clock cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) Data Path Delay: 0.694ns (logic 0.209ns (30.099%) route 0.485ns (69.901%)) Logic Levels: 1 (LUT1=1) Clock Path Skew: 0.015ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.337ns Source Clock Delay (SCD): -0.544ns Clock Pessimism Removal (CPR): 0.192ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 0.718 -0.544 pll_clk.u_rst_cpu/cpu_clk SLICE_X6Y63 FDCE r pll_clk.u_rst_cpu/delay_reg[1]/C ------------------------------------------------------------------- ------------------- SLICE_X6Y63 FDCE (Prop_fdce_C_Q) 0.164 -0.380 r pll_clk.u_rst_cpu/delay_reg[1]/Q net (fo=1, routed) 0.221 -0.159 pll_clk.u_rst_cpu/cpu_resetn SLICE_X6Y63 LUT1 (Prop_lut1_I0_O) 0.045 -0.114 f pll_clk.u_rst_cpu/reset_i_1/O net (fo=40, routed) 0.264 0.150 u_Axi_CDC/wFifo/popToPushGray_buffercc/p_0_in SLICE_X8Y59 FDCE f u_Axi_CDC/wFifo/popToPushGray_buffercc/buffers_0_reg[1]/CLR ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 0.971 -0.337 u_Axi_CDC/wFifo/popToPushGray_buffercc/cpu_clk SLICE_X8Y59 FDCE r u_Axi_CDC/wFifo/popToPushGray_buffercc/buffers_0_reg[1]/C clock pessimism -0.192 -0.529 SLICE_X8Y59 FDCE (Remov_fdce_C_CLR) -0.067 -0.596 u_Axi_CDC/wFifo/popToPushGray_buffercc/buffers_0_reg[1] ------------------------------------------------------------------- required time 0.596 arrival time 0.150 ------------------------------------------------------------------- slack 0.746 Slack (MET) : 0.746ns (arrival time - required time) Source: pll_clk.u_rst_cpu/delay_reg[1]/C (rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Destination: u_Axi_CDC/wFifo/popToPushGray_buffercc/buffers_0_reg[2]/CLR (removal check against rising-edge clock cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) Data Path Delay: 0.694ns (logic 0.209ns (30.099%) route 0.485ns (69.901%)) Logic Levels: 1 (LUT1=1) Clock Path Skew: 0.015ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.337ns Source Clock Delay (SCD): -0.544ns Clock Pessimism Removal (CPR): 0.192ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 0.718 -0.544 pll_clk.u_rst_cpu/cpu_clk SLICE_X6Y63 FDCE r pll_clk.u_rst_cpu/delay_reg[1]/C ------------------------------------------------------------------- ------------------- SLICE_X6Y63 FDCE (Prop_fdce_C_Q) 0.164 -0.380 r pll_clk.u_rst_cpu/delay_reg[1]/Q net (fo=1, routed) 0.221 -0.159 pll_clk.u_rst_cpu/cpu_resetn SLICE_X6Y63 LUT1 (Prop_lut1_I0_O) 0.045 -0.114 f pll_clk.u_rst_cpu/reset_i_1/O net (fo=40, routed) 0.264 0.150 u_Axi_CDC/wFifo/popToPushGray_buffercc/p_0_in SLICE_X8Y59 FDCE f u_Axi_CDC/wFifo/popToPushGray_buffercc/buffers_0_reg[2]/CLR ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 0.971 -0.337 u_Axi_CDC/wFifo/popToPushGray_buffercc/cpu_clk SLICE_X8Y59 FDCE r u_Axi_CDC/wFifo/popToPushGray_buffercc/buffers_0_reg[2]/C clock pessimism -0.192 -0.529 SLICE_X8Y59 FDCE (Remov_fdce_C_CLR) -0.067 -0.596 u_Axi_CDC/wFifo/popToPushGray_buffercc/buffers_0_reg[2] ------------------------------------------------------------------- required time 0.596 arrival time 0.150 ------------------------------------------------------------------- slack 0.746 Slack (MET) : 0.746ns (arrival time - required time) Source: pll_clk.u_rst_cpu/delay_reg[1]/C (rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Destination: u_Axi_CDC/wFifo/popToPushGray_buffercc/buffers_0_reg[3]/CLR (removal check against rising-edge clock cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) Data Path Delay: 0.694ns (logic 0.209ns (30.099%) route 0.485ns (69.901%)) Logic Levels: 1 (LUT1=1) Clock Path Skew: 0.015ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.337ns Source Clock Delay (SCD): -0.544ns Clock Pessimism Removal (CPR): 0.192ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 0.718 -0.544 pll_clk.u_rst_cpu/cpu_clk SLICE_X6Y63 FDCE r pll_clk.u_rst_cpu/delay_reg[1]/C ------------------------------------------------------------------- ------------------- SLICE_X6Y63 FDCE (Prop_fdce_C_Q) 0.164 -0.380 r pll_clk.u_rst_cpu/delay_reg[1]/Q net (fo=1, routed) 0.221 -0.159 pll_clk.u_rst_cpu/cpu_resetn SLICE_X6Y63 LUT1 (Prop_lut1_I0_O) 0.045 -0.114 f pll_clk.u_rst_cpu/reset_i_1/O net (fo=40, routed) 0.264 0.150 u_Axi_CDC/wFifo/popToPushGray_buffercc/p_0_in SLICE_X8Y59 FDCE f u_Axi_CDC/wFifo/popToPushGray_buffercc/buffers_0_reg[3]/CLR ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 0.971 -0.337 u_Axi_CDC/wFifo/popToPushGray_buffercc/cpu_clk SLICE_X8Y59 FDCE r u_Axi_CDC/wFifo/popToPushGray_buffercc/buffers_0_reg[3]/C clock pessimism -0.192 -0.529 SLICE_X8Y59 FDCE (Remov_fdce_C_CLR) -0.067 -0.596 u_Axi_CDC/wFifo/popToPushGray_buffercc/buffers_0_reg[3] ------------------------------------------------------------------- required time 0.596 arrival time 0.150 ------------------------------------------------------------------- slack 0.746 Slack (MET) : 0.746ns (arrival time - required time) Source: pll_clk.u_rst_cpu/delay_reg[1]/C (rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Destination: u_Axi_CDC/wFifo/popToPushGray_buffercc/buffers_1_reg[1]/CLR (removal check against rising-edge clock cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) Data Path Delay: 0.694ns (logic 0.209ns (30.099%) route 0.485ns (69.901%)) Logic Levels: 1 (LUT1=1) Clock Path Skew: 0.015ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.337ns Source Clock Delay (SCD): -0.544ns Clock Pessimism Removal (CPR): 0.192ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 0.718 -0.544 pll_clk.u_rst_cpu/cpu_clk SLICE_X6Y63 FDCE r pll_clk.u_rst_cpu/delay_reg[1]/C ------------------------------------------------------------------- ------------------- SLICE_X6Y63 FDCE (Prop_fdce_C_Q) 0.164 -0.380 r pll_clk.u_rst_cpu/delay_reg[1]/Q net (fo=1, routed) 0.221 -0.159 pll_clk.u_rst_cpu/cpu_resetn SLICE_X6Y63 LUT1 (Prop_lut1_I0_O) 0.045 -0.114 f pll_clk.u_rst_cpu/reset_i_1/O net (fo=40, routed) 0.264 0.150 u_Axi_CDC/wFifo/popToPushGray_buffercc/p_0_in SLICE_X8Y59 FDCE f u_Axi_CDC/wFifo/popToPushGray_buffercc/buffers_1_reg[1]/CLR ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 0.971 -0.337 u_Axi_CDC/wFifo/popToPushGray_buffercc/cpu_clk SLICE_X8Y59 FDCE r u_Axi_CDC/wFifo/popToPushGray_buffercc/buffers_1_reg[1]/C clock pessimism -0.192 -0.529 SLICE_X8Y59 FDCE (Remov_fdce_C_CLR) -0.067 -0.596 u_Axi_CDC/wFifo/popToPushGray_buffercc/buffers_1_reg[1] ------------------------------------------------------------------- required time 0.596 arrival time 0.150 ------------------------------------------------------------------- slack 0.746 Slack (MET) : 0.746ns (arrival time - required time) Source: pll_clk.u_rst_cpu/delay_reg[1]/C (rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Destination: u_Axi_CDC/wFifo/popToPushGray_buffercc/buffers_1_reg[2]/CLR (removal check against rising-edge clock cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) Data Path Delay: 0.694ns (logic 0.209ns (30.099%) route 0.485ns (69.901%)) Logic Levels: 1 (LUT1=1) Clock Path Skew: 0.015ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.337ns Source Clock Delay (SCD): -0.544ns Clock Pessimism Removal (CPR): 0.192ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 0.718 -0.544 pll_clk.u_rst_cpu/cpu_clk SLICE_X6Y63 FDCE r pll_clk.u_rst_cpu/delay_reg[1]/C ------------------------------------------------------------------- ------------------- SLICE_X6Y63 FDCE (Prop_fdce_C_Q) 0.164 -0.380 r pll_clk.u_rst_cpu/delay_reg[1]/Q net (fo=1, routed) 0.221 -0.159 pll_clk.u_rst_cpu/cpu_resetn SLICE_X6Y63 LUT1 (Prop_lut1_I0_O) 0.045 -0.114 f pll_clk.u_rst_cpu/reset_i_1/O net (fo=40, routed) 0.264 0.150 u_Axi_CDC/wFifo/popToPushGray_buffercc/p_0_in SLICE_X8Y59 FDCE f u_Axi_CDC/wFifo/popToPushGray_buffercc/buffers_1_reg[2]/CLR ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 0.971 -0.337 u_Axi_CDC/wFifo/popToPushGray_buffercc/cpu_clk SLICE_X8Y59 FDCE r u_Axi_CDC/wFifo/popToPushGray_buffercc/buffers_1_reg[2]/C clock pessimism -0.192 -0.529 SLICE_X8Y59 FDCE (Remov_fdce_C_CLR) -0.067 -0.596 u_Axi_CDC/wFifo/popToPushGray_buffercc/buffers_1_reg[2] ------------------------------------------------------------------- required time 0.596 arrival time 0.150 ------------------------------------------------------------------- slack 0.746 Slack (MET) : 0.746ns (arrival time - required time) Source: pll_clk.u_rst_cpu/delay_reg[1]/C (rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Destination: u_Axi_CDC/wFifo/popToPushGray_buffercc/buffers_1_reg[3]/CLR (removal check against rising-edge clock cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) Data Path Delay: 0.694ns (logic 0.209ns (30.099%) route 0.485ns (69.901%)) Logic Levels: 1 (LUT1=1) Clock Path Skew: 0.015ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.337ns Source Clock Delay (SCD): -0.544ns Clock Pessimism Removal (CPR): 0.192ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 0.718 -0.544 pll_clk.u_rst_cpu/cpu_clk SLICE_X6Y63 FDCE r pll_clk.u_rst_cpu/delay_reg[1]/C ------------------------------------------------------------------- ------------------- SLICE_X6Y63 FDCE (Prop_fdce_C_Q) 0.164 -0.380 r pll_clk.u_rst_cpu/delay_reg[1]/Q net (fo=1, routed) 0.221 -0.159 pll_clk.u_rst_cpu/cpu_resetn SLICE_X6Y63 LUT1 (Prop_lut1_I0_O) 0.045 -0.114 f pll_clk.u_rst_cpu/reset_i_1/O net (fo=40, routed) 0.264 0.150 u_Axi_CDC/wFifo/popToPushGray_buffercc/p_0_in SLICE_X8Y59 FDCE f u_Axi_CDC/wFifo/popToPushGray_buffercc/buffers_1_reg[3]/CLR ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 0.971 -0.337 u_Axi_CDC/wFifo/popToPushGray_buffercc/cpu_clk SLICE_X8Y59 FDCE r u_Axi_CDC/wFifo/popToPushGray_buffercc/buffers_1_reg[3]/C clock pessimism -0.192 -0.529 SLICE_X8Y59 FDCE (Remov_fdce_C_CLR) -0.067 -0.596 u_Axi_CDC/wFifo/popToPushGray_buffercc/buffers_1_reg[3] ------------------------------------------------------------------- required time 0.596 arrival time 0.150 ------------------------------------------------------------------- slack 0.746 Slack (MET) : 0.771ns (arrival time - required time) Source: pll_clk.u_rst_cpu/delay_reg[1]/C (rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Destination: u_Axi_CDC/wFifo/popToPushGray_buffercc/buffers_0_reg[0]/CLR (removal check against rising-edge clock cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) Data Path Delay: 0.694ns (logic 0.209ns (30.099%) route 0.485ns (69.901%)) Logic Levels: 1 (LUT1=1) Clock Path Skew: 0.015ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.337ns Source Clock Delay (SCD): -0.544ns Clock Pessimism Removal (CPR): 0.192ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 0.718 -0.544 pll_clk.u_rst_cpu/cpu_clk SLICE_X6Y63 FDCE r pll_clk.u_rst_cpu/delay_reg[1]/C ------------------------------------------------------------------- ------------------- SLICE_X6Y63 FDCE (Prop_fdce_C_Q) 0.164 -0.380 r pll_clk.u_rst_cpu/delay_reg[1]/Q net (fo=1, routed) 0.221 -0.159 pll_clk.u_rst_cpu/cpu_resetn SLICE_X6Y63 LUT1 (Prop_lut1_I0_O) 0.045 -0.114 f pll_clk.u_rst_cpu/reset_i_1/O net (fo=40, routed) 0.264 0.150 u_Axi_CDC/wFifo/popToPushGray_buffercc/p_0_in SLICE_X9Y59 FDCE f u_Axi_CDC/wFifo/popToPushGray_buffercc/buffers_0_reg[0]/CLR ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 0.971 -0.337 u_Axi_CDC/wFifo/popToPushGray_buffercc/cpu_clk SLICE_X9Y59 FDCE r u_Axi_CDC/wFifo/popToPushGray_buffercc/buffers_0_reg[0]/C clock pessimism -0.192 -0.529 SLICE_X9Y59 FDCE (Remov_fdce_C_CLR) -0.092 -0.621 u_Axi_CDC/wFifo/popToPushGray_buffercc/buffers_0_reg[0] ------------------------------------------------------------------- required time 0.621 arrival time 0.150 ------------------------------------------------------------------- slack 0.771 Slack (MET) : 0.771ns (arrival time - required time) Source: pll_clk.u_rst_cpu/delay_reg[1]/C (rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Destination: u_Axi_CDC/wFifo/popToPushGray_buffercc/buffers_1_reg[0]/CLR (removal check against rising-edge clock cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) Data Path Delay: 0.694ns (logic 0.209ns (30.099%) route 0.485ns (69.901%)) Logic Levels: 1 (LUT1=1) Clock Path Skew: 0.015ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.337ns Source Clock Delay (SCD): -0.544ns Clock Pessimism Removal (CPR): 0.192ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 0.718 -0.544 pll_clk.u_rst_cpu/cpu_clk SLICE_X6Y63 FDCE r pll_clk.u_rst_cpu/delay_reg[1]/C ------------------------------------------------------------------- ------------------- SLICE_X6Y63 FDCE (Prop_fdce_C_Q) 0.164 -0.380 r pll_clk.u_rst_cpu/delay_reg[1]/Q net (fo=1, routed) 0.221 -0.159 pll_clk.u_rst_cpu/cpu_resetn SLICE_X6Y63 LUT1 (Prop_lut1_I0_O) 0.045 -0.114 f pll_clk.u_rst_cpu/reset_i_1/O net (fo=40, routed) 0.264 0.150 u_Axi_CDC/wFifo/popToPushGray_buffercc/p_0_in SLICE_X9Y59 FDCE f u_Axi_CDC/wFifo/popToPushGray_buffercc/buffers_1_reg[0]/CLR ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 0.971 -0.337 u_Axi_CDC/wFifo/popToPushGray_buffercc/cpu_clk SLICE_X9Y59 FDCE r u_Axi_CDC/wFifo/popToPushGray_buffercc/buffers_1_reg[0]/C clock pessimism -0.192 -0.529 SLICE_X9Y59 FDCE (Remov_fdce_C_CLR) -0.092 -0.621 u_Axi_CDC/wFifo/popToPushGray_buffercc/buffers_1_reg[0] ------------------------------------------------------------------- required time 0.621 arrival time 0.150 ------------------------------------------------------------------- slack 0.771 Slack (MET) : 0.805ns (arrival time - required time) Source: u_Axi_CDC/bFifo/bufferCC_12/buffers_1_reg/C (rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Destination: u_Axi_CDC/bFifo/pushToPopGray_buffercc/buffers_0_reg[0]/CLR (removal check against rising-edge clock cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) Data Path Delay: 0.724ns (logic 0.246ns (33.995%) route 0.478ns (66.005%)) Logic Levels: 1 (LUT1=1) Clock Path Skew: 0.011ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.341ns Source Clock Delay (SCD): -0.544ns Clock Pessimism Removal (CPR): 0.192ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 0.718 -0.544 u_Axi_CDC/bFifo/bufferCC_12/cpu_clk SLICE_X6Y63 FDCE r u_Axi_CDC/bFifo/bufferCC_12/buffers_1_reg/C ------------------------------------------------------------------- ------------------- SLICE_X6Y63 FDCE (Prop_fdce_C_Q) 0.148 -0.396 r u_Axi_CDC/bFifo/bufferCC_12/buffers_1_reg/Q net (fo=1, routed) 0.125 -0.271 u_Axi_CDC/bFifo/bufferCC_12/buffers_1 SLICE_X6Y63 LUT1 (Prop_lut1_I0_O) 0.098 -0.173 f u_Axi_CDC/bFifo/bufferCC_12/popCC_popPtr[2]_i_2__0/O net (fo=30, routed) 0.352 0.179 u_Axi_CDC/bFifo/pushToPopGray_buffercc/buffers_0_reg[2]_1 SLICE_X15Y62 FDCE f u_Axi_CDC/bFifo/pushToPopGray_buffercc/buffers_0_reg[0]/CLR ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 0.967 -0.341 u_Axi_CDC/bFifo/pushToPopGray_buffercc/cpu_clk SLICE_X15Y62 FDCE r u_Axi_CDC/bFifo/pushToPopGray_buffercc/buffers_0_reg[0]/C clock pessimism -0.192 -0.533 SLICE_X15Y62 FDCE (Remov_fdce_C_CLR) -0.092 -0.625 u_Axi_CDC/bFifo/pushToPopGray_buffercc/buffers_0_reg[0] ------------------------------------------------------------------- required time 0.625 arrival time 0.179 ------------------------------------------------------------------- slack 0.805 Slack (MET) : 0.805ns (arrival time - required time) Source: u_Axi_CDC/bFifo/bufferCC_12/buffers_1_reg/C (rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Destination: u_Axi_CDC/bFifo/pushToPopGray_buffercc/buffers_0_reg[1]/CLR (removal check against rising-edge clock cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) Data Path Delay: 0.724ns (logic 0.246ns (33.995%) route 0.478ns (66.005%)) Logic Levels: 1 (LUT1=1) Clock Path Skew: 0.011ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.341ns Source Clock Delay (SCD): -0.544ns Clock Pessimism Removal (CPR): 0.192ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 0.718 -0.544 u_Axi_CDC/bFifo/bufferCC_12/cpu_clk SLICE_X6Y63 FDCE r u_Axi_CDC/bFifo/bufferCC_12/buffers_1_reg/C ------------------------------------------------------------------- ------------------- SLICE_X6Y63 FDCE (Prop_fdce_C_Q) 0.148 -0.396 r u_Axi_CDC/bFifo/bufferCC_12/buffers_1_reg/Q net (fo=1, routed) 0.125 -0.271 u_Axi_CDC/bFifo/bufferCC_12/buffers_1 SLICE_X6Y63 LUT1 (Prop_lut1_I0_O) 0.098 -0.173 f u_Axi_CDC/bFifo/bufferCC_12/popCC_popPtr[2]_i_2__0/O net (fo=30, routed) 0.352 0.179 u_Axi_CDC/bFifo/pushToPopGray_buffercc/buffers_0_reg[2]_1 SLICE_X15Y62 FDCE f u_Axi_CDC/bFifo/pushToPopGray_buffercc/buffers_0_reg[1]/CLR ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 0.967 -0.341 u_Axi_CDC/bFifo/pushToPopGray_buffercc/cpu_clk SLICE_X15Y62 FDCE r u_Axi_CDC/bFifo/pushToPopGray_buffercc/buffers_0_reg[1]/C clock pessimism -0.192 -0.533 SLICE_X15Y62 FDCE (Remov_fdce_C_CLR) -0.092 -0.625 u_Axi_CDC/bFifo/pushToPopGray_buffercc/buffers_0_reg[1] ------------------------------------------------------------------- required time 0.625 arrival time 0.179 ------------------------------------------------------------------- slack 0.805 Slack (MET) : 0.805ns (arrival time - required time) Source: u_Axi_CDC/bFifo/bufferCC_12/buffers_1_reg/C (rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Destination: u_Axi_CDC/bFifo/pushToPopGray_buffercc/buffers_0_reg[2]/CLR (removal check against rising-edge clock cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) Data Path Delay: 0.724ns (logic 0.246ns (33.995%) route 0.478ns (66.005%)) Logic Levels: 1 (LUT1=1) Clock Path Skew: 0.011ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.341ns Source Clock Delay (SCD): -0.544ns Clock Pessimism Removal (CPR): 0.192ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 0.718 -0.544 u_Axi_CDC/bFifo/bufferCC_12/cpu_clk SLICE_X6Y63 FDCE r u_Axi_CDC/bFifo/bufferCC_12/buffers_1_reg/C ------------------------------------------------------------------- ------------------- SLICE_X6Y63 FDCE (Prop_fdce_C_Q) 0.148 -0.396 r u_Axi_CDC/bFifo/bufferCC_12/buffers_1_reg/Q net (fo=1, routed) 0.125 -0.271 u_Axi_CDC/bFifo/bufferCC_12/buffers_1 SLICE_X6Y63 LUT1 (Prop_lut1_I0_O) 0.098 -0.173 f u_Axi_CDC/bFifo/bufferCC_12/popCC_popPtr[2]_i_2__0/O net (fo=30, routed) 0.352 0.179 u_Axi_CDC/bFifo/pushToPopGray_buffercc/buffers_0_reg[2]_1 SLICE_X15Y62 FDCE f u_Axi_CDC/bFifo/pushToPopGray_buffercc/buffers_0_reg[2]/CLR ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 0.967 -0.341 u_Axi_CDC/bFifo/pushToPopGray_buffercc/cpu_clk SLICE_X15Y62 FDCE r u_Axi_CDC/bFifo/pushToPopGray_buffercc/buffers_0_reg[2]/C clock pessimism -0.192 -0.533 SLICE_X15Y62 FDCE (Remov_fdce_C_CLR) -0.092 -0.625 u_Axi_CDC/bFifo/pushToPopGray_buffercc/buffers_0_reg[2] ------------------------------------------------------------------- required time 0.625 arrival time 0.179 ------------------------------------------------------------------- slack 0.805 Slack (MET) : 0.805ns (arrival time - required time) Source: u_Axi_CDC/bFifo/bufferCC_12/buffers_1_reg/C (rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Destination: u_Axi_CDC/bFifo/pushToPopGray_buffercc/buffers_1_reg[0]/CLR (removal check against rising-edge clock cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) Data Path Delay: 0.724ns (logic 0.246ns (33.995%) route 0.478ns (66.005%)) Logic Levels: 1 (LUT1=1) Clock Path Skew: 0.011ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.341ns Source Clock Delay (SCD): -0.544ns Clock Pessimism Removal (CPR): 0.192ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 0.718 -0.544 u_Axi_CDC/bFifo/bufferCC_12/cpu_clk SLICE_X6Y63 FDCE r u_Axi_CDC/bFifo/bufferCC_12/buffers_1_reg/C ------------------------------------------------------------------- ------------------- SLICE_X6Y63 FDCE (Prop_fdce_C_Q) 0.148 -0.396 r u_Axi_CDC/bFifo/bufferCC_12/buffers_1_reg/Q net (fo=1, routed) 0.125 -0.271 u_Axi_CDC/bFifo/bufferCC_12/buffers_1 SLICE_X6Y63 LUT1 (Prop_lut1_I0_O) 0.098 -0.173 f u_Axi_CDC/bFifo/bufferCC_12/popCC_popPtr[2]_i_2__0/O net (fo=30, routed) 0.352 0.179 u_Axi_CDC/bFifo/pushToPopGray_buffercc/buffers_0_reg[2]_1 SLICE_X15Y62 FDCE f u_Axi_CDC/bFifo/pushToPopGray_buffercc/buffers_1_reg[0]/CLR ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 0.967 -0.341 u_Axi_CDC/bFifo/pushToPopGray_buffercc/cpu_clk SLICE_X15Y62 FDCE r u_Axi_CDC/bFifo/pushToPopGray_buffercc/buffers_1_reg[0]/C clock pessimism -0.192 -0.533 SLICE_X15Y62 FDCE (Remov_fdce_C_CLR) -0.092 -0.625 u_Axi_CDC/bFifo/pushToPopGray_buffercc/buffers_1_reg[0] ------------------------------------------------------------------- required time 0.625 arrival time 0.179 ------------------------------------------------------------------- slack 0.805 Slack (MET) : 0.805ns (arrival time - required time) Source: u_Axi_CDC/bFifo/bufferCC_12/buffers_1_reg/C (rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Destination: u_Axi_CDC/bFifo/pushToPopGray_buffercc/buffers_1_reg[1]/CLR (removal check against rising-edge clock cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) Data Path Delay: 0.724ns (logic 0.246ns (33.995%) route 0.478ns (66.005%)) Logic Levels: 1 (LUT1=1) Clock Path Skew: 0.011ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.341ns Source Clock Delay (SCD): -0.544ns Clock Pessimism Removal (CPR): 0.192ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 0.718 -0.544 u_Axi_CDC/bFifo/bufferCC_12/cpu_clk SLICE_X6Y63 FDCE r u_Axi_CDC/bFifo/bufferCC_12/buffers_1_reg/C ------------------------------------------------------------------- ------------------- SLICE_X6Y63 FDCE (Prop_fdce_C_Q) 0.148 -0.396 r u_Axi_CDC/bFifo/bufferCC_12/buffers_1_reg/Q net (fo=1, routed) 0.125 -0.271 u_Axi_CDC/bFifo/bufferCC_12/buffers_1 SLICE_X6Y63 LUT1 (Prop_lut1_I0_O) 0.098 -0.173 f u_Axi_CDC/bFifo/bufferCC_12/popCC_popPtr[2]_i_2__0/O net (fo=30, routed) 0.352 0.179 u_Axi_CDC/bFifo/pushToPopGray_buffercc/buffers_0_reg[2]_1 SLICE_X15Y62 FDCE f u_Axi_CDC/bFifo/pushToPopGray_buffercc/buffers_1_reg[1]/CLR ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 0.967 -0.341 u_Axi_CDC/bFifo/pushToPopGray_buffercc/cpu_clk SLICE_X15Y62 FDCE r u_Axi_CDC/bFifo/pushToPopGray_buffercc/buffers_1_reg[1]/C clock pessimism -0.192 -0.533 SLICE_X15Y62 FDCE (Remov_fdce_C_CLR) -0.092 -0.625 u_Axi_CDC/bFifo/pushToPopGray_buffercc/buffers_1_reg[1] ------------------------------------------------------------------- required time 0.625 arrival time 0.179 ------------------------------------------------------------------- slack 0.805 Slack (MET) : 0.805ns (arrival time - required time) Source: u_Axi_CDC/bFifo/bufferCC_12/buffers_1_reg/C (rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Destination: u_Axi_CDC/bFifo/pushToPopGray_buffercc/buffers_1_reg[2]/CLR (removal check against rising-edge clock cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) Data Path Delay: 0.724ns (logic 0.246ns (33.995%) route 0.478ns (66.005%)) Logic Levels: 1 (LUT1=1) Clock Path Skew: 0.011ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.341ns Source Clock Delay (SCD): -0.544ns Clock Pessimism Removal (CPR): 0.192ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 0.718 -0.544 u_Axi_CDC/bFifo/bufferCC_12/cpu_clk SLICE_X6Y63 FDCE r u_Axi_CDC/bFifo/bufferCC_12/buffers_1_reg/C ------------------------------------------------------------------- ------------------- SLICE_X6Y63 FDCE (Prop_fdce_C_Q) 0.148 -0.396 r u_Axi_CDC/bFifo/bufferCC_12/buffers_1_reg/Q net (fo=1, routed) 0.125 -0.271 u_Axi_CDC/bFifo/bufferCC_12/buffers_1 SLICE_X6Y63 LUT1 (Prop_lut1_I0_O) 0.098 -0.173 f u_Axi_CDC/bFifo/bufferCC_12/popCC_popPtr[2]_i_2__0/O net (fo=30, routed) 0.352 0.179 u_Axi_CDC/bFifo/pushToPopGray_buffercc/buffers_0_reg[2]_1 SLICE_X15Y62 FDCE f u_Axi_CDC/bFifo/pushToPopGray_buffercc/buffers_1_reg[2]/CLR ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 0.967 -0.341 u_Axi_CDC/bFifo/pushToPopGray_buffercc/cpu_clk SLICE_X15Y62 FDCE r u_Axi_CDC/bFifo/pushToPopGray_buffercc/buffers_1_reg[2]/C clock pessimism -0.192 -0.533 SLICE_X15Y62 FDCE (Remov_fdce_C_CLR) -0.092 -0.625 u_Axi_CDC/bFifo/pushToPopGray_buffercc/buffers_1_reg[2] ------------------------------------------------------------------- required time 0.625 arrival time 0.179 ------------------------------------------------------------------- slack 0.805 Slack (MET) : 0.898ns (arrival time - required time) Source: u_Axi_CDC/bFifo/bufferCC_12/buffers_1_reg/C (rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Destination: u_Axi_CDC/bFifo/popCC_addressGen_rValid_reg/CLR (removal check against rising-edge clock cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) Data Path Delay: 0.844ns (logic 0.246ns (29.164%) route 0.598ns (70.836%)) Logic Levels: 1 (LUT1=1) Clock Path Skew: 0.013ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.339ns Source Clock Delay (SCD): -0.544ns Clock Pessimism Removal (CPR): 0.192ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 0.718 -0.544 u_Axi_CDC/bFifo/bufferCC_12/cpu_clk SLICE_X6Y63 FDCE r u_Axi_CDC/bFifo/bufferCC_12/buffers_1_reg/C ------------------------------------------------------------------- ------------------- SLICE_X6Y63 FDCE (Prop_fdce_C_Q) 0.148 -0.396 r u_Axi_CDC/bFifo/bufferCC_12/buffers_1_reg/Q net (fo=1, routed) 0.125 -0.271 u_Axi_CDC/bFifo/bufferCC_12/buffers_1 SLICE_X6Y63 LUT1 (Prop_lut1_I0_O) 0.098 -0.173 f u_Axi_CDC/bFifo/bufferCC_12/popCC_popPtr[2]_i_2__0/O net (fo=30, routed) 0.472 0.299 u_Axi_CDC/bFifo/buffers_1_reg SLICE_X14Y61 FDCE f u_Axi_CDC/bFifo/popCC_addressGen_rValid_reg/CLR ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 0.969 -0.339 u_Axi_CDC/bFifo/cpu_clk SLICE_X14Y61 FDCE r u_Axi_CDC/bFifo/popCC_addressGen_rValid_reg/C clock pessimism -0.192 -0.531 SLICE_X14Y61 FDCE (Remov_fdce_C_CLR) -0.067 -0.598 u_Axi_CDC/bFifo/popCC_addressGen_rValid_reg ------------------------------------------------------------------- required time 0.598 arrival time 0.299 ------------------------------------------------------------------- slack 0.898 Slack (MET) : 0.898ns (arrival time - required time) Source: u_Axi_CDC/bFifo/bufferCC_12/buffers_1_reg/C (rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Destination: u_Axi_CDC/bFifo/popCC_popPtr_reg[1]/CLR (removal check against rising-edge clock cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) Data Path Delay: 0.844ns (logic 0.246ns (29.164%) route 0.598ns (70.836%)) Logic Levels: 1 (LUT1=1) Clock Path Skew: 0.013ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.339ns Source Clock Delay (SCD): -0.544ns Clock Pessimism Removal (CPR): 0.192ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 0.718 -0.544 u_Axi_CDC/bFifo/bufferCC_12/cpu_clk SLICE_X6Y63 FDCE r u_Axi_CDC/bFifo/bufferCC_12/buffers_1_reg/C ------------------------------------------------------------------- ------------------- SLICE_X6Y63 FDCE (Prop_fdce_C_Q) 0.148 -0.396 r u_Axi_CDC/bFifo/bufferCC_12/buffers_1_reg/Q net (fo=1, routed) 0.125 -0.271 u_Axi_CDC/bFifo/bufferCC_12/buffers_1 SLICE_X6Y63 LUT1 (Prop_lut1_I0_O) 0.098 -0.173 f u_Axi_CDC/bFifo/bufferCC_12/popCC_popPtr[2]_i_2__0/O net (fo=30, routed) 0.472 0.299 u_Axi_CDC/bFifo/buffers_1_reg SLICE_X14Y61 FDCE f u_Axi_CDC/bFifo/popCC_popPtr_reg[1]/CLR ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 0.969 -0.339 u_Axi_CDC/bFifo/cpu_clk SLICE_X14Y61 FDCE r u_Axi_CDC/bFifo/popCC_popPtr_reg[1]/C clock pessimism -0.192 -0.531 SLICE_X14Y61 FDCE (Remov_fdce_C_CLR) -0.067 -0.598 u_Axi_CDC/bFifo/popCC_popPtr_reg[1] ------------------------------------------------------------------- required time 0.598 arrival time 0.299 ------------------------------------------------------------------- slack 0.898 Slack (MET) : 0.898ns (arrival time - required time) Source: u_Axi_CDC/bFifo/bufferCC_12/buffers_1_reg/C (rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Destination: u_Axi_CDC/bFifo/popCC_popPtr_reg[2]/CLR (removal check against rising-edge clock cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) Data Path Delay: 0.844ns (logic 0.246ns (29.164%) route 0.598ns (70.836%)) Logic Levels: 1 (LUT1=1) Clock Path Skew: 0.013ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.339ns Source Clock Delay (SCD): -0.544ns Clock Pessimism Removal (CPR): 0.192ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 0.718 -0.544 u_Axi_CDC/bFifo/bufferCC_12/cpu_clk SLICE_X6Y63 FDCE r u_Axi_CDC/bFifo/bufferCC_12/buffers_1_reg/C ------------------------------------------------------------------- ------------------- SLICE_X6Y63 FDCE (Prop_fdce_C_Q) 0.148 -0.396 r u_Axi_CDC/bFifo/bufferCC_12/buffers_1_reg/Q net (fo=1, routed) 0.125 -0.271 u_Axi_CDC/bFifo/bufferCC_12/buffers_1 SLICE_X6Y63 LUT1 (Prop_lut1_I0_O) 0.098 -0.173 f u_Axi_CDC/bFifo/bufferCC_12/popCC_popPtr[2]_i_2__0/O net (fo=30, routed) 0.472 0.299 u_Axi_CDC/bFifo/buffers_1_reg SLICE_X14Y61 FDCE f u_Axi_CDC/bFifo/popCC_popPtr_reg[2]/CLR ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 0.969 -0.339 u_Axi_CDC/bFifo/cpu_clk SLICE_X14Y61 FDCE r u_Axi_CDC/bFifo/popCC_popPtr_reg[2]/C clock pessimism -0.192 -0.531 SLICE_X14Y61 FDCE (Remov_fdce_C_CLR) -0.067 -0.598 u_Axi_CDC/bFifo/popCC_popPtr_reg[2] ------------------------------------------------------------------- required time 0.598 arrival time 0.299 ------------------------------------------------------------------- slack 0.898 Slack (MET) : 0.898ns (arrival time - required time) Source: u_Axi_CDC/bFifo/bufferCC_12/buffers_1_reg/C (rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Destination: u_Axi_CDC/bFifo/popCC_ptrToPush_reg[2]/CLR (removal check against rising-edge clock cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) Data Path Delay: 0.844ns (logic 0.246ns (29.164%) route 0.598ns (70.836%)) Logic Levels: 1 (LUT1=1) Clock Path Skew: 0.013ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.339ns Source Clock Delay (SCD): -0.544ns Clock Pessimism Removal (CPR): 0.192ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 0.718 -0.544 u_Axi_CDC/bFifo/bufferCC_12/cpu_clk SLICE_X6Y63 FDCE r u_Axi_CDC/bFifo/bufferCC_12/buffers_1_reg/C ------------------------------------------------------------------- ------------------- SLICE_X6Y63 FDCE (Prop_fdce_C_Q) 0.148 -0.396 r u_Axi_CDC/bFifo/bufferCC_12/buffers_1_reg/Q net (fo=1, routed) 0.125 -0.271 u_Axi_CDC/bFifo/bufferCC_12/buffers_1 SLICE_X6Y63 LUT1 (Prop_lut1_I0_O) 0.098 -0.173 f u_Axi_CDC/bFifo/bufferCC_12/popCC_popPtr[2]_i_2__0/O net (fo=30, routed) 0.472 0.299 u_Axi_CDC/bFifo/buffers_1_reg SLICE_X14Y61 FDCE f u_Axi_CDC/bFifo/popCC_ptrToPush_reg[2]/CLR ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 0.969 -0.339 u_Axi_CDC/bFifo/cpu_clk SLICE_X14Y61 FDCE r u_Axi_CDC/bFifo/popCC_ptrToPush_reg[2]/C clock pessimism -0.192 -0.531 SLICE_X14Y61 FDCE (Remov_fdce_C_CLR) -0.067 -0.598 u_Axi_CDC/bFifo/popCC_ptrToPush_reg[2] ------------------------------------------------------------------- required time 0.598 arrival time 0.299 ------------------------------------------------------------------- slack 0.898 Slack (MET) : 0.923ns (arrival time - required time) Source: u_Axi_CDC/bFifo/bufferCC_12/buffers_1_reg/C (rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Destination: u_Axi_CDC/bFifo/popCC_popPtr_reg[0]/CLR (removal check against rising-edge clock cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) Data Path Delay: 0.844ns (logic 0.246ns (29.164%) route 0.598ns (70.836%)) Logic Levels: 1 (LUT1=1) Clock Path Skew: 0.013ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.339ns Source Clock Delay (SCD): -0.544ns Clock Pessimism Removal (CPR): 0.192ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 0.718 -0.544 u_Axi_CDC/bFifo/bufferCC_12/cpu_clk SLICE_X6Y63 FDCE r u_Axi_CDC/bFifo/bufferCC_12/buffers_1_reg/C ------------------------------------------------------------------- ------------------- SLICE_X6Y63 FDCE (Prop_fdce_C_Q) 0.148 -0.396 r u_Axi_CDC/bFifo/bufferCC_12/buffers_1_reg/Q net (fo=1, routed) 0.125 -0.271 u_Axi_CDC/bFifo/bufferCC_12/buffers_1 SLICE_X6Y63 LUT1 (Prop_lut1_I0_O) 0.098 -0.173 f u_Axi_CDC/bFifo/bufferCC_12/popCC_popPtr[2]_i_2__0/O net (fo=30, routed) 0.472 0.299 u_Axi_CDC/bFifo/buffers_1_reg SLICE_X15Y61 FDCE f u_Axi_CDC/bFifo/popCC_popPtr_reg[0]/CLR ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 0.969 -0.339 u_Axi_CDC/bFifo/cpu_clk SLICE_X15Y61 FDCE r u_Axi_CDC/bFifo/popCC_popPtr_reg[0]/C clock pessimism -0.192 -0.531 SLICE_X15Y61 FDCE (Remov_fdce_C_CLR) -0.092 -0.623 u_Axi_CDC/bFifo/popCC_popPtr_reg[0] ------------------------------------------------------------------- required time 0.623 arrival time 0.299 ------------------------------------------------------------------- slack 0.923 Slack (MET) : 0.923ns (arrival time - required time) Source: u_Axi_CDC/bFifo/bufferCC_12/buffers_1_reg/C (rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Destination: u_Axi_CDC/bFifo/popCC_ptrToPush_reg[0]/CLR (removal check against rising-edge clock cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) Data Path Delay: 0.844ns (logic 0.246ns (29.164%) route 0.598ns (70.836%)) Logic Levels: 1 (LUT1=1) Clock Path Skew: 0.013ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.339ns Source Clock Delay (SCD): -0.544ns Clock Pessimism Removal (CPR): 0.192ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 0.718 -0.544 u_Axi_CDC/bFifo/bufferCC_12/cpu_clk SLICE_X6Y63 FDCE r u_Axi_CDC/bFifo/bufferCC_12/buffers_1_reg/C ------------------------------------------------------------------- ------------------- SLICE_X6Y63 FDCE (Prop_fdce_C_Q) 0.148 -0.396 r u_Axi_CDC/bFifo/bufferCC_12/buffers_1_reg/Q net (fo=1, routed) 0.125 -0.271 u_Axi_CDC/bFifo/bufferCC_12/buffers_1 SLICE_X6Y63 LUT1 (Prop_lut1_I0_O) 0.098 -0.173 f u_Axi_CDC/bFifo/bufferCC_12/popCC_popPtr[2]_i_2__0/O net (fo=30, routed) 0.472 0.299 u_Axi_CDC/bFifo/buffers_1_reg SLICE_X15Y61 FDCE f u_Axi_CDC/bFifo/popCC_ptrToPush_reg[0]/CLR ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 0.969 -0.339 u_Axi_CDC/bFifo/cpu_clk SLICE_X15Y61 FDCE r u_Axi_CDC/bFifo/popCC_ptrToPush_reg[0]/C clock pessimism -0.192 -0.531 SLICE_X15Y61 FDCE (Remov_fdce_C_CLR) -0.092 -0.623 u_Axi_CDC/bFifo/popCC_ptrToPush_reg[0] ------------------------------------------------------------------- required time 0.623 arrival time 0.299 ------------------------------------------------------------------- slack 0.923 Slack (MET) : 0.923ns (arrival time - required time) Source: u_Axi_CDC/bFifo/bufferCC_12/buffers_1_reg/C (rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Destination: u_Axi_CDC/bFifo/popCC_ptrToPush_reg[1]/CLR (removal check against rising-edge clock cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) Data Path Delay: 0.844ns (logic 0.246ns (29.164%) route 0.598ns (70.836%)) Logic Levels: 1 (LUT1=1) Clock Path Skew: 0.013ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.339ns Source Clock Delay (SCD): -0.544ns Clock Pessimism Removal (CPR): 0.192ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 0.718 -0.544 u_Axi_CDC/bFifo/bufferCC_12/cpu_clk SLICE_X6Y63 FDCE r u_Axi_CDC/bFifo/bufferCC_12/buffers_1_reg/C ------------------------------------------------------------------- ------------------- SLICE_X6Y63 FDCE (Prop_fdce_C_Q) 0.148 -0.396 r u_Axi_CDC/bFifo/bufferCC_12/buffers_1_reg/Q net (fo=1, routed) 0.125 -0.271 u_Axi_CDC/bFifo/bufferCC_12/buffers_1 SLICE_X6Y63 LUT1 (Prop_lut1_I0_O) 0.098 -0.173 f u_Axi_CDC/bFifo/bufferCC_12/popCC_popPtr[2]_i_2__0/O net (fo=30, routed) 0.472 0.299 u_Axi_CDC/bFifo/buffers_1_reg SLICE_X15Y61 FDCE f u_Axi_CDC/bFifo/popCC_ptrToPush_reg[1]/CLR ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 0.969 -0.339 u_Axi_CDC/bFifo/cpu_clk SLICE_X15Y61 FDCE r u_Axi_CDC/bFifo/popCC_ptrToPush_reg[1]/C clock pessimism -0.192 -0.531 SLICE_X15Y61 FDCE (Remov_fdce_C_CLR) -0.092 -0.623 u_Axi_CDC/bFifo/popCC_ptrToPush_reg[1] ------------------------------------------------------------------- required time 0.623 arrival time 0.299 ------------------------------------------------------------------- slack 0.923 Slack (MET) : 0.935ns (arrival time - required time) Source: u_Axi_CDC/bFifo/bufferCC_12/buffers_1_reg/C (rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Destination: u_Axi_CDC/rFifo/popCC_ptrToPush_reg[0]/CLR (removal check against rising-edge clock cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) Data Path Delay: 0.853ns (logic 0.246ns (28.849%) route 0.607ns (71.151%)) Logic Levels: 1 (LUT1=1) Clock Path Skew: 0.010ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.342ns Source Clock Delay (SCD): -0.544ns Clock Pessimism Removal (CPR): 0.192ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 0.718 -0.544 u_Axi_CDC/bFifo/bufferCC_12/cpu_clk SLICE_X6Y63 FDCE r u_Axi_CDC/bFifo/bufferCC_12/buffers_1_reg/C ------------------------------------------------------------------- ------------------- SLICE_X6Y63 FDCE (Prop_fdce_C_Q) 0.148 -0.396 r u_Axi_CDC/bFifo/bufferCC_12/buffers_1_reg/Q net (fo=1, routed) 0.125 -0.271 u_Axi_CDC/bFifo/bufferCC_12/buffers_1 SLICE_X6Y63 LUT1 (Prop_lut1_I0_O) 0.098 -0.173 f u_Axi_CDC/bFifo/bufferCC_12/popCC_popPtr[2]_i_2__0/O net (fo=30, routed) 0.481 0.308 u_Axi_CDC/rFifo/buffers_0_reg[3] SLICE_X15Y64 FDCE f u_Axi_CDC/rFifo/popCC_ptrToPush_reg[0]/CLR ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 0.966 -0.342 u_Axi_CDC/rFifo/cpu_clk SLICE_X15Y64 FDCE r u_Axi_CDC/rFifo/popCC_ptrToPush_reg[0]/C clock pessimism -0.192 -0.534 SLICE_X15Y64 FDCE (Remov_fdce_C_CLR) -0.092 -0.626 u_Axi_CDC/rFifo/popCC_ptrToPush_reg[0] ------------------------------------------------------------------- required time 0.626 arrival time 0.308 ------------------------------------------------------------------- slack 0.935 Slack (MET) : 0.935ns (arrival time - required time) Source: u_Axi_CDC/bFifo/bufferCC_12/buffers_1_reg/C (rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Destination: u_Axi_CDC/rFifo/popCC_ptrToPush_reg[1]/CLR (removal check against rising-edge clock cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) Data Path Delay: 0.853ns (logic 0.246ns (28.849%) route 0.607ns (71.151%)) Logic Levels: 1 (LUT1=1) Clock Path Skew: 0.010ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.342ns Source Clock Delay (SCD): -0.544ns Clock Pessimism Removal (CPR): 0.192ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 0.718 -0.544 u_Axi_CDC/bFifo/bufferCC_12/cpu_clk SLICE_X6Y63 FDCE r u_Axi_CDC/bFifo/bufferCC_12/buffers_1_reg/C ------------------------------------------------------------------- ------------------- SLICE_X6Y63 FDCE (Prop_fdce_C_Q) 0.148 -0.396 r u_Axi_CDC/bFifo/bufferCC_12/buffers_1_reg/Q net (fo=1, routed) 0.125 -0.271 u_Axi_CDC/bFifo/bufferCC_12/buffers_1 SLICE_X6Y63 LUT1 (Prop_lut1_I0_O) 0.098 -0.173 f u_Axi_CDC/bFifo/bufferCC_12/popCC_popPtr[2]_i_2__0/O net (fo=30, routed) 0.481 0.308 u_Axi_CDC/rFifo/buffers_0_reg[3] SLICE_X15Y64 FDCE f u_Axi_CDC/rFifo/popCC_ptrToPush_reg[1]/CLR ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 0.966 -0.342 u_Axi_CDC/rFifo/cpu_clk SLICE_X15Y64 FDCE r u_Axi_CDC/rFifo/popCC_ptrToPush_reg[1]/C clock pessimism -0.192 -0.534 SLICE_X15Y64 FDCE (Remov_fdce_C_CLR) -0.092 -0.626 u_Axi_CDC/rFifo/popCC_ptrToPush_reg[1] ------------------------------------------------------------------- required time 0.626 arrival time 0.308 ------------------------------------------------------------------- slack 0.935 Slack (MET) : 0.935ns (arrival time - required time) Source: u_Axi_CDC/bFifo/bufferCC_12/buffers_1_reg/C (rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Destination: u_Axi_CDC/rFifo/popCC_ptrToPush_reg[2]/CLR (removal check against rising-edge clock cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) Data Path Delay: 0.853ns (logic 0.246ns (28.849%) route 0.607ns (71.151%)) Logic Levels: 1 (LUT1=1) Clock Path Skew: 0.010ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.342ns Source Clock Delay (SCD): -0.544ns Clock Pessimism Removal (CPR): 0.192ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 0.718 -0.544 u_Axi_CDC/bFifo/bufferCC_12/cpu_clk SLICE_X6Y63 FDCE r u_Axi_CDC/bFifo/bufferCC_12/buffers_1_reg/C ------------------------------------------------------------------- ------------------- SLICE_X6Y63 FDCE (Prop_fdce_C_Q) 0.148 -0.396 r u_Axi_CDC/bFifo/bufferCC_12/buffers_1_reg/Q net (fo=1, routed) 0.125 -0.271 u_Axi_CDC/bFifo/bufferCC_12/buffers_1 SLICE_X6Y63 LUT1 (Prop_lut1_I0_O) 0.098 -0.173 f u_Axi_CDC/bFifo/bufferCC_12/popCC_popPtr[2]_i_2__0/O net (fo=30, routed) 0.481 0.308 u_Axi_CDC/rFifo/buffers_0_reg[3] SLICE_X15Y64 FDCE f u_Axi_CDC/rFifo/popCC_ptrToPush_reg[2]/CLR ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 0.966 -0.342 u_Axi_CDC/rFifo/cpu_clk SLICE_X15Y64 FDCE r u_Axi_CDC/rFifo/popCC_ptrToPush_reg[2]/C clock pessimism -0.192 -0.534 SLICE_X15Y64 FDCE (Remov_fdce_C_CLR) -0.092 -0.626 u_Axi_CDC/rFifo/popCC_ptrToPush_reg[2] ------------------------------------------------------------------- required time 0.626 arrival time 0.308 ------------------------------------------------------------------- slack 0.935 Slack (MET) : 0.935ns (arrival time - required time) Source: u_Axi_CDC/bFifo/bufferCC_12/buffers_1_reg/C (rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Destination: u_Axi_CDC/rFifo/popCC_ptrToPush_reg[3]/CLR (removal check against rising-edge clock cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) Data Path Delay: 0.853ns (logic 0.246ns (28.849%) route 0.607ns (71.151%)) Logic Levels: 1 (LUT1=1) Clock Path Skew: 0.010ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.342ns Source Clock Delay (SCD): -0.544ns Clock Pessimism Removal (CPR): 0.192ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 0.718 -0.544 u_Axi_CDC/bFifo/bufferCC_12/cpu_clk SLICE_X6Y63 FDCE r u_Axi_CDC/bFifo/bufferCC_12/buffers_1_reg/C ------------------------------------------------------------------- ------------------- SLICE_X6Y63 FDCE (Prop_fdce_C_Q) 0.148 -0.396 r u_Axi_CDC/bFifo/bufferCC_12/buffers_1_reg/Q net (fo=1, routed) 0.125 -0.271 u_Axi_CDC/bFifo/bufferCC_12/buffers_1 SLICE_X6Y63 LUT1 (Prop_lut1_I0_O) 0.098 -0.173 f u_Axi_CDC/bFifo/bufferCC_12/popCC_popPtr[2]_i_2__0/O net (fo=30, routed) 0.481 0.308 u_Axi_CDC/rFifo/buffers_0_reg[3] SLICE_X15Y64 FDCE f u_Axi_CDC/rFifo/popCC_ptrToPush_reg[3]/CLR ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 0.966 -0.342 u_Axi_CDC/rFifo/cpu_clk SLICE_X15Y64 FDCE r u_Axi_CDC/rFifo/popCC_ptrToPush_reg[3]/C clock pessimism -0.192 -0.534 SLICE_X15Y64 FDCE (Remov_fdce_C_CLR) -0.092 -0.626 u_Axi_CDC/rFifo/popCC_ptrToPush_reg[3] ------------------------------------------------------------------- required time 0.626 arrival time 0.308 ------------------------------------------------------------------- slack 0.935 Slack (MET) : 0.964ns (arrival time - required time) Source: u_Axi_CDC/bFifo/bufferCC_12/buffers_1_reg/C (rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Destination: u_Axi_CDC/rFifo/pushToPopGray_buffercc/buffers_0_reg[0]/CLR (removal check against rising-edge clock cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) Data Path Delay: 0.906ns (logic 0.246ns (27.148%) route 0.660ns (72.852%)) Logic Levels: 1 (LUT1=1) Clock Path Skew: 0.009ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.343ns Source Clock Delay (SCD): -0.544ns Clock Pessimism Removal (CPR): 0.192ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 0.718 -0.544 u_Axi_CDC/bFifo/bufferCC_12/cpu_clk SLICE_X6Y63 FDCE r u_Axi_CDC/bFifo/bufferCC_12/buffers_1_reg/C ------------------------------------------------------------------- ------------------- SLICE_X6Y63 FDCE (Prop_fdce_C_Q) 0.148 -0.396 r u_Axi_CDC/bFifo/bufferCC_12/buffers_1_reg/Q net (fo=1, routed) 0.125 -0.271 u_Axi_CDC/bFifo/bufferCC_12/buffers_1 SLICE_X6Y63 LUT1 (Prop_lut1_I0_O) 0.098 -0.173 f u_Axi_CDC/bFifo/bufferCC_12/popCC_popPtr[2]_i_2__0/O net (fo=30, routed) 0.535 0.362 u_Axi_CDC/rFifo/pushToPopGray_buffercc/buffers_0_reg[3]_1 SLICE_X14Y65 FDCE f u_Axi_CDC/rFifo/pushToPopGray_buffercc/buffers_0_reg[0]/CLR ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 0.965 -0.343 u_Axi_CDC/rFifo/pushToPopGray_buffercc/cpu_clk SLICE_X14Y65 FDCE r u_Axi_CDC/rFifo/pushToPopGray_buffercc/buffers_0_reg[0]/C clock pessimism -0.192 -0.535 SLICE_X14Y65 FDCE (Remov_fdce_C_CLR) -0.067 -0.602 u_Axi_CDC/rFifo/pushToPopGray_buffercc/buffers_0_reg[0] ------------------------------------------------------------------- required time 0.602 arrival time 0.362 ------------------------------------------------------------------- slack 0.964 Slack (MET) : 0.964ns (arrival time - required time) Source: u_Axi_CDC/bFifo/bufferCC_12/buffers_1_reg/C (rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Destination: u_Axi_CDC/rFifo/pushToPopGray_buffercc/buffers_0_reg[3]/CLR (removal check against rising-edge clock cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) Data Path Delay: 0.906ns (logic 0.246ns (27.148%) route 0.660ns (72.852%)) Logic Levels: 1 (LUT1=1) Clock Path Skew: 0.009ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.343ns Source Clock Delay (SCD): -0.544ns Clock Pessimism Removal (CPR): 0.192ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 0.718 -0.544 u_Axi_CDC/bFifo/bufferCC_12/cpu_clk SLICE_X6Y63 FDCE r u_Axi_CDC/bFifo/bufferCC_12/buffers_1_reg/C ------------------------------------------------------------------- ------------------- SLICE_X6Y63 FDCE (Prop_fdce_C_Q) 0.148 -0.396 r u_Axi_CDC/bFifo/bufferCC_12/buffers_1_reg/Q net (fo=1, routed) 0.125 -0.271 u_Axi_CDC/bFifo/bufferCC_12/buffers_1 SLICE_X6Y63 LUT1 (Prop_lut1_I0_O) 0.098 -0.173 f u_Axi_CDC/bFifo/bufferCC_12/popCC_popPtr[2]_i_2__0/O net (fo=30, routed) 0.535 0.362 u_Axi_CDC/rFifo/pushToPopGray_buffercc/buffers_0_reg[3]_1 SLICE_X14Y65 FDCE f u_Axi_CDC/rFifo/pushToPopGray_buffercc/buffers_0_reg[3]/CLR ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 0.965 -0.343 u_Axi_CDC/rFifo/pushToPopGray_buffercc/cpu_clk SLICE_X14Y65 FDCE r u_Axi_CDC/rFifo/pushToPopGray_buffercc/buffers_0_reg[3]/C clock pessimism -0.192 -0.535 SLICE_X14Y65 FDCE (Remov_fdce_C_CLR) -0.067 -0.602 u_Axi_CDC/rFifo/pushToPopGray_buffercc/buffers_0_reg[3] ------------------------------------------------------------------- required time 0.602 arrival time 0.362 ------------------------------------------------------------------- slack 0.964 Slack (MET) : 0.964ns (arrival time - required time) Source: u_Axi_CDC/bFifo/bufferCC_12/buffers_1_reg/C (rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Destination: u_Axi_CDC/rFifo/pushToPopGray_buffercc/buffers_1_reg[0]/CLR (removal check against rising-edge clock cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) Data Path Delay: 0.906ns (logic 0.246ns (27.148%) route 0.660ns (72.852%)) Logic Levels: 1 (LUT1=1) Clock Path Skew: 0.009ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.343ns Source Clock Delay (SCD): -0.544ns Clock Pessimism Removal (CPR): 0.192ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 0.718 -0.544 u_Axi_CDC/bFifo/bufferCC_12/cpu_clk SLICE_X6Y63 FDCE r u_Axi_CDC/bFifo/bufferCC_12/buffers_1_reg/C ------------------------------------------------------------------- ------------------- SLICE_X6Y63 FDCE (Prop_fdce_C_Q) 0.148 -0.396 r u_Axi_CDC/bFifo/bufferCC_12/buffers_1_reg/Q net (fo=1, routed) 0.125 -0.271 u_Axi_CDC/bFifo/bufferCC_12/buffers_1 SLICE_X6Y63 LUT1 (Prop_lut1_I0_O) 0.098 -0.173 f u_Axi_CDC/bFifo/bufferCC_12/popCC_popPtr[2]_i_2__0/O net (fo=30, routed) 0.535 0.362 u_Axi_CDC/rFifo/pushToPopGray_buffercc/buffers_0_reg[3]_1 SLICE_X14Y65 FDCE f u_Axi_CDC/rFifo/pushToPopGray_buffercc/buffers_1_reg[0]/CLR ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 0.965 -0.343 u_Axi_CDC/rFifo/pushToPopGray_buffercc/cpu_clk SLICE_X14Y65 FDCE r u_Axi_CDC/rFifo/pushToPopGray_buffercc/buffers_1_reg[0]/C clock pessimism -0.192 -0.535 SLICE_X14Y65 FDCE (Remov_fdce_C_CLR) -0.067 -0.602 u_Axi_CDC/rFifo/pushToPopGray_buffercc/buffers_1_reg[0] ------------------------------------------------------------------- required time 0.602 arrival time 0.362 ------------------------------------------------------------------- slack 0.964 Slack (MET) : 0.964ns (arrival time - required time) Source: u_Axi_CDC/bFifo/bufferCC_12/buffers_1_reg/C (rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Destination: u_Axi_CDC/rFifo/pushToPopGray_buffercc/buffers_1_reg[3]/CLR (removal check against rising-edge clock cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) Data Path Delay: 0.906ns (logic 0.246ns (27.148%) route 0.660ns (72.852%)) Logic Levels: 1 (LUT1=1) Clock Path Skew: 0.009ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.343ns Source Clock Delay (SCD): -0.544ns Clock Pessimism Removal (CPR): 0.192ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 0.718 -0.544 u_Axi_CDC/bFifo/bufferCC_12/cpu_clk SLICE_X6Y63 FDCE r u_Axi_CDC/bFifo/bufferCC_12/buffers_1_reg/C ------------------------------------------------------------------- ------------------- SLICE_X6Y63 FDCE (Prop_fdce_C_Q) 0.148 -0.396 r u_Axi_CDC/bFifo/bufferCC_12/buffers_1_reg/Q net (fo=1, routed) 0.125 -0.271 u_Axi_CDC/bFifo/bufferCC_12/buffers_1 SLICE_X6Y63 LUT1 (Prop_lut1_I0_O) 0.098 -0.173 f u_Axi_CDC/bFifo/bufferCC_12/popCC_popPtr[2]_i_2__0/O net (fo=30, routed) 0.535 0.362 u_Axi_CDC/rFifo/pushToPopGray_buffercc/buffers_0_reg[3]_1 SLICE_X14Y65 FDCE f u_Axi_CDC/rFifo/pushToPopGray_buffercc/buffers_1_reg[3]/CLR ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 0.965 -0.343 u_Axi_CDC/rFifo/pushToPopGray_buffercc/cpu_clk SLICE_X14Y65 FDCE r u_Axi_CDC/rFifo/pushToPopGray_buffercc/buffers_1_reg[3]/C clock pessimism -0.192 -0.535 SLICE_X14Y65 FDCE (Remov_fdce_C_CLR) -0.067 -0.602 u_Axi_CDC/rFifo/pushToPopGray_buffercc/buffers_1_reg[3] ------------------------------------------------------------------- required time 0.602 arrival time 0.362 ------------------------------------------------------------------- slack 0.964 Slack (MET) : 0.972ns (arrival time - required time) Source: pll_clk.u_rst_cpu/delay_reg[1]/C (rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Destination: u_Axi_CDC/wFifo/pushCC_pushPtrGray_reg[0]/CLR (removal check against rising-edge clock cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) Data Path Delay: 0.920ns (logic 0.209ns (22.721%) route 0.711ns (77.279%)) Logic Levels: 1 (LUT1=1) Clock Path Skew: 0.015ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.337ns Source Clock Delay (SCD): -0.544ns Clock Pessimism Removal (CPR): 0.192ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 0.718 -0.544 pll_clk.u_rst_cpu/cpu_clk SLICE_X6Y63 FDCE r pll_clk.u_rst_cpu/delay_reg[1]/C ------------------------------------------------------------------- ------------------- SLICE_X6Y63 FDCE (Prop_fdce_C_Q) 0.164 -0.380 r pll_clk.u_rst_cpu/delay_reg[1]/Q net (fo=1, routed) 0.221 -0.159 pll_clk.u_rst_cpu/cpu_resetn SLICE_X6Y63 LUT1 (Prop_lut1_I0_O) 0.045 -0.114 f pll_clk.u_rst_cpu/reset_i_1/O net (fo=40, routed) 0.490 0.375 u_Axi_CDC/wFifo/p_0_in SLICE_X10Y58 FDCE f u_Axi_CDC/wFifo/pushCC_pushPtrGray_reg[0]/CLR ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 0.971 -0.337 u_Axi_CDC/wFifo/cpu_clk SLICE_X10Y58 FDCE r u_Axi_CDC/wFifo/pushCC_pushPtrGray_reg[0]/C clock pessimism -0.192 -0.529 SLICE_X10Y58 FDCE (Remov_fdce_C_CLR) -0.067 -0.596 u_Axi_CDC/wFifo/pushCC_pushPtrGray_reg[0] ------------------------------------------------------------------- required time 0.596 arrival time 0.375 ------------------------------------------------------------------- slack 0.972 Slack (MET) : 0.972ns (arrival time - required time) Source: pll_clk.u_rst_cpu/delay_reg[1]/C (rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Destination: u_Axi_CDC/wFifo/pushCC_pushPtrGray_reg[2]/CLR (removal check against rising-edge clock cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) Data Path Delay: 0.920ns (logic 0.209ns (22.721%) route 0.711ns (77.279%)) Logic Levels: 1 (LUT1=1) Clock Path Skew: 0.015ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.337ns Source Clock Delay (SCD): -0.544ns Clock Pessimism Removal (CPR): 0.192ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 0.718 -0.544 pll_clk.u_rst_cpu/cpu_clk SLICE_X6Y63 FDCE r pll_clk.u_rst_cpu/delay_reg[1]/C ------------------------------------------------------------------- ------------------- SLICE_X6Y63 FDCE (Prop_fdce_C_Q) 0.164 -0.380 r pll_clk.u_rst_cpu/delay_reg[1]/Q net (fo=1, routed) 0.221 -0.159 pll_clk.u_rst_cpu/cpu_resetn SLICE_X6Y63 LUT1 (Prop_lut1_I0_O) 0.045 -0.114 f pll_clk.u_rst_cpu/reset_i_1/O net (fo=40, routed) 0.490 0.375 u_Axi_CDC/wFifo/p_0_in SLICE_X10Y58 FDCE f u_Axi_CDC/wFifo/pushCC_pushPtrGray_reg[2]/CLR ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 0.971 -0.337 u_Axi_CDC/wFifo/cpu_clk SLICE_X10Y58 FDCE r u_Axi_CDC/wFifo/pushCC_pushPtrGray_reg[2]/C clock pessimism -0.192 -0.529 SLICE_X10Y58 FDCE (Remov_fdce_C_CLR) -0.067 -0.596 u_Axi_CDC/wFifo/pushCC_pushPtrGray_reg[2] ------------------------------------------------------------------- required time 0.596 arrival time 0.375 ------------------------------------------------------------------- slack 0.972 Slack (MET) : 0.972ns (arrival time - required time) Source: pll_clk.u_rst_cpu/delay_reg[1]/C (rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Destination: u_Axi_CDC/wFifo/pushCC_pushPtrGray_reg[3]/CLR (removal check against rising-edge clock cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) Data Path Delay: 0.920ns (logic 0.209ns (22.721%) route 0.711ns (77.279%)) Logic Levels: 1 (LUT1=1) Clock Path Skew: 0.015ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.337ns Source Clock Delay (SCD): -0.544ns Clock Pessimism Removal (CPR): 0.192ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 0.718 -0.544 pll_clk.u_rst_cpu/cpu_clk SLICE_X6Y63 FDCE r pll_clk.u_rst_cpu/delay_reg[1]/C ------------------------------------------------------------------- ------------------- SLICE_X6Y63 FDCE (Prop_fdce_C_Q) 0.164 -0.380 r pll_clk.u_rst_cpu/delay_reg[1]/Q net (fo=1, routed) 0.221 -0.159 pll_clk.u_rst_cpu/cpu_resetn SLICE_X6Y63 LUT1 (Prop_lut1_I0_O) 0.045 -0.114 f pll_clk.u_rst_cpu/reset_i_1/O net (fo=40, routed) 0.490 0.375 u_Axi_CDC/wFifo/p_0_in SLICE_X10Y58 FDCE f u_Axi_CDC/wFifo/pushCC_pushPtrGray_reg[3]/CLR ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 0.971 -0.337 u_Axi_CDC/wFifo/cpu_clk SLICE_X10Y58 FDCE r u_Axi_CDC/wFifo/pushCC_pushPtrGray_reg[3]/C clock pessimism -0.192 -0.529 SLICE_X10Y58 FDCE (Remov_fdce_C_CLR) -0.067 -0.596 u_Axi_CDC/wFifo/pushCC_pushPtrGray_reg[3] ------------------------------------------------------------------- required time 0.596 arrival time 0.375 ------------------------------------------------------------------- slack 0.972 Slack (MET) : 0.978ns (arrival time - required time) Source: pll_clk.u_rst_cpu/delay_reg[1]/C (rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Destination: u_Axi_CDC/awFifo/popToPushGray_buffercc/buffers_0_reg[0]/CLR (removal check against rising-edge clock cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) Data Path Delay: 0.924ns (logic 0.209ns (22.613%) route 0.715ns (77.387%)) Logic Levels: 1 (LUT1=1) Clock Path Skew: 0.013ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.339ns Source Clock Delay (SCD): -0.544ns Clock Pessimism Removal (CPR): 0.192ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 0.718 -0.544 pll_clk.u_rst_cpu/cpu_clk SLICE_X6Y63 FDCE r pll_clk.u_rst_cpu/delay_reg[1]/C ------------------------------------------------------------------- ------------------- SLICE_X6Y63 FDCE (Prop_fdce_C_Q) 0.164 -0.380 r pll_clk.u_rst_cpu/delay_reg[1]/Q net (fo=1, routed) 0.221 -0.159 pll_clk.u_rst_cpu/cpu_resetn SLICE_X6Y63 LUT1 (Prop_lut1_I0_O) 0.045 -0.114 f pll_clk.u_rst_cpu/reset_i_1/O net (fo=40, routed) 0.494 0.380 u_Axi_CDC/awFifo/popToPushGray_buffercc/p_0_in SLICE_X16Y61 FDCE f u_Axi_CDC/awFifo/popToPushGray_buffercc/buffers_0_reg[0]/CLR ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 0.969 -0.339 u_Axi_CDC/awFifo/popToPushGray_buffercc/cpu_clk SLICE_X16Y61 FDCE r u_Axi_CDC/awFifo/popToPushGray_buffercc/buffers_0_reg[0]/C clock pessimism -0.192 -0.531 SLICE_X16Y61 FDCE (Remov_fdce_C_CLR) -0.067 -0.598 u_Axi_CDC/awFifo/popToPushGray_buffercc/buffers_0_reg[0] ------------------------------------------------------------------- required time 0.598 arrival time 0.380 ------------------------------------------------------------------- slack 0.978 Slack (MET) : 0.978ns (arrival time - required time) Source: pll_clk.u_rst_cpu/delay_reg[1]/C (rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Destination: u_Axi_CDC/awFifo/popToPushGray_buffercc/buffers_0_reg[1]/CLR (removal check against rising-edge clock cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) Data Path Delay: 0.924ns (logic 0.209ns (22.613%) route 0.715ns (77.387%)) Logic Levels: 1 (LUT1=1) Clock Path Skew: 0.013ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.339ns Source Clock Delay (SCD): -0.544ns Clock Pessimism Removal (CPR): 0.192ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 0.718 -0.544 pll_clk.u_rst_cpu/cpu_clk SLICE_X6Y63 FDCE r pll_clk.u_rst_cpu/delay_reg[1]/C ------------------------------------------------------------------- ------------------- SLICE_X6Y63 FDCE (Prop_fdce_C_Q) 0.164 -0.380 r pll_clk.u_rst_cpu/delay_reg[1]/Q net (fo=1, routed) 0.221 -0.159 pll_clk.u_rst_cpu/cpu_resetn SLICE_X6Y63 LUT1 (Prop_lut1_I0_O) 0.045 -0.114 f pll_clk.u_rst_cpu/reset_i_1/O net (fo=40, routed) 0.494 0.380 u_Axi_CDC/awFifo/popToPushGray_buffercc/p_0_in SLICE_X16Y61 FDCE f u_Axi_CDC/awFifo/popToPushGray_buffercc/buffers_0_reg[1]/CLR ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 0.969 -0.339 u_Axi_CDC/awFifo/popToPushGray_buffercc/cpu_clk SLICE_X16Y61 FDCE r u_Axi_CDC/awFifo/popToPushGray_buffercc/buffers_0_reg[1]/C clock pessimism -0.192 -0.531 SLICE_X16Y61 FDCE (Remov_fdce_C_CLR) -0.067 -0.598 u_Axi_CDC/awFifo/popToPushGray_buffercc/buffers_0_reg[1] ------------------------------------------------------------------- required time 0.598 arrival time 0.380 ------------------------------------------------------------------- slack 0.978 Slack (MET) : 0.978ns (arrival time - required time) Source: pll_clk.u_rst_cpu/delay_reg[1]/C (rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Destination: u_Axi_CDC/awFifo/popToPushGray_buffercc/buffers_0_reg[2]/CLR (removal check against rising-edge clock cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) Data Path Delay: 0.924ns (logic 0.209ns (22.613%) route 0.715ns (77.387%)) Logic Levels: 1 (LUT1=1) Clock Path Skew: 0.013ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.339ns Source Clock Delay (SCD): -0.544ns Clock Pessimism Removal (CPR): 0.192ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 0.718 -0.544 pll_clk.u_rst_cpu/cpu_clk SLICE_X6Y63 FDCE r pll_clk.u_rst_cpu/delay_reg[1]/C ------------------------------------------------------------------- ------------------- SLICE_X6Y63 FDCE (Prop_fdce_C_Q) 0.164 -0.380 r pll_clk.u_rst_cpu/delay_reg[1]/Q net (fo=1, routed) 0.221 -0.159 pll_clk.u_rst_cpu/cpu_resetn SLICE_X6Y63 LUT1 (Prop_lut1_I0_O) 0.045 -0.114 f pll_clk.u_rst_cpu/reset_i_1/O net (fo=40, routed) 0.494 0.380 u_Axi_CDC/awFifo/popToPushGray_buffercc/p_0_in SLICE_X16Y61 FDCE f u_Axi_CDC/awFifo/popToPushGray_buffercc/buffers_0_reg[2]/CLR ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 0.969 -0.339 u_Axi_CDC/awFifo/popToPushGray_buffercc/cpu_clk SLICE_X16Y61 FDCE r u_Axi_CDC/awFifo/popToPushGray_buffercc/buffers_0_reg[2]/C clock pessimism -0.192 -0.531 SLICE_X16Y61 FDCE (Remov_fdce_C_CLR) -0.067 -0.598 u_Axi_CDC/awFifo/popToPushGray_buffercc/buffers_0_reg[2] ------------------------------------------------------------------- required time 0.598 arrival time 0.380 ------------------------------------------------------------------- slack 0.978 Slack (MET) : 0.978ns (arrival time - required time) Source: pll_clk.u_rst_cpu/delay_reg[1]/C (rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Destination: u_Axi_CDC/awFifo/popToPushGray_buffercc/buffers_1_reg[0]/CLR (removal check against rising-edge clock cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) Data Path Delay: 0.924ns (logic 0.209ns (22.613%) route 0.715ns (77.387%)) Logic Levels: 1 (LUT1=1) Clock Path Skew: 0.013ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.339ns Source Clock Delay (SCD): -0.544ns Clock Pessimism Removal (CPR): 0.192ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 0.718 -0.544 pll_clk.u_rst_cpu/cpu_clk SLICE_X6Y63 FDCE r pll_clk.u_rst_cpu/delay_reg[1]/C ------------------------------------------------------------------- ------------------- SLICE_X6Y63 FDCE (Prop_fdce_C_Q) 0.164 -0.380 r pll_clk.u_rst_cpu/delay_reg[1]/Q net (fo=1, routed) 0.221 -0.159 pll_clk.u_rst_cpu/cpu_resetn SLICE_X6Y63 LUT1 (Prop_lut1_I0_O) 0.045 -0.114 f pll_clk.u_rst_cpu/reset_i_1/O net (fo=40, routed) 0.494 0.380 u_Axi_CDC/awFifo/popToPushGray_buffercc/p_0_in SLICE_X16Y61 FDCE f u_Axi_CDC/awFifo/popToPushGray_buffercc/buffers_1_reg[0]/CLR ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 0.969 -0.339 u_Axi_CDC/awFifo/popToPushGray_buffercc/cpu_clk SLICE_X16Y61 FDCE r u_Axi_CDC/awFifo/popToPushGray_buffercc/buffers_1_reg[0]/C clock pessimism -0.192 -0.531 SLICE_X16Y61 FDCE (Remov_fdce_C_CLR) -0.067 -0.598 u_Axi_CDC/awFifo/popToPushGray_buffercc/buffers_1_reg[0] ------------------------------------------------------------------- required time 0.598 arrival time 0.380 ------------------------------------------------------------------- slack 0.978 Slack (MET) : 0.978ns (arrival time - required time) Source: pll_clk.u_rst_cpu/delay_reg[1]/C (rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Destination: u_Axi_CDC/awFifo/popToPushGray_buffercc/buffers_1_reg[1]/CLR (removal check against rising-edge clock cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) Data Path Delay: 0.924ns (logic 0.209ns (22.613%) route 0.715ns (77.387%)) Logic Levels: 1 (LUT1=1) Clock Path Skew: 0.013ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.339ns Source Clock Delay (SCD): -0.544ns Clock Pessimism Removal (CPR): 0.192ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 0.718 -0.544 pll_clk.u_rst_cpu/cpu_clk SLICE_X6Y63 FDCE r pll_clk.u_rst_cpu/delay_reg[1]/C ------------------------------------------------------------------- ------------------- SLICE_X6Y63 FDCE (Prop_fdce_C_Q) 0.164 -0.380 r pll_clk.u_rst_cpu/delay_reg[1]/Q net (fo=1, routed) 0.221 -0.159 pll_clk.u_rst_cpu/cpu_resetn SLICE_X6Y63 LUT1 (Prop_lut1_I0_O) 0.045 -0.114 f pll_clk.u_rst_cpu/reset_i_1/O net (fo=40, routed) 0.494 0.380 u_Axi_CDC/awFifo/popToPushGray_buffercc/p_0_in SLICE_X16Y61 FDCE f u_Axi_CDC/awFifo/popToPushGray_buffercc/buffers_1_reg[1]/CLR ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 0.969 -0.339 u_Axi_CDC/awFifo/popToPushGray_buffercc/cpu_clk SLICE_X16Y61 FDCE r u_Axi_CDC/awFifo/popToPushGray_buffercc/buffers_1_reg[1]/C clock pessimism -0.192 -0.531 SLICE_X16Y61 FDCE (Remov_fdce_C_CLR) -0.067 -0.598 u_Axi_CDC/awFifo/popToPushGray_buffercc/buffers_1_reg[1] ------------------------------------------------------------------- required time 0.598 arrival time 0.380 ------------------------------------------------------------------- slack 0.978 Slack (MET) : 0.978ns (arrival time - required time) Source: pll_clk.u_rst_cpu/delay_reg[1]/C (rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Destination: u_Axi_CDC/awFifo/popToPushGray_buffercc/buffers_1_reg[2]/CLR (removal check against rising-edge clock cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) Data Path Delay: 0.924ns (logic 0.209ns (22.613%) route 0.715ns (77.387%)) Logic Levels: 1 (LUT1=1) Clock Path Skew: 0.013ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.339ns Source Clock Delay (SCD): -0.544ns Clock Pessimism Removal (CPR): 0.192ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 0.718 -0.544 pll_clk.u_rst_cpu/cpu_clk SLICE_X6Y63 FDCE r pll_clk.u_rst_cpu/delay_reg[1]/C ------------------------------------------------------------------- ------------------- SLICE_X6Y63 FDCE (Prop_fdce_C_Q) 0.164 -0.380 r pll_clk.u_rst_cpu/delay_reg[1]/Q net (fo=1, routed) 0.221 -0.159 pll_clk.u_rst_cpu/cpu_resetn SLICE_X6Y63 LUT1 (Prop_lut1_I0_O) 0.045 -0.114 f pll_clk.u_rst_cpu/reset_i_1/O net (fo=40, routed) 0.494 0.380 u_Axi_CDC/awFifo/popToPushGray_buffercc/p_0_in SLICE_X16Y61 FDCE f u_Axi_CDC/awFifo/popToPushGray_buffercc/buffers_1_reg[2]/CLR ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 0.969 -0.339 u_Axi_CDC/awFifo/popToPushGray_buffercc/cpu_clk SLICE_X16Y61 FDCE r u_Axi_CDC/awFifo/popToPushGray_buffercc/buffers_1_reg[2]/C clock pessimism -0.192 -0.531 SLICE_X16Y61 FDCE (Remov_fdce_C_CLR) -0.067 -0.598 u_Axi_CDC/awFifo/popToPushGray_buffercc/buffers_1_reg[2] ------------------------------------------------------------------- required time 0.598 arrival time 0.380 ------------------------------------------------------------------- slack 0.978 Slack (MET) : 1.003ns (arrival time - required time) Source: pll_clk.u_rst_cpu/delay_reg[1]/C (rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Destination: u_Axi_CDC/awFifo/pushCC_pushPtrGray_reg[0]/CLR (removal check against rising-edge clock cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) Data Path Delay: 0.924ns (logic 0.209ns (22.613%) route 0.715ns (77.387%)) Logic Levels: 1 (LUT1=1) Clock Path Skew: 0.013ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.339ns Source Clock Delay (SCD): -0.544ns Clock Pessimism Removal (CPR): 0.192ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 0.718 -0.544 pll_clk.u_rst_cpu/cpu_clk SLICE_X6Y63 FDCE r pll_clk.u_rst_cpu/delay_reg[1]/C ------------------------------------------------------------------- ------------------- SLICE_X6Y63 FDCE (Prop_fdce_C_Q) 0.164 -0.380 r pll_clk.u_rst_cpu/delay_reg[1]/Q net (fo=1, routed) 0.221 -0.159 pll_clk.u_rst_cpu/cpu_resetn SLICE_X6Y63 LUT1 (Prop_lut1_I0_O) 0.045 -0.114 f pll_clk.u_rst_cpu/reset_i_1/O net (fo=40, routed) 0.494 0.380 u_Axi_CDC/awFifo/p_0_in SLICE_X17Y61 FDCE f u_Axi_CDC/awFifo/pushCC_pushPtrGray_reg[0]/CLR ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 0.969 -0.339 u_Axi_CDC/awFifo/cpu_clk SLICE_X17Y61 FDCE r u_Axi_CDC/awFifo/pushCC_pushPtrGray_reg[0]/C clock pessimism -0.192 -0.531 SLICE_X17Y61 FDCE (Remov_fdce_C_CLR) -0.092 -0.623 u_Axi_CDC/awFifo/pushCC_pushPtrGray_reg[0] ------------------------------------------------------------------- required time 0.623 arrival time 0.380 ------------------------------------------------------------------- slack 1.003 Slack (MET) : 1.003ns (arrival time - required time) Source: pll_clk.u_rst_cpu/delay_reg[1]/C (rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Destination: u_Axi_CDC/awFifo/pushCC_pushPtrGray_reg[1]/CLR (removal check against rising-edge clock cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) Data Path Delay: 0.924ns (logic 0.209ns (22.613%) route 0.715ns (77.387%)) Logic Levels: 1 (LUT1=1) Clock Path Skew: 0.013ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.339ns Source Clock Delay (SCD): -0.544ns Clock Pessimism Removal (CPR): 0.192ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 0.718 -0.544 pll_clk.u_rst_cpu/cpu_clk SLICE_X6Y63 FDCE r pll_clk.u_rst_cpu/delay_reg[1]/C ------------------------------------------------------------------- ------------------- SLICE_X6Y63 FDCE (Prop_fdce_C_Q) 0.164 -0.380 r pll_clk.u_rst_cpu/delay_reg[1]/Q net (fo=1, routed) 0.221 -0.159 pll_clk.u_rst_cpu/cpu_resetn SLICE_X6Y63 LUT1 (Prop_lut1_I0_O) 0.045 -0.114 f pll_clk.u_rst_cpu/reset_i_1/O net (fo=40, routed) 0.494 0.380 u_Axi_CDC/awFifo/p_0_in SLICE_X17Y61 FDCE f u_Axi_CDC/awFifo/pushCC_pushPtrGray_reg[1]/CLR ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 0.969 -0.339 u_Axi_CDC/awFifo/cpu_clk SLICE_X17Y61 FDCE r u_Axi_CDC/awFifo/pushCC_pushPtrGray_reg[1]/C clock pessimism -0.192 -0.531 SLICE_X17Y61 FDCE (Remov_fdce_C_CLR) -0.092 -0.623 u_Axi_CDC/awFifo/pushCC_pushPtrGray_reg[1] ------------------------------------------------------------------- required time 0.623 arrival time 0.380 ------------------------------------------------------------------- slack 1.003 Slack (MET) : 1.003ns (arrival time - required time) Source: pll_clk.u_rst_cpu/delay_reg[1]/C (rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Destination: u_Axi_CDC/awFifo/pushCC_pushPtrGray_reg[2]/CLR (removal check against rising-edge clock cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) Data Path Delay: 0.924ns (logic 0.209ns (22.613%) route 0.715ns (77.387%)) Logic Levels: 1 (LUT1=1) Clock Path Skew: 0.013ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.339ns Source Clock Delay (SCD): -0.544ns Clock Pessimism Removal (CPR): 0.192ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 0.718 -0.544 pll_clk.u_rst_cpu/cpu_clk SLICE_X6Y63 FDCE r pll_clk.u_rst_cpu/delay_reg[1]/C ------------------------------------------------------------------- ------------------- SLICE_X6Y63 FDCE (Prop_fdce_C_Q) 0.164 -0.380 r pll_clk.u_rst_cpu/delay_reg[1]/Q net (fo=1, routed) 0.221 -0.159 pll_clk.u_rst_cpu/cpu_resetn SLICE_X6Y63 LUT1 (Prop_lut1_I0_O) 0.045 -0.114 f pll_clk.u_rst_cpu/reset_i_1/O net (fo=40, routed) 0.494 0.380 u_Axi_CDC/awFifo/p_0_in SLICE_X17Y61 FDCE f u_Axi_CDC/awFifo/pushCC_pushPtrGray_reg[2]/CLR ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 0.969 -0.339 u_Axi_CDC/awFifo/cpu_clk SLICE_X17Y61 FDCE r u_Axi_CDC/awFifo/pushCC_pushPtrGray_reg[2]/C clock pessimism -0.192 -0.531 SLICE_X17Y61 FDCE (Remov_fdce_C_CLR) -0.092 -0.623 u_Axi_CDC/awFifo/pushCC_pushPtrGray_reg[2] ------------------------------------------------------------------- required time 0.623 arrival time 0.380 ------------------------------------------------------------------- slack 1.003 Slack (MET) : 1.003ns (arrival time - required time) Source: pll_clk.u_rst_cpu/delay_reg[1]/C (rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Destination: u_Axi_CDC/awFifo/pushCC_pushPtr_reg[0]/CLR (removal check against rising-edge clock cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) Data Path Delay: 0.924ns (logic 0.209ns (22.613%) route 0.715ns (77.387%)) Logic Levels: 1 (LUT1=1) Clock Path Skew: 0.013ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.339ns Source Clock Delay (SCD): -0.544ns Clock Pessimism Removal (CPR): 0.192ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 0.718 -0.544 pll_clk.u_rst_cpu/cpu_clk SLICE_X6Y63 FDCE r pll_clk.u_rst_cpu/delay_reg[1]/C ------------------------------------------------------------------- ------------------- SLICE_X6Y63 FDCE (Prop_fdce_C_Q) 0.164 -0.380 r pll_clk.u_rst_cpu/delay_reg[1]/Q net (fo=1, routed) 0.221 -0.159 pll_clk.u_rst_cpu/cpu_resetn SLICE_X6Y63 LUT1 (Prop_lut1_I0_O) 0.045 -0.114 f pll_clk.u_rst_cpu/reset_i_1/O net (fo=40, routed) 0.494 0.380 u_Axi_CDC/awFifo/p_0_in SLICE_X17Y61 FDCE f u_Axi_CDC/awFifo/pushCC_pushPtr_reg[0]/CLR ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 0.969 -0.339 u_Axi_CDC/awFifo/cpu_clk SLICE_X17Y61 FDCE r u_Axi_CDC/awFifo/pushCC_pushPtr_reg[0]/C clock pessimism -0.192 -0.531 SLICE_X17Y61 FDCE (Remov_fdce_C_CLR) -0.092 -0.623 u_Axi_CDC/awFifo/pushCC_pushPtr_reg[0] ------------------------------------------------------------------- required time 0.623 arrival time 0.380 ------------------------------------------------------------------- slack 1.003 Slack (MET) : 1.003ns (arrival time - required time) Source: pll_clk.u_rst_cpu/delay_reg[1]/C (rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Destination: u_Axi_CDC/awFifo/pushCC_pushPtr_reg[1]/CLR (removal check against rising-edge clock cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) Data Path Delay: 0.924ns (logic 0.209ns (22.613%) route 0.715ns (77.387%)) Logic Levels: 1 (LUT1=1) Clock Path Skew: 0.013ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.339ns Source Clock Delay (SCD): -0.544ns Clock Pessimism Removal (CPR): 0.192ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 0.718 -0.544 pll_clk.u_rst_cpu/cpu_clk SLICE_X6Y63 FDCE r pll_clk.u_rst_cpu/delay_reg[1]/C ------------------------------------------------------------------- ------------------- SLICE_X6Y63 FDCE (Prop_fdce_C_Q) 0.164 -0.380 r pll_clk.u_rst_cpu/delay_reg[1]/Q net (fo=1, routed) 0.221 -0.159 pll_clk.u_rst_cpu/cpu_resetn SLICE_X6Y63 LUT1 (Prop_lut1_I0_O) 0.045 -0.114 f pll_clk.u_rst_cpu/reset_i_1/O net (fo=40, routed) 0.494 0.380 u_Axi_CDC/awFifo/p_0_in SLICE_X17Y61 FDCE f u_Axi_CDC/awFifo/pushCC_pushPtr_reg[1]/CLR ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 0.969 -0.339 u_Axi_CDC/awFifo/cpu_clk SLICE_X17Y61 FDCE r u_Axi_CDC/awFifo/pushCC_pushPtr_reg[1]/C clock pessimism -0.192 -0.531 SLICE_X17Y61 FDCE (Remov_fdce_C_CLR) -0.092 -0.623 u_Axi_CDC/awFifo/pushCC_pushPtr_reg[1] ------------------------------------------------------------------- required time 0.623 arrival time 0.380 ------------------------------------------------------------------- slack 1.003 Slack (MET) : 1.083ns (arrival time - required time) Source: pll_clk.u_rst_cpu/delay_reg[1]/C (rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Destination: u_Axi_CDC/wFifo/pushCC_pushPtrGray_reg[1]/CLR (removal check against rising-edge clock cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) Data Path Delay: 1.031ns (logic 0.209ns (20.279%) route 0.822ns (79.721%)) Logic Levels: 1 (LUT1=1) Clock Path Skew: 0.015ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.337ns Source Clock Delay (SCD): -0.544ns Clock Pessimism Removal (CPR): 0.192ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 0.718 -0.544 pll_clk.u_rst_cpu/cpu_clk SLICE_X6Y63 FDCE r pll_clk.u_rst_cpu/delay_reg[1]/C ------------------------------------------------------------------- ------------------- SLICE_X6Y63 FDCE (Prop_fdce_C_Q) 0.164 -0.380 r pll_clk.u_rst_cpu/delay_reg[1]/Q net (fo=1, routed) 0.221 -0.159 pll_clk.u_rst_cpu/cpu_resetn SLICE_X6Y63 LUT1 (Prop_lut1_I0_O) 0.045 -0.114 f pll_clk.u_rst_cpu/reset_i_1/O net (fo=40, routed) 0.601 0.486 u_Axi_CDC/wFifo/p_0_in SLICE_X8Y58 FDCE f u_Axi_CDC/wFifo/pushCC_pushPtrGray_reg[1]/CLR ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 0.971 -0.337 u_Axi_CDC/wFifo/cpu_clk SLICE_X8Y58 FDCE r u_Axi_CDC/wFifo/pushCC_pushPtrGray_reg[1]/C clock pessimism -0.192 -0.529 SLICE_X8Y58 FDCE (Remov_fdce_C_CLR) -0.067 -0.596 u_Axi_CDC/wFifo/pushCC_pushPtrGray_reg[1] ------------------------------------------------------------------- required time 0.596 arrival time 0.486 ------------------------------------------------------------------- slack 1.083 Slack (MET) : 1.083ns (arrival time - required time) Source: pll_clk.u_rst_cpu/delay_reg[1]/C (rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Destination: u_Axi_CDC/wFifo/pushCC_pushPtr_reg[0]/CLR (removal check against rising-edge clock cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) Data Path Delay: 1.031ns (logic 0.209ns (20.279%) route 0.822ns (79.721%)) Logic Levels: 1 (LUT1=1) Clock Path Skew: 0.015ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.337ns Source Clock Delay (SCD): -0.544ns Clock Pessimism Removal (CPR): 0.192ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 0.718 -0.544 pll_clk.u_rst_cpu/cpu_clk SLICE_X6Y63 FDCE r pll_clk.u_rst_cpu/delay_reg[1]/C ------------------------------------------------------------------- ------------------- SLICE_X6Y63 FDCE (Prop_fdce_C_Q) 0.164 -0.380 r pll_clk.u_rst_cpu/delay_reg[1]/Q net (fo=1, routed) 0.221 -0.159 pll_clk.u_rst_cpu/cpu_resetn SLICE_X6Y63 LUT1 (Prop_lut1_I0_O) 0.045 -0.114 f pll_clk.u_rst_cpu/reset_i_1/O net (fo=40, routed) 0.601 0.486 u_Axi_CDC/wFifo/p_0_in SLICE_X8Y58 FDCE f u_Axi_CDC/wFifo/pushCC_pushPtr_reg[0]/CLR ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 0.971 -0.337 u_Axi_CDC/wFifo/cpu_clk SLICE_X8Y58 FDCE r u_Axi_CDC/wFifo/pushCC_pushPtr_reg[0]/C clock pessimism -0.192 -0.529 SLICE_X8Y58 FDCE (Remov_fdce_C_CLR) -0.067 -0.596 u_Axi_CDC/wFifo/pushCC_pushPtr_reg[0] ------------------------------------------------------------------- required time 0.596 arrival time 0.486 ------------------------------------------------------------------- slack 1.083 Slack (MET) : 1.083ns (arrival time - required time) Source: pll_clk.u_rst_cpu/delay_reg[1]/C (rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Destination: u_Axi_CDC/wFifo/pushCC_pushPtr_reg[1]/CLR (removal check against rising-edge clock cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) Data Path Delay: 1.031ns (logic 0.209ns (20.279%) route 0.822ns (79.721%)) Logic Levels: 1 (LUT1=1) Clock Path Skew: 0.015ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.337ns Source Clock Delay (SCD): -0.544ns Clock Pessimism Removal (CPR): 0.192ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 0.718 -0.544 pll_clk.u_rst_cpu/cpu_clk SLICE_X6Y63 FDCE r pll_clk.u_rst_cpu/delay_reg[1]/C ------------------------------------------------------------------- ------------------- SLICE_X6Y63 FDCE (Prop_fdce_C_Q) 0.164 -0.380 r pll_clk.u_rst_cpu/delay_reg[1]/Q net (fo=1, routed) 0.221 -0.159 pll_clk.u_rst_cpu/cpu_resetn SLICE_X6Y63 LUT1 (Prop_lut1_I0_O) 0.045 -0.114 f pll_clk.u_rst_cpu/reset_i_1/O net (fo=40, routed) 0.601 0.486 u_Axi_CDC/wFifo/p_0_in SLICE_X8Y58 FDCE f u_Axi_CDC/wFifo/pushCC_pushPtr_reg[1]/CLR ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 0.971 -0.337 u_Axi_CDC/wFifo/cpu_clk SLICE_X8Y58 FDCE r u_Axi_CDC/wFifo/pushCC_pushPtr_reg[1]/C clock pessimism -0.192 -0.529 SLICE_X8Y58 FDCE (Remov_fdce_C_CLR) -0.067 -0.596 u_Axi_CDC/wFifo/pushCC_pushPtr_reg[1] ------------------------------------------------------------------- required time 0.596 arrival time 0.486 ------------------------------------------------------------------- slack 1.083 Slack (MET) : 1.083ns (arrival time - required time) Source: pll_clk.u_rst_cpu/delay_reg[1]/C (rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Destination: u_Axi_CDC/wFifo/pushCC_pushPtr_reg[2]/CLR (removal check against rising-edge clock cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) Data Path Delay: 1.031ns (logic 0.209ns (20.279%) route 0.822ns (79.721%)) Logic Levels: 1 (LUT1=1) Clock Path Skew: 0.015ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.337ns Source Clock Delay (SCD): -0.544ns Clock Pessimism Removal (CPR): 0.192ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 0.718 -0.544 pll_clk.u_rst_cpu/cpu_clk SLICE_X6Y63 FDCE r pll_clk.u_rst_cpu/delay_reg[1]/C ------------------------------------------------------------------- ------------------- SLICE_X6Y63 FDCE (Prop_fdce_C_Q) 0.164 -0.380 r pll_clk.u_rst_cpu/delay_reg[1]/Q net (fo=1, routed) 0.221 -0.159 pll_clk.u_rst_cpu/cpu_resetn SLICE_X6Y63 LUT1 (Prop_lut1_I0_O) 0.045 -0.114 f pll_clk.u_rst_cpu/reset_i_1/O net (fo=40, routed) 0.601 0.486 u_Axi_CDC/wFifo/p_0_in SLICE_X8Y58 FDCE f u_Axi_CDC/wFifo/pushCC_pushPtr_reg[2]/CLR ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 0.971 -0.337 u_Axi_CDC/wFifo/cpu_clk SLICE_X8Y58 FDCE r u_Axi_CDC/wFifo/pushCC_pushPtr_reg[2]/C clock pessimism -0.192 -0.529 SLICE_X8Y58 FDCE (Remov_fdce_C_CLR) -0.067 -0.596 u_Axi_CDC/wFifo/pushCC_pushPtr_reg[2] ------------------------------------------------------------------- required time 0.596 arrival time 0.486 ------------------------------------------------------------------- slack 1.083 Slack (MET) : 1.125ns (arrival time - required time) Source: u_Axi_CDC/bFifo/bufferCC_12/buffers_1_reg/C (rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Destination: u_Axi_CDC/rFifo/popCC_popPtr_reg[0]/CLR (removal check against rising-edge clock cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) Data Path Delay: 1.043ns (logic 0.246ns (23.575%) route 0.797ns (76.425%)) Logic Levels: 1 (LUT1=1) Clock Path Skew: 0.010ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.342ns Source Clock Delay (SCD): -0.544ns Clock Pessimism Removal (CPR): 0.192ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 0.718 -0.544 u_Axi_CDC/bFifo/bufferCC_12/cpu_clk SLICE_X6Y63 FDCE r u_Axi_CDC/bFifo/bufferCC_12/buffers_1_reg/C ------------------------------------------------------------------- ------------------- SLICE_X6Y63 FDCE (Prop_fdce_C_Q) 0.148 -0.396 r u_Axi_CDC/bFifo/bufferCC_12/buffers_1_reg/Q net (fo=1, routed) 0.125 -0.271 u_Axi_CDC/bFifo/bufferCC_12/buffers_1 SLICE_X6Y63 LUT1 (Prop_lut1_I0_O) 0.098 -0.173 f u_Axi_CDC/bFifo/bufferCC_12/popCC_popPtr[2]_i_2__0/O net (fo=30, routed) 0.672 0.499 u_Axi_CDC/rFifo/buffers_0_reg[3] SLICE_X13Y64 FDCE f u_Axi_CDC/rFifo/popCC_popPtr_reg[0]/CLR ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 0.966 -0.342 u_Axi_CDC/rFifo/cpu_clk SLICE_X13Y64 FDCE r u_Axi_CDC/rFifo/popCC_popPtr_reg[0]/C clock pessimism -0.192 -0.534 SLICE_X13Y64 FDCE (Remov_fdce_C_CLR) -0.092 -0.626 u_Axi_CDC/rFifo/popCC_popPtr_reg[0] ------------------------------------------------------------------- required time 0.626 arrival time 0.499 ------------------------------------------------------------------- slack 1.125 Slack (MET) : 1.125ns (arrival time - required time) Source: u_Axi_CDC/bFifo/bufferCC_12/buffers_1_reg/C (rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Destination: u_Axi_CDC/rFifo/popCC_popPtr_reg[1]/CLR (removal check against rising-edge clock cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) Data Path Delay: 1.043ns (logic 0.246ns (23.575%) route 0.797ns (76.425%)) Logic Levels: 1 (LUT1=1) Clock Path Skew: 0.010ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.342ns Source Clock Delay (SCD): -0.544ns Clock Pessimism Removal (CPR): 0.192ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 0.718 -0.544 u_Axi_CDC/bFifo/bufferCC_12/cpu_clk SLICE_X6Y63 FDCE r u_Axi_CDC/bFifo/bufferCC_12/buffers_1_reg/C ------------------------------------------------------------------- ------------------- SLICE_X6Y63 FDCE (Prop_fdce_C_Q) 0.148 -0.396 r u_Axi_CDC/bFifo/bufferCC_12/buffers_1_reg/Q net (fo=1, routed) 0.125 -0.271 u_Axi_CDC/bFifo/bufferCC_12/buffers_1 SLICE_X6Y63 LUT1 (Prop_lut1_I0_O) 0.098 -0.173 f u_Axi_CDC/bFifo/bufferCC_12/popCC_popPtr[2]_i_2__0/O net (fo=30, routed) 0.672 0.499 u_Axi_CDC/rFifo/buffers_0_reg[3] SLICE_X13Y64 FDCE f u_Axi_CDC/rFifo/popCC_popPtr_reg[1]/CLR ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 0.966 -0.342 u_Axi_CDC/rFifo/cpu_clk SLICE_X13Y64 FDCE r u_Axi_CDC/rFifo/popCC_popPtr_reg[1]/C clock pessimism -0.192 -0.534 SLICE_X13Y64 FDCE (Remov_fdce_C_CLR) -0.092 -0.626 u_Axi_CDC/rFifo/popCC_popPtr_reg[1] ------------------------------------------------------------------- required time 0.626 arrival time 0.499 ------------------------------------------------------------------- slack 1.125 Slack (MET) : 1.125ns (arrival time - required time) Source: u_Axi_CDC/bFifo/bufferCC_12/buffers_1_reg/C (rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Destination: u_Axi_CDC/rFifo/popCC_popPtr_reg[2]/CLR (removal check against rising-edge clock cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) Data Path Delay: 1.043ns (logic 0.246ns (23.575%) route 0.797ns (76.425%)) Logic Levels: 1 (LUT1=1) Clock Path Skew: 0.010ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.342ns Source Clock Delay (SCD): -0.544ns Clock Pessimism Removal (CPR): 0.192ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 0.718 -0.544 u_Axi_CDC/bFifo/bufferCC_12/cpu_clk SLICE_X6Y63 FDCE r u_Axi_CDC/bFifo/bufferCC_12/buffers_1_reg/C ------------------------------------------------------------------- ------------------- SLICE_X6Y63 FDCE (Prop_fdce_C_Q) 0.148 -0.396 r u_Axi_CDC/bFifo/bufferCC_12/buffers_1_reg/Q net (fo=1, routed) 0.125 -0.271 u_Axi_CDC/bFifo/bufferCC_12/buffers_1 SLICE_X6Y63 LUT1 (Prop_lut1_I0_O) 0.098 -0.173 f u_Axi_CDC/bFifo/bufferCC_12/popCC_popPtr[2]_i_2__0/O net (fo=30, routed) 0.672 0.499 u_Axi_CDC/rFifo/buffers_0_reg[3] SLICE_X13Y64 FDCE f u_Axi_CDC/rFifo/popCC_popPtr_reg[2]/CLR ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 0.966 -0.342 u_Axi_CDC/rFifo/cpu_clk SLICE_X13Y64 FDCE r u_Axi_CDC/rFifo/popCC_popPtr_reg[2]/C clock pessimism -0.192 -0.534 SLICE_X13Y64 FDCE (Remov_fdce_C_CLR) -0.092 -0.626 u_Axi_CDC/rFifo/popCC_popPtr_reg[2] ------------------------------------------------------------------- required time 0.626 arrival time 0.499 ------------------------------------------------------------------- slack 1.125 --------------------------------------------------------------------------------------------------- Path Group: **async_default** From Clock: mlkem_clk_clk_pll To Clock: mlkem_clk_clk_pll Setup : NA Failing Endpoints, Worst Slack NA , Total Violation NA Hold : 0 Failing Endpoints, Worst Slack 0.518ns, Total Violation 0.000ns --------------------------------------------------------------------------------------------------- Min Delay Paths -------------------------------------------------------------------------------------- Slack (MET) : 0.518ns (arrival time - required time) Source: pll_clk.u_rst_mlkem/delay_reg[1]/C (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/stream_lane_reg[0]/CLR (removal check against rising-edge clock mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (mlkem_clk_clk_pll rise@0.000ns - mlkem_clk_clk_pll rise@0.000ns) Data Path Delay: 0.725ns (logic 0.185ns (25.518%) route 0.540ns (74.482%)) Logic Levels: 1 (LUT1=1) Clock Path Skew: 0.336ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.386ns Source Clock Delay (SCD): -0.682ns Clock Pessimism Removal (CPR): -0.040ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock mlkem_clk_clk_pll rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout3_buf/O net (fo=25775, routed) 0.581 -0.682 pll_clk.u_rst_mlkem/mlkem_clk SLICE_X67Y102 FDCE r pll_clk.u_rst_mlkem/delay_reg[1]/C ------------------------------------------------------------------- ------------------- SLICE_X67Y102 FDCE (Prop_fdce_C_Q) 0.141 -0.541 r pll_clk.u_rst_mlkem/delay_reg[1]/Q net (fo=4, routed) 0.382 -0.159 pll_clk.u_rst_mlkem/Q[0] SLICE_X69Y98 LUT1 (Prop_lut1_I0_O) 0.044 -0.115 f pll_clk.u_rst_mlkem/rdb_addr[11]_i_2/O net (fo=1066, routed) 0.158 0.043 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/msg_word_reg[7][31]_0 SLICE_X68Y99 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/stream_lane_reg[0]/CLR ------------------------------------------------------------------- ------------------- (clock mlkem_clk_clk_pll rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout3_buf/O net (fo=25775, routed) 0.922 -0.386 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/mlkem_clk SLICE_X68Y99 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/stream_lane_reg[0]/C clock pessimism 0.040 -0.346 SLICE_X68Y99 FDCE (Remov_fdce_C_CLR) -0.129 -0.475 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/stream_lane_reg[0] ------------------------------------------------------------------- required time 0.475 arrival time 0.043 ------------------------------------------------------------------- slack 0.518 Slack (MET) : 0.518ns (arrival time - required time) Source: pll_clk.u_rst_mlkem/delay_reg[1]/C (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/stream_lane_reg[1]/CLR (removal check against rising-edge clock mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (mlkem_clk_clk_pll rise@0.000ns - mlkem_clk_clk_pll rise@0.000ns) Data Path Delay: 0.725ns (logic 0.185ns (25.518%) route 0.540ns (74.482%)) Logic Levels: 1 (LUT1=1) Clock Path Skew: 0.336ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.386ns Source Clock Delay (SCD): -0.682ns Clock Pessimism Removal (CPR): -0.040ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock mlkem_clk_clk_pll rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout3_buf/O net (fo=25775, routed) 0.581 -0.682 pll_clk.u_rst_mlkem/mlkem_clk SLICE_X67Y102 FDCE r pll_clk.u_rst_mlkem/delay_reg[1]/C ------------------------------------------------------------------- ------------------- SLICE_X67Y102 FDCE (Prop_fdce_C_Q) 0.141 -0.541 r pll_clk.u_rst_mlkem/delay_reg[1]/Q net (fo=4, routed) 0.382 -0.159 pll_clk.u_rst_mlkem/Q[0] SLICE_X69Y98 LUT1 (Prop_lut1_I0_O) 0.044 -0.115 f pll_clk.u_rst_mlkem/rdb_addr[11]_i_2/O net (fo=1066, routed) 0.158 0.043 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/msg_word_reg[7][31]_0 SLICE_X68Y99 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/stream_lane_reg[1]/CLR ------------------------------------------------------------------- ------------------- (clock mlkem_clk_clk_pll rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout3_buf/O net (fo=25775, routed) 0.922 -0.386 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/mlkem_clk SLICE_X68Y99 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/stream_lane_reg[1]/C clock pessimism 0.040 -0.346 SLICE_X68Y99 FDCE (Remov_fdce_C_CLR) -0.129 -0.475 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/stream_lane_reg[1] ------------------------------------------------------------------- required time 0.475 arrival time 0.043 ------------------------------------------------------------------- slack 0.518 Slack (MET) : 0.518ns (arrival time - required time) Source: pll_clk.u_rst_mlkem/delay_reg[1]/C (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/stream_lane_reg[2]/CLR (removal check against rising-edge clock mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (mlkem_clk_clk_pll rise@0.000ns - mlkem_clk_clk_pll rise@0.000ns) Data Path Delay: 0.725ns (logic 0.185ns (25.518%) route 0.540ns (74.482%)) Logic Levels: 1 (LUT1=1) Clock Path Skew: 0.336ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.386ns Source Clock Delay (SCD): -0.682ns Clock Pessimism Removal (CPR): -0.040ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock mlkem_clk_clk_pll rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout3_buf/O net (fo=25775, routed) 0.581 -0.682 pll_clk.u_rst_mlkem/mlkem_clk SLICE_X67Y102 FDCE r pll_clk.u_rst_mlkem/delay_reg[1]/C ------------------------------------------------------------------- ------------------- SLICE_X67Y102 FDCE (Prop_fdce_C_Q) 0.141 -0.541 r pll_clk.u_rst_mlkem/delay_reg[1]/Q net (fo=4, routed) 0.382 -0.159 pll_clk.u_rst_mlkem/Q[0] SLICE_X69Y98 LUT1 (Prop_lut1_I0_O) 0.044 -0.115 f pll_clk.u_rst_mlkem/rdb_addr[11]_i_2/O net (fo=1066, routed) 0.158 0.043 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/msg_word_reg[7][31]_0 SLICE_X68Y99 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/stream_lane_reg[2]/CLR ------------------------------------------------------------------- ------------------- (clock mlkem_clk_clk_pll rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout3_buf/O net (fo=25775, routed) 0.922 -0.386 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/mlkem_clk SLICE_X68Y99 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/stream_lane_reg[2]/C clock pessimism 0.040 -0.346 SLICE_X68Y99 FDCE (Remov_fdce_C_CLR) -0.129 -0.475 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/stream_lane_reg[2] ------------------------------------------------------------------- required time 0.475 arrival time 0.043 ------------------------------------------------------------------- slack 0.518 Slack (MET) : 0.543ns (arrival time - required time) Source: pll_clk.u_rst_mlkem/delay_reg[1]/C (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/w_state_reg[0]/CLR (removal check against rising-edge clock mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (mlkem_clk_clk_pll rise@0.000ns - mlkem_clk_clk_pll rise@0.000ns) Data Path Delay: 0.725ns (logic 0.185ns (25.518%) route 0.540ns (74.482%)) Logic Levels: 1 (LUT1=1) Clock Path Skew: 0.336ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.386ns Source Clock Delay (SCD): -0.682ns Clock Pessimism Removal (CPR): -0.040ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock mlkem_clk_clk_pll rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout3_buf/O net (fo=25775, routed) 0.581 -0.682 pll_clk.u_rst_mlkem/mlkem_clk SLICE_X67Y102 FDCE r pll_clk.u_rst_mlkem/delay_reg[1]/C ------------------------------------------------------------------- ------------------- SLICE_X67Y102 FDCE (Prop_fdce_C_Q) 0.141 -0.541 r pll_clk.u_rst_mlkem/delay_reg[1]/Q net (fo=4, routed) 0.382 -0.159 pll_clk.u_rst_mlkem/Q[0] SLICE_X69Y98 LUT1 (Prop_lut1_I0_O) 0.044 -0.115 f pll_clk.u_rst_mlkem/rdb_addr[11]_i_2/O net (fo=1066, routed) 0.158 0.043 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/msg_word_reg[7][31]_0 SLICE_X69Y99 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/w_state_reg[0]/CLR ------------------------------------------------------------------- ------------------- (clock mlkem_clk_clk_pll rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout3_buf/O net (fo=25775, routed) 0.922 -0.386 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/mlkem_clk SLICE_X69Y99 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/w_state_reg[0]/C clock pessimism 0.040 -0.346 SLICE_X69Y99 FDCE (Remov_fdce_C_CLR) -0.154 -0.500 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/w_state_reg[0] ------------------------------------------------------------------- required time 0.500 arrival time 0.043 ------------------------------------------------------------------- slack 0.543 Slack (MET) : 0.543ns (arrival time - required time) Source: pll_clk.u_rst_mlkem/delay_reg[1]/C (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/w_state_reg[2]/CLR (removal check against rising-edge clock mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (mlkem_clk_clk_pll rise@0.000ns - mlkem_clk_clk_pll rise@0.000ns) Data Path Delay: 0.725ns (logic 0.185ns (25.518%) route 0.540ns (74.482%)) Logic Levels: 1 (LUT1=1) Clock Path Skew: 0.336ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.386ns Source Clock Delay (SCD): -0.682ns Clock Pessimism Removal (CPR): -0.040ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock mlkem_clk_clk_pll rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout3_buf/O net (fo=25775, routed) 0.581 -0.682 pll_clk.u_rst_mlkem/mlkem_clk SLICE_X67Y102 FDCE r pll_clk.u_rst_mlkem/delay_reg[1]/C ------------------------------------------------------------------- ------------------- SLICE_X67Y102 FDCE (Prop_fdce_C_Q) 0.141 -0.541 r pll_clk.u_rst_mlkem/delay_reg[1]/Q net (fo=4, routed) 0.382 -0.159 pll_clk.u_rst_mlkem/Q[0] SLICE_X69Y98 LUT1 (Prop_lut1_I0_O) 0.044 -0.115 f pll_clk.u_rst_mlkem/rdb_addr[11]_i_2/O net (fo=1066, routed) 0.158 0.043 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/msg_word_reg[7][31]_0 SLICE_X69Y99 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/w_state_reg[2]/CLR ------------------------------------------------------------------- ------------------- (clock mlkem_clk_clk_pll rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout3_buf/O net (fo=25775, routed) 0.922 -0.386 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/mlkem_clk SLICE_X69Y99 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/w_state_reg[2]/C clock pessimism 0.040 -0.346 SLICE_X69Y99 FDCE (Remov_fdce_C_CLR) -0.154 -0.500 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/w_state_reg[2] ------------------------------------------------------------------- required time 0.500 arrival time 0.043 ------------------------------------------------------------------- slack 0.543 Slack (MET) : 0.568ns (arrival time - required time) Source: pll_clk.u_rst_mlkem/delay_reg[1]/C (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/s_axi_wready_reg/CLR (removal check against rising-edge clock mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (mlkem_clk_clk_pll rise@0.000ns - mlkem_clk_clk_pll rise@0.000ns) Data Path Delay: 0.774ns (logic 0.185ns (23.892%) route 0.589ns (76.108%)) Logic Levels: 1 (LUT1=1) Clock Path Skew: 0.335ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.387ns Source Clock Delay (SCD): -0.682ns Clock Pessimism Removal (CPR): -0.040ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock mlkem_clk_clk_pll rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout3_buf/O net (fo=25775, routed) 0.581 -0.682 pll_clk.u_rst_mlkem/mlkem_clk SLICE_X67Y102 FDCE r pll_clk.u_rst_mlkem/delay_reg[1]/C ------------------------------------------------------------------- ------------------- SLICE_X67Y102 FDCE (Prop_fdce_C_Q) 0.141 -0.541 r pll_clk.u_rst_mlkem/delay_reg[1]/Q net (fo=4, routed) 0.382 -0.159 pll_clk.u_rst_mlkem/Q[0] SLICE_X69Y98 LUT1 (Prop_lut1_I0_O) 0.044 -0.115 f pll_clk.u_rst_mlkem/rdb_addr[11]_i_2/O net (fo=1066, routed) 0.207 0.092 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/msg_word_reg[7][31]_0 SLICE_X72Y98 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/s_axi_wready_reg/CLR ------------------------------------------------------------------- ------------------- (clock mlkem_clk_clk_pll rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout3_buf/O net (fo=25775, routed) 0.921 -0.387 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/mlkem_clk SLICE_X72Y98 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/s_axi_wready_reg/C clock pessimism 0.040 -0.347 SLICE_X72Y98 FDCE (Remov_fdce_C_CLR) -0.129 -0.476 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/s_axi_wready_reg ------------------------------------------------------------------- required time 0.476 arrival time 0.092 ------------------------------------------------------------------- slack 0.568 Slack (MET) : 0.568ns (arrival time - required time) Source: pll_clk.u_rst_mlkem/delay_reg[1]/C (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/w_last_l_reg/CLR (removal check against rising-edge clock mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (mlkem_clk_clk_pll rise@0.000ns - mlkem_clk_clk_pll rise@0.000ns) Data Path Delay: 0.774ns (logic 0.185ns (23.892%) route 0.589ns (76.108%)) Logic Levels: 1 (LUT1=1) Clock Path Skew: 0.335ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.387ns Source Clock Delay (SCD): -0.682ns Clock Pessimism Removal (CPR): -0.040ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock mlkem_clk_clk_pll rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout3_buf/O net (fo=25775, routed) 0.581 -0.682 pll_clk.u_rst_mlkem/mlkem_clk SLICE_X67Y102 FDCE r pll_clk.u_rst_mlkem/delay_reg[1]/C ------------------------------------------------------------------- ------------------- SLICE_X67Y102 FDCE (Prop_fdce_C_Q) 0.141 -0.541 r pll_clk.u_rst_mlkem/delay_reg[1]/Q net (fo=4, routed) 0.382 -0.159 pll_clk.u_rst_mlkem/Q[0] SLICE_X69Y98 LUT1 (Prop_lut1_I0_O) 0.044 -0.115 f pll_clk.u_rst_mlkem/rdb_addr[11]_i_2/O net (fo=1066, routed) 0.207 0.092 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/msg_word_reg[7][31]_0 SLICE_X72Y98 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/w_last_l_reg/CLR ------------------------------------------------------------------- ------------------- (clock mlkem_clk_clk_pll rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout3_buf/O net (fo=25775, routed) 0.921 -0.387 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/mlkem_clk SLICE_X72Y98 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/w_last_l_reg/C clock pessimism 0.040 -0.347 SLICE_X72Y98 FDCE (Remov_fdce_C_CLR) -0.129 -0.476 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/w_last_l_reg ------------------------------------------------------------------- required time 0.476 arrival time 0.092 ------------------------------------------------------------------- slack 0.568 Slack (MET) : 0.591ns (arrival time - required time) Source: pll_clk.u_rst_mlkem/delay_reg[1]/C (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/w_state_reg[1]/CLR (removal check against rising-edge clock mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (mlkem_clk_clk_pll rise@0.000ns - mlkem_clk_clk_pll rise@0.000ns) Data Path Delay: 0.797ns (logic 0.185ns (23.221%) route 0.612ns (76.779%)) Logic Levels: 1 (LUT1=1) Clock Path Skew: 0.335ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.387ns Source Clock Delay (SCD): -0.682ns Clock Pessimism Removal (CPR): -0.040ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock mlkem_clk_clk_pll rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout3_buf/O net (fo=25775, routed) 0.581 -0.682 pll_clk.u_rst_mlkem/mlkem_clk SLICE_X67Y102 FDCE r pll_clk.u_rst_mlkem/delay_reg[1]/C ------------------------------------------------------------------- ------------------- SLICE_X67Y102 FDCE (Prop_fdce_C_Q) 0.141 -0.541 r pll_clk.u_rst_mlkem/delay_reg[1]/Q net (fo=4, routed) 0.382 -0.159 pll_clk.u_rst_mlkem/Q[0] SLICE_X69Y98 LUT1 (Prop_lut1_I0_O) 0.044 -0.115 f pll_clk.u_rst_mlkem/rdb_addr[11]_i_2/O net (fo=1066, routed) 0.230 0.115 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/msg_word_reg[7][31]_0 SLICE_X70Y98 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/w_state_reg[1]/CLR ------------------------------------------------------------------- ------------------- (clock mlkem_clk_clk_pll rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout3_buf/O net (fo=25775, routed) 0.921 -0.387 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/mlkem_clk SLICE_X70Y98 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/w_state_reg[1]/C clock pessimism 0.040 -0.347 SLICE_X70Y98 FDCE (Remov_fdce_C_CLR) -0.129 -0.476 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/w_state_reg[1] ------------------------------------------------------------------- required time 0.476 arrival time 0.115 ------------------------------------------------------------------- slack 0.591 Slack (MET) : 0.595ns (arrival time - required time) Source: pll_clk.u_rst_mlkem/delay_reg[1]/C (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/s_axi_awready_reg/PRE (removal check against rising-edge clock mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (mlkem_clk_clk_pll rise@0.000ns - mlkem_clk_clk_pll rise@0.000ns) Data Path Delay: 0.797ns (logic 0.185ns (23.221%) route 0.612ns (76.779%)) Logic Levels: 1 (LUT1=1) Clock Path Skew: 0.335ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.387ns Source Clock Delay (SCD): -0.682ns Clock Pessimism Removal (CPR): -0.040ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock mlkem_clk_clk_pll rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout3_buf/O net (fo=25775, routed) 0.581 -0.682 pll_clk.u_rst_mlkem/mlkem_clk SLICE_X67Y102 FDCE r pll_clk.u_rst_mlkem/delay_reg[1]/C ------------------------------------------------------------------- ------------------- SLICE_X67Y102 FDCE (Prop_fdce_C_Q) 0.141 -0.541 r pll_clk.u_rst_mlkem/delay_reg[1]/Q net (fo=4, routed) 0.382 -0.159 pll_clk.u_rst_mlkem/Q[0] SLICE_X69Y98 LUT1 (Prop_lut1_I0_O) 0.044 -0.115 f pll_clk.u_rst_mlkem/rdb_addr[11]_i_2/O net (fo=1066, routed) 0.230 0.115 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/msg_word_reg[7][31]_0 SLICE_X70Y98 FDPE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/s_axi_awready_reg/PRE ------------------------------------------------------------------- ------------------- (clock mlkem_clk_clk_pll rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout3_buf/O net (fo=25775, routed) 0.921 -0.387 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/mlkem_clk SLICE_X70Y98 FDPE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/s_axi_awready_reg/C clock pessimism 0.040 -0.347 SLICE_X70Y98 FDPE (Remov_fdpe_C_PRE) -0.133 -0.480 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/s_axi_awready_reg ------------------------------------------------------------------- required time 0.480 arrival time 0.115 ------------------------------------------------------------------- slack 0.595 Slack (MET) : 0.632ns (arrival time - required time) Source: pll_clk.u_rst_mlkem/delay_reg[1]/C (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/s_axi_bvalid_reg/CLR (removal check against rising-edge clock mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (mlkem_clk_clk_pll rise@0.000ns - mlkem_clk_clk_pll rise@0.000ns) Data Path Delay: 0.838ns (logic 0.185ns (22.085%) route 0.653ns (77.915%)) Logic Levels: 1 (LUT1=1) Clock Path Skew: 0.335ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.387ns Source Clock Delay (SCD): -0.682ns Clock Pessimism Removal (CPR): -0.040ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock mlkem_clk_clk_pll rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout3_buf/O net (fo=25775, routed) 0.581 -0.682 pll_clk.u_rst_mlkem/mlkem_clk SLICE_X67Y102 FDCE r pll_clk.u_rst_mlkem/delay_reg[1]/C ------------------------------------------------------------------- ------------------- SLICE_X67Y102 FDCE (Prop_fdce_C_Q) 0.141 -0.541 r pll_clk.u_rst_mlkem/delay_reg[1]/Q net (fo=4, routed) 0.382 -0.159 pll_clk.u_rst_mlkem/Q[0] SLICE_X69Y98 LUT1 (Prop_lut1_I0_O) 0.044 -0.115 f pll_clk.u_rst_mlkem/rdb_addr[11]_i_2/O net (fo=1066, routed) 0.271 0.156 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/msg_word_reg[7][31]_0 SLICE_X72Y99 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/s_axi_bvalid_reg/CLR ------------------------------------------------------------------- ------------------- (clock mlkem_clk_clk_pll rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout3_buf/O net (fo=25775, routed) 0.921 -0.387 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/mlkem_clk SLICE_X72Y99 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/s_axi_bvalid_reg/C clock pessimism 0.040 -0.347 SLICE_X72Y99 FDCE (Remov_fdce_C_CLR) -0.129 -0.476 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/s_axi_bvalid_reg ------------------------------------------------------------------- required time 0.476 arrival time 0.156 ------------------------------------------------------------------- slack 0.632 Slack (MET) : 0.793ns (arrival time - required time) Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/buffers_1_reg/C (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/popCC_ptrToPush_reg[0]/CLR (removal check against rising-edge clock mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (mlkem_clk_clk_pll rise@0.000ns - mlkem_clk_clk_pll rise@0.000ns) Data Path Delay: 0.717ns (logic 0.246ns (34.327%) route 0.471ns (65.673%)) Logic Levels: 1 (LUT1=1) Clock Path Skew: 0.016ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.388ns Source Clock Delay (SCD): -0.617ns Clock Pessimism Removal (CPR): 0.213ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock mlkem_clk_clk_pll rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout3_buf/O net (fo=25775, routed) 0.645 -0.617 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/mlkem_clk SLICE_X70Y96 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/buffers_1_reg/C ------------------------------------------------------------------- ------------------- SLICE_X70Y96 FDCE (Prop_fdce_C_Q) 0.148 -0.469 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/buffers_1_reg/Q net (fo=1, routed) 0.286 -0.183 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/buffers_1 SLICE_X70Y96 LUT1 (Prop_lut1_I0_O) 0.098 -0.085 f u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/popCC_popPtr[2]_i_2__1/O net (fo=43, routed) 0.184 0.099 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/buffers_1_reg SLICE_X73Y95 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/popCC_ptrToPush_reg[0]/CLR ------------------------------------------------------------------- ------------------- (clock mlkem_clk_clk_pll rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout3_buf/O net (fo=25775, routed) 0.920 -0.388 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/mlkem_clk SLICE_X73Y95 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/popCC_ptrToPush_reg[0]/C clock pessimism -0.213 -0.601 SLICE_X73Y95 FDCE (Remov_fdce_C_CLR) -0.092 -0.693 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/popCC_ptrToPush_reg[0] ------------------------------------------------------------------- required time 0.693 arrival time 0.099 ------------------------------------------------------------------- slack 0.793 Slack (MET) : 0.793ns (arrival time - required time) Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/buffers_1_reg/C (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/popCC_ptrToPush_reg[1]/CLR (removal check against rising-edge clock mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (mlkem_clk_clk_pll rise@0.000ns - mlkem_clk_clk_pll rise@0.000ns) Data Path Delay: 0.717ns (logic 0.246ns (34.327%) route 0.471ns (65.673%)) Logic Levels: 1 (LUT1=1) Clock Path Skew: 0.016ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.388ns Source Clock Delay (SCD): -0.617ns Clock Pessimism Removal (CPR): 0.213ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock mlkem_clk_clk_pll rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout3_buf/O net (fo=25775, routed) 0.645 -0.617 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/mlkem_clk SLICE_X70Y96 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/buffers_1_reg/C ------------------------------------------------------------------- ------------------- SLICE_X70Y96 FDCE (Prop_fdce_C_Q) 0.148 -0.469 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/buffers_1_reg/Q net (fo=1, routed) 0.286 -0.183 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/buffers_1 SLICE_X70Y96 LUT1 (Prop_lut1_I0_O) 0.098 -0.085 f u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/popCC_popPtr[2]_i_2__1/O net (fo=43, routed) 0.184 0.099 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/buffers_1_reg SLICE_X73Y95 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/popCC_ptrToPush_reg[1]/CLR ------------------------------------------------------------------- ------------------- (clock mlkem_clk_clk_pll rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout3_buf/O net (fo=25775, routed) 0.920 -0.388 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/mlkem_clk SLICE_X73Y95 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/popCC_ptrToPush_reg[1]/C clock pessimism -0.213 -0.601 SLICE_X73Y95 FDCE (Remov_fdce_C_CLR) -0.092 -0.693 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/popCC_ptrToPush_reg[1] ------------------------------------------------------------------- required time 0.693 arrival time 0.099 ------------------------------------------------------------------- slack 0.793 Slack (MET) : 0.793ns (arrival time - required time) Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/buffers_1_reg/C (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/popCC_ptrToPush_reg[2]/CLR (removal check against rising-edge clock mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (mlkem_clk_clk_pll rise@0.000ns - mlkem_clk_clk_pll rise@0.000ns) Data Path Delay: 0.717ns (logic 0.246ns (34.327%) route 0.471ns (65.673%)) Logic Levels: 1 (LUT1=1) Clock Path Skew: 0.016ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.388ns Source Clock Delay (SCD): -0.617ns Clock Pessimism Removal (CPR): 0.213ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock mlkem_clk_clk_pll rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout3_buf/O net (fo=25775, routed) 0.645 -0.617 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/mlkem_clk SLICE_X70Y96 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/buffers_1_reg/C ------------------------------------------------------------------- ------------------- SLICE_X70Y96 FDCE (Prop_fdce_C_Q) 0.148 -0.469 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/buffers_1_reg/Q net (fo=1, routed) 0.286 -0.183 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/buffers_1 SLICE_X70Y96 LUT1 (Prop_lut1_I0_O) 0.098 -0.085 f u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/popCC_popPtr[2]_i_2__1/O net (fo=43, routed) 0.184 0.099 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/buffers_1_reg SLICE_X73Y95 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/popCC_ptrToPush_reg[2]/CLR ------------------------------------------------------------------- ------------------- (clock mlkem_clk_clk_pll rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout3_buf/O net (fo=25775, routed) 0.920 -0.388 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/mlkem_clk SLICE_X73Y95 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/popCC_ptrToPush_reg[2]/C clock pessimism -0.213 -0.601 SLICE_X73Y95 FDCE (Remov_fdce_C_CLR) -0.092 -0.693 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/popCC_ptrToPush_reg[2] ------------------------------------------------------------------- required time 0.693 arrival time 0.099 ------------------------------------------------------------------- slack 0.793 Slack (MET) : 0.873ns (arrival time - required time) Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/buffers_1_reg/C (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/pushToPopGray_buffercc/buffers_0_reg[0]/CLR (removal check against rising-edge clock mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (mlkem_clk_clk_pll rise@0.000ns - mlkem_clk_clk_pll rise@0.000ns) Data Path Delay: 0.797ns (logic 0.246ns (30.872%) route 0.551ns (69.128%)) Logic Levels: 1 (LUT1=1) Clock Path Skew: 0.016ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.388ns Source Clock Delay (SCD): -0.617ns Clock Pessimism Removal (CPR): 0.213ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock mlkem_clk_clk_pll rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout3_buf/O net (fo=25775, routed) 0.645 -0.617 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/mlkem_clk SLICE_X70Y96 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/buffers_1_reg/C ------------------------------------------------------------------- ------------------- SLICE_X70Y96 FDCE (Prop_fdce_C_Q) 0.148 -0.469 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/buffers_1_reg/Q net (fo=1, routed) 0.286 -0.183 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/buffers_1 SLICE_X70Y96 LUT1 (Prop_lut1_I0_O) 0.098 -0.085 f u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/popCC_popPtr[2]_i_2__1/O net (fo=43, routed) 0.264 0.179 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/pushToPopGray_buffercc/buffers_0_reg[2]_1 SLICE_X73Y93 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/pushToPopGray_buffercc/buffers_0_reg[0]/CLR ------------------------------------------------------------------- ------------------- (clock mlkem_clk_clk_pll rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout3_buf/O net (fo=25775, routed) 0.920 -0.388 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/pushToPopGray_buffercc/mlkem_clk SLICE_X73Y93 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/pushToPopGray_buffercc/buffers_0_reg[0]/C clock pessimism -0.213 -0.601 SLICE_X73Y93 FDCE (Remov_fdce_C_CLR) -0.092 -0.693 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/pushToPopGray_buffercc/buffers_0_reg[0] ------------------------------------------------------------------- required time 0.693 arrival time 0.179 ------------------------------------------------------------------- slack 0.873 Slack (MET) : 0.873ns (arrival time - required time) Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/buffers_1_reg/C (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/pushToPopGray_buffercc/buffers_0_reg[1]/CLR (removal check against rising-edge clock mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (mlkem_clk_clk_pll rise@0.000ns - mlkem_clk_clk_pll rise@0.000ns) Data Path Delay: 0.797ns (logic 0.246ns (30.872%) route 0.551ns (69.128%)) Logic Levels: 1 (LUT1=1) Clock Path Skew: 0.016ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.388ns Source Clock Delay (SCD): -0.617ns Clock Pessimism Removal (CPR): 0.213ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock mlkem_clk_clk_pll rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout3_buf/O net (fo=25775, routed) 0.645 -0.617 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/mlkem_clk SLICE_X70Y96 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/buffers_1_reg/C ------------------------------------------------------------------- ------------------- SLICE_X70Y96 FDCE (Prop_fdce_C_Q) 0.148 -0.469 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/buffers_1_reg/Q net (fo=1, routed) 0.286 -0.183 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/buffers_1 SLICE_X70Y96 LUT1 (Prop_lut1_I0_O) 0.098 -0.085 f u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/popCC_popPtr[2]_i_2__1/O net (fo=43, routed) 0.264 0.179 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/pushToPopGray_buffercc/buffers_0_reg[2]_1 SLICE_X73Y93 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/pushToPopGray_buffercc/buffers_0_reg[1]/CLR ------------------------------------------------------------------- ------------------- (clock mlkem_clk_clk_pll rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout3_buf/O net (fo=25775, routed) 0.920 -0.388 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/pushToPopGray_buffercc/mlkem_clk SLICE_X73Y93 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/pushToPopGray_buffercc/buffers_0_reg[1]/C clock pessimism -0.213 -0.601 SLICE_X73Y93 FDCE (Remov_fdce_C_CLR) -0.092 -0.693 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/pushToPopGray_buffercc/buffers_0_reg[1] ------------------------------------------------------------------- required time 0.693 arrival time 0.179 ------------------------------------------------------------------- slack 0.873 Slack (MET) : 0.873ns (arrival time - required time) Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/buffers_1_reg/C (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/pushToPopGray_buffercc/buffers_0_reg[2]/CLR (removal check against rising-edge clock mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (mlkem_clk_clk_pll rise@0.000ns - mlkem_clk_clk_pll rise@0.000ns) Data Path Delay: 0.797ns (logic 0.246ns (30.872%) route 0.551ns (69.128%)) Logic Levels: 1 (LUT1=1) Clock Path Skew: 0.016ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.388ns Source Clock Delay (SCD): -0.617ns Clock Pessimism Removal (CPR): 0.213ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock mlkem_clk_clk_pll rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout3_buf/O net (fo=25775, routed) 0.645 -0.617 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/mlkem_clk SLICE_X70Y96 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/buffers_1_reg/C ------------------------------------------------------------------- ------------------- SLICE_X70Y96 FDCE (Prop_fdce_C_Q) 0.148 -0.469 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/buffers_1_reg/Q net (fo=1, routed) 0.286 -0.183 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/buffers_1 SLICE_X70Y96 LUT1 (Prop_lut1_I0_O) 0.098 -0.085 f u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/popCC_popPtr[2]_i_2__1/O net (fo=43, routed) 0.264 0.179 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/pushToPopGray_buffercc/buffers_0_reg[2]_1 SLICE_X73Y93 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/pushToPopGray_buffercc/buffers_0_reg[2]/CLR ------------------------------------------------------------------- ------------------- (clock mlkem_clk_clk_pll rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout3_buf/O net (fo=25775, routed) 0.920 -0.388 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/pushToPopGray_buffercc/mlkem_clk SLICE_X73Y93 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/pushToPopGray_buffercc/buffers_0_reg[2]/C clock pessimism -0.213 -0.601 SLICE_X73Y93 FDCE (Remov_fdce_C_CLR) -0.092 -0.693 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/pushToPopGray_buffercc/buffers_0_reg[2] ------------------------------------------------------------------- required time 0.693 arrival time 0.179 ------------------------------------------------------------------- slack 0.873 Slack (MET) : 0.873ns (arrival time - required time) Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/buffers_1_reg/C (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/pushToPopGray_buffercc/buffers_1_reg[0]/CLR (removal check against rising-edge clock mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (mlkem_clk_clk_pll rise@0.000ns - mlkem_clk_clk_pll rise@0.000ns) Data Path Delay: 0.797ns (logic 0.246ns (30.872%) route 0.551ns (69.128%)) Logic Levels: 1 (LUT1=1) Clock Path Skew: 0.016ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.388ns Source Clock Delay (SCD): -0.617ns Clock Pessimism Removal (CPR): 0.213ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock mlkem_clk_clk_pll rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout3_buf/O net (fo=25775, routed) 0.645 -0.617 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/mlkem_clk SLICE_X70Y96 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/buffers_1_reg/C ------------------------------------------------------------------- ------------------- SLICE_X70Y96 FDCE (Prop_fdce_C_Q) 0.148 -0.469 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/buffers_1_reg/Q net (fo=1, routed) 0.286 -0.183 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/buffers_1 SLICE_X70Y96 LUT1 (Prop_lut1_I0_O) 0.098 -0.085 f u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/popCC_popPtr[2]_i_2__1/O net (fo=43, routed) 0.264 0.179 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/pushToPopGray_buffercc/buffers_0_reg[2]_1 SLICE_X73Y93 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/pushToPopGray_buffercc/buffers_1_reg[0]/CLR ------------------------------------------------------------------- ------------------- (clock mlkem_clk_clk_pll rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout3_buf/O net (fo=25775, routed) 0.920 -0.388 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/pushToPopGray_buffercc/mlkem_clk SLICE_X73Y93 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/pushToPopGray_buffercc/buffers_1_reg[0]/C clock pessimism -0.213 -0.601 SLICE_X73Y93 FDCE (Remov_fdce_C_CLR) -0.092 -0.693 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/pushToPopGray_buffercc/buffers_1_reg[0] ------------------------------------------------------------------- required time 0.693 arrival time 0.179 ------------------------------------------------------------------- slack 0.873 Slack (MET) : 0.873ns (arrival time - required time) Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/buffers_1_reg/C (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/pushToPopGray_buffercc/buffers_1_reg[1]/CLR (removal check against rising-edge clock mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (mlkem_clk_clk_pll rise@0.000ns - mlkem_clk_clk_pll rise@0.000ns) Data Path Delay: 0.797ns (logic 0.246ns (30.872%) route 0.551ns (69.128%)) Logic Levels: 1 (LUT1=1) Clock Path Skew: 0.016ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.388ns Source Clock Delay (SCD): -0.617ns Clock Pessimism Removal (CPR): 0.213ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock mlkem_clk_clk_pll rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout3_buf/O net (fo=25775, routed) 0.645 -0.617 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/mlkem_clk SLICE_X70Y96 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/buffers_1_reg/C ------------------------------------------------------------------- ------------------- SLICE_X70Y96 FDCE (Prop_fdce_C_Q) 0.148 -0.469 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/buffers_1_reg/Q net (fo=1, routed) 0.286 -0.183 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/buffers_1 SLICE_X70Y96 LUT1 (Prop_lut1_I0_O) 0.098 -0.085 f u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/popCC_popPtr[2]_i_2__1/O net (fo=43, routed) 0.264 0.179 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/pushToPopGray_buffercc/buffers_0_reg[2]_1 SLICE_X73Y93 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/pushToPopGray_buffercc/buffers_1_reg[1]/CLR ------------------------------------------------------------------- ------------------- (clock mlkem_clk_clk_pll rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout3_buf/O net (fo=25775, routed) 0.920 -0.388 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/pushToPopGray_buffercc/mlkem_clk SLICE_X73Y93 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/pushToPopGray_buffercc/buffers_1_reg[1]/C clock pessimism -0.213 -0.601 SLICE_X73Y93 FDCE (Remov_fdce_C_CLR) -0.092 -0.693 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/pushToPopGray_buffercc/buffers_1_reg[1] ------------------------------------------------------------------- required time 0.693 arrival time 0.179 ------------------------------------------------------------------- slack 0.873 Slack (MET) : 0.873ns (arrival time - required time) Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/buffers_1_reg/C (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/pushToPopGray_buffercc/buffers_1_reg[2]/CLR (removal check against rising-edge clock mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (mlkem_clk_clk_pll rise@0.000ns - mlkem_clk_clk_pll rise@0.000ns) Data Path Delay: 0.797ns (logic 0.246ns (30.872%) route 0.551ns (69.128%)) Logic Levels: 1 (LUT1=1) Clock Path Skew: 0.016ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.388ns Source Clock Delay (SCD): -0.617ns Clock Pessimism Removal (CPR): 0.213ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock mlkem_clk_clk_pll rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout3_buf/O net (fo=25775, routed) 0.645 -0.617 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/mlkem_clk SLICE_X70Y96 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/buffers_1_reg/C ------------------------------------------------------------------- ------------------- SLICE_X70Y96 FDCE (Prop_fdce_C_Q) 0.148 -0.469 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/buffers_1_reg/Q net (fo=1, routed) 0.286 -0.183 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/buffers_1 SLICE_X70Y96 LUT1 (Prop_lut1_I0_O) 0.098 -0.085 f u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/popCC_popPtr[2]_i_2__1/O net (fo=43, routed) 0.264 0.179 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/pushToPopGray_buffercc/buffers_0_reg[2]_1 SLICE_X73Y93 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/pushToPopGray_buffercc/buffers_1_reg[2]/CLR ------------------------------------------------------------------- ------------------- (clock mlkem_clk_clk_pll rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout3_buf/O net (fo=25775, routed) 0.920 -0.388 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/pushToPopGray_buffercc/mlkem_clk SLICE_X73Y93 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/pushToPopGray_buffercc/buffers_1_reg[2]/C clock pessimism -0.213 -0.601 SLICE_X73Y93 FDCE (Remov_fdce_C_CLR) -0.092 -0.693 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/pushToPopGray_buffercc/buffers_1_reg[2] ------------------------------------------------------------------- required time 0.693 arrival time 0.179 ------------------------------------------------------------------- slack 0.873 Slack (MET) : 0.873ns (arrival time - required time) Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/buffers_1_reg/C (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/popCC_popPtr_reg[0]/CLR (removal check against rising-edge clock mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (mlkem_clk_clk_pll rise@0.000ns - mlkem_clk_clk_pll rise@0.000ns) Data Path Delay: 0.794ns (logic 0.246ns (30.970%) route 0.548ns (69.030%)) Logic Levels: 1 (LUT1=1) Clock Path Skew: 0.013ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.388ns Source Clock Delay (SCD): -0.617ns Clock Pessimism Removal (CPR): 0.216ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock mlkem_clk_clk_pll rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout3_buf/O net (fo=25775, routed) 0.645 -0.617 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/mlkem_clk SLICE_X70Y96 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/buffers_1_reg/C ------------------------------------------------------------------- ------------------- SLICE_X70Y96 FDCE (Prop_fdce_C_Q) 0.148 -0.469 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/buffers_1_reg/Q net (fo=1, routed) 0.286 -0.183 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/buffers_1 SLICE_X70Y96 LUT1 (Prop_lut1_I0_O) 0.098 -0.085 f u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/popCC_popPtr[2]_i_2__1/O net (fo=43, routed) 0.262 0.177 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/buffers_0_reg[3] SLICE_X71Y96 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/popCC_popPtr_reg[0]/CLR ------------------------------------------------------------------- ------------------- (clock mlkem_clk_clk_pll rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout3_buf/O net (fo=25775, routed) 0.920 -0.388 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/mlkem_clk SLICE_X71Y96 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/popCC_popPtr_reg[0]/C clock pessimism -0.216 -0.604 SLICE_X71Y96 FDCE (Remov_fdce_C_CLR) -0.092 -0.696 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/popCC_popPtr_reg[0] ------------------------------------------------------------------- required time 0.696 arrival time 0.177 ------------------------------------------------------------------- slack 0.873 Slack (MET) : 0.873ns (arrival time - required time) Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/buffers_1_reg/C (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/popCC_popPtr_reg[1]/CLR (removal check against rising-edge clock mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (mlkem_clk_clk_pll rise@0.000ns - mlkem_clk_clk_pll rise@0.000ns) Data Path Delay: 0.794ns (logic 0.246ns (30.970%) route 0.548ns (69.030%)) Logic Levels: 1 (LUT1=1) Clock Path Skew: 0.013ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.388ns Source Clock Delay (SCD): -0.617ns Clock Pessimism Removal (CPR): 0.216ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock mlkem_clk_clk_pll rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout3_buf/O net (fo=25775, routed) 0.645 -0.617 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/mlkem_clk SLICE_X70Y96 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/buffers_1_reg/C ------------------------------------------------------------------- ------------------- SLICE_X70Y96 FDCE (Prop_fdce_C_Q) 0.148 -0.469 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/buffers_1_reg/Q net (fo=1, routed) 0.286 -0.183 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/buffers_1 SLICE_X70Y96 LUT1 (Prop_lut1_I0_O) 0.098 -0.085 f u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/popCC_popPtr[2]_i_2__1/O net (fo=43, routed) 0.262 0.177 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/buffers_0_reg[3] SLICE_X71Y96 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/popCC_popPtr_reg[1]/CLR ------------------------------------------------------------------- ------------------- (clock mlkem_clk_clk_pll rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout3_buf/O net (fo=25775, routed) 0.920 -0.388 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/mlkem_clk SLICE_X71Y96 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/popCC_popPtr_reg[1]/C clock pessimism -0.216 -0.604 SLICE_X71Y96 FDCE (Remov_fdce_C_CLR) -0.092 -0.696 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/popCC_popPtr_reg[1] ------------------------------------------------------------------- required time 0.696 arrival time 0.177 ------------------------------------------------------------------- slack 0.873 Slack (MET) : 0.873ns (arrival time - required time) Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/buffers_1_reg/C (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/popCC_popPtr_reg[2]/CLR (removal check against rising-edge clock mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (mlkem_clk_clk_pll rise@0.000ns - mlkem_clk_clk_pll rise@0.000ns) Data Path Delay: 0.794ns (logic 0.246ns (30.970%) route 0.548ns (69.030%)) Logic Levels: 1 (LUT1=1) Clock Path Skew: 0.013ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.388ns Source Clock Delay (SCD): -0.617ns Clock Pessimism Removal (CPR): 0.216ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock mlkem_clk_clk_pll rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout3_buf/O net (fo=25775, routed) 0.645 -0.617 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/mlkem_clk SLICE_X70Y96 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/buffers_1_reg/C ------------------------------------------------------------------- ------------------- SLICE_X70Y96 FDCE (Prop_fdce_C_Q) 0.148 -0.469 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/buffers_1_reg/Q net (fo=1, routed) 0.286 -0.183 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/buffers_1 SLICE_X70Y96 LUT1 (Prop_lut1_I0_O) 0.098 -0.085 f u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/popCC_popPtr[2]_i_2__1/O net (fo=43, routed) 0.262 0.177 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/buffers_0_reg[3] SLICE_X71Y96 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/popCC_popPtr_reg[2]/CLR ------------------------------------------------------------------- ------------------- (clock mlkem_clk_clk_pll rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout3_buf/O net (fo=25775, routed) 0.920 -0.388 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/mlkem_clk SLICE_X71Y96 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/popCC_popPtr_reg[2]/C clock pessimism -0.216 -0.604 SLICE_X71Y96 FDCE (Remov_fdce_C_CLR) -0.092 -0.696 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/popCC_popPtr_reg[2] ------------------------------------------------------------------- required time 0.696 arrival time 0.177 ------------------------------------------------------------------- slack 0.873 Slack (MET) : 0.873ns (arrival time - required time) Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/buffers_1_reg/C (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/popCC_popPtr_reg[3]/CLR (removal check against rising-edge clock mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (mlkem_clk_clk_pll rise@0.000ns - mlkem_clk_clk_pll rise@0.000ns) Data Path Delay: 0.794ns (logic 0.246ns (30.970%) route 0.548ns (69.030%)) Logic Levels: 1 (LUT1=1) Clock Path Skew: 0.013ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.388ns Source Clock Delay (SCD): -0.617ns Clock Pessimism Removal (CPR): 0.216ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock mlkem_clk_clk_pll rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout3_buf/O net (fo=25775, routed) 0.645 -0.617 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/mlkem_clk SLICE_X70Y96 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/buffers_1_reg/C ------------------------------------------------------------------- ------------------- SLICE_X70Y96 FDCE (Prop_fdce_C_Q) 0.148 -0.469 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/buffers_1_reg/Q net (fo=1, routed) 0.286 -0.183 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/buffers_1 SLICE_X70Y96 LUT1 (Prop_lut1_I0_O) 0.098 -0.085 f u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/popCC_popPtr[2]_i_2__1/O net (fo=43, routed) 0.262 0.177 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/buffers_0_reg[3] SLICE_X71Y96 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/popCC_popPtr_reg[3]/CLR ------------------------------------------------------------------- ------------------- (clock mlkem_clk_clk_pll rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout3_buf/O net (fo=25775, routed) 0.920 -0.388 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/mlkem_clk SLICE_X71Y96 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/popCC_popPtr_reg[3]/C clock pessimism -0.216 -0.604 SLICE_X71Y96 FDCE (Remov_fdce_C_CLR) -0.092 -0.696 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/popCC_popPtr_reg[3] ------------------------------------------------------------------- required time 0.696 arrival time 0.177 ------------------------------------------------------------------- slack 0.873 Slack (MET) : 0.905ns (arrival time - required time) Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/buffers_1_reg/C (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/popCC_addressGen_rValid_reg/CLR (removal check against rising-edge clock mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (mlkem_clk_clk_pll rise@0.000ns - mlkem_clk_clk_pll rise@0.000ns) Data Path Delay: 0.828ns (logic 0.246ns (29.723%) route 0.582ns (70.277%)) Logic Levels: 1 (LUT1=1) Clock Path Skew: 0.015ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.389ns Source Clock Delay (SCD): -0.617ns Clock Pessimism Removal (CPR): 0.213ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock mlkem_clk_clk_pll rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout3_buf/O net (fo=25775, routed) 0.645 -0.617 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/mlkem_clk SLICE_X70Y96 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/buffers_1_reg/C ------------------------------------------------------------------- ------------------- SLICE_X70Y96 FDCE (Prop_fdce_C_Q) 0.148 -0.469 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/buffers_1_reg/Q net (fo=1, routed) 0.286 -0.183 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/buffers_1 SLICE_X70Y96 LUT1 (Prop_lut1_I0_O) 0.098 -0.085 f u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/popCC_popPtr[2]_i_2__1/O net (fo=43, routed) 0.295 0.210 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/buffers_0_reg[2] SLICE_X71Y92 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/popCC_addressGen_rValid_reg/CLR ------------------------------------------------------------------- ------------------- (clock mlkem_clk_clk_pll rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout3_buf/O net (fo=25775, routed) 0.919 -0.389 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/mlkem_clk SLICE_X71Y92 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/popCC_addressGen_rValid_reg/C clock pessimism -0.213 -0.602 SLICE_X71Y92 FDCE (Remov_fdce_C_CLR) -0.092 -0.694 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/popCC_addressGen_rValid_reg ------------------------------------------------------------------- required time 0.694 arrival time 0.210 ------------------------------------------------------------------- slack 0.905 Slack (MET) : 0.905ns (arrival time - required time) Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/buffers_1_reg/C (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/popCC_popPtr_reg[1]/CLR (removal check against rising-edge clock mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (mlkem_clk_clk_pll rise@0.000ns - mlkem_clk_clk_pll rise@0.000ns) Data Path Delay: 0.828ns (logic 0.246ns (29.723%) route 0.582ns (70.277%)) Logic Levels: 1 (LUT1=1) Clock Path Skew: 0.015ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.389ns Source Clock Delay (SCD): -0.617ns Clock Pessimism Removal (CPR): 0.213ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock mlkem_clk_clk_pll rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout3_buf/O net (fo=25775, routed) 0.645 -0.617 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/mlkem_clk SLICE_X70Y96 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/buffers_1_reg/C ------------------------------------------------------------------- ------------------- SLICE_X70Y96 FDCE (Prop_fdce_C_Q) 0.148 -0.469 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/buffers_1_reg/Q net (fo=1, routed) 0.286 -0.183 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/buffers_1 SLICE_X70Y96 LUT1 (Prop_lut1_I0_O) 0.098 -0.085 f u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/popCC_popPtr[2]_i_2__1/O net (fo=43, routed) 0.295 0.210 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/buffers_0_reg[2] SLICE_X71Y92 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/popCC_popPtr_reg[1]/CLR ------------------------------------------------------------------- ------------------- (clock mlkem_clk_clk_pll rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout3_buf/O net (fo=25775, routed) 0.919 -0.389 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/mlkem_clk SLICE_X71Y92 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/popCC_popPtr_reg[1]/C clock pessimism -0.213 -0.602 SLICE_X71Y92 FDCE (Remov_fdce_C_CLR) -0.092 -0.694 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/popCC_popPtr_reg[1] ------------------------------------------------------------------- required time 0.694 arrival time 0.210 ------------------------------------------------------------------- slack 0.905 Slack (MET) : 0.905ns (arrival time - required time) Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/buffers_1_reg/C (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/popCC_popPtr_reg[2]/CLR (removal check against rising-edge clock mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (mlkem_clk_clk_pll rise@0.000ns - mlkem_clk_clk_pll rise@0.000ns) Data Path Delay: 0.828ns (logic 0.246ns (29.723%) route 0.582ns (70.277%)) Logic Levels: 1 (LUT1=1) Clock Path Skew: 0.015ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.389ns Source Clock Delay (SCD): -0.617ns Clock Pessimism Removal (CPR): 0.213ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock mlkem_clk_clk_pll rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout3_buf/O net (fo=25775, routed) 0.645 -0.617 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/mlkem_clk SLICE_X70Y96 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/buffers_1_reg/C ------------------------------------------------------------------- ------------------- SLICE_X70Y96 FDCE (Prop_fdce_C_Q) 0.148 -0.469 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/buffers_1_reg/Q net (fo=1, routed) 0.286 -0.183 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/buffers_1 SLICE_X70Y96 LUT1 (Prop_lut1_I0_O) 0.098 -0.085 f u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/popCC_popPtr[2]_i_2__1/O net (fo=43, routed) 0.295 0.210 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/buffers_0_reg[2] SLICE_X71Y92 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/popCC_popPtr_reg[2]/CLR ------------------------------------------------------------------- ------------------- (clock mlkem_clk_clk_pll rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout3_buf/O net (fo=25775, routed) 0.919 -0.389 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/mlkem_clk SLICE_X71Y92 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/popCC_popPtr_reg[2]/C clock pessimism -0.213 -0.602 SLICE_X71Y92 FDCE (Remov_fdce_C_CLR) -0.092 -0.694 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/popCC_popPtr_reg[2] ------------------------------------------------------------------- required time 0.694 arrival time 0.210 ------------------------------------------------------------------- slack 0.905 Slack (MET) : 0.905ns (arrival time - required time) Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/buffers_1_reg/C (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/popCC_ptrToPush_reg[2]/CLR (removal check against rising-edge clock mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (mlkem_clk_clk_pll rise@0.000ns - mlkem_clk_clk_pll rise@0.000ns) Data Path Delay: 0.828ns (logic 0.246ns (29.723%) route 0.582ns (70.277%)) Logic Levels: 1 (LUT1=1) Clock Path Skew: 0.015ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.389ns Source Clock Delay (SCD): -0.617ns Clock Pessimism Removal (CPR): 0.213ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock mlkem_clk_clk_pll rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout3_buf/O net (fo=25775, routed) 0.645 -0.617 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/mlkem_clk SLICE_X70Y96 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/buffers_1_reg/C ------------------------------------------------------------------- ------------------- SLICE_X70Y96 FDCE (Prop_fdce_C_Q) 0.148 -0.469 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/buffers_1_reg/Q net (fo=1, routed) 0.286 -0.183 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/buffers_1 SLICE_X70Y96 LUT1 (Prop_lut1_I0_O) 0.098 -0.085 f u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/popCC_popPtr[2]_i_2__1/O net (fo=43, routed) 0.295 0.210 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/buffers_0_reg[2] SLICE_X71Y92 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/popCC_ptrToPush_reg[2]/CLR ------------------------------------------------------------------- ------------------- (clock mlkem_clk_clk_pll rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout3_buf/O net (fo=25775, routed) 0.919 -0.389 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/mlkem_clk SLICE_X71Y92 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/popCC_ptrToPush_reg[2]/C clock pessimism -0.213 -0.602 SLICE_X71Y92 FDCE (Remov_fdce_C_CLR) -0.092 -0.694 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/popCC_ptrToPush_reg[2] ------------------------------------------------------------------- required time 0.694 arrival time 0.210 ------------------------------------------------------------------- slack 0.905 Slack (MET) : 0.913ns (arrival time - required time) Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/buffers_1_reg/C (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/pushToPopGray_buffercc/buffers_0_reg[0]/CLR (removal check against rising-edge clock mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (mlkem_clk_clk_pll rise@0.000ns - mlkem_clk_clk_pll rise@0.000ns) Data Path Delay: 0.837ns (logic 0.246ns (29.384%) route 0.591ns (70.616%)) Logic Levels: 1 (LUT1=1) Clock Path Skew: 0.016ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.388ns Source Clock Delay (SCD): -0.617ns Clock Pessimism Removal (CPR): 0.213ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock mlkem_clk_clk_pll rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout3_buf/O net (fo=25775, routed) 0.645 -0.617 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/mlkem_clk SLICE_X70Y96 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/buffers_1_reg/C ------------------------------------------------------------------- ------------------- SLICE_X70Y96 FDCE (Prop_fdce_C_Q) 0.148 -0.469 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/buffers_1_reg/Q net (fo=1, routed) 0.286 -0.183 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/buffers_1 SLICE_X70Y96 LUT1 (Prop_lut1_I0_O) 0.098 -0.085 f u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/popCC_popPtr[2]_i_2__1/O net (fo=43, routed) 0.305 0.220 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/pushToPopGray_buffercc/buffers_0_reg[3]_0 SLICE_X71Y95 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/pushToPopGray_buffercc/buffers_0_reg[0]/CLR ------------------------------------------------------------------- ------------------- (clock mlkem_clk_clk_pll rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout3_buf/O net (fo=25775, routed) 0.920 -0.388 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/pushToPopGray_buffercc/mlkem_clk SLICE_X71Y95 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/pushToPopGray_buffercc/buffers_0_reg[0]/C clock pessimism -0.213 -0.601 SLICE_X71Y95 FDCE (Remov_fdce_C_CLR) -0.092 -0.693 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/pushToPopGray_buffercc/buffers_0_reg[0] ------------------------------------------------------------------- required time 0.693 arrival time 0.220 ------------------------------------------------------------------- slack 0.913 Slack (MET) : 0.913ns (arrival time - required time) Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/buffers_1_reg/C (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/pushToPopGray_buffercc/buffers_0_reg[1]/CLR (removal check against rising-edge clock mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (mlkem_clk_clk_pll rise@0.000ns - mlkem_clk_clk_pll rise@0.000ns) Data Path Delay: 0.837ns (logic 0.246ns (29.384%) route 0.591ns (70.616%)) Logic Levels: 1 (LUT1=1) Clock Path Skew: 0.016ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.388ns Source Clock Delay (SCD): -0.617ns Clock Pessimism Removal (CPR): 0.213ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock mlkem_clk_clk_pll rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout3_buf/O net (fo=25775, routed) 0.645 -0.617 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/mlkem_clk SLICE_X70Y96 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/buffers_1_reg/C ------------------------------------------------------------------- ------------------- SLICE_X70Y96 FDCE (Prop_fdce_C_Q) 0.148 -0.469 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/buffers_1_reg/Q net (fo=1, routed) 0.286 -0.183 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/buffers_1 SLICE_X70Y96 LUT1 (Prop_lut1_I0_O) 0.098 -0.085 f u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/popCC_popPtr[2]_i_2__1/O net (fo=43, routed) 0.305 0.220 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/pushToPopGray_buffercc/buffers_0_reg[3]_0 SLICE_X71Y95 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/pushToPopGray_buffercc/buffers_0_reg[1]/CLR ------------------------------------------------------------------- ------------------- (clock mlkem_clk_clk_pll rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout3_buf/O net (fo=25775, routed) 0.920 -0.388 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/pushToPopGray_buffercc/mlkem_clk SLICE_X71Y95 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/pushToPopGray_buffercc/buffers_0_reg[1]/C clock pessimism -0.213 -0.601 SLICE_X71Y95 FDCE (Remov_fdce_C_CLR) -0.092 -0.693 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/pushToPopGray_buffercc/buffers_0_reg[1] ------------------------------------------------------------------- required time 0.693 arrival time 0.220 ------------------------------------------------------------------- slack 0.913 Slack (MET) : 0.913ns (arrival time - required time) Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/buffers_1_reg/C (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/pushToPopGray_buffercc/buffers_0_reg[2]/CLR (removal check against rising-edge clock mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (mlkem_clk_clk_pll rise@0.000ns - mlkem_clk_clk_pll rise@0.000ns) Data Path Delay: 0.837ns (logic 0.246ns (29.384%) route 0.591ns (70.616%)) Logic Levels: 1 (LUT1=1) Clock Path Skew: 0.016ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.388ns Source Clock Delay (SCD): -0.617ns Clock Pessimism Removal (CPR): 0.213ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock mlkem_clk_clk_pll rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout3_buf/O net (fo=25775, routed) 0.645 -0.617 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/mlkem_clk SLICE_X70Y96 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/buffers_1_reg/C ------------------------------------------------------------------- ------------------- SLICE_X70Y96 FDCE (Prop_fdce_C_Q) 0.148 -0.469 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/buffers_1_reg/Q net (fo=1, routed) 0.286 -0.183 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/buffers_1 SLICE_X70Y96 LUT1 (Prop_lut1_I0_O) 0.098 -0.085 f u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/popCC_popPtr[2]_i_2__1/O net (fo=43, routed) 0.305 0.220 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/pushToPopGray_buffercc/buffers_0_reg[3]_0 SLICE_X71Y95 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/pushToPopGray_buffercc/buffers_0_reg[2]/CLR ------------------------------------------------------------------- ------------------- (clock mlkem_clk_clk_pll rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout3_buf/O net (fo=25775, routed) 0.920 -0.388 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/pushToPopGray_buffercc/mlkem_clk SLICE_X71Y95 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/pushToPopGray_buffercc/buffers_0_reg[2]/C clock pessimism -0.213 -0.601 SLICE_X71Y95 FDCE (Remov_fdce_C_CLR) -0.092 -0.693 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/pushToPopGray_buffercc/buffers_0_reg[2] ------------------------------------------------------------------- required time 0.693 arrival time 0.220 ------------------------------------------------------------------- slack 0.913 Slack (MET) : 0.913ns (arrival time - required time) Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/buffers_1_reg/C (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/pushToPopGray_buffercc/buffers_1_reg[0]/CLR (removal check against rising-edge clock mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (mlkem_clk_clk_pll rise@0.000ns - mlkem_clk_clk_pll rise@0.000ns) Data Path Delay: 0.837ns (logic 0.246ns (29.384%) route 0.591ns (70.616%)) Logic Levels: 1 (LUT1=1) Clock Path Skew: 0.016ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.388ns Source Clock Delay (SCD): -0.617ns Clock Pessimism Removal (CPR): 0.213ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock mlkem_clk_clk_pll rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout3_buf/O net (fo=25775, routed) 0.645 -0.617 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/mlkem_clk SLICE_X70Y96 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/buffers_1_reg/C ------------------------------------------------------------------- ------------------- SLICE_X70Y96 FDCE (Prop_fdce_C_Q) 0.148 -0.469 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/buffers_1_reg/Q net (fo=1, routed) 0.286 -0.183 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/buffers_1 SLICE_X70Y96 LUT1 (Prop_lut1_I0_O) 0.098 -0.085 f u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/popCC_popPtr[2]_i_2__1/O net (fo=43, routed) 0.305 0.220 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/pushToPopGray_buffercc/buffers_0_reg[3]_0 SLICE_X71Y95 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/pushToPopGray_buffercc/buffers_1_reg[0]/CLR ------------------------------------------------------------------- ------------------- (clock mlkem_clk_clk_pll rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout3_buf/O net (fo=25775, routed) 0.920 -0.388 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/pushToPopGray_buffercc/mlkem_clk SLICE_X71Y95 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/pushToPopGray_buffercc/buffers_1_reg[0]/C clock pessimism -0.213 -0.601 SLICE_X71Y95 FDCE (Remov_fdce_C_CLR) -0.092 -0.693 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/pushToPopGray_buffercc/buffers_1_reg[0] ------------------------------------------------------------------- required time 0.693 arrival time 0.220 ------------------------------------------------------------------- slack 0.913 Slack (MET) : 0.913ns (arrival time - required time) Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/buffers_1_reg/C (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/pushToPopGray_buffercc/buffers_1_reg[1]/CLR (removal check against rising-edge clock mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (mlkem_clk_clk_pll rise@0.000ns - mlkem_clk_clk_pll rise@0.000ns) Data Path Delay: 0.837ns (logic 0.246ns (29.384%) route 0.591ns (70.616%)) Logic Levels: 1 (LUT1=1) Clock Path Skew: 0.016ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.388ns Source Clock Delay (SCD): -0.617ns Clock Pessimism Removal (CPR): 0.213ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock mlkem_clk_clk_pll rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout3_buf/O net (fo=25775, routed) 0.645 -0.617 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/mlkem_clk SLICE_X70Y96 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/buffers_1_reg/C ------------------------------------------------------------------- ------------------- SLICE_X70Y96 FDCE (Prop_fdce_C_Q) 0.148 -0.469 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/buffers_1_reg/Q net (fo=1, routed) 0.286 -0.183 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/buffers_1 SLICE_X70Y96 LUT1 (Prop_lut1_I0_O) 0.098 -0.085 f u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/popCC_popPtr[2]_i_2__1/O net (fo=43, routed) 0.305 0.220 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/pushToPopGray_buffercc/buffers_0_reg[3]_0 SLICE_X71Y95 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/pushToPopGray_buffercc/buffers_1_reg[1]/CLR ------------------------------------------------------------------- ------------------- (clock mlkem_clk_clk_pll rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout3_buf/O net (fo=25775, routed) 0.920 -0.388 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/pushToPopGray_buffercc/mlkem_clk SLICE_X71Y95 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/pushToPopGray_buffercc/buffers_1_reg[1]/C clock pessimism -0.213 -0.601 SLICE_X71Y95 FDCE (Remov_fdce_C_CLR) -0.092 -0.693 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/pushToPopGray_buffercc/buffers_1_reg[1] ------------------------------------------------------------------- required time 0.693 arrival time 0.220 ------------------------------------------------------------------- slack 0.913 Slack (MET) : 0.913ns (arrival time - required time) Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/buffers_1_reg/C (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/pushToPopGray_buffercc/buffers_1_reg[2]/CLR (removal check against rising-edge clock mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (mlkem_clk_clk_pll rise@0.000ns - mlkem_clk_clk_pll rise@0.000ns) Data Path Delay: 0.837ns (logic 0.246ns (29.384%) route 0.591ns (70.616%)) Logic Levels: 1 (LUT1=1) Clock Path Skew: 0.016ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.388ns Source Clock Delay (SCD): -0.617ns Clock Pessimism Removal (CPR): 0.213ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock mlkem_clk_clk_pll rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout3_buf/O net (fo=25775, routed) 0.645 -0.617 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/mlkem_clk SLICE_X70Y96 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/buffers_1_reg/C ------------------------------------------------------------------- ------------------- SLICE_X70Y96 FDCE (Prop_fdce_C_Q) 0.148 -0.469 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/buffers_1_reg/Q net (fo=1, routed) 0.286 -0.183 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/buffers_1 SLICE_X70Y96 LUT1 (Prop_lut1_I0_O) 0.098 -0.085 f u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/popCC_popPtr[2]_i_2__1/O net (fo=43, routed) 0.305 0.220 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/pushToPopGray_buffercc/buffers_0_reg[3]_0 SLICE_X71Y95 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/pushToPopGray_buffercc/buffers_1_reg[2]/CLR ------------------------------------------------------------------- ------------------- (clock mlkem_clk_clk_pll rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout3_buf/O net (fo=25775, routed) 0.920 -0.388 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/pushToPopGray_buffercc/mlkem_clk SLICE_X71Y95 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/pushToPopGray_buffercc/buffers_1_reg[2]/C clock pessimism -0.213 -0.601 SLICE_X71Y95 FDCE (Remov_fdce_C_CLR) -0.092 -0.693 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/pushToPopGray_buffercc/buffers_1_reg[2] ------------------------------------------------------------------- required time 0.693 arrival time 0.220 ------------------------------------------------------------------- slack 0.913 Slack (MET) : 0.915ns (arrival time - required time) Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_cnt_reg[1]/C (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/m_r_reg[106]/CLR (removal check against rising-edge clock mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (mlkem_clk_clk_pll rise@0.000ns - mlkem_clk_clk_pll rise@0.000ns) Data Path Delay: 0.785ns (logic 0.213ns (27.129%) route 0.572ns (72.871%)) Logic Levels: 1 (LUT5=1) Clock Path Skew: 0.029ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.458ns Source Clock Delay (SCD): -0.676ns Clock Pessimism Removal (CPR): 0.189ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock mlkem_clk_clk_pll rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout3_buf/O net (fo=25775, routed) 0.587 -0.676 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/mlkem_clk SLICE_X56Y104 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_cnt_reg[1]/C ------------------------------------------------------------------- ------------------- SLICE_X56Y104 FDCE (Prop_fdce_C_Q) 0.164 -0.512 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_cnt_reg[1]/Q net (fo=7, routed) 0.117 -0.395 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_c_in_bram/srst_cnt_reg[1] SLICE_X57Y104 LUT5 (Prop_lut5_I1_O) 0.049 -0.346 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_c_in_bram/q_s3[12]_i_4/O net (fo=24229, routed) 0.455 0.109 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/delay_reg[1] SLICE_X61Y115 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/m_r_reg[106]/CLR ------------------------------------------------------------------- ------------------- (clock mlkem_clk_clk_pll rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout3_buf/O net (fo=25775, routed) 0.850 -0.458 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mlkem_clk SLICE_X61Y115 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/m_r_reg[106]/C clock pessimism -0.189 -0.647 SLICE_X61Y115 FDCE (Remov_fdce_C_CLR) -0.159 -0.806 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/m_r_reg[106] ------------------------------------------------------------------- required time 0.806 arrival time 0.109 ------------------------------------------------------------------- slack 0.915 Slack (MET) : 0.915ns (arrival time - required time) Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_cnt_reg[1]/C (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/m_r_reg[138]/CLR (removal check against rising-edge clock mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (mlkem_clk_clk_pll rise@0.000ns - mlkem_clk_clk_pll rise@0.000ns) Data Path Delay: 0.785ns (logic 0.213ns (27.129%) route 0.572ns (72.871%)) Logic Levels: 1 (LUT5=1) Clock Path Skew: 0.029ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.458ns Source Clock Delay (SCD): -0.676ns Clock Pessimism Removal (CPR): 0.189ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock mlkem_clk_clk_pll rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout3_buf/O net (fo=25775, routed) 0.587 -0.676 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/mlkem_clk SLICE_X56Y104 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_cnt_reg[1]/C ------------------------------------------------------------------- ------------------- SLICE_X56Y104 FDCE (Prop_fdce_C_Q) 0.164 -0.512 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_cnt_reg[1]/Q net (fo=7, routed) 0.117 -0.395 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_c_in_bram/srst_cnt_reg[1] SLICE_X57Y104 LUT5 (Prop_lut5_I1_O) 0.049 -0.346 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_c_in_bram/q_s3[12]_i_4/O net (fo=24229, routed) 0.455 0.109 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/delay_reg[1] SLICE_X61Y115 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/m_r_reg[138]/CLR ------------------------------------------------------------------- ------------------- (clock mlkem_clk_clk_pll rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout3_buf/O net (fo=25775, routed) 0.850 -0.458 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mlkem_clk SLICE_X61Y115 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/m_r_reg[138]/C clock pessimism -0.189 -0.647 SLICE_X61Y115 FDCE (Remov_fdce_C_CLR) -0.159 -0.806 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/m_r_reg[138] ------------------------------------------------------------------- required time 0.806 arrival time 0.109 ------------------------------------------------------------------- slack 0.915 Slack (MET) : 0.915ns (arrival time - required time) Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_cnt_reg[1]/C (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/m_r_reg[170]/CLR (removal check against rising-edge clock mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (mlkem_clk_clk_pll rise@0.000ns - mlkem_clk_clk_pll rise@0.000ns) Data Path Delay: 0.785ns (logic 0.213ns (27.129%) route 0.572ns (72.871%)) Logic Levels: 1 (LUT5=1) Clock Path Skew: 0.029ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.458ns Source Clock Delay (SCD): -0.676ns Clock Pessimism Removal (CPR): 0.189ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock mlkem_clk_clk_pll rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout3_buf/O net (fo=25775, routed) 0.587 -0.676 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/mlkem_clk SLICE_X56Y104 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_cnt_reg[1]/C ------------------------------------------------------------------- ------------------- SLICE_X56Y104 FDCE (Prop_fdce_C_Q) 0.164 -0.512 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_cnt_reg[1]/Q net (fo=7, routed) 0.117 -0.395 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_c_in_bram/srst_cnt_reg[1] SLICE_X57Y104 LUT5 (Prop_lut5_I1_O) 0.049 -0.346 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_c_in_bram/q_s3[12]_i_4/O net (fo=24229, routed) 0.455 0.109 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/delay_reg[1] SLICE_X61Y115 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/m_r_reg[170]/CLR ------------------------------------------------------------------- ------------------- (clock mlkem_clk_clk_pll rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout3_buf/O net (fo=25775, routed) 0.850 -0.458 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mlkem_clk SLICE_X61Y115 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/m_r_reg[170]/C clock pessimism -0.189 -0.647 SLICE_X61Y115 FDCE (Remov_fdce_C_CLR) -0.159 -0.806 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/m_r_reg[170] ------------------------------------------------------------------- required time 0.806 arrival time 0.109 ------------------------------------------------------------------- slack 0.915 Slack (MET) : 0.915ns (arrival time - required time) Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_cnt_reg[1]/C (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/m_r_reg[195]/CLR (removal check against rising-edge clock mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (mlkem_clk_clk_pll rise@0.000ns - mlkem_clk_clk_pll rise@0.000ns) Data Path Delay: 0.785ns (logic 0.213ns (27.129%) route 0.572ns (72.871%)) Logic Levels: 1 (LUT5=1) Clock Path Skew: 0.029ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.458ns Source Clock Delay (SCD): -0.676ns Clock Pessimism Removal (CPR): 0.189ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock mlkem_clk_clk_pll rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout3_buf/O net (fo=25775, routed) 0.587 -0.676 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/mlkem_clk SLICE_X56Y104 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_cnt_reg[1]/C ------------------------------------------------------------------- ------------------- SLICE_X56Y104 FDCE (Prop_fdce_C_Q) 0.164 -0.512 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_cnt_reg[1]/Q net (fo=7, routed) 0.117 -0.395 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_c_in_bram/srst_cnt_reg[1] SLICE_X57Y104 LUT5 (Prop_lut5_I1_O) 0.049 -0.346 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_c_in_bram/q_s3[12]_i_4/O net (fo=24229, routed) 0.455 0.109 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/delay_reg[1] SLICE_X61Y115 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/m_r_reg[195]/CLR ------------------------------------------------------------------- ------------------- (clock mlkem_clk_clk_pll rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout3_buf/O net (fo=25775, routed) 0.850 -0.458 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mlkem_clk SLICE_X61Y115 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/m_r_reg[195]/C clock pessimism -0.189 -0.647 SLICE_X61Y115 FDCE (Remov_fdce_C_CLR) -0.159 -0.806 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/m_r_reg[195] ------------------------------------------------------------------- required time 0.806 arrival time 0.109 ------------------------------------------------------------------- slack 0.915 Slack (MET) : 0.919ns (arrival time - required time) Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_cnt_reg[1]/C (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/m_r_reg[168]/CLR (removal check against rising-edge clock mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (mlkem_clk_clk_pll rise@0.000ns - mlkem_clk_clk_pll rise@0.000ns) Data Path Delay: 0.788ns (logic 0.213ns (27.025%) route 0.575ns (72.975%)) Logic Levels: 1 (LUT5=1) Clock Path Skew: 0.028ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.459ns Source Clock Delay (SCD): -0.676ns Clock Pessimism Removal (CPR): 0.189ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock mlkem_clk_clk_pll rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout3_buf/O net (fo=25775, routed) 0.587 -0.676 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/mlkem_clk SLICE_X56Y104 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_cnt_reg[1]/C ------------------------------------------------------------------- ------------------- SLICE_X56Y104 FDCE (Prop_fdce_C_Q) 0.164 -0.512 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_cnt_reg[1]/Q net (fo=7, routed) 0.117 -0.395 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_c_in_bram/srst_cnt_reg[1] SLICE_X57Y104 LUT5 (Prop_lut5_I1_O) 0.049 -0.346 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_c_in_bram/q_s3[12]_i_4/O net (fo=24229, routed) 0.458 0.112 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/delay_reg[1] SLICE_X59Y116 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/m_r_reg[168]/CLR ------------------------------------------------------------------- ------------------- (clock mlkem_clk_clk_pll rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout3_buf/O net (fo=25775, routed) 0.849 -0.459 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mlkem_clk SLICE_X59Y116 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/m_r_reg[168]/C clock pessimism -0.189 -0.648 SLICE_X59Y116 FDCE (Remov_fdce_C_CLR) -0.159 -0.807 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/m_r_reg[168] ------------------------------------------------------------------- required time 0.807 arrival time 0.112 ------------------------------------------------------------------- slack 0.919 Slack (MET) : 0.919ns (arrival time - required time) Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_cnt_reg[1]/C (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/m_r_reg[8]/CLR (removal check against rising-edge clock mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (mlkem_clk_clk_pll rise@0.000ns - mlkem_clk_clk_pll rise@0.000ns) Data Path Delay: 0.788ns (logic 0.213ns (27.025%) route 0.575ns (72.975%)) Logic Levels: 1 (LUT5=1) Clock Path Skew: 0.028ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.459ns Source Clock Delay (SCD): -0.676ns Clock Pessimism Removal (CPR): 0.189ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock mlkem_clk_clk_pll rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout3_buf/O net (fo=25775, routed) 0.587 -0.676 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/mlkem_clk SLICE_X56Y104 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_cnt_reg[1]/C ------------------------------------------------------------------- ------------------- SLICE_X56Y104 FDCE (Prop_fdce_C_Q) 0.164 -0.512 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_cnt_reg[1]/Q net (fo=7, routed) 0.117 -0.395 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_c_in_bram/srst_cnt_reg[1] SLICE_X57Y104 LUT5 (Prop_lut5_I1_O) 0.049 -0.346 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_c_in_bram/q_s3[12]_i_4/O net (fo=24229, routed) 0.458 0.112 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/delay_reg[1] SLICE_X59Y116 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/m_r_reg[8]/CLR ------------------------------------------------------------------- ------------------- (clock mlkem_clk_clk_pll rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout3_buf/O net (fo=25775, routed) 0.849 -0.459 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mlkem_clk SLICE_X59Y116 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/m_r_reg[8]/C clock pessimism -0.189 -0.648 SLICE_X59Y116 FDCE (Remov_fdce_C_CLR) -0.159 -0.807 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/m_r_reg[8] ------------------------------------------------------------------- required time 0.807 arrival time 0.112 ------------------------------------------------------------------- slack 0.919 Slack (MET) : 0.921ns (arrival time - required time) Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_cnt_reg[1]/C (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/m_r_reg[107]/CLR (removal check against rising-edge clock mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (mlkem_clk_clk_pll rise@0.000ns - mlkem_clk_clk_pll rise@0.000ns) Data Path Delay: 0.795ns (logic 0.213ns (26.784%) route 0.582ns (73.216%)) Logic Levels: 1 (LUT5=1) Clock Path Skew: 0.008ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.458ns Source Clock Delay (SCD): -0.676ns Clock Pessimism Removal (CPR): 0.210ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock mlkem_clk_clk_pll rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout3_buf/O net (fo=25775, routed) 0.587 -0.676 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/mlkem_clk SLICE_X56Y104 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_cnt_reg[1]/C ------------------------------------------------------------------- ------------------- SLICE_X56Y104 FDCE (Prop_fdce_C_Q) 0.164 -0.512 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_cnt_reg[1]/Q net (fo=7, routed) 0.117 -0.395 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_c_in_bram/srst_cnt_reg[1] SLICE_X57Y104 LUT5 (Prop_lut5_I1_O) 0.049 -0.346 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_c_in_bram/q_s3[12]_i_4/O net (fo=24229, routed) 0.465 0.119 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/delay_reg[1] SLICE_X56Y117 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/m_r_reg[107]/CLR ------------------------------------------------------------------- ------------------- (clock mlkem_clk_clk_pll rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout3_buf/O net (fo=25775, routed) 0.850 -0.458 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mlkem_clk SLICE_X56Y117 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/m_r_reg[107]/C clock pessimism -0.210 -0.668 SLICE_X56Y117 FDCE (Remov_fdce_C_CLR) -0.134 -0.802 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/m_r_reg[107] ------------------------------------------------------------------- required time 0.802 arrival time 0.119 ------------------------------------------------------------------- slack 0.921 Slack (MET) : 0.921ns (arrival time - required time) Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_cnt_reg[1]/C (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/m_r_reg[108]/CLR (removal check against rising-edge clock mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (mlkem_clk_clk_pll rise@0.000ns - mlkem_clk_clk_pll rise@0.000ns) Data Path Delay: 0.795ns (logic 0.213ns (26.784%) route 0.582ns (73.216%)) Logic Levels: 1 (LUT5=1) Clock Path Skew: 0.008ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.458ns Source Clock Delay (SCD): -0.676ns Clock Pessimism Removal (CPR): 0.210ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock mlkem_clk_clk_pll rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout3_buf/O net (fo=25775, routed) 0.587 -0.676 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/mlkem_clk SLICE_X56Y104 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_cnt_reg[1]/C ------------------------------------------------------------------- ------------------- SLICE_X56Y104 FDCE (Prop_fdce_C_Q) 0.164 -0.512 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_cnt_reg[1]/Q net (fo=7, routed) 0.117 -0.395 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_c_in_bram/srst_cnt_reg[1] SLICE_X57Y104 LUT5 (Prop_lut5_I1_O) 0.049 -0.346 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_c_in_bram/q_s3[12]_i_4/O net (fo=24229, routed) 0.465 0.119 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/delay_reg[1] SLICE_X56Y117 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/m_r_reg[108]/CLR ------------------------------------------------------------------- ------------------- (clock mlkem_clk_clk_pll rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout3_buf/O net (fo=25775, routed) 0.850 -0.458 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mlkem_clk SLICE_X56Y117 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/m_r_reg[108]/C clock pessimism -0.210 -0.668 SLICE_X56Y117 FDCE (Remov_fdce_C_CLR) -0.134 -0.802 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/m_r_reg[108] ------------------------------------------------------------------- required time 0.802 arrival time 0.119 ------------------------------------------------------------------- slack 0.921 Slack (MET) : 0.921ns (arrival time - required time) Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_cnt_reg[1]/C (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/m_r_reg[73]/CLR (removal check against rising-edge clock mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (mlkem_clk_clk_pll rise@0.000ns - mlkem_clk_clk_pll rise@0.000ns) Data Path Delay: 0.795ns (logic 0.213ns (26.784%) route 0.582ns (73.216%)) Logic Levels: 1 (LUT5=1) Clock Path Skew: 0.008ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.458ns Source Clock Delay (SCD): -0.676ns Clock Pessimism Removal (CPR): 0.210ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock mlkem_clk_clk_pll rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout3_buf/O net (fo=25775, routed) 0.587 -0.676 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/mlkem_clk SLICE_X56Y104 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_cnt_reg[1]/C ------------------------------------------------------------------- ------------------- SLICE_X56Y104 FDCE (Prop_fdce_C_Q) 0.164 -0.512 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_cnt_reg[1]/Q net (fo=7, routed) 0.117 -0.395 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_c_in_bram/srst_cnt_reg[1] SLICE_X57Y104 LUT5 (Prop_lut5_I1_O) 0.049 -0.346 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_c_in_bram/q_s3[12]_i_4/O net (fo=24229, routed) 0.465 0.119 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/delay_reg[1] SLICE_X56Y117 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/m_r_reg[73]/CLR ------------------------------------------------------------------- ------------------- (clock mlkem_clk_clk_pll rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout3_buf/O net (fo=25775, routed) 0.850 -0.458 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mlkem_clk SLICE_X56Y117 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/m_r_reg[73]/C clock pessimism -0.210 -0.668 SLICE_X56Y117 FDCE (Remov_fdce_C_CLR) -0.134 -0.802 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/m_r_reg[73] ------------------------------------------------------------------- required time 0.802 arrival time 0.119 ------------------------------------------------------------------- slack 0.921 Slack (MET) : 0.921ns (arrival time - required time) Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_cnt_reg[1]/C (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/m_r_reg[75]/CLR (removal check against rising-edge clock mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (mlkem_clk_clk_pll rise@0.000ns - mlkem_clk_clk_pll rise@0.000ns) Data Path Delay: 0.795ns (logic 0.213ns (26.784%) route 0.582ns (73.216%)) Logic Levels: 1 (LUT5=1) Clock Path Skew: 0.008ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.458ns Source Clock Delay (SCD): -0.676ns Clock Pessimism Removal (CPR): 0.210ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock mlkem_clk_clk_pll rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout3_buf/O net (fo=25775, routed) 0.587 -0.676 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/mlkem_clk SLICE_X56Y104 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_cnt_reg[1]/C ------------------------------------------------------------------- ------------------- SLICE_X56Y104 FDCE (Prop_fdce_C_Q) 0.164 -0.512 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_cnt_reg[1]/Q net (fo=7, routed) 0.117 -0.395 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_c_in_bram/srst_cnt_reg[1] SLICE_X57Y104 LUT5 (Prop_lut5_I1_O) 0.049 -0.346 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_c_in_bram/q_s3[12]_i_4/O net (fo=24229, routed) 0.465 0.119 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/delay_reg[1] SLICE_X56Y117 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/m_r_reg[75]/CLR ------------------------------------------------------------------- ------------------- (clock mlkem_clk_clk_pll rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout3_buf/O net (fo=25775, routed) 0.850 -0.458 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mlkem_clk SLICE_X56Y117 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/m_r_reg[75]/C clock pessimism -0.210 -0.668 SLICE_X56Y117 FDCE (Remov_fdce_C_CLR) -0.134 -0.802 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/m_r_reg[75] ------------------------------------------------------------------- required time 0.802 arrival time 0.119 ------------------------------------------------------------------- slack 0.921 Slack (MET) : 0.924ns (arrival time - required time) Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_cnt_reg[1]/C (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/m_r_reg[136]/CLR (removal check against rising-edge clock mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (mlkem_clk_clk_pll rise@0.000ns - mlkem_clk_clk_pll rise@0.000ns) Data Path Delay: 0.793ns (logic 0.213ns (26.876%) route 0.580ns (73.124%)) Logic Levels: 1 (LUT5=1) Clock Path Skew: 0.028ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.459ns Source Clock Delay (SCD): -0.676ns Clock Pessimism Removal (CPR): 0.189ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock mlkem_clk_clk_pll rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout3_buf/O net (fo=25775, routed) 0.587 -0.676 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/mlkem_clk SLICE_X56Y104 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_cnt_reg[1]/C ------------------------------------------------------------------- ------------------- SLICE_X56Y104 FDCE (Prop_fdce_C_Q) 0.164 -0.512 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_cnt_reg[1]/Q net (fo=7, routed) 0.117 -0.395 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_c_in_bram/srst_cnt_reg[1] SLICE_X57Y104 LUT5 (Prop_lut5_I1_O) 0.049 -0.346 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_c_in_bram/q_s3[12]_i_4/O net (fo=24229, routed) 0.462 0.117 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/delay_reg[1] SLICE_X58Y116 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/m_r_reg[136]/CLR ------------------------------------------------------------------- ------------------- (clock mlkem_clk_clk_pll rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout3_buf/O net (fo=25775, routed) 0.849 -0.459 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mlkem_clk SLICE_X58Y116 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/m_r_reg[136]/C clock pessimism -0.189 -0.648 SLICE_X58Y116 FDCE (Remov_fdce_C_CLR) -0.159 -0.807 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/m_r_reg[136] ------------------------------------------------------------------- required time 0.807 arrival time 0.117 ------------------------------------------------------------------- slack 0.924 Slack (MET) : 0.924ns (arrival time - required time) Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_cnt_reg[1]/C (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/m_r_reg[200]/CLR (removal check against rising-edge clock mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (mlkem_clk_clk_pll rise@0.000ns - mlkem_clk_clk_pll rise@0.000ns) Data Path Delay: 0.793ns (logic 0.213ns (26.876%) route 0.580ns (73.124%)) Logic Levels: 1 (LUT5=1) Clock Path Skew: 0.028ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.459ns Source Clock Delay (SCD): -0.676ns Clock Pessimism Removal (CPR): 0.189ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock mlkem_clk_clk_pll rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout3_buf/O net (fo=25775, routed) 0.587 -0.676 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/mlkem_clk SLICE_X56Y104 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_cnt_reg[1]/C ------------------------------------------------------------------- ------------------- SLICE_X56Y104 FDCE (Prop_fdce_C_Q) 0.164 -0.512 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_cnt_reg[1]/Q net (fo=7, routed) 0.117 -0.395 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_c_in_bram/srst_cnt_reg[1] SLICE_X57Y104 LUT5 (Prop_lut5_I1_O) 0.049 -0.346 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_c_in_bram/q_s3[12]_i_4/O net (fo=24229, routed) 0.462 0.117 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/delay_reg[1] SLICE_X58Y116 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/m_r_reg[200]/CLR ------------------------------------------------------------------- ------------------- (clock mlkem_clk_clk_pll rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout3_buf/O net (fo=25775, routed) 0.849 -0.459 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mlkem_clk SLICE_X58Y116 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/m_r_reg[200]/C clock pessimism -0.189 -0.648 SLICE_X58Y116 FDCE (Remov_fdce_C_CLR) -0.159 -0.807 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/m_r_reg[200] ------------------------------------------------------------------- required time 0.807 arrival time 0.117 ------------------------------------------------------------------- slack 0.924 Slack (MET) : 0.924ns (arrival time - required time) Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_cnt_reg[1]/C (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/m_r_reg[72]/CLR (removal check against rising-edge clock mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (mlkem_clk_clk_pll rise@0.000ns - mlkem_clk_clk_pll rise@0.000ns) Data Path Delay: 0.793ns (logic 0.213ns (26.876%) route 0.580ns (73.124%)) Logic Levels: 1 (LUT5=1) Clock Path Skew: 0.028ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.459ns Source Clock Delay (SCD): -0.676ns Clock Pessimism Removal (CPR): 0.189ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock mlkem_clk_clk_pll rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout3_buf/O net (fo=25775, routed) 0.587 -0.676 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/mlkem_clk SLICE_X56Y104 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_cnt_reg[1]/C ------------------------------------------------------------------- ------------------- SLICE_X56Y104 FDCE (Prop_fdce_C_Q) 0.164 -0.512 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_cnt_reg[1]/Q net (fo=7, routed) 0.117 -0.395 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_c_in_bram/srst_cnt_reg[1] SLICE_X57Y104 LUT5 (Prop_lut5_I1_O) 0.049 -0.346 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_c_in_bram/q_s3[12]_i_4/O net (fo=24229, routed) 0.462 0.117 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/delay_reg[1] SLICE_X58Y116 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/m_r_reg[72]/CLR ------------------------------------------------------------------- ------------------- (clock mlkem_clk_clk_pll rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout3_buf/O net (fo=25775, routed) 0.849 -0.459 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mlkem_clk SLICE_X58Y116 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/m_r_reg[72]/C clock pessimism -0.189 -0.648 SLICE_X58Y116 FDCE (Remov_fdce_C_CLR) -0.159 -0.807 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/m_r_reg[72] ------------------------------------------------------------------- required time 0.807 arrival time 0.117 ------------------------------------------------------------------- slack 0.924 Slack (MET) : 0.946ns (arrival time - required time) Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_cnt_reg[1]/C (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/m_r_reg[139]/CLR (removal check against rising-edge clock mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (mlkem_clk_clk_pll rise@0.000ns - mlkem_clk_clk_pll rise@0.000ns) Data Path Delay: 0.795ns (logic 0.213ns (26.784%) route 0.582ns (73.216%)) Logic Levels: 1 (LUT5=1) Clock Path Skew: 0.008ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.458ns Source Clock Delay (SCD): -0.676ns Clock Pessimism Removal (CPR): 0.210ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock mlkem_clk_clk_pll rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout3_buf/O net (fo=25775, routed) 0.587 -0.676 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/mlkem_clk SLICE_X56Y104 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_cnt_reg[1]/C ------------------------------------------------------------------- ------------------- SLICE_X56Y104 FDCE (Prop_fdce_C_Q) 0.164 -0.512 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_cnt_reg[1]/Q net (fo=7, routed) 0.117 -0.395 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_c_in_bram/srst_cnt_reg[1] SLICE_X57Y104 LUT5 (Prop_lut5_I1_O) 0.049 -0.346 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_c_in_bram/q_s3[12]_i_4/O net (fo=24229, routed) 0.465 0.119 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/delay_reg[1] SLICE_X57Y117 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/m_r_reg[139]/CLR ------------------------------------------------------------------- ------------------- (clock mlkem_clk_clk_pll rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout3_buf/O net (fo=25775, routed) 0.850 -0.458 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mlkem_clk SLICE_X57Y117 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/m_r_reg[139]/C clock pessimism -0.210 -0.668 SLICE_X57Y117 FDCE (Remov_fdce_C_CLR) -0.159 -0.827 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/m_r_reg[139] ------------------------------------------------------------------- required time 0.827 arrival time 0.119 ------------------------------------------------------------------- slack 0.946 Slack (MET) : 0.946ns (arrival time - required time) Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_cnt_reg[1]/C (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/m_r_reg[140]/CLR (removal check against rising-edge clock mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (mlkem_clk_clk_pll rise@0.000ns - mlkem_clk_clk_pll rise@0.000ns) Data Path Delay: 0.795ns (logic 0.213ns (26.784%) route 0.582ns (73.216%)) Logic Levels: 1 (LUT5=1) Clock Path Skew: 0.008ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.458ns Source Clock Delay (SCD): -0.676ns Clock Pessimism Removal (CPR): 0.210ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock mlkem_clk_clk_pll rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout3_buf/O net (fo=25775, routed) 0.587 -0.676 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/mlkem_clk SLICE_X56Y104 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_cnt_reg[1]/C ------------------------------------------------------------------- ------------------- SLICE_X56Y104 FDCE (Prop_fdce_C_Q) 0.164 -0.512 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_cnt_reg[1]/Q net (fo=7, routed) 0.117 -0.395 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_c_in_bram/srst_cnt_reg[1] SLICE_X57Y104 LUT5 (Prop_lut5_I1_O) 0.049 -0.346 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_c_in_bram/q_s3[12]_i_4/O net (fo=24229, routed) 0.465 0.119 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/delay_reg[1] SLICE_X57Y117 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/m_r_reg[140]/CLR ------------------------------------------------------------------- ------------------- (clock mlkem_clk_clk_pll rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout3_buf/O net (fo=25775, routed) 0.850 -0.458 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mlkem_clk SLICE_X57Y117 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/m_r_reg[140]/C clock pessimism -0.210 -0.668 SLICE_X57Y117 FDCE (Remov_fdce_C_CLR) -0.159 -0.827 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/m_r_reg[140] ------------------------------------------------------------------- required time 0.827 arrival time 0.119 ------------------------------------------------------------------- slack 0.946 Slack (MET) : 0.946ns (arrival time - required time) Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_cnt_reg[1]/C (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/m_r_reg[41]/CLR (removal check against rising-edge clock mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (mlkem_clk_clk_pll rise@0.000ns - mlkem_clk_clk_pll rise@0.000ns) Data Path Delay: 0.795ns (logic 0.213ns (26.784%) route 0.582ns (73.216%)) Logic Levels: 1 (LUT5=1) Clock Path Skew: 0.008ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.458ns Source Clock Delay (SCD): -0.676ns Clock Pessimism Removal (CPR): 0.210ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock mlkem_clk_clk_pll rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout3_buf/O net (fo=25775, routed) 0.587 -0.676 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/mlkem_clk SLICE_X56Y104 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_cnt_reg[1]/C ------------------------------------------------------------------- ------------------- SLICE_X56Y104 FDCE (Prop_fdce_C_Q) 0.164 -0.512 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_cnt_reg[1]/Q net (fo=7, routed) 0.117 -0.395 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_c_in_bram/srst_cnt_reg[1] SLICE_X57Y104 LUT5 (Prop_lut5_I1_O) 0.049 -0.346 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_c_in_bram/q_s3[12]_i_4/O net (fo=24229, routed) 0.465 0.119 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/delay_reg[1] SLICE_X57Y117 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/m_r_reg[41]/CLR ------------------------------------------------------------------- ------------------- (clock mlkem_clk_clk_pll rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout3_buf/O net (fo=25775, routed) 0.850 -0.458 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mlkem_clk SLICE_X57Y117 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/m_r_reg[41]/C clock pessimism -0.210 -0.668 SLICE_X57Y117 FDCE (Remov_fdce_C_CLR) -0.159 -0.827 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/m_r_reg[41] ------------------------------------------------------------------- required time 0.827 arrival time 0.119 ------------------------------------------------------------------- slack 0.946 Slack (MET) : 0.946ns (arrival time - required time) Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_cnt_reg[1]/C (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/m_r_reg[43]/CLR (removal check against rising-edge clock mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (mlkem_clk_clk_pll rise@0.000ns - mlkem_clk_clk_pll rise@0.000ns) Data Path Delay: 0.795ns (logic 0.213ns (26.784%) route 0.582ns (73.216%)) Logic Levels: 1 (LUT5=1) Clock Path Skew: 0.008ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.458ns Source Clock Delay (SCD): -0.676ns Clock Pessimism Removal (CPR): 0.210ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock mlkem_clk_clk_pll rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout3_buf/O net (fo=25775, routed) 0.587 -0.676 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/mlkem_clk SLICE_X56Y104 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_cnt_reg[1]/C ------------------------------------------------------------------- ------------------- SLICE_X56Y104 FDCE (Prop_fdce_C_Q) 0.164 -0.512 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_cnt_reg[1]/Q net (fo=7, routed) 0.117 -0.395 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_c_in_bram/srst_cnt_reg[1] SLICE_X57Y104 LUT5 (Prop_lut5_I1_O) 0.049 -0.346 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_c_in_bram/q_s3[12]_i_4/O net (fo=24229, routed) 0.465 0.119 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/delay_reg[1] SLICE_X57Y117 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/m_r_reg[43]/CLR ------------------------------------------------------------------- ------------------- (clock mlkem_clk_clk_pll rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout3_buf/O net (fo=25775, routed) 0.850 -0.458 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mlkem_clk SLICE_X57Y117 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/m_r_reg[43]/C clock pessimism -0.210 -0.668 SLICE_X57Y117 FDCE (Remov_fdce_C_CLR) -0.159 -0.827 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/m_r_reg[43] ------------------------------------------------------------------- required time 0.827 arrival time 0.119 ------------------------------------------------------------------- slack 0.946 --------------------------------------------------------------------------------------------------- Path Group: **async_default** From Clock: sys_clk To Clock: mlkem_clk_clk_pll Setup : NA Failing Endpoints, Worst Slack NA , Total Violation NA Hold : 0 Failing Endpoints, Worst Slack 4.195ns, Total Violation 0.000ns --------------------------------------------------------------------------------------------------- Min Delay Paths -------------------------------------------------------------------------------------- Slack (MET) : 4.195ns (arrival time - required time) Source: pll_clk.u_rst_sys/delay_reg[1]/C (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/buffers_0_reg/CLR (removal check against rising-edge clock mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (mlkem_clk_clk_pll rise@0.000ns - sys_clk rise@0.000ns) Data Path Delay: 4.644ns (logic 0.209ns (4.500%) route 4.435ns (95.500%)) Logic Levels: 1 (LUT1=1) Clock Path Skew: 0.319ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.388ns Source Clock Delay (SCD): -0.608ns Clock Pessimism Removal (CPR): -0.099ns Clock Uncertainty: 0.197ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.136ns Phase Error (PE): 0.120ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9603, routed) 0.654 -0.608 pll_clk.u_rst_sys/sys_clk SLICE_X56Y97 FDCE r pll_clk.u_rst_sys/delay_reg[1]/C ------------------------------------------------------------------- ------------------- SLICE_X56Y97 FDCE (Prop_fdce_C_Q) 0.164 -0.444 r pll_clk.u_rst_sys/delay_reg[1]/Q net (fo=114, routed) 1.550 1.105 pll_clk.u_rst_sys/Q[0] SLICE_X55Y62 LUT1 (Prop_lut1_I0_O) 0.045 1.150 f pll_clk.u_rst_sys/bf2_do_en_i_1/O net (fo=3749, routed) 2.885 4.036 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/prst SLICE_X70Y96 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/buffers_0_reg/CLR ------------------------------------------------------------------- ------------------- (clock mlkem_clk_clk_pll rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout3_buf/O net (fo=25775, routed) 0.920 -0.388 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/mlkem_clk SLICE_X70Y96 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/buffers_0_reg/C clock pessimism 0.099 -0.289 clock uncertainty 0.197 -0.093 SLICE_X70Y96 FDCE (Remov_fdce_C_CLR) -0.067 -0.160 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/buffers_0_reg ------------------------------------------------------------------- required time 0.160 arrival time 4.036 ------------------------------------------------------------------- slack 4.195 Slack (MET) : 4.195ns (arrival time - required time) Source: pll_clk.u_rst_sys/delay_reg[1]/C (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/buffers_1_reg/CLR (removal check against rising-edge clock mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (mlkem_clk_clk_pll rise@0.000ns - sys_clk rise@0.000ns) Data Path Delay: 4.644ns (logic 0.209ns (4.500%) route 4.435ns (95.500%)) Logic Levels: 1 (LUT1=1) Clock Path Skew: 0.319ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.388ns Source Clock Delay (SCD): -0.608ns Clock Pessimism Removal (CPR): -0.099ns Clock Uncertainty: 0.197ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.136ns Phase Error (PE): 0.120ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9603, routed) 0.654 -0.608 pll_clk.u_rst_sys/sys_clk SLICE_X56Y97 FDCE r pll_clk.u_rst_sys/delay_reg[1]/C ------------------------------------------------------------------- ------------------- SLICE_X56Y97 FDCE (Prop_fdce_C_Q) 0.164 -0.444 r pll_clk.u_rst_sys/delay_reg[1]/Q net (fo=114, routed) 1.550 1.105 pll_clk.u_rst_sys/Q[0] SLICE_X55Y62 LUT1 (Prop_lut1_I0_O) 0.045 1.150 f pll_clk.u_rst_sys/bf2_do_en_i_1/O net (fo=3749, routed) 2.885 4.036 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/prst SLICE_X70Y96 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/buffers_1_reg/CLR ------------------------------------------------------------------- ------------------- (clock mlkem_clk_clk_pll rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout3_buf/O net (fo=25775, routed) 0.920 -0.388 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/mlkem_clk SLICE_X70Y96 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/buffers_1_reg/C clock pessimism 0.099 -0.289 clock uncertainty 0.197 -0.093 SLICE_X70Y96 FDCE (Remov_fdce_C_CLR) -0.067 -0.160 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/buffers_1_reg ------------------------------------------------------------------- required time 0.160 arrival time 4.036 ------------------------------------------------------------------- slack 4.195 Slack (MET) : 4.406ns (arrival time - required time) Source: pll_clk.u_rst_sys/delay_reg[1]/C (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: pll_clk.u_rst_mlkem/delay_reg[0]/CLR (removal check against rising-edge clock mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (mlkem_clk_clk_pll rise@0.000ns - sys_clk rise@0.000ns) Data Path Delay: 4.762ns (logic 0.209ns (4.389%) route 4.553ns (95.611%)) Logic Levels: 1 (LUT1=1) Clock Path Skew: 0.251ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.456ns Source Clock Delay (SCD): -0.608ns Clock Pessimism Removal (CPR): -0.099ns Clock Uncertainty: 0.197ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.136ns Phase Error (PE): 0.120ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9603, routed) 0.654 -0.608 pll_clk.u_rst_sys/sys_clk SLICE_X56Y97 FDCE r pll_clk.u_rst_sys/delay_reg[1]/C ------------------------------------------------------------------- ------------------- SLICE_X56Y97 FDCE (Prop_fdce_C_Q) 0.164 -0.444 r pll_clk.u_rst_sys/delay_reg[1]/Q net (fo=114, routed) 1.550 1.105 pll_clk.u_rst_sys/Q[0] SLICE_X55Y62 LUT1 (Prop_lut1_I0_O) 0.045 1.150 f pll_clk.u_rst_sys/bf2_do_en_i_1/O net (fo=3749, routed) 3.003 4.154 pll_clk.u_rst_mlkem/prst SLICE_X67Y102 FDCE f pll_clk.u_rst_mlkem/delay_reg[0]/CLR ------------------------------------------------------------------- ------------------- (clock mlkem_clk_clk_pll rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout3_buf/O net (fo=25775, routed) 0.852 -0.456 pll_clk.u_rst_mlkem/mlkem_clk SLICE_X67Y102 FDCE r pll_clk.u_rst_mlkem/delay_reg[0]/C clock pessimism 0.099 -0.357 clock uncertainty 0.197 -0.161 SLICE_X67Y102 FDCE (Remov_fdce_C_CLR) -0.092 -0.253 pll_clk.u_rst_mlkem/delay_reg[0] ------------------------------------------------------------------- required time 0.253 arrival time 4.154 ------------------------------------------------------------------- slack 4.406 Slack (MET) : 4.406ns (arrival time - required time) Source: pll_clk.u_rst_sys/delay_reg[1]/C (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: pll_clk.u_rst_mlkem/delay_reg[1]/CLR (removal check against rising-edge clock mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (mlkem_clk_clk_pll rise@0.000ns - sys_clk rise@0.000ns) Data Path Delay: 4.762ns (logic 0.209ns (4.389%) route 4.553ns (95.611%)) Logic Levels: 1 (LUT1=1) Clock Path Skew: 0.251ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.456ns Source Clock Delay (SCD): -0.608ns Clock Pessimism Removal (CPR): -0.099ns Clock Uncertainty: 0.197ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.136ns Phase Error (PE): 0.120ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9603, routed) 0.654 -0.608 pll_clk.u_rst_sys/sys_clk SLICE_X56Y97 FDCE r pll_clk.u_rst_sys/delay_reg[1]/C ------------------------------------------------------------------- ------------------- SLICE_X56Y97 FDCE (Prop_fdce_C_Q) 0.164 -0.444 r pll_clk.u_rst_sys/delay_reg[1]/Q net (fo=114, routed) 1.550 1.105 pll_clk.u_rst_sys/Q[0] SLICE_X55Y62 LUT1 (Prop_lut1_I0_O) 0.045 1.150 f pll_clk.u_rst_sys/bf2_do_en_i_1/O net (fo=3749, routed) 3.003 4.154 pll_clk.u_rst_mlkem/prst SLICE_X67Y102 FDCE f pll_clk.u_rst_mlkem/delay_reg[1]/CLR ------------------------------------------------------------------- ------------------- (clock mlkem_clk_clk_pll rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout3_buf/O net (fo=25775, routed) 0.852 -0.456 pll_clk.u_rst_mlkem/mlkem_clk SLICE_X67Y102 FDCE r pll_clk.u_rst_mlkem/delay_reg[1]/C clock pessimism 0.099 -0.357 clock uncertainty 0.197 -0.161 SLICE_X67Y102 FDCE (Remov_fdce_C_CLR) -0.092 -0.253 pll_clk.u_rst_mlkem/delay_reg[1] ------------------------------------------------------------------- required time 0.253 arrival time 4.154 ------------------------------------------------------------------- slack 4.406 --------------------------------------------------------------------------------------------------- Path Group: **async_default** From Clock: mlkem_clk_clk_pll To Clock: sys_clk Setup : NA Failing Endpoints, Worst Slack NA , Total Violation NA Hold : 0 Failing Endpoints, Worst Slack 0.445ns, Total Violation 0.000ns --------------------------------------------------------------------------------------------------- Min Delay Paths -------------------------------------------------------------------------------------- Slack (MET) : 0.445ns (arrival time - required time) Source: pll_clk.u_rst_mlkem/delay_reg[1]/C (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/buffers_0_reg/CLR (removal check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (sys_clk rise@0.000ns - mlkem_clk_clk_pll rise@0.000ns) Data Path Delay: 0.906ns (logic 0.185ns (20.413%) route 0.721ns (79.587%)) Logic Levels: 1 (LUT1=1) Clock Path Skew: 0.394ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.387ns Source Clock Delay (SCD): -0.682ns Clock Pessimism Removal (CPR): -0.099ns Clock Uncertainty: 0.197ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.136ns Phase Error (PE): 0.120ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock mlkem_clk_clk_pll rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout3_buf/O net (fo=25775, routed) 0.581 -0.682 pll_clk.u_rst_mlkem/mlkem_clk SLICE_X67Y102 FDCE r pll_clk.u_rst_mlkem/delay_reg[1]/C ------------------------------------------------------------------- ------------------- SLICE_X67Y102 FDCE (Prop_fdce_C_Q) 0.141 -0.541 r pll_clk.u_rst_mlkem/delay_reg[1]/Q net (fo=4, routed) 0.382 -0.159 pll_clk.u_rst_mlkem/Q[0] SLICE_X69Y98 LUT1 (Prop_lut1_I0_O) 0.044 -0.115 f pll_clk.u_rst_mlkem/rdb_addr[11]_i_2/O net (fo=1066, routed) 0.339 0.224 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/buffers_0_reg_0 SLICE_X68Y94 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/buffers_0_reg/CLR ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9603, routed) 0.921 -0.387 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/sys_clk SLICE_X68Y94 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/buffers_0_reg/C clock pessimism 0.099 -0.288 clock uncertainty 0.197 -0.092 SLICE_X68Y94 FDCE (Remov_fdce_C_CLR) -0.129 -0.221 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/buffers_0_reg ------------------------------------------------------------------- required time 0.221 arrival time 0.224 ------------------------------------------------------------------- slack 0.445 Slack (MET) : 0.445ns (arrival time - required time) Source: pll_clk.u_rst_mlkem/delay_reg[1]/C (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/buffers_1_reg/CLR (removal check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (sys_clk rise@0.000ns - mlkem_clk_clk_pll rise@0.000ns) Data Path Delay: 0.906ns (logic 0.185ns (20.413%) route 0.721ns (79.587%)) Logic Levels: 1 (LUT1=1) Clock Path Skew: 0.394ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.387ns Source Clock Delay (SCD): -0.682ns Clock Pessimism Removal (CPR): -0.099ns Clock Uncertainty: 0.197ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.136ns Phase Error (PE): 0.120ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock mlkem_clk_clk_pll rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout3_buf/O net (fo=25775, routed) 0.581 -0.682 pll_clk.u_rst_mlkem/mlkem_clk SLICE_X67Y102 FDCE r pll_clk.u_rst_mlkem/delay_reg[1]/C ------------------------------------------------------------------- ------------------- SLICE_X67Y102 FDCE (Prop_fdce_C_Q) 0.141 -0.541 r pll_clk.u_rst_mlkem/delay_reg[1]/Q net (fo=4, routed) 0.382 -0.159 pll_clk.u_rst_mlkem/Q[0] SLICE_X69Y98 LUT1 (Prop_lut1_I0_O) 0.044 -0.115 f pll_clk.u_rst_mlkem/rdb_addr[11]_i_2/O net (fo=1066, routed) 0.339 0.224 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/buffers_0_reg_0 SLICE_X68Y94 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/buffers_1_reg/CLR ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9603, routed) 0.921 -0.387 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/sys_clk SLICE_X68Y94 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/buffers_1_reg/C clock pessimism 0.099 -0.288 clock uncertainty 0.197 -0.092 SLICE_X68Y94 FDCE (Remov_fdce_C_CLR) -0.129 -0.221 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/buffers_1_reg ------------------------------------------------------------------- required time 0.221 arrival time 0.224 ------------------------------------------------------------------- slack 0.445 --------------------------------------------------------------------------------------------------- Path Group: **async_default** From Clock: sys_clk To Clock: sys_clk Setup : NA Failing Endpoints, Worst Slack NA , Total Violation NA Hold : 0 Failing Endpoints, Worst Slack 0.798ns, Total Violation 0.000ns --------------------------------------------------------------------------------------------------- Min Delay Paths -------------------------------------------------------------------------------------- Slack (MET) : 0.798ns (arrival time - required time) Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/buffers_1_reg/C (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/popCC_ptrToPush_reg[0]/CLR (removal check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) Data Path Delay: 0.722ns (logic 0.246ns (34.065%) route 0.476ns (65.935%)) Logic Levels: 1 (LUT1=1) Clock Path Skew: 0.016ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.387ns Source Clock Delay (SCD): -0.616ns Clock Pessimism Removal (CPR): 0.213ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9603, routed) 0.646 -0.616 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/sys_clk SLICE_X68Y94 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/buffers_1_reg/C ------------------------------------------------------------------- ------------------- SLICE_X68Y94 FDCE (Prop_fdce_C_Q) 0.148 -0.468 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/buffers_1_reg/Q net (fo=1, routed) 0.286 -0.182 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/buffers_1 SLICE_X68Y94 LUT1 (Prop_lut1_I0_O) 0.098 -0.084 f u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/popCC_popPtr[2]_i_2__2/O net (fo=30, routed) 0.190 0.106 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/buffers_0_reg[3] SLICE_X67Y94 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/popCC_ptrToPush_reg[0]/CLR ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9603, routed) 0.921 -0.387 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/sys_clk SLICE_X67Y94 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/popCC_ptrToPush_reg[0]/C clock pessimism -0.213 -0.600 SLICE_X67Y94 FDCE (Remov_fdce_C_CLR) -0.092 -0.692 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/popCC_ptrToPush_reg[0] ------------------------------------------------------------------- required time 0.692 arrival time 0.106 ------------------------------------------------------------------- slack 0.798 Slack (MET) : 0.798ns (arrival time - required time) Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/buffers_1_reg/C (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/popCC_ptrToPush_reg[1]/CLR (removal check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) Data Path Delay: 0.722ns (logic 0.246ns (34.065%) route 0.476ns (65.935%)) Logic Levels: 1 (LUT1=1) Clock Path Skew: 0.016ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.387ns Source Clock Delay (SCD): -0.616ns Clock Pessimism Removal (CPR): 0.213ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9603, routed) 0.646 -0.616 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/sys_clk SLICE_X68Y94 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/buffers_1_reg/C ------------------------------------------------------------------- ------------------- SLICE_X68Y94 FDCE (Prop_fdce_C_Q) 0.148 -0.468 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/buffers_1_reg/Q net (fo=1, routed) 0.286 -0.182 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/buffers_1 SLICE_X68Y94 LUT1 (Prop_lut1_I0_O) 0.098 -0.084 f u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/popCC_popPtr[2]_i_2__2/O net (fo=30, routed) 0.190 0.106 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/buffers_0_reg[3] SLICE_X67Y94 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/popCC_ptrToPush_reg[1]/CLR ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9603, routed) 0.921 -0.387 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/sys_clk SLICE_X67Y94 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/popCC_ptrToPush_reg[1]/C clock pessimism -0.213 -0.600 SLICE_X67Y94 FDCE (Remov_fdce_C_CLR) -0.092 -0.692 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/popCC_ptrToPush_reg[1] ------------------------------------------------------------------- required time 0.692 arrival time 0.106 ------------------------------------------------------------------- slack 0.798 Slack (MET) : 0.798ns (arrival time - required time) Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/buffers_1_reg/C (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/popCC_ptrToPush_reg[2]/CLR (removal check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) Data Path Delay: 0.722ns (logic 0.246ns (34.065%) route 0.476ns (65.935%)) Logic Levels: 1 (LUT1=1) Clock Path Skew: 0.016ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.387ns Source Clock Delay (SCD): -0.616ns Clock Pessimism Removal (CPR): 0.213ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9603, routed) 0.646 -0.616 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/sys_clk SLICE_X68Y94 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/buffers_1_reg/C ------------------------------------------------------------------- ------------------- SLICE_X68Y94 FDCE (Prop_fdce_C_Q) 0.148 -0.468 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/buffers_1_reg/Q net (fo=1, routed) 0.286 -0.182 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/buffers_1 SLICE_X68Y94 LUT1 (Prop_lut1_I0_O) 0.098 -0.084 f u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/popCC_popPtr[2]_i_2__2/O net (fo=30, routed) 0.190 0.106 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/buffers_0_reg[3] SLICE_X67Y94 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/popCC_ptrToPush_reg[2]/CLR ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9603, routed) 0.921 -0.387 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/sys_clk SLICE_X67Y94 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/popCC_ptrToPush_reg[2]/C clock pessimism -0.213 -0.600 SLICE_X67Y94 FDCE (Remov_fdce_C_CLR) -0.092 -0.692 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/popCC_ptrToPush_reg[2] ------------------------------------------------------------------- required time 0.692 arrival time 0.106 ------------------------------------------------------------------- slack 0.798 Slack (MET) : 0.798ns (arrival time - required time) Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/buffers_1_reg/C (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/popCC_ptrToPush_reg[3]/CLR (removal check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) Data Path Delay: 0.722ns (logic 0.246ns (34.065%) route 0.476ns (65.935%)) Logic Levels: 1 (LUT1=1) Clock Path Skew: 0.016ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.387ns Source Clock Delay (SCD): -0.616ns Clock Pessimism Removal (CPR): 0.213ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9603, routed) 0.646 -0.616 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/sys_clk SLICE_X68Y94 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/buffers_1_reg/C ------------------------------------------------------------------- ------------------- SLICE_X68Y94 FDCE (Prop_fdce_C_Q) 0.148 -0.468 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/buffers_1_reg/Q net (fo=1, routed) 0.286 -0.182 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/buffers_1 SLICE_X68Y94 LUT1 (Prop_lut1_I0_O) 0.098 -0.084 f u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/popCC_popPtr[2]_i_2__2/O net (fo=30, routed) 0.190 0.106 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/buffers_0_reg[3] SLICE_X67Y94 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/popCC_ptrToPush_reg[3]/CLR ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9603, routed) 0.921 -0.387 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/sys_clk SLICE_X67Y94 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/popCC_ptrToPush_reg[3]/C clock pessimism -0.213 -0.600 SLICE_X67Y94 FDCE (Remov_fdce_C_CLR) -0.092 -0.692 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/popCC_ptrToPush_reg[3] ------------------------------------------------------------------- required time 0.692 arrival time 0.106 ------------------------------------------------------------------- slack 0.798 Slack (MET) : 0.813ns (arrival time - required time) Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/buffers_1_reg/C (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/pushToPopGray_buffercc/buffers_0_reg[0]/CLR (removal check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) Data Path Delay: 0.760ns (logic 0.246ns (32.373%) route 0.514ns (67.627%)) Logic Levels: 1 (LUT1=1) Clock Path Skew: 0.039ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.385ns Source Clock Delay (SCD): -0.616ns Clock Pessimism Removal (CPR): 0.192ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9603, routed) 0.646 -0.616 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/sys_clk SLICE_X68Y94 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/buffers_1_reg/C ------------------------------------------------------------------- ------------------- SLICE_X68Y94 FDCE (Prop_fdce_C_Q) 0.148 -0.468 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/buffers_1_reg/Q net (fo=1, routed) 0.286 -0.182 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/buffers_1 SLICE_X68Y94 LUT1 (Prop_lut1_I0_O) 0.098 -0.084 f u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/popCC_popPtr[2]_i_2__2/O net (fo=30, routed) 0.227 0.144 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/pushToPopGray_buffercc/buffers_0_reg[3]_0 SLICE_X65Y94 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/pushToPopGray_buffercc/buffers_0_reg[0]/CLR ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9603, routed) 0.923 -0.385 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/pushToPopGray_buffercc/sys_clk SLICE_X65Y94 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/pushToPopGray_buffercc/buffers_0_reg[0]/C clock pessimism -0.192 -0.577 SLICE_X65Y94 FDCE (Remov_fdce_C_CLR) -0.092 -0.669 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/pushToPopGray_buffercc/buffers_0_reg[0] ------------------------------------------------------------------- required time 0.669 arrival time 0.144 ------------------------------------------------------------------- slack 0.813 Slack (MET) : 0.813ns (arrival time - required time) Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/buffers_1_reg/C (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/pushToPopGray_buffercc/buffers_0_reg[1]/CLR (removal check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) Data Path Delay: 0.760ns (logic 0.246ns (32.373%) route 0.514ns (67.627%)) Logic Levels: 1 (LUT1=1) Clock Path Skew: 0.039ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.385ns Source Clock Delay (SCD): -0.616ns Clock Pessimism Removal (CPR): 0.192ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9603, routed) 0.646 -0.616 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/sys_clk SLICE_X68Y94 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/buffers_1_reg/C ------------------------------------------------------------------- ------------------- SLICE_X68Y94 FDCE (Prop_fdce_C_Q) 0.148 -0.468 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/buffers_1_reg/Q net (fo=1, routed) 0.286 -0.182 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/buffers_1 SLICE_X68Y94 LUT1 (Prop_lut1_I0_O) 0.098 -0.084 f u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/popCC_popPtr[2]_i_2__2/O net (fo=30, routed) 0.227 0.144 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/pushToPopGray_buffercc/buffers_0_reg[3]_0 SLICE_X65Y94 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/pushToPopGray_buffercc/buffers_0_reg[1]/CLR ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9603, routed) 0.923 -0.385 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/pushToPopGray_buffercc/sys_clk SLICE_X65Y94 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/pushToPopGray_buffercc/buffers_0_reg[1]/C clock pessimism -0.192 -0.577 SLICE_X65Y94 FDCE (Remov_fdce_C_CLR) -0.092 -0.669 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/pushToPopGray_buffercc/buffers_0_reg[1] ------------------------------------------------------------------- required time 0.669 arrival time 0.144 ------------------------------------------------------------------- slack 0.813 Slack (MET) : 0.813ns (arrival time - required time) Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/buffers_1_reg/C (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/pushToPopGray_buffercc/buffers_1_reg[0]/CLR (removal check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) Data Path Delay: 0.760ns (logic 0.246ns (32.373%) route 0.514ns (67.627%)) Logic Levels: 1 (LUT1=1) Clock Path Skew: 0.039ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.385ns Source Clock Delay (SCD): -0.616ns Clock Pessimism Removal (CPR): 0.192ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9603, routed) 0.646 -0.616 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/sys_clk SLICE_X68Y94 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/buffers_1_reg/C ------------------------------------------------------------------- ------------------- SLICE_X68Y94 FDCE (Prop_fdce_C_Q) 0.148 -0.468 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/buffers_1_reg/Q net (fo=1, routed) 0.286 -0.182 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/buffers_1 SLICE_X68Y94 LUT1 (Prop_lut1_I0_O) 0.098 -0.084 f u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/popCC_popPtr[2]_i_2__2/O net (fo=30, routed) 0.227 0.144 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/pushToPopGray_buffercc/buffers_0_reg[3]_0 SLICE_X65Y94 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/pushToPopGray_buffercc/buffers_1_reg[0]/CLR ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9603, routed) 0.923 -0.385 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/pushToPopGray_buffercc/sys_clk SLICE_X65Y94 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/pushToPopGray_buffercc/buffers_1_reg[0]/C clock pessimism -0.192 -0.577 SLICE_X65Y94 FDCE (Remov_fdce_C_CLR) -0.092 -0.669 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/pushToPopGray_buffercc/buffers_1_reg[0] ------------------------------------------------------------------- required time 0.669 arrival time 0.144 ------------------------------------------------------------------- slack 0.813 Slack (MET) : 0.813ns (arrival time - required time) Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/buffers_1_reg/C (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/pushToPopGray_buffercc/buffers_1_reg[1]/CLR (removal check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) Data Path Delay: 0.760ns (logic 0.246ns (32.373%) route 0.514ns (67.627%)) Logic Levels: 1 (LUT1=1) Clock Path Skew: 0.039ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.385ns Source Clock Delay (SCD): -0.616ns Clock Pessimism Removal (CPR): 0.192ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9603, routed) 0.646 -0.616 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/sys_clk SLICE_X68Y94 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/buffers_1_reg/C ------------------------------------------------------------------- ------------------- SLICE_X68Y94 FDCE (Prop_fdce_C_Q) 0.148 -0.468 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/buffers_1_reg/Q net (fo=1, routed) 0.286 -0.182 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/buffers_1 SLICE_X68Y94 LUT1 (Prop_lut1_I0_O) 0.098 -0.084 f u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/popCC_popPtr[2]_i_2__2/O net (fo=30, routed) 0.227 0.144 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/pushToPopGray_buffercc/buffers_0_reg[3]_0 SLICE_X65Y94 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/pushToPopGray_buffercc/buffers_1_reg[1]/CLR ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9603, routed) 0.923 -0.385 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/pushToPopGray_buffercc/sys_clk SLICE_X65Y94 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/pushToPopGray_buffercc/buffers_1_reg[1]/C clock pessimism -0.192 -0.577 SLICE_X65Y94 FDCE (Remov_fdce_C_CLR) -0.092 -0.669 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/pushToPopGray_buffercc/buffers_1_reg[1] ------------------------------------------------------------------- required time 0.669 arrival time 0.144 ------------------------------------------------------------------- slack 0.813 Slack (MET) : 0.822ns (arrival time - required time) Source: u_Axi_CDC/awFifo/bufferCC_12/buffers_1_reg/C (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: u_Axi_CDC/wFifo/pushToPopGray_buffercc/buffers_0_reg[0]/CLR (removal check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) Data Path Delay: 0.794ns (logic 0.246ns (30.984%) route 0.548ns (69.016%)) Logic Levels: 1 (LUT1=1) Clock Path Skew: 0.039ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.338ns Source Clock Delay (SCD): -0.569ns Clock Pessimism Removal (CPR): 0.192ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9603, routed) 0.693 -0.569 u_Axi_CDC/awFifo/bufferCC_12/sys_clk SLICE_X8Y60 FDCE r u_Axi_CDC/awFifo/bufferCC_12/buffers_1_reg/C ------------------------------------------------------------------- ------------------- SLICE_X8Y60 FDCE (Prop_fdce_C_Q) 0.148 -0.421 r u_Axi_CDC/awFifo/bufferCC_12/buffers_1_reg/Q net (fo=1, routed) 0.286 -0.135 u_Axi_CDC/awFifo/bufferCC_12/buffers_1 SLICE_X8Y60 LUT1 (Prop_lut1_I0_O) 0.098 -0.037 f u_Axi_CDC/awFifo/bufferCC_12/popCC_popPtr[2]_i_2/O net (fo=43, routed) 0.261 0.225 u_Axi_CDC/wFifo/pushToPopGray_buffercc/buffers_0_reg[3]_0 SLICE_X12Y59 FDCE f u_Axi_CDC/wFifo/pushToPopGray_buffercc/buffers_0_reg[0]/CLR ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9603, routed) 0.970 -0.338 u_Axi_CDC/wFifo/pushToPopGray_buffercc/sys_clk SLICE_X12Y59 FDCE r u_Axi_CDC/wFifo/pushToPopGray_buffercc/buffers_0_reg[0]/C clock pessimism -0.192 -0.530 SLICE_X12Y59 FDCE (Remov_fdce_C_CLR) -0.067 -0.597 u_Axi_CDC/wFifo/pushToPopGray_buffercc/buffers_0_reg[0] ------------------------------------------------------------------- required time 0.597 arrival time 0.225 ------------------------------------------------------------------- slack 0.822 Slack (MET) : 0.822ns (arrival time - required time) Source: u_Axi_CDC/awFifo/bufferCC_12/buffers_1_reg/C (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: u_Axi_CDC/wFifo/pushToPopGray_buffercc/buffers_0_reg[1]/CLR (removal check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) Data Path Delay: 0.794ns (logic 0.246ns (30.984%) route 0.548ns (69.016%)) Logic Levels: 1 (LUT1=1) Clock Path Skew: 0.039ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.338ns Source Clock Delay (SCD): -0.569ns Clock Pessimism Removal (CPR): 0.192ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9603, routed) 0.693 -0.569 u_Axi_CDC/awFifo/bufferCC_12/sys_clk SLICE_X8Y60 FDCE r u_Axi_CDC/awFifo/bufferCC_12/buffers_1_reg/C ------------------------------------------------------------------- ------------------- SLICE_X8Y60 FDCE (Prop_fdce_C_Q) 0.148 -0.421 r u_Axi_CDC/awFifo/bufferCC_12/buffers_1_reg/Q net (fo=1, routed) 0.286 -0.135 u_Axi_CDC/awFifo/bufferCC_12/buffers_1 SLICE_X8Y60 LUT1 (Prop_lut1_I0_O) 0.098 -0.037 f u_Axi_CDC/awFifo/bufferCC_12/popCC_popPtr[2]_i_2/O net (fo=43, routed) 0.261 0.225 u_Axi_CDC/wFifo/pushToPopGray_buffercc/buffers_0_reg[3]_0 SLICE_X12Y59 FDCE f u_Axi_CDC/wFifo/pushToPopGray_buffercc/buffers_0_reg[1]/CLR ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9603, routed) 0.970 -0.338 u_Axi_CDC/wFifo/pushToPopGray_buffercc/sys_clk SLICE_X12Y59 FDCE r u_Axi_CDC/wFifo/pushToPopGray_buffercc/buffers_0_reg[1]/C clock pessimism -0.192 -0.530 SLICE_X12Y59 FDCE (Remov_fdce_C_CLR) -0.067 -0.597 u_Axi_CDC/wFifo/pushToPopGray_buffercc/buffers_0_reg[1] ------------------------------------------------------------------- required time 0.597 arrival time 0.225 ------------------------------------------------------------------- slack 0.822 Slack (MET) : 0.822ns (arrival time - required time) Source: u_Axi_CDC/awFifo/bufferCC_12/buffers_1_reg/C (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: u_Axi_CDC/wFifo/pushToPopGray_buffercc/buffers_0_reg[2]/CLR (removal check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) Data Path Delay: 0.794ns (logic 0.246ns (30.984%) route 0.548ns (69.016%)) Logic Levels: 1 (LUT1=1) Clock Path Skew: 0.039ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.338ns Source Clock Delay (SCD): -0.569ns Clock Pessimism Removal (CPR): 0.192ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9603, routed) 0.693 -0.569 u_Axi_CDC/awFifo/bufferCC_12/sys_clk SLICE_X8Y60 FDCE r u_Axi_CDC/awFifo/bufferCC_12/buffers_1_reg/C ------------------------------------------------------------------- ------------------- SLICE_X8Y60 FDCE (Prop_fdce_C_Q) 0.148 -0.421 r u_Axi_CDC/awFifo/bufferCC_12/buffers_1_reg/Q net (fo=1, routed) 0.286 -0.135 u_Axi_CDC/awFifo/bufferCC_12/buffers_1 SLICE_X8Y60 LUT1 (Prop_lut1_I0_O) 0.098 -0.037 f u_Axi_CDC/awFifo/bufferCC_12/popCC_popPtr[2]_i_2/O net (fo=43, routed) 0.261 0.225 u_Axi_CDC/wFifo/pushToPopGray_buffercc/buffers_0_reg[3]_0 SLICE_X12Y59 FDCE f u_Axi_CDC/wFifo/pushToPopGray_buffercc/buffers_0_reg[2]/CLR ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9603, routed) 0.970 -0.338 u_Axi_CDC/wFifo/pushToPopGray_buffercc/sys_clk SLICE_X12Y59 FDCE r u_Axi_CDC/wFifo/pushToPopGray_buffercc/buffers_0_reg[2]/C clock pessimism -0.192 -0.530 SLICE_X12Y59 FDCE (Remov_fdce_C_CLR) -0.067 -0.597 u_Axi_CDC/wFifo/pushToPopGray_buffercc/buffers_0_reg[2] ------------------------------------------------------------------- required time 0.597 arrival time 0.225 ------------------------------------------------------------------- slack 0.822 Slack (MET) : 0.822ns (arrival time - required time) Source: u_Axi_CDC/awFifo/bufferCC_12/buffers_1_reg/C (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: u_Axi_CDC/wFifo/pushToPopGray_buffercc/buffers_0_reg[3]/CLR (removal check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) Data Path Delay: 0.794ns (logic 0.246ns (30.984%) route 0.548ns (69.016%)) Logic Levels: 1 (LUT1=1) Clock Path Skew: 0.039ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.338ns Source Clock Delay (SCD): -0.569ns Clock Pessimism Removal (CPR): 0.192ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9603, routed) 0.693 -0.569 u_Axi_CDC/awFifo/bufferCC_12/sys_clk SLICE_X8Y60 FDCE r u_Axi_CDC/awFifo/bufferCC_12/buffers_1_reg/C ------------------------------------------------------------------- ------------------- SLICE_X8Y60 FDCE (Prop_fdce_C_Q) 0.148 -0.421 r u_Axi_CDC/awFifo/bufferCC_12/buffers_1_reg/Q net (fo=1, routed) 0.286 -0.135 u_Axi_CDC/awFifo/bufferCC_12/buffers_1 SLICE_X8Y60 LUT1 (Prop_lut1_I0_O) 0.098 -0.037 f u_Axi_CDC/awFifo/bufferCC_12/popCC_popPtr[2]_i_2/O net (fo=43, routed) 0.261 0.225 u_Axi_CDC/wFifo/pushToPopGray_buffercc/buffers_0_reg[3]_0 SLICE_X12Y59 FDCE f u_Axi_CDC/wFifo/pushToPopGray_buffercc/buffers_0_reg[3]/CLR ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9603, routed) 0.970 -0.338 u_Axi_CDC/wFifo/pushToPopGray_buffercc/sys_clk SLICE_X12Y59 FDCE r u_Axi_CDC/wFifo/pushToPopGray_buffercc/buffers_0_reg[3]/C clock pessimism -0.192 -0.530 SLICE_X12Y59 FDCE (Remov_fdce_C_CLR) -0.067 -0.597 u_Axi_CDC/wFifo/pushToPopGray_buffercc/buffers_0_reg[3] ------------------------------------------------------------------- required time 0.597 arrival time 0.225 ------------------------------------------------------------------- slack 0.822 Slack (MET) : 0.822ns (arrival time - required time) Source: u_Axi_CDC/awFifo/bufferCC_12/buffers_1_reg/C (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: u_Axi_CDC/wFifo/pushToPopGray_buffercc/buffers_1_reg[0]/CLR (removal check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) Data Path Delay: 0.794ns (logic 0.246ns (30.984%) route 0.548ns (69.016%)) Logic Levels: 1 (LUT1=1) Clock Path Skew: 0.039ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.338ns Source Clock Delay (SCD): -0.569ns Clock Pessimism Removal (CPR): 0.192ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9603, routed) 0.693 -0.569 u_Axi_CDC/awFifo/bufferCC_12/sys_clk SLICE_X8Y60 FDCE r u_Axi_CDC/awFifo/bufferCC_12/buffers_1_reg/C ------------------------------------------------------------------- ------------------- SLICE_X8Y60 FDCE (Prop_fdce_C_Q) 0.148 -0.421 r u_Axi_CDC/awFifo/bufferCC_12/buffers_1_reg/Q net (fo=1, routed) 0.286 -0.135 u_Axi_CDC/awFifo/bufferCC_12/buffers_1 SLICE_X8Y60 LUT1 (Prop_lut1_I0_O) 0.098 -0.037 f u_Axi_CDC/awFifo/bufferCC_12/popCC_popPtr[2]_i_2/O net (fo=43, routed) 0.261 0.225 u_Axi_CDC/wFifo/pushToPopGray_buffercc/buffers_0_reg[3]_0 SLICE_X12Y59 FDCE f u_Axi_CDC/wFifo/pushToPopGray_buffercc/buffers_1_reg[0]/CLR ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9603, routed) 0.970 -0.338 u_Axi_CDC/wFifo/pushToPopGray_buffercc/sys_clk SLICE_X12Y59 FDCE r u_Axi_CDC/wFifo/pushToPopGray_buffercc/buffers_1_reg[0]/C clock pessimism -0.192 -0.530 SLICE_X12Y59 FDCE (Remov_fdce_C_CLR) -0.067 -0.597 u_Axi_CDC/wFifo/pushToPopGray_buffercc/buffers_1_reg[0] ------------------------------------------------------------------- required time 0.597 arrival time 0.225 ------------------------------------------------------------------- slack 0.822 Slack (MET) : 0.822ns (arrival time - required time) Source: u_Axi_CDC/awFifo/bufferCC_12/buffers_1_reg/C (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: u_Axi_CDC/wFifo/pushToPopGray_buffercc/buffers_1_reg[1]/CLR (removal check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) Data Path Delay: 0.794ns (logic 0.246ns (30.984%) route 0.548ns (69.016%)) Logic Levels: 1 (LUT1=1) Clock Path Skew: 0.039ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.338ns Source Clock Delay (SCD): -0.569ns Clock Pessimism Removal (CPR): 0.192ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9603, routed) 0.693 -0.569 u_Axi_CDC/awFifo/bufferCC_12/sys_clk SLICE_X8Y60 FDCE r u_Axi_CDC/awFifo/bufferCC_12/buffers_1_reg/C ------------------------------------------------------------------- ------------------- SLICE_X8Y60 FDCE (Prop_fdce_C_Q) 0.148 -0.421 r u_Axi_CDC/awFifo/bufferCC_12/buffers_1_reg/Q net (fo=1, routed) 0.286 -0.135 u_Axi_CDC/awFifo/bufferCC_12/buffers_1 SLICE_X8Y60 LUT1 (Prop_lut1_I0_O) 0.098 -0.037 f u_Axi_CDC/awFifo/bufferCC_12/popCC_popPtr[2]_i_2/O net (fo=43, routed) 0.261 0.225 u_Axi_CDC/wFifo/pushToPopGray_buffercc/buffers_0_reg[3]_0 SLICE_X12Y59 FDCE f u_Axi_CDC/wFifo/pushToPopGray_buffercc/buffers_1_reg[1]/CLR ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9603, routed) 0.970 -0.338 u_Axi_CDC/wFifo/pushToPopGray_buffercc/sys_clk SLICE_X12Y59 FDCE r u_Axi_CDC/wFifo/pushToPopGray_buffercc/buffers_1_reg[1]/C clock pessimism -0.192 -0.530 SLICE_X12Y59 FDCE (Remov_fdce_C_CLR) -0.067 -0.597 u_Axi_CDC/wFifo/pushToPopGray_buffercc/buffers_1_reg[1] ------------------------------------------------------------------- required time 0.597 arrival time 0.225 ------------------------------------------------------------------- slack 0.822 Slack (MET) : 0.822ns (arrival time - required time) Source: u_Axi_CDC/awFifo/bufferCC_12/buffers_1_reg/C (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: u_Axi_CDC/wFifo/pushToPopGray_buffercc/buffers_1_reg[2]/CLR (removal check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) Data Path Delay: 0.794ns (logic 0.246ns (30.984%) route 0.548ns (69.016%)) Logic Levels: 1 (LUT1=1) Clock Path Skew: 0.039ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.338ns Source Clock Delay (SCD): -0.569ns Clock Pessimism Removal (CPR): 0.192ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9603, routed) 0.693 -0.569 u_Axi_CDC/awFifo/bufferCC_12/sys_clk SLICE_X8Y60 FDCE r u_Axi_CDC/awFifo/bufferCC_12/buffers_1_reg/C ------------------------------------------------------------------- ------------------- SLICE_X8Y60 FDCE (Prop_fdce_C_Q) 0.148 -0.421 r u_Axi_CDC/awFifo/bufferCC_12/buffers_1_reg/Q net (fo=1, routed) 0.286 -0.135 u_Axi_CDC/awFifo/bufferCC_12/buffers_1 SLICE_X8Y60 LUT1 (Prop_lut1_I0_O) 0.098 -0.037 f u_Axi_CDC/awFifo/bufferCC_12/popCC_popPtr[2]_i_2/O net (fo=43, routed) 0.261 0.225 u_Axi_CDC/wFifo/pushToPopGray_buffercc/buffers_0_reg[3]_0 SLICE_X12Y59 FDCE f u_Axi_CDC/wFifo/pushToPopGray_buffercc/buffers_1_reg[2]/CLR ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9603, routed) 0.970 -0.338 u_Axi_CDC/wFifo/pushToPopGray_buffercc/sys_clk SLICE_X12Y59 FDCE r u_Axi_CDC/wFifo/pushToPopGray_buffercc/buffers_1_reg[2]/C clock pessimism -0.192 -0.530 SLICE_X12Y59 FDCE (Remov_fdce_C_CLR) -0.067 -0.597 u_Axi_CDC/wFifo/pushToPopGray_buffercc/buffers_1_reg[2] ------------------------------------------------------------------- required time 0.597 arrival time 0.225 ------------------------------------------------------------------- slack 0.822 Slack (MET) : 0.822ns (arrival time - required time) Source: u_Axi_CDC/awFifo/bufferCC_12/buffers_1_reg/C (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: u_Axi_CDC/wFifo/pushToPopGray_buffercc/buffers_1_reg[3]/CLR (removal check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) Data Path Delay: 0.794ns (logic 0.246ns (30.984%) route 0.548ns (69.016%)) Logic Levels: 1 (LUT1=1) Clock Path Skew: 0.039ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.338ns Source Clock Delay (SCD): -0.569ns Clock Pessimism Removal (CPR): 0.192ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9603, routed) 0.693 -0.569 u_Axi_CDC/awFifo/bufferCC_12/sys_clk SLICE_X8Y60 FDCE r u_Axi_CDC/awFifo/bufferCC_12/buffers_1_reg/C ------------------------------------------------------------------- ------------------- SLICE_X8Y60 FDCE (Prop_fdce_C_Q) 0.148 -0.421 r u_Axi_CDC/awFifo/bufferCC_12/buffers_1_reg/Q net (fo=1, routed) 0.286 -0.135 u_Axi_CDC/awFifo/bufferCC_12/buffers_1 SLICE_X8Y60 LUT1 (Prop_lut1_I0_O) 0.098 -0.037 f u_Axi_CDC/awFifo/bufferCC_12/popCC_popPtr[2]_i_2/O net (fo=43, routed) 0.261 0.225 u_Axi_CDC/wFifo/pushToPopGray_buffercc/buffers_0_reg[3]_0 SLICE_X12Y59 FDCE f u_Axi_CDC/wFifo/pushToPopGray_buffercc/buffers_1_reg[3]/CLR ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9603, routed) 0.970 -0.338 u_Axi_CDC/wFifo/pushToPopGray_buffercc/sys_clk SLICE_X12Y59 FDCE r u_Axi_CDC/wFifo/pushToPopGray_buffercc/buffers_1_reg[3]/C clock pessimism -0.192 -0.530 SLICE_X12Y59 FDCE (Remov_fdce_C_CLR) -0.067 -0.597 u_Axi_CDC/wFifo/pushToPopGray_buffercc/buffers_1_reg[3] ------------------------------------------------------------------- required time 0.597 arrival time 0.225 ------------------------------------------------------------------- slack 0.822 Slack (MET) : 0.847ns (arrival time - required time) Source: u_Axi_CDC/awFifo/bufferCC_12/buffers_1_reg/C (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: u_Axi_CDC/wFifo/popCC_ptrToPush_reg[0]/CLR (removal check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) Data Path Delay: 0.794ns (logic 0.246ns (30.984%) route 0.548ns (69.016%)) Logic Levels: 1 (LUT1=1) Clock Path Skew: 0.039ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.338ns Source Clock Delay (SCD): -0.569ns Clock Pessimism Removal (CPR): 0.192ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9603, routed) 0.693 -0.569 u_Axi_CDC/awFifo/bufferCC_12/sys_clk SLICE_X8Y60 FDCE r u_Axi_CDC/awFifo/bufferCC_12/buffers_1_reg/C ------------------------------------------------------------------- ------------------- SLICE_X8Y60 FDCE (Prop_fdce_C_Q) 0.148 -0.421 r u_Axi_CDC/awFifo/bufferCC_12/buffers_1_reg/Q net (fo=1, routed) 0.286 -0.135 u_Axi_CDC/awFifo/bufferCC_12/buffers_1 SLICE_X8Y60 LUT1 (Prop_lut1_I0_O) 0.098 -0.037 f u_Axi_CDC/awFifo/bufferCC_12/popCC_popPtr[2]_i_2/O net (fo=43, routed) 0.261 0.225 u_Axi_CDC/wFifo/buffers_0_reg[3] SLICE_X13Y59 FDCE f u_Axi_CDC/wFifo/popCC_ptrToPush_reg[0]/CLR ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9603, routed) 0.970 -0.338 u_Axi_CDC/wFifo/sys_clk SLICE_X13Y59 FDCE r u_Axi_CDC/wFifo/popCC_ptrToPush_reg[0]/C clock pessimism -0.192 -0.530 SLICE_X13Y59 FDCE (Remov_fdce_C_CLR) -0.092 -0.622 u_Axi_CDC/wFifo/popCC_ptrToPush_reg[0] ------------------------------------------------------------------- required time 0.622 arrival time 0.225 ------------------------------------------------------------------- slack 0.847 Slack (MET) : 0.847ns (arrival time - required time) Source: u_Axi_CDC/awFifo/bufferCC_12/buffers_1_reg/C (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: u_Axi_CDC/wFifo/popCC_ptrToPush_reg[1]/CLR (removal check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) Data Path Delay: 0.794ns (logic 0.246ns (30.984%) route 0.548ns (69.016%)) Logic Levels: 1 (LUT1=1) Clock Path Skew: 0.039ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.338ns Source Clock Delay (SCD): -0.569ns Clock Pessimism Removal (CPR): 0.192ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9603, routed) 0.693 -0.569 u_Axi_CDC/awFifo/bufferCC_12/sys_clk SLICE_X8Y60 FDCE r u_Axi_CDC/awFifo/bufferCC_12/buffers_1_reg/C ------------------------------------------------------------------- ------------------- SLICE_X8Y60 FDCE (Prop_fdce_C_Q) 0.148 -0.421 r u_Axi_CDC/awFifo/bufferCC_12/buffers_1_reg/Q net (fo=1, routed) 0.286 -0.135 u_Axi_CDC/awFifo/bufferCC_12/buffers_1 SLICE_X8Y60 LUT1 (Prop_lut1_I0_O) 0.098 -0.037 f u_Axi_CDC/awFifo/bufferCC_12/popCC_popPtr[2]_i_2/O net (fo=43, routed) 0.261 0.225 u_Axi_CDC/wFifo/buffers_0_reg[3] SLICE_X13Y59 FDCE f u_Axi_CDC/wFifo/popCC_ptrToPush_reg[1]/CLR ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9603, routed) 0.970 -0.338 u_Axi_CDC/wFifo/sys_clk SLICE_X13Y59 FDCE r u_Axi_CDC/wFifo/popCC_ptrToPush_reg[1]/C clock pessimism -0.192 -0.530 SLICE_X13Y59 FDCE (Remov_fdce_C_CLR) -0.092 -0.622 u_Axi_CDC/wFifo/popCC_ptrToPush_reg[1] ------------------------------------------------------------------- required time 0.622 arrival time 0.225 ------------------------------------------------------------------- slack 0.847 Slack (MET) : 0.847ns (arrival time - required time) Source: u_Axi_CDC/awFifo/bufferCC_12/buffers_1_reg/C (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: u_Axi_CDC/wFifo/popCC_ptrToPush_reg[2]/CLR (removal check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) Data Path Delay: 0.794ns (logic 0.246ns (30.984%) route 0.548ns (69.016%)) Logic Levels: 1 (LUT1=1) Clock Path Skew: 0.039ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.338ns Source Clock Delay (SCD): -0.569ns Clock Pessimism Removal (CPR): 0.192ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9603, routed) 0.693 -0.569 u_Axi_CDC/awFifo/bufferCC_12/sys_clk SLICE_X8Y60 FDCE r u_Axi_CDC/awFifo/bufferCC_12/buffers_1_reg/C ------------------------------------------------------------------- ------------------- SLICE_X8Y60 FDCE (Prop_fdce_C_Q) 0.148 -0.421 r u_Axi_CDC/awFifo/bufferCC_12/buffers_1_reg/Q net (fo=1, routed) 0.286 -0.135 u_Axi_CDC/awFifo/bufferCC_12/buffers_1 SLICE_X8Y60 LUT1 (Prop_lut1_I0_O) 0.098 -0.037 f u_Axi_CDC/awFifo/bufferCC_12/popCC_popPtr[2]_i_2/O net (fo=43, routed) 0.261 0.225 u_Axi_CDC/wFifo/buffers_0_reg[3] SLICE_X13Y59 FDCE f u_Axi_CDC/wFifo/popCC_ptrToPush_reg[2]/CLR ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9603, routed) 0.970 -0.338 u_Axi_CDC/wFifo/sys_clk SLICE_X13Y59 FDCE r u_Axi_CDC/wFifo/popCC_ptrToPush_reg[2]/C clock pessimism -0.192 -0.530 SLICE_X13Y59 FDCE (Remov_fdce_C_CLR) -0.092 -0.622 u_Axi_CDC/wFifo/popCC_ptrToPush_reg[2] ------------------------------------------------------------------- required time 0.622 arrival time 0.225 ------------------------------------------------------------------- slack 0.847 Slack (MET) : 0.847ns (arrival time - required time) Source: u_Axi_CDC/awFifo/bufferCC_12/buffers_1_reg/C (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: u_Axi_CDC/wFifo/popCC_ptrToPush_reg[3]/CLR (removal check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) Data Path Delay: 0.794ns (logic 0.246ns (30.984%) route 0.548ns (69.016%)) Logic Levels: 1 (LUT1=1) Clock Path Skew: 0.039ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.338ns Source Clock Delay (SCD): -0.569ns Clock Pessimism Removal (CPR): 0.192ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9603, routed) 0.693 -0.569 u_Axi_CDC/awFifo/bufferCC_12/sys_clk SLICE_X8Y60 FDCE r u_Axi_CDC/awFifo/bufferCC_12/buffers_1_reg/C ------------------------------------------------------------------- ------------------- SLICE_X8Y60 FDCE (Prop_fdce_C_Q) 0.148 -0.421 r u_Axi_CDC/awFifo/bufferCC_12/buffers_1_reg/Q net (fo=1, routed) 0.286 -0.135 u_Axi_CDC/awFifo/bufferCC_12/buffers_1 SLICE_X8Y60 LUT1 (Prop_lut1_I0_O) 0.098 -0.037 f u_Axi_CDC/awFifo/bufferCC_12/popCC_popPtr[2]_i_2/O net (fo=43, routed) 0.261 0.225 u_Axi_CDC/wFifo/buffers_0_reg[3] SLICE_X13Y59 FDCE f u_Axi_CDC/wFifo/popCC_ptrToPush_reg[3]/CLR ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9603, routed) 0.970 -0.338 u_Axi_CDC/wFifo/sys_clk SLICE_X13Y59 FDCE r u_Axi_CDC/wFifo/popCC_ptrToPush_reg[3]/C clock pessimism -0.192 -0.530 SLICE_X13Y59 FDCE (Remov_fdce_C_CLR) -0.092 -0.622 u_Axi_CDC/wFifo/popCC_ptrToPush_reg[3] ------------------------------------------------------------------- required time 0.622 arrival time 0.225 ------------------------------------------------------------------- slack 0.847 Slack (MET) : 0.857ns (arrival time - required time) Source: u_Axi_CDC/awFifo/bufferCC_12/buffers_1_reg/C (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: u_Axi_CDC/wFifo/popCC_popPtr_reg[0]/CLR (removal check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) Data Path Delay: 0.829ns (logic 0.246ns (29.675%) route 0.583ns (70.325%)) Logic Levels: 1 (LUT1=1) Clock Path Skew: 0.039ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.338ns Source Clock Delay (SCD): -0.569ns Clock Pessimism Removal (CPR): 0.192ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9603, routed) 0.693 -0.569 u_Axi_CDC/awFifo/bufferCC_12/sys_clk SLICE_X8Y60 FDCE r u_Axi_CDC/awFifo/bufferCC_12/buffers_1_reg/C ------------------------------------------------------------------- ------------------- SLICE_X8Y60 FDCE (Prop_fdce_C_Q) 0.148 -0.421 r u_Axi_CDC/awFifo/bufferCC_12/buffers_1_reg/Q net (fo=1, routed) 0.286 -0.135 u_Axi_CDC/awFifo/bufferCC_12/buffers_1 SLICE_X8Y60 LUT1 (Prop_lut1_I0_O) 0.098 -0.037 f u_Axi_CDC/awFifo/bufferCC_12/popCC_popPtr[2]_i_2/O net (fo=43, routed) 0.296 0.260 u_Axi_CDC/wFifo/buffers_0_reg[3] SLICE_X12Y58 FDCE f u_Axi_CDC/wFifo/popCC_popPtr_reg[0]/CLR ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9603, routed) 0.970 -0.338 u_Axi_CDC/wFifo/sys_clk SLICE_X12Y58 FDCE r u_Axi_CDC/wFifo/popCC_popPtr_reg[0]/C clock pessimism -0.192 -0.530 SLICE_X12Y58 FDCE (Remov_fdce_C_CLR) -0.067 -0.597 u_Axi_CDC/wFifo/popCC_popPtr_reg[0] ------------------------------------------------------------------- required time 0.597 arrival time 0.260 ------------------------------------------------------------------- slack 0.857 Slack (MET) : 0.857ns (arrival time - required time) Source: u_Axi_CDC/awFifo/bufferCC_12/buffers_1_reg/C (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: u_Axi_CDC/wFifo/popCC_popPtr_reg[1]/CLR (removal check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) Data Path Delay: 0.829ns (logic 0.246ns (29.675%) route 0.583ns (70.325%)) Logic Levels: 1 (LUT1=1) Clock Path Skew: 0.039ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.338ns Source Clock Delay (SCD): -0.569ns Clock Pessimism Removal (CPR): 0.192ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9603, routed) 0.693 -0.569 u_Axi_CDC/awFifo/bufferCC_12/sys_clk SLICE_X8Y60 FDCE r u_Axi_CDC/awFifo/bufferCC_12/buffers_1_reg/C ------------------------------------------------------------------- ------------------- SLICE_X8Y60 FDCE (Prop_fdce_C_Q) 0.148 -0.421 r u_Axi_CDC/awFifo/bufferCC_12/buffers_1_reg/Q net (fo=1, routed) 0.286 -0.135 u_Axi_CDC/awFifo/bufferCC_12/buffers_1 SLICE_X8Y60 LUT1 (Prop_lut1_I0_O) 0.098 -0.037 f u_Axi_CDC/awFifo/bufferCC_12/popCC_popPtr[2]_i_2/O net (fo=43, routed) 0.296 0.260 u_Axi_CDC/wFifo/buffers_0_reg[3] SLICE_X12Y58 FDCE f u_Axi_CDC/wFifo/popCC_popPtr_reg[1]/CLR ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9603, routed) 0.970 -0.338 u_Axi_CDC/wFifo/sys_clk SLICE_X12Y58 FDCE r u_Axi_CDC/wFifo/popCC_popPtr_reg[1]/C clock pessimism -0.192 -0.530 SLICE_X12Y58 FDCE (Remov_fdce_C_CLR) -0.067 -0.597 u_Axi_CDC/wFifo/popCC_popPtr_reg[1] ------------------------------------------------------------------- required time 0.597 arrival time 0.260 ------------------------------------------------------------------- slack 0.857 Slack (MET) : 0.857ns (arrival time - required time) Source: u_Axi_CDC/awFifo/bufferCC_12/buffers_1_reg/C (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: u_Axi_CDC/wFifo/popCC_popPtr_reg[2]/CLR (removal check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) Data Path Delay: 0.829ns (logic 0.246ns (29.675%) route 0.583ns (70.325%)) Logic Levels: 1 (LUT1=1) Clock Path Skew: 0.039ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.338ns Source Clock Delay (SCD): -0.569ns Clock Pessimism Removal (CPR): 0.192ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9603, routed) 0.693 -0.569 u_Axi_CDC/awFifo/bufferCC_12/sys_clk SLICE_X8Y60 FDCE r u_Axi_CDC/awFifo/bufferCC_12/buffers_1_reg/C ------------------------------------------------------------------- ------------------- SLICE_X8Y60 FDCE (Prop_fdce_C_Q) 0.148 -0.421 r u_Axi_CDC/awFifo/bufferCC_12/buffers_1_reg/Q net (fo=1, routed) 0.286 -0.135 u_Axi_CDC/awFifo/bufferCC_12/buffers_1 SLICE_X8Y60 LUT1 (Prop_lut1_I0_O) 0.098 -0.037 f u_Axi_CDC/awFifo/bufferCC_12/popCC_popPtr[2]_i_2/O net (fo=43, routed) 0.296 0.260 u_Axi_CDC/wFifo/buffers_0_reg[3] SLICE_X12Y58 FDCE f u_Axi_CDC/wFifo/popCC_popPtr_reg[2]/CLR ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9603, routed) 0.970 -0.338 u_Axi_CDC/wFifo/sys_clk SLICE_X12Y58 FDCE r u_Axi_CDC/wFifo/popCC_popPtr_reg[2]/C clock pessimism -0.192 -0.530 SLICE_X12Y58 FDCE (Remov_fdce_C_CLR) -0.067 -0.597 u_Axi_CDC/wFifo/popCC_popPtr_reg[2] ------------------------------------------------------------------- required time 0.597 arrival time 0.260 ------------------------------------------------------------------- slack 0.857 Slack (MET) : 0.857ns (arrival time - required time) Source: u_Axi_CDC/awFifo/bufferCC_12/buffers_1_reg/C (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: u_Axi_CDC/wFifo/popCC_popPtr_reg[3]/CLR (removal check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) Data Path Delay: 0.829ns (logic 0.246ns (29.675%) route 0.583ns (70.325%)) Logic Levels: 1 (LUT1=1) Clock Path Skew: 0.039ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.338ns Source Clock Delay (SCD): -0.569ns Clock Pessimism Removal (CPR): 0.192ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9603, routed) 0.693 -0.569 u_Axi_CDC/awFifo/bufferCC_12/sys_clk SLICE_X8Y60 FDCE r u_Axi_CDC/awFifo/bufferCC_12/buffers_1_reg/C ------------------------------------------------------------------- ------------------- SLICE_X8Y60 FDCE (Prop_fdce_C_Q) 0.148 -0.421 r u_Axi_CDC/awFifo/bufferCC_12/buffers_1_reg/Q net (fo=1, routed) 0.286 -0.135 u_Axi_CDC/awFifo/bufferCC_12/buffers_1 SLICE_X8Y60 LUT1 (Prop_lut1_I0_O) 0.098 -0.037 f u_Axi_CDC/awFifo/bufferCC_12/popCC_popPtr[2]_i_2/O net (fo=43, routed) 0.296 0.260 u_Axi_CDC/wFifo/buffers_0_reg[3] SLICE_X12Y58 FDCE f u_Axi_CDC/wFifo/popCC_popPtr_reg[3]/CLR ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9603, routed) 0.970 -0.338 u_Axi_CDC/wFifo/sys_clk SLICE_X12Y58 FDCE r u_Axi_CDC/wFifo/popCC_popPtr_reg[3]/C clock pessimism -0.192 -0.530 SLICE_X12Y58 FDCE (Remov_fdce_C_CLR) -0.067 -0.597 u_Axi_CDC/wFifo/popCC_popPtr_reg[3] ------------------------------------------------------------------- required time 0.597 arrival time 0.260 ------------------------------------------------------------------- slack 0.857 Slack (MET) : 0.875ns (arrival time - required time) Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/buffers_1_reg/C (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/pushToPopGray_buffercc/buffers_0_reg[0]/CLR (removal check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) Data Path Delay: 0.824ns (logic 0.246ns (29.858%) route 0.578ns (70.142%)) Logic Levels: 1 (LUT1=1) Clock Path Skew: 0.016ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.387ns Source Clock Delay (SCD): -0.616ns Clock Pessimism Removal (CPR): 0.213ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9603, routed) 0.646 -0.616 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/sys_clk SLICE_X68Y94 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/buffers_1_reg/C ------------------------------------------------------------------- ------------------- SLICE_X68Y94 FDCE (Prop_fdce_C_Q) 0.148 -0.468 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/buffers_1_reg/Q net (fo=1, routed) 0.286 -0.182 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/buffers_1 SLICE_X68Y94 LUT1 (Prop_lut1_I0_O) 0.098 -0.084 f u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/popCC_popPtr[2]_i_2__2/O net (fo=30, routed) 0.291 0.208 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/pushToPopGray_buffercc/buffers_0_reg[2]_1 SLICE_X66Y96 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/pushToPopGray_buffercc/buffers_0_reg[0]/CLR ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9603, routed) 0.921 -0.387 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/pushToPopGray_buffercc/sys_clk SLICE_X66Y96 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/pushToPopGray_buffercc/buffers_0_reg[0]/C clock pessimism -0.213 -0.600 SLICE_X66Y96 FDCE (Remov_fdce_C_CLR) -0.067 -0.667 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/pushToPopGray_buffercc/buffers_0_reg[0] ------------------------------------------------------------------- required time 0.667 arrival time 0.208 ------------------------------------------------------------------- slack 0.875 Slack (MET) : 0.875ns (arrival time - required time) Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/buffers_1_reg/C (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/pushToPopGray_buffercc/buffers_0_reg[1]/CLR (removal check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) Data Path Delay: 0.824ns (logic 0.246ns (29.858%) route 0.578ns (70.142%)) Logic Levels: 1 (LUT1=1) Clock Path Skew: 0.016ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.387ns Source Clock Delay (SCD): -0.616ns Clock Pessimism Removal (CPR): 0.213ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9603, routed) 0.646 -0.616 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/sys_clk SLICE_X68Y94 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/buffers_1_reg/C ------------------------------------------------------------------- ------------------- SLICE_X68Y94 FDCE (Prop_fdce_C_Q) 0.148 -0.468 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/buffers_1_reg/Q net (fo=1, routed) 0.286 -0.182 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/buffers_1 SLICE_X68Y94 LUT1 (Prop_lut1_I0_O) 0.098 -0.084 f u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/popCC_popPtr[2]_i_2__2/O net (fo=30, routed) 0.291 0.208 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/pushToPopGray_buffercc/buffers_0_reg[2]_1 SLICE_X66Y96 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/pushToPopGray_buffercc/buffers_0_reg[1]/CLR ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9603, routed) 0.921 -0.387 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/pushToPopGray_buffercc/sys_clk SLICE_X66Y96 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/pushToPopGray_buffercc/buffers_0_reg[1]/C clock pessimism -0.213 -0.600 SLICE_X66Y96 FDCE (Remov_fdce_C_CLR) -0.067 -0.667 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/pushToPopGray_buffercc/buffers_0_reg[1] ------------------------------------------------------------------- required time 0.667 arrival time 0.208 ------------------------------------------------------------------- slack 0.875 Slack (MET) : 0.875ns (arrival time - required time) Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/buffers_1_reg/C (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/pushToPopGray_buffercc/buffers_0_reg[2]/CLR (removal check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) Data Path Delay: 0.824ns (logic 0.246ns (29.858%) route 0.578ns (70.142%)) Logic Levels: 1 (LUT1=1) Clock Path Skew: 0.016ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.387ns Source Clock Delay (SCD): -0.616ns Clock Pessimism Removal (CPR): 0.213ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9603, routed) 0.646 -0.616 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/sys_clk SLICE_X68Y94 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/buffers_1_reg/C ------------------------------------------------------------------- ------------------- SLICE_X68Y94 FDCE (Prop_fdce_C_Q) 0.148 -0.468 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/buffers_1_reg/Q net (fo=1, routed) 0.286 -0.182 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/buffers_1 SLICE_X68Y94 LUT1 (Prop_lut1_I0_O) 0.098 -0.084 f u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/popCC_popPtr[2]_i_2__2/O net (fo=30, routed) 0.291 0.208 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/pushToPopGray_buffercc/buffers_0_reg[2]_1 SLICE_X66Y96 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/pushToPopGray_buffercc/buffers_0_reg[2]/CLR ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9603, routed) 0.921 -0.387 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/pushToPopGray_buffercc/sys_clk SLICE_X66Y96 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/pushToPopGray_buffercc/buffers_0_reg[2]/C clock pessimism -0.213 -0.600 SLICE_X66Y96 FDCE (Remov_fdce_C_CLR) -0.067 -0.667 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/pushToPopGray_buffercc/buffers_0_reg[2] ------------------------------------------------------------------- required time 0.667 arrival time 0.208 ------------------------------------------------------------------- slack 0.875 Slack (MET) : 0.875ns (arrival time - required time) Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/buffers_1_reg/C (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/pushToPopGray_buffercc/buffers_1_reg[0]/CLR (removal check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) Data Path Delay: 0.824ns (logic 0.246ns (29.858%) route 0.578ns (70.142%)) Logic Levels: 1 (LUT1=1) Clock Path Skew: 0.016ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.387ns Source Clock Delay (SCD): -0.616ns Clock Pessimism Removal (CPR): 0.213ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9603, routed) 0.646 -0.616 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/sys_clk SLICE_X68Y94 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/buffers_1_reg/C ------------------------------------------------------------------- ------------------- SLICE_X68Y94 FDCE (Prop_fdce_C_Q) 0.148 -0.468 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/buffers_1_reg/Q net (fo=1, routed) 0.286 -0.182 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/buffers_1 SLICE_X68Y94 LUT1 (Prop_lut1_I0_O) 0.098 -0.084 f u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/popCC_popPtr[2]_i_2__2/O net (fo=30, routed) 0.291 0.208 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/pushToPopGray_buffercc/buffers_0_reg[2]_1 SLICE_X66Y96 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/pushToPopGray_buffercc/buffers_1_reg[0]/CLR ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9603, routed) 0.921 -0.387 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/pushToPopGray_buffercc/sys_clk SLICE_X66Y96 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/pushToPopGray_buffercc/buffers_1_reg[0]/C clock pessimism -0.213 -0.600 SLICE_X66Y96 FDCE (Remov_fdce_C_CLR) -0.067 -0.667 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/pushToPopGray_buffercc/buffers_1_reg[0] ------------------------------------------------------------------- required time 0.667 arrival time 0.208 ------------------------------------------------------------------- slack 0.875 Slack (MET) : 0.875ns (arrival time - required time) Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/buffers_1_reg/C (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/pushToPopGray_buffercc/buffers_1_reg[1]/CLR (removal check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) Data Path Delay: 0.824ns (logic 0.246ns (29.858%) route 0.578ns (70.142%)) Logic Levels: 1 (LUT1=1) Clock Path Skew: 0.016ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.387ns Source Clock Delay (SCD): -0.616ns Clock Pessimism Removal (CPR): 0.213ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9603, routed) 0.646 -0.616 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/sys_clk SLICE_X68Y94 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/buffers_1_reg/C ------------------------------------------------------------------- ------------------- SLICE_X68Y94 FDCE (Prop_fdce_C_Q) 0.148 -0.468 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/buffers_1_reg/Q net (fo=1, routed) 0.286 -0.182 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/buffers_1 SLICE_X68Y94 LUT1 (Prop_lut1_I0_O) 0.098 -0.084 f u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/popCC_popPtr[2]_i_2__2/O net (fo=30, routed) 0.291 0.208 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/pushToPopGray_buffercc/buffers_0_reg[2]_1 SLICE_X66Y96 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/pushToPopGray_buffercc/buffers_1_reg[1]/CLR ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9603, routed) 0.921 -0.387 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/pushToPopGray_buffercc/sys_clk SLICE_X66Y96 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/pushToPopGray_buffercc/buffers_1_reg[1]/C clock pessimism -0.213 -0.600 SLICE_X66Y96 FDCE (Remov_fdce_C_CLR) -0.067 -0.667 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/pushToPopGray_buffercc/buffers_1_reg[1] ------------------------------------------------------------------- required time 0.667 arrival time 0.208 ------------------------------------------------------------------- slack 0.875 Slack (MET) : 0.875ns (arrival time - required time) Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/buffers_1_reg/C (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/pushToPopGray_buffercc/buffers_1_reg[2]/CLR (removal check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) Data Path Delay: 0.824ns (logic 0.246ns (29.858%) route 0.578ns (70.142%)) Logic Levels: 1 (LUT1=1) Clock Path Skew: 0.016ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.387ns Source Clock Delay (SCD): -0.616ns Clock Pessimism Removal (CPR): 0.213ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9603, routed) 0.646 -0.616 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/sys_clk SLICE_X68Y94 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/buffers_1_reg/C ------------------------------------------------------------------- ------------------- SLICE_X68Y94 FDCE (Prop_fdce_C_Q) 0.148 -0.468 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/buffers_1_reg/Q net (fo=1, routed) 0.286 -0.182 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/buffers_1 SLICE_X68Y94 LUT1 (Prop_lut1_I0_O) 0.098 -0.084 f u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/popCC_popPtr[2]_i_2__2/O net (fo=30, routed) 0.291 0.208 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/pushToPopGray_buffercc/buffers_0_reg[2]_1 SLICE_X66Y96 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/pushToPopGray_buffercc/buffers_1_reg[2]/CLR ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9603, routed) 0.921 -0.387 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/pushToPopGray_buffercc/sys_clk SLICE_X66Y96 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/pushToPopGray_buffercc/buffers_1_reg[2]/C clock pessimism -0.213 -0.600 SLICE_X66Y96 FDCE (Remov_fdce_C_CLR) -0.067 -0.667 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/pushToPopGray_buffercc/buffers_1_reg[2] ------------------------------------------------------------------- required time 0.667 arrival time 0.208 ------------------------------------------------------------------- slack 0.875 Slack (MET) : 0.877ns (arrival time - required time) Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/buffers_1_reg/C (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/popCC_popPtr_reg[0]/CLR (removal check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) Data Path Delay: 0.824ns (logic 0.246ns (29.846%) route 0.578ns (70.154%)) Logic Levels: 1 (LUT1=1) Clock Path Skew: 0.039ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.385ns Source Clock Delay (SCD): -0.616ns Clock Pessimism Removal (CPR): 0.192ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9603, routed) 0.646 -0.616 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/sys_clk SLICE_X68Y94 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/buffers_1_reg/C ------------------------------------------------------------------- ------------------- SLICE_X68Y94 FDCE (Prop_fdce_C_Q) 0.148 -0.468 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/buffers_1_reg/Q net (fo=1, routed) 0.286 -0.182 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/buffers_1 SLICE_X68Y94 LUT1 (Prop_lut1_I0_O) 0.098 -0.084 f u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/popCC_popPtr[2]_i_2__2/O net (fo=30, routed) 0.292 0.208 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/buffers_0_reg[3] SLICE_X65Y93 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/popCC_popPtr_reg[0]/CLR ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9603, routed) 0.923 -0.385 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/sys_clk SLICE_X65Y93 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/popCC_popPtr_reg[0]/C clock pessimism -0.192 -0.577 SLICE_X65Y93 FDCE (Remov_fdce_C_CLR) -0.092 -0.669 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/popCC_popPtr_reg[0] ------------------------------------------------------------------- required time 0.669 arrival time 0.208 ------------------------------------------------------------------- slack 0.877 Slack (MET) : 0.877ns (arrival time - required time) Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/buffers_1_reg/C (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/popCC_popPtr_reg[1]/CLR (removal check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) Data Path Delay: 0.824ns (logic 0.246ns (29.846%) route 0.578ns (70.154%)) Logic Levels: 1 (LUT1=1) Clock Path Skew: 0.039ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.385ns Source Clock Delay (SCD): -0.616ns Clock Pessimism Removal (CPR): 0.192ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9603, routed) 0.646 -0.616 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/sys_clk SLICE_X68Y94 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/buffers_1_reg/C ------------------------------------------------------------------- ------------------- SLICE_X68Y94 FDCE (Prop_fdce_C_Q) 0.148 -0.468 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/buffers_1_reg/Q net (fo=1, routed) 0.286 -0.182 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/buffers_1 SLICE_X68Y94 LUT1 (Prop_lut1_I0_O) 0.098 -0.084 f u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/popCC_popPtr[2]_i_2__2/O net (fo=30, routed) 0.292 0.208 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/buffers_0_reg[3] SLICE_X65Y93 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/popCC_popPtr_reg[1]/CLR ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9603, routed) 0.923 -0.385 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/sys_clk SLICE_X65Y93 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/popCC_popPtr_reg[1]/C clock pessimism -0.192 -0.577 SLICE_X65Y93 FDCE (Remov_fdce_C_CLR) -0.092 -0.669 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/popCC_popPtr_reg[1] ------------------------------------------------------------------- required time 0.669 arrival time 0.208 ------------------------------------------------------------------- slack 0.877 Slack (MET) : 0.877ns (arrival time - required time) Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/buffers_1_reg/C (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/popCC_popPtr_reg[2]/CLR (removal check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) Data Path Delay: 0.824ns (logic 0.246ns (29.846%) route 0.578ns (70.154%)) Logic Levels: 1 (LUT1=1) Clock Path Skew: 0.039ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.385ns Source Clock Delay (SCD): -0.616ns Clock Pessimism Removal (CPR): 0.192ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9603, routed) 0.646 -0.616 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/sys_clk SLICE_X68Y94 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/buffers_1_reg/C ------------------------------------------------------------------- ------------------- SLICE_X68Y94 FDCE (Prop_fdce_C_Q) 0.148 -0.468 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/buffers_1_reg/Q net (fo=1, routed) 0.286 -0.182 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/buffers_1 SLICE_X68Y94 LUT1 (Prop_lut1_I0_O) 0.098 -0.084 f u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/popCC_popPtr[2]_i_2__2/O net (fo=30, routed) 0.292 0.208 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/buffers_0_reg[3] SLICE_X65Y93 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/popCC_popPtr_reg[2]/CLR ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9603, routed) 0.923 -0.385 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/sys_clk SLICE_X65Y93 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/popCC_popPtr_reg[2]/C clock pessimism -0.192 -0.577 SLICE_X65Y93 FDCE (Remov_fdce_C_CLR) -0.092 -0.669 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/popCC_popPtr_reg[2] ------------------------------------------------------------------- required time 0.669 arrival time 0.208 ------------------------------------------------------------------- slack 0.877 Slack (MET) : 0.877ns (arrival time - required time) Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/buffers_1_reg/C (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/popCC_popPtr_reg[3]/CLR (removal check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) Data Path Delay: 0.824ns (logic 0.246ns (29.846%) route 0.578ns (70.154%)) Logic Levels: 1 (LUT1=1) Clock Path Skew: 0.039ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.385ns Source Clock Delay (SCD): -0.616ns Clock Pessimism Removal (CPR): 0.192ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9603, routed) 0.646 -0.616 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/sys_clk SLICE_X68Y94 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/buffers_1_reg/C ------------------------------------------------------------------- ------------------- SLICE_X68Y94 FDCE (Prop_fdce_C_Q) 0.148 -0.468 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/buffers_1_reg/Q net (fo=1, routed) 0.286 -0.182 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/buffers_1 SLICE_X68Y94 LUT1 (Prop_lut1_I0_O) 0.098 -0.084 f u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/popCC_popPtr[2]_i_2__2/O net (fo=30, routed) 0.292 0.208 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/buffers_0_reg[3] SLICE_X65Y93 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/popCC_popPtr_reg[3]/CLR ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9603, routed) 0.923 -0.385 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/sys_clk SLICE_X65Y93 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/popCC_popPtr_reg[3]/C clock pessimism -0.192 -0.577 SLICE_X65Y93 FDCE (Remov_fdce_C_CLR) -0.092 -0.669 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/popCC_popPtr_reg[3] ------------------------------------------------------------------- required time 0.669 arrival time 0.208 ------------------------------------------------------------------- slack 0.877 Slack (MET) : 0.972ns (arrival time - required time) Source: u_Axi_CDC/awFifo/bufferCC_12/buffers_1_reg/C (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: u_Axi_CDC/awFifo/pushToPopGray_buffercc/buffers_0_reg[0]/CLR (removal check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) Data Path Delay: 0.941ns (logic 0.246ns (26.142%) route 0.695ns (73.858%)) Logic Levels: 1 (LUT1=1) Clock Path Skew: 0.036ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.341ns Source Clock Delay (SCD): -0.569ns Clock Pessimism Removal (CPR): 0.192ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9603, routed) 0.693 -0.569 u_Axi_CDC/awFifo/bufferCC_12/sys_clk SLICE_X8Y60 FDCE r u_Axi_CDC/awFifo/bufferCC_12/buffers_1_reg/C ------------------------------------------------------------------- ------------------- SLICE_X8Y60 FDCE (Prop_fdce_C_Q) 0.148 -0.421 r u_Axi_CDC/awFifo/bufferCC_12/buffers_1_reg/Q net (fo=1, routed) 0.286 -0.135 u_Axi_CDC/awFifo/bufferCC_12/buffers_1 SLICE_X8Y60 LUT1 (Prop_lut1_I0_O) 0.098 -0.037 f u_Axi_CDC/awFifo/bufferCC_12/popCC_popPtr[2]_i_2/O net (fo=43, routed) 0.409 0.372 u_Axi_CDC/awFifo/pushToPopGray_buffercc/buffers_0_reg[2]_1 SLICE_X18Y62 FDCE f u_Axi_CDC/awFifo/pushToPopGray_buffercc/buffers_0_reg[0]/CLR ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9603, routed) 0.967 -0.341 u_Axi_CDC/awFifo/pushToPopGray_buffercc/sys_clk SLICE_X18Y62 FDCE r u_Axi_CDC/awFifo/pushToPopGray_buffercc/buffers_0_reg[0]/C clock pessimism -0.192 -0.533 SLICE_X18Y62 FDCE (Remov_fdce_C_CLR) -0.067 -0.600 u_Axi_CDC/awFifo/pushToPopGray_buffercc/buffers_0_reg[0] ------------------------------------------------------------------- required time 0.600 arrival time 0.372 ------------------------------------------------------------------- slack 0.972 Slack (MET) : 0.972ns (arrival time - required time) Source: u_Axi_CDC/awFifo/bufferCC_12/buffers_1_reg/C (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: u_Axi_CDC/awFifo/pushToPopGray_buffercc/buffers_0_reg[1]/CLR (removal check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) Data Path Delay: 0.941ns (logic 0.246ns (26.142%) route 0.695ns (73.858%)) Logic Levels: 1 (LUT1=1) Clock Path Skew: 0.036ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.341ns Source Clock Delay (SCD): -0.569ns Clock Pessimism Removal (CPR): 0.192ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9603, routed) 0.693 -0.569 u_Axi_CDC/awFifo/bufferCC_12/sys_clk SLICE_X8Y60 FDCE r u_Axi_CDC/awFifo/bufferCC_12/buffers_1_reg/C ------------------------------------------------------------------- ------------------- SLICE_X8Y60 FDCE (Prop_fdce_C_Q) 0.148 -0.421 r u_Axi_CDC/awFifo/bufferCC_12/buffers_1_reg/Q net (fo=1, routed) 0.286 -0.135 u_Axi_CDC/awFifo/bufferCC_12/buffers_1 SLICE_X8Y60 LUT1 (Prop_lut1_I0_O) 0.098 -0.037 f u_Axi_CDC/awFifo/bufferCC_12/popCC_popPtr[2]_i_2/O net (fo=43, routed) 0.409 0.372 u_Axi_CDC/awFifo/pushToPopGray_buffercc/buffers_0_reg[2]_1 SLICE_X18Y62 FDCE f u_Axi_CDC/awFifo/pushToPopGray_buffercc/buffers_0_reg[1]/CLR ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9603, routed) 0.967 -0.341 u_Axi_CDC/awFifo/pushToPopGray_buffercc/sys_clk SLICE_X18Y62 FDCE r u_Axi_CDC/awFifo/pushToPopGray_buffercc/buffers_0_reg[1]/C clock pessimism -0.192 -0.533 SLICE_X18Y62 FDCE (Remov_fdce_C_CLR) -0.067 -0.600 u_Axi_CDC/awFifo/pushToPopGray_buffercc/buffers_0_reg[1] ------------------------------------------------------------------- required time 0.600 arrival time 0.372 ------------------------------------------------------------------- slack 0.972 Slack (MET) : 0.972ns (arrival time - required time) Source: u_Axi_CDC/awFifo/bufferCC_12/buffers_1_reg/C (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: u_Axi_CDC/awFifo/pushToPopGray_buffercc/buffers_0_reg[2]/CLR (removal check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) Data Path Delay: 0.941ns (logic 0.246ns (26.142%) route 0.695ns (73.858%)) Logic Levels: 1 (LUT1=1) Clock Path Skew: 0.036ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.341ns Source Clock Delay (SCD): -0.569ns Clock Pessimism Removal (CPR): 0.192ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9603, routed) 0.693 -0.569 u_Axi_CDC/awFifo/bufferCC_12/sys_clk SLICE_X8Y60 FDCE r u_Axi_CDC/awFifo/bufferCC_12/buffers_1_reg/C ------------------------------------------------------------------- ------------------- SLICE_X8Y60 FDCE (Prop_fdce_C_Q) 0.148 -0.421 r u_Axi_CDC/awFifo/bufferCC_12/buffers_1_reg/Q net (fo=1, routed) 0.286 -0.135 u_Axi_CDC/awFifo/bufferCC_12/buffers_1 SLICE_X8Y60 LUT1 (Prop_lut1_I0_O) 0.098 -0.037 f u_Axi_CDC/awFifo/bufferCC_12/popCC_popPtr[2]_i_2/O net (fo=43, routed) 0.409 0.372 u_Axi_CDC/awFifo/pushToPopGray_buffercc/buffers_0_reg[2]_1 SLICE_X18Y62 FDCE f u_Axi_CDC/awFifo/pushToPopGray_buffercc/buffers_0_reg[2]/CLR ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9603, routed) 0.967 -0.341 u_Axi_CDC/awFifo/pushToPopGray_buffercc/sys_clk SLICE_X18Y62 FDCE r u_Axi_CDC/awFifo/pushToPopGray_buffercc/buffers_0_reg[2]/C clock pessimism -0.192 -0.533 SLICE_X18Y62 FDCE (Remov_fdce_C_CLR) -0.067 -0.600 u_Axi_CDC/awFifo/pushToPopGray_buffercc/buffers_0_reg[2] ------------------------------------------------------------------- required time 0.600 arrival time 0.372 ------------------------------------------------------------------- slack 0.972 Slack (MET) : 0.972ns (arrival time - required time) Source: u_Axi_CDC/awFifo/bufferCC_12/buffers_1_reg/C (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: u_Axi_CDC/awFifo/pushToPopGray_buffercc/buffers_1_reg[0]/CLR (removal check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) Data Path Delay: 0.941ns (logic 0.246ns (26.142%) route 0.695ns (73.858%)) Logic Levels: 1 (LUT1=1) Clock Path Skew: 0.036ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.341ns Source Clock Delay (SCD): -0.569ns Clock Pessimism Removal (CPR): 0.192ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9603, routed) 0.693 -0.569 u_Axi_CDC/awFifo/bufferCC_12/sys_clk SLICE_X8Y60 FDCE r u_Axi_CDC/awFifo/bufferCC_12/buffers_1_reg/C ------------------------------------------------------------------- ------------------- SLICE_X8Y60 FDCE (Prop_fdce_C_Q) 0.148 -0.421 r u_Axi_CDC/awFifo/bufferCC_12/buffers_1_reg/Q net (fo=1, routed) 0.286 -0.135 u_Axi_CDC/awFifo/bufferCC_12/buffers_1 SLICE_X8Y60 LUT1 (Prop_lut1_I0_O) 0.098 -0.037 f u_Axi_CDC/awFifo/bufferCC_12/popCC_popPtr[2]_i_2/O net (fo=43, routed) 0.409 0.372 u_Axi_CDC/awFifo/pushToPopGray_buffercc/buffers_0_reg[2]_1 SLICE_X18Y62 FDCE f u_Axi_CDC/awFifo/pushToPopGray_buffercc/buffers_1_reg[0]/CLR ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9603, routed) 0.967 -0.341 u_Axi_CDC/awFifo/pushToPopGray_buffercc/sys_clk SLICE_X18Y62 FDCE r u_Axi_CDC/awFifo/pushToPopGray_buffercc/buffers_1_reg[0]/C clock pessimism -0.192 -0.533 SLICE_X18Y62 FDCE (Remov_fdce_C_CLR) -0.067 -0.600 u_Axi_CDC/awFifo/pushToPopGray_buffercc/buffers_1_reg[0] ------------------------------------------------------------------- required time 0.600 arrival time 0.372 ------------------------------------------------------------------- slack 0.972 Slack (MET) : 0.972ns (arrival time - required time) Source: u_Axi_CDC/awFifo/bufferCC_12/buffers_1_reg/C (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: u_Axi_CDC/awFifo/pushToPopGray_buffercc/buffers_1_reg[1]/CLR (removal check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) Data Path Delay: 0.941ns (logic 0.246ns (26.142%) route 0.695ns (73.858%)) Logic Levels: 1 (LUT1=1) Clock Path Skew: 0.036ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.341ns Source Clock Delay (SCD): -0.569ns Clock Pessimism Removal (CPR): 0.192ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9603, routed) 0.693 -0.569 u_Axi_CDC/awFifo/bufferCC_12/sys_clk SLICE_X8Y60 FDCE r u_Axi_CDC/awFifo/bufferCC_12/buffers_1_reg/C ------------------------------------------------------------------- ------------------- SLICE_X8Y60 FDCE (Prop_fdce_C_Q) 0.148 -0.421 r u_Axi_CDC/awFifo/bufferCC_12/buffers_1_reg/Q net (fo=1, routed) 0.286 -0.135 u_Axi_CDC/awFifo/bufferCC_12/buffers_1 SLICE_X8Y60 LUT1 (Prop_lut1_I0_O) 0.098 -0.037 f u_Axi_CDC/awFifo/bufferCC_12/popCC_popPtr[2]_i_2/O net (fo=43, routed) 0.409 0.372 u_Axi_CDC/awFifo/pushToPopGray_buffercc/buffers_0_reg[2]_1 SLICE_X18Y62 FDCE f u_Axi_CDC/awFifo/pushToPopGray_buffercc/buffers_1_reg[1]/CLR ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9603, routed) 0.967 -0.341 u_Axi_CDC/awFifo/pushToPopGray_buffercc/sys_clk SLICE_X18Y62 FDCE r u_Axi_CDC/awFifo/pushToPopGray_buffercc/buffers_1_reg[1]/C clock pessimism -0.192 -0.533 SLICE_X18Y62 FDCE (Remov_fdce_C_CLR) -0.067 -0.600 u_Axi_CDC/awFifo/pushToPopGray_buffercc/buffers_1_reg[1] ------------------------------------------------------------------- required time 0.600 arrival time 0.372 ------------------------------------------------------------------- slack 0.972 Slack (MET) : 0.972ns (arrival time - required time) Source: u_Axi_CDC/awFifo/bufferCC_12/buffers_1_reg/C (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: u_Axi_CDC/awFifo/pushToPopGray_buffercc/buffers_1_reg[2]/CLR (removal check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) Data Path Delay: 0.941ns (logic 0.246ns (26.142%) route 0.695ns (73.858%)) Logic Levels: 1 (LUT1=1) Clock Path Skew: 0.036ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.341ns Source Clock Delay (SCD): -0.569ns Clock Pessimism Removal (CPR): 0.192ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9603, routed) 0.693 -0.569 u_Axi_CDC/awFifo/bufferCC_12/sys_clk SLICE_X8Y60 FDCE r u_Axi_CDC/awFifo/bufferCC_12/buffers_1_reg/C ------------------------------------------------------------------- ------------------- SLICE_X8Y60 FDCE (Prop_fdce_C_Q) 0.148 -0.421 r u_Axi_CDC/awFifo/bufferCC_12/buffers_1_reg/Q net (fo=1, routed) 0.286 -0.135 u_Axi_CDC/awFifo/bufferCC_12/buffers_1 SLICE_X8Y60 LUT1 (Prop_lut1_I0_O) 0.098 -0.037 f u_Axi_CDC/awFifo/bufferCC_12/popCC_popPtr[2]_i_2/O net (fo=43, routed) 0.409 0.372 u_Axi_CDC/awFifo/pushToPopGray_buffercc/buffers_0_reg[2]_1 SLICE_X18Y62 FDCE f u_Axi_CDC/awFifo/pushToPopGray_buffercc/buffers_1_reg[2]/CLR ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9603, routed) 0.967 -0.341 u_Axi_CDC/awFifo/pushToPopGray_buffercc/sys_clk SLICE_X18Y62 FDCE r u_Axi_CDC/awFifo/pushToPopGray_buffercc/buffers_1_reg[2]/C clock pessimism -0.192 -0.533 SLICE_X18Y62 FDCE (Remov_fdce_C_CLR) -0.067 -0.600 u_Axi_CDC/awFifo/pushToPopGray_buffercc/buffers_1_reg[2] ------------------------------------------------------------------- required time 0.600 arrival time 0.372 ------------------------------------------------------------------- slack 0.972 Slack (MET) : 1.001ns (arrival time - required time) Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/buffers_1_reg/C (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/pushToPopGray_buffercc/buffers_0_reg[2]/CLR (removal check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) Data Path Delay: 0.947ns (logic 0.246ns (25.986%) route 0.701ns (74.014%)) Logic Levels: 1 (LUT1=1) Clock Path Skew: 0.038ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.386ns Source Clock Delay (SCD): -0.616ns Clock Pessimism Removal (CPR): 0.192ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9603, routed) 0.646 -0.616 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/sys_clk SLICE_X68Y94 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/buffers_1_reg/C ------------------------------------------------------------------- ------------------- SLICE_X68Y94 FDCE (Prop_fdce_C_Q) 0.148 -0.468 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/buffers_1_reg/Q net (fo=1, routed) 0.286 -0.182 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/buffers_1 SLICE_X68Y94 LUT1 (Prop_lut1_I0_O) 0.098 -0.084 f u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/popCC_popPtr[2]_i_2__2/O net (fo=30, routed) 0.414 0.330 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/pushToPopGray_buffercc/buffers_0_reg[3]_0 SLICE_X65Y92 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/pushToPopGray_buffercc/buffers_0_reg[2]/CLR ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9603, routed) 0.922 -0.386 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/pushToPopGray_buffercc/sys_clk SLICE_X65Y92 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/pushToPopGray_buffercc/buffers_0_reg[2]/C clock pessimism -0.192 -0.578 SLICE_X65Y92 FDCE (Remov_fdce_C_CLR) -0.092 -0.670 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/pushToPopGray_buffercc/buffers_0_reg[2] ------------------------------------------------------------------- required time 0.670 arrival time 0.330 ------------------------------------------------------------------- slack 1.001 Slack (MET) : 1.001ns (arrival time - required time) Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/buffers_1_reg/C (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/pushToPopGray_buffercc/buffers_0_reg[3]/CLR (removal check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) Data Path Delay: 0.947ns (logic 0.246ns (25.986%) route 0.701ns (74.014%)) Logic Levels: 1 (LUT1=1) Clock Path Skew: 0.038ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.386ns Source Clock Delay (SCD): -0.616ns Clock Pessimism Removal (CPR): 0.192ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9603, routed) 0.646 -0.616 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/sys_clk SLICE_X68Y94 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/buffers_1_reg/C ------------------------------------------------------------------- ------------------- SLICE_X68Y94 FDCE (Prop_fdce_C_Q) 0.148 -0.468 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/buffers_1_reg/Q net (fo=1, routed) 0.286 -0.182 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/buffers_1 SLICE_X68Y94 LUT1 (Prop_lut1_I0_O) 0.098 -0.084 f u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/popCC_popPtr[2]_i_2__2/O net (fo=30, routed) 0.414 0.330 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/pushToPopGray_buffercc/buffers_0_reg[3]_0 SLICE_X65Y92 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/pushToPopGray_buffercc/buffers_0_reg[3]/CLR ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9603, routed) 0.922 -0.386 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/pushToPopGray_buffercc/sys_clk SLICE_X65Y92 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/pushToPopGray_buffercc/buffers_0_reg[3]/C clock pessimism -0.192 -0.578 SLICE_X65Y92 FDCE (Remov_fdce_C_CLR) -0.092 -0.670 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/pushToPopGray_buffercc/buffers_0_reg[3] ------------------------------------------------------------------- required time 0.670 arrival time 0.330 ------------------------------------------------------------------- slack 1.001 Slack (MET) : 1.001ns (arrival time - required time) Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/buffers_1_reg/C (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/pushToPopGray_buffercc/buffers_1_reg[2]/CLR (removal check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) Data Path Delay: 0.947ns (logic 0.246ns (25.986%) route 0.701ns (74.014%)) Logic Levels: 1 (LUT1=1) Clock Path Skew: 0.038ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.386ns Source Clock Delay (SCD): -0.616ns Clock Pessimism Removal (CPR): 0.192ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9603, routed) 0.646 -0.616 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/sys_clk SLICE_X68Y94 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/buffers_1_reg/C ------------------------------------------------------------------- ------------------- SLICE_X68Y94 FDCE (Prop_fdce_C_Q) 0.148 -0.468 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/buffers_1_reg/Q net (fo=1, routed) 0.286 -0.182 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/buffers_1 SLICE_X68Y94 LUT1 (Prop_lut1_I0_O) 0.098 -0.084 f u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/popCC_popPtr[2]_i_2__2/O net (fo=30, routed) 0.414 0.330 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/pushToPopGray_buffercc/buffers_0_reg[3]_0 SLICE_X65Y92 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/pushToPopGray_buffercc/buffers_1_reg[2]/CLR ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9603, routed) 0.922 -0.386 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/pushToPopGray_buffercc/sys_clk SLICE_X65Y92 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/pushToPopGray_buffercc/buffers_1_reg[2]/C clock pessimism -0.192 -0.578 SLICE_X65Y92 FDCE (Remov_fdce_C_CLR) -0.092 -0.670 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/pushToPopGray_buffercc/buffers_1_reg[2] ------------------------------------------------------------------- required time 0.670 arrival time 0.330 ------------------------------------------------------------------- slack 1.001 Slack (MET) : 1.001ns (arrival time - required time) Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/buffers_1_reg/C (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/pushToPopGray_buffercc/buffers_1_reg[3]/CLR (removal check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) Data Path Delay: 0.947ns (logic 0.246ns (25.986%) route 0.701ns (74.014%)) Logic Levels: 1 (LUT1=1) Clock Path Skew: 0.038ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.386ns Source Clock Delay (SCD): -0.616ns Clock Pessimism Removal (CPR): 0.192ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9603, routed) 0.646 -0.616 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/sys_clk SLICE_X68Y94 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/buffers_1_reg/C ------------------------------------------------------------------- ------------------- SLICE_X68Y94 FDCE (Prop_fdce_C_Q) 0.148 -0.468 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/buffers_1_reg/Q net (fo=1, routed) 0.286 -0.182 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/buffers_1 SLICE_X68Y94 LUT1 (Prop_lut1_I0_O) 0.098 -0.084 f u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/popCC_popPtr[2]_i_2__2/O net (fo=30, routed) 0.414 0.330 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/pushToPopGray_buffercc/buffers_0_reg[3]_0 SLICE_X65Y92 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/pushToPopGray_buffercc/buffers_1_reg[3]/CLR ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9603, routed) 0.922 -0.386 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/pushToPopGray_buffercc/sys_clk SLICE_X65Y92 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/pushToPopGray_buffercc/buffers_1_reg[3]/C clock pessimism -0.192 -0.578 SLICE_X65Y92 FDCE (Remov_fdce_C_CLR) -0.092 -0.670 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/pushToPopGray_buffercc/buffers_1_reg[3] ------------------------------------------------------------------- required time 0.670 arrival time 0.330 ------------------------------------------------------------------- slack 1.001 Slack (MET) : 1.051ns (arrival time - required time) Source: u_Axi_CDC/awFifo/bufferCC_12/buffers_1_reg/C (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: u_Axi_CDC/awFifo/popCC_popPtr_reg[1]/CLR (removal check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) Data Path Delay: 0.994ns (logic 0.246ns (24.738%) route 0.748ns (75.262%)) Logic Levels: 1 (LUT1=1) Clock Path Skew: 0.035ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.342ns Source Clock Delay (SCD): -0.569ns Clock Pessimism Removal (CPR): 0.192ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9603, routed) 0.693 -0.569 u_Axi_CDC/awFifo/bufferCC_12/sys_clk SLICE_X8Y60 FDCE r u_Axi_CDC/awFifo/bufferCC_12/buffers_1_reg/C ------------------------------------------------------------------- ------------------- SLICE_X8Y60 FDCE (Prop_fdce_C_Q) 0.148 -0.421 r u_Axi_CDC/awFifo/bufferCC_12/buffers_1_reg/Q net (fo=1, routed) 0.286 -0.135 u_Axi_CDC/awFifo/bufferCC_12/buffers_1 SLICE_X8Y60 LUT1 (Prop_lut1_I0_O) 0.098 -0.037 f u_Axi_CDC/awFifo/bufferCC_12/popCC_popPtr[2]_i_2/O net (fo=43, routed) 0.462 0.425 u_Axi_CDC/awFifo/buffers_1_reg SLICE_X19Y63 FDCE f u_Axi_CDC/awFifo/popCC_popPtr_reg[1]/CLR ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9603, routed) 0.966 -0.342 u_Axi_CDC/awFifo/sys_clk SLICE_X19Y63 FDCE r u_Axi_CDC/awFifo/popCC_popPtr_reg[1]/C clock pessimism -0.192 -0.534 SLICE_X19Y63 FDCE (Remov_fdce_C_CLR) -0.092 -0.626 u_Axi_CDC/awFifo/popCC_popPtr_reg[1] ------------------------------------------------------------------- required time 0.626 arrival time 0.425 ------------------------------------------------------------------- slack 1.051 Slack (MET) : 1.051ns (arrival time - required time) Source: u_Axi_CDC/awFifo/bufferCC_12/buffers_1_reg/C (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: u_Axi_CDC/awFifo/popCC_popPtr_reg[2]/CLR (removal check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) Data Path Delay: 0.994ns (logic 0.246ns (24.738%) route 0.748ns (75.262%)) Logic Levels: 1 (LUT1=1) Clock Path Skew: 0.035ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.342ns Source Clock Delay (SCD): -0.569ns Clock Pessimism Removal (CPR): 0.192ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9603, routed) 0.693 -0.569 u_Axi_CDC/awFifo/bufferCC_12/sys_clk SLICE_X8Y60 FDCE r u_Axi_CDC/awFifo/bufferCC_12/buffers_1_reg/C ------------------------------------------------------------------- ------------------- SLICE_X8Y60 FDCE (Prop_fdce_C_Q) 0.148 -0.421 r u_Axi_CDC/awFifo/bufferCC_12/buffers_1_reg/Q net (fo=1, routed) 0.286 -0.135 u_Axi_CDC/awFifo/bufferCC_12/buffers_1 SLICE_X8Y60 LUT1 (Prop_lut1_I0_O) 0.098 -0.037 f u_Axi_CDC/awFifo/bufferCC_12/popCC_popPtr[2]_i_2/O net (fo=43, routed) 0.462 0.425 u_Axi_CDC/awFifo/buffers_1_reg SLICE_X19Y63 FDCE f u_Axi_CDC/awFifo/popCC_popPtr_reg[2]/CLR ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9603, routed) 0.966 -0.342 u_Axi_CDC/awFifo/sys_clk SLICE_X19Y63 FDCE r u_Axi_CDC/awFifo/popCC_popPtr_reg[2]/C clock pessimism -0.192 -0.534 SLICE_X19Y63 FDCE (Remov_fdce_C_CLR) -0.092 -0.626 u_Axi_CDC/awFifo/popCC_popPtr_reg[2] ------------------------------------------------------------------- required time 0.626 arrival time 0.425 ------------------------------------------------------------------- slack 1.051 Slack (MET) : 1.123ns (arrival time - required time) Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/buffers_1_reg/C (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/popCC_ptrToPush_reg[0]/CLR (removal check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) Data Path Delay: 1.070ns (logic 0.246ns (22.990%) route 0.824ns (77.010%)) Logic Levels: 1 (LUT1=1) Clock Path Skew: 0.039ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.385ns Source Clock Delay (SCD): -0.616ns Clock Pessimism Removal (CPR): 0.192ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9603, routed) 0.646 -0.616 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/sys_clk SLICE_X68Y94 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/buffers_1_reg/C ------------------------------------------------------------------- ------------------- SLICE_X68Y94 FDCE (Prop_fdce_C_Q) 0.148 -0.468 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/buffers_1_reg/Q net (fo=1, routed) 0.286 -0.182 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/buffers_1 SLICE_X68Y94 LUT1 (Prop_lut1_I0_O) 0.098 -0.084 f u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/popCC_popPtr[2]_i_2__2/O net (fo=30, routed) 0.538 0.454 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/buffers_1_reg SLICE_X65Y95 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/popCC_ptrToPush_reg[0]/CLR ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9603, routed) 0.923 -0.385 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/sys_clk SLICE_X65Y95 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/popCC_ptrToPush_reg[0]/C clock pessimism -0.192 -0.577 SLICE_X65Y95 FDCE (Remov_fdce_C_CLR) -0.092 -0.669 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/popCC_ptrToPush_reg[0] ------------------------------------------------------------------- required time 0.669 arrival time 0.454 ------------------------------------------------------------------- slack 1.123 Slack (MET) : 1.148ns (arrival time - required time) Source: u_Axi_CDC/awFifo/bufferCC_12/buffers_1_reg/C (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: u_Axi_CDC/awFifo/popCC_addressGen_rValid_reg/CLR (removal check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) Data Path Delay: 1.115ns (logic 0.246ns (22.066%) route 0.869ns (77.934%)) Logic Levels: 1 (LUT1=1) Clock Path Skew: 0.034ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.343ns Source Clock Delay (SCD): -0.569ns Clock Pessimism Removal (CPR): 0.192ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9603, routed) 0.693 -0.569 u_Axi_CDC/awFifo/bufferCC_12/sys_clk SLICE_X8Y60 FDCE r u_Axi_CDC/awFifo/bufferCC_12/buffers_1_reg/C ------------------------------------------------------------------- ------------------- SLICE_X8Y60 FDCE (Prop_fdce_C_Q) 0.148 -0.421 r u_Axi_CDC/awFifo/bufferCC_12/buffers_1_reg/Q net (fo=1, routed) 0.286 -0.135 u_Axi_CDC/awFifo/bufferCC_12/buffers_1 SLICE_X8Y60 LUT1 (Prop_lut1_I0_O) 0.098 -0.037 f u_Axi_CDC/awFifo/bufferCC_12/popCC_popPtr[2]_i_2/O net (fo=43, routed) 0.582 0.545 u_Axi_CDC/awFifo/buffers_1_reg SLICE_X16Y65 FDCE f u_Axi_CDC/awFifo/popCC_addressGen_rValid_reg/CLR ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9603, routed) 0.965 -0.343 u_Axi_CDC/awFifo/sys_clk SLICE_X16Y65 FDCE r u_Axi_CDC/awFifo/popCC_addressGen_rValid_reg/C clock pessimism -0.192 -0.535 SLICE_X16Y65 FDCE (Remov_fdce_C_CLR) -0.067 -0.602 u_Axi_CDC/awFifo/popCC_addressGen_rValid_reg ------------------------------------------------------------------- required time 0.602 arrival time 0.545 ------------------------------------------------------------------- slack 1.148 Slack (MET) : 1.148ns (arrival time - required time) Source: u_Axi_CDC/awFifo/bufferCC_12/buffers_1_reg/C (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: u_Axi_CDC/awFifo/popCC_ptrToPush_reg[0]/CLR (removal check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) Data Path Delay: 1.115ns (logic 0.246ns (22.066%) route 0.869ns (77.934%)) Logic Levels: 1 (LUT1=1) Clock Path Skew: 0.034ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.343ns Source Clock Delay (SCD): -0.569ns Clock Pessimism Removal (CPR): 0.192ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9603, routed) 0.693 -0.569 u_Axi_CDC/awFifo/bufferCC_12/sys_clk SLICE_X8Y60 FDCE r u_Axi_CDC/awFifo/bufferCC_12/buffers_1_reg/C ------------------------------------------------------------------- ------------------- SLICE_X8Y60 FDCE (Prop_fdce_C_Q) 0.148 -0.421 r u_Axi_CDC/awFifo/bufferCC_12/buffers_1_reg/Q net (fo=1, routed) 0.286 -0.135 u_Axi_CDC/awFifo/bufferCC_12/buffers_1 SLICE_X8Y60 LUT1 (Prop_lut1_I0_O) 0.098 -0.037 f u_Axi_CDC/awFifo/bufferCC_12/popCC_popPtr[2]_i_2/O net (fo=43, routed) 0.582 0.545 u_Axi_CDC/awFifo/buffers_1_reg SLICE_X16Y65 FDCE f u_Axi_CDC/awFifo/popCC_ptrToPush_reg[0]/CLR ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9603, routed) 0.965 -0.343 u_Axi_CDC/awFifo/sys_clk SLICE_X16Y65 FDCE r u_Axi_CDC/awFifo/popCC_ptrToPush_reg[0]/C clock pessimism -0.192 -0.535 SLICE_X16Y65 FDCE (Remov_fdce_C_CLR) -0.067 -0.602 u_Axi_CDC/awFifo/popCC_ptrToPush_reg[0] ------------------------------------------------------------------- required time 0.602 arrival time 0.545 ------------------------------------------------------------------- slack 1.148 Slack (MET) : 1.148ns (arrival time - required time) Source: u_Axi_CDC/awFifo/bufferCC_12/buffers_1_reg/C (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: u_Axi_CDC/awFifo/popCC_ptrToPush_reg[1]/CLR (removal check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) Data Path Delay: 1.115ns (logic 0.246ns (22.066%) route 0.869ns (77.934%)) Logic Levels: 1 (LUT1=1) Clock Path Skew: 0.034ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.343ns Source Clock Delay (SCD): -0.569ns Clock Pessimism Removal (CPR): 0.192ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9603, routed) 0.693 -0.569 u_Axi_CDC/awFifo/bufferCC_12/sys_clk SLICE_X8Y60 FDCE r u_Axi_CDC/awFifo/bufferCC_12/buffers_1_reg/C ------------------------------------------------------------------- ------------------- SLICE_X8Y60 FDCE (Prop_fdce_C_Q) 0.148 -0.421 r u_Axi_CDC/awFifo/bufferCC_12/buffers_1_reg/Q net (fo=1, routed) 0.286 -0.135 u_Axi_CDC/awFifo/bufferCC_12/buffers_1 SLICE_X8Y60 LUT1 (Prop_lut1_I0_O) 0.098 -0.037 f u_Axi_CDC/awFifo/bufferCC_12/popCC_popPtr[2]_i_2/O net (fo=43, routed) 0.582 0.545 u_Axi_CDC/awFifo/buffers_1_reg SLICE_X16Y65 FDCE f u_Axi_CDC/awFifo/popCC_ptrToPush_reg[1]/CLR ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9603, routed) 0.965 -0.343 u_Axi_CDC/awFifo/sys_clk SLICE_X16Y65 FDCE r u_Axi_CDC/awFifo/popCC_ptrToPush_reg[1]/C clock pessimism -0.192 -0.535 SLICE_X16Y65 FDCE (Remov_fdce_C_CLR) -0.067 -0.602 u_Axi_CDC/awFifo/popCC_ptrToPush_reg[1] ------------------------------------------------------------------- required time 0.602 arrival time 0.545 ------------------------------------------------------------------- slack 1.148 -------------------------------------------------------------------------------------- Path Group: (none) From Clock: sys_clk To Clock: cpu_clk Max Delay 0 Endpoints Min Delay 59 Endpoints -------------------------------------------------------------------------------------- Min Delay Paths -------------------------------------------------------------------------------------- Slack: inf Source: u_Axi_CDC/bFifo/pushCC_pushPtrGray_reg[2]/C (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: u_Axi_CDC/bFifo/pushToPopGray_buffercc/buffers_0_reg[2]/D (rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Path Group: (none) Path Type: Hold (Min at Slow Process Corner) Data Path Delay: 0.607ns (logic 0.337ns (55.477%) route 0.270ns (44.523%)) Logic Levels: 0 Clock Path Skew: -0.387ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -2.399ns Source Clock Delay (SCD): -2.011ns Clock Pessimism Removal (CPR): -0.000ns Clock Uncertainty: 0.194ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.130ns Phase Error (PE): 0.120ns Timing Exception: Asynchronous Clock Groups Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.393 1.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 2.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.248 -5.674 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.755 -3.919 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 -3.828 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9603, routed) 1.817 -2.011 u_Axi_CDC/bFifo/sys_clk SLICE_X17Y62 FDCE r u_Axi_CDC/bFifo/pushCC_pushPtrGray_reg[2]/C ------------------------------------------------------------------- ------------------- SLICE_X17Y62 FDCE (Prop_fdce_C_Q) 0.337 -1.674 r u_Axi_CDC/bFifo/pushCC_pushPtrGray_reg[2]/Q net (fo=4, routed) 0.270 -1.404 u_Axi_CDC/bFifo/pushToPopGray_buffercc/buffers_0_reg[2]_0 SLICE_X15Y62 FDCE r u_Axi_CDC/bFifo/pushToPopGray_buffercc/buffers_0_reg[2]/D ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 1.943 -2.399 u_Axi_CDC/bFifo/pushToPopGray_buffercc/cpu_clk SLICE_X15Y62 FDCE r u_Axi_CDC/bFifo/pushToPopGray_buffercc/buffers_0_reg[2]/C Slack: inf Source: u_Axi_CDC/bFifo/pushCC_pushPtrGray_reg[0]/C (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: u_Axi_CDC/bFifo/pushToPopGray_buffercc/buffers_0_reg[0]/D (rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Path Group: (none) Path Type: Hold (Min at Slow Process Corner) Data Path Delay: 0.636ns (logic 0.367ns (57.720%) route 0.269ns (42.280%)) Logic Levels: 0 Clock Path Skew: -0.387ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -2.399ns Source Clock Delay (SCD): -2.011ns Clock Pessimism Removal (CPR): -0.000ns Clock Uncertainty: 0.194ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.130ns Phase Error (PE): 0.120ns Timing Exception: Asynchronous Clock Groups Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.393 1.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 2.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.248 -5.674 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.755 -3.919 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 -3.828 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9603, routed) 1.817 -2.011 u_Axi_CDC/bFifo/sys_clk SLICE_X17Y62 FDCE r u_Axi_CDC/bFifo/pushCC_pushPtrGray_reg[0]/C ------------------------------------------------------------------- ------------------- SLICE_X17Y62 FDCE (Prop_fdce_C_Q) 0.367 -1.644 r u_Axi_CDC/bFifo/pushCC_pushPtrGray_reg[0]/Q net (fo=2, routed) 0.269 -1.375 u_Axi_CDC/bFifo/pushToPopGray_buffercc/Q[0] SLICE_X15Y62 FDCE r u_Axi_CDC/bFifo/pushToPopGray_buffercc/buffers_0_reg[0]/D ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 1.943 -2.399 u_Axi_CDC/bFifo/pushToPopGray_buffercc/cpu_clk SLICE_X15Y62 FDCE r u_Axi_CDC/bFifo/pushToPopGray_buffercc/buffers_0_reg[0]/C Slack: inf Source: u_snix_axil_cdma_mux_8ch/ch_done_reg[3]/C (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: u_cpu/u_csr/csr_estat_reg[3]/D (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Path Group: (none) Path Type: Hold (Min at Slow Process Corner) Data Path Delay: 0.750ns (logic 0.467ns (62.244%) route 0.283ns (37.756%)) Logic Levels: 1 (LUT5=1) Clock Path Skew: -0.388ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -2.510ns Source Clock Delay (SCD): -2.121ns Clock Pessimism Removal (CPR): -0.000ns Clock Uncertainty: 0.194ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.130ns Phase Error (PE): 0.120ns Timing Exception: Asynchronous Clock Groups Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.393 1.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 2.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.248 -5.674 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.755 -3.919 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 -3.828 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9603, routed) 1.707 -2.121 u_snix_axil_cdma_mux_8ch/sys_clk SLICE_X49Y78 FDRE r u_snix_axil_cdma_mux_8ch/ch_done_reg[3]/C ------------------------------------------------------------------- ------------------- SLICE_X49Y78 FDRE (Prop_fdre_C_Q) 0.367 -1.754 r u_snix_axil_cdma_mux_8ch/ch_done_reg[3]/Q net (fo=3, routed) 0.283 -1.471 u_snix_axil_cdma_mux_8ch/ch_done_reg[3]_0 SLICE_X50Y78 LUT5 (Prop_lut5_I1_O) 0.100 -1.371 r u_snix_axil_cdma_mux_8ch/csr_estat[3]_i_1/O net (fo=1, routed) 0.000 -1.371 u_cpu/u_csr/interrupt[1] SLICE_X50Y78 FDRE r u_cpu/u_csr/csr_estat_reg[3]/D ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 1.832 -2.510 u_cpu/u_csr/cpu_clk SLICE_X50Y78 FDRE r u_cpu/u_csr/csr_estat_reg[3]/C Slack: inf Source: u_confreg/int_out_or_q2_reg/C (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: u_cpu/u_csr/csr_estat_reg[2]/D (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Path Group: (none) Path Type: Hold (Min at Slow Process Corner) Data Path Delay: 0.651ns (logic 0.367ns (56.354%) route 0.284ns (43.646%)) Logic Levels: 0 Clock Path Skew: -0.387ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -2.395ns Source Clock Delay (SCD): -2.007ns Clock Pessimism Removal (CPR): -0.000ns Clock Uncertainty: 0.194ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.130ns Phase Error (PE): 0.120ns Timing Exception: Asynchronous Clock Groups Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.393 1.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 2.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.248 -5.674 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.755 -3.919 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 -3.828 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9603, routed) 1.821 -2.007 u_confreg/sys_clk SLICE_X15Y56 FDRE r u_confreg/int_out_or_q2_reg/C ------------------------------------------------------------------- ------------------- SLICE_X15Y56 FDRE (Prop_fdre_C_Q) 0.367 -1.640 r u_confreg/int_out_or_q2_reg/Q net (fo=1, routed) 0.284 -1.356 u_cpu/u_csr/interrupt[0] SLICE_X19Y56 FDRE r u_cpu/u_csr/csr_estat_reg[2]/D ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 1.947 -2.395 u_cpu/u_csr/cpu_clk SLICE_X19Y56 FDRE r u_cpu/u_csr/csr_estat_reg[2]/C Slack: inf Source: u_Axi_CDC/wFifo/popCC_ptrToPush_reg[2]/C (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: u_Axi_CDC/wFifo/popToPushGray_buffercc/buffers_0_reg[2]/D (rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Path Group: (none) Path Type: Hold (Min at Slow Process Corner) Data Path Delay: 0.742ns (logic 0.337ns (45.437%) route 0.405ns (54.563%)) Logic Levels: 0 Clock Path Skew: -0.387ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -2.397ns Source Clock Delay (SCD): -2.009ns Clock Pessimism Removal (CPR): -0.000ns Clock Uncertainty: 0.194ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.130ns Phase Error (PE): 0.120ns Timing Exception: Asynchronous Clock Groups Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.393 1.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 2.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.248 -5.674 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.755 -3.919 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 -3.828 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9603, routed) 1.819 -2.009 u_Axi_CDC/wFifo/sys_clk SLICE_X13Y59 FDCE r u_Axi_CDC/wFifo/popCC_ptrToPush_reg[2]/C ------------------------------------------------------------------- ------------------- SLICE_X13Y59 FDCE (Prop_fdce_C_Q) 0.337 -1.672 r u_Axi_CDC/wFifo/popCC_ptrToPush_reg[2]/Q net (fo=1, routed) 0.405 -1.268 u_Axi_CDC/wFifo/popToPushGray_buffercc/Q[2] SLICE_X8Y59 FDCE r u_Axi_CDC/wFifo/popToPushGray_buffercc/buffers_0_reg[2]/D ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 1.945 -2.397 u_Axi_CDC/wFifo/popToPushGray_buffercc/cpu_clk SLICE_X8Y59 FDCE r u_Axi_CDC/wFifo/popToPushGray_buffercc/buffers_0_reg[2]/C Slack: inf Source: u_Axi_CDC/bFifo/pushCC_pushPtrGray_reg[1]/C (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: u_Axi_CDC/bFifo/pushToPopGray_buffercc/buffers_0_reg[1]/D (rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Path Group: (none) Path Type: Hold (Min at Slow Process Corner) Data Path Delay: 0.752ns (logic 0.367ns (48.833%) route 0.385ns (51.167%)) Logic Levels: 0 Clock Path Skew: -0.387ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -2.399ns Source Clock Delay (SCD): -2.011ns Clock Pessimism Removal (CPR): -0.000ns Clock Uncertainty: 0.194ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.130ns Phase Error (PE): 0.120ns Timing Exception: Asynchronous Clock Groups Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.393 1.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 2.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.248 -5.674 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.755 -3.919 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 -3.828 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9603, routed) 1.817 -2.011 u_Axi_CDC/bFifo/sys_clk SLICE_X17Y62 FDCE r u_Axi_CDC/bFifo/pushCC_pushPtrGray_reg[1]/C ------------------------------------------------------------------- ------------------- SLICE_X17Y62 FDCE (Prop_fdce_C_Q) 0.367 -1.644 r u_Axi_CDC/bFifo/pushCC_pushPtrGray_reg[1]/Q net (fo=2, routed) 0.385 -1.260 u_Axi_CDC/bFifo/pushToPopGray_buffercc/Q[1] SLICE_X15Y62 FDCE r u_Axi_CDC/bFifo/pushToPopGray_buffercc/buffers_0_reg[1]/D ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 1.943 -2.399 u_Axi_CDC/bFifo/pushToPopGray_buffercc/cpu_clk SLICE_X15Y62 FDCE r u_Axi_CDC/bFifo/pushToPopGray_buffercc/buffers_0_reg[1]/C Slack: inf Source: u_Axi_CDC/wFifo/popCC_ptrToPush_reg[3]/C (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: u_Axi_CDC/wFifo/popToPushGray_buffercc/buffers_0_reg[3]/D (rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Path Group: (none) Path Type: Hold (Min at Slow Process Corner) Data Path Delay: 0.774ns (logic 0.367ns (47.441%) route 0.407ns (52.559%)) Logic Levels: 0 Clock Path Skew: -0.387ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -2.397ns Source Clock Delay (SCD): -2.009ns Clock Pessimism Removal (CPR): -0.000ns Clock Uncertainty: 0.194ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.130ns Phase Error (PE): 0.120ns Timing Exception: Asynchronous Clock Groups Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.393 1.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 2.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.248 -5.674 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.755 -3.919 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 -3.828 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9603, routed) 1.819 -2.009 u_Axi_CDC/wFifo/sys_clk SLICE_X13Y59 FDCE r u_Axi_CDC/wFifo/popCC_ptrToPush_reg[3]/C ------------------------------------------------------------------- ------------------- SLICE_X13Y59 FDCE (Prop_fdce_C_Q) 0.367 -1.642 r u_Axi_CDC/wFifo/popCC_ptrToPush_reg[3]/Q net (fo=1, routed) 0.407 -1.236 u_Axi_CDC/wFifo/popToPushGray_buffercc/Q[3] SLICE_X8Y59 FDCE r u_Axi_CDC/wFifo/popToPushGray_buffercc/buffers_0_reg[3]/D ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 1.945 -2.397 u_Axi_CDC/wFifo/popToPushGray_buffercc/cpu_clk SLICE_X8Y59 FDCE r u_Axi_CDC/wFifo/popToPushGray_buffercc/buffers_0_reg[3]/C Slack: inf Source: u_Axi_CDC/wFifo/popCC_ptrToPush_reg[1]/C (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: u_Axi_CDC/wFifo/popToPushGray_buffercc/buffers_0_reg[1]/D (rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Path Group: (none) Path Type: Hold (Min at Slow Process Corner) Data Path Delay: 0.777ns (logic 0.367ns (47.258%) route 0.410ns (52.742%)) Logic Levels: 0 Clock Path Skew: -0.387ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -2.397ns Source Clock Delay (SCD): -2.009ns Clock Pessimism Removal (CPR): -0.000ns Clock Uncertainty: 0.194ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.130ns Phase Error (PE): 0.120ns Timing Exception: Asynchronous Clock Groups Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.393 1.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 2.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.248 -5.674 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.755 -3.919 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 -3.828 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9603, routed) 1.819 -2.009 u_Axi_CDC/wFifo/sys_clk SLICE_X13Y59 FDCE r u_Axi_CDC/wFifo/popCC_ptrToPush_reg[1]/C ------------------------------------------------------------------- ------------------- SLICE_X13Y59 FDCE (Prop_fdce_C_Q) 0.367 -1.642 r u_Axi_CDC/wFifo/popCC_ptrToPush_reg[1]/Q net (fo=1, routed) 0.410 -1.233 u_Axi_CDC/wFifo/popToPushGray_buffercc/Q[1] SLICE_X8Y59 FDCE r u_Axi_CDC/wFifo/popToPushGray_buffercc/buffers_0_reg[1]/D ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 1.945 -2.397 u_Axi_CDC/wFifo/popToPushGray_buffercc/cpu_clk SLICE_X8Y59 FDCE r u_Axi_CDC/wFifo/popToPushGray_buffercc/buffers_0_reg[1]/C Slack: inf Source: u_Axi_CDC/awFifo/popCC_ptrToPush_reg[0]/C (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: u_Axi_CDC/awFifo/popToPushGray_buffercc/buffers_0_reg[0]/D (rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Path Group: (none) Path Type: Hold (Min at Slow Process Corner) Data Path Delay: 0.810ns (logic 0.418ns (51.628%) route 0.392ns (48.372%)) Logic Levels: 0 Clock Path Skew: -0.384ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -2.398ns Source Clock Delay (SCD): -2.013ns Clock Pessimism Removal (CPR): -0.000ns Clock Uncertainty: 0.194ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.130ns Phase Error (PE): 0.120ns Timing Exception: Asynchronous Clock Groups Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.393 1.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 2.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.248 -5.674 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.755 -3.919 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 -3.828 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9603, routed) 1.815 -2.013 u_Axi_CDC/awFifo/sys_clk SLICE_X16Y65 FDCE r u_Axi_CDC/awFifo/popCC_ptrToPush_reg[0]/C ------------------------------------------------------------------- ------------------- SLICE_X16Y65 FDCE (Prop_fdce_C_Q) 0.418 -1.595 r u_Axi_CDC/awFifo/popCC_ptrToPush_reg[0]/Q net (fo=2, routed) 0.392 -1.204 u_Axi_CDC/awFifo/popToPushGray_buffercc/D[0] SLICE_X16Y61 FDCE r u_Axi_CDC/awFifo/popToPushGray_buffercc/buffers_0_reg[0]/D ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 1.944 -2.398 u_Axi_CDC/awFifo/popToPushGray_buffercc/cpu_clk SLICE_X16Y61 FDCE r u_Axi_CDC/awFifo/popToPushGray_buffercc/buffers_0_reg[0]/C Slack: inf Source: u_Axi_CDC/arFifo/popCC_ptrToPush_reg[0]/C (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: u_Axi_CDC/arFifo/popToPushGray_buffercc/buffers_0_reg[0]/D (rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Path Group: (none) Path Type: Hold (Min at Slow Process Corner) Data Path Delay: 0.871ns (logic 0.418ns (48.003%) route 0.453ns (51.997%)) Logic Levels: 0 Clock Path Skew: -0.383ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -2.400ns Source Clock Delay (SCD): -2.016ns Clock Pessimism Removal (CPR): -0.000ns Clock Uncertainty: 0.194ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.130ns Phase Error (PE): 0.120ns Timing Exception: Asynchronous Clock Groups Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.393 1.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 2.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.248 -5.674 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.755 -3.919 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 -3.828 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9603, routed) 1.812 -2.016 u_Axi_CDC/arFifo/sys_clk SLICE_X20Y67 FDCE r u_Axi_CDC/arFifo/popCC_ptrToPush_reg[0]/C ------------------------------------------------------------------- ------------------- SLICE_X20Y67 FDCE (Prop_fdce_C_Q) 0.418 -1.598 r u_Axi_CDC/arFifo/popCC_ptrToPush_reg[0]/Q net (fo=2, routed) 0.453 -1.145 u_Axi_CDC/arFifo/popToPushGray_buffercc/D[0] SLICE_X18Y64 FDCE r u_Axi_CDC/arFifo/popToPushGray_buffercc/buffers_0_reg[0]/D ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 1.942 -2.400 u_Axi_CDC/arFifo/popToPushGray_buffercc/cpu_clk SLICE_X18Y64 FDCE r u_Axi_CDC/arFifo/popToPushGray_buffercc/buffers_0_reg[0]/C Slack: inf Source: u_Axi_CDC/arFifo/popCC_ptrToPush_reg[2]/C (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: u_Axi_CDC/arFifo/popToPushGray_buffercc/buffers_0_reg[2]/D (rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Path Group: (none) Path Type: Hold (Min at Slow Process Corner) Data Path Delay: 0.915ns (logic 0.385ns (42.060%) route 0.530ns (57.940%)) Logic Levels: 0 Clock Path Skew: -0.383ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -2.400ns Source Clock Delay (SCD): -2.016ns Clock Pessimism Removal (CPR): -0.000ns Clock Uncertainty: 0.194ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.130ns Phase Error (PE): 0.120ns Timing Exception: Asynchronous Clock Groups Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.393 1.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 2.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.248 -5.674 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.755 -3.919 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 -3.828 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9603, routed) 1.812 -2.016 u_Axi_CDC/arFifo/sys_clk SLICE_X20Y67 FDCE r u_Axi_CDC/arFifo/popCC_ptrToPush_reg[2]/C ------------------------------------------------------------------- ------------------- SLICE_X20Y67 FDCE (Prop_fdce_C_Q) 0.385 -1.631 r u_Axi_CDC/arFifo/popCC_ptrToPush_reg[2]/Q net (fo=2, routed) 0.530 -1.101 u_Axi_CDC/arFifo/popToPushGray_buffercc/D[2] SLICE_X18Y64 FDCE r u_Axi_CDC/arFifo/popToPushGray_buffercc/buffers_0_reg[2]/D ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 1.942 -2.400 u_Axi_CDC/arFifo/popToPushGray_buffercc/cpu_clk SLICE_X18Y64 FDCE r u_Axi_CDC/arFifo/popToPushGray_buffercc/buffers_0_reg[2]/C Slack: inf Source: u_Axi_CDC/awFifo/popCC_ptrToPush_reg[1]/C (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: u_Axi_CDC/awFifo/popToPushGray_buffercc/buffers_0_reg[1]/D (rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Path Group: (none) Path Type: Hold (Min at Slow Process Corner) Data Path Delay: 0.919ns (logic 0.418ns (45.470%) route 0.501ns (54.530%)) Logic Levels: 0 Clock Path Skew: -0.384ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -2.398ns Source Clock Delay (SCD): -2.013ns Clock Pessimism Removal (CPR): -0.000ns Clock Uncertainty: 0.194ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.130ns Phase Error (PE): 0.120ns Timing Exception: Asynchronous Clock Groups Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.393 1.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 2.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.248 -5.674 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.755 -3.919 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 -3.828 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9603, routed) 1.815 -2.013 u_Axi_CDC/awFifo/sys_clk SLICE_X16Y65 FDCE r u_Axi_CDC/awFifo/popCC_ptrToPush_reg[1]/C ------------------------------------------------------------------- ------------------- SLICE_X16Y65 FDCE (Prop_fdce_C_Q) 0.418 -1.595 r u_Axi_CDC/awFifo/popCC_ptrToPush_reg[1]/Q net (fo=2, routed) 0.501 -1.094 u_Axi_CDC/awFifo/popToPushGray_buffercc/D[1] SLICE_X16Y61 FDCE r u_Axi_CDC/awFifo/popToPushGray_buffercc/buffers_0_reg[1]/D ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 1.944 -2.398 u_Axi_CDC/awFifo/popToPushGray_buffercc/cpu_clk SLICE_X16Y61 FDCE r u_Axi_CDC/awFifo/popToPushGray_buffercc/buffers_0_reg[1]/C Slack: inf Source: u_Axi_CDC/awFifo/popCC_ptrToPush_reg[2]/C (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: u_Axi_CDC/awFifo/popToPushGray_buffercc/buffers_0_reg[2]/D (rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Path Group: (none) Path Type: Hold (Min at Slow Process Corner) Data Path Delay: 0.938ns (logic 0.385ns (41.055%) route 0.553ns (58.945%)) Logic Levels: 0 Clock Path Skew: -0.384ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -2.398ns Source Clock Delay (SCD): -2.013ns Clock Pessimism Removal (CPR): -0.000ns Clock Uncertainty: 0.194ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.130ns Phase Error (PE): 0.120ns Timing Exception: Asynchronous Clock Groups Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.393 1.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 2.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.248 -5.674 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.755 -3.919 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 -3.828 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9603, routed) 1.815 -2.013 u_Axi_CDC/awFifo/sys_clk SLICE_X16Y65 FDCE r u_Axi_CDC/awFifo/popCC_ptrToPush_reg[2]/C ------------------------------------------------------------------- ------------------- SLICE_X16Y65 FDCE (Prop_fdce_C_Q) 0.385 -1.628 r u_Axi_CDC/awFifo/popCC_ptrToPush_reg[2]/Q net (fo=2, routed) 0.553 -1.075 u_Axi_CDC/awFifo/popToPushGray_buffercc/D[2] SLICE_X16Y61 FDCE r u_Axi_CDC/awFifo/popToPushGray_buffercc/buffers_0_reg[2]/D ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 1.944 -2.398 u_Axi_CDC/awFifo/popToPushGray_buffercc/cpu_clk SLICE_X16Y61 FDCE r u_Axi_CDC/awFifo/popToPushGray_buffercc/buffers_0_reg[2]/C Slack: inf Source: u_Axi_CDC/arFifo/popCC_ptrToPush_reg[1]/C (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: u_Axi_CDC/arFifo/popToPushGray_buffercc/buffers_0_reg[1]/D (rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Path Group: (none) Path Type: Hold (Min at Slow Process Corner) Data Path Delay: 0.945ns (logic 0.418ns (44.215%) route 0.527ns (55.785%)) Logic Levels: 0 Clock Path Skew: -0.383ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -2.400ns Source Clock Delay (SCD): -2.016ns Clock Pessimism Removal (CPR): -0.000ns Clock Uncertainty: 0.194ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.130ns Phase Error (PE): 0.120ns Timing Exception: Asynchronous Clock Groups Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.393 1.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 2.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.248 -5.674 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.755 -3.919 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 -3.828 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9603, routed) 1.812 -2.016 u_Axi_CDC/arFifo/sys_clk SLICE_X20Y67 FDCE r u_Axi_CDC/arFifo/popCC_ptrToPush_reg[1]/C ------------------------------------------------------------------- ------------------- SLICE_X20Y67 FDCE (Prop_fdce_C_Q) 0.418 -1.598 r u_Axi_CDC/arFifo/popCC_ptrToPush_reg[1]/Q net (fo=2, routed) 0.527 -1.071 u_Axi_CDC/arFifo/popToPushGray_buffercc/D[1] SLICE_X18Y64 FDCE r u_Axi_CDC/arFifo/popToPushGray_buffercc/buffers_0_reg[1]/D ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 1.942 -2.400 u_Axi_CDC/arFifo/popToPushGray_buffercc/cpu_clk SLICE_X18Y64 FDCE r u_Axi_CDC/arFifo/popToPushGray_buffercc/buffers_0_reg[1]/C Slack: inf Source: u_Axi_CDC/rFifo/pushCC_pushPtrGray_reg[1]/C (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: u_Axi_CDC/rFifo/pushToPopGray_buffercc/buffers_0_reg[1]/D (rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Path Group: (none) Path Type: Hold (Min at Slow Process Corner) Data Path Delay: 1.050ns (logic 0.418ns (39.818%) route 0.632ns (60.182%)) Logic Levels: 0 Clock Path Skew: -0.381ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -2.400ns Source Clock Delay (SCD): -2.018ns Clock Pessimism Removal (CPR): -0.000ns Clock Uncertainty: 0.194ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.130ns Phase Error (PE): 0.120ns Timing Exception: Asynchronous Clock Groups Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.393 1.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 2.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.248 -5.674 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.755 -3.919 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 -3.828 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9603, routed) 1.810 -2.018 u_Axi_CDC/rFifo/sys_clk SLICE_X14Y69 FDCE r u_Axi_CDC/rFifo/pushCC_pushPtrGray_reg[1]/C ------------------------------------------------------------------- ------------------- SLICE_X14Y69 FDCE (Prop_fdce_C_Q) 0.418 -1.600 r u_Axi_CDC/rFifo/pushCC_pushPtrGray_reg[1]/Q net (fo=2, routed) 0.632 -0.969 u_Axi_CDC/rFifo/pushToPopGray_buffercc/buffers_0_reg[2]_0[1] SLICE_X12Y63 FDCE r u_Axi_CDC/rFifo/pushToPopGray_buffercc/buffers_0_reg[1]/D ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 1.942 -2.400 u_Axi_CDC/rFifo/pushToPopGray_buffercc/cpu_clk SLICE_X12Y63 FDCE r u_Axi_CDC/rFifo/pushToPopGray_buffercc/buffers_0_reg[1]/C Slack: inf Source: u_Axi_CDC/rFifo/pushCC_pushPtrGray_reg[2]/C (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: u_Axi_CDC/rFifo/pushToPopGray_buffercc/buffers_0_reg[2]/D (rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Path Group: (none) Path Type: Hold (Min at Slow Process Corner) Data Path Delay: 1.125ns (logic 0.418ns (37.171%) route 0.707ns (62.829%)) Logic Levels: 0 Clock Path Skew: -0.381ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -2.400ns Source Clock Delay (SCD): -2.018ns Clock Pessimism Removal (CPR): -0.000ns Clock Uncertainty: 0.194ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.130ns Phase Error (PE): 0.120ns Timing Exception: Asynchronous Clock Groups Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.393 1.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 2.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.248 -5.674 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.755 -3.919 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 -3.828 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9603, routed) 1.810 -2.018 u_Axi_CDC/rFifo/sys_clk SLICE_X14Y69 FDCE r u_Axi_CDC/rFifo/pushCC_pushPtrGray_reg[2]/C ------------------------------------------------------------------- ------------------- SLICE_X14Y69 FDCE (Prop_fdce_C_Q) 0.418 -1.600 r u_Axi_CDC/rFifo/pushCC_pushPtrGray_reg[2]/Q net (fo=2, routed) 0.707 -0.894 u_Axi_CDC/rFifo/pushToPopGray_buffercc/buffers_0_reg[2]_0[2] SLICE_X12Y63 FDCE r u_Axi_CDC/rFifo/pushToPopGray_buffercc/buffers_0_reg[2]/D ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 1.942 -2.400 u_Axi_CDC/rFifo/pushToPopGray_buffercc/cpu_clk SLICE_X12Y63 FDCE r u_Axi_CDC/rFifo/pushToPopGray_buffercc/buffers_0_reg[2]/C Slack: inf Source: u_Axi_CDC/rFifo/pushCC_pushPtrGray_reg[3]/C (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: u_Axi_CDC/rFifo/pushToPopGray_buffercc/buffers_0_reg[3]/D (rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Path Group: (none) Path Type: Hold (Min at Slow Process Corner) Data Path Delay: 1.185ns (logic 0.385ns (32.481%) route 0.800ns (67.519%)) Logic Levels: 0 Clock Path Skew: -0.383ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -2.402ns Source Clock Delay (SCD): -2.018ns Clock Pessimism Removal (CPR): -0.000ns Clock Uncertainty: 0.194ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.130ns Phase Error (PE): 0.120ns Timing Exception: Asynchronous Clock Groups Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.393 1.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 2.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.248 -5.674 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.755 -3.919 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 -3.828 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9603, routed) 1.810 -2.018 u_Axi_CDC/rFifo/sys_clk SLICE_X14Y69 FDCE r u_Axi_CDC/rFifo/pushCC_pushPtrGray_reg[3]/C ------------------------------------------------------------------- ------------------- SLICE_X14Y69 FDCE (Prop_fdce_C_Q) 0.385 -1.633 r u_Axi_CDC/rFifo/pushCC_pushPtrGray_reg[3]/Q net (fo=4, routed) 0.800 -0.833 u_Axi_CDC/rFifo/pushToPopGray_buffercc/buffers_0_reg[3]_0 SLICE_X14Y65 FDCE r u_Axi_CDC/rFifo/pushToPopGray_buffercc/buffers_0_reg[3]/D ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 1.940 -2.402 u_Axi_CDC/rFifo/pushToPopGray_buffercc/cpu_clk SLICE_X14Y65 FDCE r u_Axi_CDC/rFifo/pushToPopGray_buffercc/buffers_0_reg[3]/C Slack: inf Source: u_Axi_CDC/wFifo/popCC_ptrToPush_reg[0]/C (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: u_Axi_CDC/wFifo/popToPushGray_buffercc/buffers_0_reg[0]/D (rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Path Group: (none) Path Type: Hold (Min at Slow Process Corner) Data Path Delay: 1.180ns (logic 0.367ns (31.113%) route 0.813ns (68.887%)) Logic Levels: 0 Clock Path Skew: -0.387ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -2.397ns Source Clock Delay (SCD): -2.009ns Clock Pessimism Removal (CPR): -0.000ns Clock Uncertainty: 0.194ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.130ns Phase Error (PE): 0.120ns Timing Exception: Asynchronous Clock Groups Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.393 1.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 2.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.248 -5.674 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.755 -3.919 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 -3.828 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9603, routed) 1.819 -2.009 u_Axi_CDC/wFifo/sys_clk SLICE_X13Y59 FDCE r u_Axi_CDC/wFifo/popCC_ptrToPush_reg[0]/C ------------------------------------------------------------------- ------------------- SLICE_X13Y59 FDCE (Prop_fdce_C_Q) 0.367 -1.642 r u_Axi_CDC/wFifo/popCC_ptrToPush_reg[0]/Q net (fo=1, routed) 0.813 -0.830 u_Axi_CDC/wFifo/popToPushGray_buffercc/Q[0] SLICE_X9Y59 FDCE r u_Axi_CDC/wFifo/popToPushGray_buffercc/buffers_0_reg[0]/D ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 1.945 -2.397 u_Axi_CDC/wFifo/popToPushGray_buffercc/cpu_clk SLICE_X9Y59 FDCE r u_Axi_CDC/wFifo/popToPushGray_buffercc/buffers_0_reg[0]/C Slack: inf Source: u_Axi_CDC/rFifo/pushCC_pushPtrGray_reg[0]/C (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: u_Axi_CDC/rFifo/pushToPopGray_buffercc/buffers_0_reg[0]/D (rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Path Group: (none) Path Type: Hold (Min at Slow Process Corner) Data Path Delay: 1.351ns (logic 0.418ns (30.944%) route 0.933ns (69.056%)) Logic Levels: 0 Clock Path Skew: -0.383ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -2.402ns Source Clock Delay (SCD): -2.018ns Clock Pessimism Removal (CPR): -0.000ns Clock Uncertainty: 0.194ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.130ns Phase Error (PE): 0.120ns Timing Exception: Asynchronous Clock Groups Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.393 1.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 2.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.248 -5.674 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.755 -3.919 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 -3.828 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9603, routed) 1.810 -2.018 u_Axi_CDC/rFifo/sys_clk SLICE_X14Y69 FDCE r u_Axi_CDC/rFifo/pushCC_pushPtrGray_reg[0]/C ------------------------------------------------------------------- ------------------- SLICE_X14Y69 FDCE (Prop_fdce_C_Q) 0.418 -1.600 r u_Axi_CDC/rFifo/pushCC_pushPtrGray_reg[0]/Q net (fo=2, routed) 0.933 -0.667 u_Axi_CDC/rFifo/pushToPopGray_buffercc/buffers_0_reg[2]_0[0] SLICE_X14Y65 FDCE r u_Axi_CDC/rFifo/pushToPopGray_buffercc/buffers_0_reg[0]/D ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 1.940 -2.402 u_Axi_CDC/rFifo/pushToPopGray_buffercc/cpu_clk SLICE_X14Y65 FDCE r u_Axi_CDC/rFifo/pushToPopGray_buffercc/buffers_0_reg[0]/C Slack: inf Source: u_Axi_CDC/rFifo/ram_reg_0_7_36_39/RAMB_D1/CLK (rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: u_Axi_CDC/rFifo/_zz_ram_port1_reg[39]/D (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Path Group: (none) Path Type: Hold (Min at Slow Process Corner) Data Path Delay: 2.050ns (logic 1.062ns (51.800%) route 0.988ns (48.200%)) Logic Levels: 0 Clock Path Skew: -0.376ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -2.395ns Source Clock Delay (SCD): -2.018ns Clock Pessimism Removal (CPR): -0.000ns Clock Uncertainty: 0.194ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.130ns Phase Error (PE): 0.120ns Timing Exception: Asynchronous Clock Groups Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.393 1.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 2.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.248 -5.674 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.755 -3.919 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 -3.828 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9603, routed) 1.810 -2.018 u_Axi_CDC/rFifo/ram_reg_0_7_36_39/WCLK SLICE_X16Y69 RAMD32 r u_Axi_CDC/rFifo/ram_reg_0_7_36_39/RAMB_D1/CLK ------------------------------------------------------------------- ------------------- SLICE_X16Y69 RAMD32 (Prop_ramd32_CLK_O) 1.062 -0.956 r u_Axi_CDC/rFifo/ram_reg_0_7_36_39/RAMB_D1/O net (fo=1, routed) 0.988 0.032 u_Axi_CDC/rFifo/_zz_ram_port10__2[39] SLICE_X13Y53 FDRE r u_Axi_CDC/rFifo/_zz_ram_port1_reg[39]/D ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 1.947 -2.395 u_Axi_CDC/rFifo/cpu_clk SLICE_X13Y53 FDRE r u_Axi_CDC/rFifo/_zz_ram_port1_reg[39]/C Slack: inf Source: u_fft_mlkem_axi_slave/mlkem_intr_sync_reg[1]/C (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: u_cpu/u_csr/csr_estat_reg[5]/D (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Path Group: (none) Path Type: Hold (Min at Slow Process Corner) Data Path Delay: 2.288ns (logic 0.385ns (16.828%) route 1.903ns (83.172%)) Logic Levels: 0 Clock Path Skew: -0.299ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -2.411ns Source Clock Delay (SCD): -2.111ns Clock Pessimism Removal (CPR): -0.000ns Clock Uncertainty: 0.194ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.130ns Phase Error (PE): 0.120ns Timing Exception: Asynchronous Clock Groups Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.393 1.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 2.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.248 -5.674 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.755 -3.919 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 -3.828 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9603, routed) 1.717 -2.111 u_fft_mlkem_axi_slave/sys_clk SLICE_X60Y93 FDCE r u_fft_mlkem_axi_slave/mlkem_intr_sync_reg[1]/C ------------------------------------------------------------------- ------------------- SLICE_X60Y93 FDCE (Prop_fdce_C_Q) 0.385 -1.726 r u_fft_mlkem_axi_slave/mlkem_intr_sync_reg[1]/Q net (fo=1, routed) 1.903 0.177 u_cpu/u_csr/interrupt[3] SLICE_X39Y54 FDRE r u_cpu/u_csr/csr_estat_reg[5]/D ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 1.931 -2.411 u_cpu/u_csr/cpu_clk SLICE_X39Y54 FDRE r u_cpu/u_csr/csr_estat_reg[5]/C Slack: inf Source: u_matmul_axi_slave/done_reg/C (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: u_cpu/u_csr/csr_estat_reg[4]/D (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Path Group: (none) Path Type: Hold (Min at Slow Process Corner) Data Path Delay: 2.355ns (logic 0.367ns (15.581%) route 1.988ns (84.419%)) Logic Levels: 0 Clock Path Skew: -0.293ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -2.405ns Source Clock Delay (SCD): -2.111ns Clock Pessimism Removal (CPR): -0.000ns Clock Uncertainty: 0.194ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.130ns Phase Error (PE): 0.120ns Timing Exception: Asynchronous Clock Groups Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.393 1.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 2.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.248 -5.674 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.755 -3.919 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 -3.828 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9603, routed) 1.717 -2.111 u_matmul_axi_slave/sys_clk SLICE_X47Y90 FDRE r u_matmul_axi_slave/done_reg/C ------------------------------------------------------------------- ------------------- SLICE_X47Y90 FDRE (Prop_fdre_C_Q) 0.367 -1.744 r u_matmul_axi_slave/done_reg/Q net (fo=11, routed) 1.988 0.244 u_cpu/u_csr/interrupt[2] SLICE_X34Y54 FDRE r u_cpu/u_csr/csr_estat_reg[4]/D ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 1.937 -2.405 u_cpu/u_csr/cpu_clk SLICE_X34Y54 FDRE r u_cpu/u_csr/csr_estat_reg[4]/C Slack: inf Source: u_Axi_CDC/rFifo/ram_reg_0_7_6_11/RAMC/CLK (rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: u_Axi_CDC/rFifo/_zz_ram_port1_reg[10]/D (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Path Group: (none) Path Type: Hold (Min at Fast Process Corner) Data Path Delay: 1.102ns (logic 0.390ns (35.383%) route 0.712ns (64.617%)) Logic Levels: 0 Clock Path Skew: 0.304ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.273ns Source Clock Delay (SCD): -0.577ns Clock Pessimism Removal (CPR): -0.000ns Clock Uncertainty: 0.194ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.130ns Phase Error (PE): 0.120ns Timing Exception: Asynchronous Clock Groups Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9603, routed) 0.685 -0.577 u_Axi_CDC/rFifo/ram_reg_0_7_6_11/WCLK SLICE_X12Y71 RAMD32 r u_Axi_CDC/rFifo/ram_reg_0_7_6_11/RAMC/CLK ------------------------------------------------------------------- ------------------- SLICE_X12Y71 RAMD32 (Prop_ramd32_CLK_O) 0.390 -0.187 r u_Axi_CDC/rFifo/ram_reg_0_7_6_11/RAMC/O net (fo=1, routed) 0.712 0.525 u_Axi_CDC/rFifo/_zz_ram_port10__2[10] SLICE_X12Y21 FDRE r u_Axi_CDC/rFifo/_zz_ram_port1_reg[10]/D ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 1.035 -0.273 u_Axi_CDC/rFifo/cpu_clk SLICE_X12Y21 FDRE r u_Axi_CDC/rFifo/_zz_ram_port1_reg[10]/C Slack: inf Source: u_Axi_CDC/rFifo/ram_reg_0_7_18_23/RAMC/CLK (rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: u_Axi_CDC/rFifo/_zz_ram_port1_reg[22]/D (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Path Group: (none) Path Type: Hold (Min at Fast Process Corner) Data Path Delay: 1.137ns (logic 0.390ns (34.303%) route 0.747ns (65.697%)) Logic Levels: 0 Clock Path Skew: 0.302ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.274ns Source Clock Delay (SCD): -0.576ns Clock Pessimism Removal (CPR): -0.000ns Clock Uncertainty: 0.194ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.130ns Phase Error (PE): 0.120ns Timing Exception: Asynchronous Clock Groups Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9603, routed) 0.686 -0.576 u_Axi_CDC/rFifo/ram_reg_0_7_18_23/WCLK SLICE_X10Y70 RAMD32 r u_Axi_CDC/rFifo/ram_reg_0_7_18_23/RAMC/CLK ------------------------------------------------------------------- ------------------- SLICE_X10Y70 RAMD32 (Prop_ramd32_CLK_O) 0.390 -0.186 r u_Axi_CDC/rFifo/ram_reg_0_7_18_23/RAMC/O net (fo=1, routed) 0.747 0.561 u_Axi_CDC/rFifo/_zz_ram_port10__2[22] SLICE_X12Y27 FDRE r u_Axi_CDC/rFifo/_zz_ram_port1_reg[22]/D ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 1.034 -0.274 u_Axi_CDC/rFifo/cpu_clk SLICE_X12Y27 FDRE r u_Axi_CDC/rFifo/_zz_ram_port1_reg[22]/C Slack: inf Source: u_Axi_CDC/rFifo/ram_reg_0_7_24_29/RAMC_D1/CLK (rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: u_Axi_CDC/rFifo/_zz_ram_port1_reg[29]/D (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Path Group: (none) Path Type: Hold (Min at Fast Process Corner) Data Path Delay: 1.157ns (logic 0.386ns (33.359%) route 0.771ns (66.641%)) Logic Levels: 0 Clock Path Skew: 0.343ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.234ns Source Clock Delay (SCD): -0.577ns Clock Pessimism Removal (CPR): -0.000ns Clock Uncertainty: 0.194ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.130ns Phase Error (PE): 0.120ns Timing Exception: Asynchronous Clock Groups Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9603, routed) 0.685 -0.577 u_Axi_CDC/rFifo/ram_reg_0_7_24_29/WCLK SLICE_X10Y71 RAMD32 r u_Axi_CDC/rFifo/ram_reg_0_7_24_29/RAMC_D1/CLK ------------------------------------------------------------------- ------------------- SLICE_X10Y71 RAMD32 (Prop_ramd32_CLK_O) 0.386 -0.191 r u_Axi_CDC/rFifo/ram_reg_0_7_24_29/RAMC_D1/O net (fo=1, routed) 0.771 0.580 u_Axi_CDC/rFifo/_zz_ram_port10__2[29] SLICE_X7Y38 FDRE r u_Axi_CDC/rFifo/_zz_ram_port1_reg[29]/D ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 1.074 -0.234 u_Axi_CDC/rFifo/cpu_clk SLICE_X7Y38 FDRE r u_Axi_CDC/rFifo/_zz_ram_port1_reg[29]/C Slack: inf Source: u_Axi_CDC/rFifo/ram_reg_0_7_12_17/RAMA/CLK (rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: u_Axi_CDC/rFifo/_zz_ram_port1_reg[12]/D (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Path Group: (none) Path Type: Hold (Min at Slow Process Corner) Data Path Delay: 2.607ns (logic 1.084ns (41.588%) route 1.523ns (58.412%)) Logic Levels: 0 Clock Path Skew: -0.116ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -2.135ns Source Clock Delay (SCD): -2.018ns Clock Pessimism Removal (CPR): -0.000ns Clock Uncertainty: 0.194ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.130ns Phase Error (PE): 0.120ns Timing Exception: Asynchronous Clock Groups Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.393 1.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 2.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.248 -5.674 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.755 -3.919 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 -3.828 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9603, routed) 1.810 -2.018 u_Axi_CDC/rFifo/ram_reg_0_7_12_17/WCLK SLICE_X14Y70 RAMD32 r u_Axi_CDC/rFifo/ram_reg_0_7_12_17/RAMA/CLK ------------------------------------------------------------------- ------------------- SLICE_X14Y70 RAMD32 (Prop_ramd32_CLK_O) 1.084 -0.934 r u_Axi_CDC/rFifo/ram_reg_0_7_12_17/RAMA/O net (fo=1, routed) 1.523 0.588 u_Axi_CDC/rFifo/_zz_ram_port10__2[12] SLICE_X7Y38 FDRE r u_Axi_CDC/rFifo/_zz_ram_port1_reg[12]/D ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 2.207 -2.135 u_Axi_CDC/rFifo/cpu_clk SLICE_X7Y38 FDRE r u_Axi_CDC/rFifo/_zz_ram_port1_reg[12]/C Slack: inf Source: u_Axi_CDC/rFifo/ram_reg_0_7_0_5/RAMA_D1/CLK (rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: u_Axi_CDC/rFifo/_zz_ram_port1_reg[1]/D (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Path Group: (none) Path Type: Hold (Min at Slow Process Corner) Data Path Delay: 2.608ns (logic 1.056ns (40.498%) route 1.552ns (59.502%)) Logic Levels: 0 Clock Path Skew: -0.208ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -2.227ns Source Clock Delay (SCD): -2.018ns Clock Pessimism Removal (CPR): -0.000ns Clock Uncertainty: 0.194ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.130ns Phase Error (PE): 0.120ns Timing Exception: Asynchronous Clock Groups Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.393 1.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 2.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.248 -5.674 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.755 -3.919 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 -3.828 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9603, routed) 1.810 -2.018 u_Axi_CDC/rFifo/ram_reg_0_7_0_5/WCLK SLICE_X12Y70 RAMD32 r u_Axi_CDC/rFifo/ram_reg_0_7_0_5/RAMA_D1/CLK ------------------------------------------------------------------- ------------------- SLICE_X12Y70 RAMD32 (Prop_ramd32_CLK_O) 1.056 -0.962 r u_Axi_CDC/rFifo/ram_reg_0_7_0_5/RAMA_D1/O net (fo=1, routed) 1.552 0.589 u_Axi_CDC/rFifo/_zz_ram_port10__2[1] SLICE_X12Y26 FDRE r u_Axi_CDC/rFifo/_zz_ram_port1_reg[1]/D ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 2.115 -2.227 u_Axi_CDC/rFifo/cpu_clk SLICE_X12Y26 FDRE r u_Axi_CDC/rFifo/_zz_ram_port1_reg[1]/C Slack: inf Source: u_Axi_CDC/rFifo/ram_reg_0_7_0_5/RAMC/CLK (rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: u_Axi_CDC/rFifo/_zz_ram_port1_reg[4]/D (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Path Group: (none) Path Type: Hold (Min at Fast Process Corner) Data Path Delay: 1.175ns (logic 0.390ns (33.190%) route 0.785ns (66.810%)) Logic Levels: 0 Clock Path Skew: 0.300ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.276ns Source Clock Delay (SCD): -0.576ns Clock Pessimism Removal (CPR): -0.000ns Clock Uncertainty: 0.194ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.130ns Phase Error (PE): 0.120ns Timing Exception: Asynchronous Clock Groups Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9603, routed) 0.686 -0.576 u_Axi_CDC/rFifo/ram_reg_0_7_0_5/WCLK SLICE_X12Y70 RAMD32 r u_Axi_CDC/rFifo/ram_reg_0_7_0_5/RAMC/CLK ------------------------------------------------------------------- ------------------- SLICE_X12Y70 RAMD32 (Prop_ramd32_CLK_O) 0.390 -0.186 r u_Axi_CDC/rFifo/ram_reg_0_7_0_5/RAMC/O net (fo=1, routed) 0.785 0.599 u_Axi_CDC/rFifo/_zz_ram_port10__2[4] SLICE_X12Y26 FDRE r u_Axi_CDC/rFifo/_zz_ram_port1_reg[4]/D ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 1.032 -0.276 u_Axi_CDC/rFifo/cpu_clk SLICE_X12Y26 FDRE r u_Axi_CDC/rFifo/_zz_ram_port1_reg[4]/C Slack: inf Source: u_Axi_CDC/rFifo/ram_reg_0_7_30_35/RAMA_D1/CLK (rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: u_Axi_CDC/rFifo/_zz_ram_port1_reg[31]/D (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Path Group: (none) Path Type: Hold (Min at Slow Process Corner) Data Path Delay: 2.619ns (logic 1.056ns (40.319%) route 1.563ns (59.681%)) Logic Levels: 0 Clock Path Skew: -0.212ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -2.231ns Source Clock Delay (SCD): -2.018ns Clock Pessimism Removal (CPR): -0.000ns Clock Uncertainty: 0.194ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.130ns Phase Error (PE): 0.120ns Timing Exception: Asynchronous Clock Groups Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.393 1.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 2.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.248 -5.674 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.755 -3.919 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 -3.828 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9603, routed) 1.810 -2.018 u_Axi_CDC/rFifo/ram_reg_0_7_30_35/WCLK SLICE_X16Y70 RAMD32 r u_Axi_CDC/rFifo/ram_reg_0_7_30_35/RAMA_D1/CLK ------------------------------------------------------------------- ------------------- SLICE_X16Y70 RAMD32 (Prop_ramd32_CLK_O) 1.056 -0.962 r u_Axi_CDC/rFifo/ram_reg_0_7_30_35/RAMA_D1/O net (fo=1, routed) 1.563 0.601 u_Axi_CDC/rFifo/_zz_ram_port10__2[31] SLICE_X8Y25 FDRE r u_Axi_CDC/rFifo/_zz_ram_port1_reg[31]/D ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 2.111 -2.231 u_Axi_CDC/rFifo/cpu_clk SLICE_X8Y25 FDRE r u_Axi_CDC/rFifo/_zz_ram_port1_reg[31]/C Slack: inf Source: u_Axi_CDC/rFifo/ram_reg_0_7_12_17/RAMA_D1/CLK (rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: u_Axi_CDC/rFifo/_zz_ram_port1_reg[13]/D (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Path Group: (none) Path Type: Hold (Min at Slow Process Corner) Data Path Delay: 2.643ns (logic 1.056ns (39.962%) route 1.587ns (60.038%)) Logic Levels: 0 Clock Path Skew: -0.125ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -2.144ns Source Clock Delay (SCD): -2.018ns Clock Pessimism Removal (CPR): -0.000ns Clock Uncertainty: 0.194ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.130ns Phase Error (PE): 0.120ns Timing Exception: Asynchronous Clock Groups Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.393 1.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 2.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.248 -5.674 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.755 -3.919 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 -3.828 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9603, routed) 1.810 -2.018 u_Axi_CDC/rFifo/ram_reg_0_7_12_17/WCLK SLICE_X14Y70 RAMD32 r u_Axi_CDC/rFifo/ram_reg_0_7_12_17/RAMA_D1/CLK ------------------------------------------------------------------- ------------------- SLICE_X14Y70 RAMD32 (Prop_ramd32_CLK_O) 1.056 -0.962 r u_Axi_CDC/rFifo/ram_reg_0_7_12_17/RAMA_D1/O net (fo=1, routed) 1.587 0.624 u_Axi_CDC/rFifo/_zz_ram_port10__2[13] SLICE_X7Y30 FDRE r u_Axi_CDC/rFifo/_zz_ram_port1_reg[13]/D ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 2.198 -2.144 u_Axi_CDC/rFifo/cpu_clk SLICE_X7Y30 FDRE r u_Axi_CDC/rFifo/_zz_ram_port1_reg[13]/C Slack: inf Source: u_Axi_CDC/rFifo/ram_reg_0_7_18_23/RAMB/CLK (rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: u_Axi_CDC/rFifo/_zz_ram_port1_reg[20]/D (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Path Group: (none) Path Type: Hold (Min at Fast Process Corner) Data Path Delay: 1.209ns (logic 0.394ns (32.586%) route 0.815ns (67.414%)) Logic Levels: 0 Clock Path Skew: 0.300ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.276ns Source Clock Delay (SCD): -0.576ns Clock Pessimism Removal (CPR): -0.000ns Clock Uncertainty: 0.194ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.130ns Phase Error (PE): 0.120ns Timing Exception: Asynchronous Clock Groups Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9603, routed) 0.686 -0.576 u_Axi_CDC/rFifo/ram_reg_0_7_18_23/WCLK SLICE_X10Y70 RAMD32 r u_Axi_CDC/rFifo/ram_reg_0_7_18_23/RAMB/CLK ------------------------------------------------------------------- ------------------- SLICE_X10Y70 RAMD32 (Prop_ramd32_CLK_O) 0.394 -0.182 r u_Axi_CDC/rFifo/ram_reg_0_7_18_23/RAMB/O net (fo=1, routed) 0.815 0.633 u_Axi_CDC/rFifo/_zz_ram_port10__2[20] SLICE_X10Y23 FDRE r u_Axi_CDC/rFifo/_zz_ram_port1_reg[20]/D ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 1.032 -0.276 u_Axi_CDC/rFifo/cpu_clk SLICE_X10Y23 FDRE r u_Axi_CDC/rFifo/_zz_ram_port1_reg[20]/C Slack: inf Source: u_Axi_CDC/rFifo/ram_reg_0_7_0_5/RAMB/CLK (rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: u_Axi_CDC/rFifo/_zz_ram_port1_reg[2]/D (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Path Group: (none) Path Type: Hold (Min at Fast Process Corner) Data Path Delay: 1.215ns (logic 0.394ns (32.430%) route 0.821ns (67.570%)) Logic Levels: 0 Clock Path Skew: 0.300ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.276ns Source Clock Delay (SCD): -0.576ns Clock Pessimism Removal (CPR): -0.000ns Clock Uncertainty: 0.194ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.130ns Phase Error (PE): 0.120ns Timing Exception: Asynchronous Clock Groups Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9603, routed) 0.686 -0.576 u_Axi_CDC/rFifo/ram_reg_0_7_0_5/WCLK SLICE_X12Y70 RAMD32 r u_Axi_CDC/rFifo/ram_reg_0_7_0_5/RAMB/CLK ------------------------------------------------------------------- ------------------- SLICE_X12Y70 RAMD32 (Prop_ramd32_CLK_O) 0.394 -0.182 r u_Axi_CDC/rFifo/ram_reg_0_7_0_5/RAMB/O net (fo=1, routed) 0.821 0.639 u_Axi_CDC/rFifo/_zz_ram_port10__2[2] SLICE_X10Y23 FDRE r u_Axi_CDC/rFifo/_zz_ram_port1_reg[2]/D ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 1.032 -0.276 u_Axi_CDC/rFifo/cpu_clk SLICE_X10Y23 FDRE r u_Axi_CDC/rFifo/_zz_ram_port1_reg[2]/C Slack: inf Source: u_Axi_CDC/rFifo/ram_reg_0_7_12_17/RAMC_D1/CLK (rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: u_Axi_CDC/rFifo/_zz_ram_port1_reg[17]/D (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Path Group: (none) Path Type: Hold (Min at Fast Process Corner) Data Path Delay: 1.228ns (logic 0.386ns (31.443%) route 0.842ns (68.557%)) Logic Levels: 0 Clock Path Skew: 0.299ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.277ns Source Clock Delay (SCD): -0.576ns Clock Pessimism Removal (CPR): -0.000ns Clock Uncertainty: 0.194ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.130ns Phase Error (PE): 0.120ns Timing Exception: Asynchronous Clock Groups Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9603, routed) 0.686 -0.576 u_Axi_CDC/rFifo/ram_reg_0_7_12_17/WCLK SLICE_X14Y70 RAMD32 r u_Axi_CDC/rFifo/ram_reg_0_7_12_17/RAMC_D1/CLK ------------------------------------------------------------------- ------------------- SLICE_X14Y70 RAMD32 (Prop_ramd32_CLK_O) 0.386 -0.190 r u_Axi_CDC/rFifo/ram_reg_0_7_12_17/RAMC_D1/O net (fo=1, routed) 0.842 0.651 u_Axi_CDC/rFifo/_zz_ram_port10__2[17] SLICE_X11Y24 FDRE r u_Axi_CDC/rFifo/_zz_ram_port1_reg[17]/D ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 1.031 -0.277 u_Axi_CDC/rFifo/cpu_clk SLICE_X11Y24 FDRE r u_Axi_CDC/rFifo/_zz_ram_port1_reg[17]/C Slack: inf Source: u_Axi_CDC/rFifo/ram_reg_0_7_12_17/RAMB/CLK (rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: u_Axi_CDC/rFifo/_zz_ram_port1_reg[14]/D (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Path Group: (none) Path Type: Hold (Min at Fast Process Corner) Data Path Delay: 1.228ns (logic 0.394ns (32.081%) route 0.834ns (67.919%)) Logic Levels: 0 Clock Path Skew: 0.300ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.276ns Source Clock Delay (SCD): -0.576ns Clock Pessimism Removal (CPR): -0.000ns Clock Uncertainty: 0.194ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.130ns Phase Error (PE): 0.120ns Timing Exception: Asynchronous Clock Groups Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9603, routed) 0.686 -0.576 u_Axi_CDC/rFifo/ram_reg_0_7_12_17/WCLK SLICE_X14Y70 RAMD32 r u_Axi_CDC/rFifo/ram_reg_0_7_12_17/RAMB/CLK ------------------------------------------------------------------- ------------------- SLICE_X14Y70 RAMD32 (Prop_ramd32_CLK_O) 0.394 -0.182 r u_Axi_CDC/rFifo/ram_reg_0_7_12_17/RAMB/O net (fo=1, routed) 0.834 0.652 u_Axi_CDC/rFifo/_zz_ram_port10__2[14] SLICE_X12Y26 FDRE r u_Axi_CDC/rFifo/_zz_ram_port1_reg[14]/D ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 1.032 -0.276 u_Axi_CDC/rFifo/cpu_clk SLICE_X12Y26 FDRE r u_Axi_CDC/rFifo/_zz_ram_port1_reg[14]/C Slack: inf Source: u_Axi_CDC/rFifo/ram_reg_0_7_18_23/RAMC_D1/CLK (rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: u_Axi_CDC/rFifo/_zz_ram_port1_reg[23]/D (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Path Group: (none) Path Type: Hold (Min at Fast Process Corner) Data Path Delay: 1.243ns (logic 0.386ns (31.060%) route 0.857ns (68.940%)) Logic Levels: 0 Clock Path Skew: 0.299ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.277ns Source Clock Delay (SCD): -0.576ns Clock Pessimism Removal (CPR): -0.000ns Clock Uncertainty: 0.194ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.130ns Phase Error (PE): 0.120ns Timing Exception: Asynchronous Clock Groups Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9603, routed) 0.686 -0.576 u_Axi_CDC/rFifo/ram_reg_0_7_18_23/WCLK SLICE_X10Y70 RAMD32 r u_Axi_CDC/rFifo/ram_reg_0_7_18_23/RAMC_D1/CLK ------------------------------------------------------------------- ------------------- SLICE_X10Y70 RAMD32 (Prop_ramd32_CLK_O) 0.386 -0.190 r u_Axi_CDC/rFifo/ram_reg_0_7_18_23/RAMC_D1/O net (fo=1, routed) 0.857 0.666 u_Axi_CDC/rFifo/_zz_ram_port10__2[23] SLICE_X11Y24 FDRE r u_Axi_CDC/rFifo/_zz_ram_port1_reg[23]/D ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 1.031 -0.277 u_Axi_CDC/rFifo/cpu_clk SLICE_X11Y24 FDRE r u_Axi_CDC/rFifo/_zz_ram_port1_reg[23]/C Slack: inf Source: u_Axi_CDC/rFifo/ram_reg_0_7_0_5/RAMB_D1/CLK (rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: u_Axi_CDC/rFifo/_zz_ram_port1_reg[3]/D (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Path Group: (none) Path Type: Hold (Min at Fast Process Corner) Data Path Delay: 1.251ns (logic 0.388ns (31.020%) route 0.863ns (68.980%)) Logic Levels: 0 Clock Path Skew: 0.300ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.276ns Source Clock Delay (SCD): -0.576ns Clock Pessimism Removal (CPR): -0.000ns Clock Uncertainty: 0.194ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.130ns Phase Error (PE): 0.120ns Timing Exception: Asynchronous Clock Groups Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9603, routed) 0.686 -0.576 u_Axi_CDC/rFifo/ram_reg_0_7_0_5/WCLK SLICE_X12Y70 RAMD32 r u_Axi_CDC/rFifo/ram_reg_0_7_0_5/RAMB_D1/CLK ------------------------------------------------------------------- ------------------- SLICE_X12Y70 RAMD32 (Prop_ramd32_CLK_O) 0.388 -0.188 r u_Axi_CDC/rFifo/ram_reg_0_7_0_5/RAMB_D1/O net (fo=1, routed) 0.863 0.674 u_Axi_CDC/rFifo/_zz_ram_port10__2[3] SLICE_X12Y26 FDRE r u_Axi_CDC/rFifo/_zz_ram_port1_reg[3]/D ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 1.032 -0.276 u_Axi_CDC/rFifo/cpu_clk SLICE_X12Y26 FDRE r u_Axi_CDC/rFifo/_zz_ram_port1_reg[3]/C Slack: inf Source: u_Axi_CDC/rFifo/ram_reg_0_7_18_23/RAMA_D1/CLK (rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: u_Axi_CDC/rFifo/_zz_ram_port1_reg[19]/D (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Path Group: (none) Path Type: Hold (Min at Fast Process Corner) Data Path Delay: 1.260ns (logic 0.478ns (37.933%) route 0.782ns (62.067%)) Logic Levels: 0 Clock Path Skew: 0.302ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.274ns Source Clock Delay (SCD): -0.576ns Clock Pessimism Removal (CPR): -0.000ns Clock Uncertainty: 0.194ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.130ns Phase Error (PE): 0.120ns Timing Exception: Asynchronous Clock Groups Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9603, routed) 0.686 -0.576 u_Axi_CDC/rFifo/ram_reg_0_7_18_23/WCLK SLICE_X10Y70 RAMD32 r u_Axi_CDC/rFifo/ram_reg_0_7_18_23/RAMA_D1/CLK ------------------------------------------------------------------- ------------------- SLICE_X10Y70 RAMD32 (Prop_ramd32_CLK_O) 0.478 -0.098 r u_Axi_CDC/rFifo/ram_reg_0_7_18_23/RAMA_D1/O net (fo=1, routed) 0.782 0.684 u_Axi_CDC/rFifo/_zz_ram_port10__2[19] SLICE_X11Y22 FDRE r u_Axi_CDC/rFifo/_zz_ram_port1_reg[19]/D ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 1.034 -0.274 u_Axi_CDC/rFifo/cpu_clk SLICE_X11Y22 FDRE r u_Axi_CDC/rFifo/_zz_ram_port1_reg[19]/C Slack: inf Source: u_Axi_CDC/rFifo/ram_reg_0_7_30_35/RAMA/CLK (rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: u_Axi_CDC/rFifo/_zz_ram_port1_reg[30]/D (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Path Group: (none) Path Type: Hold (Min at Slow Process Corner) Data Path Delay: 2.703ns (logic 1.084ns (40.106%) route 1.619ns (59.894%)) Logic Levels: 0 Clock Path Skew: -0.207ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -2.226ns Source Clock Delay (SCD): -2.018ns Clock Pessimism Removal (CPR): -0.000ns Clock Uncertainty: 0.194ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.130ns Phase Error (PE): 0.120ns Timing Exception: Asynchronous Clock Groups Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.393 1.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 2.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.248 -5.674 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.755 -3.919 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 -3.828 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9603, routed) 1.810 -2.018 u_Axi_CDC/rFifo/ram_reg_0_7_30_35/WCLK SLICE_X16Y70 RAMD32 r u_Axi_CDC/rFifo/ram_reg_0_7_30_35/RAMA/CLK ------------------------------------------------------------------- ------------------- SLICE_X16Y70 RAMD32 (Prop_ramd32_CLK_O) 1.084 -0.934 r u_Axi_CDC/rFifo/ram_reg_0_7_30_35/RAMA/O net (fo=1, routed) 1.619 0.685 u_Axi_CDC/rFifo/_zz_ram_port10__2[30] SLICE_X12Y27 FDRE r u_Axi_CDC/rFifo/_zz_ram_port1_reg[30]/D ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 2.116 -2.226 u_Axi_CDC/rFifo/cpu_clk SLICE_X12Y27 FDRE r u_Axi_CDC/rFifo/_zz_ram_port1_reg[30]/C Slack: inf Source: u_Axi_CDC/rFifo/ram_reg_0_7_24_29/RAMC/CLK (rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: u_Axi_CDC/rFifo/_zz_ram_port1_reg[28]/D (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Path Group: (none) Path Type: Hold (Min at Fast Process Corner) Data Path Delay: 1.268ns (logic 0.390ns (30.763%) route 0.878ns (69.237%)) Logic Levels: 0 Clock Path Skew: 0.309ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.268ns Source Clock Delay (SCD): -0.577ns Clock Pessimism Removal (CPR): -0.000ns Clock Uncertainty: 0.194ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.130ns Phase Error (PE): 0.120ns Timing Exception: Asynchronous Clock Groups Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9603, routed) 0.685 -0.577 u_Axi_CDC/rFifo/ram_reg_0_7_24_29/WCLK SLICE_X10Y71 RAMD32 r u_Axi_CDC/rFifo/ram_reg_0_7_24_29/RAMC/CLK ------------------------------------------------------------------- ------------------- SLICE_X10Y71 RAMD32 (Prop_ramd32_CLK_O) 0.390 -0.187 r u_Axi_CDC/rFifo/ram_reg_0_7_24_29/RAMC/O net (fo=1, routed) 0.878 0.690 u_Axi_CDC/rFifo/_zz_ram_port10__2[28] SLICE_X10Y33 FDRE r u_Axi_CDC/rFifo/_zz_ram_port1_reg[28]/D ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 1.040 -0.268 u_Axi_CDC/rFifo/cpu_clk SLICE_X10Y33 FDRE r u_Axi_CDC/rFifo/_zz_ram_port1_reg[28]/C Slack: inf Source: u_Axi_CDC/rFifo/ram_reg_0_7_30_35/RAMB/CLK (rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: u_Axi_CDC/rFifo/_zz_ram_port1_reg[32]/D (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Path Group: (none) Path Type: Hold (Min at Fast Process Corner) Data Path Delay: 1.274ns (logic 0.394ns (30.924%) route 0.880ns (69.076%)) Logic Levels: 0 Clock Path Skew: 0.300ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.276ns Source Clock Delay (SCD): -0.576ns Clock Pessimism Removal (CPR): -0.000ns Clock Uncertainty: 0.194ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.130ns Phase Error (PE): 0.120ns Timing Exception: Asynchronous Clock Groups Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9603, routed) 0.686 -0.576 u_Axi_CDC/rFifo/ram_reg_0_7_30_35/WCLK SLICE_X16Y70 RAMD32 r u_Axi_CDC/rFifo/ram_reg_0_7_30_35/RAMB/CLK ------------------------------------------------------------------- ------------------- SLICE_X16Y70 RAMD32 (Prop_ramd32_CLK_O) 0.394 -0.182 r u_Axi_CDC/rFifo/ram_reg_0_7_30_35/RAMB/O net (fo=1, routed) 0.880 0.698 u_Axi_CDC/rFifo/_zz_ram_port10__2[32] SLICE_X12Y26 FDRE r u_Axi_CDC/rFifo/_zz_ram_port1_reg[32]/D ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 1.032 -0.276 u_Axi_CDC/rFifo/cpu_clk SLICE_X12Y26 FDRE r u_Axi_CDC/rFifo/_zz_ram_port1_reg[32]/C Slack: inf Source: u_Axi_CDC/rFifo/ram_reg_0_7_6_11/RAMB/CLK (rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: u_Axi_CDC/rFifo/_zz_ram_port1_reg[8]/D (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Path Group: (none) Path Type: Hold (Min at Fast Process Corner) Data Path Delay: 1.284ns (logic 0.394ns (30.693%) route 0.890ns (69.307%)) Logic Levels: 0 Clock Path Skew: 0.301ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.276ns Source Clock Delay (SCD): -0.577ns Clock Pessimism Removal (CPR): -0.000ns Clock Uncertainty: 0.194ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.130ns Phase Error (PE): 0.120ns Timing Exception: Asynchronous Clock Groups Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9603, routed) 0.685 -0.577 u_Axi_CDC/rFifo/ram_reg_0_7_6_11/WCLK SLICE_X12Y71 RAMD32 r u_Axi_CDC/rFifo/ram_reg_0_7_6_11/RAMB/CLK ------------------------------------------------------------------- ------------------- SLICE_X12Y71 RAMD32 (Prop_ramd32_CLK_O) 0.394 -0.183 r u_Axi_CDC/rFifo/ram_reg_0_7_6_11/RAMB/O net (fo=1, routed) 0.890 0.706 u_Axi_CDC/rFifo/_zz_ram_port10__2[8] SLICE_X10Y23 FDRE r u_Axi_CDC/rFifo/_zz_ram_port1_reg[8]/D ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 1.032 -0.276 u_Axi_CDC/rFifo/cpu_clk SLICE_X10Y23 FDRE r u_Axi_CDC/rFifo/_zz_ram_port1_reg[8]/C Slack: inf Source: u_Axi_CDC/rFifo/ram_reg_0_7_6_11/RAMA_D1/CLK (rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: u_Axi_CDC/rFifo/_zz_ram_port1_reg[7]/D (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Path Group: (none) Path Type: Hold (Min at Slow Process Corner) Data Path Delay: 2.749ns (logic 1.056ns (38.419%) route 1.693ns (61.581%)) Logic Levels: 0 Clock Path Skew: -0.209ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -2.229ns Source Clock Delay (SCD): -2.019ns Clock Pessimism Removal (CPR): -0.000ns Clock Uncertainty: 0.194ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.130ns Phase Error (PE): 0.120ns Timing Exception: Asynchronous Clock Groups Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.393 1.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 2.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.248 -5.674 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.755 -3.919 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 -3.828 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9603, routed) 1.809 -2.019 u_Axi_CDC/rFifo/ram_reg_0_7_6_11/WCLK SLICE_X12Y71 RAMD32 r u_Axi_CDC/rFifo/ram_reg_0_7_6_11/RAMA_D1/CLK ------------------------------------------------------------------- ------------------- SLICE_X12Y71 RAMD32 (Prop_ramd32_CLK_O) 1.056 -0.963 r u_Axi_CDC/rFifo/ram_reg_0_7_6_11/RAMA_D1/O net (fo=1, routed) 1.693 0.729 u_Axi_CDC/rFifo/_zz_ram_port10__2[7] SLICE_X11Y24 FDRE r u_Axi_CDC/rFifo/_zz_ram_port1_reg[7]/D ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 2.113 -2.229 u_Axi_CDC/rFifo/cpu_clk SLICE_X11Y24 FDRE r u_Axi_CDC/rFifo/_zz_ram_port1_reg[7]/C Slack: inf Source: u_Axi_CDC/rFifo/ram_reg_0_7_24_29/RAMB/CLK (rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: u_Axi_CDC/rFifo/_zz_ram_port1_reg[26]/D (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Path Group: (none) Path Type: Hold (Min at Fast Process Corner) Data Path Delay: 1.324ns (logic 0.394ns (29.752%) route 0.930ns (70.248%)) Logic Levels: 0 Clock Path Skew: 0.301ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.276ns Source Clock Delay (SCD): -0.577ns Clock Pessimism Removal (CPR): -0.000ns Clock Uncertainty: 0.194ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.130ns Phase Error (PE): 0.120ns Timing Exception: Asynchronous Clock Groups Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9603, routed) 0.685 -0.577 u_Axi_CDC/rFifo/ram_reg_0_7_24_29/WCLK SLICE_X10Y71 RAMD32 r u_Axi_CDC/rFifo/ram_reg_0_7_24_29/RAMB/CLK ------------------------------------------------------------------- ------------------- SLICE_X10Y71 RAMD32 (Prop_ramd32_CLK_O) 0.394 -0.183 r u_Axi_CDC/rFifo/ram_reg_0_7_24_29/RAMB/O net (fo=1, routed) 0.930 0.747 u_Axi_CDC/rFifo/_zz_ram_port10__2[26] SLICE_X10Y23 FDRE r u_Axi_CDC/rFifo/_zz_ram_port1_reg[26]/D ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 1.032 -0.276 u_Axi_CDC/rFifo/cpu_clk SLICE_X10Y23 FDRE r u_Axi_CDC/rFifo/_zz_ram_port1_reg[26]/C Slack: inf Source: u_Axi_CDC/rFifo/ram_reg_0_7_24_29/RAMB_D1/CLK (rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: u_Axi_CDC/rFifo/_zz_ram_port1_reg[27]/D (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Path Group: (none) Path Type: Hold (Min at Fast Process Corner) Data Path Delay: 1.330ns (logic 0.388ns (29.180%) route 0.942ns (70.820%)) Logic Levels: 0 Clock Path Skew: 0.301ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.276ns Source Clock Delay (SCD): -0.577ns Clock Pessimism Removal (CPR): -0.000ns Clock Uncertainty: 0.194ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.130ns Phase Error (PE): 0.120ns Timing Exception: Asynchronous Clock Groups Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9603, routed) 0.685 -0.577 u_Axi_CDC/rFifo/ram_reg_0_7_24_29/WCLK SLICE_X10Y71 RAMD32 r u_Axi_CDC/rFifo/ram_reg_0_7_24_29/RAMB_D1/CLK ------------------------------------------------------------------- ------------------- SLICE_X10Y71 RAMD32 (Prop_ramd32_CLK_O) 0.388 -0.189 r u_Axi_CDC/rFifo/ram_reg_0_7_24_29/RAMB_D1/O net (fo=1, routed) 0.942 0.752 u_Axi_CDC/rFifo/_zz_ram_port10__2[27] SLICE_X10Y23 FDRE r u_Axi_CDC/rFifo/_zz_ram_port1_reg[27]/D ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 1.032 -0.276 u_Axi_CDC/rFifo/cpu_clk SLICE_X10Y23 FDRE r u_Axi_CDC/rFifo/_zz_ram_port1_reg[27]/C Slack: inf Source: u_Axi_CDC/rFifo/ram_reg_0_7_12_17/RAMB_D1/CLK (rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: u_Axi_CDC/rFifo/_zz_ram_port1_reg[15]/D (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Path Group: (none) Path Type: Hold (Min at Fast Process Corner) Data Path Delay: 1.332ns (logic 0.388ns (29.131%) route 0.944ns (70.869%)) Logic Levels: 0 Clock Path Skew: 0.299ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.277ns Source Clock Delay (SCD): -0.576ns Clock Pessimism Removal (CPR): -0.000ns Clock Uncertainty: 0.194ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.130ns Phase Error (PE): 0.120ns Timing Exception: Asynchronous Clock Groups Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9603, routed) 0.686 -0.576 u_Axi_CDC/rFifo/ram_reg_0_7_12_17/WCLK SLICE_X14Y70 RAMD32 r u_Axi_CDC/rFifo/ram_reg_0_7_12_17/RAMB_D1/CLK ------------------------------------------------------------------- ------------------- SLICE_X14Y70 RAMD32 (Prop_ramd32_CLK_O) 0.388 -0.188 r u_Axi_CDC/rFifo/ram_reg_0_7_12_17/RAMB_D1/O net (fo=1, routed) 0.944 0.756 u_Axi_CDC/rFifo/_zz_ram_port10__2[15] SLICE_X11Y24 FDRE r u_Axi_CDC/rFifo/_zz_ram_port1_reg[15]/D ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 1.031 -0.277 u_Axi_CDC/rFifo/cpu_clk SLICE_X11Y24 FDRE r u_Axi_CDC/rFifo/_zz_ram_port1_reg[15]/C Slack: inf Source: u_Axi_CDC/rFifo/ram_reg_0_7_0_5/RAMC_D1/CLK (rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: u_Axi_CDC/rFifo/_zz_ram_port1_reg[5]/D (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Path Group: (none) Path Type: Hold (Min at Fast Process Corner) Data Path Delay: 1.335ns (logic 0.386ns (28.910%) route 0.949ns (71.090%)) Logic Levels: 0 Clock Path Skew: 0.300ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.276ns Source Clock Delay (SCD): -0.576ns Clock Pessimism Removal (CPR): -0.000ns Clock Uncertainty: 0.194ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.130ns Phase Error (PE): 0.120ns Timing Exception: Asynchronous Clock Groups Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9603, routed) 0.686 -0.576 u_Axi_CDC/rFifo/ram_reg_0_7_0_5/WCLK SLICE_X12Y70 RAMD32 r u_Axi_CDC/rFifo/ram_reg_0_7_0_5/RAMC_D1/CLK ------------------------------------------------------------------- ------------------- SLICE_X12Y70 RAMD32 (Prop_ramd32_CLK_O) 0.386 -0.190 r u_Axi_CDC/rFifo/ram_reg_0_7_0_5/RAMC_D1/O net (fo=1, routed) 0.949 0.759 u_Axi_CDC/rFifo/_zz_ram_port10__2[5] SLICE_X10Y23 FDRE r u_Axi_CDC/rFifo/_zz_ram_port1_reg[5]/D ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 1.032 -0.276 u_Axi_CDC/rFifo/cpu_clk SLICE_X10Y23 FDRE r u_Axi_CDC/rFifo/_zz_ram_port1_reg[5]/C Slack: inf Source: u_Axi_CDC/rFifo/ram_reg_0_7_12_17/RAMC/CLK (rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: u_Axi_CDC/rFifo/_zz_ram_port1_reg[16]/D (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Path Group: (none) Path Type: Hold (Min at Fast Process Corner) Data Path Delay: 1.351ns (logic 0.390ns (28.869%) route 0.961ns (71.131%)) Logic Levels: 0 Clock Path Skew: 0.302ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.274ns Source Clock Delay (SCD): -0.576ns Clock Pessimism Removal (CPR): -0.000ns Clock Uncertainty: 0.194ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.130ns Phase Error (PE): 0.120ns Timing Exception: Asynchronous Clock Groups Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9603, routed) 0.686 -0.576 u_Axi_CDC/rFifo/ram_reg_0_7_12_17/WCLK SLICE_X14Y70 RAMD32 r u_Axi_CDC/rFifo/ram_reg_0_7_12_17/RAMC/CLK ------------------------------------------------------------------- ------------------- SLICE_X14Y70 RAMD32 (Prop_ramd32_CLK_O) 0.390 -0.186 r u_Axi_CDC/rFifo/ram_reg_0_7_12_17/RAMC/O net (fo=1, routed) 0.961 0.775 u_Axi_CDC/rFifo/_zz_ram_port10__2[16] SLICE_X11Y22 FDRE r u_Axi_CDC/rFifo/_zz_ram_port1_reg[16]/D ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 1.034 -0.274 u_Axi_CDC/rFifo/cpu_clk SLICE_X11Y22 FDRE r u_Axi_CDC/rFifo/_zz_ram_port1_reg[16]/C Slack: inf Source: u_Axi_CDC/rFifo/ram_reg_0_7_6_11/RAMB_D1/CLK (rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: u_Axi_CDC/rFifo/_zz_ram_port1_reg[9]/D (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Path Group: (none) Path Type: Hold (Min at Fast Process Corner) Data Path Delay: 1.369ns (logic 0.388ns (28.334%) route 0.981ns (71.666%)) Logic Levels: 0 Clock Path Skew: 0.304ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.273ns Source Clock Delay (SCD): -0.577ns Clock Pessimism Removal (CPR): -0.000ns Clock Uncertainty: 0.194ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.130ns Phase Error (PE): 0.120ns Timing Exception: Asynchronous Clock Groups Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9603, routed) 0.685 -0.577 u_Axi_CDC/rFifo/ram_reg_0_7_6_11/WCLK SLICE_X12Y71 RAMD32 r u_Axi_CDC/rFifo/ram_reg_0_7_6_11/RAMB_D1/CLK ------------------------------------------------------------------- ------------------- SLICE_X12Y71 RAMD32 (Prop_ramd32_CLK_O) 0.388 -0.189 r u_Axi_CDC/rFifo/ram_reg_0_7_6_11/RAMB_D1/O net (fo=1, routed) 0.981 0.792 u_Axi_CDC/rFifo/_zz_ram_port10__2[9] SLICE_X12Y21 FDRE r u_Axi_CDC/rFifo/_zz_ram_port1_reg[9]/D ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 1.035 -0.273 u_Axi_CDC/rFifo/cpu_clk SLICE_X12Y21 FDRE r u_Axi_CDC/rFifo/_zz_ram_port1_reg[9]/C Slack: inf Source: u_Axi_CDC/rFifo/ram_reg_0_7_18_23/RAMA/CLK (rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: u_Axi_CDC/rFifo/_zz_ram_port1_reg[18]/D (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Path Group: (none) Path Type: Hold (Min at Fast Process Corner) Data Path Delay: 1.382ns (logic 0.492ns (35.591%) route 0.890ns (64.409%)) Logic Levels: 0 Clock Path Skew: 0.302ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.274ns Source Clock Delay (SCD): -0.576ns Clock Pessimism Removal (CPR): -0.000ns Clock Uncertainty: 0.194ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.130ns Phase Error (PE): 0.120ns Timing Exception: Asynchronous Clock Groups Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9603, routed) 0.686 -0.576 u_Axi_CDC/rFifo/ram_reg_0_7_18_23/WCLK SLICE_X10Y70 RAMD32 r u_Axi_CDC/rFifo/ram_reg_0_7_18_23/RAMA/CLK ------------------------------------------------------------------- ------------------- SLICE_X10Y70 RAMD32 (Prop_ramd32_CLK_O) 0.492 -0.084 r u_Axi_CDC/rFifo/ram_reg_0_7_18_23/RAMA/O net (fo=1, routed) 0.890 0.806 u_Axi_CDC/rFifo/_zz_ram_port10__2[18] SLICE_X11Y22 FDRE r u_Axi_CDC/rFifo/_zz_ram_port1_reg[18]/D ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 1.034 -0.274 u_Axi_CDC/rFifo/cpu_clk SLICE_X11Y22 FDRE r u_Axi_CDC/rFifo/_zz_ram_port1_reg[18]/C Slack: inf Source: u_Axi_CDC/rFifo/ram_reg_0_7_6_11/RAMC_D1/CLK (rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: u_Axi_CDC/rFifo/_zz_ram_port1_reg[11]/D (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Path Group: (none) Path Type: Hold (Min at Fast Process Corner) Data Path Delay: 1.399ns (logic 0.386ns (27.594%) route 1.013ns (72.406%)) Logic Levels: 0 Clock Path Skew: 0.303ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.274ns Source Clock Delay (SCD): -0.577ns Clock Pessimism Removal (CPR): -0.000ns Clock Uncertainty: 0.194ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.130ns Phase Error (PE): 0.120ns Timing Exception: Asynchronous Clock Groups Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9603, routed) 0.685 -0.577 u_Axi_CDC/rFifo/ram_reg_0_7_6_11/WCLK SLICE_X12Y71 RAMD32 r u_Axi_CDC/rFifo/ram_reg_0_7_6_11/RAMC_D1/CLK ------------------------------------------------------------------- ------------------- SLICE_X12Y71 RAMD32 (Prop_ramd32_CLK_O) 0.386 -0.191 r u_Axi_CDC/rFifo/ram_reg_0_7_6_11/RAMC_D1/O net (fo=1, routed) 1.013 0.821 u_Axi_CDC/rFifo/_zz_ram_port10__2[11] SLICE_X11Y22 FDRE r u_Axi_CDC/rFifo/_zz_ram_port1_reg[11]/D ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 1.034 -0.274 u_Axi_CDC/rFifo/cpu_clk SLICE_X11Y22 FDRE r u_Axi_CDC/rFifo/_zz_ram_port1_reg[11]/C -------------------------------------------------------------------------------------- Path Group: (none) From Clock: cpu_clk To Clock: sys_clk Max Delay 0 Endpoints Min Delay 162 Endpoints -------------------------------------------------------------------------------------- Min Delay Paths -------------------------------------------------------------------------------------- Slack: inf Source: u_Axi_CDC/awFifo/pushCC_pushPtrGray_reg[2]/C (rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Destination: u_Axi_CDC/awFifo/pushToPopGray_buffercc/buffers_0_reg[2]/D (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: (none) Path Type: Hold (Min at Slow Process Corner) Data Path Delay: 0.630ns (logic 0.337ns (53.526%) route 0.293ns (46.474%)) Logic Levels: 0 Clock Path Skew: -0.388ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -2.399ns Source Clock Delay (SCD): -2.010ns Clock Pessimism Removal (CPR): -0.000ns Clock Uncertainty: 0.194ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.130ns Phase Error (PE): 0.120ns Timing Exception: Asynchronous Clock Groups Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.393 1.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 2.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -8.248 -5.674 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 1.755 -3.919 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.091 -3.828 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 1.818 -2.010 u_Axi_CDC/awFifo/cpu_clk SLICE_X17Y61 FDCE r u_Axi_CDC/awFifo/pushCC_pushPtrGray_reg[2]/C ------------------------------------------------------------------- ------------------- SLICE_X17Y61 FDCE (Prop_fdce_C_Q) 0.337 -1.673 r u_Axi_CDC/awFifo/pushCC_pushPtrGray_reg[2]/Q net (fo=4, routed) 0.293 -1.381 u_Axi_CDC/awFifo/pushToPopGray_buffercc/buffers_0_reg[2]_0 SLICE_X18Y62 FDCE r u_Axi_CDC/awFifo/pushToPopGray_buffercc/buffers_0_reg[2]/D ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9603, routed) 1.943 -2.399 u_Axi_CDC/awFifo/pushToPopGray_buffercc/sys_clk SLICE_X18Y62 FDCE r u_Axi_CDC/awFifo/pushToPopGray_buffercc/buffers_0_reg[2]/C Slack: inf Source: u_Axi_CDC/bFifo/popCC_ptrToPush_reg[2]/C (rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Destination: u_Axi_CDC/bFifo/popToPushGray_buffercc/buffers_0_reg[2]/D (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: (none) Path Type: Hold (Min at Slow Process Corner) Data Path Delay: 0.660ns (logic 0.385ns (58.316%) route 0.275ns (41.684%)) Logic Levels: 0 Clock Path Skew: -0.388ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -2.399ns Source Clock Delay (SCD): -2.010ns Clock Pessimism Removal (CPR): -0.000ns Clock Uncertainty: 0.194ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.130ns Phase Error (PE): 0.120ns Timing Exception: Asynchronous Clock Groups Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.393 1.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 2.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -8.248 -5.674 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 1.755 -3.919 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.091 -3.828 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 1.818 -2.010 u_Axi_CDC/bFifo/cpu_clk SLICE_X14Y61 FDCE r u_Axi_CDC/bFifo/popCC_ptrToPush_reg[2]/C ------------------------------------------------------------------- ------------------- SLICE_X14Y61 FDCE (Prop_fdce_C_Q) 0.385 -1.625 r u_Axi_CDC/bFifo/popCC_ptrToPush_reg[2]/Q net (fo=2, routed) 0.275 -1.350 u_Axi_CDC/bFifo/popToPushGray_buffercc/D[2] SLICE_X14Y62 FDCE r u_Axi_CDC/bFifo/popToPushGray_buffercc/buffers_0_reg[2]/D ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9603, routed) 1.943 -2.399 u_Axi_CDC/bFifo/popToPushGray_buffercc/sys_clk SLICE_X14Y62 FDCE r u_Axi_CDC/bFifo/popToPushGray_buffercc/buffers_0_reg[2]/C Slack: inf Source: u_Axi_CDC/rFifo/popCC_ptrToPush_reg[1]/C (rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Destination: u_Axi_CDC/rFifo/popToPushGray_buffercc/buffers_0_reg[1]/D (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: (none) Path Type: Hold (Min at Slow Process Corner) Data Path Delay: 0.740ns (logic 0.367ns (49.591%) route 0.373ns (50.409%)) Logic Levels: 0 Clock Path Skew: -0.386ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -2.399ns Source Clock Delay (SCD): -2.012ns Clock Pessimism Removal (CPR): -0.000ns Clock Uncertainty: 0.194ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.130ns Phase Error (PE): 0.120ns Timing Exception: Asynchronous Clock Groups Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.393 1.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 2.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -8.248 -5.674 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 1.755 -3.919 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.091 -3.828 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 1.816 -2.012 u_Axi_CDC/rFifo/cpu_clk SLICE_X15Y64 FDCE r u_Axi_CDC/rFifo/popCC_ptrToPush_reg[1]/C ------------------------------------------------------------------- ------------------- SLICE_X15Y64 FDCE (Prop_fdce_C_Q) 0.367 -1.645 r u_Axi_CDC/rFifo/popCC_ptrToPush_reg[1]/Q net (fo=1, routed) 0.373 -1.272 u_Axi_CDC/rFifo/popToPushGray_buffercc/buffers_0_reg[3]_0[1] SLICE_X14Y62 FDCE r u_Axi_CDC/rFifo/popToPushGray_buffercc/buffers_0_reg[1]/D ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9603, routed) 1.943 -2.399 u_Axi_CDC/rFifo/popToPushGray_buffercc/sys_clk SLICE_X14Y62 FDCE r u_Axi_CDC/rFifo/popToPushGray_buffercc/buffers_0_reg[1]/C Slack: inf Source: u_Axi_CDC/awFifo/pushCC_pushPtrGray_reg[0]/C (rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Destination: u_Axi_CDC/awFifo/pushToPopGray_buffercc/buffers_0_reg[0]/D (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: (none) Path Type: Hold (Min at Slow Process Corner) Data Path Delay: 0.745ns (logic 0.367ns (49.252%) route 0.378ns (50.748%)) Logic Levels: 0 Clock Path Skew: -0.388ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -2.399ns Source Clock Delay (SCD): -2.010ns Clock Pessimism Removal (CPR): -0.000ns Clock Uncertainty: 0.194ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.130ns Phase Error (PE): 0.120ns Timing Exception: Asynchronous Clock Groups Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.393 1.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 2.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -8.248 -5.674 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 1.755 -3.919 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.091 -3.828 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 1.818 -2.010 u_Axi_CDC/awFifo/cpu_clk SLICE_X17Y61 FDCE r u_Axi_CDC/awFifo/pushCC_pushPtrGray_reg[0]/C ------------------------------------------------------------------- ------------------- SLICE_X17Y61 FDCE (Prop_fdce_C_Q) 0.367 -1.643 r u_Axi_CDC/awFifo/pushCC_pushPtrGray_reg[0]/Q net (fo=2, routed) 0.378 -1.265 u_Axi_CDC/awFifo/pushToPopGray_buffercc/Q[0] SLICE_X18Y62 FDCE r u_Axi_CDC/awFifo/pushToPopGray_buffercc/buffers_0_reg[0]/D ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9603, routed) 1.943 -2.399 u_Axi_CDC/awFifo/pushToPopGray_buffercc/sys_clk SLICE_X18Y62 FDCE r u_Axi_CDC/awFifo/pushToPopGray_buffercc/buffers_0_reg[0]/C Slack: inf Source: u_Axi_CDC/rFifo/popCC_ptrToPush_reg[2]/C (rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Destination: u_Axi_CDC/rFifo/popToPushGray_buffercc/buffers_0_reg[2]/D (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: (none) Path Type: Hold (Min at Slow Process Corner) Data Path Delay: 0.752ns (logic 0.337ns (44.793%) route 0.415ns (55.207%)) Logic Levels: 0 Clock Path Skew: -0.386ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -2.399ns Source Clock Delay (SCD): -2.012ns Clock Pessimism Removal (CPR): -0.000ns Clock Uncertainty: 0.194ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.130ns Phase Error (PE): 0.120ns Timing Exception: Asynchronous Clock Groups Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.393 1.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 2.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -8.248 -5.674 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 1.755 -3.919 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.091 -3.828 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 1.816 -2.012 u_Axi_CDC/rFifo/cpu_clk SLICE_X15Y64 FDCE r u_Axi_CDC/rFifo/popCC_ptrToPush_reg[2]/C ------------------------------------------------------------------- ------------------- SLICE_X15Y64 FDCE (Prop_fdce_C_Q) 0.337 -1.675 r u_Axi_CDC/rFifo/popCC_ptrToPush_reg[2]/Q net (fo=1, routed) 0.415 -1.260 u_Axi_CDC/rFifo/popToPushGray_buffercc/buffers_0_reg[3]_0[2] SLICE_X14Y62 FDCE r u_Axi_CDC/rFifo/popToPushGray_buffercc/buffers_0_reg[2]/D ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9603, routed) 1.943 -2.399 u_Axi_CDC/rFifo/popToPushGray_buffercc/sys_clk SLICE_X14Y62 FDCE r u_Axi_CDC/rFifo/popToPushGray_buffercc/buffers_0_reg[2]/C Slack: inf Source: u_Axi_CDC/bFifo/popCC_ptrToPush_reg[1]/C (rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Destination: u_Axi_CDC/bFifo/popToPushGray_buffercc/buffers_0_reg[1]/D (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: (none) Path Type: Hold (Min at Slow Process Corner) Data Path Delay: 0.764ns (logic 0.367ns (48.064%) route 0.397ns (51.936%)) Logic Levels: 0 Clock Path Skew: -0.389ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -2.400ns Source Clock Delay (SCD): -2.010ns Clock Pessimism Removal (CPR): -0.000ns Clock Uncertainty: 0.194ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.130ns Phase Error (PE): 0.120ns Timing Exception: Asynchronous Clock Groups Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.393 1.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 2.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -8.248 -5.674 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 1.755 -3.919 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.091 -3.828 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 1.818 -2.010 u_Axi_CDC/bFifo/cpu_clk SLICE_X15Y61 FDCE r u_Axi_CDC/bFifo/popCC_ptrToPush_reg[1]/C ------------------------------------------------------------------- ------------------- SLICE_X15Y61 FDCE (Prop_fdce_C_Q) 0.367 -1.643 r u_Axi_CDC/bFifo/popCC_ptrToPush_reg[1]/Q net (fo=2, routed) 0.397 -1.247 u_Axi_CDC/bFifo/popToPushGray_buffercc/D[1] SLICE_X17Y63 FDCE r u_Axi_CDC/bFifo/popToPushGray_buffercc/buffers_0_reg[1]/D ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9603, routed) 1.942 -2.400 u_Axi_CDC/bFifo/popToPushGray_buffercc/sys_clk SLICE_X17Y63 FDCE r u_Axi_CDC/bFifo/popToPushGray_buffercc/buffers_0_reg[1]/C Slack: inf Source: u_Axi_CDC/arFifo/pushCC_pushPtrGray_reg[1]/C (rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Destination: u_Axi_CDC/arFifo/pushToPopGray_buffercc/buffers_0_reg[1]/D (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: (none) Path Type: Hold (Min at Slow Process Corner) Data Path Delay: 0.776ns (logic 0.367ns (47.306%) route 0.409ns (52.694%)) Logic Levels: 0 Clock Path Skew: -0.387ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -2.401ns Source Clock Delay (SCD): -2.013ns Clock Pessimism Removal (CPR): -0.000ns Clock Uncertainty: 0.194ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.130ns Phase Error (PE): 0.120ns Timing Exception: Asynchronous Clock Groups Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.393 1.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 2.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -8.248 -5.674 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 1.755 -3.919 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.091 -3.828 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 1.815 -2.013 u_Axi_CDC/arFifo/cpu_clk SLICE_X19Y65 FDCE r u_Axi_CDC/arFifo/pushCC_pushPtrGray_reg[1]/C ------------------------------------------------------------------- ------------------- SLICE_X19Y65 FDCE (Prop_fdce_C_Q) 0.367 -1.646 r u_Axi_CDC/arFifo/pushCC_pushPtrGray_reg[1]/Q net (fo=2, routed) 0.409 -1.237 u_Axi_CDC/arFifo/pushToPopGray_buffercc/Q[1] SLICE_X20Y64 FDCE r u_Axi_CDC/arFifo/pushToPopGray_buffercc/buffers_0_reg[1]/D ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9603, routed) 1.941 -2.401 u_Axi_CDC/arFifo/pushToPopGray_buffercc/sys_clk SLICE_X20Y64 FDCE r u_Axi_CDC/arFifo/pushToPopGray_buffercc/buffers_0_reg[1]/C Slack: inf Source: u_Axi_CDC/arFifo/pushCC_pushPtrGray_reg[0]/C (rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Destination: u_Axi_CDC/arFifo/pushToPopGray_buffercc/buffers_0_reg[0]/D (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: (none) Path Type: Hold (Min at Slow Process Corner) Data Path Delay: 0.777ns (logic 0.367ns (47.226%) route 0.410ns (52.774%)) Logic Levels: 0 Clock Path Skew: -0.387ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -2.401ns Source Clock Delay (SCD): -2.013ns Clock Pessimism Removal (CPR): -0.000ns Clock Uncertainty: 0.194ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.130ns Phase Error (PE): 0.120ns Timing Exception: Asynchronous Clock Groups Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.393 1.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 2.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -8.248 -5.674 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 1.755 -3.919 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.091 -3.828 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 1.815 -2.013 u_Axi_CDC/arFifo/cpu_clk SLICE_X19Y65 FDCE r u_Axi_CDC/arFifo/pushCC_pushPtrGray_reg[0]/C ------------------------------------------------------------------- ------------------- SLICE_X19Y65 FDCE (Prop_fdce_C_Q) 0.367 -1.646 r u_Axi_CDC/arFifo/pushCC_pushPtrGray_reg[0]/Q net (fo=2, routed) 0.410 -1.236 u_Axi_CDC/arFifo/pushToPopGray_buffercc/Q[0] SLICE_X20Y64 FDCE r u_Axi_CDC/arFifo/pushToPopGray_buffercc/buffers_0_reg[0]/D ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9603, routed) 1.941 -2.401 u_Axi_CDC/arFifo/pushToPopGray_buffercc/sys_clk SLICE_X20Y64 FDCE r u_Axi_CDC/arFifo/pushToPopGray_buffercc/buffers_0_reg[0]/C Slack: inf Source: u_Axi_CDC/wFifo/pushCC_pushPtrGray_reg[3]/C (rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Destination: u_Axi_CDC/wFifo/pushToPopGray_buffercc/buffers_0_reg[3]/D (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: (none) Path Type: Hold (Min at Slow Process Corner) Data Path Delay: 0.805ns (logic 0.385ns (47.856%) route 0.420ns (52.144%)) Logic Levels: 0 Clock Path Skew: -0.389ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -2.397ns Source Clock Delay (SCD): -2.007ns Clock Pessimism Removal (CPR): -0.000ns Clock Uncertainty: 0.194ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.130ns Phase Error (PE): 0.120ns Timing Exception: Asynchronous Clock Groups Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.393 1.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 2.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -8.248 -5.674 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 1.755 -3.919 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.091 -3.828 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 1.821 -2.007 u_Axi_CDC/wFifo/cpu_clk SLICE_X10Y58 FDCE r u_Axi_CDC/wFifo/pushCC_pushPtrGray_reg[3]/C ------------------------------------------------------------------- ------------------- SLICE_X10Y58 FDCE (Prop_fdce_C_Q) 0.385 -1.622 r u_Axi_CDC/wFifo/pushCC_pushPtrGray_reg[3]/Q net (fo=5, routed) 0.420 -1.203 u_Axi_CDC/wFifo/pushToPopGray_buffercc/D[3] SLICE_X12Y59 FDCE r u_Axi_CDC/wFifo/pushToPopGray_buffercc/buffers_0_reg[3]/D ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9603, routed) 1.945 -2.397 u_Axi_CDC/wFifo/pushToPopGray_buffercc/sys_clk SLICE_X12Y59 FDCE r u_Axi_CDC/wFifo/pushToPopGray_buffercc/buffers_0_reg[3]/C Slack: inf Source: u_Axi_CDC/wFifo/pushCC_pushPtrGray_reg[0]/C (rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Destination: u_Axi_CDC/wFifo/pushToPopGray_buffercc/buffers_0_reg[0]/D (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: (none) Path Type: Hold (Min at Slow Process Corner) Data Path Delay: 0.828ns (logic 0.418ns (50.491%) route 0.410ns (49.509%)) Logic Levels: 0 Clock Path Skew: -0.389ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -2.397ns Source Clock Delay (SCD): -2.007ns Clock Pessimism Removal (CPR): -0.000ns Clock Uncertainty: 0.194ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.130ns Phase Error (PE): 0.120ns Timing Exception: Asynchronous Clock Groups Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.393 1.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 2.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -8.248 -5.674 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 1.755 -3.919 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.091 -3.828 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 1.821 -2.007 u_Axi_CDC/wFifo/cpu_clk SLICE_X10Y58 FDCE r u_Axi_CDC/wFifo/pushCC_pushPtrGray_reg[0]/C ------------------------------------------------------------------- ------------------- SLICE_X10Y58 FDCE (Prop_fdce_C_Q) 0.418 -1.589 r u_Axi_CDC/wFifo/pushCC_pushPtrGray_reg[0]/Q net (fo=2, routed) 0.410 -1.179 u_Axi_CDC/wFifo/pushToPopGray_buffercc/D[0] SLICE_X12Y59 FDCE r u_Axi_CDC/wFifo/pushToPopGray_buffercc/buffers_0_reg[0]/D ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9603, routed) 1.945 -2.397 u_Axi_CDC/wFifo/pushToPopGray_buffercc/sys_clk SLICE_X12Y59 FDCE r u_Axi_CDC/wFifo/pushToPopGray_buffercc/buffers_0_reg[0]/C Slack: inf Source: u_Axi_CDC/arFifo/pushCC_pushPtrGray_reg[2]/C (rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Destination: u_Axi_CDC/arFifo/pushToPopGray_buffercc/buffers_0_reg[2]/D (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: (none) Path Type: Hold (Min at Slow Process Corner) Data Path Delay: 0.864ns (logic 0.337ns (38.986%) route 0.527ns (61.014%)) Logic Levels: 0 Clock Path Skew: -0.387ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -2.401ns Source Clock Delay (SCD): -2.013ns Clock Pessimism Removal (CPR): -0.000ns Clock Uncertainty: 0.194ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.130ns Phase Error (PE): 0.120ns Timing Exception: Asynchronous Clock Groups Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.393 1.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 2.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -8.248 -5.674 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 1.755 -3.919 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.091 -3.828 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 1.815 -2.013 u_Axi_CDC/arFifo/cpu_clk SLICE_X19Y65 FDCE r u_Axi_CDC/arFifo/pushCC_pushPtrGray_reg[2]/C ------------------------------------------------------------------- ------------------- SLICE_X19Y65 FDCE (Prop_fdce_C_Q) 0.337 -1.676 r u_Axi_CDC/arFifo/pushCC_pushPtrGray_reg[2]/Q net (fo=4, routed) 0.527 -1.149 u_Axi_CDC/arFifo/pushToPopGray_buffercc/buffers_0_reg[2]_0 SLICE_X20Y64 FDCE r u_Axi_CDC/arFifo/pushToPopGray_buffercc/buffers_0_reg[2]/D ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9603, routed) 1.941 -2.401 u_Axi_CDC/arFifo/pushToPopGray_buffercc/sys_clk SLICE_X20Y64 FDCE r u_Axi_CDC/arFifo/pushToPopGray_buffercc/buffers_0_reg[2]/C Slack: inf Source: u_Axi_CDC/bFifo/popCC_ptrToPush_reg[0]/C (rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Destination: u_Axi_CDC/bFifo/popToPushGray_buffercc/buffers_0_reg[0]/D (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: (none) Path Type: Hold (Min at Slow Process Corner) Data Path Delay: 0.878ns (logic 0.367ns (41.779%) route 0.511ns (58.221%)) Logic Levels: 0 Clock Path Skew: -0.389ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -2.400ns Source Clock Delay (SCD): -2.010ns Clock Pessimism Removal (CPR): -0.000ns Clock Uncertainty: 0.194ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.130ns Phase Error (PE): 0.120ns Timing Exception: Asynchronous Clock Groups Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.393 1.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 2.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -8.248 -5.674 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 1.755 -3.919 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.091 -3.828 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 1.818 -2.010 u_Axi_CDC/bFifo/cpu_clk SLICE_X15Y61 FDCE r u_Axi_CDC/bFifo/popCC_ptrToPush_reg[0]/C ------------------------------------------------------------------- ------------------- SLICE_X15Y61 FDCE (Prop_fdce_C_Q) 0.367 -1.643 r u_Axi_CDC/bFifo/popCC_ptrToPush_reg[0]/Q net (fo=2, routed) 0.511 -1.132 u_Axi_CDC/bFifo/popToPushGray_buffercc/D[0] SLICE_X17Y63 FDCE r u_Axi_CDC/bFifo/popToPushGray_buffercc/buffers_0_reg[0]/D ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9603, routed) 1.942 -2.400 u_Axi_CDC/bFifo/popToPushGray_buffercc/sys_clk SLICE_X17Y63 FDCE r u_Axi_CDC/bFifo/popToPushGray_buffercc/buffers_0_reg[0]/C Slack: inf Source: u_Axi_CDC/awFifo/pushCC_pushPtrGray_reg[1]/C (rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Destination: u_Axi_CDC/awFifo/pushToPopGray_buffercc/buffers_0_reg[1]/D (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: (none) Path Type: Hold (Min at Slow Process Corner) Data Path Delay: 0.900ns (logic 0.367ns (40.793%) route 0.533ns (59.207%)) Logic Levels: 0 Clock Path Skew: -0.388ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -2.399ns Source Clock Delay (SCD): -2.010ns Clock Pessimism Removal (CPR): -0.000ns Clock Uncertainty: 0.194ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.130ns Phase Error (PE): 0.120ns Timing Exception: Asynchronous Clock Groups Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.393 1.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 2.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -8.248 -5.674 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 1.755 -3.919 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.091 -3.828 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 1.818 -2.010 u_Axi_CDC/awFifo/cpu_clk SLICE_X17Y61 FDCE r u_Axi_CDC/awFifo/pushCC_pushPtrGray_reg[1]/C ------------------------------------------------------------------- ------------------- SLICE_X17Y61 FDCE (Prop_fdce_C_Q) 0.367 -1.643 r u_Axi_CDC/awFifo/pushCC_pushPtrGray_reg[1]/Q net (fo=2, routed) 0.533 -1.111 u_Axi_CDC/awFifo/pushToPopGray_buffercc/Q[1] SLICE_X18Y62 FDCE r u_Axi_CDC/awFifo/pushToPopGray_buffercc/buffers_0_reg[1]/D ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9603, routed) 1.943 -2.399 u_Axi_CDC/awFifo/pushToPopGray_buffercc/sys_clk SLICE_X18Y62 FDCE r u_Axi_CDC/awFifo/pushToPopGray_buffercc/buffers_0_reg[1]/C Slack: inf Source: u_Axi_CDC/rFifo/popCC_ptrToPush_reg[3]/C (rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Destination: u_Axi_CDC/rFifo/popToPushGray_buffercc/buffers_0_reg[3]/D (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: (none) Path Type: Hold (Min at Slow Process Corner) Data Path Delay: 0.907ns (logic 0.367ns (40.482%) route 0.540ns (59.518%)) Logic Levels: 0 Clock Path Skew: -0.390ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -2.403ns Source Clock Delay (SCD): -2.012ns Clock Pessimism Removal (CPR): -0.000ns Clock Uncertainty: 0.194ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.130ns Phase Error (PE): 0.120ns Timing Exception: Asynchronous Clock Groups Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.393 1.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 2.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -8.248 -5.674 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 1.755 -3.919 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.091 -3.828 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 1.816 -2.012 u_Axi_CDC/rFifo/cpu_clk SLICE_X15Y64 FDCE r u_Axi_CDC/rFifo/popCC_ptrToPush_reg[3]/C ------------------------------------------------------------------- ------------------- SLICE_X15Y64 FDCE (Prop_fdce_C_Q) 0.367 -1.645 r u_Axi_CDC/rFifo/popCC_ptrToPush_reg[3]/Q net (fo=1, routed) 0.540 -1.106 u_Axi_CDC/rFifo/popToPushGray_buffercc/buffers_0_reg[3]_0[3] SLICE_X13Y66 FDCE r u_Axi_CDC/rFifo/popToPushGray_buffercc/buffers_0_reg[3]/D ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9603, routed) 1.939 -2.403 u_Axi_CDC/rFifo/popToPushGray_buffercc/sys_clk SLICE_X13Y66 FDCE r u_Axi_CDC/rFifo/popToPushGray_buffercc/buffers_0_reg[3]/C Slack: inf Source: u_Axi_CDC/wFifo/pushCC_pushPtrGray_reg[1]/C (rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Destination: u_Axi_CDC/wFifo/pushToPopGray_buffercc/buffers_0_reg[1]/D (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: (none) Path Type: Hold (Min at Slow Process Corner) Data Path Delay: 0.944ns (logic 0.418ns (44.265%) route 0.526ns (55.735%)) Logic Levels: 0 Clock Path Skew: -0.388ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -2.397ns Source Clock Delay (SCD): -2.008ns Clock Pessimism Removal (CPR): -0.000ns Clock Uncertainty: 0.194ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.130ns Phase Error (PE): 0.120ns Timing Exception: Asynchronous Clock Groups Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.393 1.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 2.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -8.248 -5.674 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 1.755 -3.919 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.091 -3.828 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 1.820 -2.008 u_Axi_CDC/wFifo/cpu_clk SLICE_X8Y58 FDCE r u_Axi_CDC/wFifo/pushCC_pushPtrGray_reg[1]/C ------------------------------------------------------------------- ------------------- SLICE_X8Y58 FDCE (Prop_fdce_C_Q) 0.418 -1.590 r u_Axi_CDC/wFifo/pushCC_pushPtrGray_reg[1]/Q net (fo=2, routed) 0.526 -1.064 u_Axi_CDC/wFifo/pushToPopGray_buffercc/D[1] SLICE_X12Y59 FDCE r u_Axi_CDC/wFifo/pushToPopGray_buffercc/buffers_0_reg[1]/D ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9603, routed) 1.945 -2.397 u_Axi_CDC/wFifo/pushToPopGray_buffercc/sys_clk SLICE_X12Y59 FDCE r u_Axi_CDC/wFifo/pushToPopGray_buffercc/buffers_0_reg[1]/C Slack: inf Source: u_Axi_CDC/rFifo/popCC_ptrToPush_reg[0]/C (rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Destination: u_Axi_CDC/rFifo/popToPushGray_buffercc/buffers_0_reg[0]/D (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: (none) Path Type: Hold (Min at Slow Process Corner) Data Path Delay: 1.186ns (logic 0.367ns (30.949%) route 0.819ns (69.051%)) Logic Levels: 0 Clock Path Skew: -0.387ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -2.400ns Source Clock Delay (SCD): -2.012ns Clock Pessimism Removal (CPR): -0.000ns Clock Uncertainty: 0.194ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.130ns Phase Error (PE): 0.120ns Timing Exception: Asynchronous Clock Groups Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.393 1.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 2.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -8.248 -5.674 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 1.755 -3.919 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.091 -3.828 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 1.816 -2.012 u_Axi_CDC/rFifo/cpu_clk SLICE_X15Y64 FDCE r u_Axi_CDC/rFifo/popCC_ptrToPush_reg[0]/C ------------------------------------------------------------------- ------------------- SLICE_X15Y64 FDCE (Prop_fdce_C_Q) 0.367 -1.645 r u_Axi_CDC/rFifo/popCC_ptrToPush_reg[0]/Q net (fo=1, routed) 0.819 -0.826 u_Axi_CDC/rFifo/popToPushGray_buffercc/buffers_0_reg[3]_0[0] SLICE_X14Y63 FDCE r u_Axi_CDC/rFifo/popToPushGray_buffercc/buffers_0_reg[0]/D ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9603, routed) 1.942 -2.400 u_Axi_CDC/rFifo/popToPushGray_buffercc/sys_clk SLICE_X14Y63 FDCE r u_Axi_CDC/rFifo/popToPushGray_buffercc/buffers_0_reg[0]/C Slack: inf Source: u_Axi_CDC/arFifo/ram_reg_0_3_48_53/RAMA_D1/CLK (rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Destination: u_Axi_CDC/arFifo/_zz_ram_port1_reg[49]/D (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: (none) Path Type: Hold (Min at Slow Process Corner) Data Path Delay: 1.215ns (logic 1.056ns (86.901%) route 0.159ns (13.099%)) Logic Levels: 0 Clock Path Skew: -0.387ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -2.420ns Source Clock Delay (SCD): -2.032ns Clock Pessimism Removal (CPR): -0.000ns Clock Uncertainty: 0.194ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.130ns Phase Error (PE): 0.120ns Timing Exception: Asynchronous Clock Groups Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.393 1.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 2.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -8.248 -5.674 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 1.755 -3.919 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.091 -3.828 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 1.796 -2.032 u_Axi_CDC/arFifo/ram_reg_0_3_48_53/WCLK SLICE_X36Y68 RAMD32 r u_Axi_CDC/arFifo/ram_reg_0_3_48_53/RAMA_D1/CLK ------------------------------------------------------------------- ------------------- SLICE_X36Y68 RAMD32 (Prop_ramd32_CLK_O) 1.056 -0.976 r u_Axi_CDC/arFifo/ram_reg_0_3_48_53/RAMA_D1/O net (fo=1, routed) 0.159 -0.817 u_Axi_CDC/arFifo/_zz_ram_port10__1[49] SLICE_X37Y68 FDRE r u_Axi_CDC/arFifo/_zz_ram_port1_reg[49]/D ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9603, routed) 1.922 -2.420 u_Axi_CDC/arFifo/sys_clk SLICE_X37Y68 FDRE r u_Axi_CDC/arFifo/_zz_ram_port1_reg[49]/C Slack: inf Source: u_Axi_CDC/wFifo/pushCC_pushPtrGray_reg[2]/C (rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Destination: u_Axi_CDC/wFifo/pushToPopGray_buffercc/buffers_0_reg[2]/D (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: (none) Path Type: Hold (Min at Slow Process Corner) Data Path Delay: 1.202ns (logic 0.418ns (34.765%) route 0.784ns (65.235%)) Logic Levels: 0 Clock Path Skew: -0.389ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -2.397ns Source Clock Delay (SCD): -2.007ns Clock Pessimism Removal (CPR): -0.000ns Clock Uncertainty: 0.194ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.130ns Phase Error (PE): 0.120ns Timing Exception: Asynchronous Clock Groups Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.393 1.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 2.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -8.248 -5.674 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 1.755 -3.919 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.091 -3.828 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 1.821 -2.007 u_Axi_CDC/wFifo/cpu_clk SLICE_X10Y58 FDCE r u_Axi_CDC/wFifo/pushCC_pushPtrGray_reg[2]/C ------------------------------------------------------------------- ------------------- SLICE_X10Y58 FDCE (Prop_fdce_C_Q) 0.418 -1.589 r u_Axi_CDC/wFifo/pushCC_pushPtrGray_reg[2]/Q net (fo=3, routed) 0.784 -0.805 u_Axi_CDC/wFifo/pushToPopGray_buffercc/D[2] SLICE_X12Y59 FDCE r u_Axi_CDC/wFifo/pushToPopGray_buffercc/buffers_0_reg[2]/D ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9603, routed) 1.945 -2.397 u_Axi_CDC/wFifo/pushToPopGray_buffercc/sys_clk SLICE_X12Y59 FDCE r u_Axi_CDC/wFifo/pushToPopGray_buffercc/buffers_0_reg[2]/C Slack: inf Source: u_Axi_CDC/arFifo/ram_reg_0_3_36_41/RAMA_D1/CLK (rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Destination: u_Axi_CDC/arFifo/_zz_ram_port1_reg[37]/D (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: (none) Path Type: Hold (Min at Slow Process Corner) Data Path Delay: 1.215ns (logic 1.056ns (86.901%) route 0.159ns (13.099%)) Logic Levels: 0 Clock Path Skew: -0.387ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -2.406ns Source Clock Delay (SCD): -2.018ns Clock Pessimism Removal (CPR): -0.000ns Clock Uncertainty: 0.194ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.130ns Phase Error (PE): 0.120ns Timing Exception: Asynchronous Clock Groups Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.393 1.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 2.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -8.248 -5.674 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 1.755 -3.919 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.091 -3.828 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 1.810 -2.018 u_Axi_CDC/arFifo/ram_reg_0_3_36_41/WCLK SLICE_X22Y67 RAMD32 r u_Axi_CDC/arFifo/ram_reg_0_3_36_41/RAMA_D1/CLK ------------------------------------------------------------------- ------------------- SLICE_X22Y67 RAMD32 (Prop_ramd32_CLK_O) 1.056 -0.962 r u_Axi_CDC/arFifo/ram_reg_0_3_36_41/RAMA_D1/O net (fo=1, routed) 0.159 -0.803 u_Axi_CDC/arFifo/_zz_ram_port10__1[37] SLICE_X23Y67 FDRE r u_Axi_CDC/arFifo/_zz_ram_port1_reg[37]/D ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9603, routed) 1.936 -2.406 u_Axi_CDC/arFifo/sys_clk SLICE_X23Y67 FDRE r u_Axi_CDC/arFifo/_zz_ram_port1_reg[37]/C Slack: inf Source: u_Axi_CDC/awFifo/ram_reg_0_3_18_23/RAMB_D1/CLK (rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Destination: u_Axi_CDC/awFifo/_zz_ram_port1_reg[21]/D (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: (none) Path Type: Hold (Min at Slow Process Corner) Data Path Delay: 1.221ns (logic 1.062ns (86.996%) route 0.159ns (13.004%)) Logic Levels: 0 Clock Path Skew: -0.386ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -2.402ns Source Clock Delay (SCD): -2.015ns Clock Pessimism Removal (CPR): -0.000ns Clock Uncertainty: 0.194ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.130ns Phase Error (PE): 0.120ns Timing Exception: Asynchronous Clock Groups Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.393 1.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 2.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -8.248 -5.674 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 1.755 -3.919 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.091 -3.828 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 1.813 -2.015 u_Axi_CDC/awFifo/ram_reg_0_3_18_23/WCLK SLICE_X22Y63 RAMD32 r u_Axi_CDC/awFifo/ram_reg_0_3_18_23/RAMB_D1/CLK ------------------------------------------------------------------- ------------------- SLICE_X22Y63 RAMD32 (Prop_ramd32_CLK_O) 1.062 -0.953 r u_Axi_CDC/awFifo/ram_reg_0_3_18_23/RAMB_D1/O net (fo=1, routed) 0.159 -0.795 u_Axi_CDC/awFifo/_zz_ram_port10[21] SLICE_X23Y63 FDRE r u_Axi_CDC/awFifo/_zz_ram_port1_reg[21]/D ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9603, routed) 1.940 -2.402 u_Axi_CDC/awFifo/sys_clk SLICE_X23Y63 FDRE r u_Axi_CDC/awFifo/_zz_ram_port1_reg[21]/C Slack: inf Source: u_Axi_CDC/arFifo/ram_reg_0_3_42_47/RAMB/CLK (rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Destination: u_Axi_CDC/arFifo/_zz_ram_port1_reg[44]/D (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: (none) Path Type: Hold (Min at Slow Process Corner) Data Path Delay: 1.245ns (logic 1.083ns (86.954%) route 0.162ns (13.046%)) Logic Levels: 0 Clock Path Skew: -0.387ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -2.405ns Source Clock Delay (SCD): -2.017ns Clock Pessimism Removal (CPR): -0.000ns Clock Uncertainty: 0.194ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.130ns Phase Error (PE): 0.120ns Timing Exception: Asynchronous Clock Groups Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.393 1.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 2.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -8.248 -5.674 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 1.755 -3.919 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.091 -3.828 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 1.811 -2.017 u_Axi_CDC/arFifo/ram_reg_0_3_42_47/WCLK SLICE_X22Y66 RAMD32 r u_Axi_CDC/arFifo/ram_reg_0_3_42_47/RAMB/CLK ------------------------------------------------------------------- ------------------- SLICE_X22Y66 RAMD32 (Prop_ramd32_CLK_O) 1.083 -0.934 r u_Axi_CDC/arFifo/ram_reg_0_3_42_47/RAMB/O net (fo=1, routed) 0.162 -0.772 u_Axi_CDC/arFifo/_zz_ram_port10__1[44] SLICE_X23Y66 FDRE r u_Axi_CDC/arFifo/_zz_ram_port1_reg[44]/D ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9603, routed) 1.937 -2.405 u_Axi_CDC/arFifo/sys_clk SLICE_X23Y66 FDRE r u_Axi_CDC/arFifo/_zz_ram_port1_reg[44]/C Slack: inf Source: u_Axi_CDC/wFifo/ram_reg_0_7_36_36/RAMA/CLK (rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Destination: u_Axi_CDC/wFifo/_zz_ram_port1_reg[36]/D (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: (none) Path Type: Hold (Min at Slow Process Corner) Data Path Delay: 1.246ns (logic 1.084ns (86.999%) route 0.162ns (13.001%)) Logic Levels: 0 Clock Path Skew: -0.386ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -2.394ns Source Clock Delay (SCD): -2.007ns Clock Pessimism Removal (CPR): -0.000ns Clock Uncertainty: 0.194ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.130ns Phase Error (PE): 0.120ns Timing Exception: Asynchronous Clock Groups Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.393 1.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 2.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -8.248 -5.674 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 1.755 -3.919 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.091 -3.828 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 1.821 -2.007 u_Axi_CDC/wFifo/ram_reg_0_7_36_36/WCLK SLICE_X10Y57 RAMD32 r u_Axi_CDC/wFifo/ram_reg_0_7_36_36/RAMA/CLK ------------------------------------------------------------------- ------------------- SLICE_X10Y57 RAMD32 (Prop_ramd32_CLK_O) 1.084 -0.923 r u_Axi_CDC/wFifo/ram_reg_0_7_36_36/RAMA/O net (fo=1, routed) 0.162 -0.761 u_Axi_CDC/wFifo/_zz_ram_port10__0[36] SLICE_X11Y57 FDRE r u_Axi_CDC/wFifo/_zz_ram_port1_reg[36]/D ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9603, routed) 1.948 -2.394 u_Axi_CDC/wFifo/sys_clk SLICE_X11Y57 FDRE r u_Axi_CDC/wFifo/_zz_ram_port1_reg[36]/C Slack: inf Source: u_Axi_CDC/arFifo/ram_reg_0_3_30_35/RAMC_D1/CLK (rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Destination: u_Axi_CDC/arFifo/_zz_ram_port1_reg[35]/D (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: (none) Path Type: Hold (Min at Slow Process Corner) Data Path Delay: 1.301ns (logic 1.059ns (81.402%) route 0.242ns (18.598%)) Logic Levels: 0 Clock Path Skew: -0.389ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -2.420ns Source Clock Delay (SCD): -2.030ns Clock Pessimism Removal (CPR): -0.000ns Clock Uncertainty: 0.194ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.130ns Phase Error (PE): 0.120ns Timing Exception: Asynchronous Clock Groups Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.393 1.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 2.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -8.248 -5.674 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 1.755 -3.919 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.091 -3.828 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 1.798 -2.030 u_Axi_CDC/arFifo/ram_reg_0_3_30_35/WCLK SLICE_X36Y67 RAMD32 r u_Axi_CDC/arFifo/ram_reg_0_3_30_35/RAMC_D1/CLK ------------------------------------------------------------------- ------------------- SLICE_X36Y67 RAMD32 (Prop_ramd32_CLK_O) 1.059 -0.971 r u_Axi_CDC/arFifo/ram_reg_0_3_30_35/RAMC_D1/O net (fo=1, routed) 0.242 -0.729 u_Axi_CDC/arFifo/_zz_ram_port10__1[35] SLICE_X37Y68 FDRE r u_Axi_CDC/arFifo/_zz_ram_port1_reg[35]/D ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9603, routed) 1.922 -2.420 u_Axi_CDC/arFifo/sys_clk SLICE_X37Y68 FDRE r u_Axi_CDC/arFifo/_zz_ram_port1_reg[35]/C Slack: inf Source: u_Axi_CDC/awFifo/ram_reg_0_3_36_41/RAMB_D1/CLK (rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Destination: u_Axi_CDC/awFifo/_zz_ram_port1_reg[39]/D (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: (none) Path Type: Hold (Min at Slow Process Corner) Data Path Delay: 1.347ns (logic 1.062ns (78.867%) route 0.285ns (21.133%)) Logic Levels: 0 Clock Path Skew: -0.390ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -2.424ns Source Clock Delay (SCD): -2.033ns Clock Pessimism Removal (CPR): -0.000ns Clock Uncertainty: 0.194ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.130ns Phase Error (PE): 0.120ns Timing Exception: Asynchronous Clock Groups Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.393 1.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 2.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -8.248 -5.674 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 1.755 -3.919 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.091 -3.828 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 1.795 -2.033 u_Axi_CDC/awFifo/ram_reg_0_3_36_41/WCLK SLICE_X36Y70 RAMD32 r u_Axi_CDC/awFifo/ram_reg_0_3_36_41/RAMB_D1/CLK ------------------------------------------------------------------- ------------------- SLICE_X36Y70 RAMD32 (Prop_ramd32_CLK_O) 1.062 -0.971 r u_Axi_CDC/awFifo/ram_reg_0_3_36_41/RAMB_D1/O net (fo=1, routed) 0.285 -0.687 u_Axi_CDC/awFifo/_zz_ram_port10[39] SLICE_X38Y70 FDRE r u_Axi_CDC/awFifo/_zz_ram_port1_reg[39]/D ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9603, routed) 1.918 -2.424 u_Axi_CDC/awFifo/sys_clk SLICE_X38Y70 FDRE r u_Axi_CDC/awFifo/_zz_ram_port1_reg[39]/C Slack: inf Source: u_Axi_CDC/awFifo/ram_reg_0_3_36_41/RAMC_D1/CLK (rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Destination: u_Axi_CDC/awFifo/_zz_ram_port1_reg[41]/D (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: (none) Path Type: Hold (Min at Slow Process Corner) Data Path Delay: 1.349ns (logic 1.059ns (78.530%) route 0.290ns (21.470%)) Logic Levels: 0 Clock Path Skew: -0.390ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -2.424ns Source Clock Delay (SCD): -2.033ns Clock Pessimism Removal (CPR): -0.000ns Clock Uncertainty: 0.194ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.130ns Phase Error (PE): 0.120ns Timing Exception: Asynchronous Clock Groups Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.393 1.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 2.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -8.248 -5.674 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 1.755 -3.919 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.091 -3.828 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 1.795 -2.033 u_Axi_CDC/awFifo/ram_reg_0_3_36_41/WCLK SLICE_X36Y70 RAMD32 r u_Axi_CDC/awFifo/ram_reg_0_3_36_41/RAMC_D1/CLK ------------------------------------------------------------------- ------------------- SLICE_X36Y70 RAMD32 (Prop_ramd32_CLK_O) 1.059 -0.974 r u_Axi_CDC/awFifo/ram_reg_0_3_36_41/RAMC_D1/O net (fo=1, routed) 0.290 -0.685 u_Axi_CDC/awFifo/_zz_ram_port10[41] SLICE_X38Y70 FDRE r u_Axi_CDC/awFifo/_zz_ram_port1_reg[41]/D ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9603, routed) 1.918 -2.424 u_Axi_CDC/awFifo/sys_clk SLICE_X38Y70 FDRE r u_Axi_CDC/awFifo/_zz_ram_port1_reg[41]/C Slack: inf Source: u_Axi_CDC/awFifo/ram_reg_0_3_0_5/RAMB_D1/CLK (rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Destination: u_Axi_CDC/awFifo/_zz_ram_port1_reg[3]/D (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: (none) Path Type: Hold (Min at Slow Process Corner) Data Path Delay: 1.348ns (logic 1.062ns (78.762%) route 0.286ns (21.238%)) Logic Levels: 0 Clock Path Skew: -0.387ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -2.397ns Source Clock Delay (SCD): -2.009ns Clock Pessimism Removal (CPR): -0.000ns Clock Uncertainty: 0.194ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.130ns Phase Error (PE): 0.120ns Timing Exception: Asynchronous Clock Groups Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.393 1.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 2.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -8.248 -5.674 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 1.755 -3.919 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.091 -3.828 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 1.819 -2.009 u_Axi_CDC/awFifo/ram_reg_0_3_0_5/WCLK SLICE_X16Y60 RAMD32 r u_Axi_CDC/awFifo/ram_reg_0_3_0_5/RAMB_D1/CLK ------------------------------------------------------------------- ------------------- SLICE_X16Y60 RAMD32 (Prop_ramd32_CLK_O) 1.062 -0.947 r u_Axi_CDC/awFifo/ram_reg_0_3_0_5/RAMB_D1/O net (fo=1, routed) 0.286 -0.661 u_Axi_CDC/awFifo/_zz_ram_port10[3] SLICE_X14Y60 FDRE r u_Axi_CDC/awFifo/_zz_ram_port1_reg[3]/D ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9603, routed) 1.945 -2.397 u_Axi_CDC/awFifo/sys_clk SLICE_X14Y60 FDRE r u_Axi_CDC/awFifo/_zz_ram_port1_reg[3]/C Slack: inf Source: u_Axi_CDC/awFifo/ram_reg_0_3_18_23/RAMC/CLK (rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Destination: u_Axi_CDC/awFifo/_zz_ram_port1_reg[22]/D (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: (none) Path Type: Hold (Min at Slow Process Corner) Data Path Delay: 1.360ns (logic 1.078ns (79.282%) route 0.282ns (20.718%)) Logic Levels: 0 Clock Path Skew: -0.388ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -2.404ns Source Clock Delay (SCD): -2.015ns Clock Pessimism Removal (CPR): -0.000ns Clock Uncertainty: 0.194ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.130ns Phase Error (PE): 0.120ns Timing Exception: Asynchronous Clock Groups Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.393 1.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 2.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -8.248 -5.674 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 1.755 -3.919 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.091 -3.828 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 1.813 -2.015 u_Axi_CDC/awFifo/ram_reg_0_3_18_23/WCLK SLICE_X22Y63 RAMD32 r u_Axi_CDC/awFifo/ram_reg_0_3_18_23/RAMC/CLK ------------------------------------------------------------------- ------------------- SLICE_X22Y63 RAMD32 (Prop_ramd32_CLK_O) 1.078 -0.937 r u_Axi_CDC/awFifo/ram_reg_0_3_18_23/RAMC/O net (fo=1, routed) 0.282 -0.656 u_Axi_CDC/awFifo/_zz_ram_port10[22] SLICE_X23Y65 FDRE r u_Axi_CDC/awFifo/_zz_ram_port1_reg[22]/D ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9603, routed) 1.938 -2.404 u_Axi_CDC/awFifo/sys_clk SLICE_X23Y65 FDRE r u_Axi_CDC/awFifo/_zz_ram_port1_reg[22]/C Slack: inf Source: u_Axi_CDC/wFifo/ram_reg_0_7_30_35/RAMC/CLK (rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Destination: u_Axi_CDC/wFifo/_zz_ram_port1_reg[34]/D (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: (none) Path Type: Hold (Min at Slow Process Corner) Data Path Delay: 1.359ns (logic 1.078ns (79.297%) route 0.281ns (20.703%)) Logic Levels: 0 Clock Path Skew: -0.387ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -2.394ns Source Clock Delay (SCD): -2.006ns Clock Pessimism Removal (CPR): -0.000ns Clock Uncertainty: 0.194ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.130ns Phase Error (PE): 0.120ns Timing Exception: Asynchronous Clock Groups Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.393 1.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 2.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -8.248 -5.674 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 1.755 -3.919 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.091 -3.828 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 1.822 -2.006 u_Axi_CDC/wFifo/ram_reg_0_7_30_35/WCLK SLICE_X10Y56 RAMD32 r u_Axi_CDC/wFifo/ram_reg_0_7_30_35/RAMC/CLK ------------------------------------------------------------------- ------------------- SLICE_X10Y56 RAMD32 (Prop_ramd32_CLK_O) 1.078 -0.928 r u_Axi_CDC/wFifo/ram_reg_0_7_30_35/RAMC/O net (fo=1, routed) 0.281 -0.647 u_Axi_CDC/wFifo/_zz_ram_port10__0[34] SLICE_X11Y57 FDRE r u_Axi_CDC/wFifo/_zz_ram_port1_reg[34]/D ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9603, routed) 1.948 -2.394 u_Axi_CDC/wFifo/sys_clk SLICE_X11Y57 FDRE r u_Axi_CDC/wFifo/_zz_ram_port1_reg[34]/C Slack: inf Source: u_Axi_CDC/awFifo/ram_reg_0_3_6_11/RAMA/CLK (rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Destination: u_Axi_CDC/awFifo/_zz_ram_port1_reg[6]/D (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: (none) Path Type: Hold (Min at Slow Process Corner) Data Path Delay: 1.363ns (logic 1.084ns (79.504%) route 0.279ns (20.496%)) Logic Levels: 0 Clock Path Skew: -0.387ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -2.397ns Source Clock Delay (SCD): -2.009ns Clock Pessimism Removal (CPR): -0.000ns Clock Uncertainty: 0.194ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.130ns Phase Error (PE): 0.120ns Timing Exception: Asynchronous Clock Groups Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.393 1.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 2.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -8.248 -5.674 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 1.755 -3.919 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.091 -3.828 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 1.819 -2.009 u_Axi_CDC/awFifo/ram_reg_0_3_6_11/WCLK SLICE_X14Y59 RAMD32 r u_Axi_CDC/awFifo/ram_reg_0_3_6_11/RAMA/CLK ------------------------------------------------------------------- ------------------- SLICE_X14Y59 RAMD32 (Prop_ramd32_CLK_O) 1.084 -0.925 r u_Axi_CDC/awFifo/ram_reg_0_3_6_11/RAMA/O net (fo=1, routed) 0.279 -0.646 u_Axi_CDC/awFifo/_zz_ram_port10[6] SLICE_X14Y60 FDRE r u_Axi_CDC/awFifo/_zz_ram_port1_reg[6]/D ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9603, routed) 1.945 -2.397 u_Axi_CDC/awFifo/sys_clk SLICE_X14Y60 FDRE r u_Axi_CDC/awFifo/_zz_ram_port1_reg[6]/C Slack: inf Source: u_Axi_CDC/awFifo/ram_reg_0_3_6_11/RAMB/CLK (rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Destination: u_Axi_CDC/awFifo/_zz_ram_port1_reg[8]/D (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: (none) Path Type: Hold (Min at Slow Process Corner) Data Path Delay: 1.364ns (logic 1.083ns (79.398%) route 0.281ns (20.602%)) Logic Levels: 0 Clock Path Skew: -0.387ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -2.397ns Source Clock Delay (SCD): -2.009ns Clock Pessimism Removal (CPR): -0.000ns Clock Uncertainty: 0.194ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.130ns Phase Error (PE): 0.120ns Timing Exception: Asynchronous Clock Groups Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.393 1.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 2.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -8.248 -5.674 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 1.755 -3.919 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.091 -3.828 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 1.819 -2.009 u_Axi_CDC/awFifo/ram_reg_0_3_6_11/WCLK SLICE_X14Y59 RAMD32 r u_Axi_CDC/awFifo/ram_reg_0_3_6_11/RAMB/CLK ------------------------------------------------------------------- ------------------- SLICE_X14Y59 RAMD32 (Prop_ramd32_CLK_O) 1.083 -0.926 r u_Axi_CDC/awFifo/ram_reg_0_3_6_11/RAMB/O net (fo=1, routed) 0.281 -0.645 u_Axi_CDC/awFifo/_zz_ram_port10[8] SLICE_X14Y60 FDRE r u_Axi_CDC/awFifo/_zz_ram_port1_reg[8]/D ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9603, routed) 1.945 -2.397 u_Axi_CDC/awFifo/sys_clk SLICE_X14Y60 FDRE r u_Axi_CDC/awFifo/_zz_ram_port1_reg[8]/C Slack: inf Source: u_Axi_CDC/awFifo/ram_reg_0_3_0_5/RAMB/CLK (rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Destination: u_Axi_CDC/awFifo/_zz_ram_port1_reg[2]/D (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: (none) Path Type: Hold (Min at Slow Process Corner) Data Path Delay: 1.366ns (logic 1.083ns (79.267%) route 0.283ns (20.733%)) Logic Levels: 0 Clock Path Skew: -0.389ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -2.399ns Source Clock Delay (SCD): -2.009ns Clock Pessimism Removal (CPR): -0.000ns Clock Uncertainty: 0.194ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.130ns Phase Error (PE): 0.120ns Timing Exception: Asynchronous Clock Groups Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.393 1.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 2.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -8.248 -5.674 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 1.755 -3.919 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.091 -3.828 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 1.819 -2.009 u_Axi_CDC/awFifo/ram_reg_0_3_0_5/WCLK SLICE_X16Y60 RAMD32 r u_Axi_CDC/awFifo/ram_reg_0_3_0_5/RAMB/CLK ------------------------------------------------------------------- ------------------- SLICE_X16Y60 RAMD32 (Prop_ramd32_CLK_O) 1.083 -0.926 r u_Axi_CDC/awFifo/ram_reg_0_3_0_5/RAMB/O net (fo=1, routed) 0.283 -0.643 u_Axi_CDC/awFifo/_zz_ram_port10[2] SLICE_X16Y62 FDRE r u_Axi_CDC/awFifo/_zz_ram_port1_reg[2]/D ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9603, routed) 1.943 -2.399 u_Axi_CDC/awFifo/sys_clk SLICE_X16Y62 FDRE r u_Axi_CDC/awFifo/_zz_ram_port1_reg[2]/C Slack: inf Source: u_Axi_CDC/awFifo/ram_reg_0_3_12_17/RAMA/CLK (rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Destination: u_Axi_CDC/awFifo/_zz_ram_port1_reg[12]/D (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: (none) Path Type: Hold (Min at Slow Process Corner) Data Path Delay: 1.372ns (logic 1.084ns (78.983%) route 0.288ns (21.017%)) Logic Levels: 0 Clock Path Skew: -0.387ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -2.398ns Source Clock Delay (SCD): -2.010ns Clock Pessimism Removal (CPR): -0.000ns Clock Uncertainty: 0.194ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.130ns Phase Error (PE): 0.120ns Timing Exception: Asynchronous Clock Groups Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.393 1.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 2.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -8.248 -5.674 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 1.755 -3.919 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.091 -3.828 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 1.818 -2.010 u_Axi_CDC/awFifo/ram_reg_0_3_12_17/WCLK SLICE_X20Y59 RAMD32 r u_Axi_CDC/awFifo/ram_reg_0_3_12_17/RAMA/CLK ------------------------------------------------------------------- ------------------- SLICE_X20Y59 RAMD32 (Prop_ramd32_CLK_O) 1.084 -0.926 r u_Axi_CDC/awFifo/ram_reg_0_3_12_17/RAMA/O net (fo=1, routed) 0.288 -0.638 u_Axi_CDC/awFifo/_zz_ram_port10[12] SLICE_X21Y59 FDRE r u_Axi_CDC/awFifo/_zz_ram_port1_reg[12]/D ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9603, routed) 1.944 -2.398 u_Axi_CDC/awFifo/sys_clk SLICE_X21Y59 FDRE r u_Axi_CDC/awFifo/_zz_ram_port1_reg[12]/C Slack: inf Source: u_Axi_CDC/wFifo/ram_reg_0_7_6_11/RAMC_D1/CLK (rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Destination: u_Axi_CDC/wFifo/_zz_ram_port1_reg[11]/D (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: (none) Path Type: Hold (Min at Slow Process Corner) Data Path Delay: 1.315ns (logic 1.059ns (80.521%) route 0.256ns (19.479%)) Logic Levels: 0 Clock Path Skew: -0.388ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -2.318ns Source Clock Delay (SCD): -1.929ns Clock Pessimism Removal (CPR): -0.000ns Clock Uncertainty: 0.194ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.130ns Phase Error (PE): 0.120ns Timing Exception: Asynchronous Clock Groups Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.393 1.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 2.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -8.248 -5.674 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 1.755 -3.919 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.091 -3.828 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 1.899 -1.929 u_Axi_CDC/wFifo/ram_reg_0_7_6_11/WCLK SLICE_X6Y56 RAMD32 r u_Axi_CDC/wFifo/ram_reg_0_7_6_11/RAMC_D1/CLK ------------------------------------------------------------------- ------------------- SLICE_X6Y56 RAMD32 (Prop_ramd32_CLK_O) 1.059 -0.870 r u_Axi_CDC/wFifo/ram_reg_0_7_6_11/RAMC_D1/O net (fo=1, routed) 0.256 -0.614 u_Axi_CDC/wFifo/_zz_ram_port10__0[11] SLICE_X6Y58 FDRE r u_Axi_CDC/wFifo/_zz_ram_port1_reg[11]/D ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9603, routed) 2.024 -2.318 u_Axi_CDC/wFifo/sys_clk SLICE_X6Y58 FDRE r u_Axi_CDC/wFifo/_zz_ram_port1_reg[11]/C Slack: inf Source: u_Axi_CDC/awFifo/ram_reg_0_3_48_53/RAMA/CLK (rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Destination: u_Axi_CDC/awFifo/_zz_ram_port1_reg[48]/D (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: (none) Path Type: Hold (Min at Slow Process Corner) Data Path Delay: 1.430ns (logic 1.084ns (75.807%) route 0.346ns (24.193%)) Logic Levels: 0 Clock Path Skew: -0.389ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -2.429ns Source Clock Delay (SCD): -2.039ns Clock Pessimism Removal (CPR): -0.000ns Clock Uncertainty: 0.194ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.130ns Phase Error (PE): 0.120ns Timing Exception: Asynchronous Clock Groups Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.393 1.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 2.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -8.248 -5.674 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 1.755 -3.919 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.091 -3.828 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 1.789 -2.039 u_Axi_CDC/awFifo/ram_reg_0_3_48_53/WCLK SLICE_X36Y75 RAMD32 r u_Axi_CDC/awFifo/ram_reg_0_3_48_53/RAMA/CLK ------------------------------------------------------------------- ------------------- SLICE_X36Y75 RAMD32 (Prop_ramd32_CLK_O) 1.084 -0.955 r u_Axi_CDC/awFifo/ram_reg_0_3_48_53/RAMA/O net (fo=1, routed) 0.346 -0.609 u_Axi_CDC/awFifo/_zz_ram_port10[48] SLICE_X37Y75 FDRE r u_Axi_CDC/awFifo/_zz_ram_port1_reg[48]/D ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9603, routed) 1.913 -2.429 u_Axi_CDC/awFifo/sys_clk SLICE_X37Y75 FDRE r u_Axi_CDC/awFifo/_zz_ram_port1_reg[48]/C Slack: inf Source: u_Axi_CDC/arFifo/ram_reg_0_3_48_53/RAMC/CLK (rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Destination: u_Axi_CDC/arFifo/_zz_ram_port1_reg[52]/D (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: (none) Path Type: Hold (Min at Slow Process Corner) Data Path Delay: 1.434ns (logic 1.078ns (75.181%) route 0.356ns (24.819%)) Logic Levels: 0 Clock Path Skew: -0.389ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -2.422ns Source Clock Delay (SCD): -2.032ns Clock Pessimism Removal (CPR): -0.000ns Clock Uncertainty: 0.194ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.130ns Phase Error (PE): 0.120ns Timing Exception: Asynchronous Clock Groups Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.393 1.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 2.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -8.248 -5.674 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 1.755 -3.919 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.091 -3.828 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 1.796 -2.032 u_Axi_CDC/arFifo/ram_reg_0_3_48_53/WCLK SLICE_X36Y68 RAMD32 r u_Axi_CDC/arFifo/ram_reg_0_3_48_53/RAMC/CLK ------------------------------------------------------------------- ------------------- SLICE_X36Y68 RAMD32 (Prop_ramd32_CLK_O) 1.078 -0.954 r u_Axi_CDC/arFifo/ram_reg_0_3_48_53/RAMC/O net (fo=1, routed) 0.356 -0.598 u_Axi_CDC/arFifo/_zz_ram_port10__1[52] SLICE_X40Y68 FDRE r u_Axi_CDC/arFifo/_zz_ram_port1_reg[52]/D ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9603, routed) 1.920 -2.422 u_Axi_CDC/arFifo/sys_clk SLICE_X40Y68 FDRE r u_Axi_CDC/arFifo/_zz_ram_port1_reg[52]/C Slack: inf Source: u_Axi_CDC/arFifo/ram_reg_0_3_12_17/RAMA/CLK (rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Destination: u_Axi_CDC/arFifo/_zz_ram_port1_reg[12]/D (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: (none) Path Type: Hold (Min at Slow Process Corner) Data Path Delay: 1.426ns (logic 1.084ns (76.011%) route 0.342ns (23.989%)) Logic Levels: 0 Clock Path Skew: -0.391ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -2.405ns Source Clock Delay (SCD): -2.013ns Clock Pessimism Removal (CPR): -0.000ns Clock Uncertainty: 0.194ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.130ns Phase Error (PE): 0.120ns Timing Exception: Asynchronous Clock Groups Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.393 1.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 2.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -8.248 -5.674 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 1.755 -3.919 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.091 -3.828 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 1.815 -2.013 u_Axi_CDC/arFifo/ram_reg_0_3_12_17/WCLK SLICE_X22Y61 RAMD32 r u_Axi_CDC/arFifo/ram_reg_0_3_12_17/RAMA/CLK ------------------------------------------------------------------- ------------------- SLICE_X22Y61 RAMD32 (Prop_ramd32_CLK_O) 1.084 -0.929 r u_Axi_CDC/arFifo/ram_reg_0_3_12_17/RAMA/O net (fo=1, routed) 0.342 -0.587 u_Axi_CDC/arFifo/_zz_ram_port10__1[12] SLICE_X24Y61 FDRE r u_Axi_CDC/arFifo/_zz_ram_port1_reg[12]/D ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9603, routed) 1.937 -2.405 u_Axi_CDC/arFifo/sys_clk SLICE_X24Y61 FDRE r u_Axi_CDC/arFifo/_zz_ram_port1_reg[12]/C Slack: inf Source: u_Axi_CDC/awFifo/ram_reg_0_3_48_53/RAMB_D1/CLK (rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Destination: u_Axi_CDC/awFifo/_zz_ram_port1_reg[51]/D (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: (none) Path Type: Hold (Min at Slow Process Corner) Data Path Delay: 1.457ns (logic 1.062ns (72.891%) route 0.395ns (27.109%)) Logic Levels: 0 Clock Path Skew: -0.389ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -2.429ns Source Clock Delay (SCD): -2.039ns Clock Pessimism Removal (CPR): -0.000ns Clock Uncertainty: 0.194ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.130ns Phase Error (PE): 0.120ns Timing Exception: Asynchronous Clock Groups Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.393 1.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 2.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -8.248 -5.674 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 1.755 -3.919 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.091 -3.828 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 1.789 -2.039 u_Axi_CDC/awFifo/ram_reg_0_3_48_53/WCLK SLICE_X36Y75 RAMD32 r u_Axi_CDC/awFifo/ram_reg_0_3_48_53/RAMB_D1/CLK ------------------------------------------------------------------- ------------------- SLICE_X36Y75 RAMD32 (Prop_ramd32_CLK_O) 1.062 -0.977 r u_Axi_CDC/awFifo/ram_reg_0_3_48_53/RAMB_D1/O net (fo=1, routed) 0.395 -0.582 u_Axi_CDC/awFifo/_zz_ram_port10[51] SLICE_X37Y75 FDRE r u_Axi_CDC/awFifo/_zz_ram_port1_reg[51]/D ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9603, routed) 1.913 -2.429 u_Axi_CDC/awFifo/sys_clk SLICE_X37Y75 FDRE r u_Axi_CDC/awFifo/_zz_ram_port1_reg[51]/C Slack: inf Source: u_Axi_CDC/awFifo/ram_reg_0_3_48_53/RAMC_D1/CLK (rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Destination: u_Axi_CDC/awFifo/_zz_ram_port1_reg[53]/D (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: (none) Path Type: Hold (Min at Slow Process Corner) Data Path Delay: 1.462ns (logic 1.059ns (72.454%) route 0.403ns (27.546%)) Logic Levels: 0 Clock Path Skew: -0.389ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -2.429ns Source Clock Delay (SCD): -2.039ns Clock Pessimism Removal (CPR): -0.000ns Clock Uncertainty: 0.194ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.130ns Phase Error (PE): 0.120ns Timing Exception: Asynchronous Clock Groups Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.393 1.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 2.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -8.248 -5.674 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 1.755 -3.919 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.091 -3.828 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 1.789 -2.039 u_Axi_CDC/awFifo/ram_reg_0_3_48_53/WCLK SLICE_X36Y75 RAMD32 r u_Axi_CDC/awFifo/ram_reg_0_3_48_53/RAMC_D1/CLK ------------------------------------------------------------------- ------------------- SLICE_X36Y75 RAMD32 (Prop_ramd32_CLK_O) 1.059 -0.980 r u_Axi_CDC/awFifo/ram_reg_0_3_48_53/RAMC_D1/O net (fo=1, routed) 0.403 -0.578 u_Axi_CDC/awFifo/_zz_ram_port10[53] SLICE_X38Y76 FDRE r u_Axi_CDC/awFifo/_zz_ram_port1_reg[53]/D ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9603, routed) 1.913 -2.429 u_Axi_CDC/awFifo/sys_clk SLICE_X38Y76 FDRE r u_Axi_CDC/awFifo/_zz_ram_port1_reg[53]/C Slack: inf Source: u_Axi_CDC/arFifo/ram_reg_0_3_30_35/RAMB/CLK (rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Destination: u_Axi_CDC/arFifo/_zz_ram_port1_reg[32]/D (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: (none) Path Type: Hold (Min at Slow Process Corner) Data Path Delay: 1.454ns (logic 1.083ns (74.467%) route 0.371ns (25.533%)) Logic Levels: 0 Clock Path Skew: -0.389ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -2.420ns Source Clock Delay (SCD): -2.030ns Clock Pessimism Removal (CPR): -0.000ns Clock Uncertainty: 0.194ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.130ns Phase Error (PE): 0.120ns Timing Exception: Asynchronous Clock Groups Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.393 1.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 2.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -8.248 -5.674 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 1.755 -3.919 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.091 -3.828 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 1.798 -2.030 u_Axi_CDC/arFifo/ram_reg_0_3_30_35/WCLK SLICE_X36Y67 RAMD32 r u_Axi_CDC/arFifo/ram_reg_0_3_30_35/RAMB/CLK ------------------------------------------------------------------- ------------------- SLICE_X36Y67 RAMD32 (Prop_ramd32_CLK_O) 1.083 -0.947 r u_Axi_CDC/arFifo/ram_reg_0_3_30_35/RAMB/O net (fo=1, routed) 0.371 -0.576 u_Axi_CDC/arFifo/_zz_ram_port10__1[32] SLICE_X37Y68 FDRE r u_Axi_CDC/arFifo/_zz_ram_port1_reg[32]/D ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9603, routed) 1.922 -2.420 u_Axi_CDC/arFifo/sys_clk SLICE_X37Y68 FDRE r u_Axi_CDC/arFifo/_zz_ram_port1_reg[32]/C Slack: inf Source: u_Axi_CDC/awFifo/ram_reg_0_3_30_35/RAMA_D1/CLK (rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Destination: u_Axi_CDC/awFifo/_zz_ram_port1_reg[31]/D (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: (none) Path Type: Hold (Min at Slow Process Corner) Data Path Delay: 1.462ns (logic 1.056ns (72.211%) route 0.406ns (27.789%)) Logic Levels: 0 Clock Path Skew: -0.389ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -2.426ns Source Clock Delay (SCD): -2.036ns Clock Pessimism Removal (CPR): -0.000ns Clock Uncertainty: 0.194ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.130ns Phase Error (PE): 0.120ns Timing Exception: Asynchronous Clock Groups Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.393 1.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 2.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -8.248 -5.674 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 1.755 -3.919 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.091 -3.828 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 1.792 -2.036 u_Axi_CDC/awFifo/ram_reg_0_3_30_35/WCLK SLICE_X36Y72 RAMD32 r u_Axi_CDC/awFifo/ram_reg_0_3_30_35/RAMA_D1/CLK ------------------------------------------------------------------- ------------------- SLICE_X36Y72 RAMD32 (Prop_ramd32_CLK_O) 1.056 -0.980 r u_Axi_CDC/awFifo/ram_reg_0_3_30_35/RAMA_D1/O net (fo=1, routed) 0.406 -0.574 u_Axi_CDC/awFifo/_zz_ram_port10[31] SLICE_X37Y72 FDRE r u_Axi_CDC/awFifo/_zz_ram_port1_reg[31]/D ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9603, routed) 1.916 -2.426 u_Axi_CDC/awFifo/sys_clk SLICE_X37Y72 FDRE r u_Axi_CDC/awFifo/_zz_ram_port1_reg[31]/C Slack: inf Source: u_Axi_CDC/arFifo/ram_reg_0_3_24_29/RAMC_D1/CLK (rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Destination: u_Axi_CDC/arFifo/_zz_ram_port1_reg[29]/D (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: (none) Path Type: Hold (Min at Slow Process Corner) Data Path Delay: 1.455ns (logic 1.059ns (72.788%) route 0.396ns (27.212%)) Logic Levels: 0 Clock Path Skew: -0.391ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -2.408ns Source Clock Delay (SCD): -2.016ns Clock Pessimism Removal (CPR): -0.000ns Clock Uncertainty: 0.194ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.130ns Phase Error (PE): 0.120ns Timing Exception: Asynchronous Clock Groups Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.393 1.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 2.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -8.248 -5.674 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 1.755 -3.919 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.091 -3.828 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 1.812 -2.016 u_Axi_CDC/arFifo/ram_reg_0_3_24_29/WCLK SLICE_X22Y65 RAMD32 r u_Axi_CDC/arFifo/ram_reg_0_3_24_29/RAMC_D1/CLK ------------------------------------------------------------------- ------------------- SLICE_X22Y65 RAMD32 (Prop_ramd32_CLK_O) 1.059 -0.957 r u_Axi_CDC/arFifo/ram_reg_0_3_24_29/RAMC_D1/O net (fo=1, routed) 0.396 -0.561 u_Axi_CDC/arFifo/_zz_ram_port10__1[29] SLICE_X22Y68 FDRE r u_Axi_CDC/arFifo/_zz_ram_port1_reg[29]/D ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9603, routed) 1.934 -2.408 u_Axi_CDC/arFifo/sys_clk SLICE_X22Y68 FDRE r u_Axi_CDC/arFifo/_zz_ram_port1_reg[29]/C Slack: inf Source: u_Axi_CDC/arFifo/ram_reg_0_3_12_17/RAMB_D1/CLK (rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Destination: u_Axi_CDC/arFifo/_zz_ram_port1_reg[15]/D (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: (none) Path Type: Hold (Min at Slow Process Corner) Data Path Delay: 1.457ns (logic 1.062ns (72.893%) route 0.395ns (27.107%)) Logic Levels: 0 Clock Path Skew: -0.388ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -2.402ns Source Clock Delay (SCD): -2.013ns Clock Pessimism Removal (CPR): -0.000ns Clock Uncertainty: 0.194ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.130ns Phase Error (PE): 0.120ns Timing Exception: Asynchronous Clock Groups Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.393 1.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 2.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -8.248 -5.674 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 1.755 -3.919 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.091 -3.828 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 1.815 -2.013 u_Axi_CDC/arFifo/ram_reg_0_3_12_17/WCLK SLICE_X22Y61 RAMD32 r u_Axi_CDC/arFifo/ram_reg_0_3_12_17/RAMB_D1/CLK ------------------------------------------------------------------- ------------------- SLICE_X22Y61 RAMD32 (Prop_ramd32_CLK_O) 1.062 -0.951 r u_Axi_CDC/arFifo/ram_reg_0_3_12_17/RAMB_D1/O net (fo=1, routed) 0.395 -0.556 u_Axi_CDC/arFifo/_zz_ram_port10__1[15] SLICE_X23Y64 FDRE r u_Axi_CDC/arFifo/_zz_ram_port1_reg[15]/D ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9603, routed) 1.940 -2.402 u_Axi_CDC/arFifo/sys_clk SLICE_X23Y64 FDRE r u_Axi_CDC/arFifo/_zz_ram_port1_reg[15]/C Slack: inf Source: u_Axi_CDC/awFifo/ram_reg_0_3_0_5/RAMC_D1/CLK (rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Destination: u_Axi_CDC/awFifo/_zz_ram_port1_reg[5]/D (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: (none) Path Type: Hold (Min at Slow Process Corner) Data Path Delay: 1.454ns (logic 1.059ns (72.851%) route 0.395ns (27.149%)) Logic Levels: 0 Clock Path Skew: -0.389ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -2.399ns Source Clock Delay (SCD): -2.009ns Clock Pessimism Removal (CPR): -0.000ns Clock Uncertainty: 0.194ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.130ns Phase Error (PE): 0.120ns Timing Exception: Asynchronous Clock Groups Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.393 1.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 2.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -8.248 -5.674 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 1.755 -3.919 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.091 -3.828 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 1.819 -2.009 u_Axi_CDC/awFifo/ram_reg_0_3_0_5/WCLK SLICE_X16Y60 RAMD32 r u_Axi_CDC/awFifo/ram_reg_0_3_0_5/RAMC_D1/CLK ------------------------------------------------------------------- ------------------- SLICE_X16Y60 RAMD32 (Prop_ramd32_CLK_O) 1.059 -0.950 r u_Axi_CDC/awFifo/ram_reg_0_3_0_5/RAMC_D1/O net (fo=1, routed) 0.395 -0.556 u_Axi_CDC/awFifo/_zz_ram_port10[5] SLICE_X16Y62 FDRE r u_Axi_CDC/awFifo/_zz_ram_port1_reg[5]/D ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9603, routed) 1.943 -2.399 u_Axi_CDC/awFifo/sys_clk SLICE_X16Y62 FDRE r u_Axi_CDC/awFifo/_zz_ram_port1_reg[5]/C Slack: inf Source: u_Axi_CDC/wFifo/ram_reg_0_7_6_11/RAMB/CLK (rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Destination: u_Axi_CDC/wFifo/_zz_ram_port1_reg[8]/D (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: (none) Path Type: Hold (Min at Slow Process Corner) Data Path Delay: 1.375ns (logic 1.083ns (78.752%) route 0.292ns (21.248%)) Logic Levels: 0 Clock Path Skew: -0.388ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -2.318ns Source Clock Delay (SCD): -1.929ns Clock Pessimism Removal (CPR): -0.000ns Clock Uncertainty: 0.194ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.130ns Phase Error (PE): 0.120ns Timing Exception: Asynchronous Clock Groups Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.393 1.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 2.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -8.248 -5.674 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 1.755 -3.919 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.091 -3.828 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 1.899 -1.929 u_Axi_CDC/wFifo/ram_reg_0_7_6_11/WCLK SLICE_X6Y56 RAMD32 r u_Axi_CDC/wFifo/ram_reg_0_7_6_11/RAMB/CLK ------------------------------------------------------------------- ------------------- SLICE_X6Y56 RAMD32 (Prop_ramd32_CLK_O) 1.083 -0.846 r u_Axi_CDC/wFifo/ram_reg_0_7_6_11/RAMB/O net (fo=1, routed) 0.292 -0.554 u_Axi_CDC/wFifo/_zz_ram_port10__0[8] SLICE_X4Y57 FDRE r u_Axi_CDC/wFifo/_zz_ram_port1_reg[8]/D ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9603, routed) 2.024 -2.318 u_Axi_CDC/wFifo/sys_clk SLICE_X4Y57 FDRE r u_Axi_CDC/wFifo/_zz_ram_port1_reg[8]/C Slack: inf Source: u_Axi_CDC/awFifo/ram_reg_0_3_42_47/RAMC_D1/CLK (rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Destination: u_Axi_CDC/awFifo/_zz_ram_port1_reg[47]/D (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: (none) Path Type: Hold (Min at Slow Process Corner) Data Path Delay: 1.476ns (logic 1.059ns (71.725%) route 0.417ns (28.275%)) Logic Levels: 0 Clock Path Skew: -0.381ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -2.409ns Source Clock Delay (SCD): -2.027ns Clock Pessimism Removal (CPR): -0.000ns Clock Uncertainty: 0.194ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.130ns Phase Error (PE): 0.120ns Timing Exception: Asynchronous Clock Groups Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.393 1.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 2.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -8.248 -5.674 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 1.755 -3.919 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.091 -3.828 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 1.801 -2.027 u_Axi_CDC/awFifo/ram_reg_0_3_42_47/WCLK SLICE_X36Y63 RAMD32 r u_Axi_CDC/awFifo/ram_reg_0_3_42_47/RAMC_D1/CLK ------------------------------------------------------------------- ------------------- SLICE_X36Y63 RAMD32 (Prop_ramd32_CLK_O) 1.059 -0.968 r u_Axi_CDC/awFifo/ram_reg_0_3_42_47/RAMC_D1/O net (fo=1, routed) 0.417 -0.551 u_Axi_CDC/awFifo/_zz_ram_port10[47] SLICE_X33Y62 FDRE r u_Axi_CDC/awFifo/_zz_ram_port1_reg[47]/D ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9603, routed) 1.933 -2.409 u_Axi_CDC/awFifo/sys_clk SLICE_X33Y62 FDRE r u_Axi_CDC/awFifo/_zz_ram_port1_reg[47]/C Slack: inf Source: u_Axi_CDC/wFifo/ram_reg_0_7_12_17/RAMB_D1/CLK (rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Destination: u_Axi_CDC/wFifo/_zz_ram_port1_reg[15]/D (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: (none) Path Type: Hold (Min at Slow Process Corner) Data Path Delay: 1.457ns (logic 1.062ns (72.891%) route 0.395ns (27.109%)) Logic Levels: 0 Clock Path Skew: -0.387ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -2.395ns Source Clock Delay (SCD): -2.007ns Clock Pessimism Removal (CPR): -0.000ns Clock Uncertainty: 0.194ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.130ns Phase Error (PE): 0.120ns Timing Exception: Asynchronous Clock Groups Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.393 1.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 2.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -8.248 -5.674 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 1.755 -3.919 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.091 -3.828 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 1.821 -2.007 u_Axi_CDC/wFifo/ram_reg_0_7_12_17/WCLK SLICE_X8Y54 RAMD32 r u_Axi_CDC/wFifo/ram_reg_0_7_12_17/RAMB_D1/CLK ------------------------------------------------------------------- ------------------- SLICE_X8Y54 RAMD32 (Prop_ramd32_CLK_O) 1.062 -0.945 r u_Axi_CDC/wFifo/ram_reg_0_7_12_17/RAMB_D1/O net (fo=1, routed) 0.395 -0.550 u_Axi_CDC/wFifo/_zz_ram_port10__0[15] SLICE_X9Y56 FDRE r u_Axi_CDC/wFifo/_zz_ram_port1_reg[15]/D ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9603, routed) 1.947 -2.395 u_Axi_CDC/wFifo/sys_clk SLICE_X9Y56 FDRE r u_Axi_CDC/wFifo/_zz_ram_port1_reg[15]/C Slack: inf Source: u_Axi_CDC/wFifo/ram_reg_0_7_30_35/RAMB_D1/CLK (rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Destination: u_Axi_CDC/wFifo/_zz_ram_port1_reg[33]/D (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: (none) Path Type: Hold (Min at Slow Process Corner) Data Path Delay: 1.457ns (logic 1.062ns (72.904%) route 0.395ns (27.096%)) Logic Levels: 0 Clock Path Skew: -0.387ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -2.394ns Source Clock Delay (SCD): -2.006ns Clock Pessimism Removal (CPR): -0.000ns Clock Uncertainty: 0.194ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.130ns Phase Error (PE): 0.120ns Timing Exception: Asynchronous Clock Groups Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.393 1.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 2.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -8.248 -5.674 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 1.755 -3.919 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.091 -3.828 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 1.822 -2.006 u_Axi_CDC/wFifo/ram_reg_0_7_30_35/WCLK SLICE_X10Y56 RAMD32 r u_Axi_CDC/wFifo/ram_reg_0_7_30_35/RAMB_D1/CLK ------------------------------------------------------------------- ------------------- SLICE_X10Y56 RAMD32 (Prop_ramd32_CLK_O) 1.062 -0.944 r u_Axi_CDC/wFifo/ram_reg_0_7_30_35/RAMB_D1/O net (fo=1, routed) 0.395 -0.550 u_Axi_CDC/wFifo/_zz_ram_port10__0[33] SLICE_X11Y57 FDRE r u_Axi_CDC/wFifo/_zz_ram_port1_reg[33]/D ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9603, routed) 1.948 -2.394 u_Axi_CDC/wFifo/sys_clk SLICE_X11Y57 FDRE r u_Axi_CDC/wFifo/_zz_ram_port1_reg[33]/C Slack: inf Source: u_Axi_CDC/awFifo/ram_reg_0_3_36_41/RAMC/CLK (rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Destination: u_Axi_CDC/awFifo/_zz_ram_port1_reg[40]/D (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: (none) Path Type: Hold (Min at Slow Process Corner) Data Path Delay: 1.485ns (logic 1.078ns (72.582%) route 0.407ns (27.418%)) Logic Levels: 0 Clock Path Skew: -0.390ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -2.424ns Source Clock Delay (SCD): -2.033ns Clock Pessimism Removal (CPR): -0.000ns Clock Uncertainty: 0.194ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.130ns Phase Error (PE): 0.120ns Timing Exception: Asynchronous Clock Groups Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.393 1.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 2.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -8.248 -5.674 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 1.755 -3.919 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.091 -3.828 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 1.795 -2.033 u_Axi_CDC/awFifo/ram_reg_0_3_36_41/WCLK SLICE_X36Y70 RAMD32 r u_Axi_CDC/awFifo/ram_reg_0_3_36_41/RAMC/CLK ------------------------------------------------------------------- ------------------- SLICE_X36Y70 RAMD32 (Prop_ramd32_CLK_O) 1.078 -0.955 r u_Axi_CDC/awFifo/ram_reg_0_3_36_41/RAMC/O net (fo=1, routed) 0.407 -0.548 u_Axi_CDC/awFifo/_zz_ram_port10[40] SLICE_X38Y70 FDRE r u_Axi_CDC/awFifo/_zz_ram_port1_reg[40]/D ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9603, routed) 1.918 -2.424 u_Axi_CDC/awFifo/sys_clk SLICE_X38Y70 FDRE r u_Axi_CDC/awFifo/_zz_ram_port1_reg[40]/C Slack: inf Source: u_Axi_CDC/arFifo/ram_reg_0_3_30_35/RAMB_D1/CLK (rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Destination: u_Axi_CDC/arFifo/_zz_ram_port1_reg[33]/D (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: (none) Path Type: Hold (Min at Slow Process Corner) Data Path Delay: 1.483ns (logic 1.062ns (71.634%) route 0.421ns (28.366%)) Logic Levels: 0 Clock Path Skew: -0.385ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -2.416ns Source Clock Delay (SCD): -2.030ns Clock Pessimism Removal (CPR): -0.000ns Clock Uncertainty: 0.194ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.130ns Phase Error (PE): 0.120ns Timing Exception: Asynchronous Clock Groups Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.393 1.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 2.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -8.248 -5.674 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 1.755 -3.919 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.091 -3.828 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 1.798 -2.030 u_Axi_CDC/arFifo/ram_reg_0_3_30_35/WCLK SLICE_X36Y67 RAMD32 r u_Axi_CDC/arFifo/ram_reg_0_3_30_35/RAMB_D1/CLK ------------------------------------------------------------------- ------------------- SLICE_X36Y67 RAMD32 (Prop_ramd32_CLK_O) 1.062 -0.968 r u_Axi_CDC/arFifo/ram_reg_0_3_30_35/RAMB_D1/O net (fo=1, routed) 0.421 -0.548 u_Axi_CDC/arFifo/_zz_ram_port10__1[33] SLICE_X33Y68 FDRE r u_Axi_CDC/arFifo/_zz_ram_port1_reg[33]/D ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9603, routed) 1.926 -2.416 u_Axi_CDC/arFifo/sys_clk SLICE_X33Y68 FDRE r u_Axi_CDC/arFifo/_zz_ram_port1_reg[33]/C Slack: inf Source: u_Axi_CDC/awFifo/ram_reg_0_3_48_53/RAMA_D1/CLK (rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Destination: u_Axi_CDC/awFifo/_zz_ram_port1_reg[49]/D (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: (none) Path Type: Hold (Min at Slow Process Corner) Data Path Delay: 1.492ns (logic 1.056ns (70.798%) route 0.436ns (29.202%)) Logic Levels: 0 Clock Path Skew: -0.389ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -2.429ns Source Clock Delay (SCD): -2.039ns Clock Pessimism Removal (CPR): -0.000ns Clock Uncertainty: 0.194ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.130ns Phase Error (PE): 0.120ns Timing Exception: Asynchronous Clock Groups Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.393 1.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 2.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -8.248 -5.674 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 1.755 -3.919 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.091 -3.828 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 1.789 -2.039 u_Axi_CDC/awFifo/ram_reg_0_3_48_53/WCLK SLICE_X36Y75 RAMD32 r u_Axi_CDC/awFifo/ram_reg_0_3_48_53/RAMA_D1/CLK ------------------------------------------------------------------- ------------------- SLICE_X36Y75 RAMD32 (Prop_ramd32_CLK_O) 1.056 -0.983 r u_Axi_CDC/awFifo/ram_reg_0_3_48_53/RAMA_D1/O net (fo=1, routed) 0.436 -0.548 u_Axi_CDC/awFifo/_zz_ram_port10[49] SLICE_X37Y75 FDRE r u_Axi_CDC/awFifo/_zz_ram_port1_reg[49]/D ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9603, routed) 1.913 -2.429 u_Axi_CDC/awFifo/sys_clk SLICE_X37Y75 FDRE r u_Axi_CDC/awFifo/_zz_ram_port1_reg[49]/C -------------------------------------------------------------------------------------- Path Group: (none) From Clock: clkfbout_clk_pll To Clock: Max Delay 0 Endpoints Min Delay 1 Endpoint -------------------------------------------------------------------------------------- Min Delay Paths -------------------------------------------------------------------------------------- Slack: inf Source: pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKFBOUT (clock source 'clkfbout_clk_pll' {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKFBIN Path Group: (none) Path Type: Min at Slow Process Corner Data Path Delay: 3.498ns (logic 0.091ns (2.602%) route 3.407ns (97.398%)) Logic Levels: 1 (BUFG=1) Clock Uncertainty: 0.169ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.050ns Discrete Jitter (DJ): 0.075ns Phase Error (PE): 0.124ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock clkfbout_clk_pll rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.393 1.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.181 2.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll ------------------------------------------------------------------- ------------------- PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKFBOUT) -8.248 -5.674 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKFBOUT net (fo=1, routed) 1.755 -3.919 pll_clk.u_clk_pll/inst/clkfbout_clk_pll BUFGCTRL_X0Y19 BUFG (Prop_bufg_I_O) 0.091 -3.828 r pll_clk.u_clk_pll/inst/clkf_buf/O net (fo=1, routed) 1.652 -2.177 pll_clk.u_clk_pll/inst/clkfbout_buf_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKFBIN ------------------------------------------------------------------- ------------------- -------------------------------------------------------------------------------------- Path Group: (none) From Clock: sys_clk To Clock: Max Delay 0 Endpoints Min Delay 41 Endpoints -------------------------------------------------------------------------------------- Min Delay Paths -------------------------------------------------------------------------------------- Slack: inf Source: pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 (clock source 'sys_clk' {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: video_clk (output port) Path Group: (none) Path Type: Min at Fast Process Corner Data Path Delay: 2.614ns (logic 1.260ns (48.196%) route 1.354ns (51.804%)) Logic Levels: 2 (BUFG=1 OBUF=1) Clock Uncertainty: 0.190ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.050ns Discrete Jitter (DJ): 0.122ns Phase Error (PE): 0.124ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll ------------------------------------------------------------------- ------------------- PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9603, routed) 0.794 -0.468 video_clk_OBUF H22 OBUF (Prop_obuf_I_O) 1.234 0.766 r video_clk_OBUF_inst/O net (fo=0) 0.000 0.766 video_clk H22 r video_clk (OUT) ------------------------------------------------------------------- ------------------- Slack: inf Source: u_confreg/led_data_reg[7]_lopt_replica/C (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: leds[7] (output port) Path Group: (none) Path Type: Min at Fast Process Corner Data Path Delay: 2.774ns (logic 1.414ns (50.960%) route 1.360ns (49.040%)) Logic Levels: 1 (OBUF=1) Clock Uncertainty: 0.190ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.050ns Discrete Jitter (DJ): 0.122ns Phase Error (PE): 0.124ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9603, routed) 0.717 -0.545 u_confreg/sys_clk SLICE_X0Y80 FDRE r u_confreg/led_data_reg[7]_lopt_replica/C ------------------------------------------------------------------- ------------------- SLICE_X0Y80 FDRE (Prop_fdre_C_Q) 0.141 -0.404 r u_confreg/led_data_reg[7]_lopt_replica/Q net (fo=1, routed) 1.360 0.956 lopt_13 B22 OBUF (Prop_obuf_I_O) 1.273 2.228 r leds_OBUF[7]_inst/O net (fo=0) 0.000 2.228 leds[7] B22 r leds[7] (OUT) ------------------------------------------------------------------- ------------------- Slack: inf Source: u_confreg/led_data_reg[0]_lopt_replica/C (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: leds[0] (output port) Path Group: (none) Path Type: Min at Fast Process Corner Data Path Delay: 2.793ns (logic 1.416ns (50.701%) route 1.377ns (49.299%)) Logic Levels: 1 (OBUF=1) Clock Uncertainty: 0.190ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.050ns Discrete Jitter (DJ): 0.122ns Phase Error (PE): 0.124ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9603, routed) 0.720 -0.542 u_confreg/sys_clk SLICE_X4Y89 FDRE r u_confreg/led_data_reg[0]_lopt_replica/C ------------------------------------------------------------------- ------------------- SLICE_X4Y89 FDRE (Prop_fdre_C_Q) 0.141 -0.401 r u_confreg/led_data_reg[0]_lopt_replica/Q net (fo=1, routed) 1.377 0.976 lopt B24 OBUF (Prop_obuf_I_O) 1.275 2.251 r leds_OBUF[0]_inst/O net (fo=0) 0.000 2.251 leds[0] B24 r leds[0] (OUT) ------------------------------------------------------------------- ------------------- Slack: inf Source: u_confreg/led_data_reg[5]_lopt_replica/C (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: leds[5] (output port) Path Group: (none) Path Type: Min at Fast Process Corner Data Path Delay: 2.812ns (logic 1.395ns (49.604%) route 1.417ns (50.396%)) Logic Levels: 1 (OBUF=1) Clock Uncertainty: 0.190ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.050ns Discrete Jitter (DJ): 0.122ns Phase Error (PE): 0.124ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9603, routed) 0.717 -0.545 u_confreg/sys_clk SLICE_X1Y80 FDRE r u_confreg/led_data_reg[5]_lopt_replica/C ------------------------------------------------------------------- ------------------- SLICE_X1Y80 FDRE (Prop_fdre_C_Q) 0.141 -0.404 r u_confreg/led_data_reg[5]_lopt_replica/Q net (fo=1, routed) 1.417 1.013 lopt_11 C21 OBUF (Prop_obuf_I_O) 1.254 2.267 r leds_OBUF[5]_inst/O net (fo=0) 0.000 2.267 leds[5] C21 r leds[5] (OUT) ------------------------------------------------------------------- ------------------- Slack: inf Source: u_confreg/led_data_reg[12]_lopt_replica/C (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: leds[12] (output port) Path Group: (none) Path Type: Min at Fast Process Corner Data Path Delay: 2.822ns (logic 1.407ns (49.861%) route 1.415ns (50.139%)) Logic Levels: 1 (OBUF=1) Clock Uncertainty: 0.190ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.050ns Discrete Jitter (DJ): 0.122ns Phase Error (PE): 0.124ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9603, routed) 0.720 -0.542 u_confreg/sys_clk SLICE_X2Y83 FDRE r u_confreg/led_data_reg[12]_lopt_replica/C ------------------------------------------------------------------- ------------------- SLICE_X2Y83 FDRE (Prop_fdre_C_Q) 0.164 -0.378 r u_confreg/led_data_reg[12]_lopt_replica/Q net (fo=1, routed) 1.415 1.037 lopt_3 D20 OBUF (Prop_obuf_I_O) 1.243 2.280 r leds_OBUF[12]_inst/O net (fo=0) 0.000 2.280 leds[12] D20 r leds[12] (OUT) ------------------------------------------------------------------- ------------------- Slack: inf Source: u_axi_dvi/hdata_reg[8]/C (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: video_hsync (output port) Path Group: (none) Path Type: Min at Fast Process Corner Data Path Delay: 2.853ns (logic 1.432ns (50.177%) route 1.422ns (49.823%)) Logic Levels: 2 (LUT5=1 OBUF=1) Clock Uncertainty: 0.190ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.050ns Discrete Jitter (DJ): 0.122ns Phase Error (PE): 0.124ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9603, routed) 0.712 -0.550 u_axi_dvi/sys_clk SLICE_X5Y77 FDRE r u_axi_dvi/hdata_reg[8]/C ------------------------------------------------------------------- ------------------- SLICE_X5Y77 FDRE (Prop_fdre_C_Q) 0.141 -0.409 r u_axi_dvi/hdata_reg[8]/Q net (fo=12, routed) 0.308 -0.101 u_axi_dvi/hdata_reg_n_0_[8] SLICE_X1Y79 LUT5 (Prop_lut5_I2_O) 0.045 -0.056 r u_axi_dvi/video_hsync_OBUF_inst_i_1/O net (fo=1, routed) 1.113 1.057 video_hsync_OBUF J24 OBUF (Prop_obuf_I_O) 1.246 2.303 r video_hsync_OBUF_inst/O net (fo=0) 0.000 2.303 video_hsync J24 r video_hsync (OUT) ------------------------------------------------------------------- ------------------- Slack: inf Source: u_confreg/led_data_reg[6]_lopt_replica/C (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: leds[6] (output port) Path Group: (none) Path Type: Min at Fast Process Corner Data Path Delay: 2.916ns (logic 1.383ns (47.448%) route 1.532ns (52.552%)) Logic Levels: 1 (OBUF=1) Clock Uncertainty: 0.190ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.050ns Discrete Jitter (DJ): 0.122ns Phase Error (PE): 0.124ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9603, routed) 0.719 -0.543 u_confreg/sys_clk SLICE_X0Y82 FDRE r u_confreg/led_data_reg[6]_lopt_replica/C ------------------------------------------------------------------- ------------------- SLICE_X0Y82 FDRE (Prop_fdre_C_Q) 0.141 -0.402 r u_confreg/led_data_reg[6]_lopt_replica/Q net (fo=1, routed) 1.532 1.130 lopt_12 E20 OBUF (Prop_obuf_I_O) 1.242 2.372 r leds_OBUF[6]_inst/O net (fo=0) 0.000 2.372 leds[6] E20 r leds[6] (OUT) ------------------------------------------------------------------- ------------------- Slack: inf Source: u_confreg/u_digitaltube_controller/dpy0_reg_reg[2]/C (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: dpy0[2] (output port) Path Group: (none) Path Type: Min at Fast Process Corner Data Path Delay: 2.954ns (logic 1.400ns (47.401%) route 1.554ns (52.599%)) Logic Levels: 1 (OBUF=1) Clock Uncertainty: 0.190ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.050ns Discrete Jitter (DJ): 0.122ns Phase Error (PE): 0.124ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9603, routed) 0.723 -0.539 u_confreg/u_digitaltube_controller/sys_clk SLICE_X1Y61 FDCE r u_confreg/u_digitaltube_controller/dpy0_reg_reg[2]/C ------------------------------------------------------------------- ------------------- SLICE_X1Y61 FDCE (Prop_fdce_C_Q) 0.141 -0.398 r u_confreg/u_digitaltube_controller/dpy0_reg_reg[2]/Q net (fo=1, routed) 1.554 1.155 dpy0_OBUF[2] B21 OBUF (Prop_obuf_I_O) 1.259 2.414 r dpy0_OBUF[2]_inst/O net (fo=0) 0.000 2.414 dpy0[2] B21 r dpy0[2] (OUT) ------------------------------------------------------------------- ------------------- Slack: inf Source: u_confreg/u_digitaltube_controller/dpy1_reg_reg[2]/C (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: dpy1[2] (output port) Path Group: (none) Path Type: Min at Fast Process Corner Data Path Delay: 3.062ns (logic 1.383ns (45.185%) route 1.678ns (54.815%)) Logic Levels: 1 (OBUF=1) Clock Uncertainty: 0.190ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.050ns Discrete Jitter (DJ): 0.122ns Phase Error (PE): 0.124ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9603, routed) 0.724 -0.538 u_confreg/u_digitaltube_controller/sys_clk SLICE_X1Y59 FDCE r u_confreg/u_digitaltube_controller/dpy1_reg_reg[2]/C ------------------------------------------------------------------- ------------------- SLICE_X1Y59 FDCE (Prop_fdce_C_Q) 0.141 -0.397 r u_confreg/u_digitaltube_controller/dpy1_reg_reg[2]/Q net (fo=1, routed) 1.678 1.281 dpy1_OBUF[2] E17 OBUF (Prop_obuf_I_O) 1.242 2.523 r dpy1_OBUF[2]_inst/O net (fo=0) 0.000 2.523 dpy1[2] E17 r dpy1[2] (OUT) ------------------------------------------------------------------- ------------------- Slack: inf Source: u_axi_dvi/vdata_reg[6]/C (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: video_vsync (output port) Path Group: (none) Path Type: Min at Fast Process Corner Data Path Delay: 3.116ns (logic 1.482ns (47.567%) route 1.634ns (52.433%)) Logic Levels: 3 (LUT4=1 LUT6=1 OBUF=1) Clock Uncertainty: 0.190ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.050ns Discrete Jitter (DJ): 0.122ns Phase Error (PE): 0.124ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9603, routed) 0.683 -0.579 u_axi_dvi/sys_clk SLICE_X11Y73 FDRE r u_axi_dvi/vdata_reg[6]/C ------------------------------------------------------------------- ------------------- SLICE_X11Y73 FDRE (Prop_fdre_C_Q) 0.141 -0.438 r u_axi_dvi/vdata_reg[6]/Q net (fo=13, routed) 0.091 -0.348 u_axi_dvi/vdata_reg_n_0_[6] SLICE_X10Y73 LUT6 (Prop_lut6_I1_O) 0.045 -0.303 r u_axi_dvi/video_vsync_OBUF_inst_i_2/O net (fo=1, routed) 0.296 -0.007 u_axi_dvi/video_vsync_OBUF_inst_i_2_n_0 SLICE_X8Y72 LUT4 (Prop_lut4_I0_O) 0.045 0.038 r u_axi_dvi/video_vsync_OBUF_inst_i_1/O net (fo=1, routed) 1.247 1.286 video_vsync_OBUF H24 OBUF (Prop_obuf_I_O) 1.251 2.537 r video_vsync_OBUF_inst/O net (fo=0) 0.000 2.537 video_vsync H24 r video_vsync (OUT) ------------------------------------------------------------------- ------------------- Slack: inf Source: u_confreg/u_digitaltube_controller/dpy1_reg_reg[1]/C (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: dpy1[1] (output port) Path Group: (none) Path Type: Min at Fast Process Corner Data Path Delay: 3.077ns (logic 1.391ns (45.198%) route 1.686ns (54.802%)) Logic Levels: 1 (OBUF=1) Clock Uncertainty: 0.190ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.050ns Discrete Jitter (DJ): 0.122ns Phase Error (PE): 0.124ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9603, routed) 0.723 -0.539 u_confreg/u_digitaltube_controller/sys_clk SLICE_X1Y60 FDCE r u_confreg/u_digitaltube_controller/dpy1_reg_reg[1]/C ------------------------------------------------------------------- ------------------- SLICE_X1Y60 FDCE (Prop_fdce_C_Q) 0.141 -0.398 r u_confreg/u_digitaltube_controller/dpy1_reg_reg[1]/Q net (fo=1, routed) 1.686 1.288 dpy1_OBUF[1] D16 OBUF (Prop_obuf_I_O) 1.250 2.538 r dpy1_OBUF[1]_inst/O net (fo=0) 0.000 2.538 dpy1[1] D16 r dpy1[1] (OUT) ------------------------------------------------------------------- ------------------- Slack: inf Source: u_confreg/u_digitaltube_controller/dpy0_reg_reg[0]/C (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: dpy0[0] (output port) Path Group: (none) Path Type: Min at Fast Process Corner Data Path Delay: 3.083ns (logic 1.402ns (45.458%) route 1.682ns (54.542%)) Logic Levels: 1 (OBUF=1) Clock Uncertainty: 0.190ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.050ns Discrete Jitter (DJ): 0.122ns Phase Error (PE): 0.124ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9603, routed) 0.723 -0.539 u_confreg/u_digitaltube_controller/sys_clk SLICE_X0Y61 FDCE r u_confreg/u_digitaltube_controller/dpy0_reg_reg[0]/C ------------------------------------------------------------------- ------------------- SLICE_X0Y61 FDCE (Prop_fdce_C_Q) 0.141 -0.398 r u_confreg/u_digitaltube_controller/dpy0_reg_reg[0]/Q net (fo=1, routed) 1.682 1.283 dpy0_OBUF[0] B19 OBUF (Prop_obuf_I_O) 1.261 2.544 r dpy0_OBUF[0]_inst/O net (fo=0) 0.000 2.544 dpy0[0] B19 r dpy0[0] (OUT) ------------------------------------------------------------------- ------------------- Slack: inf Source: u_confreg/led_data_reg[14]_lopt_replica/C (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: leds[14] (output port) Path Group: (none) Path Type: Min at Fast Process Corner Data Path Delay: 3.123ns (logic 1.427ns (45.701%) route 1.696ns (54.299%)) Logic Levels: 1 (OBUF=1) Clock Uncertainty: 0.190ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.050ns Discrete Jitter (DJ): 0.122ns Phase Error (PE): 0.124ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9603, routed) 0.720 -0.542 u_confreg/sys_clk SLICE_X2Y83 FDRE r u_confreg/led_data_reg[14]_lopt_replica/C ------------------------------------------------------------------- ------------------- SLICE_X2Y83 FDRE (Prop_fdre_C_Q) 0.164 -0.378 r u_confreg/led_data_reg[14]_lopt_replica/Q net (fo=1, routed) 1.696 1.318 lopt_5 A20 OBUF (Prop_obuf_I_O) 1.263 2.581 r leds_OBUF[14]_inst/O net (fo=0) 0.000 2.581 leds[14] A20 r leds[14] (OUT) ------------------------------------------------------------------- ------------------- Slack: inf Source: u_confreg/u_digitaltube_controller/dpy1_reg_reg[7]/C (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: dpy1[7] (output port) Path Group: (none) Path Type: Min at Fast Process Corner Data Path Delay: 3.156ns (logic 1.362ns (43.159%) route 1.794ns (56.841%)) Logic Levels: 1 (OBUF=1) Clock Uncertainty: 0.190ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.050ns Discrete Jitter (DJ): 0.122ns Phase Error (PE): 0.124ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9603, routed) 0.723 -0.539 u_confreg/u_digitaltube_controller/sys_clk SLICE_X1Y60 FDCE r u_confreg/u_digitaltube_controller/dpy1_reg_reg[7]/C ------------------------------------------------------------------- ------------------- SLICE_X1Y60 FDCE (Prop_fdce_C_Q) 0.141 -0.398 r u_confreg/u_digitaltube_controller/dpy1_reg_reg[7]/Q net (fo=1, routed) 1.794 1.396 dpy1_OBUF[7] G17 OBUF (Prop_obuf_I_O) 1.221 2.617 r dpy1_OBUF[7]_inst/O net (fo=0) 0.000 2.617 dpy1[7] G17 r dpy1[7] (OUT) ------------------------------------------------------------------- ------------------- Slack: inf Source: u_confreg/u_digitaltube_controller/dpy1_reg_reg[0]/C (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: dpy1[0] (output port) Path Group: (none) Path Type: Min at Fast Process Corner Data Path Delay: 3.196ns (logic 1.407ns (44.017%) route 1.789ns (55.983%)) Logic Levels: 1 (OBUF=1) Clock Uncertainty: 0.190ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.050ns Discrete Jitter (DJ): 0.122ns Phase Error (PE): 0.124ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9603, routed) 0.723 -0.539 u_confreg/u_digitaltube_controller/sys_clk SLICE_X0Y60 FDCE r u_confreg/u_digitaltube_controller/dpy1_reg_reg[0]/C ------------------------------------------------------------------- ------------------- SLICE_X0Y60 FDCE (Prop_fdce_C_Q) 0.141 -0.398 r u_confreg/u_digitaltube_controller/dpy1_reg_reg[0]/Q net (fo=1, routed) 1.789 1.391 dpy1_OBUF[0] A17 OBUF (Prop_obuf_I_O) 1.266 2.657 r dpy1_OBUF[0]_inst/O net (fo=0) 0.000 2.657 dpy1[0] A17 r dpy1[0] (OUT) ------------------------------------------------------------------- ------------------- Slack: inf Source: u_confreg/led_data_reg[2]_lopt_replica/C (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: leds[2] (output port) Path Group: (none) Path Type: Min at Fast Process Corner Data Path Delay: 3.238ns (logic 1.451ns (44.816%) route 1.787ns (55.184%)) Logic Levels: 1 (OBUF=1) Clock Uncertainty: 0.190ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.050ns Discrete Jitter (DJ): 0.122ns Phase Error (PE): 0.124ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9603, routed) 0.720 -0.542 u_confreg/sys_clk SLICE_X2Y83 FDRE r u_confreg/led_data_reg[2]_lopt_replica/C ------------------------------------------------------------------- ------------------- SLICE_X2Y83 FDRE (Prop_fdre_C_Q) 0.164 -0.378 r u_confreg/led_data_reg[2]_lopt_replica/Q net (fo=1, routed) 1.787 1.408 lopt_8 A24 OBUF (Prop_obuf_I_O) 1.287 2.696 r leds_OBUF[2]_inst/O net (fo=0) 0.000 2.696 leds[2] A24 r leds[2] (OUT) ------------------------------------------------------------------- ------------------- Slack: inf Source: u_confreg/led_data_reg[3]_lopt_replica/C (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: leds[3] (output port) Path Group: (none) Path Type: Min at Fast Process Corner Data Path Delay: 3.241ns (logic 1.427ns (44.021%) route 1.814ns (55.979%)) Logic Levels: 1 (OBUF=1) Clock Uncertainty: 0.190ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.050ns Discrete Jitter (DJ): 0.122ns Phase Error (PE): 0.124ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9603, routed) 0.721 -0.541 u_confreg/sys_clk SLICE_X2Y84 FDRE r u_confreg/led_data_reg[3]_lopt_replica/C ------------------------------------------------------------------- ------------------- SLICE_X2Y84 FDRE (Prop_fdre_C_Q) 0.164 -0.377 r u_confreg/led_data_reg[3]_lopt_replica/Q net (fo=1, routed) 1.814 1.437 lopt_9 D23 OBUF (Prop_obuf_I_O) 1.263 2.700 r leds_OBUF[3]_inst/O net (fo=0) 0.000 2.700 leds[3] D23 r leds[3] (OUT) ------------------------------------------------------------------- ------------------- Slack: inf Source: u_axi_uart_controller/uart0/regs/mode_reg_reg[1]/C (rising edge-triggered cell FDSE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: UART_RX (output port) Path Group: (none) Path Type: Min at Fast Process Corner Data Path Delay: 3.306ns (logic 0.965ns (29.189%) route 2.341ns (70.811%)) Logic Levels: 1 (OBUFT=1) Clock Uncertainty: 0.190ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.050ns Discrete Jitter (DJ): 0.122ns Phase Error (PE): 0.124ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9603, routed) 0.687 -0.575 u_axi_uart_controller/uart0/regs/sys_clk SLICE_X30Y59 FDSE r u_axi_uart_controller/uart0/regs/mode_reg_reg[1]/C ------------------------------------------------------------------- ------------------- SLICE_X30Y59 FDSE (Prop_fdse_C_Q) 0.141 -0.434 r u_axi_uart_controller/uart0/regs/mode_reg_reg[1]/Q net (fo=28, routed) 2.341 1.907 UART_RX_IOBUF_inst/T J20 OBUFT (TriStatD_obuft_T_O) 0.824 2.731 r UART_RX_IOBUF_inst/OBUFT/O net (fo=1, unset) 0.000 2.731 UART_RX J20 r UART_RX (INOUT) ------------------------------------------------------------------- ------------------- Slack: inf Source: u_confreg/led_data_reg[9]_lopt_replica/C (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: leds[9] (output port) Path Group: (none) Path Type: Min at Fast Process Corner Data Path Delay: 3.346ns (logic 1.485ns (44.370%) route 1.861ns (55.630%)) Logic Levels: 1 (OBUF=1) Clock Uncertainty: 0.190ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.050ns Discrete Jitter (DJ): 0.122ns Phase Error (PE): 0.124ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9603, routed) 0.720 -0.542 u_confreg/sys_clk SLICE_X2Y83 FDRE r u_confreg/led_data_reg[9]_lopt_replica/C ------------------------------------------------------------------- ------------------- SLICE_X2Y83 FDRE (Prop_fdre_C_Q) 0.148 -0.394 r u_confreg/led_data_reg[9]_lopt_replica/Q net (fo=1, routed) 1.861 1.467 lopt_15 A23 OBUF (Prop_obuf_I_O) 1.337 2.804 r leds_OBUF[9]_inst/O net (fo=0) 0.000 2.804 leds[9] A23 r leds[9] (OUT) ------------------------------------------------------------------- ------------------- Slack: inf Source: u_confreg/led_data_reg[11]_lopt_replica/C (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: leds[11] (output port) Path Group: (none) Path Type: Min at Fast Process Corner Data Path Delay: 3.409ns (logic 1.408ns (41.311%) route 2.001ns (58.689%)) Logic Levels: 1 (OBUF=1) Clock Uncertainty: 0.190ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.050ns Discrete Jitter (DJ): 0.122ns Phase Error (PE): 0.124ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9603, routed) 0.720 -0.542 u_confreg/sys_clk SLICE_X4Y89 FDRE r u_confreg/led_data_reg[11]_lopt_replica/C ------------------------------------------------------------------- ------------------- SLICE_X4Y89 FDRE (Prop_fdre_C_Q) 0.141 -0.401 r u_confreg/led_data_reg[11]_lopt_replica/Q net (fo=1, routed) 2.001 1.599 lopt_2 A18 OBUF (Prop_obuf_I_O) 1.267 2.867 r leds_OBUF[11]_inst/O net (fo=0) 0.000 2.867 leds[11] A18 r leds[11] (OUT) ------------------------------------------------------------------- ------------------- Slack: inf Source: u_axi_uart_controller/uart0/regs/mcr_reg[4]/C (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: UART_TX (output port) Path Group: (none) Path Type: Min at Fast Process Corner Data Path Delay: 3.454ns (logic 1.416ns (40.996%) route 2.038ns (59.004%)) Logic Levels: 2 (LUT4=1 OBUFT=1) Clock Uncertainty: 0.190ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.050ns Discrete Jitter (DJ): 0.122ns Phase Error (PE): 0.124ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9603, routed) 0.687 -0.575 u_axi_uart_controller/uart0/regs/sys_clk SLICE_X28Y58 FDRE r u_axi_uart_controller/uart0/regs/mcr_reg[4]/C ------------------------------------------------------------------- ------------------- SLICE_X28Y58 FDRE (Prop_fdre_C_Q) 0.141 -0.434 r u_axi_uart_controller/uart0/regs/mcr_reg[4]/Q net (fo=8, routed) 0.158 -0.276 u_axi_uart_controller/uart0/regs/transmitter/counter_b_reg[7]_0[0] SLICE_X28Y58 LUT4 (Prop_lut4_I3_O) 0.045 -0.231 r u_axi_uart_controller/uart0/regs/transmitter/UART_TX_IOBUF_inst_i_1/O net (fo=1, routed) 1.880 1.649 UART_TX_IOBUF_inst/I H18 OBUFT (Prop_obuft_I_O) 1.230 2.879 r UART_TX_IOBUF_inst/OBUFT/O net (fo=1, unset) 0.000 2.879 UART_TX H18 r UART_TX (INOUT) ------------------------------------------------------------------- ------------------- Slack: inf Source: u_confreg/led_data_reg[1]_lopt_replica/C (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: leds[1] (output port) Path Group: (none) Path Type: Min at Fast Process Corner Data Path Delay: 3.429ns (logic 1.383ns (40.331%) route 2.046ns (59.669%)) Logic Levels: 1 (OBUF=1) Clock Uncertainty: 0.190ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.050ns Discrete Jitter (DJ): 0.122ns Phase Error (PE): 0.124ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9603, routed) 0.723 -0.539 u_confreg/sys_clk SLICE_X0Y88 FDRE r u_confreg/led_data_reg[1]_lopt_replica/C ------------------------------------------------------------------- ------------------- SLICE_X0Y88 FDRE (Prop_fdre_C_Q) 0.141 -0.398 r u_confreg/led_data_reg[1]_lopt_replica/Q net (fo=1, routed) 2.046 1.648 lopt_7 E21 OBUF (Prop_obuf_I_O) 1.242 2.889 r leds_OBUF[1]_inst/O net (fo=0) 0.000 2.889 leds[1] E21 r leds[1] (OUT) ------------------------------------------------------------------- ------------------- Slack: inf Source: u_confreg/led_data_reg[13]_lopt_replica/C (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: leds[13] (output port) Path Group: (none) Path Type: Min at Fast Process Corner Data Path Delay: 3.463ns (logic 1.412ns (40.774%) route 2.051ns (59.226%)) Logic Levels: 1 (OBUF=1) Clock Uncertainty: 0.190ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.050ns Discrete Jitter (DJ): 0.122ns Phase Error (PE): 0.124ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9603, routed) 0.720 -0.542 u_confreg/sys_clk SLICE_X4Y89 FDRE r u_confreg/led_data_reg[13]_lopt_replica/C ------------------------------------------------------------------- ------------------- SLICE_X4Y89 FDRE (Prop_fdre_C_Q) 0.141 -0.401 r u_confreg/led_data_reg[13]_lopt_replica/Q net (fo=1, routed) 2.051 1.650 lopt_4 A22 OBUF (Prop_obuf_I_O) 1.271 2.921 r leds_OBUF[13]_inst/O net (fo=0) 0.000 2.921 leds[13] A22 r leds[13] (OUT) ------------------------------------------------------------------- ------------------- Slack: inf Source: u_axi_dvi/hdata_reg[10]/C (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: video_de (output port) Path Group: (none) Path Type: Min at Fast Process Corner Data Path Delay: 3.509ns (logic 1.447ns (41.243%) route 2.062ns (58.757%)) Logic Levels: 2 (LUT6=1 OBUF=1) Clock Uncertainty: 0.190ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.050ns Discrete Jitter (DJ): 0.122ns Phase Error (PE): 0.124ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9603, routed) 0.712 -0.550 u_axi_dvi/sys_clk SLICE_X5Y78 FDRE r u_axi_dvi/hdata_reg[10]/C ------------------------------------------------------------------- ------------------- SLICE_X5Y78 FDRE (Prop_fdre_C_Q) 0.141 -0.409 f u_axi_dvi/hdata_reg[10]/Q net (fo=12, routed) 0.265 -0.145 u_axi_dvi/hdata_reg_n_0_[10] SLICE_X8Y79 LUT6 (Prop_lut6_I4_O) 0.045 -0.100 r u_axi_dvi/video_de_OBUF_inst_i_1/O net (fo=1, routed) 1.797 1.698 video_de_OBUF G24 OBUF (Prop_obuf_I_O) 1.261 2.959 r video_de_OBUF_inst/O net (fo=0) 0.000 2.959 video_de G24 r video_de (OUT) ------------------------------------------------------------------- ------------------- Slack: inf Source: u_confreg/led_data_reg[10]_lopt_replica/C (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: leds[10] (output port) Path Group: (none) Path Type: Min at Fast Process Corner Data Path Delay: 3.584ns (logic 1.389ns (38.751%) route 2.195ns (61.249%)) Logic Levels: 1 (OBUF=1) Clock Uncertainty: 0.190ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.050ns Discrete Jitter (DJ): 0.122ns Phase Error (PE): 0.124ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9603, routed) 0.721 -0.541 u_confreg/sys_clk SLICE_X3Y85 FDRE r u_confreg/led_data_reg[10]_lopt_replica/C ------------------------------------------------------------------- ------------------- SLICE_X3Y85 FDRE (Prop_fdre_C_Q) 0.141 -0.400 r u_confreg/led_data_reg[10]_lopt_replica/Q net (fo=1, routed) 2.195 1.795 lopt_1 D21 OBUF (Prop_obuf_I_O) 1.248 3.042 r leds_OBUF[10]_inst/O net (fo=0) 0.000 3.042 leds[10] D21 r leds[10] (OUT) ------------------------------------------------------------------- ------------------- Slack: inf Source: u_confreg/u_digitaltube_controller/dpy0_reg_reg[5]/C (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: dpy0[5] (output port) Path Group: (none) Path Type: Min at Fast Process Corner Data Path Delay: 3.605ns (logic 1.388ns (38.488%) route 2.218ns (61.512%)) Logic Levels: 1 (OBUF=1) Clock Uncertainty: 0.190ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.050ns Discrete Jitter (DJ): 0.122ns Phase Error (PE): 0.124ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9603, routed) 0.723 -0.539 u_confreg/u_digitaltube_controller/sys_clk SLICE_X0Y61 FDCE r u_confreg/u_digitaltube_controller/dpy0_reg_reg[5]/C ------------------------------------------------------------------- ------------------- SLICE_X0Y61 FDCE (Prop_fdce_C_Q) 0.141 -0.398 r u_confreg/u_digitaltube_controller/dpy0_reg_reg[5]/Q net (fo=1, routed) 2.218 1.819 dpy0_OBUF[5] C19 OBUF (Prop_obuf_I_O) 1.247 3.066 r dpy0_OBUF[5]_inst/O net (fo=0) 0.000 3.066 dpy0[5] C19 r dpy0[5] (OUT) ------------------------------------------------------------------- ------------------- Slack: inf Source: u_confreg/u_digitaltube_controller/dpy1_reg_reg[4]/C (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: dpy1[4] (output port) Path Group: (none) Path Type: Min at Fast Process Corner Data Path Delay: 3.630ns (logic 1.383ns (38.106%) route 2.247ns (61.894%)) Logic Levels: 1 (OBUF=1) Clock Uncertainty: 0.190ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.050ns Discrete Jitter (DJ): 0.122ns Phase Error (PE): 0.124ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9603, routed) 0.724 -0.538 u_confreg/u_digitaltube_controller/sys_clk SLICE_X1Y59 FDCE r u_confreg/u_digitaltube_controller/dpy1_reg_reg[4]/C ------------------------------------------------------------------- ------------------- SLICE_X1Y59 FDCE (Prop_fdce_C_Q) 0.141 -0.397 r u_confreg/u_digitaltube_controller/dpy1_reg_reg[4]/Q net (fo=1, routed) 2.247 1.850 dpy1_OBUF[4] E16 OBUF (Prop_obuf_I_O) 1.242 3.092 r dpy1_OBUF[4]_inst/O net (fo=0) 0.000 3.092 dpy1[4] E16 r dpy1[4] (OUT) ------------------------------------------------------------------- ------------------- Slack: inf Source: u_confreg/led_data_reg[15]_lopt_replica/C (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: leds[15] (output port) Path Group: (none) Path Type: Min at Fast Process Corner Data Path Delay: 3.697ns (logic 1.427ns (38.616%) route 2.269ns (61.384%)) Logic Levels: 1 (OBUF=1) Clock Uncertainty: 0.190ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.050ns Discrete Jitter (DJ): 0.122ns Phase Error (PE): 0.124ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9603, routed) 0.720 -0.542 u_confreg/sys_clk SLICE_X2Y83 FDRE r u_confreg/led_data_reg[15]_lopt_replica/C ------------------------------------------------------------------- ------------------- SLICE_X2Y83 FDRE (Prop_fdre_C_Q) 0.164 -0.378 r u_confreg/led_data_reg[15]_lopt_replica/Q net (fo=1, routed) 2.269 1.891 lopt_6 B20 OBUF (Prop_obuf_I_O) 1.263 3.154 r leds_OBUF[15]_inst/O net (fo=0) 0.000 3.154 leds[15] B20 r leds[15] (OUT) ------------------------------------------------------------------- ------------------- Slack: inf Source: u_confreg/u_digitaltube_controller/dpy0_reg_reg[4]/C (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: dpy0[4] (output port) Path Group: (none) Path Type: Min at Fast Process Corner Data Path Delay: 3.719ns (logic 1.381ns (37.138%) route 2.338ns (62.862%)) Logic Levels: 1 (OBUF=1) Clock Uncertainty: 0.190ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.050ns Discrete Jitter (DJ): 0.122ns Phase Error (PE): 0.124ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9603, routed) 0.723 -0.539 u_confreg/u_digitaltube_controller/sys_clk SLICE_X1Y61 FDCE r u_confreg/u_digitaltube_controller/dpy0_reg_reg[4]/C ------------------------------------------------------------------- ------------------- SLICE_X1Y61 FDCE (Prop_fdce_C_Q) 0.141 -0.398 r u_confreg/u_digitaltube_controller/dpy0_reg_reg[4]/Q net (fo=1, routed) 2.338 1.939 dpy0_OBUF[4] E18 OBUF (Prop_obuf_I_O) 1.240 3.179 r dpy0_OBUF[4]_inst/O net (fo=0) 0.000 3.179 dpy0[4] E18 r dpy0[4] (OUT) ------------------------------------------------------------------- ------------------- Slack: inf Source: u_confreg/u_digitaltube_controller/dpy0_reg_reg[3]/C (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: dpy0[3] (output port) Path Group: (none) Path Type: Min at Fast Process Corner Data Path Delay: 3.723ns (logic 1.415ns (37.994%) route 2.309ns (62.006%)) Logic Levels: 1 (OBUF=1) Clock Uncertainty: 0.190ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.050ns Discrete Jitter (DJ): 0.122ns Phase Error (PE): 0.124ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9603, routed) 0.723 -0.539 u_confreg/u_digitaltube_controller/sys_clk SLICE_X1Y61 FDCE r u_confreg/u_digitaltube_controller/dpy0_reg_reg[3]/C ------------------------------------------------------------------- ------------------- SLICE_X1Y61 FDCE (Prop_fdce_C_Q) 0.141 -0.398 r u_confreg/u_digitaltube_controller/dpy0_reg_reg[3]/Q net (fo=1, routed) 2.309 1.910 dpy0_OBUF[3] A19 OBUF (Prop_obuf_I_O) 1.274 3.184 r dpy0_OBUF[3]_inst/O net (fo=0) 0.000 3.184 dpy0[3] A19 r dpy0[3] (OUT) ------------------------------------------------------------------- ------------------- Slack: inf Source: u_confreg/led_data_reg[4]_lopt_replica/C (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: leds[4] (output port) Path Group: (none) Path Type: Min at Fast Process Corner Data Path Delay: 3.751ns (logic 1.404ns (37.422%) route 2.347ns (62.578%)) Logic Levels: 1 (OBUF=1) Clock Uncertainty: 0.190ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.050ns Discrete Jitter (DJ): 0.122ns Phase Error (PE): 0.124ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9603, routed) 0.719 -0.543 u_confreg/sys_clk SLICE_X0Y82 FDRE r u_confreg/led_data_reg[4]_lopt_replica/C ------------------------------------------------------------------- ------------------- SLICE_X0Y82 FDRE (Prop_fdre_C_Q) 0.141 -0.402 r u_confreg/led_data_reg[4]_lopt_replica/Q net (fo=1, routed) 2.347 1.945 lopt_10 C22 OBUF (Prop_obuf_I_O) 1.263 3.208 r leds_OBUF[4]_inst/O net (fo=0) 0.000 3.208 leds[4] C22 r leds[4] (OUT) ------------------------------------------------------------------- ------------------- Slack: inf Source: u_confreg/u_digitaltube_controller/dpy1_reg_reg[5]/C (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: dpy1[5] (output port) Path Group: (none) Path Type: Min at Fast Process Corner Data Path Delay: 3.824ns (logic 1.376ns (35.980%) route 2.448ns (64.020%)) Logic Levels: 1 (OBUF=1) Clock Uncertainty: 0.190ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.050ns Discrete Jitter (DJ): 0.122ns Phase Error (PE): 0.124ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9603, routed) 0.723 -0.539 u_confreg/u_digitaltube_controller/sys_clk SLICE_X1Y60 FDCE r u_confreg/u_digitaltube_controller/dpy1_reg_reg[5]/C ------------------------------------------------------------------- ------------------- SLICE_X1Y60 FDCE (Prop_fdce_C_Q) 0.141 -0.398 r u_confreg/u_digitaltube_controller/dpy1_reg_reg[5]/Q net (fo=1, routed) 2.448 2.050 dpy1_OBUF[5] G16 OBUF (Prop_obuf_I_O) 1.235 3.285 r dpy1_OBUF[5]_inst/O net (fo=0) 0.000 3.285 dpy1[5] G16 r dpy1[5] (OUT) ------------------------------------------------------------------- ------------------- Slack: inf Source: u_confreg/u_digitaltube_controller/dpy1_reg_reg[3]/C (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: dpy1[3] (output port) Path Group: (none) Path Type: Min at Fast Process Corner Data Path Delay: 3.961ns (logic 1.356ns (34.243%) route 2.605ns (65.757%)) Logic Levels: 1 (OBUF=1) Clock Uncertainty: 0.190ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.050ns Discrete Jitter (DJ): 0.122ns Phase Error (PE): 0.124ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9603, routed) 0.723 -0.539 u_confreg/u_digitaltube_controller/sys_clk SLICE_X1Y60 FDCE r u_confreg/u_digitaltube_controller/dpy1_reg_reg[3]/C ------------------------------------------------------------------- ------------------- SLICE_X1Y60 FDCE (Prop_fdce_C_Q) 0.141 -0.398 r u_confreg/u_digitaltube_controller/dpy1_reg_reg[3]/Q net (fo=1, routed) 2.605 2.206 dpy1_OBUF[3] F17 OBUF (Prop_obuf_I_O) 1.215 3.422 r dpy1_OBUF[3]_inst/O net (fo=0) 0.000 3.422 dpy1[3] F17 r dpy1[3] (OUT) ------------------------------------------------------------------- ------------------- Slack: inf Source: u_axi_dvi/hdata_reg[0]/C (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: video_red[1] (output port) Path Group: (none) Path Type: Min at Fast Process Corner Data Path Delay: 4.040ns (logic 1.683ns (41.654%) route 2.357ns (58.346%)) Logic Levels: 5 (CARRY4=2 LUT4=1 LUT5=1 OBUF=1) Clock Uncertainty: 0.190ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.050ns Discrete Jitter (DJ): 0.122ns Phase Error (PE): 0.124ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9603, routed) 0.685 -0.577 u_axi_dvi/sys_clk SLICE_X10Y78 FDRE r u_axi_dvi/hdata_reg[0]/C ------------------------------------------------------------------- ------------------- SLICE_X10Y78 FDRE (Prop_fdre_C_Q) 0.164 -0.413 r u_axi_dvi/hdata_reg[0]/Q net (fo=11, routed) 0.294 -0.119 u_axi_dvi/hdata_reg_n_0_[0] SLICE_X8Y76 LUT4 (Prop_lut4_I2_O) 0.046 -0.073 r u_axi_dvi/video_red_OBUF[2]_inst_i_44/O net (fo=1, routed) 0.000 -0.073 u_axi_dvi/video_red_OBUF[2]_inst_i_44_n_0 SLICE_X8Y76 CARRY4 (Prop_carry4_DI[0]_CO[3]) 0.127 0.054 r u_axi_dvi/video_red_OBUF[2]_inst_i_12/CO[3] net (fo=1, routed) 0.000 0.054 u_axi_dvi/video_red_OBUF[2]_inst_i_12_n_0 SLICE_X8Y77 CARRY4 (Prop_carry4_CI_CO[3]) 0.040 0.094 r u_axi_dvi/video_red_OBUF[2]_inst_i_3/CO[3] net (fo=1, routed) 0.222 0.316 u_axi_dvi/hdata1_in_range08_in SLICE_X8Y75 LUT5 (Prop_lut5_I1_O) 0.045 0.361 r u_axi_dvi/video_red_OBUF[2]_inst_i_1/O net (fo=3, routed) 1.841 2.202 video_red_OBUF[0] F24 OBUF (Prop_obuf_I_O) 1.261 3.463 r video_red_OBUF[1]_inst/O net (fo=0) 0.000 3.463 video_red[1] F24 r video_red[1] (OUT) ------------------------------------------------------------------- ------------------- Slack: inf Source: u_axi_dvi/hdata_reg[0]/C (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: video_red[2] (output port) Path Group: (none) Path Type: Min at Fast Process Corner Data Path Delay: 4.053ns (logic 1.709ns (42.167%) route 2.344ns (57.833%)) Logic Levels: 5 (CARRY4=2 LUT4=1 LUT5=1 OBUF=1) Clock Uncertainty: 0.190ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.050ns Discrete Jitter (DJ): 0.122ns Phase Error (PE): 0.124ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9603, routed) 0.685 -0.577 u_axi_dvi/sys_clk SLICE_X10Y78 FDRE r u_axi_dvi/hdata_reg[0]/C ------------------------------------------------------------------- ------------------- SLICE_X10Y78 FDRE (Prop_fdre_C_Q) 0.164 -0.413 r u_axi_dvi/hdata_reg[0]/Q net (fo=11, routed) 0.294 -0.119 u_axi_dvi/hdata_reg_n_0_[0] SLICE_X8Y76 LUT4 (Prop_lut4_I2_O) 0.046 -0.073 r u_axi_dvi/video_red_OBUF[2]_inst_i_44/O net (fo=1, routed) 0.000 -0.073 u_axi_dvi/video_red_OBUF[2]_inst_i_44_n_0 SLICE_X8Y76 CARRY4 (Prop_carry4_DI[0]_CO[3]) 0.127 0.054 r u_axi_dvi/video_red_OBUF[2]_inst_i_12/CO[3] net (fo=1, routed) 0.000 0.054 u_axi_dvi/video_red_OBUF[2]_inst_i_12_n_0 SLICE_X8Y77 CARRY4 (Prop_carry4_CI_CO[3]) 0.040 0.094 r u_axi_dvi/video_red_OBUF[2]_inst_i_3/CO[3] net (fo=1, routed) 0.222 0.316 u_axi_dvi/hdata1_in_range08_in SLICE_X8Y75 LUT5 (Prop_lut5_I1_O) 0.045 0.361 r u_axi_dvi/video_red_OBUF[2]_inst_i_1/O net (fo=3, routed) 1.828 2.188 video_red_OBUF[0] E26 OBUF (Prop_obuf_I_O) 1.287 3.475 r video_red_OBUF[2]_inst/O net (fo=0) 0.000 3.475 video_red[2] E26 r video_red[2] (OUT) ------------------------------------------------------------------- ------------------- Slack: inf Source: u_axi_dvi/hdata_reg[0]/C (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: video_red[0] (output port) Path Group: (none) Path Type: Min at Fast Process Corner Data Path Delay: 4.072ns (logic 1.655ns (40.655%) route 2.416ns (59.345%)) Logic Levels: 5 (CARRY4=2 LUT4=1 LUT5=1 OBUF=1) Clock Uncertainty: 0.190ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.050ns Discrete Jitter (DJ): 0.122ns Phase Error (PE): 0.124ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9603, routed) 0.685 -0.577 u_axi_dvi/sys_clk SLICE_X10Y78 FDRE r u_axi_dvi/hdata_reg[0]/C ------------------------------------------------------------------- ------------------- SLICE_X10Y78 FDRE (Prop_fdre_C_Q) 0.164 -0.413 r u_axi_dvi/hdata_reg[0]/Q net (fo=11, routed) 0.294 -0.119 u_axi_dvi/hdata_reg_n_0_[0] SLICE_X8Y76 LUT4 (Prop_lut4_I2_O) 0.046 -0.073 r u_axi_dvi/video_red_OBUF[2]_inst_i_44/O net (fo=1, routed) 0.000 -0.073 u_axi_dvi/video_red_OBUF[2]_inst_i_44_n_0 SLICE_X8Y76 CARRY4 (Prop_carry4_DI[0]_CO[3]) 0.127 0.054 r u_axi_dvi/video_red_OBUF[2]_inst_i_12/CO[3] net (fo=1, routed) 0.000 0.054 u_axi_dvi/video_red_OBUF[2]_inst_i_12_n_0 SLICE_X8Y77 CARRY4 (Prop_carry4_CI_CO[3]) 0.040 0.094 r u_axi_dvi/video_red_OBUF[2]_inst_i_3/CO[3] net (fo=1, routed) 0.222 0.316 u_axi_dvi/hdata1_in_range08_in SLICE_X8Y75 LUT5 (Prop_lut5_I1_O) 0.045 0.361 r u_axi_dvi/video_red_OBUF[2]_inst_i_1/O net (fo=3, routed) 1.900 2.261 video_red_OBUF[0] K23 OBUF (Prop_obuf_I_O) 1.233 3.495 r video_red_OBUF[0]_inst/O net (fo=0) 0.000 3.495 video_red[0] K23 r video_red[0] (OUT) ------------------------------------------------------------------- ------------------- Slack: inf Source: u_confreg/u_digitaltube_controller/dpy0_reg_reg[7]/C (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: dpy0[7] (output port) Path Group: (none) Path Type: Min at Fast Process Corner Data Path Delay: 4.048ns (logic 1.386ns (34.244%) route 2.662ns (65.756%)) Logic Levels: 1 (OBUF=1) Clock Uncertainty: 0.190ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.050ns Discrete Jitter (DJ): 0.122ns Phase Error (PE): 0.124ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9603, routed) 0.723 -0.539 u_confreg/u_digitaltube_controller/sys_clk SLICE_X0Y60 FDCE r u_confreg/u_digitaltube_controller/dpy0_reg_reg[7]/C ------------------------------------------------------------------- ------------------- SLICE_X0Y60 FDCE (Prop_fdce_C_Q) 0.141 -0.398 r u_confreg/u_digitaltube_controller/dpy0_reg_reg[7]/Q net (fo=1, routed) 2.662 2.264 dpy0_OBUF[7] C17 OBUF (Prop_obuf_I_O) 1.245 3.509 r dpy0_OBUF[7]_inst/O net (fo=0) 0.000 3.509 dpy0[7] C17 r dpy0[7] (OUT) ------------------------------------------------------------------- ------------------- Slack: inf Source: u_confreg/u_digitaltube_controller/dpy0_reg_reg[1]/C (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: dpy0[1] (output port) Path Group: (none) Path Type: Min at Fast Process Corner Data Path Delay: 4.342ns (logic 1.387ns (31.947%) route 2.955ns (68.053%)) Logic Levels: 1 (OBUF=1) Clock Uncertainty: 0.190ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.050ns Discrete Jitter (DJ): 0.122ns Phase Error (PE): 0.124ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9603, routed) 0.723 -0.539 u_confreg/u_digitaltube_controller/sys_clk SLICE_X0Y61 FDCE r u_confreg/u_digitaltube_controller/dpy0_reg_reg[1]/C ------------------------------------------------------------------- ------------------- SLICE_X0Y61 FDCE (Prop_fdce_C_Q) 0.141 -0.398 r u_confreg/u_digitaltube_controller/dpy0_reg_reg[1]/Q net (fo=1, routed) 2.955 2.556 dpy0_OBUF[1] D19 OBUF (Prop_obuf_I_O) 1.246 3.802 r dpy0_OBUF[1]_inst/O net (fo=0) 0.000 3.802 dpy0[1] D19 r dpy0[1] (OUT) ------------------------------------------------------------------- ------------------- Slack: inf Source: u_confreg/u_digitaltube_controller/dpy1_reg_reg[6]/C (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: dpy1[6] (output port) Path Group: (none) Path Type: Min at Fast Process Corner Data Path Delay: 4.415ns (logic 1.379ns (31.228%) route 3.036ns (68.772%)) Logic Levels: 1 (OBUF=1) Clock Uncertainty: 0.190ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.050ns Discrete Jitter (DJ): 0.122ns Phase Error (PE): 0.124ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9603, routed) 0.724 -0.538 u_confreg/u_digitaltube_controller/sys_clk SLICE_X1Y59 FDCE r u_confreg/u_digitaltube_controller/dpy1_reg_reg[6]/C ------------------------------------------------------------------- ------------------- SLICE_X1Y59 FDCE (Prop_fdce_C_Q) 0.141 -0.397 r u_confreg/u_digitaltube_controller/dpy1_reg_reg[6]/Q net (fo=1, routed) 3.036 2.639 dpy1_OBUF[6] F15 OBUF (Prop_obuf_I_O) 1.238 3.877 r dpy1_OBUF[6]_inst/O net (fo=0) 0.000 3.877 dpy1[6] F15 r dpy1[6] (OUT) ------------------------------------------------------------------- ------------------- Slack: inf Source: u_confreg/led_data_reg[8]_lopt_replica/C (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: leds[8] (output port) Path Group: (none) Path Type: Min at Fast Process Corner Data Path Delay: 4.539ns (logic 1.463ns (32.225%) route 3.076ns (67.775%)) Logic Levels: 1 (OBUF=1) Clock Uncertainty: 0.190ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.050ns Discrete Jitter (DJ): 0.122ns Phase Error (PE): 0.124ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9603, routed) 0.720 -0.542 u_confreg/sys_clk SLICE_X2Y83 FDRE r u_confreg/led_data_reg[8]_lopt_replica/C ------------------------------------------------------------------- ------------------- SLICE_X2Y83 FDRE (Prop_fdre_C_Q) 0.148 -0.394 r u_confreg/led_data_reg[8]_lopt_replica/Q net (fo=1, routed) 3.076 2.682 lopt_14 C23 OBUF (Prop_obuf_I_O) 1.315 3.996 r leds_OBUF[8]_inst/O net (fo=0) 0.000 3.996 leds[8] C23 r leds[8] (OUT) ------------------------------------------------------------------- ------------------- Slack: inf Source: u_confreg/u_digitaltube_controller/dpy0_reg_reg[6]/C (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: dpy0[6] (output port) Path Group: (none) Path Type: Min at Fast Process Corner Data Path Delay: 5.224ns (logic 1.398ns (26.760%) route 3.826ns (73.240%)) Logic Levels: 1 (OBUF=1) Clock Uncertainty: 0.190ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.050ns Discrete Jitter (DJ): 0.122ns Phase Error (PE): 0.124ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9603, routed) 0.723 -0.539 u_confreg/u_digitaltube_controller/sys_clk SLICE_X0Y61 FDCE r u_confreg/u_digitaltube_controller/dpy0_reg_reg[6]/C ------------------------------------------------------------------- ------------------- SLICE_X0Y61 FDCE (Prop_fdce_C_Q) 0.141 -0.398 r u_confreg/u_digitaltube_controller/dpy0_reg_reg[6]/Q net (fo=1, routed) 3.826 3.428 dpy0_OBUF[6] B17 OBUF (Prop_obuf_I_O) 1.257 4.685 r dpy0_OBUF[6]_inst/O net (fo=0) 0.000 4.685 dpy0[6] B17 r dpy0[6] (OUT) ------------------------------------------------------------------- ------------------- -------------------------------------------------------------------------------------- Path Group: (none) From Clock: To Clock: sys_clk Max Delay 0 Endpoints Min Delay 163 Endpoints -------------------------------------------------------------------------------------- Min Delay Paths -------------------------------------------------------------------------------------- Slack: inf Source: u_matmul_axi_slave/mult_inst[0].u_mult/prod0__17/ACOUT[0] (internal pin) Destination: u_matmul_axi_slave/mult_inst[0].u_mult/prod_reg__0/ACIN[0] (rising edge-triggered cell DSP48E1 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: (none) Path Type: Hold (Min at Slow Process Corner) Data Path Delay: 0.002ns (logic 0.000ns (0.000%) route 0.002ns (100.000%)) Logic Levels: 0 Clock Uncertainty: 0.190ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.050ns Discrete Jitter (DJ): 0.122ns Phase Error (PE): 0.124ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- DSP48_X1Y32 DSP48E1 0.000 0.000 r u_matmul_axi_slave/mult_inst[0].u_mult/prod0__17/ACOUT[0] net (fo=1, routed) 0.002 0.002 u_matmul_axi_slave/mult_inst[0].u_mult/prod0__17_n_53 DSP48_X1Y33 DSP48E1 r u_matmul_axi_slave/mult_inst[0].u_mult/prod_reg__0/ACIN[0] ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9603, routed) 2.028 -2.314 u_matmul_axi_slave/mult_inst[0].u_mult/sys_clk DSP48_X1Y33 DSP48E1 r u_matmul_axi_slave/mult_inst[0].u_mult/prod_reg__0/CLK Slack: inf Source: u_matmul_axi_slave/mult_inst[0].u_mult/prod0__17/ACOUT[10] (internal pin) Destination: u_matmul_axi_slave/mult_inst[0].u_mult/prod_reg__0/ACIN[10] (rising edge-triggered cell DSP48E1 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: (none) Path Type: Hold (Min at Slow Process Corner) Data Path Delay: 0.002ns (logic 0.000ns (0.000%) route 0.002ns (100.000%)) Logic Levels: 0 Clock Uncertainty: 0.190ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.050ns Discrete Jitter (DJ): 0.122ns Phase Error (PE): 0.124ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- DSP48_X1Y32 DSP48E1 0.000 0.000 r u_matmul_axi_slave/mult_inst[0].u_mult/prod0__17/ACOUT[10] net (fo=1, routed) 0.002 0.002 u_matmul_axi_slave/mult_inst[0].u_mult/prod0__17_n_43 DSP48_X1Y33 DSP48E1 r u_matmul_axi_slave/mult_inst[0].u_mult/prod_reg__0/ACIN[10] ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9603, routed) 2.028 -2.314 u_matmul_axi_slave/mult_inst[0].u_mult/sys_clk DSP48_X1Y33 DSP48E1 r u_matmul_axi_slave/mult_inst[0].u_mult/prod_reg__0/CLK Slack: inf Source: u_matmul_axi_slave/mult_inst[0].u_mult/prod0__17/ACOUT[11] (internal pin) Destination: u_matmul_axi_slave/mult_inst[0].u_mult/prod_reg__0/ACIN[11] (rising edge-triggered cell DSP48E1 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: (none) Path Type: Hold (Min at Slow Process Corner) Data Path Delay: 0.002ns (logic 0.000ns (0.000%) route 0.002ns (100.000%)) Logic Levels: 0 Clock Uncertainty: 0.190ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.050ns Discrete Jitter (DJ): 0.122ns Phase Error (PE): 0.124ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- DSP48_X1Y32 DSP48E1 0.000 0.000 r u_matmul_axi_slave/mult_inst[0].u_mult/prod0__17/ACOUT[11] net (fo=1, routed) 0.002 0.002 u_matmul_axi_slave/mult_inst[0].u_mult/prod0__17_n_42 DSP48_X1Y33 DSP48E1 r u_matmul_axi_slave/mult_inst[0].u_mult/prod_reg__0/ACIN[11] ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9603, routed) 2.028 -2.314 u_matmul_axi_slave/mult_inst[0].u_mult/sys_clk DSP48_X1Y33 DSP48E1 r u_matmul_axi_slave/mult_inst[0].u_mult/prod_reg__0/CLK Slack: inf Source: u_matmul_axi_slave/mult_inst[0].u_mult/prod0__17/ACOUT[12] (internal pin) Destination: u_matmul_axi_slave/mult_inst[0].u_mult/prod_reg__0/ACIN[12] (rising edge-triggered cell DSP48E1 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: (none) Path Type: Hold (Min at Slow Process Corner) Data Path Delay: 0.002ns (logic 0.000ns (0.000%) route 0.002ns (100.000%)) Logic Levels: 0 Clock Uncertainty: 0.190ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.050ns Discrete Jitter (DJ): 0.122ns Phase Error (PE): 0.124ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- DSP48_X1Y32 DSP48E1 0.000 0.000 r u_matmul_axi_slave/mult_inst[0].u_mult/prod0__17/ACOUT[12] net (fo=1, routed) 0.002 0.002 u_matmul_axi_slave/mult_inst[0].u_mult/prod0__17_n_41 DSP48_X1Y33 DSP48E1 r u_matmul_axi_slave/mult_inst[0].u_mult/prod_reg__0/ACIN[12] ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9603, routed) 2.028 -2.314 u_matmul_axi_slave/mult_inst[0].u_mult/sys_clk DSP48_X1Y33 DSP48E1 r u_matmul_axi_slave/mult_inst[0].u_mult/prod_reg__0/CLK Slack: inf Source: u_matmul_axi_slave/mult_inst[0].u_mult/prod0__17/ACOUT[13] (internal pin) Destination: u_matmul_axi_slave/mult_inst[0].u_mult/prod_reg__0/ACIN[13] (rising edge-triggered cell DSP48E1 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: (none) Path Type: Hold (Min at Slow Process Corner) Data Path Delay: 0.002ns (logic 0.000ns (0.000%) route 0.002ns (100.000%)) Logic Levels: 0 Clock Uncertainty: 0.190ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.050ns Discrete Jitter (DJ): 0.122ns Phase Error (PE): 0.124ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- DSP48_X1Y32 DSP48E1 0.000 0.000 r u_matmul_axi_slave/mult_inst[0].u_mult/prod0__17/ACOUT[13] net (fo=1, routed) 0.002 0.002 u_matmul_axi_slave/mult_inst[0].u_mult/prod0__17_n_40 DSP48_X1Y33 DSP48E1 r u_matmul_axi_slave/mult_inst[0].u_mult/prod_reg__0/ACIN[13] ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9603, routed) 2.028 -2.314 u_matmul_axi_slave/mult_inst[0].u_mult/sys_clk DSP48_X1Y33 DSP48E1 r u_matmul_axi_slave/mult_inst[0].u_mult/prod_reg__0/CLK Slack: inf Source: u_matmul_axi_slave/mult_inst[0].u_mult/prod0__17/ACOUT[14] (internal pin) Destination: u_matmul_axi_slave/mult_inst[0].u_mult/prod_reg__0/ACIN[14] (rising edge-triggered cell DSP48E1 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: (none) Path Type: Hold (Min at Slow Process Corner) Data Path Delay: 0.002ns (logic 0.000ns (0.000%) route 0.002ns (100.000%)) Logic Levels: 0 Clock Uncertainty: 0.190ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.050ns Discrete Jitter (DJ): 0.122ns Phase Error (PE): 0.124ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- DSP48_X1Y32 DSP48E1 0.000 0.000 r u_matmul_axi_slave/mult_inst[0].u_mult/prod0__17/ACOUT[14] net (fo=1, routed) 0.002 0.002 u_matmul_axi_slave/mult_inst[0].u_mult/prod0__17_n_39 DSP48_X1Y33 DSP48E1 r u_matmul_axi_slave/mult_inst[0].u_mult/prod_reg__0/ACIN[14] ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9603, routed) 2.028 -2.314 u_matmul_axi_slave/mult_inst[0].u_mult/sys_clk DSP48_X1Y33 DSP48E1 r u_matmul_axi_slave/mult_inst[0].u_mult/prod_reg__0/CLK Slack: inf Source: u_matmul_axi_slave/mult_inst[0].u_mult/prod0__17/ACOUT[15] (internal pin) Destination: u_matmul_axi_slave/mult_inst[0].u_mult/prod_reg__0/ACIN[15] (rising edge-triggered cell DSP48E1 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: (none) Path Type: Hold (Min at Slow Process Corner) Data Path Delay: 0.002ns (logic 0.000ns (0.000%) route 0.002ns (100.000%)) Logic Levels: 0 Clock Uncertainty: 0.190ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.050ns Discrete Jitter (DJ): 0.122ns Phase Error (PE): 0.124ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- DSP48_X1Y32 DSP48E1 0.000 0.000 r u_matmul_axi_slave/mult_inst[0].u_mult/prod0__17/ACOUT[15] net (fo=1, routed) 0.002 0.002 u_matmul_axi_slave/mult_inst[0].u_mult/prod0__17_n_38 DSP48_X1Y33 DSP48E1 r u_matmul_axi_slave/mult_inst[0].u_mult/prod_reg__0/ACIN[15] ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9603, routed) 2.028 -2.314 u_matmul_axi_slave/mult_inst[0].u_mult/sys_clk DSP48_X1Y33 DSP48E1 r u_matmul_axi_slave/mult_inst[0].u_mult/prod_reg__0/CLK Slack: inf Source: u_matmul_axi_slave/mult_inst[0].u_mult/prod0__17/ACOUT[16] (internal pin) Destination: u_matmul_axi_slave/mult_inst[0].u_mult/prod_reg__0/ACIN[16] (rising edge-triggered cell DSP48E1 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: (none) Path Type: Hold (Min at Slow Process Corner) Data Path Delay: 0.002ns (logic 0.000ns (0.000%) route 0.002ns (100.000%)) Logic Levels: 0 Clock Uncertainty: 0.190ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.050ns Discrete Jitter (DJ): 0.122ns Phase Error (PE): 0.124ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- DSP48_X1Y32 DSP48E1 0.000 0.000 r u_matmul_axi_slave/mult_inst[0].u_mult/prod0__17/ACOUT[16] net (fo=1, routed) 0.002 0.002 u_matmul_axi_slave/mult_inst[0].u_mult/prod0__17_n_37 DSP48_X1Y33 DSP48E1 r u_matmul_axi_slave/mult_inst[0].u_mult/prod_reg__0/ACIN[16] ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9603, routed) 2.028 -2.314 u_matmul_axi_slave/mult_inst[0].u_mult/sys_clk DSP48_X1Y33 DSP48E1 r u_matmul_axi_slave/mult_inst[0].u_mult/prod_reg__0/CLK Slack: inf Source: u_matmul_axi_slave/mult_inst[0].u_mult/prod0__17/ACOUT[17] (internal pin) Destination: u_matmul_axi_slave/mult_inst[0].u_mult/prod_reg__0/ACIN[17] (rising edge-triggered cell DSP48E1 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: (none) Path Type: Hold (Min at Slow Process Corner) Data Path Delay: 0.002ns (logic 0.000ns (0.000%) route 0.002ns (100.000%)) Logic Levels: 0 Clock Uncertainty: 0.190ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.050ns Discrete Jitter (DJ): 0.122ns Phase Error (PE): 0.124ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- DSP48_X1Y32 DSP48E1 0.000 0.000 r u_matmul_axi_slave/mult_inst[0].u_mult/prod0__17/ACOUT[17] net (fo=1, routed) 0.002 0.002 u_matmul_axi_slave/mult_inst[0].u_mult/prod0__17_n_36 DSP48_X1Y33 DSP48E1 r u_matmul_axi_slave/mult_inst[0].u_mult/prod_reg__0/ACIN[17] ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9603, routed) 2.028 -2.314 u_matmul_axi_slave/mult_inst[0].u_mult/sys_clk DSP48_X1Y33 DSP48E1 r u_matmul_axi_slave/mult_inst[0].u_mult/prod_reg__0/CLK Slack: inf Source: u_matmul_axi_slave/mult_inst[0].u_mult/prod0__17/ACOUT[18] (internal pin) Destination: u_matmul_axi_slave/mult_inst[0].u_mult/prod_reg__0/ACIN[18] (rising edge-triggered cell DSP48E1 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: (none) Path Type: Hold (Min at Slow Process Corner) Data Path Delay: 0.002ns (logic 0.000ns (0.000%) route 0.002ns (100.000%)) Logic Levels: 0 Clock Uncertainty: 0.190ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.050ns Discrete Jitter (DJ): 0.122ns Phase Error (PE): 0.124ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- DSP48_X1Y32 DSP48E1 0.000 0.000 r u_matmul_axi_slave/mult_inst[0].u_mult/prod0__17/ACOUT[18] net (fo=1, routed) 0.002 0.002 u_matmul_axi_slave/mult_inst[0].u_mult/prod0__17_n_35 DSP48_X1Y33 DSP48E1 r u_matmul_axi_slave/mult_inst[0].u_mult/prod_reg__0/ACIN[18] ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9603, routed) 2.028 -2.314 u_matmul_axi_slave/mult_inst[0].u_mult/sys_clk DSP48_X1Y33 DSP48E1 r u_matmul_axi_slave/mult_inst[0].u_mult/prod_reg__0/CLK Slack: inf Source: u_matmul_axi_slave/mult_inst[0].u_mult/prod0__17/ACOUT[19] (internal pin) Destination: u_matmul_axi_slave/mult_inst[0].u_mult/prod_reg__0/ACIN[19] (rising edge-triggered cell DSP48E1 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: (none) Path Type: Hold (Min at Slow Process Corner) Data Path Delay: 0.002ns (logic 0.000ns (0.000%) route 0.002ns (100.000%)) Logic Levels: 0 Clock Uncertainty: 0.190ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.050ns Discrete Jitter (DJ): 0.122ns Phase Error (PE): 0.124ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- DSP48_X1Y32 DSP48E1 0.000 0.000 r u_matmul_axi_slave/mult_inst[0].u_mult/prod0__17/ACOUT[19] net (fo=1, routed) 0.002 0.002 u_matmul_axi_slave/mult_inst[0].u_mult/prod0__17_n_34 DSP48_X1Y33 DSP48E1 r u_matmul_axi_slave/mult_inst[0].u_mult/prod_reg__0/ACIN[19] ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9603, routed) 2.028 -2.314 u_matmul_axi_slave/mult_inst[0].u_mult/sys_clk DSP48_X1Y33 DSP48E1 r u_matmul_axi_slave/mult_inst[0].u_mult/prod_reg__0/CLK Slack: inf Source: u_matmul_axi_slave/mult_inst[0].u_mult/prod0__17/ACOUT[1] (internal pin) Destination: u_matmul_axi_slave/mult_inst[0].u_mult/prod_reg__0/ACIN[1] (rising edge-triggered cell DSP48E1 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: (none) Path Type: Hold (Min at Slow Process Corner) Data Path Delay: 0.002ns (logic 0.000ns (0.000%) route 0.002ns (100.000%)) Logic Levels: 0 Clock Uncertainty: 0.190ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.050ns Discrete Jitter (DJ): 0.122ns Phase Error (PE): 0.124ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- DSP48_X1Y32 DSP48E1 0.000 0.000 r u_matmul_axi_slave/mult_inst[0].u_mult/prod0__17/ACOUT[1] net (fo=1, routed) 0.002 0.002 u_matmul_axi_slave/mult_inst[0].u_mult/prod0__17_n_52 DSP48_X1Y33 DSP48E1 r u_matmul_axi_slave/mult_inst[0].u_mult/prod_reg__0/ACIN[1] ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9603, routed) 2.028 -2.314 u_matmul_axi_slave/mult_inst[0].u_mult/sys_clk DSP48_X1Y33 DSP48E1 r u_matmul_axi_slave/mult_inst[0].u_mult/prod_reg__0/CLK Slack: inf Source: u_matmul_axi_slave/mult_inst[0].u_mult/prod0__17/ACOUT[20] (internal pin) Destination: u_matmul_axi_slave/mult_inst[0].u_mult/prod_reg__0/ACIN[20] (rising edge-triggered cell DSP48E1 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: (none) Path Type: Hold (Min at Slow Process Corner) Data Path Delay: 0.002ns (logic 0.000ns (0.000%) route 0.002ns (100.000%)) Logic Levels: 0 Clock Uncertainty: 0.190ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.050ns Discrete Jitter (DJ): 0.122ns Phase Error (PE): 0.124ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- DSP48_X1Y32 DSP48E1 0.000 0.000 r u_matmul_axi_slave/mult_inst[0].u_mult/prod0__17/ACOUT[20] net (fo=1, routed) 0.002 0.002 u_matmul_axi_slave/mult_inst[0].u_mult/prod0__17_n_33 DSP48_X1Y33 DSP48E1 r u_matmul_axi_slave/mult_inst[0].u_mult/prod_reg__0/ACIN[20] ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9603, routed) 2.028 -2.314 u_matmul_axi_slave/mult_inst[0].u_mult/sys_clk DSP48_X1Y33 DSP48E1 r u_matmul_axi_slave/mult_inst[0].u_mult/prod_reg__0/CLK Slack: inf Source: u_matmul_axi_slave/mult_inst[0].u_mult/prod0__17/ACOUT[21] (internal pin) Destination: u_matmul_axi_slave/mult_inst[0].u_mult/prod_reg__0/ACIN[21] (rising edge-triggered cell DSP48E1 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: (none) Path Type: Hold (Min at Slow Process Corner) Data Path Delay: 0.002ns (logic 0.000ns (0.000%) route 0.002ns (100.000%)) Logic Levels: 0 Clock Uncertainty: 0.190ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.050ns Discrete Jitter (DJ): 0.122ns Phase Error (PE): 0.124ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- DSP48_X1Y32 DSP48E1 0.000 0.000 r u_matmul_axi_slave/mult_inst[0].u_mult/prod0__17/ACOUT[21] net (fo=1, routed) 0.002 0.002 u_matmul_axi_slave/mult_inst[0].u_mult/prod0__17_n_32 DSP48_X1Y33 DSP48E1 r u_matmul_axi_slave/mult_inst[0].u_mult/prod_reg__0/ACIN[21] ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9603, routed) 2.028 -2.314 u_matmul_axi_slave/mult_inst[0].u_mult/sys_clk DSP48_X1Y33 DSP48E1 r u_matmul_axi_slave/mult_inst[0].u_mult/prod_reg__0/CLK Slack: inf Source: u_matmul_axi_slave/mult_inst[0].u_mult/prod0__17/ACOUT[22] (internal pin) Destination: u_matmul_axi_slave/mult_inst[0].u_mult/prod_reg__0/ACIN[22] (rising edge-triggered cell DSP48E1 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: (none) Path Type: Hold (Min at Slow Process Corner) Data Path Delay: 0.002ns (logic 0.000ns (0.000%) route 0.002ns (100.000%)) Logic Levels: 0 Clock Uncertainty: 0.190ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.050ns Discrete Jitter (DJ): 0.122ns Phase Error (PE): 0.124ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- DSP48_X1Y32 DSP48E1 0.000 0.000 r u_matmul_axi_slave/mult_inst[0].u_mult/prod0__17/ACOUT[22] net (fo=1, routed) 0.002 0.002 u_matmul_axi_slave/mult_inst[0].u_mult/prod0__17_n_31 DSP48_X1Y33 DSP48E1 r u_matmul_axi_slave/mult_inst[0].u_mult/prod_reg__0/ACIN[22] ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9603, routed) 2.028 -2.314 u_matmul_axi_slave/mult_inst[0].u_mult/sys_clk DSP48_X1Y33 DSP48E1 r u_matmul_axi_slave/mult_inst[0].u_mult/prod_reg__0/CLK Slack: inf Source: u_matmul_axi_slave/mult_inst[0].u_mult/prod0__17/ACOUT[23] (internal pin) Destination: u_matmul_axi_slave/mult_inst[0].u_mult/prod_reg__0/ACIN[23] (rising edge-triggered cell DSP48E1 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: (none) Path Type: Hold (Min at Slow Process Corner) Data Path Delay: 0.002ns (logic 0.000ns (0.000%) route 0.002ns (100.000%)) Logic Levels: 0 Clock Uncertainty: 0.190ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.050ns Discrete Jitter (DJ): 0.122ns Phase Error (PE): 0.124ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- DSP48_X1Y32 DSP48E1 0.000 0.000 r u_matmul_axi_slave/mult_inst[0].u_mult/prod0__17/ACOUT[23] net (fo=1, routed) 0.002 0.002 u_matmul_axi_slave/mult_inst[0].u_mult/prod0__17_n_30 DSP48_X1Y33 DSP48E1 r u_matmul_axi_slave/mult_inst[0].u_mult/prod_reg__0/ACIN[23] ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9603, routed) 2.028 -2.314 u_matmul_axi_slave/mult_inst[0].u_mult/sys_clk DSP48_X1Y33 DSP48E1 r u_matmul_axi_slave/mult_inst[0].u_mult/prod_reg__0/CLK Slack: inf Source: u_matmul_axi_slave/mult_inst[0].u_mult/prod0__17/ACOUT[24] (internal pin) Destination: u_matmul_axi_slave/mult_inst[0].u_mult/prod_reg__0/ACIN[24] (rising edge-triggered cell DSP48E1 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: (none) Path Type: Hold (Min at Slow Process Corner) Data Path Delay: 0.002ns (logic 0.000ns (0.000%) route 0.002ns (100.000%)) Logic Levels: 0 Clock Uncertainty: 0.190ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.050ns Discrete Jitter (DJ): 0.122ns Phase Error (PE): 0.124ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- DSP48_X1Y32 DSP48E1 0.000 0.000 r u_matmul_axi_slave/mult_inst[0].u_mult/prod0__17/ACOUT[24] net (fo=1, routed) 0.002 0.002 u_matmul_axi_slave/mult_inst[0].u_mult/prod0__17_n_29 DSP48_X1Y33 DSP48E1 r u_matmul_axi_slave/mult_inst[0].u_mult/prod_reg__0/ACIN[24] ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9603, routed) 2.028 -2.314 u_matmul_axi_slave/mult_inst[0].u_mult/sys_clk DSP48_X1Y33 DSP48E1 r u_matmul_axi_slave/mult_inst[0].u_mult/prod_reg__0/CLK Slack: inf Source: u_matmul_axi_slave/mult_inst[0].u_mult/prod0__17/ACOUT[25] (internal pin) Destination: u_matmul_axi_slave/mult_inst[0].u_mult/prod_reg__0/ACIN[25] (rising edge-triggered cell DSP48E1 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: (none) Path Type: Hold (Min at Slow Process Corner) Data Path Delay: 0.002ns (logic 0.000ns (0.000%) route 0.002ns (100.000%)) Logic Levels: 0 Clock Uncertainty: 0.190ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.050ns Discrete Jitter (DJ): 0.122ns Phase Error (PE): 0.124ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- DSP48_X1Y32 DSP48E1 0.000 0.000 r u_matmul_axi_slave/mult_inst[0].u_mult/prod0__17/ACOUT[25] net (fo=1, routed) 0.002 0.002 u_matmul_axi_slave/mult_inst[0].u_mult/prod0__17_n_28 DSP48_X1Y33 DSP48E1 r u_matmul_axi_slave/mult_inst[0].u_mult/prod_reg__0/ACIN[25] ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9603, routed) 2.028 -2.314 u_matmul_axi_slave/mult_inst[0].u_mult/sys_clk DSP48_X1Y33 DSP48E1 r u_matmul_axi_slave/mult_inst[0].u_mult/prod_reg__0/CLK Slack: inf Source: u_matmul_axi_slave/mult_inst[0].u_mult/prod0__17/ACOUT[26] (internal pin) Destination: u_matmul_axi_slave/mult_inst[0].u_mult/prod_reg__0/ACIN[26] (rising edge-triggered cell DSP48E1 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: (none) Path Type: Hold (Min at Slow Process Corner) Data Path Delay: 0.002ns (logic 0.000ns (0.000%) route 0.002ns (100.000%)) Logic Levels: 0 Clock Uncertainty: 0.190ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.050ns Discrete Jitter (DJ): 0.122ns Phase Error (PE): 0.124ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- DSP48_X1Y32 DSP48E1 0.000 0.000 r u_matmul_axi_slave/mult_inst[0].u_mult/prod0__17/ACOUT[26] net (fo=1, routed) 0.002 0.002 u_matmul_axi_slave/mult_inst[0].u_mult/prod0__17_n_27 DSP48_X1Y33 DSP48E1 r u_matmul_axi_slave/mult_inst[0].u_mult/prod_reg__0/ACIN[26] ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9603, routed) 2.028 -2.314 u_matmul_axi_slave/mult_inst[0].u_mult/sys_clk DSP48_X1Y33 DSP48E1 r u_matmul_axi_slave/mult_inst[0].u_mult/prod_reg__0/CLK Slack: inf Source: u_matmul_axi_slave/mult_inst[0].u_mult/prod0__17/ACOUT[27] (internal pin) Destination: u_matmul_axi_slave/mult_inst[0].u_mult/prod_reg__0/ACIN[27] (rising edge-triggered cell DSP48E1 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: (none) Path Type: Hold (Min at Slow Process Corner) Data Path Delay: 0.002ns (logic 0.000ns (0.000%) route 0.002ns (100.000%)) Logic Levels: 0 Clock Uncertainty: 0.190ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.050ns Discrete Jitter (DJ): 0.122ns Phase Error (PE): 0.124ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- DSP48_X1Y32 DSP48E1 0.000 0.000 r u_matmul_axi_slave/mult_inst[0].u_mult/prod0__17/ACOUT[27] net (fo=1, routed) 0.002 0.002 u_matmul_axi_slave/mult_inst[0].u_mult/prod0__17_n_26 DSP48_X1Y33 DSP48E1 r u_matmul_axi_slave/mult_inst[0].u_mult/prod_reg__0/ACIN[27] ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9603, routed) 2.028 -2.314 u_matmul_axi_slave/mult_inst[0].u_mult/sys_clk DSP48_X1Y33 DSP48E1 r u_matmul_axi_slave/mult_inst[0].u_mult/prod_reg__0/CLK Slack: inf Source: u_matmul_axi_slave/mult_inst[0].u_mult/prod0__17/ACOUT[28] (internal pin) Destination: u_matmul_axi_slave/mult_inst[0].u_mult/prod_reg__0/ACIN[28] (rising edge-triggered cell DSP48E1 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: (none) Path Type: Hold (Min at Slow Process Corner) Data Path Delay: 0.002ns (logic 0.000ns (0.000%) route 0.002ns (100.000%)) Logic Levels: 0 Clock Uncertainty: 0.190ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.050ns Discrete Jitter (DJ): 0.122ns Phase Error (PE): 0.124ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- DSP48_X1Y32 DSP48E1 0.000 0.000 r u_matmul_axi_slave/mult_inst[0].u_mult/prod0__17/ACOUT[28] net (fo=1, routed) 0.002 0.002 u_matmul_axi_slave/mult_inst[0].u_mult/prod0__17_n_25 DSP48_X1Y33 DSP48E1 r u_matmul_axi_slave/mult_inst[0].u_mult/prod_reg__0/ACIN[28] ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9603, routed) 2.028 -2.314 u_matmul_axi_slave/mult_inst[0].u_mult/sys_clk DSP48_X1Y33 DSP48E1 r u_matmul_axi_slave/mult_inst[0].u_mult/prod_reg__0/CLK Slack: inf Source: u_matmul_axi_slave/mult_inst[0].u_mult/prod0__17/ACOUT[29] (internal pin) Destination: u_matmul_axi_slave/mult_inst[0].u_mult/prod_reg__0/ACIN[29] (rising edge-triggered cell DSP48E1 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: (none) Path Type: Hold (Min at Slow Process Corner) Data Path Delay: 0.002ns (logic 0.000ns (0.000%) route 0.002ns (100.000%)) Logic Levels: 0 Clock Uncertainty: 0.190ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.050ns Discrete Jitter (DJ): 0.122ns Phase Error (PE): 0.124ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- DSP48_X1Y32 DSP48E1 0.000 0.000 r u_matmul_axi_slave/mult_inst[0].u_mult/prod0__17/ACOUT[29] net (fo=1, routed) 0.002 0.002 u_matmul_axi_slave/mult_inst[0].u_mult/prod0__17_n_24 DSP48_X1Y33 DSP48E1 r u_matmul_axi_slave/mult_inst[0].u_mult/prod_reg__0/ACIN[29] ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9603, routed) 2.028 -2.314 u_matmul_axi_slave/mult_inst[0].u_mult/sys_clk DSP48_X1Y33 DSP48E1 r u_matmul_axi_slave/mult_inst[0].u_mult/prod_reg__0/CLK Slack: inf Source: u_matmul_axi_slave/mult_inst[0].u_mult/prod0__17/ACOUT[2] (internal pin) Destination: u_matmul_axi_slave/mult_inst[0].u_mult/prod_reg__0/ACIN[2] (rising edge-triggered cell DSP48E1 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: (none) Path Type: Hold (Min at Slow Process Corner) Data Path Delay: 0.002ns (logic 0.000ns (0.000%) route 0.002ns (100.000%)) Logic Levels: 0 Clock Uncertainty: 0.190ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.050ns Discrete Jitter (DJ): 0.122ns Phase Error (PE): 0.124ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- DSP48_X1Y32 DSP48E1 0.000 0.000 r u_matmul_axi_slave/mult_inst[0].u_mult/prod0__17/ACOUT[2] net (fo=1, routed) 0.002 0.002 u_matmul_axi_slave/mult_inst[0].u_mult/prod0__17_n_51 DSP48_X1Y33 DSP48E1 r u_matmul_axi_slave/mult_inst[0].u_mult/prod_reg__0/ACIN[2] ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9603, routed) 2.028 -2.314 u_matmul_axi_slave/mult_inst[0].u_mult/sys_clk DSP48_X1Y33 DSP48E1 r u_matmul_axi_slave/mult_inst[0].u_mult/prod_reg__0/CLK Slack: inf Source: u_matmul_axi_slave/mult_inst[0].u_mult/prod0__17/ACOUT[3] (internal pin) Destination: u_matmul_axi_slave/mult_inst[0].u_mult/prod_reg__0/ACIN[3] (rising edge-triggered cell DSP48E1 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: (none) Path Type: Hold (Min at Slow Process Corner) Data Path Delay: 0.002ns (logic 0.000ns (0.000%) route 0.002ns (100.000%)) Logic Levels: 0 Clock Uncertainty: 0.190ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.050ns Discrete Jitter (DJ): 0.122ns Phase Error (PE): 0.124ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- DSP48_X1Y32 DSP48E1 0.000 0.000 r u_matmul_axi_slave/mult_inst[0].u_mult/prod0__17/ACOUT[3] net (fo=1, routed) 0.002 0.002 u_matmul_axi_slave/mult_inst[0].u_mult/prod0__17_n_50 DSP48_X1Y33 DSP48E1 r u_matmul_axi_slave/mult_inst[0].u_mult/prod_reg__0/ACIN[3] ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9603, routed) 2.028 -2.314 u_matmul_axi_slave/mult_inst[0].u_mult/sys_clk DSP48_X1Y33 DSP48E1 r u_matmul_axi_slave/mult_inst[0].u_mult/prod_reg__0/CLK Slack: inf Source: u_matmul_axi_slave/mult_inst[0].u_mult/prod0__17/ACOUT[4] (internal pin) Destination: u_matmul_axi_slave/mult_inst[0].u_mult/prod_reg__0/ACIN[4] (rising edge-triggered cell DSP48E1 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: (none) Path Type: Hold (Min at Slow Process Corner) Data Path Delay: 0.002ns (logic 0.000ns (0.000%) route 0.002ns (100.000%)) Logic Levels: 0 Clock Uncertainty: 0.190ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.050ns Discrete Jitter (DJ): 0.122ns Phase Error (PE): 0.124ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- DSP48_X1Y32 DSP48E1 0.000 0.000 r u_matmul_axi_slave/mult_inst[0].u_mult/prod0__17/ACOUT[4] net (fo=1, routed) 0.002 0.002 u_matmul_axi_slave/mult_inst[0].u_mult/prod0__17_n_49 DSP48_X1Y33 DSP48E1 r u_matmul_axi_slave/mult_inst[0].u_mult/prod_reg__0/ACIN[4] ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9603, routed) 2.028 -2.314 u_matmul_axi_slave/mult_inst[0].u_mult/sys_clk DSP48_X1Y33 DSP48E1 r u_matmul_axi_slave/mult_inst[0].u_mult/prod_reg__0/CLK Slack: inf Source: u_matmul_axi_slave/mult_inst[0].u_mult/prod0__17/ACOUT[5] (internal pin) Destination: u_matmul_axi_slave/mult_inst[0].u_mult/prod_reg__0/ACIN[5] (rising edge-triggered cell DSP48E1 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: (none) Path Type: Hold (Min at Slow Process Corner) Data Path Delay: 0.002ns (logic 0.000ns (0.000%) route 0.002ns (100.000%)) Logic Levels: 0 Clock Uncertainty: 0.190ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.050ns Discrete Jitter (DJ): 0.122ns Phase Error (PE): 0.124ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- DSP48_X1Y32 DSP48E1 0.000 0.000 r u_matmul_axi_slave/mult_inst[0].u_mult/prod0__17/ACOUT[5] net (fo=1, routed) 0.002 0.002 u_matmul_axi_slave/mult_inst[0].u_mult/prod0__17_n_48 DSP48_X1Y33 DSP48E1 r u_matmul_axi_slave/mult_inst[0].u_mult/prod_reg__0/ACIN[5] ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9603, routed) 2.028 -2.314 u_matmul_axi_slave/mult_inst[0].u_mult/sys_clk DSP48_X1Y33 DSP48E1 r u_matmul_axi_slave/mult_inst[0].u_mult/prod_reg__0/CLK Slack: inf Source: u_matmul_axi_slave/mult_inst[0].u_mult/prod0__17/ACOUT[6] (internal pin) Destination: u_matmul_axi_slave/mult_inst[0].u_mult/prod_reg__0/ACIN[6] (rising edge-triggered cell DSP48E1 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: (none) Path Type: Hold (Min at Slow Process Corner) Data Path Delay: 0.002ns (logic 0.000ns (0.000%) route 0.002ns (100.000%)) Logic Levels: 0 Clock Uncertainty: 0.190ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.050ns Discrete Jitter (DJ): 0.122ns Phase Error (PE): 0.124ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- DSP48_X1Y32 DSP48E1 0.000 0.000 r u_matmul_axi_slave/mult_inst[0].u_mult/prod0__17/ACOUT[6] net (fo=1, routed) 0.002 0.002 u_matmul_axi_slave/mult_inst[0].u_mult/prod0__17_n_47 DSP48_X1Y33 DSP48E1 r u_matmul_axi_slave/mult_inst[0].u_mult/prod_reg__0/ACIN[6] ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9603, routed) 2.028 -2.314 u_matmul_axi_slave/mult_inst[0].u_mult/sys_clk DSP48_X1Y33 DSP48E1 r u_matmul_axi_slave/mult_inst[0].u_mult/prod_reg__0/CLK Slack: inf Source: u_matmul_axi_slave/mult_inst[0].u_mult/prod0__17/ACOUT[7] (internal pin) Destination: u_matmul_axi_slave/mult_inst[0].u_mult/prod_reg__0/ACIN[7] (rising edge-triggered cell DSP48E1 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: (none) Path Type: Hold (Min at Slow Process Corner) Data Path Delay: 0.002ns (logic 0.000ns (0.000%) route 0.002ns (100.000%)) Logic Levels: 0 Clock Uncertainty: 0.190ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.050ns Discrete Jitter (DJ): 0.122ns Phase Error (PE): 0.124ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- DSP48_X1Y32 DSP48E1 0.000 0.000 r u_matmul_axi_slave/mult_inst[0].u_mult/prod0__17/ACOUT[7] net (fo=1, routed) 0.002 0.002 u_matmul_axi_slave/mult_inst[0].u_mult/prod0__17_n_46 DSP48_X1Y33 DSP48E1 r u_matmul_axi_slave/mult_inst[0].u_mult/prod_reg__0/ACIN[7] ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9603, routed) 2.028 -2.314 u_matmul_axi_slave/mult_inst[0].u_mult/sys_clk DSP48_X1Y33 DSP48E1 r u_matmul_axi_slave/mult_inst[0].u_mult/prod_reg__0/CLK Slack: inf Source: u_matmul_axi_slave/mult_inst[0].u_mult/prod0__17/ACOUT[8] (internal pin) Destination: u_matmul_axi_slave/mult_inst[0].u_mult/prod_reg__0/ACIN[8] (rising edge-triggered cell DSP48E1 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: (none) Path Type: Hold (Min at Slow Process Corner) Data Path Delay: 0.002ns (logic 0.000ns (0.000%) route 0.002ns (100.000%)) Logic Levels: 0 Clock Uncertainty: 0.190ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.050ns Discrete Jitter (DJ): 0.122ns Phase Error (PE): 0.124ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- DSP48_X1Y32 DSP48E1 0.000 0.000 r u_matmul_axi_slave/mult_inst[0].u_mult/prod0__17/ACOUT[8] net (fo=1, routed) 0.002 0.002 u_matmul_axi_slave/mult_inst[0].u_mult/prod0__17_n_45 DSP48_X1Y33 DSP48E1 r u_matmul_axi_slave/mult_inst[0].u_mult/prod_reg__0/ACIN[8] ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9603, routed) 2.028 -2.314 u_matmul_axi_slave/mult_inst[0].u_mult/sys_clk DSP48_X1Y33 DSP48E1 r u_matmul_axi_slave/mult_inst[0].u_mult/prod_reg__0/CLK Slack: inf Source: u_matmul_axi_slave/mult_inst[0].u_mult/prod0__17/ACOUT[9] (internal pin) Destination: u_matmul_axi_slave/mult_inst[0].u_mult/prod_reg__0/ACIN[9] (rising edge-triggered cell DSP48E1 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: (none) Path Type: Hold (Min at Slow Process Corner) Data Path Delay: 0.002ns (logic 0.000ns (0.000%) route 0.002ns (100.000%)) Logic Levels: 0 Clock Uncertainty: 0.190ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.050ns Discrete Jitter (DJ): 0.122ns Phase Error (PE): 0.124ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- DSP48_X1Y32 DSP48E1 0.000 0.000 r u_matmul_axi_slave/mult_inst[0].u_mult/prod0__17/ACOUT[9] net (fo=1, routed) 0.002 0.002 u_matmul_axi_slave/mult_inst[0].u_mult/prod0__17_n_44 DSP48_X1Y33 DSP48E1 r u_matmul_axi_slave/mult_inst[0].u_mult/prod_reg__0/ACIN[9] ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9603, routed) 2.028 -2.314 u_matmul_axi_slave/mult_inst[0].u_mult/sys_clk DSP48_X1Y33 DSP48E1 r u_matmul_axi_slave/mult_inst[0].u_mult/prod_reg__0/CLK Slack: inf Source: u_matmul_axi_slave/mult_inst[1].u_mult/prod0__17/ACOUT[0] (internal pin) Destination: u_matmul_axi_slave/mult_inst[1].u_mult/prod_reg__0/ACIN[0] (rising edge-triggered cell DSP48E1 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: (none) Path Type: Hold (Min at Slow Process Corner) Data Path Delay: 0.002ns (logic 0.000ns (0.000%) route 0.002ns (100.000%)) Logic Levels: 0 Clock Uncertainty: 0.190ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.050ns Discrete Jitter (DJ): 0.122ns Phase Error (PE): 0.124ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- DSP48_X0Y38 DSP48E1 0.000 0.000 r u_matmul_axi_slave/mult_inst[1].u_mult/prod0__17/ACOUT[0] net (fo=1, routed) 0.002 0.002 u_matmul_axi_slave/mult_inst[1].u_mult/prod0__17_n_53 DSP48_X0Y39 DSP48E1 r u_matmul_axi_slave/mult_inst[1].u_mult/prod_reg__0/ACIN[0] ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9603, routed) 2.040 -2.302 u_matmul_axi_slave/mult_inst[1].u_mult/sys_clk DSP48_X0Y39 DSP48E1 r u_matmul_axi_slave/mult_inst[1].u_mult/prod_reg__0/CLK Slack: inf Source: u_matmul_axi_slave/mult_inst[1].u_mult/prod0__17/ACOUT[10] (internal pin) Destination: u_matmul_axi_slave/mult_inst[1].u_mult/prod_reg__0/ACIN[10] (rising edge-triggered cell DSP48E1 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: (none) Path Type: Hold (Min at Slow Process Corner) Data Path Delay: 0.002ns (logic 0.000ns (0.000%) route 0.002ns (100.000%)) Logic Levels: 0 Clock Uncertainty: 0.190ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.050ns Discrete Jitter (DJ): 0.122ns Phase Error (PE): 0.124ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- DSP48_X0Y38 DSP48E1 0.000 0.000 r u_matmul_axi_slave/mult_inst[1].u_mult/prod0__17/ACOUT[10] net (fo=1, routed) 0.002 0.002 u_matmul_axi_slave/mult_inst[1].u_mult/prod0__17_n_43 DSP48_X0Y39 DSP48E1 r u_matmul_axi_slave/mult_inst[1].u_mult/prod_reg__0/ACIN[10] ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9603, routed) 2.040 -2.302 u_matmul_axi_slave/mult_inst[1].u_mult/sys_clk DSP48_X0Y39 DSP48E1 r u_matmul_axi_slave/mult_inst[1].u_mult/prod_reg__0/CLK Slack: inf Source: u_matmul_axi_slave/mult_inst[1].u_mult/prod0__17/ACOUT[11] (internal pin) Destination: u_matmul_axi_slave/mult_inst[1].u_mult/prod_reg__0/ACIN[11] (rising edge-triggered cell DSP48E1 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: (none) Path Type: Hold (Min at Slow Process Corner) Data Path Delay: 0.002ns (logic 0.000ns (0.000%) route 0.002ns (100.000%)) Logic Levels: 0 Clock Uncertainty: 0.190ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.050ns Discrete Jitter (DJ): 0.122ns Phase Error (PE): 0.124ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- DSP48_X0Y38 DSP48E1 0.000 0.000 r u_matmul_axi_slave/mult_inst[1].u_mult/prod0__17/ACOUT[11] net (fo=1, routed) 0.002 0.002 u_matmul_axi_slave/mult_inst[1].u_mult/prod0__17_n_42 DSP48_X0Y39 DSP48E1 r u_matmul_axi_slave/mult_inst[1].u_mult/prod_reg__0/ACIN[11] ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9603, routed) 2.040 -2.302 u_matmul_axi_slave/mult_inst[1].u_mult/sys_clk DSP48_X0Y39 DSP48E1 r u_matmul_axi_slave/mult_inst[1].u_mult/prod_reg__0/CLK Slack: inf Source: u_matmul_axi_slave/mult_inst[1].u_mult/prod0__17/ACOUT[12] (internal pin) Destination: u_matmul_axi_slave/mult_inst[1].u_mult/prod_reg__0/ACIN[12] (rising edge-triggered cell DSP48E1 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: (none) Path Type: Hold (Min at Slow Process Corner) Data Path Delay: 0.002ns (logic 0.000ns (0.000%) route 0.002ns (100.000%)) Logic Levels: 0 Clock Uncertainty: 0.190ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.050ns Discrete Jitter (DJ): 0.122ns Phase Error (PE): 0.124ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- DSP48_X0Y38 DSP48E1 0.000 0.000 r u_matmul_axi_slave/mult_inst[1].u_mult/prod0__17/ACOUT[12] net (fo=1, routed) 0.002 0.002 u_matmul_axi_slave/mult_inst[1].u_mult/prod0__17_n_41 DSP48_X0Y39 DSP48E1 r u_matmul_axi_slave/mult_inst[1].u_mult/prod_reg__0/ACIN[12] ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9603, routed) 2.040 -2.302 u_matmul_axi_slave/mult_inst[1].u_mult/sys_clk DSP48_X0Y39 DSP48E1 r u_matmul_axi_slave/mult_inst[1].u_mult/prod_reg__0/CLK Slack: inf Source: u_matmul_axi_slave/mult_inst[1].u_mult/prod0__17/ACOUT[13] (internal pin) Destination: u_matmul_axi_slave/mult_inst[1].u_mult/prod_reg__0/ACIN[13] (rising edge-triggered cell DSP48E1 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: (none) Path Type: Hold (Min at Slow Process Corner) Data Path Delay: 0.002ns (logic 0.000ns (0.000%) route 0.002ns (100.000%)) Logic Levels: 0 Clock Uncertainty: 0.190ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.050ns Discrete Jitter (DJ): 0.122ns Phase Error (PE): 0.124ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- DSP48_X0Y38 DSP48E1 0.000 0.000 r u_matmul_axi_slave/mult_inst[1].u_mult/prod0__17/ACOUT[13] net (fo=1, routed) 0.002 0.002 u_matmul_axi_slave/mult_inst[1].u_mult/prod0__17_n_40 DSP48_X0Y39 DSP48E1 r u_matmul_axi_slave/mult_inst[1].u_mult/prod_reg__0/ACIN[13] ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9603, routed) 2.040 -2.302 u_matmul_axi_slave/mult_inst[1].u_mult/sys_clk DSP48_X0Y39 DSP48E1 r u_matmul_axi_slave/mult_inst[1].u_mult/prod_reg__0/CLK Slack: inf Source: u_matmul_axi_slave/mult_inst[1].u_mult/prod0__17/ACOUT[14] (internal pin) Destination: u_matmul_axi_slave/mult_inst[1].u_mult/prod_reg__0/ACIN[14] (rising edge-triggered cell DSP48E1 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: (none) Path Type: Hold (Min at Slow Process Corner) Data Path Delay: 0.002ns (logic 0.000ns (0.000%) route 0.002ns (100.000%)) Logic Levels: 0 Clock Uncertainty: 0.190ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.050ns Discrete Jitter (DJ): 0.122ns Phase Error (PE): 0.124ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- DSP48_X0Y38 DSP48E1 0.000 0.000 r u_matmul_axi_slave/mult_inst[1].u_mult/prod0__17/ACOUT[14] net (fo=1, routed) 0.002 0.002 u_matmul_axi_slave/mult_inst[1].u_mult/prod0__17_n_39 DSP48_X0Y39 DSP48E1 r u_matmul_axi_slave/mult_inst[1].u_mult/prod_reg__0/ACIN[14] ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9603, routed) 2.040 -2.302 u_matmul_axi_slave/mult_inst[1].u_mult/sys_clk DSP48_X0Y39 DSP48E1 r u_matmul_axi_slave/mult_inst[1].u_mult/prod_reg__0/CLK Slack: inf Source: u_matmul_axi_slave/mult_inst[1].u_mult/prod0__17/ACOUT[15] (internal pin) Destination: u_matmul_axi_slave/mult_inst[1].u_mult/prod_reg__0/ACIN[15] (rising edge-triggered cell DSP48E1 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: (none) Path Type: Hold (Min at Slow Process Corner) Data Path Delay: 0.002ns (logic 0.000ns (0.000%) route 0.002ns (100.000%)) Logic Levels: 0 Clock Uncertainty: 0.190ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.050ns Discrete Jitter (DJ): 0.122ns Phase Error (PE): 0.124ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- DSP48_X0Y38 DSP48E1 0.000 0.000 r u_matmul_axi_slave/mult_inst[1].u_mult/prod0__17/ACOUT[15] net (fo=1, routed) 0.002 0.002 u_matmul_axi_slave/mult_inst[1].u_mult/prod0__17_n_38 DSP48_X0Y39 DSP48E1 r u_matmul_axi_slave/mult_inst[1].u_mult/prod_reg__0/ACIN[15] ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9603, routed) 2.040 -2.302 u_matmul_axi_slave/mult_inst[1].u_mult/sys_clk DSP48_X0Y39 DSP48E1 r u_matmul_axi_slave/mult_inst[1].u_mult/prod_reg__0/CLK Slack: inf Source: u_matmul_axi_slave/mult_inst[1].u_mult/prod0__17/ACOUT[16] (internal pin) Destination: u_matmul_axi_slave/mult_inst[1].u_mult/prod_reg__0/ACIN[16] (rising edge-triggered cell DSP48E1 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: (none) Path Type: Hold (Min at Slow Process Corner) Data Path Delay: 0.002ns (logic 0.000ns (0.000%) route 0.002ns (100.000%)) Logic Levels: 0 Clock Uncertainty: 0.190ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.050ns Discrete Jitter (DJ): 0.122ns Phase Error (PE): 0.124ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- DSP48_X0Y38 DSP48E1 0.000 0.000 r u_matmul_axi_slave/mult_inst[1].u_mult/prod0__17/ACOUT[16] net (fo=1, routed) 0.002 0.002 u_matmul_axi_slave/mult_inst[1].u_mult/prod0__17_n_37 DSP48_X0Y39 DSP48E1 r u_matmul_axi_slave/mult_inst[1].u_mult/prod_reg__0/ACIN[16] ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9603, routed) 2.040 -2.302 u_matmul_axi_slave/mult_inst[1].u_mult/sys_clk DSP48_X0Y39 DSP48E1 r u_matmul_axi_slave/mult_inst[1].u_mult/prod_reg__0/CLK Slack: inf Source: u_matmul_axi_slave/mult_inst[1].u_mult/prod0__17/ACOUT[17] (internal pin) Destination: u_matmul_axi_slave/mult_inst[1].u_mult/prod_reg__0/ACIN[17] (rising edge-triggered cell DSP48E1 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: (none) Path Type: Hold (Min at Slow Process Corner) Data Path Delay: 0.002ns (logic 0.000ns (0.000%) route 0.002ns (100.000%)) Logic Levels: 0 Clock Uncertainty: 0.190ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.050ns Discrete Jitter (DJ): 0.122ns Phase Error (PE): 0.124ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- DSP48_X0Y38 DSP48E1 0.000 0.000 r u_matmul_axi_slave/mult_inst[1].u_mult/prod0__17/ACOUT[17] net (fo=1, routed) 0.002 0.002 u_matmul_axi_slave/mult_inst[1].u_mult/prod0__17_n_36 DSP48_X0Y39 DSP48E1 r u_matmul_axi_slave/mult_inst[1].u_mult/prod_reg__0/ACIN[17] ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9603, routed) 2.040 -2.302 u_matmul_axi_slave/mult_inst[1].u_mult/sys_clk DSP48_X0Y39 DSP48E1 r u_matmul_axi_slave/mult_inst[1].u_mult/prod_reg__0/CLK Slack: inf Source: u_matmul_axi_slave/mult_inst[1].u_mult/prod0__17/ACOUT[18] (internal pin) Destination: u_matmul_axi_slave/mult_inst[1].u_mult/prod_reg__0/ACIN[18] (rising edge-triggered cell DSP48E1 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: (none) Path Type: Hold (Min at Slow Process Corner) Data Path Delay: 0.002ns (logic 0.000ns (0.000%) route 0.002ns (100.000%)) Logic Levels: 0 Clock Uncertainty: 0.190ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.050ns Discrete Jitter (DJ): 0.122ns Phase Error (PE): 0.124ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- DSP48_X0Y38 DSP48E1 0.000 0.000 r u_matmul_axi_slave/mult_inst[1].u_mult/prod0__17/ACOUT[18] net (fo=1, routed) 0.002 0.002 u_matmul_axi_slave/mult_inst[1].u_mult/prod0__17_n_35 DSP48_X0Y39 DSP48E1 r u_matmul_axi_slave/mult_inst[1].u_mult/prod_reg__0/ACIN[18] ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9603, routed) 2.040 -2.302 u_matmul_axi_slave/mult_inst[1].u_mult/sys_clk DSP48_X0Y39 DSP48E1 r u_matmul_axi_slave/mult_inst[1].u_mult/prod_reg__0/CLK Slack: inf Source: u_matmul_axi_slave/mult_inst[1].u_mult/prod0__17/ACOUT[19] (internal pin) Destination: u_matmul_axi_slave/mult_inst[1].u_mult/prod_reg__0/ACIN[19] (rising edge-triggered cell DSP48E1 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: (none) Path Type: Hold (Min at Slow Process Corner) Data Path Delay: 0.002ns (logic 0.000ns (0.000%) route 0.002ns (100.000%)) Logic Levels: 0 Clock Uncertainty: 0.190ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.050ns Discrete Jitter (DJ): 0.122ns Phase Error (PE): 0.124ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- DSP48_X0Y38 DSP48E1 0.000 0.000 r u_matmul_axi_slave/mult_inst[1].u_mult/prod0__17/ACOUT[19] net (fo=1, routed) 0.002 0.002 u_matmul_axi_slave/mult_inst[1].u_mult/prod0__17_n_34 DSP48_X0Y39 DSP48E1 r u_matmul_axi_slave/mult_inst[1].u_mult/prod_reg__0/ACIN[19] ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9603, routed) 2.040 -2.302 u_matmul_axi_slave/mult_inst[1].u_mult/sys_clk DSP48_X0Y39 DSP48E1 r u_matmul_axi_slave/mult_inst[1].u_mult/prod_reg__0/CLK Slack: inf Source: u_matmul_axi_slave/mult_inst[1].u_mult/prod0__17/ACOUT[1] (internal pin) Destination: u_matmul_axi_slave/mult_inst[1].u_mult/prod_reg__0/ACIN[1] (rising edge-triggered cell DSP48E1 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: (none) Path Type: Hold (Min at Slow Process Corner) Data Path Delay: 0.002ns (logic 0.000ns (0.000%) route 0.002ns (100.000%)) Logic Levels: 0 Clock Uncertainty: 0.190ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.050ns Discrete Jitter (DJ): 0.122ns Phase Error (PE): 0.124ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- DSP48_X0Y38 DSP48E1 0.000 0.000 r u_matmul_axi_slave/mult_inst[1].u_mult/prod0__17/ACOUT[1] net (fo=1, routed) 0.002 0.002 u_matmul_axi_slave/mult_inst[1].u_mult/prod0__17_n_52 DSP48_X0Y39 DSP48E1 r u_matmul_axi_slave/mult_inst[1].u_mult/prod_reg__0/ACIN[1] ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9603, routed) 2.040 -2.302 u_matmul_axi_slave/mult_inst[1].u_mult/sys_clk DSP48_X0Y39 DSP48E1 r u_matmul_axi_slave/mult_inst[1].u_mult/prod_reg__0/CLK Slack: inf Source: u_matmul_axi_slave/mult_inst[1].u_mult/prod0__17/ACOUT[20] (internal pin) Destination: u_matmul_axi_slave/mult_inst[1].u_mult/prod_reg__0/ACIN[20] (rising edge-triggered cell DSP48E1 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: (none) Path Type: Hold (Min at Slow Process Corner) Data Path Delay: 0.002ns (logic 0.000ns (0.000%) route 0.002ns (100.000%)) Logic Levels: 0 Clock Uncertainty: 0.190ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.050ns Discrete Jitter (DJ): 0.122ns Phase Error (PE): 0.124ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- DSP48_X0Y38 DSP48E1 0.000 0.000 r u_matmul_axi_slave/mult_inst[1].u_mult/prod0__17/ACOUT[20] net (fo=1, routed) 0.002 0.002 u_matmul_axi_slave/mult_inst[1].u_mult/prod0__17_n_33 DSP48_X0Y39 DSP48E1 r u_matmul_axi_slave/mult_inst[1].u_mult/prod_reg__0/ACIN[20] ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9603, routed) 2.040 -2.302 u_matmul_axi_slave/mult_inst[1].u_mult/sys_clk DSP48_X0Y39 DSP48E1 r u_matmul_axi_slave/mult_inst[1].u_mult/prod_reg__0/CLK Slack: inf Source: u_matmul_axi_slave/mult_inst[1].u_mult/prod0__17/ACOUT[21] (internal pin) Destination: u_matmul_axi_slave/mult_inst[1].u_mult/prod_reg__0/ACIN[21] (rising edge-triggered cell DSP48E1 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: (none) Path Type: Hold (Min at Slow Process Corner) Data Path Delay: 0.002ns (logic 0.000ns (0.000%) route 0.002ns (100.000%)) Logic Levels: 0 Clock Uncertainty: 0.190ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.050ns Discrete Jitter (DJ): 0.122ns Phase Error (PE): 0.124ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- DSP48_X0Y38 DSP48E1 0.000 0.000 r u_matmul_axi_slave/mult_inst[1].u_mult/prod0__17/ACOUT[21] net (fo=1, routed) 0.002 0.002 u_matmul_axi_slave/mult_inst[1].u_mult/prod0__17_n_32 DSP48_X0Y39 DSP48E1 r u_matmul_axi_slave/mult_inst[1].u_mult/prod_reg__0/ACIN[21] ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9603, routed) 2.040 -2.302 u_matmul_axi_slave/mult_inst[1].u_mult/sys_clk DSP48_X0Y39 DSP48E1 r u_matmul_axi_slave/mult_inst[1].u_mult/prod_reg__0/CLK Slack: inf Source: u_matmul_axi_slave/mult_inst[1].u_mult/prod0__17/ACOUT[22] (internal pin) Destination: u_matmul_axi_slave/mult_inst[1].u_mult/prod_reg__0/ACIN[22] (rising edge-triggered cell DSP48E1 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: (none) Path Type: Hold (Min at Slow Process Corner) Data Path Delay: 0.002ns (logic 0.000ns (0.000%) route 0.002ns (100.000%)) Logic Levels: 0 Clock Uncertainty: 0.190ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.050ns Discrete Jitter (DJ): 0.122ns Phase Error (PE): 0.124ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- DSP48_X0Y38 DSP48E1 0.000 0.000 r u_matmul_axi_slave/mult_inst[1].u_mult/prod0__17/ACOUT[22] net (fo=1, routed) 0.002 0.002 u_matmul_axi_slave/mult_inst[1].u_mult/prod0__17_n_31 DSP48_X0Y39 DSP48E1 r u_matmul_axi_slave/mult_inst[1].u_mult/prod_reg__0/ACIN[22] ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9603, routed) 2.040 -2.302 u_matmul_axi_slave/mult_inst[1].u_mult/sys_clk DSP48_X0Y39 DSP48E1 r u_matmul_axi_slave/mult_inst[1].u_mult/prod_reg__0/CLK Slack: inf Source: u_matmul_axi_slave/mult_inst[1].u_mult/prod0__17/ACOUT[23] (internal pin) Destination: u_matmul_axi_slave/mult_inst[1].u_mult/prod_reg__0/ACIN[23] (rising edge-triggered cell DSP48E1 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: (none) Path Type: Hold (Min at Slow Process Corner) Data Path Delay: 0.002ns (logic 0.000ns (0.000%) route 0.002ns (100.000%)) Logic Levels: 0 Clock Uncertainty: 0.190ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.050ns Discrete Jitter (DJ): 0.122ns Phase Error (PE): 0.124ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- DSP48_X0Y38 DSP48E1 0.000 0.000 r u_matmul_axi_slave/mult_inst[1].u_mult/prod0__17/ACOUT[23] net (fo=1, routed) 0.002 0.002 u_matmul_axi_slave/mult_inst[1].u_mult/prod0__17_n_30 DSP48_X0Y39 DSP48E1 r u_matmul_axi_slave/mult_inst[1].u_mult/prod_reg__0/ACIN[23] ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9603, routed) 2.040 -2.302 u_matmul_axi_slave/mult_inst[1].u_mult/sys_clk DSP48_X0Y39 DSP48E1 r u_matmul_axi_slave/mult_inst[1].u_mult/prod_reg__0/CLK Slack: inf Source: u_matmul_axi_slave/mult_inst[1].u_mult/prod0__17/ACOUT[24] (internal pin) Destination: u_matmul_axi_slave/mult_inst[1].u_mult/prod_reg__0/ACIN[24] (rising edge-triggered cell DSP48E1 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: (none) Path Type: Hold (Min at Slow Process Corner) Data Path Delay: 0.002ns (logic 0.000ns (0.000%) route 0.002ns (100.000%)) Logic Levels: 0 Clock Uncertainty: 0.190ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.050ns Discrete Jitter (DJ): 0.122ns Phase Error (PE): 0.124ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- DSP48_X0Y38 DSP48E1 0.000 0.000 r u_matmul_axi_slave/mult_inst[1].u_mult/prod0__17/ACOUT[24] net (fo=1, routed) 0.002 0.002 u_matmul_axi_slave/mult_inst[1].u_mult/prod0__17_n_29 DSP48_X0Y39 DSP48E1 r u_matmul_axi_slave/mult_inst[1].u_mult/prod_reg__0/ACIN[24] ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9603, routed) 2.040 -2.302 u_matmul_axi_slave/mult_inst[1].u_mult/sys_clk DSP48_X0Y39 DSP48E1 r u_matmul_axi_slave/mult_inst[1].u_mult/prod_reg__0/CLK Slack: inf Source: u_matmul_axi_slave/mult_inst[1].u_mult/prod0__17/ACOUT[25] (internal pin) Destination: u_matmul_axi_slave/mult_inst[1].u_mult/prod_reg__0/ACIN[25] (rising edge-triggered cell DSP48E1 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: (none) Path Type: Hold (Min at Slow Process Corner) Data Path Delay: 0.002ns (logic 0.000ns (0.000%) route 0.002ns (100.000%)) Logic Levels: 0 Clock Uncertainty: 0.190ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.050ns Discrete Jitter (DJ): 0.122ns Phase Error (PE): 0.124ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- DSP48_X0Y38 DSP48E1 0.000 0.000 r u_matmul_axi_slave/mult_inst[1].u_mult/prod0__17/ACOUT[25] net (fo=1, routed) 0.002 0.002 u_matmul_axi_slave/mult_inst[1].u_mult/prod0__17_n_28 DSP48_X0Y39 DSP48E1 r u_matmul_axi_slave/mult_inst[1].u_mult/prod_reg__0/ACIN[25] ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9603, routed) 2.040 -2.302 u_matmul_axi_slave/mult_inst[1].u_mult/sys_clk DSP48_X0Y39 DSP48E1 r u_matmul_axi_slave/mult_inst[1].u_mult/prod_reg__0/CLK Slack: inf Source: u_matmul_axi_slave/mult_inst[1].u_mult/prod0__17/ACOUT[26] (internal pin) Destination: u_matmul_axi_slave/mult_inst[1].u_mult/prod_reg__0/ACIN[26] (rising edge-triggered cell DSP48E1 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: (none) Path Type: Hold (Min at Slow Process Corner) Data Path Delay: 0.002ns (logic 0.000ns (0.000%) route 0.002ns (100.000%)) Logic Levels: 0 Clock Uncertainty: 0.190ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.050ns Discrete Jitter (DJ): 0.122ns Phase Error (PE): 0.124ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- DSP48_X0Y38 DSP48E1 0.000 0.000 r u_matmul_axi_slave/mult_inst[1].u_mult/prod0__17/ACOUT[26] net (fo=1, routed) 0.002 0.002 u_matmul_axi_slave/mult_inst[1].u_mult/prod0__17_n_27 DSP48_X0Y39 DSP48E1 r u_matmul_axi_slave/mult_inst[1].u_mult/prod_reg__0/ACIN[26] ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9603, routed) 2.040 -2.302 u_matmul_axi_slave/mult_inst[1].u_mult/sys_clk DSP48_X0Y39 DSP48E1 r u_matmul_axi_slave/mult_inst[1].u_mult/prod_reg__0/CLK Slack: inf Source: u_matmul_axi_slave/mult_inst[1].u_mult/prod0__17/ACOUT[27] (internal pin) Destination: u_matmul_axi_slave/mult_inst[1].u_mult/prod_reg__0/ACIN[27] (rising edge-triggered cell DSP48E1 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: (none) Path Type: Hold (Min at Slow Process Corner) Data Path Delay: 0.002ns (logic 0.000ns (0.000%) route 0.002ns (100.000%)) Logic Levels: 0 Clock Uncertainty: 0.190ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.050ns Discrete Jitter (DJ): 0.122ns Phase Error (PE): 0.124ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- DSP48_X0Y38 DSP48E1 0.000 0.000 r u_matmul_axi_slave/mult_inst[1].u_mult/prod0__17/ACOUT[27] net (fo=1, routed) 0.002 0.002 u_matmul_axi_slave/mult_inst[1].u_mult/prod0__17_n_26 DSP48_X0Y39 DSP48E1 r u_matmul_axi_slave/mult_inst[1].u_mult/prod_reg__0/ACIN[27] ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O net (fo=9603, routed) 2.040 -2.302 u_matmul_axi_slave/mult_inst[1].u_mult/sys_clk DSP48_X0Y39 DSP48E1 r u_matmul_axi_slave/mult_inst[1].u_mult/prod_reg__0/CLK